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// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module do_rotate_grp_fu_232_ACMP_fmul_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module do_rotate_grp_fu_236_ACMP_fmul_4(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module jacob (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
a_address0,
a_ce0,
a_we0,
a_d0,
a_q0,
a_address1,
a_ce1,
a_we1,
a_d1,
a_q1,
d_address0,
d_ce0,
d_we0,
d_d0,
d_q0,
d_address1,
d_ce1,
d_we1,
d_d1,
d_q1,
v_address0,
v_ce0,
v_we0,
v_d0,
v_q0,
v_address1,
v_ce1,
v_we1,
v_d1,
v_q1,
nrot_i,
nrot_o,
nrot_o_ap_vld
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output [13:0] a_address0;
output a_ce0;
output a_we0;
output [31:0] a_d0;
input [31:0] a_q0;
output [13:0] a_address1;
output a_ce1;
output a_we1;
output [31:0] a_d1;
input [31:0] a_q1;
output [6:0] d_address0;
output d_ce0;
output d_we0;
output [31:0] d_d0;
input [31:0] d_q0;
output [6:0] d_address1;
output d_ce1;
output d_we1;
output [31:0] d_d1;
input [31:0] d_q1;
output [13:0] v_address0;
output v_ce0;
output v_we0;
output [31:0] v_d0;
input [31:0] v_q0;
output [13:0] v_address1;
output v_ce1;
output v_we1;
output [31:0] v_d1;
input [31:0] v_q1;
input [31:0] nrot_i;
output [31:0] nrot_o;
output nrot_o_ap_vld;
reg ap_done;
reg ap_idle;
reg[13:0] a_address0;
reg a_ce0;
reg a_we0;
reg[31:0] a_d0;
reg a_ce1;
reg a_we1;
reg[6:0] d_address0;
reg d_ce0;
reg d_we0;
reg[31:0] d_d0;
reg[6:0] d_address1;
reg d_ce1;
reg d_we1;
reg[13:0] v_address0;
reg v_ce0;
reg v_we0;
reg[31:0] v_d0;
reg v_ce1;
reg v_we1;
reg[31:0] nrot_o;
reg nrot_o_ap_vld;
reg [8:0] ap_CS_fsm;
reg [31:0] reg_640;
wire [31:0] grp_fu_509_p2;
reg [31:0] reg_649;
reg [0:0] tmp_i5_reg_1449;
wire [63:0] grp_fu_623_p2;
reg [63:0] reg_661;
wire [63:0] grp_fu_629_p2;
reg [63:0] reg_666;
wire [31:0] grp_fu_528_p2;
reg [31:0] reg_675;
reg [31:0] reg_684;
reg [31:0] reg_692;
wire [63:0] grp_fu_618_p2;
reg [63:0] reg_698;
wire [63:0] grp_fu_635_p2;
reg [63:0] reg_704;
wire [31:0] z_q0;
reg [31:0] reg_710;
wire [63:0] tmp_9_cast_fu_732_p1;
reg [63:0] tmp_9_cast_reg_1142;
wire [15:0] tmp36_cast_fu_742_p1;
reg [15:0] tmp36_cast_reg_1147;
reg [7:0] indvar_next3_reg_1155;
wire [0:0] exitcond2_fu_772_p2;
reg [7:0] indvar_next1_reg_1176;
wire [0:0] exitcond1_fu_790_p2;
wire [0:0] tmp_6_fu_836_p2;
reg [0:0] tmp_6_reg_1191;
reg [6:0] tmp4_reg_1195;
reg [6:0] tmp_4_reg_1205;
wire [31:0] iq_1_fu_874_p2;
reg [31:0] iq_1_reg_1213;
reg [6:0] indvar_next5_reg_1221;
wire [0:0] exitcond4_fu_880_p2;
wire [0:0] grp_fu_589_p2;
reg [0:0] tmp_i_reg_1236;
reg [31:0] UnifiedRetVal_i_reg_1241;
wire [63:0] grp_fu_557_p1;
reg [63:0] tmp_s_reg_1257;
wire [31:0] grp_fu_541_p1;
reg [0:0] tmp_13_reg_1267;
reg [6:0] tmp5_reg_1271;
reg [6:0] tmp_18_reg_1276;
wire [8:0] indvar3_cast_fu_967_p1;
reg [8:0] indvar3_cast_reg_1282;
reg [6:0] tmp_19_reg_1292;
reg [6:0] d_addr_1_reg_1300;
wire [0:0] exitcond5_fu_987_p2;
reg [6:0] z_addr_1_reg_1306;
reg [8:0] iq_2_reg_1311;
wire [31:0] tmp_21_fu_1018_p2;
reg [31:0] tmp_21_reg_1316;
reg [6:0] indvar_next2_reg_1327;
reg [13:0] a_addr_2_reg_1334;
wire [0:0] exitcond7_fu_1024_p2;
reg [0:0] tmp_i1_reg_1344;
wire [31:0] UnifiedRetVal_i1_fu_1066_p3;
reg [31:0] UnifiedRetVal_i1_reg_1349;
reg [63:0] tmp_26_reg_1355;
reg [0:0] tmp_i2_reg_1362;
reg [31:0] UnifiedRetVal_i2_reg_1367;
wire [0:0] grp_fu_596_p2;
reg [0:0] tmp_28_reg_1373;
reg [0:0] tmp_i3_reg_1382;
reg [31:0] UnifiedRetVal_i3_reg_1387;
reg [31:0] tmp_29_reg_1393;
wire [6:0] d_addr_4_gep_fu_211_p3;
reg [6:0] d_addr_4_reg_1404;
wire [0:0] grp_fu_604_p2;
reg [31:0] d_load_3_reg_1410;
reg [0:0] tmp_i4_reg_1416;
reg [31:0] UnifiedRetVal_i4_reg_1421;
wire [63:0] grp_fu_561_p1;
reg [63:0] tmp_36_reg_1430;
wire [63:0] grp_fu_564_p1;
reg [63:0] tmp_38_reg_1435;
wire [31:0] grp_fu_544_p1;
reg [31:0] theta_reg_1440;
wire [0:0] grp_fu_613_p2;
wire [63:0] grp_fu_567_p1;
reg [63:0] tmp_42_reg_1454;
wire [63:0] grp_fu_570_p1;
reg [63:0] tmp_40_reg_1464;
wire [31:0] grp_fu_547_p1;
reg [31:0] tmp_47_reg_1469;
wire [31:0] grp_fu_537_p2;
reg [6:0] z_addr_3_reg_1485;
reg [31:0] tmp_59_reg_1490;
wire [31:0] z_q1;
reg [31:0] z_load_2_reg_1498;
wire [31:0] grp_fu_516_p2;
reg [31:0] tmp_61_reg_1503;
wire [31:0] grp_fu_520_p2;
reg [31:0] tmp_62_reg_1508;
wire [31:0] grp_fu_524_p2;
reg [31:0] tmp_63_reg_1513;
wire [63:0] grp_fu_573_p1;
reg [63:0] tmp_52_reg_1518;
wire [31:0] grp_fu_550_p1;
reg [31:0] c_reg_1523;
wire [63:0] grp_fu_576_p1;
reg [63:0] tmp_56_reg_1529;
wire [63:0] grp_fu_580_p1;
reg [63:0] tmp_55_reg_1534;
wire [31:0] grp_fu_553_p1;
reg [31:0] tau_reg_1539;
reg [7:0] indvar_next_reg_1547;
wire [63:0] tmp_22_fu_1124_p1;
reg [63:0] tmp_22_reg_1552;
wire [0:0] exitcond6_fu_1112_p2;
reg [6:0] b_addr_1_reg_1557;
reg [6:0] z_addr_2_reg_1562;
reg [7:0] tmp_24_reg_1567;
wire [31:0] b_q0;
reg [31:0] b_load_reg_1577;
reg [6:0] b_address0;
reg b_ce0;
reg b_we0;
reg [31:0] b_d0;
reg [6:0] z_address0;
reg z_ce0;
reg z_we0;
reg [31:0] z_d0;
wire [6:0] z_address1;
reg z_ce1;
reg z_we1;
wire [31:0] z_d1;
reg grp_do_rotate_fu_497_ap_start;
wire grp_do_rotate_fu_497_ap_done;
wire grp_do_rotate_fu_497_ap_idle;
wire [13:0] grp_do_rotate_fu_497_a_address0;
wire grp_do_rotate_fu_497_a_ce0;
wire grp_do_rotate_fu_497_a_we0;
wire [31:0] grp_do_rotate_fu_497_a_d0;
wire [31:0] grp_do_rotate_fu_497_a_q0;
wire [13:0] grp_do_rotate_fu_497_a_address1;
wire grp_do_rotate_fu_497_a_ce1;
wire grp_do_rotate_fu_497_a_we1;
wire [31:0] grp_do_rotate_fu_497_a_d1;
wire [31:0] grp_do_rotate_fu_497_a_q1;
wire [13:0] grp_do_rotate_fu_497_v_address0;
wire grp_do_rotate_fu_497_v_ce0;
wire grp_do_rotate_fu_497_v_we0;
wire [31:0] grp_do_rotate_fu_497_v_d0;
wire [31:0] grp_do_rotate_fu_497_v_q0;
wire [13:0] grp_do_rotate_fu_497_v_address1;
wire grp_do_rotate_fu_497_v_ce1;
wire grp_do_rotate_fu_497_v_we1;
wire [31:0] grp_do_rotate_fu_497_v_d1;
wire [31:0] grp_do_rotate_fu_497_v_q1;
wire [31:0] grp_do_rotate_fu_497_s;
wire [31:0] grp_do_rotate_fu_497_tau;
wire [6:0] grp_do_rotate_fu_497_ip;
wire [8:0] grp_do_rotate_fu_497_iq;
reg [7:0] indvar2_reg_253;
reg [63:0] indvar6_reg_264;
wire [0:0] exitcond_fu_746_p2;
reg [7:0] indvar5_reg_275;
reg [7:0] indvar4_reg_286;
reg [7:0] ip_1_reg_297;
reg [31:0] indvar10_reg_309;
reg [6:0] indvar7_reg_321;
reg [7:0] tmp_7_reg_332;
reg [31:0] sm_1_reg_344;
reg [6:0] indvar8_reg_356;
wire [0:0] exitcond3_fu_868_p2;
reg [31:0] iq_1_in_reg_367;
reg [31:0] sm_reg_376;
reg [31:0] tresh_reg_388;
wire [0:0] icmp_fu_939_p2;
wire [0:0] grp_fu_583_p2;
reg [6:0] indvar9_reg_400;
reg [6:0] indvar3_reg_411;
reg [7:0] tmp_17_reg_422;
reg [6:0] indvar1_reg_434;
wire [0:0] grp_fu_600_p2;
reg [31:0] iq_2_in_reg_449;
wire [31:0] t_phi_fu_465_p6;
reg [31:0] t_reg_462;
reg [7:0] indvar_reg_474;
reg [7:0] ip_4_reg_485;
wire [63:0] tmp_cast_fu_767_p1;
wire [63:0] tmp_1_fu_818_p1;
wire [63:0] tmp_2_fu_823_p1;
wire [63:0] tmp_15_fu_911_p1;
wire [63:0] tmp_48_fu_1055_p1;
wire [31:0] tmp_64_fu_1105_p2;
reg [31:0] grp_fu_509_p0;
reg [31:0] grp_fu_509_p1;
wire [31:0] grp_fu_516_p0;
wire [31:0] grp_fu_516_p1;
wire [31:0] grp_fu_520_p0;
wire [31:0] grp_fu_520_p1;
wire [31:0] grp_fu_524_p0;
wire [31:0] grp_fu_524_p1;
reg [31:0] grp_fu_528_p0;
reg [31:0] grp_fu_528_p1;
wire [31:0] grp_fu_537_p0;
wire [31:0] grp_fu_537_p1;
wire [0:0] grp_fu_609_p2;
wire [63:0] grp_fu_541_p0;
wire [63:0] grp_fu_544_p0;
wire [63:0] grp_fu_547_p0;
wire [63:0] grp_fu_550_p0;
wire [63:0] grp_fu_553_p0;
wire [31:0] grp_fu_557_p0;
wire [31:0] grp_fu_561_p0;
wire [31:0] grp_fu_564_p0;
wire [31:0] grp_fu_567_p0;
wire [31:0] grp_fu_570_p0;
wire [31:0] grp_fu_573_p0;
wire [31:0] grp_fu_576_p0;
wire [31:0] grp_fu_580_p0;
wire [31:0] grp_fu_583_p0;
wire [31:0] grp_fu_583_p1;
reg [31:0] grp_fu_589_p0;
wire [31:0] grp_fu_589_p1;
wire [31:0] grp_fu_596_p0;
wire [31:0] grp_fu_596_p1;
wire [31:0] grp_fu_600_p0;
wire [31:0] grp_fu_600_p1;
wire [31:0] grp_fu_604_p0;
wire [31:0] grp_fu_604_p1;
wire [31:0] grp_fu_609_p0;
wire [31:0] grp_fu_609_p1;
wire [31:0] grp_fu_613_p0;
wire [31:0] grp_fu_613_p1;
reg [63:0] grp_fu_618_p0;
reg [63:0] grp_fu_618_p1;
reg [63:0] grp_fu_623_p0;
reg [63:0] grp_fu_623_p1;
reg [63:0] grp_fu_629_p0;
reg [63:0] grp_fu_629_p1;
reg [63:0] grp_fu_635_p1;
wire [14:0] indvar30_cast_fu_716_p1;
wire [14:0] tmp1_fu_720_p2;
wire [14:0] tmp_9_fu_726_p2;
wire [14:0] tmp2_fu_736_p2;
wire [15:0] indvar34_cast_fu_758_p1;
wire [15:0] tmp_fu_762_p2;
wire [15:0] tmp_2_trn_cast_fu_802_p1;
wire [15:0] p_shl_fu_806_p2;
wire [15:0] a_addr6_fu_812_p2;
wire [7:0] indvar7_cast_fu_848_p1;
wire [7:0] ip_2_fu_852_p2;
wire [14:0] tmp_9_trn_cast_fu_891_p1;
wire [14:0] a_addr2_fu_895_p2;
wire [31:0] a_addr2_cast_fu_901_p1;
wire [31:0] a_addr3_fu_905_p2;
wire [29:0] tmp_5_fu_929_p4;
wire [7:0] indvar3_cast1_fu_963_p1;
wire [7:0] ip_3_fu_971_p2;
wire [7:0] indvar1_cast_fu_999_p1;
wire [7:0] tmp3_fu_1003_p2;
wire [8:0] tmp3_cast_fu_1009_p1;
wire [14:0] tmp_20_trn_cast_fu_1035_p1;
wire [14:0] a_addr_fu_1039_p2;
wire [31:0] a_addr_cast_fu_1045_p1;
wire [31:0] a_addr1_fu_1049_p2;
reg [1:0] grp_fu_509_opcode;
wire grp_fu_509_ce;
wire grp_fu_516_ce;
wire grp_fu_520_ce;
wire grp_fu_524_ce;
wire grp_fu_528_ce;
reg grp_fu_537_ce;
wire grp_fu_541_ce;
wire grp_fu_544_ce;
wire grp_fu_547_ce;
wire grp_fu_550_ce;
wire grp_fu_553_ce;
reg grp_fu_557_ce;
reg grp_fu_561_ce;
wire grp_fu_564_ce;
wire grp_fu_567_ce;
wire grp_fu_570_ce;
wire grp_fu_573_ce;
wire grp_fu_576_ce;
wire grp_fu_580_ce;
reg grp_fu_583_ce;
wire [4:0] grp_fu_583_opcode;
wire grp_fu_589_ce;
wire [4:0] grp_fu_589_opcode;
wire grp_fu_596_ce;
wire [4:0] grp_fu_596_opcode;
wire grp_fu_600_ce;
wire [4:0] grp_fu_600_opcode;
reg grp_fu_604_ce;
wire [4:0] grp_fu_604_opcode;
wire grp_fu_609_ce;
wire [4:0] grp_fu_609_opcode;
wire grp_fu_613_ce;
wire [4:0] grp_fu_613_opcode;
wire grp_fu_618_ce;
wire grp_fu_623_ce;
wire grp_fu_629_ce;
wire [63:0] grp_fu_635_p0;
wire grp_fu_635_ce;
reg [8:0] ap_NS_fsm;
wire [63:0] a_addr_2_reg_13340;
wire [63:0] b_addr_1_reg_15570;
wire [63:0] d_addr_1_reg_13000;
wire [63:0] z_addr_1_reg_13060;
wire [63:0] z_addr_2_reg_15620;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 9'b000000000;
parameter ap_ST_st1_fsm_1 = 9'b000000001;
parameter ap_ST_st2_fsm_2 = 9'b000000010;
parameter ap_ST_st3_fsm_3 = 9'b000000011;
parameter ap_ST_st4_fsm_4 = 9'b000000100;
parameter ap_ST_st5_fsm_5 = 9'b000000101;
parameter ap_ST_st6_fsm_6 = 9'b000000110;
parameter ap_ST_st7_fsm_7 = 9'b000000111;
parameter ap_ST_st8_fsm_8 = 9'b000001000;
parameter ap_ST_st9_fsm_9 = 9'b000001001;
parameter ap_ST_st10_fsm_10 = 9'b000001010;
parameter ap_ST_st11_fsm_11 = 9'b000001011;
parameter ap_ST_st12_fsm_12 = 9'b000001100;
parameter ap_ST_st13_fsm_13 = 9'b000001101;
parameter ap_ST_st14_fsm_14 = 9'b000001110;
parameter ap_ST_st15_fsm_15 = 9'b000001111;
parameter ap_ST_st16_fsm_16 = 9'b000010000;
parameter ap_ST_st17_fsm_17 = 9'b000010001;
parameter ap_ST_st18_fsm_18 = 9'b000010010;
parameter ap_ST_st19_fsm_19 = 9'b000010011;
parameter ap_ST_st20_fsm_20 = 9'b000010100;
parameter ap_ST_st21_fsm_21 = 9'b000010101;
parameter ap_ST_st22_fsm_22 = 9'b000010110;
parameter ap_ST_st23_fsm_23 = 9'b000010111;
parameter ap_ST_st24_fsm_24 = 9'b000011000;
parameter ap_ST_st25_fsm_25 = 9'b000011001;
parameter ap_ST_st26_fsm_26 = 9'b000011010;
parameter ap_ST_st27_fsm_27 = 9'b000011011;
parameter ap_ST_st28_fsm_28 = 9'b000011100;
parameter ap_ST_st29_fsm_29 = 9'b000011101;
parameter ap_ST_st30_fsm_30 = 9'b000011110;
parameter ap_ST_st31_fsm_31 = 9'b000011111;
parameter ap_ST_st32_fsm_32 = 9'b000100000;
parameter ap_ST_st33_fsm_33 = 9'b000100001;
parameter ap_ST_st34_fsm_34 = 9'b000100010;
parameter ap_ST_st35_fsm_35 = 9'b000100011;
parameter ap_ST_st36_fsm_36 = 9'b000100100;
parameter ap_ST_st37_fsm_37 = 9'b000100101;
parameter ap_ST_st38_fsm_38 = 9'b000100110;
parameter ap_ST_st39_fsm_39 = 9'b000100111;
parameter ap_ST_st40_fsm_40 = 9'b000101000;
parameter ap_ST_st41_fsm_41 = 9'b000101001;
parameter ap_ST_st42_fsm_42 = 9'b000101010;
parameter ap_ST_st43_fsm_43 = 9'b000101011;
parameter ap_ST_st44_fsm_44 = 9'b000101100;
parameter ap_ST_st45_fsm_45 = 9'b000101101;
parameter ap_ST_st46_fsm_46 = 9'b000101110;
parameter ap_ST_st47_fsm_47 = 9'b000101111;
parameter ap_ST_st48_fsm_48 = 9'b000110000;
parameter ap_ST_st49_fsm_49 = 9'b000110001;
parameter ap_ST_st50_fsm_50 = 9'b000110010;
parameter ap_ST_st51_fsm_51 = 9'b000110011;
parameter ap_ST_st52_fsm_52 = 9'b000110100;
parameter ap_ST_st53_fsm_53 = 9'b000110101;
parameter ap_ST_st54_fsm_54 = 9'b000110110;
parameter ap_ST_st55_fsm_55 = 9'b000110111;
parameter ap_ST_st56_fsm_56 = 9'b000111000;
parameter ap_ST_st57_fsm_57 = 9'b000111001;
parameter ap_ST_st58_fsm_58 = 9'b000111010;
parameter ap_ST_st59_fsm_59 = 9'b000111011;
parameter ap_ST_st60_fsm_60 = 9'b000111100;
parameter ap_ST_st61_fsm_61 = 9'b000111101;
parameter ap_ST_st62_fsm_62 = 9'b000111110;
parameter ap_ST_st63_fsm_63 = 9'b000111111;
parameter ap_ST_st64_fsm_64 = 9'b001000000;
parameter ap_ST_st65_fsm_65 = 9'b001000001;
parameter ap_ST_st66_fsm_66 = 9'b001000010;
parameter ap_ST_st67_fsm_67 = 9'b001000011;
parameter ap_ST_st68_fsm_68 = 9'b001000100;
parameter ap_ST_st69_fsm_69 = 9'b001000101;
parameter ap_ST_st70_fsm_70 = 9'b001000110;
parameter ap_ST_st71_fsm_71 = 9'b001000111;
parameter ap_ST_st72_fsm_72 = 9'b001001000;
parameter ap_ST_st73_fsm_73 = 9'b001001001;
parameter ap_ST_st74_fsm_74 = 9'b001001010;
parameter ap_ST_st75_fsm_75 = 9'b001001011;
parameter ap_ST_st76_fsm_76 = 9'b001001100;
parameter ap_ST_st77_fsm_77 = 9'b001001101;
parameter ap_ST_st78_fsm_78 = 9'b001001110;
parameter ap_ST_st79_fsm_79 = 9'b001001111;
parameter ap_ST_st80_fsm_80 = 9'b001010000;
parameter ap_ST_st81_fsm_81 = 9'b001010001;
parameter ap_ST_st82_fsm_82 = 9'b001010010;
parameter ap_ST_st83_fsm_83 = 9'b001010011;
parameter ap_ST_st84_fsm_84 = 9'b001010100;
parameter ap_ST_st85_fsm_85 = 9'b001010101;
parameter ap_ST_st86_fsm_86 = 9'b001010110;
parameter ap_ST_st87_fsm_87 = 9'b001010111;
parameter ap_ST_st88_fsm_88 = 9'b001011000;
parameter ap_ST_st89_fsm_89 = 9'b001011001;
parameter ap_ST_st90_fsm_90 = 9'b001011010;
parameter ap_ST_st91_fsm_91 = 9'b001011011;
parameter ap_ST_st92_fsm_92 = 9'b001011100;
parameter ap_ST_st93_fsm_93 = 9'b001011101;
parameter ap_ST_st94_fsm_94 = 9'b001011110;
parameter ap_ST_st95_fsm_95 = 9'b001011111;
parameter ap_ST_st96_fsm_96 = 9'b001100000;
parameter ap_ST_st97_fsm_97 = 9'b001100001;
parameter ap_ST_st98_fsm_98 = 9'b001100010;
parameter ap_ST_st99_fsm_99 = 9'b001100011;
parameter ap_ST_st100_fsm_100 = 9'b001100100;
parameter ap_ST_st101_fsm_101 = 9'b001100101;
parameter ap_ST_st102_fsm_102 = 9'b001100110;
parameter ap_ST_st103_fsm_103 = 9'b001100111;
parameter ap_ST_st104_fsm_104 = 9'b001101000;
parameter ap_ST_st105_fsm_105 = 9'b001101001;
parameter ap_ST_st106_fsm_106 = 9'b001101010;
parameter ap_ST_st107_fsm_107 = 9'b001101011;
parameter ap_ST_st108_fsm_108 = 9'b001101100;
parameter ap_ST_st109_fsm_109 = 9'b001101101;
parameter ap_ST_st110_fsm_110 = 9'b001101110;
parameter ap_ST_st111_fsm_111 = 9'b001101111;
parameter ap_ST_st112_fsm_112 = 9'b001110000;
parameter ap_ST_st113_fsm_113 = 9'b001110001;
parameter ap_ST_st114_fsm_114 = 9'b001110010;
parameter ap_ST_st115_fsm_115 = 9'b001110011;
parameter ap_ST_st116_fsm_116 = 9'b001110100;
parameter ap_ST_st117_fsm_117 = 9'b001110101;
parameter ap_ST_st118_fsm_118 = 9'b001110110;
parameter ap_ST_st119_fsm_119 = 9'b001110111;
parameter ap_ST_st120_fsm_120 = 9'b001111000;
parameter ap_ST_st121_fsm_121 = 9'b001111001;
parameter ap_ST_st122_fsm_122 = 9'b001111010;
parameter ap_ST_st123_fsm_123 = 9'b001111011;
parameter ap_ST_st124_fsm_124 = 9'b001111100;
parameter ap_ST_st125_fsm_125 = 9'b001111101;
parameter ap_ST_st126_fsm_126 = 9'b001111110;
parameter ap_ST_st127_fsm_127 = 9'b001111111;
parameter ap_ST_st128_fsm_128 = 9'b010000000;
parameter ap_ST_st129_fsm_129 = 9'b010000001;
parameter ap_ST_st130_fsm_130 = 9'b010000010;
parameter ap_ST_st131_fsm_131 = 9'b010000011;
parameter ap_ST_st132_fsm_132 = 9'b010000100;
parameter ap_ST_st133_fsm_133 = 9'b010000101;
parameter ap_ST_st134_fsm_134 = 9'b010000110;
parameter ap_ST_st135_fsm_135 = 9'b010000111;
parameter ap_ST_st136_fsm_136 = 9'b010001000;
parameter ap_ST_st137_fsm_137 = 9'b010001001;
parameter ap_ST_st138_fsm_138 = 9'b010001010;
parameter ap_ST_st139_fsm_139 = 9'b010001011;
parameter ap_ST_st140_fsm_140 = 9'b010001100;
parameter ap_ST_st141_fsm_141 = 9'b010001101;
parameter ap_ST_st142_fsm_142 = 9'b010001110;
parameter ap_ST_st143_fsm_143 = 9'b010001111;
parameter ap_ST_st144_fsm_144 = 9'b010010000;
parameter ap_ST_st145_fsm_145 = 9'b010010001;
parameter ap_ST_st146_fsm_146 = 9'b010010010;
parameter ap_ST_st147_fsm_147 = 9'b010010011;
parameter ap_ST_st148_fsm_148 = 9'b010010100;
parameter ap_ST_st149_fsm_149 = 9'b010010101;
parameter ap_ST_st150_fsm_150 = 9'b010010110;
parameter ap_ST_st151_fsm_151 = 9'b010010111;
parameter ap_ST_st152_fsm_152 = 9'b010011000;
parameter ap_ST_st153_fsm_153 = 9'b010011001;
parameter ap_ST_st154_fsm_154 = 9'b010011010;
parameter ap_ST_st155_fsm_155 = 9'b010011011;
parameter ap_ST_st156_fsm_156 = 9'b010011100;
parameter ap_ST_st157_fsm_157 = 9'b010011101;
parameter ap_ST_st158_fsm_158 = 9'b010011110;
parameter ap_ST_st159_fsm_159 = 9'b010011111;
parameter ap_ST_st160_fsm_160 = 9'b010100000;
parameter ap_ST_st161_fsm_161 = 9'b010100001;
parameter ap_ST_st162_fsm_162 = 9'b010100010;
parameter ap_ST_st163_fsm_163 = 9'b010100011;
parameter ap_ST_st164_fsm_164 = 9'b010100100;
parameter ap_ST_st165_fsm_165 = 9'b010100101;
parameter ap_ST_st166_fsm_166 = 9'b010100110;
parameter ap_ST_st167_fsm_167 = 9'b010100111;
parameter ap_ST_st168_fsm_168 = 9'b010101000;
parameter ap_ST_st169_fsm_169 = 9'b010101001;
parameter ap_ST_st170_fsm_170 = 9'b010101010;
parameter ap_ST_st171_fsm_171 = 9'b010101011;
parameter ap_ST_st172_fsm_172 = 9'b010101100;
parameter ap_ST_st173_fsm_173 = 9'b010101101;
parameter ap_ST_st174_fsm_174 = 9'b010101110;
parameter ap_ST_st175_fsm_175 = 9'b010101111;
parameter ap_ST_st176_fsm_176 = 9'b010110000;
parameter ap_ST_st177_fsm_177 = 9'b010110001;
parameter ap_ST_st178_fsm_178 = 9'b010110010;
parameter ap_ST_st179_fsm_179 = 9'b010110011;
parameter ap_ST_st180_fsm_180 = 9'b010110100;
parameter ap_ST_st181_fsm_181 = 9'b010110101;
parameter ap_ST_st182_fsm_182 = 9'b010110110;
parameter ap_ST_st183_fsm_183 = 9'b010110111;
parameter ap_ST_st184_fsm_184 = 9'b010111000;
parameter ap_ST_st185_fsm_185 = 9'b010111001;
parameter ap_ST_st186_fsm_186 = 9'b010111010;
parameter ap_ST_st187_fsm_187 = 9'b010111011;
parameter ap_ST_st188_fsm_188 = 9'b010111100;
parameter ap_ST_st189_fsm_189 = 9'b010111101;
parameter ap_ST_st190_fsm_190 = 9'b010111110;
parameter ap_ST_st191_fsm_191 = 9'b010111111;
parameter ap_ST_st192_fsm_192 = 9'b011000000;
parameter ap_ST_st193_fsm_193 = 9'b011000001;
parameter ap_ST_st194_fsm_194 = 9'b011000010;
parameter ap_ST_st195_fsm_195 = 9'b011000011;
parameter ap_ST_st196_fsm_196 = 9'b011000100;
parameter ap_ST_st197_fsm_197 = 9'b011000101;
parameter ap_ST_st198_fsm_198 = 9'b011000110;
parameter ap_ST_st199_fsm_199 = 9'b011000111;
parameter ap_ST_st200_fsm_200 = 9'b011001000;
parameter ap_ST_st201_fsm_201 = 9'b011001001;
parameter ap_ST_st202_fsm_202 = 9'b011001010;
parameter ap_ST_st203_fsm_203 = 9'b011001011;
parameter ap_ST_st204_fsm_204 = 9'b011001100;
parameter ap_ST_st205_fsm_205 = 9'b011001101;
parameter ap_ST_st206_fsm_206 = 9'b011001110;
parameter ap_ST_st207_fsm_207 = 9'b011001111;
parameter ap_ST_st208_fsm_208 = 9'b011010000;
parameter ap_ST_st209_fsm_209 = 9'b011010001;
parameter ap_ST_st210_fsm_210 = 9'b011010010;
parameter ap_ST_st211_fsm_211 = 9'b011010011;
parameter ap_ST_st212_fsm_212 = 9'b011010100;
parameter ap_ST_st213_fsm_213 = 9'b011010101;
parameter ap_ST_st214_fsm_214 = 9'b011010110;
parameter ap_ST_st215_fsm_215 = 9'b011010111;
parameter ap_ST_st216_fsm_216 = 9'b011011000;
parameter ap_ST_st217_fsm_217 = 9'b011011001;
parameter ap_ST_st218_fsm_218 = 9'b011011010;
parameter ap_ST_st219_fsm_219 = 9'b011011011;
parameter ap_ST_st220_fsm_220 = 9'b011011100;
parameter ap_ST_st221_fsm_221 = 9'b011011101;
parameter ap_ST_st222_fsm_222 = 9'b011011110;
parameter ap_ST_st223_fsm_223 = 9'b011011111;
parameter ap_ST_st224_fsm_224 = 9'b011100000;
parameter ap_ST_st225_fsm_225 = 9'b011100001;
parameter ap_ST_st226_fsm_226 = 9'b011100010;
parameter ap_ST_st227_fsm_227 = 9'b011100011;
parameter ap_ST_st228_fsm_228 = 9'b011100100;
parameter ap_ST_st229_fsm_229 = 9'b011100101;
parameter ap_ST_st230_fsm_230 = 9'b011100110;
parameter ap_ST_st231_fsm_231 = 9'b011100111;
parameter ap_ST_st232_fsm_232 = 9'b011101000;
parameter ap_ST_st233_fsm_233 = 9'b011101001;
parameter ap_ST_st234_fsm_234 = 9'b011101010;
parameter ap_ST_st235_fsm_235 = 9'b011101011;
parameter ap_ST_st236_fsm_236 = 9'b011101100;
parameter ap_ST_st237_fsm_237 = 9'b011101101;
parameter ap_ST_st238_fsm_238 = 9'b011101110;
parameter ap_ST_st239_fsm_239 = 9'b011101111;
parameter ap_ST_st240_fsm_240 = 9'b011110000;
parameter ap_ST_st241_fsm_241 = 9'b011110001;
parameter ap_ST_st242_fsm_242 = 9'b011110010;
parameter ap_ST_st243_fsm_243 = 9'b011110011;
parameter ap_ST_st244_fsm_244 = 9'b011110100;
parameter ap_ST_st245_fsm_245 = 9'b011110101;
parameter ap_ST_st246_fsm_246 = 9'b011110110;
parameter ap_ST_st247_fsm_247 = 9'b011110111;
parameter ap_ST_st248_fsm_248 = 9'b011111000;
parameter ap_ST_st249_fsm_249 = 9'b011111001;
parameter ap_ST_st250_fsm_250 = 9'b011111010;
parameter ap_ST_st251_fsm_251 = 9'b011111011;
parameter ap_ST_st252_fsm_252 = 9'b011111100;
parameter ap_ST_st253_fsm_253 = 9'b011111101;
parameter ap_ST_st254_fsm_254 = 9'b011111110;
parameter ap_ST_st255_fsm_255 = 9'b011111111;
parameter ap_ST_st256_fsm_256 = 9'b100000000;
parameter ap_ST_st257_fsm_257 = 9'b100000001;
parameter ap_ST_st258_fsm_258 = 9'b100000010;
parameter ap_ST_st259_fsm_259 = 9'b100000011;
parameter ap_ST_st260_fsm_260 = 9'b100000100;
parameter ap_ST_st261_fsm_261 = 9'b100000101;
parameter ap_ST_st262_fsm_262 = 9'b100000110;
parameter ap_ST_st263_fsm_263 = 9'b100000111;
parameter ap_ST_st264_fsm_264 = 9'b100001000;
parameter ap_ST_st265_fsm_265 = 9'b100001001;
parameter ap_ST_st266_fsm_266 = 9'b100001010;
parameter ap_ST_st267_fsm_267 = 9'b100001011;
parameter ap_ST_st268_fsm_268 = 9'b100001100;
parameter ap_ST_st269_fsm_269 = 9'b100001101;
parameter ap_ST_st270_fsm_270 = 9'b100001110;
parameter ap_ST_st271_fsm_271 = 9'b100001111;
parameter ap_ST_st272_fsm_272 = 9'b100010000;
parameter ap_ST_st273_fsm_273 = 9'b100010001;
parameter ap_ST_st274_fsm_274 = 9'b100010010;
parameter ap_ST_st275_fsm_275 = 9'b100010011;
parameter ap_ST_st276_fsm_276 = 9'b100010100;
parameter ap_ST_st277_fsm_277 = 9'b100010101;
parameter ap_ST_st278_fsm_278 = 9'b100010110;
parameter ap_ST_st279_fsm_279 = 9'b100010111;
parameter ap_ST_st280_fsm_280 = 9'b100011000;
parameter ap_ST_st281_fsm_281 = 9'b100011001;
parameter ap_ST_st282_fsm_282 = 9'b100011010;
parameter ap_ST_st283_fsm_283 = 9'b100011011;
parameter ap_ST_st284_fsm_284 = 9'b100011100;
parameter ap_ST_st285_fsm_285 = 9'b100011101;
parameter ap_ST_st286_fsm_286 = 9'b100011110;
parameter ap_ST_st287_fsm_287 = 9'b100011111;
parameter ap_ST_st288_fsm_288 = 9'b100100000;
parameter ap_ST_st289_fsm_289 = 9'b100100001;
parameter ap_ST_st290_fsm_290 = 9'b100100010;
parameter ap_ST_st291_fsm_291 = 9'b100100011;
parameter ap_ST_st292_fsm_292 = 9'b100100100;
parameter ap_ST_st293_fsm_293 = 9'b100100101;
parameter ap_ST_st294_fsm_294 = 9'b100100110;
parameter ap_ST_st295_fsm_295 = 9'b100100111;
parameter ap_ST_st296_fsm_296 = 9'b100101000;
parameter ap_ST_st297_fsm_297 = 9'b100101001;
parameter ap_ST_st298_fsm_298 = 9'b100101010;
parameter ap_ST_st299_fsm_299 = 9'b100101011;
parameter ap_ST_st300_fsm_300 = 9'b100101100;
parameter ap_ST_st301_fsm_301 = 9'b100101101;
parameter ap_ST_st302_fsm_302 = 9'b100101110;
parameter ap_ST_st303_fsm_303 = 9'b100101111;
parameter ap_ST_st304_fsm_304 = 9'b100110000;
parameter ap_ST_st305_fsm_305 = 9'b100110001;
parameter ap_ST_st306_fsm_306 = 9'b100110010;
parameter ap_ST_st307_fsm_307 = 9'b100110011;
parameter ap_ST_st308_fsm_308 = 9'b100110100;
parameter ap_ST_st309_fsm_309 = 9'b100110101;
parameter ap_ST_st310_fsm_310 = 9'b100110110;
parameter ap_ST_st311_fsm_311 = 9'b100110111;
parameter ap_ST_st312_fsm_312 = 9'b100111000;
parameter ap_ST_st313_fsm_313 = 9'b100111001;
parameter ap_ST_st314_fsm_314 = 9'b100111010;
parameter ap_ST_st315_fsm_315 = 9'b100111011;
parameter ap_ST_st316_fsm_316 = 9'b100111100;
parameter ap_ST_st317_fsm_317 = 9'b100111101;
parameter ap_ST_st318_fsm_318 = 9'b100111110;
parameter ap_ST_st319_fsm_319 = 9'b100111111;
parameter ap_ST_st320_fsm_320 = 9'b101000000;
parameter ap_ST_st321_fsm_321 = 9'b101000001;
parameter ap_ST_st322_fsm_322 = 9'b101000010;
parameter ap_ST_st323_fsm_323 = 9'b101000011;
parameter ap_ST_st324_fsm_324 = 9'b101000100;
parameter ap_ST_st325_fsm_325 = 9'b101000101;
parameter ap_ST_st326_fsm_326 = 9'b101000110;
parameter ap_ST_st327_fsm_327 = 9'b101000111;
parameter ap_ST_st328_fsm_328 = 9'b101001000;
parameter ap_ST_st329_fsm_329 = 9'b101001001;
parameter ap_ST_st330_fsm_330 = 9'b101001010;
parameter ap_ST_st331_fsm_331 = 9'b101001011;
parameter ap_ST_st332_fsm_332 = 9'b101001100;
parameter ap_ST_st333_fsm_333 = 9'b101001101;
parameter ap_ST_st334_fsm_334 = 9'b101001110;
parameter ap_ST_st335_fsm_335 = 9'b101001111;
parameter ap_ST_st336_fsm_336 = 9'b101010000;
parameter ap_ST_st337_fsm_337 = 9'b101010001;
parameter ap_ST_st338_fsm_338 = 9'b101010010;
parameter ap_ST_st339_fsm_339 = 9'b101010011;
parameter ap_ST_st340_fsm_340 = 9'b101010100;
parameter ap_ST_st341_fsm_341 = 9'b101010101;
parameter ap_ST_st342_fsm_342 = 9'b101010110;
parameter ap_ST_st343_fsm_343 = 9'b101010111;
parameter ap_ST_st344_fsm_344 = 9'b101011000;
parameter ap_ST_st345_fsm_345 = 9'b101011001;
parameter ap_ST_st346_fsm_346 = 9'b101011010;
parameter ap_ST_st347_fsm_347 = 9'b101011011;
parameter ap_ST_st348_fsm_348 = 9'b101011100;
parameter ap_ST_st349_fsm_349 = 9'b101011101;
parameter ap_ST_st350_fsm_350 = 9'b101011110;
parameter ap_ST_st351_fsm_351 = 9'b101011111;
parameter ap_ST_st352_fsm_352 = 9'b101100000;
parameter ap_ST_st353_fsm_353 = 9'b101100001;
parameter ap_ST_st354_fsm_354 = 9'b101100010;
parameter ap_ST_st355_fsm_355 = 9'b101100011;
parameter ap_ST_st356_fsm_356 = 9'b101100100;
parameter ap_ST_st357_fsm_357 = 9'b101100101;
parameter ap_ST_st358_fsm_358 = 9'b101100110;
parameter ap_ST_st359_fsm_359 = 9'b101100111;
parameter ap_ST_st360_fsm_360 = 9'b101101000;
parameter ap_ST_st361_fsm_361 = 9'b101101001;
parameter ap_ST_st362_fsm_362 = 9'b101101010;
parameter ap_ST_st363_fsm_363 = 9'b101101011;
parameter ap_ST_st364_fsm_364 = 9'b101101100;
parameter ap_ST_st365_fsm_365 = 9'b101101101;
parameter ap_ST_st366_fsm_366 = 9'b101101110;
parameter ap_ST_st367_fsm_367 = 9'b101101111;
parameter ap_ST_st368_fsm_368 = 9'b101110000;
parameter ap_ST_st369_fsm_369 = 9'b101110001;
parameter ap_ST_st370_fsm_370 = 9'b101110010;
parameter ap_ST_st371_fsm_371 = 9'b101110011;
parameter ap_ST_st372_fsm_372 = 9'b101110100;
parameter ap_ST_st373_fsm_373 = 9'b101110101;
parameter ap_ST_st374_fsm_374 = 9'b101110110;
parameter ap_ST_st375_fsm_375 = 9'b101110111;
parameter ap_ST_st376_fsm_376 = 9'b101111000;
parameter ap_ST_st377_fsm_377 = 9'b101111001;
parameter ap_ST_st378_fsm_378 = 9'b101111010;
parameter ap_ST_st379_fsm_379 = 9'b101111011;
parameter ap_ST_st380_fsm_380 = 9'b101111100;
parameter ap_ST_st381_fsm_381 = 9'b101111101;
parameter ap_ST_st382_fsm_382 = 9'b101111110;
parameter ap_ST_st383_fsm_383 = 9'b101111111;
parameter ap_ST_st384_fsm_384 = 9'b110000000;
parameter ap_ST_st385_fsm_385 = 9'b110000001;
parameter ap_ST_st386_fsm_386 = 9'b110000010;
parameter ap_ST_st387_fsm_387 = 9'b110000011;
parameter ap_ST_st388_fsm_388 = 9'b110000100;
parameter ap_ST_st389_fsm_389 = 9'b110000101;
parameter ap_ST_st390_fsm_390 = 9'b110000110;
parameter ap_ST_st391_fsm_391 = 9'b110000111;
parameter ap_ST_st392_fsm_392 = 9'b110001000;
parameter ap_ST_st393_fsm_393 = 9'b110001001;
parameter ap_ST_st394_fsm_394 = 9'b110001010;
parameter ap_ST_st395_fsm_395 = 9'b110001011;
parameter ap_ST_st396_fsm_396 = 9'b110001100;
parameter ap_ST_st397_fsm_397 = 9'b110001101;
parameter ap_ST_st398_fsm_398 = 9'b110001110;
parameter ap_ST_st399_fsm_399 = 9'b110001111;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_1F = 32'b00000000000000000000000000011111;
parameter ap_const_lv32_3F800000 = 32'b00111111100000000000000000000000;
parameter ap_const_lv32_80000000 = 32'b10000000000000000000000000000000;
parameter ap_const_lv32_42C80000 = 32'b01000010110010000000000000000000;
parameter ap_const_lv64_3FF0000000000000 = 64'b0011111111110000000000000000000000000000000000000000000000000000;
parameter ap_const_lv64_3FC999999999999A = 64'b0011111111001001100110011001100110011001100110011001100110011010;
parameter ap_const_lv64_3FE0000000000000 = 64'b0011111111100000000000000000000000000000000000000000000000000000;
parameter ap_const_lv64_40D0000000000000 = 64'b0100000011010000000000000000000000000000000000000000000000000000;
parameter ap_const_lv15_7 = 15'b000000000000111;
parameter ap_const_lv15_101 = 15'b000000100000001;
parameter ap_const_lv15_81 = 15'b000000010000001;
parameter ap_const_lv8_80 = 8'b10000000;
parameter ap_const_lv64_1 = 64'b0000000000000000000000000000000000000000000000000000000000000001;
parameter ap_const_lv16_7 = 16'b0000000000000111;
parameter ap_const_lv32_33 = 32'b00000000000000000000000000110011;
parameter ap_const_lv7_7F = 7'b1111111;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv32_2 = 32'b00000000000000000000000000000010;
parameter ap_const_lv30_1 = 30'b000000000000000000000000000001;
parameter ap_const_lv32_5 = 32'b00000000000000000000000000000101;
parameter ap_const_lv8_2 = 8'b00000010;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_const_lv5_1 = 5'b00001;
parameter ap_const_lv5_4 = 5'b00100;
parameter ap_const_lv5_E = 5'b01110;
parameter ap_const_lv5_2 = 5'b00010;
parameter ap_true = 1'b1;
jacob_b #(
.DataWidth( 32 ),
.AddressRange( 128 ),
.AddressWidth( 7 ))
b_U(
.clk( ap_clk ),
.address0( b_address0 ),
.ce0( b_ce0 ),
.we0( b_we0 ),
.d0( b_d0 ),
.q0( b_q0 )
);
jacob_z #(
.DataWidth( 32 ),
.AddressRange( 128 ),
.AddressWidth( 7 ))
z_U(
.clk( ap_clk ),
.address0( z_address0 ),
.ce0( z_ce0 ),
.we0( z_we0 ),
.d0( z_d0 ),
.q0( z_q0 ),
.address1( z_address1 ),
.ce1( z_ce1 ),
.we1( z_we1 ),
.d1( z_d1 ),
.q1( z_q1 )
);
do_rotate grp_do_rotate_fu_497(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_do_rotate_fu_497_ap_start ),
.ap_done( grp_do_rotate_fu_497_ap_done ),
.ap_idle( grp_do_rotate_fu_497_ap_idle ),
.a_address0( grp_do_rotate_fu_497_a_address0 ),
.a_ce0( grp_do_rotate_fu_497_a_ce0 ),
.a_we0( grp_do_rotate_fu_497_a_we0 ),
.a_d0( grp_do_rotate_fu_497_a_d0 ),
.a_q0( grp_do_rotate_fu_497_a_q0 ),
.a_address1( grp_do_rotate_fu_497_a_address1 ),
.a_ce1( grp_do_rotate_fu_497_a_ce1 ),
.a_we1( grp_do_rotate_fu_497_a_we1 ),
.a_d1( grp_do_rotate_fu_497_a_d1 ),
.a_q1( grp_do_rotate_fu_497_a_q1 ),
.v_address0( grp_do_rotate_fu_497_v_address0 ),
.v_ce0( grp_do_rotate_fu_497_v_ce0 ),
.v_we0( grp_do_rotate_fu_497_v_we0 ),
.v_d0( grp_do_rotate_fu_497_v_d0 ),
.v_q0( grp_do_rotate_fu_497_v_q0 ),
.v_address1( grp_do_rotate_fu_497_v_address1 ),
.v_ce1( grp_do_rotate_fu_497_v_ce1 ),
.v_we1( grp_do_rotate_fu_497_v_we1 ),
.v_d1( grp_do_rotate_fu_497_v_d1 ),
.v_q1( grp_do_rotate_fu_497_v_q1 ),
.s( grp_do_rotate_fu_497_s ),
.tau( grp_do_rotate_fu_497_tau ),
.ip( grp_do_rotate_fu_497_ip ),
.iq( grp_do_rotate_fu_497_iq )
);
jacob_grp_fu_509_ACMP_faddfsub_11 #(
.ID( 11 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_509_ACMP_faddfsub_11_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_509_p0 ),
.din1( grp_fu_509_p1 ),
.opcode( grp_fu_509_opcode ),
.ce( grp_fu_509_ce ),
.dout( grp_fu_509_p2 )
);
jacob_grp_fu_516_ACMP_fadd_12 #(
.ID( 12 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_516_ACMP_fadd_12_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_516_p0 ),
.din1( grp_fu_516_p1 ),
.ce( grp_fu_516_ce ),
.dout( grp_fu_516_p2 )
);
jacob_grp_fu_520_ACMP_fsub_13 #(
.ID( 13 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_520_ACMP_fsub_13_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_520_p0 ),
.din1( grp_fu_520_p1 ),
.ce( grp_fu_520_ce ),
.dout( grp_fu_520_p2 )
);
jacob_grp_fu_524_ACMP_fadd_14 #(
.ID( 14 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_524_ACMP_fadd_14_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_524_p0 ),
.din1( grp_fu_524_p1 ),
.ce( grp_fu_524_ce ),
.dout( grp_fu_524_p2 )
);
jacob_grp_fu_528_ACMP_fmul_15 #(
.ID( 15 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_528_ACMP_fmul_15_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_528_p0 ),
.din1( grp_fu_528_p1 ),
.ce( grp_fu_528_ce ),
.dout( grp_fu_528_p2 )
);
jacob_grp_fu_537_ACMP_fdiv_16 #(
.ID( 16 ),
.NUM_STAGE( 12 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_537_ACMP_fdiv_16_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_537_p0 ),
.din1( grp_fu_537_p1 ),
.ce( grp_fu_537_ce ),
.dout( grp_fu_537_p2 )
);
jacob_grp_fu_541_ACMP_fptrunc_17 #(
.ID( 17 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_541_ACMP_fptrunc_17_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_541_p0 ),
.ce( grp_fu_541_ce ),
.dout( grp_fu_541_p1 )
);
jacob_grp_fu_544_ACMP_fptrunc_18 #(
.ID( 18 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_544_ACMP_fptrunc_18_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_544_p0 ),
.ce( grp_fu_544_ce ),
.dout( grp_fu_544_p1 )
);
jacob_grp_fu_547_ACMP_fptrunc_19 #(
.ID( 19 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_547_ACMP_fptrunc_19_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_547_p0 ),
.ce( grp_fu_547_ce ),
.dout( grp_fu_547_p1 )
);
jacob_grp_fu_550_ACMP_fptrunc_20 #(
.ID( 20 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_550_ACMP_fptrunc_20_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_550_p0 ),
.ce( grp_fu_550_ce ),
.dout( grp_fu_550_p1 )
);
jacob_grp_fu_553_ACMP_fptrunc_21 #(
.ID( 21 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_553_ACMP_fptrunc_21_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_553_p0 ),
.ce( grp_fu_553_ce ),
.dout( grp_fu_553_p1 )
);
jacob_grp_fu_557_ACMP_fpext_22 #(
.ID( 22 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_557_ACMP_fpext_22_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_557_p0 ),
.ce( grp_fu_557_ce ),
.dout( grp_fu_557_p1 )
);
jacob_grp_fu_561_ACMP_fpext_23 #(
.ID( 23 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_561_ACMP_fpext_23_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_561_p0 ),
.ce( grp_fu_561_ce ),
.dout( grp_fu_561_p1 )
);
jacob_grp_fu_564_ACMP_fpext_24 #(
.ID( 24 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_564_ACMP_fpext_24_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_564_p0 ),
.ce( grp_fu_564_ce ),
.dout( grp_fu_564_p1 )
);
jacob_grp_fu_567_ACMP_fpext_25 #(
.ID( 25 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_567_ACMP_fpext_25_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_567_p0 ),
.ce( grp_fu_567_ce ),
.dout( grp_fu_567_p1 )
);
jacob_grp_fu_570_ACMP_fpext_26 #(
.ID( 26 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_570_ACMP_fpext_26_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_570_p0 ),
.ce( grp_fu_570_ce ),
.dout( grp_fu_570_p1 )
);
jacob_grp_fu_573_ACMP_fpext_27 #(
.ID( 27 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_573_ACMP_fpext_27_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_573_p0 ),
.ce( grp_fu_573_ce ),
.dout( grp_fu_573_p1 )
);
jacob_grp_fu_576_ACMP_fpext_28 #(
.ID( 28 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_576_ACMP_fpext_28_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_576_p0 ),
.ce( grp_fu_576_ce ),
.dout( grp_fu_576_p1 )
);
jacob_grp_fu_580_ACMP_fpext_29 #(
.ID( 29 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_580_ACMP_fpext_29_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_580_p0 ),
.ce( grp_fu_580_ce ),
.dout( grp_fu_580_p1 )
);
jacob_grp_fu_583_ACMP_fcmp_30 #(
.ID( 30 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_583_ACMP_fcmp_30_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_583_p0 ),
.din1( grp_fu_583_p1 ),
.ce( grp_fu_583_ce ),
.opcode( grp_fu_583_opcode ),
.dout( grp_fu_583_p2 )
);
jacob_grp_fu_589_ACMP_fcmp_31 #(
.ID( 31 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_589_ACMP_fcmp_31_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_589_p0 ),
.din1( grp_fu_589_p1 ),
.ce( grp_fu_589_ce ),
.opcode( grp_fu_589_opcode ),
.dout( grp_fu_589_p2 )
);
jacob_grp_fu_596_ACMP_fcmp_32 #(
.ID( 32 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_596_ACMP_fcmp_32_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_596_p0 ),
.din1( grp_fu_596_p1 ),
.ce( grp_fu_596_ce ),
.opcode( grp_fu_596_opcode ),
.dout( grp_fu_596_p2 )
);
jacob_grp_fu_600_ACMP_fcmp_33 #(
.ID( 33 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_600_ACMP_fcmp_33_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_600_p0 ),
.din1( grp_fu_600_p1 ),
.ce( grp_fu_600_ce ),
.opcode( grp_fu_600_opcode ),
.dout( grp_fu_600_p2 )
);
jacob_grp_fu_604_ACMP_fcmp_34 #(
.ID( 34 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_604_ACMP_fcmp_34_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_604_p0 ),
.din1( grp_fu_604_p1 ),
.ce( grp_fu_604_ce ),
.opcode( grp_fu_604_opcode ),
.dout( grp_fu_604_p2 )
);
jacob_grp_fu_609_ACMP_fcmp_35 #(
.ID( 35 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_609_ACMP_fcmp_35_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_609_p0 ),
.din1( grp_fu_609_p1 ),
.ce( grp_fu_609_ce ),
.opcode( grp_fu_609_opcode ),
.dout( grp_fu_609_p2 )
);
jacob_grp_fu_613_ACMP_fcmp_36 #(
.ID( 36 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_613_ACMP_fcmp_36_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_613_p0 ),
.din1( grp_fu_613_p1 ),
.ce( grp_fu_613_ce ),
.opcode( grp_fu_613_opcode ),
.dout( grp_fu_613_p2 )
);
jacob_grp_fu_618_ACMP_dadd_37 #(
.ID( 37 ),
.NUM_STAGE( 6 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_618_ACMP_dadd_37_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_618_p0 ),
.din1( grp_fu_618_p1 ),
.ce( grp_fu_618_ce ),
.dout( grp_fu_618_p2 )
);
jacob_grp_fu_623_ACMP_dmul_38 #(
.ID( 38 ),
.NUM_STAGE( 7 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_623_ACMP_dmul_38_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_623_p0 ),
.din1( grp_fu_623_p1 ),
.ce( grp_fu_623_ce ),
.dout( grp_fu_623_p2 )
);
jacob_grp_fu_629_ACMP_ddiv_39 #(
.ID( 39 ),
.NUM_STAGE( 34 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_629_ACMP_ddiv_39_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_629_p0 ),
.din1( grp_fu_629_p1 ),
.ce( grp_fu_629_ce ),
.dout( grp_fu_629_p2 )
);
jacob_grp_fu_635_ACMP_dsqrt_40 #(
.ID( 40 ),
.NUM_STAGE( 30 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_635_ACMP_dsqrt_40_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_635_p0 ),
.din1( grp_fu_635_p1 ),
.ce( grp_fu_635_ce ),
.dout( grp_fu_635_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
if (tmp_i1_reg_1344) begin
UnifiedRetVal_i1_reg_1349 <= reg_649;
end else begin
UnifiedRetVal_i1_reg_1349 <= reg_640;
end
end
if ((ap_ST_st85_fsm_85 == ap_CS_fsm)) begin
if (tmp_i2_reg_1362) begin
UnifiedRetVal_i2_reg_1367 <= reg_649;
end else begin
UnifiedRetVal_i2_reg_1367 <= reg_684;
end
end
if ((ap_ST_st99_fsm_99 == ap_CS_fsm)) begin
if (tmp_i3_reg_1382) begin
UnifiedRetVal_i3_reg_1387 <= reg_649;
end else begin
UnifiedRetVal_i3_reg_1387 <= reg_684;
end
end
if ((ap_ST_st119_fsm_119 == ap_CS_fsm)) begin
if (tmp_i4_reg_1416) begin
UnifiedRetVal_i4_reg_1421 <= reg_692;
end else begin
UnifiedRetVal_i4_reg_1421 <= reg_649;
end
end
if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
if (tmp_i_reg_1236) begin
UnifiedRetVal_i_reg_1241 <= reg_649;
end else begin
UnifiedRetVal_i_reg_1241 <= reg_640;
end
end
if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
a_addr_2_reg_1334 <= a_addr_2_reg_13340;
end
if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
b_addr_1_reg_1557 <= b_addr_1_reg_15570;
end
if ((ap_ST_st393_fsm_393 == ap_CS_fsm)) begin
b_load_reg_1577 <= b_q0;
end
if ((ap_ST_st347_fsm_347 == ap_CS_fsm)) begin
c_reg_1523 <= grp_fu_550_p1;
end
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
d_addr_1_reg_1300 <= d_addr_1_reg_13000;
end
if (((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2))) begin
d_addr_4_reg_1404 <= tmp_26_reg_1355;
end
if ((ap_ST_st108_fsm_108 == ap_CS_fsm)) begin
d_load_3_reg_1410 <= d_q1;
end
if (((ap_ST_st4_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_790_p2))) begin
indvar10_reg_309 <= ap_const_lv32_1;
end else if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
indvar10_reg_309 <= (indvar10_reg_309 + ap_const_lv32_1);
end
if ((((ap_ST_st391_fsm_391 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_do_rotate_fu_497_ap_done)) | ((ap_ST_st107_fsm_107 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_604_p2)) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
indvar1_reg_434 <= indvar_next2_reg_1327;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
indvar1_reg_434 <= ap_const_lv7_0;
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar2_reg_253 <= ap_const_lv8_0;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
indvar2_reg_253 <= indvar_next3_reg_1155;
end
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
indvar3_cast_reg_1282[0] <= indvar3_cast_fu_967_p1[0];
indvar3_cast_reg_1282[1] <= indvar3_cast_fu_967_p1[1];
indvar3_cast_reg_1282[2] <= indvar3_cast_fu_967_p1[2];
indvar3_cast_reg_1282[3] <= indvar3_cast_fu_967_p1[3];
indvar3_cast_reg_1282[4] <= indvar3_cast_fu_967_p1[4];
indvar3_cast_reg_1282[5] <= indvar3_cast_fu_967_p1[5];
indvar3_cast_reg_1282[6] <= indvar3_cast_fu_967_p1[6];
end
if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
indvar3_reg_411 <= ap_const_lv7_0;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
indvar3_reg_411 <= tmp_19_reg_1292;
end
if (((ap_ST_st2_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_746_p2))) begin
indvar4_reg_286 <= ap_const_lv8_0;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
indvar4_reg_286 <= indvar_next1_reg_1176;
end
if (((ap_ST_st2_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_746_p2))) begin
indvar5_reg_275 <= ap_const_lv8_0;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
indvar5_reg_275 <= (indvar5_reg_275 + ap_const_lv8_1);
end
if (((ap_ST_st2_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_746_p2))) begin
indvar6_reg_264 <= ap_const_lv64_0;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
indvar6_reg_264 <= (indvar6_reg_264 + ap_const_lv64_1);
end
if (((ap_ST_st6_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_fu_836_p2))) begin
indvar7_reg_321 <= ap_const_lv7_0;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_880_p2))) begin
indvar7_reg_321 <= tmp_4_reg_1205;
end
if (((ap_ST_st7_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_868_p2))) begin
indvar8_reg_356 <= ap_const_lv7_0;
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
indvar8_reg_356 <= indvar_next5_reg_1221;
end
if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
indvar9_reg_400 <= ap_const_lv7_0;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
indvar9_reg_400 <= tmp_18_reg_1276;
end
if ((ap_ST_st4_fsm_4 == ap_CS_fsm)) begin
indvar_next1_reg_1176 <= (indvar4_reg_286 + ap_const_lv8_1);
end
if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
indvar_next2_reg_1327 <= (indvar1_reg_434 + ap_const_lv7_1);
end
if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
indvar_next3_reg_1155 <= (indvar2_reg_253 + ap_const_lv8_1);
end
if ((ap_ST_st8_fsm_8 == ap_CS_fsm)) begin
indvar_next5_reg_1221 <= (indvar8_reg_356 + ap_const_lv7_1);
end
if ((ap_ST_st392_fsm_392 == ap_CS_fsm)) begin
indvar_next_reg_1547 <= (indvar_reg_474 + ap_const_lv8_1);
end
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
indvar_reg_474 <= ap_const_lv8_0;
end else if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
indvar_reg_474 <= indvar_next_reg_1547;
end
if (((ap_ST_st2_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_746_p2))) begin
ip_1_reg_297 <= ap_const_lv8_1;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
ip_1_reg_297 <= (ip_1_reg_297 + ap_const_lv8_1);
end
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
ip_4_reg_485 <= ap_const_lv8_1;
end else if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
ip_4_reg_485 <= tmp_24_reg_1567;
end
if (((ap_ST_st7_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_868_p2))) begin
iq_1_in_reg_367 <= {{24{1'b0}}, {ip_2_fu_852_p2}};
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
iq_1_in_reg_367 <= iq_1_reg_1213;
end
if ((ap_ST_st8_fsm_8 == ap_CS_fsm)) begin
iq_1_reg_1213 <= (iq_1_in_reg_367 + ap_const_lv32_1);
end
if ((((ap_ST_st391_fsm_391 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_do_rotate_fu_497_ap_done)) | ((ap_ST_st107_fsm_107 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_604_p2)) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
iq_2_in_reg_449 <= tmp_21_reg_1316;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
iq_2_in_reg_449 <= {{24{1'b0}}, {ip_3_fu_971_p2}};
end
if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
iq_2_reg_1311 <= (tmp3_cast_fu_1009_p1 + indvar3_cast_reg_1282);
end
if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm))) begin
reg_640 <= a_q0;
end
if (((ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st113_fsm_113 == ap_CS_fsm) | ((ap_ST_st210_fsm_210 == ap_CS_fsm) & (tmp_i5_reg_1449 == ap_const_lv1_1)) | (ap_ST_st279_fsm_279 == ap_CS_fsm) | (ap_ST_st398_fsm_398 == ap_CS_fsm))) begin
reg_649 <= grp_fu_509_p2;
end
if (((ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st134_fsm_134 == ap_CS_fsm))) begin
reg_661 <= grp_fu_623_p2;
end
if (((ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st168_fsm_168 == ap_CS_fsm) | (ap_ST_st252_fsm_252 == ap_CS_fsm) | (ap_ST_st345_fsm_345 == ap_CS_fsm) | (ap_ST_st388_fsm_388 == ap_CS_fsm))) begin
reg_666 <= grp_fu_629_p2;
end
if (((ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st174_fsm_174 == ap_CS_fsm) | (ap_ST_st274_fsm_274 == ap_CS_fsm) | (ap_ST_st351_fsm_351 == ap_CS_fsm))) begin
reg_675 <= grp_fu_528_p2;
end
if (((ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st275_fsm_275 == ap_CS_fsm))) begin
reg_684 <= d_q0;
end
if (((ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st280_fsm_280 == ap_CS_fsm))) begin
reg_692 <= grp_fu_509_p2;
end
if (((ap_ST_st182_fsm_182 == ap_CS_fsm) | (ap_ST_st218_fsm_218 == ap_CS_fsm) | (ap_ST_st354_fsm_354 == ap_CS_fsm))) begin
reg_698 <= grp_fu_618_p2;
end
if (((ap_ST_st212_fsm_212 == ap_CS_fsm) | (ap_ST_st311_fsm_311 == ap_CS_fsm))) begin
reg_704 <= grp_fu_635_p2;
end
if (((ap_ST_st275_fsm_275 == ap_CS_fsm) | (ap_ST_st393_fsm_393 == ap_CS_fsm))) begin
reg_710 <= z_q0;
end
if (((ap_ST_st6_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_fu_836_p2))) begin
sm_1_reg_344 <= ap_const_lv32_0;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_880_p2))) begin
sm_1_reg_344 <= sm_reg_376;
end
if (((ap_ST_st7_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_868_p2))) begin
sm_reg_376 <= sm_1_reg_344;
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
sm_reg_376 <= grp_fu_509_p2;
end
if (((ap_ST_st254_fsm_254 == ap_CS_fsm) & (tmp_i5_reg_1449 == ap_const_lv1_0))) begin
t_reg_462 <= grp_fu_547_p1;
end else if ((ap_ST_st259_fsm_259 == ap_CS_fsm)) begin
t_reg_462 <= grp_fu_509_p2;
end else if ((ap_ST_st270_fsm_270 == ap_CS_fsm)) begin
t_reg_462 <= grp_fu_537_p2;
end
if ((ap_ST_st390_fsm_390 == ap_CS_fsm)) begin
tau_reg_1539 <= grp_fu_553_p1;
end
if ((ap_ST_st170_fsm_170 == ap_CS_fsm)) begin
theta_reg_1440 <= grp_fu_544_p1;
end
if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
tmp36_cast_reg_1147[7] <= tmp36_cast_fu_742_p1[7];
tmp36_cast_reg_1147[8] <= tmp36_cast_fu_742_p1[8];
tmp36_cast_reg_1147[9] <= tmp36_cast_fu_742_p1[9];
tmp36_cast_reg_1147[10] <= tmp36_cast_fu_742_p1[10];
tmp36_cast_reg_1147[11] <= tmp36_cast_fu_742_p1[11];
tmp36_cast_reg_1147[12] <= tmp36_cast_fu_742_p1[12];
tmp36_cast_reg_1147[13] <= tmp36_cast_fu_742_p1[13];
tmp36_cast_reg_1147[14] <= tmp36_cast_fu_742_p1[14];
end
if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
tmp4_reg_1195 <= (indvar7_reg_321 ^ ap_const_lv7_7F);
end
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
tmp5_reg_1271 <= (indvar9_reg_400 ^ ap_const_lv7_7F);
end
if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
tmp_13_reg_1267 <= ($signed(indvar10_reg_309) < $signed(32'b00000000000000000000000000000101)? 1'b1: 1'b0);
end
if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
tmp_17_reg_422 <= ap_const_lv8_1;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
tmp_17_reg_422 <= (tmp_17_reg_422 + ap_const_lv8_1);
end
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
tmp_18_reg_1276 <= (indvar9_reg_400 + ap_const_lv7_1);
end
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
tmp_19_reg_1292 <= (indvar3_reg_411 + ap_const_lv7_1);
end
if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
tmp_21_reg_1316 <= (iq_2_in_reg_449 + ap_const_lv32_1);
end
if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
tmp_22_reg_1552[0] <= tmp_22_fu_1124_p1[0];
tmp_22_reg_1552[1] <= tmp_22_fu_1124_p1[1];
tmp_22_reg_1552[2] <= tmp_22_fu_1124_p1[2];
tmp_22_reg_1552[3] <= tmp_22_fu_1124_p1[3];
tmp_22_reg_1552[4] <= tmp_22_fu_1124_p1[4];
tmp_22_reg_1552[5] <= tmp_22_fu_1124_p1[5];
tmp_22_reg_1552[6] <= tmp_22_fu_1124_p1[6];
tmp_22_reg_1552[7] <= tmp_22_fu_1124_p1[7];
end
if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
tmp_24_reg_1567 <= (ip_4_reg_485 + ap_const_lv8_1);
end
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
tmp_26_reg_1355 <= {{32{tmp_21_reg_1316[31]}}, {tmp_21_reg_1316}};
end
if ((ap_ST_st92_fsm_92 == ap_CS_fsm)) begin
tmp_28_reg_1373 <= grp_fu_596_p2;
end
if ((ap_ST_st104_fsm_104 == ap_CS_fsm)) begin
tmp_29_reg_1393 <= grp_fu_509_p2;
end
if ((ap_ST_st127_fsm_127 == ap_CS_fsm)) begin
tmp_36_reg_1430 <= grp_fu_561_p1;
end
if ((ap_ST_st134_fsm_134 == ap_CS_fsm)) begin
tmp_38_reg_1435 <= grp_fu_564_p1;
end
if ((ap_ST_st212_fsm_212 == ap_CS_fsm)) begin
tmp_40_reg_1464 <= grp_fu_570_p1;
end
if ((ap_ST_st176_fsm_176 == ap_CS_fsm)) begin
tmp_42_reg_1454 <= grp_fu_567_p1;
end
if ((ap_ST_st254_fsm_254 == ap_CS_fsm)) begin
tmp_47_reg_1469 <= grp_fu_547_p1;
end
if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
tmp_4_reg_1205 <= (indvar7_reg_321 + ap_const_lv7_1);
end
if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
tmp_52_reg_1518 <= grp_fu_573_p1;
end
if ((ap_ST_st354_fsm_354 == ap_CS_fsm)) begin
tmp_55_reg_1534 <= grp_fu_580_p1;
end
if ((ap_ST_st348_fsm_348 == ap_CS_fsm)) begin
tmp_56_reg_1529 <= grp_fu_576_p1;
end
if ((ap_ST_st275_fsm_275 == ap_CS_fsm)) begin
tmp_59_reg_1490 <= grp_fu_528_p2;
end
if ((ap_ST_st280_fsm_280 == ap_CS_fsm)) begin
tmp_61_reg_1503 <= grp_fu_516_p2;
end
if ((ap_ST_st280_fsm_280 == ap_CS_fsm)) begin
tmp_62_reg_1508 <= grp_fu_520_p2;
end
if ((ap_ST_st280_fsm_280 == ap_CS_fsm)) begin
tmp_63_reg_1513 <= grp_fu_524_p2;
end
if ((ap_ST_st6_fsm_6 == ap_CS_fsm)) begin
tmp_6_reg_1191 <= ($signed(indvar10_reg_309) < $signed(32'b00000000000000000000000000110011)? 1'b1: 1'b0);
end
if (((ap_ST_st6_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_fu_836_p2))) begin
tmp_7_reg_332 <= ap_const_lv8_1;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_880_p2))) begin
tmp_7_reg_332 <= (tmp_7_reg_332 + ap_const_lv8_1);
end
if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
tmp_9_cast_reg_1142[7] <= tmp_9_cast_fu_732_p1[7];
tmp_9_cast_reg_1142[8] <= tmp_9_cast_fu_732_p1[8];
tmp_9_cast_reg_1142[9] <= tmp_9_cast_fu_732_p1[9];
tmp_9_cast_reg_1142[10] <= tmp_9_cast_fu_732_p1[10];
tmp_9_cast_reg_1142[11] <= tmp_9_cast_fu_732_p1[11];
tmp_9_cast_reg_1142[12] <= tmp_9_cast_fu_732_p1[12];
tmp_9_cast_reg_1142[13] <= tmp_9_cast_fu_732_p1[13];
tmp_9_cast_reg_1142[14] <= tmp_9_cast_fu_732_p1[14];
end
if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
tmp_i1_reg_1344 <= grp_fu_589_p2;
end
if ((ap_ST_st80_fsm_80 == ap_CS_fsm)) begin
tmp_i2_reg_1362 <= grp_fu_589_p2;
end
if ((ap_ST_st94_fsm_94 == ap_CS_fsm)) begin
tmp_i3_reg_1382 <= grp_fu_589_p2;
end
if ((ap_ST_st115_fsm_115 == ap_CS_fsm)) begin
tmp_i4_reg_1416 <= grp_fu_589_p2;
end
if ((ap_ST_st172_fsm_172 == ap_CS_fsm)) begin
tmp_i5_reg_1449 <= grp_fu_613_p2;
end
if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
tmp_i_reg_1236 <= grp_fu_589_p2;
end
if ((ap_ST_st22_fsm_22 == ap_CS_fsm)) begin
tmp_s_reg_1257 <= grp_fu_557_p1;
end
if (((ap_ST_st21_fsm_21 == ap_CS_fsm) & (ap_const_lv1_0 == icmp_fu_939_p2) & ~(ap_const_lv1_0 == tmp_6_reg_1191) & (ap_const_lv1_0 == grp_fu_583_p2))) begin
tresh_reg_388 <= ap_const_lv32_0;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
tresh_reg_388 <= grp_fu_541_p1;
end
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
z_addr_1_reg_1306 <= z_addr_1_reg_13060;
end
if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
z_addr_2_reg_1562 <= z_addr_2_reg_15620;
end
if ((ap_ST_st271_fsm_271 == ap_CS_fsm)) begin
z_addr_3_reg_1485 <= tmp_26_reg_1355;
end
if ((ap_ST_st275_fsm_275 == ap_CS_fsm)) begin
z_load_2_reg_1498 <= z_q1;
end
end
/// a_address0 assign process. ///
always @ (ap_CS_fsm or exitcond1_fu_790_p2 or exitcond4_fu_880_p2 or tmp_13_reg_1267 or a_addr_2_reg_1334 or exitcond7_fu_1024_p2 or tmp_28_reg_1373 or grp_do_rotate_fu_497_a_address0 or grp_fu_600_p2 or tmp_1_fu_818_p1 or tmp_15_fu_911_p1 or tmp_48_fu_1055_p1)
begin
if (((ap_ST_st271_fsm_271 == ap_CS_fsm) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
a_address0 = a_addr_2_reg_1334;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
a_address0 = tmp_48_fu_1055_p1;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond4_fu_880_p2))) begin
a_address0 = tmp_15_fu_911_p1;
end else if (((ap_ST_st4_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_790_p2))) begin
a_address0 = tmp_1_fu_818_p1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_address0 = grp_do_rotate_fu_497_a_address0;
end else begin
a_address0 = grp_do_rotate_fu_497_a_address0;
end
end
/// a_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond1_fu_790_p2 or exitcond4_fu_880_p2 or tmp_13_reg_1267 or exitcond7_fu_1024_p2 or tmp_28_reg_1373 or grp_do_rotate_fu_497_a_ce0 or grp_fu_600_p2)
begin
if ((((ap_ST_st4_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_790_p2)) | ((ap_ST_st8_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond4_fu_880_p2)) | ((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond7_fu_1024_p2)) | (ap_ST_st271_fsm_271 == ap_CS_fsm) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
a_ce0 = ap_const_logic_1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_ce0 = grp_do_rotate_fu_497_a_ce0;
end else begin
a_ce0 = ap_const_logic_0;
end
end
/// a_ce1 assign process. ///
always @ (ap_CS_fsm or grp_do_rotate_fu_497_a_ce1)
begin
if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_ce1 = grp_do_rotate_fu_497_a_ce1;
end else begin
a_ce1 = ap_const_logic_0;
end
end
/// a_d0 assign process. ///
always @ (ap_CS_fsm or tmp_13_reg_1267 or tmp_28_reg_1373 or grp_do_rotate_fu_497_a_d0 or grp_fu_600_p2)
begin
if (((ap_ST_st271_fsm_271 == ap_CS_fsm) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
a_d0 = ap_const_lv32_0;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_d0 = grp_do_rotate_fu_497_a_d0;
end else begin
a_d0 = ap_const_lv32_0;
end
end
/// a_we0 assign process. ///
always @ (ap_CS_fsm or tmp_13_reg_1267 or tmp_28_reg_1373 or grp_do_rotate_fu_497_a_we0 or grp_fu_600_p2)
begin
if (((ap_ST_st271_fsm_271 == ap_CS_fsm) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
a_we0 = ap_const_logic_1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_we0 = grp_do_rotate_fu_497_a_we0;
end else begin
a_we0 = ap_const_logic_0;
end
end
/// a_we1 assign process. ///
always @ (ap_CS_fsm or grp_do_rotate_fu_497_a_we1)
begin
if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_we1 = grp_do_rotate_fu_497_a_we1;
end else begin
a_we1 = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or tmp_i5_reg_1449 or exitcond2_fu_772_p2 or exitcond1_fu_790_p2 or tmp_6_fu_836_p2 or tmp_6_reg_1191 or exitcond4_fu_880_p2 or tmp_13_reg_1267 or exitcond5_fu_987_p2 or exitcond7_fu_1024_p2 or grp_fu_596_p2 or tmp_28_reg_1373 or grp_fu_604_p2 or exitcond6_fu_1112_p2 or grp_do_rotate_fu_497_ap_done or exitcond_fu_746_p2 or exitcond3_fu_868_p2 or icmp_fu_939_p2 or grp_fu_583_p2 or grp_fu_600_p2 or grp_fu_609_p2)
begin
if ((ap_ST_st398_fsm_398 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st399_fsm_399;
end else if ((ap_ST_st397_fsm_397 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st398_fsm_398;
end else if ((ap_ST_st396_fsm_396 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st397_fsm_397;
end else if ((ap_ST_st395_fsm_395 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st396_fsm_396;
end else if ((ap_ST_st394_fsm_394 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st395_fsm_395;
end else if ((ap_ST_st393_fsm_393 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st394_fsm_394;
end else if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
ap_NS_fsm = ap_ST_st393_fsm_393;
end else if ((ap_ST_st390_fsm_390 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st391_fsm_391;
end else if ((ap_ST_st389_fsm_389 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st390_fsm_390;
end else if ((ap_ST_st388_fsm_388 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st389_fsm_389;
end else if ((ap_ST_st387_fsm_387 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st388_fsm_388;
end else if ((ap_ST_st386_fsm_386 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st387_fsm_387;
end else if ((ap_ST_st385_fsm_385 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st386_fsm_386;
end else if ((ap_ST_st384_fsm_384 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st385_fsm_385;
end else if ((ap_ST_st383_fsm_383 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st384_fsm_384;
end else if ((ap_ST_st382_fsm_382 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st383_fsm_383;
end else if ((ap_ST_st381_fsm_381 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st382_fsm_382;
end else if ((ap_ST_st380_fsm_380 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st381_fsm_381;
end else if ((ap_ST_st379_fsm_379 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st380_fsm_380;
end else if ((ap_ST_st378_fsm_378 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st379_fsm_379;
end else if ((ap_ST_st377_fsm_377 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st378_fsm_378;
end else if ((ap_ST_st376_fsm_376 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st377_fsm_377;
end else if ((ap_ST_st375_fsm_375 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st376_fsm_376;
end else if ((ap_ST_st374_fsm_374 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st375_fsm_375;
end else if ((ap_ST_st373_fsm_373 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st374_fsm_374;
end else if ((ap_ST_st372_fsm_372 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st373_fsm_373;
end else if ((ap_ST_st371_fsm_371 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st372_fsm_372;
end else if ((ap_ST_st370_fsm_370 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st371_fsm_371;
end else if ((ap_ST_st369_fsm_369 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st370_fsm_370;
end else if ((ap_ST_st368_fsm_368 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st369_fsm_369;
end else if ((ap_ST_st367_fsm_367 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st368_fsm_368;
end else if ((ap_ST_st366_fsm_366 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st367_fsm_367;
end else if ((ap_ST_st365_fsm_365 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st366_fsm_366;
end else if ((ap_ST_st364_fsm_364 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st365_fsm_365;
end else if ((ap_ST_st363_fsm_363 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st364_fsm_364;
end else if ((ap_ST_st362_fsm_362 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st363_fsm_363;
end else if ((ap_ST_st361_fsm_361 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st362_fsm_362;
end else if ((ap_ST_st360_fsm_360 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st361_fsm_361;
end else if ((ap_ST_st359_fsm_359 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st360_fsm_360;
end else if ((ap_ST_st358_fsm_358 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st359_fsm_359;
end else if ((ap_ST_st357_fsm_357 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st358_fsm_358;
end else if ((ap_ST_st356_fsm_356 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st357_fsm_357;
end else if ((ap_ST_st355_fsm_355 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st356_fsm_356;
end else if ((ap_ST_st354_fsm_354 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st355_fsm_355;
end else if ((ap_ST_st353_fsm_353 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st354_fsm_354;
end else if ((ap_ST_st352_fsm_352 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st353_fsm_353;
end else if ((ap_ST_st351_fsm_351 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st352_fsm_352;
end else if ((ap_ST_st350_fsm_350 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st351_fsm_351;
end else if ((ap_ST_st349_fsm_349 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st350_fsm_350;
end else if ((ap_ST_st348_fsm_348 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st349_fsm_349;
end else if ((ap_ST_st347_fsm_347 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st348_fsm_348;
end else if ((ap_ST_st346_fsm_346 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st347_fsm_347;
end else if ((ap_ST_st345_fsm_345 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st346_fsm_346;
end else if ((ap_ST_st344_fsm_344 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st345_fsm_345;
end else if ((ap_ST_st343_fsm_343 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st344_fsm_344;
end else if ((ap_ST_st342_fsm_342 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st343_fsm_343;
end else if ((ap_ST_st341_fsm_341 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st342_fsm_342;
end else if ((ap_ST_st340_fsm_340 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st341_fsm_341;
end else if ((ap_ST_st339_fsm_339 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st340_fsm_340;
end else if ((ap_ST_st338_fsm_338 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st339_fsm_339;
end else if ((ap_ST_st337_fsm_337 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st338_fsm_338;
end else if ((ap_ST_st336_fsm_336 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st337_fsm_337;
end else if ((ap_ST_st335_fsm_335 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st336_fsm_336;
end else if ((ap_ST_st334_fsm_334 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st335_fsm_335;
end else if ((ap_ST_st333_fsm_333 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st334_fsm_334;
end else if ((ap_ST_st332_fsm_332 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st333_fsm_333;
end else if ((ap_ST_st331_fsm_331 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st332_fsm_332;
end else if ((ap_ST_st330_fsm_330 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st331_fsm_331;
end else if ((ap_ST_st329_fsm_329 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st330_fsm_330;
end else if ((ap_ST_st328_fsm_328 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st329_fsm_329;
end else if ((ap_ST_st327_fsm_327 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st328_fsm_328;
end else if ((ap_ST_st326_fsm_326 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st327_fsm_327;
end else if ((ap_ST_st325_fsm_325 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st326_fsm_326;
end else if ((ap_ST_st324_fsm_324 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st325_fsm_325;
end else if ((ap_ST_st323_fsm_323 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st324_fsm_324;
end else if ((ap_ST_st322_fsm_322 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st323_fsm_323;
end else if ((ap_ST_st321_fsm_321 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st322_fsm_322;
end else if ((ap_ST_st320_fsm_320 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st321_fsm_321;
end else if ((ap_ST_st319_fsm_319 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st320_fsm_320;
end else if ((ap_ST_st318_fsm_318 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st319_fsm_319;
end else if ((ap_ST_st317_fsm_317 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st318_fsm_318;
end else if ((ap_ST_st316_fsm_316 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st317_fsm_317;
end else if ((ap_ST_st315_fsm_315 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st316_fsm_316;
end else if ((ap_ST_st314_fsm_314 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st315_fsm_315;
end else if ((ap_ST_st313_fsm_313 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st314_fsm_314;
end else if ((ap_ST_st312_fsm_312 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st313_fsm_313;
end else if ((ap_ST_st311_fsm_311 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st312_fsm_312;
end else if ((ap_ST_st310_fsm_310 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st311_fsm_311;
end else if ((ap_ST_st309_fsm_309 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st310_fsm_310;
end else if ((ap_ST_st308_fsm_308 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st309_fsm_309;
end else if ((ap_ST_st307_fsm_307 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st308_fsm_308;
end else if ((ap_ST_st306_fsm_306 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st307_fsm_307;
end else if ((ap_ST_st305_fsm_305 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st306_fsm_306;
end else if ((ap_ST_st304_fsm_304 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st305_fsm_305;
end else if ((ap_ST_st303_fsm_303 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st304_fsm_304;
end else if ((ap_ST_st302_fsm_302 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st303_fsm_303;
end else if ((ap_ST_st301_fsm_301 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st302_fsm_302;
end else if ((ap_ST_st300_fsm_300 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st301_fsm_301;
end else if ((ap_ST_st299_fsm_299 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st300_fsm_300;
end else if ((ap_ST_st298_fsm_298 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st299_fsm_299;
end else if ((ap_ST_st297_fsm_297 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st298_fsm_298;
end else if ((ap_ST_st296_fsm_296 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st297_fsm_297;
end else if ((ap_ST_st295_fsm_295 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st296_fsm_296;
end else if ((ap_ST_st294_fsm_294 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st295_fsm_295;
end else if ((ap_ST_st293_fsm_293 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st294_fsm_294;
end else if ((ap_ST_st292_fsm_292 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st293_fsm_293;
end else if ((ap_ST_st291_fsm_291 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st292_fsm_292;
end else if ((ap_ST_st290_fsm_290 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st291_fsm_291;
end else if ((ap_ST_st289_fsm_289 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st290_fsm_290;
end else if ((ap_ST_st288_fsm_288 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st289_fsm_289;
end else if ((ap_ST_st287_fsm_287 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st288_fsm_288;
end else if ((ap_ST_st286_fsm_286 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st287_fsm_287;
end else if ((ap_ST_st285_fsm_285 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st286_fsm_286;
end else if ((ap_ST_st284_fsm_284 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st285_fsm_285;
end else if ((ap_ST_st283_fsm_283 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st284_fsm_284;
end else if ((ap_ST_st282_fsm_282 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st283_fsm_283;
end else if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st282_fsm_282;
end else if ((ap_ST_st280_fsm_280 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st281_fsm_281;
end else if ((ap_ST_st279_fsm_279 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st280_fsm_280;
end else if ((ap_ST_st278_fsm_278 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st279_fsm_279;
end else if ((ap_ST_st277_fsm_277 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st278_fsm_278;
end else if ((ap_ST_st276_fsm_276 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st277_fsm_277;
end else if ((ap_ST_st275_fsm_275 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st276_fsm_276;
end else if ((ap_ST_st274_fsm_274 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st275_fsm_275;
end else if ((ap_ST_st273_fsm_273 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st274_fsm_274;
end else if ((ap_ST_st272_fsm_272 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st273_fsm_273;
end else if ((ap_ST_st271_fsm_271 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st272_fsm_272;
end else if ((ap_ST_st269_fsm_269 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st270_fsm_270;
end else if ((ap_ST_st268_fsm_268 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st269_fsm_269;
end else if ((ap_ST_st267_fsm_267 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st268_fsm_268;
end else if ((ap_ST_st266_fsm_266 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st267_fsm_267;
end else if ((ap_ST_st265_fsm_265 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st266_fsm_266;
end else if ((ap_ST_st264_fsm_264 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st265_fsm_265;
end else if ((ap_ST_st263_fsm_263 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st264_fsm_264;
end else if ((ap_ST_st262_fsm_262 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st263_fsm_263;
end else if ((ap_ST_st261_fsm_261 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st262_fsm_262;
end else if ((ap_ST_st260_fsm_260 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st261_fsm_261;
end else if ((ap_ST_st258_fsm_258 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st259_fsm_259;
end else if ((ap_ST_st257_fsm_257 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st258_fsm_258;
end else if ((ap_ST_st256_fsm_256 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st257_fsm_257;
end else if ((ap_ST_st255_fsm_255 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st256_fsm_256;
end else if (((ap_ST_st259_fsm_259 == ap_CS_fsm) | (ap_ST_st270_fsm_270 == ap_CS_fsm) | ((ap_ST_st254_fsm_254 == ap_CS_fsm) & (tmp_i5_reg_1449 == ap_const_lv1_0)))) begin
ap_NS_fsm = ap_ST_st271_fsm_271;
end else if (((ap_ST_st254_fsm_254 == ap_CS_fsm) & ~(tmp_i5_reg_1449 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st255_fsm_255;
end else if ((ap_ST_st253_fsm_253 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st254_fsm_254;
end else if ((ap_ST_st252_fsm_252 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st253_fsm_253;
end else if ((ap_ST_st251_fsm_251 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st252_fsm_252;
end else if ((ap_ST_st250_fsm_250 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st251_fsm_251;
end else if ((ap_ST_st249_fsm_249 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st250_fsm_250;
end else if ((ap_ST_st248_fsm_248 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st249_fsm_249;
end else if ((ap_ST_st247_fsm_247 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st248_fsm_248;
end else if ((ap_ST_st246_fsm_246 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st247_fsm_247;
end else if ((ap_ST_st245_fsm_245 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st246_fsm_246;
end else if ((ap_ST_st244_fsm_244 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st245_fsm_245;
end else if ((ap_ST_st243_fsm_243 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st244_fsm_244;
end else if ((ap_ST_st242_fsm_242 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st243_fsm_243;
end else if ((ap_ST_st241_fsm_241 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st242_fsm_242;
end else if ((ap_ST_st240_fsm_240 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st241_fsm_241;
end else if ((ap_ST_st239_fsm_239 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st240_fsm_240;
end else if ((ap_ST_st238_fsm_238 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st239_fsm_239;
end else if ((ap_ST_st237_fsm_237 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st238_fsm_238;
end else if ((ap_ST_st236_fsm_236 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st237_fsm_237;
end else if ((ap_ST_st235_fsm_235 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st236_fsm_236;
end else if ((ap_ST_st234_fsm_234 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st235_fsm_235;
end else if ((ap_ST_st233_fsm_233 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st234_fsm_234;
end else if ((ap_ST_st232_fsm_232 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st233_fsm_233;
end else if ((ap_ST_st231_fsm_231 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st232_fsm_232;
end else if ((ap_ST_st230_fsm_230 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st231_fsm_231;
end else if ((ap_ST_st229_fsm_229 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st230_fsm_230;
end else if ((ap_ST_st228_fsm_228 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st229_fsm_229;
end else if ((ap_ST_st227_fsm_227 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st228_fsm_228;
end else if ((ap_ST_st226_fsm_226 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st227_fsm_227;
end else if ((ap_ST_st225_fsm_225 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st226_fsm_226;
end else if ((ap_ST_st224_fsm_224 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st225_fsm_225;
end else if ((ap_ST_st223_fsm_223 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st224_fsm_224;
end else if ((ap_ST_st222_fsm_222 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st223_fsm_223;
end else if ((ap_ST_st221_fsm_221 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st222_fsm_222;
end else if ((ap_ST_st220_fsm_220 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st221_fsm_221;
end else if ((ap_ST_st219_fsm_219 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st220_fsm_220;
end else if ((ap_ST_st218_fsm_218 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st219_fsm_219;
end else if ((ap_ST_st217_fsm_217 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st218_fsm_218;
end else if ((ap_ST_st216_fsm_216 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st217_fsm_217;
end else if ((ap_ST_st215_fsm_215 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st216_fsm_216;
end else if ((ap_ST_st214_fsm_214 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st215_fsm_215;
end else if ((ap_ST_st213_fsm_213 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st214_fsm_214;
end else if ((ap_ST_st212_fsm_212 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st213_fsm_213;
end else if ((ap_ST_st211_fsm_211 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st212_fsm_212;
end else if ((ap_ST_st210_fsm_210 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st211_fsm_211;
end else if ((ap_ST_st209_fsm_209 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st210_fsm_210;
end else if ((ap_ST_st208_fsm_208 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st209_fsm_209;
end else if ((ap_ST_st207_fsm_207 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st208_fsm_208;
end else if ((ap_ST_st206_fsm_206 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st207_fsm_207;
end else if ((ap_ST_st205_fsm_205 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st206_fsm_206;
end else if ((ap_ST_st204_fsm_204 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st205_fsm_205;
end else if ((ap_ST_st203_fsm_203 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st204_fsm_204;
end else if ((ap_ST_st202_fsm_202 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st203_fsm_203;
end else if ((ap_ST_st201_fsm_201 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st202_fsm_202;
end else if ((ap_ST_st200_fsm_200 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st201_fsm_201;
end else if ((ap_ST_st199_fsm_199 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st200_fsm_200;
end else if ((ap_ST_st198_fsm_198 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st199_fsm_199;
end else if ((ap_ST_st197_fsm_197 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st198_fsm_198;
end else if ((ap_ST_st196_fsm_196 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st197_fsm_197;
end else if ((ap_ST_st195_fsm_195 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st196_fsm_196;
end else if ((ap_ST_st194_fsm_194 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st195_fsm_195;
end else if ((ap_ST_st193_fsm_193 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st194_fsm_194;
end else if ((ap_ST_st192_fsm_192 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st193_fsm_193;
end else if ((ap_ST_st191_fsm_191 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st192_fsm_192;
end else if ((ap_ST_st190_fsm_190 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st191_fsm_191;
end else if ((ap_ST_st189_fsm_189 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st190_fsm_190;
end else if ((ap_ST_st188_fsm_188 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st189_fsm_189;
end else if ((ap_ST_st187_fsm_187 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st188_fsm_188;
end else if ((ap_ST_st186_fsm_186 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st187_fsm_187;
end else if ((ap_ST_st185_fsm_185 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st186_fsm_186;
end else if ((ap_ST_st184_fsm_184 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st185_fsm_185;
end else if ((ap_ST_st183_fsm_183 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st184_fsm_184;
end else if ((ap_ST_st182_fsm_182 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st183_fsm_183;
end else if ((ap_ST_st181_fsm_181 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st182_fsm_182;
end else if ((ap_ST_st180_fsm_180 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st181_fsm_181;
end else if ((ap_ST_st179_fsm_179 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st180_fsm_180;
end else if ((ap_ST_st178_fsm_178 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st179_fsm_179;
end else if ((ap_ST_st177_fsm_177 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st178_fsm_178;
end else if ((ap_ST_st176_fsm_176 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st177_fsm_177;
end else if ((ap_ST_st175_fsm_175 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st176_fsm_176;
end else if ((ap_ST_st174_fsm_174 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st175_fsm_175;
end else if ((ap_ST_st173_fsm_173 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st174_fsm_174;
end else if ((ap_ST_st172_fsm_172 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st173_fsm_173;
end else if ((ap_ST_st171_fsm_171 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st172_fsm_172;
end else if ((ap_ST_st170_fsm_170 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st171_fsm_171;
end else if ((ap_ST_st169_fsm_169 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st170_fsm_170;
end else if ((ap_ST_st168_fsm_168 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st169_fsm_169;
end else if ((ap_ST_st167_fsm_167 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st168_fsm_168;
end else if ((ap_ST_st166_fsm_166 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st167_fsm_167;
end else if ((ap_ST_st165_fsm_165 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st166_fsm_166;
end else if ((ap_ST_st164_fsm_164 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st165_fsm_165;
end else if ((ap_ST_st163_fsm_163 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st164_fsm_164;
end else if ((ap_ST_st162_fsm_162 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st163_fsm_163;
end else if ((ap_ST_st161_fsm_161 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st162_fsm_162;
end else if ((ap_ST_st160_fsm_160 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st161_fsm_161;
end else if ((ap_ST_st159_fsm_159 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st160_fsm_160;
end else if ((ap_ST_st158_fsm_158 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st159_fsm_159;
end else if ((ap_ST_st157_fsm_157 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st158_fsm_158;
end else if ((ap_ST_st156_fsm_156 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st157_fsm_157;
end else if ((ap_ST_st155_fsm_155 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st156_fsm_156;
end else if ((ap_ST_st154_fsm_154 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st155_fsm_155;
end else if ((ap_ST_st153_fsm_153 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st154_fsm_154;
end else if ((ap_ST_st152_fsm_152 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st153_fsm_153;
end else if ((ap_ST_st151_fsm_151 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st152_fsm_152;
end else if ((ap_ST_st150_fsm_150 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st151_fsm_151;
end else if ((ap_ST_st149_fsm_149 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st150_fsm_150;
end else if ((ap_ST_st148_fsm_148 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st149_fsm_149;
end else if ((ap_ST_st147_fsm_147 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st148_fsm_148;
end else if ((ap_ST_st146_fsm_146 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st147_fsm_147;
end else if ((ap_ST_st145_fsm_145 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st146_fsm_146;
end else if ((ap_ST_st144_fsm_144 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st145_fsm_145;
end else if ((ap_ST_st143_fsm_143 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st144_fsm_144;
end else if ((ap_ST_st142_fsm_142 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st143_fsm_143;
end else if ((ap_ST_st141_fsm_141 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st142_fsm_142;
end else if ((ap_ST_st140_fsm_140 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st141_fsm_141;
end else if ((ap_ST_st139_fsm_139 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st140_fsm_140;
end else if ((ap_ST_st138_fsm_138 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st139_fsm_139;
end else if ((ap_ST_st137_fsm_137 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st138_fsm_138;
end else if ((ap_ST_st136_fsm_136 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st137_fsm_137;
end else if ((ap_ST_st135_fsm_135 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st136_fsm_136;
end else if ((ap_ST_st134_fsm_134 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st135_fsm_135;
end else if ((ap_ST_st133_fsm_133 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st134_fsm_134;
end else if ((ap_ST_st132_fsm_132 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st133_fsm_133;
end else if ((ap_ST_st131_fsm_131 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st132_fsm_132;
end else if ((ap_ST_st130_fsm_130 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st131_fsm_131;
end else if ((ap_ST_st129_fsm_129 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st130_fsm_130;
end else if ((ap_ST_st128_fsm_128 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st129_fsm_129;
end else if ((ap_ST_st127_fsm_127 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st128_fsm_128;
end else if (((ap_ST_st126_fsm_126 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_609_p2))) begin
ap_NS_fsm = ap_ST_st260_fsm_260;
end else if (((ap_ST_st126_fsm_126 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_609_p2))) begin
ap_NS_fsm = ap_ST_st127_fsm_127;
end else if ((ap_ST_st125_fsm_125 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st126_fsm_126;
end else if ((ap_ST_st124_fsm_124 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st125_fsm_125;
end else if ((ap_ST_st123_fsm_123 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st124_fsm_124;
end else if ((ap_ST_st122_fsm_122 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st123_fsm_123;
end else if ((ap_ST_st121_fsm_121 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st122_fsm_122;
end else if ((ap_ST_st120_fsm_120 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st121_fsm_121;
end else if ((ap_ST_st119_fsm_119 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st120_fsm_120;
end else if ((ap_ST_st118_fsm_118 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st119_fsm_119;
end else if ((ap_ST_st117_fsm_117 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st118_fsm_118;
end else if ((ap_ST_st116_fsm_116 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st117_fsm_117;
end else if ((ap_ST_st115_fsm_115 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st116_fsm_116;
end else if ((ap_ST_st114_fsm_114 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st115_fsm_115;
end else if ((ap_ST_st113_fsm_113 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st114_fsm_114;
end else if ((ap_ST_st112_fsm_112 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st113_fsm_113;
end else if ((ap_ST_st111_fsm_111 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st112_fsm_112;
end else if ((ap_ST_st110_fsm_110 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st111_fsm_111;
end else if ((ap_ST_st109_fsm_109 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st110_fsm_110;
end else if ((ap_ST_st108_fsm_108 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st109_fsm_109;
end else if (((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2))) begin
ap_NS_fsm = ap_ST_st108_fsm_108;
end else if (((ap_ST_st106_fsm_106 == ap_CS_fsm) & (~(ap_const_lv1_0 == tmp_13_reg_1267) | ~(ap_const_lv1_0 == tmp_28_reg_1373) | ~(ap_const_lv1_0 == grp_fu_600_p2)))) begin
ap_NS_fsm = ap_ST_st107_fsm_107;
end else if ((ap_ST_st104_fsm_104 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st105_fsm_105;
end else if ((ap_ST_st103_fsm_103 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st104_fsm_104;
end else if ((ap_ST_st102_fsm_102 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st103_fsm_103;
end else if ((ap_ST_st101_fsm_101 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st102_fsm_102;
end else if ((ap_ST_st100_fsm_100 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st101_fsm_101;
end else if ((ap_ST_st99_fsm_99 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st100_fsm_100;
end else if ((ap_ST_st98_fsm_98 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st99_fsm_99;
end else if ((ap_ST_st97_fsm_97 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st98_fsm_98;
end else if ((ap_ST_st96_fsm_96 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st97_fsm_97;
end else if ((ap_ST_st95_fsm_95 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st96_fsm_96;
end else if ((ap_ST_st94_fsm_94 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st95_fsm_95;
end else if ((ap_ST_st93_fsm_93 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st94_fsm_94;
end else if (((ap_ST_st92_fsm_92 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_596_p2))) begin
ap_NS_fsm = ap_ST_st93_fsm_93;
end else if ((ap_ST_st91_fsm_91 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st92_fsm_92;
end else if ((ap_ST_st90_fsm_90 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st91_fsm_91;
end else if ((ap_ST_st89_fsm_89 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st90_fsm_90;
end else if ((ap_ST_st88_fsm_88 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st89_fsm_89;
end else if ((ap_ST_st87_fsm_87 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st88_fsm_88;
end else if ((ap_ST_st86_fsm_86 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st87_fsm_87;
end else if ((ap_ST_st85_fsm_85 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st86_fsm_86;
end else if ((ap_ST_st84_fsm_84 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st85_fsm_85;
end else if ((ap_ST_st83_fsm_83 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st84_fsm_84;
end else if ((ap_ST_st82_fsm_82 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st83_fsm_83;
end else if ((ap_ST_st81_fsm_81 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st82_fsm_82;
end else if ((ap_ST_st80_fsm_80 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st81_fsm_81;
end else if ((ap_ST_st79_fsm_79 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st80_fsm_80;
end else if (((ap_ST_st105_fsm_105 == ap_CS_fsm) | ((ap_ST_st78_fsm_78 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_13_reg_1267)) | ((ap_ST_st92_fsm_92 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_596_p2)))) begin
ap_NS_fsm = ap_ST_st106_fsm_106;
end else if (((ap_ST_st78_fsm_78 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267))) begin
ap_NS_fsm = ap_ST_st79_fsm_79;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st78_fsm_78;
end else if ((ap_ST_st76_fsm_76 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st77_fsm_77;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st76_fsm_76;
end else if ((ap_ST_st74_fsm_74 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st75_fsm_75;
end else if ((ap_ST_st73_fsm_73 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st74_fsm_74;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st73_fsm_73;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st72_fsm_72;
end else if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st71_fsm_71;
end else if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st70_fsm_70;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
ap_NS_fsm = ap_ST_st69_fsm_69;
end else if ((((ap_ST_st67_fsm_67 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond5_fu_987_p2)) | ((ap_ST_st391_fsm_391 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_do_rotate_fu_497_ap_done)) | ((ap_ST_st107_fsm_107 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_604_p2)) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
ap_NS_fsm = ap_ST_st68_fsm_68;
end else if (((ap_ST_st399_fsm_399 == ap_CS_fsm) | ((ap_ST_st67_fsm_67 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond5_fu_987_p2)))) begin
ap_NS_fsm = ap_ST_st392_fsm_392;
end else if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | ((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_1024_p2)))) begin
ap_NS_fsm = ap_ST_st67_fsm_67;
end else if ((ap_ST_st64_fsm_64 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st65_fsm_65;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st64_fsm_64;
end else if ((ap_ST_st62_fsm_62 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st63_fsm_63;
end else if ((ap_ST_st61_fsm_61 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st62_fsm_62;
end else if ((ap_ST_st60_fsm_60 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st61_fsm_61;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st60_fsm_60;
end else if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st59_fsm_59;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st58_fsm_58;
end else if ((ap_ST_st56_fsm_56 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st57_fsm_57;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st56_fsm_56;
end else if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st55_fsm_55;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st54_fsm_54;
end else if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st53_fsm_53;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st52_fsm_52;
end else if ((ap_ST_st50_fsm_50 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st51_fsm_51;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st50_fsm_50;
end else if ((ap_ST_st48_fsm_48 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st49_fsm_49;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st48_fsm_48;
end else if ((ap_ST_st46_fsm_46 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st47_fsm_47;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st46_fsm_46;
end else if ((ap_ST_st44_fsm_44 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st45_fsm_45;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st44_fsm_44;
end else if ((ap_ST_st42_fsm_42 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st43_fsm_43;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st42_fsm_42;
end else if ((ap_ST_st40_fsm_40 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st41_fsm_41;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st40_fsm_40;
end else if ((ap_ST_st38_fsm_38 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st39_fsm_39;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st38_fsm_38;
end else if ((ap_ST_st36_fsm_36 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st37_fsm_37;
end else if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st36_fsm_36;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st35_fsm_35;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st34_fsm_34;
end else if ((ap_ST_st32_fsm_32 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st33_fsm_33;
end else if ((ap_ST_st31_fsm_31 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st32_fsm_32;
end else if ((ap_ST_st30_fsm_30 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st31_fsm_31;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st30_fsm_30;
end else if ((ap_ST_st28_fsm_28 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st29_fsm_29;
end else if ((ap_ST_st27_fsm_27 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st28_fsm_28;
end else if ((ap_ST_st26_fsm_26 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st27_fsm_27;
end else if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st26_fsm_26;
end else if ((ap_ST_st24_fsm_24 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st25_fsm_25;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st24_fsm_24;
end else if ((ap_ST_st22_fsm_22 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st23_fsm_23;
end else if (((ap_ST_st21_fsm_21 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_start) & ((ap_const_lv1_0 == tmp_6_reg_1191) | ~(ap_const_lv1_0 == grp_fu_583_p2)))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if (((ap_ST_st65_fsm_65 == ap_CS_fsm) | ((ap_ST_st21_fsm_21 == ap_CS_fsm) & (ap_const_lv1_0 == icmp_fu_939_p2) & ~(ap_const_lv1_0 == tmp_6_reg_1191) & (ap_const_lv1_0 == grp_fu_583_p2)))) begin
ap_NS_fsm = ap_ST_st66_fsm_66;
end else if (((ap_ST_st21_fsm_21 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_reg_1191) & (ap_const_lv1_0 == grp_fu_583_p2) & ~(ap_const_lv1_0 == icmp_fu_939_p2))) begin
ap_NS_fsm = ap_ST_st22_fsm_22;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st20_fsm_20;
end else if ((ap_ST_st18_fsm_18 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st19_fsm_19;
end else if ((ap_ST_st17_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st18_fsm_18;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st17_fsm_17;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st16_fsm_16;
end else if ((ap_ST_st14_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st15_fsm_15;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st14_fsm_14;
end else if ((ap_ST_st12_fsm_12 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st13_fsm_13;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st12_fsm_12;
end else if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st11_fsm_11;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st10_fsm_10;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond4_fu_880_p2))) begin
ap_NS_fsm = ap_ST_st9_fsm_9;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | ((ap_ST_st7_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_868_p2)))) begin
ap_NS_fsm = ap_ST_st8_fsm_8;
end else if ((((ap_ST_st7_fsm_7 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_868_p2)) | ((ap_ST_st6_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_836_p2)))) begin
ap_NS_fsm = ap_ST_st21_fsm_21;
end else if ((((ap_ST_st8_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_880_p2)) | ((ap_ST_st6_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_fu_836_p2)))) begin
ap_NS_fsm = ap_ST_st7_fsm_7;
end else if ((((ap_ST_st392_fsm_392 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_1112_p2)) | ((ap_ST_st4_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_790_p2)))) begin
ap_NS_fsm = ap_ST_st6_fsm_6;
end else if (((ap_ST_st4_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_790_p2))) begin
ap_NS_fsm = ap_ST_st5_fsm_5;
end else if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | ((ap_ST_st2_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_746_p2)))) begin
ap_NS_fsm = ap_ST_st4_fsm_4;
end else if ((((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0)) | ((ap_ST_st2_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_746_p2)))) begin
ap_NS_fsm = ap_ST_st3_fsm_3;
end else if ((((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0)) | (ap_ST_st1_fsm_1 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st2_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_ST_st21_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_start) & ((ap_const_lv1_0 == tmp_6_reg_1191) | ~(ap_const_lv1_0 == grp_fu_583_p2))))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm or tmp_6_reg_1191 or grp_fu_583_p2)
begin
if (((ap_ST_st21_fsm_21 == ap_CS_fsm) & ((ap_const_lv1_0 == tmp_6_reg_1191) | ~(ap_const_lv1_0 == grp_fu_583_p2)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// b_address0 assign process. ///
always @ (ap_CS_fsm or tmp_22_fu_1124_p1 or exitcond6_fu_1112_p2 or b_addr_1_reg_1557 or tmp_2_fu_823_p1)
begin
if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
b_address0 = b_addr_1_reg_1557;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
b_address0 = tmp_2_fu_823_p1;
end else if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
b_address0 = tmp_22_fu_1124_p1;
end else begin
b_address0 = tmp_2_fu_823_p1;
end
end
/// b_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond6_fu_1112_p2)
begin
if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | ((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2)) | (ap_ST_st399_fsm_399 == ap_CS_fsm))) begin
b_ce0 = ap_const_logic_1;
end else begin
b_ce0 = ap_const_logic_0;
end
end
/// b_d0 assign process. ///
always @ (ap_CS_fsm or a_q0 or reg_649)
begin
if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
b_d0 = reg_649;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
b_d0 = a_q0;
end else begin
b_d0 = reg_649;
end
end
/// b_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st399_fsm_399 == ap_CS_fsm))) begin
b_we0 = ap_const_logic_1;
end else begin
b_we0 = ap_const_logic_0;
end
end
/// d_address0 assign process. ///
always @ (ap_CS_fsm or tmp_13_reg_1267 or d_addr_1_reg_1300 or tmp_26_reg_1355 or grp_fu_596_p2 or d_addr_4_gep_fu_211_p3 or d_addr_4_reg_1404 or grp_fu_604_p2 or tmp_22_reg_1552 or tmp_2_fu_823_p1)
begin
if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
d_address0 = tmp_22_reg_1552;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
d_address0 = tmp_2_fu_823_p1;
end else if ((ap_ST_st274_fsm_274 == ap_CS_fsm)) begin
d_address0 = d_addr_4_reg_1404;
end else if (((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2))) begin
d_address0 = d_addr_4_gep_fu_211_p3;
end else if (((ap_ST_st92_fsm_92 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_596_p2))) begin
d_address0 = tmp_26_reg_1355;
end else if (((ap_ST_st281_fsm_281 == ap_CS_fsm) | ((ap_ST_st78_fsm_78 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267)))) begin
d_address0 = d_addr_1_reg_1300;
end else begin
d_address0 = tmp_22_reg_1552;
end
end
/// d_address1 assign process. ///
always @ (ap_CS_fsm or d_addr_1_reg_1300 or d_addr_4_reg_1404 or grp_fu_604_p2)
begin
if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
d_address1 = d_addr_4_reg_1404;
end else if (((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2))) begin
d_address1 = d_addr_1_reg_1300;
end else begin
d_address1 = d_addr_4_reg_1404;
end
end
/// d_ce0 assign process. ///
always @ (ap_CS_fsm or tmp_13_reg_1267 or grp_fu_596_p2 or grp_fu_604_p2)
begin
if (((ap_ST_st274_fsm_274 == ap_CS_fsm) | (ap_ST_st5_fsm_5 == ap_CS_fsm) | ((ap_ST_st92_fsm_92 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_596_p2)) | ((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2)) | (ap_ST_st281_fsm_281 == ap_CS_fsm) | (ap_ST_st399_fsm_399 == ap_CS_fsm) | ((ap_ST_st78_fsm_78 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267)))) begin
d_ce0 = ap_const_logic_1;
end else begin
d_ce0 = ap_const_logic_0;
end
end
/// d_ce1 assign process. ///
always @ (ap_CS_fsm or grp_fu_604_p2)
begin
if ((((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2)) | (ap_ST_st281_fsm_281 == ap_CS_fsm))) begin
d_ce1 = ap_const_logic_1;
end else begin
d_ce1 = ap_const_logic_0;
end
end
/// d_d0 assign process. ///
always @ (ap_CS_fsm or a_q0 or reg_649 or tmp_62_reg_1508)
begin
if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
d_d0 = reg_649;
end else if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
d_d0 = tmp_62_reg_1508;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
d_d0 = a_q0;
end else begin
d_d0 = tmp_62_reg_1508;
end
end
/// d_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st281_fsm_281 == ap_CS_fsm) | (ap_ST_st399_fsm_399 == ap_CS_fsm))) begin
d_we0 = ap_const_logic_1;
end else begin
d_we0 = ap_const_logic_0;
end
end
/// d_we1 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
d_we1 = ap_const_logic_1;
end else begin
d_we1 = ap_const_logic_0;
end
end
/// grp_do_rotate_fu_497_ap_start assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st390_fsm_390 == ap_CS_fsm)) begin
grp_do_rotate_fu_497_ap_start = ap_const_logic_1;
end else begin
grp_do_rotate_fu_497_ap_start = ap_const_logic_0;
end
end
/// grp_fu_509_opcode assign process. ///
always @ (ap_CS_fsm or tmp_i5_reg_1449)
begin
if (((ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st109_fsm_109 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | ((tmp_i5_reg_1449 == ap_const_lv1_1) & (ap_ST_st206_fsm_206 == ap_CS_fsm)) | (ap_ST_st255_fsm_255 == ap_CS_fsm) | (ap_ST_st276_fsm_276 == ap_CS_fsm))) begin
grp_fu_509_opcode = ap_const_lv2_1;
end else if (((ap_ST_st275_fsm_275 == ap_CS_fsm) | (ap_ST_st394_fsm_394 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_fu_509_opcode = ap_const_lv2_0;
end else begin
grp_fu_509_opcode = ap_const_lv2_1;
end
end
/// grp_fu_509_p0 assign process. ///
always @ (ap_CS_fsm or tmp_i5_reg_1449 or reg_675 or reg_684 or reg_710 or UnifiedRetVal_i_reg_1241 or UnifiedRetVal_i2_reg_1367 or UnifiedRetVal_i3_reg_1387 or UnifiedRetVal_i4_reg_1421 or b_load_reg_1577)
begin
if ((ap_ST_st394_fsm_394 == ap_CS_fsm)) begin
grp_fu_509_p0 = b_load_reg_1577;
end else if ((ap_ST_st276_fsm_276 == ap_CS_fsm)) begin
grp_fu_509_p0 = reg_710;
end else if ((ap_ST_st275_fsm_275 == ap_CS_fsm)) begin
grp_fu_509_p0 = reg_675;
end else if ((ap_ST_st120_fsm_120 == ap_CS_fsm)) begin
grp_fu_509_p0 = UnifiedRetVal_i4_reg_1421;
end else if ((ap_ST_st109_fsm_109 == ap_CS_fsm)) begin
grp_fu_509_p0 = reg_684;
end else if ((ap_ST_st100_fsm_100 == ap_CS_fsm)) begin
grp_fu_509_p0 = UnifiedRetVal_i3_reg_1387;
end else if ((ap_ST_st86_fsm_86 == ap_CS_fsm)) begin
grp_fu_509_p0 = UnifiedRetVal_i2_reg_1367;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
grp_fu_509_p0 = UnifiedRetVal_i_reg_1241;
end else if (((ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | ((tmp_i5_reg_1449 == ap_const_lv1_1) & (ap_ST_st206_fsm_206 == ap_CS_fsm)) | (ap_ST_st255_fsm_255 == ap_CS_fsm))) begin
grp_fu_509_p0 = ap_const_lv32_80000000;
end else begin
grp_fu_509_p0 = ap_const_lv32_80000000;
end
end
/// grp_fu_509_p1 assign process. ///
always @ (ap_CS_fsm or reg_640 or reg_649 or tmp_i5_reg_1449 or reg_675 or reg_684 or reg_710 or d_load_3_reg_1410 or theta_reg_1440 or tmp_47_reg_1469 or tmp_59_reg_1490 or sm_reg_376)
begin
if ((ap_ST_st394_fsm_394 == ap_CS_fsm)) begin
grp_fu_509_p1 = reg_710;
end else if ((ap_ST_st276_fsm_276 == ap_CS_fsm)) begin
grp_fu_509_p1 = tmp_59_reg_1490;
end else if ((ap_ST_st275_fsm_275 == ap_CS_fsm)) begin
grp_fu_509_p1 = ap_const_lv32_3F800000;
end else if ((ap_ST_st255_fsm_255 == ap_CS_fsm)) begin
grp_fu_509_p1 = tmp_47_reg_1469;
end else if (((tmp_i5_reg_1449 == ap_const_lv1_1) & (ap_ST_st206_fsm_206 == ap_CS_fsm))) begin
grp_fu_509_p1 = theta_reg_1440;
end else if ((ap_ST_st114_fsm_114 == ap_CS_fsm)) begin
grp_fu_509_p1 = reg_649;
end else if ((ap_ST_st109_fsm_109 == ap_CS_fsm)) begin
grp_fu_509_p1 = d_load_3_reg_1410;
end else if (((ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_fu_509_p1 = reg_675;
end else if (((ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm))) begin
grp_fu_509_p1 = reg_684;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
grp_fu_509_p1 = sm_reg_376;
end else if (((ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm))) begin
grp_fu_509_p1 = reg_640;
end else begin
grp_fu_509_p1 = ap_const_lv32_3F800000;
end
end
/// grp_fu_528_p0 assign process. ///
always @ (ap_CS_fsm or reg_640 or UnifiedRetVal_i1_fu_1066_p3 or theta_reg_1440 or t_phi_fu_465_p6 or t_reg_462)
begin
if ((ap_ST_st348_fsm_348 == ap_CS_fsm)) begin
grp_fu_528_p0 = t_reg_462;
end else if ((ap_ST_st272_fsm_272 == ap_CS_fsm)) begin
grp_fu_528_p0 = reg_640;
end else if ((ap_ST_st271_fsm_271 == ap_CS_fsm)) begin
grp_fu_528_p0 = t_phi_fu_465_p6;
end else if ((ap_ST_st171_fsm_171 == ap_CS_fsm)) begin
grp_fu_528_p0 = theta_reg_1440;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
grp_fu_528_p0 = UnifiedRetVal_i1_fu_1066_p3;
end else begin
grp_fu_528_p0 = t_reg_462;
end
end
/// grp_fu_528_p1 assign process. ///
always @ (ap_CS_fsm or theta_reg_1440 or c_reg_1523 or t_phi_fu_465_p6 or t_reg_462)
begin
if ((ap_ST_st348_fsm_348 == ap_CS_fsm)) begin
grp_fu_528_p1 = c_reg_1523;
end else if ((ap_ST_st272_fsm_272 == ap_CS_fsm)) begin
grp_fu_528_p1 = t_reg_462;
end else if ((ap_ST_st271_fsm_271 == ap_CS_fsm)) begin
grp_fu_528_p1 = t_phi_fu_465_p6;
end else if ((ap_ST_st171_fsm_171 == ap_CS_fsm)) begin
grp_fu_528_p1 = theta_reg_1440;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
grp_fu_528_p1 = ap_const_lv32_42C80000;
end else begin
grp_fu_528_p1 = ap_const_lv32_42C80000;
end
end
/// grp_fu_537_ce assign process. ///
always @ (ap_CS_fsm or grp_fu_609_p2)
begin
if (((ap_ST_st270_fsm_270 == ap_CS_fsm) | ((ap_ST_st126_fsm_126 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_609_p2)) | (ap_ST_st260_fsm_260 == ap_CS_fsm) | (ap_ST_st261_fsm_261 == ap_CS_fsm) | (ap_ST_st262_fsm_262 == ap_CS_fsm) | (ap_ST_st263_fsm_263 == ap_CS_fsm) | (ap_ST_st264_fsm_264 == ap_CS_fsm) | (ap_ST_st265_fsm_265 == ap_CS_fsm) | (ap_ST_st266_fsm_266 == ap_CS_fsm) | (ap_ST_st267_fsm_267 == ap_CS_fsm) | (ap_ST_st268_fsm_268 == ap_CS_fsm) | (ap_ST_st269_fsm_269 == ap_CS_fsm))) begin
grp_fu_537_ce = ap_const_logic_1;
end else begin
grp_fu_537_ce = ap_const_logic_0;
end
end
/// grp_fu_557_ce assign process. ///
always @ (ap_CS_fsm or tmp_6_reg_1191 or icmp_fu_939_p2 or grp_fu_583_p2)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | ((ap_ST_st21_fsm_21 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_reg_1191) & (ap_const_lv1_0 == grp_fu_583_p2) & ~(ap_const_lv1_0 == icmp_fu_939_p2)))) begin
grp_fu_557_ce = ap_const_logic_1;
end else begin
grp_fu_557_ce = ap_const_logic_0;
end
end
/// grp_fu_561_ce assign process. ///
always @ (ap_CS_fsm or grp_fu_609_p2)
begin
if (((ap_ST_st127_fsm_127 == ap_CS_fsm) | ((ap_ST_st126_fsm_126 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_609_p2)))) begin
grp_fu_561_ce = ap_const_logic_1;
end else begin
grp_fu_561_ce = ap_const_logic_0;
end
end
/// grp_fu_583_ce assign process. ///
always @ (ap_CS_fsm or tmp_6_reg_1191 or exitcond3_fu_868_p2)
begin
if ((((ap_ST_st7_fsm_7 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_868_p2)) | ((ap_ST_st21_fsm_21 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_reg_1191)))) begin
grp_fu_583_ce = ap_const_logic_1;
end else begin
grp_fu_583_ce = ap_const_logic_0;
end
end
/// grp_fu_589_p0 assign process. ///
always @ (ap_CS_fsm or a_q0 or d_q0 or reg_649)
begin
if ((ap_ST_st114_fsm_114 == ap_CS_fsm)) begin
grp_fu_589_p0 = reg_649;
end else if (((ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm))) begin
grp_fu_589_p0 = d_q0;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm))) begin
grp_fu_589_p0 = a_q0;
end else begin
grp_fu_589_p0 = reg_649;
end
end
/// grp_fu_604_ce assign process. ///
always @ (ap_CS_fsm or tmp_13_reg_1267 or tmp_28_reg_1373 or grp_fu_600_p2)
begin
if (((ap_ST_st107_fsm_107 == ap_CS_fsm) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (~(ap_const_lv1_0 == tmp_13_reg_1267) | ~(ap_const_lv1_0 == tmp_28_reg_1373) | ~(ap_const_lv1_0 == grp_fu_600_p2))))) begin
grp_fu_604_ce = ap_const_logic_1;
end else begin
grp_fu_604_ce = ap_const_logic_0;
end
end
/// grp_fu_618_p0 assign process. ///
always @ (ap_CS_fsm or tmp_42_reg_1454 or tmp_40_reg_1464 or tmp_56_reg_1529)
begin
if ((ap_ST_st349_fsm_349 == ap_CS_fsm)) begin
grp_fu_618_p0 = tmp_56_reg_1529;
end else if ((ap_ST_st213_fsm_213 == ap_CS_fsm)) begin
grp_fu_618_p0 = tmp_40_reg_1464;
end else if ((ap_ST_st177_fsm_177 == ap_CS_fsm)) begin
grp_fu_618_p0 = tmp_42_reg_1454;
end else begin
grp_fu_618_p0 = tmp_56_reg_1529;
end
end
/// grp_fu_618_p1 assign process. ///
always @ (ap_CS_fsm or reg_704)
begin
if ((ap_ST_st213_fsm_213 == ap_CS_fsm)) begin
grp_fu_618_p1 = reg_704;
end else if (((ap_ST_st177_fsm_177 == ap_CS_fsm) | (ap_ST_st349_fsm_349 == ap_CS_fsm))) begin
grp_fu_618_p1 = ap_const_lv64_3FF0000000000000;
end else begin
grp_fu_618_p1 = ap_const_lv64_3FF0000000000000;
end
end
/// grp_fu_623_p0 assign process. ///
always @ (ap_CS_fsm or tmp_s_reg_1257 or tmp_36_reg_1430)
begin
if ((ap_ST_st128_fsm_128 == ap_CS_fsm)) begin
grp_fu_623_p0 = tmp_36_reg_1430;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
grp_fu_623_p0 = tmp_s_reg_1257;
end else begin
grp_fu_623_p0 = tmp_36_reg_1430;
end
end
/// grp_fu_623_p1 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st128_fsm_128 == ap_CS_fsm)) begin
grp_fu_623_p1 = ap_const_lv64_3FE0000000000000;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
grp_fu_623_p1 = ap_const_lv64_3FC999999999999A;
end else begin
grp_fu_623_p1 = ap_const_lv64_3FE0000000000000;
end
end
/// grp_fu_629_p0 assign process. ///
always @ (ap_CS_fsm or reg_661 or tmp_55_reg_1534)
begin
if ((ap_ST_st355_fsm_355 == ap_CS_fsm)) begin
grp_fu_629_p0 = tmp_55_reg_1534;
end else if (((ap_ST_st219_fsm_219 == ap_CS_fsm) | (ap_ST_st312_fsm_312 == ap_CS_fsm))) begin
grp_fu_629_p0 = ap_const_lv64_3FF0000000000000;
end else if (((ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st135_fsm_135 == ap_CS_fsm))) begin
grp_fu_629_p0 = reg_661;
end else begin
grp_fu_629_p0 = ap_const_lv64_3FF0000000000000;
end
end
/// grp_fu_629_p1 assign process. ///
always @ (ap_CS_fsm or reg_698 or reg_704 or tmp_38_reg_1435)
begin
if ((ap_ST_st312_fsm_312 == ap_CS_fsm)) begin
grp_fu_629_p1 = reg_704;
end else if (((ap_ST_st219_fsm_219 == ap_CS_fsm) | (ap_ST_st355_fsm_355 == ap_CS_fsm))) begin
grp_fu_629_p1 = reg_698;
end else if ((ap_ST_st135_fsm_135 == ap_CS_fsm)) begin
grp_fu_629_p1 = tmp_38_reg_1435;
end else if ((ap_ST_st30_fsm_30 == ap_CS_fsm)) begin
grp_fu_629_p1 = ap_const_lv64_40D0000000000000;
end else begin
grp_fu_629_p1 = ap_const_lv64_40D0000000000000;
end
end
/// grp_fu_635_p1 assign process. ///
always @ (ap_CS_fsm or reg_698 or tmp_52_reg_1518)
begin
if ((ap_ST_st282_fsm_282 == ap_CS_fsm)) begin
grp_fu_635_p1 = tmp_52_reg_1518;
end else if ((ap_ST_st183_fsm_183 == ap_CS_fsm)) begin
grp_fu_635_p1 = reg_698;
end else begin
grp_fu_635_p1 = tmp_52_reg_1518;
end
end
/// nrot_o assign process. ///
always @ (ap_CS_fsm or exitcond1_fu_790_p2 or tmp_64_fu_1105_p2)
begin
if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
nrot_o = tmp_64_fu_1105_p2;
end else if (((ap_ST_st4_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_790_p2))) begin
nrot_o = ap_const_lv32_0;
end else begin
nrot_o = tmp_64_fu_1105_p2;
end
end
/// nrot_o_ap_vld assign process. ///
always @ (ap_CS_fsm or exitcond1_fu_790_p2 or grp_do_rotate_fu_497_ap_done)
begin
if ((((ap_ST_st4_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_790_p2)) | ((ap_ST_st391_fsm_391 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_do_rotate_fu_497_ap_done)))) begin
nrot_o_ap_vld = ap_const_logic_1;
end else begin
nrot_o_ap_vld = ap_const_logic_0;
end
end
/// v_address0 assign process. ///
always @ (ap_CS_fsm or tmp_9_cast_reg_1142 or exitcond2_fu_772_p2 or grp_do_rotate_fu_497_v_address0 or tmp_cast_fu_767_p1)
begin
if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
v_address0 = tmp_9_cast_reg_1142;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
v_address0 = tmp_cast_fu_767_p1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_address0 = grp_do_rotate_fu_497_v_address0;
end else begin
v_address0 = tmp_9_cast_reg_1142;
end
end
/// v_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_772_p2 or grp_do_rotate_fu_497_v_ce0)
begin
if ((((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0)) | ((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0)))) begin
v_ce0 = ap_const_logic_1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_ce0 = grp_do_rotate_fu_497_v_ce0;
end else begin
v_ce0 = ap_const_logic_0;
end
end
/// v_ce1 assign process. ///
always @ (ap_CS_fsm or grp_do_rotate_fu_497_v_ce1)
begin
if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_ce1 = grp_do_rotate_fu_497_v_ce1;
end else begin
v_ce1 = ap_const_logic_0;
end
end
/// v_d0 assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_772_p2 or grp_do_rotate_fu_497_v_d0)
begin
if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
v_d0 = ap_const_lv32_3F800000;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
v_d0 = ap_const_lv32_0;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_d0 = grp_do_rotate_fu_497_v_d0;
end else begin
v_d0 = ap_const_lv32_3F800000;
end
end
/// v_we0 assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_772_p2 or grp_do_rotate_fu_497_v_we0)
begin
if ((((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0)) | ((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0)))) begin
v_we0 = ap_const_logic_1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_we0 = grp_do_rotate_fu_497_v_we0;
end else begin
v_we0 = ap_const_logic_0;
end
end
/// v_we1 assign process. ///
always @ (ap_CS_fsm or grp_do_rotate_fu_497_v_we1)
begin
if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_we1 = grp_do_rotate_fu_497_v_we1;
end else begin
v_we1 = ap_const_logic_0;
end
end
/// z_address0 assign process. ///
always @ (ap_CS_fsm or z_addr_1_reg_1306 or tmp_22_fu_1124_p1 or exitcond6_fu_1112_p2 or z_addr_2_reg_1562 or tmp_2_fu_823_p1)
begin
if ((ap_ST_st394_fsm_394 == ap_CS_fsm)) begin
z_address0 = z_addr_2_reg_1562;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
z_address0 = tmp_2_fu_823_p1;
end else if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
z_address0 = tmp_22_fu_1124_p1;
end else if (((ap_ST_st274_fsm_274 == ap_CS_fsm) | (ap_ST_st281_fsm_281 == ap_CS_fsm))) begin
z_address0 = z_addr_1_reg_1306;
end else begin
z_address0 = tmp_2_fu_823_p1;
end
end
/// z_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond6_fu_1112_p2)
begin
if (((ap_ST_st274_fsm_274 == ap_CS_fsm) | (ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st281_fsm_281 == ap_CS_fsm) | ((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2)) | (ap_ST_st394_fsm_394 == ap_CS_fsm))) begin
z_ce0 = ap_const_logic_1;
end else begin
z_ce0 = ap_const_logic_0;
end
end
/// z_ce1 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st274_fsm_274 == ap_CS_fsm) | (ap_ST_st281_fsm_281 == ap_CS_fsm))) begin
z_ce1 = ap_const_logic_1;
end else begin
z_ce1 = ap_const_logic_0;
end
end
/// z_d0 assign process. ///
always @ (ap_CS_fsm or reg_692)
begin
if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
z_d0 = reg_692;
end else if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st394_fsm_394 == ap_CS_fsm))) begin
z_d0 = ap_const_lv32_0;
end else begin
z_d0 = ap_const_lv32_0;
end
end
/// z_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st281_fsm_281 == ap_CS_fsm) | (ap_ST_st394_fsm_394 == ap_CS_fsm))) begin
z_we0 = ap_const_logic_1;
end else begin
z_we0 = ap_const_logic_0;
end
end
/// z_we1 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
z_we1 = ap_const_logic_1;
end else begin
z_we1 = ap_const_logic_0;
end
end
assign UnifiedRetVal_i1_fu_1066_p3 = ((tmp_i1_reg_1344)? reg_649: reg_640);
assign a_addr1_fu_1049_p2 = (a_addr_cast_fu_1045_p1 + tmp_21_fu_1018_p2);
assign a_addr2_cast_fu_901_p1 = {{17{1'b0}}, {a_addr2_fu_895_p2}};
assign a_addr2_fu_895_p2 = tmp_9_trn_cast_fu_891_p1 << ap_const_lv15_7;
assign a_addr3_fu_905_p2 = (a_addr2_cast_fu_901_p1 + iq_1_fu_874_p2);
assign a_addr6_fu_812_p2 = (p_shl_fu_806_p2 + tmp_2_trn_cast_fu_802_p1);
assign a_addr_2_reg_13340 = {{32{a_addr1_fu_1049_p2[31]}}, {a_addr1_fu_1049_p2}};
assign a_addr_cast_fu_1045_p1 = {{17{1'b0}}, {a_addr_fu_1039_p2}};
assign a_addr_fu_1039_p2 = tmp_20_trn_cast_fu_1035_p1 << ap_const_lv15_7;
assign a_address1 = grp_do_rotate_fu_497_a_address1;
assign a_d1 = grp_do_rotate_fu_497_a_d1;
assign b_addr_1_reg_15570 = {{56{1'b0}}, {ip_4_reg_485}};
assign d_addr_1_reg_13000 = {{56{1'b0}}, {tmp_17_reg_422}};
assign d_addr_4_gep_fu_211_p3 = tmp_26_reg_1355;
assign d_d1 = tmp_63_reg_1513;
assign exitcond1_fu_790_p2 = (indvar4_reg_286 == ap_const_lv8_80? 1'b1: 1'b0);
assign exitcond2_fu_772_p2 = (indvar5_reg_275 == ap_const_lv8_80? 1'b1: 1'b0);
assign exitcond3_fu_868_p2 = (indvar7_reg_321 == ap_const_lv7_7F? 1'b1: 1'b0);
assign exitcond4_fu_880_p2 = (indvar8_reg_356 == tmp4_reg_1195? 1'b1: 1'b0);
assign exitcond5_fu_987_p2 = (indvar9_reg_400 == ap_const_lv7_7F? 1'b1: 1'b0);
assign exitcond6_fu_1112_p2 = (indvar_reg_474 == ap_const_lv8_80? 1'b1: 1'b0);
assign exitcond7_fu_1024_p2 = (indvar1_reg_434 == tmp5_reg_1271? 1'b1: 1'b0);
assign exitcond_fu_746_p2 = (indvar2_reg_253 == ap_const_lv8_80? 1'b1: 1'b0);
assign grp_do_rotate_fu_497_a_q0 = a_q0;
assign grp_do_rotate_fu_497_a_q1 = a_q1;
assign grp_do_rotate_fu_497_ip = tmp_18_reg_1276;
assign grp_do_rotate_fu_497_iq = iq_2_reg_1311;
assign grp_do_rotate_fu_497_s = reg_675;
assign grp_do_rotate_fu_497_tau = tau_reg_1539;
assign grp_do_rotate_fu_497_v_q0 = v_q0;
assign grp_do_rotate_fu_497_v_q1 = v_q1;
assign grp_fu_509_ce = ap_const_logic_1;
assign grp_fu_516_ce = ap_const_logic_1;
assign grp_fu_516_p0 = z_load_2_reg_1498;
assign grp_fu_516_p1 = tmp_59_reg_1490;
assign grp_fu_520_ce = ap_const_logic_1;
assign grp_fu_520_p0 = d_load_3_reg_1410;
assign grp_fu_520_p1 = tmp_59_reg_1490;
assign grp_fu_524_ce = ap_const_logic_1;
assign grp_fu_524_p0 = reg_684;
assign grp_fu_524_p1 = tmp_59_reg_1490;
assign grp_fu_528_ce = ap_const_logic_1;
assign grp_fu_537_p0 = reg_640;
assign grp_fu_537_p1 = reg_649;
assign grp_fu_541_ce = ap_const_logic_1;
assign grp_fu_541_p0 = reg_666;
assign grp_fu_544_ce = ap_const_logic_1;
assign grp_fu_544_p0 = reg_666;
assign grp_fu_547_ce = ap_const_logic_1;
assign grp_fu_547_p0 = reg_666;
assign grp_fu_550_ce = ap_const_logic_1;
assign grp_fu_550_p0 = reg_666;
assign grp_fu_553_ce = ap_const_logic_1;
assign grp_fu_553_p0 = reg_666;
assign grp_fu_557_p0 = sm_1_reg_344;
assign grp_fu_561_p0 = reg_649;
assign grp_fu_564_ce = ap_const_logic_1;
assign grp_fu_564_p0 = reg_640;
assign grp_fu_567_ce = ap_const_logic_1;
assign grp_fu_567_p0 = reg_675;
assign grp_fu_570_ce = ap_const_logic_1;
assign grp_fu_570_p0 = ((tmp_i5_reg_1449)? reg_649: theta_reg_1440);
assign grp_fu_573_ce = ap_const_logic_1;
assign grp_fu_573_p0 = reg_649;
assign grp_fu_576_ce = ap_const_logic_1;
assign grp_fu_576_p0 = grp_fu_550_p1;
assign grp_fu_580_ce = ap_const_logic_1;
assign grp_fu_580_p0 = reg_675;
assign grp_fu_583_opcode = ap_const_lv5_1;
assign grp_fu_583_p0 = sm_1_reg_344;
assign grp_fu_583_p1 = ap_const_lv32_0;
assign grp_fu_589_ce = ap_const_logic_1;
assign grp_fu_589_opcode = ap_const_lv5_4;
assign grp_fu_589_p1 = ap_const_lv32_0;
assign grp_fu_596_ce = ap_const_logic_1;
assign grp_fu_596_opcode = ap_const_lv5_E;
assign grp_fu_596_p0 = reg_649;
assign grp_fu_596_p1 = UnifiedRetVal_i2_reg_1367;
assign grp_fu_600_ce = ap_const_logic_1;
assign grp_fu_600_opcode = ap_const_lv5_E;
assign grp_fu_600_p0 = tmp_29_reg_1393;
assign grp_fu_600_p1 = UnifiedRetVal_i3_reg_1387;
assign grp_fu_604_opcode = ap_const_lv5_2;
assign grp_fu_604_p0 = UnifiedRetVal_i1_reg_1349;
assign grp_fu_604_p1 = tresh_reg_388;
assign grp_fu_609_ce = ap_const_logic_1;
assign grp_fu_609_opcode = ap_const_lv5_1;
assign grp_fu_609_p0 = reg_692;
assign grp_fu_609_p1 = UnifiedRetVal_i4_reg_1421;
assign grp_fu_613_ce = ap_const_logic_1;
assign grp_fu_613_opcode = ap_const_lv5_4;
assign grp_fu_613_p0 = theta_reg_1440;
assign grp_fu_613_p1 = ap_const_lv32_0;
assign grp_fu_618_ce = ap_const_logic_1;
assign grp_fu_623_ce = ap_const_logic_1;
assign grp_fu_629_ce = ap_const_logic_1;
assign grp_fu_635_ce = ap_const_logic_1;
assign grp_fu_635_p0 = ap_const_lv64_1;
assign icmp_fu_939_p2 = ($signed(tmp_5_fu_929_p4) < $signed(30'b000000000000000000000000000001)? 1'b1: 1'b0);
assign indvar1_cast_fu_999_p1 = {{1{1'b0}}, {indvar1_reg_434}};
assign indvar30_cast_fu_716_p1 = {{7{1'b0}}, {indvar2_reg_253}};
assign indvar34_cast_fu_758_p1 = indvar6_reg_264[15:0];
assign indvar3_cast1_fu_963_p1 = {{1{1'b0}}, {indvar3_reg_411}};
assign indvar3_cast_fu_967_p1 = {{2{1'b0}}, {indvar3_reg_411}};
assign indvar7_cast_fu_848_p1 = {{1{1'b0}}, {indvar7_reg_321}};
assign ip_2_fu_852_p2 = (indvar7_cast_fu_848_p1 + ap_const_lv8_1);
assign ip_3_fu_971_p2 = (indvar3_cast1_fu_963_p1 + ap_const_lv8_1);
assign iq_1_fu_874_p2 = (iq_1_in_reg_367 + ap_const_lv32_1);
assign p_shl_fu_806_p2 = tmp_2_trn_cast_fu_802_p1 << ap_const_lv16_7;
assign t_phi_fu_465_p6 = t_reg_462;
assign tmp1_fu_720_p2 = indvar30_cast_fu_716_p1 << ap_const_lv15_7;
assign tmp2_fu_736_p2 = (tmp1_fu_720_p2 + ap_const_lv15_81);
assign tmp36_cast_fu_742_p1 = {{1{1'b0}}, {tmp2_fu_736_p2}};
assign tmp3_cast_fu_1009_p1 = {{1{1'b0}}, {tmp3_fu_1003_p2}};
assign tmp3_fu_1003_p2 = (indvar1_cast_fu_999_p1 + ap_const_lv8_2);
assign tmp_15_fu_911_p1 = {{32{a_addr3_fu_905_p2[31]}}, {a_addr3_fu_905_p2}};
assign tmp_1_fu_818_p1 = {{48{1'b0}}, {a_addr6_fu_812_p2}};
assign tmp_20_trn_cast_fu_1035_p1 = {{7{1'b0}}, {tmp_17_reg_422}};
assign tmp_21_fu_1018_p2 = (iq_2_in_reg_449 + ap_const_lv32_1);
assign tmp_22_fu_1124_p1 = {{56{1'b0}}, {ip_4_reg_485}};
assign tmp_2_fu_823_p1 = {{56{1'b0}}, {ip_1_reg_297}};
assign tmp_2_trn_cast_fu_802_p1 = {{8{1'b0}}, {ip_1_reg_297}};
assign tmp_48_fu_1055_p1 = {{32{a_addr1_fu_1049_p2[31]}}, {a_addr1_fu_1049_p2}};
assign tmp_5_fu_929_p4 = {{indvar10_reg_309[ap_const_lv32_1F : ap_const_lv32_2]}};
assign tmp_64_fu_1105_p2 = (nrot_i + ap_const_lv32_1);
assign tmp_6_fu_836_p2 = ($signed(indvar10_reg_309) < $signed(32'b00000000000000000000000000110011)? 1'b1: 1'b0);
assign tmp_9_cast_fu_732_p1 = {{49{1'b0}}, {tmp_9_fu_726_p2}};
assign tmp_9_fu_726_p2 = (tmp1_fu_720_p2 + ap_const_lv15_101);
assign tmp_9_trn_cast_fu_891_p1 = {{7{1'b0}}, {tmp_7_reg_332}};
assign tmp_cast_fu_767_p1 = {{48{1'b0}}, {tmp_fu_762_p2}};
assign tmp_fu_762_p2 = (tmp36_cast_reg_1147 + indvar34_cast_fu_758_p1);
assign v_address1 = grp_do_rotate_fu_497_v_address1;
assign v_d1 = grp_do_rotate_fu_497_v_d1;
assign z_addr_1_reg_13060 = {{56{1'b0}}, {tmp_17_reg_422}};
assign z_addr_2_reg_15620 = {{56{1'b0}}, {ip_4_reg_485}};
assign z_address1 = z_addr_3_reg_1485;
assign z_d1 = tmp_61_reg_1503;
always @ (ap_clk)
begin
tmp_9_cast_reg_1142[0] <= 1'b1;
tmp_9_cast_reg_1142[1] <= 1'b0;
tmp_9_cast_reg_1142[2] <= 1'b0;
tmp_9_cast_reg_1142[3] <= 1'b0;
tmp_9_cast_reg_1142[4] <= 1'b0;
tmp_9_cast_reg_1142[5] <= 1'b0;
tmp_9_cast_reg_1142[6] <= 1'b0;
tmp_9_cast_reg_1142[15] <= 1'b0;
tmp_9_cast_reg_1142[16] <= 1'b0;
tmp_9_cast_reg_1142[17] <= 1'b0;
tmp_9_cast_reg_1142[18] <= 1'b0;
tmp_9_cast_reg_1142[19] <= 1'b0;
tmp_9_cast_reg_1142[20] <= 1'b0;
tmp_9_cast_reg_1142[21] <= 1'b0;
tmp_9_cast_reg_1142[22] <= 1'b0;
tmp_9_cast_reg_1142[23] <= 1'b0;
tmp_9_cast_reg_1142[24] <= 1'b0;
tmp_9_cast_reg_1142[25] <= 1'b0;
tmp_9_cast_reg_1142[26] <= 1'b0;
tmp_9_cast_reg_1142[27] <= 1'b0;
tmp_9_cast_reg_1142[28] <= 1'b0;
tmp_9_cast_reg_1142[29] <= 1'b0;
tmp_9_cast_reg_1142[30] <= 1'b0;
tmp_9_cast_reg_1142[31] <= 1'b0;
tmp_9_cast_reg_1142[32] <= 1'b0;
tmp_9_cast_reg_1142[33] <= 1'b0;
tmp_9_cast_reg_1142[34] <= 1'b0;
tmp_9_cast_reg_1142[35] <= 1'b0;
tmp_9_cast_reg_1142[36] <= 1'b0;
tmp_9_cast_reg_1142[37] <= 1'b0;
tmp_9_cast_reg_1142[38] <= 1'b0;
tmp_9_cast_reg_1142[39] <= 1'b0;
tmp_9_cast_reg_1142[40] <= 1'b0;
tmp_9_cast_reg_1142[41] <= 1'b0;
tmp_9_cast_reg_1142[42] <= 1'b0;
tmp_9_cast_reg_1142[43] <= 1'b0;
tmp_9_cast_reg_1142[44] <= 1'b0;
tmp_9_cast_reg_1142[45] <= 1'b0;
tmp_9_cast_reg_1142[46] <= 1'b0;
tmp_9_cast_reg_1142[47] <= 1'b0;
tmp_9_cast_reg_1142[48] <= 1'b0;
tmp_9_cast_reg_1142[49] <= 1'b0;
tmp_9_cast_reg_1142[50] <= 1'b0;
tmp_9_cast_reg_1142[51] <= 1'b0;
tmp_9_cast_reg_1142[52] <= 1'b0;
tmp_9_cast_reg_1142[53] <= 1'b0;
tmp_9_cast_reg_1142[54] <= 1'b0;
tmp_9_cast_reg_1142[55] <= 1'b0;
tmp_9_cast_reg_1142[56] <= 1'b0;
tmp_9_cast_reg_1142[57] <= 1'b0;
tmp_9_cast_reg_1142[58] <= 1'b0;
tmp_9_cast_reg_1142[59] <= 1'b0;
tmp_9_cast_reg_1142[60] <= 1'b0;
tmp_9_cast_reg_1142[61] <= 1'b0;
tmp_9_cast_reg_1142[62] <= 1'b0;
tmp_9_cast_reg_1142[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp36_cast_reg_1147[0] <= 1'b1;
tmp36_cast_reg_1147[1] <= 1'b0;
tmp36_cast_reg_1147[2] <= 1'b0;
tmp36_cast_reg_1147[3] <= 1'b0;
tmp36_cast_reg_1147[4] <= 1'b0;
tmp36_cast_reg_1147[5] <= 1'b0;
tmp36_cast_reg_1147[6] <= 1'b0;
tmp36_cast_reg_1147[15] <= 1'b0;
end
always @ (ap_clk)
begin
indvar3_cast_reg_1282[7] <= 1'b0;
indvar3_cast_reg_1282[8] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_22_reg_1552[8] <= 1'b0;
tmp_22_reg_1552[9] <= 1'b0;
tmp_22_reg_1552[10] <= 1'b0;
tmp_22_reg_1552[11] <= 1'b0;
tmp_22_reg_1552[12] <= 1'b0;
tmp_22_reg_1552[13] <= 1'b0;
tmp_22_reg_1552[14] <= 1'b0;
tmp_22_reg_1552[15] <= 1'b0;
tmp_22_reg_1552[16] <= 1'b0;
tmp_22_reg_1552[17] <= 1'b0;
tmp_22_reg_1552[18] <= 1'b0;
tmp_22_reg_1552[19] <= 1'b0;
tmp_22_reg_1552[20] <= 1'b0;
tmp_22_reg_1552[21] <= 1'b0;
tmp_22_reg_1552[22] <= 1'b0;
tmp_22_reg_1552[23] <= 1'b0;
tmp_22_reg_1552[24] <= 1'b0;
tmp_22_reg_1552[25] <= 1'b0;
tmp_22_reg_1552[26] <= 1'b0;
tmp_22_reg_1552[27] <= 1'b0;
tmp_22_reg_1552[28] <= 1'b0;
tmp_22_reg_1552[29] <= 1'b0;
tmp_22_reg_1552[30] <= 1'b0;
tmp_22_reg_1552[31] <= 1'b0;
tmp_22_reg_1552[32] <= 1'b0;
tmp_22_reg_1552[33] <= 1'b0;
tmp_22_reg_1552[34] <= 1'b0;
tmp_22_reg_1552[35] <= 1'b0;
tmp_22_reg_1552[36] <= 1'b0;
tmp_22_reg_1552[37] <= 1'b0;
tmp_22_reg_1552[38] <= 1'b0;
tmp_22_reg_1552[39] <= 1'b0;
tmp_22_reg_1552[40] <= 1'b0;
tmp_22_reg_1552[41] <= 1'b0;
tmp_22_reg_1552[42] <= 1'b0;
tmp_22_reg_1552[43] <= 1'b0;
tmp_22_reg_1552[44] <= 1'b0;
tmp_22_reg_1552[45] <= 1'b0;
tmp_22_reg_1552[46] <= 1'b0;
tmp_22_reg_1552[47] <= 1'b0;
tmp_22_reg_1552[48] <= 1'b0;
tmp_22_reg_1552[49] <= 1'b0;
tmp_22_reg_1552[50] <= 1'b0;
tmp_22_reg_1552[51] <= 1'b0;
tmp_22_reg_1552[52] <= 1'b0;
tmp_22_reg_1552[53] <= 1'b0;
tmp_22_reg_1552[54] <= 1'b0;
tmp_22_reg_1552[55] <= 1'b0;
tmp_22_reg_1552[56] <= 1'b0;
tmp_22_reg_1552[57] <= 1'b0;
tmp_22_reg_1552[58] <= 1'b0;
tmp_22_reg_1552[59] <= 1'b0;
tmp_22_reg_1552[60] <= 1'b0;
tmp_22_reg_1552[61] <= 1'b0;
tmp_22_reg_1552[62] <= 1'b0;
tmp_22_reg_1552[63] <= 1'b0;
end
endmodule //jacob
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_b_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd7;
parameter WORD_COUNT=32'd128;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module jacob_b (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
jacob_b_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_509_ACMP_faddfsub_11(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_516_ACMP_fadd_12(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_520_ACMP_fsub_13(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_524_ACMP_fadd_14(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_528_ACMP_fmul_15(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_537_ACMP_fdiv_16(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fdiv #(
.ID( ID ),
.NUM_STAGE( 12 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fdiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_541_ACMP_fptrunc_17(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fptrunc #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fptrunc_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_544_ACMP_fptrunc_18(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fptrunc #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fptrunc_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_547_ACMP_fptrunc_19(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fptrunc #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fptrunc_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_550_ACMP_fptrunc_20(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fptrunc #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fptrunc_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_553_ACMP_fptrunc_21(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fptrunc #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fptrunc_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_557_ACMP_fpext_22(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_561_ACMP_fpext_23(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_564_ACMP_fpext_24(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_567_ACMP_fpext_25(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_570_ACMP_fpext_26(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_573_ACMP_fpext_27(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_576_ACMP_fpext_28(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_580_ACMP_fpext_29(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_583_ACMP_fcmp_30(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_589_ACMP_fcmp_31(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_596_ACMP_fcmp_32(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_600_ACMP_fcmp_33(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_604_ACMP_fcmp_34(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_609_ACMP_fcmp_35(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_613_ACMP_fcmp_36(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_618_ACMP_dadd_37(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_dadd #(
.ID( ID ),
.NUM_STAGE( 6 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_dadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_623_ACMP_dmul_38(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_dmul #(
.ID( ID ),
.NUM_STAGE( 7 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_dmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_629_ACMP_ddiv_39(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_ddiv #(
.ID( ID ),
.NUM_STAGE( 34 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_ddiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_635_ACMP_dsqrt_40(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_dsqrt #(
.ID( ID ),
.NUM_STAGE( 30 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_dsqrt_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_z_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd7;
parameter WORD_COUNT=32'd128;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module jacob_z (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
jacob_z_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
/*-----------------------------------------------------------------------
-- AESL_FPSim_pkg.v:
-- Floating point simulation model for verilog.
--
-----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-- FAdd, FSub, FAddSub, FMul, FDiv, FSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision units.
-- DAdd, DSub, DAddSub, DMul, DDiv, DSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision Add.
-------------------------------------------------------------------------------
*/
module ACMP_fadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Sub.
-------------------------------------------------------------------------------
*/
module ACMP_fsub_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision AddSub.
-------------------------------------------------------------------------------
*/
module ACMP_faddfsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_faddfsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision ADD
-------------------------------------------------------------------------------
*/
module ACMP_dadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Sub
-------------------------------------------------------------------------------
*/
module ACMP_dsub_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision AddSub
-------------------------------------------------------------------------------
*/
module ACMP_dadddsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadddsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_fcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_dcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_fptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_dptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_sitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_sitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_fptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_dptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_uitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_uitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- single to double precision
-------------------------------------------------------------------------------
*/
module ACMP_fpext_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fpext(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- double to single precision
-------------------------------------------------------------------------------
*/
module ACMP_fptrunc_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptrunc(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module do_rotate (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
a_address0,
a_ce0,
a_we0,
a_d0,
a_q0,
a_address1,
a_ce1,
a_we1,
a_d1,
a_q1,
v_address0,
v_ce0,
v_we0,
v_d0,
v_q0,
v_address1,
v_ce1,
v_we1,
v_d1,
v_q1,
s,
tau,
ip,
iq
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output [13:0] a_address0;
output a_ce0;
output a_we0;
output [31:0] a_d0;
input [31:0] a_q0;
output [13:0] a_address1;
output a_ce1;
output a_we1;
output [31:0] a_d1;
input [31:0] a_q1;
output [13:0] v_address0;
output v_ce0;
output v_we0;
output [31:0] v_d0;
input [31:0] v_q0;
output [13:0] v_address1;
output v_ce1;
output v_we1;
output [31:0] v_d1;
input [31:0] v_q1;
input [31:0] s;
input [31:0] tau;
input [6:0] ip;
input [8:0] iq;
reg ap_done;
reg ap_idle;
reg[13:0] a_address0;
reg a_ce0;
reg a_we0;
reg[13:0] a_address1;
reg a_ce1;
reg a_we1;
reg[31:0] a_d1;
reg[13:0] v_address0;
reg v_ce0;
reg v_we0;
reg[13:0] v_address1;
reg v_ce1;
reg v_we1;
reg [3:0] ap_CS_fsm;
reg [31:0] indvar2_reg_168;
reg [31:0] indvar4_reg_179;
reg [31:0] indvar1_reg_190;
reg [7:0] indvar_reg_201;
reg [7:0] j_3_reg_212;
reg [31:0] reg_240;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg ap_reg_ppiten_pp0_it4;
reg ap_reg_ppiten_pp0_it5;
reg ap_reg_ppiten_pp0_it6;
reg ap_reg_ppiten_pp0_it7;
reg ap_reg_ppiten_pp0_it8;
reg ap_reg_ppiten_pp0_it9;
reg ap_reg_ppiten_pp0_it10;
reg ap_reg_ppiten_pp0_it11;
reg [0:0] tmp_4_reg_683;
reg ap_reg_ppiten_pp1_it0;
reg ap_reg_ppiten_pp1_it1;
reg ap_reg_ppiten_pp1_it2;
reg ap_reg_ppiten_pp1_it3;
reg ap_reg_ppiten_pp1_it4;
reg ap_reg_ppiten_pp1_it5;
reg ap_reg_ppiten_pp1_it6;
reg ap_reg_ppiten_pp1_it7;
reg ap_reg_ppiten_pp1_it8;
reg ap_reg_ppiten_pp1_it9;
reg ap_reg_ppiten_pp1_it10;
reg ap_reg_ppiten_pp1_it11;
reg [0:0] tmp_13_reg_707;
reg ap_reg_ppiten_pp2_it0;
reg ap_reg_ppiten_pp2_it1;
reg ap_reg_ppiten_pp2_it2;
reg ap_reg_ppiten_pp2_it3;
reg ap_reg_ppiten_pp2_it4;
reg ap_reg_ppiten_pp2_it5;
reg ap_reg_ppiten_pp2_it6;
reg ap_reg_ppiten_pp2_it7;
reg ap_reg_ppiten_pp2_it8;
reg ap_reg_ppiten_pp2_it9;
reg ap_reg_ppiten_pp2_it10;
reg ap_reg_ppiten_pp2_it11;
reg [0:0] exitcond_reg_736;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it1;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it2;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it3;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it4;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it5;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it6;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it1;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it2;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it3;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it4;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it5;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it6;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it1;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it2;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it3;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it4;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it5;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it6;
reg [31:0] reg_247;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it1;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it2;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it3;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it4;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it5;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it6;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it1;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it2;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it3;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it4;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it5;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it6;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it1;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it2;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it3;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it4;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it5;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it6;
wire [31:0] grp_fu_232_p2;
reg [31:0] reg_254;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it2;
reg ap_reg_ppiten_pp3_it2;
reg ap_reg_ppiten_pp3_it0;
reg ap_reg_ppiten_pp3_it1;
reg ap_reg_ppiten_pp3_it3;
reg ap_reg_ppiten_pp3_it4;
reg ap_reg_ppiten_pp3_it5;
reg ap_reg_ppiten_pp3_it6;
reg ap_reg_ppiten_pp3_it7;
reg ap_reg_ppiten_pp3_it8;
reg ap_reg_ppiten_pp3_it9;
reg ap_reg_ppiten_pp3_it10;
reg ap_reg_ppiten_pp3_it11;
reg [0:0] exitcond1_reg_755;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it2;
wire [31:0] grp_fu_236_p2;
reg [31:0] reg_259;
wire [31:0] grp_fu_224_p2;
reg [31:0] reg_264;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it4;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it4;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it4;
wire [31:0] grp_fu_228_p2;
reg [31:0] reg_269;
reg [31:0] reg_274;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it6;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it6;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it6;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it6;
reg [31:0] reg_279;
reg [31:0] reg_284;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it9;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it9;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it9;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it9;
reg [31:0] reg_290;
reg [31:0] ap_reg_ppstg_reg_290_pp0_it10;
reg [31:0] ap_reg_ppstg_reg_290_pp1_it10;
reg [31:0] ap_reg_ppstg_reg_290_pp2_it10;
reg [31:0] ap_reg_ppstg_reg_290_pp3_it10;
wire [7:0] ip_cast2_fu_296_p1;
reg [7:0] ip_cast2_reg_636;
reg [31:0] tmp_1_cast_reg_641;
wire [31:0] tmp1_fu_314_p1;
reg [31:0] tmp1_reg_646;
wire [15:0] tmp33_cast_fu_322_p1;
reg [15:0] tmp33_cast_reg_651;
wire [31:0] tmp34_cast_fu_332_p1;
reg [31:0] tmp34_cast_reg_657;
wire [15:0] tmp36_cast1_fu_336_p1;
reg [15:0] tmp36_cast1_reg_662;
wire [13:0] tmp36_cast_fu_344_p1;
reg [13:0] tmp36_cast_reg_667;
wire [31:0] tmp37_cast_fu_354_p1;
reg [31:0] tmp37_cast_reg_673;
wire [31:0] j_fu_374_p2;
reg [31:0] j_reg_678;
wire [0:0] tmp_4_fu_380_p2;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it7;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it8;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it10;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it11;
reg [13:0] a_addr_2_reg_687;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it1;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it2;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it3;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it4;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it5;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it6;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it7;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it8;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it9;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it10;
reg [13:0] a_addr_1_reg_692;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it1;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it2;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it3;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it4;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it5;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it6;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it7;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it8;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it9;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it10;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it11;
reg [31:0] tmp_5_cast_reg_697;
wire [31:0] tmp6_cast_fu_413_p1;
reg [31:0] tmp6_cast_reg_702;
wire [0:0] tmp_13_fu_422_p2;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it1;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it3;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it5;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it7;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it8;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it10;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it11;
reg [31:0] indvar_next5_reg_711;
reg [13:0] a_addr_2_6_reg_716;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it1;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it2;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it3;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it4;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it5;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it6;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it7;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it8;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it9;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it10;
reg [13:0] a_addr_3_reg_721;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it1;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it2;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it3;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it4;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it5;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it6;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it7;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it8;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it9;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it10;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it11;
wire [31:0] tmp_cast_fu_478_p1;
reg [31:0] tmp_cast_reg_726;
reg [31:0] tmp10_reg_731;
wire [0:0] exitcond_fu_509_p2;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it1;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it3;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it5;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it7;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it8;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it10;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it11;
reg [31:0] indvar_next2_reg_740;
reg [13:0] a_addr_4_reg_745;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it1;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it2;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it3;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it4;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it5;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it6;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it7;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it8;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it9;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it10;
reg [13:0] a_addr_5_reg_750;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it1;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it2;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it3;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it4;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it5;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it6;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it7;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it8;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it9;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it10;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it11;
wire [0:0] exitcond1_fu_565_p2;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it1;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it3;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it5;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it7;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it8;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it10;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it11;
reg [7:0] indvar_next_reg_759;
reg [13:0] v_addr_12_reg_764;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it1;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it2;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it3;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it4;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it5;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it6;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it7;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it8;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it9;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it10;
reg [13:0] v_addr_1_reg_769;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it1;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it2;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it3;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it4;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it5;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it6;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it7;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it8;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it9;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it10;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it11;
reg [7:0] tmp_41_reg_774;
reg [31:0] v_load_reg_779;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it1;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it2;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it3;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it4;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it5;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it6;
reg [31:0] v_load_1_reg_786;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it1;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it2;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it3;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it4;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it5;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it6;
reg [31:0] indvar2_phi_fu_172_p4;
reg [31:0] indvar4_phi_fu_183_p4;
reg [31:0] indvar1_phi_fu_194_p4;
reg [7:0] indvar_phi_fu_205_p4;
reg [7:0] j_3_phi_fu_216_p4;
wire [63:0] tmp_3_fu_385_p1;
wire [63:0] tmp_14_fu_390_p1;
wire [63:0] tmp_32_fu_448_p1;
wire [63:0] tmp_42_fu_464_p1;
wire [63:0] tmp_44_fu_540_p1;
wire [63:0] tmp_46_fu_560_p1;
wire [63:0] tmp_47_fu_596_p1;
wire [63:0] tmp_48_fu_606_p1;
reg [31:0] grp_fu_224_p0;
reg [31:0] grp_fu_224_p1;
reg [31:0] grp_fu_228_p0;
reg [31:0] grp_fu_228_p1;
reg [31:0] grp_fu_232_p0;
reg [31:0] grp_fu_232_p1;
reg [31:0] grp_fu_236_p0;
reg [31:0] grp_fu_236_p1;
wire [8:0] ip_cast1_cast_fu_300_p1;
wire [8:0] tmp_1_fu_304_p2;
wire [9:0] tmp33_cast1_fu_318_p1;
wire [9:0] tmp2_fu_326_p2;
wire [8:0] tmp36_cast2_fu_340_p1;
wire [8:0] tmp5_fu_348_p2;
wire [31:0] tmp7_fu_358_p2;
wire [31:0] a_addr5_fu_369_p2;
wire [31:0] a_addr8_fu_364_p2;
wire [9:0] iq_cast_cast_fu_395_p1;
wire [9:0] tmp_5_fu_398_p2;
wire [7:0] tmp6_fu_408_p2;
wire [31:0] j_1_fu_417_p2;
wire [13:0] a_addr9_fu_433_p2;
wire [31:0] a_addr9_cast_fu_438_p1;
wire [31:0] a_addr2_fu_442_p2;
wire [31:0] a_addr6_fu_453_p2;
wire [31:0] a_addr7_fu_459_p2;
wire [9:0] iq_cast1_fu_469_p1;
wire [9:0] tmp_fu_472_p2;
wire [0:0] tmp3_fu_482_p2;
wire [8:0] tmp4_fu_488_p3;
wire [9:0] tmp8_fu_495_p1;
wire [9:0] tmp9_fu_499_p2;
wire [13:0] a_addr3_fu_525_p2;
wire [31:0] a_addr3_cast_fu_530_p1;
wire [31:0] j_2_fu_520_p2;
wire [31:0] a_addr4_fu_534_p2;
wire [15:0] a_addr_fu_545_p2;
wire [31:0] a_addr_cast_fu_550_p1;
wire [31:0] a_addr1_fu_554_p2;
wire [14:0] tmp_32_trn_cast_fu_577_p1;
wire [14:0] v_addr_fu_581_p2;
wire [15:0] v_addr_cast_fu_587_p1;
wire [15:0] v_addr1_fu_591_p2;
wire [15:0] v_addr2_fu_601_p2;
reg [1:0] grp_fu_224_opcode;
wire grp_fu_224_ce;
reg [1:0] grp_fu_228_opcode;
wire grp_fu_228_ce;
wire grp_fu_232_ce;
wire grp_fu_236_ce;
reg [3:0] ap_NS_fsm;
wire [63:0] a_addr_1_reg_6920;
wire [63:0] a_addr_2_6_reg_7160;
wire [63:0] a_addr_2_reg_6870;
wire [63:0] a_addr_3_reg_7210;
wire [63:0] a_addr_4_reg_7450;
wire [63:0] a_addr_5_reg_7500;
wire [63:0] v_addr_12_reg_7640;
wire [63:0] v_addr_1_reg_7690;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 4'b0000;
parameter ap_ST_st1_fsm_1 = 4'b0001;
parameter ap_ST_pp0_stg0_fsm_2 = 4'b0010;
parameter ap_ST_pp0_stg1_fsm_3 = 4'b0011;
parameter ap_ST_st26_fsm_4 = 4'b0100;
parameter ap_ST_pp1_stg0_fsm_5 = 4'b0101;
parameter ap_ST_pp1_stg1_fsm_6 = 4'b0110;
parameter ap_ST_st51_fsm_7 = 4'b0111;
parameter ap_ST_pp2_stg0_fsm_8 = 4'b1000;
parameter ap_ST_pp2_stg1_fsm_9 = 4'b1001;
parameter ap_ST_pp3_stg0_fsm_10 = 4'b1010;
parameter ap_ST_pp3_stg1_fsm_11 = 4'b1011;
parameter ap_ST_st100_fsm_12 = 4'b1100;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv9_1FF = 9'b111111111;
parameter ap_const_lv10_80 = 10'b0010000000;
parameter ap_const_lv9_80 = 9'b010000000;
parameter ap_const_lv32_7 = 32'b00000000000000000000000000000111;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv10_3FF = 10'b1111111111;
parameter ap_const_lv14_7 = 14'b00000000000111;
parameter ap_const_lv10_1 = 10'b0000000001;
parameter ap_const_lv10_81 = 10'b0010000001;
parameter ap_const_lv16_7 = 16'b0000000000000111;
parameter ap_const_lv8_80 = 8'b10000000;
parameter ap_const_lv15_7 = 15'b000000000000111;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_true = 1'b1;
do_rotate_grp_fu_224_ACMP_faddfsub_1 #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
do_rotate_grp_fu_224_ACMP_faddfsub_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_224_p0 ),
.din1( grp_fu_224_p1 ),
.opcode( grp_fu_224_opcode ),
.ce( grp_fu_224_ce ),
.dout( grp_fu_224_p2 )
);
do_rotate_grp_fu_228_ACMP_faddfsub_2 #(
.ID( 2 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
do_rotate_grp_fu_228_ACMP_faddfsub_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_228_p0 ),
.din1( grp_fu_228_p1 ),
.opcode( grp_fu_228_opcode ),
.ce( grp_fu_228_ce ),
.dout( grp_fu_228_p2 )
);
do_rotate_grp_fu_232_ACMP_fmul_3 #(
.ID( 3 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
do_rotate_grp_fu_232_ACMP_fmul_3_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_232_p0 ),
.din1( grp_fu_232_p1 ),
.ce( grp_fu_232_ce ),
.dout( grp_fu_232_p2 )
);
do_rotate_grp_fu_236_ACMP_fmul_4 #(
.ID( 4 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
do_rotate_grp_fu_236_ACMP_fmul_4_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_236_p0 ),
.din1( grp_fu_236_p1 ),
.ce( grp_fu_236_ce ),
.dout( grp_fu_236_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_4_fu_380_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (tmp_4_reg_683 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~(tmp_4_reg_683 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_13_fu_422_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_707))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if (((ap_ST_st26_fsm_4 == ap_CS_fsm) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_13_reg_707)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it10 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it10 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it10 <= ap_reg_ppiten_pp1_it9;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it10 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it11 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it11 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it11 <= ap_reg_ppiten_pp1_it10;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it11 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it2 <= ap_reg_ppiten_pp1_it1;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it3 <= ap_reg_ppiten_pp1_it2;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it4 <= ap_reg_ppiten_pp1_it3;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it5 <= ap_reg_ppiten_pp1_it4;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it6 <= ap_reg_ppiten_pp1_it5;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it7 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it7 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it7 <= ap_reg_ppiten_pp1_it6;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it7 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it8 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it8 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it8 <= ap_reg_ppiten_pp1_it7;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it8 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it9 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it9 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it9 <= ap_reg_ppiten_pp1_it8;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it9 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_0;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp2_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_736))) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_1;
end else if (((ap_ST_st51_fsm_7 == ap_CS_fsm) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_reg_736)))) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it10 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it10 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it10 <= ap_reg_ppiten_pp2_it9;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it10 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it11 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it11 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it11 <= ap_reg_ppiten_pp2_it10;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it11 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it2 <= ap_reg_ppiten_pp2_it1;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it3 <= ap_reg_ppiten_pp2_it2;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it4 <= ap_reg_ppiten_pp2_it3;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it5 <= ap_reg_ppiten_pp2_it4;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it6 <= ap_reg_ppiten_pp2_it5;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it7 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it7 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it7 <= ap_reg_ppiten_pp2_it6;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it7 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it8 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it8 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it8 <= ap_reg_ppiten_pp2_it7;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it8 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it9 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it9 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it9 <= ap_reg_ppiten_pp2_it8;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it9 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp3_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_reg_755)))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it10 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it10 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it10 <= ap_reg_ppiten_pp3_it9;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it10 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it11 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it11 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it11 <= ap_reg_ppiten_pp3_it10;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it11 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it2 <= ap_reg_ppiten_pp3_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it3 <= ap_reg_ppiten_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it4 <= ap_reg_ppiten_pp3_it3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it5 <= ap_reg_ppiten_pp3_it4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it6 <= ap_reg_ppiten_pp3_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it7 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it7 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it7 <= ap_reg_ppiten_pp3_it6;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it7 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it8 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it8 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it8 <= ap_reg_ppiten_pp3_it7;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it8 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it9 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it9 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it9 <= ap_reg_ppiten_pp3_it8;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it9 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2))) begin
a_addr_1_reg_692 <= a_addr_1_reg_6920;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2))) begin
a_addr_2_6_reg_716 <= a_addr_2_6_reg_7160;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2))) begin
a_addr_2_reg_687 <= a_addr_2_reg_6870;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2))) begin
a_addr_3_reg_721 <= a_addr_3_reg_7210;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2))) begin
a_addr_4_reg_745 <= a_addr_4_reg_7450;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2))) begin
a_addr_5_reg_750 <= a_addr_5_reg_7500;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it1 <= a_addr_1_reg_692;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it10 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it11 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it10;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it2 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it3 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it4 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it5 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it6 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it7 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it8 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it9 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it8;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it1 <= a_addr_2_6_reg_716;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it10 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it9;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it2 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it1;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it3 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it2;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it4 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it3;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it5 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it4;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it6 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it5;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it7 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it6;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it8 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it7;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it9 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it8;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it1 <= a_addr_2_reg_687;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it10 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it2 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it3 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it4 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it5 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it6 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it7 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it8 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it9 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it8;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it1 <= a_addr_3_reg_721;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it10 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it9;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it11 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it10;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it2 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it1;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it3 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it2;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it4 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it3;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it5 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it4;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it6 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it5;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it7 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it6;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it8 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it7;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it9 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it8;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it1 <= a_addr_4_reg_745;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it10 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it9;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it2 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it1;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it3 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it2;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it4 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it3;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it5 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it4;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it6 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it5;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it7 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it6;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it8 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it7;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it9 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it8;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it1 <= a_addr_5_reg_750;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it10 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it9;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it11 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it10;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it2 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it1;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it3 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it2;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it4 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it3;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it5 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it4;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it6 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it5;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it7 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it6;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it8 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it7;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it9 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it8;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it1 <= exitcond1_reg_755;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it10 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it9;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it11 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it10;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it2 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it1;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it3 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it2;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it4 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it3;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it5 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it4;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it6 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it5;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it7 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it6;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it8 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it7;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it9 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it8;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it1 <= exitcond_reg_736;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it10 <= ap_reg_ppstg_exitcond_reg_736_pp2_it9;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it11 <= ap_reg_ppstg_exitcond_reg_736_pp2_it10;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it2 <= ap_reg_ppstg_exitcond_reg_736_pp2_it1;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it3 <= ap_reg_ppstg_exitcond_reg_736_pp2_it2;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it4 <= ap_reg_ppstg_exitcond_reg_736_pp2_it3;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it5 <= ap_reg_ppstg_exitcond_reg_736_pp2_it4;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it6 <= ap_reg_ppstg_exitcond_reg_736_pp2_it5;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it7 <= ap_reg_ppstg_exitcond_reg_736_pp2_it6;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it8 <= ap_reg_ppstg_exitcond_reg_736_pp2_it7;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it9 <= ap_reg_ppstg_exitcond_reg_736_pp2_it8;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it1 <= reg_240;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it2 <= ap_reg_ppstg_reg_240_pp0_it1;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it3 <= ap_reg_ppstg_reg_240_pp0_it2;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it4 <= ap_reg_ppstg_reg_240_pp0_it3;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it5 <= ap_reg_ppstg_reg_240_pp0_it4;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it6 <= ap_reg_ppstg_reg_240_pp0_it5;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it1 <= reg_240;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it2 <= ap_reg_ppstg_reg_240_pp1_it1;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it3 <= ap_reg_ppstg_reg_240_pp1_it2;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it4 <= ap_reg_ppstg_reg_240_pp1_it3;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it5 <= ap_reg_ppstg_reg_240_pp1_it4;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it6 <= ap_reg_ppstg_reg_240_pp1_it5;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it1 <= reg_240;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it2 <= ap_reg_ppstg_reg_240_pp2_it1;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it3 <= ap_reg_ppstg_reg_240_pp2_it2;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it4 <= ap_reg_ppstg_reg_240_pp2_it3;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it5 <= ap_reg_ppstg_reg_240_pp2_it4;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it6 <= ap_reg_ppstg_reg_240_pp2_it5;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it1 <= reg_247;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it2 <= ap_reg_ppstg_reg_247_pp0_it1;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it3 <= ap_reg_ppstg_reg_247_pp0_it2;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it4 <= ap_reg_ppstg_reg_247_pp0_it3;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it5 <= ap_reg_ppstg_reg_247_pp0_it4;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it6 <= ap_reg_ppstg_reg_247_pp0_it5;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it1 <= reg_247;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it2 <= ap_reg_ppstg_reg_247_pp1_it1;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it3 <= ap_reg_ppstg_reg_247_pp1_it2;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it4 <= ap_reg_ppstg_reg_247_pp1_it3;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it5 <= ap_reg_ppstg_reg_247_pp1_it4;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it6 <= ap_reg_ppstg_reg_247_pp1_it5;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it1 <= reg_247;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it2 <= ap_reg_ppstg_reg_247_pp2_it1;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it3 <= ap_reg_ppstg_reg_247_pp2_it2;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it4 <= ap_reg_ppstg_reg_247_pp2_it3;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it5 <= ap_reg_ppstg_reg_247_pp2_it4;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it6 <= ap_reg_ppstg_reg_247_pp2_it5;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_290_pp0_it10 <= reg_290;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_290_pp1_it10 <= reg_290;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_290_pp2_it10 <= reg_290;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_290_pp3_it10 <= reg_290;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it1 <= tmp_13_reg_707;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it10 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it9;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it11 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it10;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it2 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it1;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it3 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it2;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it4 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it3;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it5 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it4;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it6 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it5;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it7 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it6;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it8 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it7;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it9 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it8;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it1 <= tmp_4_reg_683;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it10 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it11 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it10;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it2 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it3 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it4 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it5 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it6 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it7 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it8 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it9 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it8;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it1 <= v_addr_12_reg_764;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it10 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it9;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it2 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it1;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it3 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it2;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it4 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it3;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it5 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it4;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it6 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it5;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it7 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it6;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it8 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it7;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it9 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it8;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it1 <= v_addr_1_reg_769;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it10 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it9;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it11 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it10;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it2 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it1;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it3 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it2;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it4 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it3;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it5 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it4;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it6 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it5;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it7 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it6;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it8 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it7;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it9 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it8;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it1 <= v_load_1_reg_786;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it2 <= ap_reg_ppstg_v_load_1_reg_786_pp3_it1;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it3 <= ap_reg_ppstg_v_load_1_reg_786_pp3_it2;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it4 <= ap_reg_ppstg_v_load_1_reg_786_pp3_it3;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it5 <= ap_reg_ppstg_v_load_1_reg_786_pp3_it4;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it6 <= ap_reg_ppstg_v_load_1_reg_786_pp3_it5;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it1 <= v_load_reg_779;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it2 <= ap_reg_ppstg_v_load_reg_779_pp3_it1;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it3 <= ap_reg_ppstg_v_load_reg_779_pp3_it2;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it4 <= ap_reg_ppstg_v_load_reg_779_pp3_it3;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it5 <= ap_reg_ppstg_v_load_reg_779_pp3_it4;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it6 <= ap_reg_ppstg_v_load_reg_779_pp3_it5;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm))) begin
exitcond1_reg_755 <= (indvar_phi_fu_205_p4 == ap_const_lv8_80? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
exitcond_reg_736 <= (indvar1_phi_fu_194_p4 == tmp10_reg_731? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
indvar1_reg_190 <= indvar_next2_reg_740;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
indvar1_reg_190 <= ap_const_lv32_0;
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar2_reg_168 <= ap_const_lv32_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar2_reg_168 <= j_reg_678;
end
if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
indvar4_reg_179 <= ap_const_lv32_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
indvar4_reg_179 <= indvar_next5_reg_711;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
indvar_next2_reg_740 <= (indvar1_phi_fu_194_p4 + ap_const_lv32_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
indvar_next5_reg_711 <= (indvar4_phi_fu_183_p4 + ap_const_lv32_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm))) begin
indvar_next_reg_759 <= (indvar_phi_fu_205_p4 + ap_const_lv8_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
indvar_reg_201 <= ap_const_lv8_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
indvar_reg_201 <= indvar_next_reg_759;
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ip_cast2_reg_636[0] <= ip_cast2_fu_296_p1[0];
ip_cast2_reg_636[1] <= ip_cast2_fu_296_p1[1];
ip_cast2_reg_636[2] <= ip_cast2_fu_296_p1[2];
ip_cast2_reg_636[3] <= ip_cast2_fu_296_p1[3];
ip_cast2_reg_636[4] <= ip_cast2_fu_296_p1[4];
ip_cast2_reg_636[5] <= ip_cast2_fu_296_p1[5];
ip_cast2_reg_636[6] <= ip_cast2_fu_296_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
j_3_reg_212 <= ap_const_lv8_1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
j_3_reg_212 <= tmp_41_reg_774;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
j_reg_678 <= (indvar2_phi_fu_172_p4 + ap_const_lv32_1);
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (tmp_4_reg_683 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == tmp_13_reg_707)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_lv1_0 == exitcond_reg_736)))) begin
reg_240 <= a_q0;
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (tmp_4_reg_683 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == tmp_13_reg_707)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_lv1_0 == exitcond_reg_736)))) begin
reg_247 <= a_q1;
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2)))) begin
reg_254 <= grp_fu_232_p2;
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2)))) begin
reg_259 <= grp_fu_236_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it4)))) begin
reg_264 <= grp_fu_224_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it4)))) begin
reg_269 <= grp_fu_228_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it6)))) begin
reg_274 <= grp_fu_232_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it6)))) begin
reg_279 <= grp_fu_236_p2;
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it9)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it9) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it9)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it9) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it9)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it9) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it9)))) begin
reg_284 <= grp_fu_224_p2;
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it9)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it9) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it9)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it9) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it9)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it9) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it9)))) begin
reg_290 <= grp_fu_228_p2;
end
if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
tmp10_reg_731 <= {{22{tmp9_fu_499_p2[9]}}, {tmp9_fu_499_p2}};
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp1_reg_646[0] <= tmp1_fu_314_p1[0];
tmp1_reg_646[1] <= tmp1_fu_314_p1[1];
tmp1_reg_646[2] <= tmp1_fu_314_p1[2];
tmp1_reg_646[3] <= tmp1_fu_314_p1[3];
tmp1_reg_646[4] <= tmp1_fu_314_p1[4];
tmp1_reg_646[5] <= tmp1_fu_314_p1[5];
tmp1_reg_646[6] <= tmp1_fu_314_p1[6];
tmp1_reg_646[7] <= tmp1_fu_314_p1[7];
tmp1_reg_646[8] <= tmp1_fu_314_p1[8];
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp33_cast_reg_651[0] <= tmp33_cast_fu_322_p1[0];
tmp33_cast_reg_651[1] <= tmp33_cast_fu_322_p1[1];
tmp33_cast_reg_651[2] <= tmp33_cast_fu_322_p1[2];
tmp33_cast_reg_651[3] <= tmp33_cast_fu_322_p1[3];
tmp33_cast_reg_651[4] <= tmp33_cast_fu_322_p1[4];
tmp33_cast_reg_651[5] <= tmp33_cast_fu_322_p1[5];
tmp33_cast_reg_651[6] <= tmp33_cast_fu_322_p1[6];
tmp33_cast_reg_651[7] <= tmp33_cast_fu_322_p1[7];
tmp33_cast_reg_651[8] <= tmp33_cast_fu_322_p1[8];
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp34_cast_reg_657[0] <= tmp34_cast_fu_332_p1[0];
tmp34_cast_reg_657[1] <= tmp34_cast_fu_332_p1[1];
tmp34_cast_reg_657[2] <= tmp34_cast_fu_332_p1[2];
tmp34_cast_reg_657[3] <= tmp34_cast_fu_332_p1[3];
tmp34_cast_reg_657[4] <= tmp34_cast_fu_332_p1[4];
tmp34_cast_reg_657[5] <= tmp34_cast_fu_332_p1[5];
tmp34_cast_reg_657[6] <= tmp34_cast_fu_332_p1[6];
tmp34_cast_reg_657[7] <= tmp34_cast_fu_332_p1[7];
tmp34_cast_reg_657[8] <= tmp34_cast_fu_332_p1[8];
tmp34_cast_reg_657[9] <= tmp34_cast_fu_332_p1[9];
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp36_cast1_reg_662[0] <= tmp36_cast1_fu_336_p1[0];
tmp36_cast1_reg_662[1] <= tmp36_cast1_fu_336_p1[1];
tmp36_cast1_reg_662[2] <= tmp36_cast1_fu_336_p1[2];
tmp36_cast1_reg_662[3] <= tmp36_cast1_fu_336_p1[3];
tmp36_cast1_reg_662[4] <= tmp36_cast1_fu_336_p1[4];
tmp36_cast1_reg_662[5] <= tmp36_cast1_fu_336_p1[5];
tmp36_cast1_reg_662[6] <= tmp36_cast1_fu_336_p1[6];
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp36_cast_reg_667[0] <= tmp36_cast_fu_344_p1[0];
tmp36_cast_reg_667[1] <= tmp36_cast_fu_344_p1[1];
tmp36_cast_reg_667[2] <= tmp36_cast_fu_344_p1[2];
tmp36_cast_reg_667[3] <= tmp36_cast_fu_344_p1[3];
tmp36_cast_reg_667[4] <= tmp36_cast_fu_344_p1[4];
tmp36_cast_reg_667[5] <= tmp36_cast_fu_344_p1[5];
tmp36_cast_reg_667[6] <= tmp36_cast_fu_344_p1[6];
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp37_cast_reg_673[0] <= tmp37_cast_fu_354_p1[0];
tmp37_cast_reg_673[1] <= tmp37_cast_fu_354_p1[1];
tmp37_cast_reg_673[2] <= tmp37_cast_fu_354_p1[2];
tmp37_cast_reg_673[3] <= tmp37_cast_fu_354_p1[3];
tmp37_cast_reg_673[4] <= tmp37_cast_fu_354_p1[4];
tmp37_cast_reg_673[5] <= tmp37_cast_fu_354_p1[5];
tmp37_cast_reg_673[6] <= tmp37_cast_fu_354_p1[6];
end
if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
tmp6_cast_reg_702[0] <= tmp6_cast_fu_413_p1[0];
tmp6_cast_reg_702[1] <= tmp6_cast_fu_413_p1[1];
tmp6_cast_reg_702[2] <= tmp6_cast_fu_413_p1[2];
tmp6_cast_reg_702[3] <= tmp6_cast_fu_413_p1[3];
tmp6_cast_reg_702[4] <= tmp6_cast_fu_413_p1[4];
tmp6_cast_reg_702[5] <= tmp6_cast_fu_413_p1[5];
tmp6_cast_reg_702[6] <= tmp6_cast_fu_413_p1[6];
tmp6_cast_reg_702[7] <= tmp6_cast_fu_413_p1[7];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
tmp_13_reg_707 <= ($signed(tmp_5_cast_reg_697) < $signed(j_1_fu_417_p2)? 1'b1: 1'b0);
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp_1_cast_reg_641 <= {{23{tmp_1_fu_304_p2[8]}}, {tmp_1_fu_304_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
tmp_41_reg_774 <= (j_3_phi_fu_216_p4 + ap_const_lv8_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
tmp_4_reg_683 <= ($signed(tmp_1_cast_reg_641) < $signed(j_fu_374_p2)? 1'b1: 1'b0);
end
if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
tmp_5_cast_reg_697 <= {{22{tmp_5_fu_398_p2[9]}}, {tmp_5_fu_398_p2}};
end
if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
tmp_cast_reg_726[0] <= tmp_cast_fu_478_p1[0];
tmp_cast_reg_726[1] <= tmp_cast_fu_478_p1[1];
tmp_cast_reg_726[2] <= tmp_cast_fu_478_p1[2];
tmp_cast_reg_726[3] <= tmp_cast_fu_478_p1[3];
tmp_cast_reg_726[4] <= tmp_cast_fu_478_p1[4];
tmp_cast_reg_726[5] <= tmp_cast_fu_478_p1[5];
tmp_cast_reg_726[6] <= tmp_cast_fu_478_p1[6];
tmp_cast_reg_726[7] <= tmp_cast_fu_478_p1[7];
tmp_cast_reg_726[8] <= tmp_cast_fu_478_p1[8];
tmp_cast_reg_726[9] <= tmp_cast_fu_478_p1[9];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
v_addr_12_reg_764 <= v_addr_12_reg_7640;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
v_addr_1_reg_769 <= v_addr_1_reg_7690;
end
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
v_load_1_reg_786 <= v_q1;
end
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
v_load_reg_779 <= v_q0;
end
end
/// a_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it10 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it10 or tmp_4_fu_380_p2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it10 or ap_reg_ppstg_a_addr_2_reg_687_pp0_it10 or tmp_13_fu_422_p2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it10 or ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it10 or exitcond_fu_509_p2 or ap_reg_ppstg_exitcond_reg_736_pp2_it10 or ap_reg_ppstg_a_addr_4_reg_745_pp2_it10 or tmp_3_fu_385_p1 or tmp_32_fu_448_p1 or tmp_44_fu_540_p1)
begin
if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it10))) begin
a_address0 = ap_reg_ppstg_a_addr_4_reg_745_pp2_it10;
end else if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it10))) begin
a_address0 = ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it10;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it10))) begin
a_address0 = ap_reg_ppstg_a_addr_2_reg_687_pp0_it10;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2))) begin
a_address0 = tmp_44_fu_540_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2))) begin
a_address0 = tmp_32_fu_448_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2))) begin
a_address0 = tmp_3_fu_385_p1;
end else begin
a_address0 = ap_reg_ppstg_a_addr_4_reg_745_pp2_it10;
end
end
/// a_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it11 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it11 or tmp_4_fu_380_p2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it11 or ap_reg_ppstg_a_addr_1_reg_692_pp0_it11 or tmp_13_fu_422_p2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it11 or ap_reg_ppstg_a_addr_3_reg_721_pp1_it11 or exitcond_fu_509_p2 or ap_reg_ppstg_exitcond_reg_736_pp2_it11 or ap_reg_ppstg_a_addr_5_reg_750_pp2_it11 or tmp_14_fu_390_p1 or tmp_42_fu_464_p1 or tmp_46_fu_560_p1)
begin
if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it11))) begin
a_address1 = ap_reg_ppstg_a_addr_5_reg_750_pp2_it11;
end else if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it11))) begin
a_address1 = ap_reg_ppstg_a_addr_3_reg_721_pp1_it11;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it11))) begin
a_address1 = ap_reg_ppstg_a_addr_1_reg_692_pp0_it11;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2))) begin
a_address1 = tmp_46_fu_560_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2))) begin
a_address1 = tmp_42_fu_464_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2))) begin
a_address1 = tmp_14_fu_390_p1;
end else begin
a_address1 = ap_reg_ppstg_a_addr_5_reg_750_pp2_it11;
end
end
/// a_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it10 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it10 or tmp_4_fu_380_p2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it10 or tmp_13_fu_422_p2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it10 or exitcond_fu_509_p2 or ap_reg_ppstg_exitcond_reg_736_pp2_it10)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it10)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it10)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it10)))) begin
a_ce0 = ap_const_logic_1;
end else begin
a_ce0 = ap_const_logic_0;
end
end
/// a_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it11 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it11 or tmp_4_fu_380_p2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it11 or tmp_13_fu_422_p2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it11 or exitcond_fu_509_p2 or ap_reg_ppstg_exitcond_reg_736_pp2_it11)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it11)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it11)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it11)))) begin
a_ce1 = ap_const_logic_1;
end else begin
a_ce1 = ap_const_logic_0;
end
end
/// a_d1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp1_it11 or ap_reg_ppiten_pp2_it11 or ap_reg_ppstg_reg_290_pp0_it10 or ap_reg_ppstg_reg_290_pp1_it10 or ap_reg_ppstg_reg_290_pp2_it10 or ap_reg_ppstg_tmp_4_reg_683_pp0_it11 or ap_reg_ppstg_tmp_13_reg_707_pp1_it11 or ap_reg_ppstg_exitcond_reg_736_pp2_it11)
begin
if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it11))) begin
a_d1 = ap_reg_ppstg_reg_290_pp2_it10;
end else if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it11))) begin
a_d1 = ap_reg_ppstg_reg_290_pp1_it10;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it11))) begin
a_d1 = ap_reg_ppstg_reg_290_pp0_it10;
end else begin
a_d1 = ap_reg_ppstg_reg_290_pp2_it10;
end
end
/// a_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp1_it10 or ap_reg_ppiten_pp2_it10 or ap_reg_ppstg_tmp_4_reg_683_pp0_it10 or ap_reg_ppstg_tmp_13_reg_707_pp1_it10 or ap_reg_ppstg_exitcond_reg_736_pp2_it10)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it10)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it10)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it10)))) begin
a_we0 = ap_const_logic_1;
end else begin
a_we0 = ap_const_logic_0;
end
end
/// a_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp1_it11 or ap_reg_ppiten_pp2_it11 or ap_reg_ppstg_tmp_4_reg_683_pp0_it11 or ap_reg_ppstg_tmp_13_reg_707_pp1_it11 or ap_reg_ppstg_exitcond_reg_736_pp2_it11)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it11)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it11)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it11)))) begin
a_we1 = ap_const_logic_1;
end else begin
a_we1 = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it10 or ap_reg_ppiten_pp1_it11 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it10 or ap_reg_ppiten_pp2_it11 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it10 or ap_reg_ppiten_pp3_it11 or tmp_4_fu_380_p2 or tmp_13_fu_422_p2 or exitcond_fu_509_p2 or exitcond1_fu_565_p2)
begin
if (((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~(ap_const_lv1_0 == exitcond1_fu_565_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
ap_NS_fsm = ap_ST_pp3_stg1_fsm_11;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_565_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it10)))) begin
ap_NS_fsm = ap_ST_st100_fsm_12;
end else if (((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond_fu_509_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it1)))) begin
ap_NS_fsm = ap_ST_pp2_stg1_fsm_9;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it1)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it10)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & ~((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it10))))) begin
ap_NS_fsm = ap_ST_pp3_stg0_fsm_10;
end else if (((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_const_lv1_0 == tmp_13_fu_422_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_pp1_stg1_fsm_6;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_13_fu_422_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it10)))) begin
ap_NS_fsm = ap_ST_st51_fsm_7;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_const_lv1_0 == tmp_4_fu_380_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_pp0_stg1_fsm_3;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_4_fu_380_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it10)))) begin
ap_NS_fsm = ap_ST_st26_fsm_4;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st100_fsm_12 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if (((ap_ST_st51_fsm_7 == ap_CS_fsm) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & ~((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it10))))) begin
ap_NS_fsm = ap_ST_pp2_stg0_fsm_8;
end else if (((ap_ST_st26_fsm_4 == ap_CS_fsm) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & ~((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it10))))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_5;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it10))))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st100_fsm_12 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st100_fsm_12 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// grp_fu_224_opcode assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7)))) begin
grp_fu_224_opcode = ap_const_lv2_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)))) begin
grp_fu_224_opcode = ap_const_lv2_0;
end else begin
grp_fu_224_opcode = ap_const_lv2_1;
end
end
/// grp_fu_224_p0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_reg_240_pp0_it6 or ap_reg_ppstg_reg_240_pp1_it6 or ap_reg_ppstg_reg_240_pp2_it6 or reg_254 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7 or ap_reg_ppstg_v_load_reg_779_pp3_it6)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7))) begin
grp_fu_224_p0 = ap_reg_ppstg_v_load_reg_779_pp3_it6;
end else if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7))) begin
grp_fu_224_p0 = ap_reg_ppstg_reg_240_pp2_it6;
end else if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7))) begin
grp_fu_224_p0 = ap_reg_ppstg_reg_240_pp1_it6;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7))) begin
grp_fu_224_p0 = ap_reg_ppstg_reg_240_pp0_it6;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)))) begin
grp_fu_224_p0 = reg_254;
end else begin
grp_fu_224_p0 = ap_reg_ppstg_v_load_reg_779_pp3_it6;
end
end
/// grp_fu_224_p1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_reg_247_pp0_it2 or ap_reg_ppstg_reg_247_pp1_it2 or ap_reg_ppstg_reg_247_pp2_it2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or reg_274 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7 or ap_reg_ppstg_v_load_1_reg_786_pp3_it2)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm))) begin
grp_fu_224_p1 = ap_reg_ppstg_v_load_1_reg_786_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
grp_fu_224_p1 = ap_reg_ppstg_reg_247_pp2_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
grp_fu_224_p1 = ap_reg_ppstg_reg_247_pp1_it2;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7)))) begin
grp_fu_224_p1 = reg_274;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
grp_fu_224_p1 = ap_reg_ppstg_reg_247_pp0_it2;
end else begin
grp_fu_224_p1 = ap_reg_ppstg_v_load_1_reg_786_pp3_it2;
end
end
/// grp_fu_228_opcode assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)))) begin
grp_fu_228_opcode = ap_const_lv2_1;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7)))) begin
grp_fu_228_opcode = ap_const_lv2_0;
end else begin
grp_fu_228_opcode = ap_const_lv2_1;
end
end
/// grp_fu_228_p0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_reg_240_pp0_it2 or ap_reg_ppstg_reg_240_pp1_it2 or ap_reg_ppstg_reg_240_pp2_it2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or reg_279 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7 or ap_reg_ppstg_v_load_reg_779_pp3_it2)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm))) begin
grp_fu_228_p0 = ap_reg_ppstg_v_load_reg_779_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
grp_fu_228_p0 = ap_reg_ppstg_reg_240_pp2_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
grp_fu_228_p0 = ap_reg_ppstg_reg_240_pp1_it2;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7)))) begin
grp_fu_228_p0 = reg_279;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
grp_fu_228_p0 = ap_reg_ppstg_reg_240_pp0_it2;
end else begin
grp_fu_228_p0 = ap_reg_ppstg_v_load_reg_779_pp3_it2;
end
end
/// grp_fu_228_p1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_reg_247_pp0_it6 or ap_reg_ppstg_reg_247_pp1_it6 or ap_reg_ppstg_reg_247_pp2_it6 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or reg_259 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7 or ap_reg_ppstg_v_load_1_reg_786_pp3_it6)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7))) begin
grp_fu_228_p1 = ap_reg_ppstg_v_load_1_reg_786_pp3_it6;
end else if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7))) begin
grp_fu_228_p1 = ap_reg_ppstg_reg_247_pp2_it6;
end else if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7))) begin
grp_fu_228_p1 = ap_reg_ppstg_reg_247_pp1_it6;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7))) begin
grp_fu_228_p1 = ap_reg_ppstg_reg_247_pp0_it6;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)))) begin
grp_fu_228_p1 = reg_259;
end else begin
grp_fu_228_p1 = ap_reg_ppstg_v_load_1_reg_786_pp3_it6;
end
end
/// grp_fu_232_p0 assign process. ///
always @ (ap_CS_fsm or reg_240 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or tmp_4_reg_683 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it5 or tmp_13_reg_707 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it5 or exitcond_reg_736 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it5 or exitcond1_reg_755 or reg_264 or ap_reg_ppstg_tmp_4_reg_683_pp0_it5 or ap_reg_ppstg_tmp_13_reg_707_pp1_it5 or ap_reg_ppstg_exitcond_reg_736_pp2_it5 or ap_reg_ppstg_exitcond1_reg_755_pp3_it5 or v_load_reg_779)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
grp_fu_232_p0 = v_load_reg_779;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it5)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it5)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it5)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it5)))) begin
grp_fu_232_p0 = reg_264;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)))) begin
grp_fu_232_p0 = reg_240;
end else begin
grp_fu_232_p0 = v_load_reg_779;
end
end
/// grp_fu_232_p1 assign process. ///
always @ (ap_CS_fsm or s or tau or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or tmp_4_reg_683 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it5 or tmp_13_reg_707 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it5 or exitcond_reg_736 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it5 or exitcond1_reg_755 or ap_reg_ppstg_tmp_4_reg_683_pp0_it5 or ap_reg_ppstg_tmp_13_reg_707_pp1_it5 or ap_reg_ppstg_exitcond_reg_736_pp2_it5 or ap_reg_ppstg_exitcond1_reg_755_pp3_it5)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it5)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it5)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it5)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it5)))) begin
grp_fu_232_p1 = s;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755)))) begin
grp_fu_232_p1 = tau;
end else begin
grp_fu_232_p1 = s;
end
end
/// grp_fu_236_p0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or tmp_4_reg_683 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it5 or tmp_13_reg_707 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it5 or exitcond_reg_736 or reg_247 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it5 or exitcond1_reg_755 or reg_269 or ap_reg_ppstg_tmp_4_reg_683_pp0_it5 or ap_reg_ppstg_tmp_13_reg_707_pp1_it5 or ap_reg_ppstg_exitcond_reg_736_pp2_it5 or ap_reg_ppstg_exitcond1_reg_755_pp3_it5 or v_load_1_reg_786)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
grp_fu_236_p0 = v_load_1_reg_786;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it5)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it5)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it5)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it5)))) begin
grp_fu_236_p0 = reg_269;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)))) begin
grp_fu_236_p0 = reg_247;
end else begin
grp_fu_236_p0 = v_load_1_reg_786;
end
end
/// grp_fu_236_p1 assign process. ///
always @ (ap_CS_fsm or s or tau or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or tmp_4_reg_683 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it5 or tmp_13_reg_707 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it5 or exitcond_reg_736 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it5 or exitcond1_reg_755 or ap_reg_ppstg_tmp_4_reg_683_pp0_it5 or ap_reg_ppstg_tmp_13_reg_707_pp1_it5 or ap_reg_ppstg_exitcond_reg_736_pp2_it5 or ap_reg_ppstg_exitcond1_reg_755_pp3_it5)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it5)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it5)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it5)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it5)))) begin
grp_fu_236_p1 = s;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755)))) begin
grp_fu_236_p1 = tau;
end else begin
grp_fu_236_p1 = s;
end
end
/// indvar1_phi_fu_194_p4 assign process. ///
always @ (ap_CS_fsm or indvar1_reg_190 or ap_reg_ppiten_pp2_it1 or exitcond_reg_736 or indvar_next2_reg_740)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
indvar1_phi_fu_194_p4 = indvar_next2_reg_740;
end else begin
indvar1_phi_fu_194_p4 = indvar1_reg_190;
end
end
/// indvar2_phi_fu_172_p4 assign process. ///
always @ (ap_CS_fsm or indvar2_reg_168 or ap_reg_ppiten_pp0_it1 or tmp_4_reg_683 or j_reg_678)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar2_phi_fu_172_p4 = j_reg_678;
end else begin
indvar2_phi_fu_172_p4 = indvar2_reg_168;
end
end
/// indvar4_phi_fu_183_p4 assign process. ///
always @ (ap_CS_fsm or indvar4_reg_179 or ap_reg_ppiten_pp1_it1 or tmp_13_reg_707 or indvar_next5_reg_711)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
indvar4_phi_fu_183_p4 = indvar_next5_reg_711;
end else begin
indvar4_phi_fu_183_p4 = indvar4_reg_179;
end
end
/// indvar_phi_fu_205_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_201 or ap_reg_ppiten_pp3_it1 or exitcond1_reg_755 or indvar_next_reg_759)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
indvar_phi_fu_205_p4 = indvar_next_reg_759;
end else begin
indvar_phi_fu_205_p4 = indvar_reg_201;
end
end
/// j_3_phi_fu_216_p4 assign process. ///
always @ (ap_CS_fsm or j_3_reg_212 or ap_reg_ppiten_pp3_it1 or exitcond1_reg_755 or tmp_41_reg_774)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
j_3_phi_fu_216_p4 = tmp_41_reg_774;
end else begin
j_3_phi_fu_216_p4 = j_3_reg_212;
end
end
/// v_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it10 or exitcond1_fu_565_p2 or ap_reg_ppstg_exitcond1_reg_755_pp3_it10 or ap_reg_ppstg_v_addr_12_reg_764_pp3_it10 or tmp_47_fu_596_p1)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it10))) begin
v_address0 = ap_reg_ppstg_v_addr_12_reg_764_pp3_it10;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
v_address0 = tmp_47_fu_596_p1;
end else begin
v_address0 = ap_reg_ppstg_v_addr_12_reg_764_pp3_it10;
end
end
/// v_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it11 or exitcond1_fu_565_p2 or ap_reg_ppstg_exitcond1_reg_755_pp3_it11 or ap_reg_ppstg_v_addr_1_reg_769_pp3_it11 or tmp_48_fu_606_p1)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it11))) begin
v_address1 = ap_reg_ppstg_v_addr_1_reg_769_pp3_it11;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
v_address1 = tmp_48_fu_606_p1;
end else begin
v_address1 = ap_reg_ppstg_v_addr_1_reg_769_pp3_it11;
end
end
/// v_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it10 or exitcond1_fu_565_p2 or ap_reg_ppstg_exitcond1_reg_755_pp3_it10)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it10)))) begin
v_ce0 = ap_const_logic_1;
end else begin
v_ce0 = ap_const_logic_0;
end
end
/// v_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it11 or exitcond1_fu_565_p2 or ap_reg_ppstg_exitcond1_reg_755_pp3_it11)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it11)))) begin
v_ce1 = ap_const_logic_1;
end else begin
v_ce1 = ap_const_logic_0;
end
end
/// v_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it10 or ap_reg_ppstg_exitcond1_reg_755_pp3_it10)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it10))) begin
v_we0 = ap_const_logic_1;
end else begin
v_we0 = ap_const_logic_0;
end
end
/// v_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it11 or ap_reg_ppstg_exitcond1_reg_755_pp3_it11)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it11))) begin
v_we1 = ap_const_logic_1;
end else begin
v_we1 = ap_const_logic_0;
end
end
assign a_addr1_fu_554_p2 = (a_addr_cast_fu_550_p1 + j_2_fu_520_p2);
assign a_addr2_fu_442_p2 = (a_addr9_cast_fu_438_p1 + j_1_fu_417_p2);
assign a_addr3_cast_fu_530_p1 = {{18{1'b0}}, {a_addr3_fu_525_p2}};
assign a_addr3_fu_525_p2 = tmp36_cast_reg_667 << ap_const_lv14_7;
assign a_addr4_fu_534_p2 = (a_addr3_cast_fu_530_p1 + j_2_fu_520_p2);
assign a_addr5_fu_369_p2 = (tmp37_cast_reg_673 + tmp7_fu_358_p2);
assign a_addr6_fu_453_p2 = j_1_fu_417_p2 << ap_const_lv32_7;
assign a_addr7_fu_459_p2 = (a_addr6_fu_453_p2 + tmp1_reg_646);
assign a_addr8_fu_364_p2 = (tmp34_cast_reg_657 + tmp7_fu_358_p2);
assign a_addr9_cast_fu_438_p1 = {{18{1'b0}}, {a_addr9_fu_433_p2}};
assign a_addr9_fu_433_p2 = tmp36_cast_reg_667 << ap_const_lv14_7;
assign a_addr_1_reg_6920 = {{32{a_addr8_fu_364_p2[31]}}, {a_addr8_fu_364_p2}};
assign a_addr_2_6_reg_7160 = {{32{a_addr2_fu_442_p2[31]}}, {a_addr2_fu_442_p2}};
assign a_addr_2_reg_6870 = {{32{a_addr5_fu_369_p2[31]}}, {a_addr5_fu_369_p2}};
assign a_addr_3_reg_7210 = {{32{a_addr7_fu_459_p2[31]}}, {a_addr7_fu_459_p2}};
assign a_addr_4_reg_7450 = {{32{a_addr4_fu_534_p2[31]}}, {a_addr4_fu_534_p2}};
assign a_addr_5_reg_7500 = {{32{a_addr1_fu_554_p2[31]}}, {a_addr1_fu_554_p2}};
assign a_addr_cast_fu_550_p1 = {{16{1'b0}}, {a_addr_fu_545_p2}};
assign a_addr_fu_545_p2 = tmp33_cast_reg_651 << ap_const_lv16_7;
assign a_d0 = reg_284;
assign exitcond1_fu_565_p2 = (indvar_phi_fu_205_p4 == ap_const_lv8_80? 1'b1: 1'b0);
assign exitcond_fu_509_p2 = (indvar1_phi_fu_194_p4 == tmp10_reg_731? 1'b1: 1'b0);
assign grp_fu_224_ce = ap_const_logic_1;
assign grp_fu_228_ce = ap_const_logic_1;
assign grp_fu_232_ce = ap_const_logic_1;
assign grp_fu_236_ce = ap_const_logic_1;
assign ip_cast1_cast_fu_300_p1 = {{2{1'b0}}, {ip}};
assign ip_cast2_fu_296_p1 = {{1{1'b0}}, {ip}};
assign iq_cast1_fu_469_p1 = {{1{1'b0}}, {iq}};
assign iq_cast_cast_fu_395_p1 = {{1{1'b0}}, {iq}};
assign j_1_fu_417_p2 = (tmp6_cast_reg_702 + indvar4_phi_fu_183_p4);
assign j_2_fu_520_p2 = (tmp_cast_reg_726 + indvar1_phi_fu_194_p4);
assign j_fu_374_p2 = (indvar2_phi_fu_172_p4 + ap_const_lv32_1);
assign tmp1_fu_314_p1 = {{23{1'b0}}, {iq}};
assign tmp2_fu_326_p2 = (tmp33_cast1_fu_318_p1 + ap_const_lv10_80);
assign tmp33_cast1_fu_318_p1 = {{1{1'b0}}, {iq}};
assign tmp33_cast_fu_322_p1 = {{7{1'b0}}, {iq}};
assign tmp34_cast_fu_332_p1 = {{22{1'b0}}, {tmp2_fu_326_p2}};
assign tmp36_cast1_fu_336_p1 = {{9{1'b0}}, {ip}};
assign tmp36_cast2_fu_340_p1 = {{2{1'b0}}, {ip}};
assign tmp36_cast_fu_344_p1 = {{7{1'b0}}, {ip}};
assign tmp37_cast_fu_354_p1 = {{23{1'b0}}, {tmp5_fu_348_p2}};
assign tmp3_fu_482_p2 = (tmp_fu_472_p2 > ap_const_lv10_81? 1'b1: 1'b0);
assign tmp4_fu_488_p3 = ((tmp3_fu_482_p2)? iq: ap_const_lv9_80);
assign tmp5_fu_348_p2 = (tmp36_cast2_fu_340_p1 | ap_const_lv9_80);
assign tmp6_cast_fu_413_p1 = {{24{1'b0}}, {tmp6_fu_408_p2}};
assign tmp6_fu_408_p2 = (ip_cast2_reg_636 + ap_const_lv8_1);
assign tmp7_fu_358_p2 = indvar2_phi_fu_172_p4 << ap_const_lv32_7;
assign tmp8_fu_495_p1 = {{1{1'b0}}, {tmp4_fu_488_p3}};
assign tmp9_fu_499_p2 = (tmp8_fu_495_p1 - iq_cast1_fu_469_p1);
assign tmp_13_fu_422_p2 = ($signed(tmp_5_cast_reg_697) < $signed(j_1_fu_417_p2)? 1'b1: 1'b0);
assign tmp_14_fu_390_p1 = {{32{a_addr8_fu_364_p2[31]}}, {a_addr8_fu_364_p2}};
assign tmp_1_fu_304_p2 = (ip_cast1_cast_fu_300_p1 + ap_const_lv9_1FF);
assign tmp_32_fu_448_p1 = {{32{a_addr2_fu_442_p2[31]}}, {a_addr2_fu_442_p2}};
assign tmp_32_trn_cast_fu_577_p1 = {{7{1'b0}}, {j_3_phi_fu_216_p4}};
assign tmp_3_fu_385_p1 = {{32{a_addr5_fu_369_p2[31]}}, {a_addr5_fu_369_p2}};
assign tmp_42_fu_464_p1 = {{32{a_addr7_fu_459_p2[31]}}, {a_addr7_fu_459_p2}};
assign tmp_44_fu_540_p1 = {{32{a_addr4_fu_534_p2[31]}}, {a_addr4_fu_534_p2}};
assign tmp_46_fu_560_p1 = {{32{a_addr1_fu_554_p2[31]}}, {a_addr1_fu_554_p2}};
assign tmp_47_fu_596_p1 = {{48{1'b0}}, {v_addr1_fu_591_p2}};
assign tmp_48_fu_606_p1 = {{48{1'b0}}, {v_addr2_fu_601_p2}};
assign tmp_4_fu_380_p2 = ($signed(tmp_1_cast_reg_641) < $signed(j_fu_374_p2)? 1'b1: 1'b0);
assign tmp_5_fu_398_p2 = (iq_cast_cast_fu_395_p1 + ap_const_lv10_3FF);
assign tmp_cast_fu_478_p1 = {{22{1'b0}}, {tmp_fu_472_p2}};
assign tmp_fu_472_p2 = (iq_cast1_fu_469_p1 + ap_const_lv10_1);
assign v_addr1_fu_591_p2 = (v_addr_cast_fu_587_p1 | tmp36_cast1_reg_662);
assign v_addr2_fu_601_p2 = (v_addr_cast_fu_587_p1 + tmp33_cast_reg_651);
assign v_addr_12_reg_7640 = {{48{1'b0}}, {v_addr1_fu_591_p2}};
assign v_addr_1_reg_7690 = {{48{1'b0}}, {v_addr2_fu_601_p2}};
assign v_addr_cast_fu_587_p1 = {{1{1'b0}}, {v_addr_fu_581_p2}};
assign v_addr_fu_581_p2 = tmp_32_trn_cast_fu_577_p1 << ap_const_lv15_7;
assign v_d0 = reg_284;
assign v_d1 = ap_reg_ppstg_reg_290_pp3_it10;
always @ (ap_clk)
begin
ip_cast2_reg_636[7] <= 1'b0;
end
always @ (ap_clk)
begin
tmp1_reg_646[9] <= 1'b0;
tmp1_reg_646[10] <= 1'b0;
tmp1_reg_646[11] <= 1'b0;
tmp1_reg_646[12] <= 1'b0;
tmp1_reg_646[13] <= 1'b0;
tmp1_reg_646[14] <= 1'b0;
tmp1_reg_646[15] <= 1'b0;
tmp1_reg_646[16] <= 1'b0;
tmp1_reg_646[17] <= 1'b0;
tmp1_reg_646[18] <= 1'b0;
tmp1_reg_646[19] <= 1'b0;
tmp1_reg_646[20] <= 1'b0;
tmp1_reg_646[21] <= 1'b0;
tmp1_reg_646[22] <= 1'b0;
tmp1_reg_646[23] <= 1'b0;
tmp1_reg_646[24] <= 1'b0;
tmp1_reg_646[25] <= 1'b0;
tmp1_reg_646[26] <= 1'b0;
tmp1_reg_646[27] <= 1'b0;
tmp1_reg_646[28] <= 1'b0;
tmp1_reg_646[29] <= 1'b0;
tmp1_reg_646[30] <= 1'b0;
tmp1_reg_646[31] <= 1'b0;
end
always @ (ap_clk)
begin
tmp33_cast_reg_651[9] <= 1'b0;
tmp33_cast_reg_651[10] <= 1'b0;
tmp33_cast_reg_651[11] <= 1'b0;
tmp33_cast_reg_651[12] <= 1'b0;
tmp33_cast_reg_651[13] <= 1'b0;
tmp33_cast_reg_651[14] <= 1'b0;
tmp33_cast_reg_651[15] <= 1'b0;
end
always @ (ap_clk)
begin
tmp34_cast_reg_657[10] <= 1'b0;
tmp34_cast_reg_657[11] <= 1'b0;
tmp34_cast_reg_657[12] <= 1'b0;
tmp34_cast_reg_657[13] <= 1'b0;
tmp34_cast_reg_657[14] <= 1'b0;
tmp34_cast_reg_657[15] <= 1'b0;
tmp34_cast_reg_657[16] <= 1'b0;
tmp34_cast_reg_657[17] <= 1'b0;
tmp34_cast_reg_657[18] <= 1'b0;
tmp34_cast_reg_657[19] <= 1'b0;
tmp34_cast_reg_657[20] <= 1'b0;
tmp34_cast_reg_657[21] <= 1'b0;
tmp34_cast_reg_657[22] <= 1'b0;
tmp34_cast_reg_657[23] <= 1'b0;
tmp34_cast_reg_657[24] <= 1'b0;
tmp34_cast_reg_657[25] <= 1'b0;
tmp34_cast_reg_657[26] <= 1'b0;
tmp34_cast_reg_657[27] <= 1'b0;
tmp34_cast_reg_657[28] <= 1'b0;
tmp34_cast_reg_657[29] <= 1'b0;
tmp34_cast_reg_657[30] <= 1'b0;
tmp34_cast_reg_657[31] <= 1'b0;
end
always @ (ap_clk)
begin
tmp36_cast1_reg_662[7] <= 1'b0;
tmp36_cast1_reg_662[8] <= 1'b0;
tmp36_cast1_reg_662[9] <= 1'b0;
tmp36_cast1_reg_662[10] <= 1'b0;
tmp36_cast1_reg_662[11] <= 1'b0;
tmp36_cast1_reg_662[12] <= 1'b0;
tmp36_cast1_reg_662[13] <= 1'b0;
tmp36_cast1_reg_662[14] <= 1'b0;
tmp36_cast1_reg_662[15] <= 1'b0;
end
always @ (ap_clk)
begin
tmp36_cast_reg_667[7] <= 1'b0;
tmp36_cast_reg_667[8] <= 1'b0;
tmp36_cast_reg_667[9] <= 1'b0;
tmp36_cast_reg_667[10] <= 1'b0;
tmp36_cast_reg_667[11] <= 1'b0;
tmp36_cast_reg_667[12] <= 1'b0;
tmp36_cast_reg_667[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp37_cast_reg_673[7] <= 1'b1;
tmp37_cast_reg_673[8] <= 1'b0;
tmp37_cast_reg_673[9] <= 1'b0;
tmp37_cast_reg_673[10] <= 1'b0;
tmp37_cast_reg_673[11] <= 1'b0;
tmp37_cast_reg_673[12] <= 1'b0;
tmp37_cast_reg_673[13] <= 1'b0;
tmp37_cast_reg_673[14] <= 1'b0;
tmp37_cast_reg_673[15] <= 1'b0;
tmp37_cast_reg_673[16] <= 1'b0;
tmp37_cast_reg_673[17] <= 1'b0;
tmp37_cast_reg_673[18] <= 1'b0;
tmp37_cast_reg_673[19] <= 1'b0;
tmp37_cast_reg_673[20] <= 1'b0;
tmp37_cast_reg_673[21] <= 1'b0;
tmp37_cast_reg_673[22] <= 1'b0;
tmp37_cast_reg_673[23] <= 1'b0;
tmp37_cast_reg_673[24] <= 1'b0;
tmp37_cast_reg_673[25] <= 1'b0;
tmp37_cast_reg_673[26] <= 1'b0;
tmp37_cast_reg_673[27] <= 1'b0;
tmp37_cast_reg_673[28] <= 1'b0;
tmp37_cast_reg_673[29] <= 1'b0;
tmp37_cast_reg_673[30] <= 1'b0;
tmp37_cast_reg_673[31] <= 1'b0;
end
always @ (ap_clk)
begin
tmp6_cast_reg_702[8] <= 1'b0;
tmp6_cast_reg_702[9] <= 1'b0;
tmp6_cast_reg_702[10] <= 1'b0;
tmp6_cast_reg_702[11] <= 1'b0;
tmp6_cast_reg_702[12] <= 1'b0;
tmp6_cast_reg_702[13] <= 1'b0;
tmp6_cast_reg_702[14] <= 1'b0;
tmp6_cast_reg_702[15] <= 1'b0;
tmp6_cast_reg_702[16] <= 1'b0;
tmp6_cast_reg_702[17] <= 1'b0;
tmp6_cast_reg_702[18] <= 1'b0;
tmp6_cast_reg_702[19] <= 1'b0;
tmp6_cast_reg_702[20] <= 1'b0;
tmp6_cast_reg_702[21] <= 1'b0;
tmp6_cast_reg_702[22] <= 1'b0;
tmp6_cast_reg_702[23] <= 1'b0;
tmp6_cast_reg_702[24] <= 1'b0;
tmp6_cast_reg_702[25] <= 1'b0;
tmp6_cast_reg_702[26] <= 1'b0;
tmp6_cast_reg_702[27] <= 1'b0;
tmp6_cast_reg_702[28] <= 1'b0;
tmp6_cast_reg_702[29] <= 1'b0;
tmp6_cast_reg_702[30] <= 1'b0;
tmp6_cast_reg_702[31] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_cast_reg_726[10] <= 1'b0;
tmp_cast_reg_726[11] <= 1'b0;
tmp_cast_reg_726[12] <= 1'b0;
tmp_cast_reg_726[13] <= 1'b0;
tmp_cast_reg_726[14] <= 1'b0;
tmp_cast_reg_726[15] <= 1'b0;
tmp_cast_reg_726[16] <= 1'b0;
tmp_cast_reg_726[17] <= 1'b0;
tmp_cast_reg_726[18] <= 1'b0;
tmp_cast_reg_726[19] <= 1'b0;
tmp_cast_reg_726[20] <= 1'b0;
tmp_cast_reg_726[21] <= 1'b0;
tmp_cast_reg_726[22] <= 1'b0;
tmp_cast_reg_726[23] <= 1'b0;
tmp_cast_reg_726[24] <= 1'b0;
tmp_cast_reg_726[25] <= 1'b0;
tmp_cast_reg_726[26] <= 1'b0;
tmp_cast_reg_726[27] <= 1'b0;
tmp_cast_reg_726[28] <= 1'b0;
tmp_cast_reg_726[29] <= 1'b0;
tmp_cast_reg_726[30] <= 1'b0;
tmp_cast_reg_726[31] <= 1'b0;
end
endmodule //do_rotate
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module do_rotate_grp_fu_224_ACMP_faddfsub_1(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module do_rotate_grp_fu_228_ACMP_faddfsub_2(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module do_rotate_grp_fu_232_ACMP_fmul_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module do_rotate_grp_fu_236_ACMP_fmul_4(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module jacob (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
a_address0,
a_ce0,
a_we0,
a_d0,
a_q0,
a_address1,
a_ce1,
a_we1,
a_d1,
a_q1,
d_address0,
d_ce0,
d_we0,
d_d0,
d_q0,
d_address1,
d_ce1,
d_we1,
d_d1,
d_q1,
v_address0,
v_ce0,
v_we0,
v_d0,
v_q0,
v_address1,
v_ce1,
v_we1,
v_d1,
v_q1,
nrot_i,
nrot_o,
nrot_o_ap_vld
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output [13:0] a_address0;
output a_ce0;
output a_we0;
output [31:0] a_d0;
input [31:0] a_q0;
output [13:0] a_address1;
output a_ce1;
output a_we1;
output [31:0] a_d1;
input [31:0] a_q1;
output [6:0] d_address0;
output d_ce0;
output d_we0;
output [31:0] d_d0;
input [31:0] d_q0;
output [6:0] d_address1;
output d_ce1;
output d_we1;
output [31:0] d_d1;
input [31:0] d_q1;
output [13:0] v_address0;
output v_ce0;
output v_we0;
output [31:0] v_d0;
input [31:0] v_q0;
output [13:0] v_address1;
output v_ce1;
output v_we1;
output [31:0] v_d1;
input [31:0] v_q1;
input [31:0] nrot_i;
output [31:0] nrot_o;
output nrot_o_ap_vld;
reg ap_done;
reg ap_idle;
reg[13:0] a_address0;
reg a_ce0;
reg a_we0;
reg[31:0] a_d0;
reg a_ce1;
reg a_we1;
reg[6:0] d_address0;
reg d_ce0;
reg d_we0;
reg[31:0] d_d0;
reg[6:0] d_address1;
reg d_ce1;
reg d_we1;
reg[13:0] v_address0;
reg v_ce0;
reg v_we0;
reg[31:0] v_d0;
reg v_ce1;
reg v_we1;
reg[31:0] nrot_o;
reg nrot_o_ap_vld;
reg [8:0] ap_CS_fsm;
reg [31:0] reg_640;
wire [31:0] grp_fu_509_p2;
reg [31:0] reg_649;
reg [0:0] tmp_i5_reg_1449;
wire [63:0] grp_fu_623_p2;
reg [63:0] reg_661;
wire [63:0] grp_fu_629_p2;
reg [63:0] reg_666;
wire [31:0] grp_fu_528_p2;
reg [31:0] reg_675;
reg [31:0] reg_684;
reg [31:0] reg_692;
wire [63:0] grp_fu_618_p2;
reg [63:0] reg_698;
wire [63:0] grp_fu_635_p2;
reg [63:0] reg_704;
wire [31:0] z_q0;
reg [31:0] reg_710;
wire [63:0] tmp_9_cast_fu_732_p1;
reg [63:0] tmp_9_cast_reg_1142;
wire [15:0] tmp36_cast_fu_742_p1;
reg [15:0] tmp36_cast_reg_1147;
reg [7:0] indvar_next3_reg_1155;
wire [0:0] exitcond2_fu_772_p2;
reg [7:0] indvar_next1_reg_1176;
wire [0:0] exitcond1_fu_790_p2;
wire [0:0] tmp_6_fu_836_p2;
reg [0:0] tmp_6_reg_1191;
reg [6:0] tmp4_reg_1195;
reg [6:0] tmp_4_reg_1205;
wire [31:0] iq_1_fu_874_p2;
reg [31:0] iq_1_reg_1213;
reg [6:0] indvar_next5_reg_1221;
wire [0:0] exitcond4_fu_880_p2;
wire [0:0] grp_fu_589_p2;
reg [0:0] tmp_i_reg_1236;
reg [31:0] UnifiedRetVal_i_reg_1241;
wire [63:0] grp_fu_557_p1;
reg [63:0] tmp_s_reg_1257;
wire [31:0] grp_fu_541_p1;
reg [0:0] tmp_13_reg_1267;
reg [6:0] tmp5_reg_1271;
reg [6:0] tmp_18_reg_1276;
wire [8:0] indvar3_cast_fu_967_p1;
reg [8:0] indvar3_cast_reg_1282;
reg [6:0] tmp_19_reg_1292;
reg [6:0] d_addr_1_reg_1300;
wire [0:0] exitcond5_fu_987_p2;
reg [6:0] z_addr_1_reg_1306;
reg [8:0] iq_2_reg_1311;
wire [31:0] tmp_21_fu_1018_p2;
reg [31:0] tmp_21_reg_1316;
reg [6:0] indvar_next2_reg_1327;
reg [13:0] a_addr_2_reg_1334;
wire [0:0] exitcond7_fu_1024_p2;
reg [0:0] tmp_i1_reg_1344;
wire [31:0] UnifiedRetVal_i1_fu_1066_p3;
reg [31:0] UnifiedRetVal_i1_reg_1349;
reg [63:0] tmp_26_reg_1355;
reg [0:0] tmp_i2_reg_1362;
reg [31:0] UnifiedRetVal_i2_reg_1367;
wire [0:0] grp_fu_596_p2;
reg [0:0] tmp_28_reg_1373;
reg [0:0] tmp_i3_reg_1382;
reg [31:0] UnifiedRetVal_i3_reg_1387;
reg [31:0] tmp_29_reg_1393;
wire [6:0] d_addr_4_gep_fu_211_p3;
reg [6:0] d_addr_4_reg_1404;
wire [0:0] grp_fu_604_p2;
reg [31:0] d_load_3_reg_1410;
reg [0:0] tmp_i4_reg_1416;
reg [31:0] UnifiedRetVal_i4_reg_1421;
wire [63:0] grp_fu_561_p1;
reg [63:0] tmp_36_reg_1430;
wire [63:0] grp_fu_564_p1;
reg [63:0] tmp_38_reg_1435;
wire [31:0] grp_fu_544_p1;
reg [31:0] theta_reg_1440;
wire [0:0] grp_fu_613_p2;
wire [63:0] grp_fu_567_p1;
reg [63:0] tmp_42_reg_1454;
wire [63:0] grp_fu_570_p1;
reg [63:0] tmp_40_reg_1464;
wire [31:0] grp_fu_547_p1;
reg [31:0] tmp_47_reg_1469;
wire [31:0] grp_fu_537_p2;
reg [6:0] z_addr_3_reg_1485;
reg [31:0] tmp_59_reg_1490;
wire [31:0] z_q1;
reg [31:0] z_load_2_reg_1498;
wire [31:0] grp_fu_516_p2;
reg [31:0] tmp_61_reg_1503;
wire [31:0] grp_fu_520_p2;
reg [31:0] tmp_62_reg_1508;
wire [31:0] grp_fu_524_p2;
reg [31:0] tmp_63_reg_1513;
wire [63:0] grp_fu_573_p1;
reg [63:0] tmp_52_reg_1518;
wire [31:0] grp_fu_550_p1;
reg [31:0] c_reg_1523;
wire [63:0] grp_fu_576_p1;
reg [63:0] tmp_56_reg_1529;
wire [63:0] grp_fu_580_p1;
reg [63:0] tmp_55_reg_1534;
wire [31:0] grp_fu_553_p1;
reg [31:0] tau_reg_1539;
reg [7:0] indvar_next_reg_1547;
wire [63:0] tmp_22_fu_1124_p1;
reg [63:0] tmp_22_reg_1552;
wire [0:0] exitcond6_fu_1112_p2;
reg [6:0] b_addr_1_reg_1557;
reg [6:0] z_addr_2_reg_1562;
reg [7:0] tmp_24_reg_1567;
wire [31:0] b_q0;
reg [31:0] b_load_reg_1577;
reg [6:0] b_address0;
reg b_ce0;
reg b_we0;
reg [31:0] b_d0;
reg [6:0] z_address0;
reg z_ce0;
reg z_we0;
reg [31:0] z_d0;
wire [6:0] z_address1;
reg z_ce1;
reg z_we1;
wire [31:0] z_d1;
reg grp_do_rotate_fu_497_ap_start;
wire grp_do_rotate_fu_497_ap_done;
wire grp_do_rotate_fu_497_ap_idle;
wire [13:0] grp_do_rotate_fu_497_a_address0;
wire grp_do_rotate_fu_497_a_ce0;
wire grp_do_rotate_fu_497_a_we0;
wire [31:0] grp_do_rotate_fu_497_a_d0;
wire [31:0] grp_do_rotate_fu_497_a_q0;
wire [13:0] grp_do_rotate_fu_497_a_address1;
wire grp_do_rotate_fu_497_a_ce1;
wire grp_do_rotate_fu_497_a_we1;
wire [31:0] grp_do_rotate_fu_497_a_d1;
wire [31:0] grp_do_rotate_fu_497_a_q1;
wire [13:0] grp_do_rotate_fu_497_v_address0;
wire grp_do_rotate_fu_497_v_ce0;
wire grp_do_rotate_fu_497_v_we0;
wire [31:0] grp_do_rotate_fu_497_v_d0;
wire [31:0] grp_do_rotate_fu_497_v_q0;
wire [13:0] grp_do_rotate_fu_497_v_address1;
wire grp_do_rotate_fu_497_v_ce1;
wire grp_do_rotate_fu_497_v_we1;
wire [31:0] grp_do_rotate_fu_497_v_d1;
wire [31:0] grp_do_rotate_fu_497_v_q1;
wire [31:0] grp_do_rotate_fu_497_s;
wire [31:0] grp_do_rotate_fu_497_tau;
wire [6:0] grp_do_rotate_fu_497_ip;
wire [8:0] grp_do_rotate_fu_497_iq;
reg [7:0] indvar2_reg_253;
reg [63:0] indvar6_reg_264;
wire [0:0] exitcond_fu_746_p2;
reg [7:0] indvar5_reg_275;
reg [7:0] indvar4_reg_286;
reg [7:0] ip_1_reg_297;
reg [31:0] indvar10_reg_309;
reg [6:0] indvar7_reg_321;
reg [7:0] tmp_7_reg_332;
reg [31:0] sm_1_reg_344;
reg [6:0] indvar8_reg_356;
wire [0:0] exitcond3_fu_868_p2;
reg [31:0] iq_1_in_reg_367;
reg [31:0] sm_reg_376;
reg [31:0] tresh_reg_388;
wire [0:0] icmp_fu_939_p2;
wire [0:0] grp_fu_583_p2;
reg [6:0] indvar9_reg_400;
reg [6:0] indvar3_reg_411;
reg [7:0] tmp_17_reg_422;
reg [6:0] indvar1_reg_434;
wire [0:0] grp_fu_600_p2;
reg [31:0] iq_2_in_reg_449;
wire [31:0] t_phi_fu_465_p6;
reg [31:0] t_reg_462;
reg [7:0] indvar_reg_474;
reg [7:0] ip_4_reg_485;
wire [63:0] tmp_cast_fu_767_p1;
wire [63:0] tmp_1_fu_818_p1;
wire [63:0] tmp_2_fu_823_p1;
wire [63:0] tmp_15_fu_911_p1;
wire [63:0] tmp_48_fu_1055_p1;
wire [31:0] tmp_64_fu_1105_p2;
reg [31:0] grp_fu_509_p0;
reg [31:0] grp_fu_509_p1;
wire [31:0] grp_fu_516_p0;
wire [31:0] grp_fu_516_p1;
wire [31:0] grp_fu_520_p0;
wire [31:0] grp_fu_520_p1;
wire [31:0] grp_fu_524_p0;
wire [31:0] grp_fu_524_p1;
reg [31:0] grp_fu_528_p0;
reg [31:0] grp_fu_528_p1;
wire [31:0] grp_fu_537_p0;
wire [31:0] grp_fu_537_p1;
wire [0:0] grp_fu_609_p2;
wire [63:0] grp_fu_541_p0;
wire [63:0] grp_fu_544_p0;
wire [63:0] grp_fu_547_p0;
wire [63:0] grp_fu_550_p0;
wire [63:0] grp_fu_553_p0;
wire [31:0] grp_fu_557_p0;
wire [31:0] grp_fu_561_p0;
wire [31:0] grp_fu_564_p0;
wire [31:0] grp_fu_567_p0;
wire [31:0] grp_fu_570_p0;
wire [31:0] grp_fu_573_p0;
wire [31:0] grp_fu_576_p0;
wire [31:0] grp_fu_580_p0;
wire [31:0] grp_fu_583_p0;
wire [31:0] grp_fu_583_p1;
reg [31:0] grp_fu_589_p0;
wire [31:0] grp_fu_589_p1;
wire [31:0] grp_fu_596_p0;
wire [31:0] grp_fu_596_p1;
wire [31:0] grp_fu_600_p0;
wire [31:0] grp_fu_600_p1;
wire [31:0] grp_fu_604_p0;
wire [31:0] grp_fu_604_p1;
wire [31:0] grp_fu_609_p0;
wire [31:0] grp_fu_609_p1;
wire [31:0] grp_fu_613_p0;
wire [31:0] grp_fu_613_p1;
reg [63:0] grp_fu_618_p0;
reg [63:0] grp_fu_618_p1;
reg [63:0] grp_fu_623_p0;
reg [63:0] grp_fu_623_p1;
reg [63:0] grp_fu_629_p0;
reg [63:0] grp_fu_629_p1;
reg [63:0] grp_fu_635_p1;
wire [14:0] indvar30_cast_fu_716_p1;
wire [14:0] tmp1_fu_720_p2;
wire [14:0] tmp_9_fu_726_p2;
wire [14:0] tmp2_fu_736_p2;
wire [15:0] indvar34_cast_fu_758_p1;
wire [15:0] tmp_fu_762_p2;
wire [15:0] tmp_2_trn_cast_fu_802_p1;
wire [15:0] p_shl_fu_806_p2;
wire [15:0] a_addr6_fu_812_p2;
wire [7:0] indvar7_cast_fu_848_p1;
wire [7:0] ip_2_fu_852_p2;
wire [14:0] tmp_9_trn_cast_fu_891_p1;
wire [14:0] a_addr2_fu_895_p2;
wire [31:0] a_addr2_cast_fu_901_p1;
wire [31:0] a_addr3_fu_905_p2;
wire [29:0] tmp_5_fu_929_p4;
wire [7:0] indvar3_cast1_fu_963_p1;
wire [7:0] ip_3_fu_971_p2;
wire [7:0] indvar1_cast_fu_999_p1;
wire [7:0] tmp3_fu_1003_p2;
wire [8:0] tmp3_cast_fu_1009_p1;
wire [14:0] tmp_20_trn_cast_fu_1035_p1;
wire [14:0] a_addr_fu_1039_p2;
wire [31:0] a_addr_cast_fu_1045_p1;
wire [31:0] a_addr1_fu_1049_p2;
reg [1:0] grp_fu_509_opcode;
wire grp_fu_509_ce;
wire grp_fu_516_ce;
wire grp_fu_520_ce;
wire grp_fu_524_ce;
wire grp_fu_528_ce;
reg grp_fu_537_ce;
wire grp_fu_541_ce;
wire grp_fu_544_ce;
wire grp_fu_547_ce;
wire grp_fu_550_ce;
wire grp_fu_553_ce;
reg grp_fu_557_ce;
reg grp_fu_561_ce;
wire grp_fu_564_ce;
wire grp_fu_567_ce;
wire grp_fu_570_ce;
wire grp_fu_573_ce;
wire grp_fu_576_ce;
wire grp_fu_580_ce;
reg grp_fu_583_ce;
wire [4:0] grp_fu_583_opcode;
wire grp_fu_589_ce;
wire [4:0] grp_fu_589_opcode;
wire grp_fu_596_ce;
wire [4:0] grp_fu_596_opcode;
wire grp_fu_600_ce;
wire [4:0] grp_fu_600_opcode;
reg grp_fu_604_ce;
wire [4:0] grp_fu_604_opcode;
wire grp_fu_609_ce;
wire [4:0] grp_fu_609_opcode;
wire grp_fu_613_ce;
wire [4:0] grp_fu_613_opcode;
wire grp_fu_618_ce;
wire grp_fu_623_ce;
wire grp_fu_629_ce;
wire [63:0] grp_fu_635_p0;
wire grp_fu_635_ce;
reg [8:0] ap_NS_fsm;
wire [63:0] a_addr_2_reg_13340;
wire [63:0] b_addr_1_reg_15570;
wire [63:0] d_addr_1_reg_13000;
wire [63:0] z_addr_1_reg_13060;
wire [63:0] z_addr_2_reg_15620;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 9'b000000000;
parameter ap_ST_st1_fsm_1 = 9'b000000001;
parameter ap_ST_st2_fsm_2 = 9'b000000010;
parameter ap_ST_st3_fsm_3 = 9'b000000011;
parameter ap_ST_st4_fsm_4 = 9'b000000100;
parameter ap_ST_st5_fsm_5 = 9'b000000101;
parameter ap_ST_st6_fsm_6 = 9'b000000110;
parameter ap_ST_st7_fsm_7 = 9'b000000111;
parameter ap_ST_st8_fsm_8 = 9'b000001000;
parameter ap_ST_st9_fsm_9 = 9'b000001001;
parameter ap_ST_st10_fsm_10 = 9'b000001010;
parameter ap_ST_st11_fsm_11 = 9'b000001011;
parameter ap_ST_st12_fsm_12 = 9'b000001100;
parameter ap_ST_st13_fsm_13 = 9'b000001101;
parameter ap_ST_st14_fsm_14 = 9'b000001110;
parameter ap_ST_st15_fsm_15 = 9'b000001111;
parameter ap_ST_st16_fsm_16 = 9'b000010000;
parameter ap_ST_st17_fsm_17 = 9'b000010001;
parameter ap_ST_st18_fsm_18 = 9'b000010010;
parameter ap_ST_st19_fsm_19 = 9'b000010011;
parameter ap_ST_st20_fsm_20 = 9'b000010100;
parameter ap_ST_st21_fsm_21 = 9'b000010101;
parameter ap_ST_st22_fsm_22 = 9'b000010110;
parameter ap_ST_st23_fsm_23 = 9'b000010111;
parameter ap_ST_st24_fsm_24 = 9'b000011000;
parameter ap_ST_st25_fsm_25 = 9'b000011001;
parameter ap_ST_st26_fsm_26 = 9'b000011010;
parameter ap_ST_st27_fsm_27 = 9'b000011011;
parameter ap_ST_st28_fsm_28 = 9'b000011100;
parameter ap_ST_st29_fsm_29 = 9'b000011101;
parameter ap_ST_st30_fsm_30 = 9'b000011110;
parameter ap_ST_st31_fsm_31 = 9'b000011111;
parameter ap_ST_st32_fsm_32 = 9'b000100000;
parameter ap_ST_st33_fsm_33 = 9'b000100001;
parameter ap_ST_st34_fsm_34 = 9'b000100010;
parameter ap_ST_st35_fsm_35 = 9'b000100011;
parameter ap_ST_st36_fsm_36 = 9'b000100100;
parameter ap_ST_st37_fsm_37 = 9'b000100101;
parameter ap_ST_st38_fsm_38 = 9'b000100110;
parameter ap_ST_st39_fsm_39 = 9'b000100111;
parameter ap_ST_st40_fsm_40 = 9'b000101000;
parameter ap_ST_st41_fsm_41 = 9'b000101001;
parameter ap_ST_st42_fsm_42 = 9'b000101010;
parameter ap_ST_st43_fsm_43 = 9'b000101011;
parameter ap_ST_st44_fsm_44 = 9'b000101100;
parameter ap_ST_st45_fsm_45 = 9'b000101101;
parameter ap_ST_st46_fsm_46 = 9'b000101110;
parameter ap_ST_st47_fsm_47 = 9'b000101111;
parameter ap_ST_st48_fsm_48 = 9'b000110000;
parameter ap_ST_st49_fsm_49 = 9'b000110001;
parameter ap_ST_st50_fsm_50 = 9'b000110010;
parameter ap_ST_st51_fsm_51 = 9'b000110011;
parameter ap_ST_st52_fsm_52 = 9'b000110100;
parameter ap_ST_st53_fsm_53 = 9'b000110101;
parameter ap_ST_st54_fsm_54 = 9'b000110110;
parameter ap_ST_st55_fsm_55 = 9'b000110111;
parameter ap_ST_st56_fsm_56 = 9'b000111000;
parameter ap_ST_st57_fsm_57 = 9'b000111001;
parameter ap_ST_st58_fsm_58 = 9'b000111010;
parameter ap_ST_st59_fsm_59 = 9'b000111011;
parameter ap_ST_st60_fsm_60 = 9'b000111100;
parameter ap_ST_st61_fsm_61 = 9'b000111101;
parameter ap_ST_st62_fsm_62 = 9'b000111110;
parameter ap_ST_st63_fsm_63 = 9'b000111111;
parameter ap_ST_st64_fsm_64 = 9'b001000000;
parameter ap_ST_st65_fsm_65 = 9'b001000001;
parameter ap_ST_st66_fsm_66 = 9'b001000010;
parameter ap_ST_st67_fsm_67 = 9'b001000011;
parameter ap_ST_st68_fsm_68 = 9'b001000100;
parameter ap_ST_st69_fsm_69 = 9'b001000101;
parameter ap_ST_st70_fsm_70 = 9'b001000110;
parameter ap_ST_st71_fsm_71 = 9'b001000111;
parameter ap_ST_st72_fsm_72 = 9'b001001000;
parameter ap_ST_st73_fsm_73 = 9'b001001001;
parameter ap_ST_st74_fsm_74 = 9'b001001010;
parameter ap_ST_st75_fsm_75 = 9'b001001011;
parameter ap_ST_st76_fsm_76 = 9'b001001100;
parameter ap_ST_st77_fsm_77 = 9'b001001101;
parameter ap_ST_st78_fsm_78 = 9'b001001110;
parameter ap_ST_st79_fsm_79 = 9'b001001111;
parameter ap_ST_st80_fsm_80 = 9'b001010000;
parameter ap_ST_st81_fsm_81 = 9'b001010001;
parameter ap_ST_st82_fsm_82 = 9'b001010010;
parameter ap_ST_st83_fsm_83 = 9'b001010011;
parameter ap_ST_st84_fsm_84 = 9'b001010100;
parameter ap_ST_st85_fsm_85 = 9'b001010101;
parameter ap_ST_st86_fsm_86 = 9'b001010110;
parameter ap_ST_st87_fsm_87 = 9'b001010111;
parameter ap_ST_st88_fsm_88 = 9'b001011000;
parameter ap_ST_st89_fsm_89 = 9'b001011001;
parameter ap_ST_st90_fsm_90 = 9'b001011010;
parameter ap_ST_st91_fsm_91 = 9'b001011011;
parameter ap_ST_st92_fsm_92 = 9'b001011100;
parameter ap_ST_st93_fsm_93 = 9'b001011101;
parameter ap_ST_st94_fsm_94 = 9'b001011110;
parameter ap_ST_st95_fsm_95 = 9'b001011111;
parameter ap_ST_st96_fsm_96 = 9'b001100000;
parameter ap_ST_st97_fsm_97 = 9'b001100001;
parameter ap_ST_st98_fsm_98 = 9'b001100010;
parameter ap_ST_st99_fsm_99 = 9'b001100011;
parameter ap_ST_st100_fsm_100 = 9'b001100100;
parameter ap_ST_st101_fsm_101 = 9'b001100101;
parameter ap_ST_st102_fsm_102 = 9'b001100110;
parameter ap_ST_st103_fsm_103 = 9'b001100111;
parameter ap_ST_st104_fsm_104 = 9'b001101000;
parameter ap_ST_st105_fsm_105 = 9'b001101001;
parameter ap_ST_st106_fsm_106 = 9'b001101010;
parameter ap_ST_st107_fsm_107 = 9'b001101011;
parameter ap_ST_st108_fsm_108 = 9'b001101100;
parameter ap_ST_st109_fsm_109 = 9'b001101101;
parameter ap_ST_st110_fsm_110 = 9'b001101110;
parameter ap_ST_st111_fsm_111 = 9'b001101111;
parameter ap_ST_st112_fsm_112 = 9'b001110000;
parameter ap_ST_st113_fsm_113 = 9'b001110001;
parameter ap_ST_st114_fsm_114 = 9'b001110010;
parameter ap_ST_st115_fsm_115 = 9'b001110011;
parameter ap_ST_st116_fsm_116 = 9'b001110100;
parameter ap_ST_st117_fsm_117 = 9'b001110101;
parameter ap_ST_st118_fsm_118 = 9'b001110110;
parameter ap_ST_st119_fsm_119 = 9'b001110111;
parameter ap_ST_st120_fsm_120 = 9'b001111000;
parameter ap_ST_st121_fsm_121 = 9'b001111001;
parameter ap_ST_st122_fsm_122 = 9'b001111010;
parameter ap_ST_st123_fsm_123 = 9'b001111011;
parameter ap_ST_st124_fsm_124 = 9'b001111100;
parameter ap_ST_st125_fsm_125 = 9'b001111101;
parameter ap_ST_st126_fsm_126 = 9'b001111110;
parameter ap_ST_st127_fsm_127 = 9'b001111111;
parameter ap_ST_st128_fsm_128 = 9'b010000000;
parameter ap_ST_st129_fsm_129 = 9'b010000001;
parameter ap_ST_st130_fsm_130 = 9'b010000010;
parameter ap_ST_st131_fsm_131 = 9'b010000011;
parameter ap_ST_st132_fsm_132 = 9'b010000100;
parameter ap_ST_st133_fsm_133 = 9'b010000101;
parameter ap_ST_st134_fsm_134 = 9'b010000110;
parameter ap_ST_st135_fsm_135 = 9'b010000111;
parameter ap_ST_st136_fsm_136 = 9'b010001000;
parameter ap_ST_st137_fsm_137 = 9'b010001001;
parameter ap_ST_st138_fsm_138 = 9'b010001010;
parameter ap_ST_st139_fsm_139 = 9'b010001011;
parameter ap_ST_st140_fsm_140 = 9'b010001100;
parameter ap_ST_st141_fsm_141 = 9'b010001101;
parameter ap_ST_st142_fsm_142 = 9'b010001110;
parameter ap_ST_st143_fsm_143 = 9'b010001111;
parameter ap_ST_st144_fsm_144 = 9'b010010000;
parameter ap_ST_st145_fsm_145 = 9'b010010001;
parameter ap_ST_st146_fsm_146 = 9'b010010010;
parameter ap_ST_st147_fsm_147 = 9'b010010011;
parameter ap_ST_st148_fsm_148 = 9'b010010100;
parameter ap_ST_st149_fsm_149 = 9'b010010101;
parameter ap_ST_st150_fsm_150 = 9'b010010110;
parameter ap_ST_st151_fsm_151 = 9'b010010111;
parameter ap_ST_st152_fsm_152 = 9'b010011000;
parameter ap_ST_st153_fsm_153 = 9'b010011001;
parameter ap_ST_st154_fsm_154 = 9'b010011010;
parameter ap_ST_st155_fsm_155 = 9'b010011011;
parameter ap_ST_st156_fsm_156 = 9'b010011100;
parameter ap_ST_st157_fsm_157 = 9'b010011101;
parameter ap_ST_st158_fsm_158 = 9'b010011110;
parameter ap_ST_st159_fsm_159 = 9'b010011111;
parameter ap_ST_st160_fsm_160 = 9'b010100000;
parameter ap_ST_st161_fsm_161 = 9'b010100001;
parameter ap_ST_st162_fsm_162 = 9'b010100010;
parameter ap_ST_st163_fsm_163 = 9'b010100011;
parameter ap_ST_st164_fsm_164 = 9'b010100100;
parameter ap_ST_st165_fsm_165 = 9'b010100101;
parameter ap_ST_st166_fsm_166 = 9'b010100110;
parameter ap_ST_st167_fsm_167 = 9'b010100111;
parameter ap_ST_st168_fsm_168 = 9'b010101000;
parameter ap_ST_st169_fsm_169 = 9'b010101001;
parameter ap_ST_st170_fsm_170 = 9'b010101010;
parameter ap_ST_st171_fsm_171 = 9'b010101011;
parameter ap_ST_st172_fsm_172 = 9'b010101100;
parameter ap_ST_st173_fsm_173 = 9'b010101101;
parameter ap_ST_st174_fsm_174 = 9'b010101110;
parameter ap_ST_st175_fsm_175 = 9'b010101111;
parameter ap_ST_st176_fsm_176 = 9'b010110000;
parameter ap_ST_st177_fsm_177 = 9'b010110001;
parameter ap_ST_st178_fsm_178 = 9'b010110010;
parameter ap_ST_st179_fsm_179 = 9'b010110011;
parameter ap_ST_st180_fsm_180 = 9'b010110100;
parameter ap_ST_st181_fsm_181 = 9'b010110101;
parameter ap_ST_st182_fsm_182 = 9'b010110110;
parameter ap_ST_st183_fsm_183 = 9'b010110111;
parameter ap_ST_st184_fsm_184 = 9'b010111000;
parameter ap_ST_st185_fsm_185 = 9'b010111001;
parameter ap_ST_st186_fsm_186 = 9'b010111010;
parameter ap_ST_st187_fsm_187 = 9'b010111011;
parameter ap_ST_st188_fsm_188 = 9'b010111100;
parameter ap_ST_st189_fsm_189 = 9'b010111101;
parameter ap_ST_st190_fsm_190 = 9'b010111110;
parameter ap_ST_st191_fsm_191 = 9'b010111111;
parameter ap_ST_st192_fsm_192 = 9'b011000000;
parameter ap_ST_st193_fsm_193 = 9'b011000001;
parameter ap_ST_st194_fsm_194 = 9'b011000010;
parameter ap_ST_st195_fsm_195 = 9'b011000011;
parameter ap_ST_st196_fsm_196 = 9'b011000100;
parameter ap_ST_st197_fsm_197 = 9'b011000101;
parameter ap_ST_st198_fsm_198 = 9'b011000110;
parameter ap_ST_st199_fsm_199 = 9'b011000111;
parameter ap_ST_st200_fsm_200 = 9'b011001000;
parameter ap_ST_st201_fsm_201 = 9'b011001001;
parameter ap_ST_st202_fsm_202 = 9'b011001010;
parameter ap_ST_st203_fsm_203 = 9'b011001011;
parameter ap_ST_st204_fsm_204 = 9'b011001100;
parameter ap_ST_st205_fsm_205 = 9'b011001101;
parameter ap_ST_st206_fsm_206 = 9'b011001110;
parameter ap_ST_st207_fsm_207 = 9'b011001111;
parameter ap_ST_st208_fsm_208 = 9'b011010000;
parameter ap_ST_st209_fsm_209 = 9'b011010001;
parameter ap_ST_st210_fsm_210 = 9'b011010010;
parameter ap_ST_st211_fsm_211 = 9'b011010011;
parameter ap_ST_st212_fsm_212 = 9'b011010100;
parameter ap_ST_st213_fsm_213 = 9'b011010101;
parameter ap_ST_st214_fsm_214 = 9'b011010110;
parameter ap_ST_st215_fsm_215 = 9'b011010111;
parameter ap_ST_st216_fsm_216 = 9'b011011000;
parameter ap_ST_st217_fsm_217 = 9'b011011001;
parameter ap_ST_st218_fsm_218 = 9'b011011010;
parameter ap_ST_st219_fsm_219 = 9'b011011011;
parameter ap_ST_st220_fsm_220 = 9'b011011100;
parameter ap_ST_st221_fsm_221 = 9'b011011101;
parameter ap_ST_st222_fsm_222 = 9'b011011110;
parameter ap_ST_st223_fsm_223 = 9'b011011111;
parameter ap_ST_st224_fsm_224 = 9'b011100000;
parameter ap_ST_st225_fsm_225 = 9'b011100001;
parameter ap_ST_st226_fsm_226 = 9'b011100010;
parameter ap_ST_st227_fsm_227 = 9'b011100011;
parameter ap_ST_st228_fsm_228 = 9'b011100100;
parameter ap_ST_st229_fsm_229 = 9'b011100101;
parameter ap_ST_st230_fsm_230 = 9'b011100110;
parameter ap_ST_st231_fsm_231 = 9'b011100111;
parameter ap_ST_st232_fsm_232 = 9'b011101000;
parameter ap_ST_st233_fsm_233 = 9'b011101001;
parameter ap_ST_st234_fsm_234 = 9'b011101010;
parameter ap_ST_st235_fsm_235 = 9'b011101011;
parameter ap_ST_st236_fsm_236 = 9'b011101100;
parameter ap_ST_st237_fsm_237 = 9'b011101101;
parameter ap_ST_st238_fsm_238 = 9'b011101110;
parameter ap_ST_st239_fsm_239 = 9'b011101111;
parameter ap_ST_st240_fsm_240 = 9'b011110000;
parameter ap_ST_st241_fsm_241 = 9'b011110001;
parameter ap_ST_st242_fsm_242 = 9'b011110010;
parameter ap_ST_st243_fsm_243 = 9'b011110011;
parameter ap_ST_st244_fsm_244 = 9'b011110100;
parameter ap_ST_st245_fsm_245 = 9'b011110101;
parameter ap_ST_st246_fsm_246 = 9'b011110110;
parameter ap_ST_st247_fsm_247 = 9'b011110111;
parameter ap_ST_st248_fsm_248 = 9'b011111000;
parameter ap_ST_st249_fsm_249 = 9'b011111001;
parameter ap_ST_st250_fsm_250 = 9'b011111010;
parameter ap_ST_st251_fsm_251 = 9'b011111011;
parameter ap_ST_st252_fsm_252 = 9'b011111100;
parameter ap_ST_st253_fsm_253 = 9'b011111101;
parameter ap_ST_st254_fsm_254 = 9'b011111110;
parameter ap_ST_st255_fsm_255 = 9'b011111111;
parameter ap_ST_st256_fsm_256 = 9'b100000000;
parameter ap_ST_st257_fsm_257 = 9'b100000001;
parameter ap_ST_st258_fsm_258 = 9'b100000010;
parameter ap_ST_st259_fsm_259 = 9'b100000011;
parameter ap_ST_st260_fsm_260 = 9'b100000100;
parameter ap_ST_st261_fsm_261 = 9'b100000101;
parameter ap_ST_st262_fsm_262 = 9'b100000110;
parameter ap_ST_st263_fsm_263 = 9'b100000111;
parameter ap_ST_st264_fsm_264 = 9'b100001000;
parameter ap_ST_st265_fsm_265 = 9'b100001001;
parameter ap_ST_st266_fsm_266 = 9'b100001010;
parameter ap_ST_st267_fsm_267 = 9'b100001011;
parameter ap_ST_st268_fsm_268 = 9'b100001100;
parameter ap_ST_st269_fsm_269 = 9'b100001101;
parameter ap_ST_st270_fsm_270 = 9'b100001110;
parameter ap_ST_st271_fsm_271 = 9'b100001111;
parameter ap_ST_st272_fsm_272 = 9'b100010000;
parameter ap_ST_st273_fsm_273 = 9'b100010001;
parameter ap_ST_st274_fsm_274 = 9'b100010010;
parameter ap_ST_st275_fsm_275 = 9'b100010011;
parameter ap_ST_st276_fsm_276 = 9'b100010100;
parameter ap_ST_st277_fsm_277 = 9'b100010101;
parameter ap_ST_st278_fsm_278 = 9'b100010110;
parameter ap_ST_st279_fsm_279 = 9'b100010111;
parameter ap_ST_st280_fsm_280 = 9'b100011000;
parameter ap_ST_st281_fsm_281 = 9'b100011001;
parameter ap_ST_st282_fsm_282 = 9'b100011010;
parameter ap_ST_st283_fsm_283 = 9'b100011011;
parameter ap_ST_st284_fsm_284 = 9'b100011100;
parameter ap_ST_st285_fsm_285 = 9'b100011101;
parameter ap_ST_st286_fsm_286 = 9'b100011110;
parameter ap_ST_st287_fsm_287 = 9'b100011111;
parameter ap_ST_st288_fsm_288 = 9'b100100000;
parameter ap_ST_st289_fsm_289 = 9'b100100001;
parameter ap_ST_st290_fsm_290 = 9'b100100010;
parameter ap_ST_st291_fsm_291 = 9'b100100011;
parameter ap_ST_st292_fsm_292 = 9'b100100100;
parameter ap_ST_st293_fsm_293 = 9'b100100101;
parameter ap_ST_st294_fsm_294 = 9'b100100110;
parameter ap_ST_st295_fsm_295 = 9'b100100111;
parameter ap_ST_st296_fsm_296 = 9'b100101000;
parameter ap_ST_st297_fsm_297 = 9'b100101001;
parameter ap_ST_st298_fsm_298 = 9'b100101010;
parameter ap_ST_st299_fsm_299 = 9'b100101011;
parameter ap_ST_st300_fsm_300 = 9'b100101100;
parameter ap_ST_st301_fsm_301 = 9'b100101101;
parameter ap_ST_st302_fsm_302 = 9'b100101110;
parameter ap_ST_st303_fsm_303 = 9'b100101111;
parameter ap_ST_st304_fsm_304 = 9'b100110000;
parameter ap_ST_st305_fsm_305 = 9'b100110001;
parameter ap_ST_st306_fsm_306 = 9'b100110010;
parameter ap_ST_st307_fsm_307 = 9'b100110011;
parameter ap_ST_st308_fsm_308 = 9'b100110100;
parameter ap_ST_st309_fsm_309 = 9'b100110101;
parameter ap_ST_st310_fsm_310 = 9'b100110110;
parameter ap_ST_st311_fsm_311 = 9'b100110111;
parameter ap_ST_st312_fsm_312 = 9'b100111000;
parameter ap_ST_st313_fsm_313 = 9'b100111001;
parameter ap_ST_st314_fsm_314 = 9'b100111010;
parameter ap_ST_st315_fsm_315 = 9'b100111011;
parameter ap_ST_st316_fsm_316 = 9'b100111100;
parameter ap_ST_st317_fsm_317 = 9'b100111101;
parameter ap_ST_st318_fsm_318 = 9'b100111110;
parameter ap_ST_st319_fsm_319 = 9'b100111111;
parameter ap_ST_st320_fsm_320 = 9'b101000000;
parameter ap_ST_st321_fsm_321 = 9'b101000001;
parameter ap_ST_st322_fsm_322 = 9'b101000010;
parameter ap_ST_st323_fsm_323 = 9'b101000011;
parameter ap_ST_st324_fsm_324 = 9'b101000100;
parameter ap_ST_st325_fsm_325 = 9'b101000101;
parameter ap_ST_st326_fsm_326 = 9'b101000110;
parameter ap_ST_st327_fsm_327 = 9'b101000111;
parameter ap_ST_st328_fsm_328 = 9'b101001000;
parameter ap_ST_st329_fsm_329 = 9'b101001001;
parameter ap_ST_st330_fsm_330 = 9'b101001010;
parameter ap_ST_st331_fsm_331 = 9'b101001011;
parameter ap_ST_st332_fsm_332 = 9'b101001100;
parameter ap_ST_st333_fsm_333 = 9'b101001101;
parameter ap_ST_st334_fsm_334 = 9'b101001110;
parameter ap_ST_st335_fsm_335 = 9'b101001111;
parameter ap_ST_st336_fsm_336 = 9'b101010000;
parameter ap_ST_st337_fsm_337 = 9'b101010001;
parameter ap_ST_st338_fsm_338 = 9'b101010010;
parameter ap_ST_st339_fsm_339 = 9'b101010011;
parameter ap_ST_st340_fsm_340 = 9'b101010100;
parameter ap_ST_st341_fsm_341 = 9'b101010101;
parameter ap_ST_st342_fsm_342 = 9'b101010110;
parameter ap_ST_st343_fsm_343 = 9'b101010111;
parameter ap_ST_st344_fsm_344 = 9'b101011000;
parameter ap_ST_st345_fsm_345 = 9'b101011001;
parameter ap_ST_st346_fsm_346 = 9'b101011010;
parameter ap_ST_st347_fsm_347 = 9'b101011011;
parameter ap_ST_st348_fsm_348 = 9'b101011100;
parameter ap_ST_st349_fsm_349 = 9'b101011101;
parameter ap_ST_st350_fsm_350 = 9'b101011110;
parameter ap_ST_st351_fsm_351 = 9'b101011111;
parameter ap_ST_st352_fsm_352 = 9'b101100000;
parameter ap_ST_st353_fsm_353 = 9'b101100001;
parameter ap_ST_st354_fsm_354 = 9'b101100010;
parameter ap_ST_st355_fsm_355 = 9'b101100011;
parameter ap_ST_st356_fsm_356 = 9'b101100100;
parameter ap_ST_st357_fsm_357 = 9'b101100101;
parameter ap_ST_st358_fsm_358 = 9'b101100110;
parameter ap_ST_st359_fsm_359 = 9'b101100111;
parameter ap_ST_st360_fsm_360 = 9'b101101000;
parameter ap_ST_st361_fsm_361 = 9'b101101001;
parameter ap_ST_st362_fsm_362 = 9'b101101010;
parameter ap_ST_st363_fsm_363 = 9'b101101011;
parameter ap_ST_st364_fsm_364 = 9'b101101100;
parameter ap_ST_st365_fsm_365 = 9'b101101101;
parameter ap_ST_st366_fsm_366 = 9'b101101110;
parameter ap_ST_st367_fsm_367 = 9'b101101111;
parameter ap_ST_st368_fsm_368 = 9'b101110000;
parameter ap_ST_st369_fsm_369 = 9'b101110001;
parameter ap_ST_st370_fsm_370 = 9'b101110010;
parameter ap_ST_st371_fsm_371 = 9'b101110011;
parameter ap_ST_st372_fsm_372 = 9'b101110100;
parameter ap_ST_st373_fsm_373 = 9'b101110101;
parameter ap_ST_st374_fsm_374 = 9'b101110110;
parameter ap_ST_st375_fsm_375 = 9'b101110111;
parameter ap_ST_st376_fsm_376 = 9'b101111000;
parameter ap_ST_st377_fsm_377 = 9'b101111001;
parameter ap_ST_st378_fsm_378 = 9'b101111010;
parameter ap_ST_st379_fsm_379 = 9'b101111011;
parameter ap_ST_st380_fsm_380 = 9'b101111100;
parameter ap_ST_st381_fsm_381 = 9'b101111101;
parameter ap_ST_st382_fsm_382 = 9'b101111110;
parameter ap_ST_st383_fsm_383 = 9'b101111111;
parameter ap_ST_st384_fsm_384 = 9'b110000000;
parameter ap_ST_st385_fsm_385 = 9'b110000001;
parameter ap_ST_st386_fsm_386 = 9'b110000010;
parameter ap_ST_st387_fsm_387 = 9'b110000011;
parameter ap_ST_st388_fsm_388 = 9'b110000100;
parameter ap_ST_st389_fsm_389 = 9'b110000101;
parameter ap_ST_st390_fsm_390 = 9'b110000110;
parameter ap_ST_st391_fsm_391 = 9'b110000111;
parameter ap_ST_st392_fsm_392 = 9'b110001000;
parameter ap_ST_st393_fsm_393 = 9'b110001001;
parameter ap_ST_st394_fsm_394 = 9'b110001010;
parameter ap_ST_st395_fsm_395 = 9'b110001011;
parameter ap_ST_st396_fsm_396 = 9'b110001100;
parameter ap_ST_st397_fsm_397 = 9'b110001101;
parameter ap_ST_st398_fsm_398 = 9'b110001110;
parameter ap_ST_st399_fsm_399 = 9'b110001111;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_1F = 32'b00000000000000000000000000011111;
parameter ap_const_lv32_3F800000 = 32'b00111111100000000000000000000000;
parameter ap_const_lv32_80000000 = 32'b10000000000000000000000000000000;
parameter ap_const_lv32_42C80000 = 32'b01000010110010000000000000000000;
parameter ap_const_lv64_3FF0000000000000 = 64'b0011111111110000000000000000000000000000000000000000000000000000;
parameter ap_const_lv64_3FC999999999999A = 64'b0011111111001001100110011001100110011001100110011001100110011010;
parameter ap_const_lv64_3FE0000000000000 = 64'b0011111111100000000000000000000000000000000000000000000000000000;
parameter ap_const_lv64_40D0000000000000 = 64'b0100000011010000000000000000000000000000000000000000000000000000;
parameter ap_const_lv15_7 = 15'b000000000000111;
parameter ap_const_lv15_101 = 15'b000000100000001;
parameter ap_const_lv15_81 = 15'b000000010000001;
parameter ap_const_lv8_80 = 8'b10000000;
parameter ap_const_lv64_1 = 64'b0000000000000000000000000000000000000000000000000000000000000001;
parameter ap_const_lv16_7 = 16'b0000000000000111;
parameter ap_const_lv32_33 = 32'b00000000000000000000000000110011;
parameter ap_const_lv7_7F = 7'b1111111;
parameter ap_const_lv7_1 = 7'b0000001;
parameter ap_const_lv32_2 = 32'b00000000000000000000000000000010;
parameter ap_const_lv30_1 = 30'b000000000000000000000000000001;
parameter ap_const_lv32_5 = 32'b00000000000000000000000000000101;
parameter ap_const_lv8_2 = 8'b00000010;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_const_lv5_1 = 5'b00001;
parameter ap_const_lv5_4 = 5'b00100;
parameter ap_const_lv5_E = 5'b01110;
parameter ap_const_lv5_2 = 5'b00010;
parameter ap_true = 1'b1;
jacob_b #(
.DataWidth( 32 ),
.AddressRange( 128 ),
.AddressWidth( 7 ))
b_U(
.clk( ap_clk ),
.address0( b_address0 ),
.ce0( b_ce0 ),
.we0( b_we0 ),
.d0( b_d0 ),
.q0( b_q0 )
);
jacob_z #(
.DataWidth( 32 ),
.AddressRange( 128 ),
.AddressWidth( 7 ))
z_U(
.clk( ap_clk ),
.address0( z_address0 ),
.ce0( z_ce0 ),
.we0( z_we0 ),
.d0( z_d0 ),
.q0( z_q0 ),
.address1( z_address1 ),
.ce1( z_ce1 ),
.we1( z_we1 ),
.d1( z_d1 ),
.q1( z_q1 )
);
do_rotate grp_do_rotate_fu_497(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_do_rotate_fu_497_ap_start ),
.ap_done( grp_do_rotate_fu_497_ap_done ),
.ap_idle( grp_do_rotate_fu_497_ap_idle ),
.a_address0( grp_do_rotate_fu_497_a_address0 ),
.a_ce0( grp_do_rotate_fu_497_a_ce0 ),
.a_we0( grp_do_rotate_fu_497_a_we0 ),
.a_d0( grp_do_rotate_fu_497_a_d0 ),
.a_q0( grp_do_rotate_fu_497_a_q0 ),
.a_address1( grp_do_rotate_fu_497_a_address1 ),
.a_ce1( grp_do_rotate_fu_497_a_ce1 ),
.a_we1( grp_do_rotate_fu_497_a_we1 ),
.a_d1( grp_do_rotate_fu_497_a_d1 ),
.a_q1( grp_do_rotate_fu_497_a_q1 ),
.v_address0( grp_do_rotate_fu_497_v_address0 ),
.v_ce0( grp_do_rotate_fu_497_v_ce0 ),
.v_we0( grp_do_rotate_fu_497_v_we0 ),
.v_d0( grp_do_rotate_fu_497_v_d0 ),
.v_q0( grp_do_rotate_fu_497_v_q0 ),
.v_address1( grp_do_rotate_fu_497_v_address1 ),
.v_ce1( grp_do_rotate_fu_497_v_ce1 ),
.v_we1( grp_do_rotate_fu_497_v_we1 ),
.v_d1( grp_do_rotate_fu_497_v_d1 ),
.v_q1( grp_do_rotate_fu_497_v_q1 ),
.s( grp_do_rotate_fu_497_s ),
.tau( grp_do_rotate_fu_497_tau ),
.ip( grp_do_rotate_fu_497_ip ),
.iq( grp_do_rotate_fu_497_iq )
);
jacob_grp_fu_509_ACMP_faddfsub_11 #(
.ID( 11 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_509_ACMP_faddfsub_11_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_509_p0 ),
.din1( grp_fu_509_p1 ),
.opcode( grp_fu_509_opcode ),
.ce( grp_fu_509_ce ),
.dout( grp_fu_509_p2 )
);
jacob_grp_fu_516_ACMP_fadd_12 #(
.ID( 12 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_516_ACMP_fadd_12_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_516_p0 ),
.din1( grp_fu_516_p1 ),
.ce( grp_fu_516_ce ),
.dout( grp_fu_516_p2 )
);
jacob_grp_fu_520_ACMP_fsub_13 #(
.ID( 13 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_520_ACMP_fsub_13_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_520_p0 ),
.din1( grp_fu_520_p1 ),
.ce( grp_fu_520_ce ),
.dout( grp_fu_520_p2 )
);
jacob_grp_fu_524_ACMP_fadd_14 #(
.ID( 14 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_524_ACMP_fadd_14_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_524_p0 ),
.din1( grp_fu_524_p1 ),
.ce( grp_fu_524_ce ),
.dout( grp_fu_524_p2 )
);
jacob_grp_fu_528_ACMP_fmul_15 #(
.ID( 15 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_528_ACMP_fmul_15_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_528_p0 ),
.din1( grp_fu_528_p1 ),
.ce( grp_fu_528_ce ),
.dout( grp_fu_528_p2 )
);
jacob_grp_fu_537_ACMP_fdiv_16 #(
.ID( 16 ),
.NUM_STAGE( 12 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_537_ACMP_fdiv_16_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_537_p0 ),
.din1( grp_fu_537_p1 ),
.ce( grp_fu_537_ce ),
.dout( grp_fu_537_p2 )
);
jacob_grp_fu_541_ACMP_fptrunc_17 #(
.ID( 17 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_541_ACMP_fptrunc_17_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_541_p0 ),
.ce( grp_fu_541_ce ),
.dout( grp_fu_541_p1 )
);
jacob_grp_fu_544_ACMP_fptrunc_18 #(
.ID( 18 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_544_ACMP_fptrunc_18_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_544_p0 ),
.ce( grp_fu_544_ce ),
.dout( grp_fu_544_p1 )
);
jacob_grp_fu_547_ACMP_fptrunc_19 #(
.ID( 19 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_547_ACMP_fptrunc_19_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_547_p0 ),
.ce( grp_fu_547_ce ),
.dout( grp_fu_547_p1 )
);
jacob_grp_fu_550_ACMP_fptrunc_20 #(
.ID( 20 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_550_ACMP_fptrunc_20_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_550_p0 ),
.ce( grp_fu_550_ce ),
.dout( grp_fu_550_p1 )
);
jacob_grp_fu_553_ACMP_fptrunc_21 #(
.ID( 21 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
jacob_grp_fu_553_ACMP_fptrunc_21_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_553_p0 ),
.ce( grp_fu_553_ce ),
.dout( grp_fu_553_p1 )
);
jacob_grp_fu_557_ACMP_fpext_22 #(
.ID( 22 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_557_ACMP_fpext_22_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_557_p0 ),
.ce( grp_fu_557_ce ),
.dout( grp_fu_557_p1 )
);
jacob_grp_fu_561_ACMP_fpext_23 #(
.ID( 23 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_561_ACMP_fpext_23_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_561_p0 ),
.ce( grp_fu_561_ce ),
.dout( grp_fu_561_p1 )
);
jacob_grp_fu_564_ACMP_fpext_24 #(
.ID( 24 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_564_ACMP_fpext_24_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_564_p0 ),
.ce( grp_fu_564_ce ),
.dout( grp_fu_564_p1 )
);
jacob_grp_fu_567_ACMP_fpext_25 #(
.ID( 25 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_567_ACMP_fpext_25_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_567_p0 ),
.ce( grp_fu_567_ce ),
.dout( grp_fu_567_p1 )
);
jacob_grp_fu_570_ACMP_fpext_26 #(
.ID( 26 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_570_ACMP_fpext_26_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_570_p0 ),
.ce( grp_fu_570_ce ),
.dout( grp_fu_570_p1 )
);
jacob_grp_fu_573_ACMP_fpext_27 #(
.ID( 27 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_573_ACMP_fpext_27_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_573_p0 ),
.ce( grp_fu_573_ce ),
.dout( grp_fu_573_p1 )
);
jacob_grp_fu_576_ACMP_fpext_28 #(
.ID( 28 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_576_ACMP_fpext_28_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_576_p0 ),
.ce( grp_fu_576_ce ),
.dout( grp_fu_576_p1 )
);
jacob_grp_fu_580_ACMP_fpext_29 #(
.ID( 29 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_580_ACMP_fpext_29_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_580_p0 ),
.ce( grp_fu_580_ce ),
.dout( grp_fu_580_p1 )
);
jacob_grp_fu_583_ACMP_fcmp_30 #(
.ID( 30 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_583_ACMP_fcmp_30_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_583_p0 ),
.din1( grp_fu_583_p1 ),
.ce( grp_fu_583_ce ),
.opcode( grp_fu_583_opcode ),
.dout( grp_fu_583_p2 )
);
jacob_grp_fu_589_ACMP_fcmp_31 #(
.ID( 31 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_589_ACMP_fcmp_31_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_589_p0 ),
.din1( grp_fu_589_p1 ),
.ce( grp_fu_589_ce ),
.opcode( grp_fu_589_opcode ),
.dout( grp_fu_589_p2 )
);
jacob_grp_fu_596_ACMP_fcmp_32 #(
.ID( 32 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_596_ACMP_fcmp_32_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_596_p0 ),
.din1( grp_fu_596_p1 ),
.ce( grp_fu_596_ce ),
.opcode( grp_fu_596_opcode ),
.dout( grp_fu_596_p2 )
);
jacob_grp_fu_600_ACMP_fcmp_33 #(
.ID( 33 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_600_ACMP_fcmp_33_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_600_p0 ),
.din1( grp_fu_600_p1 ),
.ce( grp_fu_600_ce ),
.opcode( grp_fu_600_opcode ),
.dout( grp_fu_600_p2 )
);
jacob_grp_fu_604_ACMP_fcmp_34 #(
.ID( 34 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_604_ACMP_fcmp_34_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_604_p0 ),
.din1( grp_fu_604_p1 ),
.ce( grp_fu_604_ce ),
.opcode( grp_fu_604_opcode ),
.dout( grp_fu_604_p2 )
);
jacob_grp_fu_609_ACMP_fcmp_35 #(
.ID( 35 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_609_ACMP_fcmp_35_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_609_p0 ),
.din1( grp_fu_609_p1 ),
.ce( grp_fu_609_ce ),
.opcode( grp_fu_609_opcode ),
.dout( grp_fu_609_p2 )
);
jacob_grp_fu_613_ACMP_fcmp_36 #(
.ID( 36 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
jacob_grp_fu_613_ACMP_fcmp_36_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_613_p0 ),
.din1( grp_fu_613_p1 ),
.ce( grp_fu_613_ce ),
.opcode( grp_fu_613_opcode ),
.dout( grp_fu_613_p2 )
);
jacob_grp_fu_618_ACMP_dadd_37 #(
.ID( 37 ),
.NUM_STAGE( 6 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_618_ACMP_dadd_37_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_618_p0 ),
.din1( grp_fu_618_p1 ),
.ce( grp_fu_618_ce ),
.dout( grp_fu_618_p2 )
);
jacob_grp_fu_623_ACMP_dmul_38 #(
.ID( 38 ),
.NUM_STAGE( 7 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_623_ACMP_dmul_38_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_623_p0 ),
.din1( grp_fu_623_p1 ),
.ce( grp_fu_623_ce ),
.dout( grp_fu_623_p2 )
);
jacob_grp_fu_629_ACMP_ddiv_39 #(
.ID( 39 ),
.NUM_STAGE( 34 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_629_ACMP_ddiv_39_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_629_p0 ),
.din1( grp_fu_629_p1 ),
.ce( grp_fu_629_ce ),
.dout( grp_fu_629_p2 )
);
jacob_grp_fu_635_ACMP_dsqrt_40 #(
.ID( 40 ),
.NUM_STAGE( 30 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
jacob_grp_fu_635_ACMP_dsqrt_40_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_635_p0 ),
.din1( grp_fu_635_p1 ),
.ce( grp_fu_635_ce ),
.dout( grp_fu_635_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
if (tmp_i1_reg_1344) begin
UnifiedRetVal_i1_reg_1349 <= reg_649;
end else begin
UnifiedRetVal_i1_reg_1349 <= reg_640;
end
end
if ((ap_ST_st85_fsm_85 == ap_CS_fsm)) begin
if (tmp_i2_reg_1362) begin
UnifiedRetVal_i2_reg_1367 <= reg_649;
end else begin
UnifiedRetVal_i2_reg_1367 <= reg_684;
end
end
if ((ap_ST_st99_fsm_99 == ap_CS_fsm)) begin
if (tmp_i3_reg_1382) begin
UnifiedRetVal_i3_reg_1387 <= reg_649;
end else begin
UnifiedRetVal_i3_reg_1387 <= reg_684;
end
end
if ((ap_ST_st119_fsm_119 == ap_CS_fsm)) begin
if (tmp_i4_reg_1416) begin
UnifiedRetVal_i4_reg_1421 <= reg_692;
end else begin
UnifiedRetVal_i4_reg_1421 <= reg_649;
end
end
if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
if (tmp_i_reg_1236) begin
UnifiedRetVal_i_reg_1241 <= reg_649;
end else begin
UnifiedRetVal_i_reg_1241 <= reg_640;
end
end
if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
a_addr_2_reg_1334 <= a_addr_2_reg_13340;
end
if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
b_addr_1_reg_1557 <= b_addr_1_reg_15570;
end
if ((ap_ST_st393_fsm_393 == ap_CS_fsm)) begin
b_load_reg_1577 <= b_q0;
end
if ((ap_ST_st347_fsm_347 == ap_CS_fsm)) begin
c_reg_1523 <= grp_fu_550_p1;
end
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
d_addr_1_reg_1300 <= d_addr_1_reg_13000;
end
if (((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2))) begin
d_addr_4_reg_1404 <= tmp_26_reg_1355;
end
if ((ap_ST_st108_fsm_108 == ap_CS_fsm)) begin
d_load_3_reg_1410 <= d_q1;
end
if (((ap_ST_st4_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_790_p2))) begin
indvar10_reg_309 <= ap_const_lv32_1;
end else if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
indvar10_reg_309 <= (indvar10_reg_309 + ap_const_lv32_1);
end
if ((((ap_ST_st391_fsm_391 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_do_rotate_fu_497_ap_done)) | ((ap_ST_st107_fsm_107 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_604_p2)) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
indvar1_reg_434 <= indvar_next2_reg_1327;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
indvar1_reg_434 <= ap_const_lv7_0;
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar2_reg_253 <= ap_const_lv8_0;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
indvar2_reg_253 <= indvar_next3_reg_1155;
end
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
indvar3_cast_reg_1282[0] <= indvar3_cast_fu_967_p1[0];
indvar3_cast_reg_1282[1] <= indvar3_cast_fu_967_p1[1];
indvar3_cast_reg_1282[2] <= indvar3_cast_fu_967_p1[2];
indvar3_cast_reg_1282[3] <= indvar3_cast_fu_967_p1[3];
indvar3_cast_reg_1282[4] <= indvar3_cast_fu_967_p1[4];
indvar3_cast_reg_1282[5] <= indvar3_cast_fu_967_p1[5];
indvar3_cast_reg_1282[6] <= indvar3_cast_fu_967_p1[6];
end
if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
indvar3_reg_411 <= ap_const_lv7_0;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
indvar3_reg_411 <= tmp_19_reg_1292;
end
if (((ap_ST_st2_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_746_p2))) begin
indvar4_reg_286 <= ap_const_lv8_0;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
indvar4_reg_286 <= indvar_next1_reg_1176;
end
if (((ap_ST_st2_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_746_p2))) begin
indvar5_reg_275 <= ap_const_lv8_0;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
indvar5_reg_275 <= (indvar5_reg_275 + ap_const_lv8_1);
end
if (((ap_ST_st2_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_746_p2))) begin
indvar6_reg_264 <= ap_const_lv64_0;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
indvar6_reg_264 <= (indvar6_reg_264 + ap_const_lv64_1);
end
if (((ap_ST_st6_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_fu_836_p2))) begin
indvar7_reg_321 <= ap_const_lv7_0;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_880_p2))) begin
indvar7_reg_321 <= tmp_4_reg_1205;
end
if (((ap_ST_st7_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_868_p2))) begin
indvar8_reg_356 <= ap_const_lv7_0;
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
indvar8_reg_356 <= indvar_next5_reg_1221;
end
if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
indvar9_reg_400 <= ap_const_lv7_0;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
indvar9_reg_400 <= tmp_18_reg_1276;
end
if ((ap_ST_st4_fsm_4 == ap_CS_fsm)) begin
indvar_next1_reg_1176 <= (indvar4_reg_286 + ap_const_lv8_1);
end
if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
indvar_next2_reg_1327 <= (indvar1_reg_434 + ap_const_lv7_1);
end
if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
indvar_next3_reg_1155 <= (indvar2_reg_253 + ap_const_lv8_1);
end
if ((ap_ST_st8_fsm_8 == ap_CS_fsm)) begin
indvar_next5_reg_1221 <= (indvar8_reg_356 + ap_const_lv7_1);
end
if ((ap_ST_st392_fsm_392 == ap_CS_fsm)) begin
indvar_next_reg_1547 <= (indvar_reg_474 + ap_const_lv8_1);
end
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
indvar_reg_474 <= ap_const_lv8_0;
end else if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
indvar_reg_474 <= indvar_next_reg_1547;
end
if (((ap_ST_st2_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_746_p2))) begin
ip_1_reg_297 <= ap_const_lv8_1;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
ip_1_reg_297 <= (ip_1_reg_297 + ap_const_lv8_1);
end
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
ip_4_reg_485 <= ap_const_lv8_1;
end else if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
ip_4_reg_485 <= tmp_24_reg_1567;
end
if (((ap_ST_st7_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_868_p2))) begin
iq_1_in_reg_367 <= {{24{1'b0}}, {ip_2_fu_852_p2}};
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
iq_1_in_reg_367 <= iq_1_reg_1213;
end
if ((ap_ST_st8_fsm_8 == ap_CS_fsm)) begin
iq_1_reg_1213 <= (iq_1_in_reg_367 + ap_const_lv32_1);
end
if ((((ap_ST_st391_fsm_391 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_do_rotate_fu_497_ap_done)) | ((ap_ST_st107_fsm_107 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_604_p2)) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
iq_2_in_reg_449 <= tmp_21_reg_1316;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
iq_2_in_reg_449 <= {{24{1'b0}}, {ip_3_fu_971_p2}};
end
if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
iq_2_reg_1311 <= (tmp3_cast_fu_1009_p1 + indvar3_cast_reg_1282);
end
if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm))) begin
reg_640 <= a_q0;
end
if (((ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st113_fsm_113 == ap_CS_fsm) | ((ap_ST_st210_fsm_210 == ap_CS_fsm) & (tmp_i5_reg_1449 == ap_const_lv1_1)) | (ap_ST_st279_fsm_279 == ap_CS_fsm) | (ap_ST_st398_fsm_398 == ap_CS_fsm))) begin
reg_649 <= grp_fu_509_p2;
end
if (((ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st134_fsm_134 == ap_CS_fsm))) begin
reg_661 <= grp_fu_623_p2;
end
if (((ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st168_fsm_168 == ap_CS_fsm) | (ap_ST_st252_fsm_252 == ap_CS_fsm) | (ap_ST_st345_fsm_345 == ap_CS_fsm) | (ap_ST_st388_fsm_388 == ap_CS_fsm))) begin
reg_666 <= grp_fu_629_p2;
end
if (((ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st174_fsm_174 == ap_CS_fsm) | (ap_ST_st274_fsm_274 == ap_CS_fsm) | (ap_ST_st351_fsm_351 == ap_CS_fsm))) begin
reg_675 <= grp_fu_528_p2;
end
if (((ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st275_fsm_275 == ap_CS_fsm))) begin
reg_684 <= d_q0;
end
if (((ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st280_fsm_280 == ap_CS_fsm))) begin
reg_692 <= grp_fu_509_p2;
end
if (((ap_ST_st182_fsm_182 == ap_CS_fsm) | (ap_ST_st218_fsm_218 == ap_CS_fsm) | (ap_ST_st354_fsm_354 == ap_CS_fsm))) begin
reg_698 <= grp_fu_618_p2;
end
if (((ap_ST_st212_fsm_212 == ap_CS_fsm) | (ap_ST_st311_fsm_311 == ap_CS_fsm))) begin
reg_704 <= grp_fu_635_p2;
end
if (((ap_ST_st275_fsm_275 == ap_CS_fsm) | (ap_ST_st393_fsm_393 == ap_CS_fsm))) begin
reg_710 <= z_q0;
end
if (((ap_ST_st6_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_fu_836_p2))) begin
sm_1_reg_344 <= ap_const_lv32_0;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_880_p2))) begin
sm_1_reg_344 <= sm_reg_376;
end
if (((ap_ST_st7_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_868_p2))) begin
sm_reg_376 <= sm_1_reg_344;
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
sm_reg_376 <= grp_fu_509_p2;
end
if (((ap_ST_st254_fsm_254 == ap_CS_fsm) & (tmp_i5_reg_1449 == ap_const_lv1_0))) begin
t_reg_462 <= grp_fu_547_p1;
end else if ((ap_ST_st259_fsm_259 == ap_CS_fsm)) begin
t_reg_462 <= grp_fu_509_p2;
end else if ((ap_ST_st270_fsm_270 == ap_CS_fsm)) begin
t_reg_462 <= grp_fu_537_p2;
end
if ((ap_ST_st390_fsm_390 == ap_CS_fsm)) begin
tau_reg_1539 <= grp_fu_553_p1;
end
if ((ap_ST_st170_fsm_170 == ap_CS_fsm)) begin
theta_reg_1440 <= grp_fu_544_p1;
end
if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
tmp36_cast_reg_1147[7] <= tmp36_cast_fu_742_p1[7];
tmp36_cast_reg_1147[8] <= tmp36_cast_fu_742_p1[8];
tmp36_cast_reg_1147[9] <= tmp36_cast_fu_742_p1[9];
tmp36_cast_reg_1147[10] <= tmp36_cast_fu_742_p1[10];
tmp36_cast_reg_1147[11] <= tmp36_cast_fu_742_p1[11];
tmp36_cast_reg_1147[12] <= tmp36_cast_fu_742_p1[12];
tmp36_cast_reg_1147[13] <= tmp36_cast_fu_742_p1[13];
tmp36_cast_reg_1147[14] <= tmp36_cast_fu_742_p1[14];
end
if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
tmp4_reg_1195 <= (indvar7_reg_321 ^ ap_const_lv7_7F);
end
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
tmp5_reg_1271 <= (indvar9_reg_400 ^ ap_const_lv7_7F);
end
if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
tmp_13_reg_1267 <= ($signed(indvar10_reg_309) < $signed(32'b00000000000000000000000000000101)? 1'b1: 1'b0);
end
if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
tmp_17_reg_422 <= ap_const_lv8_1;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
tmp_17_reg_422 <= (tmp_17_reg_422 + ap_const_lv8_1);
end
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
tmp_18_reg_1276 <= (indvar9_reg_400 + ap_const_lv7_1);
end
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
tmp_19_reg_1292 <= (indvar3_reg_411 + ap_const_lv7_1);
end
if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
tmp_21_reg_1316 <= (iq_2_in_reg_449 + ap_const_lv32_1);
end
if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
tmp_22_reg_1552[0] <= tmp_22_fu_1124_p1[0];
tmp_22_reg_1552[1] <= tmp_22_fu_1124_p1[1];
tmp_22_reg_1552[2] <= tmp_22_fu_1124_p1[2];
tmp_22_reg_1552[3] <= tmp_22_fu_1124_p1[3];
tmp_22_reg_1552[4] <= tmp_22_fu_1124_p1[4];
tmp_22_reg_1552[5] <= tmp_22_fu_1124_p1[5];
tmp_22_reg_1552[6] <= tmp_22_fu_1124_p1[6];
tmp_22_reg_1552[7] <= tmp_22_fu_1124_p1[7];
end
if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
tmp_24_reg_1567 <= (ip_4_reg_485 + ap_const_lv8_1);
end
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
tmp_26_reg_1355 <= {{32{tmp_21_reg_1316[31]}}, {tmp_21_reg_1316}};
end
if ((ap_ST_st92_fsm_92 == ap_CS_fsm)) begin
tmp_28_reg_1373 <= grp_fu_596_p2;
end
if ((ap_ST_st104_fsm_104 == ap_CS_fsm)) begin
tmp_29_reg_1393 <= grp_fu_509_p2;
end
if ((ap_ST_st127_fsm_127 == ap_CS_fsm)) begin
tmp_36_reg_1430 <= grp_fu_561_p1;
end
if ((ap_ST_st134_fsm_134 == ap_CS_fsm)) begin
tmp_38_reg_1435 <= grp_fu_564_p1;
end
if ((ap_ST_st212_fsm_212 == ap_CS_fsm)) begin
tmp_40_reg_1464 <= grp_fu_570_p1;
end
if ((ap_ST_st176_fsm_176 == ap_CS_fsm)) begin
tmp_42_reg_1454 <= grp_fu_567_p1;
end
if ((ap_ST_st254_fsm_254 == ap_CS_fsm)) begin
tmp_47_reg_1469 <= grp_fu_547_p1;
end
if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
tmp_4_reg_1205 <= (indvar7_reg_321 + ap_const_lv7_1);
end
if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
tmp_52_reg_1518 <= grp_fu_573_p1;
end
if ((ap_ST_st354_fsm_354 == ap_CS_fsm)) begin
tmp_55_reg_1534 <= grp_fu_580_p1;
end
if ((ap_ST_st348_fsm_348 == ap_CS_fsm)) begin
tmp_56_reg_1529 <= grp_fu_576_p1;
end
if ((ap_ST_st275_fsm_275 == ap_CS_fsm)) begin
tmp_59_reg_1490 <= grp_fu_528_p2;
end
if ((ap_ST_st280_fsm_280 == ap_CS_fsm)) begin
tmp_61_reg_1503 <= grp_fu_516_p2;
end
if ((ap_ST_st280_fsm_280 == ap_CS_fsm)) begin
tmp_62_reg_1508 <= grp_fu_520_p2;
end
if ((ap_ST_st280_fsm_280 == ap_CS_fsm)) begin
tmp_63_reg_1513 <= grp_fu_524_p2;
end
if ((ap_ST_st6_fsm_6 == ap_CS_fsm)) begin
tmp_6_reg_1191 <= ($signed(indvar10_reg_309) < $signed(32'b00000000000000000000000000110011)? 1'b1: 1'b0);
end
if (((ap_ST_st6_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_fu_836_p2))) begin
tmp_7_reg_332 <= ap_const_lv8_1;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_880_p2))) begin
tmp_7_reg_332 <= (tmp_7_reg_332 + ap_const_lv8_1);
end
if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
tmp_9_cast_reg_1142[7] <= tmp_9_cast_fu_732_p1[7];
tmp_9_cast_reg_1142[8] <= tmp_9_cast_fu_732_p1[8];
tmp_9_cast_reg_1142[9] <= tmp_9_cast_fu_732_p1[9];
tmp_9_cast_reg_1142[10] <= tmp_9_cast_fu_732_p1[10];
tmp_9_cast_reg_1142[11] <= tmp_9_cast_fu_732_p1[11];
tmp_9_cast_reg_1142[12] <= tmp_9_cast_fu_732_p1[12];
tmp_9_cast_reg_1142[13] <= tmp_9_cast_fu_732_p1[13];
tmp_9_cast_reg_1142[14] <= tmp_9_cast_fu_732_p1[14];
end
if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
tmp_i1_reg_1344 <= grp_fu_589_p2;
end
if ((ap_ST_st80_fsm_80 == ap_CS_fsm)) begin
tmp_i2_reg_1362 <= grp_fu_589_p2;
end
if ((ap_ST_st94_fsm_94 == ap_CS_fsm)) begin
tmp_i3_reg_1382 <= grp_fu_589_p2;
end
if ((ap_ST_st115_fsm_115 == ap_CS_fsm)) begin
tmp_i4_reg_1416 <= grp_fu_589_p2;
end
if ((ap_ST_st172_fsm_172 == ap_CS_fsm)) begin
tmp_i5_reg_1449 <= grp_fu_613_p2;
end
if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
tmp_i_reg_1236 <= grp_fu_589_p2;
end
if ((ap_ST_st22_fsm_22 == ap_CS_fsm)) begin
tmp_s_reg_1257 <= grp_fu_557_p1;
end
if (((ap_ST_st21_fsm_21 == ap_CS_fsm) & (ap_const_lv1_0 == icmp_fu_939_p2) & ~(ap_const_lv1_0 == tmp_6_reg_1191) & (ap_const_lv1_0 == grp_fu_583_p2))) begin
tresh_reg_388 <= ap_const_lv32_0;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
tresh_reg_388 <= grp_fu_541_p1;
end
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond5_fu_987_p2))) begin
z_addr_1_reg_1306 <= z_addr_1_reg_13060;
end
if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
z_addr_2_reg_1562 <= z_addr_2_reg_15620;
end
if ((ap_ST_st271_fsm_271 == ap_CS_fsm)) begin
z_addr_3_reg_1485 <= tmp_26_reg_1355;
end
if ((ap_ST_st275_fsm_275 == ap_CS_fsm)) begin
z_load_2_reg_1498 <= z_q1;
end
end
/// a_address0 assign process. ///
always @ (ap_CS_fsm or exitcond1_fu_790_p2 or exitcond4_fu_880_p2 or tmp_13_reg_1267 or a_addr_2_reg_1334 or exitcond7_fu_1024_p2 or tmp_28_reg_1373 or grp_do_rotate_fu_497_a_address0 or grp_fu_600_p2 or tmp_1_fu_818_p1 or tmp_15_fu_911_p1 or tmp_48_fu_1055_p1)
begin
if (((ap_ST_st271_fsm_271 == ap_CS_fsm) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
a_address0 = a_addr_2_reg_1334;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
a_address0 = tmp_48_fu_1055_p1;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond4_fu_880_p2))) begin
a_address0 = tmp_15_fu_911_p1;
end else if (((ap_ST_st4_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_790_p2))) begin
a_address0 = tmp_1_fu_818_p1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_address0 = grp_do_rotate_fu_497_a_address0;
end else begin
a_address0 = grp_do_rotate_fu_497_a_address0;
end
end
/// a_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond1_fu_790_p2 or exitcond4_fu_880_p2 or tmp_13_reg_1267 or exitcond7_fu_1024_p2 or tmp_28_reg_1373 or grp_do_rotate_fu_497_a_ce0 or grp_fu_600_p2)
begin
if ((((ap_ST_st4_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_790_p2)) | ((ap_ST_st8_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond4_fu_880_p2)) | ((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond7_fu_1024_p2)) | (ap_ST_st271_fsm_271 == ap_CS_fsm) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
a_ce0 = ap_const_logic_1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_ce0 = grp_do_rotate_fu_497_a_ce0;
end else begin
a_ce0 = ap_const_logic_0;
end
end
/// a_ce1 assign process. ///
always @ (ap_CS_fsm or grp_do_rotate_fu_497_a_ce1)
begin
if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_ce1 = grp_do_rotate_fu_497_a_ce1;
end else begin
a_ce1 = ap_const_logic_0;
end
end
/// a_d0 assign process. ///
always @ (ap_CS_fsm or tmp_13_reg_1267 or tmp_28_reg_1373 or grp_do_rotate_fu_497_a_d0 or grp_fu_600_p2)
begin
if (((ap_ST_st271_fsm_271 == ap_CS_fsm) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
a_d0 = ap_const_lv32_0;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_d0 = grp_do_rotate_fu_497_a_d0;
end else begin
a_d0 = ap_const_lv32_0;
end
end
/// a_we0 assign process. ///
always @ (ap_CS_fsm or tmp_13_reg_1267 or tmp_28_reg_1373 or grp_do_rotate_fu_497_a_we0 or grp_fu_600_p2)
begin
if (((ap_ST_st271_fsm_271 == ap_CS_fsm) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
a_we0 = ap_const_logic_1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_we0 = grp_do_rotate_fu_497_a_we0;
end else begin
a_we0 = ap_const_logic_0;
end
end
/// a_we1 assign process. ///
always @ (ap_CS_fsm or grp_do_rotate_fu_497_a_we1)
begin
if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
a_we1 = grp_do_rotate_fu_497_a_we1;
end else begin
a_we1 = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or tmp_i5_reg_1449 or exitcond2_fu_772_p2 or exitcond1_fu_790_p2 or tmp_6_fu_836_p2 or tmp_6_reg_1191 or exitcond4_fu_880_p2 or tmp_13_reg_1267 or exitcond5_fu_987_p2 or exitcond7_fu_1024_p2 or grp_fu_596_p2 or tmp_28_reg_1373 or grp_fu_604_p2 or exitcond6_fu_1112_p2 or grp_do_rotate_fu_497_ap_done or exitcond_fu_746_p2 or exitcond3_fu_868_p2 or icmp_fu_939_p2 or grp_fu_583_p2 or grp_fu_600_p2 or grp_fu_609_p2)
begin
if ((ap_ST_st398_fsm_398 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st399_fsm_399;
end else if ((ap_ST_st397_fsm_397 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st398_fsm_398;
end else if ((ap_ST_st396_fsm_396 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st397_fsm_397;
end else if ((ap_ST_st395_fsm_395 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st396_fsm_396;
end else if ((ap_ST_st394_fsm_394 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st395_fsm_395;
end else if ((ap_ST_st393_fsm_393 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st394_fsm_394;
end else if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
ap_NS_fsm = ap_ST_st393_fsm_393;
end else if ((ap_ST_st390_fsm_390 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st391_fsm_391;
end else if ((ap_ST_st389_fsm_389 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st390_fsm_390;
end else if ((ap_ST_st388_fsm_388 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st389_fsm_389;
end else if ((ap_ST_st387_fsm_387 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st388_fsm_388;
end else if ((ap_ST_st386_fsm_386 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st387_fsm_387;
end else if ((ap_ST_st385_fsm_385 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st386_fsm_386;
end else if ((ap_ST_st384_fsm_384 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st385_fsm_385;
end else if ((ap_ST_st383_fsm_383 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st384_fsm_384;
end else if ((ap_ST_st382_fsm_382 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st383_fsm_383;
end else if ((ap_ST_st381_fsm_381 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st382_fsm_382;
end else if ((ap_ST_st380_fsm_380 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st381_fsm_381;
end else if ((ap_ST_st379_fsm_379 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st380_fsm_380;
end else if ((ap_ST_st378_fsm_378 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st379_fsm_379;
end else if ((ap_ST_st377_fsm_377 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st378_fsm_378;
end else if ((ap_ST_st376_fsm_376 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st377_fsm_377;
end else if ((ap_ST_st375_fsm_375 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st376_fsm_376;
end else if ((ap_ST_st374_fsm_374 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st375_fsm_375;
end else if ((ap_ST_st373_fsm_373 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st374_fsm_374;
end else if ((ap_ST_st372_fsm_372 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st373_fsm_373;
end else if ((ap_ST_st371_fsm_371 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st372_fsm_372;
end else if ((ap_ST_st370_fsm_370 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st371_fsm_371;
end else if ((ap_ST_st369_fsm_369 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st370_fsm_370;
end else if ((ap_ST_st368_fsm_368 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st369_fsm_369;
end else if ((ap_ST_st367_fsm_367 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st368_fsm_368;
end else if ((ap_ST_st366_fsm_366 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st367_fsm_367;
end else if ((ap_ST_st365_fsm_365 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st366_fsm_366;
end else if ((ap_ST_st364_fsm_364 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st365_fsm_365;
end else if ((ap_ST_st363_fsm_363 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st364_fsm_364;
end else if ((ap_ST_st362_fsm_362 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st363_fsm_363;
end else if ((ap_ST_st361_fsm_361 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st362_fsm_362;
end else if ((ap_ST_st360_fsm_360 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st361_fsm_361;
end else if ((ap_ST_st359_fsm_359 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st360_fsm_360;
end else if ((ap_ST_st358_fsm_358 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st359_fsm_359;
end else if ((ap_ST_st357_fsm_357 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st358_fsm_358;
end else if ((ap_ST_st356_fsm_356 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st357_fsm_357;
end else if ((ap_ST_st355_fsm_355 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st356_fsm_356;
end else if ((ap_ST_st354_fsm_354 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st355_fsm_355;
end else if ((ap_ST_st353_fsm_353 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st354_fsm_354;
end else if ((ap_ST_st352_fsm_352 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st353_fsm_353;
end else if ((ap_ST_st351_fsm_351 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st352_fsm_352;
end else if ((ap_ST_st350_fsm_350 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st351_fsm_351;
end else if ((ap_ST_st349_fsm_349 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st350_fsm_350;
end else if ((ap_ST_st348_fsm_348 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st349_fsm_349;
end else if ((ap_ST_st347_fsm_347 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st348_fsm_348;
end else if ((ap_ST_st346_fsm_346 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st347_fsm_347;
end else if ((ap_ST_st345_fsm_345 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st346_fsm_346;
end else if ((ap_ST_st344_fsm_344 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st345_fsm_345;
end else if ((ap_ST_st343_fsm_343 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st344_fsm_344;
end else if ((ap_ST_st342_fsm_342 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st343_fsm_343;
end else if ((ap_ST_st341_fsm_341 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st342_fsm_342;
end else if ((ap_ST_st340_fsm_340 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st341_fsm_341;
end else if ((ap_ST_st339_fsm_339 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st340_fsm_340;
end else if ((ap_ST_st338_fsm_338 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st339_fsm_339;
end else if ((ap_ST_st337_fsm_337 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st338_fsm_338;
end else if ((ap_ST_st336_fsm_336 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st337_fsm_337;
end else if ((ap_ST_st335_fsm_335 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st336_fsm_336;
end else if ((ap_ST_st334_fsm_334 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st335_fsm_335;
end else if ((ap_ST_st333_fsm_333 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st334_fsm_334;
end else if ((ap_ST_st332_fsm_332 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st333_fsm_333;
end else if ((ap_ST_st331_fsm_331 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st332_fsm_332;
end else if ((ap_ST_st330_fsm_330 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st331_fsm_331;
end else if ((ap_ST_st329_fsm_329 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st330_fsm_330;
end else if ((ap_ST_st328_fsm_328 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st329_fsm_329;
end else if ((ap_ST_st327_fsm_327 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st328_fsm_328;
end else if ((ap_ST_st326_fsm_326 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st327_fsm_327;
end else if ((ap_ST_st325_fsm_325 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st326_fsm_326;
end else if ((ap_ST_st324_fsm_324 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st325_fsm_325;
end else if ((ap_ST_st323_fsm_323 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st324_fsm_324;
end else if ((ap_ST_st322_fsm_322 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st323_fsm_323;
end else if ((ap_ST_st321_fsm_321 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st322_fsm_322;
end else if ((ap_ST_st320_fsm_320 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st321_fsm_321;
end else if ((ap_ST_st319_fsm_319 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st320_fsm_320;
end else if ((ap_ST_st318_fsm_318 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st319_fsm_319;
end else if ((ap_ST_st317_fsm_317 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st318_fsm_318;
end else if ((ap_ST_st316_fsm_316 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st317_fsm_317;
end else if ((ap_ST_st315_fsm_315 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st316_fsm_316;
end else if ((ap_ST_st314_fsm_314 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st315_fsm_315;
end else if ((ap_ST_st313_fsm_313 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st314_fsm_314;
end else if ((ap_ST_st312_fsm_312 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st313_fsm_313;
end else if ((ap_ST_st311_fsm_311 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st312_fsm_312;
end else if ((ap_ST_st310_fsm_310 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st311_fsm_311;
end else if ((ap_ST_st309_fsm_309 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st310_fsm_310;
end else if ((ap_ST_st308_fsm_308 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st309_fsm_309;
end else if ((ap_ST_st307_fsm_307 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st308_fsm_308;
end else if ((ap_ST_st306_fsm_306 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st307_fsm_307;
end else if ((ap_ST_st305_fsm_305 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st306_fsm_306;
end else if ((ap_ST_st304_fsm_304 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st305_fsm_305;
end else if ((ap_ST_st303_fsm_303 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st304_fsm_304;
end else if ((ap_ST_st302_fsm_302 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st303_fsm_303;
end else if ((ap_ST_st301_fsm_301 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st302_fsm_302;
end else if ((ap_ST_st300_fsm_300 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st301_fsm_301;
end else if ((ap_ST_st299_fsm_299 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st300_fsm_300;
end else if ((ap_ST_st298_fsm_298 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st299_fsm_299;
end else if ((ap_ST_st297_fsm_297 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st298_fsm_298;
end else if ((ap_ST_st296_fsm_296 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st297_fsm_297;
end else if ((ap_ST_st295_fsm_295 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st296_fsm_296;
end else if ((ap_ST_st294_fsm_294 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st295_fsm_295;
end else if ((ap_ST_st293_fsm_293 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st294_fsm_294;
end else if ((ap_ST_st292_fsm_292 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st293_fsm_293;
end else if ((ap_ST_st291_fsm_291 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st292_fsm_292;
end else if ((ap_ST_st290_fsm_290 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st291_fsm_291;
end else if ((ap_ST_st289_fsm_289 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st290_fsm_290;
end else if ((ap_ST_st288_fsm_288 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st289_fsm_289;
end else if ((ap_ST_st287_fsm_287 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st288_fsm_288;
end else if ((ap_ST_st286_fsm_286 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st287_fsm_287;
end else if ((ap_ST_st285_fsm_285 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st286_fsm_286;
end else if ((ap_ST_st284_fsm_284 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st285_fsm_285;
end else if ((ap_ST_st283_fsm_283 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st284_fsm_284;
end else if ((ap_ST_st282_fsm_282 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st283_fsm_283;
end else if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st282_fsm_282;
end else if ((ap_ST_st280_fsm_280 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st281_fsm_281;
end else if ((ap_ST_st279_fsm_279 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st280_fsm_280;
end else if ((ap_ST_st278_fsm_278 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st279_fsm_279;
end else if ((ap_ST_st277_fsm_277 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st278_fsm_278;
end else if ((ap_ST_st276_fsm_276 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st277_fsm_277;
end else if ((ap_ST_st275_fsm_275 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st276_fsm_276;
end else if ((ap_ST_st274_fsm_274 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st275_fsm_275;
end else if ((ap_ST_st273_fsm_273 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st274_fsm_274;
end else if ((ap_ST_st272_fsm_272 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st273_fsm_273;
end else if ((ap_ST_st271_fsm_271 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st272_fsm_272;
end else if ((ap_ST_st269_fsm_269 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st270_fsm_270;
end else if ((ap_ST_st268_fsm_268 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st269_fsm_269;
end else if ((ap_ST_st267_fsm_267 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st268_fsm_268;
end else if ((ap_ST_st266_fsm_266 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st267_fsm_267;
end else if ((ap_ST_st265_fsm_265 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st266_fsm_266;
end else if ((ap_ST_st264_fsm_264 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st265_fsm_265;
end else if ((ap_ST_st263_fsm_263 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st264_fsm_264;
end else if ((ap_ST_st262_fsm_262 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st263_fsm_263;
end else if ((ap_ST_st261_fsm_261 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st262_fsm_262;
end else if ((ap_ST_st260_fsm_260 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st261_fsm_261;
end else if ((ap_ST_st258_fsm_258 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st259_fsm_259;
end else if ((ap_ST_st257_fsm_257 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st258_fsm_258;
end else if ((ap_ST_st256_fsm_256 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st257_fsm_257;
end else if ((ap_ST_st255_fsm_255 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st256_fsm_256;
end else if (((ap_ST_st259_fsm_259 == ap_CS_fsm) | (ap_ST_st270_fsm_270 == ap_CS_fsm) | ((ap_ST_st254_fsm_254 == ap_CS_fsm) & (tmp_i5_reg_1449 == ap_const_lv1_0)))) begin
ap_NS_fsm = ap_ST_st271_fsm_271;
end else if (((ap_ST_st254_fsm_254 == ap_CS_fsm) & ~(tmp_i5_reg_1449 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st255_fsm_255;
end else if ((ap_ST_st253_fsm_253 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st254_fsm_254;
end else if ((ap_ST_st252_fsm_252 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st253_fsm_253;
end else if ((ap_ST_st251_fsm_251 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st252_fsm_252;
end else if ((ap_ST_st250_fsm_250 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st251_fsm_251;
end else if ((ap_ST_st249_fsm_249 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st250_fsm_250;
end else if ((ap_ST_st248_fsm_248 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st249_fsm_249;
end else if ((ap_ST_st247_fsm_247 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st248_fsm_248;
end else if ((ap_ST_st246_fsm_246 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st247_fsm_247;
end else if ((ap_ST_st245_fsm_245 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st246_fsm_246;
end else if ((ap_ST_st244_fsm_244 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st245_fsm_245;
end else if ((ap_ST_st243_fsm_243 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st244_fsm_244;
end else if ((ap_ST_st242_fsm_242 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st243_fsm_243;
end else if ((ap_ST_st241_fsm_241 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st242_fsm_242;
end else if ((ap_ST_st240_fsm_240 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st241_fsm_241;
end else if ((ap_ST_st239_fsm_239 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st240_fsm_240;
end else if ((ap_ST_st238_fsm_238 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st239_fsm_239;
end else if ((ap_ST_st237_fsm_237 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st238_fsm_238;
end else if ((ap_ST_st236_fsm_236 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st237_fsm_237;
end else if ((ap_ST_st235_fsm_235 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st236_fsm_236;
end else if ((ap_ST_st234_fsm_234 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st235_fsm_235;
end else if ((ap_ST_st233_fsm_233 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st234_fsm_234;
end else if ((ap_ST_st232_fsm_232 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st233_fsm_233;
end else if ((ap_ST_st231_fsm_231 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st232_fsm_232;
end else if ((ap_ST_st230_fsm_230 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st231_fsm_231;
end else if ((ap_ST_st229_fsm_229 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st230_fsm_230;
end else if ((ap_ST_st228_fsm_228 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st229_fsm_229;
end else if ((ap_ST_st227_fsm_227 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st228_fsm_228;
end else if ((ap_ST_st226_fsm_226 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st227_fsm_227;
end else if ((ap_ST_st225_fsm_225 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st226_fsm_226;
end else if ((ap_ST_st224_fsm_224 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st225_fsm_225;
end else if ((ap_ST_st223_fsm_223 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st224_fsm_224;
end else if ((ap_ST_st222_fsm_222 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st223_fsm_223;
end else if ((ap_ST_st221_fsm_221 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st222_fsm_222;
end else if ((ap_ST_st220_fsm_220 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st221_fsm_221;
end else if ((ap_ST_st219_fsm_219 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st220_fsm_220;
end else if ((ap_ST_st218_fsm_218 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st219_fsm_219;
end else if ((ap_ST_st217_fsm_217 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st218_fsm_218;
end else if ((ap_ST_st216_fsm_216 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st217_fsm_217;
end else if ((ap_ST_st215_fsm_215 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st216_fsm_216;
end else if ((ap_ST_st214_fsm_214 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st215_fsm_215;
end else if ((ap_ST_st213_fsm_213 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st214_fsm_214;
end else if ((ap_ST_st212_fsm_212 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st213_fsm_213;
end else if ((ap_ST_st211_fsm_211 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st212_fsm_212;
end else if ((ap_ST_st210_fsm_210 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st211_fsm_211;
end else if ((ap_ST_st209_fsm_209 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st210_fsm_210;
end else if ((ap_ST_st208_fsm_208 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st209_fsm_209;
end else if ((ap_ST_st207_fsm_207 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st208_fsm_208;
end else if ((ap_ST_st206_fsm_206 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st207_fsm_207;
end else if ((ap_ST_st205_fsm_205 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st206_fsm_206;
end else if ((ap_ST_st204_fsm_204 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st205_fsm_205;
end else if ((ap_ST_st203_fsm_203 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st204_fsm_204;
end else if ((ap_ST_st202_fsm_202 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st203_fsm_203;
end else if ((ap_ST_st201_fsm_201 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st202_fsm_202;
end else if ((ap_ST_st200_fsm_200 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st201_fsm_201;
end else if ((ap_ST_st199_fsm_199 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st200_fsm_200;
end else if ((ap_ST_st198_fsm_198 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st199_fsm_199;
end else if ((ap_ST_st197_fsm_197 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st198_fsm_198;
end else if ((ap_ST_st196_fsm_196 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st197_fsm_197;
end else if ((ap_ST_st195_fsm_195 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st196_fsm_196;
end else if ((ap_ST_st194_fsm_194 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st195_fsm_195;
end else if ((ap_ST_st193_fsm_193 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st194_fsm_194;
end else if ((ap_ST_st192_fsm_192 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st193_fsm_193;
end else if ((ap_ST_st191_fsm_191 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st192_fsm_192;
end else if ((ap_ST_st190_fsm_190 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st191_fsm_191;
end else if ((ap_ST_st189_fsm_189 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st190_fsm_190;
end else if ((ap_ST_st188_fsm_188 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st189_fsm_189;
end else if ((ap_ST_st187_fsm_187 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st188_fsm_188;
end else if ((ap_ST_st186_fsm_186 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st187_fsm_187;
end else if ((ap_ST_st185_fsm_185 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st186_fsm_186;
end else if ((ap_ST_st184_fsm_184 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st185_fsm_185;
end else if ((ap_ST_st183_fsm_183 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st184_fsm_184;
end else if ((ap_ST_st182_fsm_182 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st183_fsm_183;
end else if ((ap_ST_st181_fsm_181 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st182_fsm_182;
end else if ((ap_ST_st180_fsm_180 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st181_fsm_181;
end else if ((ap_ST_st179_fsm_179 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st180_fsm_180;
end else if ((ap_ST_st178_fsm_178 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st179_fsm_179;
end else if ((ap_ST_st177_fsm_177 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st178_fsm_178;
end else if ((ap_ST_st176_fsm_176 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st177_fsm_177;
end else if ((ap_ST_st175_fsm_175 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st176_fsm_176;
end else if ((ap_ST_st174_fsm_174 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st175_fsm_175;
end else if ((ap_ST_st173_fsm_173 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st174_fsm_174;
end else if ((ap_ST_st172_fsm_172 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st173_fsm_173;
end else if ((ap_ST_st171_fsm_171 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st172_fsm_172;
end else if ((ap_ST_st170_fsm_170 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st171_fsm_171;
end else if ((ap_ST_st169_fsm_169 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st170_fsm_170;
end else if ((ap_ST_st168_fsm_168 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st169_fsm_169;
end else if ((ap_ST_st167_fsm_167 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st168_fsm_168;
end else if ((ap_ST_st166_fsm_166 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st167_fsm_167;
end else if ((ap_ST_st165_fsm_165 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st166_fsm_166;
end else if ((ap_ST_st164_fsm_164 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st165_fsm_165;
end else if ((ap_ST_st163_fsm_163 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st164_fsm_164;
end else if ((ap_ST_st162_fsm_162 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st163_fsm_163;
end else if ((ap_ST_st161_fsm_161 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st162_fsm_162;
end else if ((ap_ST_st160_fsm_160 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st161_fsm_161;
end else if ((ap_ST_st159_fsm_159 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st160_fsm_160;
end else if ((ap_ST_st158_fsm_158 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st159_fsm_159;
end else if ((ap_ST_st157_fsm_157 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st158_fsm_158;
end else if ((ap_ST_st156_fsm_156 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st157_fsm_157;
end else if ((ap_ST_st155_fsm_155 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st156_fsm_156;
end else if ((ap_ST_st154_fsm_154 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st155_fsm_155;
end else if ((ap_ST_st153_fsm_153 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st154_fsm_154;
end else if ((ap_ST_st152_fsm_152 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st153_fsm_153;
end else if ((ap_ST_st151_fsm_151 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st152_fsm_152;
end else if ((ap_ST_st150_fsm_150 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st151_fsm_151;
end else if ((ap_ST_st149_fsm_149 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st150_fsm_150;
end else if ((ap_ST_st148_fsm_148 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st149_fsm_149;
end else if ((ap_ST_st147_fsm_147 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st148_fsm_148;
end else if ((ap_ST_st146_fsm_146 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st147_fsm_147;
end else if ((ap_ST_st145_fsm_145 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st146_fsm_146;
end else if ((ap_ST_st144_fsm_144 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st145_fsm_145;
end else if ((ap_ST_st143_fsm_143 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st144_fsm_144;
end else if ((ap_ST_st142_fsm_142 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st143_fsm_143;
end else if ((ap_ST_st141_fsm_141 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st142_fsm_142;
end else if ((ap_ST_st140_fsm_140 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st141_fsm_141;
end else if ((ap_ST_st139_fsm_139 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st140_fsm_140;
end else if ((ap_ST_st138_fsm_138 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st139_fsm_139;
end else if ((ap_ST_st137_fsm_137 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st138_fsm_138;
end else if ((ap_ST_st136_fsm_136 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st137_fsm_137;
end else if ((ap_ST_st135_fsm_135 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st136_fsm_136;
end else if ((ap_ST_st134_fsm_134 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st135_fsm_135;
end else if ((ap_ST_st133_fsm_133 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st134_fsm_134;
end else if ((ap_ST_st132_fsm_132 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st133_fsm_133;
end else if ((ap_ST_st131_fsm_131 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st132_fsm_132;
end else if ((ap_ST_st130_fsm_130 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st131_fsm_131;
end else if ((ap_ST_st129_fsm_129 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st130_fsm_130;
end else if ((ap_ST_st128_fsm_128 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st129_fsm_129;
end else if ((ap_ST_st127_fsm_127 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st128_fsm_128;
end else if (((ap_ST_st126_fsm_126 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_609_p2))) begin
ap_NS_fsm = ap_ST_st260_fsm_260;
end else if (((ap_ST_st126_fsm_126 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_609_p2))) begin
ap_NS_fsm = ap_ST_st127_fsm_127;
end else if ((ap_ST_st125_fsm_125 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st126_fsm_126;
end else if ((ap_ST_st124_fsm_124 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st125_fsm_125;
end else if ((ap_ST_st123_fsm_123 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st124_fsm_124;
end else if ((ap_ST_st122_fsm_122 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st123_fsm_123;
end else if ((ap_ST_st121_fsm_121 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st122_fsm_122;
end else if ((ap_ST_st120_fsm_120 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st121_fsm_121;
end else if ((ap_ST_st119_fsm_119 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st120_fsm_120;
end else if ((ap_ST_st118_fsm_118 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st119_fsm_119;
end else if ((ap_ST_st117_fsm_117 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st118_fsm_118;
end else if ((ap_ST_st116_fsm_116 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st117_fsm_117;
end else if ((ap_ST_st115_fsm_115 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st116_fsm_116;
end else if ((ap_ST_st114_fsm_114 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st115_fsm_115;
end else if ((ap_ST_st113_fsm_113 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st114_fsm_114;
end else if ((ap_ST_st112_fsm_112 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st113_fsm_113;
end else if ((ap_ST_st111_fsm_111 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st112_fsm_112;
end else if ((ap_ST_st110_fsm_110 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st111_fsm_111;
end else if ((ap_ST_st109_fsm_109 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st110_fsm_110;
end else if ((ap_ST_st108_fsm_108 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st109_fsm_109;
end else if (((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2))) begin
ap_NS_fsm = ap_ST_st108_fsm_108;
end else if (((ap_ST_st106_fsm_106 == ap_CS_fsm) & (~(ap_const_lv1_0 == tmp_13_reg_1267) | ~(ap_const_lv1_0 == tmp_28_reg_1373) | ~(ap_const_lv1_0 == grp_fu_600_p2)))) begin
ap_NS_fsm = ap_ST_st107_fsm_107;
end else if ((ap_ST_st104_fsm_104 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st105_fsm_105;
end else if ((ap_ST_st103_fsm_103 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st104_fsm_104;
end else if ((ap_ST_st102_fsm_102 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st103_fsm_103;
end else if ((ap_ST_st101_fsm_101 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st102_fsm_102;
end else if ((ap_ST_st100_fsm_100 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st101_fsm_101;
end else if ((ap_ST_st99_fsm_99 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st100_fsm_100;
end else if ((ap_ST_st98_fsm_98 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st99_fsm_99;
end else if ((ap_ST_st97_fsm_97 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st98_fsm_98;
end else if ((ap_ST_st96_fsm_96 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st97_fsm_97;
end else if ((ap_ST_st95_fsm_95 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st96_fsm_96;
end else if ((ap_ST_st94_fsm_94 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st95_fsm_95;
end else if ((ap_ST_st93_fsm_93 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st94_fsm_94;
end else if (((ap_ST_st92_fsm_92 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_596_p2))) begin
ap_NS_fsm = ap_ST_st93_fsm_93;
end else if ((ap_ST_st91_fsm_91 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st92_fsm_92;
end else if ((ap_ST_st90_fsm_90 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st91_fsm_91;
end else if ((ap_ST_st89_fsm_89 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st90_fsm_90;
end else if ((ap_ST_st88_fsm_88 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st89_fsm_89;
end else if ((ap_ST_st87_fsm_87 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st88_fsm_88;
end else if ((ap_ST_st86_fsm_86 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st87_fsm_87;
end else if ((ap_ST_st85_fsm_85 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st86_fsm_86;
end else if ((ap_ST_st84_fsm_84 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st85_fsm_85;
end else if ((ap_ST_st83_fsm_83 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st84_fsm_84;
end else if ((ap_ST_st82_fsm_82 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st83_fsm_83;
end else if ((ap_ST_st81_fsm_81 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st82_fsm_82;
end else if ((ap_ST_st80_fsm_80 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st81_fsm_81;
end else if ((ap_ST_st79_fsm_79 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st80_fsm_80;
end else if (((ap_ST_st105_fsm_105 == ap_CS_fsm) | ((ap_ST_st78_fsm_78 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_13_reg_1267)) | ((ap_ST_st92_fsm_92 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_596_p2)))) begin
ap_NS_fsm = ap_ST_st106_fsm_106;
end else if (((ap_ST_st78_fsm_78 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267))) begin
ap_NS_fsm = ap_ST_st79_fsm_79;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st78_fsm_78;
end else if ((ap_ST_st76_fsm_76 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st77_fsm_77;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st76_fsm_76;
end else if ((ap_ST_st74_fsm_74 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st75_fsm_75;
end else if ((ap_ST_st73_fsm_73 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st74_fsm_74;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st73_fsm_73;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st72_fsm_72;
end else if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st71_fsm_71;
end else if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st70_fsm_70;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond7_fu_1024_p2))) begin
ap_NS_fsm = ap_ST_st69_fsm_69;
end else if ((((ap_ST_st67_fsm_67 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond5_fu_987_p2)) | ((ap_ST_st391_fsm_391 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_do_rotate_fu_497_ap_done)) | ((ap_ST_st107_fsm_107 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_604_p2)) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267) & (ap_const_lv1_0 == tmp_28_reg_1373) & (ap_const_lv1_0 == grp_fu_600_p2)))) begin
ap_NS_fsm = ap_ST_st68_fsm_68;
end else if (((ap_ST_st399_fsm_399 == ap_CS_fsm) | ((ap_ST_st67_fsm_67 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond5_fu_987_p2)))) begin
ap_NS_fsm = ap_ST_st392_fsm_392;
end else if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | ((ap_ST_st68_fsm_68 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond7_fu_1024_p2)))) begin
ap_NS_fsm = ap_ST_st67_fsm_67;
end else if ((ap_ST_st64_fsm_64 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st65_fsm_65;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st64_fsm_64;
end else if ((ap_ST_st62_fsm_62 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st63_fsm_63;
end else if ((ap_ST_st61_fsm_61 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st62_fsm_62;
end else if ((ap_ST_st60_fsm_60 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st61_fsm_61;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st60_fsm_60;
end else if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st59_fsm_59;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st58_fsm_58;
end else if ((ap_ST_st56_fsm_56 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st57_fsm_57;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st56_fsm_56;
end else if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st55_fsm_55;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st54_fsm_54;
end else if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st53_fsm_53;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st52_fsm_52;
end else if ((ap_ST_st50_fsm_50 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st51_fsm_51;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st50_fsm_50;
end else if ((ap_ST_st48_fsm_48 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st49_fsm_49;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st48_fsm_48;
end else if ((ap_ST_st46_fsm_46 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st47_fsm_47;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st46_fsm_46;
end else if ((ap_ST_st44_fsm_44 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st45_fsm_45;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st44_fsm_44;
end else if ((ap_ST_st42_fsm_42 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st43_fsm_43;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st42_fsm_42;
end else if ((ap_ST_st40_fsm_40 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st41_fsm_41;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st40_fsm_40;
end else if ((ap_ST_st38_fsm_38 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st39_fsm_39;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st38_fsm_38;
end else if ((ap_ST_st36_fsm_36 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st37_fsm_37;
end else if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st36_fsm_36;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st35_fsm_35;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st34_fsm_34;
end else if ((ap_ST_st32_fsm_32 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st33_fsm_33;
end else if ((ap_ST_st31_fsm_31 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st32_fsm_32;
end else if ((ap_ST_st30_fsm_30 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st31_fsm_31;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st30_fsm_30;
end else if ((ap_ST_st28_fsm_28 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st29_fsm_29;
end else if ((ap_ST_st27_fsm_27 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st28_fsm_28;
end else if ((ap_ST_st26_fsm_26 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st27_fsm_27;
end else if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st26_fsm_26;
end else if ((ap_ST_st24_fsm_24 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st25_fsm_25;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st24_fsm_24;
end else if ((ap_ST_st22_fsm_22 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st23_fsm_23;
end else if (((ap_ST_st21_fsm_21 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_start) & ((ap_const_lv1_0 == tmp_6_reg_1191) | ~(ap_const_lv1_0 == grp_fu_583_p2)))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if (((ap_ST_st65_fsm_65 == ap_CS_fsm) | ((ap_ST_st21_fsm_21 == ap_CS_fsm) & (ap_const_lv1_0 == icmp_fu_939_p2) & ~(ap_const_lv1_0 == tmp_6_reg_1191) & (ap_const_lv1_0 == grp_fu_583_p2)))) begin
ap_NS_fsm = ap_ST_st66_fsm_66;
end else if (((ap_ST_st21_fsm_21 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_reg_1191) & (ap_const_lv1_0 == grp_fu_583_p2) & ~(ap_const_lv1_0 == icmp_fu_939_p2))) begin
ap_NS_fsm = ap_ST_st22_fsm_22;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st20_fsm_20;
end else if ((ap_ST_st18_fsm_18 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st19_fsm_19;
end else if ((ap_ST_st17_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st18_fsm_18;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st17_fsm_17;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st16_fsm_16;
end else if ((ap_ST_st14_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st15_fsm_15;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st14_fsm_14;
end else if ((ap_ST_st12_fsm_12 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st13_fsm_13;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st12_fsm_12;
end else if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st11_fsm_11;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st10_fsm_10;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond4_fu_880_p2))) begin
ap_NS_fsm = ap_ST_st9_fsm_9;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | ((ap_ST_st7_fsm_7 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond3_fu_868_p2)))) begin
ap_NS_fsm = ap_ST_st8_fsm_8;
end else if ((((ap_ST_st7_fsm_7 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_868_p2)) | ((ap_ST_st6_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_6_fu_836_p2)))) begin
ap_NS_fsm = ap_ST_st21_fsm_21;
end else if ((((ap_ST_st8_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond4_fu_880_p2)) | ((ap_ST_st6_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_fu_836_p2)))) begin
ap_NS_fsm = ap_ST_st7_fsm_7;
end else if ((((ap_ST_st392_fsm_392 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond6_fu_1112_p2)) | ((ap_ST_st4_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_790_p2)))) begin
ap_NS_fsm = ap_ST_st6_fsm_6;
end else if (((ap_ST_st4_fsm_4 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_790_p2))) begin
ap_NS_fsm = ap_ST_st5_fsm_5;
end else if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | ((ap_ST_st2_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_746_p2)))) begin
ap_NS_fsm = ap_ST_st4_fsm_4;
end else if ((((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0)) | ((ap_ST_st2_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_746_p2)))) begin
ap_NS_fsm = ap_ST_st3_fsm_3;
end else if ((((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0)) | (ap_ST_st1_fsm_1 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st2_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_ST_st21_fsm_21 == ap_CS_fsm) & (ap_const_logic_1 == ap_start) & ((ap_const_lv1_0 == tmp_6_reg_1191) | ~(ap_const_lv1_0 == grp_fu_583_p2))))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm or tmp_6_reg_1191 or grp_fu_583_p2)
begin
if (((ap_ST_st21_fsm_21 == ap_CS_fsm) & ((ap_const_lv1_0 == tmp_6_reg_1191) | ~(ap_const_lv1_0 == grp_fu_583_p2)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// b_address0 assign process. ///
always @ (ap_CS_fsm or tmp_22_fu_1124_p1 or exitcond6_fu_1112_p2 or b_addr_1_reg_1557 or tmp_2_fu_823_p1)
begin
if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
b_address0 = b_addr_1_reg_1557;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
b_address0 = tmp_2_fu_823_p1;
end else if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
b_address0 = tmp_22_fu_1124_p1;
end else begin
b_address0 = tmp_2_fu_823_p1;
end
end
/// b_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond6_fu_1112_p2)
begin
if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | ((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2)) | (ap_ST_st399_fsm_399 == ap_CS_fsm))) begin
b_ce0 = ap_const_logic_1;
end else begin
b_ce0 = ap_const_logic_0;
end
end
/// b_d0 assign process. ///
always @ (ap_CS_fsm or a_q0 or reg_649)
begin
if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
b_d0 = reg_649;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
b_d0 = a_q0;
end else begin
b_d0 = reg_649;
end
end
/// b_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st399_fsm_399 == ap_CS_fsm))) begin
b_we0 = ap_const_logic_1;
end else begin
b_we0 = ap_const_logic_0;
end
end
/// d_address0 assign process. ///
always @ (ap_CS_fsm or tmp_13_reg_1267 or d_addr_1_reg_1300 or tmp_26_reg_1355 or grp_fu_596_p2 or d_addr_4_gep_fu_211_p3 or d_addr_4_reg_1404 or grp_fu_604_p2 or tmp_22_reg_1552 or tmp_2_fu_823_p1)
begin
if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
d_address0 = tmp_22_reg_1552;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
d_address0 = tmp_2_fu_823_p1;
end else if ((ap_ST_st274_fsm_274 == ap_CS_fsm)) begin
d_address0 = d_addr_4_reg_1404;
end else if (((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2))) begin
d_address0 = d_addr_4_gep_fu_211_p3;
end else if (((ap_ST_st92_fsm_92 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_596_p2))) begin
d_address0 = tmp_26_reg_1355;
end else if (((ap_ST_st281_fsm_281 == ap_CS_fsm) | ((ap_ST_st78_fsm_78 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267)))) begin
d_address0 = d_addr_1_reg_1300;
end else begin
d_address0 = tmp_22_reg_1552;
end
end
/// d_address1 assign process. ///
always @ (ap_CS_fsm or d_addr_1_reg_1300 or d_addr_4_reg_1404 or grp_fu_604_p2)
begin
if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
d_address1 = d_addr_4_reg_1404;
end else if (((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2))) begin
d_address1 = d_addr_1_reg_1300;
end else begin
d_address1 = d_addr_4_reg_1404;
end
end
/// d_ce0 assign process. ///
always @ (ap_CS_fsm or tmp_13_reg_1267 or grp_fu_596_p2 or grp_fu_604_p2)
begin
if (((ap_ST_st274_fsm_274 == ap_CS_fsm) | (ap_ST_st5_fsm_5 == ap_CS_fsm) | ((ap_ST_st92_fsm_92 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_596_p2)) | ((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2)) | (ap_ST_st281_fsm_281 == ap_CS_fsm) | (ap_ST_st399_fsm_399 == ap_CS_fsm) | ((ap_ST_st78_fsm_78 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_1267)))) begin
d_ce0 = ap_const_logic_1;
end else begin
d_ce0 = ap_const_logic_0;
end
end
/// d_ce1 assign process. ///
always @ (ap_CS_fsm or grp_fu_604_p2)
begin
if ((((ap_ST_st107_fsm_107 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_604_p2)) | (ap_ST_st281_fsm_281 == ap_CS_fsm))) begin
d_ce1 = ap_const_logic_1;
end else begin
d_ce1 = ap_const_logic_0;
end
end
/// d_d0 assign process. ///
always @ (ap_CS_fsm or a_q0 or reg_649 or tmp_62_reg_1508)
begin
if ((ap_ST_st399_fsm_399 == ap_CS_fsm)) begin
d_d0 = reg_649;
end else if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
d_d0 = tmp_62_reg_1508;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
d_d0 = a_q0;
end else begin
d_d0 = tmp_62_reg_1508;
end
end
/// d_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st281_fsm_281 == ap_CS_fsm) | (ap_ST_st399_fsm_399 == ap_CS_fsm))) begin
d_we0 = ap_const_logic_1;
end else begin
d_we0 = ap_const_logic_0;
end
end
/// d_we1 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
d_we1 = ap_const_logic_1;
end else begin
d_we1 = ap_const_logic_0;
end
end
/// grp_do_rotate_fu_497_ap_start assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st390_fsm_390 == ap_CS_fsm)) begin
grp_do_rotate_fu_497_ap_start = ap_const_logic_1;
end else begin
grp_do_rotate_fu_497_ap_start = ap_const_logic_0;
end
end
/// grp_fu_509_opcode assign process. ///
always @ (ap_CS_fsm or tmp_i5_reg_1449)
begin
if (((ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st109_fsm_109 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | ((tmp_i5_reg_1449 == ap_const_lv1_1) & (ap_ST_st206_fsm_206 == ap_CS_fsm)) | (ap_ST_st255_fsm_255 == ap_CS_fsm) | (ap_ST_st276_fsm_276 == ap_CS_fsm))) begin
grp_fu_509_opcode = ap_const_lv2_1;
end else if (((ap_ST_st275_fsm_275 == ap_CS_fsm) | (ap_ST_st394_fsm_394 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_fu_509_opcode = ap_const_lv2_0;
end else begin
grp_fu_509_opcode = ap_const_lv2_1;
end
end
/// grp_fu_509_p0 assign process. ///
always @ (ap_CS_fsm or tmp_i5_reg_1449 or reg_675 or reg_684 or reg_710 or UnifiedRetVal_i_reg_1241 or UnifiedRetVal_i2_reg_1367 or UnifiedRetVal_i3_reg_1387 or UnifiedRetVal_i4_reg_1421 or b_load_reg_1577)
begin
if ((ap_ST_st394_fsm_394 == ap_CS_fsm)) begin
grp_fu_509_p0 = b_load_reg_1577;
end else if ((ap_ST_st276_fsm_276 == ap_CS_fsm)) begin
grp_fu_509_p0 = reg_710;
end else if ((ap_ST_st275_fsm_275 == ap_CS_fsm)) begin
grp_fu_509_p0 = reg_675;
end else if ((ap_ST_st120_fsm_120 == ap_CS_fsm)) begin
grp_fu_509_p0 = UnifiedRetVal_i4_reg_1421;
end else if ((ap_ST_st109_fsm_109 == ap_CS_fsm)) begin
grp_fu_509_p0 = reg_684;
end else if ((ap_ST_st100_fsm_100 == ap_CS_fsm)) begin
grp_fu_509_p0 = UnifiedRetVal_i3_reg_1387;
end else if ((ap_ST_st86_fsm_86 == ap_CS_fsm)) begin
grp_fu_509_p0 = UnifiedRetVal_i2_reg_1367;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
grp_fu_509_p0 = UnifiedRetVal_i_reg_1241;
end else if (((ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | ((tmp_i5_reg_1449 == ap_const_lv1_1) & (ap_ST_st206_fsm_206 == ap_CS_fsm)) | (ap_ST_st255_fsm_255 == ap_CS_fsm))) begin
grp_fu_509_p0 = ap_const_lv32_80000000;
end else begin
grp_fu_509_p0 = ap_const_lv32_80000000;
end
end
/// grp_fu_509_p1 assign process. ///
always @ (ap_CS_fsm or reg_640 or reg_649 or tmp_i5_reg_1449 or reg_675 or reg_684 or reg_710 or d_load_3_reg_1410 or theta_reg_1440 or tmp_47_reg_1469 or tmp_59_reg_1490 or sm_reg_376)
begin
if ((ap_ST_st394_fsm_394 == ap_CS_fsm)) begin
grp_fu_509_p1 = reg_710;
end else if ((ap_ST_st276_fsm_276 == ap_CS_fsm)) begin
grp_fu_509_p1 = tmp_59_reg_1490;
end else if ((ap_ST_st275_fsm_275 == ap_CS_fsm)) begin
grp_fu_509_p1 = ap_const_lv32_3F800000;
end else if ((ap_ST_st255_fsm_255 == ap_CS_fsm)) begin
grp_fu_509_p1 = tmp_47_reg_1469;
end else if (((tmp_i5_reg_1449 == ap_const_lv1_1) & (ap_ST_st206_fsm_206 == ap_CS_fsm))) begin
grp_fu_509_p1 = theta_reg_1440;
end else if ((ap_ST_st114_fsm_114 == ap_CS_fsm)) begin
grp_fu_509_p1 = reg_649;
end else if ((ap_ST_st109_fsm_109 == ap_CS_fsm)) begin
grp_fu_509_p1 = d_load_3_reg_1410;
end else if (((ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_fu_509_p1 = reg_675;
end else if (((ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm))) begin
grp_fu_509_p1 = reg_684;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
grp_fu_509_p1 = sm_reg_376;
end else if (((ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm))) begin
grp_fu_509_p1 = reg_640;
end else begin
grp_fu_509_p1 = ap_const_lv32_3F800000;
end
end
/// grp_fu_528_p0 assign process. ///
always @ (ap_CS_fsm or reg_640 or UnifiedRetVal_i1_fu_1066_p3 or theta_reg_1440 or t_phi_fu_465_p6 or t_reg_462)
begin
if ((ap_ST_st348_fsm_348 == ap_CS_fsm)) begin
grp_fu_528_p0 = t_reg_462;
end else if ((ap_ST_st272_fsm_272 == ap_CS_fsm)) begin
grp_fu_528_p0 = reg_640;
end else if ((ap_ST_st271_fsm_271 == ap_CS_fsm)) begin
grp_fu_528_p0 = t_phi_fu_465_p6;
end else if ((ap_ST_st171_fsm_171 == ap_CS_fsm)) begin
grp_fu_528_p0 = theta_reg_1440;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
grp_fu_528_p0 = UnifiedRetVal_i1_fu_1066_p3;
end else begin
grp_fu_528_p0 = t_reg_462;
end
end
/// grp_fu_528_p1 assign process. ///
always @ (ap_CS_fsm or theta_reg_1440 or c_reg_1523 or t_phi_fu_465_p6 or t_reg_462)
begin
if ((ap_ST_st348_fsm_348 == ap_CS_fsm)) begin
grp_fu_528_p1 = c_reg_1523;
end else if ((ap_ST_st272_fsm_272 == ap_CS_fsm)) begin
grp_fu_528_p1 = t_reg_462;
end else if ((ap_ST_st271_fsm_271 == ap_CS_fsm)) begin
grp_fu_528_p1 = t_phi_fu_465_p6;
end else if ((ap_ST_st171_fsm_171 == ap_CS_fsm)) begin
grp_fu_528_p1 = theta_reg_1440;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
grp_fu_528_p1 = ap_const_lv32_42C80000;
end else begin
grp_fu_528_p1 = ap_const_lv32_42C80000;
end
end
/// grp_fu_537_ce assign process. ///
always @ (ap_CS_fsm or grp_fu_609_p2)
begin
if (((ap_ST_st270_fsm_270 == ap_CS_fsm) | ((ap_ST_st126_fsm_126 == ap_CS_fsm) & ~(ap_const_lv1_0 == grp_fu_609_p2)) | (ap_ST_st260_fsm_260 == ap_CS_fsm) | (ap_ST_st261_fsm_261 == ap_CS_fsm) | (ap_ST_st262_fsm_262 == ap_CS_fsm) | (ap_ST_st263_fsm_263 == ap_CS_fsm) | (ap_ST_st264_fsm_264 == ap_CS_fsm) | (ap_ST_st265_fsm_265 == ap_CS_fsm) | (ap_ST_st266_fsm_266 == ap_CS_fsm) | (ap_ST_st267_fsm_267 == ap_CS_fsm) | (ap_ST_st268_fsm_268 == ap_CS_fsm) | (ap_ST_st269_fsm_269 == ap_CS_fsm))) begin
grp_fu_537_ce = ap_const_logic_1;
end else begin
grp_fu_537_ce = ap_const_logic_0;
end
end
/// grp_fu_557_ce assign process. ///
always @ (ap_CS_fsm or tmp_6_reg_1191 or icmp_fu_939_p2 or grp_fu_583_p2)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | ((ap_ST_st21_fsm_21 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_reg_1191) & (ap_const_lv1_0 == grp_fu_583_p2) & ~(ap_const_lv1_0 == icmp_fu_939_p2)))) begin
grp_fu_557_ce = ap_const_logic_1;
end else begin
grp_fu_557_ce = ap_const_logic_0;
end
end
/// grp_fu_561_ce assign process. ///
always @ (ap_CS_fsm or grp_fu_609_p2)
begin
if (((ap_ST_st127_fsm_127 == ap_CS_fsm) | ((ap_ST_st126_fsm_126 == ap_CS_fsm) & (ap_const_lv1_0 == grp_fu_609_p2)))) begin
grp_fu_561_ce = ap_const_logic_1;
end else begin
grp_fu_561_ce = ap_const_logic_0;
end
end
/// grp_fu_583_ce assign process. ///
always @ (ap_CS_fsm or tmp_6_reg_1191 or exitcond3_fu_868_p2)
begin
if ((((ap_ST_st7_fsm_7 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond3_fu_868_p2)) | ((ap_ST_st21_fsm_21 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_6_reg_1191)))) begin
grp_fu_583_ce = ap_const_logic_1;
end else begin
grp_fu_583_ce = ap_const_logic_0;
end
end
/// grp_fu_589_p0 assign process. ///
always @ (ap_CS_fsm or a_q0 or d_q0 or reg_649)
begin
if ((ap_ST_st114_fsm_114 == ap_CS_fsm)) begin
grp_fu_589_p0 = reg_649;
end else if (((ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm))) begin
grp_fu_589_p0 = d_q0;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm))) begin
grp_fu_589_p0 = a_q0;
end else begin
grp_fu_589_p0 = reg_649;
end
end
/// grp_fu_604_ce assign process. ///
always @ (ap_CS_fsm or tmp_13_reg_1267 or tmp_28_reg_1373 or grp_fu_600_p2)
begin
if (((ap_ST_st107_fsm_107 == ap_CS_fsm) | ((ap_ST_st106_fsm_106 == ap_CS_fsm) & (~(ap_const_lv1_0 == tmp_13_reg_1267) | ~(ap_const_lv1_0 == tmp_28_reg_1373) | ~(ap_const_lv1_0 == grp_fu_600_p2))))) begin
grp_fu_604_ce = ap_const_logic_1;
end else begin
grp_fu_604_ce = ap_const_logic_0;
end
end
/// grp_fu_618_p0 assign process. ///
always @ (ap_CS_fsm or tmp_42_reg_1454 or tmp_40_reg_1464 or tmp_56_reg_1529)
begin
if ((ap_ST_st349_fsm_349 == ap_CS_fsm)) begin
grp_fu_618_p0 = tmp_56_reg_1529;
end else if ((ap_ST_st213_fsm_213 == ap_CS_fsm)) begin
grp_fu_618_p0 = tmp_40_reg_1464;
end else if ((ap_ST_st177_fsm_177 == ap_CS_fsm)) begin
grp_fu_618_p0 = tmp_42_reg_1454;
end else begin
grp_fu_618_p0 = tmp_56_reg_1529;
end
end
/// grp_fu_618_p1 assign process. ///
always @ (ap_CS_fsm or reg_704)
begin
if ((ap_ST_st213_fsm_213 == ap_CS_fsm)) begin
grp_fu_618_p1 = reg_704;
end else if (((ap_ST_st177_fsm_177 == ap_CS_fsm) | (ap_ST_st349_fsm_349 == ap_CS_fsm))) begin
grp_fu_618_p1 = ap_const_lv64_3FF0000000000000;
end else begin
grp_fu_618_p1 = ap_const_lv64_3FF0000000000000;
end
end
/// grp_fu_623_p0 assign process. ///
always @ (ap_CS_fsm or tmp_s_reg_1257 or tmp_36_reg_1430)
begin
if ((ap_ST_st128_fsm_128 == ap_CS_fsm)) begin
grp_fu_623_p0 = tmp_36_reg_1430;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
grp_fu_623_p0 = tmp_s_reg_1257;
end else begin
grp_fu_623_p0 = tmp_36_reg_1430;
end
end
/// grp_fu_623_p1 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st128_fsm_128 == ap_CS_fsm)) begin
grp_fu_623_p1 = ap_const_lv64_3FE0000000000000;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
grp_fu_623_p1 = ap_const_lv64_3FC999999999999A;
end else begin
grp_fu_623_p1 = ap_const_lv64_3FE0000000000000;
end
end
/// grp_fu_629_p0 assign process. ///
always @ (ap_CS_fsm or reg_661 or tmp_55_reg_1534)
begin
if ((ap_ST_st355_fsm_355 == ap_CS_fsm)) begin
grp_fu_629_p0 = tmp_55_reg_1534;
end else if (((ap_ST_st219_fsm_219 == ap_CS_fsm) | (ap_ST_st312_fsm_312 == ap_CS_fsm))) begin
grp_fu_629_p0 = ap_const_lv64_3FF0000000000000;
end else if (((ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st135_fsm_135 == ap_CS_fsm))) begin
grp_fu_629_p0 = reg_661;
end else begin
grp_fu_629_p0 = ap_const_lv64_3FF0000000000000;
end
end
/// grp_fu_629_p1 assign process. ///
always @ (ap_CS_fsm or reg_698 or reg_704 or tmp_38_reg_1435)
begin
if ((ap_ST_st312_fsm_312 == ap_CS_fsm)) begin
grp_fu_629_p1 = reg_704;
end else if (((ap_ST_st219_fsm_219 == ap_CS_fsm) | (ap_ST_st355_fsm_355 == ap_CS_fsm))) begin
grp_fu_629_p1 = reg_698;
end else if ((ap_ST_st135_fsm_135 == ap_CS_fsm)) begin
grp_fu_629_p1 = tmp_38_reg_1435;
end else if ((ap_ST_st30_fsm_30 == ap_CS_fsm)) begin
grp_fu_629_p1 = ap_const_lv64_40D0000000000000;
end else begin
grp_fu_629_p1 = ap_const_lv64_40D0000000000000;
end
end
/// grp_fu_635_p1 assign process. ///
always @ (ap_CS_fsm or reg_698 or tmp_52_reg_1518)
begin
if ((ap_ST_st282_fsm_282 == ap_CS_fsm)) begin
grp_fu_635_p1 = tmp_52_reg_1518;
end else if ((ap_ST_st183_fsm_183 == ap_CS_fsm)) begin
grp_fu_635_p1 = reg_698;
end else begin
grp_fu_635_p1 = tmp_52_reg_1518;
end
end
/// nrot_o assign process. ///
always @ (ap_CS_fsm or exitcond1_fu_790_p2 or tmp_64_fu_1105_p2)
begin
if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
nrot_o = tmp_64_fu_1105_p2;
end else if (((ap_ST_st4_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_790_p2))) begin
nrot_o = ap_const_lv32_0;
end else begin
nrot_o = tmp_64_fu_1105_p2;
end
end
/// nrot_o_ap_vld assign process. ///
always @ (ap_CS_fsm or exitcond1_fu_790_p2 or grp_do_rotate_fu_497_ap_done)
begin
if ((((ap_ST_st4_fsm_4 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_790_p2)) | ((ap_ST_st391_fsm_391 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_do_rotate_fu_497_ap_done)))) begin
nrot_o_ap_vld = ap_const_logic_1;
end else begin
nrot_o_ap_vld = ap_const_logic_0;
end
end
/// v_address0 assign process. ///
always @ (ap_CS_fsm or tmp_9_cast_reg_1142 or exitcond2_fu_772_p2 or grp_do_rotate_fu_497_v_address0 or tmp_cast_fu_767_p1)
begin
if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
v_address0 = tmp_9_cast_reg_1142;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
v_address0 = tmp_cast_fu_767_p1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_address0 = grp_do_rotate_fu_497_v_address0;
end else begin
v_address0 = tmp_9_cast_reg_1142;
end
end
/// v_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_772_p2 or grp_do_rotate_fu_497_v_ce0)
begin
if ((((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0)) | ((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0)))) begin
v_ce0 = ap_const_logic_1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_ce0 = grp_do_rotate_fu_497_v_ce0;
end else begin
v_ce0 = ap_const_logic_0;
end
end
/// v_ce1 assign process. ///
always @ (ap_CS_fsm or grp_do_rotate_fu_497_v_ce1)
begin
if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_ce1 = grp_do_rotate_fu_497_v_ce1;
end else begin
v_ce1 = ap_const_logic_0;
end
end
/// v_d0 assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_772_p2 or grp_do_rotate_fu_497_v_d0)
begin
if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
v_d0 = ap_const_lv32_3F800000;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0))) begin
v_d0 = ap_const_lv32_0;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_d0 = grp_do_rotate_fu_497_v_d0;
end else begin
v_d0 = ap_const_lv32_3F800000;
end
end
/// v_we0 assign process. ///
always @ (ap_CS_fsm or exitcond2_fu_772_p2 or grp_do_rotate_fu_497_v_we0)
begin
if ((((ap_ST_st3_fsm_3 == ap_CS_fsm) & (exitcond2_fu_772_p2 == ap_const_lv1_0)) | ((ap_ST_st3_fsm_3 == ap_CS_fsm) & ~(exitcond2_fu_772_p2 == ap_const_lv1_0)))) begin
v_we0 = ap_const_logic_1;
end else if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_we0 = grp_do_rotate_fu_497_v_we0;
end else begin
v_we0 = ap_const_logic_0;
end
end
/// v_we1 assign process. ///
always @ (ap_CS_fsm or grp_do_rotate_fu_497_v_we1)
begin
if ((ap_ST_st391_fsm_391 == ap_CS_fsm)) begin
v_we1 = grp_do_rotate_fu_497_v_we1;
end else begin
v_we1 = ap_const_logic_0;
end
end
/// z_address0 assign process. ///
always @ (ap_CS_fsm or z_addr_1_reg_1306 or tmp_22_fu_1124_p1 or exitcond6_fu_1112_p2 or z_addr_2_reg_1562 or tmp_2_fu_823_p1)
begin
if ((ap_ST_st394_fsm_394 == ap_CS_fsm)) begin
z_address0 = z_addr_2_reg_1562;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
z_address0 = tmp_2_fu_823_p1;
end else if (((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2))) begin
z_address0 = tmp_22_fu_1124_p1;
end else if (((ap_ST_st274_fsm_274 == ap_CS_fsm) | (ap_ST_st281_fsm_281 == ap_CS_fsm))) begin
z_address0 = z_addr_1_reg_1306;
end else begin
z_address0 = tmp_2_fu_823_p1;
end
end
/// z_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond6_fu_1112_p2)
begin
if (((ap_ST_st274_fsm_274 == ap_CS_fsm) | (ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st281_fsm_281 == ap_CS_fsm) | ((ap_ST_st392_fsm_392 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond6_fu_1112_p2)) | (ap_ST_st394_fsm_394 == ap_CS_fsm))) begin
z_ce0 = ap_const_logic_1;
end else begin
z_ce0 = ap_const_logic_0;
end
end
/// z_ce1 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st274_fsm_274 == ap_CS_fsm) | (ap_ST_st281_fsm_281 == ap_CS_fsm))) begin
z_ce1 = ap_const_logic_1;
end else begin
z_ce1 = ap_const_logic_0;
end
end
/// z_d0 assign process. ///
always @ (ap_CS_fsm or reg_692)
begin
if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
z_d0 = reg_692;
end else if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st394_fsm_394 == ap_CS_fsm))) begin
z_d0 = ap_const_lv32_0;
end else begin
z_d0 = ap_const_lv32_0;
end
end
/// z_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st281_fsm_281 == ap_CS_fsm) | (ap_ST_st394_fsm_394 == ap_CS_fsm))) begin
z_we0 = ap_const_logic_1;
end else begin
z_we0 = ap_const_logic_0;
end
end
/// z_we1 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st281_fsm_281 == ap_CS_fsm)) begin
z_we1 = ap_const_logic_1;
end else begin
z_we1 = ap_const_logic_0;
end
end
assign UnifiedRetVal_i1_fu_1066_p3 = ((tmp_i1_reg_1344)? reg_649: reg_640);
assign a_addr1_fu_1049_p2 = (a_addr_cast_fu_1045_p1 + tmp_21_fu_1018_p2);
assign a_addr2_cast_fu_901_p1 = {{17{1'b0}}, {a_addr2_fu_895_p2}};
assign a_addr2_fu_895_p2 = tmp_9_trn_cast_fu_891_p1 << ap_const_lv15_7;
assign a_addr3_fu_905_p2 = (a_addr2_cast_fu_901_p1 + iq_1_fu_874_p2);
assign a_addr6_fu_812_p2 = (p_shl_fu_806_p2 + tmp_2_trn_cast_fu_802_p1);
assign a_addr_2_reg_13340 = {{32{a_addr1_fu_1049_p2[31]}}, {a_addr1_fu_1049_p2}};
assign a_addr_cast_fu_1045_p1 = {{17{1'b0}}, {a_addr_fu_1039_p2}};
assign a_addr_fu_1039_p2 = tmp_20_trn_cast_fu_1035_p1 << ap_const_lv15_7;
assign a_address1 = grp_do_rotate_fu_497_a_address1;
assign a_d1 = grp_do_rotate_fu_497_a_d1;
assign b_addr_1_reg_15570 = {{56{1'b0}}, {ip_4_reg_485}};
assign d_addr_1_reg_13000 = {{56{1'b0}}, {tmp_17_reg_422}};
assign d_addr_4_gep_fu_211_p3 = tmp_26_reg_1355;
assign d_d1 = tmp_63_reg_1513;
assign exitcond1_fu_790_p2 = (indvar4_reg_286 == ap_const_lv8_80? 1'b1: 1'b0);
assign exitcond2_fu_772_p2 = (indvar5_reg_275 == ap_const_lv8_80? 1'b1: 1'b0);
assign exitcond3_fu_868_p2 = (indvar7_reg_321 == ap_const_lv7_7F? 1'b1: 1'b0);
assign exitcond4_fu_880_p2 = (indvar8_reg_356 == tmp4_reg_1195? 1'b1: 1'b0);
assign exitcond5_fu_987_p2 = (indvar9_reg_400 == ap_const_lv7_7F? 1'b1: 1'b0);
assign exitcond6_fu_1112_p2 = (indvar_reg_474 == ap_const_lv8_80? 1'b1: 1'b0);
assign exitcond7_fu_1024_p2 = (indvar1_reg_434 == tmp5_reg_1271? 1'b1: 1'b0);
assign exitcond_fu_746_p2 = (indvar2_reg_253 == ap_const_lv8_80? 1'b1: 1'b0);
assign grp_do_rotate_fu_497_a_q0 = a_q0;
assign grp_do_rotate_fu_497_a_q1 = a_q1;
assign grp_do_rotate_fu_497_ip = tmp_18_reg_1276;
assign grp_do_rotate_fu_497_iq = iq_2_reg_1311;
assign grp_do_rotate_fu_497_s = reg_675;
assign grp_do_rotate_fu_497_tau = tau_reg_1539;
assign grp_do_rotate_fu_497_v_q0 = v_q0;
assign grp_do_rotate_fu_497_v_q1 = v_q1;
assign grp_fu_509_ce = ap_const_logic_1;
assign grp_fu_516_ce = ap_const_logic_1;
assign grp_fu_516_p0 = z_load_2_reg_1498;
assign grp_fu_516_p1 = tmp_59_reg_1490;
assign grp_fu_520_ce = ap_const_logic_1;
assign grp_fu_520_p0 = d_load_3_reg_1410;
assign grp_fu_520_p1 = tmp_59_reg_1490;
assign grp_fu_524_ce = ap_const_logic_1;
assign grp_fu_524_p0 = reg_684;
assign grp_fu_524_p1 = tmp_59_reg_1490;
assign grp_fu_528_ce = ap_const_logic_1;
assign grp_fu_537_p0 = reg_640;
assign grp_fu_537_p1 = reg_649;
assign grp_fu_541_ce = ap_const_logic_1;
assign grp_fu_541_p0 = reg_666;
assign grp_fu_544_ce = ap_const_logic_1;
assign grp_fu_544_p0 = reg_666;
assign grp_fu_547_ce = ap_const_logic_1;
assign grp_fu_547_p0 = reg_666;
assign grp_fu_550_ce = ap_const_logic_1;
assign grp_fu_550_p0 = reg_666;
assign grp_fu_553_ce = ap_const_logic_1;
assign grp_fu_553_p0 = reg_666;
assign grp_fu_557_p0 = sm_1_reg_344;
assign grp_fu_561_p0 = reg_649;
assign grp_fu_564_ce = ap_const_logic_1;
assign grp_fu_564_p0 = reg_640;
assign grp_fu_567_ce = ap_const_logic_1;
assign grp_fu_567_p0 = reg_675;
assign grp_fu_570_ce = ap_const_logic_1;
assign grp_fu_570_p0 = ((tmp_i5_reg_1449)? reg_649: theta_reg_1440);
assign grp_fu_573_ce = ap_const_logic_1;
assign grp_fu_573_p0 = reg_649;
assign grp_fu_576_ce = ap_const_logic_1;
assign grp_fu_576_p0 = grp_fu_550_p1;
assign grp_fu_580_ce = ap_const_logic_1;
assign grp_fu_580_p0 = reg_675;
assign grp_fu_583_opcode = ap_const_lv5_1;
assign grp_fu_583_p0 = sm_1_reg_344;
assign grp_fu_583_p1 = ap_const_lv32_0;
assign grp_fu_589_ce = ap_const_logic_1;
assign grp_fu_589_opcode = ap_const_lv5_4;
assign grp_fu_589_p1 = ap_const_lv32_0;
assign grp_fu_596_ce = ap_const_logic_1;
assign grp_fu_596_opcode = ap_const_lv5_E;
assign grp_fu_596_p0 = reg_649;
assign grp_fu_596_p1 = UnifiedRetVal_i2_reg_1367;
assign grp_fu_600_ce = ap_const_logic_1;
assign grp_fu_600_opcode = ap_const_lv5_E;
assign grp_fu_600_p0 = tmp_29_reg_1393;
assign grp_fu_600_p1 = UnifiedRetVal_i3_reg_1387;
assign grp_fu_604_opcode = ap_const_lv5_2;
assign grp_fu_604_p0 = UnifiedRetVal_i1_reg_1349;
assign grp_fu_604_p1 = tresh_reg_388;
assign grp_fu_609_ce = ap_const_logic_1;
assign grp_fu_609_opcode = ap_const_lv5_1;
assign grp_fu_609_p0 = reg_692;
assign grp_fu_609_p1 = UnifiedRetVal_i4_reg_1421;
assign grp_fu_613_ce = ap_const_logic_1;
assign grp_fu_613_opcode = ap_const_lv5_4;
assign grp_fu_613_p0 = theta_reg_1440;
assign grp_fu_613_p1 = ap_const_lv32_0;
assign grp_fu_618_ce = ap_const_logic_1;
assign grp_fu_623_ce = ap_const_logic_1;
assign grp_fu_629_ce = ap_const_logic_1;
assign grp_fu_635_ce = ap_const_logic_1;
assign grp_fu_635_p0 = ap_const_lv64_1;
assign icmp_fu_939_p2 = ($signed(tmp_5_fu_929_p4) < $signed(30'b000000000000000000000000000001)? 1'b1: 1'b0);
assign indvar1_cast_fu_999_p1 = {{1{1'b0}}, {indvar1_reg_434}};
assign indvar30_cast_fu_716_p1 = {{7{1'b0}}, {indvar2_reg_253}};
assign indvar34_cast_fu_758_p1 = indvar6_reg_264[15:0];
assign indvar3_cast1_fu_963_p1 = {{1{1'b0}}, {indvar3_reg_411}};
assign indvar3_cast_fu_967_p1 = {{2{1'b0}}, {indvar3_reg_411}};
assign indvar7_cast_fu_848_p1 = {{1{1'b0}}, {indvar7_reg_321}};
assign ip_2_fu_852_p2 = (indvar7_cast_fu_848_p1 + ap_const_lv8_1);
assign ip_3_fu_971_p2 = (indvar3_cast1_fu_963_p1 + ap_const_lv8_1);
assign iq_1_fu_874_p2 = (iq_1_in_reg_367 + ap_const_lv32_1);
assign p_shl_fu_806_p2 = tmp_2_trn_cast_fu_802_p1 << ap_const_lv16_7;
assign t_phi_fu_465_p6 = t_reg_462;
assign tmp1_fu_720_p2 = indvar30_cast_fu_716_p1 << ap_const_lv15_7;
assign tmp2_fu_736_p2 = (tmp1_fu_720_p2 + ap_const_lv15_81);
assign tmp36_cast_fu_742_p1 = {{1{1'b0}}, {tmp2_fu_736_p2}};
assign tmp3_cast_fu_1009_p1 = {{1{1'b0}}, {tmp3_fu_1003_p2}};
assign tmp3_fu_1003_p2 = (indvar1_cast_fu_999_p1 + ap_const_lv8_2);
assign tmp_15_fu_911_p1 = {{32{a_addr3_fu_905_p2[31]}}, {a_addr3_fu_905_p2}};
assign tmp_1_fu_818_p1 = {{48{1'b0}}, {a_addr6_fu_812_p2}};
assign tmp_20_trn_cast_fu_1035_p1 = {{7{1'b0}}, {tmp_17_reg_422}};
assign tmp_21_fu_1018_p2 = (iq_2_in_reg_449 + ap_const_lv32_1);
assign tmp_22_fu_1124_p1 = {{56{1'b0}}, {ip_4_reg_485}};
assign tmp_2_fu_823_p1 = {{56{1'b0}}, {ip_1_reg_297}};
assign tmp_2_trn_cast_fu_802_p1 = {{8{1'b0}}, {ip_1_reg_297}};
assign tmp_48_fu_1055_p1 = {{32{a_addr1_fu_1049_p2[31]}}, {a_addr1_fu_1049_p2}};
assign tmp_5_fu_929_p4 = {{indvar10_reg_309[ap_const_lv32_1F : ap_const_lv32_2]}};
assign tmp_64_fu_1105_p2 = (nrot_i + ap_const_lv32_1);
assign tmp_6_fu_836_p2 = ($signed(indvar10_reg_309) < $signed(32'b00000000000000000000000000110011)? 1'b1: 1'b0);
assign tmp_9_cast_fu_732_p1 = {{49{1'b0}}, {tmp_9_fu_726_p2}};
assign tmp_9_fu_726_p2 = (tmp1_fu_720_p2 + ap_const_lv15_101);
assign tmp_9_trn_cast_fu_891_p1 = {{7{1'b0}}, {tmp_7_reg_332}};
assign tmp_cast_fu_767_p1 = {{48{1'b0}}, {tmp_fu_762_p2}};
assign tmp_fu_762_p2 = (tmp36_cast_reg_1147 + indvar34_cast_fu_758_p1);
assign v_address1 = grp_do_rotate_fu_497_v_address1;
assign v_d1 = grp_do_rotate_fu_497_v_d1;
assign z_addr_1_reg_13060 = {{56{1'b0}}, {tmp_17_reg_422}};
assign z_addr_2_reg_15620 = {{56{1'b0}}, {ip_4_reg_485}};
assign z_address1 = z_addr_3_reg_1485;
assign z_d1 = tmp_61_reg_1503;
always @ (ap_clk)
begin
tmp_9_cast_reg_1142[0] <= 1'b1;
tmp_9_cast_reg_1142[1] <= 1'b0;
tmp_9_cast_reg_1142[2] <= 1'b0;
tmp_9_cast_reg_1142[3] <= 1'b0;
tmp_9_cast_reg_1142[4] <= 1'b0;
tmp_9_cast_reg_1142[5] <= 1'b0;
tmp_9_cast_reg_1142[6] <= 1'b0;
tmp_9_cast_reg_1142[15] <= 1'b0;
tmp_9_cast_reg_1142[16] <= 1'b0;
tmp_9_cast_reg_1142[17] <= 1'b0;
tmp_9_cast_reg_1142[18] <= 1'b0;
tmp_9_cast_reg_1142[19] <= 1'b0;
tmp_9_cast_reg_1142[20] <= 1'b0;
tmp_9_cast_reg_1142[21] <= 1'b0;
tmp_9_cast_reg_1142[22] <= 1'b0;
tmp_9_cast_reg_1142[23] <= 1'b0;
tmp_9_cast_reg_1142[24] <= 1'b0;
tmp_9_cast_reg_1142[25] <= 1'b0;
tmp_9_cast_reg_1142[26] <= 1'b0;
tmp_9_cast_reg_1142[27] <= 1'b0;
tmp_9_cast_reg_1142[28] <= 1'b0;
tmp_9_cast_reg_1142[29] <= 1'b0;
tmp_9_cast_reg_1142[30] <= 1'b0;
tmp_9_cast_reg_1142[31] <= 1'b0;
tmp_9_cast_reg_1142[32] <= 1'b0;
tmp_9_cast_reg_1142[33] <= 1'b0;
tmp_9_cast_reg_1142[34] <= 1'b0;
tmp_9_cast_reg_1142[35] <= 1'b0;
tmp_9_cast_reg_1142[36] <= 1'b0;
tmp_9_cast_reg_1142[37] <= 1'b0;
tmp_9_cast_reg_1142[38] <= 1'b0;
tmp_9_cast_reg_1142[39] <= 1'b0;
tmp_9_cast_reg_1142[40] <= 1'b0;
tmp_9_cast_reg_1142[41] <= 1'b0;
tmp_9_cast_reg_1142[42] <= 1'b0;
tmp_9_cast_reg_1142[43] <= 1'b0;
tmp_9_cast_reg_1142[44] <= 1'b0;
tmp_9_cast_reg_1142[45] <= 1'b0;
tmp_9_cast_reg_1142[46] <= 1'b0;
tmp_9_cast_reg_1142[47] <= 1'b0;
tmp_9_cast_reg_1142[48] <= 1'b0;
tmp_9_cast_reg_1142[49] <= 1'b0;
tmp_9_cast_reg_1142[50] <= 1'b0;
tmp_9_cast_reg_1142[51] <= 1'b0;
tmp_9_cast_reg_1142[52] <= 1'b0;
tmp_9_cast_reg_1142[53] <= 1'b0;
tmp_9_cast_reg_1142[54] <= 1'b0;
tmp_9_cast_reg_1142[55] <= 1'b0;
tmp_9_cast_reg_1142[56] <= 1'b0;
tmp_9_cast_reg_1142[57] <= 1'b0;
tmp_9_cast_reg_1142[58] <= 1'b0;
tmp_9_cast_reg_1142[59] <= 1'b0;
tmp_9_cast_reg_1142[60] <= 1'b0;
tmp_9_cast_reg_1142[61] <= 1'b0;
tmp_9_cast_reg_1142[62] <= 1'b0;
tmp_9_cast_reg_1142[63] <= 1'b0;
end
always @ (ap_clk)
begin
tmp36_cast_reg_1147[0] <= 1'b1;
tmp36_cast_reg_1147[1] <= 1'b0;
tmp36_cast_reg_1147[2] <= 1'b0;
tmp36_cast_reg_1147[3] <= 1'b0;
tmp36_cast_reg_1147[4] <= 1'b0;
tmp36_cast_reg_1147[5] <= 1'b0;
tmp36_cast_reg_1147[6] <= 1'b0;
tmp36_cast_reg_1147[15] <= 1'b0;
end
always @ (ap_clk)
begin
indvar3_cast_reg_1282[7] <= 1'b0;
indvar3_cast_reg_1282[8] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_22_reg_1552[8] <= 1'b0;
tmp_22_reg_1552[9] <= 1'b0;
tmp_22_reg_1552[10] <= 1'b0;
tmp_22_reg_1552[11] <= 1'b0;
tmp_22_reg_1552[12] <= 1'b0;
tmp_22_reg_1552[13] <= 1'b0;
tmp_22_reg_1552[14] <= 1'b0;
tmp_22_reg_1552[15] <= 1'b0;
tmp_22_reg_1552[16] <= 1'b0;
tmp_22_reg_1552[17] <= 1'b0;
tmp_22_reg_1552[18] <= 1'b0;
tmp_22_reg_1552[19] <= 1'b0;
tmp_22_reg_1552[20] <= 1'b0;
tmp_22_reg_1552[21] <= 1'b0;
tmp_22_reg_1552[22] <= 1'b0;
tmp_22_reg_1552[23] <= 1'b0;
tmp_22_reg_1552[24] <= 1'b0;
tmp_22_reg_1552[25] <= 1'b0;
tmp_22_reg_1552[26] <= 1'b0;
tmp_22_reg_1552[27] <= 1'b0;
tmp_22_reg_1552[28] <= 1'b0;
tmp_22_reg_1552[29] <= 1'b0;
tmp_22_reg_1552[30] <= 1'b0;
tmp_22_reg_1552[31] <= 1'b0;
tmp_22_reg_1552[32] <= 1'b0;
tmp_22_reg_1552[33] <= 1'b0;
tmp_22_reg_1552[34] <= 1'b0;
tmp_22_reg_1552[35] <= 1'b0;
tmp_22_reg_1552[36] <= 1'b0;
tmp_22_reg_1552[37] <= 1'b0;
tmp_22_reg_1552[38] <= 1'b0;
tmp_22_reg_1552[39] <= 1'b0;
tmp_22_reg_1552[40] <= 1'b0;
tmp_22_reg_1552[41] <= 1'b0;
tmp_22_reg_1552[42] <= 1'b0;
tmp_22_reg_1552[43] <= 1'b0;
tmp_22_reg_1552[44] <= 1'b0;
tmp_22_reg_1552[45] <= 1'b0;
tmp_22_reg_1552[46] <= 1'b0;
tmp_22_reg_1552[47] <= 1'b0;
tmp_22_reg_1552[48] <= 1'b0;
tmp_22_reg_1552[49] <= 1'b0;
tmp_22_reg_1552[50] <= 1'b0;
tmp_22_reg_1552[51] <= 1'b0;
tmp_22_reg_1552[52] <= 1'b0;
tmp_22_reg_1552[53] <= 1'b0;
tmp_22_reg_1552[54] <= 1'b0;
tmp_22_reg_1552[55] <= 1'b0;
tmp_22_reg_1552[56] <= 1'b0;
tmp_22_reg_1552[57] <= 1'b0;
tmp_22_reg_1552[58] <= 1'b0;
tmp_22_reg_1552[59] <= 1'b0;
tmp_22_reg_1552[60] <= 1'b0;
tmp_22_reg_1552[61] <= 1'b0;
tmp_22_reg_1552[62] <= 1'b0;
tmp_22_reg_1552[63] <= 1'b0;
end
endmodule //jacob
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_b_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd7;
parameter WORD_COUNT=32'd128;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module jacob_b (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
jacob_b_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_509_ACMP_faddfsub_11(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_516_ACMP_fadd_12(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_520_ACMP_fsub_13(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_524_ACMP_fadd_14(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_528_ACMP_fmul_15(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_537_ACMP_fdiv_16(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fdiv #(
.ID( ID ),
.NUM_STAGE( 12 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fdiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_541_ACMP_fptrunc_17(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fptrunc #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fptrunc_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_544_ACMP_fptrunc_18(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fptrunc #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fptrunc_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_547_ACMP_fptrunc_19(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fptrunc #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fptrunc_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_550_ACMP_fptrunc_20(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fptrunc #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fptrunc_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_553_ACMP_fptrunc_21(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fptrunc #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fptrunc_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_557_ACMP_fpext_22(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_561_ACMP_fpext_23(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_564_ACMP_fpext_24(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_567_ACMP_fpext_25(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_570_ACMP_fpext_26(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_573_ACMP_fpext_27(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_576_ACMP_fpext_28(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_580_ACMP_fpext_29(
clk,
reset,
ce,
din0,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
output[dout_WIDTH - 1:0] dout;
ACMP_fpext #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fpext_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_583_ACMP_fcmp_30(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_589_ACMP_fcmp_31(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_596_ACMP_fcmp_32(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_600_ACMP_fcmp_33(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_604_ACMP_fcmp_34(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_609_ACMP_fcmp_35(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_613_ACMP_fcmp_36(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 2 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_618_ACMP_dadd_37(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_dadd #(
.ID( ID ),
.NUM_STAGE( 6 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_dadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_623_ACMP_dmul_38(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_dmul #(
.ID( ID ),
.NUM_STAGE( 7 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_dmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_629_ACMP_ddiv_39(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_ddiv #(
.ID( ID ),
.NUM_STAGE( 34 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_ddiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_grp_fu_635_ACMP_dsqrt_40(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_dsqrt #(
.ID( ID ),
.NUM_STAGE( 30 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_dsqrt_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacob_z_core (q, ra, ce, clk
, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd2;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd7;
parameter WORD_COUNT=32'd128;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
genvar x;
generate
for (x = 0; x < READ_PORT_COUNT; x = x + 1) begin : gen_q
assign q[x*DATA_WIDTH+DATA_WIDTH-1:x*DATA_WIDTH] = (rai_reg[x]<WORD_COUNT)?
mem[rai_reg[x]] : {DATA_WIDTH{1'b0}};
end
endgenerate
endmodule
module jacob_z (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
we1,
d1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input we1;
input[DataWidth-1:0] d1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[2 - 1:0] mem_we;
wire[2 * DataWidth - 1:0] mem_d;
wire[2 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
jacob_z_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 2 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[1] = we0;
assign mem_we[0] = we1;
assign mem_d = {d0, d1};
assign mem_wa = {address0, address1};
endmodule
|
//----------------------------------------------------------------------------//
// Generated by LegUp High-Level Synthesis Tool Version 2.0 (http://legup.org)
// University of Toronto
// Date: Fri Jul 6 17:21:11 2012
// For research and academic purposes only. Commercial use is prohibited.
// Please send bugs to: [email protected]
//----------------------------------------------------------------------------//
`define MEMORY_CONTROLLER_ADDR_SIZE 32
`define MEMORY_CONTROLLER_DATA_SIZE 64
// Number of RAM elements: 55
`define MEMORY_CONTROLLER_TAG_SIZE 9
`define TAG_NULL `MEMORY_CONTROLLER_TAG_SIZE'd0
`define TAG_PROCESSOR `MEMORY_CONTROLLER_TAG_SIZE'd1
// %QuantBuff = alloca [64 x i32], align 4
`define TAG_decode_block_0_QuantBuff `MEMORY_CONTROLLER_TAG_SIZE'd52
`define TAG_decode_block_0_QuantBuff_a {`TAG_decode_block_0_QuantBuff, 23'b0}
// @CurHuffReadBuf = internal unnamed_addr global i8* null, align 4
`define TAG_g_CurHuffReadBuf `MEMORY_CONTROLLER_TAG_SIZE'd34
`define TAG_g_CurHuffReadBuf_a {`TAG_g_CurHuffReadBuf, 23'b0}
// @JpegFileBuf = internal global [5310 x i8] zeroinitializer, align 1
`define TAG_g_JpegFileBuf `MEMORY_CONTROLLER_TAG_SIZE'd51
`define TAG_g_JpegFileBuf_a {`TAG_g_JpegFileBuf, 23'b0}
// @OutData_comp_buf = internal global [3 x [5310 x i8]] zeroinitializer, align 1
`define TAG_g_OutData_comp_buf `MEMORY_CONTROLLER_TAG_SIZE'd35
`define TAG_g_OutData_comp_buf_a {`TAG_g_OutData_comp_buf, 23'b0}
// @OutData_comp_hpos = internal global [3 x i32] zeroinitializer, align 4
`define TAG_g_OutData_comp_hpos `MEMORY_CONTROLLER_TAG_SIZE'd50
`define TAG_g_OutData_comp_hpos_a {`TAG_g_OutData_comp_hpos, 23'b0}
// @OutData_comp_vpos = internal global [3 x i32] zeroinitializer, align 4
`define TAG_g_OutData_comp_vpos `MEMORY_CONTROLLER_TAG_SIZE'd49
`define TAG_g_OutData_comp_vpos_a {`TAG_g_OutData_comp_vpos, 23'b0}
// @bit_set_mask = internal unnamed_addr constant [32 x i32] [i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 512, i32 1024, i32 2048, i32 4096, i32 8192, i32 16384, i32 32768, i32 65536, i32 131072, i32 262144, i32 524288, i32 1048576, i32 2097152, i32 4194304, i32 8388608, i32 16777216, i32 33554432, i32 67108864, i32 134217728, i32 268435456, i32 536870912, i32 1073741824, i32 -2147483648], align 4
`define TAG_g_bit_set_mask `MEMORY_CONTROLLER_TAG_SIZE'd36
`define TAG_g_bit_set_mask_a {`TAG_g_bit_set_mask, 23'b0}
// @current_read_byte = internal unnamed_addr global i32 0, align 4
`define TAG_g_current_read_byte `MEMORY_CONTROLLER_TAG_SIZE'd39
`define TAG_g_current_read_byte_a {`TAG_g_current_read_byte, 23'b0}
// @extend_mask = internal unnamed_addr constant [20 x i32] [i32 -2, i32 -4, i32 -8, i32 -16, i32 -32, i32 -64, i32 -128, i32 -256, i32 -512, i32 -1024, i32 -2048, i32 -4096, i32 -8192, i32 -16384, i32 -32768, i32 -65536, i32 -131072, i32 -262144, i32 -524288, i32 -1048576], align 4
`define TAG_g_extend_mask `MEMORY_CONTROLLER_TAG_SIZE'd44
`define TAG_g_extend_mask_a {`TAG_g_extend_mask, 23'b0}
// @hana_bmp = internal unnamed_addr constant [3 x [5310 x i8]] [[5310 x i8] c"\BC\D1\BE\99\8Fg\95\C0\AC\9D\BD\C0\A4\C3\BC\B5\C1\A7\BC\D2\B1\8E%\0A\1F('4 \1D\22\0E\0A\12\0E\1A\07l\B5\BE\B5\7F[cI$\0B$B]ZA3 $#&58#\19\19 1)6 \1F\1F\22\18\19&+ \0B\09\0D\14\19\17\11\10\12\1E\19!-$\1D\A6\C1eZ\AA\81\92\D5\A9X\91\C7\CF\A5\89q\C9\9B\8B\D1\BF\C9\ABg3\1D\11\09\1D+!$\18\0E\18\18\04l\B9\B4\BA\BC\B7\C3\C0l0KgUE1.7,*23)\1E\12\0E\1E006\22(&$\1F\1C47-\0F\0E\10\17\15\0F\0B\11\19\1F\1A,I\22'\91\84.\B5\CD\D1\BB\AA\8C84\8Ez\B0\C6S\9A\D7\C8\D1\B8\A4\C4\AE\807YL\1C&/.#\1B'\1F\10:t\89\A9\B8\B4\AF\A6xI[aT $>:()0- \14\0F\10\0C\1B\18$(\10\22\18\16!=A7\12\15\16\1D\13\12\0F\15\1C!\1D0K$&o\0F>\E2\CF\BB\CD\BC=\02\0D\1F\09i\8C1\18\BF\D1\C6\BA\B8\93uY:\8A\B3\87>43\17\14\22\1C\1A\0A*p\97\9D\8Bzq6OT`.\13 5:(('&\15\15\11\17\06ne\0E\12\07\0F\1B\07\1B@F?\16\1E &\16\08\0A\12\14\1A\1B+:,(\8B\8C\81\9Cq\B1\D7\AEoe$\0E\14\8BbjQ%a\DF\C8\D9\95\99\94\83F\92\B2\AC\83P\0D\11+\10\12\14\18b\82\A3\90UGQNXD\1D'8;1()'\14\0B?P\01Y\B3\BA`\00%\0F\15\14\1B@LI\1D\1F!+\22\0D\0C\13\10\10\0E\1C&<2\B3\C4\D9\847y\D5\B4\B1\B7\AEf\A1\B6\8C\93\C5\CE\A4\D6\D9\AF(\8D\AE\B7{Daw{~1\15'\11\17\1C\0E{\95\C2\C1_KIF?;207:*06 $\0CU\9Fn}\B1\BB\89\196:7\12\13;ML\22\1E 0/\22\12\0D\0D\0C\05\0C\1249\88\86\AF\D6\86\A1\BE\8D\B1\BD\8D\A4\CB\B3\B9\90I\8D\CE\94\B5\C0qE\95\B0\8DtS.epO\1F\19(\1E\1A\0Cb\A2\C3\[email protected]$,/\1B7\B1\C8\AF\A9\B2\9Cr~k=.2<NL.*0;:-\19\14\16\1A\13\13\0F8:)r\C4\C3\D0\C5\BA\B0\AE\CCy\88\D0\CD\C9V\0C\BE\B4\B1\94\B2\DD\91a\92\88\99\A9\8A\93\BF\A79/\A8|!\056\BD\B4\C5\BC\88D6?2NSJPZ:,<-,\12\80\C2\B0\C9\CB\C4\AF\8Ek=,=JVS>@GH??7941'$\18=9\13K\C2\A5\A8\BA\C4\BB\CB\CFVA\82\C0\D6\B8\90\AE\B4\D1\93Llt\9B\9A\BB\AC\B3\B4\BB\C7\CC96\A5\7F/ZC\BD\B3\AA\D6\C3\9Fg( @aB55CM./'\0A5z\97\CA\D5\D6\BC\A1\91j<:N]aefVUG927664+(\15\16q\0B.Bh\8C\A4\A7\B1\D2Gsi\BE\A3\B5\BB\B8\8E\B1k\CF\80qy\9C\99\8F\A1\9A\A5\B6\B67-t*4x^}\B4\BB\BA\C7\BF\BAN\00+`vR\13LLG7\1D\09\08;o\A8\BD\CD\BB\A6\8Ao2)7L^kte\5CH32/'+%\1D(\19\1BdD3.8Q\5C\98\B0\CAG\8E\CF\C4\C5\90\B5\B5ixO@\B3pfa@?3^\B4\A4\93%D\A9^da\8A\01D\B2\B5\AD\A6\B6\A33w\A5\BB\BBA'ORG\0F\0E\0A\0C@\90\B9\B0tF<)'\19\17+?VnndK1\1B \1B\12\15$%\1D ]>\22\1FG>f\AF\90j:\C9\AA\BF\BD\A7n\AA\AE\86yT\A1xU>@+\09N\BA\B9\AA\14d\B4\9F\B0\AC\BDdj\A9\AA\99\B4\BD\BB\BF\96g\8A\9B}1M=>H\17\12\15\1B'RP55GT:!\04\12#?exkF'\1C\1D\19\1C\18 !\22\1Fb; \11\22\1CEy\1A.L\ACk\13\8E\99\88\92\D6\A5\BB\CF\B3~?Q&-&a\AD\B8\9B\18d\CE\B0\C6\CE\E2\98k\81\99\92\BC\BB\AA\B3\B3|\9B\B3\9A]IAQB9\14:<$/8\191JZU,\08\0C\180SzxW%\1D\1C\17\17\14\1D\1F\17\14a3\09\0F\0E\10\17X %K0\12\11\18\C5\C8\AA\C4\BF\CA\CD\B6d8#\1Cq\5CG]VV\22N\BA\C2\B6\C1\B4\A5NVz@i\C3\A3\94\BC\94\96\96vx_IMKF?O_@R;\1F\14+F]T\1D\1D,>Npx],\22\22#\11\11\1C\14\17\1AU:\15\18\1D\11\0D\1F\0D\15Y\1F-\13\15\92\E1\D2\CE\B9B\A4\B7\BF\95<Bw4J7\8E\9E\14K\9A\A1\C9\93\8A\B6\8FzT\15t\AE\AE\A8\C6\80IN\A6\9FNI5$q|X\80\7FjB\09\17\14)JYA4>I?[ob6F=?<2\1D\16\19\1C%P\19\17\10\04\0B\16\0D\16V\1D\122\19\08w\A3\A0\B9\A1\9E\BD\B3\84wt'\81\AB\89\B4\AE\13u\C2\C0\C1\AE\9Fw\A5\B1\A8,y\A1\B9\C8\C2\A7RR\A2\A2J37\0Fc\9Cv\7F\B1\A3H\09\0D\0A\05%GMFm\8D{\85\89uIOESPRC/\1C\1A\0DM\17\12\0F\10\10\22!\15U\0E\00%,\00\B3\E1\BB\CE\D1\8D\95N9?H\81\9F\A4mas\1F$[\19]\D7ld\B4\B5xDR\A8\C3\C2\95\B9\B3\83H\83K7. =\90\96\81\C4\B6yWQ\06\05\14&8d\99\AC\CC\CC\C6\D4V A3;9;43,+\1E \142F1\13\1A(EdK2(\12d\C0hdiv\83\81*L#I|\92h\01\1CKb\C5\A6\B1\D4\C9\AF\AE\C0\8Ec!W\D8\BD\C1\D1\B9\BC~~\5CV:#\1Ct\AE\B5\BC\B4\A6\88V\10\01\00\06\17?g\88\AE\C0\9B\C6\AD#\10*3(&:+,\1A\1D\19\0E%K#;\13;=e7QO\1D0VmQB\BB\8F\B6\8E\0D\02'N\90i\1C\22T\1B]\FD\A9\F2]\D8\A1\9B\C2\E7\8B\07[\CD\CC\E2\B8\DF\EA\BEp\5C+%\14\84\C2\C6\CB\AE\8A:\07\00\1Afn[yx\84m\AB\A7\A5\D9\B0RMD3\16&,,\05\16\1D\1D\07c\1E\8Be5<d\87L@ $36Wo\93\F0\BA\AC\CD.\00.\15\0B>%-\1A\00.\C2\BA<\EFb\8C\C0y\13\B2\A4^\B7CW\C2\C2\C4\BES\22 8U\AB\B6\AF\CE\99=\01\06@\A1\C6\B3\AC\B3\AAp\A2\DD\BF\B9\B5\88ZV9\1D\1B,+5\14\0C\12!`8\9C\8B\84=/uqe$\1B\05?\A6{\15\A3\CF\E0\B4\81\D4\9F\C1\CD*\143\17\1B\110\F04\B1\B1\95@\01\8C\BA\B4\CC\D3\D5e\BB\C6\96:p\81V7?MJf\92\9Ac50\1CW\B3\B1\AF\B2\AFt\86\9D\B2\C1\B4\94}U\1C\14\12:;\1F+\0AG\B1\92-\99v\B8\8D3\1B8M-\1EH\91\9FZX\A8\8E\B7\D4V\AD\CC\C9\84\00!1\15\09\00}\BE=Q\B1_H\17\0F`\AD\D6\B4\E5\DA\BA\B9\DFH\92\A0\81V>NB]oqZIRJ\03B\96\BF\B5hxZtr}\ABz\84B\15\19\1B;<%!\0D\1A\C9\BF4\AA\89\BD\D9\D0\98\1Ao(\0A\94\A9\A2\99\86\CC\CB\AB\92=e\CA\8E\00\09,6\13\0C\00$\A7R\1C\D9{f\0C5\17\00/\00\C3\C2\BC\AC\B0\AE=e\9D\88m(,}\92\93\80MaqS6\AC\BE\A5\9F\BFUA?!-?<!\15\13\10?=\22390$\89\18zZ\E6\C2\D2\BEP*3\12\95\D3\9F'{\AC`?\09J*\94\E0w\0054\1E\00+\BDu^%\9F\9D\D6g\16\1E\0D:<,Cd\A8\A3\B36\8B\DB\C1qD\8C\8F\8D\A5y~W\92|_\A6\A7\82\9C\BDl*+)\11(\1E\1D\17\13\12=<\0D#^z2u\CD\AC\93l\DD\BA\B7\89&%\1Fj\D0\9C\12\AF\E5\8B\00irc\0C\92\8D\A24*\00>\B1\BA\88^ {\92\D2\C1l\A8\91\08\C1$=E=\A6\9C\CB\7F\C3\E4\92\A9\8DZ\88m_bZ\99\8FVRa`c\7F\84&.$\1E\18#\17\19\1B\0C\10\1E\0E\00\04\16r\99\9E\AD\BC\BC/p\F8m\CD.\22O\B5j,\B6\C9\8D\00\96\AC~\AA\A0\86zk7\CCm>\98\EB\5C&\86e\B7\D9\94\98\9Fs\BF\B0\9B\90_>4\BA\92\D8\B2\FB`I~\8A8a7gx~I0\2290\8D\8A9!\22#\17\16\1F\1C\14\17!\1E.\01\13\1D\1B|\A4\AC\CA\DA\B0d\18n\BD2,%c\1D\1Fb\A40G\C5\99\CA\A7\9C\C4\C08\80\D9\AF}\991j\0F\80\EF\B6\C3\AB\5C%nVv\94b7\22\1E\150\E8\D1jWk\AC\1EGVXH>1B.@PDLo-*#\22\1C\1A1+\16\1D \90)\00\15\02\00X\A0\A7\C0\A8W\00\A9\EB2#\16\0Cb\00\17=\00G5\F0\90\CE\B2\BC\E1\C8\A7\CE\DFv\0CKm$Q\E1\C2\90\B6I p\A7]2,\1E\113+]uqI\D2\A2cWWA\22\22\16\15#Hgc:8/-(\1A\1E\22>9 %\1E\1E\B7p\00\08\0B\1A\00w\CD\94\D2\00<\E1S:#\1E\06%=\07i\1F$\07Y\E5\AB\AC\C3\DB\D3\AF\B1\DB\90J/j%2\C2\BCdS\19@1\BB\AF\84\19+\19 0\1EJlZ\8B\D2\C5\83jO*V@#$&D]Wg6W))\15\18\1D=:&7\14\1E\91L\05\0A\02#\00\91\BF\D7;\05\96\B3\89.,\18\09\18F>\15\0BA\8DW\7F\AD\8B\A9l\D4\B5\96\C2\CA\9AR:P<Y\8DT\00hh\1AR\A1U\0C\10<LH\02R|a\A2\F1\B9t\91*1XD*\14\1BAUdO]:L\1E\16\15\1C=:%A \1Cc(\05\09\0B\17*\DC\C4\FF\00\1A\E2\A4\82n\1D\1F\00\1FF)%'f~\9C\D1\9E\D7\F9\E2\DE\C3\E8\E2\CA\A3]?T3\83\9D\00\8BKr;\0B|^\1CEna/,\91hc'\B5\BC\B9\B76\12'.C-\07g\A3\86mMK(\1A\16\18#>@%2 \1F\87h\0A\02\14\14\1A\00\1E\0E\15O\88le&8\16\19\1FA=\0E\16;w:RbJ)\9D\C8HR\DA\9D\A6yRq\11\9E\D1\92\7F>~8\07FbaIIb\04\A6ju*%\01\B6\CB\B2<\1E\19-7)\16@\B7\C5\B4aB'\22\15\16(8D,\1F\1F!U >\00\14\11#,\13\17\00\93\D0IU\0EF\09$%:N\17/\04\0B\14\03>A\12\92\C5\86o\C0\DF\BA\A0\7F}<\AB\D2\D4\CF\A8\AE\90\BF\00\94x#B\1DO\B6_G\19^rG\A6\BF\93`\18\14/\1F'(p\A8\D1\98M'\11\0C\1D3AJ,\0F\07\15QB\0C(\00\0DZ\18\13#\01\95/\5C[\07D\0A,\1C\1C_\00\A0j\0E\1D\0CE+\15\F5\BFz\C3\E5\D1\CF\9Ba\8A\FE\AFv\F7\D9\D9\B7^ksBf\8A\0D\10\9C\80/\16\0F,\A2\8A\9B\A5\A7\ACX\03#\1F\87\86\B4\9B\C0\BE\A55\09\11\1C5KNF7\1E&9q\07!\0A\1FE\17*\0D\1C\08\017\1B;=\1B)!\0D%(\84\8F\08\16\10,XTH\98\A8\AC\C1\93\C9\B2e\00\E0\E7\FA0\03\C1\E9<N!\9F\8F\D4\002\00\09\0BK'AC\C6\C8\918RO\142S'i3F\B9\D2\D0\BD9\0F\19);HPp\1F$@ra\00\18X\95\1C\0F.\10\096>\01\00n?\10\1B!8\17\11\00+.B>\0C\7F\A7\BD9\FB\E3z\02\00\07D6_P\F7\A5\D4@o>\DB2\7F+S8$\111B{oy\91\7F\AF\BBT`_\0F!8\82\82\CE\A8\BB\CE\B3\90-+\1B\18Knz#\1D^IK\86\0D\22PJ\0Byo-3\1D\22\BE\D5z\11\19\19\0Bns!,B\0A+\05Bs\859J\F4\82\00#\10\14Y*<\E6\DBN\C5\EB\8B\93.\0AzuoZ68CR:\10\8B\91\9E\D2g\12%0# %\09!#x\A1\AFyD.\0E\168gzG\5CWS\00\5C\7F\14,\0Fv|yP/S\95\8C\B6A\11\1A1Af\BAt\16\82\0D\00?(7\18e\0A\1C\82\02\15.\08/:z\FB\13j\D0\B4\D4e\067\5C>}AY'\22\1E\02!oVw\D5\00\A3]\11\19#\1B\1B%#?i\AA}2\18\02\10+RNbaX\12\1B\00o|\17\22\8F\D7\9C\B9\9F|n\5C\A1@\16\0F;BAN9#\16*\0CX\00\17!wS+\00\12 6\1627\03%\9D@\00\0B\92\16BcD\5CNF\A7\1A\18\07\0C,<\05W\904\C2\AAU\19\1C\1E\0F\19\16\155|~R6\0C\1C$8=gk\87\0D\19)\18\8E-\1C\13\F3\CA\BA\AA\EB`o\8CP,\08#\15d\14\0F\09\00\0B%\00\1F\01g\8Ed\00\0CV(h>\0C\14023\135\8E\13<TdC?]X\02)\16\16\1C*2(,#Vx\8Bw9\12\14\08\02\12\16\07&3C:<[&0Gjr\A8\F8F\14)\00\138m0\D1\BD\9Cy\FB\AC\CAu\82s>\11Q\10+\BF\A5C\02\120\B2\A0r\00\8F\CC\BB\A9+($.#N9\06\11V\B4\1Eg\1C\17sb>\14A:7HVRQPA\179\5C\9A@aN:(!+['\19\0A IH!18\0C\00N\8C\BE\00\5Cl\12\0D\8B\C4\C7\D7:J]\D7\AD`:U_\151R\00f\DB\BE\96\03\97\7F\9E\9D\00\CD\DD\AD\BCg+0$H[{k8\09]\02X\0EQ`I<\14>-6D)9\1F\18<Z\084S\81\C3\81]NX\83lh4\1D/YM34T\01\03ZF\82\01\8A\C1\CC\85\9F\AF\B8\DCMg\B6\B9\D1\83h,0-\1AJ\16\00\88\DF\BB\B4\A2D\E291\A9\98\D6\D6\B2\152,<5Qg=& \162\02C\AC\B7\B1\1B#\17\0F\0ErP(-\1C\0C\09V\AC\AF\B7\B7}W}X\82Z;\12AoN%\22<\01\05\0C\1E\08\11\17|\C4\DF\D4\92y\C6\E6\E6\A2\D4\83C#'\0E\1E\11&+\BA\C0\B3\DA\B8\D8\F9\1E\16\05+\AD\A5\9C\005\05:4Dg\1F)\0E\10P \0Ec\F8\C3Vh\BC\CAWR\B6\8CY\14\12\12/0l\E1\B0\C6\CEbauZG)\0E*c5\1D\1C)\07\00\1Ff\1A6\09\00\9C\C5\E3\C7\CB\C8\EB\C2\8A\CA\9F\0E/ \004$\0Cl\96\A4\B3\B3b\9D\CF\01\0E\00gv\98\9F\00\22\99`M\7F\12\04g\13\1AN@\A1\E54\00\00D\A9\82\E7H\D0\C5|\05.]/GT7\E5\CA\CCaq\96\9A\88\8A\84}4I\16K)\16\00YK8IL\88q\E2\B5\86\B0\D6\D6g\96\87\D5\00/\12\05\0F5\18\1C?\7F\C6\C5\AB\A1\DB\CC\1E\00u]n\9A4\95^g\8F\91\00\7F\92}C\B3\B4k\00\09Y\C3\00\D1\9A\8C\C3\97\EB\A9\02-1G\9A\94\B0\BD\DAkG\BC\C7\97K5PJ2D\15D8\04\0B !M\87\C5\C0\B4\93\CF[\93\8D\C3\B6ad\93\01,\14\0C\0D\08! \19\1ERs\96\D2\C0\DF\D6\00-\C6\B1\B9\DCW\5C\844\A9\BA\9A\A6:)X-\14\18W\FFR\A2\BE\E6\D4\C0\C1\F1S\13.>\81\B4\A8\B6\E4\EDe\07\AE\BF\AB\A4mC\0A;<\1B\1F6\0F\0CU\1F\89\5C\AD\CA\C0\BC\EB\1A[\DD\9F\D0\B5\18\0B\13\0C\12\04\0EA\19(\1AnL\86m\CB\C0\A0\ABC\00\F7\C7\D4\F1\A6\8D\8DJ\1C\D9\CE\BF\0B@0gd<<\E6{1\83z\AE\D7\00wh\00k\88W\5Ct\82Ob\F9\82\CF\D5\A0\00\00\13!:M)'?\11\12WHxYJ\DE\DD\AF\B6\D3\DF\AB\E1\C1\88\08\0C\0B\0F\00\0D\01R\19\22-\AFP\9B>\A3\A2\85\00\8D\AC\C0\C8G\92\F8\C3\8C\B5\F0\9D\D8\D3\02UqY\1A\A0\E0\A8\99aQ\C1*\C9\03\D1\BEZG\81Y??j\04\04\D2\B1\D6\9C\EC&\0B\07\19_`)1=@\816|g`_\B9\12\93\D0\B8\A0\B9\A8\D1\00\0F\16\07\15\1A\1B\15\04\1E\18\8D\A5\BCm-~y\8F\B4\BA\C1\E7\A4D\08\A4\C1q|\8D\AF\A8\E3~$4\00\A0\88\BB\CBj\AAR;8\CB\E8\AA\98b*,Ob\849\0BX\C6\C1\ADV\A5\F6?!\0CI8*)1z|miQT\16HA\94\C3\DC\B8\D3\87\CA4\00\0E ./,\19#\1D\19&D\089NY\87,\8B\A5\BE\AA\CAY\C7\C1\C8\88\80\9Bb$\C5\EA:\00%Hr\EF\A15\00\13\00?\A3\9A\B8\96Ybhf{J\07Y\06~\E88\11>\C6uiC%\1C+2\1C\83\8D/\1C#[F#\10\16\CE\BCAT\C8\8Em\1A%\15\06\1D\05\1E\0F\11\1F\0B\0B+>&\08\14^f\B2\A1\9C\92\EB\AD\9D\87ob\18'#&\D4s\000?\14\EE\00\05\0C\01\12\22\86\8F\CF>Ua}\9A@\004\09#:d\16\13\19f\D61. 74.1\8C\89;\17\08Wn\00\17\02\1A\A2%Y1\BEvO\03\0B\11\15\15\0B\15\04.\11\17-3.\1A6\00\0D\FE\E9\B8\D0\96\F0\A8\90S\08\04\EC\CC\06\B8\00\22;4\0F\00\19-\03\0B7\1Chv\B6\1BD^\9E\82\0Av;\1E)?\15\12+,\0B`\07,33-35m\93D\00\01\00[A\07\0AKoJ\18\C7\8F\8Dc\00\0A/\0C\16\19\10\10&\0A\05<Y\08\15D\127\EB\DB\FF\C3k\FF\D3\C0z\0B\A3\A6\B2\17L#!O\190\0E,\0D\0D\13\07\1A<GS\1B3\85{\00]h\13' \1F\00\02\15h\06\8C+# *!6\88\90\13\18\06\00\02/\04\13EXb\84\DB\C7atS\00\12\12\08\14\1B\0C\0E\0D\14C\04\0C/\09\19\10L\ACU\17\19b\C4\B8J\13\B1\8D\DA\F2[\BB\80Uk\D8\5C\00\10\0F\0B9U\125\92\17VU\03X: 3\1D\10\0A*\C8\9B\A8$a\15\16\1B\1D1*\1D\98\9D\1A\0B\0F\0A\0C\0C\0A\19PPM\1B_\A1sh\15\11\0C\0F(\0E\12\0D\04s\D4m\C0!\1E7.\1B\0FO \DE>\08\06\8F\A8\A0\AC\B2\B3UUA\CDx7\89\D1\0B\0E\00Mx\22'K1)4\12+[C\0E\0F\06\16\1Ak?\1C\00' \18\1D\14 \1F'-\98\9B\0F\0D\00\00\0E\0C\04\22>5]8I\06'xn\00\10\00\00\09\0D\00 \BC(\CF\F3\E2\00\06\0E\14`/\18\B3\F8+\06V\DC\96\B3\CF\A3\A2\8A\CC\D2J+\C6\A6\BE\D3\AE\074'\228\1E\1F\0B3?7;WSF,2\1B \22# &\1F!\1A;9-4CI\00\00\06\03\0B\08\02\05,#\AA3L:\8DR\0F\00\00\10!<\05\00<\AE\C5i\E2\F4\F2\00\00RA\1B\10-\A4\00\00\83qqH\D7\BF\CD\AE\C7\D0\89\00\CF\AF\EA\D2\F0:#\1A\22\19\14\0C8<\12\16\16\1A.B^OV\1E\10\12\1D\16PM9\1E8&-FL[\02\04\09\12\01\03\04\00\00}c\1A\02\00\00\07\06\06\1C`>\04\16\1F\1D\F9\F9\D1\A4\EC\EF\A4\CE\AE\07B\A8\00\07\8C\00\C1\EF2\DA\B9\97\CF\D8\AD\BDK\DC\CB\A8\E0\CD\80\00'\14\03*34,\17\0C\0A\0A\14)\0A!\22>D\19\12NVUEQ1%#S[", [5310 x i8] c"\BF\D5\C2\9B\8Fc\93\BC\AF\A1\C1\C2\A4\BF\BA\B1\C1\A5\B9\D3\BC\92/\12\1F&$5+!,\16\13\1A\11\18\08k\BB\D2\BE\87^aJ#\118TjbMC.( 8B@/)'$.*7!!%&\1E$',!\0D\0F\11\1A$$\1B\15\13\1C\15\1B&1'\A7\BFbW\AC\88\96\D4\AAV\8E\C4\D1\AC\8Dp\C8\97\88\CF\BE\C6\ADj2\19\0E\07\1C(#'!\18\1D\18\01j\C1\C7\C3\C6\BC\C3\BDj8^vZI=?F4-A8-*#\1D&36;$/2-&&:</\16\1A\19\1E\1F\18\12\13\17\1B\13%A'(\8D\81/\AF\CA\D9\C2\AB\8855\88w\B8\CDT\9A\D6\C7\D0\B6\A2\BE\AA\806XK\1A$)*.&/!\0D?\83\A0\B4\C3\BC\B1\A3}XrjZ'0NH.)93' \1F\1E\12\1B\1B*/\1A0&!*@G>\1C#$(\1C\15\12\16\1A\1F\19.H\22\22p\0C=\DE\CE\C5\D2\BC>\00\0C\1B\08s\911\17\BF\D4\C5\B9\B6\8DnX:\8D\B2\86<.,\22\1E' \1B\109\85\A2\A7\90~r<^ik; /EF)#23\22$!#\07id\10\17\10\19&\11%?HD\1F(+0 \0E\0F\17\18\1E\1F/@&!\96\8C\7F\96q\BB\DB\A7ze\22\08\14\95fcQ$e\DC\C2\D1\8F\95\94\82J\8F\AC\A4}L\19\18.\12\14\14\1Bj\8E\AA\93WIQQ`W,7IH5'':#\1BP]\05X\B1\BC`\00,\19\1D\1C\22BLH$))3)\13\14\1A\19\1B\19'1E9\C7\CA\DB\88:|\D3\AD\C5\BD\B0j\A4\B9\8A\8C\C4\C9\A5\D1\D8\A7#\8D\AD\B2|?`ov~=\1B(\13\19\1C\0E}\A1\C8\C2aMIFA?4>JG022$&\1Ah\ACt\7F\AD\BC\8D >@A\1C\18<QS*$*:4'\19\16\17\18\11\19\1F67\9D\90\B5\DC\8C\AB\C6\8B\C6\C7\93\AA\D1\BD\C1\8EJ\8C\CB\92\B7\BFsE\96\AF\8ArU-gp\5C%\1A*\1F\1A\0Db\AF\C9\D8|8A>DB3OKGQ8#.4&A\B5\C9\AF\A8\B2\A5\83\8CtH:9<W]<3;GA1\1E\1A\1F$\1D\1D\19438v\C6\CC\DD\D6\CB\BB\BD\D0{\91\DD\DE\DAa\0B\C0\B3\AD\90\B5\E5\92`\94\87\95\A5\8D\9B\C0\B5@2\A9v\1C\053\CB\BB\C8\BD\82?6<'MYU_a?61,2\1D\8F\C9\B5\D3\CC\CB\BE\A2{J8IK]bRPTTK@9=;81+\1F61\16O\C6\A7\A8\B6\C2\B7\CE\D3ZC\82\BC\D4\B4\90\AC\B1\D2\9EPv|\9B\98\B8\AD\BE\B8\C5\CF\D5A9\A3\80.`W\C6\BB\AD\D4\C4\9Em<2MiNECGJ@</\16E\88\9B\C7\D6\D7\BD\A3\97nBEO^bglZ[RF<<740%!\22 r\09+?j\93\A8\A6\B2\D0Dpk\C5\A7\B4\BA\B4\8B\AFj\CC\82tx\98\96\8D\A0\97\A7\B9\BFA2t'2\80q\86\BE\C0\BA\C4\BD\C2a\0F0d\82c\22TOV<!\15\19Jw\AB\C3\D2\BD\AD\96x93=Q`r\80ncR<91%'\1E\16 \1E\1C`A4(5Yc\99\AC\C7H\88\CC\CC\CC\91\B5\B4hwM>\ADlf`?>1\5C\AE\A0\9E0L\AB[ip\A1\0CO\BA\B7\AA\AB\C5\BA<}\AC\C7\CBO-O[M\16\1A\1A\1AF\90\BC\B6{PJ72\22\1A1F`||oT4\1E!\19\10\11\22\22\1B\1C^;!\1BFHk\AF\91g9\C5\A9\C9\C2\A7m\AA\B1\85xR\9BqT>C*\08L\B4\B2\B5\1Ei\B8\A0\B6\BB\D2ot\AE\AE\9A\BA\CC\D0\CA\A3t\99\AB\892HHKU&\22!\1C\22QR:>Q_D+\03\14(Ho\83uP-!\22\1D \1C$'\1C\18m;\1E\0B\22&Ir%.J\A6k\1D\92\92\88\91\DA\A2\B5\C7\ADz?P** Y\A7\B4\A7\1Fg\D0\B2\C6\D1\EA\A4r\84\9B\94\BC\BE\B2\C6\C2\8C\AC\C0\9E\5CGT`RJ!>;\2218\188Tb]3\0A\0C\177]\82\80^+%# \22\1F(* \1Bu9\0B\13\11\13\15Q4+M4\15\14\16\BE\C7\A5\C5\BA\C9\C5\B1d7\1E\1Dl[?XVb(O\BC\C4\B6\C1\B6\B1TW|Bi\C3\A5\98\BE\A2\A9\A3|z[MOYYLUa<S?&\1C1PgY\1E!3FTz\82b1)+-\1D\1D)!\19\18jD\1B\1E#\1B\15\1D\22\1F_%3\1D\1D\90\E2\D1\CB\B7D\A3\B9\BF\96;?u6I9\8E\AB\1AL\9C\A2\C9\94\8A\C3\95{V\16t\AF\AE\AA\CB\8BSR\A7\9FMK:/{\80Y\80~jK\1A%\1D4V`A=OWHf{i:KCHF<' \15\154T\1B \1D\15\1C!\1C\1AX&\1FC*\13v\A5\9F\B5\9D\A1\C5\B4\83ys#}\AE\91\B5\BC\1Ax\C3\BA\BC\AE\9C\85\AC\B4\A9&t\A1\B6\BD\C1\AD]a\A9\A7T(6\15n\AB}\84\BB\A4O\18!\1A\121SNM|\A1\8B\92\95\81JQIZW\5CJ6\15\12\16[\22%\1B\1B\182*#`!\0B04\09\B4\E2\BC\D0\DD\95\98T:@I\83\AB\ACpg\85!\22W\1Cd\D9cv\B6\B3tGY\AA\BA\BF\94\BA\B7\89P\82J4-!A\96\9E\80\C3\B6y]X\0E\06\13%8d\9F\B3\D4\CD\C5\D3_'I:BAD@<36.'\1B9P4\1D%8LkR<+\1Ck\C0gcj|\8D\891L\22H}\98r\09,Ob\C6\AB\B4\D4\C5\BF\B2\C0\8Fh$W\D4\BD\C8\D2\BA\BF\8A\80\5CVA$\1Dw\BA\B7\BC\B7\AA\8CZ\15\03\00\07\1ACk\8C\B3\C2\9B\C7\AE&\14.5.,@33'+!\14&P)I IEk8VU+8^pNE\C1\8E\B6\96\15\05$Q\96h\1C6_\19[\FE\A7\F4Y\EC\AC\99\C0\E8\89\09W\C8\CE\E5\B7\E2\F0\C6xW-(\13\87\C8\CE\D3\AF\90>\08\00\1Cfl\5C\7F|\85n\AD\A7\A3\D6\AFRNE5\18(34\14#$!\03`!\9AtBCh\83IC/)6:Xr\9F\F3\C2\B1\D02\001!\0EF<;\1F\010\C0\BE<\FFp\91\C1{\11\B6\A4^\B5CU\C8\C3\CD\C5S 6[\AC\BF\B6\CB\9E=\00\04D\A2\CB\B0\B1\B3\A9n\A6\DE\C4\C1\BC\8E]V6\1A\1757?\19\0C\0E\1F`8\A9\95\89=+sqe1%\0AD\AC|\1A\A3\CF\EA\B9\86\DA\A0\C6\CD*$9\1A \1B3\F38\C1\B7\98E\0B\8F\BD\B8\C9\D4\D4f\C2\C9\9FCm\82U8FPSo\97\A2c40\1EY\BF\B6\B7\B2\AEt\88\9F\BE\CF\C1\9F\86Y\1F\18\17;>&2\12H\B1\93/\A1}\BF\954\1B9O5,U\95\A3ZV\A7\91\C5\E1Z\B1\CC\C7\83\00$5 \16\07\80\C5JT\B5jU$\12g\BA\D6\B0\E8\E0\BF\BD\ECR\92\9C\84\5CCROgw{^JTQ\0BL\9E\C9\B9iza||\91\BD\89\8FJ\1D\22&?@& \16!\CA\C27\B0\8A\BC\E2\D7\99\1Dr.\1A\A4\B6\AB\9C\86\D1\CF\BB\A2Jn\CD\8E\03\0D$8\19\18\0C&\AEZ\14\DB\81r\1A7\1E\027\00\C8\C5\C2\B1\BC\B0Eb\A2\8Bs-8\7F\95\99\87Oex]A\AF\C4\AC\A1\C3\5CKJ/;KH-!#\22AC$3A8,\8E\16}\5C\E6\CA\DA\C6U(6#\A1\E3\A1\22y\AFfP\15Z,\8F\DEz\02+4$\09?\BEwa\1B\9F\A3\E9{\17 \108@/?e\B1\A8\B74\8F\DE\BDrM\91\93\95\A9\81\84V\8A}k\AE\AB\8A\A2\BCd+72\1C4*)$\22\22CB\161i\8D>\80\D5\BC\9Cz\E8\CD\C3\94.5 k\D1\9E\1E\B7\E8\91\00jse\18\9A\90\A8F,\00:\B4\C1\8AU2}\90\CE\C4s\AA\88\05\C0%AKE\A5\9B\C8~\C4\E8\98\B1\8CY\88meib\9A\8EURafj\87\85%--% *\1E!$\18\19%\19\10\0B\1Dy\A3\A1\B7\C7\CC6w\FFw\D08)O\B4i-\BC\D3\95\04\96\AB}\AB\A6\90\82{;\CCnC\9B\EBX6\8Ae\B8\DE\97\98\9Bs\C6\B1\9C\93k@4\BA\99\D9\B3\FElK~\8D<e;lz~J3&=4\92\8C9\22#&\1B\1A!\22\1A\1D)%;\0F\1B#\1C\81\AA\BA\D7\E8\B8j\19s\C3@4-f\1A\22h\A30O\CD\9C\C7\AA\A2\C3\C0L\8B\D7\AD~\973f#\8B\ED\B4\C4\A9^!iXy\93e=*&\102\EB\D0m]s\B4\1FMZYI@1@/FTEMq-( !\1C\1B2-\18\1F'(\9F6\00\19\00\00[\AF\B6\CD\AF[\00\A6\EEA(\19\10c\02#@\04L8\F4\91\D1\BE\BF\E9\DF\B5\D3\E0x\0AOm;_\E6\C3\92\B4M n\A7[8-'\183)]swJ\DB\A9`\5CW@ &\17\1A Mgb8<020!$%>6\1D!'*\C1u\00\04\09\1A\00\84\D7\99\D2\00:\E1SG-#\0B+>\0Ci\1F.\0C^\EB\AC\B1\C3\DB\E3\B5\B4\E0\9AM2n58\C5\C1nV\1CD.\BC\AE\85 .\22)-\1FIma\8E\DB\CE\88rO)VB%0+L]Vg8Y57\22#&A=*<\15!\98S\0D\0B\02$\00\99\C6\DEC\06\96\B4\8B6:%\0D\1CF<\14\0EO\9A[\83\AD\89\A8o\D7\B9\A1\CF\D7\9DYGS@d\9Aa\01ou\1AN\A4[\11\14IVH\00U\82f\A6\FE\C3|\9B.2ZK2\1E#KYeQdBV2($'EB.L$ d'\0E\10\0C\1A-\E2\C5\FE\09!\E3\A7\85t-/\0D(I)*+v\8E\A9\DA\A1\D7\FE\E6\D6\C5\EE\EE\D8\A5dGL5\89\A9\0A\8DRzC\08\81a\22Jzc7)\96ki,\C1\BE\BC\BD=\14+5M8\0Am\AA\88qTU3($$/JL5D\22%\89h\12\0A\1C\19\18\00 \0E\1DW\90qc)I\22)!<;\11\1CL\83JT]H,\A3\BEHX\ED\B1\A7{Ug\11\A4\E4\A6\80@\816\0BI^bRNf\02\AAmq+.\06\BA\D3\B6D$\18%85\1ED\BF\CB\B3YC3+ \224DQ;/%'a+G\0E\1D\13#-\1F\22\09\A1\D9KU\0F[\1A2(;S\1A0\19\1C\22\06?F\15\93\C9\86m\C2\E3\BD\A0|\81<\A9\D4\D8\D2\A8\AB\8C\BD\00\99\81*?\17K\B4^L\22eoA\A2\B7\94j \15.&# q\B2\D9\99L.!#*6FP4\16\17,VN\1A9\08\1Ae\1E\18/\0F\A6<if\0DW\1F:\22!g\03\A3}#+\12J3\1B\F8\BE}\C5\EE\D9\D2\A0c\89\FF\B1\7F\FF\DC\DE\B9^kqGu\95\13\0B\9C\80-\1B\1E7\A8\85\9C\A6\AB\B3X\00\19\11\88\87\B8\A2\C0\B8\9B'\15!&9II>-+)?~\15.\12-T\1F0\1A*\15\09E*CJ-8+\16+/\87\9C\1A%\1A5^[K\9B\AA\B2\CB\9E\D2\B7f\03\E2\ED\FF;\0C\C6\EA7O&\A7\A0\E3\070\00\0A\10S8PM\C4\C9\96>ZQ\0E'>(n9N\BB\CC\C5\A89\0F\1F5DOZv$*G\7Ft\0D\1E\5C\9B\1C\16;#\18<B\07\00}O!(*? \19\0B;?OG\13\88\AF\BC>\FF\ED\85\0A\05\0DC;cZ\FF\AD\DCFqA\E0C\92<]<&\146S\8E\80\83\95\8B\B8\BEVbZ\08\15D\8B\85\D0\AA\B6\C7\A7\8B$--'X\82\8B+$iUY\91\14 PF\16\85}8:\1B\22\BA\DC\84\22) \0Eqs(6S\1A2\08Es\84:J\FA\8C\0A2\1A\13Z*B\F0\E7]\CF\EF\90\9B>\19\8B\84\7F^;@SaK\1F\9B\9F\A8\DBo\17(/$./\12)({\A0\B0{7.\1F\17,`nSle_\07]\80\11*\07\84\88\82Q0P\93\84\BCO!.<Bk\B6z$\92!\0A@-3\1Bf\0A\1F\8B\10\228\0B0:}\FF!w\DA\BC\DCj\0CAdIzIa,((\0A,l\5C\81\E0\00\A4`\13\1F)%&($Bk\B0\82 \17\1A\14#UJlea $\03ox\12 \98\E5\A5\BC\9FxiZ\AAP!\1DC?AKB3!8\14U\00\14#}U0\01\16(9\1889\08*\A1H\00\0F\95\18FgC\5CEJ\AA\1C\1C\0B\0B,3\0Ad\9D:\C6\AEW\1A!+\1C\1F\1A\197}}40('%LOef\97\1E\1C-\1C\95/##\FF\CD\BE\AE\F2bv\94`;\161\17_\0E\17\19\08\193\00\1A\00i\92f\00\0EX*f@\10\16145\153\8F\13=XdB=ZY\02*\1A\16\1B(/1<,Xy\8Dw4\1B$\11\04\13\18\07!B-5TV\131Fbh\B4\FFO\222\00\139y;\DA\CB\A5{\FB\AD\DF\86\90v?\16T\11@\D0\B3F\03\173\B3\A4r\00\91\D0\BE\A9(,$,%R<\06\0ER\B2\1Dl%\1Ep\5C:\12@?@OSLMHB!A]\99G]F;2),Z.)!-LM'9?\1C\0DS\98\CC\0Aiy\1D\13\90\D0\D5\E8GWh\DD\C0uH[d\1D7U\0D{\E9\C4\9B\0B\9D\82\9D\A0\00\D6\E5\B0\C1i*3&Qc~p:\09]\00]\1D\5CfD<\14<2EO/4 \19@a\08.Is\C4\82aUX}bZ@-9]K.,J\0E\06`S\90\0E\92\CF\DB\8D\A5\BC\C6\E9Uu\C5\C1\DE\95w693!M#\0A\97\E9\C4\BA\A9G\E5;7\B3\A3\DF\DB\B3\1842F@Zl>!!\1B:\13R\B6\B5\AC\1C(\1F \1D|N)2\22\14\0BP\A1\9A\B8\BC\83_\7FRwE;\12G{W,,B\06\0B\13+\1B \1D\80\CA\DF\DB\9F\8C\D5\EC\EA\A8\D4\92S44\17%\1A.:\CA\D1\C0\E3\BF\E1\FF\1D\1B\095\B8\AD\A4\034\0A>>Oo'/\10\13U1!t\FF\C7Xk\C1\DBjc\C0\90e\1D\15\141+e\D5\BC\CF\D1dcpS;$\05,uD*0:\0F\06*r(A\10\00\9C\C1\EE\D3\D9\D3\F2\C0\8A\C6\A6\18@0\077'\0Cs\A0\B5\C3\BAe\A0\CF\00\0F\00m\80\A4\AE\07!\9A`S\89\1E\13q\17\1FVP\B0\F6C\0C\00I\B1\92\F6Y\DF\D5\8A\0F7e4JS8\F3\D4\D5iv\99\99\89\8Cw}EJ\0AD\1D\22\0DgWAJM\85o\DA\C3\92\B9\D7\D7d\94\7F\DB\0D?&\10\10:\14\22M\8F\DA\D0\AC\A6\D7\CF\1F\00xf|\A7>\98_g\92\9A\0A\8C\9C\85K\B8\BAu\05\14V\CB\08\D6\A0\96\CB\A2\E8\AF\0C84H\9D\96\B6\C3\E4vJ\BD\CA\99Q:>IJH\0DG4\0E\0F)/V\8A\C5\BC\AF\91\D8i\9C\90\C3\B2\5Cb\9C\117\22\14\0A\08\1E)))`{\93\D2\BD\E1\DC\002\CB\B5\C1\DFYb\869\AE\BE\A2\A9>,Z1\18\17W\F6V\A5\C0\EA\D8\BF\C1\E8X ;D\85\B8\AA\B7\E9\FAr\0D\B2\C3\AD\A5l%\04WG\1C3H\0D\07e0\8C`\B1\D1\C2\C3\FB+^\E1\A3\D7\B7\1F\13#\1B \12\10<\130*}Z\94o\C6\BA\A2\AFE\00\F9\C9\D6\EF\A8\91\8FK\1E\DB\D0\BD\0C@1kd;:\E3|1\84~\AE\D6\00tq\0Et\8AX^t}Xr\FF\84\D0\D7\A0\00\09\00\1CRH\16(>\09\08j[\84_G\DD\DA\BB\C9\E6\EB\B1\DE\C0\85\14\15\18\1F\0C\17\00[!+:\BF^\A5:\AC\AA\89\00\84\AB\BE\C7F\8E\FC\C2\83\B4\EE\9C\D7\CF\03WpT\12\9F\DB\A2\9AcP\BC\22\C8\00\CB\C8jR\8Da??h\0E\14\DD\BD\DE\9C\EC$\00\02\19[U\17\1D+0|E\8DucZ\BA\13\98\DF\C9\AE\BC\A3\D2\00\14 \12!'%\16\0C%\22\98\B1\C9w.\86\80\97\B5\B5\C2\E8\A8H\06\AC\C2l}\8E\B3\AC\E1\82)9\03\9F\8C\BB\C9n\AFW>7\CF\E8\A8\A0n27Zj\8CA\13d\CE\CC\B8^\AD\FE:'\19Q8#!,zxtt`]\16OG\97\CA\E7\C7\DC\87\D1:\00\14+982\1C)&\1F1O\11?Q_\90:\8E\A4\C0\AF\D3_\C8\CF\CB\87\82\A0k*\C6\F3E\06/P}\F3\A2>\05\1F\04G\AE\9E\B9\A1emtt\89X\15d\12\89\F4F\1FL\D4yyY6&,1\1Ex{8%-aC\22\14\19\D7\C5KZ\C5\8Dq\1D+\1E\10$\09!\10\1A%\14\152B)\09\1Dlm\B6\A6\9F\96\EC\AA\AB\8Esg\1B+$#\D4x\089J$\FA\08\05\11\0B\1B-\96\9B\D9Pcm\8A\ABT\07B\1B1Fq'''t\DDCF7I@8<xw?\1D\11_o\00\1A\0F\1E\A8.a2\BCy\5C\0B\14\1A\18\15\0D\13\076\1A 030\189\03\12\FF\EC\B6\CB\92\E9\AB\95V\0B\02\E7\C8\00\B4\00)?;\1B\07\22)\03\12;#t\80\BF-Pi\AC\92 \87K05J#\22A=\1B_\12>DA5:>h\99B\04\09\04]:\05\0EItR \C9\88\8Bg\05\139\0D\13\16\0B\10/\13\0F=V\05\10D\0D:\F1\DE\FD\B7h\FA\CE\C3\80\0E\A0\9A\AF\0FG\22%Q\1D7\164\08\0C\17\09\1ECO[-?\92\88\08sz!9,-,\0C\18'v\05\96=4*,\227\95\98\10\1C\0D\03\04*\06\1AB\5Ci\89\DD\C2c{Z\05\1F\15\03\0A\18\0C\15\16!F\00\02,\09\11\11U\B3R\0C\14]\BC\B9S\1A\AE\82\D5\EDV\BA\84Vo\E1f\07\0B\0E\0F:Y\1B?\9B+cb\11jN0>1\1D\178\DA\AF\B8/^ ),*7.\22\98\96\19\0D\15\10\0F\06\0A\1BORS!b\9Bsj \1C\1A\11$\04\11\0B\0F~\E2o\BC\17\1D5(\1D\1DX\1E\D68\01\00\91\B6\A9\AA\AA\ADNP@\D4{=\93\DD\15\09\00T{(1W;>A\1F:mW \1B\1B#'zQ0\0F3\22'4).',3\90\96\22 \0A\03\0B\0B\01.QHi>F\05$\84w\07 \09\09\05\16\06)\C98\DD\FD\DE\03\0E\12\13W.\16\B2\F7'\0AU\D3\95\B1\CE\A2\9E\8B\CE\D1E#\C5\A1\B8\D4\B0\06/\1F!3\18)\1B>K?;WQP<='(\22#\1E\16\1A!\160'\19\223D\0A\0A\14\06\06\09\03\0A;4\B86G;\8EW\19\09\0C\1D+=\0D\01F\B9\D1v\EC\F5\FA\01\02S<\1C\111\A8\00\06\84lrI\DB\C3\CB\B2\CC\D5\8C\00\D3\AF\E8\D6\F5?&\19&\19\12\14DD\1D!\1E\226JjWa)\18\1A%\11VZA\1E1\1E(FHb\0D\13\12\12\08\09\07\03\08\8Cl\1A\09\03\00\0D\11\11%fA\0A\1F%(\FF\FF\D7\A7\F2\F8\B2\D1\AD\09G\B1\00\08\9A\03\C0\F17\E3\BF\98\D8\E3\B9\C7S\E7\CF\A9\E9\D8\8C\06/\1F\07+>@7#\1A\18\18\224\16,.LR' RfkV[2$%HI", [5310 x i8] c"\EC\DE\B4\96\A9\95\BB\D4\DC\AA\B3\BD\BE\F1\E2\C9\C1\BD\D8\E7\9E\93\0C\00\1F>CI\0D\22\09\00\00\03\180\1C\93\D3\9F\A9pey^K)\05 ?=%\1F\13\19\19\04\17\1B\07\05\0C\15'.2\1B\0A\00\15\14\00+'\1B\00\00\00\10\00\09\03\00\01\0D\09\0F\1C\16\0F\B9\CCkh\B9\8E\AF\FE\BCc\97\D5\DE\B2\A6\9A\DA\BC\B3\F4\DD\F5\BCaD>9,;W2\1E\0C\00\170.\99\CB\99\AE\AC\B6\DB\EA\99B0=B1\0F\153'\1C\08 \15\00\00\0A\19\22*4\1F\0E\00\02\14\0E.5*\00\00\00\0C\07\05\02\05\0B\12\0D\1F>\11\16\A8z\0F\C9\F7\DB\D4\D7\A3.\15\A2\A4\BA\DF\80\B6\F8\E7\F0\DE\C7\EC\CD\9CXxkBIWM \15 .8UbX\A6\B2\AD\BE\CE\937*=4\06\0C*;<A\0C\0D\06\00\00\11 3.&\1D\00\00\00\00\0FSC,\00\00\00\00\01\00\00\06\0D\12\0E\22?\13\16r\1F9\F9\ED\BD\E7\E0@\12\086'k\A6U6\D9\D9\E4\DB\CD\BB\A4wT\92\D1\A8S\5Cb\1C\1D*,7\1C\1CL\9C\A6\93\8A\8EHA0C\05\00\08\142EK\0A\00\00\00\00\0F#\91\8E'\13\00\00\00\00\00i_@\00\00\00\00\00\00\00\00\00\05\06\16&\1A\17\92\AE\94\C2\89\98\DC\D3v\8774,rg\8FwLh\FF\F2\FF\BF\B6\BA\AAM\BE\DC\DF\ADm\15(M+*6<u\8A\BA\B2p_srk\1F\0D\1D\1D\1A$,*\02\04\01$/\00]\B4\C9|\0C\0B\00\00\00\00OhV\03\00\00\00\00\00\00\00\00\00\00\09\132)\A2\E2\E7\89C\81\EB\CC\A0\D5\BCk\AD\BE\A2\AB\E3\FF\BB\F9\EA\E0K\A9\CC\E8\92gr\A8\9E\9A95T,%>@\A4\9D\E2\EEzYkxhdmI\1D\1B\0C\1AAI_%;\80Pg\BC\C1\7F\00\17\1A\05\00\00AC1\03\00\00\00\00\07\00\00\00\00\00\00\04(+e\88\AB\CE\8A\A2\C8\B3\8E\BF\89\9C\CF\B4\C3\B6`\AB\E6\AA\B2\CD\80k\AC\CE\A5\8AP;t\96U=9912)\86\A8\E1\F7\8BJYZhNPeURUBM:Q<K\C0\CD\B9\D2\CC\8A;[a\1E\00\0FV<\15\0B \11\07\17\10\00\00\04\0A\03\03\00+-\0Fw\C5\AF\C2\B6\A9\BF\94\D1zt\C2\BE\B8e*\BB\C3\D0\B1\BA\DA\B0\7F\8F\97\B8\C6\92\90\DE\A4RA\BB\A6D\1Fj\BA\CD\D7\CF\B2gPsOm{W4QU@YLT\1Fd\B9\CB\DD\E8\D3\97eW/\12#ge;\15,9.%\16\12\1A\19\17\0F\09\000.CX\B8\A2\C2\E8\EA\CF\FB\DCL>\9C\EE\FC\CC\90\C4\D0\E6\80QSc\9B\B0\D7\C1\A0\B9\A2\B6\C0*@\BB\94Vx$\B1\A4\B4\EC\D8\C6\85\09\00\22D&!(8C\0C\11\0A\00!m\8C\C0\DA\D2\B7\8Cq]8\1DSY\5CPFIQ*+$&%%$\19\17\07\08\84\164Pw\99\C1\D0\C4\DDM\81x\CB\C0\DE\CC\D9\B6\D4\89\FB\91k\8A\BD\C1\B2\BF\C6\B6\B0\AA',\8CTa\8ACq\A4\BA\D2\F1\EC\CC3\00\18LT9\0FG>\1D$\09\00\007j\9A\B7\CB\B8\8CXM'\1B1J[QBCQ:))#\19\1E\18\10\1D\08\0A{:\14Bb[u\C5\C7\C0(\A2\F9\CE\DE\BD\D1\D6\88\97uc\DB\8F\82\82_^Y\81\DC\C3\90\1F=\B8\86\7FOY\00>\AB\C4\D5\C1\A4r\0FW\8B\A3\A7B;g.'\00\00\00\0DT\A8\CF\B2i-\0F\00\0A\07--4=AAG9\1F\0B\11\0C\03\06\16\19\0C\10`N\1D6e@\80\D3\93z5\E0\C8\C1\D7\CB\8C\C4\B6\A4\9Ai\C9\A7sXHI*c\E2\E8\AF\1Dl\C4\BC\C2\9E\99is\B1\BA\B6\C6\AF\97\A2mHrzuNp \15)\00\00\0D8J{i6\1F\1D%\0F\00-+$);I@\1B\0B\01\04\02\07\03\0B\0D\10\0Ei]37:\03J\9E!P_\D2\83\00\93\BE\AE\B9\DD\D1\E5\FF\DD\9Bex-YP\94\D7\D5\A3/\86\E9\C8\E8\F2\F5\A0\82\A3\B4\AA\DE\DF\BD\8E\A3r\80\92\8DaJ\1CA8\1E\00-@%>T&\17\18'!\00\17(%\16!GD\1B\05\00\01\01\04\01\0A\0C\0D\0BPQ\17\14\1A\18-p\0FCY5\1E\19.\DD\E6\DB\DB\E2\DB\FE\D9\80VT3\94mx\80r^B{\D5\D0\D8\F3\DD\ADn\83\95N\8B\F5\CC\BD\F7\AD|wXbjr\88d, 1IKX1\04\00\0B\14 !#\13\11\1F.>;*\11\0A\0E\13\05\05\0E\06\0B\0C2<\11\10!\12\17E\00\17U\171\14\1F\B8\F8\F0\E6\CF?\B1\C6\E5\ACZZ\8D1WF\B4\A42k\AB\B4\E1\B0\AE\BC\AD\9Ae(\8C\CB\D2\B6\E8\A1]]\AB\A9wWWE\85\8B]\8A\A8\840\00\00\0A\0A\166[\22\07&5<;?\19+'-,\22\0D\05\0C\0F\0BU\1A\03\02\00\00%\00\1BW\09\04#\08\17\95\A0\AF\D8\BE\A6\BA\D2\A2t\83F\9E\B3\86\D3\AB,\87\D5\EA\E4\C8\D3t\BE\C3\BBV\9C\BB\ED\E5\E1\CF_6\99\BD^PV7p\80m\9A\C5\C0W\00\00\00\00\0B-jUUdgwo[ *&86:(\14\0F\0F\007(\08\0D\0D#\15\0B\00f\04\00\22?\00\C8\F8\D0\E7\B7\88\ABTNV]\9A\85\9F\83g_77\89G\81\FF\A2P\CC\C8\A6rv\D1\F9\EA\BE\D6\C3\877\92\5C_W=M\94\85\90\D5\D8\9D]P\00\18\18!Z\88\9F\AB\C5\DF\CA\CFD\06\22\11\19\18\17\0E!\12%\09D5AH_)\14\13i\85Z4V([\DA\89\8D\88|s~!fDr\9B\98X\00\0FXb\C0\AE\D7\EC\DE\A2\BB\C0\89kGo\ED\D9\C1\EE\D9\D0d\8Cvr:@<\88\94\C3\D6\BE\B6\97e\18\12\09\01!Ov\97\B6\D1\A5\C1\B2\1D\00\0B\0D\02\00\10\0C\0A\13\12. 8J7<\0C0RwJPc\1E+O\7F{X\BD\BA\DC\89\06\14Qd\92\94B\10Q$`\F9\BE\F3r\C6\9E\A4\C5\E3\A0\08p\F0\DD\F6\DF\F5\FC\B9m\7F<9;\9A\D4\C1\C8\C5\82?\1C\13(~\81rq}\99\82\B9\BF\B8\F5\BDH/\1D\06\00\00\0A\0B\00\1C4,&}D\97S;Ss\A6ff,-IFn{w\FF\C5\B5\E3>\14:\00!I\10 \1B\00\22\CB\B0D\DAU\8D\BCm\1C\A8\ACj\CC[\86\C6\EF\CC\CB_78gY\D8\BE\BC\F8\97G\12\19G\B6\C5\DD\AA\BD\BB\83\A9\F2\BE\B6\AAt><#\0B\0B\08\056.>@7l^\A0\8C\9Eo]\8B}\8B(\1C\1FJ\9E\90\1E\C7\FF\E1\CE\8C\CC\B4\CA\F1\5C\1A]E&\008\FFQ\B7\DB\C3K\00\94\D0\D1\DA\D6\E2|\BA\DC\9EJ~\84cN>cRv\91\8Bo:2\1Be\9B\B0\A0\BE\B4v\85\AB\9A\B4\A5\81kA\0A\00\00?5\04+\15f\C9\97E\A3[\B8\98R3=e7\11:\A0\A6r\88\D3\B4\AA\C6e\B4\E4\F9\AF E[4\0F\00\91\CF8u\DB~N\08#q\A8\D6\C9\D5\C6\AB\C0\C1G\92\B5qB/U$\5ChVMB<(\001\8F\A4\A8ab8ca^\8D^o1\06\07\06&\1D\04%\05+\E9\CB@\AEh\C1\D1\E1\B8&{,\00\80\88\8C\A1\A8\E6\E8\96~\1CO\D2\B0\18&9G;$\00<\B6d)\EA\A3~\03M&\0C\08\12\AA\B2\9E\9B\8E\C6\16w\84xO\17\0A\95\B8\95f7@L+\17\D2\C0\8B\89\9E0\19 \0E\18% \07\00\00\00\19\17\00)6B.\92;\84\1B\DC\BF\E4\C8YM=\00\97\A5\AEX\A1\D0t,\0B\1C9\C5\FF\9B\10\1F(>\00\00\DD\90\84\0F\93\BD\C9<693C(\14PUx\90\BA?w\C3\CEb\14y\96\A2\B2XXD\B1\7F9\BB\B4av\AA\8B-\05\13\00\04\00\00\00\00\00\15\12\00\0Dop0r\E0\9F}V\EE\B0\B5\869\184\81\E5\B5\00\AA\FB\91\12\80\87|\00\8D\A3\A8 B\12l\DF\DE\B1\94\0C\93\A5\FF\EF\90\D1\C70\EAAMI,\B5\AD\F3\A8\E0\F4\96\98\9Ck\AA\91eaS\AC\93Qt\85fbx\97*)\12\04\00\01\00\00\00\00\00\04\08\00(7\81\9B\CC\C3\B6\A7S\91\FFo\FBD\19i\D6\93K\BC\B9\8A\00\B0\CD\A7\C9\A6vw^D\CChF\BE\FFq\19\93e\B2\E1\BA\B0\B4\8F\BF\CD\BB\A4ELN\D6\92\F5\D2\FFFW\98\94HpFo\89\88D:2H?\95\9BC\1C'\1D\02\00\00\00\00\00\02\00'\00(/.{\B8\AD\C3\CF\C5v+m\D13'\1EuG5d\CFVB\BE\AB\F4\BD\9E\EF\E6&}\E2\B2y\AE2\7F\00}\F8\B9\BF\C0]:\91g\8A\BBxI\1D\1B8A\FC\F8\80if\A95?[m]LIUE8UYa}E=?/\12\00\0A\00\00\00\00\00~/\10$!\19~\AC\95\C6\BFf\1E\C3\FF>,,\1Cy\0B\00S\07PK\FF\A7\DA\96\D2\EC\B3\9A\CF\DBj\15Au\0FD\E2\BE\84\BF?(,\85\BF\8C6Y&\1E?@u\A4uv\DA\AF\8DUaR5)+\14MFqtM?D,%\0F\0A\06$#\0E\15\00\00\B8\8A06!&\22{\CE\AE\FF+R\EDy>$8\11\1DR\10\8DQ%!d\DD\C0\B5\E7\FF\D9\D9\DF\E6wRE\87+\5C\F0\C7K[/]?\BE\BC\9B\18A!0>!W\83Y\A1\DA\D5\82[[/X?1\0C%5i\5Ci5e\11\1C\06\05\0B)(\11\1E\19\18vL\10)\1A(\14\9B\A4\D7F$\AE\B8\A18\1F\0A\18\1F^n@14\7Ff\86\C5\BB\D4\92\F8\DF\B5\C8\BB\AEc5tfx\93E\12yc\1Ag\91A\00\17\1EKH\17BhR\A9\D3\B8mv\1D*B\22\19\03\14&H]9;);\00\00\00\07,+\13,\0B\00B,\00\1A+#6\E0\A3\FF\00+\FF\B0\8Er\08\0B\00\09NK?DQj{\BB\A6\F9\FF\FF\EB\D4\FF\FA\C1\BBlQaD\AB\B5\00\A3Z\84\14\1DcN\004Ly\08>xXE\16\93\D4\DF\B9\1C\00\06\09\1B\0E-i\89pL(#\09\07\01\00\07$$\06\10\00\00H^\07\14\1E\1D=\07\00\04\12a\92u\880%\18\00.rc2*(y\0Ca\93pM\B1\B2<r\CDr\C6\94x[\05\BE\C4g\9FY\A4A\00.oR\196i\0D\92R\82\1B\00\00\BD\E0\BF\1B\00\06L:\03+M\96\9F\A1\80E\01\0C\00\00\02\16&\12\08\00\001\096\00\0A\22%\1D\00\00\00~\C6ZW\002\00\0F-?=#O\00\00\00\0BC0\1E\B2\B1\90\92\D9\EE\D0\B8\9BiF\CE\EB\E3\E5\C0\CA\A5\C0\04\85b\096\01d\B7c8\03Df+\A3\E6\99G\13)<\04$Ov\8F\CC\ADZ\0C\04\00\00\0B\1E*\05\00\00\00P(\00\0F\00\00C\12\12\09\00|*MD\01:\00\17\14\0DR\00\B4`\00\08\046\1E\11\FF\C4v\D2\DD\CC\E5\99b\8F\FA\BEn\F2\EF\D7\B8fk\86C>w\00\05\A4\80B\17\00\19\86\7F\A0\AB\9C\94Z\1942\8C\8C\A9\83\C2\D4\B6H\07\00\00\00\0C\0F\00\00\00\005P\00\1D&\1E5,&\00\06\04\1D6\0BPP\07\17\11\01!(\96\A2\00\04\00 TTZ\92\A9\A8\B1\80\BD\B3h\00\E1\E3\EA\1D\00\C2\ECoS \9As\C4\00;2\0E\0AF\0B1(\CF\E5\9A43,\00\11QDr/'\96\B4\AF\BB;\00\00\07\17&&R\00\04Oc<\00,y\994\1E\1F\00\00J_\05\15v3\00\0C%7\0F\0A\04\1F\123B\0Bw\A0\CC:\FE\D2g\00\00\01S7b?\E4\A0\C3:~F\D9\0Fb\1A\5C;3\19/\1F^^\82\94s\B5\D1UMD\00\05,\88\98\CF\95\A0\AA\97x\00\06\05\06:O_\00\03oU>\83\04-8G\1C\85b**(\0A\BB\F8\8D\02\05*!v\8BD?3\00<\1BJ\8B\A4Ld\F6q\00\00\003lD>\D5\C3$\AA\F8\8A\84\0D\02xe>g5)\22J8\00Zn\8E\C6Z\00\15-\14\00\15\00\14\10h\9E\A0T\00\00\00\090XrE?f]\0C|\82\1A\13\04\85\86\87p2Y|\81\D4B\07\004ag\D9\92\17x\00\02_)V z&0v\00\00 \10DV\8E\EF\00K\C2\A3\B5V\0CBq;\A50:\18()\17\1E\97Ri\C2\0E\C2q*\1D\1F\0D\087BS\82\AEl\00\00\00\00\18DK8(p\05!\14\89\9D0.\A7\CA\A2\CD\B9\9D\87h\A9+\1D\10NtM^A\0E\1D+\1F\8A\0B'0ob4\05\22\1BH%*F\0C.\AD;\0F\0E\8A\0B8r}x~I\9F\0F\0E\16EHl\108o8\D2\B7n9'\00\00\1D&\22N\9C\A9>\1A\00\00\05\19%(,j\00?H5\9DV5\00\CD\F0\D9\C7\FA\89\88\973\1E\00\180\88*\1A\00\00\00\1A\17C\17\7F\9Bs\14%nA\95V\19#GKK,b\91\11/@\80bTe[\00\1C\022;?:,\0D\1Bd}\8CyR\16\00\00\10\17\17\09?I\18\0D\18,\00\00\10!7\84\E1>\00\1F\0E\15)I\19\C9\A8\92\8A\FD\9D\B6bm{C\00]0\17\AC\90K\07\01<\D2\8C|!\A8\DB\D1\C1G\14.Q<]O\1E-k\B5\22X\06\00gFS\15E+!.J6NwG\004q\A7%^u@\0F\1C@h\0C\0C\00\01!%\01\0A\1E\00\00Mr\A8\00W]\00\07\8A\AA\B1\BE5;F\D1\A3=%MP\08-f\00C\C6\B6\87\00\93\93\A3\99\0C\C5\D8\C3\BAh0,3@V\91i9\11]\15Y\00>D>D\14Q.\0E1\0D.$\1E1B\0AJd\94\C8\87R6Z\99}{2\00\05 \0E\00\00\19\00\00V%l\00\A6\C0\BC\9A\9B\8E\A2\D8if\A6\CE\E4oV\1C$)\1A\5C)\00v\CF\AF\B0\A2V\DC:-\99\85\CA\D7\B5\0F3(,\22Eh@Y%\15-\003\91\C0\E4 \22\12\00\00WYE6\18\00\008\8B\AD\D4\C0y8Z:aX=\00#M*\03\00\1E\00\00\1B\0F\00\00+\9D\C8\F7\E3\83T\B4\FA\FF\A6\EC\8B7\07\18\12\1D\09\1F3\AE\A4\A4\DE\B7\D0\F2-\17\08\1A\9A\A0\8B\00D\06=#1b\0E#\1D\18N\00\00R\FF\C6ep\BA\A7:A\BF\8FM\1A(\13\1C\15H\C5\A4\CC\E4cNZ6+\11\00\05M#\0C\00\0E\00\000r\0D3\00\0B\84\C2\F4\D3\BE\C5\E2\CDr\C7\C2! \0C\11J,$\8F\A9\95\9F\C4x\A5\E7 !\17ie\80u\00A\ACzOn\00\00L \19?\1F\99\E3$\00\09C\9Aa\DFF\C0\94Y\00\22P\1C7Q(\C2\BA\C0T^\86\97ye@K\1B<\0E<!\14\00hUFiO\8EX\D7\C4\90\BE\F6\D9m}|\F3\00%\00\08/67:@u\A5\C8\CB\A2\FA\D43\1B\89QG{&\9Ds\83\A3\85\00`\84l$\A4\BAv\12\06\81\B2\00\C2\A0\97\D8\94\FF\A5\00\1ACf\AE\AD\B4\B9\CCXY\DB\DB\B0O$\0E\10\0C%\0265\00\008\14S\9B\DF\E1\CD\9F\E7N\99\A1\DD\D7zp\9B\003\15\1F?\141(\04%S\86\C8\DE\D0\EE\CE\0C6\CF\C1\B4\EEfT\93=\B2\CA\95\B8=!M##Qs\FFU\9A\B3\DC\E3\F9\DD\FF^\00\0DB\91\C1\C1\D6\EF\CED\0B\BE\CC\C4\C4\98/\00&\1F\00\00\1E\00\008\00\AF{\CA\D9\E9\D5\CE\00\81\FC\BC\DF\DE1\16\00\00\05\00)e/3\00`?{\88\EF\D6\B8\B8R\14\FF\DF\ED\FF\BE\9A\9Ca5\F1\E7\EC\0E>#S\80[Q\EE~/vf\CA\F6\15\7Fl\00c\96\5C]v\9BSC\F1\90\D4\D6\A2\19\10\00\00\16\1E\00\00\08\00\002$vod\EF\FF\A3\91\AF\DD\C1\FB\D2\B0\00\00\04\05\00\0E8V.\16&\A5G\9Cu\A7\B7\A2\07\97\8D\C9\E9X\A6\FF\CA\96\96\F9\BE\E9\E7\00Luj7\9B\F1\BE\94XU\D2G\C4\14\E7\E1=*]JeW\7F'\00\B5\8D\C7\C2\FF;\00\00\006\1F\00\00\000_\1Ca\5Cr\82\BC)\AD\B6\9D\95\CB\CB\D4\14)\05\02\17\16\0D(\00-\07\88\A7\B8_@y\88\A4\C9\CD\B2\ED\B1T\1B\B9\D6\84m\93\BC\B8\F6\8B%5\0A\B1{\C7\E1w\ABSEI\BE\F4\C0\C4Z\19\0F:l\7F,7P\B5\A4\98`\A0\E9$\00\00 \00\00\00\00VSlfAJ .9\B8\C2\D9\A8\C9\91\B0,\1E\06\1A(%\18\13\1D\11\11 >\00%HS{-\9D\B6\BB\B3\CEo\E6\C2\DA\99}\A4f:\E4\F25\00$So\FF\D0=\00\07\00J\A0\B7\E7\A3OMPPpA\00f\00i\D0\22\065\B3^H+\16\03\0C\1B\09B;\1B\22%]`2\17(\BA\C2CV\E2\9Dt,!\0D\00\12\00\06\0B\00\1B\03\00 )\0E\04\00Ke\B9\A2\A6\A1\FF\D7\8A\86vc\226:P\FF\96\0A>D\00\E4\009/\0D 'o\85\CE&@El\89/\00+\00\0E\1ES\05\02\16]\BE\0F\12\09\0F\00\00\00;70\1B\0CTs\12\0F\00\0F\A6)V6\D1n0\00\03\09\11\00\00\14\00\1F\09\0F)\19\08\190\00\00\FA\E3\C3\EC\A0\FF\98}O\02\0F\FF\D6)\E6\1E3XE\03\00\0F[%\1CT-\5Ch\AC\008I\95u\00g'\00\1D*\0C\05\10\1D\00M\00\16 \10\00\04\05RiO\00\00\00Zc\1C\0DVmC\15\C6\B1\A2f\00\02\17\05\04\03\0F\12\1E\02\005G\00\14F\14)\E5\D5\FF\DFc\FF\D5\B2t\05\AB\C2\AA(pD1z6/\00\1B1.#27;8B\00+wt\00BR\00\05\18\12\18\00\00\00R\00W\03\08\00\00\00\0B`g\17\0E\05\06\01H\03\0AINa\8C\DA\E0`kS\00\00\04\00\13\13\0E\0E\05\005\00\0B'\0B \0B@\AC],\10s\CB\B3>\13\B9\A2\D1\FF~\DA\8F\86\8C\E0N\003.\1Ajv\1A'\80\00EF\00T(\09 \00\00\00\1F\C4\89\91\11;\00\00\00\00\00\00\00ZR\15\0A\13\0E\08*\14'KOQ\1F[\BF}v\10\0E\00\04\18\0C\00\19\00p\B1b\B0\1F\0BC,\18\00U)\EFB\22\04\8C\93\A6\B5\C3\B7ox`\DC\A8U\92\C5\001\1F\5C\A8@0?!\05#\04\1DU1\00\00\00\05\0C]9\0A\00\0F\00\00\00\00\00\00\00\00PU\00\00\00\13(\1D,\16\19\11[Nc\17Olb\00\06\00\00@\11\13\14\B5\1E\C6\F4\FF\00\1B+\1Bj\10!\D4\FF?#]\E6w\BC\F0\B4\B6\85\C3\D6[H\C1\B7\D4\CE\A5\0BED\1DI4B\00\16\1B(aohi\0F\15\00\11H;5\16\00\00\00\00\00\00\003'\00\00\00\15.\0B\19\1F\12\08\9FEo=\A4l\00\00\02\0C\13O\00\09+\A9\C7e\D4\FF\ED\09\0FgT\0C\16:\B4\13\13\98\84bN\E4\CF\E0\BB\C8\D1\93\10\C2\BB\FF\DF\F1;-+\15%*80+\00\01 \15!nV>9\09\1A\0D\10\00&%\10\00\00\00\00\22#Z\00\00\00\1C\00\00(\00\00mY$\00\00\1F\00\00\00\12L8\00\0A\17\17\F3\EF\BD\9E\E6\E3\A5\E0\BF\04K\AC\10&\8D\12\D2\EC;\DE\CF\B6\D7\D3\A1\BCV\D9\E8\D7\E8\C8t\002\11 Y@*\17\00\00\00\01\016\00\0C\0A(9\10\0075=68\12\0E\10\12\09"], align 1
`define TAG_g_hana_bmp `MEMORY_CONTROLLER_TAG_SIZE'd3
`define TAG_g_hana_bmp_a {`TAG_g_hana_bmp, 23'b0}
// @hana_jpg = internal unnamed_addr constant [5207 x i8] c"\FF\D8\FF\E0\00\10JFIF\00\01\01\00\00\01\00\01\00\00\FF\DB\00C\00\03\02\02\02\02\02\03\02\02\02\03\03\03\03\04\06\04\04\04\04\04\08\06\06\05\06\09\08\0A\0A\09\08\09\09\0A\0C\0F\0C\0A\0B\0E\0B\09\09\0D\11\0D\0E\0F\10\10\11\10\0A\0C\12\13\12\10\13\0F\10\10\10\FF\DB\00C\01\03\03\03\04\03\04\08\04\04\08\10\0B\09\0B\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\FF\C0\00\11\08\00;\00Z\03\01\22\00\02\11\01\03\11\01\FF\C4\00\1F\00\00\01\05\01\01\01\01\01\01\00\00\00\00\00\00\00\00\01\02\03\04\05\06\07\08\09\0A\0B\FF\C4\00\B5\10\00\02\01\03\03\02\04\03\05\05\04\04\00\00\01}\01\02\03\00\04\11\05\12!1A\06\13Qa\07\22q\142\81\91\A1\08#B\B1\C1\15R\D1\F0$3br\82\09\0A\16\17\18\19\1A%&'()*456789:CDEFGHIJSTUVWXYZcdefghijstuvwxyz\83\84\85\86\87\88\89\8A\92\93\94\95\96\97\98\99\9A\A2\A3\A4\A5\A6\A7\A8\A9\AA\B2\B3\B4\B5\B6\B7\B8\B9\BA\C2\C3\C4\C5\C6\C7\C8\C9\CA\D2\D3\D4\D5\D6\D7\D8\D9\DA\E1\E2\E3\E4\E5\E6\E7\E8\E9\EA\F1\F2\F3\F4\F5\F6\F7\F8\F9\FA\FF\C4\00\1F\01\00\03\01\01\01\01\01\01\01\01\01\00\00\00\00\00\00\01\02\03\04\05\06\07\08\09\0A\0B\FF\C4\00\B5\11\00\02\01\02\04\04\03\04\07\05\04\04\00\01\02w\00\01\02\03\11\04\05!1\06\12AQ\07aq\13\222\81\08\14B\91\A1\B1\C1\09#3R\F0\15br\D1\0A\16$4\E1%\F1\17\18\19\1A&'()*56789:CDEFGHIJSTUVWXYZcdefghijstuvwxyz\82\83\84\85\86\87\88\89\8A\92\93\94\95\96\97\98\99\9A\A2\A3\A4\A5\A6\A7\A8\A9\AA\B2\B3\B4\B5\B6\B7\B8\B9\BA\C2\C3\C4\C5\C6\C7\C8\C9\CA\D2\D3\D4\D5\D6\D7\D8\D9\DA\E2\E3\E4\E5\E6\E7\E8\E9\EA\F2\F3\F4\F5\F6\F7\F8\F9\FA\FF\DA\00\0C\03\01\00\02\11\03\11\00?\00\F5\AF\00Z\EA\17\B3\AF\8A<O1\F1\A4z\9B\CF\A9\E9\BE\22\B0g\16zlV\F1*[\DA\AC\0CI,\C7\CC&@\19d,x\E3\0B\C0\E8\BA7\ED;\A3M\E3M;[\F1\7F\855M\06\D2\D6\E2\F6;\B8D\F0\DDXKr\04\883\90V(\90<\98,U\BEQ\EC\BF*x3\F6\8B\F1\0F\C2_\88m\A4E\AC\EAg\C2\D1\DE,q\DA\C3u\98#\B6\91\8C\8C!\8D\B7\04C\BF \00\02p:W\B0\F8\17\F6\C6\F0\C0\F1a\F1G\88\FC1,\1A\BF\8E\AE#\B6\BA\D5\12\FF\00\CB\B6\D2t\F5\8E;h\A4r\DC\C8\04\B0\B3HY@\0A\C4\8E\A5\1F\B7\0D\8E\A5\CF\19)k6\9B\BE\9A5\B7\9E\BD\FE\F3\17$\D2\E8}\0B\A9j\16\1E5\F8\18&\F1N\81\A4x\96MF\DA;\E9-t\EBi\EF\EDu\0ByD[\AF\E3\8Au\8EH\90\0D\D3\18\93,\81AR\E1\81?(\F8\93\F6a\F0\AB\93\A6\E8\CF\ACK\7Fs1k;\AB\0By/t\BB\A8\E5]\E9\11\5C\97\B7u\1F.r\C1\80\1DI\C0\FA\AB\C5\9E\0A\BA\D7\BE\C9\1B\F8\AA\D6\EEAcu5\BE\95gk\1D\C5\94\93\88\D53\05\C7\DD\B7<C\22\92\E1\882/(^\BC'\E1\87\C5O\8C\B0|G\82\D3\C4cV\9FE\B4i-f\D2\ACm\12[\95s\84\86m\EB\F2\ACFV`\1D\9F\0EU\8F@q\EA\CA\18Z\8B\92\B2Ml\B4\F4\D2\FD\1D\FF\00\22\BC\D9\F3O\C2\CDC\C7\1F\03\BE%\E9^+\83E}(C\A8\BF\87\EFn\AE\AD\9F\EC\F1\C9$\8A\B2\C5\B9\86\03\AA\ECoP;W\D6\1F\B5d+`\9AE\97\88\FC\09\A0\9B]P\C5\A8\B6\A5\16\9E\0C\DFhRCB\D2\E0a\F2\01 \9EGn\E3c\E1o\C3/\09|E\B6\F1/\8A|u>\BFn\D6~6\D7\E6\B8\85T\BA1i\96#\94\19\8D\DC(d%y\04\B1\07\1C\8E\B7\C3\FE(]Am>\0A|J\B5\D4\B5\D3\A9\D9\DF\ED\D4.\ED\A11j\91\C5\B5D\DEd` fY\10\02\83vv\93\8E\B5\E7R\C0\CA\AE\0EXjS\B7:\DE\D7\B5\FA|\CC\B5\94O\84<I\06\B3\ACG}\AB\5C\DA\AC\96\9206\A8\17\E4\B7\80\1C\02=s\EC;\F1\C5i|!\F8\07\E2\AF\8E\1A\F3\BE\9D\AC\DB\DA\C3\A4_Z\A6\A1n\087\11\D9I\9F\DFD\87\87;\94\A6\DE\C4\E7\9C`\FD\11\F1\13\E0\9F\82</\E1\F7\F0W\87m\AE\13Y\F0\ED\BCz\C5\AD\C5\C9\95\EE\1BO\09\FB\D5\B8\91\9B\CB~Y\86\11r\18\02\00\C1\AF\09\F8}\E1o\88V\9E;\8F\E2\0F\C2-@K<\12\AD\AC\D0)>K\DC\05\12$\05A\07k\0EA\CF^\87\9C\0F\03\0F\95\D5\C1b\A1N\B2RMtv\FC\EC\F4\EA\EC4\EF-t\B1\CE\FCm\F8\0B\F1\13\E1\7F\89\B5K{\AB5\B9\D2\22\BC[}>\EAX\D6)o\22\C2\95m\99\E0\E0\95=\06S#\AE+\99\F1w\81g\9B[\82\E6\C3M\91U\EC\95\B7\05\C0F\F9\BA\FE\95\EC?\17>>\F8\EB\E2\B7\8Auo\02\F8\DBQ\B7\D1om\8A\DB\C3k\0C*\B1\F9\E8\A0\EDgpd\CE}\FF\00\A8\A6|.\B6\F1\CE\B1\E1{\CB\1F\16\E8\B33\08d\FB-\D2[\B3)t\18 \B0\18\EF\EB^fsVP\C5?\AB\A7\EE\E8\D3\F3\FC\D7\99\A2i\E8\D9\F3v\9Bm\A8h\B7\D1\DDj\9AD\B3$3n\90\94;[\19\F5\EA+\AA\7F\11\F8vWi\17E\DA\1C\96\03j\F0\0F\E3Qj\BA7\8C[u\F5\D5\B5\CB\DA),\E2<\10\07Q\909\EE?\ADr\0F\1D\E1v)m1RN8#\8A\BAx\87k\E8_;\A7\A2G\AF\FC$\F8u\17\8En\AFo\F5\DD[K\83O\B3\B8\D2\AC^9\E4Xo$\8A\E2\EE\18D\D6\CA\E3\1B\11X\A3\15c\B0\B4}\B1\9FL\F8\A1\FB?M\F0\EF\C1V\97\FA\C6\89\F6\BD\13S\B3?\D8\BA\EA\98\18:\CD\03M\F6y\C0a\221\C6\E5#1\B9s\80K(\AE+\E1\BF\C4\8D[\E0g\ED\10\FE\13\F0\D6\A6\97^\16\83V\1Ar?\88\A5\FB'\D9,\AE\1E0\F2y\B20[`\AA\CC\CC\DC#\A2|\C3\A1\1FP|F\F1\EE\81\E3Mc\E2.\91\E1\BDoC\D4\FC\05\A0\F8j56\F1_\DB\CDay\AF\DD\C3!\86KI\1C\C8\B1\A5\BC,\F3J\B1\15_\B50\0F\B5\D0M_K\83\8E\1ExX\CA\1A\BB>\8B\AAo\CE\EB_\91\CE\E1k\A7\B8\BF\095_\88^)\B0\F0\96\A1\F1\93Z}WL\F1N\995\C8\B1\93X[x\E3\D3\E1\B6\1E]\E1Y\08Y\1C\80\B1\BA\E1T,\8D\B9\C3\90k\85\F1?\83\FC-\E1O\07\FC]\D5\FE\19\FCn\BB\D4|)\A4[\A3\C9\A5A\A5\BD\F4\F1\86\8D\02\B4\170L\825\F3\83\C4fua\09\8C\97iO\CD^%\E0\FF\00\DA\03\E2\87\84\ED\CC\9An\AF\0CI\E1\BD\1E\FF\00\C3\16\8B=\A2\C8#\B5\BC\1B\C6\C0\C5p\C2eP\C5\9B\05B\8CeJ\BF\D8\BF\00a\F8j\9E\11\F0\D6\9D\E2M\1F\C3\1An\B3\A6\DAG\A4\A0\B3\D7\AD\22\96{P\88\D0\A4r\CF,r,\B2\0F \14$o\957+H\85V-\B0S\86c\15\DA\1B\B6\9D\F5[][\C9\EF\AA\DCw\BA\B9\F3\AF\EC\CD\F1sT\D3<K\E2\AF\0C\CD\E1\0D\0A\FEC\E1\8DOS\B6\D6g\D2\FC\EB\BB\1B\B7\B21\ED\92l\11$w\12\98\D5\84\D8\05\C0\C3\1C\98d\F5\EF\8B\1F\17\BC-\A5x\A7\C0\9E,\BC\D2u?\0DxN\E8\8D[I\F1n\9Fl\D2KglaI\A1\D3\84 \B4N\A1'A6\E4\95\C8VU\89>\FAu\DF\13~\1Bh_\0B~\1D\CD\AB|\1A\9FH\16\F0\DE\DD\E8\FE'h\A4\82\E2}R\01 .\CF\1C_\BB\17Q\F9\9B7H\81\A3B\A2?/\E4e\E1\AC\BE x\93J\FD\9D\FC!\E1\7F\08xr\E2\0DN\E6K\9B\09u\B9F\FB;k\BBY\96\D7\CE]\E1\97sG\22\C2a\0A\A5\9F-\B7j\C8\E1a\E7W\0D(Q\A5S\9B\DD\BE\9EM-\15\FEW\D0\13\E5\F7d\B5G\B4\BF\8A\BE\1C|a\F0\A6\A6\DAn\A3\E1?\17\E2\C2V\D2\EDm#\B8\D2\B5\18o\17\CE\8E\7F1&gh\C4\CCG\96\EE\9BJ\C8\BB\81\18\91\BEx\F8Q\1E\B1\F03\C4\F1\F8\A2?\0E\1F\15\E8\9E<\10\BE\92\D1\C5-\B4k\229`\E8\85I\F9\06\EC\B9\00aA\CA\F7\E0\BCY\E3}O\C4>\1F\F0P\F8h\B6\B6z\A4\FAy\B7\D45Km>\0B\09,.-\94[\0BQ,gv\C5\8D\0Ch2Y\91W\92\0E\17\D9\FE\16\FC\5C\D4\FE%i>\09\F0?\C6\AF\14Xi\16\BA\AD\DD\ED\C4\17-\1A\C1>\BB$\8D$\96\CA\E5\00UY\DAH\F0\AA#YT\C2\18\16h\98c\88\CCiT\94SO\9A\FA?7m5\EC\9B\BA{|\8B\94Z\D5\1E[\F1\BF\C0\E3\C6?\1Dc\F1W\8C\FC=\ABj\1E\10\B5E\B8\9BJ\D3\9A+{\D8\92M\A2I\96h\F1\E6\95%\18\82A#\1E\A0\1F\A3\93[\D0?g=6\D2\185\1Dt\F8V\DDc\B7\BBcz\935\BD\C3\8D\F0\0C\9C\B6F\C6\DC1\B4\EF\03<\F1\F2\8F\C5}\7F\C6\BF\0E<c\AFx k\8E\9A\CC\16\E8/\05\CCj\EFw\1C\CB\E6\B8\CA\91\1A`0\04.9\C0\18\0A\B4\DB\9D\1F\C5\91\FC\1A\B7\D7\AE~\D6\BA\1F\89m\A32\DD\5C\93<l\D1\B9u\D8\D9&&\0C\A4\15\EB\80x\CA\A8<\F5\F3\08\C2SS\83rW\BF[.\97k\A6\DA\8D-9\91\8B\FBE\EB\7F\08d\D6f\F1\0F\C1\8DFE\8FW\BB72Z\012Gj\C7\E6\90\04\93;T\B9a\B0p\0E\ECq\8A\E2\AD\F5M-\E0\8D\E7K3+ .A\1F{\1C\FE\B5\CD\D8\E8v\FA\CC\1A\84\CF+F\22\965\0EO\0A\A5\B0\C4\8F\A63]:\F8#\C1\B1\01\19\F1\CD\BEPm\E0\8Cq_5\88\9D\1CD\DC\9A\E5\F2_\D3\1Cj$\BD\E4hx\8BD\F0\EC\DA\FE\BD\AF\DB\C7}v\FA\143\D9j6\80,r\C1; \84]\C6\1CbH\C5\C3\10\F1\FC\AD\1C\8F\B86\D9\03/\A7\FF\00\C33\FCg\F0\B7\84-\B4\81\AFF<\0B\AF\DB\DBk\17\D70D\B761}\A6(Q\AE\15#o2\E3t-\1Cp\BE\E8\C7\EFH\DC\8C\ECOU\F0\9B\C0^$\F8\EF\E3s\E2?\8A\DE\0F\D2\BCg\E1\D1\A7Z\E9W\DA\9F\9Fqc\A9\D8\8Bv\91b\B9\83\0Cf\95\D1\DAHK0\C9\8A\DD\17\92\BE[}W\A9\DD|=\D0t%\F1&\9Fq\AC}\8F\E1\D6\B5\A9Y\BD\B6\96\A2\CE\0Bx\84\9B/\8D\EA\A1+9B\AF\BB\04\0C\DC\B1\95v;\13\F4X\5C\05\E3*\94\FD\E8\B7\A5\9D\B4OU\D9\AD\F6\ECe\0Fy\DD\BB\1F\9D\BA\97\86\F4\AF\0F\FCo\D6\FC1m\E2KX\B4m3V.\D7\9A\B5\A1x\A6\8E9\BE\D1\E6\CBn\84\99#\DF\13n\0A\C3\F7{\B3\91\95<\FF\00\85\BCY\E1/\05x\F6\DF\C5.\FAu\C5\AD\B6\A3\1E\A7x4\DD\AB\05\B4\B0\DC\BB\C5\1D\BC2\A3\06\0A\C69U$\12!\87pq\94ll|r\F8\BBs\E3/\8A\1A\CC\B6\B7\16\17\F6\10\EA\DA\8C\B6\8Dnd\B8\B7\9DRi\13z\97fa\14\D1nc\FC;]I\1DZ\BE\BF\F8\11c\F0[\E2\AF\82\FC\03\A7^[j:\B7\88\FC*~\CBk\ACjJ\B6\BA\B5\94+\14\A0\B43\08\1A)\92\22\1B\CAG2\15\F2\B2K\BCjB\C0a\AF^q\A3-\22\EE\BE\FB=/}?\22i\DF\E18?\89\DF\B5\E7\88\AD|\14\9F\0F\BC\15\E0\AF\B0x\A3]\BF\9A\F7Q\83T\B33,\FAu\D8\DDmv\AD\03\A4\91\5C#\14\81\D6BWq&0\CAvG\B3\F0\83\F6\BE\D1\87\81c\B4\F1v\AB\A7\F8~\EBF6\16\B3XY\E9A\AD\F5%x\A5\8E\E2\F3P\88!\CC\B1Lb\90\C7\A7\B47\13\CA\E4\BAl;\E0\D1\F8E\1F\C6\FB\F7\F8\EB\F0\DA\F7\E1\F7\855\9F\12\DCj\0F4\96v,[M\92{\BD8%\893\19U\E4\B6\95 (\9F0e\F2\E52\FE\F0\92\BE5\E1\BF\D9\E7\C5\B7\82o\05\E8\B0iz\D6\A5v\91I\7Fk\7Ff\22kK=\CC\B2^\88\E4\1Ed\8B\1C\8A\B1\AE\C0\AD\BEdwX\95\B1]\15\E1\8B\A7(\FDV\F2[[kk\FDm\F9\1A7\AD\CB\BE?\93\C2^ \9F\5C\F0-\B6\B1u\AEi\B7\9Fek\8F\14\DD\DB\C9\0D\D2\DE\86P\B0\A5\B9(c\91mb\86\09\8B\87\91v\CF\08'1\AC\1E{\A1\F8\FF\00O\D0\BE%Z]x\F3P\BB\F1F\A4\B3Ci,\AA\D0%\8Ai\EC\88\B2C$1)\8Cl\8DB\18\D0++\AB.U\94\14\E8\BE\12\E9\16\13\F8\8B\C3\BA\A6\BD}w\F1\17[\D6$m\17J\D1,\EE%\B4\B7\96\F2e\8E\D2\07\B8\D5.\15E\ACB\08`+\B0K#\83\82\109a\EB\7F\0F\BFf\0F\01k\DAF\9F\E3\0Dg\C7\11\F8v\DAk\FB\AB}b\DE=z\D9\ACmZ{\B9\A0\B7\F2\DEEK\88\97\CFkr\AB1\DE\EB!G\D9*\18_\9AXj\D9\8E!\D4\82IG\A3v\DD\F5z\E9\F7\BB\5Cm\CDI4p\9F\B4L\D6\DF\1A4K\7F\1D\F8\1Et\D5-4=:\DBQ\BB\8AV\8A\19\ED\1Eg\9A'\B5D\00O*,P\A4\8E\8F&\E8\FC\E8\88/\92\AA\9F\06\FF\00i\EF\86\F3\E9\93\FC!\F8\89\E1\8BX\BC?\AC\A2[L\EDq\04V\B0\CAT\01(\8A\0Bx\8Ce\9D\E4b\E6F#\E5\0B\B7\15\85\F0W\C0z\CD\FF\00\C4\AB\9DM\F5K[\BD\17N\BC\D44\D5\8FV\BD{\08\B5;t\9C\C2TO\83$\8C@$\AB#,`\B0(w\15\AF\A0\FE*|\19\F06\A1\E2O\16x\97\C2\16\DAe\96\8F\A5h\10jW\1A\B4\D6\90\B6\9Fr&3\AB\B5\AC\FB\85\BF\96\BES,\9F\BD\01\1D\19I\DB\90j\8F\B6\C5M\D4\83I\FC-=S\B7Eu\B7M\CB\A74\9D\E4\AE|i\A2\D9h>\1F\F1\C6\A3\E1\9DKN\B9\BC\F0\A4\B7\93\C0\93\99\95\84\A03\18\D0H\BC6U}\89\EB\C5t\D2\F8\AB\C1\91J\F1\DA|9\F0B\C0\8CV%\97Q\888@x\0C3\D7\18\CDrwShv\DAe\AD\87\87\B5\18o\D2=jb\F7\A2\DDbF\90\A32\C4\02I\222\8C*\EFV \EF?\DD9\E6W\E0\ACZ\8A\8DA$\D5Qn\87\9C\15lr\00np\0Ey\1C\D7\CB\D5\A3\05^q\C4>F\9FGu\BF\935\E5\E4v\86\D6Ok\EEwZ\7F\EDC\E2\CF\0E\FD\A2\FB\C2z\80\D3u;9\A3\B3[x\96H\A1\D44\FF\00:96\F9\8A\DEnL\B0\A7\98\85\D7zH\FB\B7|\CB_[x\EB\E2\B6\BB\FBA\FC9\F1\F7\86$6>\1E\D3\A7\D2\B4\F5\86;m\5C\BD\E24\862\C8b$3\C4\B3G*\17\09\1Al\94\A9F\12\B9\87\F3W\C5\96\D0\E9\1E(\D5\EC\F4\E0\F1Ei\AB\5C\C1\0F\CE\CC\CA\91\CA\E1\06\E2I8\00rNx\AFG\F1W\8E<K\A3|(\F8i\E2\CD>\F6\14\D5\A7]G}\D3\D9\C3#\16\8E\F2\E1Q\F0\E8@u\120\0E\06\E1\C6\0F\CA\B8\FA\DC\1C\1E\1E\94\A9\D3\D9kn\8F\A3[7gs\99F\D7G\0E\F7\EF\A7\B2\88l\A0\86\E2\13\22;\A4\8CX\1F\99J\19\14\ED`F\FF\00\BB\F2\B2\B7\19\19\07\DC\B4\9F\8A_\19\FC#\E1\8F\0Cj\B3i\D7v\9A5\95\C4phS\CB\A0\BC\16\F2\DB\B2\CF\89\8C\B1*4\DB\D5\AEB\E6BY\BC\D2\8A[\CCj\F1\ED*\CA\DBV\F07\89|A\A9\C6n\B5/\ED\0B47R\B1i\08\9AW2\FC\C4\E7,FI\EB\C9\F55\FA\F1\FB.x3\C2\9F\13\7Fd\AF\87:'\8E\F4\0B=_O\F8\85\15\FE\99\E2;ic\0B\1D\F46R\5C\C3h\DBS\02)\A2\8E\DE\DDRx\F6\CA<\88\8E\FC\C6\A4pP\9DE7\1AN\DD\1F\E0\D7\AE\B6*\14\D4\93g\8B|3\F8\BB\F0?\C4\BF\B3\DE\8D\1F\8F<O\06\90\DA\95\EE\FF\00\14\E9\BAN\9Ds\15\C6\9B\22j)\9B\D9\EEm\22O.<\CB\04\D2\CB\88\F7<\FBQ\BC\C2\AE\9BZ\BF\8D>5k>?\F1>\B7\F0\E7\C4Z4zM\96\9Bm\E2\1B\0DRG{\8D?\C4\17\82&h\AD\C4\F7\12\C7o\1C/\14R,\D7^c\15\F3\90\0Cob<\07\F6\8F\F0\AE\8D\F0C^\F1\85\9F\C2\A8\EE\FC;\0D\B7\C2\FD*(\D6\DA\FAv\F95\0DS\EC\97\AA\DB\DD\B7\89afR\1B8c\BCa\C0j\FAO\E05\85\BE\8D\E0-%4\FF\005!\B7\D3|oa\15\BC\93<\B0,\1An\BFg\05\92\F9NJf8\DEA\BB\1B\98\BB\B3\96f$\FB8:\8E\A5G*\9B\AB'n\BA\FF\00\C1\B9J-\FB\B7\D8\F9\CBE\D6\FE#|$\F1\B7\8B~(|=\F8qi7\87d\B0\D5\AF\F4m*\EBQ\8AX\F4\DD\08$\91\A3\C3\E5\B1w\8E\19dYf\B6\8F'm\BBE!\1EZ\C8\BC\B7\EC\E7\F1\C3\C4\B6\9E9O\16\FCK\8EMkE\D5dkKa-\9D\B4p\C7*\5C[L\D3\C4\1B\08\B2\A9\B5\85\9As\CA<0\B1\93x\DD_\A1\BA\BF\86\B4+O\8CV\DA\AD\BE\9B\12\5C\E9\DE\0D\D4-m\9B\92\AB\14wZd\88\85O\CA\C1]\98\8D\C0\E3s\0E\84\8A\F8\03\FE\0A\0Fikc\FBTj\90X\C0\96\C9\A8Yi3\5C\88F\CF2G\0F\0B\B1\C7s\1C1\A9=N\DFRI\BCm9e\EB\DA\D2w\8A\96\CF\D3\CA\DD\CC\B9\A4\9D\AEV\F1/\C4-/[\F0\DD\F7\89\A5\BC6\DE\22\D5$}CR\98\EE\9E\DFMiT\ECX\D5\DBj\DDJ\C0\05n\91\A8\DF!\DD\B1Y>\1D|~\F8\A1\A3\F8\07\C3~\1F\F0\D4^\1A\B7\F0\7F\84o\AE\BE\DD\1D\FC\B6\B6\F6\BA\A4W\1B\D9\AC$\86w\DFu\0E\C9n\01\11$\B27\DA0\E1\D9\93w\85\F8\8FR\D44-Z\DA\1D\1E\FA\E2\CE8\D4\00\B0\C8Ts\C9'\D4\9C\9C\93\C9\EFW\EE/&\D7t=kR\D4\84oua0H%\8E%\84\80f*wl\03\7F\03\F8\B3\DC\F5&\BER8\BA\91\93\C4\C5\D9\CF{i\BE\BF\99\973VH\B5\E2\1B\9F\09=\ED\CD\8F\86t\D3\A5\E8\E6\F1\EE\ED\AC-\E73-\B9n\06\E7 \09%U\C2\B1\8Cye\95\CAnR\09\F5\1B\1F\DA?\C4\96VV\F6v\FF\00\0D\B4\C6\8A\08\92$;\E3\5C\AA\80\07\1B\B8\E0t\AE7\E2/\86t\1D\1FA\B4\9BL\D3\22\B7p\96\E8Y3\96\049\CBs\F3\1C\A8\E4\E4\F5\E7\93^\CD\E1\8F\02xZ\F3\C3zM\DD\CE\9A\EF4\F60I#}\A6Q\B9\9A5$\E06:\9A\F01R\85G\CD5}^\F7\FD\19\DDJ\B5X\D4\92R?\FF\D9", align 1
`define TAG_g_hana_jpg `MEMORY_CONTROLLER_TAG_SIZE'd2
`define TAG_g_hana_jpg_a {`TAG_g_hana_jpg, 23'b0}
// @izigzag_index = internal unnamed_addr constant [64 x i32] [i32 0, i32 1, i32 8, i32 16, i32 9, i32 2, i32 3, i32 10, i32 17, i32 24, i32 32, i32 25, i32 18, i32 11, i32 4, i32 5, i32 12, i32 19, i32 26, i32 33, i32 40, i32 48, i32 41, i32 34, i32 27, i32 20, i32 13, i32 6, i32 7, i32 14, i32 21, i32 28, i32 35, i32 42, i32 49, i32 56, i32 57, i32 50, i32 43, i32 36, i32 29, i32 22, i32 15, i32 23, i32 30, i32 37, i32 44, i32 51, i32 58, i32 59, i32 52, i32 45, i32 38, i32 31, i32 39, i32 46, i32 53, i32 60, i32 61, i32 54, i32 47, i32 55, i32 62, i32 63], align 4
`define TAG_g_izigzag_index `MEMORY_CONTROLLER_TAG_SIZE'd15
`define TAG_g_izigzag_index_a {`TAG_g_izigzag_index, 23'b0}
// @lmask = internal unnamed_addr constant [32 x i32] [i32 1, i32 3, i32 7, i32 15, i32 31, i32 63, i32 127, i32 255, i32 511, i32 1023, i32 2047, i32 4095, i32 8191, i32 16383, i32 32767, i32 65535, i32 131071, i32 262143, i32 524287, i32 1048575, i32 2097151, i32 4194303, i32 8388607, i32 16777215, i32 33554431, i32 67108863, i32 134217727, i32 268435455, i32 536870911, i32 1073741823, i32 2147483647, i32 -1], align 4
`define TAG_g_lmask `MEMORY_CONTROLLER_TAG_SIZE'd37
`define TAG_g_lmask_a {`TAG_g_lmask, 23'b0}
// @main_result = internal unnamed_addr global i32 0, align 4
`define TAG_g_main_result `MEMORY_CONTROLLER_TAG_SIZE'd16
`define TAG_g_main_result_a {`TAG_g_main_result, 23'b0}
// @out_ac_tbl_no_get_sos = internal unnamed_addr constant [3 x i32] [i32 0, i32 1, i32 1], align 4
`define TAG_g_out_ac_tbl_no_get_sos `MEMORY_CONTROLLER_TAG_SIZE'd8
`define TAG_g_out_ac_tbl_no_get_sos_a {`TAG_g_out_ac_tbl_no_get_sos, 23'b0}
// @out_comp_id_get_sos = internal unnamed_addr constant [3 x i32] [i32 1, i32 2, i32 3], align 4
`define TAG_g_out_comp_id_get_sos `MEMORY_CONTROLLER_TAG_SIZE'd7
`define TAG_g_out_comp_id_get_sos_a {`TAG_g_out_comp_id_get_sos, 23'b0}
// @out_count_get_dht = internal unnamed_addr constant [4 x i32] [i32 12, i32 162, i32 12, i32 162], align 4
`define TAG_g_out_count_get_dht `MEMORY_CONTROLLER_TAG_SIZE'd11
`define TAG_g_out_count_get_dht_a {`TAG_g_out_count_get_dht, 23'b0}
// @out_index_get_dht = internal unnamed_addr constant [4 x i32] [i32 0, i32 16, i32 1, i32 17], align 4
`define TAG_g_out_index_get_dht `MEMORY_CONTROLLER_TAG_SIZE'd10
`define TAG_g_out_index_get_dht_a {`TAG_g_out_index_get_dht, 23'b0}
// @out_index_get_sof = internal unnamed_addr constant [3 x i32] [i32 0, i32 1, i32 2], align 4
`define TAG_g_out_index_get_sof `MEMORY_CONTROLLER_TAG_SIZE'd5
`define TAG_g_out_index_get_sof_a {`TAG_g_out_index_get_sof, 23'b0}
// @out_length_get_dht = internal unnamed_addr constant [4 x i32] [i32 29, i32 179, i32 29, i32 179], align 4
`define TAG_g_out_length_get_dht `MEMORY_CONTROLLER_TAG_SIZE'd9
`define TAG_g_out_length_get_dht_a {`TAG_g_out_length_get_dht, 23'b0}
// @out_length_get_dqt = internal unnamed_addr constant [2 x i32] [i32 65, i32 65], align 4
`define TAG_g_out_length_get_dqt `MEMORY_CONTROLLER_TAG_SIZE'd12
`define TAG_g_out_length_get_dqt_a {`TAG_g_out_length_get_dqt, 23'b0}
// @out_num_get_dht = internal unnamed_addr constant [2 x i32] [i32 0, i32 1], align 4
`define TAG_g_out_num_get_dht `MEMORY_CONTROLLER_TAG_SIZE'd14
`define TAG_g_out_num_get_dht_a {`TAG_g_out_num_get_dht, 23'b0}
// @out_prec_get_dht = internal unnamed_addr constant [2 x i32] zeroinitializer, align 4
`define TAG_g_out_prec_get_dht `MEMORY_CONTROLLER_TAG_SIZE'd13
`define TAG_g_out_prec_get_dht_a {`TAG_g_out_prec_get_dht, 23'b0}
// @out_unread_marker = internal unnamed_addr constant [10 x i32] [i32 216, i32 224, i32 219, i32 219, i32 192, i32 196, i32 196, i32 196, i32 196, i32 218], align 4
`define TAG_g_out_unread_marker `MEMORY_CONTROLLER_TAG_SIZE'd4
`define TAG_g_out_unread_marker_a {`TAG_g_out_unread_marker, 23'b0}
// @out_v_samp_factor_get_sof = internal unnamed_addr constant [3 x i32] [i32 2, i32 1, i32 1], align 4
`define TAG_g_out_v_samp_factor_get_sof `MEMORY_CONTROLLER_TAG_SIZE'd6
`define TAG_g_out_v_samp_factor_get_sof_a {`TAG_g_out_v_samp_factor_get_sof, 23'b0}
// @p_jinfo_MCUWidth = internal unnamed_addr global i32 0, align 4
`define TAG_g_p_jinfo_MCUWidth `MEMORY_CONTROLLER_TAG_SIZE'd32
`define TAG_g_p_jinfo_MCUWidth_a {`TAG_g_p_jinfo_MCUWidth, 23'b0}
// @p_jinfo_ac_dhuff_tbl_maxcode = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_dhuff_tbl_maxcode `MEMORY_CONTROLLER_TAG_SIZE'd46
`define TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a {`TAG_g_p_jinfo_ac_dhuff_tbl_maxcode, 23'b0}
// @p_jinfo_ac_dhuff_tbl_mincode = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_dhuff_tbl_mincode `MEMORY_CONTROLLER_TAG_SIZE'd47
`define TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a {`TAG_g_p_jinfo_ac_dhuff_tbl_mincode, 23'b0}
// @p_jinfo_ac_dhuff_tbl_ml = internal unnamed_addr global [2 x i32] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_dhuff_tbl_ml `MEMORY_CONTROLLER_TAG_SIZE'd45
`define TAG_g_p_jinfo_ac_dhuff_tbl_ml_a {`TAG_g_p_jinfo_ac_dhuff_tbl_ml, 23'b0}
// @p_jinfo_ac_dhuff_tbl_valptr = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_dhuff_tbl_valptr `MEMORY_CONTROLLER_TAG_SIZE'd48
`define TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a {`TAG_g_p_jinfo_ac_dhuff_tbl_valptr, 23'b0}
// @p_jinfo_ac_xhuff_tbl_bits = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_xhuff_tbl_bits `MEMORY_CONTROLLER_TAG_SIZE'd26
`define TAG_g_p_jinfo_ac_xhuff_tbl_bits_a {`TAG_g_p_jinfo_ac_xhuff_tbl_bits, 23'b0}
// @p_jinfo_ac_xhuff_tbl_huffval = internal global [2 x [257 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_xhuff_tbl_huffval `MEMORY_CONTROLLER_TAG_SIZE'd27
`define TAG_g_p_jinfo_ac_xhuff_tbl_huffval_a {`TAG_g_p_jinfo_ac_xhuff_tbl_huffval, 23'b0}
// @p_jinfo_comps_info_ac_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_ac_tbl_no `MEMORY_CONTROLLER_TAG_SIZE'd25
`define TAG_g_p_jinfo_comps_info_ac_tbl_no_a {`TAG_g_p_jinfo_comps_info_ac_tbl_no, 23'b0}
// @p_jinfo_comps_info_dc_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_dc_tbl_no `MEMORY_CONTROLLER_TAG_SIZE'd24
`define TAG_g_p_jinfo_comps_info_dc_tbl_no_a {`TAG_g_p_jinfo_comps_info_dc_tbl_no, 23'b0}
// @p_jinfo_comps_info_h_samp_factor = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_h_samp_factor `MEMORY_CONTROLLER_TAG_SIZE'd21
`define TAG_g_p_jinfo_comps_info_h_samp_factor_a {`TAG_g_p_jinfo_comps_info_h_samp_factor, 23'b0}
// @p_jinfo_comps_info_id = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_id `MEMORY_CONTROLLER_TAG_SIZE'd20
`define TAG_g_p_jinfo_comps_info_id_a {`TAG_g_p_jinfo_comps_info_id, 23'b0}
// @p_jinfo_comps_info_index = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_index `MEMORY_CONTROLLER_TAG_SIZE'd19
`define TAG_g_p_jinfo_comps_info_index_a {`TAG_g_p_jinfo_comps_info_index, 23'b0}
// @p_jinfo_comps_info_quant_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_quant_tbl_no `MEMORY_CONTROLLER_TAG_SIZE'd23
`define TAG_g_p_jinfo_comps_info_quant_tbl_no_a {`TAG_g_p_jinfo_comps_info_quant_tbl_no, 23'b0}
// @p_jinfo_comps_info_v_samp_factor = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_v_samp_factor `MEMORY_CONTROLLER_TAG_SIZE'd22
`define TAG_g_p_jinfo_comps_info_v_samp_factor_a {`TAG_g_p_jinfo_comps_info_v_samp_factor, 23'b0}
// @p_jinfo_dc_dhuff_tbl_maxcode = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_dhuff_tbl_maxcode `MEMORY_CONTROLLER_TAG_SIZE'd41
`define TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a {`TAG_g_p_jinfo_dc_dhuff_tbl_maxcode, 23'b0}
// @p_jinfo_dc_dhuff_tbl_mincode = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_dhuff_tbl_mincode `MEMORY_CONTROLLER_TAG_SIZE'd42
`define TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a {`TAG_g_p_jinfo_dc_dhuff_tbl_mincode, 23'b0}
// @p_jinfo_dc_dhuff_tbl_ml = internal unnamed_addr global [2 x i32] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_dhuff_tbl_ml `MEMORY_CONTROLLER_TAG_SIZE'd40
`define TAG_g_p_jinfo_dc_dhuff_tbl_ml_a {`TAG_g_p_jinfo_dc_dhuff_tbl_ml, 23'b0}
// @p_jinfo_dc_dhuff_tbl_valptr = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_dhuff_tbl_valptr `MEMORY_CONTROLLER_TAG_SIZE'd43
`define TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a {`TAG_g_p_jinfo_dc_dhuff_tbl_valptr, 23'b0}
// @p_jinfo_dc_xhuff_tbl_bits = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_xhuff_tbl_bits `MEMORY_CONTROLLER_TAG_SIZE'd28
`define TAG_g_p_jinfo_dc_xhuff_tbl_bits_a {`TAG_g_p_jinfo_dc_xhuff_tbl_bits, 23'b0}
// @p_jinfo_dc_xhuff_tbl_huffval = internal global [2 x [257 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_xhuff_tbl_huffval `MEMORY_CONTROLLER_TAG_SIZE'd29
`define TAG_g_p_jinfo_dc_xhuff_tbl_huffval_a {`TAG_g_p_jinfo_dc_xhuff_tbl_huffval, 23'b0}
// @p_jinfo_image_height = internal unnamed_addr global i16 0, align 2
`define TAG_g_p_jinfo_image_height `MEMORY_CONTROLLER_TAG_SIZE'd17
`define TAG_g_p_jinfo_image_height_a {`TAG_g_p_jinfo_image_height, 23'b0}
// @p_jinfo_image_width = internal unnamed_addr global i16 0, align 2
`define TAG_g_p_jinfo_image_width `MEMORY_CONTROLLER_TAG_SIZE'd18
`define TAG_g_p_jinfo_image_width_a {`TAG_g_p_jinfo_image_width, 23'b0}
// @p_jinfo_quant_tbl_quantval = internal unnamed_addr global [4 x [64 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_quant_tbl_quantval `MEMORY_CONTROLLER_TAG_SIZE'd30
`define TAG_g_p_jinfo_quant_tbl_quantval_a {`TAG_g_p_jinfo_quant_tbl_quantval, 23'b0}
// @read_position = internal unnamed_addr global i32 -1, align 4
`define TAG_g_read_position `MEMORY_CONTROLLER_TAG_SIZE'd38
`define TAG_g_read_position_a {`TAG_g_read_position, 23'b0}
// @rgb_buf = internal global [4 x [3 x [64 x i32]]] zeroinitializer, align 4
`define TAG_g_rgb_buf `MEMORY_CONTROLLER_TAG_SIZE'd33
`define TAG_g_rgb_buf_a {`TAG_g_rgb_buf, 23'b0}
// @zigzag_index = internal unnamed_addr constant [64 x i32] [i32 0, i32 1, i32 5, i32 6, i32 14, i32 15, i32 27, i32 28, i32 2, i32 4, i32 7, i32 13, i32 16, i32 26, i32 29, i32 42, i32 3, i32 8, i32 12, i32 17, i32 25, i32 30, i32 41, i32 43, i32 9, i32 11, i32 18, i32 24, i32 31, i32 40, i32 44, i32 53, i32 10, i32 19, i32 23, i32 32, i32 39, i32 45, i32 52, i32 54, i32 20, i32 22, i32 33, i32 38, i32 46, i32 51, i32 55, i32 60, i32 21, i32 34, i32 37, i32 47, i32 50, i32 56, i32 59, i32 61, i32 35, i32 36, i32 48, i32 49, i32 57, i32 58, i32 62, i32 63], align 4
`define TAG_g_zigzag_index `MEMORY_CONTROLLER_TAG_SIZE'd31
`define TAG_g_zigzag_index_a {`TAG_g_zigzag_index, 23'b0}
// %huffcode = alloca [257 x i32], align 4
`define TAG_huff_make_dhuff_tb_0_huffcode `MEMORY_CONTROLLER_TAG_SIZE'd54
`define TAG_huff_make_dhuff_tb_0_huffcode_a {`TAG_huff_make_dhuff_tb_0_huffcode, 23'b0}
// %huffsize = alloca [257 x i32], align 4
`define TAG_huff_make_dhuff_tb_0_huffsize `MEMORY_CONTROLLER_TAG_SIZE'd53
`define TAG_huff_make_dhuff_tb_0_huffsize_a {`TAG_huff_make_dhuff_tb_0_huffsize, 23'b0}
// %HuffBuff.i.i = alloca [3 x [64 x i32]], align 4
`define TAG_main_0_HuffBuff_i_i `MEMORY_CONTROLLER_TAG_SIZE'd55
`define TAG_main_0_HuffBuff_i_i_a {`TAG_main_0_HuffBuff_i_i, 23'b0}
// %IDCTBuff.i.i = alloca [6 x [64 x i32]], align 4
`define TAG_main_0_IDCTBuff_i_i `MEMORY_CONTROLLER_TAG_SIZE'd56
`define TAG_main_0_IDCTBuff_i_i_a {`TAG_main_0_IDCTBuff_i_i, 23'b0}
// Turn off warning 'ignoring unsupported system task'
// altera message_off 10175
module top
(
clk,
reset,
start,
finish,
return_val
);
input clk;
input reset;
input start;
output wire finish;
output wire [31:0] return_val;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
wire memory_controller_enable;
wire memory_controller_write_enable;
wire memory_controller_waitrequest;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
wire [1:0] memory_controller_size;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
assign memory_controller_waitrequest = 0;
memory_controller memory_controller_inst (
.clk( clk ),
.memory_controller_address_a( memory_controller_address ),
.memory_controller_address_b( memory_controller_address ),
.memory_controller_enable( memory_controller_enable ),
.memory_controller_write_enable_a( 1'd0 ),
.memory_controller_write_enable_b( memory_controller_write_enable ),
.memory_controller_in_a( memory_controller_in ),
.memory_controller_in_b( memory_controller_in ),
.memory_controller_size_a( memory_controller_size ),
.memory_controller_size_b( memory_controller_size ),
.memory_controller_out_reg_a( ),
.memory_controller_out_reg_b( memory_controller_out )
);
main main_inst(
.clk( clk ),
.reset( reset ),
.start( start ),
.finish( finish ),
.return_val( return_val ),
.memory_controller_address( memory_controller_address ),
.memory_controller_enable( memory_controller_enable ),
.memory_controller_write_enable( memory_controller_write_enable ),
.memory_controller_waitrequest( memory_controller_waitrequest ),
.memory_controller_in( memory_controller_in ),
.memory_controller_size( memory_controller_size ),
.memory_controller_out( memory_controller_out )
);
endmodule
`timescale 1 ns / 1 ns
module memory_controller
(
clk,
memory_controller_address_a,
memory_controller_address_b,
memory_controller_enable,
memory_controller_write_enable_a,
memory_controller_write_enable_b,
memory_controller_in_a,
memory_controller_in_b,
memory_controller_size_a,
memory_controller_size_b,
memory_controller_out_reg_a,
memory_controller_out_reg_b
);
input clk;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_a;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_b;
input memory_controller_enable;
input memory_controller_write_enable_a;
input memory_controller_write_enable_b;
input [64-1:0] memory_controller_in_a;
input [1:0] memory_controller_size_a;
output reg [64-1:0] memory_controller_out_reg_a;
reg [64-1:0] memory_controller_out_a;
input [64-1:0] memory_controller_in_b;
input [1:0] memory_controller_size_b;
output reg [64-1:0] memory_controller_out_reg_b;
reg [64-1:0] memory_controller_out_b;
reg [12:0] hana_jpg_address_a;
reg hana_jpg_write_enable_a;
reg [7:0] hana_jpg_in_a;
wire [7:0] hana_jpg_out_a;
reg [12:0] hana_jpg_address_b;
reg hana_jpg_write_enable_b;
reg [7:0] hana_jpg_in_b;
wire [7:0] hana_jpg_out_b;
// @hana_jpg = internal unnamed_addr constant [5207 x i8] c"\FF\D8\FF\E0\00\10JFIF\00\01\01\00\00\01\00\01\00\00\FF\DB\00C\00\03\02\02\02\02\02\03\02\02\02\03\03\03\03\04\06\04\04\04\04\04\08\06\06\05\06\09\08\0A\0A\09\08\09\09\0A\0C\0F\0C\0A\0B\0E\0B\09\09\0D\11\0D\0E\0F\10\10\11\10\0A\0C\12\13\12\10\13\0F\10\10\10\FF\DB\00C\01\03\03\03\04\03\04\08\04\04\08\10\0B\09\0B\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\FF\C0\00\11\08\00;\00Z\03\01\22\00\02\11\01\03\11\01\FF\C4\00\1F\00\00\01\05\01\01\01\01\01\01\00\00\00\00\00\00\00\00\01\02\03\04\05\06\07\08\09\0A\0B\FF\C4\00\B5\10\00\02\01\03\03\02\04\03\05\05\04\04\00\00\01}\01\02\03\00\04\11\05\12!1A\06\13Qa\07\22q\142\81\91\A1\08#B\B1\C1\15R\D1\F0$3br\82\09\0A\16\17\18\19\1A%&'()*456789:CDEFGHIJSTUVWXYZcdefghijstuvwxyz\83\84\85\86\87\88\89\8A\92\93\94\95\96\97\98\99\9A\A2\A3\A4\A5\A6\A7\A8\A9\AA\B2\B3\B4\B5\B6\B7\B8\B9\BA\C2\C3\C4\C5\C6\C7\C8\C9\CA\D2\D3\D4\D5\D6\D7\D8\D9\DA\E1\E2\E3\E4\E5\E6\E7\E8\E9\EA\F1\F2\F3\F4\F5\F6\F7\F8\F9\FA\FF\C4\00\1F\01\00\03\01\01\01\01\01\01\01\01\01\00\00\00\00\00\00\01\02\03\04\05\06\07\08\09\0A\0B\FF\C4\00\B5\11\00\02\01\02\04\04\03\04\07\05\04\04\00\01\02w\00\01\02\03\11\04\05!1\06\12AQ\07aq\13\222\81\08\14B\91\A1\B1\C1\09#3R\F0\15br\D1\0A\16$4\E1%\F1\17\18\19\1A&'()*56789:CDEFGHIJSTUVWXYZcdefghijstuvwxyz\82\83\84\85\86\87\88\89\8A\92\93\94\95\96\97\98\99\9A\A2\A3\A4\A5\A6\A7\A8\A9\AA\B2\B3\B4\B5\B6\B7\B8\B9\BA\C2\C3\C4\C5\C6\C7\C8\C9\CA\D2\D3\D4\D5\D6\D7\D8\D9\DA\E2\E3\E4\E5\E6\E7\E8\E9\EA\F2\F3\F4\F5\F6\F7\F8\F9\FA\FF\DA\00\0C\03\01\00\02\11\03\11\00?\00\F5\AF\00Z\EA\17\B3\AF\8A<O1\F1\A4z\9B\CF\A9\E9\BE\22\B0g\16zlV\F1*[\DA\AC\0CI,\C7\CC&@\19d,x\E3\0B\C0\E8\BA7\ED;\A3M\E3M;[\F1\7F\855M\06\D2\D6\E2\F6;\B8D\F0\DDXKr\04\883\90V(\90<\98,U\BEQ\EC\BF*x3\F6\8B\F1\0F\C2_\88m\A4E\AC\EAg\C2\D1\DE,q\DA\C3u\98#\B6\91\8C\8C!\8D\B7\04C\BF \00\02p:W\B0\F8\17\F6\C6\F0\C0\F1a\F1G\88\FC1,\1A\BF\8E\AE#\B6\BA\D5\12\FF\00\CB\B6\D2t\F5\8E;h\A4r\DC\C8\04\B0\B3HY@\0A\C4\8E\A5\1F\B7\0D\8E\A5\CF\19)k6\9B\BE\9A5\B7\9E\BD\FE\F3\17$\D2\E8}\0B\A9j\16\1E5\F8\18&\F1N\81\A4x\96MF\DA;\E9-t\EBi\EF\EDu\0ByD[\AF\E3\8Au\8EH\90\0D\D3\18\93,\81AR\E1\81?(\F8\93\F6a\F0\AB\93\A6\E8\CF\ACK\7Fs1k;\AB\0By/t\BB\A8\E5]\E9\11\5C\97\B7u\1F.r\C1\80\1DI\C0\FA\AB\C5\9E\0A\BA\D7\BE\C9\1B\F8\AA\D6\EEAcu5\BE\95gk\1D\C5\94\93\88\D53\05\C7\DD\B7<C\22\92\E1\882/(^\BC'\E1\87\C5O\8C\B0|G\82\D3\C4cV\9FE\B4i-f\D2\ACm\12[\95s\84\86m\EB\F2\ACFV`\1D\9F\0EU\8F@q\EA\CA\18Z\8B\92\B2Ml\B4\F4\D2\FD\1D\FF\00\22\BC\D9\F3O\C2\CDC\C7\1F\03\BE%\E9^+\83E}(C\A8\BF\87\EFn\AE\AD\9F\EC\F1\C9$\8A\B2\C5\B9\86\03\AA\ECoP;W\D6\1F\B5d+`\9AE\97\88\FC\09\A0\9B]P\C5\A8\B6\A5\16\9E\0C\DFhRCB\D2\E0a\F2\01 \9EGn\E3c\E1o\C3/\09|E\B6\F1/\8A|u>\BFn\D6~6\D7\E6\B8\85T\BA1i\96#\94\19\8D\DC(d%y\04\B1\07\1C\8E\B7\C3\FE(]Am>\0A|J\B5\D4\B5\D3\A9\D9\DF\ED\D4.\ED\A11j\91\C5\B5D\DEd` fY\10\02\83vv\93\8E\B5\E7R\C0\CA\AE\0EXjS\B7:\DE\D7\B5\FA|\CC\B5\94O\84<I\06\B3\ACG}\AB\5C\DA\AC\96\9206\A8\17\E4\B7\80\1C\02=s\EC;\F1\C5i|!\F8\07\E2\AF\8E\1A\F3\BE\9D\AC\DB\DA\C3\A4_Z\A6\A1n\087\11\D9I\9F\DFD\87\87;\94\A6\DE\C4\E7\9C`\FD\11\F1\13\E0\9F\82</\E1\F7\F0W\87m\AE\13Y\F0\ED\BCz\C5\AD\C5\C9\95\EE\1BO\09\FB\D5\B8\91\9B\CB~Y\86\11r\18\02\00\C1\AF\09\F8}\E1o\88V\9E;\8F\E2\0F\C2-@K<\12\AD\AC\D0)>K\DC\05\12$\05A\07k\0EA\CF^\87\9C\0F\03\0F\95\D5\C1b\A1N\B2RMtv\FC\EC\F4\EA\EC4\EF-t\B1\CE\FCm\F8\0B\F1\13\E1\7F\89\B5K{\AB5\B9\D2\22\BC[}>\EAX\D6)o\22\C2\95m\99\E0\E0\95=\06S#\AE+\99\F1w\81g\9B[\82\E6\C3M\91U\EC\95\B7\05\C0F\F9\BA\FE\95\EC?\17>>\F8\EB\E2\B7\8Auo\02\F8\DBQ\B7\D1om\8A\DB\C3k\0C*\B1\F9\E8\A0\EDgpd\CE}\FF\00\A8\A6|.\B6\F1\CE\B1\E1{\CB\1F\16\E8\B33\08d\FB-\D2[\B3)t\18 \B0\18\EF\EB^fsVP\C5?\AB\A7\EE\E8\D3\F3\FC\D7\99\A2i\E8\D9\F3v\9Bm\A8h\B7\D1\DDj\9AD\B3$3n\90\94;[\19\F5\EA+\AA\7F\11\F8vWi\17E\DA\1C\96\03j\F0\0F\E3Qj\BA7\8C[u\F5\D5\B5\CB\DA),\E2<\10\07Q\909\EE?\ADr\0F\1D\E1v)m1RN8#\8A\BAx\87k\E8_;\A7\A2G\AF\FC$\F8u\17\8En\AFo\F5\DD[K\83O\B3\B8\D2\AC^9\E4Xo$\8A\E2\EE\18D\D6\CA\E3\1B\11X\A3\15c\B0\B4}\B1\9FL\F8\A1\FB?M\F0\EF\C1V\97\FA\C6\89\F6\BD\13S\B3?\D8\BA\EA\98\18:\CD\03M\F6y\C0a\221\C6\E5#1\B9s\80K(\AE+\E1\BF\C4\8D[\E0g\ED\10\FE\13\F0\D6\A6\97^\16\83V\1Ar?\88\A5\FB'\D9,\AE\1E0\F2y\B20[`\AA\CC\CC\DC#\A2|\C3\A1\1FP|F\F1\EE\81\E3Mc\E2.\91\E1\BDoC\D4\FC\05\A0\F8j56\F1_\DB\CDay\AF\DD\C3!\86KI\1C\C8\B1\A5\BC,\F3J\B1\15_\B50\0F\B5\D0M_K\83\8E\1ExX\CA\1A\BB>\8B\AAo\CE\EB_\91\CE\E1k\A7\B8\BF\095_\88^)\B0\F0\96\A1\F1\93Z}WL\F1N\995\C8\B1\93X[x\E3\D3\E1\B6\1E]\E1Y\08Y\1C\80\B1\BA\E1T,\8D\B9\C3\90k\85\F1?\83\FC-\E1O\07\FC]\D5\FE\19\FCn\BB\D4|)\A4[\A3\C9\A5A\A5\BD\F4\F1\86\8D\02\B4\170L\825\F3\83\C4fua\09\8C\97iO\CD^%\E0\FF\00\DA\03\E2\87\84\ED\CC\9An\AF\0CI\E1\BD\1E\FF\00\C3\16\8B=\A2\C8#\B5\BC\1B\C6\C0\C5p\C2eP\C5\9B\05B\8CeJ\BF\D8\BF\00a\F8j\9E\11\F0\D6\9D\E2M\1F\C3\1An\B3\A6\DAG\A4\A0\B3\D7\AD\22\96{P\88\D0\A4r\CF,r,\B2\0F \14$o\957+H\85V-\B0S\86c\15\DA\1B\B6\9D\F5[][\C9\EF\AA\DCw\BA\B9\F3\AF\EC\CD\F1sT\D3<K\E2\AF\0C\CD\E1\0D\0A\FEC\E1\8DOS\B6\D6g\D2\FC\EB\BB\1B\B7\B21\ED\92l\11$w\12\98\D5\84\D8\05\C0\C3\1C\98d\F5\EF\8B\1F\17\BC-\A5x\A7\C0\9E,\BC\D2u?\0DxN\E8\8D[I\F1n\9Fl\D2KglaI\A1\D3\84 \B4N\A1'A6\E4\95\C8VU\89>\FAu\DF\13~\1Bh_\0B~\1D\CD\AB|\1A\9FH\16\F0\DE\DD\E8\FE'h\A4\82\E2}R\01 .\CF\1C_\BB\17Q\F9\9B7H\81\A3B\A2?/\E4e\E1\AC\BE x\93J\FD\9D\FC!\E1\7F\08xr\E2\0DN\E6K\9B\09u\B9F\FB;k\BBY\96\D7\CE]\E1\97sG\22\C2a\0A\A5\9F-\B7j\C8\E1a\E7W\0D(Q\A5S\9B\DD\BE\9EM-\15\FEW\D0\13\E5\F7d\B5G\B4\BF\8A\BE\1C|a\F0\A6\A6\DAn\A3\E1?\17\E2\C2V\D2\EDm#\B8\D2\B5\18o\17\CE\8E\7F1&gh\C4\CCG\96\EE\9BJ\C8\BB\81\18\91\BEx\F8Q\1E\B1\F03\C4\F1\F8\A2?\0E\1F\15\E8\9E<\10\BE\92\D1\C5-\B4k\229`\E8\85I\F9\06\EC\B9\00aA\CA\F7\E0\BCY\E3}O\C4>\1F\F0P\F8h\B6\B6z\A4\FAy\B7\D45Km>\0B\09,.-\94[\0BQ,gv\C5\8D\0Ch2Y\91W\92\0E\17\D9\FE\16\FC\5C\D4\FE%i>\09\F0?\C6\AF\14Xi\16\BA\AD\DD\ED\C4\17-\1A\C1>\BB$\8D$\96\CA\E5\00UY\DAH\F0\AA#YT\C2\18\16h\98c\88\CCiT\94SO\9A\FA?7m5\EC\9B\BA{|\8B\94Z\D5\1E[\F1\BF\C0\E3\C6?\1Dc\F1W\8C\FC=\ABj\1E\10\B5E\B8\9BJ\D3\9A+{\D8\92M\A2I\96h\F1\E6\95%\18\82A#\1E\A0\1F\A3\93[\D0?g=6\D2\185\1Dt\F8V\DDc\B7\BBcz\935\BD\C3\8D\F0\0C\9C\B6F\C6\DC1\B4\EF\03<\F1\F2\8F\C5}\7F\C6\BF\0E<c\AFx k\8E\9A\CC\16\E8/\05\CCj\EFw\1C\CB\E6\B8\CA\91\1A`0\04.9\C0\18\0A\B4\DB\9D\1F\C5\91\FC\1A\B7\D7\AE~\D6\BA\1F\89m\A32\DD\5C\93<l\D1\B9u\D8\D9&&\0C\A4\15\EB\80x\CA\A8<\F5\F3\08\C2SS\83rW\BF[.\97k\A6\DA\8D-9\91\8B\FBE\EB\7F\08d\D6f\F1\0F\C1\8DFE\8FW\BB72Z\012Gj\C7\E6\90\04\93;T\B9a\B0p\0E\ECq\8A\E2\AD\F5M-\E0\8D\E7K3+ .A\1F{\1C\FE\B5\CD\D8\E8v\FA\CC\1A\84\CF+F\22\965\0EO\0A\A5\B0\C4\8F\A63]:\F8#\C1\B1\01\19\F1\CD\BEPm\E0\8Cq_5\88\9D\1CD\DC\9A\E5\F2_\D3\1Cj$\BD\E4hx\8BD\F0\EC\DA\FE\BD\AF\DB\C7}v\FA\143\D9j6\80,r\C1; \84]\C6\1CbH\C5\C3\10\F1\FC\AD\1C\8F\B86\D9\03/\A7\FF\00\C33\FCg\F0\B7\84-\B4\81\AFF<\0B\AF\DB\DBk\17\D70D\B761}\A6(Q\AE\15#o2\E3t-\1Cp\BE\E8\C7\EFH\DC\8C\ECOU\F0\9B\C0^$\F8\EF\E3s\E2?\8A\DE\0F\D2\BCg\E1\D1\A7Z\E9W\DA\9F\9Fqc\A9\D8\8Bv\91b\B9\83\0Cf\95\D1\DAHK0\C9\8A\DD\17\92\BE[}W\A9\DD|=\D0t%\F1&\9Fq\AC}\8F\E1\D6\B5\A9Y\BD\B6\96\A2\CE\0Bx\84\9B/\8D\EA\A1+9B\AF\BB\04\0C\DC\B1\95v;\13\F4X\5C\05\E3*\94\FD\E8\B7\A5\9D\B4OU\D9\AD\F6\ECe\0Fy\DD\BB\1F\9D\BA\97\86\F4\AF\0F\FCo\D6\FC1m\E2KX\B4m3V.\D7\9A\B5\A1x\A6\8E9\BE\D1\E6\CBn\84\99#\DF\13n\0A\C3\F7{\B3\91\95<\FF\00\85\BCY\E1/\05x\F6\DF\C5.\FAu\C5\AD\B6\A3\1E\A7x4\DD\AB\05\B4\B0\DC\BB\C5\1D\BC2\A3\06\0A\C69U$\12!\87pq\94ll|r\F8\BBs\E3/\8A\1A\CC\B6\B7\16\17\F6\10\EA\DA\8C\B6\8Dnd\B8\B7\9DRi\13z\97fa\14\D1nc\FC;]I\1DZ\BE\BF\F8\11c\F0[\E2\AF\82\FC\03\A7^[j:\B7\88\FC*~\CBk\ACjJ\B6\BA\B5\94+\14\A0\B43\08\1A)\92\22\1B\CAG2\15\F2\B2K\BCjB\C0a\AF^q\A3-\22\EE\BE\FB=/}?\22i\DF\E18?\89\DF\B5\E7\88\AD|\14\9F\0F\BC\15\E0\AF\B0x\A3]\BF\9A\F7Q\83T\B33,\FAu\D8\DDmv\AD\03\A4\91\5C#\14\81\D6BWq&0\CAvG\B3\F0\83\F6\BE\D1\87\81c\B4\F1v\AB\A7\F8~\EBF6\16\B3XY\E9A\AD\F5%x\A5\8E\E2\F3P\88!\CC\B1Lb\90\C7\A7\B47\13\CA\E4\BAl;\E0\D1\F8E\1F\C6\FB\F7\F8\EB\F0\DA\F7\E1\F7\855\9F\12\DCj\0F4\96v,[M\92{\BD8%\893\19U\E4\B6\95 (\9F0e\F2\E52\FE\F0\92\BE5\E1\BF\D9\E7\C5\B7\82o\05\E8\B0iz\D6\A5v\91I\7Fk\7Ff\22kK=\CC\B2^\88\E4\1Ed\8B\1C\8A\B1\AE\C0\AD\BEdwX\95\B1]\15\E1\8B\A7(\FDV\F2[[kk\FDm\F9\1A7\AD\CB\BE?\93\C2^ \9F\5C\F0-\B6\B1u\AEi\B7\9Fek\8F\14\DD\DB\C9\0D\D2\DE\86P\B0\A5\B9(c\91mb\86\09\8B\87\91v\CF\08'1\AC\1E{\A1\F8\FF\00O\D0\BE%Z]x\F3P\BB\F1F\A4\B3Ci,\AA\D0%\8Ai\EC\88\B2C$1)\8Cl\8DB\18\D0++\AB.U\94\14\E8\BE\12\E9\16\13\F8\8B\C3\BA\A6\BD}w\F1\17[\D6$m\17J\D1,\EE%\B4\B7\96\F2e\8E\D2\07\B8\D5.\15E\ACB\08`+\B0K#\83\82\109a\EB\7F\0F\BFf\0F\01k\DAF\9F\E3\0Dg\C7\11\F8v\DAk\FB\AB}b\DE=z\D9\ACmZ{\B9\A0\B7\F2\DEEK\88\97\CFkr\AB1\DE\EB!G\D9*\18_\9AXj\D9\8E!\D4\82IG\A3v\DD\F5z\E9\F7\BB\5Cm\CDI4p\9F\B4L\D6\DF\1A4K\7F\1D\F8\1Et\D5-4=:\DBQ\BB\8AV\8A\19\ED\1Eg\9A'\B5D\00O*,P\A4\8E\8F&\E8\FC\E8\88/\92\AA\9F\06\FF\00i\EF\86\F3\E9\93\FC!\F8\89\E1\8BX\BC?\AC\A2[L\EDq\04V\B0\CAT\01(\8A\0Bx\8Ce\9D\E4b\E6F#\E5\0B\B7\15\85\F0W\C0z\CD\FF\00\C4\AB\9DM\F5K[\BD\17N\BC\D44\D5\8FV\BD{\08\B5;t\9C\C2TO\83$\8C@$\AB#,`\B0(w\15\AF\A0\FE*|\19\F06\A1\E2O\16x\97\C2\16\DAe\96\8F\A5h\10jW\1A\B4\D6\90\B6\9Fr&3\AB\B5\AC\FB\85\BF\96\BES,\9F\BD\01\1D\19I\DB\90j\8F\B6\C5M\D4\83I\FC-=S\B7Eu\B7M\CB\A74\9D\E4\AE|i\A2\D9h>\1F\F1\C6\A3\E1\9DKN\B9\BC\F0\A4\B7\93\C0\93\99\95\84\A03\18\D0H\BC6U}\89\EB\C5t\D2\F8\AB\C1\91J\F1\DA|9\F0B\C0\8CV%\97Q\888@x\0C3\D7\18\CDrwShv\DAe\AD\87\87\B5\18o\D2=jb\F7\A2\DDbF\90\A32\C4\02I\222\8C*\EFV \EF?\DD9\E6W\E0\ACZ\8A\8DA$\D5Qn\87\9C\15lr\00np\0Ey\1C\D7\CB\D5\A3\05^q\C4>F\9FGu\BF\935\E5\E4v\86\D6Ok\EEwZ\7F\EDC\E2\CF\0E\FD\A2\FB\C2z\80\D3u;9\A3\B3[x\96H\A1\D44\FF\00:96\F9\8A\DEnL\B0\A7\98\85\D7zH\FB\B7|\CB_[x\EB\E2\B6\BB\FBA\FC9\F1\F7\86$6>\1E\D3\A7\D2\B4\F5\86;m\5C\BD\E24\862\C8b$3\C4\B3G*\17\09\1Al\94\A9F\12\B9\87\F3W\C5\96\D0\E9\1E(\D5\EC\F4\E0\F1Ei\AB\5C\C1\0F\CE\CC\CA\91\CA\E1\06\E2I8\00rNx\AFG\F1W\8E<K\A3|(\F8i\E2\CD>\F6\14\D5\A7]G}\D3\D9\C3#\16\8E\F2\E1Q\F0\E8@u\120\0E\06\E1\C6\0F\CA\B8\FA\DC\1C\1E\1E\94\A9\D3\D9kn\8F\A3[7gs\99F\D7G\0E\F7\EF\A7\B2\88l\A0\86\E2\13\22;\A4\8CX\1F\99J\19\14\ED`F\FF\00\BB\F2\B2\B7\19\19\07\DC\B4\9F\8A_\19\FC#\E1\8F\0Cj\B3i\D7v\9A5\95\C4phS\CB\A0\BC\16\F2\DB\B2\CF\89\8C\B1*4\DB\D5\AEB\E6BY\BC\D2\8A[\CCj\F1\ED*\CA\DBV\F07\89|A\A9\C6n\B5/\ED\0B47R\B1i\08\9AW2\FC\C4\E7,FI\EB\C9\F55\FA\F1\FB.x3\C2\9F\13\7Fd\AF\87:'\8E\F4\0B=_O\F8\85\15\FE\99\E2;ic\0B\1D\F46R\5C\C3h\DBS\02)\A2\8E\DE\DDRx\F6\CA<\88\8E\FC\C6\A4pP\9DE7\1AN\DD\1F\E0\D7\AE\B6*\14\D4\93g\8B|3\F8\BB\F0?\C4\BF\B3\DE\8D\1F\8F<O\06\90\DA\95\EE\FF\00\14\E9\BAN\9Ds\15\C6\9B\22j)\9B\D9\EEm\22O.<\CB\04\D2\CB\88\F7<\FBQ\BC\C2\AE\9BZ\BF\8D>5k>?\F1>\B7\F0\E7\C4Z4zM\96\9Bm\E2\1B\0DRG{\8D?\C4\17\82&h\AD\C4\F7\12\C7o\1C/\14R,\D7^c\15\F3\90\0Cob<\07\F6\8F\F0\AE\8D\F0C^\F1\85\9F\C2\A8\EE\FC;\0D\B7\C2\FD*(\D6\DA\FAv\F95\0DS\EC\97\AA\DB\DD\B7\89afR\1B8c\BCa\C0j\FAO\E05\85\BE\8D\E0-%4\FF\005!\B7\D3|oa\15\BC\93<\B0,\1An\BFg\05\92\F9NJf8\DEA\BB\1B\98\BB\B3\96f$\FB8:\8E\A5G*\9B\AB'n\BA\FF\00\C1\B9J-\FB\B7\D8\F9\CBE\D6\FE#|$\F1\B7\8B~(|=\F8qi7\87d\B0\D5\AF\F4m*\EBQ\8AX\F4\DD\08$\91\A3\C3\E5\B1w\8E\19dYf\B6\8F'm\BBE!\1EZ\C8\BC\B7\EC\E7\F1\C3\C4\B6\9E9O\16\FCK\8EMkE\D5dkKa-\9D\B4p\C7*\5C[L\D3\C4\1B\08\B2\A9\B5\85\9As\CA<0\B1\93x\DD_\A1\BA\BF\86\B4+O\8CV\DA\AD\BE\9B\12\5C\E9\DE\0D\D4-m\9B\92\AB\14wZd\88\85O\CA\C1]\98\8D\C0\E3s\0E\84\8A\F8\03\FE\0A\0Fikc\FBTj\90X\C0\96\C9\A8Yi3\5C\88F\CF2G\0F\0B\B1\C7s\1C1\A9=N\DFRI\BCm9e\EB\DA\D2w\8A\96\CF\D3\CA\DD\CC\B9\A4\9D\AEV\F1/\C4-/[\F0\DD\F7\89\A5\BC6\DE\22\D5$}CR\98\EE\9E\DFMiT\ECX\D5\DBj\DDJ\C0\05n\91\A8\DF!\DD\B1Y>\1D|~\F8\A1\A3\F8\07\C3~\1F\F0\D4^\1A\B7\F0\7F\84o\AE\BE\DD\1D\FC\B6\B6\F6\BA\A4W\1B\D9\AC$\86w\DFu\0E\C9n\01\11$\B27\DA0\E1\D9\93w\85\F8\8FR\D44-Z\DA\1D\1E\FA\E2\CE8\D4\00\B0\C8Ts\C9'\D4\9C\9C\93\C9\EFW\EE/&\D7t=kR\D4\84oua0H%\8E%\84\80f*wl\03\7F\03\F8\B3\DC\F5&\BER8\BA\91\93\C4\C5\D9\CF{i\BE\BF\99\973VH\B5\E2\1B\9F\09=\ED\CD\8F\86t\D3\A5\E8\E6\F1\EE\ED\AC-\E73-\B9n\06\E7 \09%U\C2\B1\8Cye\95\CAnR\09\F5\1B\1F\DA?\C4\96VV\F6v\FF\00\0D\B4\C6\8A\08\92$;\E3\5C\AA\80\07\1B\B8\E0t\AE7\E2/\86t\1D\1FA\B4\9BL\D3\22\B7p\96\E8Y3\96\049\CBs\F3\1C\A8\E4\E4\F5\E7\93^\CD\E1\8F\02xZ\F3\C3zM\DD\CE\9A\EF4\F60I#}\A6Q\B9\9A5$\E06:\9A\F01R\85G\CD5}^\F7\FD\19\DDJ\B5X\D4\92R?\FF\D9", align 1
ram_two_ports hana_jpg (
.clk( clk ),
.address_a( hana_jpg_address_a ),
.wren_a( hana_jpg_write_enable_a ),
.data_a( hana_jpg_in_a ),
.address_b( hana_jpg_address_b ),
.wren_b( hana_jpg_write_enable_b ),
.data_b( hana_jpg_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( hana_jpg_out_a ),
.q_b( hana_jpg_out_b)
);
defparam hana_jpg.width_a = 8;
defparam hana_jpg.widthad_a = 13;
defparam hana_jpg.width_b = 8;
defparam hana_jpg.widthad_b = 13;
defparam hana_jpg.width_be_a = 1;
defparam hana_jpg.width_be_b = 1;
defparam hana_jpg.numwords_a = 5207;
defparam hana_jpg.numwords_b = 5207;
defparam hana_jpg.init_file = "hana_jpg.mif";
reg [13:0] hana_bmp_address_a;
reg hana_bmp_write_enable_a;
reg [7:0] hana_bmp_in_a;
wire [7:0] hana_bmp_out_a;
reg [13:0] hana_bmp_address_b;
reg hana_bmp_write_enable_b;
reg [7:0] hana_bmp_in_b;
wire [7:0] hana_bmp_out_b;
// @hana_bmp = internal unnamed_addr constant [3 x [5310 x i8]] [[5310 x i8] c"\BC\D1\BE\99\8Fg\95\C0\AC\9D\BD\C0\A4\C3\BC\B5\C1\A7\BC\D2\B1\8E%\0A\1F('4 \1D\22\0E\0A\12\0E\1A\07l\B5\BE\B5\7F[cI$\0B$B]ZA3 $#&58#\19\19 1)6 \1F\1F\22\18\19&+ \0B\09\0D\14\19\17\11\10\12\1E\19!-$\1D\A6\C1eZ\AA\81\92\D5\A9X\91\C7\CF\A5\89q\C9\9B\8B\D1\BF\C9\ABg3\1D\11\09\1D+!$\18\0E\18\18\04l\B9\B4\BA\BC\B7\C3\C0l0KgUE1.7,*23)\1E\12\0E\1E006\22(&$\1F\1C47-\0F\0E\10\17\15\0F\0B\11\19\1F\1A,I\22'\91\84.\B5\CD\D1\BB\AA\8C84\8Ez\B0\C6S\9A\D7\C8\D1\B8\A4\C4\AE\807YL\1C&/.#\1B'\1F\10:t\89\A9\B8\B4\AF\A6xI[aT $>:()0- \14\0F\10\0C\1B\18$(\10\22\18\16!=A7\12\15\16\1D\13\12\0F\15\1C!\1D0K$&o\0F>\E2\CF\BB\CD\BC=\02\0D\1F\09i\8C1\18\BF\D1\C6\BA\B8\93uY:\8A\B3\87>43\17\14\22\1C\1A\0A*p\97\9D\8Bzq6OT`.\13 5:(('&\15\15\11\17\06ne\0E\12\07\0F\1B\07\1B@F?\16\1E &\16\08\0A\12\14\1A\1B+:,(\8B\8C\81\9Cq\B1\D7\AEoe$\0E\14\8BbjQ%a\DF\C8\D9\95\99\94\83F\92\B2\AC\83P\0D\11+\10\12\14\18b\82\A3\90UGQNXD\1D'8;1()'\14\0B?P\01Y\B3\BA`\00%\0F\15\14\1B@LI\1D\1F!+\22\0D\0C\13\10\10\0E\1C&<2\B3\C4\D9\847y\D5\B4\B1\B7\AEf\A1\B6\8C\93\C5\CE\A4\D6\D9\AF(\8D\AE\B7{Daw{~1\15'\11\17\1C\0E{\95\C2\C1_KIF?;207:*06 $\0CU\9Fn}\B1\BB\89\196:7\12\13;ML\22\1E 0/\22\12\0D\0D\0C\05\0C\1249\88\86\AF\D6\86\A1\BE\8D\B1\BD\8D\A4\CB\B3\B9\90I\8D\CE\94\B5\C0qE\95\B0\8DtS.epO\1F\19(\1E\1A\0Cb\A2\C3\[email protected]$,/\1B7\B1\C8\AF\A9\B2\9Cr~k=.2<NL.*0;:-\19\14\16\1A\13\13\0F8:)r\C4\C3\D0\C5\BA\B0\AE\CCy\88\D0\CD\C9V\0C\BE\B4\B1\94\B2\DD\91a\92\88\99\A9\8A\93\BF\A79/\A8|!\056\BD\B4\C5\BC\88D6?2NSJPZ:,<-,\12\80\C2\B0\C9\CB\C4\AF\8Ek=,=JVS>@GH??7941'$\18=9\13K\C2\A5\A8\BA\C4\BB\CB\CFVA\82\C0\D6\B8\90\AE\B4\D1\93Llt\9B\9A\BB\AC\B3\B4\BB\C7\CC96\A5\7F/ZC\BD\B3\AA\D6\C3\9Fg( @aB55CM./'\0A5z\97\CA\D5\D6\BC\A1\91j<:N]aefVUG927664+(\15\16q\0B.Bh\8C\A4\A7\B1\D2Gsi\BE\A3\B5\BB\B8\8E\B1k\CF\80qy\9C\99\8F\A1\9A\A5\B6\B67-t*4x^}\B4\BB\BA\C7\BF\BAN\00+`vR\13LLG7\1D\09\08;o\A8\BD\CD\BB\A6\8Ao2)7L^kte\5CH32/'+%\1D(\19\1BdD3.8Q\5C\98\B0\CAG\8E\CF\C4\C5\90\B5\B5ixO@\B3pfa@?3^\B4\A4\93%D\A9^da\8A\01D\B2\B5\AD\A6\B6\A33w\A5\BB\BBA'ORG\0F\0E\0A\0C@\90\B9\B0tF<)'\19\17+?VnndK1\1B \1B\12\15$%\1D ]>\22\1FG>f\AF\90j:\C9\AA\BF\BD\A7n\AA\AE\86yT\A1xU>@+\09N\BA\B9\AA\14d\B4\9F\B0\AC\BDdj\A9\AA\99\B4\BD\BB\BF\96g\8A\9B}1M=>H\17\12\15\1B'RP55GT:!\04\12#?exkF'\1C\1D\19\1C\18 !\22\1Fb; \11\22\1CEy\1A.L\ACk\13\8E\99\88\92\D6\A5\BB\CF\B3~?Q&-&a\AD\B8\9B\18d\CE\B0\C6\CE\E2\98k\81\99\92\BC\BB\AA\B3\B3|\9B\B3\9A]IAQB9\14:<$/8\191JZU,\08\0C\180SzxW%\1D\1C\17\17\14\1D\1F\17\14a3\09\0F\0E\10\17X %K0\12\11\18\C5\C8\AA\C4\BF\CA\CD\B6d8#\1Cq\5CG]VV\22N\BA\C2\B6\C1\B4\A5NVz@i\C3\A3\94\BC\94\96\96vx_IMKF?O_@R;\1F\14+F]T\1D\1D,>Npx],\22\22#\11\11\1C\14\17\1AU:\15\18\1D\11\0D\1F\0D\15Y\1F-\13\15\92\E1\D2\CE\B9B\A4\B7\BF\95<Bw4J7\8E\9E\14K\9A\A1\C9\93\8A\B6\8FzT\15t\AE\AE\A8\C6\80IN\A6\9FNI5$q|X\80\7FjB\09\17\14)JYA4>I?[ob6F=?<2\1D\16\19\1C%P\19\17\10\04\0B\16\0D\16V\1D\122\19\08w\A3\A0\B9\A1\9E\BD\B3\84wt'\81\AB\89\B4\AE\13u\C2\C0\C1\AE\9Fw\A5\B1\A8,y\A1\B9\C8\C2\A7RR\A2\A2J37\0Fc\9Cv\7F\B1\A3H\09\0D\0A\05%GMFm\8D{\85\89uIOESPRC/\1C\1A\0DM\17\12\0F\10\10\22!\15U\0E\00%,\00\B3\E1\BB\CE\D1\8D\95N9?H\81\9F\A4mas\1F$[\19]\D7ld\B4\B5xDR\A8\C3\C2\95\B9\B3\83H\83K7. =\90\96\81\C4\B6yWQ\06\05\14&8d\99\AC\CC\CC\C6\D4V A3;9;43,+\1E \142F1\13\1A(EdK2(\12d\C0hdiv\83\81*L#I|\92h\01\1CKb\C5\A6\B1\D4\C9\AF\AE\C0\8Ec!W\D8\BD\C1\D1\B9\BC~~\5CV:#\1Ct\AE\B5\BC\B4\A6\88V\10\01\00\06\17?g\88\AE\C0\9B\C6\AD#\10*3(&:+,\1A\1D\19\0E%K#;\13;=e7QO\1D0VmQB\BB\8F\B6\8E\0D\02'N\90i\1C\22T\1B]\FD\A9\F2]\D8\A1\9B\C2\E7\8B\07[\CD\CC\E2\B8\DF\EA\BEp\5C+%\14\84\C2\C6\CB\AE\8A:\07\00\1Afn[yx\84m\AB\A7\A5\D9\B0RMD3\16&,,\05\16\1D\1D\07c\1E\8Be5<d\87L@ $36Wo\93\F0\BA\AC\CD.\00.\15\0B>%-\1A\00.\C2\BA<\EFb\8C\C0y\13\B2\A4^\B7CW\C2\C2\C4\BES\22 8U\AB\B6\AF\CE\99=\01\06@\A1\C6\B3\AC\B3\AAp\A2\DD\BF\B9\B5\88ZV9\1D\1B,+5\14\0C\12!`8\9C\8B\84=/uqe$\1B\05?\A6{\15\A3\CF\E0\B4\81\D4\9F\C1\CD*\143\17\1B\110\F04\B1\B1\95@\01\8C\BA\B4\CC\D3\D5e\BB\C6\96:p\81V7?MJf\92\9Ac50\1CW\B3\B1\AF\B2\AFt\86\9D\B2\C1\B4\94}U\1C\14\12:;\1F+\0AG\B1\92-\99v\B8\8D3\1B8M-\1EH\91\9FZX\A8\8E\B7\D4V\AD\CC\C9\84\00!1\15\09\00}\BE=Q\B1_H\17\0F`\AD\D6\B4\E5\DA\BA\B9\DFH\92\A0\81V>NB]oqZIRJ\03B\96\BF\B5hxZtr}\ABz\84B\15\19\1B;<%!\0D\1A\C9\BF4\AA\89\BD\D9\D0\98\1Ao(\0A\94\A9\A2\99\86\CC\CB\AB\92=e\CA\8E\00\09,6\13\0C\00$\A7R\1C\D9{f\0C5\17\00/\00\C3\C2\BC\AC\B0\AE=e\9D\88m(,}\92\93\80MaqS6\AC\BE\A5\9F\BFUA?!-?<!\15\13\10?=\22390$\89\18zZ\E6\C2\D2\BEP*3\12\95\D3\9F'{\AC`?\09J*\94\E0w\0054\1E\00+\BDu^%\9F\9D\D6g\16\1E\0D:<,Cd\A8\A3\B36\8B\DB\C1qD\8C\8F\8D\A5y~W\92|_\A6\A7\82\9C\BDl*+)\11(\1E\1D\17\13\12=<\0D#^z2u\CD\AC\93l\DD\BA\B7\89&%\1Fj\D0\9C\12\AF\E5\8B\00irc\0C\92\8D\A24*\00>\B1\BA\88^ {\92\D2\C1l\A8\91\08\C1$=E=\A6\9C\CB\7F\C3\E4\92\A9\8DZ\88m_bZ\99\8FVRa`c\7F\84&.$\1E\18#\17\19\1B\0C\10\1E\0E\00\04\16r\99\9E\AD\BC\BC/p\F8m\CD.\22O\B5j,\B6\C9\8D\00\96\AC~\AA\A0\86zk7\CCm>\98\EB\5C&\86e\B7\D9\94\98\9Fs\BF\B0\9B\90_>4\BA\92\D8\B2\FB`I~\8A8a7gx~I0\2290\8D\8A9!\22#\17\16\1F\1C\14\17!\1E.\01\13\1D\1B|\A4\AC\CA\DA\B0d\18n\BD2,%c\1D\1Fb\A40G\C5\99\CA\A7\9C\C4\C08\80\D9\AF}\991j\0F\80\EF\B6\C3\AB\5C%nVv\94b7\22\1E\150\E8\D1jWk\AC\1EGVXH>1B.@PDLo-*#\22\1C\1A1+\16\1D \90)\00\15\02\00X\A0\A7\C0\A8W\00\A9\EB2#\16\0Cb\00\17=\00G5\F0\90\CE\B2\BC\E1\C8\A7\CE\DFv\0CKm$Q\E1\C2\90\B6I p\A7]2,\1E\113+]uqI\D2\A2cWWA\22\22\16\15#Hgc:8/-(\1A\1E\22>9 %\1E\1E\B7p\00\08\0B\1A\00w\CD\94\D2\00<\E1S:#\1E\06%=\07i\1F$\07Y\E5\AB\AC\C3\DB\D3\AF\B1\DB\90J/j%2\C2\BCdS\19@1\BB\AF\84\19+\19 0\1EJlZ\8B\D2\C5\83jO*V@#$&D]Wg6W))\15\18\1D=:&7\14\1E\91L\05\0A\02#\00\91\BF\D7;\05\96\B3\89.,\18\09\18F>\15\0BA\8DW\7F\AD\8B\A9l\D4\B5\96\C2\CA\9AR:P<Y\8DT\00hh\1AR\A1U\0C\10<LH\02R|a\A2\F1\B9t\91*1XD*\14\1BAUdO]:L\1E\16\15\1C=:%A \1Cc(\05\09\0B\17*\DC\C4\FF\00\1A\E2\A4\82n\1D\1F\00\1FF)%'f~\9C\D1\9E\D7\F9\E2\DE\C3\E8\E2\CA\A3]?T3\83\9D\00\8BKr;\0B|^\1CEna/,\91hc'\B5\BC\B9\B76\12'.C-\07g\A3\86mMK(\1A\16\18#>@%2 \1F\87h\0A\02\14\14\1A\00\1E\0E\15O\88le&8\16\19\1FA=\0E\16;w:RbJ)\9D\C8HR\DA\9D\A6yRq\11\9E\D1\92\7F>~8\07FbaIIb\04\A6ju*%\01\B6\CB\B2<\1E\19-7)\16@\B7\C5\B4aB'\22\15\16(8D,\1F\1F!U >\00\14\11#,\13\17\00\93\D0IU\0EF\09$%:N\17/\04\0B\14\03>A\12\92\C5\86o\C0\DF\BA\A0\7F}<\AB\D2\D4\CF\A8\AE\90\BF\00\94x#B\1DO\B6_G\19^rG\A6\BF\93`\18\14/\1F'(p\A8\D1\98M'\11\0C\1D3AJ,\0F\07\15QB\0C(\00\0DZ\18\13#\01\95/\5C[\07D\0A,\1C\1C_\00\A0j\0E\1D\0CE+\15\F5\BFz\C3\E5\D1\CF\9Ba\8A\FE\AFv\F7\D9\D9\B7^ksBf\8A\0D\10\9C\80/\16\0F,\A2\8A\9B\A5\A7\ACX\03#\1F\87\86\B4\9B\C0\BE\A55\09\11\1C5KNF7\1E&9q\07!\0A\1FE\17*\0D\1C\08\017\1B;=\1B)!\0D%(\84\8F\08\16\10,XTH\98\A8\AC\C1\93\C9\B2e\00\E0\E7\FA0\03\C1\E9<N!\9F\8F\D4\002\00\09\0BK'AC\C6\C8\918RO\142S'i3F\B9\D2\D0\BD9\0F\19);HPp\1F$@ra\00\18X\95\1C\0F.\10\096>\01\00n?\10\1B!8\17\11\00+.B>\0C\7F\A7\BD9\FB\E3z\02\00\07D6_P\F7\A5\D4@o>\DB2\7F+S8$\111B{oy\91\7F\AF\BBT`_\0F!8\82\82\CE\A8\BB\CE\B3\90-+\1B\18Knz#\1D^IK\86\0D\22PJ\0Byo-3\1D\22\BE\D5z\11\19\19\0Bns!,B\0A+\05Bs\859J\F4\82\00#\10\14Y*<\E6\DBN\C5\EB\8B\93.\0AzuoZ68CR:\10\8B\91\9E\D2g\12%0# %\09!#x\A1\AFyD.\0E\168gzG\5CWS\00\5C\7F\14,\0Fv|yP/S\95\8C\B6A\11\1A1Af\BAt\16\82\0D\00?(7\18e\0A\1C\82\02\15.\08/:z\FB\13j\D0\B4\D4e\067\5C>}AY'\22\1E\02!oVw\D5\00\A3]\11\19#\1B\1B%#?i\AA}2\18\02\10+RNbaX\12\1B\00o|\17\22\8F\D7\9C\B9\9F|n\5C\A1@\16\0F;BAN9#\16*\0CX\00\17!wS+\00\12 6\1627\03%\9D@\00\0B\92\16BcD\5CNF\A7\1A\18\07\0C,<\05W\904\C2\AAU\19\1C\1E\0F\19\16\155|~R6\0C\1C$8=gk\87\0D\19)\18\8E-\1C\13\F3\CA\BA\AA\EB`o\8CP,\08#\15d\14\0F\09\00\0B%\00\1F\01g\8Ed\00\0CV(h>\0C\14023\135\8E\13<TdC?]X\02)\16\16\1C*2(,#Vx\8Bw9\12\14\08\02\12\16\07&3C:<[&0Gjr\A8\F8F\14)\00\138m0\D1\BD\9Cy\FB\AC\CAu\82s>\11Q\10+\BF\A5C\02\120\B2\A0r\00\8F\CC\BB\A9+($.#N9\06\11V\B4\1Eg\1C\17sb>\14A:7HVRQPA\179\5C\9A@aN:(!+['\19\0A IH!18\0C\00N\8C\BE\00\5Cl\12\0D\8B\C4\C7\D7:J]\D7\AD`:U_\151R\00f\DB\BE\96\03\97\7F\9E\9D\00\CD\DD\AD\BCg+0$H[{k8\09]\02X\0EQ`I<\14>-6D)9\1F\18<Z\084S\81\C3\81]NX\83lh4\1D/YM34T\01\03ZF\82\01\8A\C1\CC\85\9F\AF\B8\DCMg\B6\B9\D1\83h,0-\1AJ\16\00\88\DF\BB\B4\A2D\E291\A9\98\D6\D6\B2\152,<5Qg=& \162\02C\AC\B7\B1\1B#\17\0F\0ErP(-\1C\0C\09V\AC\AF\B7\B7}W}X\82Z;\12AoN%\22<\01\05\0C\1E\08\11\17|\C4\DF\D4\92y\C6\E6\E6\A2\D4\83C#'\0E\1E\11&+\BA\C0\B3\DA\B8\D8\F9\1E\16\05+\AD\A5\9C\005\05:4Dg\1F)\0E\10P \0Ec\F8\C3Vh\BC\CAWR\B6\8CY\14\12\12/0l\E1\B0\C6\CEbauZG)\0E*c5\1D\1C)\07\00\1Ff\1A6\09\00\9C\C5\E3\C7\CB\C8\EB\C2\8A\CA\9F\0E/ \004$\0Cl\96\A4\B3\B3b\9D\CF\01\0E\00gv\98\9F\00\22\99`M\7F\12\04g\13\1AN@\A1\E54\00\00D\A9\82\E7H\D0\C5|\05.]/GT7\E5\CA\CCaq\96\9A\88\8A\84}4I\16K)\16\00YK8IL\88q\E2\B5\86\B0\D6\D6g\96\87\D5\00/\12\05\0F5\18\1C?\7F\C6\C5\AB\A1\DB\CC\1E\00u]n\9A4\95^g\8F\91\00\7F\92}C\B3\B4k\00\09Y\C3\00\D1\9A\8C\C3\97\EB\A9\02-1G\9A\94\B0\BD\DAkG\BC\C7\97K5PJ2D\15D8\04\0B !M\87\C5\C0\B4\93\CF[\93\8D\C3\B6ad\93\01,\14\0C\0D\08! \19\1ERs\96\D2\C0\DF\D6\00-\C6\B1\B9\DCW\5C\844\A9\BA\9A\A6:)X-\14\18W\FFR\A2\BE\E6\D4\C0\C1\F1S\13.>\81\B4\A8\B6\E4\EDe\07\AE\BF\AB\A4mC\0A;<\1B\1F6\0F\0CU\1F\89\5C\AD\CA\C0\BC\EB\1A[\DD\9F\D0\B5\18\0B\13\0C\12\04\0EA\19(\1AnL\86m\CB\C0\A0\ABC\00\F7\C7\D4\F1\A6\8D\8DJ\1C\D9\CE\BF\0B@0gd<<\E6{1\83z\AE\D7\00wh\00k\88W\5Ct\82Ob\F9\82\CF\D5\A0\00\00\13!:M)'?\11\12WHxYJ\DE\DD\AF\B6\D3\DF\AB\E1\C1\88\08\0C\0B\0F\00\0D\01R\19\22-\AFP\9B>\A3\A2\85\00\8D\AC\C0\C8G\92\F8\C3\8C\B5\F0\9D\D8\D3\02UqY\1A\A0\E0\A8\99aQ\C1*\C9\03\D1\BEZG\81Y??j\04\04\D2\B1\D6\9C\EC&\0B\07\19_`)1=@\816|g`_\B9\12\93\D0\B8\A0\B9\A8\D1\00\0F\16\07\15\1A\1B\15\04\1E\18\8D\A5\BCm-~y\8F\B4\BA\C1\E7\A4D\08\A4\C1q|\8D\AF\A8\E3~$4\00\A0\88\BB\CBj\AAR;8\CB\E8\AA\98b*,Ob\849\0BX\C6\C1\ADV\A5\F6?!\0CI8*)1z|miQT\16HA\94\C3\DC\B8\D3\87\CA4\00\0E ./,\19#\1D\19&D\089NY\87,\8B\A5\BE\AA\CAY\C7\C1\C8\88\80\9Bb$\C5\EA:\00%Hr\EF\A15\00\13\00?\A3\9A\B8\96Ybhf{J\07Y\06~\E88\11>\C6uiC%\1C+2\1C\83\8D/\1C#[F#\10\16\CE\BCAT\C8\8Em\1A%\15\06\1D\05\1E\0F\11\1F\0B\0B+>&\08\14^f\B2\A1\9C\92\EB\AD\9D\87ob\18'#&\D4s\000?\14\EE\00\05\0C\01\12\22\86\8F\CF>Ua}\9A@\004\09#:d\16\13\19f\D61. 74.1\8C\89;\17\08Wn\00\17\02\1A\A2%Y1\BEvO\03\0B\11\15\15\0B\15\04.\11\17-3.\1A6\00\0D\FE\E9\B8\D0\96\F0\A8\90S\08\04\EC\CC\06\B8\00\22;4\0F\00\19-\03\0B7\1Chv\B6\1BD^\9E\82\0Av;\1E)?\15\12+,\0B`\07,33-35m\93D\00\01\00[A\07\0AKoJ\18\C7\8F\8Dc\00\0A/\0C\16\19\10\10&\0A\05<Y\08\15D\127\EB\DB\FF\C3k\FF\D3\C0z\0B\A3\A6\B2\17L#!O\190\0E,\0D\0D\13\07\1A<GS\1B3\85{\00]h\13' \1F\00\02\15h\06\8C+# *!6\88\90\13\18\06\00\02/\04\13EXb\84\DB\C7atS\00\12\12\08\14\1B\0C\0E\0D\14C\04\0C/\09\19\10L\ACU\17\19b\C4\B8J\13\B1\8D\DA\F2[\BB\80Uk\D8\5C\00\10\0F\0B9U\125\92\17VU\03X: 3\1D\10\0A*\C8\9B\A8$a\15\16\1B\1D1*\1D\98\9D\1A\0B\0F\0A\0C\0C\0A\19PPM\1B_\A1sh\15\11\0C\0F(\0E\12\0D\04s\D4m\C0!\1E7.\1B\0FO \DE>\08\06\8F\A8\A0\AC\B2\B3UUA\CDx7\89\D1\0B\0E\00Mx\22'K1)4\12+[C\0E\0F\06\16\1Ak?\1C\00' \18\1D\14 \1F'-\98\9B\0F\0D\00\00\0E\0C\04\22>5]8I\06'xn\00\10\00\00\09\0D\00 \BC(\CF\F3\E2\00\06\0E\14`/\18\B3\F8+\06V\DC\96\B3\CF\A3\A2\8A\CC\D2J+\C6\A6\BE\D3\AE\074'\228\1E\1F\0B3?7;WSF,2\1B \22# &\1F!\1A;9-4CI\00\00\06\03\0B\08\02\05,#\AA3L:\8DR\0F\00\00\10!<\05\00<\AE\C5i\E2\F4\F2\00\00RA\1B\10-\A4\00\00\83qqH\D7\BF\CD\AE\C7\D0\89\00\CF\AF\EA\D2\F0:#\1A\22\19\14\0C8<\12\16\16\1A.B^OV\1E\10\12\1D\16PM9\1E8&-FL[\02\04\09\12\01\03\04\00\00}c\1A\02\00\00\07\06\06\1C`>\04\16\1F\1D\F9\F9\D1\A4\EC\EF\A4\CE\AE\07B\A8\00\07\8C\00\C1\EF2\DA\B9\97\CF\D8\AD\BDK\DC\CB\A8\E0\CD\80\00'\14\03*34,\17\0C\0A\0A\14)\0A!\22>D\19\12NVUEQ1%#S[", [5310 x i8] c"\BF\D5\C2\9B\8Fc\93\BC\AF\A1\C1\C2\A4\BF\BA\B1\C1\A5\B9\D3\BC\92/\12\1F&$5+!,\16\13\1A\11\18\08k\BB\D2\BE\87^aJ#\118TjbMC.( 8B@/)'$.*7!!%&\1E$',!\0D\0F\11\1A$$\1B\15\13\1C\15\1B&1'\A7\BFbW\AC\88\96\D4\AAV\8E\C4\D1\AC\8Dp\C8\97\88\CF\BE\C6\ADj2\19\0E\07\1C(#'!\18\1D\18\01j\C1\C7\C3\C6\BC\C3\BDj8^vZI=?F4-A8-*#\1D&36;$/2-&&:</\16\1A\19\1E\1F\18\12\13\17\1B\13%A'(\8D\81/\AF\CA\D9\C2\AB\8855\88w\B8\CDT\9A\D6\C7\D0\B6\A2\BE\AA\806XK\1A$)*.&/!\0D?\83\A0\B4\C3\BC\B1\A3}XrjZ'0NH.)93' \1F\1E\12\1B\1B*/\1A0&!*@G>\1C#$(\1C\15\12\16\1A\1F\19.H\22\22p\0C=\DE\CE\C5\D2\BC>\00\0C\1B\08s\911\17\BF\D4\C5\B9\B6\8DnX:\8D\B2\86<.,\22\1E' \1B\109\85\A2\A7\90~r<^ik; /EF)#23\22$!#\07id\10\17\10\19&\11%?HD\1F(+0 \0E\0F\17\18\1E\1F/@&!\96\8C\7F\96q\BB\DB\A7ze\22\08\14\95fcQ$e\DC\C2\D1\8F\95\94\82J\8F\AC\A4}L\19\18.\12\14\14\1Bj\8E\AA\93WIQQ`W,7IH5'':#\1BP]\05X\B1\BC`\00,\19\1D\1C\22BLH$))3)\13\14\1A\19\1B\19'1E9\C7\CA\DB\88:|\D3\AD\C5\BD\B0j\A4\B9\8A\8C\C4\C9\A5\D1\D8\A7#\8D\AD\B2|?`ov~=\1B(\13\19\1C\0E}\A1\C8\C2aMIFA?4>JG022$&\1Ah\ACt\7F\AD\BC\8D >@A\1C\18<QS*$*:4'\19\16\17\18\11\19\1F67\9D\90\B5\DC\8C\AB\C6\8B\C6\C7\93\AA\D1\BD\C1\8EJ\8C\CB\92\B7\BFsE\96\AF\8ArU-gp\5C%\1A*\1F\1A\0Db\AF\C9\D8|8A>DB3OKGQ8#.4&A\B5\C9\AF\A8\B2\A5\83\8CtH:9<W]<3;GA1\1E\1A\1F$\1D\1D\19438v\C6\CC\DD\D6\CB\BB\BD\D0{\91\DD\DE\DAa\0B\C0\B3\AD\90\B5\E5\92`\94\87\95\A5\8D\9B\C0\B5@2\A9v\1C\053\CB\BB\C8\BD\82?6<'MYU_a?61,2\1D\8F\C9\B5\D3\CC\CB\BE\A2{J8IK]bRPTTK@9=;81+\1F61\16O\C6\A7\A8\B6\C2\B7\CE\D3ZC\82\BC\D4\B4\90\AC\B1\D2\9EPv|\9B\98\B8\AD\BE\B8\C5\CF\D5A9\A3\80.`W\C6\BB\AD\D4\C4\9Em<2MiNECGJ@</\16E\88\9B\C7\D6\D7\BD\A3\97nBEO^bglZ[RF<<740%!\22 r\09+?j\93\A8\A6\B2\D0Dpk\C5\A7\B4\BA\B4\8B\AFj\CC\82tx\98\96\8D\A0\97\A7\B9\BFA2t'2\80q\86\BE\C0\BA\C4\BD\C2a\0F0d\82c\22TOV<!\15\19Jw\AB\C3\D2\BD\AD\96x93=Q`r\80ncR<91%'\1E\16 \1E\1C`A4(5Yc\99\AC\C7H\88\CC\CC\CC\91\B5\B4hwM>\ADlf`?>1\5C\AE\A0\9E0L\AB[ip\A1\0CO\BA\B7\AA\AB\C5\BA<}\AC\C7\CBO-O[M\16\1A\1A\1AF\90\BC\B6{PJ72\22\1A1F`||oT4\1E!\19\10\11\22\22\1B\1C^;!\1BFHk\AF\91g9\C5\A9\C9\C2\A7m\AA\B1\85xR\9BqT>C*\08L\B4\B2\B5\1Ei\B8\A0\B6\BB\D2ot\AE\AE\9A\BA\CC\D0\CA\A3t\99\AB\892HHKU&\22!\1C\22QR:>Q_D+\03\14(Ho\83uP-!\22\1D \1C$'\1C\18m;\1E\0B\22&Ir%.J\A6k\1D\92\92\88\91\DA\A2\B5\C7\ADz?P** Y\A7\B4\A7\1Fg\D0\B2\C6\D1\EA\A4r\84\9B\94\BC\BE\B2\C6\C2\8C\AC\C0\9E\5CGT`RJ!>;\2218\188Tb]3\0A\0C\177]\82\80^+%# \22\1F(* \1Bu9\0B\13\11\13\15Q4+M4\15\14\16\BE\C7\A5\C5\BA\C9\C5\B1d7\1E\1Dl[?XVb(O\BC\C4\B6\C1\B6\B1TW|Bi\C3\A5\98\BE\A2\A9\A3|z[MOYYLUa<S?&\1C1PgY\1E!3FTz\82b1)+-\1D\1D)!\19\18jD\1B\1E#\1B\15\1D\22\1F_%3\1D\1D\90\E2\D1\CB\B7D\A3\B9\BF\96;?u6I9\8E\AB\1AL\9C\A2\C9\94\8A\C3\95{V\16t\AF\AE\AA\CB\8BSR\A7\9FMK:/{\80Y\80~jK\1A%\1D4V`A=OWHf{i:KCHF<' \15\154T\1B \1D\15\1C!\1C\1AX&\1FC*\13v\A5\9F\B5\9D\A1\C5\B4\83ys#}\AE\91\B5\BC\1Ax\C3\BA\BC\AE\9C\85\AC\B4\A9&t\A1\B6\BD\C1\AD]a\A9\A7T(6\15n\AB}\84\BB\A4O\18!\1A\121SNM|\A1\8B\92\95\81JQIZW\5CJ6\15\12\16[\22%\1B\1B\182*#`!\0B04\09\B4\E2\BC\D0\DD\95\98T:@I\83\AB\ACpg\85!\22W\1Cd\D9cv\B6\B3tGY\AA\BA\BF\94\BA\B7\89P\82J4-!A\96\9E\80\C3\B6y]X\0E\06\13%8d\9F\B3\D4\CD\C5\D3_'I:BAD@<36.'\1B9P4\1D%8LkR<+\1Ck\C0gcj|\8D\891L\22H}\98r\09,Ob\C6\AB\B4\D4\C5\BF\B2\C0\8Fh$W\D4\BD\C8\D2\BA\BF\8A\80\5CVA$\1Dw\BA\B7\BC\B7\AA\8CZ\15\03\00\07\1ACk\8C\B3\C2\9B\C7\AE&\14.5.,@33'+!\14&P)I IEk8VU+8^pNE\C1\8E\B6\96\15\05$Q\96h\1C6_\19[\FE\A7\F4Y\EC\AC\99\C0\E8\89\09W\C8\CE\E5\B7\E2\F0\C6xW-(\13\87\C8\CE\D3\AF\90>\08\00\1Cfl\5C\7F|\85n\AD\A7\A3\D6\AFRNE5\18(34\14#$!\03`!\9AtBCh\83IC/)6:Xr\9F\F3\C2\B1\D02\001!\0EF<;\1F\010\C0\BE<\FFp\91\C1{\11\B6\A4^\B5CU\C8\C3\CD\C5S 6[\AC\BF\B6\CB\9E=\00\04D\A2\CB\B0\B1\B3\A9n\A6\DE\C4\C1\BC\8E]V6\1A\1757?\19\0C\0E\1F`8\A9\95\89=+sqe1%\0AD\AC|\1A\A3\CF\EA\B9\86\DA\A0\C6\CD*$9\1A \1B3\F38\C1\B7\98E\0B\8F\BD\B8\C9\D4\D4f\C2\C9\9FCm\82U8FPSo\97\A2c40\1EY\BF\B6\B7\B2\AEt\88\9F\BE\CF\C1\9F\86Y\1F\18\17;>&2\12H\B1\93/\A1}\BF\954\1B9O5,U\95\A3ZV\A7\91\C5\E1Z\B1\CC\C7\83\00$5 \16\07\80\C5JT\B5jU$\12g\BA\D6\B0\E8\E0\BF\BD\ECR\92\9C\84\5CCROgw{^JTQ\0BL\9E\C9\B9iza||\91\BD\89\8FJ\1D\22&?@& \16!\CA\C27\B0\8A\BC\E2\D7\99\1Dr.\1A\A4\B6\AB\9C\86\D1\CF\BB\A2Jn\CD\8E\03\0D$8\19\18\0C&\AEZ\14\DB\81r\1A7\1E\027\00\C8\C5\C2\B1\BC\B0Eb\A2\8Bs-8\7F\95\99\87Oex]A\AF\C4\AC\A1\C3\5CKJ/;KH-!#\22AC$3A8,\8E\16}\5C\E6\CA\DA\C6U(6#\A1\E3\A1\22y\AFfP\15Z,\8F\DEz\02+4$\09?\BEwa\1B\9F\A3\E9{\17 \108@/?e\B1\A8\B74\8F\DE\BDrM\91\93\95\A9\81\84V\8A}k\AE\AB\8A\A2\BCd+72\1C4*)$\22\22CB\161i\8D>\80\D5\BC\9Cz\E8\CD\C3\94.5 k\D1\9E\1E\B7\E8\91\00jse\18\9A\90\A8F,\00:\B4\C1\8AU2}\90\CE\C4s\AA\88\05\C0%AKE\A5\9B\C8~\C4\E8\98\B1\8CY\88meib\9A\8EURafj\87\85%--% *\1E!$\18\19%\19\10\0B\1Dy\A3\A1\B7\C7\CC6w\FFw\D08)O\B4i-\BC\D3\95\04\96\AB}\AB\A6\90\82{;\CCnC\9B\EBX6\8Ae\B8\DE\97\98\9Bs\C6\B1\9C\93k@4\BA\99\D9\B3\FElK~\8D<e;lz~J3&=4\92\8C9\22#&\1B\1A!\22\1A\1D)%;\0F\1B#\1C\81\AA\BA\D7\E8\B8j\19s\C3@4-f\1A\22h\A30O\CD\9C\C7\AA\A2\C3\C0L\8B\D7\AD~\973f#\8B\ED\B4\C4\A9^!iXy\93e=*&\102\EB\D0m]s\B4\1FMZYI@1@/FTEMq-( !\1C\1B2-\18\1F'(\9F6\00\19\00\00[\AF\B6\CD\AF[\00\A6\EEA(\19\10c\02#@\04L8\F4\91\D1\BE\BF\E9\DF\B5\D3\E0x\0AOm;_\E6\C3\92\B4M n\A7[8-'\183)]swJ\DB\A9`\5CW@ &\17\1A Mgb8<020!$%>6\1D!'*\C1u\00\04\09\1A\00\84\D7\99\D2\00:\E1SG-#\0B+>\0Ci\1F.\0C^\EB\AC\B1\C3\DB\E3\B5\B4\E0\9AM2n58\C5\C1nV\1CD.\BC\AE\85 .\22)-\1FIma\8E\DB\CE\88rO)VB%0+L]Vg8Y57\22#&A=*<\15!\98S\0D\0B\02$\00\99\C6\DEC\06\96\B4\8B6:%\0D\1CF<\14\0EO\9A[\83\AD\89\A8o\D7\B9\A1\CF\D7\9DYGS@d\9Aa\01ou\1AN\A4[\11\14IVH\00U\82f\A6\FE\C3|\9B.2ZK2\1E#KYeQdBV2($'EB.L$ d'\0E\10\0C\1A-\E2\C5\FE\09!\E3\A7\85t-/\0D(I)*+v\8E\A9\DA\A1\D7\FE\E6\D6\C5\EE\EE\D8\A5dGL5\89\A9\0A\8DRzC\08\81a\22Jzc7)\96ki,\C1\BE\BC\BD=\14+5M8\0Am\AA\88qTU3($$/JL5D\22%\89h\12\0A\1C\19\18\00 \0E\1DW\90qc)I\22)!<;\11\1CL\83JT]H,\A3\BEHX\ED\B1\A7{Ug\11\A4\E4\A6\80@\816\0BI^bRNf\02\AAmq+.\06\BA\D3\B6D$\18%85\1ED\BF\CB\B3YC3+ \224DQ;/%'a+G\0E\1D\13#-\1F\22\09\A1\D9KU\0F[\1A2(;S\1A0\19\1C\22\06?F\15\93\C9\86m\C2\E3\BD\A0|\81<\A9\D4\D8\D2\A8\AB\8C\BD\00\99\81*?\17K\B4^L\22eoA\A2\B7\94j \15.&# q\B2\D9\99L.!#*6FP4\16\17,VN\1A9\08\1Ae\1E\18/\0F\A6<if\0DW\1F:\22!g\03\A3}#+\12J3\1B\F8\BE}\C5\EE\D9\D2\A0c\89\FF\B1\7F\FF\DC\DE\B9^kqGu\95\13\0B\9C\80-\1B\1E7\A8\85\9C\A6\AB\B3X\00\19\11\88\87\B8\A2\C0\B8\9B'\15!&9II>-+)?~\15.\12-T\1F0\1A*\15\09E*CJ-8+\16+/\87\9C\1A%\1A5^[K\9B\AA\B2\CB\9E\D2\B7f\03\E2\ED\FF;\0C\C6\EA7O&\A7\A0\E3\070\00\0A\10S8PM\C4\C9\96>ZQ\0E'>(n9N\BB\CC\C5\A89\0F\1F5DOZv$*G\7Ft\0D\1E\5C\9B\1C\16;#\18<B\07\00}O!(*? \19\0B;?OG\13\88\AF\BC>\FF\ED\85\0A\05\0DC;cZ\FF\AD\DCFqA\E0C\92<]<&\146S\8E\80\83\95\8B\B8\BEVbZ\08\15D\8B\85\D0\AA\B6\C7\A7\8B$--'X\82\8B+$iUY\91\14 PF\16\85}8:\1B\22\BA\DC\84\22) \0Eqs(6S\1A2\08Es\84:J\FA\8C\0A2\1A\13Z*B\F0\E7]\CF\EF\90\9B>\19\8B\84\7F^;@SaK\1F\9B\9F\A8\DBo\17(/$./\12)({\A0\B0{7.\1F\17,`nSle_\07]\80\11*\07\84\88\82Q0P\93\84\BCO!.<Bk\B6z$\92!\0A@-3\1Bf\0A\1F\8B\10\228\0B0:}\FF!w\DA\BC\DCj\0CAdIzIa,((\0A,l\5C\81\E0\00\A4`\13\1F)%&($Bk\B0\82 \17\1A\14#UJlea $\03ox\12 \98\E5\A5\BC\9FxiZ\AAP!\1DC?AKB3!8\14U\00\14#}U0\01\16(9\1889\08*\A1H\00\0F\95\18FgC\5CEJ\AA\1C\1C\0B\0B,3\0Ad\9D:\C6\AEW\1A!+\1C\1F\1A\197}}40('%LOef\97\1E\1C-\1C\95/##\FF\CD\BE\AE\F2bv\94`;\161\17_\0E\17\19\08\193\00\1A\00i\92f\00\0EX*f@\10\16145\153\8F\13=XdB=ZY\02*\1A\16\1B(/1<,Xy\8Dw4\1B$\11\04\13\18\07!B-5TV\131Fbh\B4\FFO\222\00\139y;\DA\CB\A5{\FB\AD\DF\86\90v?\16T\11@\D0\B3F\03\173\B3\A4r\00\91\D0\BE\A9(,$,%R<\06\0ER\B2\1Dl%\1Ep\5C:\12@?@OSLMHB!A]\99G]F;2),Z.)!-LM'9?\1C\0DS\98\CC\0Aiy\1D\13\90\D0\D5\E8GWh\DD\C0uH[d\1D7U\0D{\E9\C4\9B\0B\9D\82\9D\A0\00\D6\E5\B0\C1i*3&Qc~p:\09]\00]\1D\5CfD<\14<2EO/4 \19@a\08.Is\C4\82aUX}bZ@-9]K.,J\0E\06`S\90\0E\92\CF\DB\8D\A5\BC\C6\E9Uu\C5\C1\DE\95w693!M#\0A\97\E9\C4\BA\A9G\E5;7\B3\A3\DF\DB\B3\1842F@Zl>!!\1B:\13R\B6\B5\AC\1C(\1F \1D|N)2\22\14\0BP\A1\9A\B8\BC\83_\7FRwE;\12G{W,,B\06\0B\13+\1B \1D\80\CA\DF\DB\9F\8C\D5\EC\EA\A8\D4\92S44\17%\1A.:\CA\D1\C0\E3\BF\E1\FF\1D\1B\095\B8\AD\A4\034\0A>>Oo'/\10\13U1!t\FF\C7Xk\C1\DBjc\C0\90e\1D\15\141+e\D5\BC\CF\D1dcpS;$\05,uD*0:\0F\06*r(A\10\00\9C\C1\EE\D3\D9\D3\F2\C0\8A\C6\A6\18@0\077'\0Cs\A0\B5\C3\BAe\A0\CF\00\0F\00m\80\A4\AE\07!\9A`S\89\1E\13q\17\1FVP\B0\F6C\0C\00I\B1\92\F6Y\DF\D5\8A\0F7e4JS8\F3\D4\D5iv\99\99\89\8Cw}EJ\0AD\1D\22\0DgWAJM\85o\DA\C3\92\B9\D7\D7d\94\7F\DB\0D?&\10\10:\14\22M\8F\DA\D0\AC\A6\D7\CF\1F\00xf|\A7>\98_g\92\9A\0A\8C\9C\85K\B8\BAu\05\14V\CB\08\D6\A0\96\CB\A2\E8\AF\0C84H\9D\96\B6\C3\E4vJ\BD\CA\99Q:>IJH\0DG4\0E\0F)/V\8A\C5\BC\AF\91\D8i\9C\90\C3\B2\5Cb\9C\117\22\14\0A\08\1E)))`{\93\D2\BD\E1\DC\002\CB\B5\C1\DFYb\869\AE\BE\A2\A9>,Z1\18\17W\F6V\A5\C0\EA\D8\BF\C1\E8X ;D\85\B8\AA\B7\E9\FAr\0D\B2\C3\AD\A5l%\04WG\1C3H\0D\07e0\8C`\B1\D1\C2\C3\FB+^\E1\A3\D7\B7\1F\13#\1B \12\10<\130*}Z\94o\C6\BA\A2\AFE\00\F9\C9\D6\EF\A8\91\8FK\1E\DB\D0\BD\0C@1kd;:\E3|1\84~\AE\D6\00tq\0Et\8AX^t}Xr\FF\84\D0\D7\A0\00\09\00\1CRH\16(>\09\08j[\84_G\DD\DA\BB\C9\E6\EB\B1\DE\C0\85\14\15\18\1F\0C\17\00[!+:\BF^\A5:\AC\AA\89\00\84\AB\BE\C7F\8E\FC\C2\83\B4\EE\9C\D7\CF\03WpT\12\9F\DB\A2\9AcP\BC\22\C8\00\CB\C8jR\8Da??h\0E\14\DD\BD\DE\9C\EC$\00\02\19[U\17\1D+0|E\8DucZ\BA\13\98\DF\C9\AE\BC\A3\D2\00\14 \12!'%\16\0C%\22\98\B1\C9w.\86\80\97\B5\B5\C2\E8\A8H\06\AC\C2l}\8E\B3\AC\E1\82)9\03\9F\8C\BB\C9n\AFW>7\CF\E8\A8\A0n27Zj\8CA\13d\CE\CC\B8^\AD\FE:'\19Q8#!,zxtt`]\16OG\97\CA\E7\C7\DC\87\D1:\00\14+982\1C)&\1F1O\11?Q_\90:\8E\A4\C0\AF\D3_\C8\CF\CB\87\82\A0k*\C6\F3E\06/P}\F3\A2>\05\1F\04G\AE\9E\B9\A1emtt\89X\15d\12\89\F4F\1FL\D4yyY6&,1\1Ex{8%-aC\22\14\19\D7\C5KZ\C5\8Dq\1D+\1E\10$\09!\10\1A%\14\152B)\09\1Dlm\B6\A6\9F\96\EC\AA\AB\8Esg\1B+$#\D4x\089J$\FA\08\05\11\0B\1B-\96\9B\D9Pcm\8A\ABT\07B\1B1Fq'''t\DDCF7I@8<xw?\1D\11_o\00\1A\0F\1E\A8.a2\BCy\5C\0B\14\1A\18\15\0D\13\076\1A 030\189\03\12\FF\EC\B6\CB\92\E9\AB\95V\0B\02\E7\C8\00\B4\00)?;\1B\07\22)\03\12;#t\80\BF-Pi\AC\92 \87K05J#\22A=\1B_\12>DA5:>h\99B\04\09\04]:\05\0EItR \C9\88\8Bg\05\139\0D\13\16\0B\10/\13\0F=V\05\10D\0D:\F1\DE\FD\B7h\FA\CE\C3\80\0E\A0\9A\AF\0FG\22%Q\1D7\164\08\0C\17\09\1ECO[-?\92\88\08sz!9,-,\0C\18'v\05\96=4*,\227\95\98\10\1C\0D\03\04*\06\1AB\5Ci\89\DD\C2c{Z\05\1F\15\03\0A\18\0C\15\16!F\00\02,\09\11\11U\B3R\0C\14]\BC\B9S\1A\AE\82\D5\EDV\BA\84Vo\E1f\07\0B\0E\0F:Y\1B?\9B+cb\11jN0>1\1D\178\DA\AF\B8/^ ),*7.\22\98\96\19\0D\15\10\0F\06\0A\1BORS!b\9Bsj \1C\1A\11$\04\11\0B\0F~\E2o\BC\17\1D5(\1D\1DX\1E\D68\01\00\91\B6\A9\AA\AA\ADNP@\D4{=\93\DD\15\09\00T{(1W;>A\1F:mW \1B\1B#'zQ0\0F3\22'4).',3\90\96\22 \0A\03\0B\0B\01.QHi>F\05$\84w\07 \09\09\05\16\06)\C98\DD\FD\DE\03\0E\12\13W.\16\B2\F7'\0AU\D3\95\B1\CE\A2\9E\8B\CE\D1E#\C5\A1\B8\D4\B0\06/\1F!3\18)\1B>K?;WQP<='(\22#\1E\16\1A!\160'\19\223D\0A\0A\14\06\06\09\03\0A;4\B86G;\8EW\19\09\0C\1D+=\0D\01F\B9\D1v\EC\F5\FA\01\02S<\1C\111\A8\00\06\84lrI\DB\C3\CB\B2\CC\D5\8C\00\D3\AF\E8\D6\F5?&\19&\19\12\14DD\1D!\1E\226JjWa)\18\1A%\11VZA\1E1\1E(FHb\0D\13\12\12\08\09\07\03\08\8Cl\1A\09\03\00\0D\11\11%fA\0A\1F%(\FF\FF\D7\A7\F2\F8\B2\D1\AD\09G\B1\00\08\9A\03\C0\F17\E3\BF\98\D8\E3\B9\C7S\E7\CF\A9\E9\D8\8C\06/\1F\07+>@7#\1A\18\18\224\16,.LR' RfkV[2$%HI", [5310 x i8] c"\EC\DE\B4\96\A9\95\BB\D4\DC\AA\B3\BD\BE\F1\E2\C9\C1\BD\D8\E7\9E\93\0C\00\1F>CI\0D\22\09\00\00\03\180\1C\93\D3\9F\A9pey^K)\05 ?=%\1F\13\19\19\04\17\1B\07\05\0C\15'.2\1B\0A\00\15\14\00+'\1B\00\00\00\10\00\09\03\00\01\0D\09\0F\1C\16\0F\B9\CCkh\B9\8E\AF\FE\BCc\97\D5\DE\B2\A6\9A\DA\BC\B3\F4\DD\F5\BCaD>9,;W2\1E\0C\00\170.\99\CB\99\AE\AC\B6\DB\EA\99B0=B1\0F\153'\1C\08 \15\00\00\0A\19\22*4\1F\0E\00\02\14\0E.5*\00\00\00\0C\07\05\02\05\0B\12\0D\1F>\11\16\A8z\0F\C9\F7\DB\D4\D7\A3.\15\A2\A4\BA\DF\80\B6\F8\E7\F0\DE\C7\EC\CD\9CXxkBIWM \15 .8UbX\A6\B2\AD\BE\CE\937*=4\06\0C*;<A\0C\0D\06\00\00\11 3.&\1D\00\00\00\00\0FSC,\00\00\00\00\01\00\00\06\0D\12\0E\22?\13\16r\1F9\F9\ED\BD\E7\E0@\12\086'k\A6U6\D9\D9\E4\DB\CD\BB\A4wT\92\D1\A8S\5Cb\1C\1D*,7\1C\1CL\9C\A6\93\8A\8EHA0C\05\00\08\142EK\0A\00\00\00\00\0F#\91\8E'\13\00\00\00\00\00i_@\00\00\00\00\00\00\00\00\00\05\06\16&\1A\17\92\AE\94\C2\89\98\DC\D3v\8774,rg\8FwLh\FF\F2\FF\BF\B6\BA\AAM\BE\DC\DF\ADm\15(M+*6<u\8A\BA\B2p_srk\1F\0D\1D\1D\1A$,*\02\04\01$/\00]\B4\C9|\0C\0B\00\00\00\00OhV\03\00\00\00\00\00\00\00\00\00\00\09\132)\A2\E2\E7\89C\81\EB\CC\A0\D5\BCk\AD\BE\A2\AB\E3\FF\BB\F9\EA\E0K\A9\CC\E8\92gr\A8\9E\9A95T,%>@\A4\9D\E2\EEzYkxhdmI\1D\1B\0C\1AAI_%;\80Pg\BC\C1\7F\00\17\1A\05\00\00AC1\03\00\00\00\00\07\00\00\00\00\00\00\04(+e\88\AB\CE\8A\A2\C8\B3\8E\BF\89\9C\CF\B4\C3\B6`\AB\E6\AA\B2\CD\80k\AC\CE\A5\8AP;t\96U=9912)\86\A8\E1\F7\8BJYZhNPeURUBM:Q<K\C0\CD\B9\D2\CC\8A;[a\1E\00\0FV<\15\0B \11\07\17\10\00\00\04\0A\03\03\00+-\0Fw\C5\AF\C2\B6\A9\BF\94\D1zt\C2\BE\B8e*\BB\C3\D0\B1\BA\DA\B0\7F\8F\97\B8\C6\92\90\DE\A4RA\BB\A6D\1Fj\BA\CD\D7\CF\B2gPsOm{W4QU@YLT\1Fd\B9\CB\DD\E8\D3\97eW/\12#ge;\15,9.%\16\12\1A\19\17\0F\09\000.CX\B8\A2\C2\E8\EA\CF\FB\DCL>\9C\EE\FC\CC\90\C4\D0\E6\80QSc\9B\B0\D7\C1\A0\B9\A2\B6\C0*@\BB\94Vx$\B1\A4\B4\EC\D8\C6\85\09\00\22D&!(8C\0C\11\0A\00!m\8C\C0\DA\D2\B7\8Cq]8\1DSY\5CPFIQ*+$&%%$\19\17\07\08\84\164Pw\99\C1\D0\C4\DDM\81x\CB\C0\DE\CC\D9\B6\D4\89\FB\91k\8A\BD\C1\B2\BF\C6\B6\B0\AA',\8CTa\8ACq\A4\BA\D2\F1\EC\CC3\00\18LT9\0FG>\1D$\09\00\007j\9A\B7\CB\B8\8CXM'\1B1J[QBCQ:))#\19\1E\18\10\1D\08\0A{:\14Bb[u\C5\C7\C0(\A2\F9\CE\DE\BD\D1\D6\88\97uc\DB\8F\82\82_^Y\81\DC\C3\90\1F=\B8\86\7FOY\00>\AB\C4\D5\C1\A4r\0FW\8B\A3\A7B;g.'\00\00\00\0DT\A8\CF\B2i-\0F\00\0A\07--4=AAG9\1F\0B\11\0C\03\06\16\19\0C\10`N\1D6e@\80\D3\93z5\E0\C8\C1\D7\CB\8C\C4\B6\A4\9Ai\C9\A7sXHI*c\E2\E8\AF\1Dl\C4\BC\C2\9E\99is\B1\BA\B6\C6\AF\97\A2mHrzuNp \15)\00\00\0D8J{i6\1F\1D%\0F\00-+$);I@\1B\0B\01\04\02\07\03\0B\0D\10\0Ei]37:\03J\9E!P_\D2\83\00\93\BE\AE\B9\DD\D1\E5\FF\DD\9Bex-YP\94\D7\D5\A3/\86\E9\C8\E8\F2\F5\A0\82\A3\B4\AA\DE\DF\BD\8E\A3r\80\92\8DaJ\1CA8\1E\00-@%>T&\17\18'!\00\17(%\16!GD\1B\05\00\01\01\04\01\0A\0C\0D\0BPQ\17\14\1A\18-p\0FCY5\1E\19.\DD\E6\DB\DB\E2\DB\FE\D9\80VT3\94mx\80r^B{\D5\D0\D8\F3\DD\ADn\83\95N\8B\F5\CC\BD\F7\AD|wXbjr\88d, 1IKX1\04\00\0B\14 !#\13\11\1F.>;*\11\0A\0E\13\05\05\0E\06\0B\0C2<\11\10!\12\17E\00\17U\171\14\1F\B8\F8\F0\E6\CF?\B1\C6\E5\ACZZ\8D1WF\B4\A42k\AB\B4\E1\B0\AE\BC\AD\9Ae(\8C\CB\D2\B6\E8\A1]]\AB\A9wWWE\85\8B]\8A\A8\840\00\00\0A\0A\166[\22\07&5<;?\19+'-,\22\0D\05\0C\0F\0BU\1A\03\02\00\00%\00\1BW\09\04#\08\17\95\A0\AF\D8\BE\A6\BA\D2\A2t\83F\9E\B3\86\D3\AB,\87\D5\EA\E4\C8\D3t\BE\C3\BBV\9C\BB\ED\E5\E1\CF_6\99\BD^PV7p\80m\9A\C5\C0W\00\00\00\00\0B-jUUdgwo[ *&86:(\14\0F\0F\007(\08\0D\0D#\15\0B\00f\04\00\22?\00\C8\F8\D0\E7\B7\88\ABTNV]\9A\85\9F\83g_77\89G\81\FF\A2P\CC\C8\A6rv\D1\F9\EA\BE\D6\C3\877\92\5C_W=M\94\85\90\D5\D8\9D]P\00\18\18!Z\88\9F\AB\C5\DF\CA\CFD\06\22\11\19\18\17\0E!\12%\09D5AH_)\14\13i\85Z4V([\DA\89\8D\88|s~!fDr\9B\98X\00\0FXb\C0\AE\D7\EC\DE\A2\BB\C0\89kGo\ED\D9\C1\EE\D9\D0d\8Cvr:@<\88\94\C3\D6\BE\B6\97e\18\12\09\01!Ov\97\B6\D1\A5\C1\B2\1D\00\0B\0D\02\00\10\0C\0A\13\12. 8J7<\0C0RwJPc\1E+O\7F{X\BD\BA\DC\89\06\14Qd\92\94B\10Q$`\F9\BE\F3r\C6\9E\A4\C5\E3\A0\08p\F0\DD\F6\DF\F5\FC\B9m\7F<9;\9A\D4\C1\C8\C5\82?\1C\13(~\81rq}\99\82\B9\BF\B8\F5\BDH/\1D\06\00\00\0A\0B\00\1C4,&}D\97S;Ss\A6ff,-IFn{w\FF\C5\B5\E3>\14:\00!I\10 \1B\00\22\CB\B0D\DAU\8D\BCm\1C\A8\ACj\CC[\86\C6\EF\CC\CB_78gY\D8\BE\BC\F8\97G\12\19G\B6\C5\DD\AA\BD\BB\83\A9\F2\BE\B6\AAt><#\0B\0B\08\056.>@7l^\A0\8C\9Eo]\8B}\8B(\1C\1FJ\9E\90\1E\C7\FF\E1\CE\8C\CC\B4\CA\F1\5C\1A]E&\008\FFQ\B7\DB\C3K\00\94\D0\D1\DA\D6\E2|\BA\DC\9EJ~\84cN>cRv\91\8Bo:2\1Be\9B\B0\A0\BE\B4v\85\AB\9A\B4\A5\81kA\0A\00\00?5\04+\15f\C9\97E\A3[\B8\98R3=e7\11:\A0\A6r\88\D3\B4\AA\C6e\B4\E4\F9\AF E[4\0F\00\91\CF8u\DB~N\08#q\A8\D6\C9\D5\C6\AB\C0\C1G\92\B5qB/U$\5ChVMB<(\001\8F\A4\A8ab8ca^\8D^o1\06\07\06&\1D\04%\05+\E9\CB@\AEh\C1\D1\E1\B8&{,\00\80\88\8C\A1\A8\E6\E8\96~\1CO\D2\B0\18&9G;$\00<\B6d)\EA\A3~\03M&\0C\08\12\AA\B2\9E\9B\8E\C6\16w\84xO\17\0A\95\B8\95f7@L+\17\D2\C0\8B\89\9E0\19 \0E\18% \07\00\00\00\19\17\00)6B.\92;\84\1B\DC\BF\E4\C8YM=\00\97\A5\AEX\A1\D0t,\0B\1C9\C5\FF\9B\10\1F(>\00\00\DD\90\84\0F\93\BD\C9<693C(\14PUx\90\BA?w\C3\CEb\14y\96\A2\B2XXD\B1\7F9\BB\B4av\AA\8B-\05\13\00\04\00\00\00\00\00\15\12\00\0Dop0r\E0\9F}V\EE\B0\B5\869\184\81\E5\B5\00\AA\FB\91\12\80\87|\00\8D\A3\A8 B\12l\DF\DE\B1\94\0C\93\A5\FF\EF\90\D1\C70\EAAMI,\B5\AD\F3\A8\E0\F4\96\98\9Ck\AA\91eaS\AC\93Qt\85fbx\97*)\12\04\00\01\00\00\00\00\00\04\08\00(7\81\9B\CC\C3\B6\A7S\91\FFo\FBD\19i\D6\93K\BC\B9\8A\00\B0\CD\A7\C9\A6vw^D\CChF\BE\FFq\19\93e\B2\E1\BA\B0\B4\8F\BF\CD\BB\A4ELN\D6\92\F5\D2\FFFW\98\94HpFo\89\88D:2H?\95\9BC\1C'\1D\02\00\00\00\00\00\02\00'\00(/.{\B8\AD\C3\CF\C5v+m\D13'\1EuG5d\CFVB\BE\AB\F4\BD\9E\EF\E6&}\E2\B2y\AE2\7F\00}\F8\B9\BF\C0]:\91g\8A\BBxI\1D\1B8A\FC\F8\80if\A95?[m]LIUE8UYa}E=?/\12\00\0A\00\00\00\00\00~/\10$!\19~\AC\95\C6\BFf\1E\C3\FF>,,\1Cy\0B\00S\07PK\FF\A7\DA\96\D2\EC\B3\9A\CF\DBj\15Au\0FD\E2\BE\84\BF?(,\85\BF\8C6Y&\1E?@u\A4uv\DA\AF\8DUaR5)+\14MFqtM?D,%\0F\0A\06$#\0E\15\00\00\B8\8A06!&\22{\CE\AE\FF+R\EDy>$8\11\1DR\10\8DQ%!d\DD\C0\B5\E7\FF\D9\D9\DF\E6wRE\87+\5C\F0\C7K[/]?\BE\BC\9B\18A!0>!W\83Y\A1\DA\D5\82[[/X?1\0C%5i\5Ci5e\11\1C\06\05\0B)(\11\1E\19\18vL\10)\1A(\14\9B\A4\D7F$\AE\B8\A18\1F\0A\18\1F^n@14\7Ff\86\C5\BB\D4\92\F8\DF\B5\C8\BB\AEc5tfx\93E\12yc\1Ag\91A\00\17\1EKH\17BhR\A9\D3\B8mv\1D*B\22\19\03\14&H]9;);\00\00\00\07,+\13,\0B\00B,\00\1A+#6\E0\A3\FF\00+\FF\B0\8Er\08\0B\00\09NK?DQj{\BB\A6\F9\FF\FF\EB\D4\FF\FA\C1\BBlQaD\AB\B5\00\A3Z\84\14\1DcN\004Ly\08>xXE\16\93\D4\DF\B9\1C\00\06\09\1B\0E-i\89pL(#\09\07\01\00\07$$\06\10\00\00H^\07\14\1E\1D=\07\00\04\12a\92u\880%\18\00.rc2*(y\0Ca\93pM\B1\B2<r\CDr\C6\94x[\05\BE\C4g\9FY\A4A\00.oR\196i\0D\92R\82\1B\00\00\BD\E0\BF\1B\00\06L:\03+M\96\9F\A1\80E\01\0C\00\00\02\16&\12\08\00\001\096\00\0A\22%\1D\00\00\00~\C6ZW\002\00\0F-?=#O\00\00\00\0BC0\1E\B2\B1\90\92\D9\EE\D0\B8\9BiF\CE\EB\E3\E5\C0\CA\A5\C0\04\85b\096\01d\B7c8\03Df+\A3\E6\99G\13)<\04$Ov\8F\CC\ADZ\0C\04\00\00\0B\1E*\05\00\00\00P(\00\0F\00\00C\12\12\09\00|*MD\01:\00\17\14\0DR\00\B4`\00\08\046\1E\11\FF\C4v\D2\DD\CC\E5\99b\8F\FA\BEn\F2\EF\D7\B8fk\86C>w\00\05\A4\80B\17\00\19\86\7F\A0\AB\9C\94Z\1942\8C\8C\A9\83\C2\D4\B6H\07\00\00\00\0C\0F\00\00\00\005P\00\1D&\1E5,&\00\06\04\1D6\0BPP\07\17\11\01!(\96\A2\00\04\00 TTZ\92\A9\A8\B1\80\BD\B3h\00\E1\E3\EA\1D\00\C2\ECoS \9As\C4\00;2\0E\0AF\0B1(\CF\E5\9A43,\00\11QDr/'\96\B4\AF\BB;\00\00\07\17&&R\00\04Oc<\00,y\994\1E\1F\00\00J_\05\15v3\00\0C%7\0F\0A\04\1F\123B\0Bw\A0\CC:\FE\D2g\00\00\01S7b?\E4\A0\C3:~F\D9\0Fb\1A\5C;3\19/\1F^^\82\94s\B5\D1UMD\00\05,\88\98\CF\95\A0\AA\97x\00\06\05\06:O_\00\03oU>\83\04-8G\1C\85b**(\0A\BB\F8\8D\02\05*!v\8BD?3\00<\1BJ\8B\A4Ld\F6q\00\00\003lD>\D5\C3$\AA\F8\8A\84\0D\02xe>g5)\22J8\00Zn\8E\C6Z\00\15-\14\00\15\00\14\10h\9E\A0T\00\00\00\090XrE?f]\0C|\82\1A\13\04\85\86\87p2Y|\81\D4B\07\004ag\D9\92\17x\00\02_)V z&0v\00\00 \10DV\8E\EF\00K\C2\A3\B5V\0CBq;\A50:\18()\17\1E\97Ri\C2\0E\C2q*\1D\1F\0D\087BS\82\AEl\00\00\00\00\18DK8(p\05!\14\89\9D0.\A7\CA\A2\CD\B9\9D\87h\A9+\1D\10NtM^A\0E\1D+\1F\8A\0B'0ob4\05\22\1BH%*F\0C.\AD;\0F\0E\8A\0B8r}x~I\9F\0F\0E\16EHl\108o8\D2\B7n9'\00\00\1D&\22N\9C\A9>\1A\00\00\05\19%(,j\00?H5\9DV5\00\CD\F0\D9\C7\FA\89\88\973\1E\00\180\88*\1A\00\00\00\1A\17C\17\7F\9Bs\14%nA\95V\19#GKK,b\91\11/@\80bTe[\00\1C\022;?:,\0D\1Bd}\8CyR\16\00\00\10\17\17\09?I\18\0D\18,\00\00\10!7\84\E1>\00\1F\0E\15)I\19\C9\A8\92\8A\FD\9D\B6bm{C\00]0\17\AC\90K\07\01<\D2\8C|!\A8\DB\D1\C1G\14.Q<]O\1E-k\B5\22X\06\00gFS\15E+!.J6NwG\004q\A7%^u@\0F\1C@h\0C\0C\00\01!%\01\0A\1E\00\00Mr\A8\00W]\00\07\8A\AA\B1\BE5;F\D1\A3=%MP\08-f\00C\C6\B6\87\00\93\93\A3\99\0C\C5\D8\C3\BAh0,3@V\91i9\11]\15Y\00>D>D\14Q.\0E1\0D.$\1E1B\0AJd\94\C8\87R6Z\99}{2\00\05 \0E\00\00\19\00\00V%l\00\A6\C0\BC\9A\9B\8E\A2\D8if\A6\CE\E4oV\1C$)\1A\5C)\00v\CF\AF\B0\A2V\DC:-\99\85\CA\D7\B5\0F3(,\22Eh@Y%\15-\003\91\C0\E4 \22\12\00\00WYE6\18\00\008\8B\AD\D4\C0y8Z:aX=\00#M*\03\00\1E\00\00\1B\0F\00\00+\9D\C8\F7\E3\83T\B4\FA\FF\A6\EC\8B7\07\18\12\1D\09\1F3\AE\A4\A4\DE\B7\D0\F2-\17\08\1A\9A\A0\8B\00D\06=#1b\0E#\1D\18N\00\00R\FF\C6ep\BA\A7:A\BF\8FM\1A(\13\1C\15H\C5\A4\CC\E4cNZ6+\11\00\05M#\0C\00\0E\00\000r\0D3\00\0B\84\C2\F4\D3\BE\C5\E2\CDr\C7\C2! \0C\11J,$\8F\A9\95\9F\C4x\A5\E7 !\17ie\80u\00A\ACzOn\00\00L \19?\1F\99\E3$\00\09C\9Aa\DFF\C0\94Y\00\22P\1C7Q(\C2\BA\C0T^\86\97ye@K\1B<\0E<!\14\00hUFiO\8EX\D7\C4\90\BE\F6\D9m}|\F3\00%\00\08/67:@u\A5\C8\CB\A2\FA\D43\1B\89QG{&\9Ds\83\A3\85\00`\84l$\A4\BAv\12\06\81\B2\00\C2\A0\97\D8\94\FF\A5\00\1ACf\AE\AD\B4\B9\CCXY\DB\DB\B0O$\0E\10\0C%\0265\00\008\14S\9B\DF\E1\CD\9F\E7N\99\A1\DD\D7zp\9B\003\15\1F?\141(\04%S\86\C8\DE\D0\EE\CE\0C6\CF\C1\B4\EEfT\93=\B2\CA\95\B8=!M##Qs\FFU\9A\B3\DC\E3\F9\DD\FF^\00\0DB\91\C1\C1\D6\EF\CED\0B\BE\CC\C4\C4\98/\00&\1F\00\00\1E\00\008\00\AF{\CA\D9\E9\D5\CE\00\81\FC\BC\DF\DE1\16\00\00\05\00)e/3\00`?{\88\EF\D6\B8\B8R\14\FF\DF\ED\FF\BE\9A\9Ca5\F1\E7\EC\0E>#S\80[Q\EE~/vf\CA\F6\15\7Fl\00c\96\5C]v\9BSC\F1\90\D4\D6\A2\19\10\00\00\16\1E\00\00\08\00\002$vod\EF\FF\A3\91\AF\DD\C1\FB\D2\B0\00\00\04\05\00\0E8V.\16&\A5G\9Cu\A7\B7\A2\07\97\8D\C9\E9X\A6\FF\CA\96\96\F9\BE\E9\E7\00Luj7\9B\F1\BE\94XU\D2G\C4\14\E7\E1=*]JeW\7F'\00\B5\8D\C7\C2\FF;\00\00\006\1F\00\00\000_\1Ca\5Cr\82\BC)\AD\B6\9D\95\CB\CB\D4\14)\05\02\17\16\0D(\00-\07\88\A7\B8_@y\88\A4\C9\CD\B2\ED\B1T\1B\B9\D6\84m\93\BC\B8\F6\8B%5\0A\B1{\C7\E1w\ABSEI\BE\F4\C0\C4Z\19\0F:l\7F,7P\B5\A4\98`\A0\E9$\00\00 \00\00\00\00VSlfAJ .9\B8\C2\D9\A8\C9\91\B0,\1E\06\1A(%\18\13\1D\11\11 >\00%HS{-\9D\B6\BB\B3\CEo\E6\C2\DA\99}\A4f:\E4\F25\00$So\FF\D0=\00\07\00J\A0\B7\E7\A3OMPPpA\00f\00i\D0\22\065\B3^H+\16\03\0C\1B\09B;\1B\22%]`2\17(\BA\C2CV\E2\9Dt,!\0D\00\12\00\06\0B\00\1B\03\00 )\0E\04\00Ke\B9\A2\A6\A1\FF\D7\8A\86vc\226:P\FF\96\0A>D\00\E4\009/\0D 'o\85\CE&@El\89/\00+\00\0E\1ES\05\02\16]\BE\0F\12\09\0F\00\00\00;70\1B\0CTs\12\0F\00\0F\A6)V6\D1n0\00\03\09\11\00\00\14\00\1F\09\0F)\19\08\190\00\00\FA\E3\C3\EC\A0\FF\98}O\02\0F\FF\D6)\E6\1E3XE\03\00\0F[%\1CT-\5Ch\AC\008I\95u\00g'\00\1D*\0C\05\10\1D\00M\00\16 \10\00\04\05RiO\00\00\00Zc\1C\0DVmC\15\C6\B1\A2f\00\02\17\05\04\03\0F\12\1E\02\005G\00\14F\14)\E5\D5\FF\DFc\FF\D5\B2t\05\AB\C2\AA(pD1z6/\00\1B1.#27;8B\00+wt\00BR\00\05\18\12\18\00\00\00R\00W\03\08\00\00\00\0B`g\17\0E\05\06\01H\03\0AINa\8C\DA\E0`kS\00\00\04\00\13\13\0E\0E\05\005\00\0B'\0B \0B@\AC],\10s\CB\B3>\13\B9\A2\D1\FF~\DA\8F\86\8C\E0N\003.\1Ajv\1A'\80\00EF\00T(\09 \00\00\00\1F\C4\89\91\11;\00\00\00\00\00\00\00ZR\15\0A\13\0E\08*\14'KOQ\1F[\BF}v\10\0E\00\04\18\0C\00\19\00p\B1b\B0\1F\0BC,\18\00U)\EFB\22\04\8C\93\A6\B5\C3\B7ox`\DC\A8U\92\C5\001\1F\5C\A8@0?!\05#\04\1DU1\00\00\00\05\0C]9\0A\00\0F\00\00\00\00\00\00\00\00PU\00\00\00\13(\1D,\16\19\11[Nc\17Olb\00\06\00\00@\11\13\14\B5\1E\C6\F4\FF\00\1B+\1Bj\10!\D4\FF?#]\E6w\BC\F0\B4\B6\85\C3\D6[H\C1\B7\D4\CE\A5\0BED\1DI4B\00\16\1B(aohi\0F\15\00\11H;5\16\00\00\00\00\00\00\003'\00\00\00\15.\0B\19\1F\12\08\9FEo=\A4l\00\00\02\0C\13O\00\09+\A9\C7e\D4\FF\ED\09\0FgT\0C\16:\B4\13\13\98\84bN\E4\CF\E0\BB\C8\D1\93\10\C2\BB\FF\DF\F1;-+\15%*80+\00\01 \15!nV>9\09\1A\0D\10\00&%\10\00\00\00\00\22#Z\00\00\00\1C\00\00(\00\00mY$\00\00\1F\00\00\00\12L8\00\0A\17\17\F3\EF\BD\9E\E6\E3\A5\E0\BF\04K\AC\10&\8D\12\D2\EC;\DE\CF\B6\D7\D3\A1\BCV\D9\E8\D7\E8\C8t\002\11 Y@*\17\00\00\00\01\016\00\0C\0A(9\10\0075=68\12\0E\10\12\09"], align 1
ram_two_ports hana_bmp (
.clk( clk ),
.address_a( hana_bmp_address_a ),
.wren_a( hana_bmp_write_enable_a ),
.data_a( hana_bmp_in_a ),
.address_b( hana_bmp_address_b ),
.wren_b( hana_bmp_write_enable_b ),
.data_b( hana_bmp_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( hana_bmp_out_a ),
.q_b( hana_bmp_out_b)
);
defparam hana_bmp.width_a = 8;
defparam hana_bmp.widthad_a = 14;
defparam hana_bmp.width_b = 8;
defparam hana_bmp.widthad_b = 14;
defparam hana_bmp.width_be_a = 1;
defparam hana_bmp.width_be_b = 1;
defparam hana_bmp.numwords_a = 15930;
defparam hana_bmp.numwords_b = 15930;
defparam hana_bmp.init_file = "hana_bmp.mif";
reg [3:0] out_unread_marker_address_a;
reg out_unread_marker_write_enable_a;
reg [31:0] out_unread_marker_in_a;
wire [31:0] out_unread_marker_out_a;
reg [3:0] out_unread_marker_address_b;
reg out_unread_marker_write_enable_b;
reg [31:0] out_unread_marker_in_b;
wire [31:0] out_unread_marker_out_b;
// @out_unread_marker = internal unnamed_addr constant [10 x i32] [i32 216, i32 224, i32 219, i32 219, i32 192, i32 196, i32 196, i32 196, i32 196, i32 218], align 4
ram_two_ports out_unread_marker (
.clk( clk ),
.address_a( out_unread_marker_address_a ),
.wren_a( out_unread_marker_write_enable_a ),
.data_a( out_unread_marker_in_a ),
.address_b( out_unread_marker_address_b ),
.wren_b( out_unread_marker_write_enable_b ),
.data_b( out_unread_marker_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_unread_marker_out_a ),
.q_b( out_unread_marker_out_b)
);
defparam out_unread_marker.width_a = 32;
defparam out_unread_marker.widthad_a = 4;
defparam out_unread_marker.width_b = 32;
defparam out_unread_marker.widthad_b = 4;
defparam out_unread_marker.width_be_a = 1;
defparam out_unread_marker.width_be_b = 1;
defparam out_unread_marker.numwords_a = 10;
defparam out_unread_marker.numwords_b = 10;
defparam out_unread_marker.init_file = "out_unread_marker.mif";
reg [1:0] out_index_get_sof_address_a;
reg out_index_get_sof_write_enable_a;
reg [31:0] out_index_get_sof_in_a;
wire [31:0] out_index_get_sof_out_a;
reg [1:0] out_index_get_sof_address_b;
reg out_index_get_sof_write_enable_b;
reg [31:0] out_index_get_sof_in_b;
wire [31:0] out_index_get_sof_out_b;
// @out_index_get_sof = internal unnamed_addr constant [3 x i32] [i32 0, i32 1, i32 2], align 4
ram_two_ports out_index_get_sof (
.clk( clk ),
.address_a( out_index_get_sof_address_a ),
.wren_a( out_index_get_sof_write_enable_a ),
.data_a( out_index_get_sof_in_a ),
.address_b( out_index_get_sof_address_b ),
.wren_b( out_index_get_sof_write_enable_b ),
.data_b( out_index_get_sof_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_index_get_sof_out_a ),
.q_b( out_index_get_sof_out_b)
);
defparam out_index_get_sof.width_a = 32;
defparam out_index_get_sof.widthad_a = 2;
defparam out_index_get_sof.width_b = 32;
defparam out_index_get_sof.widthad_b = 2;
defparam out_index_get_sof.width_be_a = 1;
defparam out_index_get_sof.width_be_b = 1;
defparam out_index_get_sof.numwords_a = 3;
defparam out_index_get_sof.numwords_b = 3;
defparam out_index_get_sof.init_file = "out_index_get_sof.mif";
reg [1:0] out_v_samp_factor_get_sof_address_a;
reg out_v_samp_factor_get_sof_write_enable_a;
reg [31:0] out_v_samp_factor_get_sof_in_a;
wire [31:0] out_v_samp_factor_get_sof_out_a;
reg [1:0] out_v_samp_factor_get_sof_address_b;
reg out_v_samp_factor_get_sof_write_enable_b;
reg [31:0] out_v_samp_factor_get_sof_in_b;
wire [31:0] out_v_samp_factor_get_sof_out_b;
// @out_v_samp_factor_get_sof = internal unnamed_addr constant [3 x i32] [i32 2, i32 1, i32 1], align 4
ram_two_ports out_v_samp_factor_get_sof (
.clk( clk ),
.address_a( out_v_samp_factor_get_sof_address_a ),
.wren_a( out_v_samp_factor_get_sof_write_enable_a ),
.data_a( out_v_samp_factor_get_sof_in_a ),
.address_b( out_v_samp_factor_get_sof_address_b ),
.wren_b( out_v_samp_factor_get_sof_write_enable_b ),
.data_b( out_v_samp_factor_get_sof_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_v_samp_factor_get_sof_out_a ),
.q_b( out_v_samp_factor_get_sof_out_b)
);
defparam out_v_samp_factor_get_sof.width_a = 32;
defparam out_v_samp_factor_get_sof.widthad_a = 2;
defparam out_v_samp_factor_get_sof.width_b = 32;
defparam out_v_samp_factor_get_sof.widthad_b = 2;
defparam out_v_samp_factor_get_sof.width_be_a = 1;
defparam out_v_samp_factor_get_sof.width_be_b = 1;
defparam out_v_samp_factor_get_sof.numwords_a = 3;
defparam out_v_samp_factor_get_sof.numwords_b = 3;
defparam out_v_samp_factor_get_sof.init_file = "out_v_samp_factor_get_sof.mif";
reg [1:0] out_comp_id_get_sos_address_a;
reg out_comp_id_get_sos_write_enable_a;
reg [31:0] out_comp_id_get_sos_in_a;
wire [31:0] out_comp_id_get_sos_out_a;
reg [1:0] out_comp_id_get_sos_address_b;
reg out_comp_id_get_sos_write_enable_b;
reg [31:0] out_comp_id_get_sos_in_b;
wire [31:0] out_comp_id_get_sos_out_b;
// @out_comp_id_get_sos = internal unnamed_addr constant [3 x i32] [i32 1, i32 2, i32 3], align 4
ram_two_ports out_comp_id_get_sos (
.clk( clk ),
.address_a( out_comp_id_get_sos_address_a ),
.wren_a( out_comp_id_get_sos_write_enable_a ),
.data_a( out_comp_id_get_sos_in_a ),
.address_b( out_comp_id_get_sos_address_b ),
.wren_b( out_comp_id_get_sos_write_enable_b ),
.data_b( out_comp_id_get_sos_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_comp_id_get_sos_out_a ),
.q_b( out_comp_id_get_sos_out_b)
);
defparam out_comp_id_get_sos.width_a = 32;
defparam out_comp_id_get_sos.widthad_a = 2;
defparam out_comp_id_get_sos.width_b = 32;
defparam out_comp_id_get_sos.widthad_b = 2;
defparam out_comp_id_get_sos.width_be_a = 1;
defparam out_comp_id_get_sos.width_be_b = 1;
defparam out_comp_id_get_sos.numwords_a = 3;
defparam out_comp_id_get_sos.numwords_b = 3;
defparam out_comp_id_get_sos.init_file = "out_comp_id_get_sos.mif";
reg [1:0] out_ac_tbl_no_get_sos_address_a;
reg out_ac_tbl_no_get_sos_write_enable_a;
reg [31:0] out_ac_tbl_no_get_sos_in_a;
wire [31:0] out_ac_tbl_no_get_sos_out_a;
reg [1:0] out_ac_tbl_no_get_sos_address_b;
reg out_ac_tbl_no_get_sos_write_enable_b;
reg [31:0] out_ac_tbl_no_get_sos_in_b;
wire [31:0] out_ac_tbl_no_get_sos_out_b;
// @out_ac_tbl_no_get_sos = internal unnamed_addr constant [3 x i32] [i32 0, i32 1, i32 1], align 4
ram_two_ports out_ac_tbl_no_get_sos (
.clk( clk ),
.address_a( out_ac_tbl_no_get_sos_address_a ),
.wren_a( out_ac_tbl_no_get_sos_write_enable_a ),
.data_a( out_ac_tbl_no_get_sos_in_a ),
.address_b( out_ac_tbl_no_get_sos_address_b ),
.wren_b( out_ac_tbl_no_get_sos_write_enable_b ),
.data_b( out_ac_tbl_no_get_sos_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_ac_tbl_no_get_sos_out_a ),
.q_b( out_ac_tbl_no_get_sos_out_b)
);
defparam out_ac_tbl_no_get_sos.width_a = 32;
defparam out_ac_tbl_no_get_sos.widthad_a = 2;
defparam out_ac_tbl_no_get_sos.width_b = 32;
defparam out_ac_tbl_no_get_sos.widthad_b = 2;
defparam out_ac_tbl_no_get_sos.width_be_a = 1;
defparam out_ac_tbl_no_get_sos.width_be_b = 1;
defparam out_ac_tbl_no_get_sos.numwords_a = 3;
defparam out_ac_tbl_no_get_sos.numwords_b = 3;
defparam out_ac_tbl_no_get_sos.init_file = "out_ac_tbl_no_get_sos.mif";
reg [1:0] out_length_get_dht_address_a;
reg out_length_get_dht_write_enable_a;
reg [31:0] out_length_get_dht_in_a;
wire [31:0] out_length_get_dht_out_a;
reg [1:0] out_length_get_dht_address_b;
reg out_length_get_dht_write_enable_b;
reg [31:0] out_length_get_dht_in_b;
wire [31:0] out_length_get_dht_out_b;
// @out_length_get_dht = internal unnamed_addr constant [4 x i32] [i32 29, i32 179, i32 29, i32 179], align 4
ram_two_ports out_length_get_dht (
.clk( clk ),
.address_a( out_length_get_dht_address_a ),
.wren_a( out_length_get_dht_write_enable_a ),
.data_a( out_length_get_dht_in_a ),
.address_b( out_length_get_dht_address_b ),
.wren_b( out_length_get_dht_write_enable_b ),
.data_b( out_length_get_dht_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_length_get_dht_out_a ),
.q_b( out_length_get_dht_out_b)
);
defparam out_length_get_dht.width_a = 32;
defparam out_length_get_dht.widthad_a = 2;
defparam out_length_get_dht.width_b = 32;
defparam out_length_get_dht.widthad_b = 2;
defparam out_length_get_dht.width_be_a = 1;
defparam out_length_get_dht.width_be_b = 1;
defparam out_length_get_dht.numwords_a = 4;
defparam out_length_get_dht.numwords_b = 4;
defparam out_length_get_dht.init_file = "out_length_get_dht.mif";
reg [1:0] out_index_get_dht_address_a;
reg out_index_get_dht_write_enable_a;
reg [31:0] out_index_get_dht_in_a;
wire [31:0] out_index_get_dht_out_a;
reg [1:0] out_index_get_dht_address_b;
reg out_index_get_dht_write_enable_b;
reg [31:0] out_index_get_dht_in_b;
wire [31:0] out_index_get_dht_out_b;
// @out_index_get_dht = internal unnamed_addr constant [4 x i32] [i32 0, i32 16, i32 1, i32 17], align 4
ram_two_ports out_index_get_dht (
.clk( clk ),
.address_a( out_index_get_dht_address_a ),
.wren_a( out_index_get_dht_write_enable_a ),
.data_a( out_index_get_dht_in_a ),
.address_b( out_index_get_dht_address_b ),
.wren_b( out_index_get_dht_write_enable_b ),
.data_b( out_index_get_dht_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_index_get_dht_out_a ),
.q_b( out_index_get_dht_out_b)
);
defparam out_index_get_dht.width_a = 32;
defparam out_index_get_dht.widthad_a = 2;
defparam out_index_get_dht.width_b = 32;
defparam out_index_get_dht.widthad_b = 2;
defparam out_index_get_dht.width_be_a = 1;
defparam out_index_get_dht.width_be_b = 1;
defparam out_index_get_dht.numwords_a = 4;
defparam out_index_get_dht.numwords_b = 4;
defparam out_index_get_dht.init_file = "out_index_get_dht.mif";
reg [1:0] out_count_get_dht_address_a;
reg out_count_get_dht_write_enable_a;
reg [31:0] out_count_get_dht_in_a;
wire [31:0] out_count_get_dht_out_a;
reg [1:0] out_count_get_dht_address_b;
reg out_count_get_dht_write_enable_b;
reg [31:0] out_count_get_dht_in_b;
wire [31:0] out_count_get_dht_out_b;
// @out_count_get_dht = internal unnamed_addr constant [4 x i32] [i32 12, i32 162, i32 12, i32 162], align 4
ram_two_ports out_count_get_dht (
.clk( clk ),
.address_a( out_count_get_dht_address_a ),
.wren_a( out_count_get_dht_write_enable_a ),
.data_a( out_count_get_dht_in_a ),
.address_b( out_count_get_dht_address_b ),
.wren_b( out_count_get_dht_write_enable_b ),
.data_b( out_count_get_dht_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_count_get_dht_out_a ),
.q_b( out_count_get_dht_out_b)
);
defparam out_count_get_dht.width_a = 32;
defparam out_count_get_dht.widthad_a = 2;
defparam out_count_get_dht.width_b = 32;
defparam out_count_get_dht.widthad_b = 2;
defparam out_count_get_dht.width_be_a = 1;
defparam out_count_get_dht.width_be_b = 1;
defparam out_count_get_dht.numwords_a = 4;
defparam out_count_get_dht.numwords_b = 4;
defparam out_count_get_dht.init_file = "out_count_get_dht.mif";
reg [0:0] out_length_get_dqt_address_a;
reg out_length_get_dqt_write_enable_a;
reg [31:0] out_length_get_dqt_in_a;
wire [31:0] out_length_get_dqt_out_a;
reg [0:0] out_length_get_dqt_address_b;
reg out_length_get_dqt_write_enable_b;
reg [31:0] out_length_get_dqt_in_b;
wire [31:0] out_length_get_dqt_out_b;
// @out_length_get_dqt = internal unnamed_addr constant [2 x i32] [i32 65, i32 65], align 4
ram_two_ports out_length_get_dqt (
.clk( clk ),
.address_a( out_length_get_dqt_address_a ),
.wren_a( out_length_get_dqt_write_enable_a ),
.data_a( out_length_get_dqt_in_a ),
.address_b( out_length_get_dqt_address_b ),
.wren_b( out_length_get_dqt_write_enable_b ),
.data_b( out_length_get_dqt_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_length_get_dqt_out_a ),
.q_b( out_length_get_dqt_out_b)
);
defparam out_length_get_dqt.width_a = 32;
defparam out_length_get_dqt.widthad_a = 1;
defparam out_length_get_dqt.width_b = 32;
defparam out_length_get_dqt.widthad_b = 1;
defparam out_length_get_dqt.width_be_a = 1;
defparam out_length_get_dqt.width_be_b = 1;
defparam out_length_get_dqt.numwords_a = 2;
defparam out_length_get_dqt.numwords_b = 2;
defparam out_length_get_dqt.init_file = "out_length_get_dqt.mif";
reg [0:0] out_prec_get_dht_address_a;
reg out_prec_get_dht_write_enable_a;
reg [31:0] out_prec_get_dht_in_a;
wire [31:0] out_prec_get_dht_out_a;
reg [0:0] out_prec_get_dht_address_b;
reg out_prec_get_dht_write_enable_b;
reg [31:0] out_prec_get_dht_in_b;
wire [31:0] out_prec_get_dht_out_b;
// @out_prec_get_dht = internal unnamed_addr constant [2 x i32] zeroinitializer, align 4
ram_two_ports out_prec_get_dht (
.clk( clk ),
.address_a( out_prec_get_dht_address_a ),
.wren_a( out_prec_get_dht_write_enable_a ),
.data_a( out_prec_get_dht_in_a ),
.address_b( out_prec_get_dht_address_b ),
.wren_b( out_prec_get_dht_write_enable_b ),
.data_b( out_prec_get_dht_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_prec_get_dht_out_a ),
.q_b( out_prec_get_dht_out_b)
);
defparam out_prec_get_dht.width_a = 32;
defparam out_prec_get_dht.widthad_a = 1;
defparam out_prec_get_dht.width_b = 32;
defparam out_prec_get_dht.widthad_b = 1;
defparam out_prec_get_dht.width_be_a = 1;
defparam out_prec_get_dht.width_be_b = 1;
defparam out_prec_get_dht.numwords_a = 2;
defparam out_prec_get_dht.numwords_b = 2;
defparam out_prec_get_dht.init_file = "out_prec_get_dht.mif";
reg [0:0] out_num_get_dht_address_a;
reg out_num_get_dht_write_enable_a;
reg [31:0] out_num_get_dht_in_a;
wire [31:0] out_num_get_dht_out_a;
reg [0:0] out_num_get_dht_address_b;
reg out_num_get_dht_write_enable_b;
reg [31:0] out_num_get_dht_in_b;
wire [31:0] out_num_get_dht_out_b;
// @out_num_get_dht = internal unnamed_addr constant [2 x i32] [i32 0, i32 1], align 4
ram_two_ports out_num_get_dht (
.clk( clk ),
.address_a( out_num_get_dht_address_a ),
.wren_a( out_num_get_dht_write_enable_a ),
.data_a( out_num_get_dht_in_a ),
.address_b( out_num_get_dht_address_b ),
.wren_b( out_num_get_dht_write_enable_b ),
.data_b( out_num_get_dht_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_num_get_dht_out_a ),
.q_b( out_num_get_dht_out_b)
);
defparam out_num_get_dht.width_a = 32;
defparam out_num_get_dht.widthad_a = 1;
defparam out_num_get_dht.width_b = 32;
defparam out_num_get_dht.widthad_b = 1;
defparam out_num_get_dht.width_be_a = 1;
defparam out_num_get_dht.width_be_b = 1;
defparam out_num_get_dht.numwords_a = 2;
defparam out_num_get_dht.numwords_b = 2;
defparam out_num_get_dht.init_file = "out_num_get_dht.mif";
reg [5:0] izigzag_index_address_a;
reg izigzag_index_write_enable_a;
reg [31:0] izigzag_index_in_a;
wire [31:0] izigzag_index_out_a;
reg [5:0] izigzag_index_address_b;
reg izigzag_index_write_enable_b;
reg [31:0] izigzag_index_in_b;
wire [31:0] izigzag_index_out_b;
// @izigzag_index = internal unnamed_addr constant [64 x i32] [i32 0, i32 1, i32 8, i32 16, i32 9, i32 2, i32 3, i32 10, i32 17, i32 24, i32 32, i32 25, i32 18, i32 11, i32 4, i32 5, i32 12, i32 19, i32 26, i32 33, i32 40, i32 48, i32 41, i32 34, i32 27, i32 20, i32 13, i32 6, i32 7, i32 14, i32 21, i32 28, i32 35, i32 42, i32 49, i32 56, i32 57, i32 50, i32 43, i32 36, i32 29, i32 22, i32 15, i32 23, i32 30, i32 37, i32 44, i32 51, i32 58, i32 59, i32 52, i32 45, i32 38, i32 31, i32 39, i32 46, i32 53, i32 60, i32 61, i32 54, i32 47, i32 55, i32 62, i32 63], align 4
ram_two_ports izigzag_index (
.clk( clk ),
.address_a( izigzag_index_address_a ),
.wren_a( izigzag_index_write_enable_a ),
.data_a( izigzag_index_in_a ),
.address_b( izigzag_index_address_b ),
.wren_b( izigzag_index_write_enable_b ),
.data_b( izigzag_index_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( izigzag_index_out_a ),
.q_b( izigzag_index_out_b)
);
defparam izigzag_index.width_a = 32;
defparam izigzag_index.widthad_a = 6;
defparam izigzag_index.width_b = 32;
defparam izigzag_index.widthad_b = 6;
defparam izigzag_index.width_be_a = 1;
defparam izigzag_index.width_be_b = 1;
defparam izigzag_index.numwords_a = 64;
defparam izigzag_index.numwords_b = 64;
defparam izigzag_index.init_file = "izigzag_index.mif";
reg [0:0] main_result_address_a;
reg main_result_write_enable_a;
reg [31:0] main_result_in_a;
wire [31:0] main_result_out_a;
reg [0:0] main_result_address_b;
reg main_result_write_enable_b;
reg [31:0] main_result_in_b;
wire [31:0] main_result_out_b;
// @main_result = internal unnamed_addr global i32 0, align 4
ram_two_ports main_result (
.clk( clk ),
.address_a( main_result_address_a ),
.wren_a( main_result_write_enable_a ),
.data_a( main_result_in_a ),
.address_b( main_result_address_b ),
.wren_b( main_result_write_enable_b ),
.data_b( main_result_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( main_result_out_a ),
.q_b( main_result_out_b)
);
defparam main_result.width_a = 32;
defparam main_result.widthad_a = 1;
defparam main_result.width_b = 32;
defparam main_result.widthad_b = 1;
defparam main_result.width_be_a = 1;
defparam main_result.width_be_b = 1;
defparam main_result.numwords_a = 1;
defparam main_result.numwords_b = 1;
defparam main_result.init_file = "main_result.mif";
reg [0:0] p_jinfo_image_height_address_a;
reg p_jinfo_image_height_write_enable_a;
reg [15:0] p_jinfo_image_height_in_a;
wire [15:0] p_jinfo_image_height_out_a;
reg [0:0] p_jinfo_image_height_address_b;
reg p_jinfo_image_height_write_enable_b;
reg [15:0] p_jinfo_image_height_in_b;
wire [15:0] p_jinfo_image_height_out_b;
// @p_jinfo_image_height = internal unnamed_addr global i16 0, align 2
ram_two_ports p_jinfo_image_height (
.clk( clk ),
.address_a( p_jinfo_image_height_address_a ),
.wren_a( p_jinfo_image_height_write_enable_a ),
.data_a( p_jinfo_image_height_in_a ),
.address_b( p_jinfo_image_height_address_b ),
.wren_b( p_jinfo_image_height_write_enable_b ),
.data_b( p_jinfo_image_height_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_image_height_out_a ),
.q_b( p_jinfo_image_height_out_b)
);
defparam p_jinfo_image_height.width_a = 16;
defparam p_jinfo_image_height.widthad_a = 1;
defparam p_jinfo_image_height.width_b = 16;
defparam p_jinfo_image_height.widthad_b = 1;
defparam p_jinfo_image_height.width_be_a = 1;
defparam p_jinfo_image_height.width_be_b = 1;
defparam p_jinfo_image_height.numwords_a = 1;
defparam p_jinfo_image_height.numwords_b = 1;
defparam p_jinfo_image_height.init_file = "p_jinfo_image_height.mif";
reg [0:0] p_jinfo_image_width_address_a;
reg p_jinfo_image_width_write_enable_a;
reg [15:0] p_jinfo_image_width_in_a;
wire [15:0] p_jinfo_image_width_out_a;
reg [0:0] p_jinfo_image_width_address_b;
reg p_jinfo_image_width_write_enable_b;
reg [15:0] p_jinfo_image_width_in_b;
wire [15:0] p_jinfo_image_width_out_b;
// @p_jinfo_image_width = internal unnamed_addr global i16 0, align 2
ram_two_ports p_jinfo_image_width (
.clk( clk ),
.address_a( p_jinfo_image_width_address_a ),
.wren_a( p_jinfo_image_width_write_enable_a ),
.data_a( p_jinfo_image_width_in_a ),
.address_b( p_jinfo_image_width_address_b ),
.wren_b( p_jinfo_image_width_write_enable_b ),
.data_b( p_jinfo_image_width_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_image_width_out_a ),
.q_b( p_jinfo_image_width_out_b)
);
defparam p_jinfo_image_width.width_a = 16;
defparam p_jinfo_image_width.widthad_a = 1;
defparam p_jinfo_image_width.width_b = 16;
defparam p_jinfo_image_width.widthad_b = 1;
defparam p_jinfo_image_width.width_be_a = 1;
defparam p_jinfo_image_width.width_be_b = 1;
defparam p_jinfo_image_width.numwords_a = 1;
defparam p_jinfo_image_width.numwords_b = 1;
defparam p_jinfo_image_width.init_file = "p_jinfo_image_width.mif";
reg [1:0] p_jinfo_comps_info_index_address_a;
reg p_jinfo_comps_info_index_write_enable_a;
reg [7:0] p_jinfo_comps_info_index_in_a;
wire [7:0] p_jinfo_comps_info_index_out_a;
reg [1:0] p_jinfo_comps_info_index_address_b;
reg p_jinfo_comps_info_index_write_enable_b;
reg [7:0] p_jinfo_comps_info_index_in_b;
wire [7:0] p_jinfo_comps_info_index_out_b;
// @p_jinfo_comps_info_index = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_index (
.clk( clk ),
.address_a( p_jinfo_comps_info_index_address_a ),
.wren_a( p_jinfo_comps_info_index_write_enable_a ),
.data_a( p_jinfo_comps_info_index_in_a ),
.address_b( p_jinfo_comps_info_index_address_b ),
.wren_b( p_jinfo_comps_info_index_write_enable_b ),
.data_b( p_jinfo_comps_info_index_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_index_out_a ),
.q_b( p_jinfo_comps_info_index_out_b)
);
defparam p_jinfo_comps_info_index.width_a = 8;
defparam p_jinfo_comps_info_index.widthad_a = 2;
defparam p_jinfo_comps_info_index.width_b = 8;
defparam p_jinfo_comps_info_index.widthad_b = 2;
defparam p_jinfo_comps_info_index.width_be_a = 1;
defparam p_jinfo_comps_info_index.width_be_b = 1;
defparam p_jinfo_comps_info_index.numwords_a = 3;
defparam p_jinfo_comps_info_index.numwords_b = 3;
defparam p_jinfo_comps_info_index.init_file = "p_jinfo_comps_info_index.mif";
reg [1:0] p_jinfo_comps_info_id_address_a;
reg p_jinfo_comps_info_id_write_enable_a;
reg [7:0] p_jinfo_comps_info_id_in_a;
wire [7:0] p_jinfo_comps_info_id_out_a;
reg [1:0] p_jinfo_comps_info_id_address_b;
reg p_jinfo_comps_info_id_write_enable_b;
reg [7:0] p_jinfo_comps_info_id_in_b;
wire [7:0] p_jinfo_comps_info_id_out_b;
// @p_jinfo_comps_info_id = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_id (
.clk( clk ),
.address_a( p_jinfo_comps_info_id_address_a ),
.wren_a( p_jinfo_comps_info_id_write_enable_a ),
.data_a( p_jinfo_comps_info_id_in_a ),
.address_b( p_jinfo_comps_info_id_address_b ),
.wren_b( p_jinfo_comps_info_id_write_enable_b ),
.data_b( p_jinfo_comps_info_id_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_id_out_a ),
.q_b( p_jinfo_comps_info_id_out_b)
);
defparam p_jinfo_comps_info_id.width_a = 8;
defparam p_jinfo_comps_info_id.widthad_a = 2;
defparam p_jinfo_comps_info_id.width_b = 8;
defparam p_jinfo_comps_info_id.widthad_b = 2;
defparam p_jinfo_comps_info_id.width_be_a = 1;
defparam p_jinfo_comps_info_id.width_be_b = 1;
defparam p_jinfo_comps_info_id.numwords_a = 3;
defparam p_jinfo_comps_info_id.numwords_b = 3;
defparam p_jinfo_comps_info_id.init_file = "p_jinfo_comps_info_id.mif";
reg [1:0] p_jinfo_comps_info_h_samp_factor_address_a;
reg p_jinfo_comps_info_h_samp_factor_write_enable_a;
reg [7:0] p_jinfo_comps_info_h_samp_factor_in_a;
wire [7:0] p_jinfo_comps_info_h_samp_factor_out_a;
reg [1:0] p_jinfo_comps_info_h_samp_factor_address_b;
reg p_jinfo_comps_info_h_samp_factor_write_enable_b;
reg [7:0] p_jinfo_comps_info_h_samp_factor_in_b;
wire [7:0] p_jinfo_comps_info_h_samp_factor_out_b;
// @p_jinfo_comps_info_h_samp_factor = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_h_samp_factor (
.clk( clk ),
.address_a( p_jinfo_comps_info_h_samp_factor_address_a ),
.wren_a( p_jinfo_comps_info_h_samp_factor_write_enable_a ),
.data_a( p_jinfo_comps_info_h_samp_factor_in_a ),
.address_b( p_jinfo_comps_info_h_samp_factor_address_b ),
.wren_b( p_jinfo_comps_info_h_samp_factor_write_enable_b ),
.data_b( p_jinfo_comps_info_h_samp_factor_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_h_samp_factor_out_a ),
.q_b( p_jinfo_comps_info_h_samp_factor_out_b)
);
defparam p_jinfo_comps_info_h_samp_factor.width_a = 8;
defparam p_jinfo_comps_info_h_samp_factor.widthad_a = 2;
defparam p_jinfo_comps_info_h_samp_factor.width_b = 8;
defparam p_jinfo_comps_info_h_samp_factor.widthad_b = 2;
defparam p_jinfo_comps_info_h_samp_factor.width_be_a = 1;
defparam p_jinfo_comps_info_h_samp_factor.width_be_b = 1;
defparam p_jinfo_comps_info_h_samp_factor.numwords_a = 3;
defparam p_jinfo_comps_info_h_samp_factor.numwords_b = 3;
defparam p_jinfo_comps_info_h_samp_factor.init_file = "p_jinfo_comps_info_h_samp_factor.mif";
reg [1:0] p_jinfo_comps_info_v_samp_factor_address_a;
reg p_jinfo_comps_info_v_samp_factor_write_enable_a;
reg [7:0] p_jinfo_comps_info_v_samp_factor_in_a;
wire [7:0] p_jinfo_comps_info_v_samp_factor_out_a;
reg [1:0] p_jinfo_comps_info_v_samp_factor_address_b;
reg p_jinfo_comps_info_v_samp_factor_write_enable_b;
reg [7:0] p_jinfo_comps_info_v_samp_factor_in_b;
wire [7:0] p_jinfo_comps_info_v_samp_factor_out_b;
// @p_jinfo_comps_info_v_samp_factor = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_v_samp_factor (
.clk( clk ),
.address_a( p_jinfo_comps_info_v_samp_factor_address_a ),
.wren_a( p_jinfo_comps_info_v_samp_factor_write_enable_a ),
.data_a( p_jinfo_comps_info_v_samp_factor_in_a ),
.address_b( p_jinfo_comps_info_v_samp_factor_address_b ),
.wren_b( p_jinfo_comps_info_v_samp_factor_write_enable_b ),
.data_b( p_jinfo_comps_info_v_samp_factor_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_v_samp_factor_out_a ),
.q_b( p_jinfo_comps_info_v_samp_factor_out_b)
);
defparam p_jinfo_comps_info_v_samp_factor.width_a = 8;
defparam p_jinfo_comps_info_v_samp_factor.widthad_a = 2;
defparam p_jinfo_comps_info_v_samp_factor.width_b = 8;
defparam p_jinfo_comps_info_v_samp_factor.widthad_b = 2;
defparam p_jinfo_comps_info_v_samp_factor.width_be_a = 1;
defparam p_jinfo_comps_info_v_samp_factor.width_be_b = 1;
defparam p_jinfo_comps_info_v_samp_factor.numwords_a = 3;
defparam p_jinfo_comps_info_v_samp_factor.numwords_b = 3;
defparam p_jinfo_comps_info_v_samp_factor.init_file = "p_jinfo_comps_info_v_samp_factor.mif";
reg [1:0] p_jinfo_comps_info_quant_tbl_no_address_a;
reg p_jinfo_comps_info_quant_tbl_no_write_enable_a;
reg [7:0] p_jinfo_comps_info_quant_tbl_no_in_a;
wire [7:0] p_jinfo_comps_info_quant_tbl_no_out_a;
reg [1:0] p_jinfo_comps_info_quant_tbl_no_address_b;
reg p_jinfo_comps_info_quant_tbl_no_write_enable_b;
reg [7:0] p_jinfo_comps_info_quant_tbl_no_in_b;
wire [7:0] p_jinfo_comps_info_quant_tbl_no_out_b;
// @p_jinfo_comps_info_quant_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_quant_tbl_no (
.clk( clk ),
.address_a( p_jinfo_comps_info_quant_tbl_no_address_a ),
.wren_a( p_jinfo_comps_info_quant_tbl_no_write_enable_a ),
.data_a( p_jinfo_comps_info_quant_tbl_no_in_a ),
.address_b( p_jinfo_comps_info_quant_tbl_no_address_b ),
.wren_b( p_jinfo_comps_info_quant_tbl_no_write_enable_b ),
.data_b( p_jinfo_comps_info_quant_tbl_no_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_quant_tbl_no_out_a ),
.q_b( p_jinfo_comps_info_quant_tbl_no_out_b)
);
defparam p_jinfo_comps_info_quant_tbl_no.width_a = 8;
defparam p_jinfo_comps_info_quant_tbl_no.widthad_a = 2;
defparam p_jinfo_comps_info_quant_tbl_no.width_b = 8;
defparam p_jinfo_comps_info_quant_tbl_no.widthad_b = 2;
defparam p_jinfo_comps_info_quant_tbl_no.width_be_a = 1;
defparam p_jinfo_comps_info_quant_tbl_no.width_be_b = 1;
defparam p_jinfo_comps_info_quant_tbl_no.numwords_a = 3;
defparam p_jinfo_comps_info_quant_tbl_no.numwords_b = 3;
defparam p_jinfo_comps_info_quant_tbl_no.init_file = "p_jinfo_comps_info_quant_tbl_no.mif";
reg [1:0] p_jinfo_comps_info_dc_tbl_no_address_a;
reg p_jinfo_comps_info_dc_tbl_no_write_enable_a;
reg [7:0] p_jinfo_comps_info_dc_tbl_no_in_a;
wire [7:0] p_jinfo_comps_info_dc_tbl_no_out_a;
reg [1:0] p_jinfo_comps_info_dc_tbl_no_address_b;
reg p_jinfo_comps_info_dc_tbl_no_write_enable_b;
reg [7:0] p_jinfo_comps_info_dc_tbl_no_in_b;
wire [7:0] p_jinfo_comps_info_dc_tbl_no_out_b;
// @p_jinfo_comps_info_dc_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_dc_tbl_no (
.clk( clk ),
.address_a( p_jinfo_comps_info_dc_tbl_no_address_a ),
.wren_a( p_jinfo_comps_info_dc_tbl_no_write_enable_a ),
.data_a( p_jinfo_comps_info_dc_tbl_no_in_a ),
.address_b( p_jinfo_comps_info_dc_tbl_no_address_b ),
.wren_b( p_jinfo_comps_info_dc_tbl_no_write_enable_b ),
.data_b( p_jinfo_comps_info_dc_tbl_no_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_dc_tbl_no_out_a ),
.q_b( p_jinfo_comps_info_dc_tbl_no_out_b)
);
defparam p_jinfo_comps_info_dc_tbl_no.width_a = 8;
defparam p_jinfo_comps_info_dc_tbl_no.widthad_a = 2;
defparam p_jinfo_comps_info_dc_tbl_no.width_b = 8;
defparam p_jinfo_comps_info_dc_tbl_no.widthad_b = 2;
defparam p_jinfo_comps_info_dc_tbl_no.width_be_a = 1;
defparam p_jinfo_comps_info_dc_tbl_no.width_be_b = 1;
defparam p_jinfo_comps_info_dc_tbl_no.numwords_a = 3;
defparam p_jinfo_comps_info_dc_tbl_no.numwords_b = 3;
defparam p_jinfo_comps_info_dc_tbl_no.init_file = "p_jinfo_comps_info_dc_tbl_no.mif";
reg [1:0] p_jinfo_comps_info_ac_tbl_no_address_a;
reg p_jinfo_comps_info_ac_tbl_no_write_enable_a;
reg [7:0] p_jinfo_comps_info_ac_tbl_no_in_a;
wire [7:0] p_jinfo_comps_info_ac_tbl_no_out_a;
reg [1:0] p_jinfo_comps_info_ac_tbl_no_address_b;
reg p_jinfo_comps_info_ac_tbl_no_write_enable_b;
reg [7:0] p_jinfo_comps_info_ac_tbl_no_in_b;
wire [7:0] p_jinfo_comps_info_ac_tbl_no_out_b;
// @p_jinfo_comps_info_ac_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_ac_tbl_no (
.clk( clk ),
.address_a( p_jinfo_comps_info_ac_tbl_no_address_a ),
.wren_a( p_jinfo_comps_info_ac_tbl_no_write_enable_a ),
.data_a( p_jinfo_comps_info_ac_tbl_no_in_a ),
.address_b( p_jinfo_comps_info_ac_tbl_no_address_b ),
.wren_b( p_jinfo_comps_info_ac_tbl_no_write_enable_b ),
.data_b( p_jinfo_comps_info_ac_tbl_no_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_ac_tbl_no_out_a ),
.q_b( p_jinfo_comps_info_ac_tbl_no_out_b)
);
defparam p_jinfo_comps_info_ac_tbl_no.width_a = 8;
defparam p_jinfo_comps_info_ac_tbl_no.widthad_a = 2;
defparam p_jinfo_comps_info_ac_tbl_no.width_b = 8;
defparam p_jinfo_comps_info_ac_tbl_no.widthad_b = 2;
defparam p_jinfo_comps_info_ac_tbl_no.width_be_a = 1;
defparam p_jinfo_comps_info_ac_tbl_no.width_be_b = 1;
defparam p_jinfo_comps_info_ac_tbl_no.numwords_a = 3;
defparam p_jinfo_comps_info_ac_tbl_no.numwords_b = 3;
defparam p_jinfo_comps_info_ac_tbl_no.init_file = "p_jinfo_comps_info_ac_tbl_no.mif";
reg [6:0] p_jinfo_ac_xhuff_tbl_bits_address_a;
reg p_jinfo_ac_xhuff_tbl_bits_write_enable_a;
reg [31:0] p_jinfo_ac_xhuff_tbl_bits_in_a;
wire [31:0] p_jinfo_ac_xhuff_tbl_bits_out_a;
reg [6:0] p_jinfo_ac_xhuff_tbl_bits_address_b;
reg p_jinfo_ac_xhuff_tbl_bits_write_enable_b;
reg [31:0] p_jinfo_ac_xhuff_tbl_bits_in_b;
wire [31:0] p_jinfo_ac_xhuff_tbl_bits_out_b;
// @p_jinfo_ac_xhuff_tbl_bits = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_xhuff_tbl_bits (
.clk( clk ),
.address_a( p_jinfo_ac_xhuff_tbl_bits_address_a ),
.wren_a( p_jinfo_ac_xhuff_tbl_bits_write_enable_a ),
.data_a( p_jinfo_ac_xhuff_tbl_bits_in_a ),
.address_b( p_jinfo_ac_xhuff_tbl_bits_address_b ),
.wren_b( p_jinfo_ac_xhuff_tbl_bits_write_enable_b ),
.data_b( p_jinfo_ac_xhuff_tbl_bits_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_xhuff_tbl_bits_out_a ),
.q_b( p_jinfo_ac_xhuff_tbl_bits_out_b)
);
defparam p_jinfo_ac_xhuff_tbl_bits.width_a = 32;
defparam p_jinfo_ac_xhuff_tbl_bits.widthad_a = 7;
defparam p_jinfo_ac_xhuff_tbl_bits.width_b = 32;
defparam p_jinfo_ac_xhuff_tbl_bits.widthad_b = 7;
defparam p_jinfo_ac_xhuff_tbl_bits.width_be_a = 1;
defparam p_jinfo_ac_xhuff_tbl_bits.width_be_b = 1;
defparam p_jinfo_ac_xhuff_tbl_bits.numwords_a = 72;
defparam p_jinfo_ac_xhuff_tbl_bits.numwords_b = 72;
defparam p_jinfo_ac_xhuff_tbl_bits.init_file = "p_jinfo_ac_xhuff_tbl_bits.mif";
reg [9:0] p_jinfo_ac_xhuff_tbl_huffval_address_a;
reg p_jinfo_ac_xhuff_tbl_huffval_write_enable_a;
reg [31:0] p_jinfo_ac_xhuff_tbl_huffval_in_a;
wire [31:0] p_jinfo_ac_xhuff_tbl_huffval_out_a;
reg [9:0] p_jinfo_ac_xhuff_tbl_huffval_address_b;
reg p_jinfo_ac_xhuff_tbl_huffval_write_enable_b;
reg [31:0] p_jinfo_ac_xhuff_tbl_huffval_in_b;
wire [31:0] p_jinfo_ac_xhuff_tbl_huffval_out_b;
// @p_jinfo_ac_xhuff_tbl_huffval = internal global [2 x [257 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_xhuff_tbl_huffval (
.clk( clk ),
.address_a( p_jinfo_ac_xhuff_tbl_huffval_address_a ),
.wren_a( p_jinfo_ac_xhuff_tbl_huffval_write_enable_a ),
.data_a( p_jinfo_ac_xhuff_tbl_huffval_in_a ),
.address_b( p_jinfo_ac_xhuff_tbl_huffval_address_b ),
.wren_b( p_jinfo_ac_xhuff_tbl_huffval_write_enable_b ),
.data_b( p_jinfo_ac_xhuff_tbl_huffval_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_xhuff_tbl_huffval_out_a ),
.q_b( p_jinfo_ac_xhuff_tbl_huffval_out_b)
);
defparam p_jinfo_ac_xhuff_tbl_huffval.width_a = 32;
defparam p_jinfo_ac_xhuff_tbl_huffval.widthad_a = 10;
defparam p_jinfo_ac_xhuff_tbl_huffval.width_b = 32;
defparam p_jinfo_ac_xhuff_tbl_huffval.widthad_b = 10;
defparam p_jinfo_ac_xhuff_tbl_huffval.width_be_a = 1;
defparam p_jinfo_ac_xhuff_tbl_huffval.width_be_b = 1;
defparam p_jinfo_ac_xhuff_tbl_huffval.numwords_a = 514;
defparam p_jinfo_ac_xhuff_tbl_huffval.numwords_b = 514;
defparam p_jinfo_ac_xhuff_tbl_huffval.init_file = "p_jinfo_ac_xhuff_tbl_huffval.mif";
reg [6:0] p_jinfo_dc_xhuff_tbl_bits_address_a;
reg p_jinfo_dc_xhuff_tbl_bits_write_enable_a;
reg [31:0] p_jinfo_dc_xhuff_tbl_bits_in_a;
wire [31:0] p_jinfo_dc_xhuff_tbl_bits_out_a;
reg [6:0] p_jinfo_dc_xhuff_tbl_bits_address_b;
reg p_jinfo_dc_xhuff_tbl_bits_write_enable_b;
reg [31:0] p_jinfo_dc_xhuff_tbl_bits_in_b;
wire [31:0] p_jinfo_dc_xhuff_tbl_bits_out_b;
// @p_jinfo_dc_xhuff_tbl_bits = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_xhuff_tbl_bits (
.clk( clk ),
.address_a( p_jinfo_dc_xhuff_tbl_bits_address_a ),
.wren_a( p_jinfo_dc_xhuff_tbl_bits_write_enable_a ),
.data_a( p_jinfo_dc_xhuff_tbl_bits_in_a ),
.address_b( p_jinfo_dc_xhuff_tbl_bits_address_b ),
.wren_b( p_jinfo_dc_xhuff_tbl_bits_write_enable_b ),
.data_b( p_jinfo_dc_xhuff_tbl_bits_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_xhuff_tbl_bits_out_a ),
.q_b( p_jinfo_dc_xhuff_tbl_bits_out_b)
);
defparam p_jinfo_dc_xhuff_tbl_bits.width_a = 32;
defparam p_jinfo_dc_xhuff_tbl_bits.widthad_a = 7;
defparam p_jinfo_dc_xhuff_tbl_bits.width_b = 32;
defparam p_jinfo_dc_xhuff_tbl_bits.widthad_b = 7;
defparam p_jinfo_dc_xhuff_tbl_bits.width_be_a = 1;
defparam p_jinfo_dc_xhuff_tbl_bits.width_be_b = 1;
defparam p_jinfo_dc_xhuff_tbl_bits.numwords_a = 72;
defparam p_jinfo_dc_xhuff_tbl_bits.numwords_b = 72;
defparam p_jinfo_dc_xhuff_tbl_bits.init_file = "p_jinfo_dc_xhuff_tbl_bits.mif";
reg [9:0] p_jinfo_dc_xhuff_tbl_huffval_address_a;
reg p_jinfo_dc_xhuff_tbl_huffval_write_enable_a;
reg [31:0] p_jinfo_dc_xhuff_tbl_huffval_in_a;
wire [31:0] p_jinfo_dc_xhuff_tbl_huffval_out_a;
reg [9:0] p_jinfo_dc_xhuff_tbl_huffval_address_b;
reg p_jinfo_dc_xhuff_tbl_huffval_write_enable_b;
reg [31:0] p_jinfo_dc_xhuff_tbl_huffval_in_b;
wire [31:0] p_jinfo_dc_xhuff_tbl_huffval_out_b;
// @p_jinfo_dc_xhuff_tbl_huffval = internal global [2 x [257 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_xhuff_tbl_huffval (
.clk( clk ),
.address_a( p_jinfo_dc_xhuff_tbl_huffval_address_a ),
.wren_a( p_jinfo_dc_xhuff_tbl_huffval_write_enable_a ),
.data_a( p_jinfo_dc_xhuff_tbl_huffval_in_a ),
.address_b( p_jinfo_dc_xhuff_tbl_huffval_address_b ),
.wren_b( p_jinfo_dc_xhuff_tbl_huffval_write_enable_b ),
.data_b( p_jinfo_dc_xhuff_tbl_huffval_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_xhuff_tbl_huffval_out_a ),
.q_b( p_jinfo_dc_xhuff_tbl_huffval_out_b)
);
defparam p_jinfo_dc_xhuff_tbl_huffval.width_a = 32;
defparam p_jinfo_dc_xhuff_tbl_huffval.widthad_a = 10;
defparam p_jinfo_dc_xhuff_tbl_huffval.width_b = 32;
defparam p_jinfo_dc_xhuff_tbl_huffval.widthad_b = 10;
defparam p_jinfo_dc_xhuff_tbl_huffval.width_be_a = 1;
defparam p_jinfo_dc_xhuff_tbl_huffval.width_be_b = 1;
defparam p_jinfo_dc_xhuff_tbl_huffval.numwords_a = 514;
defparam p_jinfo_dc_xhuff_tbl_huffval.numwords_b = 514;
defparam p_jinfo_dc_xhuff_tbl_huffval.init_file = "p_jinfo_dc_xhuff_tbl_huffval.mif";
reg [7:0] p_jinfo_quant_tbl_quantval_address_a;
reg p_jinfo_quant_tbl_quantval_write_enable_a;
reg [31:0] p_jinfo_quant_tbl_quantval_in_a;
wire [31:0] p_jinfo_quant_tbl_quantval_out_a;
reg [7:0] p_jinfo_quant_tbl_quantval_address_b;
reg p_jinfo_quant_tbl_quantval_write_enable_b;
reg [31:0] p_jinfo_quant_tbl_quantval_in_b;
wire [31:0] p_jinfo_quant_tbl_quantval_out_b;
// @p_jinfo_quant_tbl_quantval = internal unnamed_addr global [4 x [64 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_quant_tbl_quantval (
.clk( clk ),
.address_a( p_jinfo_quant_tbl_quantval_address_a ),
.wren_a( p_jinfo_quant_tbl_quantval_write_enable_a ),
.data_a( p_jinfo_quant_tbl_quantval_in_a ),
.address_b( p_jinfo_quant_tbl_quantval_address_b ),
.wren_b( p_jinfo_quant_tbl_quantval_write_enable_b ),
.data_b( p_jinfo_quant_tbl_quantval_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_quant_tbl_quantval_out_a ),
.q_b( p_jinfo_quant_tbl_quantval_out_b)
);
defparam p_jinfo_quant_tbl_quantval.width_a = 32;
defparam p_jinfo_quant_tbl_quantval.widthad_a = 8;
defparam p_jinfo_quant_tbl_quantval.width_b = 32;
defparam p_jinfo_quant_tbl_quantval.widthad_b = 8;
defparam p_jinfo_quant_tbl_quantval.width_be_a = 1;
defparam p_jinfo_quant_tbl_quantval.width_be_b = 1;
defparam p_jinfo_quant_tbl_quantval.numwords_a = 256;
defparam p_jinfo_quant_tbl_quantval.numwords_b = 256;
defparam p_jinfo_quant_tbl_quantval.init_file = "p_jinfo_quant_tbl_quantval.mif";
reg [5:0] zigzag_index_address_a;
reg zigzag_index_write_enable_a;
reg [31:0] zigzag_index_in_a;
wire [31:0] zigzag_index_out_a;
reg [5:0] zigzag_index_address_b;
reg zigzag_index_write_enable_b;
reg [31:0] zigzag_index_in_b;
wire [31:0] zigzag_index_out_b;
// @zigzag_index = internal unnamed_addr constant [64 x i32] [i32 0, i32 1, i32 5, i32 6, i32 14, i32 15, i32 27, i32 28, i32 2, i32 4, i32 7, i32 13, i32 16, i32 26, i32 29, i32 42, i32 3, i32 8, i32 12, i32 17, i32 25, i32 30, i32 41, i32 43, i32 9, i32 11, i32 18, i32 24, i32 31, i32 40, i32 44, i32 53, i32 10, i32 19, i32 23, i32 32, i32 39, i32 45, i32 52, i32 54, i32 20, i32 22, i32 33, i32 38, i32 46, i32 51, i32 55, i32 60, i32 21, i32 34, i32 37, i32 47, i32 50, i32 56, i32 59, i32 61, i32 35, i32 36, i32 48, i32 49, i32 57, i32 58, i32 62, i32 63], align 4
ram_two_ports zigzag_index (
.clk( clk ),
.address_a( zigzag_index_address_a ),
.wren_a( zigzag_index_write_enable_a ),
.data_a( zigzag_index_in_a ),
.address_b( zigzag_index_address_b ),
.wren_b( zigzag_index_write_enable_b ),
.data_b( zigzag_index_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( zigzag_index_out_a ),
.q_b( zigzag_index_out_b)
);
defparam zigzag_index.width_a = 32;
defparam zigzag_index.widthad_a = 6;
defparam zigzag_index.width_b = 32;
defparam zigzag_index.widthad_b = 6;
defparam zigzag_index.width_be_a = 1;
defparam zigzag_index.width_be_b = 1;
defparam zigzag_index.numwords_a = 64;
defparam zigzag_index.numwords_b = 64;
defparam zigzag_index.init_file = "zigzag_index.mif";
reg [0:0] p_jinfo_MCUWidth_address_a;
reg p_jinfo_MCUWidth_write_enable_a;
reg [31:0] p_jinfo_MCUWidth_in_a;
wire [31:0] p_jinfo_MCUWidth_out_a;
reg [0:0] p_jinfo_MCUWidth_address_b;
reg p_jinfo_MCUWidth_write_enable_b;
reg [31:0] p_jinfo_MCUWidth_in_b;
wire [31:0] p_jinfo_MCUWidth_out_b;
// @p_jinfo_MCUWidth = internal unnamed_addr global i32 0, align 4
ram_two_ports p_jinfo_MCUWidth (
.clk( clk ),
.address_a( p_jinfo_MCUWidth_address_a ),
.wren_a( p_jinfo_MCUWidth_write_enable_a ),
.data_a( p_jinfo_MCUWidth_in_a ),
.address_b( p_jinfo_MCUWidth_address_b ),
.wren_b( p_jinfo_MCUWidth_write_enable_b ),
.data_b( p_jinfo_MCUWidth_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_MCUWidth_out_a ),
.q_b( p_jinfo_MCUWidth_out_b)
);
defparam p_jinfo_MCUWidth.width_a = 32;
defparam p_jinfo_MCUWidth.widthad_a = 1;
defparam p_jinfo_MCUWidth.width_b = 32;
defparam p_jinfo_MCUWidth.widthad_b = 1;
defparam p_jinfo_MCUWidth.width_be_a = 1;
defparam p_jinfo_MCUWidth.width_be_b = 1;
defparam p_jinfo_MCUWidth.numwords_a = 1;
defparam p_jinfo_MCUWidth.numwords_b = 1;
defparam p_jinfo_MCUWidth.init_file = "p_jinfo_MCUWidth.mif";
reg [9:0] rgb_buf_address_a;
reg rgb_buf_write_enable_a;
reg [31:0] rgb_buf_in_a;
wire [31:0] rgb_buf_out_a;
reg [9:0] rgb_buf_address_b;
reg rgb_buf_write_enable_b;
reg [31:0] rgb_buf_in_b;
wire [31:0] rgb_buf_out_b;
// @rgb_buf = internal global [4 x [3 x [64 x i32]]] zeroinitializer, align 4
ram_two_ports rgb_buf (
.clk( clk ),
.address_a( rgb_buf_address_a ),
.wren_a( rgb_buf_write_enable_a ),
.data_a( rgb_buf_in_a ),
.address_b( rgb_buf_address_b ),
.wren_b( rgb_buf_write_enable_b ),
.data_b( rgb_buf_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( rgb_buf_out_a ),
.q_b( rgb_buf_out_b)
);
defparam rgb_buf.width_a = 32;
defparam rgb_buf.widthad_a = 10;
defparam rgb_buf.width_b = 32;
defparam rgb_buf.widthad_b = 10;
defparam rgb_buf.width_be_a = 1;
defparam rgb_buf.width_be_b = 1;
defparam rgb_buf.numwords_a = 768;
defparam rgb_buf.numwords_b = 768;
defparam rgb_buf.init_file = "rgb_buf.mif";
reg [0:0] CurHuffReadBuf_address_a;
reg CurHuffReadBuf_write_enable_a;
reg [31:0] CurHuffReadBuf_in_a;
wire [31:0] CurHuffReadBuf_out_a;
reg [0:0] CurHuffReadBuf_address_b;
reg CurHuffReadBuf_write_enable_b;
reg [31:0] CurHuffReadBuf_in_b;
wire [31:0] CurHuffReadBuf_out_b;
// @CurHuffReadBuf = internal unnamed_addr global i8* null, align 4
ram_two_ports CurHuffReadBuf (
.clk( clk ),
.address_a( CurHuffReadBuf_address_a ),
.wren_a( CurHuffReadBuf_write_enable_a ),
.data_a( CurHuffReadBuf_in_a ),
.address_b( CurHuffReadBuf_address_b ),
.wren_b( CurHuffReadBuf_write_enable_b ),
.data_b( CurHuffReadBuf_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( CurHuffReadBuf_out_a ),
.q_b( CurHuffReadBuf_out_b)
);
defparam CurHuffReadBuf.width_a = 32;
defparam CurHuffReadBuf.widthad_a = 1;
defparam CurHuffReadBuf.width_b = 32;
defparam CurHuffReadBuf.widthad_b = 1;
defparam CurHuffReadBuf.width_be_a = 1;
defparam CurHuffReadBuf.width_be_b = 1;
defparam CurHuffReadBuf.numwords_a = 1;
defparam CurHuffReadBuf.numwords_b = 1;
defparam CurHuffReadBuf.init_file = "CurHuffReadBuf.mif";
reg [13:0] OutData_comp_buf_address_a;
reg OutData_comp_buf_write_enable_a;
reg [7:0] OutData_comp_buf_in_a;
wire [7:0] OutData_comp_buf_out_a;
reg [13:0] OutData_comp_buf_address_b;
reg OutData_comp_buf_write_enable_b;
reg [7:0] OutData_comp_buf_in_b;
wire [7:0] OutData_comp_buf_out_b;
// @OutData_comp_buf = internal global [3 x [5310 x i8]] zeroinitializer, align 1
ram_two_ports OutData_comp_buf (
.clk( clk ),
.address_a( OutData_comp_buf_address_a ),
.wren_a( OutData_comp_buf_write_enable_a ),
.data_a( OutData_comp_buf_in_a ),
.address_b( OutData_comp_buf_address_b ),
.wren_b( OutData_comp_buf_write_enable_b ),
.data_b( OutData_comp_buf_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( OutData_comp_buf_out_a ),
.q_b( OutData_comp_buf_out_b)
);
defparam OutData_comp_buf.width_a = 8;
defparam OutData_comp_buf.widthad_a = 14;
defparam OutData_comp_buf.width_b = 8;
defparam OutData_comp_buf.widthad_b = 14;
defparam OutData_comp_buf.width_be_a = 1;
defparam OutData_comp_buf.width_be_b = 1;
defparam OutData_comp_buf.numwords_a = 15930;
defparam OutData_comp_buf.numwords_b = 15930;
defparam OutData_comp_buf.init_file = "OutData_comp_buf.mif";
reg [4:0] bit_set_mask_address_a;
reg bit_set_mask_write_enable_a;
reg [31:0] bit_set_mask_in_a;
wire [31:0] bit_set_mask_out_a;
reg [4:0] bit_set_mask_address_b;
reg bit_set_mask_write_enable_b;
reg [31:0] bit_set_mask_in_b;
wire [31:0] bit_set_mask_out_b;
// @bit_set_mask = internal unnamed_addr constant [32 x i32] [i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 512, i32 1024, i32 2048, i32 4096, i32 8192, i32 16384, i32 32768, i32 65536, i32 131072, i32 262144, i32 524288, i32 1048576, i32 2097152, i32 4194304, i32 8388608, i32 16777216, i32 33554432, i32 67108864, i32 134217728, i32 268435456, i32 536870912, i32 1073741824, i32 -2147483648], align 4
ram_two_ports bit_set_mask (
.clk( clk ),
.address_a( bit_set_mask_address_a ),
.wren_a( bit_set_mask_write_enable_a ),
.data_a( bit_set_mask_in_a ),
.address_b( bit_set_mask_address_b ),
.wren_b( bit_set_mask_write_enable_b ),
.data_b( bit_set_mask_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( bit_set_mask_out_a ),
.q_b( bit_set_mask_out_b)
);
defparam bit_set_mask.width_a = 32;
defparam bit_set_mask.widthad_a = 5;
defparam bit_set_mask.width_b = 32;
defparam bit_set_mask.widthad_b = 5;
defparam bit_set_mask.width_be_a = 1;
defparam bit_set_mask.width_be_b = 1;
defparam bit_set_mask.numwords_a = 32;
defparam bit_set_mask.numwords_b = 32;
defparam bit_set_mask.init_file = "bit_set_mask.mif";
reg [4:0] lmask_address_a;
reg lmask_write_enable_a;
reg [31:0] lmask_in_a;
wire [31:0] lmask_out_a;
reg [4:0] lmask_address_b;
reg lmask_write_enable_b;
reg [31:0] lmask_in_b;
wire [31:0] lmask_out_b;
// @lmask = internal unnamed_addr constant [32 x i32] [i32 1, i32 3, i32 7, i32 15, i32 31, i32 63, i32 127, i32 255, i32 511, i32 1023, i32 2047, i32 4095, i32 8191, i32 16383, i32 32767, i32 65535, i32 131071, i32 262143, i32 524287, i32 1048575, i32 2097151, i32 4194303, i32 8388607, i32 16777215, i32 33554431, i32 67108863, i32 134217727, i32 268435455, i32 536870911, i32 1073741823, i32 2147483647, i32 -1], align 4
ram_two_ports lmask (
.clk( clk ),
.address_a( lmask_address_a ),
.wren_a( lmask_write_enable_a ),
.data_a( lmask_in_a ),
.address_b( lmask_address_b ),
.wren_b( lmask_write_enable_b ),
.data_b( lmask_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( lmask_out_a ),
.q_b( lmask_out_b)
);
defparam lmask.width_a = 32;
defparam lmask.widthad_a = 5;
defparam lmask.width_b = 32;
defparam lmask.widthad_b = 5;
defparam lmask.width_be_a = 1;
defparam lmask.width_be_b = 1;
defparam lmask.numwords_a = 32;
defparam lmask.numwords_b = 32;
defparam lmask.init_file = "lmask.mif";
reg [0:0] read_position_address_a;
reg read_position_write_enable_a;
reg [31:0] read_position_in_a;
wire [31:0] read_position_out_a;
reg [0:0] read_position_address_b;
reg read_position_write_enable_b;
reg [31:0] read_position_in_b;
wire [31:0] read_position_out_b;
// @read_position = internal unnamed_addr global i32 -1, align 4
ram_two_ports read_position (
.clk( clk ),
.address_a( read_position_address_a ),
.wren_a( read_position_write_enable_a ),
.data_a( read_position_in_a ),
.address_b( read_position_address_b ),
.wren_b( read_position_write_enable_b ),
.data_b( read_position_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( read_position_out_a ),
.q_b( read_position_out_b)
);
defparam read_position.width_a = 32;
defparam read_position.widthad_a = 1;
defparam read_position.width_b = 32;
defparam read_position.widthad_b = 1;
defparam read_position.width_be_a = 1;
defparam read_position.width_be_b = 1;
defparam read_position.numwords_a = 1;
defparam read_position.numwords_b = 1;
defparam read_position.init_file = "read_position.mif";
reg [0:0] current_read_byte_address_a;
reg current_read_byte_write_enable_a;
reg [31:0] current_read_byte_in_a;
wire [31:0] current_read_byte_out_a;
reg [0:0] current_read_byte_address_b;
reg current_read_byte_write_enable_b;
reg [31:0] current_read_byte_in_b;
wire [31:0] current_read_byte_out_b;
// @current_read_byte = internal unnamed_addr global i32 0, align 4
ram_two_ports current_read_byte (
.clk( clk ),
.address_a( current_read_byte_address_a ),
.wren_a( current_read_byte_write_enable_a ),
.data_a( current_read_byte_in_a ),
.address_b( current_read_byte_address_b ),
.wren_b( current_read_byte_write_enable_b ),
.data_b( current_read_byte_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( current_read_byte_out_a ),
.q_b( current_read_byte_out_b)
);
defparam current_read_byte.width_a = 32;
defparam current_read_byte.widthad_a = 1;
defparam current_read_byte.width_b = 32;
defparam current_read_byte.widthad_b = 1;
defparam current_read_byte.width_be_a = 1;
defparam current_read_byte.width_be_b = 1;
defparam current_read_byte.numwords_a = 1;
defparam current_read_byte.numwords_b = 1;
defparam current_read_byte.init_file = "current_read_byte.mif";
reg [0:0] p_jinfo_dc_dhuff_tbl_ml_address_a;
reg p_jinfo_dc_dhuff_tbl_ml_write_enable_a;
reg [31:0] p_jinfo_dc_dhuff_tbl_ml_in_a;
wire [31:0] p_jinfo_dc_dhuff_tbl_ml_out_a;
reg [0:0] p_jinfo_dc_dhuff_tbl_ml_address_b;
reg p_jinfo_dc_dhuff_tbl_ml_write_enable_b;
reg [31:0] p_jinfo_dc_dhuff_tbl_ml_in_b;
wire [31:0] p_jinfo_dc_dhuff_tbl_ml_out_b;
// @p_jinfo_dc_dhuff_tbl_ml = internal unnamed_addr global [2 x i32] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_dhuff_tbl_ml (
.clk( clk ),
.address_a( p_jinfo_dc_dhuff_tbl_ml_address_a ),
.wren_a( p_jinfo_dc_dhuff_tbl_ml_write_enable_a ),
.data_a( p_jinfo_dc_dhuff_tbl_ml_in_a ),
.address_b( p_jinfo_dc_dhuff_tbl_ml_address_b ),
.wren_b( p_jinfo_dc_dhuff_tbl_ml_write_enable_b ),
.data_b( p_jinfo_dc_dhuff_tbl_ml_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_dhuff_tbl_ml_out_a ),
.q_b( p_jinfo_dc_dhuff_tbl_ml_out_b)
);
defparam p_jinfo_dc_dhuff_tbl_ml.width_a = 32;
defparam p_jinfo_dc_dhuff_tbl_ml.widthad_a = 1;
defparam p_jinfo_dc_dhuff_tbl_ml.width_b = 32;
defparam p_jinfo_dc_dhuff_tbl_ml.widthad_b = 1;
defparam p_jinfo_dc_dhuff_tbl_ml.width_be_a = 1;
defparam p_jinfo_dc_dhuff_tbl_ml.width_be_b = 1;
defparam p_jinfo_dc_dhuff_tbl_ml.numwords_a = 2;
defparam p_jinfo_dc_dhuff_tbl_ml.numwords_b = 2;
defparam p_jinfo_dc_dhuff_tbl_ml.init_file = "p_jinfo_dc_dhuff_tbl_ml.mif";
reg [6:0] p_jinfo_dc_dhuff_tbl_maxcode_address_a;
reg p_jinfo_dc_dhuff_tbl_maxcode_write_enable_a;
reg [31:0] p_jinfo_dc_dhuff_tbl_maxcode_in_a;
wire [31:0] p_jinfo_dc_dhuff_tbl_maxcode_out_a;
reg [6:0] p_jinfo_dc_dhuff_tbl_maxcode_address_b;
reg p_jinfo_dc_dhuff_tbl_maxcode_write_enable_b;
reg [31:0] p_jinfo_dc_dhuff_tbl_maxcode_in_b;
wire [31:0] p_jinfo_dc_dhuff_tbl_maxcode_out_b;
// @p_jinfo_dc_dhuff_tbl_maxcode = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_dhuff_tbl_maxcode (
.clk( clk ),
.address_a( p_jinfo_dc_dhuff_tbl_maxcode_address_a ),
.wren_a( p_jinfo_dc_dhuff_tbl_maxcode_write_enable_a ),
.data_a( p_jinfo_dc_dhuff_tbl_maxcode_in_a ),
.address_b( p_jinfo_dc_dhuff_tbl_maxcode_address_b ),
.wren_b( p_jinfo_dc_dhuff_tbl_maxcode_write_enable_b ),
.data_b( p_jinfo_dc_dhuff_tbl_maxcode_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_dhuff_tbl_maxcode_out_a ),
.q_b( p_jinfo_dc_dhuff_tbl_maxcode_out_b)
);
defparam p_jinfo_dc_dhuff_tbl_maxcode.width_a = 32;
defparam p_jinfo_dc_dhuff_tbl_maxcode.widthad_a = 7;
defparam p_jinfo_dc_dhuff_tbl_maxcode.width_b = 32;
defparam p_jinfo_dc_dhuff_tbl_maxcode.widthad_b = 7;
defparam p_jinfo_dc_dhuff_tbl_maxcode.width_be_a = 1;
defparam p_jinfo_dc_dhuff_tbl_maxcode.width_be_b = 1;
defparam p_jinfo_dc_dhuff_tbl_maxcode.numwords_a = 72;
defparam p_jinfo_dc_dhuff_tbl_maxcode.numwords_b = 72;
defparam p_jinfo_dc_dhuff_tbl_maxcode.init_file = "p_jinfo_dc_dhuff_tbl_maxcode.mif";
reg [6:0] p_jinfo_dc_dhuff_tbl_mincode_address_a;
reg p_jinfo_dc_dhuff_tbl_mincode_write_enable_a;
reg [31:0] p_jinfo_dc_dhuff_tbl_mincode_in_a;
wire [31:0] p_jinfo_dc_dhuff_tbl_mincode_out_a;
reg [6:0] p_jinfo_dc_dhuff_tbl_mincode_address_b;
reg p_jinfo_dc_dhuff_tbl_mincode_write_enable_b;
reg [31:0] p_jinfo_dc_dhuff_tbl_mincode_in_b;
wire [31:0] p_jinfo_dc_dhuff_tbl_mincode_out_b;
// @p_jinfo_dc_dhuff_tbl_mincode = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_dhuff_tbl_mincode (
.clk( clk ),
.address_a( p_jinfo_dc_dhuff_tbl_mincode_address_a ),
.wren_a( p_jinfo_dc_dhuff_tbl_mincode_write_enable_a ),
.data_a( p_jinfo_dc_dhuff_tbl_mincode_in_a ),
.address_b( p_jinfo_dc_dhuff_tbl_mincode_address_b ),
.wren_b( p_jinfo_dc_dhuff_tbl_mincode_write_enable_b ),
.data_b( p_jinfo_dc_dhuff_tbl_mincode_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_dhuff_tbl_mincode_out_a ),
.q_b( p_jinfo_dc_dhuff_tbl_mincode_out_b)
);
defparam p_jinfo_dc_dhuff_tbl_mincode.width_a = 32;
defparam p_jinfo_dc_dhuff_tbl_mincode.widthad_a = 7;
defparam p_jinfo_dc_dhuff_tbl_mincode.width_b = 32;
defparam p_jinfo_dc_dhuff_tbl_mincode.widthad_b = 7;
defparam p_jinfo_dc_dhuff_tbl_mincode.width_be_a = 1;
defparam p_jinfo_dc_dhuff_tbl_mincode.width_be_b = 1;
defparam p_jinfo_dc_dhuff_tbl_mincode.numwords_a = 72;
defparam p_jinfo_dc_dhuff_tbl_mincode.numwords_b = 72;
defparam p_jinfo_dc_dhuff_tbl_mincode.init_file = "p_jinfo_dc_dhuff_tbl_mincode.mif";
reg [6:0] p_jinfo_dc_dhuff_tbl_valptr_address_a;
reg p_jinfo_dc_dhuff_tbl_valptr_write_enable_a;
reg [31:0] p_jinfo_dc_dhuff_tbl_valptr_in_a;
wire [31:0] p_jinfo_dc_dhuff_tbl_valptr_out_a;
reg [6:0] p_jinfo_dc_dhuff_tbl_valptr_address_b;
reg p_jinfo_dc_dhuff_tbl_valptr_write_enable_b;
reg [31:0] p_jinfo_dc_dhuff_tbl_valptr_in_b;
wire [31:0] p_jinfo_dc_dhuff_tbl_valptr_out_b;
// @p_jinfo_dc_dhuff_tbl_valptr = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_dhuff_tbl_valptr (
.clk( clk ),
.address_a( p_jinfo_dc_dhuff_tbl_valptr_address_a ),
.wren_a( p_jinfo_dc_dhuff_tbl_valptr_write_enable_a ),
.data_a( p_jinfo_dc_dhuff_tbl_valptr_in_a ),
.address_b( p_jinfo_dc_dhuff_tbl_valptr_address_b ),
.wren_b( p_jinfo_dc_dhuff_tbl_valptr_write_enable_b ),
.data_b( p_jinfo_dc_dhuff_tbl_valptr_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_dhuff_tbl_valptr_out_a ),
.q_b( p_jinfo_dc_dhuff_tbl_valptr_out_b)
);
defparam p_jinfo_dc_dhuff_tbl_valptr.width_a = 32;
defparam p_jinfo_dc_dhuff_tbl_valptr.widthad_a = 7;
defparam p_jinfo_dc_dhuff_tbl_valptr.width_b = 32;
defparam p_jinfo_dc_dhuff_tbl_valptr.widthad_b = 7;
defparam p_jinfo_dc_dhuff_tbl_valptr.width_be_a = 1;
defparam p_jinfo_dc_dhuff_tbl_valptr.width_be_b = 1;
defparam p_jinfo_dc_dhuff_tbl_valptr.numwords_a = 72;
defparam p_jinfo_dc_dhuff_tbl_valptr.numwords_b = 72;
defparam p_jinfo_dc_dhuff_tbl_valptr.init_file = "p_jinfo_dc_dhuff_tbl_valptr.mif";
reg [4:0] extend_mask_address_a;
reg extend_mask_write_enable_a;
reg [31:0] extend_mask_in_a;
wire [31:0] extend_mask_out_a;
reg [4:0] extend_mask_address_b;
reg extend_mask_write_enable_b;
reg [31:0] extend_mask_in_b;
wire [31:0] extend_mask_out_b;
// @extend_mask = internal unnamed_addr constant [20 x i32] [i32 -2, i32 -4, i32 -8, i32 -16, i32 -32, i32 -64, i32 -128, i32 -256, i32 -512, i32 -1024, i32 -2048, i32 -4096, i32 -8192, i32 -16384, i32 -32768, i32 -65536, i32 -131072, i32 -262144, i32 -524288, i32 -1048576], align 4
ram_two_ports extend_mask (
.clk( clk ),
.address_a( extend_mask_address_a ),
.wren_a( extend_mask_write_enable_a ),
.data_a( extend_mask_in_a ),
.address_b( extend_mask_address_b ),
.wren_b( extend_mask_write_enable_b ),
.data_b( extend_mask_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( extend_mask_out_a ),
.q_b( extend_mask_out_b)
);
defparam extend_mask.width_a = 32;
defparam extend_mask.widthad_a = 5;
defparam extend_mask.width_b = 32;
defparam extend_mask.widthad_b = 5;
defparam extend_mask.width_be_a = 1;
defparam extend_mask.width_be_b = 1;
defparam extend_mask.numwords_a = 20;
defparam extend_mask.numwords_b = 20;
defparam extend_mask.init_file = "extend_mask.mif";
reg [0:0] p_jinfo_ac_dhuff_tbl_ml_address_a;
reg p_jinfo_ac_dhuff_tbl_ml_write_enable_a;
reg [31:0] p_jinfo_ac_dhuff_tbl_ml_in_a;
wire [31:0] p_jinfo_ac_dhuff_tbl_ml_out_a;
reg [0:0] p_jinfo_ac_dhuff_tbl_ml_address_b;
reg p_jinfo_ac_dhuff_tbl_ml_write_enable_b;
reg [31:0] p_jinfo_ac_dhuff_tbl_ml_in_b;
wire [31:0] p_jinfo_ac_dhuff_tbl_ml_out_b;
// @p_jinfo_ac_dhuff_tbl_ml = internal unnamed_addr global [2 x i32] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_dhuff_tbl_ml (
.clk( clk ),
.address_a( p_jinfo_ac_dhuff_tbl_ml_address_a ),
.wren_a( p_jinfo_ac_dhuff_tbl_ml_write_enable_a ),
.data_a( p_jinfo_ac_dhuff_tbl_ml_in_a ),
.address_b( p_jinfo_ac_dhuff_tbl_ml_address_b ),
.wren_b( p_jinfo_ac_dhuff_tbl_ml_write_enable_b ),
.data_b( p_jinfo_ac_dhuff_tbl_ml_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_dhuff_tbl_ml_out_a ),
.q_b( p_jinfo_ac_dhuff_tbl_ml_out_b)
);
defparam p_jinfo_ac_dhuff_tbl_ml.width_a = 32;
defparam p_jinfo_ac_dhuff_tbl_ml.widthad_a = 1;
defparam p_jinfo_ac_dhuff_tbl_ml.width_b = 32;
defparam p_jinfo_ac_dhuff_tbl_ml.widthad_b = 1;
defparam p_jinfo_ac_dhuff_tbl_ml.width_be_a = 1;
defparam p_jinfo_ac_dhuff_tbl_ml.width_be_b = 1;
defparam p_jinfo_ac_dhuff_tbl_ml.numwords_a = 2;
defparam p_jinfo_ac_dhuff_tbl_ml.numwords_b = 2;
defparam p_jinfo_ac_dhuff_tbl_ml.init_file = "p_jinfo_ac_dhuff_tbl_ml.mif";
reg [6:0] p_jinfo_ac_dhuff_tbl_maxcode_address_a;
reg p_jinfo_ac_dhuff_tbl_maxcode_write_enable_a;
reg [31:0] p_jinfo_ac_dhuff_tbl_maxcode_in_a;
wire [31:0] p_jinfo_ac_dhuff_tbl_maxcode_out_a;
reg [6:0] p_jinfo_ac_dhuff_tbl_maxcode_address_b;
reg p_jinfo_ac_dhuff_tbl_maxcode_write_enable_b;
reg [31:0] p_jinfo_ac_dhuff_tbl_maxcode_in_b;
wire [31:0] p_jinfo_ac_dhuff_tbl_maxcode_out_b;
// @p_jinfo_ac_dhuff_tbl_maxcode = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_dhuff_tbl_maxcode (
.clk( clk ),
.address_a( p_jinfo_ac_dhuff_tbl_maxcode_address_a ),
.wren_a( p_jinfo_ac_dhuff_tbl_maxcode_write_enable_a ),
.data_a( p_jinfo_ac_dhuff_tbl_maxcode_in_a ),
.address_b( p_jinfo_ac_dhuff_tbl_maxcode_address_b ),
.wren_b( p_jinfo_ac_dhuff_tbl_maxcode_write_enable_b ),
.data_b( p_jinfo_ac_dhuff_tbl_maxcode_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_dhuff_tbl_maxcode_out_a ),
.q_b( p_jinfo_ac_dhuff_tbl_maxcode_out_b)
);
defparam p_jinfo_ac_dhuff_tbl_maxcode.width_a = 32;
defparam p_jinfo_ac_dhuff_tbl_maxcode.widthad_a = 7;
defparam p_jinfo_ac_dhuff_tbl_maxcode.width_b = 32;
defparam p_jinfo_ac_dhuff_tbl_maxcode.widthad_b = 7;
defparam p_jinfo_ac_dhuff_tbl_maxcode.width_be_a = 1;
defparam p_jinfo_ac_dhuff_tbl_maxcode.width_be_b = 1;
defparam p_jinfo_ac_dhuff_tbl_maxcode.numwords_a = 72;
defparam p_jinfo_ac_dhuff_tbl_maxcode.numwords_b = 72;
defparam p_jinfo_ac_dhuff_tbl_maxcode.init_file = "p_jinfo_ac_dhuff_tbl_maxcode.mif";
reg [6:0] p_jinfo_ac_dhuff_tbl_mincode_address_a;
reg p_jinfo_ac_dhuff_tbl_mincode_write_enable_a;
reg [31:0] p_jinfo_ac_dhuff_tbl_mincode_in_a;
wire [31:0] p_jinfo_ac_dhuff_tbl_mincode_out_a;
reg [6:0] p_jinfo_ac_dhuff_tbl_mincode_address_b;
reg p_jinfo_ac_dhuff_tbl_mincode_write_enable_b;
reg [31:0] p_jinfo_ac_dhuff_tbl_mincode_in_b;
wire [31:0] p_jinfo_ac_dhuff_tbl_mincode_out_b;
// @p_jinfo_ac_dhuff_tbl_mincode = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_dhuff_tbl_mincode (
.clk( clk ),
.address_a( p_jinfo_ac_dhuff_tbl_mincode_address_a ),
.wren_a( p_jinfo_ac_dhuff_tbl_mincode_write_enable_a ),
.data_a( p_jinfo_ac_dhuff_tbl_mincode_in_a ),
.address_b( p_jinfo_ac_dhuff_tbl_mincode_address_b ),
.wren_b( p_jinfo_ac_dhuff_tbl_mincode_write_enable_b ),
.data_b( p_jinfo_ac_dhuff_tbl_mincode_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_dhuff_tbl_mincode_out_a ),
.q_b( p_jinfo_ac_dhuff_tbl_mincode_out_b)
);
defparam p_jinfo_ac_dhuff_tbl_mincode.width_a = 32;
defparam p_jinfo_ac_dhuff_tbl_mincode.widthad_a = 7;
defparam p_jinfo_ac_dhuff_tbl_mincode.width_b = 32;
defparam p_jinfo_ac_dhuff_tbl_mincode.widthad_b = 7;
defparam p_jinfo_ac_dhuff_tbl_mincode.width_be_a = 1;
defparam p_jinfo_ac_dhuff_tbl_mincode.width_be_b = 1;
defparam p_jinfo_ac_dhuff_tbl_mincode.numwords_a = 72;
defparam p_jinfo_ac_dhuff_tbl_mincode.numwords_b = 72;
defparam p_jinfo_ac_dhuff_tbl_mincode.init_file = "p_jinfo_ac_dhuff_tbl_mincode.mif";
reg [6:0] p_jinfo_ac_dhuff_tbl_valptr_address_a;
reg p_jinfo_ac_dhuff_tbl_valptr_write_enable_a;
reg [31:0] p_jinfo_ac_dhuff_tbl_valptr_in_a;
wire [31:0] p_jinfo_ac_dhuff_tbl_valptr_out_a;
reg [6:0] p_jinfo_ac_dhuff_tbl_valptr_address_b;
reg p_jinfo_ac_dhuff_tbl_valptr_write_enable_b;
reg [31:0] p_jinfo_ac_dhuff_tbl_valptr_in_b;
wire [31:0] p_jinfo_ac_dhuff_tbl_valptr_out_b;
// @p_jinfo_ac_dhuff_tbl_valptr = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_dhuff_tbl_valptr (
.clk( clk ),
.address_a( p_jinfo_ac_dhuff_tbl_valptr_address_a ),
.wren_a( p_jinfo_ac_dhuff_tbl_valptr_write_enable_a ),
.data_a( p_jinfo_ac_dhuff_tbl_valptr_in_a ),
.address_b( p_jinfo_ac_dhuff_tbl_valptr_address_b ),
.wren_b( p_jinfo_ac_dhuff_tbl_valptr_write_enable_b ),
.data_b( p_jinfo_ac_dhuff_tbl_valptr_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_dhuff_tbl_valptr_out_a ),
.q_b( p_jinfo_ac_dhuff_tbl_valptr_out_b)
);
defparam p_jinfo_ac_dhuff_tbl_valptr.width_a = 32;
defparam p_jinfo_ac_dhuff_tbl_valptr.widthad_a = 7;
defparam p_jinfo_ac_dhuff_tbl_valptr.width_b = 32;
defparam p_jinfo_ac_dhuff_tbl_valptr.widthad_b = 7;
defparam p_jinfo_ac_dhuff_tbl_valptr.width_be_a = 1;
defparam p_jinfo_ac_dhuff_tbl_valptr.width_be_b = 1;
defparam p_jinfo_ac_dhuff_tbl_valptr.numwords_a = 72;
defparam p_jinfo_ac_dhuff_tbl_valptr.numwords_b = 72;
defparam p_jinfo_ac_dhuff_tbl_valptr.init_file = "p_jinfo_ac_dhuff_tbl_valptr.mif";
reg [1:0] OutData_comp_vpos_address_a;
reg OutData_comp_vpos_write_enable_a;
reg [31:0] OutData_comp_vpos_in_a;
wire [31:0] OutData_comp_vpos_out_a;
reg [1:0] OutData_comp_vpos_address_b;
reg OutData_comp_vpos_write_enable_b;
reg [31:0] OutData_comp_vpos_in_b;
wire [31:0] OutData_comp_vpos_out_b;
// @OutData_comp_vpos = internal global [3 x i32] zeroinitializer, align 4
ram_two_ports OutData_comp_vpos (
.clk( clk ),
.address_a( OutData_comp_vpos_address_a ),
.wren_a( OutData_comp_vpos_write_enable_a ),
.data_a( OutData_comp_vpos_in_a ),
.address_b( OutData_comp_vpos_address_b ),
.wren_b( OutData_comp_vpos_write_enable_b ),
.data_b( OutData_comp_vpos_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( OutData_comp_vpos_out_a ),
.q_b( OutData_comp_vpos_out_b)
);
defparam OutData_comp_vpos.width_a = 32;
defparam OutData_comp_vpos.widthad_a = 2;
defparam OutData_comp_vpos.width_b = 32;
defparam OutData_comp_vpos.widthad_b = 2;
defparam OutData_comp_vpos.width_be_a = 1;
defparam OutData_comp_vpos.width_be_b = 1;
defparam OutData_comp_vpos.numwords_a = 3;
defparam OutData_comp_vpos.numwords_b = 3;
defparam OutData_comp_vpos.init_file = "OutData_comp_vpos.mif";
reg [1:0] OutData_comp_hpos_address_a;
reg OutData_comp_hpos_write_enable_a;
reg [31:0] OutData_comp_hpos_in_a;
wire [31:0] OutData_comp_hpos_out_a;
reg [1:0] OutData_comp_hpos_address_b;
reg OutData_comp_hpos_write_enable_b;
reg [31:0] OutData_comp_hpos_in_b;
wire [31:0] OutData_comp_hpos_out_b;
// @OutData_comp_hpos = internal global [3 x i32] zeroinitializer, align 4
ram_two_ports OutData_comp_hpos (
.clk( clk ),
.address_a( OutData_comp_hpos_address_a ),
.wren_a( OutData_comp_hpos_write_enable_a ),
.data_a( OutData_comp_hpos_in_a ),
.address_b( OutData_comp_hpos_address_b ),
.wren_b( OutData_comp_hpos_write_enable_b ),
.data_b( OutData_comp_hpos_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( OutData_comp_hpos_out_a ),
.q_b( OutData_comp_hpos_out_b)
);
defparam OutData_comp_hpos.width_a = 32;
defparam OutData_comp_hpos.widthad_a = 2;
defparam OutData_comp_hpos.width_b = 32;
defparam OutData_comp_hpos.widthad_b = 2;
defparam OutData_comp_hpos.width_be_a = 1;
defparam OutData_comp_hpos.width_be_b = 1;
defparam OutData_comp_hpos.numwords_a = 3;
defparam OutData_comp_hpos.numwords_b = 3;
defparam OutData_comp_hpos.init_file = "OutData_comp_hpos.mif";
reg [12:0] JpegFileBuf_address_a;
reg JpegFileBuf_write_enable_a;
reg [7:0] JpegFileBuf_in_a;
wire [7:0] JpegFileBuf_out_a;
reg [12:0] JpegFileBuf_address_b;
reg JpegFileBuf_write_enable_b;
reg [7:0] JpegFileBuf_in_b;
wire [7:0] JpegFileBuf_out_b;
// @JpegFileBuf = internal global [5310 x i8] zeroinitializer, align 1
ram_two_ports JpegFileBuf (
.clk( clk ),
.address_a( JpegFileBuf_address_a ),
.wren_a( JpegFileBuf_write_enable_a ),
.data_a( JpegFileBuf_in_a ),
.address_b( JpegFileBuf_address_b ),
.wren_b( JpegFileBuf_write_enable_b ),
.data_b( JpegFileBuf_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( JpegFileBuf_out_a ),
.q_b( JpegFileBuf_out_b)
);
defparam JpegFileBuf.width_a = 8;
defparam JpegFileBuf.widthad_a = 13;
defparam JpegFileBuf.width_b = 8;
defparam JpegFileBuf.widthad_b = 13;
defparam JpegFileBuf.width_be_a = 1;
defparam JpegFileBuf.width_be_b = 1;
defparam JpegFileBuf.numwords_a = 5310;
defparam JpegFileBuf.numwords_b = 5310;
defparam JpegFileBuf.init_file = "JpegFileBuf.mif";
reg [5:0] decode_block_0_QuantBuff_address_a;
reg decode_block_0_QuantBuff_write_enable_a;
reg [31:0] decode_block_0_QuantBuff_in_a;
wire [31:0] decode_block_0_QuantBuff_out_a;
reg [5:0] decode_block_0_QuantBuff_address_b;
reg decode_block_0_QuantBuff_write_enable_b;
reg [31:0] decode_block_0_QuantBuff_in_b;
wire [31:0] decode_block_0_QuantBuff_out_b;
// %QuantBuff = alloca [64 x i32], align 4
ram_two_ports decode_block_0_QuantBuff (
.clk( clk ),
.address_a( decode_block_0_QuantBuff_address_a ),
.wren_a( decode_block_0_QuantBuff_write_enable_a ),
.data_a( decode_block_0_QuantBuff_in_a ),
.address_b( decode_block_0_QuantBuff_address_b ),
.wren_b( decode_block_0_QuantBuff_write_enable_b ),
.data_b( decode_block_0_QuantBuff_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( decode_block_0_QuantBuff_out_a ),
.q_b( decode_block_0_QuantBuff_out_b)
);
defparam decode_block_0_QuantBuff.width_a = 32;
defparam decode_block_0_QuantBuff.widthad_a = 6;
defparam decode_block_0_QuantBuff.width_b = 32;
defparam decode_block_0_QuantBuff.widthad_b = 6;
defparam decode_block_0_QuantBuff.width_be_a = 1;
defparam decode_block_0_QuantBuff.width_be_b = 1;
defparam decode_block_0_QuantBuff.numwords_a = 64;
defparam decode_block_0_QuantBuff.numwords_b = 64;
reg [8:0] huff_make_dhuff_tb_0_huffsize_address_a;
reg huff_make_dhuff_tb_0_huffsize_write_enable_a;
reg [31:0] huff_make_dhuff_tb_0_huffsize_in_a;
wire [31:0] huff_make_dhuff_tb_0_huffsize_out_a;
reg [8:0] huff_make_dhuff_tb_0_huffsize_address_b;
reg huff_make_dhuff_tb_0_huffsize_write_enable_b;
reg [31:0] huff_make_dhuff_tb_0_huffsize_in_b;
wire [31:0] huff_make_dhuff_tb_0_huffsize_out_b;
// %huffsize = alloca [257 x i32], align 4
ram_two_ports huff_make_dhuff_tb_0_huffsize (
.clk( clk ),
.address_a( huff_make_dhuff_tb_0_huffsize_address_a ),
.wren_a( huff_make_dhuff_tb_0_huffsize_write_enable_a ),
.data_a( huff_make_dhuff_tb_0_huffsize_in_a ),
.address_b( huff_make_dhuff_tb_0_huffsize_address_b ),
.wren_b( huff_make_dhuff_tb_0_huffsize_write_enable_b ),
.data_b( huff_make_dhuff_tb_0_huffsize_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( huff_make_dhuff_tb_0_huffsize_out_a ),
.q_b( huff_make_dhuff_tb_0_huffsize_out_b)
);
defparam huff_make_dhuff_tb_0_huffsize.width_a = 32;
defparam huff_make_dhuff_tb_0_huffsize.widthad_a = 9;
defparam huff_make_dhuff_tb_0_huffsize.width_b = 32;
defparam huff_make_dhuff_tb_0_huffsize.widthad_b = 9;
defparam huff_make_dhuff_tb_0_huffsize.width_be_a = 1;
defparam huff_make_dhuff_tb_0_huffsize.width_be_b = 1;
defparam huff_make_dhuff_tb_0_huffsize.numwords_a = 257;
defparam huff_make_dhuff_tb_0_huffsize.numwords_b = 257;
reg [8:0] huff_make_dhuff_tb_0_huffcode_address_a;
reg huff_make_dhuff_tb_0_huffcode_write_enable_a;
reg [31:0] huff_make_dhuff_tb_0_huffcode_in_a;
wire [31:0] huff_make_dhuff_tb_0_huffcode_out_a;
reg [8:0] huff_make_dhuff_tb_0_huffcode_address_b;
reg huff_make_dhuff_tb_0_huffcode_write_enable_b;
reg [31:0] huff_make_dhuff_tb_0_huffcode_in_b;
wire [31:0] huff_make_dhuff_tb_0_huffcode_out_b;
// %huffcode = alloca [257 x i32], align 4
ram_two_ports huff_make_dhuff_tb_0_huffcode (
.clk( clk ),
.address_a( huff_make_dhuff_tb_0_huffcode_address_a ),
.wren_a( huff_make_dhuff_tb_0_huffcode_write_enable_a ),
.data_a( huff_make_dhuff_tb_0_huffcode_in_a ),
.address_b( huff_make_dhuff_tb_0_huffcode_address_b ),
.wren_b( huff_make_dhuff_tb_0_huffcode_write_enable_b ),
.data_b( huff_make_dhuff_tb_0_huffcode_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( huff_make_dhuff_tb_0_huffcode_out_a ),
.q_b( huff_make_dhuff_tb_0_huffcode_out_b)
);
defparam huff_make_dhuff_tb_0_huffcode.width_a = 32;
defparam huff_make_dhuff_tb_0_huffcode.widthad_a = 9;
defparam huff_make_dhuff_tb_0_huffcode.width_b = 32;
defparam huff_make_dhuff_tb_0_huffcode.widthad_b = 9;
defparam huff_make_dhuff_tb_0_huffcode.width_be_a = 1;
defparam huff_make_dhuff_tb_0_huffcode.width_be_b = 1;
defparam huff_make_dhuff_tb_0_huffcode.numwords_a = 257;
defparam huff_make_dhuff_tb_0_huffcode.numwords_b = 257;
reg [7:0] main_0_HuffBuff_i_i_address_a;
reg main_0_HuffBuff_i_i_write_enable_a;
reg [31:0] main_0_HuffBuff_i_i_in_a;
wire [31:0] main_0_HuffBuff_i_i_out_a;
reg [7:0] main_0_HuffBuff_i_i_address_b;
reg main_0_HuffBuff_i_i_write_enable_b;
reg [31:0] main_0_HuffBuff_i_i_in_b;
wire [31:0] main_0_HuffBuff_i_i_out_b;
// %HuffBuff.i.i = alloca [3 x [64 x i32]], align 4
ram_two_ports main_0_HuffBuff_i_i (
.clk( clk ),
.address_a( main_0_HuffBuff_i_i_address_a ),
.wren_a( main_0_HuffBuff_i_i_write_enable_a ),
.data_a( main_0_HuffBuff_i_i_in_a ),
.address_b( main_0_HuffBuff_i_i_address_b ),
.wren_b( main_0_HuffBuff_i_i_write_enable_b ),
.data_b( main_0_HuffBuff_i_i_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( main_0_HuffBuff_i_i_out_a ),
.q_b( main_0_HuffBuff_i_i_out_b)
);
defparam main_0_HuffBuff_i_i.width_a = 32;
defparam main_0_HuffBuff_i_i.widthad_a = 8;
defparam main_0_HuffBuff_i_i.width_b = 32;
defparam main_0_HuffBuff_i_i.widthad_b = 8;
defparam main_0_HuffBuff_i_i.width_be_a = 1;
defparam main_0_HuffBuff_i_i.width_be_b = 1;
defparam main_0_HuffBuff_i_i.numwords_a = 192;
defparam main_0_HuffBuff_i_i.numwords_b = 192;
reg [8:0] main_0_IDCTBuff_i_i_address_a;
reg main_0_IDCTBuff_i_i_write_enable_a;
reg [31:0] main_0_IDCTBuff_i_i_in_a;
wire [31:0] main_0_IDCTBuff_i_i_out_a;
reg [8:0] main_0_IDCTBuff_i_i_address_b;
reg main_0_IDCTBuff_i_i_write_enable_b;
reg [31:0] main_0_IDCTBuff_i_i_in_b;
wire [31:0] main_0_IDCTBuff_i_i_out_b;
// %IDCTBuff.i.i = alloca [6 x [64 x i32]], align 4
ram_two_ports main_0_IDCTBuff_i_i (
.clk( clk ),
.address_a( main_0_IDCTBuff_i_i_address_a ),
.wren_a( main_0_IDCTBuff_i_i_write_enable_a ),
.data_a( main_0_IDCTBuff_i_i_in_a ),
.address_b( main_0_IDCTBuff_i_i_address_b ),
.wren_b( main_0_IDCTBuff_i_i_write_enable_b ),
.data_b( main_0_IDCTBuff_i_i_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( main_0_IDCTBuff_i_i_out_a ),
.q_b( main_0_IDCTBuff_i_i_out_b)
);
defparam main_0_IDCTBuff_i_i.width_a = 32;
defparam main_0_IDCTBuff_i_i.widthad_a = 9;
defparam main_0_IDCTBuff_i_i.width_b = 32;
defparam main_0_IDCTBuff_i_i.widthad_b = 9;
defparam main_0_IDCTBuff_i_i.width_be_a = 1;
defparam main_0_IDCTBuff_i_i.width_be_b = 1;
defparam main_0_IDCTBuff_i_i.numwords_a = 384;
defparam main_0_IDCTBuff_i_i.numwords_b = 384;
wire [`MEMORY_CONTROLLER_TAG_SIZE-1:0] tag_a = memory_controller_address_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:`MEMORY_CONTROLLER_ADDR_SIZE-`MEMORY_CONTROLLER_TAG_SIZE];
wire [`MEMORY_CONTROLLER_TAG_SIZE-1:0] tag_b = memory_controller_address_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:`MEMORY_CONTROLLER_ADDR_SIZE-`MEMORY_CONTROLLER_TAG_SIZE];
reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag_a;
reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag_b;
reg [2:0] prevAddr_a;
reg [2:0] prevAddr_b;
reg [1:0] prevSize_a;
reg [1:0] prevSize_b;
reg [2:0] prevSize_a_and;
reg [2:0] prevSize_b_and;
always @(posedge clk)
begin
prevTag_a <= tag_a;
prevTag_b <= tag_b;
prevAddr_a <= memory_controller_address_a[2:0];
prevAddr_b <= memory_controller_address_b[2:0];
prevSize_a <= memory_controller_size_a;
prevSize_b <= memory_controller_size_b;
end
reg [2:0] select_not_struct_a;
reg [2:0] select_not_struct_b;
wire select_hana_jpg_a = (tag_a ==`TAG_g_hana_jpg);
wire select_hana_jpg_b = (tag_b ==`TAG_g_hana_jpg);
reg select_hana_jpg_reg_a;
reg select_hana_jpg_reg_b;
wire [7:0] memory_controller_hana_jpg_out_a = {8{ select_hana_jpg_reg_a}} & hana_jpg_out_a;
wire [7:0] memory_controller_hana_jpg_out_b = {8{ select_hana_jpg_reg_b}} & hana_jpg_out_b;
wire select_hana_bmp_a = (tag_a ==`TAG_g_hana_bmp);
wire select_hana_bmp_b = (tag_b ==`TAG_g_hana_bmp);
reg select_hana_bmp_reg_a;
reg select_hana_bmp_reg_b;
wire [7:0] memory_controller_hana_bmp_out_a = {8{ select_hana_bmp_reg_a}} & hana_bmp_out_a;
wire [7:0] memory_controller_hana_bmp_out_b = {8{ select_hana_bmp_reg_b}} & hana_bmp_out_b;
wire select_out_unread_marker_a = (tag_a ==`TAG_g_out_unread_marker);
wire select_out_unread_marker_b = (tag_b ==`TAG_g_out_unread_marker);
reg select_out_unread_marker_reg_a;
reg select_out_unread_marker_reg_b;
wire [31:0] memory_controller_out_unread_marker_out_a = {32{ select_out_unread_marker_reg_a}} & out_unread_marker_out_a;
wire [31:0] memory_controller_out_unread_marker_out_b = {32{ select_out_unread_marker_reg_b}} & out_unread_marker_out_b;
wire select_out_index_get_sof_a = (tag_a ==`TAG_g_out_index_get_sof);
wire select_out_index_get_sof_b = (tag_b ==`TAG_g_out_index_get_sof);
reg select_out_index_get_sof_reg_a;
reg select_out_index_get_sof_reg_b;
wire [31:0] memory_controller_out_index_get_sof_out_a = {32{ select_out_index_get_sof_reg_a}} & out_index_get_sof_out_a;
wire [31:0] memory_controller_out_index_get_sof_out_b = {32{ select_out_index_get_sof_reg_b}} & out_index_get_sof_out_b;
wire select_out_v_samp_factor_get_sof_a = (tag_a ==`TAG_g_out_v_samp_factor_get_sof);
wire select_out_v_samp_factor_get_sof_b = (tag_b ==`TAG_g_out_v_samp_factor_get_sof);
reg select_out_v_samp_factor_get_sof_reg_a;
reg select_out_v_samp_factor_get_sof_reg_b;
wire [31:0] memory_controller_out_v_samp_factor_get_sof_out_a = {32{ select_out_v_samp_factor_get_sof_reg_a}} & out_v_samp_factor_get_sof_out_a;
wire [31:0] memory_controller_out_v_samp_factor_get_sof_out_b = {32{ select_out_v_samp_factor_get_sof_reg_b}} & out_v_samp_factor_get_sof_out_b;
wire select_out_comp_id_get_sos_a = (tag_a ==`TAG_g_out_comp_id_get_sos);
wire select_out_comp_id_get_sos_b = (tag_b ==`TAG_g_out_comp_id_get_sos);
reg select_out_comp_id_get_sos_reg_a;
reg select_out_comp_id_get_sos_reg_b;
wire [31:0] memory_controller_out_comp_id_get_sos_out_a = {32{ select_out_comp_id_get_sos_reg_a}} & out_comp_id_get_sos_out_a;
wire [31:0] memory_controller_out_comp_id_get_sos_out_b = {32{ select_out_comp_id_get_sos_reg_b}} & out_comp_id_get_sos_out_b;
wire select_out_ac_tbl_no_get_sos_a = (tag_a ==`TAG_g_out_ac_tbl_no_get_sos);
wire select_out_ac_tbl_no_get_sos_b = (tag_b ==`TAG_g_out_ac_tbl_no_get_sos);
reg select_out_ac_tbl_no_get_sos_reg_a;
reg select_out_ac_tbl_no_get_sos_reg_b;
wire [31:0] memory_controller_out_ac_tbl_no_get_sos_out_a = {32{ select_out_ac_tbl_no_get_sos_reg_a}} & out_ac_tbl_no_get_sos_out_a;
wire [31:0] memory_controller_out_ac_tbl_no_get_sos_out_b = {32{ select_out_ac_tbl_no_get_sos_reg_b}} & out_ac_tbl_no_get_sos_out_b;
wire select_out_length_get_dht_a = (tag_a ==`TAG_g_out_length_get_dht);
wire select_out_length_get_dht_b = (tag_b ==`TAG_g_out_length_get_dht);
reg select_out_length_get_dht_reg_a;
reg select_out_length_get_dht_reg_b;
wire [31:0] memory_controller_out_length_get_dht_out_a = {32{ select_out_length_get_dht_reg_a}} & out_length_get_dht_out_a;
wire [31:0] memory_controller_out_length_get_dht_out_b = {32{ select_out_length_get_dht_reg_b}} & out_length_get_dht_out_b;
wire select_out_index_get_dht_a = (tag_a ==`TAG_g_out_index_get_dht);
wire select_out_index_get_dht_b = (tag_b ==`TAG_g_out_index_get_dht);
reg select_out_index_get_dht_reg_a;
reg select_out_index_get_dht_reg_b;
wire [31:0] memory_controller_out_index_get_dht_out_a = {32{ select_out_index_get_dht_reg_a}} & out_index_get_dht_out_a;
wire [31:0] memory_controller_out_index_get_dht_out_b = {32{ select_out_index_get_dht_reg_b}} & out_index_get_dht_out_b;
wire select_out_count_get_dht_a = (tag_a ==`TAG_g_out_count_get_dht);
wire select_out_count_get_dht_b = (tag_b ==`TAG_g_out_count_get_dht);
reg select_out_count_get_dht_reg_a;
reg select_out_count_get_dht_reg_b;
wire [31:0] memory_controller_out_count_get_dht_out_a = {32{ select_out_count_get_dht_reg_a}} & out_count_get_dht_out_a;
wire [31:0] memory_controller_out_count_get_dht_out_b = {32{ select_out_count_get_dht_reg_b}} & out_count_get_dht_out_b;
wire select_out_length_get_dqt_a = (tag_a ==`TAG_g_out_length_get_dqt);
wire select_out_length_get_dqt_b = (tag_b ==`TAG_g_out_length_get_dqt);
reg select_out_length_get_dqt_reg_a;
reg select_out_length_get_dqt_reg_b;
wire [31:0] memory_controller_out_length_get_dqt_out_a = {32{ select_out_length_get_dqt_reg_a}} & out_length_get_dqt_out_a;
wire [31:0] memory_controller_out_length_get_dqt_out_b = {32{ select_out_length_get_dqt_reg_b}} & out_length_get_dqt_out_b;
wire select_out_prec_get_dht_a = (tag_a ==`TAG_g_out_prec_get_dht);
wire select_out_prec_get_dht_b = (tag_b ==`TAG_g_out_prec_get_dht);
reg select_out_prec_get_dht_reg_a;
reg select_out_prec_get_dht_reg_b;
wire [31:0] memory_controller_out_prec_get_dht_out_a = {32{ select_out_prec_get_dht_reg_a}} & out_prec_get_dht_out_a;
wire [31:0] memory_controller_out_prec_get_dht_out_b = {32{ select_out_prec_get_dht_reg_b}} & out_prec_get_dht_out_b;
wire select_out_num_get_dht_a = (tag_a ==`TAG_g_out_num_get_dht);
wire select_out_num_get_dht_b = (tag_b ==`TAG_g_out_num_get_dht);
reg select_out_num_get_dht_reg_a;
reg select_out_num_get_dht_reg_b;
wire [31:0] memory_controller_out_num_get_dht_out_a = {32{ select_out_num_get_dht_reg_a}} & out_num_get_dht_out_a;
wire [31:0] memory_controller_out_num_get_dht_out_b = {32{ select_out_num_get_dht_reg_b}} & out_num_get_dht_out_b;
wire select_izigzag_index_a = (tag_a ==`TAG_g_izigzag_index);
wire select_izigzag_index_b = (tag_b ==`TAG_g_izigzag_index);
reg select_izigzag_index_reg_a;
reg select_izigzag_index_reg_b;
wire [31:0] memory_controller_izigzag_index_out_a = {32{ select_izigzag_index_reg_a}} & izigzag_index_out_a;
wire [31:0] memory_controller_izigzag_index_out_b = {32{ select_izigzag_index_reg_b}} & izigzag_index_out_b;
wire select_main_result_a = (tag_a ==`TAG_g_main_result);
wire select_main_result_b = (tag_b ==`TAG_g_main_result);
reg select_main_result_reg_a;
reg select_main_result_reg_b;
wire [31:0] memory_controller_main_result_out_a = {32{ select_main_result_reg_a}} & main_result_out_a;
wire [31:0] memory_controller_main_result_out_b = {32{ select_main_result_reg_b}} & main_result_out_b;
wire select_p_jinfo_image_height_a = (tag_a ==`TAG_g_p_jinfo_image_height);
wire select_p_jinfo_image_height_b = (tag_b ==`TAG_g_p_jinfo_image_height);
reg select_p_jinfo_image_height_reg_a;
reg select_p_jinfo_image_height_reg_b;
wire [15:0] memory_controller_p_jinfo_image_height_out_a = {16{ select_p_jinfo_image_height_reg_a}} & p_jinfo_image_height_out_a;
wire [15:0] memory_controller_p_jinfo_image_height_out_b = {16{ select_p_jinfo_image_height_reg_b}} & p_jinfo_image_height_out_b;
wire select_p_jinfo_image_width_a = (tag_a ==`TAG_g_p_jinfo_image_width);
wire select_p_jinfo_image_width_b = (tag_b ==`TAG_g_p_jinfo_image_width);
reg select_p_jinfo_image_width_reg_a;
reg select_p_jinfo_image_width_reg_b;
wire [15:0] memory_controller_p_jinfo_image_width_out_a = {16{ select_p_jinfo_image_width_reg_a}} & p_jinfo_image_width_out_a;
wire [15:0] memory_controller_p_jinfo_image_width_out_b = {16{ select_p_jinfo_image_width_reg_b}} & p_jinfo_image_width_out_b;
wire select_p_jinfo_comps_info_index_a = (tag_a ==`TAG_g_p_jinfo_comps_info_index);
wire select_p_jinfo_comps_info_index_b = (tag_b ==`TAG_g_p_jinfo_comps_info_index);
reg select_p_jinfo_comps_info_index_reg_a;
reg select_p_jinfo_comps_info_index_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_index_out_a = {8{ select_p_jinfo_comps_info_index_reg_a}} & p_jinfo_comps_info_index_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_index_out_b = {8{ select_p_jinfo_comps_info_index_reg_b}} & p_jinfo_comps_info_index_out_b;
wire select_p_jinfo_comps_info_id_a = (tag_a ==`TAG_g_p_jinfo_comps_info_id);
wire select_p_jinfo_comps_info_id_b = (tag_b ==`TAG_g_p_jinfo_comps_info_id);
reg select_p_jinfo_comps_info_id_reg_a;
reg select_p_jinfo_comps_info_id_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_id_out_a = {8{ select_p_jinfo_comps_info_id_reg_a}} & p_jinfo_comps_info_id_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_id_out_b = {8{ select_p_jinfo_comps_info_id_reg_b}} & p_jinfo_comps_info_id_out_b;
wire select_p_jinfo_comps_info_h_samp_factor_a = (tag_a ==`TAG_g_p_jinfo_comps_info_h_samp_factor);
wire select_p_jinfo_comps_info_h_samp_factor_b = (tag_b ==`TAG_g_p_jinfo_comps_info_h_samp_factor);
reg select_p_jinfo_comps_info_h_samp_factor_reg_a;
reg select_p_jinfo_comps_info_h_samp_factor_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_h_samp_factor_out_a = {8{ select_p_jinfo_comps_info_h_samp_factor_reg_a}} & p_jinfo_comps_info_h_samp_factor_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_h_samp_factor_out_b = {8{ select_p_jinfo_comps_info_h_samp_factor_reg_b}} & p_jinfo_comps_info_h_samp_factor_out_b;
wire select_p_jinfo_comps_info_v_samp_factor_a = (tag_a ==`TAG_g_p_jinfo_comps_info_v_samp_factor);
wire select_p_jinfo_comps_info_v_samp_factor_b = (tag_b ==`TAG_g_p_jinfo_comps_info_v_samp_factor);
reg select_p_jinfo_comps_info_v_samp_factor_reg_a;
reg select_p_jinfo_comps_info_v_samp_factor_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_v_samp_factor_out_a = {8{ select_p_jinfo_comps_info_v_samp_factor_reg_a}} & p_jinfo_comps_info_v_samp_factor_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_v_samp_factor_out_b = {8{ select_p_jinfo_comps_info_v_samp_factor_reg_b}} & p_jinfo_comps_info_v_samp_factor_out_b;
wire select_p_jinfo_comps_info_quant_tbl_no_a = (tag_a ==`TAG_g_p_jinfo_comps_info_quant_tbl_no);
wire select_p_jinfo_comps_info_quant_tbl_no_b = (tag_b ==`TAG_g_p_jinfo_comps_info_quant_tbl_no);
reg select_p_jinfo_comps_info_quant_tbl_no_reg_a;
reg select_p_jinfo_comps_info_quant_tbl_no_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_quant_tbl_no_out_a = {8{ select_p_jinfo_comps_info_quant_tbl_no_reg_a}} & p_jinfo_comps_info_quant_tbl_no_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_quant_tbl_no_out_b = {8{ select_p_jinfo_comps_info_quant_tbl_no_reg_b}} & p_jinfo_comps_info_quant_tbl_no_out_b;
wire select_p_jinfo_comps_info_dc_tbl_no_a = (tag_a ==`TAG_g_p_jinfo_comps_info_dc_tbl_no);
wire select_p_jinfo_comps_info_dc_tbl_no_b = (tag_b ==`TAG_g_p_jinfo_comps_info_dc_tbl_no);
reg select_p_jinfo_comps_info_dc_tbl_no_reg_a;
reg select_p_jinfo_comps_info_dc_tbl_no_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_dc_tbl_no_out_a = {8{ select_p_jinfo_comps_info_dc_tbl_no_reg_a}} & p_jinfo_comps_info_dc_tbl_no_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_dc_tbl_no_out_b = {8{ select_p_jinfo_comps_info_dc_tbl_no_reg_b}} & p_jinfo_comps_info_dc_tbl_no_out_b;
wire select_p_jinfo_comps_info_ac_tbl_no_a = (tag_a ==`TAG_g_p_jinfo_comps_info_ac_tbl_no);
wire select_p_jinfo_comps_info_ac_tbl_no_b = (tag_b ==`TAG_g_p_jinfo_comps_info_ac_tbl_no);
reg select_p_jinfo_comps_info_ac_tbl_no_reg_a;
reg select_p_jinfo_comps_info_ac_tbl_no_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_ac_tbl_no_out_a = {8{ select_p_jinfo_comps_info_ac_tbl_no_reg_a}} & p_jinfo_comps_info_ac_tbl_no_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_ac_tbl_no_out_b = {8{ select_p_jinfo_comps_info_ac_tbl_no_reg_b}} & p_jinfo_comps_info_ac_tbl_no_out_b;
wire select_p_jinfo_ac_xhuff_tbl_bits_a = (tag_a ==`TAG_g_p_jinfo_ac_xhuff_tbl_bits);
wire select_p_jinfo_ac_xhuff_tbl_bits_b = (tag_b ==`TAG_g_p_jinfo_ac_xhuff_tbl_bits);
reg select_p_jinfo_ac_xhuff_tbl_bits_reg_a;
reg select_p_jinfo_ac_xhuff_tbl_bits_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_xhuff_tbl_bits_out_a = {32{ select_p_jinfo_ac_xhuff_tbl_bits_reg_a}} & p_jinfo_ac_xhuff_tbl_bits_out_a;
wire [31:0] memory_controller_p_jinfo_ac_xhuff_tbl_bits_out_b = {32{ select_p_jinfo_ac_xhuff_tbl_bits_reg_b}} & p_jinfo_ac_xhuff_tbl_bits_out_b;
wire select_p_jinfo_ac_xhuff_tbl_huffval_a = (tag_a ==`TAG_g_p_jinfo_ac_xhuff_tbl_huffval);
wire select_p_jinfo_ac_xhuff_tbl_huffval_b = (tag_b ==`TAG_g_p_jinfo_ac_xhuff_tbl_huffval);
reg select_p_jinfo_ac_xhuff_tbl_huffval_reg_a;
reg select_p_jinfo_ac_xhuff_tbl_huffval_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_xhuff_tbl_huffval_out_a = {32{ select_p_jinfo_ac_xhuff_tbl_huffval_reg_a}} & p_jinfo_ac_xhuff_tbl_huffval_out_a;
wire [31:0] memory_controller_p_jinfo_ac_xhuff_tbl_huffval_out_b = {32{ select_p_jinfo_ac_xhuff_tbl_huffval_reg_b}} & p_jinfo_ac_xhuff_tbl_huffval_out_b;
wire select_p_jinfo_dc_xhuff_tbl_bits_a = (tag_a ==`TAG_g_p_jinfo_dc_xhuff_tbl_bits);
wire select_p_jinfo_dc_xhuff_tbl_bits_b = (tag_b ==`TAG_g_p_jinfo_dc_xhuff_tbl_bits);
reg select_p_jinfo_dc_xhuff_tbl_bits_reg_a;
reg select_p_jinfo_dc_xhuff_tbl_bits_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_xhuff_tbl_bits_out_a = {32{ select_p_jinfo_dc_xhuff_tbl_bits_reg_a}} & p_jinfo_dc_xhuff_tbl_bits_out_a;
wire [31:0] memory_controller_p_jinfo_dc_xhuff_tbl_bits_out_b = {32{ select_p_jinfo_dc_xhuff_tbl_bits_reg_b}} & p_jinfo_dc_xhuff_tbl_bits_out_b;
wire select_p_jinfo_dc_xhuff_tbl_huffval_a = (tag_a ==`TAG_g_p_jinfo_dc_xhuff_tbl_huffval);
wire select_p_jinfo_dc_xhuff_tbl_huffval_b = (tag_b ==`TAG_g_p_jinfo_dc_xhuff_tbl_huffval);
reg select_p_jinfo_dc_xhuff_tbl_huffval_reg_a;
reg select_p_jinfo_dc_xhuff_tbl_huffval_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_xhuff_tbl_huffval_out_a = {32{ select_p_jinfo_dc_xhuff_tbl_huffval_reg_a}} & p_jinfo_dc_xhuff_tbl_huffval_out_a;
wire [31:0] memory_controller_p_jinfo_dc_xhuff_tbl_huffval_out_b = {32{ select_p_jinfo_dc_xhuff_tbl_huffval_reg_b}} & p_jinfo_dc_xhuff_tbl_huffval_out_b;
wire select_p_jinfo_quant_tbl_quantval_a = (tag_a ==`TAG_g_p_jinfo_quant_tbl_quantval);
wire select_p_jinfo_quant_tbl_quantval_b = (tag_b ==`TAG_g_p_jinfo_quant_tbl_quantval);
reg select_p_jinfo_quant_tbl_quantval_reg_a;
reg select_p_jinfo_quant_tbl_quantval_reg_b;
wire [31:0] memory_controller_p_jinfo_quant_tbl_quantval_out_a = {32{ select_p_jinfo_quant_tbl_quantval_reg_a}} & p_jinfo_quant_tbl_quantval_out_a;
wire [31:0] memory_controller_p_jinfo_quant_tbl_quantval_out_b = {32{ select_p_jinfo_quant_tbl_quantval_reg_b}} & p_jinfo_quant_tbl_quantval_out_b;
wire select_zigzag_index_a = (tag_a ==`TAG_g_zigzag_index);
wire select_zigzag_index_b = (tag_b ==`TAG_g_zigzag_index);
reg select_zigzag_index_reg_a;
reg select_zigzag_index_reg_b;
wire [31:0] memory_controller_zigzag_index_out_a = {32{ select_zigzag_index_reg_a}} & zigzag_index_out_a;
wire [31:0] memory_controller_zigzag_index_out_b = {32{ select_zigzag_index_reg_b}} & zigzag_index_out_b;
wire select_p_jinfo_MCUWidth_a = (tag_a ==`TAG_g_p_jinfo_MCUWidth);
wire select_p_jinfo_MCUWidth_b = (tag_b ==`TAG_g_p_jinfo_MCUWidth);
reg select_p_jinfo_MCUWidth_reg_a;
reg select_p_jinfo_MCUWidth_reg_b;
wire [31:0] memory_controller_p_jinfo_MCUWidth_out_a = {32{ select_p_jinfo_MCUWidth_reg_a}} & p_jinfo_MCUWidth_out_a;
wire [31:0] memory_controller_p_jinfo_MCUWidth_out_b = {32{ select_p_jinfo_MCUWidth_reg_b}} & p_jinfo_MCUWidth_out_b;
wire select_rgb_buf_a = (tag_a ==`TAG_g_rgb_buf);
wire select_rgb_buf_b = (tag_b ==`TAG_g_rgb_buf);
reg select_rgb_buf_reg_a;
reg select_rgb_buf_reg_b;
wire [31:0] memory_controller_rgb_buf_out_a = {32{ select_rgb_buf_reg_a}} & rgb_buf_out_a;
wire [31:0] memory_controller_rgb_buf_out_b = {32{ select_rgb_buf_reg_b}} & rgb_buf_out_b;
wire select_CurHuffReadBuf_a = (tag_a ==`TAG_g_CurHuffReadBuf);
wire select_CurHuffReadBuf_b = (tag_b ==`TAG_g_CurHuffReadBuf);
reg select_CurHuffReadBuf_reg_a;
reg select_CurHuffReadBuf_reg_b;
wire [31:0] memory_controller_CurHuffReadBuf_out_a = {32{ select_CurHuffReadBuf_reg_a}} & CurHuffReadBuf_out_a;
wire [31:0] memory_controller_CurHuffReadBuf_out_b = {32{ select_CurHuffReadBuf_reg_b}} & CurHuffReadBuf_out_b;
wire select_OutData_comp_buf_a = (tag_a ==`TAG_g_OutData_comp_buf);
wire select_OutData_comp_buf_b = (tag_b ==`TAG_g_OutData_comp_buf);
reg select_OutData_comp_buf_reg_a;
reg select_OutData_comp_buf_reg_b;
wire [7:0] memory_controller_OutData_comp_buf_out_a = {8{ select_OutData_comp_buf_reg_a}} & OutData_comp_buf_out_a;
wire [7:0] memory_controller_OutData_comp_buf_out_b = {8{ select_OutData_comp_buf_reg_b}} & OutData_comp_buf_out_b;
wire select_bit_set_mask_a = (tag_a ==`TAG_g_bit_set_mask);
wire select_bit_set_mask_b = (tag_b ==`TAG_g_bit_set_mask);
reg select_bit_set_mask_reg_a;
reg select_bit_set_mask_reg_b;
wire [31:0] memory_controller_bit_set_mask_out_a = {32{ select_bit_set_mask_reg_a}} & bit_set_mask_out_a;
wire [31:0] memory_controller_bit_set_mask_out_b = {32{ select_bit_set_mask_reg_b}} & bit_set_mask_out_b;
wire select_lmask_a = (tag_a ==`TAG_g_lmask);
wire select_lmask_b = (tag_b ==`TAG_g_lmask);
reg select_lmask_reg_a;
reg select_lmask_reg_b;
wire [31:0] memory_controller_lmask_out_a = {32{ select_lmask_reg_a}} & lmask_out_a;
wire [31:0] memory_controller_lmask_out_b = {32{ select_lmask_reg_b}} & lmask_out_b;
wire select_read_position_a = (tag_a ==`TAG_g_read_position);
wire select_read_position_b = (tag_b ==`TAG_g_read_position);
reg select_read_position_reg_a;
reg select_read_position_reg_b;
wire [31:0] memory_controller_read_position_out_a = {32{ select_read_position_reg_a}} & read_position_out_a;
wire [31:0] memory_controller_read_position_out_b = {32{ select_read_position_reg_b}} & read_position_out_b;
wire select_current_read_byte_a = (tag_a ==`TAG_g_current_read_byte);
wire select_current_read_byte_b = (tag_b ==`TAG_g_current_read_byte);
reg select_current_read_byte_reg_a;
reg select_current_read_byte_reg_b;
wire [31:0] memory_controller_current_read_byte_out_a = {32{ select_current_read_byte_reg_a}} & current_read_byte_out_a;
wire [31:0] memory_controller_current_read_byte_out_b = {32{ select_current_read_byte_reg_b}} & current_read_byte_out_b;
wire select_p_jinfo_dc_dhuff_tbl_ml_a = (tag_a ==`TAG_g_p_jinfo_dc_dhuff_tbl_ml);
wire select_p_jinfo_dc_dhuff_tbl_ml_b = (tag_b ==`TAG_g_p_jinfo_dc_dhuff_tbl_ml);
reg select_p_jinfo_dc_dhuff_tbl_ml_reg_a;
reg select_p_jinfo_dc_dhuff_tbl_ml_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_ml_out_a = {32{ select_p_jinfo_dc_dhuff_tbl_ml_reg_a}} & p_jinfo_dc_dhuff_tbl_ml_out_a;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_ml_out_b = {32{ select_p_jinfo_dc_dhuff_tbl_ml_reg_b}} & p_jinfo_dc_dhuff_tbl_ml_out_b;
wire select_p_jinfo_dc_dhuff_tbl_maxcode_a = (tag_a ==`TAG_g_p_jinfo_dc_dhuff_tbl_maxcode);
wire select_p_jinfo_dc_dhuff_tbl_maxcode_b = (tag_b ==`TAG_g_p_jinfo_dc_dhuff_tbl_maxcode);
reg select_p_jinfo_dc_dhuff_tbl_maxcode_reg_a;
reg select_p_jinfo_dc_dhuff_tbl_maxcode_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_maxcode_out_a = {32{ select_p_jinfo_dc_dhuff_tbl_maxcode_reg_a}} & p_jinfo_dc_dhuff_tbl_maxcode_out_a;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_maxcode_out_b = {32{ select_p_jinfo_dc_dhuff_tbl_maxcode_reg_b}} & p_jinfo_dc_dhuff_tbl_maxcode_out_b;
wire select_p_jinfo_dc_dhuff_tbl_mincode_a = (tag_a ==`TAG_g_p_jinfo_dc_dhuff_tbl_mincode);
wire select_p_jinfo_dc_dhuff_tbl_mincode_b = (tag_b ==`TAG_g_p_jinfo_dc_dhuff_tbl_mincode);
reg select_p_jinfo_dc_dhuff_tbl_mincode_reg_a;
reg select_p_jinfo_dc_dhuff_tbl_mincode_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_mincode_out_a = {32{ select_p_jinfo_dc_dhuff_tbl_mincode_reg_a}} & p_jinfo_dc_dhuff_tbl_mincode_out_a;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_mincode_out_b = {32{ select_p_jinfo_dc_dhuff_tbl_mincode_reg_b}} & p_jinfo_dc_dhuff_tbl_mincode_out_b;
wire select_p_jinfo_dc_dhuff_tbl_valptr_a = (tag_a ==`TAG_g_p_jinfo_dc_dhuff_tbl_valptr);
wire select_p_jinfo_dc_dhuff_tbl_valptr_b = (tag_b ==`TAG_g_p_jinfo_dc_dhuff_tbl_valptr);
reg select_p_jinfo_dc_dhuff_tbl_valptr_reg_a;
reg select_p_jinfo_dc_dhuff_tbl_valptr_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_valptr_out_a = {32{ select_p_jinfo_dc_dhuff_tbl_valptr_reg_a}} & p_jinfo_dc_dhuff_tbl_valptr_out_a;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_valptr_out_b = {32{ select_p_jinfo_dc_dhuff_tbl_valptr_reg_b}} & p_jinfo_dc_dhuff_tbl_valptr_out_b;
wire select_extend_mask_a = (tag_a ==`TAG_g_extend_mask);
wire select_extend_mask_b = (tag_b ==`TAG_g_extend_mask);
reg select_extend_mask_reg_a;
reg select_extend_mask_reg_b;
wire [31:0] memory_controller_extend_mask_out_a = {32{ select_extend_mask_reg_a}} & extend_mask_out_a;
wire [31:0] memory_controller_extend_mask_out_b = {32{ select_extend_mask_reg_b}} & extend_mask_out_b;
wire select_p_jinfo_ac_dhuff_tbl_ml_a = (tag_a ==`TAG_g_p_jinfo_ac_dhuff_tbl_ml);
wire select_p_jinfo_ac_dhuff_tbl_ml_b = (tag_b ==`TAG_g_p_jinfo_ac_dhuff_tbl_ml);
reg select_p_jinfo_ac_dhuff_tbl_ml_reg_a;
reg select_p_jinfo_ac_dhuff_tbl_ml_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_ml_out_a = {32{ select_p_jinfo_ac_dhuff_tbl_ml_reg_a}} & p_jinfo_ac_dhuff_tbl_ml_out_a;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_ml_out_b = {32{ select_p_jinfo_ac_dhuff_tbl_ml_reg_b}} & p_jinfo_ac_dhuff_tbl_ml_out_b;
wire select_p_jinfo_ac_dhuff_tbl_maxcode_a = (tag_a ==`TAG_g_p_jinfo_ac_dhuff_tbl_maxcode);
wire select_p_jinfo_ac_dhuff_tbl_maxcode_b = (tag_b ==`TAG_g_p_jinfo_ac_dhuff_tbl_maxcode);
reg select_p_jinfo_ac_dhuff_tbl_maxcode_reg_a;
reg select_p_jinfo_ac_dhuff_tbl_maxcode_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_maxcode_out_a = {32{ select_p_jinfo_ac_dhuff_tbl_maxcode_reg_a}} & p_jinfo_ac_dhuff_tbl_maxcode_out_a;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_maxcode_out_b = {32{ select_p_jinfo_ac_dhuff_tbl_maxcode_reg_b}} & p_jinfo_ac_dhuff_tbl_maxcode_out_b;
wire select_p_jinfo_ac_dhuff_tbl_mincode_a = (tag_a ==`TAG_g_p_jinfo_ac_dhuff_tbl_mincode);
wire select_p_jinfo_ac_dhuff_tbl_mincode_b = (tag_b ==`TAG_g_p_jinfo_ac_dhuff_tbl_mincode);
reg select_p_jinfo_ac_dhuff_tbl_mincode_reg_a;
reg select_p_jinfo_ac_dhuff_tbl_mincode_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_mincode_out_a = {32{ select_p_jinfo_ac_dhuff_tbl_mincode_reg_a}} & p_jinfo_ac_dhuff_tbl_mincode_out_a;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_mincode_out_b = {32{ select_p_jinfo_ac_dhuff_tbl_mincode_reg_b}} & p_jinfo_ac_dhuff_tbl_mincode_out_b;
wire select_p_jinfo_ac_dhuff_tbl_valptr_a = (tag_a ==`TAG_g_p_jinfo_ac_dhuff_tbl_valptr);
wire select_p_jinfo_ac_dhuff_tbl_valptr_b = (tag_b ==`TAG_g_p_jinfo_ac_dhuff_tbl_valptr);
reg select_p_jinfo_ac_dhuff_tbl_valptr_reg_a;
reg select_p_jinfo_ac_dhuff_tbl_valptr_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_valptr_out_a = {32{ select_p_jinfo_ac_dhuff_tbl_valptr_reg_a}} & p_jinfo_ac_dhuff_tbl_valptr_out_a;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_valptr_out_b = {32{ select_p_jinfo_ac_dhuff_tbl_valptr_reg_b}} & p_jinfo_ac_dhuff_tbl_valptr_out_b;
wire select_OutData_comp_vpos_a = (tag_a ==`TAG_g_OutData_comp_vpos);
wire select_OutData_comp_vpos_b = (tag_b ==`TAG_g_OutData_comp_vpos);
reg select_OutData_comp_vpos_reg_a;
reg select_OutData_comp_vpos_reg_b;
wire [31:0] memory_controller_OutData_comp_vpos_out_a = {32{ select_OutData_comp_vpos_reg_a}} & OutData_comp_vpos_out_a;
wire [31:0] memory_controller_OutData_comp_vpos_out_b = {32{ select_OutData_comp_vpos_reg_b}} & OutData_comp_vpos_out_b;
wire select_OutData_comp_hpos_a = (tag_a ==`TAG_g_OutData_comp_hpos);
wire select_OutData_comp_hpos_b = (tag_b ==`TAG_g_OutData_comp_hpos);
reg select_OutData_comp_hpos_reg_a;
reg select_OutData_comp_hpos_reg_b;
wire [31:0] memory_controller_OutData_comp_hpos_out_a = {32{ select_OutData_comp_hpos_reg_a}} & OutData_comp_hpos_out_a;
wire [31:0] memory_controller_OutData_comp_hpos_out_b = {32{ select_OutData_comp_hpos_reg_b}} & OutData_comp_hpos_out_b;
wire select_JpegFileBuf_a = (tag_a ==`TAG_g_JpegFileBuf);
wire select_JpegFileBuf_b = (tag_b ==`TAG_g_JpegFileBuf);
reg select_JpegFileBuf_reg_a;
reg select_JpegFileBuf_reg_b;
wire [7:0] memory_controller_JpegFileBuf_out_a = {8{ select_JpegFileBuf_reg_a}} & JpegFileBuf_out_a;
wire [7:0] memory_controller_JpegFileBuf_out_b = {8{ select_JpegFileBuf_reg_b}} & JpegFileBuf_out_b;
wire select_decode_block_0_QuantBuff_a = (tag_a ==`TAG_decode_block_0_QuantBuff);
wire select_decode_block_0_QuantBuff_b = (tag_b ==`TAG_decode_block_0_QuantBuff);
reg select_decode_block_0_QuantBuff_reg_a;
reg select_decode_block_0_QuantBuff_reg_b;
wire [31:0] memory_controller_decode_block_0_QuantBuff_out_a = {32{ select_decode_block_0_QuantBuff_reg_a}} & decode_block_0_QuantBuff_out_a;
wire [31:0] memory_controller_decode_block_0_QuantBuff_out_b = {32{ select_decode_block_0_QuantBuff_reg_b}} & decode_block_0_QuantBuff_out_b;
wire select_huff_make_dhuff_tb_0_huffsize_a = (tag_a ==`TAG_huff_make_dhuff_tb_0_huffsize);
wire select_huff_make_dhuff_tb_0_huffsize_b = (tag_b ==`TAG_huff_make_dhuff_tb_0_huffsize);
reg select_huff_make_dhuff_tb_0_huffsize_reg_a;
reg select_huff_make_dhuff_tb_0_huffsize_reg_b;
wire [31:0] memory_controller_huff_make_dhuff_tb_0_huffsize_out_a = {32{ select_huff_make_dhuff_tb_0_huffsize_reg_a}} & huff_make_dhuff_tb_0_huffsize_out_a;
wire [31:0] memory_controller_huff_make_dhuff_tb_0_huffsize_out_b = {32{ select_huff_make_dhuff_tb_0_huffsize_reg_b}} & huff_make_dhuff_tb_0_huffsize_out_b;
wire select_huff_make_dhuff_tb_0_huffcode_a = (tag_a ==`TAG_huff_make_dhuff_tb_0_huffcode);
wire select_huff_make_dhuff_tb_0_huffcode_b = (tag_b ==`TAG_huff_make_dhuff_tb_0_huffcode);
reg select_huff_make_dhuff_tb_0_huffcode_reg_a;
reg select_huff_make_dhuff_tb_0_huffcode_reg_b;
wire [31:0] memory_controller_huff_make_dhuff_tb_0_huffcode_out_a = {32{ select_huff_make_dhuff_tb_0_huffcode_reg_a}} & huff_make_dhuff_tb_0_huffcode_out_a;
wire [31:0] memory_controller_huff_make_dhuff_tb_0_huffcode_out_b = {32{ select_huff_make_dhuff_tb_0_huffcode_reg_b}} & huff_make_dhuff_tb_0_huffcode_out_b;
wire select_main_0_HuffBuff_i_i_a = (tag_a ==`TAG_main_0_HuffBuff_i_i);
wire select_main_0_HuffBuff_i_i_b = (tag_b ==`TAG_main_0_HuffBuff_i_i);
reg select_main_0_HuffBuff_i_i_reg_a;
reg select_main_0_HuffBuff_i_i_reg_b;
wire [31:0] memory_controller_main_0_HuffBuff_i_i_out_a = {32{ select_main_0_HuffBuff_i_i_reg_a}} & main_0_HuffBuff_i_i_out_a;
wire [31:0] memory_controller_main_0_HuffBuff_i_i_out_b = {32{ select_main_0_HuffBuff_i_i_reg_b}} & main_0_HuffBuff_i_i_out_b;
wire select_main_0_IDCTBuff_i_i_a = (tag_a ==`TAG_main_0_IDCTBuff_i_i);
wire select_main_0_IDCTBuff_i_i_b = (tag_b ==`TAG_main_0_IDCTBuff_i_i);
reg select_main_0_IDCTBuff_i_i_reg_a;
reg select_main_0_IDCTBuff_i_i_reg_b;
wire [31:0] memory_controller_main_0_IDCTBuff_i_i_out_a = {32{ select_main_0_IDCTBuff_i_i_reg_a}} & main_0_IDCTBuff_i_i_out_a;
wire [31:0] memory_controller_main_0_IDCTBuff_i_i_out_b = {32{ select_main_0_IDCTBuff_i_i_reg_b}} & main_0_IDCTBuff_i_i_out_b;
always @(*)
begin
hana_jpg_address_a = memory_controller_address_a [13-1+0:0] & {13{select_hana_jpg_a}};
hana_jpg_address_b = memory_controller_address_b [13-1+0:0] & {13{select_hana_jpg_b}};
hana_jpg_write_enable_a = memory_controller_write_enable_a & select_hana_jpg_a;
hana_jpg_write_enable_b = memory_controller_write_enable_b & select_hana_jpg_b;
hana_jpg_in_a [8-1:0] = memory_controller_in_a[8-1:0];
hana_jpg_in_b [8-1:0] = memory_controller_in_b[8-1:0];
hana_bmp_address_a = memory_controller_address_a [14-1+0:0] & {14{select_hana_bmp_a}};
hana_bmp_address_b = memory_controller_address_b [14-1+0:0] & {14{select_hana_bmp_b}};
hana_bmp_write_enable_a = memory_controller_write_enable_a & select_hana_bmp_a;
hana_bmp_write_enable_b = memory_controller_write_enable_b & select_hana_bmp_b;
hana_bmp_in_a [8-1:0] = memory_controller_in_a[8-1:0];
hana_bmp_in_b [8-1:0] = memory_controller_in_b[8-1:0];
out_unread_marker_address_a = memory_controller_address_a [4-1+2:2] & {4{select_out_unread_marker_a}};
out_unread_marker_address_b = memory_controller_address_b [4-1+2:2] & {4{select_out_unread_marker_b}};
out_unread_marker_write_enable_a = memory_controller_write_enable_a & select_out_unread_marker_a;
out_unread_marker_write_enable_b = memory_controller_write_enable_b & select_out_unread_marker_b;
out_unread_marker_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_unread_marker_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_index_get_sof_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_index_get_sof_a}};
out_index_get_sof_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_index_get_sof_b}};
out_index_get_sof_write_enable_a = memory_controller_write_enable_a & select_out_index_get_sof_a;
out_index_get_sof_write_enable_b = memory_controller_write_enable_b & select_out_index_get_sof_b;
out_index_get_sof_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_index_get_sof_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_v_samp_factor_get_sof_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_v_samp_factor_get_sof_a}};
out_v_samp_factor_get_sof_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_v_samp_factor_get_sof_b}};
out_v_samp_factor_get_sof_write_enable_a = memory_controller_write_enable_a & select_out_v_samp_factor_get_sof_a;
out_v_samp_factor_get_sof_write_enable_b = memory_controller_write_enable_b & select_out_v_samp_factor_get_sof_b;
out_v_samp_factor_get_sof_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_v_samp_factor_get_sof_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_comp_id_get_sos_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_comp_id_get_sos_a}};
out_comp_id_get_sos_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_comp_id_get_sos_b}};
out_comp_id_get_sos_write_enable_a = memory_controller_write_enable_a & select_out_comp_id_get_sos_a;
out_comp_id_get_sos_write_enable_b = memory_controller_write_enable_b & select_out_comp_id_get_sos_b;
out_comp_id_get_sos_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_comp_id_get_sos_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_ac_tbl_no_get_sos_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_ac_tbl_no_get_sos_a}};
out_ac_tbl_no_get_sos_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_ac_tbl_no_get_sos_b}};
out_ac_tbl_no_get_sos_write_enable_a = memory_controller_write_enable_a & select_out_ac_tbl_no_get_sos_a;
out_ac_tbl_no_get_sos_write_enable_b = memory_controller_write_enable_b & select_out_ac_tbl_no_get_sos_b;
out_ac_tbl_no_get_sos_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_ac_tbl_no_get_sos_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_length_get_dht_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_length_get_dht_a}};
out_length_get_dht_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_length_get_dht_b}};
out_length_get_dht_write_enable_a = memory_controller_write_enable_a & select_out_length_get_dht_a;
out_length_get_dht_write_enable_b = memory_controller_write_enable_b & select_out_length_get_dht_b;
out_length_get_dht_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_length_get_dht_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_index_get_dht_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_index_get_dht_a}};
out_index_get_dht_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_index_get_dht_b}};
out_index_get_dht_write_enable_a = memory_controller_write_enable_a & select_out_index_get_dht_a;
out_index_get_dht_write_enable_b = memory_controller_write_enable_b & select_out_index_get_dht_b;
out_index_get_dht_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_index_get_dht_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_count_get_dht_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_count_get_dht_a}};
out_count_get_dht_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_count_get_dht_b}};
out_count_get_dht_write_enable_a = memory_controller_write_enable_a & select_out_count_get_dht_a;
out_count_get_dht_write_enable_b = memory_controller_write_enable_b & select_out_count_get_dht_b;
out_count_get_dht_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_count_get_dht_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_length_get_dqt_address_a = memory_controller_address_a [1-1+2:2] & {1{select_out_length_get_dqt_a}};
out_length_get_dqt_address_b = memory_controller_address_b [1-1+2:2] & {1{select_out_length_get_dqt_b}};
out_length_get_dqt_write_enable_a = memory_controller_write_enable_a & select_out_length_get_dqt_a;
out_length_get_dqt_write_enable_b = memory_controller_write_enable_b & select_out_length_get_dqt_b;
out_length_get_dqt_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_length_get_dqt_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_prec_get_dht_address_a = memory_controller_address_a [1-1+2:2] & {1{select_out_prec_get_dht_a}};
out_prec_get_dht_address_b = memory_controller_address_b [1-1+2:2] & {1{select_out_prec_get_dht_b}};
out_prec_get_dht_write_enable_a = memory_controller_write_enable_a & select_out_prec_get_dht_a;
out_prec_get_dht_write_enable_b = memory_controller_write_enable_b & select_out_prec_get_dht_b;
out_prec_get_dht_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_prec_get_dht_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_num_get_dht_address_a = memory_controller_address_a [1-1+2:2] & {1{select_out_num_get_dht_a}};
out_num_get_dht_address_b = memory_controller_address_b [1-1+2:2] & {1{select_out_num_get_dht_b}};
out_num_get_dht_write_enable_a = memory_controller_write_enable_a & select_out_num_get_dht_a;
out_num_get_dht_write_enable_b = memory_controller_write_enable_b & select_out_num_get_dht_b;
out_num_get_dht_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_num_get_dht_in_b [32-1:0] = memory_controller_in_b[32-1:0];
izigzag_index_address_a = memory_controller_address_a [6-1+2:2] & {6{select_izigzag_index_a}};
izigzag_index_address_b = memory_controller_address_b [6-1+2:2] & {6{select_izigzag_index_b}};
izigzag_index_write_enable_a = memory_controller_write_enable_a & select_izigzag_index_a;
izigzag_index_write_enable_b = memory_controller_write_enable_b & select_izigzag_index_b;
izigzag_index_in_a [32-1:0] = memory_controller_in_a[32-1:0];
izigzag_index_in_b [32-1:0] = memory_controller_in_b[32-1:0];
main_result_address_a = memory_controller_address_a [1-1+2:2] & {1{select_main_result_a}};
main_result_address_b = memory_controller_address_b [1-1+2:2] & {1{select_main_result_b}};
main_result_write_enable_a = memory_controller_write_enable_a & select_main_result_a;
main_result_write_enable_b = memory_controller_write_enable_b & select_main_result_b;
main_result_in_a [32-1:0] = memory_controller_in_a[32-1:0];
main_result_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_image_height_address_a = memory_controller_address_a [1-1+1:1] & {1{select_p_jinfo_image_height_a}};
p_jinfo_image_height_address_b = memory_controller_address_b [1-1+1:1] & {1{select_p_jinfo_image_height_b}};
p_jinfo_image_height_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_image_height_a;
p_jinfo_image_height_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_image_height_b;
p_jinfo_image_height_in_a [16-1:0] = memory_controller_in_a[16-1:0];
p_jinfo_image_height_in_b [16-1:0] = memory_controller_in_b[16-1:0];
p_jinfo_image_width_address_a = memory_controller_address_a [1-1+1:1] & {1{select_p_jinfo_image_width_a}};
p_jinfo_image_width_address_b = memory_controller_address_b [1-1+1:1] & {1{select_p_jinfo_image_width_b}};
p_jinfo_image_width_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_image_width_a;
p_jinfo_image_width_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_image_width_b;
p_jinfo_image_width_in_a [16-1:0] = memory_controller_in_a[16-1:0];
p_jinfo_image_width_in_b [16-1:0] = memory_controller_in_b[16-1:0];
p_jinfo_comps_info_index_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_index_a}};
p_jinfo_comps_info_index_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_index_b}};
p_jinfo_comps_info_index_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_index_a;
p_jinfo_comps_info_index_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_index_b;
p_jinfo_comps_info_index_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_index_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_id_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_id_a}};
p_jinfo_comps_info_id_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_id_b}};
p_jinfo_comps_info_id_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_id_a;
p_jinfo_comps_info_id_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_id_b;
p_jinfo_comps_info_id_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_id_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_h_samp_factor_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_h_samp_factor_a}};
p_jinfo_comps_info_h_samp_factor_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_h_samp_factor_b}};
p_jinfo_comps_info_h_samp_factor_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_h_samp_factor_a;
p_jinfo_comps_info_h_samp_factor_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_h_samp_factor_b;
p_jinfo_comps_info_h_samp_factor_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_h_samp_factor_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_v_samp_factor_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_v_samp_factor_a}};
p_jinfo_comps_info_v_samp_factor_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_v_samp_factor_b}};
p_jinfo_comps_info_v_samp_factor_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_v_samp_factor_a;
p_jinfo_comps_info_v_samp_factor_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_v_samp_factor_b;
p_jinfo_comps_info_v_samp_factor_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_v_samp_factor_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_quant_tbl_no_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_quant_tbl_no_a}};
p_jinfo_comps_info_quant_tbl_no_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_quant_tbl_no_b}};
p_jinfo_comps_info_quant_tbl_no_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_quant_tbl_no_a;
p_jinfo_comps_info_quant_tbl_no_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_quant_tbl_no_b;
p_jinfo_comps_info_quant_tbl_no_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_quant_tbl_no_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_dc_tbl_no_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_dc_tbl_no_a}};
p_jinfo_comps_info_dc_tbl_no_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_dc_tbl_no_b}};
p_jinfo_comps_info_dc_tbl_no_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_dc_tbl_no_a;
p_jinfo_comps_info_dc_tbl_no_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_dc_tbl_no_b;
p_jinfo_comps_info_dc_tbl_no_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_dc_tbl_no_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_ac_tbl_no_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_ac_tbl_no_a}};
p_jinfo_comps_info_ac_tbl_no_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_ac_tbl_no_b}};
p_jinfo_comps_info_ac_tbl_no_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_ac_tbl_no_a;
p_jinfo_comps_info_ac_tbl_no_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_ac_tbl_no_b;
p_jinfo_comps_info_ac_tbl_no_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_ac_tbl_no_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_ac_xhuff_tbl_bits_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_ac_xhuff_tbl_bits_a}};
p_jinfo_ac_xhuff_tbl_bits_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_ac_xhuff_tbl_bits_b}};
p_jinfo_ac_xhuff_tbl_bits_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_xhuff_tbl_bits_a;
p_jinfo_ac_xhuff_tbl_bits_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_xhuff_tbl_bits_b;
p_jinfo_ac_xhuff_tbl_bits_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_xhuff_tbl_bits_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_ac_xhuff_tbl_huffval_address_a = memory_controller_address_a [10-1+2:2] & {10{select_p_jinfo_ac_xhuff_tbl_huffval_a}};
p_jinfo_ac_xhuff_tbl_huffval_address_b = memory_controller_address_b [10-1+2:2] & {10{select_p_jinfo_ac_xhuff_tbl_huffval_b}};
p_jinfo_ac_xhuff_tbl_huffval_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_xhuff_tbl_huffval_a;
p_jinfo_ac_xhuff_tbl_huffval_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_xhuff_tbl_huffval_b;
p_jinfo_ac_xhuff_tbl_huffval_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_xhuff_tbl_huffval_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_xhuff_tbl_bits_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_dc_xhuff_tbl_bits_a}};
p_jinfo_dc_xhuff_tbl_bits_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_dc_xhuff_tbl_bits_b}};
p_jinfo_dc_xhuff_tbl_bits_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_xhuff_tbl_bits_a;
p_jinfo_dc_xhuff_tbl_bits_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_xhuff_tbl_bits_b;
p_jinfo_dc_xhuff_tbl_bits_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_xhuff_tbl_bits_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_xhuff_tbl_huffval_address_a = memory_controller_address_a [10-1+2:2] & {10{select_p_jinfo_dc_xhuff_tbl_huffval_a}};
p_jinfo_dc_xhuff_tbl_huffval_address_b = memory_controller_address_b [10-1+2:2] & {10{select_p_jinfo_dc_xhuff_tbl_huffval_b}};
p_jinfo_dc_xhuff_tbl_huffval_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_xhuff_tbl_huffval_a;
p_jinfo_dc_xhuff_tbl_huffval_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_xhuff_tbl_huffval_b;
p_jinfo_dc_xhuff_tbl_huffval_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_xhuff_tbl_huffval_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_quant_tbl_quantval_address_a = memory_controller_address_a [8-1+2:2] & {8{select_p_jinfo_quant_tbl_quantval_a}};
p_jinfo_quant_tbl_quantval_address_b = memory_controller_address_b [8-1+2:2] & {8{select_p_jinfo_quant_tbl_quantval_b}};
p_jinfo_quant_tbl_quantval_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_quant_tbl_quantval_a;
p_jinfo_quant_tbl_quantval_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_quant_tbl_quantval_b;
p_jinfo_quant_tbl_quantval_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_quant_tbl_quantval_in_b [32-1:0] = memory_controller_in_b[32-1:0];
zigzag_index_address_a = memory_controller_address_a [6-1+2:2] & {6{select_zigzag_index_a}};
zigzag_index_address_b = memory_controller_address_b [6-1+2:2] & {6{select_zigzag_index_b}};
zigzag_index_write_enable_a = memory_controller_write_enable_a & select_zigzag_index_a;
zigzag_index_write_enable_b = memory_controller_write_enable_b & select_zigzag_index_b;
zigzag_index_in_a [32-1:0] = memory_controller_in_a[32-1:0];
zigzag_index_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_MCUWidth_address_a = memory_controller_address_a [1-1+2:2] & {1{select_p_jinfo_MCUWidth_a}};
p_jinfo_MCUWidth_address_b = memory_controller_address_b [1-1+2:2] & {1{select_p_jinfo_MCUWidth_b}};
p_jinfo_MCUWidth_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_MCUWidth_a;
p_jinfo_MCUWidth_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_MCUWidth_b;
p_jinfo_MCUWidth_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_MCUWidth_in_b [32-1:0] = memory_controller_in_b[32-1:0];
rgb_buf_address_a = memory_controller_address_a [10-1+2:2] & {10{select_rgb_buf_a}};
rgb_buf_address_b = memory_controller_address_b [10-1+2:2] & {10{select_rgb_buf_b}};
rgb_buf_write_enable_a = memory_controller_write_enable_a & select_rgb_buf_a;
rgb_buf_write_enable_b = memory_controller_write_enable_b & select_rgb_buf_b;
rgb_buf_in_a [32-1:0] = memory_controller_in_a[32-1:0];
rgb_buf_in_b [32-1:0] = memory_controller_in_b[32-1:0];
CurHuffReadBuf_address_a = memory_controller_address_a [1-1+2:2] & {1{select_CurHuffReadBuf_a}};
CurHuffReadBuf_address_b = memory_controller_address_b [1-1+2:2] & {1{select_CurHuffReadBuf_b}};
CurHuffReadBuf_write_enable_a = memory_controller_write_enable_a & select_CurHuffReadBuf_a;
CurHuffReadBuf_write_enable_b = memory_controller_write_enable_b & select_CurHuffReadBuf_b;
CurHuffReadBuf_in_a [32-1:0] = memory_controller_in_a[32-1:0];
CurHuffReadBuf_in_b [32-1:0] = memory_controller_in_b[32-1:0];
OutData_comp_buf_address_a = memory_controller_address_a [14-1+0:0] & {14{select_OutData_comp_buf_a}};
OutData_comp_buf_address_b = memory_controller_address_b [14-1+0:0] & {14{select_OutData_comp_buf_b}};
OutData_comp_buf_write_enable_a = memory_controller_write_enable_a & select_OutData_comp_buf_a;
OutData_comp_buf_write_enable_b = memory_controller_write_enable_b & select_OutData_comp_buf_b;
OutData_comp_buf_in_a [8-1:0] = memory_controller_in_a[8-1:0];
OutData_comp_buf_in_b [8-1:0] = memory_controller_in_b[8-1:0];
bit_set_mask_address_a = memory_controller_address_a [5-1+2:2] & {5{select_bit_set_mask_a}};
bit_set_mask_address_b = memory_controller_address_b [5-1+2:2] & {5{select_bit_set_mask_b}};
bit_set_mask_write_enable_a = memory_controller_write_enable_a & select_bit_set_mask_a;
bit_set_mask_write_enable_b = memory_controller_write_enable_b & select_bit_set_mask_b;
bit_set_mask_in_a [32-1:0] = memory_controller_in_a[32-1:0];
bit_set_mask_in_b [32-1:0] = memory_controller_in_b[32-1:0];
lmask_address_a = memory_controller_address_a [5-1+2:2] & {5{select_lmask_a}};
lmask_address_b = memory_controller_address_b [5-1+2:2] & {5{select_lmask_b}};
lmask_write_enable_a = memory_controller_write_enable_a & select_lmask_a;
lmask_write_enable_b = memory_controller_write_enable_b & select_lmask_b;
lmask_in_a [32-1:0] = memory_controller_in_a[32-1:0];
lmask_in_b [32-1:0] = memory_controller_in_b[32-1:0];
read_position_address_a = memory_controller_address_a [1-1+2:2] & {1{select_read_position_a}};
read_position_address_b = memory_controller_address_b [1-1+2:2] & {1{select_read_position_b}};
read_position_write_enable_a = memory_controller_write_enable_a & select_read_position_a;
read_position_write_enable_b = memory_controller_write_enable_b & select_read_position_b;
read_position_in_a [32-1:0] = memory_controller_in_a[32-1:0];
read_position_in_b [32-1:0] = memory_controller_in_b[32-1:0];
current_read_byte_address_a = memory_controller_address_a [1-1+2:2] & {1{select_current_read_byte_a}};
current_read_byte_address_b = memory_controller_address_b [1-1+2:2] & {1{select_current_read_byte_b}};
current_read_byte_write_enable_a = memory_controller_write_enable_a & select_current_read_byte_a;
current_read_byte_write_enable_b = memory_controller_write_enable_b & select_current_read_byte_b;
current_read_byte_in_a [32-1:0] = memory_controller_in_a[32-1:0];
current_read_byte_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_dhuff_tbl_ml_address_a = memory_controller_address_a [1-1+2:2] & {1{select_p_jinfo_dc_dhuff_tbl_ml_a}};
p_jinfo_dc_dhuff_tbl_ml_address_b = memory_controller_address_b [1-1+2:2] & {1{select_p_jinfo_dc_dhuff_tbl_ml_b}};
p_jinfo_dc_dhuff_tbl_ml_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_dhuff_tbl_ml_a;
p_jinfo_dc_dhuff_tbl_ml_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_dhuff_tbl_ml_b;
p_jinfo_dc_dhuff_tbl_ml_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_dhuff_tbl_ml_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_dhuff_tbl_maxcode_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_maxcode_a}};
p_jinfo_dc_dhuff_tbl_maxcode_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_maxcode_b}};
p_jinfo_dc_dhuff_tbl_maxcode_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_dhuff_tbl_maxcode_a;
p_jinfo_dc_dhuff_tbl_maxcode_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_dhuff_tbl_maxcode_b;
p_jinfo_dc_dhuff_tbl_maxcode_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_dhuff_tbl_maxcode_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_dhuff_tbl_mincode_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_mincode_a}};
p_jinfo_dc_dhuff_tbl_mincode_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_mincode_b}};
p_jinfo_dc_dhuff_tbl_mincode_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_dhuff_tbl_mincode_a;
p_jinfo_dc_dhuff_tbl_mincode_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_dhuff_tbl_mincode_b;
p_jinfo_dc_dhuff_tbl_mincode_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_dhuff_tbl_mincode_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_dhuff_tbl_valptr_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_valptr_a}};
p_jinfo_dc_dhuff_tbl_valptr_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_valptr_b}};
p_jinfo_dc_dhuff_tbl_valptr_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_dhuff_tbl_valptr_a;
p_jinfo_dc_dhuff_tbl_valptr_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_dhuff_tbl_valptr_b;
p_jinfo_dc_dhuff_tbl_valptr_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_dhuff_tbl_valptr_in_b [32-1:0] = memory_controller_in_b[32-1:0];
extend_mask_address_a = memory_controller_address_a [5-1+2:2] & {5{select_extend_mask_a}};
extend_mask_address_b = memory_controller_address_b [5-1+2:2] & {5{select_extend_mask_b}};
extend_mask_write_enable_a = memory_controller_write_enable_a & select_extend_mask_a;
extend_mask_write_enable_b = memory_controller_write_enable_b & select_extend_mask_b;
extend_mask_in_a [32-1:0] = memory_controller_in_a[32-1:0];
extend_mask_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_ac_dhuff_tbl_ml_address_a = memory_controller_address_a [1-1+2:2] & {1{select_p_jinfo_ac_dhuff_tbl_ml_a}};
p_jinfo_ac_dhuff_tbl_ml_address_b = memory_controller_address_b [1-1+2:2] & {1{select_p_jinfo_ac_dhuff_tbl_ml_b}};
p_jinfo_ac_dhuff_tbl_ml_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_dhuff_tbl_ml_a;
p_jinfo_ac_dhuff_tbl_ml_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_dhuff_tbl_ml_b;
p_jinfo_ac_dhuff_tbl_ml_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_dhuff_tbl_ml_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_ac_dhuff_tbl_maxcode_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_maxcode_a}};
p_jinfo_ac_dhuff_tbl_maxcode_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_maxcode_b}};
p_jinfo_ac_dhuff_tbl_maxcode_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_dhuff_tbl_maxcode_a;
p_jinfo_ac_dhuff_tbl_maxcode_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_dhuff_tbl_maxcode_b;
p_jinfo_ac_dhuff_tbl_maxcode_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_dhuff_tbl_maxcode_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_ac_dhuff_tbl_mincode_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_mincode_a}};
p_jinfo_ac_dhuff_tbl_mincode_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_mincode_b}};
p_jinfo_ac_dhuff_tbl_mincode_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_dhuff_tbl_mincode_a;
p_jinfo_ac_dhuff_tbl_mincode_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_dhuff_tbl_mincode_b;
p_jinfo_ac_dhuff_tbl_mincode_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_dhuff_tbl_mincode_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_ac_dhuff_tbl_valptr_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_valptr_a}};
p_jinfo_ac_dhuff_tbl_valptr_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_valptr_b}};
p_jinfo_ac_dhuff_tbl_valptr_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_dhuff_tbl_valptr_a;
p_jinfo_ac_dhuff_tbl_valptr_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_dhuff_tbl_valptr_b;
p_jinfo_ac_dhuff_tbl_valptr_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_dhuff_tbl_valptr_in_b [32-1:0] = memory_controller_in_b[32-1:0];
OutData_comp_vpos_address_a = memory_controller_address_a [2-1+2:2] & {2{select_OutData_comp_vpos_a}};
OutData_comp_vpos_address_b = memory_controller_address_b [2-1+2:2] & {2{select_OutData_comp_vpos_b}};
OutData_comp_vpos_write_enable_a = memory_controller_write_enable_a & select_OutData_comp_vpos_a;
OutData_comp_vpos_write_enable_b = memory_controller_write_enable_b & select_OutData_comp_vpos_b;
OutData_comp_vpos_in_a [32-1:0] = memory_controller_in_a[32-1:0];
OutData_comp_vpos_in_b [32-1:0] = memory_controller_in_b[32-1:0];
OutData_comp_hpos_address_a = memory_controller_address_a [2-1+2:2] & {2{select_OutData_comp_hpos_a}};
OutData_comp_hpos_address_b = memory_controller_address_b [2-1+2:2] & {2{select_OutData_comp_hpos_b}};
OutData_comp_hpos_write_enable_a = memory_controller_write_enable_a & select_OutData_comp_hpos_a;
OutData_comp_hpos_write_enable_b = memory_controller_write_enable_b & select_OutData_comp_hpos_b;
OutData_comp_hpos_in_a [32-1:0] = memory_controller_in_a[32-1:0];
OutData_comp_hpos_in_b [32-1:0] = memory_controller_in_b[32-1:0];
JpegFileBuf_address_a = memory_controller_address_a [13-1+0:0] & {13{select_JpegFileBuf_a}};
JpegFileBuf_address_b = memory_controller_address_b [13-1+0:0] & {13{select_JpegFileBuf_b}};
JpegFileBuf_write_enable_a = memory_controller_write_enable_a & select_JpegFileBuf_a;
JpegFileBuf_write_enable_b = memory_controller_write_enable_b & select_JpegFileBuf_b;
JpegFileBuf_in_a [8-1:0] = memory_controller_in_a[8-1:0];
JpegFileBuf_in_b [8-1:0] = memory_controller_in_b[8-1:0];
decode_block_0_QuantBuff_address_a = memory_controller_address_a [6-1+2:2] & {6{select_decode_block_0_QuantBuff_a}};
decode_block_0_QuantBuff_address_b = memory_controller_address_b [6-1+2:2] & {6{select_decode_block_0_QuantBuff_b}};
decode_block_0_QuantBuff_write_enable_a = memory_controller_write_enable_a & select_decode_block_0_QuantBuff_a;
decode_block_0_QuantBuff_write_enable_b = memory_controller_write_enable_b & select_decode_block_0_QuantBuff_b;
decode_block_0_QuantBuff_in_a [32-1:0] = memory_controller_in_a[32-1:0];
decode_block_0_QuantBuff_in_b [32-1:0] = memory_controller_in_b[32-1:0];
huff_make_dhuff_tb_0_huffsize_address_a = memory_controller_address_a [9-1+2:2] & {9{select_huff_make_dhuff_tb_0_huffsize_a}};
huff_make_dhuff_tb_0_huffsize_address_b = memory_controller_address_b [9-1+2:2] & {9{select_huff_make_dhuff_tb_0_huffsize_b}};
huff_make_dhuff_tb_0_huffsize_write_enable_a = memory_controller_write_enable_a & select_huff_make_dhuff_tb_0_huffsize_a;
huff_make_dhuff_tb_0_huffsize_write_enable_b = memory_controller_write_enable_b & select_huff_make_dhuff_tb_0_huffsize_b;
huff_make_dhuff_tb_0_huffsize_in_a [32-1:0] = memory_controller_in_a[32-1:0];
huff_make_dhuff_tb_0_huffsize_in_b [32-1:0] = memory_controller_in_b[32-1:0];
huff_make_dhuff_tb_0_huffcode_address_a = memory_controller_address_a [9-1+2:2] & {9{select_huff_make_dhuff_tb_0_huffcode_a}};
huff_make_dhuff_tb_0_huffcode_address_b = memory_controller_address_b [9-1+2:2] & {9{select_huff_make_dhuff_tb_0_huffcode_b}};
huff_make_dhuff_tb_0_huffcode_write_enable_a = memory_controller_write_enable_a & select_huff_make_dhuff_tb_0_huffcode_a;
huff_make_dhuff_tb_0_huffcode_write_enable_b = memory_controller_write_enable_b & select_huff_make_dhuff_tb_0_huffcode_b;
huff_make_dhuff_tb_0_huffcode_in_a [32-1:0] = memory_controller_in_a[32-1:0];
huff_make_dhuff_tb_0_huffcode_in_b [32-1:0] = memory_controller_in_b[32-1:0];
main_0_HuffBuff_i_i_address_a = memory_controller_address_a [8-1+2:2] & {8{select_main_0_HuffBuff_i_i_a}};
main_0_HuffBuff_i_i_address_b = memory_controller_address_b [8-1+2:2] & {8{select_main_0_HuffBuff_i_i_b}};
main_0_HuffBuff_i_i_write_enable_a = memory_controller_write_enable_a & select_main_0_HuffBuff_i_i_a;
main_0_HuffBuff_i_i_write_enable_b = memory_controller_write_enable_b & select_main_0_HuffBuff_i_i_b;
main_0_HuffBuff_i_i_in_a [32-1:0] = memory_controller_in_a[32-1:0];
main_0_HuffBuff_i_i_in_b [32-1:0] = memory_controller_in_b[32-1:0];
main_0_IDCTBuff_i_i_address_a = memory_controller_address_a [9-1+2:2] & {9{select_main_0_IDCTBuff_i_i_a}};
main_0_IDCTBuff_i_i_address_b = memory_controller_address_b [9-1+2:2] & {9{select_main_0_IDCTBuff_i_i_b}};
main_0_IDCTBuff_i_i_write_enable_a = memory_controller_write_enable_a & select_main_0_IDCTBuff_i_i_a;
main_0_IDCTBuff_i_i_write_enable_b = memory_controller_write_enable_b & select_main_0_IDCTBuff_i_i_b;
main_0_IDCTBuff_i_i_in_a [32-1:0] = memory_controller_in_a[32-1:0];
main_0_IDCTBuff_i_i_in_b [32-1:0] = memory_controller_in_b[32-1:0];
end
always @(*)
begin
select_not_struct_a [2:0] = 3'b0 | {2{select_out_unread_marker_reg_a}} | {2{select_out_index_get_sof_reg_a}} | {2{select_out_v_samp_factor_get_sof_reg_a}} | {2{select_out_comp_id_get_sos_reg_a}} | {2{select_out_ac_tbl_no_get_sos_reg_a}} | {2{select_out_length_get_dht_reg_a}} | {2{select_out_index_get_dht_reg_a}} | {2{select_out_count_get_dht_reg_a}} | {2{select_out_length_get_dqt_reg_a}} | {2{select_out_prec_get_dht_reg_a}} | {2{select_out_num_get_dht_reg_a}} | {2{select_izigzag_index_reg_a}} | {2{select_main_result_reg_a}} | {1{select_p_jinfo_image_height_reg_a}} | {1{select_p_jinfo_image_width_reg_a}} | {2{select_p_jinfo_ac_xhuff_tbl_bits_reg_a}} | {2{select_p_jinfo_ac_xhuff_tbl_huffval_reg_a}} | {2{select_p_jinfo_dc_xhuff_tbl_bits_reg_a}} | {2{select_p_jinfo_dc_xhuff_tbl_huffval_reg_a}} | {2{select_p_jinfo_quant_tbl_quantval_reg_a}} | {2{select_zigzag_index_reg_a}} | {2{select_p_jinfo_MCUWidth_reg_a}} | {2{select_rgb_buf_reg_a}} | {2{select_CurHuffReadBuf_reg_a}} | {2{select_bit_set_mask_reg_a}} | {2{select_lmask_reg_a}} | {2{select_read_position_reg_a}} | {2{select_current_read_byte_reg_a}} | {2{select_p_jinfo_dc_dhuff_tbl_ml_reg_a}} | {2{select_p_jinfo_dc_dhuff_tbl_maxcode_reg_a}} | {2{select_p_jinfo_dc_dhuff_tbl_mincode_reg_a}} | {2{select_p_jinfo_dc_dhuff_tbl_valptr_reg_a}} | {2{select_extend_mask_reg_a}} | {2{select_p_jinfo_ac_dhuff_tbl_ml_reg_a}} | {2{select_p_jinfo_ac_dhuff_tbl_maxcode_reg_a}} | {2{select_p_jinfo_ac_dhuff_tbl_mincode_reg_a}} | {2{select_p_jinfo_ac_dhuff_tbl_valptr_reg_a}} | {2{select_OutData_comp_vpos_reg_a}} | {2{select_OutData_comp_hpos_reg_a}} | {2{select_decode_block_0_QuantBuff_reg_a}} | {2{select_huff_make_dhuff_tb_0_huffsize_reg_a}} | {2{select_huff_make_dhuff_tb_0_huffcode_reg_a}} | {2{select_main_0_HuffBuff_i_i_reg_a}} | {2{select_main_0_IDCTBuff_i_i_reg_a}};
select_not_struct_b[2:0] = 3'b0 | {2{select_out_unread_marker_reg_b}} | {2{select_out_index_get_sof_reg_b}} | {2{select_out_v_samp_factor_get_sof_reg_b}} | {2{select_out_comp_id_get_sos_reg_b}} | {2{select_out_ac_tbl_no_get_sos_reg_b}} | {2{select_out_length_get_dht_reg_b}} | {2{select_out_index_get_dht_reg_b}} | {2{select_out_count_get_dht_reg_b}} | {2{select_out_length_get_dqt_reg_b}} | {2{select_out_prec_get_dht_reg_b}} | {2{select_out_num_get_dht_reg_b}} | {2{select_izigzag_index_reg_b}} | {2{select_main_result_reg_b}} | {1{select_p_jinfo_image_height_reg_b}} | {1{select_p_jinfo_image_width_reg_b}} | {2{select_p_jinfo_ac_xhuff_tbl_bits_reg_b}} | {2{select_p_jinfo_ac_xhuff_tbl_huffval_reg_b}} | {2{select_p_jinfo_dc_xhuff_tbl_bits_reg_b}} | {2{select_p_jinfo_dc_xhuff_tbl_huffval_reg_b}} | {2{select_p_jinfo_quant_tbl_quantval_reg_b}} | {2{select_zigzag_index_reg_b}} | {2{select_p_jinfo_MCUWidth_reg_b}} | {2{select_rgb_buf_reg_b}} | {2{select_CurHuffReadBuf_reg_b}} | {2{select_bit_set_mask_reg_b}} | {2{select_lmask_reg_b}} | {2{select_read_position_reg_b}} | {2{select_current_read_byte_reg_b}} | {2{select_p_jinfo_dc_dhuff_tbl_ml_reg_b}} | {2{select_p_jinfo_dc_dhuff_tbl_maxcode_reg_b}} | {2{select_p_jinfo_dc_dhuff_tbl_mincode_reg_b}} | {2{select_p_jinfo_dc_dhuff_tbl_valptr_reg_b}} | {2{select_extend_mask_reg_b}} | {2{select_p_jinfo_ac_dhuff_tbl_ml_reg_b}} | {2{select_p_jinfo_ac_dhuff_tbl_maxcode_reg_b}} | {2{select_p_jinfo_ac_dhuff_tbl_mincode_reg_b}} | {2{select_p_jinfo_ac_dhuff_tbl_valptr_reg_b}} | {2{select_OutData_comp_vpos_reg_b}} | {2{select_OutData_comp_hpos_reg_b}} | {2{select_decode_block_0_QuantBuff_reg_b}} | {2{select_huff_make_dhuff_tb_0_huffsize_reg_b}} | {2{select_huff_make_dhuff_tb_0_huffcode_reg_b}} | {2{select_main_0_HuffBuff_i_i_reg_b}} | {2{select_main_0_IDCTBuff_i_i_reg_b}};
if (prevAddr_a[2:0] & select_not_struct_a[2:0] != 0)
begin
$display("Error: memory address not aligned to ram word size!");
$finish;
end
if (prevAddr_b[2:0] & select_not_struct_b[2:0] != 0)
begin
$display("Error: memory address not aligned to ram word size!");
$finish;
end
prevSize_a_and[0] = prevSize_a[1] | prevSize_a[0];
prevSize_a_and[1] = prevSize_a[1];
prevSize_a_and[2] = prevSize_a[1] & prevSize_a[0];
if ((prevAddr_a & prevSize_a_and) != 0)
begin
$display("Error: memory address not aligned to ram size!");
$finish;
end
prevSize_b_and[0] = prevSize_b[1] | prevSize_b[0];
prevSize_b_and[1] = prevSize_b[1];
prevSize_b_and[2] = prevSize_b[1] & prevSize_b[0];
if ((prevAddr_b & prevSize_b_and) != 0)
begin
$display("Error: memory address not aligned to ram size!");
$finish;
end
memory_controller_out_a = 1'b0 | memory_controller_hana_jpg_out_a | memory_controller_hana_bmp_out_a | memory_controller_out_unread_marker_out_a | memory_controller_out_index_get_sof_out_a | memory_controller_out_v_samp_factor_get_sof_out_a | memory_controller_out_comp_id_get_sos_out_a | memory_controller_out_ac_tbl_no_get_sos_out_a | memory_controller_out_length_get_dht_out_a | memory_controller_out_index_get_dht_out_a | memory_controller_out_count_get_dht_out_a | memory_controller_out_length_get_dqt_out_a | memory_controller_out_prec_get_dht_out_a | memory_controller_out_num_get_dht_out_a | memory_controller_izigzag_index_out_a | memory_controller_main_result_out_a | memory_controller_p_jinfo_image_height_out_a | memory_controller_p_jinfo_image_width_out_a | memory_controller_p_jinfo_comps_info_index_out_a | memory_controller_p_jinfo_comps_info_id_out_a | memory_controller_p_jinfo_comps_info_h_samp_factor_out_a | memory_controller_p_jinfo_comps_info_v_samp_factor_out_a | memory_controller_p_jinfo_comps_info_quant_tbl_no_out_a | memory_controller_p_jinfo_comps_info_dc_tbl_no_out_a | memory_controller_p_jinfo_comps_info_ac_tbl_no_out_a | memory_controller_p_jinfo_ac_xhuff_tbl_bits_out_a | memory_controller_p_jinfo_ac_xhuff_tbl_huffval_out_a | memory_controller_p_jinfo_dc_xhuff_tbl_bits_out_a | memory_controller_p_jinfo_dc_xhuff_tbl_huffval_out_a | memory_controller_p_jinfo_quant_tbl_quantval_out_a | memory_controller_zigzag_index_out_a | memory_controller_p_jinfo_MCUWidth_out_a | memory_controller_rgb_buf_out_a | memory_controller_CurHuffReadBuf_out_a | memory_controller_OutData_comp_buf_out_a | memory_controller_bit_set_mask_out_a | memory_controller_lmask_out_a | memory_controller_read_position_out_a | memory_controller_current_read_byte_out_a | memory_controller_p_jinfo_dc_dhuff_tbl_ml_out_a | memory_controller_p_jinfo_dc_dhuff_tbl_maxcode_out_a | memory_controller_p_jinfo_dc_dhuff_tbl_mincode_out_a | memory_controller_p_jinfo_dc_dhuff_tbl_valptr_out_a | memory_controller_extend_mask_out_a | memory_controller_p_jinfo_ac_dhuff_tbl_ml_out_a | memory_controller_p_jinfo_ac_dhuff_tbl_maxcode_out_a | memory_controller_p_jinfo_ac_dhuff_tbl_mincode_out_a | memory_controller_p_jinfo_ac_dhuff_tbl_valptr_out_a | memory_controller_OutData_comp_vpos_out_a | memory_controller_OutData_comp_hpos_out_a | memory_controller_JpegFileBuf_out_a | memory_controller_decode_block_0_QuantBuff_out_a | memory_controller_huff_make_dhuff_tb_0_huffsize_out_a | memory_controller_huff_make_dhuff_tb_0_huffcode_out_a | memory_controller_main_0_HuffBuff_i_i_out_a | memory_controller_main_0_IDCTBuff_i_i_out_a;
memory_controller_out_b = 1'b0 | memory_controller_hana_jpg_out_b | memory_controller_hana_bmp_out_b | memory_controller_out_unread_marker_out_b | memory_controller_out_index_get_sof_out_b | memory_controller_out_v_samp_factor_get_sof_out_b | memory_controller_out_comp_id_get_sos_out_b | memory_controller_out_ac_tbl_no_get_sos_out_b | memory_controller_out_length_get_dht_out_b | memory_controller_out_index_get_dht_out_b | memory_controller_out_count_get_dht_out_b | memory_controller_out_length_get_dqt_out_b | memory_controller_out_prec_get_dht_out_b | memory_controller_out_num_get_dht_out_b | memory_controller_izigzag_index_out_b | memory_controller_main_result_out_b | memory_controller_p_jinfo_image_height_out_b | memory_controller_p_jinfo_image_width_out_b | memory_controller_p_jinfo_comps_info_index_out_b | memory_controller_p_jinfo_comps_info_id_out_b | memory_controller_p_jinfo_comps_info_h_samp_factor_out_b | memory_controller_p_jinfo_comps_info_v_samp_factor_out_b | memory_controller_p_jinfo_comps_info_quant_tbl_no_out_b | memory_controller_p_jinfo_comps_info_dc_tbl_no_out_b | memory_controller_p_jinfo_comps_info_ac_tbl_no_out_b | memory_controller_p_jinfo_ac_xhuff_tbl_bits_out_b | memory_controller_p_jinfo_ac_xhuff_tbl_huffval_out_b | memory_controller_p_jinfo_dc_xhuff_tbl_bits_out_b | memory_controller_p_jinfo_dc_xhuff_tbl_huffval_out_b | memory_controller_p_jinfo_quant_tbl_quantval_out_b | memory_controller_zigzag_index_out_b | memory_controller_p_jinfo_MCUWidth_out_b | memory_controller_rgb_buf_out_b | memory_controller_CurHuffReadBuf_out_b | memory_controller_OutData_comp_buf_out_b | memory_controller_bit_set_mask_out_b | memory_controller_lmask_out_b | memory_controller_read_position_out_b | memory_controller_current_read_byte_out_b | memory_controller_p_jinfo_dc_dhuff_tbl_ml_out_b | memory_controller_p_jinfo_dc_dhuff_tbl_maxcode_out_b | memory_controller_p_jinfo_dc_dhuff_tbl_mincode_out_b | memory_controller_p_jinfo_dc_dhuff_tbl_valptr_out_b | memory_controller_extend_mask_out_b | memory_controller_p_jinfo_ac_dhuff_tbl_ml_out_b | memory_controller_p_jinfo_ac_dhuff_tbl_maxcode_out_b | memory_controller_p_jinfo_ac_dhuff_tbl_mincode_out_b | memory_controller_p_jinfo_ac_dhuff_tbl_valptr_out_b | memory_controller_OutData_comp_vpos_out_b | memory_controller_OutData_comp_hpos_out_b | memory_controller_JpegFileBuf_out_b | memory_controller_decode_block_0_QuantBuff_out_b | memory_controller_huff_make_dhuff_tb_0_huffsize_out_b | memory_controller_huff_make_dhuff_tb_0_huffcode_out_b | memory_controller_main_0_HuffBuff_i_i_out_b | memory_controller_main_0_IDCTBuff_i_i_out_b;
end
always @(posedge clk)
begin
memory_controller_out_reg_a <= memory_controller_out_a;
memory_controller_out_reg_b <= memory_controller_out_b;
select_hana_jpg_reg_a <= select_hana_jpg_a;
select_hana_jpg_reg_b <= select_hana_jpg_b;
select_hana_bmp_reg_a <= select_hana_bmp_a;
select_hana_bmp_reg_b <= select_hana_bmp_b;
select_out_unread_marker_reg_a <= select_out_unread_marker_a;
select_out_unread_marker_reg_b <= select_out_unread_marker_b;
select_out_index_get_sof_reg_a <= select_out_index_get_sof_a;
select_out_index_get_sof_reg_b <= select_out_index_get_sof_b;
select_out_v_samp_factor_get_sof_reg_a <= select_out_v_samp_factor_get_sof_a;
select_out_v_samp_factor_get_sof_reg_b <= select_out_v_samp_factor_get_sof_b;
select_out_comp_id_get_sos_reg_a <= select_out_comp_id_get_sos_a;
select_out_comp_id_get_sos_reg_b <= select_out_comp_id_get_sos_b;
select_out_ac_tbl_no_get_sos_reg_a <= select_out_ac_tbl_no_get_sos_a;
select_out_ac_tbl_no_get_sos_reg_b <= select_out_ac_tbl_no_get_sos_b;
select_out_length_get_dht_reg_a <= select_out_length_get_dht_a;
select_out_length_get_dht_reg_b <= select_out_length_get_dht_b;
select_out_index_get_dht_reg_a <= select_out_index_get_dht_a;
select_out_index_get_dht_reg_b <= select_out_index_get_dht_b;
select_out_count_get_dht_reg_a <= select_out_count_get_dht_a;
select_out_count_get_dht_reg_b <= select_out_count_get_dht_b;
select_out_length_get_dqt_reg_a <= select_out_length_get_dqt_a;
select_out_length_get_dqt_reg_b <= select_out_length_get_dqt_b;
select_out_prec_get_dht_reg_a <= select_out_prec_get_dht_a;
select_out_prec_get_dht_reg_b <= select_out_prec_get_dht_b;
select_out_num_get_dht_reg_a <= select_out_num_get_dht_a;
select_out_num_get_dht_reg_b <= select_out_num_get_dht_b;
select_izigzag_index_reg_a <= select_izigzag_index_a;
select_izigzag_index_reg_b <= select_izigzag_index_b;
select_main_result_reg_a <= select_main_result_a;
select_main_result_reg_b <= select_main_result_b;
select_p_jinfo_image_height_reg_a <= select_p_jinfo_image_height_a;
select_p_jinfo_image_height_reg_b <= select_p_jinfo_image_height_b;
select_p_jinfo_image_width_reg_a <= select_p_jinfo_image_width_a;
select_p_jinfo_image_width_reg_b <= select_p_jinfo_image_width_b;
select_p_jinfo_comps_info_index_reg_a <= select_p_jinfo_comps_info_index_a;
select_p_jinfo_comps_info_index_reg_b <= select_p_jinfo_comps_info_index_b;
select_p_jinfo_comps_info_id_reg_a <= select_p_jinfo_comps_info_id_a;
select_p_jinfo_comps_info_id_reg_b <= select_p_jinfo_comps_info_id_b;
select_p_jinfo_comps_info_h_samp_factor_reg_a <= select_p_jinfo_comps_info_h_samp_factor_a;
select_p_jinfo_comps_info_h_samp_factor_reg_b <= select_p_jinfo_comps_info_h_samp_factor_b;
select_p_jinfo_comps_info_v_samp_factor_reg_a <= select_p_jinfo_comps_info_v_samp_factor_a;
select_p_jinfo_comps_info_v_samp_factor_reg_b <= select_p_jinfo_comps_info_v_samp_factor_b;
select_p_jinfo_comps_info_quant_tbl_no_reg_a <= select_p_jinfo_comps_info_quant_tbl_no_a;
select_p_jinfo_comps_info_quant_tbl_no_reg_b <= select_p_jinfo_comps_info_quant_tbl_no_b;
select_p_jinfo_comps_info_dc_tbl_no_reg_a <= select_p_jinfo_comps_info_dc_tbl_no_a;
select_p_jinfo_comps_info_dc_tbl_no_reg_b <= select_p_jinfo_comps_info_dc_tbl_no_b;
select_p_jinfo_comps_info_ac_tbl_no_reg_a <= select_p_jinfo_comps_info_ac_tbl_no_a;
select_p_jinfo_comps_info_ac_tbl_no_reg_b <= select_p_jinfo_comps_info_ac_tbl_no_b;
select_p_jinfo_ac_xhuff_tbl_bits_reg_a <= select_p_jinfo_ac_xhuff_tbl_bits_a;
select_p_jinfo_ac_xhuff_tbl_bits_reg_b <= select_p_jinfo_ac_xhuff_tbl_bits_b;
select_p_jinfo_ac_xhuff_tbl_huffval_reg_a <= select_p_jinfo_ac_xhuff_tbl_huffval_a;
select_p_jinfo_ac_xhuff_tbl_huffval_reg_b <= select_p_jinfo_ac_xhuff_tbl_huffval_b;
select_p_jinfo_dc_xhuff_tbl_bits_reg_a <= select_p_jinfo_dc_xhuff_tbl_bits_a;
select_p_jinfo_dc_xhuff_tbl_bits_reg_b <= select_p_jinfo_dc_xhuff_tbl_bits_b;
select_p_jinfo_dc_xhuff_tbl_huffval_reg_a <= select_p_jinfo_dc_xhuff_tbl_huffval_a;
select_p_jinfo_dc_xhuff_tbl_huffval_reg_b <= select_p_jinfo_dc_xhuff_tbl_huffval_b;
select_p_jinfo_quant_tbl_quantval_reg_a <= select_p_jinfo_quant_tbl_quantval_a;
select_p_jinfo_quant_tbl_quantval_reg_b <= select_p_jinfo_quant_tbl_quantval_b;
select_zigzag_index_reg_a <= select_zigzag_index_a;
select_zigzag_index_reg_b <= select_zigzag_index_b;
select_p_jinfo_MCUWidth_reg_a <= select_p_jinfo_MCUWidth_a;
select_p_jinfo_MCUWidth_reg_b <= select_p_jinfo_MCUWidth_b;
select_rgb_buf_reg_a <= select_rgb_buf_a;
select_rgb_buf_reg_b <= select_rgb_buf_b;
select_CurHuffReadBuf_reg_a <= select_CurHuffReadBuf_a;
select_CurHuffReadBuf_reg_b <= select_CurHuffReadBuf_b;
select_OutData_comp_buf_reg_a <= select_OutData_comp_buf_a;
select_OutData_comp_buf_reg_b <= select_OutData_comp_buf_b;
select_bit_set_mask_reg_a <= select_bit_set_mask_a;
select_bit_set_mask_reg_b <= select_bit_set_mask_b;
select_lmask_reg_a <= select_lmask_a;
select_lmask_reg_b <= select_lmask_b;
select_read_position_reg_a <= select_read_position_a;
select_read_position_reg_b <= select_read_position_b;
select_current_read_byte_reg_a <= select_current_read_byte_a;
select_current_read_byte_reg_b <= select_current_read_byte_b;
select_p_jinfo_dc_dhuff_tbl_ml_reg_a <= select_p_jinfo_dc_dhuff_tbl_ml_a;
select_p_jinfo_dc_dhuff_tbl_ml_reg_b <= select_p_jinfo_dc_dhuff_tbl_ml_b;
select_p_jinfo_dc_dhuff_tbl_maxcode_reg_a <= select_p_jinfo_dc_dhuff_tbl_maxcode_a;
select_p_jinfo_dc_dhuff_tbl_maxcode_reg_b <= select_p_jinfo_dc_dhuff_tbl_maxcode_b;
select_p_jinfo_dc_dhuff_tbl_mincode_reg_a <= select_p_jinfo_dc_dhuff_tbl_mincode_a;
select_p_jinfo_dc_dhuff_tbl_mincode_reg_b <= select_p_jinfo_dc_dhuff_tbl_mincode_b;
select_p_jinfo_dc_dhuff_tbl_valptr_reg_a <= select_p_jinfo_dc_dhuff_tbl_valptr_a;
select_p_jinfo_dc_dhuff_tbl_valptr_reg_b <= select_p_jinfo_dc_dhuff_tbl_valptr_b;
select_extend_mask_reg_a <= select_extend_mask_a;
select_extend_mask_reg_b <= select_extend_mask_b;
select_p_jinfo_ac_dhuff_tbl_ml_reg_a <= select_p_jinfo_ac_dhuff_tbl_ml_a;
select_p_jinfo_ac_dhuff_tbl_ml_reg_b <= select_p_jinfo_ac_dhuff_tbl_ml_b;
select_p_jinfo_ac_dhuff_tbl_maxcode_reg_a <= select_p_jinfo_ac_dhuff_tbl_maxcode_a;
select_p_jinfo_ac_dhuff_tbl_maxcode_reg_b <= select_p_jinfo_ac_dhuff_tbl_maxcode_b;
select_p_jinfo_ac_dhuff_tbl_mincode_reg_a <= select_p_jinfo_ac_dhuff_tbl_mincode_a;
select_p_jinfo_ac_dhuff_tbl_mincode_reg_b <= select_p_jinfo_ac_dhuff_tbl_mincode_b;
select_p_jinfo_ac_dhuff_tbl_valptr_reg_a <= select_p_jinfo_ac_dhuff_tbl_valptr_a;
select_p_jinfo_ac_dhuff_tbl_valptr_reg_b <= select_p_jinfo_ac_dhuff_tbl_valptr_b;
select_OutData_comp_vpos_reg_a <= select_OutData_comp_vpos_a;
select_OutData_comp_vpos_reg_b <= select_OutData_comp_vpos_b;
select_OutData_comp_hpos_reg_a <= select_OutData_comp_hpos_a;
select_OutData_comp_hpos_reg_b <= select_OutData_comp_hpos_b;
select_JpegFileBuf_reg_a <= select_JpegFileBuf_a;
select_JpegFileBuf_reg_b <= select_JpegFileBuf_b;
select_decode_block_0_QuantBuff_reg_a <= select_decode_block_0_QuantBuff_a;
select_decode_block_0_QuantBuff_reg_b <= select_decode_block_0_QuantBuff_b;
select_huff_make_dhuff_tb_0_huffsize_reg_a <= select_huff_make_dhuff_tb_0_huffsize_a;
select_huff_make_dhuff_tb_0_huffsize_reg_b <= select_huff_make_dhuff_tb_0_huffsize_b;
select_huff_make_dhuff_tb_0_huffcode_reg_a <= select_huff_make_dhuff_tb_0_huffcode_a;
select_huff_make_dhuff_tb_0_huffcode_reg_b <= select_huff_make_dhuff_tb_0_huffcode_b;
select_main_0_HuffBuff_i_i_reg_a <= select_main_0_HuffBuff_i_i_a;
select_main_0_HuffBuff_i_i_reg_b <= select_main_0_HuffBuff_i_i_b;
select_main_0_IDCTBuff_i_i_reg_a <= select_main_0_IDCTBuff_i_i_a;
select_main_0_IDCTBuff_i_i_reg_b <= select_main_0_IDCTBuff_i_i_b;
end
endmodule
`timescale 1 ns / 1 ns
module Write4Blocks
(
clk,
reset,
start,
finish,
arg_store1,
arg_store2,
arg_store3,
arg_store4,
arg_p_out_vpos,
arg_p_out_hpos,
arg_p_out_buf,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [5:0] LEGUP_0 = 6'd0;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_1 = 6'd1;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_2 = 6'd2;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_3 = 6'd3;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_4 = 6'd4;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_5 = 6'd5;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_6 = 6'd6;
parameter [5:0] LEGUP_F_Write4Blocks_BB1_7 = 6'd7;
parameter [5:0] LEGUP_F_Write4Blocks_BB1_8 = 6'd8;
parameter [5:0] LEGUP_F_Write4Blocks_BB1_9 = 6'd9;
parameter [5:0] LEGUP_F_Write4Blocks_BB2_10 = 6'd10;
parameter [5:0] LEGUP_F_Write4Blocks_BB3_11 = 6'd11;
parameter [5:0] LEGUP_F_Write4Blocks_BB3_12 = 6'd12;
parameter [5:0] LEGUP_F_Write4Blocks_BB3_13 = 6'd13;
parameter [5:0] LEGUP_F_Write4Blocks_BB4_14 = 6'd14;
parameter [5:0] LEGUP_F_Write4Blocks_BB5_15 = 6'd15;
parameter [5:0] LEGUP_F_Write4Blocks_BB6_16 = 6'd16;
parameter [5:0] LEGUP_F_Write4Blocks_BB7_17 = 6'd17;
parameter [5:0] LEGUP_F_Write4Blocks_BB7_18 = 6'd18;
parameter [5:0] LEGUP_F_Write4Blocks_BB7_19 = 6'd19;
parameter [5:0] LEGUP_F_Write4Blocks_BB8_20 = 6'd20;
parameter [5:0] LEGUP_F_Write4Blocks_BB9_21 = 6'd21;
parameter [5:0] LEGUP_F_Write4Blocks_BB9_22 = 6'd22;
parameter [5:0] LEGUP_F_Write4Blocks_BB9_23 = 6'd23;
parameter [5:0] LEGUP_F_Write4Blocks_BB10_24 = 6'd24;
parameter [5:0] LEGUP_F_Write4Blocks_BB11_25 = 6'd25;
parameter [5:0] LEGUP_F_Write4Blocks_BB12_26 = 6'd26;
parameter [5:0] LEGUP_F_Write4Blocks_BB12_27 = 6'd27;
parameter [5:0] LEGUP_F_Write4Blocks_BB12_28 = 6'd28;
parameter [5:0] LEGUP_F_Write4Blocks_BB13_29 = 6'd29;
parameter [5:0] LEGUP_F_Write4Blocks_BB14_30 = 6'd30;
parameter [5:0] LEGUP_F_Write4Blocks_BB14_31 = 6'd31;
parameter [5:0] LEGUP_F_Write4Blocks_BB14_32 = 6'd32;
parameter [5:0] LEGUP_F_Write4Blocks_BB15_33 = 6'd33;
parameter [5:0] LEGUP_F_Write4Blocks_BB16_34 = 6'd34;
parameter [5:0] LEGUP_F_Write4Blocks_BB17_35 = 6'd35;
parameter [5:0] LEGUP_F_Write4Blocks_BB17_36 = 6'd36;
parameter [5:0] LEGUP_F_Write4Blocks_BB17_37 = 6'd37;
parameter [5:0] LEGUP_F_Write4Blocks_BB18_38 = 6'd38;
parameter [5:0] LEGUP_F_Write4Blocks_BB19_39 = 6'd39;
parameter [5:0] LEGUP_F_Write4Blocks_BB19_40 = 6'd40;
parameter [5:0] LEGUP_F_Write4Blocks_BB19_41 = 6'd41;
parameter [5:0] LEGUP_F_Write4Blocks_BB20_42 = 6'd42;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_43 = 6'd43;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_44 = 6'd44;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_45 = 6'd45;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_46 = 6'd46;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_47 = 6'd47;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_48 = 6'd48;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_49 = 6'd49;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_50 = 6'd50;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_51 = 6'd51;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_52 = 6'd52;
parameter [5:0] LEGUP_F_Write4Blocks_BB22_53 = 6'd53;
parameter [5:0] LEGUP_F_Write4Blocks_BB23_54 = 6'd54;
parameter [5:0] LEGUP_F_Write4Blocks_BB24_55 = 6'd55;
input clk;
input reset;
input start;
output reg finish;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_store1;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_store2;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_store3;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_store4;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_out_vpos;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_out_hpos;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_out_buf;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [5:0] cur_state;
reg [31:0] Write4Blocks_0_1;
reg [31:0] Write4Blocks_0_1_reg;
reg [31:0] Write4Blocks_0_2;
reg [31:0] Write4Blocks_0_2_reg;
reg [31:0] Write4Blocks_0_3;
reg [31:0] Write4Blocks_0_4;
reg [31:0] Write4Blocks_0_4_reg;
reg [15:0] Write4Blocks_0_5;
reg [31:0] Write4Blocks_0_6;
reg [31:0] Write4Blocks_0_6_reg;
reg [15:0] Write4Blocks_0_7;
reg [31:0] Write4Blocks_0_8;
reg [31:0] Write4Blocks_0_8_reg;
reg Write4Blocks_0_9;
reg Write4Blocks_0_9_reg;
reg Write4Blocks_0_10;
reg Write4Blocks_0_10_reg;
reg Write4Blocks_0_or_cond_i;
reg [31:0] Write4Blocks_0_tmp287;
reg [31:0] Write4Blocks_0_tmp287_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp288340;
reg Write4Blocks__lr_ph8_split_us_i_tmp289;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_smax290;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp291;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp291_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp293;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp293_reg;
reg Write4Blocks__lr_ph8_split_us_i_tmp294;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_umax295;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp296;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp296_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp307;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp308341;
reg Write4Blocks__lr_ph8_split_us_i_tmp309;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_smax310;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_smax310_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp311;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp313;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp313_reg;
reg Write4Blocks__lr_ph8_split_us_i_tmp314;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_umax315;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_umax315_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp316;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp316_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp332;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp333;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp334;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp334_reg;
reg [31:0] Write4Blocks_11_indvar_next18_i;
reg Write4Blocks_11_exitcond317;
reg [31:0] Write4Blocks_12_indvar_i;
reg [31:0] Write4Blocks_12_tmp330;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_12__14_us_i;
reg [31:0] Write4Blocks_12_tmp336;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_12_scevgep24_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_12_scevgep24_i_reg;
reg [31:0] Write4Blocks_12_13;
reg [7:0] Write4Blocks_12_14;
reg [31:0] Write4Blocks_12_indvar_next_i;
reg [31:0] Write4Blocks_12_indvar_next_i_reg;
reg Write4Blocks_12_exitcond297;
reg Write4Blocks_12_exitcond297_reg;
reg [31:0] Write4Blocks__lr_ph_us_i_indvar17_i;
reg [31:0] Write4Blocks__lr_ph_us_i_indvar17_i_reg;
reg [31:0] Write4Blocks__lr_ph_us_i_tmp329;
reg [31:0] Write4Blocks__lr_ph_us_i_tmp329_reg;
reg [31:0] Write4Blocks__lr_ph_us_i_tmp331;
reg [31:0] Write4Blocks__lr_ph_us_i_tmp335;
reg [31:0] Write4Blocks__lr_ph_us_i_tmp335_reg;
reg Write4Blocks_WriteOneBlock_exit_15;
reg Write4Blocks_WriteOneBlock_exit_15_reg;
reg Write4Blocks_WriteOneBlock_exit_or_cond_i75;
reg [31:0] Write4Blocks_WriteOneBlock_exit_WriteOneBlock_exit111_crit_edge__pre349;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp232;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp233;
reg Write4Blocks__lr_ph8_split_us_i96_tmp234;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_smax235;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_smax235_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp236;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp238;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp238_reg;
reg Write4Blocks__lr_ph8_split_us_i96_tmp239;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_umax240;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_umax240_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp241;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp241_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp254;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp254_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp255339;
reg Write4Blocks__lr_ph8_split_us_i96_tmp256;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_smax257;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_smax257_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp258;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp260;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp260_reg;
reg Write4Blocks__lr_ph8_split_us_i96_tmp261;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_umax262;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_umax262_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp263;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp263_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp280;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp281;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp282;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp282_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp283;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp283_reg;
reg [31:0] Write4Blocks_16_indvar_next18_i98;
reg Write4Blocks_16_exitcond264;
reg [31:0] Write4Blocks_17_indvar_i100;
reg [31:0] Write4Blocks_17_tmp278;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_17__14_us_i103;
reg [31:0] Write4Blocks_17_tmp285;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_17_scevgep24_i102;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_17_scevgep24_i102_reg;
reg [31:0] Write4Blocks_17_18;
reg [7:0] Write4Blocks_17_19;
reg [31:0] Write4Blocks_17_indvar_next_i104;
reg [31:0] Write4Blocks_17_indvar_next_i104_reg;
reg Write4Blocks_17_exitcond242;
reg Write4Blocks_17_exitcond242_reg;
reg [31:0] Write4Blocks__lr_ph_us_i110_indvar17_i106;
reg [31:0] Write4Blocks__lr_ph_us_i110_indvar17_i106_reg;
reg [31:0] Write4Blocks__lr_ph_us_i110_tmp277;
reg [31:0] Write4Blocks__lr_ph_us_i110_tmp277_reg;
reg [31:0] Write4Blocks__lr_ph_us_i110_tmp279;
reg [31:0] Write4Blocks__lr_ph_us_i110_tmp284;
reg [31:0] Write4Blocks__lr_ph_us_i110_tmp284_reg;
reg [31:0] Write4Blocks_WriteOneBlock_exit111__pre_phi350;
reg [31:0] Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg;
reg Write4Blocks_WriteOneBlock_exit111_20;
reg Write4Blocks_WriteOneBlock_exit111_20_reg;
reg Write4Blocks_WriteOneBlock_exit111_or_cond_i38;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp179337;
reg Write4Blocks__lr_ph8_split_us_i59_tmp180;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_smax181;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp182;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp182_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp184;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp184_reg;
reg Write4Blocks__lr_ph8_split_us_i59_tmp185;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_umax186;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp187;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp187_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp199;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp200;
reg Write4Blocks__lr_ph8_split_us_i59_tmp201;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_smax202;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_smax202_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp203;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp206;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp206_reg;
reg Write4Blocks__lr_ph8_split_us_i59_tmp207;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_umax208;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_umax208_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp209;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp209_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp226;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp227;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp227_reg;
reg [31:0] Write4Blocks_21_indvar_next18_i61;
reg Write4Blocks_21_exitcond210;
reg [31:0] Write4Blocks_22_indvar_i63;
reg [31:0] Write4Blocks_22_tmp223;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_22__14_us_i66;
reg [31:0] Write4Blocks_22_tmp229;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_22_scevgep24_i65;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_22_scevgep24_i65_reg;
reg [31:0] Write4Blocks_22_23;
reg [7:0] Write4Blocks_22_24;
reg [31:0] Write4Blocks_22_indvar_next_i67;
reg [31:0] Write4Blocks_22_indvar_next_i67_reg;
reg Write4Blocks_22_exitcond188;
reg Write4Blocks_22_exitcond188_reg;
reg [31:0] Write4Blocks__lr_ph_us_i73_indvar17_i69;
reg [31:0] Write4Blocks__lr_ph_us_i73_indvar17_i69_reg;
reg [31:0] Write4Blocks__lr_ph_us_i73_tmp222;
reg [31:0] Write4Blocks__lr_ph_us_i73_tmp222_reg;
reg [31:0] Write4Blocks__lr_ph_us_i73_tmp224;
reg [31:0] Write4Blocks__lr_ph_us_i73_tmp228;
reg [31:0] Write4Blocks__lr_ph_us_i73_tmp228_reg;
reg Write4Blocks_WriteOneBlock_exit74_or_cond_i1;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp125;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp126;
reg Write4Blocks__lr_ph8_split_us_i22_tmp127;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_smax;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_smax_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp128;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp130;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp130_reg;
reg Write4Blocks__lr_ph8_split_us_i22_tmp131;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_umax;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_umax_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp132;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp132_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp144;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp145;
reg Write4Blocks__lr_ph8_split_us_i22_tmp146;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_smax147;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_smax147_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp148;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp151;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp151_reg;
reg Write4Blocks__lr_ph8_split_us_i22_tmp152;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_umax153;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_umax153_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp154;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp154_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp172;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp173;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp174;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp174_reg;
reg [31:0] Write4Blocks_25_indvar_next18_i24;
reg Write4Blocks_25_exitcond155;
reg [31:0] Write4Blocks_26_indvar_i26;
reg [31:0] Write4Blocks_26_tmp169;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_26__14_us_i29;
reg [31:0] Write4Blocks_26_tmp176;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_26_scevgep24_i28;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_26_scevgep24_i28_reg;
reg [31:0] Write4Blocks_26_27;
reg [7:0] Write4Blocks_26_28;
reg [31:0] Write4Blocks_26_indvar_next_i30;
reg [31:0] Write4Blocks_26_indvar_next_i30_reg;
reg Write4Blocks_26_exitcond;
reg Write4Blocks_26_exitcond_reg;
reg [31:0] Write4Blocks__lr_ph_us_i36_indvar17_i32;
reg [31:0] Write4Blocks__lr_ph_us_i36_indvar17_i32_reg;
reg [31:0] Write4Blocks__lr_ph_us_i36_tmp168;
reg [31:0] Write4Blocks__lr_ph_us_i36_tmp168_reg;
reg [31:0] Write4Blocks__lr_ph_us_i36_tmp170;
reg [31:0] Write4Blocks__lr_ph_us_i36_tmp175;
reg [31:0] Write4Blocks__lr_ph_us_i36_tmp175_reg;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_29;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_30;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_31;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_31_reg;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_32;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_33;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_33_reg;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_34;
reg Write4Blocks_WriteOneBlock_exit37_35;
reg [31:0] Write4Blocks_signed_multiply_32_0_op0;
reg [31:0] Write4Blocks_signed_multiply_32_0_op1;
reg [31:0] Write4Blocks_signed_multiply_32_0;
reg [31:0] Write4Blocks_signed_multiply_32_1_op0;
reg [31:0] Write4Blocks_signed_multiply_32_1_op1;
reg [31:0] Write4Blocks_signed_multiply_32_1;
reg [31:0] Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp;
reg [31:0] Write4Blocks_12_indvar_i_phi_temp;
reg [31:0] Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
reg [31:0] Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp;
reg [31:0] Write4Blocks_17_indvar_i100_phi_temp;
reg [31:0] Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp;
reg [31:0] Write4Blocks_22_indvar_i63_phi_temp;
reg [31:0] Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp;
reg [31:0] Write4Blocks_26_indvar_i26_phi_temp;
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 6'd0;
if (^reset !== 1'bX && ^(6'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_3 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_4;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_4;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_4 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_5;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_5;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_6;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_6;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_6 & memory_controller_waitrequest == 1'd0 & Write4Blocks_0_or_cond_i == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_7;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_6 & memory_controller_waitrequest == 1'd0 & Write4Blocks_0_or_cond_i == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB5_15;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB5_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_7;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_7 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_8;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_8;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_8 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_9;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_9;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_9 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB4_14;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB4_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB2_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB2_10;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB2_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB2_10 & memory_controller_waitrequest == 1'd0 & Write4Blocks_11_exitcond317 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB5_15;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB5_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB2_10 & memory_controller_waitrequest == 1'd0 & Write4Blocks_11_exitcond317 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB4_14;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB4_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_11;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_12;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_12;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_12 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_13 & memory_controller_waitrequest == 1'd0 & Write4Blocks_12_exitcond297_reg == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB2_10;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB2_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_13 & memory_controller_waitrequest == 1'd0 & Write4Blocks_12_exitcond297_reg == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_11;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB4_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB4_14;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB4_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB4_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_11;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB5_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB5_15;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB5_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB5_15 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit_or_cond_i75 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_17;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB5_15 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit_or_cond_i75 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB6_16;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB6_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB6_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB6_16;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB6_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB6_16 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB11_25;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB11_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_17;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_17 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_18;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_18;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_18 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_19;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_19;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB10_24;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB10_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB8_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB8_20;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB8_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB8_20 & memory_controller_waitrequest == 1'd0 & Write4Blocks_16_exitcond264 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB11_25;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB11_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB8_20 & memory_controller_waitrequest == 1'd0 & Write4Blocks_16_exitcond264 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB10_24;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB10_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_21;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_21 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_22;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_22;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_22 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_23;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_23;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_23 & memory_controller_waitrequest == 1'd0 & Write4Blocks_17_exitcond242_reg == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB8_20;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB8_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_23 & memory_controller_waitrequest == 1'd0 & Write4Blocks_17_exitcond242_reg == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_21;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB10_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB10_24;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB10_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB10_24 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_21;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB11_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB11_25;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB11_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB11_25 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit111_or_cond_i38 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_26;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB11_25 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit111_or_cond_i38 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB16_34;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB16_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_26;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_26 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_27;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_27;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_27 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_28;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_28;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_28 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB15_33;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB15_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB13_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB13_29;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB13_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB13_29 & memory_controller_waitrequest == 1'd0 & Write4Blocks_21_exitcond210 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB16_34;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB16_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB13_29 & memory_controller_waitrequest == 1'd0 & Write4Blocks_21_exitcond210 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB15_33;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB15_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_30;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_30 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_31;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_31;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_32;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_32;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_32 & memory_controller_waitrequest == 1'd0 & Write4Blocks_22_exitcond188_reg == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB13_29;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB13_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_32 & memory_controller_waitrequest == 1'd0 & Write4Blocks_22_exitcond188_reg == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_30;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB15_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB15_33;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB15_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB15_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_30;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB16_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB16_34;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB16_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB16_34 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit74_or_cond_i1 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_35;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB16_34 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit74_or_cond_i1 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_43;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_35;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_35 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_36;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_36;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_36 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_37;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_37;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB20_42;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB20_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB18_38 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB18_38;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB18_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB18_38 & memory_controller_waitrequest == 1'd0 & Write4Blocks_25_exitcond155 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_43;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB18_38 & memory_controller_waitrequest == 1'd0 & Write4Blocks_25_exitcond155 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB20_42;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB20_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_39 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_39;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_39 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_40;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_40 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_40;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_40 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_41;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_41 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_41;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_41 & memory_controller_waitrequest == 1'd0 & Write4Blocks_26_exitcond_reg == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB18_38;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB18_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_41 & memory_controller_waitrequest == 1'd0 & Write4Blocks_26_exitcond_reg == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_39;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB20_42 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB20_42;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB20_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB20_42 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_39;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_43 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_43;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_43 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_44;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_44 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_44;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_44 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_45;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_45 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_45;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_45 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_46;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_46 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_46;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_46 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_47;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_47 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_47;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_47 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_48;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_48 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_48;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_48 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_49;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_49 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_49;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_49 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_50;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_50 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_50;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_50 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_51;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_51 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_51;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_51 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_52;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_52 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_52;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_52 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit37_35 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB22_53;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB22_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_52 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit37_35 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB23_54;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB23_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB22_53 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB22_53;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB22_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB22_53 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB24_55;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB24_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB23_54 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB23_54;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB23_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB23_54 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB24_55;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB24_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB24_55 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB24_55;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB24_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB24_55 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
begin
Write4Blocks_0_1 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
Write4Blocks_0_1_reg <= Write4Blocks_0_1;
if (^reset !== 1'bX && ^(Write4Blocks_0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_1_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %2 = shl nsw i32 %1, 3*/
begin
Write4Blocks_0_2 = Write4Blocks_0_1 <<< 32'd3 % 32;
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %2 = shl nsw i32 %1, 3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
Write4Blocks_0_2_reg <= Write4Blocks_0_2;
if (^reset !== 1'bX && ^(Write4Blocks_0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_2_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %3 = load i32* %p_out_hpos, align 4, !tbaa !0*/
begin
Write4Blocks_0_3 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %4 = shl nsw i32 %3, 3*/
begin
Write4Blocks_0_4 = Write4Blocks_0_3 <<< 32'd3 % 32;
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %4 = shl nsw i32 %3, 3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
Write4Blocks_0_4_reg <= Write4Blocks_0_4;
if (^reset !== 1'bX && ^(Write4Blocks_0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_4_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %5 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
begin
Write4Blocks_0_5 = memory_controller_out[15:0];
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %6 = sext i16 %5 to i32*/
begin
Write4Blocks_0_6 = $signed(Write4Blocks_0_5);
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %6 = sext i16 %5 to i32*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_5)
begin
Write4Blocks_0_6_reg <= Write4Blocks_0_6;
if (^reset !== 1'bX && ^(Write4Blocks_0_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_6_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %7 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
begin
Write4Blocks_0_7 = memory_controller_out[15:0];
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %8 = sext i16 %7 to i32*/
begin
Write4Blocks_0_8 = $signed(Write4Blocks_0_7);
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %8 = sext i16 %7 to i32*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_6)
begin
Write4Blocks_0_8_reg <= Write4Blocks_0_8;
if (^reset !== 1'bX && ^(Write4Blocks_0_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_8_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %9 = icmp slt i32 %2, %8*/
begin
Write4Blocks_0_9 = $signed(Write4Blocks_0_2_reg) < $signed(Write4Blocks_0_8);
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %9 = icmp slt i32 %2, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_6)
begin
Write4Blocks_0_9_reg <= Write4Blocks_0_9;
if (^reset !== 1'bX && ^(Write4Blocks_0_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_9_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %10 = icmp slt i32 %4, %6*/
begin
Write4Blocks_0_10 = $signed(Write4Blocks_0_4_reg) < $signed(Write4Blocks_0_6);
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %10 = icmp slt i32 %4, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_5)
begin
Write4Blocks_0_10_reg <= Write4Blocks_0_10;
if (^reset !== 1'bX && ^(Write4Blocks_0_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_10_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %or.cond.i = and i1 %9, %10*/
begin
Write4Blocks_0_or_cond_i = Write4Blocks_0_9 & Write4Blocks_0_10_reg;
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %tmp287 = add i32 %4, 8*/
begin
Write4Blocks_0_tmp287 = Write4Blocks_0_4 + 32'd8;
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %tmp287 = add i32 %4, 8*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
Write4Blocks_0_tmp287_reg <= Write4Blocks_0_tmp287;
if (^reset !== 1'bX && ^(Write4Blocks_0_tmp287) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_tmp287_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp288340 = or i32 %4, 1*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp288340 = Write4Blocks_0_4_reg | 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp289 = icmp sgt i32 %tmp287, %tmp288340*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp289 = $signed(Write4Blocks_0_tmp287_reg) > $signed(Write4Blocks__lr_ph8_split_us_i_tmp288340);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %smax290 = select i1 %tmp289, i32 %tmp287, i32 %tmp288340*/
begin
Write4Blocks__lr_ph8_split_us_i_smax290 = (Write4Blocks__lr_ph8_split_us_i_tmp289 ? Write4Blocks_0_tmp287_reg : Write4Blocks__lr_ph8_split_us_i_tmp288340);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp291 = sub i32 %4, %smax290*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp291 = Write4Blocks_0_4_reg - Write4Blocks__lr_ph8_split_us_i_smax290;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp291 = sub i32 %4, %smax290*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks__lr_ph8_split_us_i_tmp291_reg <= Write4Blocks__lr_ph8_split_us_i_tmp291;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp291) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp291_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp293 = sub i32 %4, %6*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp293 = Write4Blocks_0_4_reg - Write4Blocks_0_6_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp293 = sub i32 %4, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks__lr_ph8_split_us_i_tmp293_reg <= Write4Blocks__lr_ph8_split_us_i_tmp293;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp293) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp293_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp294 = icmp ugt i32 %tmp291, %tmp293*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp294 = Write4Blocks__lr_ph8_split_us_i_tmp291_reg > Write4Blocks__lr_ph8_split_us_i_tmp293_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %umax295 = select i1 %tmp294, i32 %tmp291, i32 %tmp293*/
begin
Write4Blocks__lr_ph8_split_us_i_umax295 = (Write4Blocks__lr_ph8_split_us_i_tmp294 ? Write4Blocks__lr_ph8_split_us_i_tmp291_reg : Write4Blocks__lr_ph8_split_us_i_tmp293_reg);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp296 = sub i32 0, %umax295*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp296 = 32'd0 - Write4Blocks__lr_ph8_split_us_i_umax295;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp296 = sub i32 0, %umax295*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_8)
begin
Write4Blocks__lr_ph8_split_us_i_tmp296_reg <= Write4Blocks__lr_ph8_split_us_i_tmp296;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp296) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp296_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp307 = add i32 %2, 8*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp307 = Write4Blocks_0_2_reg + 32'd8;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp308341 = or i32 %2, 1*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp308341 = Write4Blocks_0_2_reg | 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp309 = icmp sgt i32 %tmp307, %tmp308341*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp309 = $signed(Write4Blocks__lr_ph8_split_us_i_tmp307) > $signed(Write4Blocks__lr_ph8_split_us_i_tmp308341);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %smax310 = select i1 %tmp309, i32 %tmp307, i32 %tmp308341*/
begin
Write4Blocks__lr_ph8_split_us_i_smax310 = (Write4Blocks__lr_ph8_split_us_i_tmp309 ? Write4Blocks__lr_ph8_split_us_i_tmp307 : Write4Blocks__lr_ph8_split_us_i_tmp308341);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %smax310 = select i1 %tmp309, i32 %tmp307, i32 %tmp308341*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks__lr_ph8_split_us_i_smax310_reg <= Write4Blocks__lr_ph8_split_us_i_smax310;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_smax310) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_smax310_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp311 = sub i32 %2, %smax310*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp311 = Write4Blocks_0_2_reg - Write4Blocks__lr_ph8_split_us_i_smax310_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp313 = sub i32 %2, %8*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp313 = Write4Blocks_0_2_reg - Write4Blocks_0_8_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp313 = sub i32 %2, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks__lr_ph8_split_us_i_tmp313_reg <= Write4Blocks__lr_ph8_split_us_i_tmp313;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp313) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp313_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp314 = icmp ugt i32 %tmp311, %tmp313*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp314 = Write4Blocks__lr_ph8_split_us_i_tmp311 > Write4Blocks__lr_ph8_split_us_i_tmp313_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %umax315 = select i1 %tmp314, i32 %tmp311, i32 %tmp313*/
begin
Write4Blocks__lr_ph8_split_us_i_umax315 = (Write4Blocks__lr_ph8_split_us_i_tmp314 ? Write4Blocks__lr_ph8_split_us_i_tmp311 : Write4Blocks__lr_ph8_split_us_i_tmp313_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %umax315 = select i1 %tmp314, i32 %tmp311, i32 %tmp313*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_8)
begin
Write4Blocks__lr_ph8_split_us_i_umax315_reg <= Write4Blocks__lr_ph8_split_us_i_umax315;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_umax315) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_umax315_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp316 = sub i32 0, %umax315*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp316 = 32'd0 - Write4Blocks__lr_ph8_split_us_i_umax315_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp316 = sub i32 0, %umax315*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_9)
begin
Write4Blocks__lr_ph8_split_us_i_tmp316_reg <= Write4Blocks__lr_ph8_split_us_i_tmp316;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp316) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp316_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp332 = mul i32 %1, %6*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp332 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp333 = shl i32 %tmp332, 3*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp333 = Write4Blocks__lr_ph8_split_us_i_tmp332 <<< 32'd3 % 32;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp334 = add i32 %4, %tmp333*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp334 = Write4Blocks_0_4_reg + Write4Blocks__lr_ph8_split_us_i_tmp333;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp334 = add i32 %4, %tmp333*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks__lr_ph8_split_us_i_tmp334_reg <= Write4Blocks__lr_ph8_split_us_i_tmp334;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp334) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp334_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %11*/
/* %indvar.next18.i = add i32 %indvar17.i, 1*/
begin
Write4Blocks_11_indvar_next18_i = Write4Blocks__lr_ph_us_i_indvar17_i_reg + 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %11*/
/* %exitcond317 = icmp eq i32 %indvar.next18.i, %tmp316*/
begin
Write4Blocks_11_exitcond317 = Write4Blocks_11_indvar_next18_i == Write4Blocks__lr_ph8_split_us_i_tmp316_reg;
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %indvar.i = phi i32 [ 0, %.lr.ph.us.i ], [ %indvar.next.i, %12 ]*/
begin
Write4Blocks_12_indvar_i = Write4Blocks_12_indvar_i_phi_temp;
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %tmp330 = add i32 %tmp329, %indvar.i*/
begin
Write4Blocks_12_tmp330 = Write4Blocks__lr_ph_us_i_tmp329_reg + Write4Blocks_12_indvar_i;
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %.14.us.i = getelementptr i32* %store1, i32 %tmp330*/
begin
Write4Blocks_12__14_us_i = arg_store1 + 4 * Write4Blocks_12_tmp330;
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %tmp336 = add i32 %tmp335, %indvar.i*/
begin
Write4Blocks_12_tmp336 = Write4Blocks__lr_ph_us_i_tmp335_reg + Write4Blocks_12_indvar_i;
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %scevgep24.i = getelementptr i8* %p_out_buf, i32 %tmp336*/
begin
Write4Blocks_12_scevgep24_i = arg_p_out_buf + 1 * Write4Blocks_12_tmp336;
end
end
always @(posedge clk) begin
/* Write4Blocks: %12*/
/* %scevgep24.i = getelementptr i8* %p_out_buf, i32 %tmp336*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
Write4Blocks_12_scevgep24_i_reg <= Write4Blocks_12_scevgep24_i;
if (^reset !== 1'bX && ^(Write4Blocks_12_scevgep24_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_12_scevgep24_i_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %13 = load i32* %.14.us.i, align 4, !tbaa !0*/
begin
Write4Blocks_12_13 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %14 = trunc i32 %13 to i8*/
begin
Write4Blocks_12_14 = Write4Blocks_12_13[7:0];
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %indvar.next.i = add i32 %indvar.i, 1*/
begin
Write4Blocks_12_indvar_next_i = Write4Blocks_12_indvar_i + 32'd1;
end
end
always @(posedge clk) begin
/* Write4Blocks: %12*/
/* %indvar.next.i = add i32 %indvar.i, 1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
Write4Blocks_12_indvar_next_i_reg <= Write4Blocks_12_indvar_next_i;
if (^reset !== 1'bX && ^(Write4Blocks_12_indvar_next_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_12_indvar_next_i_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %exitcond297 = icmp eq i32 %indvar.next.i, %tmp296*/
begin
Write4Blocks_12_exitcond297 = Write4Blocks_12_indvar_next_i == Write4Blocks__lr_ph8_split_us_i_tmp296_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %12*/
/* %exitcond297 = icmp eq i32 %indvar.next.i, %tmp296*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
Write4Blocks_12_exitcond297_reg <= Write4Blocks_12_exitcond297;
if (^reset !== 1'bX && ^(Write4Blocks_12_exitcond297) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_12_exitcond297_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i_indvar17_i = Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp;
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB4_14) */
begin
Write4Blocks__lr_ph_us_i_indvar17_i = Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i_indvar17_i_reg <= Write4Blocks__lr_ph_us_i_indvar17_i;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i_indvar17_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_indvar17_i_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i_indvar17_i_reg <= Write4Blocks__lr_ph_us_i_indvar17_i;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i_indvar17_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_indvar17_i_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i_indvar17_i_reg <= Write4Blocks__lr_ph_us_i_indvar17_i;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i_indvar17_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_indvar17_i_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp329 = mul i32 %indvar17.i, %tmp296*/
begin
Write4Blocks__lr_ph_us_i_tmp329 = Write4Blocks_signed_multiply_32_1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp329 = mul i32 %indvar17.i, %tmp296*/
Write4Blocks__lr_ph_us_i_tmp329_reg = Write4Blocks__lr_ph_us_i36_tmp168_reg;
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp331 = mul i32 %6, %indvar17.i*/
begin
Write4Blocks__lr_ph_us_i_tmp331 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp335 = add i32 %tmp334, %tmp331*/
begin
Write4Blocks__lr_ph_us_i_tmp335 = Write4Blocks__lr_ph8_split_us_i_tmp334_reg + Write4Blocks__lr_ph_us_i_tmp331;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp335 = add i32 %tmp334, %tmp331*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i_tmp335_reg <= Write4Blocks__lr_ph_us_i_tmp335;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i_tmp335) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_tmp335_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit*/
/* %15 = icmp slt i32 %tmp287, %6*/
begin
Write4Blocks_WriteOneBlock_exit_15 = $signed(Write4Blocks_0_tmp287_reg) < $signed(Write4Blocks_0_6_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit*/
/* %15 = icmp slt i32 %tmp287, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB5_15)
begin
Write4Blocks_WriteOneBlock_exit_15_reg <= Write4Blocks_WriteOneBlock_exit_15;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit_15_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit*/
/* %or.cond.i75 = and i1 %9, %15*/
begin
Write4Blocks_WriteOneBlock_exit_or_cond_i75 = Write4Blocks_0_9_reg & Write4Blocks_WriteOneBlock_exit_15;
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge*/
/* %.pre349 = add nsw i32 %2, 8*/
begin
Write4Blocks_WriteOneBlock_exit_WriteOneBlock_exit111_crit_edge__pre349 = Write4Blocks_0_2_reg + 32'd8;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp232 = add i32 %4, 16*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp232 = Write4Blocks_0_4_reg + 32'd16;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp233 = add i32 %4, 9*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp233 = Write4Blocks_0_4_reg + 32'd9;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp234 = icmp sgt i32 %tmp232, %tmp233*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp234 = $signed(Write4Blocks__lr_ph8_split_us_i96_tmp232) > $signed(Write4Blocks__lr_ph8_split_us_i96_tmp233);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %smax235 = select i1 %tmp234, i32 %tmp232, i32 %tmp233*/
begin
Write4Blocks__lr_ph8_split_us_i96_smax235 = (Write4Blocks__lr_ph8_split_us_i96_tmp234 ? Write4Blocks__lr_ph8_split_us_i96_tmp232 : Write4Blocks__lr_ph8_split_us_i96_tmp233);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %smax235 = select i1 %tmp234, i32 %tmp232, i32 %tmp233*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_smax235_reg <= Write4Blocks__lr_ph8_split_us_i96_smax235;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_smax235) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_smax235_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp236 = sub i32 %tmp287, %smax235*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp236 = Write4Blocks_0_tmp287_reg - Write4Blocks__lr_ph8_split_us_i96_smax235_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp238 = sub i32 %tmp287, %6*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp238 = Write4Blocks_0_tmp287_reg - Write4Blocks_0_6_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp238 = sub i32 %tmp287, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp238_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp238;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp238) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp238_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp239 = icmp ugt i32 %tmp236, %tmp238*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp239 = Write4Blocks__lr_ph8_split_us_i96_tmp236 > Write4Blocks__lr_ph8_split_us_i96_tmp238_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %umax240 = select i1 %tmp239, i32 %tmp236, i32 %tmp238*/
begin
Write4Blocks__lr_ph8_split_us_i96_umax240 = (Write4Blocks__lr_ph8_split_us_i96_tmp239 ? Write4Blocks__lr_ph8_split_us_i96_tmp236 : Write4Blocks__lr_ph8_split_us_i96_tmp238_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %umax240 = select i1 %tmp239, i32 %tmp236, i32 %tmp238*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_18)
begin
Write4Blocks__lr_ph8_split_us_i96_umax240_reg <= Write4Blocks__lr_ph8_split_us_i96_umax240;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_umax240) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_umax240_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp241 = sub i32 0, %umax240*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp241 = 32'd0 - Write4Blocks__lr_ph8_split_us_i96_umax240_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp241 = sub i32 0, %umax240*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_19)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp241_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp241;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp241) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp241_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp254 = add i32 %2, 8*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp254 = Write4Blocks_0_2_reg + 32'd8;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp254 = add i32 %2, 8*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp254_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp254;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp254) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp254_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp255339 = or i32 %2, 1*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp255339 = Write4Blocks_0_2_reg | 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp256 = icmp sgt i32 %tmp254, %tmp255339*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp256 = $signed(Write4Blocks__lr_ph8_split_us_i96_tmp254) > $signed(Write4Blocks__lr_ph8_split_us_i96_tmp255339);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %smax257 = select i1 %tmp256, i32 %tmp254, i32 %tmp255339*/
begin
Write4Blocks__lr_ph8_split_us_i96_smax257 = (Write4Blocks__lr_ph8_split_us_i96_tmp256 ? Write4Blocks__lr_ph8_split_us_i96_tmp254 : Write4Blocks__lr_ph8_split_us_i96_tmp255339);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %smax257 = select i1 %tmp256, i32 %tmp254, i32 %tmp255339*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_smax257_reg <= Write4Blocks__lr_ph8_split_us_i96_smax257;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_smax257) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_smax257_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp258 = sub i32 %2, %smax257*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp258 = Write4Blocks_0_2_reg - Write4Blocks__lr_ph8_split_us_i96_smax257_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp260 = sub i32 %2, %8*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp260 = Write4Blocks_0_2_reg - Write4Blocks_0_8_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp260 = sub i32 %2, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp260_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp260;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp260) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp260_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp261 = icmp ugt i32 %tmp258, %tmp260*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp261 = Write4Blocks__lr_ph8_split_us_i96_tmp258 > Write4Blocks__lr_ph8_split_us_i96_tmp260_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %umax262 = select i1 %tmp261, i32 %tmp258, i32 %tmp260*/
begin
Write4Blocks__lr_ph8_split_us_i96_umax262 = (Write4Blocks__lr_ph8_split_us_i96_tmp261 ? Write4Blocks__lr_ph8_split_us_i96_tmp258 : Write4Blocks__lr_ph8_split_us_i96_tmp260_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %umax262 = select i1 %tmp261, i32 %tmp258, i32 %tmp260*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_18)
begin
Write4Blocks__lr_ph8_split_us_i96_umax262_reg <= Write4Blocks__lr_ph8_split_us_i96_umax262;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_umax262) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_umax262_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp263 = sub i32 0, %umax262*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp263 = 32'd0 - Write4Blocks__lr_ph8_split_us_i96_umax262_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp263 = sub i32 0, %umax262*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_19)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp263_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp263;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp263) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp263_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp280 = mul i32 %1, %6*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp280 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp281 = shl i32 %tmp280, 3*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp281 = Write4Blocks__lr_ph8_split_us_i96_tmp280 <<< 32'd3 % 32;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp282 = add i32 %4, %tmp281*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp282 = Write4Blocks_0_4_reg + Write4Blocks__lr_ph8_split_us_i96_tmp281;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp282 = add i32 %4, %tmp281*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp282_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp282;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp282) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp282_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp283 = add i32 %tmp282, 8*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp283 = Write4Blocks__lr_ph8_split_us_i96_tmp282_reg + 32'd8;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp283 = add i32 %tmp282, 8*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_18)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp283_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp283;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp283) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp283_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %16*/
/* %indvar.next18.i98 = add i32 %indvar17.i106, 1*/
begin
Write4Blocks_16_indvar_next18_i98 = Write4Blocks__lr_ph_us_i110_indvar17_i106_reg + 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %16*/
/* %exitcond264 = icmp eq i32 %indvar.next18.i98, %tmp263*/
begin
Write4Blocks_16_exitcond264 = Write4Blocks_16_indvar_next18_i98 == Write4Blocks__lr_ph8_split_us_i96_tmp263_reg;
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %indvar.i100 = phi i32 [ 0, %.lr.ph.us.i110 ], [ %indvar.next.i104, %17 ]*/
begin
Write4Blocks_17_indvar_i100 = Write4Blocks_17_indvar_i100_phi_temp;
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %tmp278 = add i32 %tmp277, %indvar.i100*/
begin
Write4Blocks_17_tmp278 = Write4Blocks__lr_ph_us_i110_tmp277_reg + Write4Blocks_17_indvar_i100;
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %.14.us.i103 = getelementptr i32* %store2, i32 %tmp278*/
begin
Write4Blocks_17__14_us_i103 = arg_store2 + 4 * Write4Blocks_17_tmp278;
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %tmp285 = add i32 %tmp284, %indvar.i100*/
begin
Write4Blocks_17_tmp285 = Write4Blocks__lr_ph_us_i110_tmp284_reg + Write4Blocks_17_indvar_i100;
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %scevgep24.i102 = getelementptr i8* %p_out_buf, i32 %tmp285*/
begin
Write4Blocks_17_scevgep24_i102 = arg_p_out_buf + 1 * Write4Blocks_17_tmp285;
end
end
always @(posedge clk) begin
/* Write4Blocks: %17*/
/* %scevgep24.i102 = getelementptr i8* %p_out_buf, i32 %tmp285*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
Write4Blocks_17_scevgep24_i102_reg <= Write4Blocks_17_scevgep24_i102;
if (^reset !== 1'bX && ^(Write4Blocks_17_scevgep24_i102) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_17_scevgep24_i102_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %18 = load i32* %.14.us.i103, align 4, !tbaa !0*/
begin
Write4Blocks_17_18 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %19 = trunc i32 %18 to i8*/
begin
Write4Blocks_17_19 = Write4Blocks_17_18[7:0];
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %indvar.next.i104 = add i32 %indvar.i100, 1*/
begin
Write4Blocks_17_indvar_next_i104 = Write4Blocks_17_indvar_i100 + 32'd1;
end
end
always @(posedge clk) begin
/* Write4Blocks: %17*/
/* %indvar.next.i104 = add i32 %indvar.i100, 1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
Write4Blocks_17_indvar_next_i104_reg <= Write4Blocks_17_indvar_next_i104;
if (^reset !== 1'bX && ^(Write4Blocks_17_indvar_next_i104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_17_indvar_next_i104_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %exitcond242 = icmp eq i32 %indvar.next.i104, %tmp241*/
begin
Write4Blocks_17_exitcond242 = Write4Blocks_17_indvar_next_i104 == Write4Blocks__lr_ph8_split_us_i96_tmp241_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %17*/
/* %exitcond242 = icmp eq i32 %indvar.next.i104, %tmp241*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
Write4Blocks_17_exitcond242_reg <= Write4Blocks_17_exitcond242;
if (^reset !== 1'bX && ^(Write4Blocks_17_exitcond242) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_17_exitcond242_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106 = Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp;
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB10_24) */
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106 = Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106_reg <= Write4Blocks__lr_ph_us_i110_indvar17_i106;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i110_indvar17_i106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_indvar17_i106_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106_reg <= Write4Blocks__lr_ph_us_i110_indvar17_i106;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i110_indvar17_i106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_indvar17_i106_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106_reg <= Write4Blocks__lr_ph_us_i110_indvar17_i106;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i110_indvar17_i106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_indvar17_i106_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp277 = mul i32 %indvar17.i106, %tmp241*/
begin
Write4Blocks__lr_ph_us_i110_tmp277 = Write4Blocks_signed_multiply_32_1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp277 = mul i32 %indvar17.i106, %tmp241*/
Write4Blocks__lr_ph_us_i110_tmp277_reg = Write4Blocks__lr_ph_us_i36_tmp168_reg;
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp279 = mul i32 %6, %indvar17.i106*/
begin
Write4Blocks__lr_ph_us_i110_tmp279 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp284 = add i32 %tmp283, %tmp279*/
begin
Write4Blocks__lr_ph_us_i110_tmp284 = Write4Blocks__lr_ph8_split_us_i96_tmp283_reg + Write4Blocks__lr_ph_us_i110_tmp279;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp284 = add i32 %tmp283, %tmp279*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i110_tmp284_reg <= Write4Blocks__lr_ph_us_i110_tmp284;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i110_tmp284) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_tmp284_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB11_25) */
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %20 = icmp slt i32 %.pre-phi350, %8*/
begin
Write4Blocks_WriteOneBlock_exit111_20 = $signed(Write4Blocks_WriteOneBlock_exit111__pre_phi350) < $signed(Write4Blocks_0_8_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %20 = icmp slt i32 %.pre-phi350, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111_20_reg <= Write4Blocks_WriteOneBlock_exit111_20;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111_20_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %or.cond.i38 = and i1 %20, %10*/
begin
Write4Blocks_WriteOneBlock_exit111_or_cond_i38 = Write4Blocks_WriteOneBlock_exit111_20 & Write4Blocks_0_10_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp179337 = or i32 %4, 1*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp179337 = Write4Blocks_0_4_reg | 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp180 = icmp sgt i32 %tmp287, %tmp179337*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp180 = $signed(Write4Blocks_0_tmp287_reg) > $signed(Write4Blocks__lr_ph8_split_us_i59_tmp179337);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %smax181 = select i1 %tmp180, i32 %tmp287, i32 %tmp179337*/
begin
Write4Blocks__lr_ph8_split_us_i59_smax181 = (Write4Blocks__lr_ph8_split_us_i59_tmp180 ? Write4Blocks_0_tmp287_reg : Write4Blocks__lr_ph8_split_us_i59_tmp179337);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp182 = sub i32 %4, %smax181*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp182 = Write4Blocks_0_4_reg - Write4Blocks__lr_ph8_split_us_i59_smax181;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp182 = sub i32 %4, %smax181*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp182_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp182;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp182) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp182_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp184 = sub i32 %4, %6*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp184 = Write4Blocks_0_4_reg - Write4Blocks_0_6_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp184 = sub i32 %4, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp184_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp184;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp184) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp184_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp185 = icmp ugt i32 %tmp182, %tmp184*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp185 = Write4Blocks__lr_ph8_split_us_i59_tmp182_reg > Write4Blocks__lr_ph8_split_us_i59_tmp184_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %umax186 = select i1 %tmp185, i32 %tmp182, i32 %tmp184*/
begin
Write4Blocks__lr_ph8_split_us_i59_umax186 = (Write4Blocks__lr_ph8_split_us_i59_tmp185 ? Write4Blocks__lr_ph8_split_us_i59_tmp182_reg : Write4Blocks__lr_ph8_split_us_i59_tmp184_reg);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp187 = sub i32 0, %umax186*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp187 = 32'd0 - Write4Blocks__lr_ph8_split_us_i59_umax186;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp187 = sub i32 0, %umax186*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_27)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp187_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp187;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp187) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp187_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp199 = add i32 %2, 16*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp199 = Write4Blocks_0_2_reg + 32'd16;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp200 = add i32 %2, 9*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp200 = Write4Blocks_0_2_reg + 32'd9;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp201 = icmp sgt i32 %tmp199, %tmp200*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp201 = $signed(Write4Blocks__lr_ph8_split_us_i59_tmp199) > $signed(Write4Blocks__lr_ph8_split_us_i59_tmp200);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %smax202 = select i1 %tmp201, i32 %tmp199, i32 %tmp200*/
begin
Write4Blocks__lr_ph8_split_us_i59_smax202 = (Write4Blocks__lr_ph8_split_us_i59_tmp201 ? Write4Blocks__lr_ph8_split_us_i59_tmp199 : Write4Blocks__lr_ph8_split_us_i59_tmp200);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %smax202 = select i1 %tmp201, i32 %tmp199, i32 %tmp200*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks__lr_ph8_split_us_i59_smax202_reg <= Write4Blocks__lr_ph8_split_us_i59_smax202;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_smax202) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_smax202_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp203 = sub i32 %.pre-phi350, %smax202*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp203 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg - Write4Blocks__lr_ph8_split_us_i59_smax202_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp206 = sub i32 %.pre-phi350, %8*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp206 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg - Write4Blocks_0_8_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp206 = sub i32 %.pre-phi350, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp206_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp206;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp206) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp206_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp207 = icmp ugt i32 %tmp203, %tmp206*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp207 = Write4Blocks__lr_ph8_split_us_i59_tmp203 > Write4Blocks__lr_ph8_split_us_i59_tmp206_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %umax208 = select i1 %tmp207, i32 %tmp203, i32 %tmp206*/
begin
Write4Blocks__lr_ph8_split_us_i59_umax208 = (Write4Blocks__lr_ph8_split_us_i59_tmp207 ? Write4Blocks__lr_ph8_split_us_i59_tmp203 : Write4Blocks__lr_ph8_split_us_i59_tmp206_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %umax208 = select i1 %tmp207, i32 %tmp203, i32 %tmp206*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_27)
begin
Write4Blocks__lr_ph8_split_us_i59_umax208_reg <= Write4Blocks__lr_ph8_split_us_i59_umax208;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_umax208) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_umax208_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp209 = sub i32 0, %umax208*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp209 = 32'd0 - Write4Blocks__lr_ph8_split_us_i59_umax208_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp209 = sub i32 0, %umax208*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_28)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp209_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp209;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp209) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp209_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp226 = mul i32 %.pre-phi350, %6*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp226 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp227 = add i32 %tmp226, %4*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp227 = Write4Blocks__lr_ph8_split_us_i59_tmp226 + Write4Blocks_0_4_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp227 = add i32 %tmp226, %4*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp227_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp227;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp227) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp227_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %21*/
/* %indvar.next18.i61 = add i32 %indvar17.i69, 1*/
begin
Write4Blocks_21_indvar_next18_i61 = Write4Blocks__lr_ph_us_i73_indvar17_i69_reg + 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %21*/
/* %exitcond210 = icmp eq i32 %indvar.next18.i61, %tmp209*/
begin
Write4Blocks_21_exitcond210 = Write4Blocks_21_indvar_next18_i61 == Write4Blocks__lr_ph8_split_us_i59_tmp209_reg;
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %indvar.i63 = phi i32 [ 0, %.lr.ph.us.i73 ], [ %indvar.next.i67, %22 ]*/
begin
Write4Blocks_22_indvar_i63 = Write4Blocks_22_indvar_i63_phi_temp;
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %tmp223 = add i32 %tmp222, %indvar.i63*/
begin
Write4Blocks_22_tmp223 = Write4Blocks__lr_ph_us_i73_tmp222_reg + Write4Blocks_22_indvar_i63;
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %.14.us.i66 = getelementptr i32* %store3, i32 %tmp223*/
begin
Write4Blocks_22__14_us_i66 = arg_store3 + 4 * Write4Blocks_22_tmp223;
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %tmp229 = add i32 %tmp228, %indvar.i63*/
begin
Write4Blocks_22_tmp229 = Write4Blocks__lr_ph_us_i73_tmp228_reg + Write4Blocks_22_indvar_i63;
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %scevgep24.i65 = getelementptr i8* %p_out_buf, i32 %tmp229*/
begin
Write4Blocks_22_scevgep24_i65 = arg_p_out_buf + 1 * Write4Blocks_22_tmp229;
end
end
always @(posedge clk) begin
/* Write4Blocks: %22*/
/* %scevgep24.i65 = getelementptr i8* %p_out_buf, i32 %tmp229*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
Write4Blocks_22_scevgep24_i65_reg <= Write4Blocks_22_scevgep24_i65;
if (^reset !== 1'bX && ^(Write4Blocks_22_scevgep24_i65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_22_scevgep24_i65_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %23 = load i32* %.14.us.i66, align 4, !tbaa !0*/
begin
Write4Blocks_22_23 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %24 = trunc i32 %23 to i8*/
begin
Write4Blocks_22_24 = Write4Blocks_22_23[7:0];
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %indvar.next.i67 = add i32 %indvar.i63, 1*/
begin
Write4Blocks_22_indvar_next_i67 = Write4Blocks_22_indvar_i63 + 32'd1;
end
end
always @(posedge clk) begin
/* Write4Blocks: %22*/
/* %indvar.next.i67 = add i32 %indvar.i63, 1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
Write4Blocks_22_indvar_next_i67_reg <= Write4Blocks_22_indvar_next_i67;
if (^reset !== 1'bX && ^(Write4Blocks_22_indvar_next_i67) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_22_indvar_next_i67_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %exitcond188 = icmp eq i32 %indvar.next.i67, %tmp187*/
begin
Write4Blocks_22_exitcond188 = Write4Blocks_22_indvar_next_i67 == Write4Blocks__lr_ph8_split_us_i59_tmp187_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %22*/
/* %exitcond188 = icmp eq i32 %indvar.next.i67, %tmp187*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
Write4Blocks_22_exitcond188_reg <= Write4Blocks_22_exitcond188;
if (^reset !== 1'bX && ^(Write4Blocks_22_exitcond188) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_22_exitcond188_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69 = Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp;
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB15_33) */
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69 = Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69_reg <= Write4Blocks__lr_ph_us_i73_indvar17_i69;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i73_indvar17_i69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_indvar17_i69_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69_reg <= Write4Blocks__lr_ph_us_i73_indvar17_i69;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i73_indvar17_i69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_indvar17_i69_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69_reg <= Write4Blocks__lr_ph_us_i73_indvar17_i69;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i73_indvar17_i69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_indvar17_i69_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp222 = mul i32 %indvar17.i69, %tmp187*/
begin
Write4Blocks__lr_ph_us_i73_tmp222 = Write4Blocks_signed_multiply_32_1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp222 = mul i32 %indvar17.i69, %tmp187*/
Write4Blocks__lr_ph_us_i73_tmp222_reg = Write4Blocks__lr_ph_us_i36_tmp168_reg;
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp224 = mul i32 %6, %indvar17.i69*/
begin
Write4Blocks__lr_ph_us_i73_tmp224 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp228 = add i32 %tmp227, %tmp224*/
begin
Write4Blocks__lr_ph_us_i73_tmp228 = Write4Blocks__lr_ph8_split_us_i59_tmp227_reg + Write4Blocks__lr_ph_us_i73_tmp224;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp228 = add i32 %tmp227, %tmp224*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i73_tmp228_reg <= Write4Blocks__lr_ph_us_i73_tmp228;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i73_tmp228) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_tmp228_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit74*/
/* %or.cond.i1 = and i1 %20, %15*/
begin
Write4Blocks_WriteOneBlock_exit74_or_cond_i1 = Write4Blocks_WriteOneBlock_exit111_20_reg & Write4Blocks_WriteOneBlock_exit_15_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp125 = add i32 %4, 16*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp125 = Write4Blocks_0_4_reg + 32'd16;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp126 = add i32 %4, 9*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp126 = Write4Blocks_0_4_reg + 32'd9;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp127 = icmp sgt i32 %tmp125, %tmp126*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp127 = $signed(Write4Blocks__lr_ph8_split_us_i22_tmp125) > $signed(Write4Blocks__lr_ph8_split_us_i22_tmp126);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %smax = select i1 %tmp127, i32 %tmp125, i32 %tmp126*/
begin
Write4Blocks__lr_ph8_split_us_i22_smax = (Write4Blocks__lr_ph8_split_us_i22_tmp127 ? Write4Blocks__lr_ph8_split_us_i22_tmp125 : Write4Blocks__lr_ph8_split_us_i22_tmp126);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %smax = select i1 %tmp127, i32 %tmp125, i32 %tmp126*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks__lr_ph8_split_us_i22_smax_reg <= Write4Blocks__lr_ph8_split_us_i22_smax;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_smax) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_smax_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp128 = sub i32 %tmp287, %smax*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp128 = Write4Blocks_0_tmp287_reg - Write4Blocks__lr_ph8_split_us_i22_smax_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp130 = sub i32 %tmp287, %6*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp130 = Write4Blocks_0_tmp287_reg - Write4Blocks_0_6_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp130 = sub i32 %tmp287, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks__lr_ph8_split_us_i22_tmp130_reg <= Write4Blocks__lr_ph8_split_us_i22_tmp130;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_tmp130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_tmp130_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp131 = icmp ugt i32 %tmp128, %tmp130*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp131 = Write4Blocks__lr_ph8_split_us_i22_tmp128 > Write4Blocks__lr_ph8_split_us_i22_tmp130_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %umax = select i1 %tmp131, i32 %tmp128, i32 %tmp130*/
begin
Write4Blocks__lr_ph8_split_us_i22_umax = (Write4Blocks__lr_ph8_split_us_i22_tmp131 ? Write4Blocks__lr_ph8_split_us_i22_tmp128 : Write4Blocks__lr_ph8_split_us_i22_tmp130_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %umax = select i1 %tmp131, i32 %tmp128, i32 %tmp130*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_36)
begin
Write4Blocks__lr_ph8_split_us_i22_umax_reg <= Write4Blocks__lr_ph8_split_us_i22_umax;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_umax) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_umax_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp132 = sub i32 0, %umax*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp132 = 32'd0 - Write4Blocks__lr_ph8_split_us_i22_umax_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp132 = sub i32 0, %umax*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_37)
begin
Write4Blocks__lr_ph8_split_us_i22_tmp132_reg <= Write4Blocks__lr_ph8_split_us_i22_tmp132;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_tmp132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_tmp132_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp144 = add i32 %2, 16*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp144 = Write4Blocks_0_2_reg + 32'd16;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp145 = add i32 %2, 9*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp145 = Write4Blocks_0_2_reg + 32'd9;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp146 = icmp sgt i32 %tmp144, %tmp145*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp146 = $signed(Write4Blocks__lr_ph8_split_us_i22_tmp144) > $signed(Write4Blocks__lr_ph8_split_us_i22_tmp145);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %smax147 = select i1 %tmp146, i32 %tmp144, i32 %tmp145*/
begin
Write4Blocks__lr_ph8_split_us_i22_smax147 = (Write4Blocks__lr_ph8_split_us_i22_tmp146 ? Write4Blocks__lr_ph8_split_us_i22_tmp144 : Write4Blocks__lr_ph8_split_us_i22_tmp145);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %smax147 = select i1 %tmp146, i32 %tmp144, i32 %tmp145*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks__lr_ph8_split_us_i22_smax147_reg <= Write4Blocks__lr_ph8_split_us_i22_smax147;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_smax147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_smax147_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp148 = sub i32 %.pre-phi350, %smax147*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp148 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg - Write4Blocks__lr_ph8_split_us_i22_smax147_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp151 = sub i32 %.pre-phi350, %8*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp151 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg - Write4Blocks_0_8_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp151 = sub i32 %.pre-phi350, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks__lr_ph8_split_us_i22_tmp151_reg <= Write4Blocks__lr_ph8_split_us_i22_tmp151;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_tmp151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_tmp151_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp152 = icmp ugt i32 %tmp148, %tmp151*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp152 = Write4Blocks__lr_ph8_split_us_i22_tmp148 > Write4Blocks__lr_ph8_split_us_i22_tmp151_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %umax153 = select i1 %tmp152, i32 %tmp148, i32 %tmp151*/
begin
Write4Blocks__lr_ph8_split_us_i22_umax153 = (Write4Blocks__lr_ph8_split_us_i22_tmp152 ? Write4Blocks__lr_ph8_split_us_i22_tmp148 : Write4Blocks__lr_ph8_split_us_i22_tmp151_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %umax153 = select i1 %tmp152, i32 %tmp148, i32 %tmp151*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_36)
begin
Write4Blocks__lr_ph8_split_us_i22_umax153_reg <= Write4Blocks__lr_ph8_split_us_i22_umax153;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_umax153) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_umax153_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp154 = sub i32 0, %umax153*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp154 = 32'd0 - Write4Blocks__lr_ph8_split_us_i22_umax153_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp154 = sub i32 0, %umax153*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_37)
begin
Write4Blocks__lr_ph8_split_us_i22_tmp154_reg <= Write4Blocks__lr_ph8_split_us_i22_tmp154;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_tmp154) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_tmp154_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp172 = mul i32 %.pre-phi350, %6*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp172 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp173 = add i32 %tmp172, %4*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp173 = Write4Blocks__lr_ph8_split_us_i22_tmp172 + Write4Blocks_0_4_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp174 = add i32 %tmp173, 8*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp174 = Write4Blocks__lr_ph8_split_us_i22_tmp173 + 32'd8;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp174 = add i32 %tmp173, 8*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks__lr_ph8_split_us_i22_tmp174_reg <= Write4Blocks__lr_ph8_split_us_i22_tmp174;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_tmp174) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_tmp174_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %25*/
/* %indvar.next18.i24 = add i32 %indvar17.i32, 1*/
begin
Write4Blocks_25_indvar_next18_i24 = Write4Blocks__lr_ph_us_i36_indvar17_i32_reg + 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %25*/
/* %exitcond155 = icmp eq i32 %indvar.next18.i24, %tmp154*/
begin
Write4Blocks_25_exitcond155 = Write4Blocks_25_indvar_next18_i24 == Write4Blocks__lr_ph8_split_us_i22_tmp154_reg;
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %indvar.i26 = phi i32 [ 0, %.lr.ph.us.i36 ], [ %indvar.next.i30, %26 ]*/
begin
Write4Blocks_26_indvar_i26 = Write4Blocks_26_indvar_i26_phi_temp;
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %tmp169 = add i32 %tmp168, %indvar.i26*/
begin
Write4Blocks_26_tmp169 = Write4Blocks__lr_ph_us_i36_tmp168_reg + Write4Blocks_26_indvar_i26;
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %.14.us.i29 = getelementptr i32* %store4, i32 %tmp169*/
begin
Write4Blocks_26__14_us_i29 = arg_store4 + 4 * Write4Blocks_26_tmp169;
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %tmp176 = add i32 %tmp175, %indvar.i26*/
begin
Write4Blocks_26_tmp176 = Write4Blocks__lr_ph_us_i36_tmp175_reg + Write4Blocks_26_indvar_i26;
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %scevgep24.i28 = getelementptr i8* %p_out_buf, i32 %tmp176*/
begin
Write4Blocks_26_scevgep24_i28 = arg_p_out_buf + 1 * Write4Blocks_26_tmp176;
end
end
always @(posedge clk) begin
/* Write4Blocks: %26*/
/* %scevgep24.i28 = getelementptr i8* %p_out_buf, i32 %tmp176*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
Write4Blocks_26_scevgep24_i28_reg <= Write4Blocks_26_scevgep24_i28;
if (^reset !== 1'bX && ^(Write4Blocks_26_scevgep24_i28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_26_scevgep24_i28_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %27 = load i32* %.14.us.i29, align 4, !tbaa !0*/
begin
Write4Blocks_26_27 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %28 = trunc i32 %27 to i8*/
begin
Write4Blocks_26_28 = Write4Blocks_26_27[7:0];
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %indvar.next.i30 = add i32 %indvar.i26, 1*/
begin
Write4Blocks_26_indvar_next_i30 = Write4Blocks_26_indvar_i26 + 32'd1;
end
end
always @(posedge clk) begin
/* Write4Blocks: %26*/
/* %indvar.next.i30 = add i32 %indvar.i26, 1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
Write4Blocks_26_indvar_next_i30_reg <= Write4Blocks_26_indvar_next_i30;
if (^reset !== 1'bX && ^(Write4Blocks_26_indvar_next_i30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_26_indvar_next_i30_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %exitcond = icmp eq i32 %indvar.next.i30, %tmp132*/
begin
Write4Blocks_26_exitcond = Write4Blocks_26_indvar_next_i30 == Write4Blocks__lr_ph8_split_us_i22_tmp132_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %26*/
/* %exitcond = icmp eq i32 %indvar.next.i30, %tmp132*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
Write4Blocks_26_exitcond_reg <= Write4Blocks_26_exitcond;
if (^reset !== 1'bX && ^(Write4Blocks_26_exitcond) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_26_exitcond_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32 = Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp;
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB20_42) */
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32 = Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32_reg <= Write4Blocks__lr_ph_us_i36_indvar17_i32;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i36_indvar17_i32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_indvar17_i32_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32_reg <= Write4Blocks__lr_ph_us_i36_indvar17_i32;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i36_indvar17_i32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_indvar17_i32_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32_reg <= Write4Blocks__lr_ph_us_i36_indvar17_i32;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i36_indvar17_i32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_indvar17_i32_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp168 = mul i32 %indvar17.i32, %tmp132*/
begin
Write4Blocks__lr_ph_us_i36_tmp168 = Write4Blocks_signed_multiply_32_1;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp168 = mul i32 %indvar17.i32, %tmp132*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_tmp168_reg <= Write4Blocks__lr_ph_us_i36_tmp168;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i36_tmp168) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_tmp168_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp329 = mul i32 %indvar17.i, %tmp296*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i36_tmp168_reg <= Write4Blocks__lr_ph_us_i_tmp329;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i_tmp329) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_tmp168_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp222 = mul i32 %indvar17.i69, %tmp187*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i36_tmp168_reg <= Write4Blocks__lr_ph_us_i73_tmp222;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i73_tmp222) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_tmp168_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp277 = mul i32 %indvar17.i106, %tmp241*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i36_tmp168_reg <= Write4Blocks__lr_ph_us_i110_tmp277;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i110_tmp277) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_tmp168_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp170 = mul i32 %6, %indvar17.i32*/
begin
Write4Blocks__lr_ph_us_i36_tmp170 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp175 = add i32 %tmp174, %tmp170*/
begin
Write4Blocks__lr_ph_us_i36_tmp175 = Write4Blocks__lr_ph8_split_us_i22_tmp174_reg + Write4Blocks__lr_ph_us_i36_tmp170;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp175 = add i32 %tmp174, %tmp170*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_tmp175_reg <= Write4Blocks__lr_ph_us_i36_tmp175;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i36_tmp175) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_tmp175_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %29 = load i32* %p_out_hpos, align 4, !tbaa !0*/
begin
Write4Blocks_WriteOneBlock_exit37_29 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %30 = add nsw i32 %29, 2*/
begin
Write4Blocks_WriteOneBlock_exit37_30 = Write4Blocks_WriteOneBlock_exit37_29 + 32'd2;
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
begin
Write4Blocks_WriteOneBlock_exit37_31 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
Write4Blocks_WriteOneBlock_exit37_31_reg <= Write4Blocks_WriteOneBlock_exit37_31;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit37_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit37_31_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %32 = add nsw i32 %31, 2*/
begin
Write4Blocks_WriteOneBlock_exit37_32 = Write4Blocks_WriteOneBlock_exit37_31 + 32'd2;
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
begin
Write4Blocks_WriteOneBlock_exit37_33 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_51)
begin
Write4Blocks_WriteOneBlock_exit37_33_reg <= Write4Blocks_WriteOneBlock_exit37_33;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit37_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit37_33_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %34 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
begin
Write4Blocks_WriteOneBlock_exit37_34 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %35 = icmp slt i32 %33, %34*/
begin
Write4Blocks_WriteOneBlock_exit37_35 = $signed(Write4Blocks_WriteOneBlock_exit37_33_reg) < $signed(Write4Blocks_WriteOneBlock_exit37_34);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp332 = mul i32 %1, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_1_reg;
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp331 = mul i32 %6, %indvar17.i*/
else if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp280 = mul i32 %1, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_1_reg;
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp279 = mul i32 %6, %indvar17.i106*/
else if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp226 = mul i32 %.pre-phi350, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg;
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp224 = mul i32 %6, %indvar17.i69*/
else if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp172 = mul i32 %.pre-phi350, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg;
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp170 = mul i32 %6, %indvar17.i32*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB20_42) */
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_6_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp332 = mul i32 %1, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp331 = mul i32 %6, %indvar17.i*/
else if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks__lr_ph_us_i_indvar17_i;
end
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp280 = mul i32 %1, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp279 = mul i32 %6, %indvar17.i106*/
else if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks__lr_ph_us_i110_indvar17_i106;
end
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp226 = mul i32 %.pre-phi350, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp224 = mul i32 %6, %indvar17.i69*/
else if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks__lr_ph_us_i73_indvar17_i69;
end
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp172 = mul i32 %.pre-phi350, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp170 = mul i32 %6, %indvar17.i32*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB20_42) */
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks__lr_ph_us_i36_indvar17_i32;
end
end
always @(*) begin
Write4Blocks_signed_multiply_32_0 = Write4Blocks_signed_multiply_32_0_op0 * Write4Blocks_signed_multiply_32_0_op1;
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp329 = mul i32 %indvar17.i, %tmp296*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks_signed_multiply_32_1_op0 = Write4Blocks__lr_ph_us_i_indvar17_i;
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp277 = mul i32 %indvar17.i106, %tmp241*/
else if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks_signed_multiply_32_1_op0 = Write4Blocks__lr_ph_us_i110_indvar17_i106;
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp222 = mul i32 %indvar17.i69, %tmp187*/
else if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks_signed_multiply_32_1_op0 = Write4Blocks__lr_ph_us_i73_indvar17_i69;
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp168 = mul i32 %indvar17.i32, %tmp132*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB20_42) */
begin
Write4Blocks_signed_multiply_32_1_op0 = Write4Blocks__lr_ph_us_i36_indvar17_i32;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp329 = mul i32 %indvar17.i, %tmp296*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks_signed_multiply_32_1_op1 = Write4Blocks__lr_ph8_split_us_i_tmp296_reg;
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp277 = mul i32 %indvar17.i106, %tmp241*/
else if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks_signed_multiply_32_1_op1 = Write4Blocks__lr_ph8_split_us_i96_tmp241_reg;
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp222 = mul i32 %indvar17.i69, %tmp187*/
else if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks_signed_multiply_32_1_op1 = Write4Blocks__lr_ph8_split_us_i59_tmp187_reg;
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp168 = mul i32 %indvar17.i32, %tmp132*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB20_42) */
begin
Write4Blocks_signed_multiply_32_1_op1 = Write4Blocks__lr_ph8_split_us_i22_tmp132_reg;
end
end
always @(*) begin
Write4Blocks_signed_multiply_32_1 = Write4Blocks_signed_multiply_32_1_op0 * Write4Blocks_signed_multiply_32_1_op1;
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_9 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB2_10 & memory_controller_waitrequest == 1'd0 & Write4Blocks_11_exitcond317 == 1'd0)
begin
Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp <= Write4Blocks_11_indvar_next18_i;
if (^reset !== 1'bX && ^(Write4Blocks_11_indvar_next18_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %12*/
/* %indvar.i = phi i32 [ 0, %.lr.ph.us.i ], [ %indvar.next.i, %12 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13 & memory_controller_waitrequest == 1'd0 & Write4Blocks_12_exitcond297_reg == 1'd0)
begin
Write4Blocks_12_indvar_i_phi_temp <= Write4Blocks_12_indvar_next_i_reg;
if (^reset !== 1'bX && ^(Write4Blocks_12_indvar_next_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_12_indvar_i_phi_temp"); $finish; end
end
/* Write4Blocks: %12*/
/* %indvar.i = phi i32 [ 0, %.lr.ph.us.i ], [ %indvar.next.i, %12 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks_12_indvar_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_12_indvar_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB6_16 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp <= Write4Blocks_WriteOneBlock_exit_WriteOneBlock_exit111_crit_edge__pre349;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit_WriteOneBlock_exit111_crit_edge__pre349) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB8_20 & memory_controller_waitrequest == 1'd0 & Write4Blocks_16_exitcond264 == 1'd1)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp <= Write4Blocks__lr_ph8_split_us_i96_tmp254_reg;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp254_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_19 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB8_20 & memory_controller_waitrequest == 1'd0 & Write4Blocks_16_exitcond264 == 1'd0)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp <= Write4Blocks_16_indvar_next18_i98;
if (^reset !== 1'bX && ^(Write4Blocks_16_indvar_next18_i98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %17*/
/* %indvar.i100 = phi i32 [ 0, %.lr.ph.us.i110 ], [ %indvar.next.i104, %17 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23 & memory_controller_waitrequest == 1'd0 & Write4Blocks_17_exitcond242_reg == 1'd0)
begin
Write4Blocks_17_indvar_i100_phi_temp <= Write4Blocks_17_indvar_next_i104_reg;
if (^reset !== 1'bX && ^(Write4Blocks_17_indvar_next_i104_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_17_indvar_i100_phi_temp"); $finish; end
end
/* Write4Blocks: %17*/
/* %indvar.i100 = phi i32 [ 0, %.lr.ph.us.i110 ], [ %indvar.next.i104, %17 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks_17_indvar_i100_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_17_indvar_i100_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_28 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB13_29 & memory_controller_waitrequest == 1'd0 & Write4Blocks_21_exitcond210 == 1'd0)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp <= Write4Blocks_21_indvar_next18_i61;
if (^reset !== 1'bX && ^(Write4Blocks_21_indvar_next18_i61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %22*/
/* %indvar.i63 = phi i32 [ 0, %.lr.ph.us.i73 ], [ %indvar.next.i67, %22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32 & memory_controller_waitrequest == 1'd0 & Write4Blocks_22_exitcond188_reg == 1'd0)
begin
Write4Blocks_22_indvar_i63_phi_temp <= Write4Blocks_22_indvar_next_i67_reg;
if (^reset !== 1'bX && ^(Write4Blocks_22_indvar_next_i67_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_22_indvar_i63_phi_temp"); $finish; end
end
/* Write4Blocks: %22*/
/* %indvar.i63 = phi i32 [ 0, %.lr.ph.us.i73 ], [ %indvar.next.i67, %22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks_22_indvar_i63_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_22_indvar_i63_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_37 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB18_38 & memory_controller_waitrequest == 1'd0 & Write4Blocks_25_exitcond155 == 1'd0)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp <= Write4Blocks_25_indvar_next18_i24;
if (^reset !== 1'bX && ^(Write4Blocks_25_indvar_next18_i24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %26*/
/* %indvar.i26 = phi i32 [ 0, %.lr.ph.us.i36 ], [ %indvar.next.i30, %26 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41 & memory_controller_waitrequest == 1'd0 & Write4Blocks_26_exitcond_reg == 1'd0)
begin
Write4Blocks_26_indvar_i26_phi_temp <= Write4Blocks_26_indvar_next_i30_reg;
if (^reset !== 1'bX && ^(Write4Blocks_26_indvar_next_i30_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_26_indvar_i26_phi_temp"); $finish; end
end
/* Write4Blocks: %26*/
/* %indvar.i26 = phi i32 [ 0, %.lr.ph.us.i36 ], [ %indvar.next.i30, %26 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks_26_indvar_i26_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_26_indvar_i26_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* Write4Blocks: %38*/
/* ret void*/
if (cur_state == LEGUP_F_Write4Blocks_BB24_55)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_1)
begin
memory_controller_address = arg_p_out_vpos;
end
/* Write4Blocks: %0*/
/* %3 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_2)
begin
memory_controller_address = arg_p_out_hpos;
end
/* Write4Blocks: %0*/
/* %5 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* Write4Blocks: %0*/
/* %7 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* Write4Blocks: %12*/
/* %13 = load i32* %.14.us.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
memory_controller_address = Write4Blocks_12__14_us_i;
end
/* Write4Blocks: %12*/
/* store i8 %14, i8* %scevgep24.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13)
begin
memory_controller_address = Write4Blocks_12_scevgep24_i_reg;
end
/* Write4Blocks: %17*/
/* %18 = load i32* %.14.us.i103, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
memory_controller_address = Write4Blocks_17__14_us_i103;
end
/* Write4Blocks: %17*/
/* store i8 %19, i8* %scevgep24.i102, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23)
begin
memory_controller_address = Write4Blocks_17_scevgep24_i102_reg;
end
/* Write4Blocks: %22*/
/* %23 = load i32* %.14.us.i66, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
memory_controller_address = Write4Blocks_22__14_us_i66;
end
/* Write4Blocks: %22*/
/* store i8 %24, i8* %scevgep24.i65, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32)
begin
memory_controller_address = Write4Blocks_22_scevgep24_i65_reg;
end
/* Write4Blocks: %26*/
/* %27 = load i32* %.14.us.i29, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
memory_controller_address = Write4Blocks_26__14_us_i29;
end
/* Write4Blocks: %26*/
/* store i8 %28, i8* %scevgep24.i28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41)
begin
memory_controller_address = Write4Blocks_26_scevgep24_i28_reg;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %29 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_43)
begin
memory_controller_address = arg_p_out_hpos;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %30, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_45)
begin
memory_controller_address = arg_p_out_hpos;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_46)
begin
memory_controller_address = arg_p_out_vpos;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %32, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
memory_controller_address = arg_p_out_vpos;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_49)
begin
memory_controller_address = arg_p_out_hpos;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %34 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_50)
begin
memory_controller_address = `TAG_g_p_jinfo_MCUWidth_a;
end
/* Write4Blocks: %36*/
/* store i32 %31, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB22_53)
begin
memory_controller_address = arg_p_out_vpos;
end
/* Write4Blocks: %37*/
/* store i32 0, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB23_54)
begin
memory_controller_address = arg_p_out_hpos;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_1)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %0*/
/* %3 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_2)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %0*/
/* %5 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %0*/
/* %7 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %12*/
/* %13 = load i32* %.14.us.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %12*/
/* store i8 %14, i8* %scevgep24.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %17*/
/* %18 = load i32* %.14.us.i103, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %17*/
/* store i8 %19, i8* %scevgep24.i102, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %22*/
/* %23 = load i32* %.14.us.i66, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %22*/
/* store i8 %24, i8* %scevgep24.i65, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %26*/
/* %27 = load i32* %.14.us.i29, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %26*/
/* store i8 %28, i8* %scevgep24.i28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %29 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_43)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %30, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_45)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_46)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %32, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_49)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %34 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_50)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %36*/
/* store i32 %31, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB22_53)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %37*/
/* store i32 0, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB23_54)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_1)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %0*/
/* %3 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_2)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %0*/
/* %5 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %0*/
/* %7 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %12*/
/* %13 = load i32* %.14.us.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %12*/
/* store i8 %14, i8* %scevgep24.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %17*/
/* %18 = load i32* %.14.us.i103, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %17*/
/* store i8 %19, i8* %scevgep24.i102, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %22*/
/* %23 = load i32* %.14.us.i66, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %22*/
/* store i8 %24, i8* %scevgep24.i65, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %26*/
/* %27 = load i32* %.14.us.i29, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %26*/
/* store i8 %28, i8* %scevgep24.i28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %29 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_43)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %30, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_45)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_46)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %32, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_49)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %34 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_50)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %36*/
/* store i32 %31, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB22_53)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %37*/
/* store i32 0, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB23_54)
begin
memory_controller_write_enable = 1'd1;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* Write4Blocks: %12*/
/* store i8 %14, i8* %scevgep24.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13)
begin
memory_controller_in = Write4Blocks_12_14;
end
/* Write4Blocks: %17*/
/* store i8 %19, i8* %scevgep24.i102, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23)
begin
memory_controller_in = Write4Blocks_17_19;
end
/* Write4Blocks: %22*/
/* store i8 %24, i8* %scevgep24.i65, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32)
begin
memory_controller_in = Write4Blocks_22_24;
end
/* Write4Blocks: %26*/
/* store i8 %28, i8* %scevgep24.i28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41)
begin
memory_controller_in = Write4Blocks_26_28;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %30, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_45)
begin
memory_controller_in = Write4Blocks_WriteOneBlock_exit37_30;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %32, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
memory_controller_in = Write4Blocks_WriteOneBlock_exit37_32;
end
/* Write4Blocks: %36*/
/* store i32 %31, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB22_53)
begin
memory_controller_in = Write4Blocks_WriteOneBlock_exit37_31_reg;
end
/* Write4Blocks: %37*/
/* store i32 0, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB23_54)
begin
memory_controller_in = 32'd0;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_1)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %0*/
/* %3 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_2)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %0*/
/* %5 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
memory_controller_size = 2'd1;
end
/* Write4Blocks: %0*/
/* %7 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
memory_controller_size = 2'd1;
end
/* Write4Blocks: %12*/
/* %13 = load i32* %.14.us.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %12*/
/* store i8 %14, i8* %scevgep24.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13)
begin
memory_controller_size = 2'd0;
end
/* Write4Blocks: %17*/
/* %18 = load i32* %.14.us.i103, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %17*/
/* store i8 %19, i8* %scevgep24.i102, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23)
begin
memory_controller_size = 2'd0;
end
/* Write4Blocks: %22*/
/* %23 = load i32* %.14.us.i66, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %22*/
/* store i8 %24, i8* %scevgep24.i65, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32)
begin
memory_controller_size = 2'd0;
end
/* Write4Blocks: %26*/
/* %27 = load i32* %.14.us.i29, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %26*/
/* store i8 %28, i8* %scevgep24.i28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41)
begin
memory_controller_size = 2'd0;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %29 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_43)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %30, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_45)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_46)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %32, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_49)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %34 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_50)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %36*/
/* store i32 %31, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB22_53)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %37*/
/* store i32 0, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB23_54)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module decode_block
(
clk,
reset,
start,
finish,
arg_comp_no,
arg_out_buf,
arg_HuffBuff,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [7:0] LEGUP_0 = 8'd0;
parameter [7:0] LEGUP_F_decode_block_BB0_1 = 8'd1;
parameter [7:0] LEGUP_F_decode_block_BB0_2 = 8'd2;
parameter [7:0] LEGUP_F_decode_block_BB0_3 = 8'd3;
parameter [7:0] LEGUP_F_decode_block_BB0_4 = 8'd4;
parameter [7:0] LEGUP_F_decode_block_BB0_5 = 8'd5;
parameter [7:0] LEGUP_F_decode_block_BB1_8 = 8'd8;
parameter [7:0] LEGUP_F_decode_block_BB1_11 = 8'd11;
parameter [7:0] LEGUP_F_decode_block_BB1_12 = 8'd12;
parameter [7:0] LEGUP_F_decode_block_BB1_13 = 8'd13;
parameter [7:0] LEGUP_F_decode_block_BB2_14 = 8'd14;
parameter [7:0] LEGUP_F_decode_block_BB2_15 = 8'd15;
parameter [7:0] LEGUP_F_decode_block_BB2_16 = 8'd16;
parameter [7:0] LEGUP_F_decode_block_BB3_17 = 8'd17;
parameter [7:0] LEGUP_F_decode_block_BB3_18 = 8'd18;
parameter [7:0] LEGUP_F_decode_block_BB3_19 = 8'd19;
parameter [7:0] LEGUP_F_decode_block_BB4_20 = 8'd20;
parameter [7:0] LEGUP_F_decode_block_BB5_21 = 8'd21;
parameter [7:0] LEGUP_F_decode_block_BB6_22 = 8'd22;
parameter [7:0] LEGUP_F_decode_block_BB7_23 = 8'd23;
parameter [7:0] LEGUP_F_decode_block_BB7_24 = 8'd24;
parameter [7:0] LEGUP_F_decode_block_BB7_25 = 8'd25;
parameter [7:0] LEGUP_F_decode_block_BB8_28 = 8'd28;
parameter [7:0] LEGUP_F_decode_block_BB9_29 = 8'd29;
parameter [7:0] LEGUP_F_decode_block_BB9_32 = 8'd32;
parameter [7:0] LEGUP_F_decode_block_BB9_33 = 8'd33;
parameter [7:0] LEGUP_F_decode_block_BB9_34 = 8'd34;
parameter [7:0] LEGUP_F_decode_block_BB9_35 = 8'd35;
parameter [7:0] LEGUP_F_decode_block_BB10_36 = 8'd36;
parameter [7:0] LEGUP_F_decode_block_BB10_37 = 8'd37;
parameter [7:0] LEGUP_F_decode_block_BB10_38 = 8'd38;
parameter [7:0] LEGUP_F_decode_block_BB11_39 = 8'd39;
parameter [7:0] LEGUP_F_decode_block_BB12_40 = 8'd40;
parameter [7:0] LEGUP_F_decode_block_BB13_41 = 8'd41;
parameter [7:0] LEGUP_F_decode_block_BB14_42 = 8'd42;
parameter [7:0] LEGUP_F_decode_block_BB14_43 = 8'd43;
parameter [7:0] LEGUP_F_decode_block_BB14_44 = 8'd44;
parameter [7:0] LEGUP_F_decode_block_BB14_45 = 8'd45;
parameter [7:0] LEGUP_F_decode_block_BB14_46 = 8'd46;
parameter [7:0] LEGUP_F_decode_block_BB15_47 = 8'd47;
parameter [7:0] LEGUP_F_decode_block_BB15_48 = 8'd48;
parameter [7:0] LEGUP_F_decode_block_BB15_49 = 8'd49;
parameter [7:0] LEGUP_F_decode_block_BB16_50 = 8'd50;
parameter [7:0] LEGUP_F_decode_block_BB16_51 = 8'd51;
parameter [7:0] LEGUP_F_decode_block_BB16_52 = 8'd52;
parameter [7:0] LEGUP_F_decode_block_BB16_53 = 8'd53;
parameter [7:0] LEGUP_F_decode_block_BB17_54 = 8'd54;
parameter [7:0] LEGUP_F_decode_block_BB17_55 = 8'd55;
parameter [7:0] LEGUP_F_decode_block_BB17_56 = 8'd56;
parameter [7:0] LEGUP_F_decode_block_BB17_57 = 8'd57;
parameter [7:0] LEGUP_F_decode_block_BB17_58 = 8'd58;
parameter [7:0] LEGUP_F_decode_block_BB17_59 = 8'd59;
parameter [7:0] LEGUP_F_decode_block_BB17_60 = 8'd60;
parameter [7:0] LEGUP_F_decode_block_BB17_61 = 8'd61;
parameter [7:0] LEGUP_F_decode_block_BB17_62 = 8'd62;
parameter [7:0] LEGUP_F_decode_block_BB17_63 = 8'd63;
parameter [7:0] LEGUP_F_decode_block_BB17_64 = 8'd64;
parameter [7:0] LEGUP_F_decode_block_BB17_65 = 8'd65;
parameter [7:0] LEGUP_F_decode_block_BB17_66 = 8'd66;
parameter [7:0] LEGUP_F_decode_block_BB17_67 = 8'd67;
parameter [7:0] LEGUP_F_decode_block_BB17_68 = 8'd68;
parameter [7:0] LEGUP_F_decode_block_BB17_69 = 8'd69;
parameter [7:0] LEGUP_F_decode_block_BB17_70 = 8'd70;
parameter [7:0] LEGUP_F_decode_block_BB17_71 = 8'd71;
parameter [7:0] LEGUP_F_decode_block_BB18_72 = 8'd72;
parameter [7:0] LEGUP_F_decode_block_BB18_73 = 8'd73;
parameter [7:0] LEGUP_F_decode_block_BB18_74 = 8'd74;
parameter [7:0] LEGUP_F_decode_block_BB18_75 = 8'd75;
parameter [7:0] LEGUP_F_decode_block_BB18_76 = 8'd76;
parameter [7:0] LEGUP_F_decode_block_BB18_77 = 8'd77;
parameter [7:0] LEGUP_F_decode_block_BB18_78 = 8'd78;
parameter [7:0] LEGUP_F_decode_block_BB18_79 = 8'd79;
parameter [7:0] LEGUP_F_decode_block_BB18_80 = 8'd80;
parameter [7:0] LEGUP_F_decode_block_BB18_81 = 8'd81;
parameter [7:0] LEGUP_F_decode_block_BB18_82 = 8'd82;
parameter [7:0] LEGUP_F_decode_block_BB18_83 = 8'd83;
parameter [7:0] LEGUP_F_decode_block_BB18_84 = 8'd84;
parameter [7:0] LEGUP_F_decode_block_BB18_85 = 8'd85;
parameter [7:0] LEGUP_F_decode_block_BB18_86 = 8'd86;
parameter [7:0] LEGUP_F_decode_block_BB18_87 = 8'd87;
parameter [7:0] LEGUP_F_decode_block_BB18_88 = 8'd88;
parameter [7:0] LEGUP_F_decode_block_BB18_89 = 8'd89;
parameter [7:0] LEGUP_F_decode_block_BB19_90 = 8'd90;
parameter [7:0] LEGUP_F_decode_block_BB19_91 = 8'd91;
parameter [7:0] LEGUP_F_decode_block_BB19_92 = 8'd92;
parameter [7:0] LEGUP_F_decode_block_BB19_93 = 8'd93;
parameter [7:0] LEGUP_F_decode_block_BB19_94 = 8'd94;
parameter [7:0] LEGUP_F_decode_block_BB19_95 = 8'd95;
parameter [7:0] LEGUP_F_decode_block_BB19_96 = 8'd96;
parameter [7:0] LEGUP_F_decode_block_BB19_97 = 8'd97;
parameter [7:0] LEGUP_F_decode_block_BB19_98 = 8'd98;
parameter [7:0] LEGUP_F_decode_block_BB19_99 = 8'd99;
parameter [7:0] LEGUP_F_decode_block_BB19_100 = 8'd100;
parameter [7:0] LEGUP_F_decode_block_BB19_101 = 8'd101;
parameter [7:0] LEGUP_F_decode_block_BB19_102 = 8'd102;
parameter [7:0] LEGUP_F_decode_block_BB19_103 = 8'd103;
parameter [7:0] LEGUP_F_decode_block_BB19_104 = 8'd104;
parameter [7:0] LEGUP_F_decode_block_BB19_105 = 8'd105;
parameter [7:0] LEGUP_F_decode_block_BB19_106 = 8'd106;
parameter [7:0] LEGUP_F_decode_block_BB19_107 = 8'd107;
parameter [7:0] LEGUP_F_decode_block_BB19_108 = 8'd108;
parameter [7:0] LEGUP_F_decode_block_BB19_109 = 8'd109;
parameter [7:0] LEGUP_F_decode_block_BB19_110 = 8'd110;
parameter [7:0] LEGUP_F_decode_block_BB19_111 = 8'd111;
parameter [7:0] LEGUP_F_decode_block_BB19_112 = 8'd112;
parameter [7:0] LEGUP_F_decode_block_BB19_113 = 8'd113;
parameter [7:0] LEGUP_F_decode_block_BB19_114 = 8'd114;
parameter [7:0] LEGUP_F_decode_block_BB19_115 = 8'd115;
parameter [7:0] LEGUP_F_decode_block_BB19_116 = 8'd116;
parameter [7:0] LEGUP_F_decode_block_BB19_117 = 8'd117;
parameter [7:0] LEGUP_F_decode_block_BB19_118 = 8'd118;
parameter [7:0] LEGUP_F_decode_block_BB19_119 = 8'd119;
parameter [7:0] LEGUP_F_decode_block_BB19_120 = 8'd120;
parameter [7:0] LEGUP_F_decode_block_BB19_121 = 8'd121;
parameter [7:0] LEGUP_F_decode_block_BB19_122 = 8'd122;
parameter [7:0] LEGUP_F_decode_block_BB19_123 = 8'd123;
parameter [7:0] LEGUP_F_decode_block_BB19_124 = 8'd124;
parameter [7:0] LEGUP_F_decode_block_BB19_125 = 8'd125;
parameter [7:0] LEGUP_F_decode_block_BB19_126 = 8'd126;
parameter [7:0] LEGUP_F_decode_block_BB19_127 = 8'd127;
parameter [7:0] LEGUP_F_decode_block_BB19_128 = 8'd128;
parameter [7:0] LEGUP_F_decode_block_BB19_129 = 8'd129;
parameter [7:0] LEGUP_F_decode_block_BB19_130 = 8'd130;
parameter [7:0] LEGUP_F_decode_block_BB19_131 = 8'd131;
parameter [7:0] LEGUP_F_decode_block_BB19_132 = 8'd132;
parameter [7:0] LEGUP_F_decode_block_BB19_133 = 8'd133;
parameter [7:0] LEGUP_F_decode_block_BB19_134 = 8'd134;
parameter [7:0] LEGUP_F_decode_block_BB19_135 = 8'd135;
parameter [7:0] LEGUP_F_decode_block_BB19_136 = 8'd136;
parameter [7:0] LEGUP_F_decode_block_BB19_137 = 8'd137;
parameter [7:0] LEGUP_F_decode_block_BB19_138 = 8'd138;
parameter [7:0] LEGUP_F_decode_block_BB19_139 = 8'd139;
parameter [7:0] LEGUP_F_decode_block_BB19_140 = 8'd140;
parameter [7:0] LEGUP_F_decode_block_BB20_141 = 8'd141;
parameter [7:0] LEGUP_F_decode_block_BB20_142 = 8'd142;
parameter [7:0] LEGUP_F_decode_block_BB20_143 = 8'd143;
parameter [7:0] LEGUP_F_decode_block_BB21_144 = 8'd144;
parameter [7:0] LEGUP_F_decode_block_BB21_145 = 8'd145;
parameter [7:0] LEGUP_F_decode_block_BB21_146 = 8'd146;
parameter [7:0] LEGUP_F_decode_block_BB22_147 = 8'd147;
parameter [7:0] LEGUP_F_decode_block_BB23_148 = 8'd148;
parameter [7:0] LEGUP_F_decode_block_BB24_149 = 8'd149;
parameter [7:0] LEGUP_F_decode_block_BB25_150 = 8'd150;
parameter [7:0] LEGUP_F_decode_block_BB26_151 = 8'd151;
parameter [7:0] LEGUP_function_call_6 = 8'd6;
parameter [7:0] LEGUP_function_call_7 = 8'd7;
parameter [7:0] LEGUP_function_call_9 = 8'd9;
parameter [7:0] LEGUP_function_call_10 = 8'd10;
parameter [7:0] LEGUP_function_call_26 = 8'd26;
parameter [7:0] LEGUP_function_call_27 = 8'd27;
parameter [7:0] LEGUP_function_call_30 = 8'd30;
parameter [7:0] LEGUP_function_call_31 = 8'd31;
input clk;
input reset;
input start;
output reg finish;
input [31:0] arg_comp_no;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_out_buf;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_HuffBuff;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [7:0] cur_state;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_1;
reg [7:0] decode_block_0_2;
reg [31:0] decode_block_0_3;
reg [31:0] decode_block_0_3_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_4_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_5;
reg [31:0] decode_block_0_6;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_7_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_8;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_8_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_9;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_9_reg;
reg [31:0] decode_block_0_10;
reg [31:0] decode_block_0_10_reg;
reg decode_block_0_11;
reg [31:0] decode_block_12_13;
reg [31:0] decode_block_12_13_reg;
reg [31:0] decode_block_12_14;
reg [31:0] decode_block_12_14_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_12_15;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_12_15_reg;
reg [31:0] decode_block_12_16;
reg [31:0] decode_block_12_17;
reg decode_block_12_18;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_19_20;
reg [31:0] decode_block_19_21;
reg [31:0] decode_block_19_22;
reg [31:0] decode_block_19_23;
reg [31:0] decode_block_24_diff_0_i;
reg [31:0] decode_block_24_diff_0_i_reg;
reg [31:0] decode_block_24_25;
reg [31:0] decode_block_24_26;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_27;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_27_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_28;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_28_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_29;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_29_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_30;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_30_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_31;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_31_reg;
reg [31:0] decode_block__lr_ph_i_indvar_i2;
reg [31:0] decode_block__lr_ph_i_tmp_i4;
reg [31:0] decode_block__lr_ph_i_tmp4_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__lr_ph_i_mptr_03_i;
reg decode_block__lr_ph_i_32;
reg [31:0] decode_block__backedge_i_k_0_i;
reg [31:0] decode_block__backedge_i_k_0_i_reg;
reg decode_block__backedge_i_33;
reg [31:0] decode_block_34_35;
reg [31:0] decode_block_34_36;
reg [31:0] decode_block_34_36_reg;
reg [31:0] decode_block_34_37;
reg [31:0] decode_block_34_37_reg;
reg [31:0] decode_block_34_38;
reg [31:0] decode_block_34_39;
reg [31:0] decode_block_34_39_reg;
reg decode_block_34_40;
reg [31:0] decode_block_41_42;
reg [31:0] decode_block_41_42_reg;
reg decode_block_41_43;
reg [31:0] decode_block_44_45;
reg [31:0] decode_block_44_45_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_44_46;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_44_46_reg;
reg [31:0] decode_block_44_47;
reg [31:0] decode_block_44_47_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_44_48;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_44_48_reg;
reg [31:0] decode_block_44_49;
reg [31:0] decode_block_44_50;
reg decode_block_44_51;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_52_53;
reg [31:0] decode_block_52_54;
reg [31:0] decode_block_52_55;
reg [31:0] decode_block_52_56;
reg [31:0] decode_block_57_58;
reg decode_block_59_60;
reg [31:0] decode_block_61_62;
reg [31:0] decode_block_DecodeHuffMCU_exit_i_02_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_DecodeHuffMCU_exit__01_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_DecodeHuffMCU_exit__01_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_DecodeHuffMCU_exit_scevgep_i;
reg [31:0] decode_block_DecodeHuffMCU_exit_63;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_DecodeHuffMCU_exit_64;
reg [31:0] decode_block_DecodeHuffMCU_exit_65;
reg [31:0] decode_block_DecodeHuffMCU_exit_66;
reg [31:0] decode_block_DecodeHuffMCU_exit_66_reg;
reg decode_block_DecodeHuffMCU_exit_exitcond10;
reg decode_block_DecodeHuffMCU_exit_exitcond10_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IZigzagMatrix_exit_67;
reg [7:0] decode_block_IZigzagMatrix_exit_68;
reg [31:0] decode_block_IZigzagMatrix_exit_tmp;
reg [31:0] decode_block_IZigzagMatrix_exit_tmp9;
reg [31:0] decode_block_IZigzagMatrix_exit_tmp9_reg;
reg [31:0] decode_block_69_indvar_i4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_69__01_i6;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_69__01_i6_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_69_mptr_02_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_69_mptr_02_i_reg;
reg [31:0] decode_block_69_tmp_i5;
reg [31:0] decode_block_69_tmp_i5_reg;
reg [31:0] decode_block_69_70;
reg [31:0] decode_block_69_70_reg;
reg [31:0] decode_block_69_71;
reg [31:0] decode_block_69_72;
reg decode_block_69_exitcond8;
reg decode_block_69_exitcond8_reg;
reg [31:0] decode_block_IQuantize_exit_i_027_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep44_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep45_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep45_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp46_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep47_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep47_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep48_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep48_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp49_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep50_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep50_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep51_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep51_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp52_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep53_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep53_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep54_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep54_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp55_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep56_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep56_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep57_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep57_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp58_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep59_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep59_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep60_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep60_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp61_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep62_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep62_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep63_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep63_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp64_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep65_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep65_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep66_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep66_i_reg;
reg [31:0] decode_block_IQuantize_exit_73;
reg [31:0] decode_block_IQuantize_exit_74;
reg [31:0] decode_block_IQuantize_exit_74_reg;
reg [31:0] decode_block_IQuantize_exit_75;
reg [31:0] decode_block_IQuantize_exit_76;
reg [31:0] decode_block_IQuantize_exit_77;
reg [31:0] decode_block_IQuantize_exit_78;
reg [31:0] decode_block_IQuantize_exit_79;
reg [31:0] decode_block_IQuantize_exit_80;
reg [31:0] decode_block_IQuantize_exit_81;
reg [31:0] decode_block_IQuantize_exit_82;
reg [31:0] decode_block_IQuantize_exit_83;
reg [31:0] decode_block_IQuantize_exit_83_reg;
reg [31:0] decode_block_IQuantize_exit_84;
reg [31:0] decode_block_IQuantize_exit_85;
reg [31:0] decode_block_IQuantize_exit_86;
reg [31:0] decode_block_IQuantize_exit_86_reg;
reg [31:0] decode_block_IQuantize_exit_87;
reg [31:0] decode_block_IQuantize_exit_88;
reg [31:0] decode_block_IQuantize_exit_88_reg;
reg [31:0] decode_block_IQuantize_exit_89;
reg [31:0] decode_block_IQuantize_exit_90;
reg [31:0] decode_block_IQuantize_exit_90_reg;
reg [31:0] decode_block_IQuantize_exit_91;
reg [31:0] decode_block_IQuantize_exit_91_reg;
reg [31:0] decode_block_IQuantize_exit_92;
reg [31:0] decode_block_IQuantize_exit_93;
reg [31:0] decode_block_IQuantize_exit_94;
reg [31:0] decode_block_IQuantize_exit_94_reg;
reg [31:0] decode_block_IQuantize_exit_95;
reg [31:0] decode_block_IQuantize_exit_95_reg;
reg [31:0] decode_block_IQuantize_exit_96;
reg [31:0] decode_block_IQuantize_exit_97;
reg [31:0] decode_block_IQuantize_exit_98;
reg [31:0] decode_block_IQuantize_exit_98_reg;
reg [31:0] decode_block_IQuantize_exit_99;
reg [31:0] decode_block_IQuantize_exit_100;
reg [31:0] decode_block_IQuantize_exit_100_reg;
reg [31:0] decode_block_IQuantize_exit_101;
reg [31:0] decode_block_IQuantize_exit_101_reg;
reg [31:0] decode_block_IQuantize_exit_102;
reg [31:0] decode_block_IQuantize_exit_103;
reg [31:0] decode_block_IQuantize_exit_103_reg;
reg [31:0] decode_block_IQuantize_exit_104;
reg [31:0] decode_block_IQuantize_exit_104_reg;
reg [31:0] decode_block_IQuantize_exit_105;
reg [31:0] decode_block_IQuantize_exit_105_reg;
reg [31:0] decode_block_IQuantize_exit_106;
reg [31:0] decode_block_IQuantize_exit_107;
reg [31:0] decode_block_IQuantize_exit_108;
reg [31:0] decode_block_IQuantize_exit_108_reg;
reg [31:0] decode_block_IQuantize_exit_109;
reg [31:0] decode_block_IQuantize_exit_109_reg;
reg [31:0] decode_block_IQuantize_exit_110;
reg [31:0] decode_block_IQuantize_exit_111;
reg [31:0] decode_block_IQuantize_exit_112;
reg [31:0] decode_block_IQuantize_exit_112_reg;
reg [31:0] decode_block_IQuantize_exit_113;
reg [31:0] decode_block_IQuantize_exit_113_reg;
reg [31:0] decode_block_IQuantize_exit_114;
reg [31:0] decode_block_IQuantize_exit_114_reg;
reg [31:0] decode_block_IQuantize_exit_115;
reg [31:0] decode_block_IQuantize_exit_115_reg;
reg [31:0] decode_block_IQuantize_exit_116;
reg [31:0] decode_block_IQuantize_exit_116_reg;
reg [31:0] decode_block_IQuantize_exit_117;
reg [31:0] decode_block_IQuantize_exit_118;
reg [31:0] decode_block_IQuantize_exit_119;
reg [31:0] decode_block_IQuantize_exit_120;
reg [31:0] decode_block_IQuantize_exit_121;
reg [31:0] decode_block_IQuantize_exit_122;
reg [31:0] decode_block_IQuantize_exit_122_reg;
reg [31:0] decode_block_IQuantize_exit_123;
reg [31:0] decode_block_IQuantize_exit_124;
reg [31:0] decode_block_IQuantize_exit_125;
reg [31:0] decode_block_IQuantize_exit_125_reg;
reg [31:0] decode_block_IQuantize_exit_126;
reg [31:0] decode_block_IQuantize_exit_127;
reg [31:0] decode_block_IQuantize_exit_128;
reg [31:0] decode_block_IQuantize_exit_129;
reg [31:0] decode_block_IQuantize_exit_129_reg;
reg [31:0] decode_block_IQuantize_exit_130;
reg [31:0] decode_block_IQuantize_exit_130_reg;
reg [31:0] decode_block_IQuantize_exit_131;
reg [31:0] decode_block_IQuantize_exit_131_reg;
reg [31:0] decode_block_IQuantize_exit_132;
reg [31:0] decode_block_IQuantize_exit_132_reg;
reg [31:0] decode_block_IQuantize_exit_133;
reg [31:0] decode_block_IQuantize_exit_133_reg;
reg [31:0] decode_block_IQuantize_exit_134;
reg [31:0] decode_block_IQuantize_exit_134_reg;
reg [31:0] decode_block_IQuantize_exit_135;
reg [31:0] decode_block_IQuantize_exit_135_reg;
reg decode_block_IQuantize_exit_exitcond43_i;
reg decode_block_IQuantize_exit_exitcond43_i_reg;
reg [31:0] decode_block__preheader25_i_i_126_i;
reg [31:0] decode_block__preheader25_i_tmp_i6;
reg [31:0] decode_block__preheader25_i_tmp2967_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep_i7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep_i7_reg;
reg [31:0] decode_block__preheader25_i_tmp3068_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep31_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep31_i_reg;
reg [31:0] decode_block__preheader25_i_tmp3269_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep33_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep33_i_reg;
reg [31:0] decode_block__preheader25_i_tmp3470_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep35_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep35_i_reg;
reg [31:0] decode_block__preheader25_i_tmp3671_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep37_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep37_i_reg;
reg [31:0] decode_block__preheader25_i_tmp3872_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep39_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep39_i_reg;
reg [31:0] decode_block__preheader25_i_tmp4073_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep41_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep41_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep42_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep42_i_reg;
reg [31:0] decode_block__preheader25_i_136;
reg [31:0] decode_block__preheader25_i_136_reg;
reg [31:0] decode_block__preheader25_i_137;
reg [31:0] decode_block__preheader25_i_138;
reg [31:0] decode_block__preheader25_i_139;
reg [31:0] decode_block__preheader25_i_140;
reg [31:0] decode_block__preheader25_i_141;
reg [31:0] decode_block__preheader25_i_142;
reg [31:0] decode_block__preheader25_i_143;
reg [31:0] decode_block__preheader25_i_144;
reg [31:0] decode_block__preheader25_i_144_reg;
reg [31:0] decode_block__preheader25_i_145;
reg [31:0] decode_block__preheader25_i_146;
reg [31:0] decode_block__preheader25_i_147;
reg [31:0] decode_block__preheader25_i_147_reg;
reg [31:0] decode_block__preheader25_i_148;
reg [31:0] decode_block__preheader25_i_149;
reg [31:0] decode_block__preheader25_i_149_reg;
reg [31:0] decode_block__preheader25_i_150;
reg [31:0] decode_block__preheader25_i_151;
reg [31:0] decode_block__preheader25_i_151_reg;
reg [31:0] decode_block__preheader25_i_152;
reg [31:0] decode_block__preheader25_i_152_reg;
reg [31:0] decode_block__preheader25_i_153;
reg [31:0] decode_block__preheader25_i_154;
reg [31:0] decode_block__preheader25_i_155;
reg [31:0] decode_block__preheader25_i_155_reg;
reg [31:0] decode_block__preheader25_i_156;
reg [31:0] decode_block__preheader25_i_156_reg;
reg [31:0] decode_block__preheader25_i_157;
reg [31:0] decode_block__preheader25_i_158;
reg [31:0] decode_block__preheader25_i_159;
reg [31:0] decode_block__preheader25_i_159_reg;
reg [31:0] decode_block__preheader25_i_160;
reg [31:0] decode_block__preheader25_i_161;
reg [31:0] decode_block__preheader25_i_162;
reg [31:0] decode_block__preheader25_i_162_reg;
reg [31:0] decode_block__preheader25_i_163;
reg [31:0] decode_block__preheader25_i_164;
reg [31:0] decode_block__preheader25_i_165;
reg [31:0] decode_block__preheader25_i_165_reg;
reg [31:0] decode_block__preheader25_i_166;
reg [31:0] decode_block__preheader25_i_166_reg;
reg [31:0] decode_block__preheader25_i_167;
reg [31:0] decode_block__preheader25_i_168;
reg [31:0] decode_block__preheader25_i_169;
reg [31:0] decode_block__preheader25_i_169_reg;
reg [31:0] decode_block__preheader25_i_170;
reg [31:0] decode_block__preheader25_i_170_reg;
reg [31:0] decode_block__preheader25_i_171;
reg [31:0] decode_block__preheader25_i_172;
reg [31:0] decode_block__preheader25_i_173;
reg [31:0] decode_block__preheader25_i_173_reg;
reg [31:0] decode_block__preheader25_i_174;
reg [31:0] decode_block__preheader25_i_174_reg;
reg [31:0] decode_block__preheader25_i_175;
reg [31:0] decode_block__preheader25_i_175_reg;
reg [31:0] decode_block__preheader25_i_176;
reg [31:0] decode_block__preheader25_i_176_reg;
reg [31:0] decode_block__preheader25_i_177;
reg [31:0] decode_block__preheader25_i_177_reg;
reg [31:0] decode_block__preheader25_i_178;
reg [31:0] decode_block__preheader25_i_179;
reg [31:0] decode_block__preheader25_i_180;
reg [31:0] decode_block__preheader25_i_181;
reg [31:0] decode_block__preheader25_i_182;
reg [31:0] decode_block__preheader25_i_183;
reg [31:0] decode_block__preheader25_i_183_reg;
reg [31:0] decode_block__preheader25_i_184;
reg [31:0] decode_block__preheader25_i_185;
reg [31:0] decode_block__preheader25_i_186;
reg [31:0] decode_block__preheader25_i_186_reg;
reg [31:0] decode_block__preheader25_i_187;
reg [31:0] decode_block__preheader25_i_188;
reg [31:0] decode_block__preheader25_i_189;
reg [31:0] decode_block__preheader25_i_190;
reg [31:0] decode_block__preheader25_i_190_reg;
reg [31:0] decode_block__preheader25_i_191;
reg [31:0] decode_block__preheader25_i_191_reg;
reg [31:0] decode_block__preheader25_i_192;
reg [31:0] decode_block__preheader25_i_192_reg;
reg [31:0] decode_block__preheader25_i_193;
reg [31:0] decode_block__preheader25_i_193_reg;
reg [31:0] decode_block__preheader25_i_194;
reg [31:0] decode_block__preheader25_i_194_reg;
reg [31:0] decode_block__preheader25_i_195;
reg [31:0] decode_block__preheader25_i_195_reg;
reg [31:0] decode_block__preheader25_i_196;
reg [31:0] decode_block__preheader25_i_196_reg;
reg decode_block__preheader25_i_exitcond28_i;
reg decode_block__preheader25_i_exitcond28_i_reg;
reg [31:0] decode_block__preheader_i8_i_224_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i8_aptr_023_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i8_aptr_023_i_reg;
reg [31:0] decode_block__preheader_i8_197;
reg [31:0] decode_block__preheader_i8_198;
reg [31:0] decode_block__preheader_i8_199;
reg [31:0] decode_block__preheader_i8_200;
reg [31:0] decode_block__preheader_i8_201;
reg [31:0] decode_block__preheader_i8_201_reg;
reg [31:0] decode_block__preheader_i8_202;
reg [31:0] decode_block__preheader_i8_202_reg;
reg [31:0] decode_block__preheader_i8_203;
reg [31:0] decode_block__preheader_i8_203_reg;
reg decode_block__preheader_i8_exitcond_i;
reg decode_block__preheader_i8_exitcond_i_reg;
reg [31:0] decode_block_ChenIDct_exit_indvar_i1;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_ChenIDct_exit_mptr_01_i2;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_ChenIDct_exit_mptr_01_i2_reg;
reg [31:0] decode_block_ChenIDct_exit_tmp_i3;
reg [31:0] decode_block_ChenIDct_exit_tmp_i3_reg;
reg [31:0] decode_block_ChenIDct_exit_204;
reg [31:0] decode_block_ChenIDct_exit_205;
reg decode_block_ChenIDct_exit_exitcond7;
reg decode_block_ChenIDct_exit_exitcond7_reg;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_indvar_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_PostshiftIDctMatrix_exit_mptr_01_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_PostshiftIDctMatrix_exit_mptr_01_i_reg;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_tmp_i;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_tmp_i_reg;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_206;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_206_reg;
reg decode_block_PostshiftIDctMatrix_exit_207;
reg decode_block_209_210;
reg decode_block_212_exitcond;
reg DecodeHuffman_start;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_arg_Xhuff_huffval;
reg [31:0] DecodeHuffman_arg_Dhuff_ml;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_arg_Dhuff_maxcode;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_arg_Dhuff_mincode;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_arg_Dhuff_valptr;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_memory_controller_address;
wire DecodeHuffman_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] DecodeHuffman_memory_controller_in;
reg DecodeHuffman_memory_controller_waitrequest;
wire DecodeHuffman_memory_controller_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] DecodeHuffman_memory_controller_out;
wire [1:0] DecodeHuffman_memory_controller_size;
wire DecodeHuffman_finish;
wire [31:0] DecodeHuffman_return_val;
reg legup_function_call;
reg buf_getv_start;
reg [31:0] buf_getv_arg_n;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_memory_controller_address;
wire buf_getv_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] buf_getv_memory_controller_in;
reg buf_getv_memory_controller_waitrequest;
wire buf_getv_memory_controller_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] buf_getv_memory_controller_out;
wire [1:0] buf_getv_memory_controller_size;
wire buf_getv_finish;
wire [31:0] buf_getv_return_val;
reg [31:0] decode_block_signed_multiply_32_1_op0;
reg [31:0] decode_block_signed_multiply_32_1_op1;
reg [31:0] decode_block_signed_multiply_32_1;
reg [31:0] decode_block_signed_multiply_32_0_op0;
reg [31:0] decode_block_signed_multiply_32_0_op1;
reg [31:0] decode_block_signed_multiply_32_0;
reg [31:0] decode_block_signed_multiply_32_2_op0;
reg [31:0] decode_block_signed_multiply_32_2_op1;
reg [31:0] decode_block_signed_multiply_32_2;
reg [31:0] decode_block_signed_multiply_32_3_op0;
reg [31:0] decode_block_signed_multiply_32_3_op1;
reg [31:0] decode_block_signed_multiply_32_3;
reg [31:0] decode_block_signed_divide_32_0_op0;
reg [31:0] decode_block_signed_divide_32_0_op1;
reg [31:0] decode_block_signed_divide_32_0;
wire [31:0] lpm_divide_decode_block__preheader_i8_202_out;
wire [31:0] decode_block__preheader_i8_202_unused;
reg lpm_divide_decode_block__preheader_i8_202_en;
reg [31:0] decode_block__lr_ph_i_indvar_i2_phi_temp;
reg [31:0] decode_block_24_diff_0_i_phi_temp;
reg [31:0] decode_block__backedge_i_k_0_i_phi_temp;
reg [31:0] decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp;
reg [31:0] decode_block_69_indvar_i4_phi_temp;
reg [31:0] decode_block_IQuantize_exit_i_027_i_phi_temp;
reg [31:0] decode_block__preheader25_i_i_126_i_phi_temp;
reg [31:0] decode_block__preheader_i8_i_224_i_phi_temp;
reg [31:0] decode_block_ChenIDct_exit_indvar_i1_phi_temp;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp;
/* %202 = sdiv i32 %201, 16*/
lpm_divide lpm_divide_decode_block__preheader_i8_202 (
.numer (decode_block_signed_divide_32_0_op0),
.denom (decode_block_signed_divide_32_0_op1),
.quotient (lpm_divide_decode_block__preheader_i8_202_out),
.remain (decode_block__preheader_i8_202_unused),
.clock (clk),
.aclr (1'd0),
.clken (lpm_divide_decode_block__preheader_i8_202_en)
);
defparam
lpm_divide_decode_block__preheader_i8_202.lpm_pipeline = 32,
lpm_divide_decode_block__preheader_i8_202.lpm_widthd = 32,
lpm_divide_decode_block__preheader_i8_202.lpm_widthn = 32,
lpm_divide_decode_block__preheader_i8_202.lpm_drepresentation = "SIGNED",
lpm_divide_decode_block__preheader_i8_202.lpm_nrepresentation = "SIGNED",
lpm_divide_decode_block__preheader_i8_202.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE";
DecodeHuffman DecodeHuffman_inst (
.clk (clk),
.reset (reset),
.start (DecodeHuffman_start),
.finish (DecodeHuffman_finish),
.return_val (DecodeHuffman_return_val),
.memory_controller_address (DecodeHuffman_memory_controller_address),
.memory_controller_write_enable (DecodeHuffman_memory_controller_write_enable),
.memory_controller_enable (DecodeHuffman_memory_controller_enable),
.memory_controller_in (DecodeHuffman_memory_controller_in),
.memory_controller_size (DecodeHuffman_memory_controller_size),
.memory_controller_waitrequest (DecodeHuffman_memory_controller_waitrequest),
.memory_controller_out (DecodeHuffman_memory_controller_out),
.arg_Xhuff_huffval (DecodeHuffman_arg_Xhuff_huffval),
.arg_Dhuff_ml (DecodeHuffman_arg_Dhuff_ml),
.arg_Dhuff_maxcode (DecodeHuffman_arg_Dhuff_maxcode),
.arg_Dhuff_mincode (DecodeHuffman_arg_Dhuff_mincode),
.arg_Dhuff_valptr (DecodeHuffman_arg_Dhuff_valptr)
);
buf_getv buf_getv_inst (
.clk (clk),
.reset (reset),
.start (buf_getv_start),
.finish (buf_getv_finish),
.return_val (buf_getv_return_val),
.memory_controller_address (buf_getv_memory_controller_address),
.memory_controller_write_enable (buf_getv_memory_controller_write_enable),
.memory_controller_enable (buf_getv_memory_controller_enable),
.memory_controller_in (buf_getv_memory_controller_in),
.memory_controller_size (buf_getv_memory_controller_size),
.memory_controller_waitrequest (buf_getv_memory_controller_waitrequest),
.memory_controller_out (buf_getv_memory_controller_out),
.arg_n (buf_getv_arg_n)
);
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 8'd0;
if (^reset !== 1'bX && ^(8'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_3 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB0_4;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_4;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_4 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB0_5;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_5;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_6;
if (^reset !== 1'bX && ^(LEGUP_function_call_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_6;
if (^reset !== 1'bX && ^(LEGUP_function_call_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_6 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_7;
if (^reset !== 1'bX && ^(LEGUP_function_call_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_6 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_6;
if (^reset !== 1'bX && ^(LEGUP_function_call_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_7;
if (^reset !== 1'bX && ^(LEGUP_function_call_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_7 & memory_controller_waitrequest == 1'd0 & decode_block_0_11 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB5_21;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB5_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_7 & memory_controller_waitrequest == 1'd0 & decode_block_0_11 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB1_8;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB1_8;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_8 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_9;
if (^reset !== 1'bX && ^(LEGUP_function_call_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_9;
if (^reset !== 1'bX && ^(LEGUP_function_call_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_9 & memory_controller_waitrequest == 1'd0 & buf_getv_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_10;
if (^reset !== 1'bX && ^(LEGUP_function_call_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_9 & memory_controller_waitrequest == 1'd0 & buf_getv_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_9;
if (^reset !== 1'bX && ^(LEGUP_function_call_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_10;
if (^reset !== 1'bX && ^(LEGUP_function_call_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_10 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB1_11;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB1_11;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB1_12;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB1_12;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_12 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB1_13;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB1_13;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_13 & memory_controller_waitrequest == 1'd0 & decode_block_12_18 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB2_14;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_13 & memory_controller_waitrequest == 1'd0 & decode_block_12_18 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB3_17;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB2_14;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB2_15;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB2_15;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_15 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB2_16;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB2_16;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_16 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB3_17;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB3_17;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_17 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB3_18;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB3_18;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_18 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB3_19;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB3_19;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB5_21;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB5_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB4_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB4_20;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB4_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB4_20 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB6_22;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB6_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB5_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB5_21;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB5_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB5_21 & memory_controller_waitrequest == 1'd0 & decode_block__lr_ph_i_32 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB5_21;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB5_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB5_21 & memory_controller_waitrequest == 1'd0 & decode_block__lr_ph_i_32 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB4_20;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB4_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB6_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB6_22;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB6_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB6_22 & memory_controller_waitrequest == 1'd0 & decode_block__backedge_i_33 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB6_22 & memory_controller_waitrequest == 1'd0 & decode_block__backedge_i_33 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_23 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_24 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB7_25;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB7_25;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_25 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_26;
if (^reset !== 1'bX && ^(LEGUP_function_call_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_26;
if (^reset !== 1'bX && ^(LEGUP_function_call_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_27;
if (^reset !== 1'bX && ^(LEGUP_function_call_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_26;
if (^reset !== 1'bX && ^(LEGUP_function_call_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_27;
if (^reset !== 1'bX && ^(LEGUP_function_call_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_27 & memory_controller_waitrequest == 1'd0 & decode_block_34_40 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB12_40;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB12_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_27 & memory_controller_waitrequest == 1'd0 & decode_block_34_40 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB8_28;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB8_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB8_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB8_28;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB8_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB8_28 & memory_controller_waitrequest == 1'd0 & decode_block_41_43 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB8_28 & memory_controller_waitrequest == 1'd0 & decode_block_41_43 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB9_29;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB9_29;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_29 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_30;
if (^reset !== 1'bX && ^(LEGUP_function_call_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_30;
if (^reset !== 1'bX && ^(LEGUP_function_call_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_30 & memory_controller_waitrequest == 1'd0 & buf_getv_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_31;
if (^reset !== 1'bX && ^(LEGUP_function_call_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_30 & memory_controller_waitrequest == 1'd0 & buf_getv_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_30;
if (^reset !== 1'bX && ^(LEGUP_function_call_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_31;
if (^reset !== 1'bX && ^(LEGUP_function_call_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_32 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB9_33;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB9_33;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB9_34;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB9_34;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_34 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB9_35;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB9_35;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_35 & memory_controller_waitrequest == 1'd0 & decode_block_44_51 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_35 & memory_controller_waitrequest == 1'd0 & decode_block_44_51 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_36 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB10_37;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB10_37;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB10_38;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_38 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB10_38;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_38 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB11_39 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB11_39 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB6_22;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB6_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB12_40 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB12_40;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB12_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB12_40 & memory_controller_waitrequest == 1'd0 & decode_block_59_60 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB13_41;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB13_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB12_40 & memory_controller_waitrequest == 1'd0 & decode_block_59_60 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB13_41 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB13_41;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB13_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB13_41 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB6_22;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB6_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_42 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_42 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_43 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_43 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_44 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_44 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_45 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_45 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_46;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_46 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_46;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_46 & memory_controller_waitrequest == 1'd0 & decode_block_DecodeHuffMCU_exit_exitcond10_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB15_47;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_46 & memory_controller_waitrequest == 1'd0 & decode_block_DecodeHuffMCU_exit_exitcond10_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_47 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB15_47;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_47 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_48 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_48 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB15_49;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_49 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB15_49;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_49 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB16_50;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_50 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB16_50;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_50 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB16_51;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_51 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB16_51;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_51 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB16_52;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_52 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB16_52;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_52 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_53 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_53 & memory_controller_waitrequest == 1'd0 & decode_block_69_exitcond8_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_54;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_53 & memory_controller_waitrequest == 1'd0 & decode_block_69_exitcond8_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB16_50;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_54 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_54;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_54 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_55;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_55 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_55;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_55 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_56;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_56 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_56;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_56 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_57;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_57 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_57;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_57 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_58;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_58 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_58;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_58 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_59;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_59) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_59 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_59;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_59) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_59 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_60;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_60 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_60;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_60 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_61;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_61 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_61;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_61 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_62;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_62) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_62 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_62;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_62) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_62 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_63;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_63) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_63 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_63;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_63) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_63 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_64;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_64) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_64 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_64;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_64) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_64 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_65;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_65 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_65;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_65 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_66;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_66) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_66 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_66;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_66) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_66 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_67;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_67) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_67 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_67;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_67) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_67 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_68;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_68) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_68 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_68;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_68) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_68 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_69;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_69 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_69;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_69 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_70;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_70) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_70 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_70;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_70) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_70 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_71;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_71 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_71;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_71 & memory_controller_waitrequest == 1'd0 & decode_block_IQuantize_exit_exitcond43_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_72;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_71 & memory_controller_waitrequest == 1'd0 & decode_block_IQuantize_exit_exitcond43_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_54;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_72 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_72;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_72 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_73;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_73 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_73;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_73 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_74;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_74) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_74 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_74;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_74) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_74 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_75;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_75) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_75 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_75;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_75) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_75 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_76;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_76) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_76 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_76;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_76) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_76 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_77;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_77) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_77 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_77;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_77) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_77 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_78;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_78) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_78 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_78;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_78) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_78 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_79;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_79) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_79 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_79;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_79) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_79 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_80;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_80) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_80 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_80;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_80) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_80 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_81;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_81) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_81 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_81;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_81) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_81 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_82;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_82 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_82;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_82 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_83;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_83) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_83 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_83;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_83) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_83 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_84;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_84) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_84 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_84;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_84) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_84 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_85;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_85) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_85 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_85;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_85) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_85 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_86;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_86) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_86 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_86;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_86) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_86 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_87;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_87) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_87 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_87;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_87) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_87 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_88;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_88) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_88 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_88;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_88) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_88 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_89;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_89) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_89 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_89;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_89) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_89 & memory_controller_waitrequest == 1'd0 & decode_block__preheader25_i_exitcond28_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_90;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_89 & memory_controller_waitrequest == 1'd0 & decode_block__preheader25_i_exitcond28_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_72;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_90 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_90;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_90 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_91;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_91) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_91 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_91;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_91) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_91 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_92;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_92) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_92 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_92;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_92) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_92 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_93;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_93) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_93 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_93;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_93) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_93 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_94;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_94) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_94 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_94;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_94) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_94 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_95;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_95) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_95 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_95;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_95) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_95 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_96;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_96) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_96 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_96;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_96) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_96 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_97;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_97) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_97 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_97;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_97) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_97 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_98;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_98 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_98;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_98 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_99;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_99 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_99;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_99 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_100;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_100 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_100;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_100 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_101;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_101 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_101;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_101 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_102;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_102) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_102 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_102;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_102) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_102 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_103;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_103 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_103;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_103 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_104;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_104 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_104;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_104 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_105;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_105 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_105;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_105 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_106;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_106 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_106;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_106 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_107;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_107) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_107 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_107;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_107) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_107 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_108;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_108) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_108 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_108;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_108) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_108 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_109;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_109 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_109;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_109 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_110;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_110) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_110 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_110;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_110) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_110 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_111;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_111) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_111 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_111;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_111) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_111 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_112;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_112 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_112;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_112 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_113;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_113) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_113 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_113;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_113) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_113 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_114;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_114 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_114;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_114 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_115;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_115) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_115 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_115;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_115) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_115 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_116;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_116 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_116;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_116 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_117;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_117) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_117 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_117;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_117) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_117 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_118;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_118) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_118 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_118;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_118) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_118 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_119;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_119) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_119 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_119;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_119) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_119 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_120;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_120) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_120 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_120;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_120) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_120 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_121;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_121) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_121 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_121;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_121) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_121 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_122;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_122 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_122;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_122 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_123;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_123) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_123 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_123;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_123) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_123 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_124;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_124) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_124 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_124;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_124) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_124 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_125;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_125) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_125 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_125;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_125) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_125 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_126;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_126) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_126 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_126;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_126) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_126 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_127;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_127) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_127 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_127;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_127) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_127 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_128;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_128) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_128 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_128;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_128) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_128 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_129;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_129 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_129;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_129 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_130;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_130 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_130;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_130 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_131;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_131 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_131;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_131 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_132;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_132 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_132;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_132 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_133;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_133 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_133;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_133 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_134;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_134 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_134;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_134 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_135;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_135 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_135;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_135 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_136;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_136 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_136;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_136 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_137;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_137) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_137 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_137;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_137) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_137 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_138;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_138) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_138 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_138;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_138) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_138 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_139;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_139 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_139;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_139 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_140;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_140 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_140;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_140 & memory_controller_waitrequest == 1'd0 & decode_block__preheader_i8_exitcond_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB20_141;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_141) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_140 & memory_controller_waitrequest == 1'd0 & decode_block__preheader_i8_exitcond_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_90;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_141 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB20_141;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_141) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_141 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB20_142;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_142) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_142 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB20_142;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_142) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_142 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB20_143;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_143) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_143 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB20_143;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_143) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_143 & memory_controller_waitrequest == 1'd0 & decode_block_ChenIDct_exit_exitcond7_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB21_144;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_143 & memory_controller_waitrequest == 1'd0 & decode_block_ChenIDct_exit_exitcond7_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB20_141;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_141) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_144 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB21_144;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_144 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB21_145;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_145) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_145 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB21_145;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_145) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_145 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB21_146;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_146) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_146 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB21_146;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_146) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_146 & memory_controller_waitrequest == 1'd0 & decode_block_PostshiftIDctMatrix_exit_207 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB22_147;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB22_147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_146 & memory_controller_waitrequest == 1'd0 & decode_block_PostshiftIDctMatrix_exit_207 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB23_148;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB23_148) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB22_147 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB22_147;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB22_147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB22_147 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB25_150;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB25_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB23_148 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB23_148;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB23_148) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB23_148 & memory_controller_waitrequest == 1'd0 & decode_block_209_210 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB24_149;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB24_149) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB23_148 & memory_controller_waitrequest == 1'd0 & decode_block_209_210 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB25_150;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB25_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB24_149 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB24_149;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB24_149) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB24_149 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB25_150;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB25_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB25_150 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB25_150;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB25_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB25_150 & memory_controller_waitrequest == 1'd0 & decode_block_212_exitcond == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB26_151;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB26_151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB25_150 & memory_controller_waitrequest == 1'd0 & decode_block_212_exitcond == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB21_144;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB26_151 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB26_151;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB26_151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB26_151 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %1 = getelementptr inbounds [3 x i8]* @p_jinfo_comps_info_dc_tbl_no, i32 0, i32 %comp_no*/
begin
decode_block_0_1 = `TAG_g_p_jinfo_comps_info_dc_tbl_no_a + 1 * arg_comp_no;
end
end
always @(*) begin
/* decode_block: %0*/
/* %2 = load i8* %1, align 1, !tbaa !0*/
begin
decode_block_0_2 = memory_controller_out[7:0];
end
end
always @(*) begin
/* decode_block: %0*/
/* %3 = sext i8 %2 to i32*/
begin
decode_block_0_3 = $signed(decode_block_0_2);
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %3 = sext i8 %2 to i32*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
decode_block_0_3_reg <= decode_block_0_3;
if (^reset !== 1'bX && ^(decode_block_0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_3_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %4 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_dc_xhuff_tbl_huffval, i32 0, i32 %3, i32 0*/
begin
decode_block_0_4 = `TAG_g_p_jinfo_dc_xhuff_tbl_huffval_a + 1028 * decode_block_0_3;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %4 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_dc_xhuff_tbl_huffval, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
decode_block_0_4_reg <= decode_block_0_4;
if (^reset !== 1'bX && ^(decode_block_0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_4_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %5 = getelementptr inbounds [2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 %3*/
begin
decode_block_0_5 = `TAG_g_p_jinfo_dc_dhuff_tbl_ml_a + 4 * decode_block_0_3;
end
end
always @(*) begin
/* decode_block: %0*/
/* %6 = load i32* %5, align 4, !tbaa !2*/
begin
decode_block_0_6 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %0*/
/* %7 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 %3, i32 0*/
begin
decode_block_0_7 = `TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a + 144 * decode_block_0_3;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %7 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
decode_block_0_7_reg <= decode_block_0_7;
if (^reset !== 1'bX && ^(decode_block_0_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_7_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %8 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 %3, i32 0*/
begin
decode_block_0_8 = `TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a + 144 * decode_block_0_3;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %8 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
decode_block_0_8_reg <= decode_block_0_8;
if (^reset !== 1'bX && ^(decode_block_0_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_8_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %9 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 %3, i32 0*/
begin
decode_block_0_9 = `TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a + 144 * decode_block_0_3;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %9 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
decode_block_0_9_reg <= decode_block_0_9;
if (^reset !== 1'bX && ^(decode_block_0_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_9_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
begin
decode_block_0_10 = DecodeHuffman_return_val;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
decode_block_0_10_reg <= decode_block_0_10;
if (^reset !== 1'bX && ^(decode_block_0_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_10_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %11 = icmp eq i32 %10, 0*/
begin
decode_block_0_11 = decode_block_0_10_reg == 32'd0;
end
end
always @(*) begin
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
begin
decode_block_12_13 = buf_getv_return_val;
end
end
always @(posedge clk) begin
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
decode_block_12_13_reg <= decode_block_12_13;
if (^reset !== 1'bX && ^(decode_block_12_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_12_13_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %12*/
/* %14 = add nsw i32 %10, -1*/
begin
decode_block_12_14 = decode_block_0_10_reg + -32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %12*/
/* %14 = add nsw i32 %10, -1*/
if (cur_state == LEGUP_function_call_10)
begin
decode_block_12_14_reg <= decode_block_12_14;
if (^reset !== 1'bX && ^(decode_block_12_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_12_14_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %12*/
/* %15 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %14*/
begin
decode_block_12_15 = `TAG_g_bit_set_mask_a + 4 * decode_block_12_14;
end
end
always @(posedge clk) begin
/* decode_block: %12*/
/* %15 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %14*/
if (cur_state == LEGUP_function_call_10)
begin
decode_block_12_15_reg <= decode_block_12_15;
if (^reset !== 1'bX && ^(decode_block_12_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_12_15_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %12*/
/* %16 = load i32* %15, align 4, !tbaa !2*/
begin
decode_block_12_16 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %12*/
/* %17 = and i32 %16, %13*/
begin
decode_block_12_17 = decode_block_12_16 & decode_block_12_13_reg;
end
end
always @(*) begin
/* decode_block: %12*/
/* %18 = icmp eq i32 %17, 0*/
begin
decode_block_12_18 = decode_block_12_17 == 32'd0;
end
end
always @(*) begin
/* decode_block: %19*/
/* %20 = getelementptr inbounds [20 x i32]* @extend_mask, i32 0, i32 %14*/
begin
decode_block_19_20 = `TAG_g_extend_mask_a + 4 * decode_block_12_14_reg;
end
end
always @(*) begin
/* decode_block: %19*/
/* %21 = load i32* %20, align 4, !tbaa !2*/
begin
decode_block_19_21 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %19*/
/* %22 = or i32 %21, %13*/
begin
decode_block_19_22 = decode_block_19_21 | decode_block_12_13_reg;
end
end
always @(*) begin
/* decode_block: %19*/
/* %23 = add nsw i32 %22, 1*/
begin
decode_block_19_23 = decode_block_19_22 + 32'd1;
end
end
always @(*) begin
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
decode_block_24_diff_0_i = decode_block_24_diff_0_i_phi_temp;
end
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
else /* if (cur_state == LEGUP_F_decode_block_BB3_17) */
begin
decode_block_24_diff_0_i = decode_block_24_diff_0_i_phi_temp;
end
end
always @(posedge clk) begin
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
decode_block_24_diff_0_i_reg <= decode_block_24_diff_0_i;
if (^reset !== 1'bX && ^(decode_block_24_diff_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_24_diff_0_i_reg"); $finish; end
end
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
decode_block_24_diff_0_i_reg <= decode_block_24_diff_0_i;
if (^reset !== 1'bX && ^(decode_block_24_diff_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_24_diff_0_i_reg"); $finish; end
end
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
decode_block_24_diff_0_i_reg <= decode_block_24_diff_0_i;
if (^reset !== 1'bX && ^(decode_block_24_diff_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_24_diff_0_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %24*/
/* %25 = load i32* %HuffBuff, align 4, !tbaa !2*/
begin
decode_block_24_25 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %24*/
/* %26 = add nsw i32 %25, %diff.0.i*/
begin
decode_block_24_26 = decode_block_24_25 + decode_block_24_diff_0_i_reg;
end
end
always @(*) begin
/* decode_block: %.preheader.i*/
/* %27 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_ac_xhuff_tbl_huffval, i32 0, i32 %3, i32 0*/
begin
decode_block__preheader_i_27 = `TAG_g_p_jinfo_ac_xhuff_tbl_huffval_a + 1028 * decode_block_0_3_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i*/
/* %27 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_ac_xhuff_tbl_huffval, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB4_20)
begin
decode_block__preheader_i_27_reg <= decode_block__preheader_i_27;
if (^reset !== 1'bX && ^(decode_block__preheader_i_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i_27_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i*/
/* %28 = getelementptr inbounds [2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 %3*/
begin
decode_block__preheader_i_28 = `TAG_g_p_jinfo_ac_dhuff_tbl_ml_a + 4 * decode_block_0_3_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i*/
/* %28 = getelementptr inbounds [2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 %3*/
if (cur_state == LEGUP_F_decode_block_BB4_20)
begin
decode_block__preheader_i_28_reg <= decode_block__preheader_i_28;
if (^reset !== 1'bX && ^(decode_block__preheader_i_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i_28_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i*/
/* %29 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 %3, i32 0*/
begin
decode_block__preheader_i_29 = `TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a + 144 * decode_block_0_3_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i*/
/* %29 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB4_20)
begin
decode_block__preheader_i_29_reg <= decode_block__preheader_i_29;
if (^reset !== 1'bX && ^(decode_block__preheader_i_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i_29_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i*/
/* %30 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 %3, i32 0*/
begin
decode_block__preheader_i_30 = `TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a + 144 * decode_block_0_3_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i*/
/* %30 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB4_20)
begin
decode_block__preheader_i_30_reg <= decode_block__preheader_i_30;
if (^reset !== 1'bX && ^(decode_block__preheader_i_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i_30_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i*/
/* %31 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 %3, i32 0*/
begin
decode_block__preheader_i_31 = `TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a + 144 * decode_block_0_3_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i*/
/* %31 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB4_20)
begin
decode_block__preheader_i_31_reg <= decode_block__preheader_i_31;
if (^reset !== 1'bX && ^(decode_block__preheader_i_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i_31_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.lr.ph.i*/
/* %indvar.i2 = phi i32 [ %tmp4.i, %.lr.ph.i ], [ 0, %0 ], [ 0, %24 ]*/
begin
decode_block__lr_ph_i_indvar_i2 = decode_block__lr_ph_i_indvar_i2_phi_temp;
end
end
always @(*) begin
/* decode_block: %.lr.ph.i*/
/* %tmp.i4 = add i32 %indvar.i2, 2*/
begin
decode_block__lr_ph_i_tmp_i4 = decode_block__lr_ph_i_indvar_i2 + 32'd2;
end
end
always @(*) begin
/* decode_block: %.lr.ph.i*/
/* %tmp4.i = add i32 %indvar.i2, 1*/
begin
decode_block__lr_ph_i_tmp4_i = decode_block__lr_ph_i_indvar_i2 + 32'd1;
end
end
always @(*) begin
/* decode_block: %.lr.ph.i*/
/* %mptr.03.i = getelementptr i32* %HuffBuff, i32 %tmp4.i*/
begin
decode_block__lr_ph_i_mptr_03_i = arg_HuffBuff + 4 * decode_block__lr_ph_i_tmp4_i;
end
end
always @(*) begin
/* decode_block: %.lr.ph.i*/
/* %32 = icmp slt i32 %tmp.i4, 64*/
begin
decode_block__lr_ph_i_32 = $signed(decode_block__lr_ph_i_tmp_i4) < $signed(32'd64);
end
end
always @(*) begin
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i = decode_block__backedge_i_k_0_i_phi_temp;
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
else if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i = decode_block__backedge_i_k_0_i_phi_temp;
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
else /* if (cur_state == LEGUP_F_decode_block_BB6_22) */
begin
decode_block__backedge_i_k_0_i = decode_block__backedge_i_k_0_i_phi_temp;
end
end
always @(posedge clk) begin
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i_reg <= decode_block__backedge_i_k_0_i;
if (^reset !== 1'bX && ^(decode_block__backedge_i_k_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_reg"); $finish; end
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i_reg <= decode_block__backedge_i_k_0_i;
if (^reset !== 1'bX && ^(decode_block__backedge_i_k_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_reg"); $finish; end
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i_reg <= decode_block__backedge_i_k_0_i;
if (^reset !== 1'bX && ^(decode_block__backedge_i_k_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_reg"); $finish; end
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i_reg <= decode_block__backedge_i_k_0_i;
if (^reset !== 1'bX && ^(decode_block__backedge_i_k_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.backedge.i*/
/* %33 = icmp slt i32 %k.0.i, 64*/
begin
decode_block__backedge_i_33 = $signed(decode_block__backedge_i_k_0_i) < $signed(32'd64);
end
end
always @(*) begin
/* decode_block: %34*/
/* %35 = load i32* %28, align 4, !tbaa !2*/
begin
decode_block_34_35 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
begin
decode_block_34_36 = DecodeHuffman_return_val;
end
end
always @(posedge clk) begin
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
decode_block_34_36_reg <= decode_block_34_36;
if (^reset !== 1'bX && ^(decode_block_34_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_34_36_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %34*/
/* %37 = and i32 %36, 15*/
begin
decode_block_34_37 = decode_block_34_36_reg & 32'd15;
end
end
always @(posedge clk) begin
/* decode_block: %34*/
/* %37 = and i32 %36, 15*/
if (cur_state == LEGUP_function_call_27)
begin
decode_block_34_37_reg <= decode_block_34_37;
if (^reset !== 1'bX && ^(decode_block_34_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_34_37_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %34*/
/* %38 = lshr i32 %36, 4*/
begin
decode_block_34_38 = decode_block_34_36_reg >>> 32'd4 % 32;
end
end
always @(*) begin
/* decode_block: %34*/
/* %39 = and i32 %38, 15*/
begin
decode_block_34_39 = decode_block_34_38 & 32'd15;
end
end
always @(posedge clk) begin
/* decode_block: %34*/
/* %39 = and i32 %38, 15*/
if (cur_state == LEGUP_function_call_27)
begin
decode_block_34_39_reg <= decode_block_34_39;
if (^reset !== 1'bX && ^(decode_block_34_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_34_39_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %34*/
/* %40 = icmp eq i32 %37, 0*/
begin
decode_block_34_40 = decode_block_34_37 == 32'd0;
end
end
always @(*) begin
/* decode_block: %41*/
/* %42 = add nsw i32 %39, %k.0.i*/
begin
decode_block_41_42 = decode_block_34_39_reg + decode_block__backedge_i_k_0_i_reg;
end
end
always @(posedge clk) begin
/* decode_block: %41*/
/* %42 = add nsw i32 %39, %k.0.i*/
if (cur_state == LEGUP_F_decode_block_BB8_28)
begin
decode_block_41_42_reg <= decode_block_41_42;
if (^reset !== 1'bX && ^(decode_block_41_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_41_42_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %41*/
/* %43 = icmp sgt i32 %42, 63*/
begin
decode_block_41_43 = $signed(decode_block_41_42) > $signed(32'd63);
end
end
always @(*) begin
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
begin
decode_block_44_45 = buf_getv_return_val;
end
end
always @(posedge clk) begin
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
decode_block_44_45_reg <= decode_block_44_45;
if (^reset !== 1'bX && ^(decode_block_44_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_44_45_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %44*/
/* %46 = getelementptr inbounds i32* %HuffBuff, i32 %42*/
begin
decode_block_44_46 = arg_HuffBuff + 4 * decode_block_41_42_reg;
end
end
always @(posedge clk) begin
/* decode_block: %44*/
/* %46 = getelementptr inbounds i32* %HuffBuff, i32 %42*/
if (cur_state == LEGUP_function_call_31)
begin
decode_block_44_46_reg <= decode_block_44_46;
if (^reset !== 1'bX && ^(decode_block_44_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_44_46_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %44*/
/* %47 = add nsw i32 %37, -1*/
begin
decode_block_44_47 = decode_block_34_37_reg + -32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %44*/
/* %47 = add nsw i32 %37, -1*/
if (cur_state == LEGUP_function_call_31)
begin
decode_block_44_47_reg <= decode_block_44_47;
if (^reset !== 1'bX && ^(decode_block_44_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_44_47_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %44*/
/* %48 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %47*/
begin
decode_block_44_48 = `TAG_g_bit_set_mask_a + 4 * decode_block_44_47;
end
end
always @(posedge clk) begin
/* decode_block: %44*/
/* %48 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %47*/
if (cur_state == LEGUP_function_call_31)
begin
decode_block_44_48_reg <= decode_block_44_48;
if (^reset !== 1'bX && ^(decode_block_44_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_44_48_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %44*/
/* %49 = load i32* %48, align 4, !tbaa !2*/
begin
decode_block_44_49 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %44*/
/* %50 = and i32 %49, %45*/
begin
decode_block_44_50 = decode_block_44_49 & decode_block_44_45_reg;
end
end
always @(*) begin
/* decode_block: %44*/
/* %51 = icmp eq i32 %50, 0*/
begin
decode_block_44_51 = decode_block_44_50 == 32'd0;
end
end
always @(*) begin
/* decode_block: %52*/
/* %53 = getelementptr inbounds [20 x i32]* @extend_mask, i32 0, i32 %47*/
begin
decode_block_52_53 = `TAG_g_extend_mask_a + 4 * decode_block_44_47_reg;
end
end
always @(*) begin
/* decode_block: %52*/
/* %54 = load i32* %53, align 4, !tbaa !2*/
begin
decode_block_52_54 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %52*/
/* %55 = or i32 %54, %45*/
begin
decode_block_52_55 = decode_block_52_54 | decode_block_44_45_reg;
end
end
always @(*) begin
/* decode_block: %52*/
/* %56 = add nsw i32 %55, 1*/
begin
decode_block_52_56 = decode_block_52_55 + 32'd1;
end
end
always @(*) begin
/* decode_block: %57*/
/* %58 = add nsw i32 %42, 1*/
begin
decode_block_57_58 = decode_block_41_42_reg + 32'd1;
end
end
always @(*) begin
/* decode_block: %59*/
/* %60 = icmp eq i32 %39, 15*/
begin
decode_block_59_60 = decode_block_34_39_reg == 32'd15;
end
end
always @(*) begin
/* decode_block: %61*/
/* %62 = add nsw i32 %k.0.i, 16*/
begin
decode_block_61_62 = decode_block__backedge_i_k_0_i_reg + 32'd16;
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %i.02.i = phi i32 [ %66, %DecodeHuffMCU.exit ], [ 0, %.backedge.i ], [ 0, %41 ], [ 0, %59 ]*/
begin
decode_block_DecodeHuffMCU_exit_i_02_i = decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp;
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %.01.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %i.02.i*/
begin
decode_block_DecodeHuffMCU_exit__01_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_DecodeHuffMCU_exit_i_02_i;
end
end
always @(posedge clk) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %.01.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %i.02.i*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
decode_block_DecodeHuffMCU_exit__01_i_reg <= decode_block_DecodeHuffMCU_exit__01_i;
if (^reset !== 1'bX && ^(decode_block_DecodeHuffMCU_exit__01_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit__01_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %scevgep.i = getelementptr [64 x i32]* @zigzag_index, i32 0, i32 %i.02.i*/
begin
decode_block_DecodeHuffMCU_exit_scevgep_i = `TAG_g_zigzag_index_a + 4 * decode_block_DecodeHuffMCU_exit_i_02_i;
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %63 = load i32* %scevgep.i, align 4, !tbaa !2*/
begin
decode_block_DecodeHuffMCU_exit_63 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %64 = getelementptr inbounds i32* %HuffBuff, i32 %63*/
begin
decode_block_DecodeHuffMCU_exit_64 = arg_HuffBuff + 4 * decode_block_DecodeHuffMCU_exit_63;
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %65 = load i32* %64, align 4, !tbaa !2*/
begin
decode_block_DecodeHuffMCU_exit_65 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %66 = add nsw i32 %i.02.i, 1*/
begin
decode_block_DecodeHuffMCU_exit_66 = decode_block_DecodeHuffMCU_exit_i_02_i + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %66 = add nsw i32 %i.02.i, 1*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
decode_block_DecodeHuffMCU_exit_66_reg <= decode_block_DecodeHuffMCU_exit_66;
if (^reset !== 1'bX && ^(decode_block_DecodeHuffMCU_exit_66) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_66_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %exitcond10 = icmp eq i32 %66, 64*/
begin
decode_block_DecodeHuffMCU_exit_exitcond10 = decode_block_DecodeHuffMCU_exit_66 == 32'd64;
end
end
always @(posedge clk) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %exitcond10 = icmp eq i32 %66, 64*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
decode_block_DecodeHuffMCU_exit_exitcond10_reg <= decode_block_DecodeHuffMCU_exit_exitcond10;
if (^reset !== 1'bX && ^(decode_block_DecodeHuffMCU_exit_exitcond10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_exitcond10_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IZigzagMatrix.exit*/
/* %67 = getelementptr inbounds [3 x i8]* @p_jinfo_comps_info_quant_tbl_no, i32 0, i32 %comp_no*/
begin
decode_block_IZigzagMatrix_exit_67 = `TAG_g_p_jinfo_comps_info_quant_tbl_no_a + 1 * arg_comp_no;
end
end
always @(*) begin
/* decode_block: %IZigzagMatrix.exit*/
/* %68 = load i8* %67, align 1, !tbaa !0*/
begin
decode_block_IZigzagMatrix_exit_68 = memory_controller_out[7:0];
end
end
always @(*) begin
/* decode_block: %IZigzagMatrix.exit*/
/* %tmp = sext i8 %68 to i32*/
begin
decode_block_IZigzagMatrix_exit_tmp = $signed(decode_block_IZigzagMatrix_exit_68);
end
end
always @(*) begin
/* decode_block: %IZigzagMatrix.exit*/
/* %tmp9 = add i32 %tmp, 1*/
begin
decode_block_IZigzagMatrix_exit_tmp9 = decode_block_IZigzagMatrix_exit_tmp + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %IZigzagMatrix.exit*/
/* %tmp9 = add i32 %tmp, 1*/
if (cur_state == LEGUP_F_decode_block_BB15_49)
begin
decode_block_IZigzagMatrix_exit_tmp9_reg <= decode_block_IZigzagMatrix_exit_tmp9;
if (^reset !== 1'bX && ^(decode_block_IZigzagMatrix_exit_tmp9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IZigzagMatrix_exit_tmp9_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %69*/
/* %indvar.i4 = phi i32 [ 0, %IZigzagMatrix.exit ], [ %tmp.i5, %69 ]*/
begin
decode_block_69_indvar_i4 = decode_block_69_indvar_i4_phi_temp;
end
end
always @(*) begin
/* decode_block: %69*/
/* %.01.i6 = getelementptr [4 x [64 x i32]]* @p_jinfo_quant_tbl_quantval, i32 0, i32 %tmp9, i32 %indvar.i4*/
begin
decode_block_69__01_i6 = `TAG_g_p_jinfo_quant_tbl_quantval_a + 256 * decode_block_IZigzagMatrix_exit_tmp9_reg + 4 * decode_block_69_indvar_i4;
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %.01.i6 = getelementptr [4 x [64 x i32]]* @p_jinfo_quant_tbl_quantval, i32 0, i32 %tmp9, i32 %indvar.i4*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
decode_block_69__01_i6_reg <= decode_block_69__01_i6;
if (^reset !== 1'bX && ^(decode_block_69__01_i6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69__01_i6_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %69*/
/* %mptr.02.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %indvar.i4*/
begin
decode_block_69_mptr_02_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_69_indvar_i4;
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %mptr.02.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %indvar.i4*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
decode_block_69_mptr_02_i_reg <= decode_block_69_mptr_02_i;
if (^reset !== 1'bX && ^(decode_block_69_mptr_02_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_mptr_02_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %69*/
/* %tmp.i5 = add i32 %indvar.i4, 1*/
begin
decode_block_69_tmp_i5 = decode_block_69_indvar_i4 + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %tmp.i5 = add i32 %indvar.i4, 1*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
decode_block_69_tmp_i5_reg <= decode_block_69_tmp_i5;
if (^reset !== 1'bX && ^(decode_block_69_tmp_i5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_tmp_i5_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
begin
decode_block_69_70 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_52)
begin
decode_block_69_70_reg <= decode_block_69_70;
if (^reset !== 1'bX && ^(decode_block_69_70) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_70_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %69*/
/* %71 = load i32* %.01.i6, align 4, !tbaa !2*/
begin
decode_block_69_71 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %69*/
/* %72 = mul nsw i32 %71, %70*/
begin
decode_block_69_72 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %69*/
/* %exitcond8 = icmp eq i32 %tmp.i5, 64*/
begin
decode_block_69_exitcond8 = decode_block_69_tmp_i5 == 32'd64;
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %exitcond8 = icmp eq i32 %tmp.i5, 64*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
decode_block_69_exitcond8_reg <= decode_block_69_exitcond8;
if (^reset !== 1'bX && ^(decode_block_69_exitcond8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_exitcond8_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %i.027.i = phi i32 [ %135, %IQuantize.exit ], [ 0, %69 ]*/
begin
decode_block_IQuantize_exit_i_027_i = decode_block_IQuantize_exit_i_027_i_phi_temp;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep44.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %i.027.i*/
begin
decode_block_IQuantize_exit_scevgep44_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_i_027_i;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep45.i = getelementptr i32* %out_buf, i32 %i.027.i*/
begin
decode_block_IQuantize_exit_scevgep45_i = arg_out_buf + 4 * decode_block_IQuantize_exit_i_027_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep45.i = getelementptr i32* %out_buf, i32 %i.027.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep45_i_reg <= decode_block_IQuantize_exit_scevgep45_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep45_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep45_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp46.i = add i32 %i.027.i, 8*/
begin
decode_block_IQuantize_exit_tmp46_i = decode_block_IQuantize_exit_i_027_i + 32'd8;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep47.i = getelementptr i32* %out_buf, i32 %tmp46.i*/
begin
decode_block_IQuantize_exit_scevgep47_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp46_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep47.i = getelementptr i32* %out_buf, i32 %tmp46.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep47_i_reg <= decode_block_IQuantize_exit_scevgep47_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep47_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep47_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep48.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp46.i*/
begin
decode_block_IQuantize_exit_scevgep48_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp46_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep48.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp46.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep48_i_reg <= decode_block_IQuantize_exit_scevgep48_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep48_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep48_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp49.i = add i32 %i.027.i, 16*/
begin
decode_block_IQuantize_exit_tmp49_i = decode_block_IQuantize_exit_i_027_i + 32'd16;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep50.i = getelementptr i32* %out_buf, i32 %tmp49.i*/
begin
decode_block_IQuantize_exit_scevgep50_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp49_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep50.i = getelementptr i32* %out_buf, i32 %tmp49.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep50_i_reg <= decode_block_IQuantize_exit_scevgep50_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep50_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep50_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep51.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp49.i*/
begin
decode_block_IQuantize_exit_scevgep51_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp49_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep51.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp49.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep51_i_reg <= decode_block_IQuantize_exit_scevgep51_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep51_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep51_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp52.i = add i32 %i.027.i, 24*/
begin
decode_block_IQuantize_exit_tmp52_i = decode_block_IQuantize_exit_i_027_i + 32'd24;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep53.i = getelementptr i32* %out_buf, i32 %tmp52.i*/
begin
decode_block_IQuantize_exit_scevgep53_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp52_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep53.i = getelementptr i32* %out_buf, i32 %tmp52.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep53_i_reg <= decode_block_IQuantize_exit_scevgep53_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep53_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep53_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep54.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp52.i*/
begin
decode_block_IQuantize_exit_scevgep54_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp52_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep54.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp52.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep54_i_reg <= decode_block_IQuantize_exit_scevgep54_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep54_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep54_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp55.i = add i32 %i.027.i, 32*/
begin
decode_block_IQuantize_exit_tmp55_i = decode_block_IQuantize_exit_i_027_i + 32'd32;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep56.i = getelementptr i32* %out_buf, i32 %tmp55.i*/
begin
decode_block_IQuantize_exit_scevgep56_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp55_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep56.i = getelementptr i32* %out_buf, i32 %tmp55.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep56_i_reg <= decode_block_IQuantize_exit_scevgep56_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep56_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep56_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep57.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp55.i*/
begin
decode_block_IQuantize_exit_scevgep57_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp55_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep57.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp55.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep57_i_reg <= decode_block_IQuantize_exit_scevgep57_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep57_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep57_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp58.i = add i32 %i.027.i, 40*/
begin
decode_block_IQuantize_exit_tmp58_i = decode_block_IQuantize_exit_i_027_i + 32'd40;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep59.i = getelementptr i32* %out_buf, i32 %tmp58.i*/
begin
decode_block_IQuantize_exit_scevgep59_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp58_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep59.i = getelementptr i32* %out_buf, i32 %tmp58.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep59_i_reg <= decode_block_IQuantize_exit_scevgep59_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep59_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep59_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep60.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp58.i*/
begin
decode_block_IQuantize_exit_scevgep60_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp58_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep60.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp58.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep60_i_reg <= decode_block_IQuantize_exit_scevgep60_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep60_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep60_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp61.i = add i32 %i.027.i, 48*/
begin
decode_block_IQuantize_exit_tmp61_i = decode_block_IQuantize_exit_i_027_i + 32'd48;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep62.i = getelementptr i32* %out_buf, i32 %tmp61.i*/
begin
decode_block_IQuantize_exit_scevgep62_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp61_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep62.i = getelementptr i32* %out_buf, i32 %tmp61.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep62_i_reg <= decode_block_IQuantize_exit_scevgep62_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep62_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep62_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep63.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp61.i*/
begin
decode_block_IQuantize_exit_scevgep63_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp61_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep63.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp61.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep63_i_reg <= decode_block_IQuantize_exit_scevgep63_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep63_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep63_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp64.i = add i32 %i.027.i, 56*/
begin
decode_block_IQuantize_exit_tmp64_i = decode_block_IQuantize_exit_i_027_i + 32'd56;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep65.i = getelementptr i32* %out_buf, i32 %tmp64.i*/
begin
decode_block_IQuantize_exit_scevgep65_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp64_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep65.i = getelementptr i32* %out_buf, i32 %tmp64.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep65_i_reg <= decode_block_IQuantize_exit_scevgep65_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep65_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep65_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep66.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp64.i*/
begin
decode_block_IQuantize_exit_scevgep66_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp64_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep66.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp64.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep66_i_reg <= decode_block_IQuantize_exit_scevgep66_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep66_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep66_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %73 = load i32* %scevgep44.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_73 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %74 = shl i32 %73, 2*/
begin
decode_block_IQuantize_exit_74 = decode_block_IQuantize_exit_73 <<< 32'd2 % 32;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %74 = shl i32 %73, 2*/
if (cur_state == LEGUP_F_decode_block_BB17_56)
begin
decode_block_IQuantize_exit_74_reg <= decode_block_IQuantize_exit_74;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_74) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_74_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %75 = load i32* %scevgep48.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_75 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %76 = load i32* %scevgep51.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_76 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %77 = load i32* %scevgep54.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_77 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %78 = load i32* %scevgep57.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_78 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %79 = shl i32 %78, 2*/
begin
decode_block_IQuantize_exit_79 = decode_block_IQuantize_exit_78 <<< 32'd2 % 32;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %80 = load i32* %scevgep60.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_80 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %81 = load i32* %scevgep63.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_81 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %82 = load i32* %scevgep66.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_82 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %83 = mul i32 %75, 400*/
begin
decode_block_IQuantize_exit_83 = decode_block_signed_multiply_32_1;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %83 = mul i32 %75, 400*/
decode_block_IQuantize_exit_83_reg = decode_block__preheader25_i_144_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %84 = mul i32 %82, -2008*/
begin
decode_block_IQuantize_exit_84 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %85 = add i32 %84, %83*/
begin
decode_block_IQuantize_exit_85 = decode_block_IQuantize_exit_84 + decode_block_IQuantize_exit_83_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %86 = ashr i32 %85, 9*/
begin
decode_block_IQuantize_exit_86 = $signed(decode_block_IQuantize_exit_85) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %86 = ashr i32 %85, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_86_reg <= decode_block_IQuantize_exit_86;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_86) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_86_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %87 = mul i32 %80, 1704*/
begin
decode_block_IQuantize_exit_87 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %88 = mul i32 %77, -1136*/
begin
decode_block_IQuantize_exit_88 = decode_block_signed_multiply_32_1;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %88 = mul i32 %77, -1136*/
decode_block_IQuantize_exit_88_reg = decode_block__preheader25_i_149_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %89 = add i32 %87, %88*/
begin
decode_block_IQuantize_exit_89 = decode_block_IQuantize_exit_87 + decode_block_IQuantize_exit_88_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %90 = ashr i32 %89, 9*/
begin
decode_block_IQuantize_exit_90 = $signed(decode_block_IQuantize_exit_89) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %90 = ashr i32 %89, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_IQuantize_exit_90_reg <= decode_block_IQuantize_exit_90;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_90_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %91 = mul i32 %77, 1704*/
begin
decode_block_IQuantize_exit_91 = decode_block_signed_multiply_32_3;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %91 = mul i32 %77, 1704*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block_IQuantize_exit_91_reg <= decode_block_IQuantize_exit_91;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_91) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_91_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %92 = mul i32 %80, 1136*/
begin
decode_block_IQuantize_exit_92 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %93 = add nsw i32 %92, %91*/
begin
decode_block_IQuantize_exit_93 = decode_block_IQuantize_exit_92 + decode_block_IQuantize_exit_91_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %94 = ashr i32 %93, 9*/
begin
decode_block_IQuantize_exit_94 = $signed(decode_block_IQuantize_exit_93) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %94 = ashr i32 %93, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_IQuantize_exit_94_reg <= decode_block_IQuantize_exit_94;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_94) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_94_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %95 = mul i32 %75, 2008*/
begin
decode_block_IQuantize_exit_95 = decode_block_signed_multiply_32_2;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %95 = mul i32 %75, 2008*/
decode_block_IQuantize_exit_95_reg = decode_block__preheader25_i_152_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %96 = mul i32 %82, 400*/
begin
decode_block_IQuantize_exit_96 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %97 = add nsw i32 %96, %95*/
begin
decode_block_IQuantize_exit_97 = decode_block_IQuantize_exit_96 + decode_block_IQuantize_exit_95_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %98 = ashr i32 %97, 9*/
begin
decode_block_IQuantize_exit_98 = $signed(decode_block_IQuantize_exit_97) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %98 = ashr i32 %97, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_98_reg <= decode_block_IQuantize_exit_98;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_98_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %99 = add nsw i32 %79, %74*/
begin
decode_block_IQuantize_exit_99 = decode_block_IQuantize_exit_79 + decode_block_IQuantize_exit_74_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %100 = mul nsw i32 %99, 362*/
begin
decode_block_IQuantize_exit_100 = decode_block_signed_multiply_32_0;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %100 = mul nsw i32 %99, 362*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block_IQuantize_exit_100_reg <= decode_block_IQuantize_exit_100;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_100_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %101 = ashr i32 %100, 9*/
begin
decode_block_IQuantize_exit_101 = $signed(decode_block_IQuantize_exit_100_reg) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %101 = ashr i32 %100, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_IQuantize_exit_101_reg <= decode_block_IQuantize_exit_101;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_101_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %102 = sub nsw i32 %74, %79*/
begin
decode_block_IQuantize_exit_102 = decode_block_IQuantize_exit_74_reg - decode_block_IQuantize_exit_79;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %103 = mul nsw i32 %102, 362*/
begin
decode_block_IQuantize_exit_103 = decode_block_signed_multiply_32_1;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %103 = mul nsw i32 %102, 362*/
decode_block_IQuantize_exit_103_reg = decode_block__preheader25_i_166_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %104 = ashr i32 %103, 9*/
begin
decode_block_IQuantize_exit_104 = $signed(decode_block_IQuantize_exit_103_reg) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %104 = ashr i32 %103, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_IQuantize_exit_104_reg <= decode_block_IQuantize_exit_104;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_104_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %105 = mul i32 %76, 784*/
begin
decode_block_IQuantize_exit_105 = decode_block_signed_multiply_32_3;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %105 = mul i32 %76, 784*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block_IQuantize_exit_105_reg <= decode_block_IQuantize_exit_105;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_105_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %106 = mul i32 %81, -1892*/
begin
decode_block_IQuantize_exit_106 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %107 = add i32 %106, %105*/
begin
decode_block_IQuantize_exit_107 = decode_block_IQuantize_exit_106 + decode_block_IQuantize_exit_105_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %108 = ashr i32 %107, 9*/
begin
decode_block_IQuantize_exit_108 = $signed(decode_block_IQuantize_exit_107) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %108 = ashr i32 %107, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_IQuantize_exit_108_reg <= decode_block_IQuantize_exit_108;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_108) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_108_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %109 = mul i32 %76, 1892*/
begin
decode_block_IQuantize_exit_109 = decode_block_signed_multiply_32_2;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %109 = mul i32 %76, 1892*/
decode_block_IQuantize_exit_109_reg = decode_block__preheader25_i_156_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %110 = mul i32 %81, 784*/
begin
decode_block_IQuantize_exit_110 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %111 = add nsw i32 %110, %109*/
begin
decode_block_IQuantize_exit_111 = decode_block_IQuantize_exit_110 + decode_block_IQuantize_exit_109_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %112 = ashr i32 %111, 9*/
begin
decode_block_IQuantize_exit_112 = $signed(decode_block_IQuantize_exit_111) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %112 = ashr i32 %111, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_IQuantize_exit_112_reg <= decode_block_IQuantize_exit_112;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_112_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %113 = add nsw i32 %112, %101*/
begin
decode_block_IQuantize_exit_113 = decode_block_IQuantize_exit_112_reg + decode_block_IQuantize_exit_101_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %113 = add nsw i32 %112, %101*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_113_reg <= decode_block_IQuantize_exit_113;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_113) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_113_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %114 = add nsw i32 %108, %104*/
begin
decode_block_IQuantize_exit_114 = decode_block_IQuantize_exit_108_reg + decode_block_IQuantize_exit_104_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %114 = add nsw i32 %108, %104*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_114_reg <= decode_block_IQuantize_exit_114;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_114_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %115 = sub nsw i32 %104, %108*/
begin
decode_block_IQuantize_exit_115 = decode_block_IQuantize_exit_104_reg - decode_block_IQuantize_exit_108_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %115 = sub nsw i32 %104, %108*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_115_reg <= decode_block_IQuantize_exit_115;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_115) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_115_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %116 = sub nsw i32 %101, %112*/
begin
decode_block_IQuantize_exit_116 = decode_block_IQuantize_exit_101_reg - decode_block_IQuantize_exit_112_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %116 = sub nsw i32 %101, %112*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_116_reg <= decode_block_IQuantize_exit_116;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_116_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %117 = add nsw i32 %86, %90*/
begin
decode_block_IQuantize_exit_117 = decode_block_IQuantize_exit_86_reg + decode_block_IQuantize_exit_90_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %118 = sub nsw i32 %86, %90*/
begin
decode_block_IQuantize_exit_118 = decode_block_IQuantize_exit_86_reg - decode_block_IQuantize_exit_90_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %119 = sub nsw i32 %98, %94*/
begin
decode_block_IQuantize_exit_119 = decode_block_IQuantize_exit_98_reg - decode_block_IQuantize_exit_94_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %120 = add nsw i32 %98, %94*/
begin
decode_block_IQuantize_exit_120 = decode_block_IQuantize_exit_98_reg + decode_block_IQuantize_exit_94_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %121 = sub nsw i32 %119, %118*/
begin
decode_block_IQuantize_exit_121 = decode_block_IQuantize_exit_119 - decode_block_IQuantize_exit_118;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %122 = mul nsw i32 %121, 362*/
begin
decode_block_IQuantize_exit_122 = decode_block_signed_multiply_32_1;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %122 = mul nsw i32 %121, 362*/
decode_block_IQuantize_exit_122_reg = decode_block__preheader25_i_144_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %123 = ashr i32 %122, 9*/
begin
decode_block_IQuantize_exit_123 = $signed(decode_block_IQuantize_exit_122_reg) >>> 32'd9;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %124 = add nsw i32 %119, %118*/
begin
decode_block_IQuantize_exit_124 = decode_block_IQuantize_exit_119 + decode_block_IQuantize_exit_118;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %125 = mul nsw i32 %124, 362*/
begin
decode_block_IQuantize_exit_125 = decode_block_signed_multiply_32_2;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %125 = mul nsw i32 %124, 362*/
decode_block_IQuantize_exit_125_reg = decode_block__preheader25_i_152_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %126 = ashr i32 %125, 9*/
begin
decode_block_IQuantize_exit_126 = $signed(decode_block_IQuantize_exit_125_reg) >>> 32'd9;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %127 = add nsw i32 %120, %113*/
begin
decode_block_IQuantize_exit_127 = decode_block_IQuantize_exit_120 + decode_block_IQuantize_exit_113_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %128 = add nsw i32 %126, %114*/
begin
decode_block_IQuantize_exit_128 = decode_block_IQuantize_exit_126 + decode_block_IQuantize_exit_114_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %129 = add nsw i32 %123, %115*/
begin
decode_block_IQuantize_exit_129 = decode_block_IQuantize_exit_123 + decode_block_IQuantize_exit_115_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %129 = add nsw i32 %123, %115*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
decode_block_IQuantize_exit_129_reg <= decode_block_IQuantize_exit_129;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_129_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %130 = add nsw i32 %117, %116*/
begin
decode_block_IQuantize_exit_130 = decode_block_IQuantize_exit_117 + decode_block_IQuantize_exit_116_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %130 = add nsw i32 %117, %116*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_IQuantize_exit_130_reg <= decode_block_IQuantize_exit_130;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_130_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %131 = sub nsw i32 %116, %117*/
begin
decode_block_IQuantize_exit_131 = decode_block_IQuantize_exit_116_reg - decode_block_IQuantize_exit_117;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %131 = sub nsw i32 %116, %117*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_IQuantize_exit_131_reg <= decode_block_IQuantize_exit_131;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_131_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %132 = sub nsw i32 %115, %123*/
begin
decode_block_IQuantize_exit_132 = decode_block_IQuantize_exit_115_reg - decode_block_IQuantize_exit_123;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %132 = sub nsw i32 %115, %123*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
decode_block_IQuantize_exit_132_reg <= decode_block_IQuantize_exit_132;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_132_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %133 = sub nsw i32 %114, %126*/
begin
decode_block_IQuantize_exit_133 = decode_block_IQuantize_exit_114_reg - decode_block_IQuantize_exit_126;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %133 = sub nsw i32 %114, %126*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
decode_block_IQuantize_exit_133_reg <= decode_block_IQuantize_exit_133;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_133_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %134 = sub nsw i32 %113, %120*/
begin
decode_block_IQuantize_exit_134 = decode_block_IQuantize_exit_113_reg - decode_block_IQuantize_exit_120;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %134 = sub nsw i32 %113, %120*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_IQuantize_exit_134_reg <= decode_block_IQuantize_exit_134;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_134_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %135 = add nsw i32 %i.027.i, 1*/
begin
decode_block_IQuantize_exit_135 = decode_block_IQuantize_exit_i_027_i + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %135 = add nsw i32 %i.027.i, 1*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_135_reg <= decode_block_IQuantize_exit_135;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_135_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %exitcond43.i = icmp eq i32 %135, 8*/
begin
decode_block_IQuantize_exit_exitcond43_i = decode_block_IQuantize_exit_135 == 32'd8;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %exitcond43.i = icmp eq i32 %135, 8*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_exitcond43_i_reg <= decode_block_IQuantize_exit_exitcond43_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_exitcond43_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_exitcond43_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %i.126.i = phi i32 [ %196, %.preheader25.i ], [ 0, %IQuantize.exit ]*/
begin
decode_block__preheader25_i_i_126_i = decode_block__preheader25_i_i_126_i_phi_temp;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp.i6 = shl i32 %i.126.i, 3*/
begin
decode_block__preheader25_i_tmp_i6 = decode_block__preheader25_i_i_126_i <<< 32'd3 % 32;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp2967.i = or i32 %tmp.i6, 7*/
begin
decode_block__preheader25_i_tmp2967_i = decode_block__preheader25_i_tmp_i6 | 32'd7;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep.i7 = getelementptr i32* %out_buf, i32 %tmp2967.i*/
begin
decode_block__preheader25_i_scevgep_i7 = arg_out_buf + 4 * decode_block__preheader25_i_tmp2967_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep.i7 = getelementptr i32* %out_buf, i32 %tmp2967.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep_i7_reg <= decode_block__preheader25_i_scevgep_i7;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep_i7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep_i7_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp3068.i = or i32 %tmp.i6, 6*/
begin
decode_block__preheader25_i_tmp3068_i = decode_block__preheader25_i_tmp_i6 | 32'd6;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep31.i = getelementptr i32* %out_buf, i32 %tmp3068.i*/
begin
decode_block__preheader25_i_scevgep31_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp3068_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep31.i = getelementptr i32* %out_buf, i32 %tmp3068.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep31_i_reg <= decode_block__preheader25_i_scevgep31_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep31_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep31_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp3269.i = or i32 %tmp.i6, 5*/
begin
decode_block__preheader25_i_tmp3269_i = decode_block__preheader25_i_tmp_i6 | 32'd5;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep33.i = getelementptr i32* %out_buf, i32 %tmp3269.i*/
begin
decode_block__preheader25_i_scevgep33_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp3269_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep33.i = getelementptr i32* %out_buf, i32 %tmp3269.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep33_i_reg <= decode_block__preheader25_i_scevgep33_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep33_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep33_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp3470.i = or i32 %tmp.i6, 4*/
begin
decode_block__preheader25_i_tmp3470_i = decode_block__preheader25_i_tmp_i6 | 32'd4;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep35.i = getelementptr i32* %out_buf, i32 %tmp3470.i*/
begin
decode_block__preheader25_i_scevgep35_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp3470_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep35.i = getelementptr i32* %out_buf, i32 %tmp3470.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep35_i_reg <= decode_block__preheader25_i_scevgep35_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep35_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep35_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp3671.i = or i32 %tmp.i6, 3*/
begin
decode_block__preheader25_i_tmp3671_i = decode_block__preheader25_i_tmp_i6 | 32'd3;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep37.i = getelementptr i32* %out_buf, i32 %tmp3671.i*/
begin
decode_block__preheader25_i_scevgep37_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp3671_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep37.i = getelementptr i32* %out_buf, i32 %tmp3671.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep37_i_reg <= decode_block__preheader25_i_scevgep37_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep37_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep37_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp3872.i = or i32 %tmp.i6, 2*/
begin
decode_block__preheader25_i_tmp3872_i = decode_block__preheader25_i_tmp_i6 | 32'd2;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep39.i = getelementptr i32* %out_buf, i32 %tmp3872.i*/
begin
decode_block__preheader25_i_scevgep39_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp3872_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep39.i = getelementptr i32* %out_buf, i32 %tmp3872.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep39_i_reg <= decode_block__preheader25_i_scevgep39_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep39_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep39_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp4073.i = or i32 %tmp.i6, 1*/
begin
decode_block__preheader25_i_tmp4073_i = decode_block__preheader25_i_tmp_i6 | 32'd1;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep41.i = getelementptr i32* %out_buf, i32 %tmp4073.i*/
begin
decode_block__preheader25_i_scevgep41_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp4073_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep41.i = getelementptr i32* %out_buf, i32 %tmp4073.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep41_i_reg <= decode_block__preheader25_i_scevgep41_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep41_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep41_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep42.i = getelementptr i32* %out_buf, i32 %tmp.i6*/
begin
decode_block__preheader25_i_scevgep42_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp_i6;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep42.i = getelementptr i32* %out_buf, i32 %tmp.i6*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep42_i_reg <= decode_block__preheader25_i_scevgep42_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep42_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep42_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_136 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_74)
begin
decode_block__preheader25_i_136_reg <= decode_block__preheader25_i_136;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_136_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %137 = load i32* %scevgep41.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_137 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %138 = load i32* %scevgep39.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_138 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %139 = load i32* %scevgep37.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_139 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %140 = load i32* %scevgep35.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_140 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %141 = load i32* %scevgep33.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_141 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %142 = load i32* %scevgep31.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_142 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %143 = load i32* %scevgep.i7, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_143 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %144 = mul nsw i32 %137, 100*/
begin
decode_block__preheader25_i_144 = decode_block_signed_multiply_32_1;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %144 = mul nsw i32 %137, 100*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block__preheader25_i_144_reg <= decode_block__preheader25_i_144;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_144_reg"); $finish; end
end
/* decode_block: %.preheader25.i*/
/* %183 = mul nsw i32 %182, 362*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
decode_block__preheader25_i_144_reg <= decode_block__preheader25_i_183;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_183) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_144_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %83 = mul i32 %75, 400*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block__preheader25_i_144_reg <= decode_block_IQuantize_exit_83;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_83) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_144_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %122 = mul nsw i32 %121, 362*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block__preheader25_i_144_reg <= decode_block_IQuantize_exit_122;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_144_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %145 = mul i32 %143, -502*/
begin
decode_block__preheader25_i_145 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %146 = add i32 %145, %144*/
begin
decode_block__preheader25_i_146 = decode_block__preheader25_i_145 + decode_block__preheader25_i_144_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %147 = ashr i32 %146, 9*/
begin
decode_block__preheader25_i_147 = $signed(decode_block__preheader25_i_146) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %147 = ashr i32 %146, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_147_reg <= decode_block__preheader25_i_147;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_147_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %148 = mul nsw i32 %141, 426*/
begin
decode_block__preheader25_i_148 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %149 = mul i32 %139, -284*/
begin
decode_block__preheader25_i_149 = decode_block_signed_multiply_32_1;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %149 = mul i32 %139, -284*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block__preheader25_i_149_reg <= decode_block__preheader25_i_149;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_149) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_149_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %88 = mul i32 %77, -1136*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block__preheader25_i_149_reg <= decode_block_IQuantize_exit_88;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_88) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_149_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %150 = add i32 %148, %149*/
begin
decode_block__preheader25_i_150 = decode_block__preheader25_i_148 + decode_block__preheader25_i_149_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %151 = ashr i32 %150, 9*/
begin
decode_block__preheader25_i_151 = $signed(decode_block__preheader25_i_150) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %151 = ashr i32 %150, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block__preheader25_i_151_reg <= decode_block__preheader25_i_151;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_151_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %152 = mul nsw i32 %139, 426*/
begin
decode_block__preheader25_i_152 = decode_block_signed_multiply_32_2;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %152 = mul nsw i32 %139, 426*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block__preheader25_i_152_reg <= decode_block__preheader25_i_152;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_152) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_152_reg"); $finish; end
end
/* decode_block: %.preheader25.i*/
/* %186 = mul nsw i32 %185, 362*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
decode_block__preheader25_i_152_reg <= decode_block__preheader25_i_186;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_186) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_152_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %95 = mul i32 %75, 2008*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block__preheader25_i_152_reg <= decode_block_IQuantize_exit_95;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_95) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_152_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %125 = mul nsw i32 %124, 362*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block__preheader25_i_152_reg <= decode_block_IQuantize_exit_125;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_125) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_152_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %153 = mul nsw i32 %141, 284*/
begin
decode_block__preheader25_i_153 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %154 = add nsw i32 %153, %152*/
begin
decode_block__preheader25_i_154 = decode_block__preheader25_i_153 + decode_block__preheader25_i_152_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %155 = ashr i32 %154, 9*/
begin
decode_block__preheader25_i_155 = $signed(decode_block__preheader25_i_154) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %155 = ashr i32 %154, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block__preheader25_i_155_reg <= decode_block__preheader25_i_155;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_155) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_155_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %156 = mul nsw i32 %137, 502*/
begin
decode_block__preheader25_i_156 = decode_block_signed_multiply_32_2;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %156 = mul nsw i32 %137, 502*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block__preheader25_i_156_reg <= decode_block__preheader25_i_156;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_156) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_156_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %109 = mul i32 %76, 1892*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block__preheader25_i_156_reg <= decode_block_IQuantize_exit_109;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_156_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %157 = mul nsw i32 %143, 100*/
begin
decode_block__preheader25_i_157 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %158 = add nsw i32 %157, %156*/
begin
decode_block__preheader25_i_158 = decode_block__preheader25_i_157 + decode_block__preheader25_i_156_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %159 = ashr i32 %158, 9*/
begin
decode_block__preheader25_i_159 = $signed(decode_block__preheader25_i_158) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %159 = ashr i32 %158, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_159_reg <= decode_block__preheader25_i_159;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_159) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_159_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %160 = add nsw i32 %140, %136*/
begin
decode_block__preheader25_i_160 = decode_block__preheader25_i_140 + decode_block__preheader25_i_136_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %161 = mul nsw i32 %160, 362*/
begin
decode_block__preheader25_i_161 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %162 = ashr i32 %161, 9*/
begin
decode_block__preheader25_i_162 = $signed(decode_block__preheader25_i_161) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %162 = ashr i32 %161, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block__preheader25_i_162_reg <= decode_block__preheader25_i_162;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_162) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_162_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %163 = sub nsw i32 %136, %140*/
begin
decode_block__preheader25_i_163 = decode_block__preheader25_i_136_reg - decode_block__preheader25_i_140;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %164 = mul nsw i32 %163, 362*/
begin
decode_block__preheader25_i_164 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %165 = ashr i32 %164, 9*/
begin
decode_block__preheader25_i_165 = $signed(decode_block__preheader25_i_164) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %165 = ashr i32 %164, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block__preheader25_i_165_reg <= decode_block__preheader25_i_165;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_165) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_165_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %166 = mul nsw i32 %138, 196*/
begin
decode_block__preheader25_i_166 = decode_block_signed_multiply_32_1;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %166 = mul nsw i32 %138, 196*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block__preheader25_i_166_reg <= decode_block__preheader25_i_166;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_166) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_166_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %103 = mul nsw i32 %102, 362*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block__preheader25_i_166_reg <= decode_block_IQuantize_exit_103;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_166_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %167 = mul i32 %142, -473*/
begin
decode_block__preheader25_i_167 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %168 = add i32 %167, %166*/
begin
decode_block__preheader25_i_168 = decode_block__preheader25_i_167 + decode_block__preheader25_i_166_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %169 = ashr i32 %168, 9*/
begin
decode_block__preheader25_i_169 = $signed(decode_block__preheader25_i_168) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %169 = ashr i32 %168, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block__preheader25_i_169_reg <= decode_block__preheader25_i_169;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_169) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_169_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %170 = mul nsw i32 %138, 473*/
begin
decode_block__preheader25_i_170 = decode_block_signed_multiply_32_2;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %170 = mul nsw i32 %138, 473*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block__preheader25_i_170_reg <= decode_block__preheader25_i_170;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_170) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_170_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %171 = mul nsw i32 %142, 196*/
begin
decode_block__preheader25_i_171 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %172 = add nsw i32 %171, %170*/
begin
decode_block__preheader25_i_172 = decode_block__preheader25_i_171 + decode_block__preheader25_i_170_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %173 = ashr i32 %172, 9*/
begin
decode_block__preheader25_i_173 = $signed(decode_block__preheader25_i_172) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %173 = ashr i32 %172, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block__preheader25_i_173_reg <= decode_block__preheader25_i_173;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_173) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_173_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %174 = add nsw i32 %173, %162*/
begin
decode_block__preheader25_i_174 = decode_block__preheader25_i_173_reg + decode_block__preheader25_i_162_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %174 = add nsw i32 %173, %162*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_174_reg <= decode_block__preheader25_i_174;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_174) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_174_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %175 = add nsw i32 %169, %165*/
begin
decode_block__preheader25_i_175 = decode_block__preheader25_i_169_reg + decode_block__preheader25_i_165_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %175 = add nsw i32 %169, %165*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_175_reg <= decode_block__preheader25_i_175;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_175) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_175_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %176 = sub nsw i32 %165, %169*/
begin
decode_block__preheader25_i_176 = decode_block__preheader25_i_165_reg - decode_block__preheader25_i_169_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %176 = sub nsw i32 %165, %169*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_176_reg <= decode_block__preheader25_i_176;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_176) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_176_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %177 = sub nsw i32 %162, %173*/
begin
decode_block__preheader25_i_177 = decode_block__preheader25_i_162_reg - decode_block__preheader25_i_173_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %177 = sub nsw i32 %162, %173*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_177_reg <= decode_block__preheader25_i_177;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_177) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_177_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %178 = add nsw i32 %147, %151*/
begin
decode_block__preheader25_i_178 = decode_block__preheader25_i_147_reg + decode_block__preheader25_i_151_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %179 = sub nsw i32 %147, %151*/
begin
decode_block__preheader25_i_179 = decode_block__preheader25_i_147_reg - decode_block__preheader25_i_151_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %180 = sub nsw i32 %159, %155*/
begin
decode_block__preheader25_i_180 = decode_block__preheader25_i_159_reg - decode_block__preheader25_i_155_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %181 = add nsw i32 %159, %155*/
begin
decode_block__preheader25_i_181 = decode_block__preheader25_i_159_reg + decode_block__preheader25_i_155_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %182 = sub nsw i32 %180, %179*/
begin
decode_block__preheader25_i_182 = decode_block__preheader25_i_180 - decode_block__preheader25_i_179;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %183 = mul nsw i32 %182, 362*/
begin
decode_block__preheader25_i_183 = decode_block_signed_multiply_32_1;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %183 = mul nsw i32 %182, 362*/
decode_block__preheader25_i_183_reg = decode_block__preheader25_i_144_reg;
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %184 = ashr i32 %183, 9*/
begin
decode_block__preheader25_i_184 = $signed(decode_block__preheader25_i_183_reg) >>> 32'd9;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %185 = add nsw i32 %180, %179*/
begin
decode_block__preheader25_i_185 = decode_block__preheader25_i_180 + decode_block__preheader25_i_179;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %186 = mul nsw i32 %185, 362*/
begin
decode_block__preheader25_i_186 = decode_block_signed_multiply_32_2;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %186 = mul nsw i32 %185, 362*/
decode_block__preheader25_i_186_reg = decode_block__preheader25_i_152_reg;
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %187 = ashr i32 %186, 9*/
begin
decode_block__preheader25_i_187 = $signed(decode_block__preheader25_i_186_reg) >>> 32'd9;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %188 = add nsw i32 %181, %174*/
begin
decode_block__preheader25_i_188 = decode_block__preheader25_i_181 + decode_block__preheader25_i_174_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %189 = add nsw i32 %187, %175*/
begin
decode_block__preheader25_i_189 = decode_block__preheader25_i_187 + decode_block__preheader25_i_175_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %190 = add nsw i32 %184, %176*/
begin
decode_block__preheader25_i_190 = decode_block__preheader25_i_184 + decode_block__preheader25_i_176_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %190 = add nsw i32 %184, %176*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
decode_block__preheader25_i_190_reg <= decode_block__preheader25_i_190;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_190) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_190_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %191 = add nsw i32 %178, %177*/
begin
decode_block__preheader25_i_191 = decode_block__preheader25_i_178 + decode_block__preheader25_i_177_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %191 = add nsw i32 %178, %177*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
decode_block__preheader25_i_191_reg <= decode_block__preheader25_i_191;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_191) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_191_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %192 = sub nsw i32 %177, %178*/
begin
decode_block__preheader25_i_192 = decode_block__preheader25_i_177_reg - decode_block__preheader25_i_178;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %192 = sub nsw i32 %177, %178*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
decode_block__preheader25_i_192_reg <= decode_block__preheader25_i_192;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_192_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %193 = sub nsw i32 %176, %184*/
begin
decode_block__preheader25_i_193 = decode_block__preheader25_i_176_reg - decode_block__preheader25_i_184;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %193 = sub nsw i32 %176, %184*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
decode_block__preheader25_i_193_reg <= decode_block__preheader25_i_193;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_193) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_193_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %194 = sub nsw i32 %175, %187*/
begin
decode_block__preheader25_i_194 = decode_block__preheader25_i_175_reg - decode_block__preheader25_i_187;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %194 = sub nsw i32 %175, %187*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
decode_block__preheader25_i_194_reg <= decode_block__preheader25_i_194;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_194) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_194_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %195 = sub nsw i32 %174, %181*/
begin
decode_block__preheader25_i_195 = decode_block__preheader25_i_174_reg - decode_block__preheader25_i_181;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %195 = sub nsw i32 %174, %181*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
decode_block__preheader25_i_195_reg <= decode_block__preheader25_i_195;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_195) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_195_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %196 = add nsw i32 %i.126.i, 1*/
begin
decode_block__preheader25_i_196 = decode_block__preheader25_i_i_126_i + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %196 = add nsw i32 %i.126.i, 1*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_196_reg <= decode_block__preheader25_i_196;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_196) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_196_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %exitcond28.i = icmp eq i32 %196, 8*/
begin
decode_block__preheader25_i_exitcond28_i = decode_block__preheader25_i_196 == 32'd8;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %exitcond28.i = icmp eq i32 %196, 8*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_exitcond28_i_reg <= decode_block__preheader25_i_exitcond28_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_exitcond28_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_exitcond28_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %i.224.i = phi i32 [ %203, %.preheader.i8 ], [ 0, %.preheader25.i ]*/
begin
decode_block__preheader_i8_i_224_i = decode_block__preheader_i8_i_224_i_phi_temp;
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %aptr.023.i = getelementptr i32* %out_buf, i32 %i.224.i*/
begin
decode_block__preheader_i8_aptr_023_i = arg_out_buf + 4 * decode_block__preheader_i8_i_224_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %aptr.023.i = getelementptr i32* %out_buf, i32 %i.224.i*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
decode_block__preheader_i8_aptr_023_i_reg <= decode_block__preheader_i8_aptr_023_i;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_aptr_023_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_aptr_023_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %197 = load i32* %aptr.023.i, align 4, !tbaa !2*/
begin
decode_block__preheader_i8_197 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %198 = ashr i32 %197, 31*/
begin
decode_block__preheader_i8_198 = $signed(decode_block__preheader_i8_197) >>> 32'd31;
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %199 = and i32 %198, -16*/
begin
decode_block__preheader_i8_199 = decode_block__preheader_i8_198 & -32'd16;
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %200 = or i32 %199, 8*/
begin
decode_block__preheader_i8_200 = decode_block__preheader_i8_199 | 32'd8;
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %201 = add i32 %200, %197*/
begin
decode_block__preheader_i8_201 = decode_block__preheader_i8_200 + decode_block__preheader_i8_197;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %201 = add i32 %200, %197*/
if (cur_state == LEGUP_F_decode_block_BB19_92)
begin
decode_block__preheader_i8_201_reg <= decode_block__preheader_i8_201;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_201_reg"); $finish; end
end
end
always @(*) begin
decode_block__preheader_i8_202 = decode_block_signed_divide_32_0;
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %202 = sdiv i32 %201, 16*/
if (cur_state == LEGUP_F_decode_block_BB19_132)
begin
decode_block__preheader_i8_202_reg <= decode_block__preheader_i8_202;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_202) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_202_reg"); $finish; end
end
/* decode_block: %.preheader.i8*/
/* %202 = sdiv i32 %201, 16*/
if (cur_state == LEGUP_F_decode_block_BB19_132)
begin
decode_block__preheader_i8_202_reg <= decode_block__preheader_i8_202;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_202) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_202_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %203 = add nsw i32 %i.224.i, 1*/
begin
decode_block__preheader_i8_203 = decode_block__preheader_i8_i_224_i + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %203 = add nsw i32 %i.224.i, 1*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
decode_block__preheader_i8_203_reg <= decode_block__preheader_i8_203;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_203) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_203_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %exitcond.i = icmp eq i32 %203, 64*/
begin
decode_block__preheader_i8_exitcond_i = decode_block__preheader_i8_203 == 32'd64;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %exitcond.i = icmp eq i32 %203, 64*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
decode_block__preheader_i8_exitcond_i_reg <= decode_block__preheader_i8_exitcond_i;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_exitcond_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_exitcond_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %indvar.i1 = phi i32 [ %tmp.i3, %ChenIDct.exit ], [ 0, %.preheader.i8 ]*/
begin
decode_block_ChenIDct_exit_indvar_i1 = decode_block_ChenIDct_exit_indvar_i1_phi_temp;
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %mptr.01.i2 = getelementptr i32* %out_buf, i32 %indvar.i1*/
begin
decode_block_ChenIDct_exit_mptr_01_i2 = arg_out_buf + 4 * decode_block_ChenIDct_exit_indvar_i1;
end
end
always @(posedge clk) begin
/* decode_block: %ChenIDct.exit*/
/* %mptr.01.i2 = getelementptr i32* %out_buf, i32 %indvar.i1*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
decode_block_ChenIDct_exit_mptr_01_i2_reg <= decode_block_ChenIDct_exit_mptr_01_i2;
if (^reset !== 1'bX && ^(decode_block_ChenIDct_exit_mptr_01_i2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_ChenIDct_exit_mptr_01_i2_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %tmp.i3 = add i32 %indvar.i1, 1*/
begin
decode_block_ChenIDct_exit_tmp_i3 = decode_block_ChenIDct_exit_indvar_i1 + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %ChenIDct.exit*/
/* %tmp.i3 = add i32 %indvar.i1, 1*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
decode_block_ChenIDct_exit_tmp_i3_reg <= decode_block_ChenIDct_exit_tmp_i3;
if (^reset !== 1'bX && ^(decode_block_ChenIDct_exit_tmp_i3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_ChenIDct_exit_tmp_i3_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %204 = load i32* %mptr.01.i2, align 4, !tbaa !2*/
begin
decode_block_ChenIDct_exit_204 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %205 = add nsw i32 %204, 128*/
begin
decode_block_ChenIDct_exit_205 = decode_block_ChenIDct_exit_204 + 32'd128;
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %exitcond7 = icmp eq i32 %tmp.i3, 64*/
begin
decode_block_ChenIDct_exit_exitcond7 = decode_block_ChenIDct_exit_tmp_i3 == 32'd64;
end
end
always @(posedge clk) begin
/* decode_block: %ChenIDct.exit*/
/* %exitcond7 = icmp eq i32 %tmp.i3, 64*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
decode_block_ChenIDct_exit_exitcond7_reg <= decode_block_ChenIDct_exit_exitcond7;
if (^reset !== 1'bX && ^(decode_block_ChenIDct_exit_exitcond7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_ChenIDct_exit_exitcond7_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %indvar.i = phi i32 [ %tmp.i, %212 ], [ 0, %ChenIDct.exit ]*/
begin
decode_block_PostshiftIDctMatrix_exit_indvar_i = decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp;
end
end
always @(*) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %mptr.01.i = getelementptr i32* %out_buf, i32 %indvar.i*/
begin
decode_block_PostshiftIDctMatrix_exit_mptr_01_i = arg_out_buf + 4 * decode_block_PostshiftIDctMatrix_exit_indvar_i;
end
end
always @(posedge clk) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %mptr.01.i = getelementptr i32* %out_buf, i32 %indvar.i*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
decode_block_PostshiftIDctMatrix_exit_mptr_01_i_reg <= decode_block_PostshiftIDctMatrix_exit_mptr_01_i;
if (^reset !== 1'bX && ^(decode_block_PostshiftIDctMatrix_exit_mptr_01_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_PostshiftIDctMatrix_exit_mptr_01_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %tmp.i = add i32 %indvar.i, 1*/
begin
decode_block_PostshiftIDctMatrix_exit_tmp_i = decode_block_PostshiftIDctMatrix_exit_indvar_i + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %tmp.i = add i32 %indvar.i, 1*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
decode_block_PostshiftIDctMatrix_exit_tmp_i_reg <= decode_block_PostshiftIDctMatrix_exit_tmp_i;
if (^reset !== 1'bX && ^(decode_block_PostshiftIDctMatrix_exit_tmp_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_PostshiftIDctMatrix_exit_tmp_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
begin
decode_block_PostshiftIDctMatrix_exit_206 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB21_146)
begin
decode_block_PostshiftIDctMatrix_exit_206_reg <= decode_block_PostshiftIDctMatrix_exit_206;
if (^reset !== 1'bX && ^(decode_block_PostshiftIDctMatrix_exit_206) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_PostshiftIDctMatrix_exit_206_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %207 = icmp slt i32 %206, 0*/
begin
decode_block_PostshiftIDctMatrix_exit_207 = $signed(decode_block_PostshiftIDctMatrix_exit_206) < $signed(32'd0);
end
end
always @(*) begin
/* decode_block: %209*/
/* %210 = icmp sgt i32 %206, 255*/
begin
decode_block_209_210 = $signed(decode_block_PostshiftIDctMatrix_exit_206_reg) > $signed(32'd255);
end
end
always @(*) begin
/* decode_block: %212*/
/* %exitcond = icmp eq i32 %tmp.i, 64*/
begin
decode_block_212_exitcond = decode_block_PostshiftIDctMatrix_exit_tmp_i_reg == 32'd64;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_start"); $finish; end
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
DecodeHuffman_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_start"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_start"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
DecodeHuffman_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_start"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_arg_Xhuff_huffval <= decode_block_0_4_reg;
if (^reset !== 1'bX && ^(decode_block_0_4_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Xhuff_huffval"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_arg_Xhuff_huffval <= decode_block__preheader_i_27_reg;
if (^reset !== 1'bX && ^(decode_block__preheader_i_27_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Xhuff_huffval"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_arg_Dhuff_ml <= decode_block_0_6;
if (^reset !== 1'bX && ^(decode_block_0_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_ml"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_arg_Dhuff_ml <= decode_block_34_35;
if (^reset !== 1'bX && ^(decode_block_34_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_ml"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_arg_Dhuff_maxcode <= decode_block_0_7_reg;
if (^reset !== 1'bX && ^(decode_block_0_7_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_maxcode"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_arg_Dhuff_maxcode <= decode_block__preheader_i_29_reg;
if (^reset !== 1'bX && ^(decode_block__preheader_i_29_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_maxcode"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_arg_Dhuff_mincode <= decode_block_0_8_reg;
if (^reset !== 1'bX && ^(decode_block_0_8_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_mincode"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_arg_Dhuff_mincode <= decode_block__preheader_i_30_reg;
if (^reset !== 1'bX && ^(decode_block__preheader_i_30_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_mincode"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_arg_Dhuff_valptr <= decode_block_0_9_reg;
if (^reset !== 1'bX && ^(decode_block_0_9_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_valptr"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_arg_Dhuff_valptr <= decode_block__preheader_i_31_reg;
if (^reset !== 1'bX && ^(decode_block__preheader_i_31_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_valptr"); $finish; end
end
end
always @(*) begin
DecodeHuffman_memory_controller_waitrequest = 1'd0;
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
DecodeHuffman_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
DecodeHuffman_memory_controller_waitrequest = memory_controller_waitrequest;
end
end
always @(*) begin
DecodeHuffman_memory_controller_out = 1'd0;
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
DecodeHuffman_memory_controller_out = memory_controller_out;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
DecodeHuffman_memory_controller_out = memory_controller_out;
end
end
always @(*) begin
legup_function_call = 1'd0;
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
legup_function_call = 1'd1;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
legup_function_call = 1'd1;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB1_8)
begin
legup_function_call = 1'd1;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
legup_function_call = 1'd1;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
legup_function_call = 1'd1;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
legup_function_call = 1'd1;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB9_29)
begin
legup_function_call = 1'd1;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
legup_function_call = 1'd1;
end
end
always @(posedge clk) begin
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB1_8)
begin
buf_getv_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_start"); $finish; end
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
buf_getv_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_start"); $finish; end
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB9_29)
begin
buf_getv_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_start"); $finish; end
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
buf_getv_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_start"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB1_8)
begin
buf_getv_arg_n <= decode_block_0_10_reg;
if (^reset !== 1'bX && ^(decode_block_0_10_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_arg_n"); $finish; end
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB9_29)
begin
buf_getv_arg_n <= decode_block_34_37_reg;
if (^reset !== 1'bX && ^(decode_block_34_37_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_arg_n"); $finish; end
end
end
always @(*) begin
buf_getv_memory_controller_waitrequest = 1'd0;
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
buf_getv_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
buf_getv_memory_controller_waitrequest = memory_controller_waitrequest;
end
end
always @(*) begin
buf_getv_memory_controller_out = 1'd0;
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
buf_getv_memory_controller_out = memory_controller_out;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
buf_getv_memory_controller_out = memory_controller_out;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %83 = mul i32 %75, 400*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block_signed_multiply_32_1_op0 = decode_block_IQuantize_exit_75;
end
/* decode_block: %IQuantize.exit*/
/* %88 = mul i32 %77, -1136*/
else if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block_signed_multiply_32_1_op0 = decode_block_IQuantize_exit_77;
end
/* decode_block: %IQuantize.exit*/
/* %103 = mul nsw i32 %102, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block_signed_multiply_32_1_op0 = decode_block_IQuantize_exit_102;
end
/* decode_block: %IQuantize.exit*/
/* %122 = mul nsw i32 %121, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_signed_multiply_32_1_op0 = decode_block_IQuantize_exit_121;
end
/* decode_block: %.preheader25.i*/
/* %144 = mul nsw i32 %137, 100*/
else if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block_signed_multiply_32_1_op0 = decode_block__preheader25_i_137;
end
/* decode_block: %.preheader25.i*/
/* %166 = mul nsw i32 %138, 196*/
else if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block_signed_multiply_32_1_op0 = decode_block__preheader25_i_138;
end
/* decode_block: %.preheader25.i*/
/* %149 = mul i32 %139, -284*/
else if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block_signed_multiply_32_1_op0 = decode_block__preheader25_i_139;
end
/* decode_block: %.preheader25.i*/
/* %183 = mul nsw i32 %182, 362*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_82) */
begin
decode_block_signed_multiply_32_1_op0 = decode_block__preheader25_i_182;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %83 = mul i32 %75, 400*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block_signed_multiply_32_1_op1 = 32'd400;
end
/* decode_block: %IQuantize.exit*/
/* %88 = mul i32 %77, -1136*/
else if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block_signed_multiply_32_1_op1 = -32'd1136;
end
/* decode_block: %IQuantize.exit*/
/* %103 = mul nsw i32 %102, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block_signed_multiply_32_1_op1 = 32'd362;
end
/* decode_block: %IQuantize.exit*/
/* %122 = mul nsw i32 %121, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_signed_multiply_32_1_op1 = 32'd362;
end
/* decode_block: %.preheader25.i*/
/* %144 = mul nsw i32 %137, 100*/
else if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block_signed_multiply_32_1_op1 = 32'd100;
end
/* decode_block: %.preheader25.i*/
/* %166 = mul nsw i32 %138, 196*/
else if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block_signed_multiply_32_1_op1 = 32'd196;
end
/* decode_block: %.preheader25.i*/
/* %149 = mul i32 %139, -284*/
else if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block_signed_multiply_32_1_op1 = -32'd284;
end
/* decode_block: %.preheader25.i*/
/* %183 = mul nsw i32 %182, 362*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_82) */
begin
decode_block_signed_multiply_32_1_op1 = 32'd362;
end
end
always @(*) begin
decode_block_signed_multiply_32_1 = decode_block_signed_multiply_32_1_op0 * decode_block_signed_multiply_32_1_op1;
end
always @(*) begin
/* decode_block: %69*/
/* %72 = mul nsw i32 %71, %70*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
decode_block_signed_multiply_32_0_op0 = decode_block_69_71;
end
/* decode_block: %IQuantize.exit*/
/* %100 = mul nsw i32 %99, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block_signed_multiply_32_0_op0 = decode_block_IQuantize_exit_99;
end
/* decode_block: %IQuantize.exit*/
/* %87 = mul i32 %80, 1704*/
else if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_signed_multiply_32_0_op0 = decode_block_IQuantize_exit_80;
end
/* decode_block: %IQuantize.exit*/
/* %106 = mul i32 %81, -1892*/
else if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_signed_multiply_32_0_op0 = decode_block_IQuantize_exit_81;
end
/* decode_block: %IQuantize.exit*/
/* %84 = mul i32 %82, -2008*/
else if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_signed_multiply_32_0_op0 = decode_block_IQuantize_exit_82;
end
/* decode_block: %.preheader25.i*/
/* %161 = mul nsw i32 %160, 362*/
else if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block_signed_multiply_32_0_op0 = decode_block__preheader25_i_160;
end
/* decode_block: %.preheader25.i*/
/* %148 = mul nsw i32 %141, 426*/
else if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block_signed_multiply_32_0_op0 = decode_block__preheader25_i_141;
end
/* decode_block: %.preheader25.i*/
/* %167 = mul i32 %142, -473*/
else if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block_signed_multiply_32_0_op0 = decode_block__preheader25_i_142;
end
/* decode_block: %.preheader25.i*/
/* %145 = mul i32 %143, -502*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_81) */
begin
decode_block_signed_multiply_32_0_op0 = decode_block__preheader25_i_143;
end
end
always @(*) begin
/* decode_block: %69*/
/* %72 = mul nsw i32 %71, %70*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
decode_block_signed_multiply_32_0_op1 = decode_block_69_70_reg;
end
/* decode_block: %IQuantize.exit*/
/* %100 = mul nsw i32 %99, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block_signed_multiply_32_0_op1 = 32'd362;
end
/* decode_block: %IQuantize.exit*/
/* %87 = mul i32 %80, 1704*/
else if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_signed_multiply_32_0_op1 = 32'd1704;
end
/* decode_block: %IQuantize.exit*/
/* %106 = mul i32 %81, -1892*/
else if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_signed_multiply_32_0_op1 = -32'd1892;
end
/* decode_block: %IQuantize.exit*/
/* %84 = mul i32 %82, -2008*/
else if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_signed_multiply_32_0_op1 = -32'd2008;
end
/* decode_block: %.preheader25.i*/
/* %161 = mul nsw i32 %160, 362*/
else if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block_signed_multiply_32_0_op1 = 32'd362;
end
/* decode_block: %.preheader25.i*/
/* %148 = mul nsw i32 %141, 426*/
else if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block_signed_multiply_32_0_op1 = 32'd426;
end
/* decode_block: %.preheader25.i*/
/* %167 = mul i32 %142, -473*/
else if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block_signed_multiply_32_0_op1 = -32'd473;
end
/* decode_block: %.preheader25.i*/
/* %145 = mul i32 %143, -502*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_81) */
begin
decode_block_signed_multiply_32_0_op1 = -32'd502;
end
end
always @(*) begin
decode_block_signed_multiply_32_0 = decode_block_signed_multiply_32_0_op0 * decode_block_signed_multiply_32_0_op1;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %95 = mul i32 %75, 2008*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block_signed_multiply_32_2_op0 = decode_block_IQuantize_exit_75;
end
/* decode_block: %IQuantize.exit*/
/* %109 = mul i32 %76, 1892*/
else if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block_signed_multiply_32_2_op0 = decode_block_IQuantize_exit_76;
end
/* decode_block: %IQuantize.exit*/
/* %125 = mul nsw i32 %124, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_signed_multiply_32_2_op0 = decode_block_IQuantize_exit_124;
end
/* decode_block: %.preheader25.i*/
/* %156 = mul nsw i32 %137, 502*/
else if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block_signed_multiply_32_2_op0 = decode_block__preheader25_i_137;
end
/* decode_block: %.preheader25.i*/
/* %170 = mul nsw i32 %138, 473*/
else if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block_signed_multiply_32_2_op0 = decode_block__preheader25_i_138;
end
/* decode_block: %.preheader25.i*/
/* %152 = mul nsw i32 %139, 426*/
else if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block_signed_multiply_32_2_op0 = decode_block__preheader25_i_139;
end
/* decode_block: %.preheader25.i*/
/* %186 = mul nsw i32 %185, 362*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_82) */
begin
decode_block_signed_multiply_32_2_op0 = decode_block__preheader25_i_185;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %95 = mul i32 %75, 2008*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block_signed_multiply_32_2_op1 = 32'd2008;
end
/* decode_block: %IQuantize.exit*/
/* %109 = mul i32 %76, 1892*/
else if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block_signed_multiply_32_2_op1 = 32'd1892;
end
/* decode_block: %IQuantize.exit*/
/* %125 = mul nsw i32 %124, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_signed_multiply_32_2_op1 = 32'd362;
end
/* decode_block: %.preheader25.i*/
/* %156 = mul nsw i32 %137, 502*/
else if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block_signed_multiply_32_2_op1 = 32'd502;
end
/* decode_block: %.preheader25.i*/
/* %170 = mul nsw i32 %138, 473*/
else if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block_signed_multiply_32_2_op1 = 32'd473;
end
/* decode_block: %.preheader25.i*/
/* %152 = mul nsw i32 %139, 426*/
else if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block_signed_multiply_32_2_op1 = 32'd426;
end
/* decode_block: %.preheader25.i*/
/* %186 = mul nsw i32 %185, 362*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_82) */
begin
decode_block_signed_multiply_32_2_op1 = 32'd362;
end
end
always @(*) begin
decode_block_signed_multiply_32_2 = decode_block_signed_multiply_32_2_op0 * decode_block_signed_multiply_32_2_op1;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %105 = mul i32 %76, 784*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block_signed_multiply_32_3_op0 = decode_block_IQuantize_exit_76;
end
/* decode_block: %IQuantize.exit*/
/* %91 = mul i32 %77, 1704*/
else if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block_signed_multiply_32_3_op0 = decode_block_IQuantize_exit_77;
end
/* decode_block: %IQuantize.exit*/
/* %92 = mul i32 %80, 1136*/
else if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_signed_multiply_32_3_op0 = decode_block_IQuantize_exit_80;
end
/* decode_block: %IQuantize.exit*/
/* %110 = mul i32 %81, 784*/
else if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_signed_multiply_32_3_op0 = decode_block_IQuantize_exit_81;
end
/* decode_block: %IQuantize.exit*/
/* %96 = mul i32 %82, 400*/
else if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_signed_multiply_32_3_op0 = decode_block_IQuantize_exit_82;
end
/* decode_block: %.preheader25.i*/
/* %164 = mul nsw i32 %163, 362*/
else if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block_signed_multiply_32_3_op0 = decode_block__preheader25_i_163;
end
/* decode_block: %.preheader25.i*/
/* %153 = mul nsw i32 %141, 284*/
else if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block_signed_multiply_32_3_op0 = decode_block__preheader25_i_141;
end
/* decode_block: %.preheader25.i*/
/* %171 = mul nsw i32 %142, 196*/
else if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block_signed_multiply_32_3_op0 = decode_block__preheader25_i_142;
end
/* decode_block: %.preheader25.i*/
/* %157 = mul nsw i32 %143, 100*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_81) */
begin
decode_block_signed_multiply_32_3_op0 = decode_block__preheader25_i_143;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %105 = mul i32 %76, 784*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block_signed_multiply_32_3_op1 = 32'd784;
end
/* decode_block: %IQuantize.exit*/
/* %91 = mul i32 %77, 1704*/
else if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block_signed_multiply_32_3_op1 = 32'd1704;
end
/* decode_block: %IQuantize.exit*/
/* %92 = mul i32 %80, 1136*/
else if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_signed_multiply_32_3_op1 = 32'd1136;
end
/* decode_block: %IQuantize.exit*/
/* %110 = mul i32 %81, 784*/
else if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_signed_multiply_32_3_op1 = 32'd784;
end
/* decode_block: %IQuantize.exit*/
/* %96 = mul i32 %82, 400*/
else if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_signed_multiply_32_3_op1 = 32'd400;
end
/* decode_block: %.preheader25.i*/
/* %164 = mul nsw i32 %163, 362*/
else if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block_signed_multiply_32_3_op1 = 32'd362;
end
/* decode_block: %.preheader25.i*/
/* %153 = mul nsw i32 %141, 284*/
else if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block_signed_multiply_32_3_op1 = 32'd284;
end
/* decode_block: %.preheader25.i*/
/* %171 = mul nsw i32 %142, 196*/
else if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block_signed_multiply_32_3_op1 = 32'd196;
end
/* decode_block: %.preheader25.i*/
/* %157 = mul nsw i32 %143, 100*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_81) */
begin
decode_block_signed_multiply_32_3_op1 = 32'd100;
end
end
always @(*) begin
decode_block_signed_multiply_32_3 = decode_block_signed_multiply_32_3_op0 * decode_block_signed_multiply_32_3_op1;
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %202 = sdiv i32 %201, 16*/
begin
decode_block_signed_divide_32_0_op0 = decode_block__preheader_i8_201_reg;
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %202 = sdiv i32 %201, 16*/
if (reset) begin decode_block_signed_divide_32_0_op1 = 0; end
begin
decode_block_signed_divide_32_0_op1 = 32'd16;
end
end
always @(*) begin
decode_block_signed_divide_32_0 = lpm_divide_decode_block__preheader_i8_202_out;
end
always @(*) begin
lpm_divide_decode_block__preheader_i8_202_en = memory_controller_waitrequest == 1'd0 & legup_function_call == 1'd0;
end
always @(posedge clk) begin
/* decode_block: %.lr.ph.i*/
/* %indvar.i2 = phi i32 [ %tmp4.i, %.lr.ph.i ], [ 0, %0 ], [ 0, %24 ]*/
if (cur_state == LEGUP_function_call_7 & memory_controller_waitrequest == 1'd0 & decode_block_0_11 == 1'd1)
begin
decode_block__lr_ph_i_indvar_i2_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__lr_ph_i_indvar_i2_phi_temp"); $finish; end
end
/* decode_block: %.lr.ph.i*/
/* %indvar.i2 = phi i32 [ %tmp4.i, %.lr.ph.i ], [ 0, %0 ], [ 0, %24 ]*/
if (cur_state == LEGUP_F_decode_block_BB3_19 & memory_controller_waitrequest == 1'd0)
begin
decode_block__lr_ph_i_indvar_i2_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__lr_ph_i_indvar_i2_phi_temp"); $finish; end
end
/* decode_block: %.lr.ph.i*/
/* %indvar.i2 = phi i32 [ %tmp4.i, %.lr.ph.i ], [ 0, %0 ], [ 0, %24 ]*/
if (cur_state == LEGUP_F_decode_block_BB5_21 & memory_controller_waitrequest == 1'd0 & decode_block__lr_ph_i_32 == 1'd1)
begin
decode_block__lr_ph_i_indvar_i2_phi_temp <= decode_block__lr_ph_i_tmp4_i;
if (^reset !== 1'bX && ^(decode_block__lr_ph_i_tmp4_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__lr_ph_i_indvar_i2_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB1_13 & memory_controller_waitrequest == 1'd0 & decode_block_12_18 == 1'd0)
begin
decode_block_24_diff_0_i_phi_temp <= decode_block_12_13_reg;
if (^reset !== 1'bX && ^(decode_block_12_13_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_24_diff_0_i_phi_temp"); $finish; end
end
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB2_16 & memory_controller_waitrequest == 1'd0)
begin
decode_block_24_diff_0_i_phi_temp <= decode_block_19_23;
if (^reset !== 1'bX && ^(decode_block_19_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_24_diff_0_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB4_20 & memory_controller_waitrequest == 1'd0)
begin
decode_block__backedge_i_k_0_i_phi_temp <= 32'd1;
if (^reset !== 1'bX && ^(32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_phi_temp"); $finish; end
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB11_39 & memory_controller_waitrequest == 1'd0)
begin
decode_block__backedge_i_k_0_i_phi_temp <= decode_block_57_58;
if (^reset !== 1'bX && ^(decode_block_57_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_phi_temp"); $finish; end
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB13_41 & memory_controller_waitrequest == 1'd0)
begin
decode_block__backedge_i_k_0_i_phi_temp <= decode_block_61_62;
if (^reset !== 1'bX && ^(decode_block_61_62) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %i.02.i = phi i32 [ %66, %DecodeHuffMCU.exit ], [ 0, %.backedge.i ], [ 0, %41 ], [ 0, %59 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22 & memory_controller_waitrequest == 1'd0 & decode_block__backedge_i_33 == 1'd0)
begin
decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp"); $finish; end
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %i.02.i = phi i32 [ %66, %DecodeHuffMCU.exit ], [ 0, %.backedge.i ], [ 0, %41 ], [ 0, %59 ]*/
if (cur_state == LEGUP_F_decode_block_BB8_28 & memory_controller_waitrequest == 1'd0 & decode_block_41_43 == 1'd1)
begin
decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp"); $finish; end
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %i.02.i = phi i32 [ %66, %DecodeHuffMCU.exit ], [ 0, %.backedge.i ], [ 0, %41 ], [ 0, %59 ]*/
if (cur_state == LEGUP_F_decode_block_BB12_40 & memory_controller_waitrequest == 1'd0 & decode_block_59_60 == 1'd0)
begin
decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp"); $finish; end
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %i.02.i = phi i32 [ %66, %DecodeHuffMCU.exit ], [ 0, %.backedge.i ], [ 0, %41 ], [ 0, %59 ]*/
if (cur_state == LEGUP_F_decode_block_BB14_46 & memory_controller_waitrequest == 1'd0 & decode_block_DecodeHuffMCU_exit_exitcond10_reg == 1'd0)
begin
decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp <= decode_block_DecodeHuffMCU_exit_66_reg;
if (^reset !== 1'bX && ^(decode_block_DecodeHuffMCU_exit_66_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %indvar.i4 = phi i32 [ 0, %IZigzagMatrix.exit ], [ %tmp.i5, %69 ]*/
if (cur_state == LEGUP_F_decode_block_BB15_49 & memory_controller_waitrequest == 1'd0)
begin
decode_block_69_indvar_i4_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_indvar_i4_phi_temp"); $finish; end
end
/* decode_block: %69*/
/* %indvar.i4 = phi i32 [ 0, %IZigzagMatrix.exit ], [ %tmp.i5, %69 ]*/
if (cur_state == LEGUP_F_decode_block_BB16_53 & memory_controller_waitrequest == 1'd0 & decode_block_69_exitcond8_reg == 1'd0)
begin
decode_block_69_indvar_i4_phi_temp <= decode_block_69_tmp_i5_reg;
if (^reset !== 1'bX && ^(decode_block_69_tmp_i5_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_indvar_i4_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %i.027.i = phi i32 [ %135, %IQuantize.exit ], [ 0, %69 ]*/
if (cur_state == LEGUP_F_decode_block_BB16_53 & memory_controller_waitrequest == 1'd0 & decode_block_69_exitcond8_reg == 1'd1)
begin
decode_block_IQuantize_exit_i_027_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_i_027_i_phi_temp"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %i.027.i = phi i32 [ %135, %IQuantize.exit ], [ 0, %69 ]*/
if (cur_state == LEGUP_F_decode_block_BB17_71 & memory_controller_waitrequest == 1'd0 & decode_block_IQuantize_exit_exitcond43_i_reg == 1'd0)
begin
decode_block_IQuantize_exit_i_027_i_phi_temp <= decode_block_IQuantize_exit_135_reg;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_135_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_i_027_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %i.126.i = phi i32 [ %196, %.preheader25.i ], [ 0, %IQuantize.exit ]*/
if (cur_state == LEGUP_F_decode_block_BB17_71 & memory_controller_waitrequest == 1'd0 & decode_block_IQuantize_exit_exitcond43_i_reg == 1'd1)
begin
decode_block__preheader25_i_i_126_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_i_126_i_phi_temp"); $finish; end
end
/* decode_block: %.preheader25.i*/
/* %i.126.i = phi i32 [ %196, %.preheader25.i ], [ 0, %IQuantize.exit ]*/
if (cur_state == LEGUP_F_decode_block_BB18_89 & memory_controller_waitrequest == 1'd0 & decode_block__preheader25_i_exitcond28_i_reg == 1'd0)
begin
decode_block__preheader25_i_i_126_i_phi_temp <= decode_block__preheader25_i_196_reg;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_196_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_i_126_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %i.224.i = phi i32 [ %203, %.preheader.i8 ], [ 0, %.preheader25.i ]*/
if (cur_state == LEGUP_F_decode_block_BB18_89 & memory_controller_waitrequest == 1'd0 & decode_block__preheader25_i_exitcond28_i_reg == 1'd1)
begin
decode_block__preheader_i8_i_224_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_i_224_i_phi_temp"); $finish; end
end
/* decode_block: %.preheader.i8*/
/* %i.224.i = phi i32 [ %203, %.preheader.i8 ], [ 0, %.preheader25.i ]*/
if (cur_state == LEGUP_F_decode_block_BB19_140 & memory_controller_waitrequest == 1'd0 & decode_block__preheader_i8_exitcond_i_reg == 1'd0)
begin
decode_block__preheader_i8_i_224_i_phi_temp <= decode_block__preheader_i8_203_reg;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_203_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_i_224_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %ChenIDct.exit*/
/* %indvar.i1 = phi i32 [ %tmp.i3, %ChenIDct.exit ], [ 0, %.preheader.i8 ]*/
if (cur_state == LEGUP_F_decode_block_BB19_140 & memory_controller_waitrequest == 1'd0 & decode_block__preheader_i8_exitcond_i_reg == 1'd1)
begin
decode_block_ChenIDct_exit_indvar_i1_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_ChenIDct_exit_indvar_i1_phi_temp"); $finish; end
end
/* decode_block: %ChenIDct.exit*/
/* %indvar.i1 = phi i32 [ %tmp.i3, %ChenIDct.exit ], [ 0, %.preheader.i8 ]*/
if (cur_state == LEGUP_F_decode_block_BB20_143 & memory_controller_waitrequest == 1'd0 & decode_block_ChenIDct_exit_exitcond7_reg == 1'd0)
begin
decode_block_ChenIDct_exit_indvar_i1_phi_temp <= decode_block_ChenIDct_exit_tmp_i3_reg;
if (^reset !== 1'bX && ^(decode_block_ChenIDct_exit_tmp_i3_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_ChenIDct_exit_indvar_i1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %indvar.i = phi i32 [ %tmp.i, %212 ], [ 0, %ChenIDct.exit ]*/
if (cur_state == LEGUP_F_decode_block_BB20_143 & memory_controller_waitrequest == 1'd0 & decode_block_ChenIDct_exit_exitcond7_reg == 1'd1)
begin
decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp"); $finish; end
end
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %indvar.i = phi i32 [ %tmp.i, %212 ], [ 0, %ChenIDct.exit ]*/
if (cur_state == LEGUP_F_decode_block_BB25_150 & memory_controller_waitrequest == 1'd0 & decode_block_212_exitcond == 1'd0)
begin
decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp <= decode_block_PostshiftIDctMatrix_exit_tmp_i_reg;
if (^reset !== 1'bX && ^(decode_block_PostshiftIDctMatrix_exit_tmp_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* decode_block: %BoundIDctMatrix.exit*/
/* ret void*/
if (cur_state == LEGUP_F_decode_block_BB26_151)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
memory_controller_address = DecodeHuffman_memory_controller_address;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
memory_controller_address = buf_getv_memory_controller_address;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
memory_controller_address = DecodeHuffman_memory_controller_address;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
memory_controller_address = buf_getv_memory_controller_address;
end
/* decode_block: %0*/
/* %2 = load i8* %1, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB0_1)
begin
memory_controller_address = decode_block_0_1;
end
/* decode_block: %0*/
/* %6 = load i32* %5, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
memory_controller_address = decode_block_0_5;
end
/* decode_block: %12*/
/* %16 = load i32* %15, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB1_11)
begin
memory_controller_address = decode_block_12_15_reg;
end
/* decode_block: %19*/
/* %21 = load i32* %20, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB2_14)
begin
memory_controller_address = decode_block_19_20;
end
/* decode_block: %24*/
/* %25 = load i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
memory_controller_address = arg_HuffBuff;
end
/* decode_block: %24*/
/* store i32 %26, i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_19)
begin
memory_controller_address = arg_HuffBuff;
end
/* decode_block: %.lr.ph.i*/
/* store i32 0, i32* %mptr.03.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB5_21)
begin
memory_controller_address = decode_block__lr_ph_i_mptr_03_i;
end
/* decode_block: %34*/
/* %35 = load i32* %28, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB7_23)
begin
memory_controller_address = decode_block__preheader_i_28_reg;
end
/* decode_block: %44*/
/* store i32 %45, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_32)
begin
memory_controller_address = decode_block_44_46_reg;
end
/* decode_block: %44*/
/* %49 = load i32* %48, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_33)
begin
memory_controller_address = decode_block_44_48_reg;
end
/* decode_block: %52*/
/* %54 = load i32* %53, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_36)
begin
memory_controller_address = decode_block_52_53;
end
/* decode_block: %52*/
/* store i32 %56, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_38)
begin
memory_controller_address = decode_block_44_46_reg;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %63 = load i32* %scevgep.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
memory_controller_address = decode_block_DecodeHuffMCU_exit_scevgep_i;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %65 = load i32* %64, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_44)
begin
memory_controller_address = decode_block_DecodeHuffMCU_exit_64;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* store i32 %65, i32* %.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_46)
begin
memory_controller_address = decode_block_DecodeHuffMCU_exit__01_i_reg;
end
/* decode_block: %IZigzagMatrix.exit*/
/* %68 = load i8* %67, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB15_47)
begin
memory_controller_address = decode_block_IZigzagMatrix_exit_67;
end
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
memory_controller_address = decode_block_69_mptr_02_i;
end
/* decode_block: %69*/
/* %71 = load i32* %.01.i6, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_51)
begin
memory_controller_address = decode_block_69__01_i6_reg;
end
/* decode_block: %69*/
/* store i32 %72, i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
memory_controller_address = decode_block_69_mptr_02_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %73 = load i32* %scevgep44.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep44_i;
end
/* decode_block: %IQuantize.exit*/
/* %75 = load i32* %scevgep48.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_55)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep48_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %76 = load i32* %scevgep51.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_56)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep51_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %77 = load i32* %scevgep54.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep54_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %78 = load i32* %scevgep57.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep57_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %80 = load i32* %scevgep60.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep60_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %81 = load i32* %scevgep63.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep63_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %82 = load i32* %scevgep66.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep66_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %127, i32* %scevgep45.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep45_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %128, i32* %scevgep47.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep47_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %129, i32* %scevgep50.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_66)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep50_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %130, i32* %scevgep53.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_67)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep53_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %131, i32* %scevgep56.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_68)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep56_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %132, i32* %scevgep59.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_69)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep59_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %133, i32* %scevgep62.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_70)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep62_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %134, i32* %scevgep65.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_71)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep65_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
memory_controller_address = decode_block__preheader25_i_scevgep42_i;
end
/* decode_block: %.preheader25.i*/
/* %137 = load i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_73)
begin
memory_controller_address = decode_block__preheader25_i_scevgep41_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %138 = load i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_74)
begin
memory_controller_address = decode_block__preheader25_i_scevgep39_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %139 = load i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
memory_controller_address = decode_block__preheader25_i_scevgep37_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %140 = load i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
memory_controller_address = decode_block__preheader25_i_scevgep35_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %141 = load i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
memory_controller_address = decode_block__preheader25_i_scevgep33_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %142 = load i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
memory_controller_address = decode_block__preheader25_i_scevgep31_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %143 = load i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
memory_controller_address = decode_block__preheader25_i_scevgep_i7_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %188, i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
memory_controller_address = decode_block__preheader25_i_scevgep42_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %189, i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
memory_controller_address = decode_block__preheader25_i_scevgep41_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %190, i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_84)
begin
memory_controller_address = decode_block__preheader25_i_scevgep39_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %191, i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_85)
begin
memory_controller_address = decode_block__preheader25_i_scevgep37_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %192, i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_86)
begin
memory_controller_address = decode_block__preheader25_i_scevgep35_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %193, i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_87)
begin
memory_controller_address = decode_block__preheader25_i_scevgep33_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %194, i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_88)
begin
memory_controller_address = decode_block__preheader25_i_scevgep31_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %195, i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_89)
begin
memory_controller_address = decode_block__preheader25_i_scevgep_i7_reg;
end
/* decode_block: %.preheader.i8*/
/* %197 = load i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
memory_controller_address = decode_block__preheader_i8_aptr_023_i;
end
/* decode_block: %.preheader.i8*/
/* store i32 %202, i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_140)
begin
memory_controller_address = decode_block__preheader_i8_aptr_023_i_reg;
end
/* decode_block: %ChenIDct.exit*/
/* %204 = load i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
memory_controller_address = decode_block_ChenIDct_exit_mptr_01_i2;
end
/* decode_block: %ChenIDct.exit*/
/* store i32 %205, i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_143)
begin
memory_controller_address = decode_block_ChenIDct_exit_mptr_01_i2_reg;
end
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
memory_controller_address = decode_block_PostshiftIDctMatrix_exit_mptr_01_i;
end
/* decode_block: %208*/
/* store i32 0, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB22_147)
begin
memory_controller_address = decode_block_PostshiftIDctMatrix_exit_mptr_01_i_reg;
end
/* decode_block: %211*/
/* store i32 255, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB24_149)
begin
memory_controller_address = decode_block_PostshiftIDctMatrix_exit_mptr_01_i_reg;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
memory_controller_enable = DecodeHuffman_memory_controller_enable;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
memory_controller_enable = buf_getv_memory_controller_enable;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
memory_controller_enable = DecodeHuffman_memory_controller_enable;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
memory_controller_enable = buf_getv_memory_controller_enable;
end
/* decode_block: %0*/
/* %2 = load i8* %1, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB0_1)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %0*/
/* %6 = load i32* %5, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %12*/
/* %16 = load i32* %15, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB1_11)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %19*/
/* %21 = load i32* %20, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB2_14)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %24*/
/* %25 = load i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %24*/
/* store i32 %26, i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_19)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.lr.ph.i*/
/* store i32 0, i32* %mptr.03.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB5_21)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %34*/
/* %35 = load i32* %28, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB7_23)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %44*/
/* store i32 %45, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_32)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %44*/
/* %49 = load i32* %48, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_33)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %52*/
/* %54 = load i32* %53, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_36)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %52*/
/* store i32 %56, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_38)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %63 = load i32* %scevgep.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %65 = load i32* %64, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_44)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* store i32 %65, i32* %.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_46)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IZigzagMatrix.exit*/
/* %68 = load i8* %67, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB15_47)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %69*/
/* %71 = load i32* %.01.i6, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_51)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %69*/
/* store i32 %72, i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %73 = load i32* %scevgep44.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %75 = load i32* %scevgep48.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_55)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %76 = load i32* %scevgep51.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_56)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %77 = load i32* %scevgep54.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %78 = load i32* %scevgep57.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %80 = load i32* %scevgep60.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %81 = load i32* %scevgep63.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %82 = load i32* %scevgep66.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %127, i32* %scevgep45.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %128, i32* %scevgep47.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %129, i32* %scevgep50.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_66)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %130, i32* %scevgep53.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_67)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %131, i32* %scevgep56.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_68)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %132, i32* %scevgep59.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_69)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %133, i32* %scevgep62.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_70)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %134, i32* %scevgep65.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_71)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %137 = load i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_73)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %138 = load i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_74)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %139 = load i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %140 = load i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %141 = load i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %142 = load i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %143 = load i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %188, i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %189, i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %190, i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_84)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %191, i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_85)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %192, i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_86)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %193, i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_87)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %194, i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_88)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %195, i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_89)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader.i8*/
/* %197 = load i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader.i8*/
/* store i32 %202, i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_140)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %ChenIDct.exit*/
/* %204 = load i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %ChenIDct.exit*/
/* store i32 %205, i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_143)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %208*/
/* store i32 0, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB22_147)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %211*/
/* store i32 255, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB24_149)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
memory_controller_write_enable = DecodeHuffman_memory_controller_write_enable;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
memory_controller_write_enable = buf_getv_memory_controller_write_enable;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
memory_controller_write_enable = DecodeHuffman_memory_controller_write_enable;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
memory_controller_write_enable = buf_getv_memory_controller_write_enable;
end
/* decode_block: %0*/
/* %2 = load i8* %1, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB0_1)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %0*/
/* %6 = load i32* %5, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %12*/
/* %16 = load i32* %15, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB1_11)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %19*/
/* %21 = load i32* %20, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB2_14)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %24*/
/* %25 = load i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %24*/
/* store i32 %26, i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_19)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.lr.ph.i*/
/* store i32 0, i32* %mptr.03.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB5_21)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %34*/
/* %35 = load i32* %28, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB7_23)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %44*/
/* store i32 %45, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_32)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %44*/
/* %49 = load i32* %48, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_33)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %52*/
/* %54 = load i32* %53, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_36)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %52*/
/* store i32 %56, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_38)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %63 = load i32* %scevgep.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %65 = load i32* %64, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_44)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* store i32 %65, i32* %.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_46)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IZigzagMatrix.exit*/
/* %68 = load i8* %67, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB15_47)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %69*/
/* %71 = load i32* %.01.i6, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_51)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %69*/
/* store i32 %72, i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %73 = load i32* %scevgep44.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %75 = load i32* %scevgep48.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_55)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %76 = load i32* %scevgep51.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_56)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %77 = load i32* %scevgep54.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %78 = load i32* %scevgep57.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %80 = load i32* %scevgep60.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %81 = load i32* %scevgep63.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %82 = load i32* %scevgep66.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %127, i32* %scevgep45.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %128, i32* %scevgep47.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %129, i32* %scevgep50.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_66)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %130, i32* %scevgep53.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_67)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %131, i32* %scevgep56.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_68)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %132, i32* %scevgep59.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_69)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %133, i32* %scevgep62.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_70)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %134, i32* %scevgep65.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_71)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %137 = load i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_73)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %138 = load i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_74)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %139 = load i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %140 = load i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %141 = load i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %142 = load i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %143 = load i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* store i32 %188, i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %189, i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %190, i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_84)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %191, i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_85)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %192, i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_86)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %193, i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_87)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %194, i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_88)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %195, i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_89)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader.i8*/
/* %197 = load i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader.i8*/
/* store i32 %202, i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_140)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %ChenIDct.exit*/
/* %204 = load i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %ChenIDct.exit*/
/* store i32 %205, i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_143)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %208*/
/* store i32 0, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB22_147)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %211*/
/* store i32 255, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB24_149)
begin
memory_controller_write_enable = 1'd1;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
memory_controller_in = DecodeHuffman_memory_controller_in;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
memory_controller_in = buf_getv_memory_controller_in;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
memory_controller_in = DecodeHuffman_memory_controller_in;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
memory_controller_in = buf_getv_memory_controller_in;
end
/* decode_block: %24*/
/* store i32 %26, i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_19)
begin
memory_controller_in = decode_block_24_26;
end
/* decode_block: %.lr.ph.i*/
/* store i32 0, i32* %mptr.03.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB5_21)
begin
memory_controller_in = 32'd0;
end
/* decode_block: %44*/
/* store i32 %45, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_32)
begin
memory_controller_in = decode_block_44_45_reg;
end
/* decode_block: %52*/
/* store i32 %56, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_38)
begin
memory_controller_in = decode_block_52_56;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* store i32 %65, i32* %.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_46)
begin
memory_controller_in = decode_block_DecodeHuffMCU_exit_65;
end
/* decode_block: %69*/
/* store i32 %72, i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
memory_controller_in = decode_block_69_72;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %127, i32* %scevgep45.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
memory_controller_in = decode_block_IQuantize_exit_127;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %128, i32* %scevgep47.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
memory_controller_in = decode_block_IQuantize_exit_128;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %129, i32* %scevgep50.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_66)
begin
memory_controller_in = decode_block_IQuantize_exit_129_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %130, i32* %scevgep53.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_67)
begin
memory_controller_in = decode_block_IQuantize_exit_130_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %131, i32* %scevgep56.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_68)
begin
memory_controller_in = decode_block_IQuantize_exit_131_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %132, i32* %scevgep59.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_69)
begin
memory_controller_in = decode_block_IQuantize_exit_132_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %133, i32* %scevgep62.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_70)
begin
memory_controller_in = decode_block_IQuantize_exit_133_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %134, i32* %scevgep65.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_71)
begin
memory_controller_in = decode_block_IQuantize_exit_134_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %188, i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
memory_controller_in = decode_block__preheader25_i_188;
end
/* decode_block: %.preheader25.i*/
/* store i32 %189, i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
memory_controller_in = decode_block__preheader25_i_189;
end
/* decode_block: %.preheader25.i*/
/* store i32 %190, i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_84)
begin
memory_controller_in = decode_block__preheader25_i_190_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %191, i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_85)
begin
memory_controller_in = decode_block__preheader25_i_191_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %192, i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_86)
begin
memory_controller_in = decode_block__preheader25_i_192_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %193, i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_87)
begin
memory_controller_in = decode_block__preheader25_i_193_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %194, i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_88)
begin
memory_controller_in = decode_block__preheader25_i_194_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %195, i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_89)
begin
memory_controller_in = decode_block__preheader25_i_195_reg;
end
/* decode_block: %.preheader.i8*/
/* store i32 %202, i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_140)
begin
memory_controller_in = decode_block__preheader_i8_202_reg;
end
/* decode_block: %ChenIDct.exit*/
/* store i32 %205, i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_143)
begin
memory_controller_in = decode_block_ChenIDct_exit_205;
end
/* decode_block: %208*/
/* store i32 0, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB22_147)
begin
memory_controller_in = 32'd0;
end
/* decode_block: %211*/
/* store i32 255, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB24_149)
begin
memory_controller_in = 32'd255;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
memory_controller_size = DecodeHuffman_memory_controller_size;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
memory_controller_size = buf_getv_memory_controller_size;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
memory_controller_size = DecodeHuffman_memory_controller_size;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
memory_controller_size = buf_getv_memory_controller_size;
end
/* decode_block: %0*/
/* %2 = load i8* %1, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB0_1)
begin
memory_controller_size = 2'd0;
end
/* decode_block: %0*/
/* %6 = load i32* %5, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %12*/
/* %16 = load i32* %15, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB1_11)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %19*/
/* %21 = load i32* %20, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB2_14)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %24*/
/* %25 = load i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %24*/
/* store i32 %26, i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_19)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.lr.ph.i*/
/* store i32 0, i32* %mptr.03.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB5_21)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %34*/
/* %35 = load i32* %28, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB7_23)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %44*/
/* store i32 %45, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_32)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %44*/
/* %49 = load i32* %48, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_33)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %52*/
/* %54 = load i32* %53, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_36)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %52*/
/* store i32 %56, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_38)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %63 = load i32* %scevgep.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %65 = load i32* %64, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_44)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* store i32 %65, i32* %.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_46)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IZigzagMatrix.exit*/
/* %68 = load i8* %67, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB15_47)
begin
memory_controller_size = 2'd0;
end
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %69*/
/* %71 = load i32* %.01.i6, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_51)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %69*/
/* store i32 %72, i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %73 = load i32* %scevgep44.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %75 = load i32* %scevgep48.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_55)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %76 = load i32* %scevgep51.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_56)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %77 = load i32* %scevgep54.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %78 = load i32* %scevgep57.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %80 = load i32* %scevgep60.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %81 = load i32* %scevgep63.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %82 = load i32* %scevgep66.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %127, i32* %scevgep45.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %128, i32* %scevgep47.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %129, i32* %scevgep50.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_66)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %130, i32* %scevgep53.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_67)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %131, i32* %scevgep56.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_68)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %132, i32* %scevgep59.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_69)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %133, i32* %scevgep62.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_70)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %134, i32* %scevgep65.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_71)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %137 = load i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_73)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %138 = load i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_74)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %139 = load i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %140 = load i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %141 = load i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %142 = load i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %143 = load i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %188, i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %189, i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %190, i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_84)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %191, i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_85)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %192, i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_86)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %193, i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_87)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %194, i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_88)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %195, i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_89)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader.i8*/
/* %197 = load i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader.i8*/
/* store i32 %202, i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_140)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %ChenIDct.exit*/
/* %204 = load i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %ChenIDct.exit*/
/* store i32 %205, i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_143)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %208*/
/* store i32 0, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB22_147)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %211*/
/* store i32 255, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB24_149)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module buf_getv
(
clk,
reset,
start,
finish,
return_val,
arg_n,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [5:0] LEGUP_0 = 6'd0;
parameter [5:0] LEGUP_F_buf_getv_BB0_1 = 6'd1;
parameter [5:0] LEGUP_F_buf_getv_BB0_2 = 6'd2;
parameter [5:0] LEGUP_F_buf_getv_BB0_3 = 6'd3;
parameter [5:0] LEGUP_F_buf_getv_BB1_4 = 6'd4;
parameter [5:0] LEGUP_F_buf_getv_BB2_5 = 6'd5;
parameter [5:0] LEGUP_F_buf_getv_BB2_6 = 6'd6;
parameter [5:0] LEGUP_F_buf_getv_BB2_7 = 6'd7;
parameter [5:0] LEGUP_F_buf_getv_BB3_8 = 6'd8;
parameter [5:0] LEGUP_F_buf_getv_BB3_9 = 6'd9;
parameter [5:0] LEGUP_F_buf_getv_BB3_10 = 6'd10;
parameter [5:0] LEGUP_F_buf_getv_BB3_11 = 6'd11;
parameter [5:0] LEGUP_F_buf_getv_BB3_12 = 6'd12;
parameter [5:0] LEGUP_F_buf_getv_BB3_13 = 6'd13;
parameter [5:0] LEGUP_F_buf_getv_BB4_14 = 6'd14;
parameter [5:0] LEGUP_F_buf_getv_BB4_15 = 6'd15;
parameter [5:0] LEGUP_F_buf_getv_BB4_16 = 6'd16;
parameter [5:0] LEGUP_F_buf_getv_BB4_17 = 6'd17;
parameter [5:0] LEGUP_F_buf_getv_BB5_18 = 6'd18;
parameter [5:0] LEGUP_F_buf_getv_BB6_19 = 6'd19;
parameter [5:0] LEGUP_F_buf_getv_BB7_20 = 6'd20;
parameter [5:0] LEGUP_F_buf_getv_BB7_21 = 6'd21;
parameter [5:0] LEGUP_F_buf_getv_BB7_22 = 6'd22;
parameter [5:0] LEGUP_F_buf_getv_BB7_23 = 6'd23;
parameter [5:0] LEGUP_F_buf_getv_BB7_24 = 6'd24;
parameter [5:0] LEGUP_F_buf_getv_BB8_25 = 6'd25;
parameter [5:0] LEGUP_F_buf_getv_BB8_26 = 6'd26;
parameter [5:0] LEGUP_F_buf_getv_BB8_27 = 6'd27;
parameter [5:0] LEGUP_F_buf_getv_BB8_28 = 6'd28;
parameter [5:0] LEGUP_F_buf_getv_BB8_29 = 6'd29;
parameter [5:0] LEGUP_F_buf_getv_BB8_30 = 6'd30;
parameter [5:0] LEGUP_F_buf_getv_BB9_31 = 6'd31;
parameter [5:0] LEGUP_F_buf_getv_BB9_32 = 6'd32;
parameter [5:0] LEGUP_F_buf_getv_BB9_33 = 6'd33;
parameter [5:0] LEGUP_F_buf_getv_BB9_34 = 6'd34;
parameter [5:0] LEGUP_F_buf_getv_BB10_35 = 6'd35;
parameter [5:0] LEGUP_F_buf_getv_BB10_36 = 6'd36;
parameter [5:0] LEGUP_F_buf_getv_BB10_37 = 6'd37;
parameter [5:0] LEGUP_F_buf_getv_BB10_38 = 6'd38;
parameter [5:0] LEGUP_F_buf_getv_BB11_39 = 6'd39;
parameter [5:0] LEGUP_F_buf_getv_BB12_40 = 6'd40;
parameter [5:0] LEGUP_F_buf_getv_BB12_41 = 6'd41;
parameter [5:0] LEGUP_F_buf_getv_BB13_42 = 6'd42;
parameter [5:0] LEGUP_F_buf_getv_BB14_43 = 6'd43;
parameter [5:0] LEGUP_F_buf_getv_BB14_44 = 6'd44;
parameter [5:0] LEGUP_F_buf_getv_BB14_45 = 6'd45;
parameter [5:0] LEGUP_F_buf_getv_BB14_46 = 6'd46;
parameter [5:0] LEGUP_F_buf_getv_BB14_47 = 6'd47;
parameter [5:0] LEGUP_F_buf_getv_BB15_48 = 6'd48;
parameter [5:0] LEGUP_F_buf_getv_BB15_49 = 6'd49;
parameter [5:0] LEGUP_F_buf_getv_BB15_50 = 6'd50;
parameter [5:0] LEGUP_F_buf_getv_BB15_51 = 6'd51;
parameter [5:0] LEGUP_F_buf_getv_BB15_52 = 6'd52;
parameter [5:0] LEGUP_F_buf_getv_BB16_53 = 6'd53;
input clk;
input reset;
input start;
output reg finish;
output reg [31:0] return_val;
input [31:0] arg_n;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [5:0] cur_state;
reg [31:0] buf_getv_0_1;
reg [31:0] buf_getv_0_1_reg;
reg [31:0] buf_getv_0_2;
reg [31:0] buf_getv_0_3;
reg [31:0] buf_getv_0_3_reg;
reg [31:0] buf_getv_4_5;
reg [31:0] buf_getv_4_5_reg;
reg [31:0] buf_getv_4_indvar;
reg [31:0] buf_getv_4_indvar_reg;
reg [31:0] buf_getv_4_tmp;
reg [31:0] buf_getv_4_p_0;
reg [31:0] buf_getv_4_p_0_reg;
reg buf_getv_4_6;
reg buf_getv_7_8;
reg buf_getv_7_8_reg;
reg [31:0] buf_getv_7_9;
reg [31:0] buf_getv_7_9_reg;
reg [31:0] buf_getv_10_11;
reg [31:0] buf_getv_10_11_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_10_12;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_10_12_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_10_13;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_10_13_reg;
reg [7:0] buf_getv_10_14;
reg buf_getv_10_15;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_16_17;
reg [7:0] buf_getv_16_18;
reg [7:0] buf_getv_16_18_reg;
reg buf_getv_16_19;
reg [7:0] buf_getv_22_temp_0_in_i;
reg [31:0] buf_getv_22_temp_0_i;
reg [31:0] buf_getv_pgetc_exit__0_i;
reg [31:0] buf_getv_pgetc_exit_23;
reg [31:0] buf_getv_pgetc_exit_24;
reg [31:0] buf_getv_pgetc_exit_25;
reg [31:0] buf_getv_pgetc_exit_25_reg;
reg [31:0] buf_getv_pgetc_exit_26;
reg [31:0] buf_getv_pgetc_exit_26_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_pgetc_exit_27;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_pgetc_exit_27_reg;
reg [31:0] buf_getv_pgetc_exit_28;
reg [31:0] buf_getv_pgetc_exit_29;
reg [31:0] buf_getv_30_31;
reg [31:0] buf_getv_30_31_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_30_32;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_30_32_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_30_33;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_30_33_reg;
reg [7:0] buf_getv_30_34;
reg buf_getv_30_35;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_36_37;
reg [7:0] buf_getv_36_38;
reg [7:0] buf_getv_36_38_reg;
reg buf_getv_36_39;
reg [31:0] buf_getv_40__pre_pre;
reg [31:0] buf_getv_42__pre;
reg [7:0] buf_getv_42_temp_0_in_i1;
reg [31:0] buf_getv_42_temp_0_i2;
reg [31:0] buf_getv_pgetc_exit4_43;
reg [31:0] buf_getv_pgetc_exit4__0_i3;
reg [31:0] buf_getv_pgetc_exit4_44;
reg [31:0] buf_getv_pgetc_exit4_45;
reg [31:0] buf_getv_pgetc_exit4_45_reg;
reg [31:0] buf_getv_pgetc_exit4_indvar_next;
reg [31:0] buf_getv_pgetc_exit4_indvar_next_reg;
reg buf_getv_46_47;
reg [31:0] buf_getv_48_49;
reg [31:0] buf_getv_48_49_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_48_50;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_48_50_reg;
reg [31:0] buf_getv_48_51;
reg [31:0] buf_getv_48_52;
reg [31:0] buf_getv_53_54;
reg [31:0] buf_getv_53_54_reg;
reg [31:0] buf_getv_53_55;
reg [31:0] buf_getv_53_56;
reg [31:0] buf_getv_53_57;
reg [31:0] buf_getv_53_57_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_53_58;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_53_58_reg;
reg [31:0] buf_getv_53_59;
reg [31:0] buf_getv_53_60;
reg [31:0] buf_getv_61__0;
reg [31:0] buf_getv_signed_multiply_32_0_op0;
reg [31:0] buf_getv_signed_multiply_32_0_op1;
reg [31:0] buf_getv_signed_multiply_32_0;
reg [31:0] buf_getv_4_5_phi_temp;
reg [31:0] buf_getv_4_indvar_phi_temp;
reg [7:0] buf_getv_22_temp_0_in_i_phi_temp;
reg [31:0] buf_getv_pgetc_exit__0_i_phi_temp;
reg [31:0] buf_getv_61__0_phi_temp;
reg [31:0] buf_getv_42__pre_phi_temp;
reg [7:0] buf_getv_42_temp_0_in_i1_phi_temp;
reg [31:0] buf_getv_pgetc_exit4_43_phi_temp;
reg [31:0] buf_getv_pgetc_exit4__0_i3_phi_temp;
/* Unsynthesizable Statements */
always @(posedge clk) begin
/* buf_getv: %20*/
/* %21 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str30, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_buf_getv_BB5_18)
begin
$write("Unanticipated marker detected.\n");
end
/* buf_getv: %40*/
/* %41 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str30, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_buf_getv_BB10_35)
begin
$write("Unanticipated marker detected.\n");
end
end
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 6'd0;
if (^reset !== 1'bX && ^(6'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_3 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB1_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB1_4 & memory_controller_waitrequest == 1'd0 & buf_getv_4_6 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB1_4 & memory_controller_waitrequest == 1'd0 & buf_getv_4_6 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB13_42;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB13_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB2_6;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB2_6;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_6 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB2_7;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB2_7;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_7 & memory_controller_waitrequest == 1'd0 & buf_getv_7_8_reg == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_8;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_7 & memory_controller_waitrequest == 1'd0 & buf_getv_7_8_reg == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_25;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_8;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_8 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB3_9;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_9;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_9 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB3_10;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_10;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_10 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB3_11;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_11;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB3_12;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_12;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_12 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_13 & memory_controller_waitrequest == 1'd0 & buf_getv_10_15 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB4_14;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_13 & memory_controller_waitrequest == 1'd0 & buf_getv_10_15 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB4_14;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB4_15;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB4_15;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_15 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB4_16;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB4_16;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_16 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB4_17;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB4_17;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_17 & memory_controller_waitrequest == 1'd0 & buf_getv_16_19 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_20;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_17 & memory_controller_waitrequest == 1'd0 & buf_getv_16_19 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB5_18;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB5_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB5_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB5_18;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB5_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB5_18 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB6_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB6_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB7_20;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_20;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_20 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB7_21;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_21;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_21 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB7_22;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_22;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_22 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_23 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_24 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_25;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_25 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_26;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_26;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_26 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_27;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_27;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_27 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_28;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_28;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_28 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_29;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_29;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_29 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_30;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_30;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_30 & memory_controller_waitrequest == 1'd0 & buf_getv_30_35 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB9_31;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_30 & memory_controller_waitrequest == 1'd0 & buf_getv_30_35 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB9_31;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_32 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB9_33;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB9_33;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB9_34;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB9_34;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_34 & memory_controller_waitrequest == 1'd0 & buf_getv_36_39 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB12_40;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB12_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_34 & memory_controller_waitrequest == 1'd0 & buf_getv_36_39 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB10_35;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB10_35;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_35 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_36 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB10_37;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB10_37;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB10_38;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_38 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB10_38;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_38 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB11_39 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB11_39 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB12_40;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB12_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB12_40 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB12_40;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB12_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB12_40 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB12_41;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB12_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB12_41 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB12_41;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB12_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB12_41 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB13_42 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB13_42;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB13_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB13_42 & memory_controller_waitrequest == 1'd0 & buf_getv_46_47 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB13_42 & memory_controller_waitrequest == 1'd0 & buf_getv_46_47 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_43 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_43 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_44 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_44 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_45 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_45 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB14_46;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_46 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_46;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_46 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB14_47;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_47 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_47;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_47 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_48 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_48 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB15_49;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_49 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB15_49;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_49 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB15_50;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_50 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB15_50;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_50 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB15_51;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_51 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB15_51;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_51 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB15_52;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_52 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB15_52;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_52 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB16_53 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB16_53 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* buf_getv: %0*/
/* %1 = add nsw i32 %n, -1*/
begin
buf_getv_0_1 = arg_n + -32'd1;
end
end
always @(posedge clk) begin
/* buf_getv: %0*/
/* %1 = add nsw i32 %n, -1*/
if (cur_state == LEGUP_F_buf_getv_BB0_1)
begin
buf_getv_0_1_reg <= buf_getv_0_1;
if (^reset !== 1'bX && ^(buf_getv_0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_0_1_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %0*/
/* %2 = load i32* @read_position, align 4, !tbaa !0*/
begin
buf_getv_0_2 = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %0*/
/* %3 = sub nsw i32 %1, %2*/
begin
buf_getv_0_3 = buf_getv_0_1_reg - buf_getv_0_2;
end
end
always @(posedge clk) begin
/* buf_getv: %0*/
/* %3 = sub nsw i32 %1, %2*/
if (cur_state == LEGUP_F_buf_getv_BB0_3)
begin
buf_getv_0_3_reg <= buf_getv_0_3;
if (^reset !== 1'bX && ^(buf_getv_0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_0_3_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5 = buf_getv_4_5_phi_temp;
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
else if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5 = buf_getv_4_5_phi_temp;
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
else if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5 = buf_getv_4_5_phi_temp;
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
else /* if (cur_state == LEGUP_F_buf_getv_BB1_4) */
begin
buf_getv_4_5 = buf_getv_4_5_phi_temp;
end
end
always @(posedge clk) begin
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5_reg <= buf_getv_4_5;
if (^reset !== 1'bX && ^(buf_getv_4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_reg"); $finish; end
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5_reg <= buf_getv_4_5;
if (^reset !== 1'bX && ^(buf_getv_4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_reg"); $finish; end
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5_reg <= buf_getv_4_5;
if (^reset !== 1'bX && ^(buf_getv_4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_reg"); $finish; end
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5_reg <= buf_getv_4_5;
if (^reset !== 1'bX && ^(buf_getv_4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_reg"); $finish; end
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5_reg <= buf_getv_4_5;
if (^reset !== 1'bX && ^(buf_getv_4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_indvar = buf_getv_4_indvar_phi_temp;
end
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
else /* if (cur_state == LEGUP_F_buf_getv_BB1_4) */
begin
buf_getv_4_indvar = buf_getv_4_indvar_phi_temp;
end
end
always @(posedge clk) begin
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_indvar_reg <= buf_getv_4_indvar;
if (^reset !== 1'bX && ^(buf_getv_4_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_indvar_reg"); $finish; end
end
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_indvar_reg <= buf_getv_4_indvar;
if (^reset !== 1'bX && ^(buf_getv_4_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_indvar_reg"); $finish; end
end
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_indvar_reg <= buf_getv_4_indvar;
if (^reset !== 1'bX && ^(buf_getv_4_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_indvar_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %4*/
/* %tmp = mul i32 %indvar, -8*/
begin
buf_getv_4_tmp = buf_getv_signed_multiply_32_0;
end
end
always @(*) begin
/* buf_getv: %4*/
/* %p.0 = add i32 %3, %tmp*/
begin
buf_getv_4_p_0 = buf_getv_0_3_reg + buf_getv_4_tmp;
end
end
always @(posedge clk) begin
/* buf_getv: %4*/
/* %p.0 = add i32 %3, %tmp*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_p_0_reg <= buf_getv_4_p_0;
if (^reset !== 1'bX && ^(buf_getv_4_p_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_p_0_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %4*/
/* %6 = icmp sgt i32 %p.0, 0*/
begin
buf_getv_4_6 = $signed(buf_getv_4_p_0) > $signed(32'd0);
end
end
always @(*) begin
/* buf_getv: %7*/
/* %8 = icmp sgt i32 %5, 23*/
begin
buf_getv_7_8 = $signed(buf_getv_4_5_reg) > $signed(32'd23);
end
end
always @(posedge clk) begin
/* buf_getv: %7*/
/* %8 = icmp sgt i32 %5, 23*/
if (cur_state == LEGUP_F_buf_getv_BB2_5)
begin
buf_getv_7_8_reg <= buf_getv_7_8;
if (^reset !== 1'bX && ^(buf_getv_7_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_7_8_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
begin
buf_getv_7_9 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB2_7)
begin
buf_getv_7_9_reg <= buf_getv_7_9;
if (^reset !== 1'bX && ^(buf_getv_7_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_7_9_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %10*/
/* %11 = shl i32 %9, %p.0*/
begin
buf_getv_10_11 = buf_getv_7_9_reg <<< buf_getv_4_p_0_reg % 32;
end
end
always @(posedge clk) begin
/* buf_getv: %10*/
/* %11 = shl i32 %9, %p.0*/
if (cur_state == LEGUP_F_buf_getv_BB3_8)
begin
buf_getv_10_11_reg <= buf_getv_10_11;
if (^reset !== 1'bX && ^(buf_getv_10_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_10_11_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
begin
buf_getv_10_12 = memory_controller_out[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
end
always @(posedge clk) begin
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
buf_getv_10_12_reg <= buf_getv_10_12;
if (^reset !== 1'bX && ^(buf_getv_10_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_10_12_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %10*/
/* %13 = getelementptr inbounds i8* %12, i32 1*/
begin
buf_getv_10_13 = buf_getv_10_12 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* buf_getv: %10*/
/* %13 = getelementptr inbounds i8* %12, i32 1*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
buf_getv_10_13_reg <= buf_getv_10_13;
if (^reset !== 1'bX && ^(buf_getv_10_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_10_13_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %10*/
/* %14 = load i8* %12, align 1, !tbaa !1*/
begin
buf_getv_10_14 = memory_controller_out[7:0];
end
end
always @(*) begin
/* buf_getv: %10*/
/* %15 = icmp eq i8 %14, -1*/
begin
buf_getv_10_15 = buf_getv_10_14 == -8'd1;
end
end
always @(*) begin
/* buf_getv: %16*/
/* %17 = getelementptr inbounds i8* %12, i32 2*/
begin
buf_getv_16_17 = buf_getv_10_12_reg + 1 * 32'd2;
end
end
always @(*) begin
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
begin
buf_getv_16_18 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB4_17)
begin
buf_getv_16_18_reg <= buf_getv_16_18;
if (^reset !== 1'bX && ^(buf_getv_16_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_16_18_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %16*/
/* %19 = icmp eq i8 %18, 0*/
begin
buf_getv_16_19 = buf_getv_16_18 == 8'd0;
end
end
always @(*) begin
/* buf_getv: %22*/
/* %temp.0.in.i = phi i8 [ %18, %20 ], [ %14, %10 ]*/
begin
buf_getv_22_temp_0_in_i = buf_getv_22_temp_0_in_i_phi_temp;
end
end
always @(*) begin
/* buf_getv: %22*/
/* %temp.0.i = zext i8 %temp.0.in.i to i32*/
begin
buf_getv_22_temp_0_i = buf_getv_22_temp_0_in_i;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %.0.i = phi i32 [ %temp.0.i, %22 ], [ 255, %16 ]*/
begin
buf_getv_pgetc_exit__0_i = buf_getv_pgetc_exit__0_i_phi_temp;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %23 = sub nsw i32 8, %p.0*/
begin
buf_getv_pgetc_exit_23 = 32'd8 - buf_getv_4_p_0_reg;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %24 = lshr i32 %.0.i, %23*/
begin
buf_getv_pgetc_exit_24 = buf_getv_pgetc_exit__0_i >>> buf_getv_pgetc_exit_23 % 32;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %25 = or i32 %24, %11*/
begin
buf_getv_pgetc_exit_25 = buf_getv_pgetc_exit_24 | buf_getv_10_11_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit*/
/* %25 = or i32 %24, %11*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
buf_getv_pgetc_exit_25_reg <= buf_getv_pgetc_exit_25;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit_25_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %26 = sub nsw i32 7, %p.0*/
begin
buf_getv_pgetc_exit_26 = 32'd7 - buf_getv_4_p_0_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit*/
/* %26 = sub nsw i32 7, %p.0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
buf_getv_pgetc_exit_26_reg <= buf_getv_pgetc_exit_26;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit_26_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %27 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
begin
buf_getv_pgetc_exit_27 = `TAG_g_lmask_a + 4 * buf_getv_0_1_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit*/
/* %27 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
buf_getv_pgetc_exit_27_reg <= buf_getv_pgetc_exit_27;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit_27_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %28 = load i32* %27, align 4, !tbaa !0*/
begin
buf_getv_pgetc_exit_28 = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %29 = and i32 %25, %28*/
begin
buf_getv_pgetc_exit_29 = buf_getv_pgetc_exit_25_reg & buf_getv_pgetc_exit_28;
end
end
always @(*) begin
/* buf_getv: %30*/
/* %31 = shl i32 %9, 8*/
begin
buf_getv_30_31 = buf_getv_7_9_reg <<< 32'd8 % 32;
end
end
always @(posedge clk) begin
/* buf_getv: %30*/
/* %31 = shl i32 %9, 8*/
if (cur_state == LEGUP_F_buf_getv_BB8_25)
begin
buf_getv_30_31_reg <= buf_getv_30_31;
if (^reset !== 1'bX && ^(buf_getv_30_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_30_31_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
begin
buf_getv_30_32 = memory_controller_out[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
end
always @(posedge clk) begin
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
buf_getv_30_32_reg <= buf_getv_30_32;
if (^reset !== 1'bX && ^(buf_getv_30_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_30_32_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %30*/
/* %33 = getelementptr inbounds i8* %32, i32 1*/
begin
buf_getv_30_33 = buf_getv_30_32 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* buf_getv: %30*/
/* %33 = getelementptr inbounds i8* %32, i32 1*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
buf_getv_30_33_reg <= buf_getv_30_33;
if (^reset !== 1'bX && ^(buf_getv_30_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_30_33_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %30*/
/* %34 = load i8* %32, align 1, !tbaa !1*/
begin
buf_getv_30_34 = memory_controller_out[7:0];
end
end
always @(*) begin
/* buf_getv: %30*/
/* %35 = icmp eq i8 %34, -1*/
begin
buf_getv_30_35 = buf_getv_30_34 == -8'd1;
end
end
always @(*) begin
/* buf_getv: %36*/
/* %37 = getelementptr inbounds i8* %32, i32 2*/
begin
buf_getv_36_37 = buf_getv_30_32_reg + 1 * 32'd2;
end
end
always @(*) begin
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
begin
buf_getv_36_38 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB9_34)
begin
buf_getv_36_38_reg <= buf_getv_36_38;
if (^reset !== 1'bX && ^(buf_getv_36_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_36_38_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %36*/
/* %39 = icmp eq i8 %38, 0*/
begin
buf_getv_36_39 = buf_getv_36_38 == 8'd0;
end
end
always @(*) begin
/* buf_getv: %40*/
/* %.pre.pre = load i32* @read_position, align 4, !tbaa !0*/
begin
buf_getv_40__pre_pre = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %42*/
/* %.pre = phi i32 [ %.pre.pre, %40 ], [ %5, %30 ]*/
begin
buf_getv_42__pre = buf_getv_42__pre_phi_temp;
end
end
always @(*) begin
/* buf_getv: %42*/
/* %temp.0.in.i1 = phi i8 [ %38, %40 ], [ %34, %30 ]*/
begin
buf_getv_42_temp_0_in_i1 = buf_getv_42_temp_0_in_i1_phi_temp;
end
end
always @(*) begin
/* buf_getv: %42*/
/* %temp.0.i2 = zext i8 %temp.0.in.i1 to i32*/
begin
buf_getv_42_temp_0_i2 = buf_getv_42_temp_0_in_i1;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit4*/
/* %43 = phi i32 [ %.pre, %42 ], [ %5, %36 ]*/
begin
buf_getv_pgetc_exit4_43 = buf_getv_pgetc_exit4_43_phi_temp;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit4*/
/* %.0.i3 = phi i32 [ %temp.0.i2, %42 ], [ 255, %36 ]*/
begin
buf_getv_pgetc_exit4__0_i3 = buf_getv_pgetc_exit4__0_i3_phi_temp;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit4*/
/* %44 = or i32 %.0.i3, %31*/
begin
buf_getv_pgetc_exit4_44 = buf_getv_pgetc_exit4__0_i3 | buf_getv_30_31_reg;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit4*/
/* %45 = add nsw i32 %43, 8*/
begin
buf_getv_pgetc_exit4_45 = buf_getv_pgetc_exit4_43 + 32'd8;
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit4*/
/* %45 = add nsw i32 %43, 8*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
buf_getv_pgetc_exit4_45_reg <= buf_getv_pgetc_exit4_45;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit4_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4_45_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %pgetc.exit4*/
/* %indvar.next = add i32 %indvar, 1*/
begin
buf_getv_pgetc_exit4_indvar_next = buf_getv_4_indvar_reg + 32'd1;
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit4*/
/* %indvar.next = add i32 %indvar, 1*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
buf_getv_pgetc_exit4_indvar_next_reg <= buf_getv_pgetc_exit4_indvar_next;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit4_indvar_next) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4_indvar_next_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %46*/
/* %47 = icmp eq i32 %p.0, 0*/
begin
buf_getv_46_47 = buf_getv_4_p_0_reg == 32'd0;
end
end
always @(*) begin
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
begin
buf_getv_48_49 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_46)
begin
buf_getv_48_49_reg <= buf_getv_48_49;
if (^reset !== 1'bX && ^(buf_getv_48_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_48_49_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %48*/
/* %50 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
begin
buf_getv_48_50 = `TAG_g_lmask_a + 4 * buf_getv_0_1_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %48*/
/* %50 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
buf_getv_48_50_reg <= buf_getv_48_50;
if (^reset !== 1'bX && ^(buf_getv_48_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_48_50_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %48*/
/* %51 = load i32* %50, align 4, !tbaa !0*/
begin
buf_getv_48_51 = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %48*/
/* %52 = and i32 %51, %49*/
begin
buf_getv_48_52 = buf_getv_48_51 & buf_getv_48_49_reg;
end
end
always @(*) begin
/* buf_getv: %53*/
/* %54 = sub nsw i32 0, %p.0*/
begin
buf_getv_53_54 = 32'd0 - buf_getv_4_p_0_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %53*/
/* %54 = sub nsw i32 0, %p.0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
buf_getv_53_54_reg <= buf_getv_53_54;
if (^reset !== 1'bX && ^(buf_getv_53_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_53_54_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %53*/
/* %55 = xor i32 %p.0, -1*/
begin
buf_getv_53_55 = buf_getv_4_p_0_reg ^ -32'd1;
end
end
always @(*) begin
/* buf_getv: %53*/
/* %56 = load i32* @current_read_byte, align 4, !tbaa !0*/
begin
buf_getv_53_56 = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %53*/
/* %57 = lshr i32 %56, %54*/
begin
buf_getv_53_57 = buf_getv_53_56 >>> buf_getv_53_54_reg % 32;
end
end
always @(posedge clk) begin
/* buf_getv: %53*/
/* %57 = lshr i32 %56, %54*/
if (cur_state == LEGUP_F_buf_getv_BB15_51)
begin
buf_getv_53_57_reg <= buf_getv_53_57;
if (^reset !== 1'bX && ^(buf_getv_53_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_53_57_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %53*/
/* %58 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
begin
buf_getv_53_58 = `TAG_g_lmask_a + 4 * buf_getv_0_1_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %53*/
/* %58 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
buf_getv_53_58_reg <= buf_getv_53_58;
if (^reset !== 1'bX && ^(buf_getv_53_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_53_58_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %53*/
/* %59 = load i32* %58, align 4, !tbaa !0*/
begin
buf_getv_53_59 = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %53*/
/* %60 = and i32 %57, %59*/
begin
buf_getv_53_60 = buf_getv_53_57_reg & buf_getv_53_59;
end
end
always @(*) begin
/* buf_getv: %61*/
/* %.0 = phi i32 [ %29, %pgetc.exit ], [ %60, %53 ], [ %52, %48 ]*/
begin
buf_getv_61__0 = buf_getv_61__0_phi_temp;
end
end
always @(*) begin
/* buf_getv: %4*/
/* %tmp = mul i32 %indvar, -8*/
begin
buf_getv_signed_multiply_32_0_op0 = buf_getv_4_indvar;
end
end
always @(*) begin
/* buf_getv: %4*/
/* %tmp = mul i32 %indvar, -8*/
if (reset) begin buf_getv_signed_multiply_32_0_op1 = 0; end
begin
buf_getv_signed_multiply_32_0_op1 = -32'd8;
end
end
always @(*) begin
buf_getv_signed_multiply_32_0 = buf_getv_signed_multiply_32_0_op0 * buf_getv_signed_multiply_32_0_op1;
end
always @(posedge clk) begin
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB0_3 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_4_5_phi_temp <= buf_getv_0_2;
if (^reset !== 1'bX && ^(buf_getv_0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_phi_temp"); $finish; end
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB12_41 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_4_5_phi_temp <= buf_getv_pgetc_exit4_45_reg;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit4_45_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB0_3 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_4_indvar_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_indvar_phi_temp"); $finish; end
end
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB12_41 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_4_indvar_phi_temp <= buf_getv_pgetc_exit4_indvar_next_reg;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit4_indvar_next_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_indvar_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %22*/
/* %temp.0.in.i = phi i8 [ %18, %20 ], [ %14, %10 ]*/
if (cur_state == LEGUP_F_buf_getv_BB3_13 & memory_controller_waitrequest == 1'd0 & buf_getv_10_15 == 1'd0)
begin
buf_getv_22_temp_0_in_i_phi_temp <= buf_getv_10_14;
if (^reset !== 1'bX && ^(buf_getv_10_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_22_temp_0_in_i_phi_temp"); $finish; end
end
/* buf_getv: %22*/
/* %temp.0.in.i = phi i8 [ %18, %20 ], [ %14, %10 ]*/
if (cur_state == LEGUP_F_buf_getv_BB5_18 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_22_temp_0_in_i_phi_temp <= buf_getv_16_18_reg;
if (^reset !== 1'bX && ^(buf_getv_16_18_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_22_temp_0_in_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit*/
/* %.0.i = phi i32 [ %temp.0.i, %22 ], [ 255, %16 ]*/
if (cur_state == LEGUP_F_buf_getv_BB4_17 & memory_controller_waitrequest == 1'd0 & buf_getv_16_19 == 1'd1)
begin
buf_getv_pgetc_exit__0_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit__0_i_phi_temp"); $finish; end
end
/* buf_getv: %pgetc.exit*/
/* %.0.i = phi i32 [ %temp.0.i, %22 ], [ 255, %16 ]*/
if (cur_state == LEGUP_F_buf_getv_BB6_19 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_pgetc_exit__0_i_phi_temp <= buf_getv_22_temp_0_i;
if (^reset !== 1'bX && ^(buf_getv_22_temp_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit__0_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %61*/
/* %.0 = phi i32 [ %29, %pgetc.exit ], [ %60, %53 ], [ %52, %48 ]*/
if (cur_state == LEGUP_F_buf_getv_BB7_24 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_61__0_phi_temp <= buf_getv_pgetc_exit_29;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_61__0_phi_temp"); $finish; end
end
/* buf_getv: %61*/
/* %.0 = phi i32 [ %29, %pgetc.exit ], [ %60, %53 ], [ %52, %48 ]*/
if (cur_state == LEGUP_F_buf_getv_BB14_47 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_61__0_phi_temp <= buf_getv_48_52;
if (^reset !== 1'bX && ^(buf_getv_48_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_61__0_phi_temp"); $finish; end
end
/* buf_getv: %61*/
/* %.0 = phi i32 [ %29, %pgetc.exit ], [ %60, %53 ], [ %52, %48 ]*/
if (cur_state == LEGUP_F_buf_getv_BB15_52 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_61__0_phi_temp <= buf_getv_53_60;
if (^reset !== 1'bX && ^(buf_getv_53_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_61__0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %42*/
/* %.pre = phi i32 [ %.pre.pre, %40 ], [ %5, %30 ]*/
if (cur_state == LEGUP_F_buf_getv_BB8_30 & memory_controller_waitrequest == 1'd0 & buf_getv_30_35 == 1'd0)
begin
buf_getv_42__pre_phi_temp <= buf_getv_4_5_reg;
if (^reset !== 1'bX && ^(buf_getv_4_5_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_42__pre_phi_temp"); $finish; end
end
/* buf_getv: %42*/
/* %.pre = phi i32 [ %.pre.pre, %40 ], [ %5, %30 ]*/
if (cur_state == LEGUP_F_buf_getv_BB10_38 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_42__pre_phi_temp <= buf_getv_40__pre_pre;
if (^reset !== 1'bX && ^(buf_getv_40__pre_pre) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_42__pre_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %42*/
/* %temp.0.in.i1 = phi i8 [ %38, %40 ], [ %34, %30 ]*/
if (cur_state == LEGUP_F_buf_getv_BB8_30 & memory_controller_waitrequest == 1'd0 & buf_getv_30_35 == 1'd0)
begin
buf_getv_42_temp_0_in_i1_phi_temp <= buf_getv_30_34;
if (^reset !== 1'bX && ^(buf_getv_30_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_42_temp_0_in_i1_phi_temp"); $finish; end
end
/* buf_getv: %42*/
/* %temp.0.in.i1 = phi i8 [ %38, %40 ], [ %34, %30 ]*/
if (cur_state == LEGUP_F_buf_getv_BB10_38 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_42_temp_0_in_i1_phi_temp <= buf_getv_36_38_reg;
if (^reset !== 1'bX && ^(buf_getv_36_38_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_42_temp_0_in_i1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit4*/
/* %43 = phi i32 [ %.pre, %42 ], [ %5, %36 ]*/
if (cur_state == LEGUP_F_buf_getv_BB9_34 & memory_controller_waitrequest == 1'd0 & buf_getv_36_39 == 1'd1)
begin
buf_getv_pgetc_exit4_43_phi_temp <= buf_getv_4_5_reg;
if (^reset !== 1'bX && ^(buf_getv_4_5_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4_43_phi_temp"); $finish; end
end
/* buf_getv: %pgetc.exit4*/
/* %43 = phi i32 [ %.pre, %42 ], [ %5, %36 ]*/
if (cur_state == LEGUP_F_buf_getv_BB11_39 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_pgetc_exit4_43_phi_temp <= buf_getv_42__pre;
if (^reset !== 1'bX && ^(buf_getv_42__pre) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4_43_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit4*/
/* %.0.i3 = phi i32 [ %temp.0.i2, %42 ], [ 255, %36 ]*/
if (cur_state == LEGUP_F_buf_getv_BB9_34 & memory_controller_waitrequest == 1'd0 & buf_getv_36_39 == 1'd1)
begin
buf_getv_pgetc_exit4__0_i3_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4__0_i3_phi_temp"); $finish; end
end
/* buf_getv: %pgetc.exit4*/
/* %.0.i3 = phi i32 [ %temp.0.i2, %42 ], [ 255, %36 ]*/
if (cur_state == LEGUP_F_buf_getv_BB11_39 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_pgetc_exit4__0_i3_phi_temp <= buf_getv_42_temp_0_i2;
if (^reset !== 1'bX && ^(buf_getv_42_temp_0_i2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4__0_i3_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* buf_getv: %61*/
/* ret i32 %.0*/
if (cur_state == LEGUP_F_buf_getv_BB16_53)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
return_val <= 0;
if (^reset !== 1'bX && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
/* buf_getv: %61*/
/* ret i32 %.0*/
if (cur_state == LEGUP_F_buf_getv_BB16_53)
begin
return_val <= buf_getv_61__0;
if (^reset !== 1'bX && ^(buf_getv_61__0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* buf_getv: %0*/
/* %2 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB0_1)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB2_5)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_8)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %10*/
/* store i8* %13, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %10*/
/* %14 = load i8* %12, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB3_11)
begin
memory_controller_address = buf_getv_10_12_reg;
end
/* buf_getv: %16*/
/* store i8* %17, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB4_14)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB4_15)
begin
memory_controller_address = buf_getv_10_13_reg;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %.0.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %26, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_21)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %pgetc.exit*/
/* %28 = load i32* %27, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_22)
begin
memory_controller_address = buf_getv_pgetc_exit_27_reg;
end
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_25)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %30*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %30*/
/* %34 = load i8* %32, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB8_28)
begin
memory_controller_address = buf_getv_30_32_reg;
end
/* buf_getv: %36*/
/* store i8* %37, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB9_31)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB9_32)
begin
memory_controller_address = buf_getv_30_33_reg;
end
/* buf_getv: %40*/
/* %.pre.pre = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB10_36)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %44, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %45, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_41)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %48*/
/* store i32 -1, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_44)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* buf_getv: %48*/
/* %51 = load i32* %50, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_45)
begin
memory_controller_address = buf_getv_48_50_reg;
end
/* buf_getv: %53*/
/* store i32 %55, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %53*/
/* %56 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_49)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* buf_getv: %53*/
/* %59 = load i32* %58, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_50)
begin
memory_controller_address = buf_getv_53_58_reg;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* buf_getv: %0*/
/* %2 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB0_1)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB2_5)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_8)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %10*/
/* store i8* %13, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %10*/
/* %14 = load i8* %12, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB3_11)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %16*/
/* store i8* %17, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB4_14)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB4_15)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %.0.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %26, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_21)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %pgetc.exit*/
/* %28 = load i32* %27, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_22)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_25)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %30*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %30*/
/* %34 = load i8* %32, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB8_28)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %36*/
/* store i8* %37, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB9_31)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB9_32)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %40*/
/* %.pre.pre = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB10_36)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %44, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %45, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_41)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %48*/
/* store i32 -1, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_44)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %48*/
/* %51 = load i32* %50, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_45)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %53*/
/* store i32 %55, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %53*/
/* %56 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_49)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %53*/
/* %59 = load i32* %58, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_50)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %0*/
/* %2 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB0_1)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB2_5)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_8)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %10*/
/* store i8* %13, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %10*/
/* %14 = load i8* %12, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB3_11)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %16*/
/* store i8* %17, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB4_14)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB4_15)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %.0.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %26, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_21)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %pgetc.exit*/
/* %28 = load i32* %27, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_22)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_25)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %30*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %30*/
/* %34 = load i8* %32, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB8_28)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %36*/
/* store i8* %37, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB9_31)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB9_32)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %40*/
/* %.pre.pre = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB10_36)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %44, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %45, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_41)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %48*/
/* store i32 -1, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_44)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %48*/
/* %51 = load i32* %50, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_45)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %53*/
/* store i32 %55, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %53*/
/* %56 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_49)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %53*/
/* %59 = load i32* %58, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_50)
begin
memory_controller_write_enable = 1'd0;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* buf_getv: %10*/
/* store i8* %13, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
memory_controller_in = buf_getv_10_13;
end
/* buf_getv: %16*/
/* store i8* %17, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB4_14)
begin
memory_controller_in = buf_getv_16_17;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %.0.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
memory_controller_in = buf_getv_pgetc_exit__0_i;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %26, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_21)
begin
memory_controller_in = buf_getv_pgetc_exit_26_reg;
end
/* buf_getv: %30*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
memory_controller_in = buf_getv_30_33;
end
/* buf_getv: %36*/
/* store i8* %37, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB9_31)
begin
memory_controller_in = buf_getv_36_37;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %44, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
memory_controller_in = buf_getv_pgetc_exit4_44;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %45, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_41)
begin
memory_controller_in = buf_getv_pgetc_exit4_45_reg;
end
/* buf_getv: %48*/
/* store i32 -1, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
memory_controller_in = -32'd1;
end
/* buf_getv: %53*/
/* store i32 %55, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
memory_controller_in = buf_getv_53_55;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* buf_getv: %0*/
/* %2 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB0_1)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB2_5)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_8)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %10*/
/* store i8* %13, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %10*/
/* %14 = load i8* %12, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB3_11)
begin
memory_controller_size = 2'd0;
end
/* buf_getv: %16*/
/* store i8* %17, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB4_14)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB4_15)
begin
memory_controller_size = 2'd0;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %.0.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %26, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_21)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %pgetc.exit*/
/* %28 = load i32* %27, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_22)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_25)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %30*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %30*/
/* %34 = load i8* %32, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB8_28)
begin
memory_controller_size = 2'd0;
end
/* buf_getv: %36*/
/* store i8* %37, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB9_31)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB9_32)
begin
memory_controller_size = 2'd0;
end
/* buf_getv: %40*/
/* %.pre.pre = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB10_36)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %44, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %45, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_41)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %48*/
/* store i32 -1, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_44)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %48*/
/* %51 = load i32* %50, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_45)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %53*/
/* store i32 %55, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %53*/
/* %56 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_49)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %53*/
/* %59 = load i32* %58, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_50)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module huff_make_dhuff_tb
(
clk,
reset,
start,
finish,
return_val,
arg_p_xhtbl_bits,
arg_p_dhtbl_maxcode,
arg_p_dhtbl_mincode,
arg_p_dhtbl_valptr,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [5:0] LEGUP_0 = 6'd0;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB0_1 = 6'd1;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB1_2 = 6'd2;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB1_3 = 6'd3;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB1_4 = 6'd4;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB2_5 = 6'd5;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB3_6 = 6'd6;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB4_7 = 6'd7;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB5_8 = 6'd8;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB6_9 = 6'd9;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB6_10 = 6'd10;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB6_11 = 6'd11;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB6_12 = 6'd12;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB7_13 = 6'd13;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB8_14 = 6'd14;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB8_15 = 6'd15;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB8_16 = 6'd16;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB8_17 = 6'd17;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB9_18 = 6'd18;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB10_19 = 6'd19;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB11_20 = 6'd20;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB12_21 = 6'd21;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB12_22 = 6'd22;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB12_23 = 6'd23;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB13_24 = 6'd24;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_25 = 6'd25;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_26 = 6'd26;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_27 = 6'd27;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_28 = 6'd28;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_29 = 6'd29;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_30 = 6'd30;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_31 = 6'd31;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_32 = 6'd32;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_33 = 6'd33;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB15_34 = 6'd34;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB16_35 = 6'd35;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB16_36 = 6'd36;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB16_37 = 6'd37;
input clk;
input reset;
input start;
output reg finish;
output reg [31:0] return_val;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_xhtbl_bits;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_dhtbl_maxcode;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_dhtbl_mincode;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_dhtbl_valptr;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [5:0] cur_state;
reg [31:0] huff_make_dhuff_tb__preheader10_indvar44;
reg [31:0] huff_make_dhuff_tb__preheader10_p_013;
reg [31:0] huff_make_dhuff_tb__preheader10_p_013_reg;
reg [31:0] huff_make_dhuff_tb__preheader10_i_014;
reg [31:0] huff_make_dhuff_tb__preheader10_i_014_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb__preheader10_scevgep48;
reg [31:0] huff_make_dhuff_tb__preheader10_1;
reg [31:0] huff_make_dhuff_tb__preheader10_1_reg;
reg huff_make_dhuff_tb__preheader10_2;
reg huff_make_dhuff_tb__lr_ph_tmp37;
reg [31:0] huff_make_dhuff_tb__lr_ph_smax;
reg [31:0] huff_make_dhuff_tb__lr_ph_smax_reg;
reg [31:0] huff_make_dhuff_tb_3_indvar39;
reg [31:0] huff_make_dhuff_tb_3_tmp42;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_3_scevgep43;
reg [31:0] huff_make_dhuff_tb_3_indvar_next40;
reg huff_make_dhuff_tb_3_exitcond41;
reg [31:0] huff_make_dhuff_tb___crit_edge_tmp38;
reg [31:0] huff_make_dhuff_tb_4_p_1_lcssa;
reg [31:0] huff_make_dhuff_tb_4_p_1_lcssa_reg;
reg huff_make_dhuff_tb_4_exitcond46;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_5_6;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_5_7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_5_7_reg;
reg [31:0] huff_make_dhuff_tb_5_8;
reg [31:0] huff_make_dhuff_tb__outer_p_2_ph;
reg [31:0] huff_make_dhuff_tb__outer_p_2_ph_reg;
reg [31:0] huff_make_dhuff_tb__outer_code_0_ph;
reg [31:0] huff_make_dhuff_tb__outer_code_0_ph_reg;
reg [31:0] huff_make_dhuff_tb__outer_size_0_ph;
reg [31:0] huff_make_dhuff_tb__outer_size_0_ph_reg;
reg [31:0] huff_make_dhuff_tb__outer_tmp28;
reg [31:0] huff_make_dhuff_tb__outer_tmp28_reg;
reg [31:0] huff_make_dhuff_tb__outer_tmp3349;
reg [31:0] huff_make_dhuff_tb__outer_tmp3349_reg;
reg [31:0] huff_make_dhuff_tb_9_indvar26;
reg [31:0] huff_make_dhuff_tb_9_indvar26_reg;
reg [31:0] huff_make_dhuff_tb_9_tmp29;
reg [31:0] huff_make_dhuff_tb_9_tmp29_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_9_scevgep30;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_9_scevgep30_reg;
reg [31:0] huff_make_dhuff_tb_9_tmp31;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_9_scevgep32;
reg [31:0] huff_make_dhuff_tb_9_code_0;
reg [31:0] huff_make_dhuff_tb_9_10;
reg [31:0] huff_make_dhuff_tb_9_10_reg;
reg huff_make_dhuff_tb_9_11;
reg huff_make_dhuff_tb_9_12;
reg huff_make_dhuff_tb_9_12_reg;
reg huff_make_dhuff_tb_9_or_cond;
reg [31:0] huff_make_dhuff_tb_9_indvar_next27;
reg [31:0] huff_make_dhuff_tb_9_indvar_next27_reg;
reg huff_make_dhuff_tb__critedge_13;
reg [31:0] huff_make_dhuff_tb__preheader4_tmp34;
reg [31:0] huff_make_dhuff_tb__preheader4_tmp;
reg [31:0] huff_make_dhuff_tb__preheader4_tmp_reg;
reg [31:0] huff_make_dhuff_tb_14_indvar19;
reg [31:0] huff_make_dhuff_tb_14_code_1;
reg [31:0] huff_make_dhuff_tb_14_15;
reg [31:0] huff_make_dhuff_tb_14_indvar_next20;
reg huff_make_dhuff_tb_14_exitcond21;
reg [31:0] huff_make_dhuff_tb__preheader_indvar;
reg [31:0] huff_make_dhuff_tb__preheader_p_dhtbl_ml_03;
reg [31:0] huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg;
reg [31:0] huff_make_dhuff_tb__preheader_p_31;
reg [31:0] huff_make_dhuff_tb__preheader_p_31_reg;
reg [31:0] huff_make_dhuff_tb__preheader_l_02;
reg [31:0] huff_make_dhuff_tb__preheader_l_02_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb__preheader_scevgep;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb__preheader_scevgep_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb__preheader_scevgep15;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb__preheader_scevgep15_reg;
reg [31:0] huff_make_dhuff_tb__preheader_16;
reg huff_make_dhuff_tb__preheader_17;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_scevgep17;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_scevgep17_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_scevgep16;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_20;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_20_reg;
reg [31:0] huff_make_dhuff_tb_19_21;
reg [31:0] huff_make_dhuff_tb_19_22;
reg [31:0] huff_make_dhuff_tb_19_23;
reg [31:0] huff_make_dhuff_tb_19_23_reg;
reg [31:0] huff_make_dhuff_tb_19_24;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_25;
reg [31:0] huff_make_dhuff_tb_19_26;
reg [31:0] huff_make_dhuff_tb_19_27;
reg [31:0] huff_make_dhuff_tb_19_27_reg;
reg [31:0] huff_make_dhuff_tb_28_p_4;
reg [31:0] huff_make_dhuff_tb_28_p_dhtbl_ml_1;
reg [31:0] huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg;
reg huff_make_dhuff_tb_28_exitcond;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_29_30;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_29_30_reg;
reg [31:0] huff_make_dhuff_tb_29_31;
reg [31:0] huff_make_dhuff_tb_29_32;
reg [31:0] huff_make_dhuff_tb__preheader10_indvar44_phi_temp;
reg [31:0] huff_make_dhuff_tb__preheader10_p_013_phi_temp;
reg [31:0] huff_make_dhuff_tb_4_p_1_lcssa_phi_temp;
reg [31:0] huff_make_dhuff_tb_3_indvar39_phi_temp;
reg [31:0] huff_make_dhuff_tb__outer_p_2_ph_phi_temp;
reg [31:0] huff_make_dhuff_tb__outer_code_0_ph_phi_temp;
reg [31:0] huff_make_dhuff_tb__outer_size_0_ph_phi_temp;
reg [31:0] huff_make_dhuff_tb_9_indvar26_phi_temp;
reg [31:0] huff_make_dhuff_tb__preheader_indvar_phi_temp;
reg [31:0] huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp;
reg [31:0] huff_make_dhuff_tb__preheader_p_31_phi_temp;
reg [31:0] huff_make_dhuff_tb_14_indvar19_phi_temp;
reg [31:0] huff_make_dhuff_tb_14_code_1_phi_temp;
reg [31:0] huff_make_dhuff_tb_28_p_4_phi_temp;
reg [31:0] huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp;
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 6'd0;
if (^reset !== 1'bX && ^(6'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_3;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_3;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_3 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_4 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__preheader10_2 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_4 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__preheader10_2 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB2_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_3_exitcond41 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB4_7;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB4_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_3_exitcond41 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB4_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB4_7;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB4_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_4_exitcond46 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_4_exitcond46 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_10;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_10;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_11;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_11;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_12;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_12;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_12 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB7_13;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB7_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB7_13;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB7_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_14;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_14;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_15;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_15;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_16;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_16;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_16 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_17;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_17;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_17 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_9_or_cond == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_14;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_17 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_9_or_cond == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB9_18;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB9_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB9_18;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB9_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__critedge_13 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_21;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__critedge_13 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB10_19;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB10_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB10_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB10_19;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB10_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB10_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB11_20;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB11_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB11_20;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB11_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB7_13;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB7_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB11_20;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB11_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_21;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_22;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_22;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_22 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_23;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_23;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_23 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__preheader_17 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB13_24;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB13_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_23 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__preheader_17 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_25;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB13_24;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB13_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB15_34;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB15_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_25;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_26;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_26;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_27;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_27;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_27 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_28;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_28;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_29;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_29;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_30;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_30;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_30 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_31;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_31;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_32;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_32;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_32 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_33;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_33;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB15_34;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB15_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB15_34;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB15_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_28_exitcond == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_35;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_28_exitcond == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_21;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_35;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_36;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_36;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_36 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_37;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_37;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %indvar44 = phi i32 [ 0, %0 ], [ %i.014, %4 ]*/
begin
huff_make_dhuff_tb__preheader10_indvar44 = huff_make_dhuff_tb__preheader10_indvar44_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013 = huff_make_dhuff_tb__preheader10_p_013_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013 = huff_make_dhuff_tb__preheader10_p_013_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013 = huff_make_dhuff_tb__preheader10_p_013_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2) */
begin
huff_make_dhuff_tb__preheader10_p_013 = huff_make_dhuff_tb__preheader10_p_013_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013_reg <= huff_make_dhuff_tb__preheader10_p_013;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013_reg <= huff_make_dhuff_tb__preheader10_p_013;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013_reg <= huff_make_dhuff_tb__preheader10_p_013;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013_reg <= huff_make_dhuff_tb__preheader10_p_013;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013_reg <= huff_make_dhuff_tb__preheader10_p_013;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %i.014 = add i32 %indvar44, 1*/
begin
huff_make_dhuff_tb__preheader10_i_014 = huff_make_dhuff_tb__preheader10_indvar44 + 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %i.014 = add i32 %indvar44, 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_i_014_reg <= huff_make_dhuff_tb__preheader10_i_014;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_i_014) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_i_014_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %scevgep48 = getelementptr i32* %p_xhtbl_bits, i32 %i.014*/
begin
huff_make_dhuff_tb__preheader10_scevgep48 = arg_p_xhtbl_bits + 4 * huff_make_dhuff_tb__preheader10_i_014;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb__preheader10_1 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_4)
begin
huff_make_dhuff_tb__preheader10_1_reg <= huff_make_dhuff_tb__preheader10_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_1_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %2 = icmp slt i32 %1, 1*/
begin
huff_make_dhuff_tb__preheader10_2 = $signed(huff_make_dhuff_tb__preheader10_1) < $signed(32'd1);
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.lr.ph*/
/* %tmp37 = icmp sgt i32 %1, 1*/
begin
huff_make_dhuff_tb__lr_ph_tmp37 = $signed(huff_make_dhuff_tb__preheader10_1_reg) > $signed(32'd1);
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.lr.ph*/
/* %smax = select i1 %tmp37, i32 %1, i32 1*/
begin
huff_make_dhuff_tb__lr_ph_smax = (huff_make_dhuff_tb__lr_ph_tmp37 ? huff_make_dhuff_tb__preheader10_1_reg : 32'd1);
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.lr.ph*/
/* %smax = select i1 %tmp37, i32 %1, i32 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB2_5)
begin
huff_make_dhuff_tb__lr_ph_smax_reg <= huff_make_dhuff_tb__lr_ph_smax;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__lr_ph_smax) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__lr_ph_smax_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %3*/
/* %indvar39 = phi i32 [ 0, %.lr.ph ], [ %indvar.next40, %3 ]*/
begin
huff_make_dhuff_tb_3_indvar39 = huff_make_dhuff_tb_3_indvar39_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %3*/
/* %tmp42 = add i32 %p.013, %indvar39*/
begin
huff_make_dhuff_tb_3_tmp42 = huff_make_dhuff_tb__preheader10_p_013_reg + huff_make_dhuff_tb_3_indvar39;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %3*/
/* %scevgep43 = getelementptr [257 x i32]* %huffsize, i32 0, i32 %tmp42*/
begin
huff_make_dhuff_tb_3_scevgep43 = `TAG_huff_make_dhuff_tb_0_huffsize_a + 4 * huff_make_dhuff_tb_3_tmp42;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %3*/
/* %indvar.next40 = add i32 %indvar39, 1*/
begin
huff_make_dhuff_tb_3_indvar_next40 = huff_make_dhuff_tb_3_indvar39 + 32'd1;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %3*/
/* %exitcond41 = icmp eq i32 %indvar.next40, %smax*/
begin
huff_make_dhuff_tb_3_exitcond41 = huff_make_dhuff_tb_3_indvar_next40 == huff_make_dhuff_tb__lr_ph_smax_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %._crit_edge*/
/* %tmp38 = add i32 %p.013, %smax*/
begin
huff_make_dhuff_tb___crit_edge_tmp38 = huff_make_dhuff_tb__preheader10_p_013_reg + huff_make_dhuff_tb__lr_ph_smax_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8)
begin
huff_make_dhuff_tb_4_p_1_lcssa = huff_make_dhuff_tb_4_p_1_lcssa_phi_temp;
end
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8) */
begin
huff_make_dhuff_tb_4_p_1_lcssa = huff_make_dhuff_tb_4_p_1_lcssa_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8)
begin
huff_make_dhuff_tb_4_p_1_lcssa_reg <= huff_make_dhuff_tb_4_p_1_lcssa;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_4_p_1_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_4_p_1_lcssa_reg"); $finish; end
end
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8)
begin
huff_make_dhuff_tb_4_p_1_lcssa_reg <= huff_make_dhuff_tb_4_p_1_lcssa;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_4_p_1_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_4_p_1_lcssa_reg"); $finish; end
end
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8)
begin
huff_make_dhuff_tb_4_p_1_lcssa_reg <= huff_make_dhuff_tb_4_p_1_lcssa;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_4_p_1_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_4_p_1_lcssa_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %4*/
/* %exitcond46 = icmp eq i32 %i.014, 16*/
begin
huff_make_dhuff_tb_4_exitcond46 = huff_make_dhuff_tb__preheader10_i_014_reg == 32'd16;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %5*/
/* %6 = getelementptr inbounds [257 x i32]* %huffsize, i32 0, i32 %p.1.lcssa*/
begin
huff_make_dhuff_tb_5_6 = `TAG_huff_make_dhuff_tb_0_huffsize_a + 4 * huff_make_dhuff_tb_4_p_1_lcssa_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %5*/
/* %7 = getelementptr inbounds [257 x i32]* %huffsize, i32 0, i32 0*/
if (reset) begin huff_make_dhuff_tb_5_7 = 0; end
begin
huff_make_dhuff_tb_5_7 = `TAG_huff_make_dhuff_tb_0_huffsize_a;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %5*/
/* %7 = getelementptr inbounds [257 x i32]* %huffsize, i32 0, i32 0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
huff_make_dhuff_tb_5_7_reg <= huff_make_dhuff_tb_5_7;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_5_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_5_7_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %5*/
/* %8 = load i32* %7, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_5_8 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_p_2_ph = huff_make_dhuff_tb__outer_p_2_ph_phi_temp;
end
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13) */
begin
huff_make_dhuff_tb__outer_p_2_ph = huff_make_dhuff_tb__outer_p_2_ph_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_p_2_ph_reg <= huff_make_dhuff_tb__outer_p_2_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_p_2_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_p_2_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_p_2_ph_reg <= huff_make_dhuff_tb__outer_p_2_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_p_2_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_p_2_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_p_2_ph_reg <= huff_make_dhuff_tb__outer_p_2_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_p_2_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_p_2_ph_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_code_0_ph = huff_make_dhuff_tb__outer_code_0_ph_phi_temp;
end
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13) */
begin
huff_make_dhuff_tb__outer_code_0_ph = huff_make_dhuff_tb__outer_code_0_ph_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_code_0_ph_reg <= huff_make_dhuff_tb__outer_code_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_code_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_code_0_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_code_0_ph_reg <= huff_make_dhuff_tb__outer_code_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_code_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_code_0_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_code_0_ph_reg <= huff_make_dhuff_tb__outer_code_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_code_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_code_0_ph_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph = huff_make_dhuff_tb__outer_size_0_ph_phi_temp;
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph = huff_make_dhuff_tb__outer_size_0_ph_phi_temp;
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13) */
begin
huff_make_dhuff_tb__outer_size_0_ph = huff_make_dhuff_tb__outer_size_0_ph_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph_reg <= huff_make_dhuff_tb__outer_size_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_size_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph_reg <= huff_make_dhuff_tb__outer_size_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_size_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph_reg <= huff_make_dhuff_tb__outer_size_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_size_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph_reg <= huff_make_dhuff_tb__outer_size_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_size_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.outer*/
/* %tmp28 = add i32 %p.2.ph, 1*/
begin
huff_make_dhuff_tb__outer_tmp28 = huff_make_dhuff_tb__outer_p_2_ph + 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %tmp28 = add i32 %p.2.ph, 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_tmp28_reg <= huff_make_dhuff_tb__outer_tmp28;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_tmp28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_tmp28_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.outer*/
/* %tmp3349 = or i32 %code.0.ph, 1*/
begin
huff_make_dhuff_tb__outer_tmp3349 = huff_make_dhuff_tb__outer_code_0_ph | 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %tmp3349 = or i32 %code.0.ph, 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_tmp3349_reg <= huff_make_dhuff_tb__outer_tmp3349;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_tmp3349) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_tmp3349_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_indvar26 = huff_make_dhuff_tb_9_indvar26_phi_temp;
end
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14) */
begin
huff_make_dhuff_tb_9_indvar26 = huff_make_dhuff_tb_9_indvar26_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_indvar26_reg <= huff_make_dhuff_tb_9_indvar26;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_indvar26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar26_reg"); $finish; end
end
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_indvar26_reg <= huff_make_dhuff_tb_9_indvar26;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_indvar26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar26_reg"); $finish; end
end
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_indvar26_reg <= huff_make_dhuff_tb_9_indvar26;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_indvar26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar26_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %tmp29 = add i32 %tmp28, %indvar26*/
begin
huff_make_dhuff_tb_9_tmp29 = huff_make_dhuff_tb__outer_tmp28_reg + huff_make_dhuff_tb_9_indvar26;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %tmp29 = add i32 %tmp28, %indvar26*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_tmp29_reg <= huff_make_dhuff_tb_9_tmp29;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_tmp29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_tmp29_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %scevgep30 = getelementptr [257 x i32]* %huffsize, i32 0, i32 %tmp29*/
begin
huff_make_dhuff_tb_9_scevgep30 = `TAG_huff_make_dhuff_tb_0_huffsize_a + 4 * huff_make_dhuff_tb_9_tmp29;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %scevgep30 = getelementptr [257 x i32]* %huffsize, i32 0, i32 %tmp29*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_scevgep30_reg <= huff_make_dhuff_tb_9_scevgep30;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_scevgep30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_scevgep30_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %tmp31 = add i32 %p.2.ph, %indvar26*/
begin
huff_make_dhuff_tb_9_tmp31 = huff_make_dhuff_tb__outer_p_2_ph_reg + huff_make_dhuff_tb_9_indvar26;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %scevgep32 = getelementptr [257 x i32]* %huffcode, i32 0, i32 %tmp31*/
begin
huff_make_dhuff_tb_9_scevgep32 = `TAG_huff_make_dhuff_tb_0_huffcode_a + 4 * huff_make_dhuff_tb_9_tmp31;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %code.0 = add i32 %code.0.ph, %indvar26*/
begin
huff_make_dhuff_tb_9_code_0 = huff_make_dhuff_tb__outer_code_0_ph_reg + huff_make_dhuff_tb_9_indvar26;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_9_10 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_17)
begin
huff_make_dhuff_tb_9_10_reg <= huff_make_dhuff_tb_9_10;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_10_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %11 = icmp eq i32 %10, %size.0.ph*/
begin
huff_make_dhuff_tb_9_11 = huff_make_dhuff_tb_9_10 == huff_make_dhuff_tb__outer_size_0_ph_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %12 = icmp slt i32 %tmp29, 257*/
begin
huff_make_dhuff_tb_9_12 = $signed(huff_make_dhuff_tb_9_tmp29) < $signed(32'd257);
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %12 = icmp slt i32 %tmp29, 257*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_12_reg <= huff_make_dhuff_tb_9_12;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_12_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %or.cond = and i1 %11, %12*/
begin
huff_make_dhuff_tb_9_or_cond = huff_make_dhuff_tb_9_11 & huff_make_dhuff_tb_9_12_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %indvar.next27 = add i32 %indvar26, 1*/
begin
huff_make_dhuff_tb_9_indvar_next27 = huff_make_dhuff_tb_9_indvar26 + 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %indvar.next27 = add i32 %indvar26, 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_indvar_next27_reg <= huff_make_dhuff_tb_9_indvar_next27;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_indvar_next27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar_next27_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.critedge*/
/* %13 = icmp eq i32 %10, 0*/
begin
huff_make_dhuff_tb__critedge_13 = huff_make_dhuff_tb_9_10_reg == 32'd0;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader4*/
/* %tmp34 = add i32 %tmp3349, %indvar26*/
begin
huff_make_dhuff_tb__preheader4_tmp34 = huff_make_dhuff_tb__outer_tmp3349_reg + huff_make_dhuff_tb_9_indvar26_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader4*/
/* %tmp = sub i32 %10, %size.0.ph*/
begin
huff_make_dhuff_tb__preheader4_tmp = huff_make_dhuff_tb_9_10_reg - huff_make_dhuff_tb__outer_size_0_ph_reg;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader4*/
/* %tmp = sub i32 %10, %size.0.ph*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB10_19)
begin
huff_make_dhuff_tb__preheader4_tmp_reg <= huff_make_dhuff_tb__preheader4_tmp;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader4_tmp) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader4_tmp_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %14*/
/* %indvar19 = phi i32 [ 0, %.preheader4 ], [ %indvar.next20, %14 ]*/
begin
huff_make_dhuff_tb_14_indvar19 = huff_make_dhuff_tb_14_indvar19_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %14*/
/* %code.1 = phi i32 [ %tmp34, %.preheader4 ], [ %15, %14 ]*/
begin
huff_make_dhuff_tb_14_code_1 = huff_make_dhuff_tb_14_code_1_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %14*/
/* %15 = shl i32 %code.1, 1*/
begin
huff_make_dhuff_tb_14_15 = huff_make_dhuff_tb_14_code_1 <<< 32'd1 % 32;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %14*/
/* %indvar.next20 = add i32 %indvar19, 1*/
begin
huff_make_dhuff_tb_14_indvar_next20 = huff_make_dhuff_tb_14_indvar19 + 32'd1;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %14*/
/* %exitcond21 = icmp eq i32 %indvar.next20, %tmp*/
begin
huff_make_dhuff_tb_14_exitcond21 = huff_make_dhuff_tb_14_indvar_next20 == huff_make_dhuff_tb__preheader4_tmp_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %indvar = phi i32 [ %l.02, %28 ], [ 0, %.critedge ]*/
begin
huff_make_dhuff_tb__preheader_indvar = huff_make_dhuff_tb__preheader_indvar_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03 = huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21) */
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03 = huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg <= huff_make_dhuff_tb__preheader_p_dhtbl_ml_03;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_dhtbl_ml_03) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg <= huff_make_dhuff_tb__preheader_p_dhtbl_ml_03;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_dhtbl_ml_03) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg <= huff_make_dhuff_tb__preheader_p_dhtbl_ml_03;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_dhtbl_ml_03) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21) */
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %l.02 = add i32 %indvar, 1*/
begin
huff_make_dhuff_tb__preheader_l_02 = huff_make_dhuff_tb__preheader_indvar + 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %l.02 = add i32 %indvar, 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_l_02_reg <= huff_make_dhuff_tb__preheader_l_02;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_l_02) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_l_02_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %scevgep = getelementptr i32* %p_xhtbl_bits, i32 %l.02*/
begin
huff_make_dhuff_tb__preheader_scevgep = arg_p_xhtbl_bits + 4 * huff_make_dhuff_tb__preheader_l_02;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %scevgep = getelementptr i32* %p_xhtbl_bits, i32 %l.02*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_scevgep_reg <= huff_make_dhuff_tb__preheader_scevgep;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_scevgep) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_scevgep_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %scevgep15 = getelementptr i32* %p_dhtbl_maxcode, i32 %l.02*/
begin
huff_make_dhuff_tb__preheader_scevgep15 = arg_p_dhtbl_maxcode + 4 * huff_make_dhuff_tb__preheader_l_02;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %scevgep15 = getelementptr i32* %p_dhtbl_maxcode, i32 %l.02*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_scevgep15_reg <= huff_make_dhuff_tb__preheader_scevgep15;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_scevgep15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_scevgep15_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %16 = load i32* %scevgep, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb__preheader_16 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %17 = icmp eq i32 %16, 0*/
begin
huff_make_dhuff_tb__preheader_17 = huff_make_dhuff_tb__preheader_16 == 32'd0;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %scevgep17 = getelementptr i32* %p_dhtbl_mincode, i32 %l.02*/
begin
huff_make_dhuff_tb_19_scevgep17 = arg_p_dhtbl_mincode + 4 * huff_make_dhuff_tb__preheader_l_02_reg;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %19*/
/* %scevgep17 = getelementptr i32* %p_dhtbl_mincode, i32 %l.02*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
huff_make_dhuff_tb_19_scevgep17_reg <= huff_make_dhuff_tb_19_scevgep17;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_19_scevgep17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_19_scevgep17_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %scevgep16 = getelementptr i32* %p_dhtbl_valptr, i32 %l.02*/
begin
huff_make_dhuff_tb_19_scevgep16 = arg_p_dhtbl_valptr + 4 * huff_make_dhuff_tb__preheader_l_02_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %20 = getelementptr inbounds [257 x i32]* %huffcode, i32 0, i32 %p.31*/
begin
huff_make_dhuff_tb_19_20 = `TAG_huff_make_dhuff_tb_0_huffcode_a + 4 * huff_make_dhuff_tb__preheader_p_31_reg;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %19*/
/* %20 = getelementptr inbounds [257 x i32]* %huffcode, i32 0, i32 %p.31*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
huff_make_dhuff_tb_19_20_reg <= huff_make_dhuff_tb_19_20;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_19_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_19_20_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %21 = load i32* %20, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_19_21 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %22 = load i32* %scevgep, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_19_22 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %23 = add i32 %p.31, -1*/
begin
huff_make_dhuff_tb_19_23 = huff_make_dhuff_tb__preheader_p_31_reg + -32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %19*/
/* %23 = add i32 %p.31, -1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
huff_make_dhuff_tb_19_23_reg <= huff_make_dhuff_tb_19_23;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_19_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_19_23_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %24 = add i32 %23, %22*/
begin
huff_make_dhuff_tb_19_24 = huff_make_dhuff_tb_19_23_reg + huff_make_dhuff_tb_19_22;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %25 = getelementptr inbounds [257 x i32]* %huffcode, i32 0, i32 %24*/
begin
huff_make_dhuff_tb_19_25 = `TAG_huff_make_dhuff_tb_0_huffcode_a + 4 * huff_make_dhuff_tb_19_24;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_19_26 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %27 = add i32 %22, %p.31*/
begin
huff_make_dhuff_tb_19_27 = huff_make_dhuff_tb_19_22 + huff_make_dhuff_tb__preheader_p_31_reg;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %19*/
/* %27 = add i32 %22, %p.31*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31)
begin
huff_make_dhuff_tb_19_27_reg <= huff_make_dhuff_tb_19_27;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_19_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_19_27_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %28*/
/* %p.4 = phi i32 [ %p.31, %18 ], [ %27, %19 ]*/
begin
huff_make_dhuff_tb_28_p_4 = huff_make_dhuff_tb_28_p_4_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1 = huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp;
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1 = huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp;
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34) */
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1 = huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg <= huff_make_dhuff_tb_28_p_dhtbl_ml_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg"); $finish; end
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg <= huff_make_dhuff_tb_28_p_dhtbl_ml_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg"); $finish; end
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg <= huff_make_dhuff_tb_28_p_dhtbl_ml_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg"); $finish; end
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg <= huff_make_dhuff_tb_28_p_dhtbl_ml_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %28*/
/* %exitcond = icmp eq i32 %l.02, 16*/
begin
huff_make_dhuff_tb_28_exitcond = huff_make_dhuff_tb__preheader_l_02_reg == 32'd16;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %29*/
/* %30 = getelementptr inbounds i32* %p_dhtbl_maxcode, i32 %p_dhtbl_ml.1*/
begin
huff_make_dhuff_tb_29_30 = arg_p_dhtbl_maxcode + 4 * huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %29*/
/* %30 = getelementptr inbounds i32* %p_dhtbl_maxcode, i32 %p_dhtbl_ml.1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35)
begin
huff_make_dhuff_tb_29_30_reg <= huff_make_dhuff_tb_29_30;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_29_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_29_30_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %29*/
/* %31 = load i32* %30, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_29_31 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %29*/
/* %32 = add nsw i32 %31, 1*/
begin
huff_make_dhuff_tb_29_32 = huff_make_dhuff_tb_29_31 + 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %indvar44 = phi i32 [ 0, %0 ], [ %i.014, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb__preheader10_indvar44_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_indvar44_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %indvar44 = phi i32 [ 0, %0 ], [ %i.014, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_4_exitcond46 == 1'd0)
begin
huff_make_dhuff_tb__preheader10_indvar44_phi_temp <= huff_make_dhuff_tb__preheader10_i_014_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_i_014_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_indvar44_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb__preheader10_p_013_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_4_exitcond46 == 1'd0)
begin
huff_make_dhuff_tb__preheader10_p_013_phi_temp <= huff_make_dhuff_tb_4_p_1_lcssa;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_4_p_1_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_4 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__preheader10_2 == 1'd1)
begin
huff_make_dhuff_tb_4_p_1_lcssa_phi_temp <= huff_make_dhuff_tb__preheader10_p_013_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_4_p_1_lcssa_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_4_p_1_lcssa_phi_temp <= huff_make_dhuff_tb___crit_edge_tmp38;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb___crit_edge_tmp38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_4_p_1_lcssa_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %3*/
/* %indvar39 = phi i32 [ 0, %.lr.ph ], [ %indvar.next40, %3 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_3_indvar39_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_3_indvar39_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %3*/
/* %indvar39 = phi i32 [ 0, %.lr.ph ], [ %indvar.next40, %3 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_3_exitcond41 == 1'd0)
begin
huff_make_dhuff_tb_3_indvar39_phi_temp <= huff_make_dhuff_tb_3_indvar_next40;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_3_indvar_next40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_3_indvar39_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_12 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb__outer_p_2_ph_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_p_2_ph_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd1)
begin
huff_make_dhuff_tb__outer_p_2_ph_phi_temp <= huff_make_dhuff_tb_9_tmp29_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_tmp29_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_p_2_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_12 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb__outer_code_0_ph_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_code_0_ph_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd1)
begin
huff_make_dhuff_tb__outer_code_0_ph_phi_temp <= huff_make_dhuff_tb_14_15;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_14_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_code_0_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_12 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb__outer_size_0_ph_phi_temp <= huff_make_dhuff_tb_5_8;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd1)
begin
huff_make_dhuff_tb__outer_size_0_ph_phi_temp <= huff_make_dhuff_tb_9_10_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_10_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_9_indvar26_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar26_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_17 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_9_or_cond == 1'd1)
begin
huff_make_dhuff_tb_9_indvar26_phi_temp <= huff_make_dhuff_tb_9_indvar_next27_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_indvar_next27_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar26_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %indvar = phi i32 [ %l.02, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__critedge_13 == 1'd1)
begin
huff_make_dhuff_tb__preheader_indvar_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_indvar_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %indvar = phi i32 [ %l.02, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_28_exitcond == 1'd0)
begin
huff_make_dhuff_tb__preheader_indvar_phi_temp <= huff_make_dhuff_tb__preheader_l_02_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_l_02_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_indvar_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__critedge_13 == 1'd1)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp <= 32'd1;
if (^reset !== 1'bX && ^(32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_28_exitcond == 1'd0)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp <= huff_make_dhuff_tb_28_p_dhtbl_ml_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__critedge_13 == 1'd1)
begin
huff_make_dhuff_tb__preheader_p_31_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_28_exitcond == 1'd0)
begin
huff_make_dhuff_tb__preheader_p_31_phi_temp <= huff_make_dhuff_tb_28_p_4;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %14*/
/* %indvar19 = phi i32 [ 0, %.preheader4 ], [ %indvar.next20, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB10_19 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_14_indvar19_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_14_indvar19_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %14*/
/* %indvar19 = phi i32 [ 0, %.preheader4 ], [ %indvar.next20, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd0)
begin
huff_make_dhuff_tb_14_indvar19_phi_temp <= huff_make_dhuff_tb_14_indvar_next20;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_14_indvar_next20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_14_indvar19_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %14*/
/* %code.1 = phi i32 [ %tmp34, %.preheader4 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB10_19 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_14_code_1_phi_temp <= huff_make_dhuff_tb__preheader4_tmp34;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader4_tmp34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_14_code_1_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %14*/
/* %code.1 = phi i32 [ %tmp34, %.preheader4 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd0)
begin
huff_make_dhuff_tb_14_code_1_phi_temp <= huff_make_dhuff_tb_14_15;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_14_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_14_code_1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %28*/
/* %p.4 = phi i32 [ %p.31, %18 ], [ %27, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_28_p_4_phi_temp <= huff_make_dhuff_tb__preheader_p_31_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_4_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %28*/
/* %p.4 = phi i32 [ %p.31, %18 ], [ %27, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_28_p_4_phi_temp <= huff_make_dhuff_tb_19_27_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_19_27_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_4_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp <= huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp <= huff_make_dhuff_tb__preheader_l_02_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_l_02_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* huff_make_dhuff_tb: %29*/
/* ret i32 %p_dhtbl_ml.1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
return_val <= 0;
if (^reset !== 1'bX && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
/* huff_make_dhuff_tb: %29*/
/* ret i32 %p_dhtbl_ml.1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
return_val <= huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
memory_controller_address = huff_make_dhuff_tb__preheader10_scevgep48;
end
/* huff_make_dhuff_tb: %3*/
/* store i32 %i.014, i32* %scevgep43, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6)
begin
memory_controller_address = huff_make_dhuff_tb_3_scevgep43;
end
/* huff_make_dhuff_tb: %5*/
/* store i32 0, i32* %6, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
memory_controller_address = huff_make_dhuff_tb_5_6;
end
/* huff_make_dhuff_tb: %5*/
/* %8 = load i32* %7, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10)
begin
memory_controller_address = huff_make_dhuff_tb_5_7_reg;
end
/* huff_make_dhuff_tb: %9*/
/* store i32 %code.0, i32* %scevgep32, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
memory_controller_address = huff_make_dhuff_tb_9_scevgep32;
end
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15)
begin
memory_controller_address = huff_make_dhuff_tb_9_scevgep30_reg;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %16 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
memory_controller_address = huff_make_dhuff_tb__preheader_scevgep;
end
/* huff_make_dhuff_tb: %18*/
/* store i32 -1, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24)
begin
memory_controller_address = huff_make_dhuff_tb__preheader_scevgep15_reg;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %p.31, i32* %scevgep16, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
memory_controller_address = huff_make_dhuff_tb_19_scevgep16;
end
/* huff_make_dhuff_tb: %19*/
/* %21 = load i32* %20, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26)
begin
memory_controller_address = huff_make_dhuff_tb_19_20_reg;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %21, i32* %scevgep17, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28)
begin
memory_controller_address = huff_make_dhuff_tb_19_scevgep17_reg;
end
/* huff_make_dhuff_tb: %19*/
/* %22 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29)
begin
memory_controller_address = huff_make_dhuff_tb__preheader_scevgep_reg;
end
/* huff_make_dhuff_tb: %19*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31)
begin
memory_controller_address = huff_make_dhuff_tb_19_25;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %26, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33)
begin
memory_controller_address = huff_make_dhuff_tb__preheader_scevgep15_reg;
end
/* huff_make_dhuff_tb: %29*/
/* %31 = load i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35)
begin
memory_controller_address = huff_make_dhuff_tb_29_30;
end
/* huff_make_dhuff_tb: %29*/
/* store i32 %32, i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
memory_controller_address = huff_make_dhuff_tb_29_30_reg;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %3*/
/* store i32 %i.014, i32* %scevgep43, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %5*/
/* store i32 0, i32* %6, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %5*/
/* %8 = load i32* %7, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %9*/
/* store i32 %code.0, i32* %scevgep32, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %16 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %18*/
/* store i32 -1, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %p.31, i32* %scevgep16, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* %21 = load i32* %20, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %21, i32* %scevgep17, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* %22 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %26, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %29*/
/* %31 = load i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %29*/
/* store i32 %32, i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %3*/
/* store i32 %i.014, i32* %scevgep43, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %5*/
/* store i32 0, i32* %6, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %5*/
/* %8 = load i32* %7, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %9*/
/* store i32 %code.0, i32* %scevgep32, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %16 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %18*/
/* store i32 -1, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %p.31, i32* %scevgep16, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* %21 = load i32* %20, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %21, i32* %scevgep17, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* %22 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %19*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %26, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %29*/
/* %31 = load i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %29*/
/* store i32 %32, i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
memory_controller_write_enable = 1'd1;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* huff_make_dhuff_tb: %3*/
/* store i32 %i.014, i32* %scevgep43, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6)
begin
memory_controller_in = huff_make_dhuff_tb__preheader10_i_014_reg;
end
/* huff_make_dhuff_tb: %5*/
/* store i32 0, i32* %6, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
memory_controller_in = 32'd0;
end
/* huff_make_dhuff_tb: %9*/
/* store i32 %code.0, i32* %scevgep32, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
memory_controller_in = huff_make_dhuff_tb_9_code_0;
end
/* huff_make_dhuff_tb: %18*/
/* store i32 -1, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24)
begin
memory_controller_in = -32'd1;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %p.31, i32* %scevgep16, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
memory_controller_in = huff_make_dhuff_tb__preheader_p_31_reg;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %21, i32* %scevgep17, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28)
begin
memory_controller_in = huff_make_dhuff_tb_19_21;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %26, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33)
begin
memory_controller_in = huff_make_dhuff_tb_19_26;
end
/* huff_make_dhuff_tb: %29*/
/* store i32 %32, i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
memory_controller_in = huff_make_dhuff_tb_29_32;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %3*/
/* store i32 %i.014, i32* %scevgep43, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %5*/
/* store i32 0, i32* %6, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %5*/
/* %8 = load i32* %7, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %9*/
/* store i32 %code.0, i32* %scevgep32, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %16 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %18*/
/* store i32 -1, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %p.31, i32* %scevgep16, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* %21 = load i32* %20, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %21, i32* %scevgep17, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* %22 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %26, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %29*/
/* %31 = load i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %29*/
/* store i32 %32, i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module DecodeHuffman
(
clk,
reset,
start,
finish,
return_val,
arg_Xhuff_huffval,
arg_Dhuff_ml,
arg_Dhuff_maxcode,
arg_Dhuff_mincode,
arg_Dhuff_valptr,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [5:0] LEGUP_0 = 6'd0;
parameter [5:0] LEGUP_F_DecodeHuffman_BB0_1 = 6'd1;
parameter [5:0] LEGUP_F_DecodeHuffman_BB0_2 = 6'd2;
parameter [5:0] LEGUP_F_DecodeHuffman_BB0_3 = 6'd3;
parameter [5:0] LEGUP_F_DecodeHuffman_BB1_4 = 6'd4;
parameter [5:0] LEGUP_F_DecodeHuffman_BB1_5 = 6'd5;
parameter [5:0] LEGUP_F_DecodeHuffman_BB1_6 = 6'd6;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_7 = 6'd7;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_8 = 6'd8;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_9 = 6'd9;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_10 = 6'd10;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_11 = 6'd11;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_12 = 6'd12;
parameter [5:0] LEGUP_F_DecodeHuffman_BB3_13 = 6'd13;
parameter [5:0] LEGUP_F_DecodeHuffman_BB3_14 = 6'd14;
parameter [5:0] LEGUP_F_DecodeHuffman_BB3_15 = 6'd15;
parameter [5:0] LEGUP_F_DecodeHuffman_BB3_16 = 6'd16;
parameter [5:0] LEGUP_F_DecodeHuffman_BB4_17 = 6'd17;
parameter [5:0] LEGUP_F_DecodeHuffman_BB5_18 = 6'd18;
parameter [5:0] LEGUP_F_DecodeHuffman_BB6_19 = 6'd19;
parameter [5:0] LEGUP_F_DecodeHuffman_BB6_20 = 6'd20;
parameter [5:0] LEGUP_F_DecodeHuffman_BB7_21 = 6'd21;
parameter [5:0] LEGUP_F_DecodeHuffman_BB7_22 = 6'd22;
parameter [5:0] LEGUP_F_DecodeHuffman_BB7_23 = 6'd23;
parameter [5:0] LEGUP_F_DecodeHuffman_BB7_24 = 6'd24;
parameter [5:0] LEGUP_F_DecodeHuffman_BB7_25 = 6'd25;
parameter [5:0] LEGUP_F_DecodeHuffman_BB8_26 = 6'd26;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_27 = 6'd27;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_28 = 6'd28;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_29 = 6'd29;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_30 = 6'd30;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_31 = 6'd31;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_32 = 6'd32;
parameter [5:0] LEGUP_F_DecodeHuffman_BB10_33 = 6'd33;
parameter [5:0] LEGUP_F_DecodeHuffman_BB10_34 = 6'd34;
parameter [5:0] LEGUP_F_DecodeHuffman_BB10_35 = 6'd35;
parameter [5:0] LEGUP_F_DecodeHuffman_BB10_36 = 6'd36;
parameter [5:0] LEGUP_F_DecodeHuffman_BB11_37 = 6'd37;
parameter [5:0] LEGUP_F_DecodeHuffman_BB12_38 = 6'd38;
parameter [5:0] LEGUP_F_DecodeHuffman_BB13_39 = 6'd39;
parameter [5:0] LEGUP_F_DecodeHuffman_BB13_40 = 6'd40;
parameter [5:0] LEGUP_F_DecodeHuffman_BB14_41 = 6'd41;
parameter [5:0] LEGUP_F_DecodeHuffman_BB14_42 = 6'd42;
parameter [5:0] LEGUP_F_DecodeHuffman_BB14_43 = 6'd43;
parameter [5:0] LEGUP_F_DecodeHuffman_BB14_44 = 6'd44;
parameter [5:0] LEGUP_F_DecodeHuffman_BB14_45 = 6'd45;
parameter [5:0] LEGUP_F_DecodeHuffman_BB15_46 = 6'd46;
parameter [5:0] LEGUP_F_DecodeHuffman_BB15_47 = 6'd47;
parameter [5:0] LEGUP_F_DecodeHuffman_BB15_48 = 6'd48;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_49 = 6'd49;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_50 = 6'd50;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_51 = 6'd51;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_52 = 6'd52;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_53 = 6'd53;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_54 = 6'd54;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_55 = 6'd55;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_56 = 6'd56;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_57 = 6'd57;
parameter [5:0] LEGUP_F_DecodeHuffman_BB17_58 = 6'd58;
input clk;
input reset;
input start;
output reg finish;
output reg [31:0] return_val;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_Xhuff_huffval;
input [31:0] arg_Dhuff_ml;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_Dhuff_maxcode;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_Dhuff_mincode;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_Dhuff_valptr;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [5:0] cur_state;
reg [31:0] DecodeHuffman_0_1;
reg [31:0] DecodeHuffman_0_1_reg;
reg DecodeHuffman_0_2;
reg [31:0] DecodeHuffman___crit_edge_i__pre_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_3_4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_3_4_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_3_5;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_3_5_reg;
reg [7:0] DecodeHuffman_3_6;
reg DecodeHuffman_3_7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_8_9;
reg [7:0] DecodeHuffman_8_10;
reg [7:0] DecodeHuffman_8_10_reg;
reg DecodeHuffman_8_11;
reg [7:0] DecodeHuffman_14_temp_0_in_i_i;
reg [31:0] DecodeHuffman_14_temp_0_i_i;
reg [31:0] DecodeHuffman_pgetc_exit_i__0_i_i;
reg [31:0] DecodeHuffman_pgetc_exit_i__0_i_i_reg;
reg [31:0] DecodeHuffman_buf_getb_exit_15;
reg [31:0] DecodeHuffman_buf_getb_exit_15_reg;
reg [31:0] DecodeHuffman_buf_getb_exit_16;
reg [31:0] DecodeHuffman_buf_getb_exit_17;
reg [31:0] DecodeHuffman_buf_getb_exit_17_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit_18;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit_18_reg;
reg [31:0] DecodeHuffman_buf_getb_exit_19;
reg [31:0] DecodeHuffman_buf_getb_exit_20;
reg DecodeHuffman_buf_getb_exit_not__i;
reg [31:0] DecodeHuffman_buf_getb_exit___i;
reg [31:0] DecodeHuffman_buf_getb_exit___i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit_21;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit_21_reg;
reg [31:0] DecodeHuffman_buf_getb_exit_22;
reg DecodeHuffman_buf_getb_exit_23;
reg [31:0] DecodeHuffman__lr_ph__pre_i1;
reg [31:0] DecodeHuffman__lr_ph_24;
reg [31:0] DecodeHuffman__lr_ph_indvar;
reg [31:0] DecodeHuffman__lr_ph_indvar_reg;
reg [31:0] DecodeHuffman__lr_ph_code_010;
reg [31:0] DecodeHuffman__lr_ph_tmp;
reg [31:0] DecodeHuffman__lr_ph_tmp_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman__lr_ph_scevgep;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman__lr_ph_scevgep_reg;
reg [31:0] DecodeHuffman__lr_ph_25;
reg [31:0] DecodeHuffman__lr_ph_25_reg;
reg DecodeHuffman__lr_ph_26;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_27_28;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_27_28_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_27_29;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_27_29_reg;
reg [7:0] DecodeHuffman_27_30;
reg DecodeHuffman_27_31;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_32_33;
reg [7:0] DecodeHuffman_32_34;
reg [7:0] DecodeHuffman_32_34_reg;
reg DecodeHuffman_32_35;
reg [7:0] DecodeHuffman_38_temp_0_in_i_i3;
reg [31:0] DecodeHuffman_38_temp_0_i_i4;
reg [31:0] DecodeHuffman_pgetc_exit_i6__0_i_i5;
reg [31:0] DecodeHuffman_pgetc_exit_i6__0_i_i5_reg;
reg [31:0] DecodeHuffman_buf_getb_exit9_39;
reg [31:0] DecodeHuffman_buf_getb_exit9_39_reg;
reg [31:0] DecodeHuffman_buf_getb_exit9_40;
reg [31:0] DecodeHuffman_buf_getb_exit9_41;
reg [31:0] DecodeHuffman_buf_getb_exit9_41_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit9_42;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit9_42_reg;
reg [31:0] DecodeHuffman_buf_getb_exit9_43;
reg [31:0] DecodeHuffman_buf_getb_exit9_44;
reg DecodeHuffman_buf_getb_exit9_not__i7;
reg [31:0] DecodeHuffman_buf_getb_exit9___i8;
reg [31:0] DecodeHuffman_buf_getb_exit9_45;
reg [31:0] DecodeHuffman_buf_getb_exit9_45_reg;
reg [31:0] DecodeHuffman_buf_getb_exit9_46;
reg DecodeHuffman_buf_getb_exit9_47;
reg [31:0] DecodeHuffman_buf_getb_exit9_indvar_next;
reg [31:0] DecodeHuffman_buf_getb_exit9_indvar_next_reg;
reg [31:0] DecodeHuffman___crit_edge_l_0_lcssa;
reg [31:0] DecodeHuffman___crit_edge_l_0_lcssa_reg;
reg [31:0] DecodeHuffman___crit_edge_code_0_lcssa;
reg [31:0] DecodeHuffman___crit_edge_code_0_lcssa_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman___crit_edge_48;
reg [31:0] DecodeHuffman___crit_edge_49;
reg DecodeHuffman___crit_edge_50;
reg [31:0] DecodeHuffman_51_52;
reg [31:0] DecodeHuffman_51_53;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_51_54;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_51_54_reg;
reg [31:0] DecodeHuffman_51_55;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_51_56;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_51_56_reg;
reg [31:0] DecodeHuffman_51_57;
reg [31:0] DecodeHuffman_51_58;
reg [31:0] DecodeHuffman_51_58_reg;
reg [31:0] DecodeHuffman_51_59;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_51_60;
reg [31:0] DecodeHuffman_51_61;
reg [31:0] DecodeHuffman_buf_getb_exit_15_phi_temp;
reg [31:0] DecodeHuffman_buf_getb_exit_16_phi_temp;
reg [7:0] DecodeHuffman_14_temp_0_in_i_i_phi_temp;
reg [31:0] DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp;
reg [31:0] DecodeHuffman__lr_ph__pre_i1_phi_temp;
reg [31:0] DecodeHuffman__lr_ph_24_phi_temp;
reg [31:0] DecodeHuffman__lr_ph_indvar_phi_temp;
reg [31:0] DecodeHuffman__lr_ph_code_010_phi_temp;
reg [31:0] DecodeHuffman___crit_edge_l_0_lcssa_phi_temp;
reg [31:0] DecodeHuffman___crit_edge_code_0_lcssa_phi_temp;
reg [31:0] DecodeHuffman_buf_getb_exit9_39_phi_temp;
reg [31:0] DecodeHuffman_buf_getb_exit9_40_phi_temp;
reg [7:0] DecodeHuffman_38_temp_0_in_i_i3_phi_temp;
reg [31:0] DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp;
/* Unsynthesizable Statements */
always @(posedge clk) begin
/* DecodeHuffman: %12*/
/* %13 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str30, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_DecodeHuffman_BB4_17)
begin
$write("Unanticipated marker detected.\n");
end
/* DecodeHuffman: %36*/
/* %37 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str30, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_DecodeHuffman_BB11_37)
begin
$write("Unanticipated marker detected.\n");
end
/* DecodeHuffman: %62*/
/* %63 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([20 x i8]* @.str26, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_DecodeHuffman_BB17_58)
begin
$write("Huffman read error\n");
end
/* DecodeHuffman: %62*/
/* tail call void @exit(i32 0) noreturn nounwind*/
if (cur_state == LEGUP_F_DecodeHuffman_BB17_58)
begin
$finish;
end
end
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 6'd0;
if (^reset !== 1'bX && ^(6'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_3 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_0_2 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_7;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_3 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_0_2 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_5;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_5;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_6;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_6;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_6 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_21;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_7;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_8;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_8;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_8 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_9;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_9;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_10;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_10;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_11;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_11;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_12;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_12;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_12 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_3_7 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_12 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_3_7 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB5_18;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB5_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_14;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_14;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_15;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_15;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_15 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_16;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_16;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_16 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_8_11 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_16 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_8_11 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB4_17;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB4_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB4_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB4_17;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB4_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB4_17 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB5_18;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB5_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB5_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB5_18;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB5_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB5_18 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB6_20;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB6_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB6_20;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB6_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_21;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_21;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_22;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_22;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_24 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_25;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_25;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB8_26;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB8_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_46;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB8_26;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB8_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman__lr_ph_26 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_27;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman__lr_ph_26 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_41;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_27;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_28;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_28;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_28 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_29;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_29;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_30;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_30;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_31;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_31;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_32 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_27_31 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_33;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_32 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_27_31 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB12_38;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB12_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_33;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_34;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_34;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_35;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_35;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_35 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_36 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_32_35 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB13_39;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB13_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_36 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_32_35 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB11_37;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB11_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB11_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB11_37;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB11_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB11_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB12_38;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB12_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB12_38 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB12_38;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB12_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB12_38 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB13_39;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB13_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB13_39;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB13_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB13_40;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB13_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB13_40;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB13_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_41;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_41;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_44 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_44 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB8_26;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB8_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_46;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_46;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_47;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_47 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_47;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_47 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_48 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_48 & memory_controller_waitrequest == 1'd0 & DecodeHuffman___crit_edge_50 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_49;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_48 & memory_controller_waitrequest == 1'd0 & DecodeHuffman___crit_edge_50 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB17_58;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB17_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_49;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_50;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_50 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_50;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_50 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_51;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_51;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_52;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_52;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_54;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_54 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_54;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_54 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_55;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_55;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_56;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_56 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_56;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_56 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_57;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_57 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_57;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_57 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB17_58 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB17_58;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB17_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB17_58 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
begin
DecodeHuffman_0_1 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB0_3)
begin
DecodeHuffman_0_1_reg <= DecodeHuffman_0_1;
if (^reset !== 1'bX && ^(DecodeHuffman_0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_0_1_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %0*/
/* %2 = icmp slt i32 %1, 0*/
begin
DecodeHuffman_0_2 = $signed(DecodeHuffman_0_1) < $signed(32'd0);
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge.i*/
/* %.pre.i = load i32* @current_read_byte, align 4, !tbaa !0*/
begin
DecodeHuffman___crit_edge_i__pre_i = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
begin
DecodeHuffman_3_4 = memory_controller_out[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
DecodeHuffman_3_4_reg <= DecodeHuffman_3_4;
if (^reset !== 1'bX && ^(DecodeHuffman_3_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_3_4_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %3*/
/* %5 = getelementptr inbounds i8* %4, i32 1*/
begin
DecodeHuffman_3_5 = DecodeHuffman_3_4 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %3*/
/* %5 = getelementptr inbounds i8* %4, i32 1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
DecodeHuffman_3_5_reg <= DecodeHuffman_3_5;
if (^reset !== 1'bX && ^(DecodeHuffman_3_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_3_5_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %3*/
/* %6 = load i8* %4, align 1, !tbaa !1*/
begin
DecodeHuffman_3_6 = memory_controller_out[7:0];
end
end
always @(*) begin
/* DecodeHuffman: %3*/
/* %7 = icmp eq i8 %6, -1*/
begin
DecodeHuffman_3_7 = DecodeHuffman_3_6 == -8'd1;
end
end
always @(*) begin
/* DecodeHuffman: %8*/
/* %9 = getelementptr inbounds i8* %4, i32 2*/
begin
DecodeHuffman_8_9 = DecodeHuffman_3_4_reg + 1 * 32'd2;
end
end
always @(*) begin
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
begin
DecodeHuffman_8_10 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_16)
begin
DecodeHuffman_8_10_reg <= DecodeHuffman_8_10;
if (^reset !== 1'bX && ^(DecodeHuffman_8_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_8_10_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %8*/
/* %11 = icmp eq i8 %10, 0*/
begin
DecodeHuffman_8_11 = DecodeHuffman_8_10 == 8'd0;
end
end
always @(*) begin
/* DecodeHuffman: %14*/
/* %temp.0.in.i.i = phi i8 [ %10, %12 ], [ %6, %3 ]*/
begin
DecodeHuffman_14_temp_0_in_i_i = DecodeHuffman_14_temp_0_in_i_i_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %14*/
/* %temp.0.i.i = zext i8 %temp.0.in.i.i to i32*/
begin
DecodeHuffman_14_temp_0_i_i = DecodeHuffman_14_temp_0_in_i_i;
end
end
always @(*) begin
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
DecodeHuffman_pgetc_exit_i__0_i_i = DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB6_19) */
begin
DecodeHuffman_pgetc_exit_i__0_i_i = DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
DecodeHuffman_pgetc_exit_i__0_i_i_reg <= DecodeHuffman_pgetc_exit_i__0_i_i;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i__0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i__0_i_i_reg"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
DecodeHuffman_pgetc_exit_i__0_i_i_reg <= DecodeHuffman_pgetc_exit_i__0_i_i;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i__0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i__0_i_i_reg"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
DecodeHuffman_pgetc_exit_i__0_i_i_reg <= DecodeHuffman_pgetc_exit_i__0_i_i;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i__0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i__0_i_i_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15 = DecodeHuffman_buf_getb_exit_15_phi_temp;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
else if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15 = DecodeHuffman_buf_getb_exit_15_phi_temp;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB7_21) */
begin
DecodeHuffman_buf_getb_exit_15 = DecodeHuffman_buf_getb_exit_15_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15_reg <= DecodeHuffman_buf_getb_exit_15;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15_reg <= DecodeHuffman_buf_getb_exit_15;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15_reg <= DecodeHuffman_buf_getb_exit_15;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15_reg <= DecodeHuffman_buf_getb_exit_15;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %16 = phi i32 [ 7, %pgetc.exit.i ], [ %1, %._crit_edge.i ]*/
begin
DecodeHuffman_buf_getb_exit_16 = DecodeHuffman_buf_getb_exit_16_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %17 = add nsw i32 %16, -1*/
begin
DecodeHuffman_buf_getb_exit_17 = DecodeHuffman_buf_getb_exit_16 + -32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %17 = add nsw i32 %16, -1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_17_reg <= DecodeHuffman_buf_getb_exit_17;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_17_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %18 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %16*/
begin
DecodeHuffman_buf_getb_exit_18 = `TAG_g_bit_set_mask_a + 4 * DecodeHuffman_buf_getb_exit_16;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %18 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %16*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_18_reg <= DecodeHuffman_buf_getb_exit_18;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_18_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %19 = load i32* %18, align 4, !tbaa !0*/
begin
DecodeHuffman_buf_getb_exit_19 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %20 = and i32 %19, %15*/
begin
DecodeHuffman_buf_getb_exit_20 = DecodeHuffman_buf_getb_exit_19 & DecodeHuffman_buf_getb_exit_15_reg;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %not..i = icmp ne i32 %20, 0*/
begin
DecodeHuffman_buf_getb_exit_not__i = DecodeHuffman_buf_getb_exit_20 != 32'd0;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %..i = zext i1 %not..i to i32*/
begin
DecodeHuffman_buf_getb_exit___i = DecodeHuffman_buf_getb_exit_not__i;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %..i = zext i1 %not..i to i32*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_24)
begin
DecodeHuffman_buf_getb_exit___i_reg <= DecodeHuffman_buf_getb_exit___i;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit___i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit___i_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %21 = getelementptr inbounds i32* %Dhuff_maxcode, i32 1*/
begin
DecodeHuffman_buf_getb_exit_21 = arg_Dhuff_maxcode + 4 * 32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %21 = getelementptr inbounds i32* %Dhuff_maxcode, i32 1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_21_reg <= DecodeHuffman_buf_getb_exit_21;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_21_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %22 = load i32* %21, align 4, !tbaa !0*/
begin
DecodeHuffman_buf_getb_exit_22 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %23 = icmp sgt i32 %..i, %22*/
begin
DecodeHuffman_buf_getb_exit_23 = $signed(DecodeHuffman_buf_getb_exit___i_reg) > $signed(DecodeHuffman_buf_getb_exit_22);
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %.pre.i1 = phi i32 [ %39, %buf_getb.exit9 ], [ %15, %buf_getb.exit ]*/
begin
DecodeHuffman__lr_ph__pre_i1 = DecodeHuffman__lr_ph__pre_i1_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %24 = phi i32 [ %41, %buf_getb.exit9 ], [ %17, %buf_getb.exit ]*/
begin
DecodeHuffman__lr_ph_24 = DecodeHuffman__lr_ph_24_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_indvar = DecodeHuffman__lr_ph_indvar_phi_temp;
end
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB8_26) */
begin
DecodeHuffman__lr_ph_indvar = DecodeHuffman__lr_ph_indvar_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_indvar_reg <= DecodeHuffman__lr_ph_indvar;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_indvar_reg"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_indvar_reg <= DecodeHuffman__lr_ph_indvar;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_indvar_reg"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_indvar_reg <= DecodeHuffman__lr_ph_indvar;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_indvar_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %code.010 = phi i32 [ %45, %buf_getb.exit9 ], [ %..i, %buf_getb.exit ]*/
begin
DecodeHuffman__lr_ph_code_010 = DecodeHuffman__lr_ph_code_010_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %tmp = add i32 %indvar, 2*/
begin
DecodeHuffman__lr_ph_tmp = DecodeHuffman__lr_ph_indvar + 32'd2;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %tmp = add i32 %indvar, 2*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_tmp_reg <= DecodeHuffman__lr_ph_tmp;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_tmp) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_tmp_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %scevgep = getelementptr i32* %Dhuff_maxcode, i32 %tmp*/
begin
DecodeHuffman__lr_ph_scevgep = arg_Dhuff_maxcode + 4 * DecodeHuffman__lr_ph_tmp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %scevgep = getelementptr i32* %Dhuff_maxcode, i32 %tmp*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_scevgep_reg <= DecodeHuffman__lr_ph_scevgep;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_scevgep) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_scevgep_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %25 = shl i32 %code.010, 1*/
begin
DecodeHuffman__lr_ph_25 = DecodeHuffman__lr_ph_code_010 <<< 32'd1 % 32;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %25 = shl i32 %code.010, 1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_25_reg <= DecodeHuffman__lr_ph_25;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_25_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %26 = icmp slt i32 %24, 0*/
begin
DecodeHuffman__lr_ph_26 = $signed(DecodeHuffman__lr_ph_24) < $signed(32'd0);
end
end
always @(*) begin
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
begin
DecodeHuffman_27_28 = memory_controller_out[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
DecodeHuffman_27_28_reg <= DecodeHuffman_27_28;
if (^reset !== 1'bX && ^(DecodeHuffman_27_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_27_28_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %27*/
/* %29 = getelementptr inbounds i8* %28, i32 1*/
begin
DecodeHuffman_27_29 = DecodeHuffman_27_28 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %27*/
/* %29 = getelementptr inbounds i8* %28, i32 1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
DecodeHuffman_27_29_reg <= DecodeHuffman_27_29;
if (^reset !== 1'bX && ^(DecodeHuffman_27_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_27_29_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %27*/
/* %30 = load i8* %28, align 1, !tbaa !1*/
begin
DecodeHuffman_27_30 = memory_controller_out[7:0];
end
end
always @(*) begin
/* DecodeHuffman: %27*/
/* %31 = icmp eq i8 %30, -1*/
begin
DecodeHuffman_27_31 = DecodeHuffman_27_30 == -8'd1;
end
end
always @(*) begin
/* DecodeHuffman: %32*/
/* %33 = getelementptr inbounds i8* %28, i32 2*/
begin
DecodeHuffman_32_33 = DecodeHuffman_27_28_reg + 1 * 32'd2;
end
end
always @(*) begin
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
begin
DecodeHuffman_32_34 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_36)
begin
DecodeHuffman_32_34_reg <= DecodeHuffman_32_34;
if (^reset !== 1'bX && ^(DecodeHuffman_32_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_32_34_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %32*/
/* %35 = icmp eq i8 %34, 0*/
begin
DecodeHuffman_32_35 = DecodeHuffman_32_34 == 8'd0;
end
end
always @(*) begin
/* DecodeHuffman: %38*/
/* %temp.0.in.i.i3 = phi i8 [ %34, %36 ], [ %30, %27 ]*/
begin
DecodeHuffman_38_temp_0_in_i_i3 = DecodeHuffman_38_temp_0_in_i_i3_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %38*/
/* %temp.0.i.i4 = zext i8 %temp.0.in.i.i3 to i32*/
begin
DecodeHuffman_38_temp_0_i_i4 = DecodeHuffman_38_temp_0_in_i_i3;
end
end
always @(*) begin
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5 = DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB13_39) */
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5 = DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5_reg <= DecodeHuffman_pgetc_exit_i6__0_i_i5;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i6__0_i_i5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i6__0_i_i5_reg"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5_reg <= DecodeHuffman_pgetc_exit_i6__0_i_i5;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i6__0_i_i5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i6__0_i_i5_reg"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5_reg <= DecodeHuffman_pgetc_exit_i6__0_i_i5;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i6__0_i_i5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i6__0_i_i5_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39 = DecodeHuffman_buf_getb_exit9_39_phi_temp;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
else if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39 = DecodeHuffman_buf_getb_exit9_39_phi_temp;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB14_41) */
begin
DecodeHuffman_buf_getb_exit9_39 = DecodeHuffman_buf_getb_exit9_39_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39_reg <= DecodeHuffman_buf_getb_exit9_39;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39_reg <= DecodeHuffman_buf_getb_exit9_39;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39_reg <= DecodeHuffman_buf_getb_exit9_39;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39_reg <= DecodeHuffman_buf_getb_exit9_39;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %40 = phi i32 [ 7, %pgetc.exit.i6 ], [ %24, %.lr.ph ]*/
begin
DecodeHuffman_buf_getb_exit9_40 = DecodeHuffman_buf_getb_exit9_40_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %41 = add nsw i32 %40, -1*/
begin
DecodeHuffman_buf_getb_exit9_41 = DecodeHuffman_buf_getb_exit9_40 + -32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %41 = add nsw i32 %40, -1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_41_reg <= DecodeHuffman_buf_getb_exit9_41;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_41_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %42 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %40*/
begin
DecodeHuffman_buf_getb_exit9_42 = `TAG_g_bit_set_mask_a + 4 * DecodeHuffman_buf_getb_exit9_40;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %42 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %40*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_42_reg <= DecodeHuffman_buf_getb_exit9_42;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_42_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %43 = load i32* %42, align 4, !tbaa !0*/
begin
DecodeHuffman_buf_getb_exit9_43 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %44 = and i32 %43, %39*/
begin
DecodeHuffman_buf_getb_exit9_44 = DecodeHuffman_buf_getb_exit9_43 & DecodeHuffman_buf_getb_exit9_39_reg;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %not..i7 = icmp ne i32 %44, 0*/
begin
DecodeHuffman_buf_getb_exit9_not__i7 = DecodeHuffman_buf_getb_exit9_44 != 32'd0;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %..i8 = zext i1 %not..i7 to i32*/
begin
DecodeHuffman_buf_getb_exit9___i8 = DecodeHuffman_buf_getb_exit9_not__i7;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %45 = or i32 %..i8, %25*/
begin
DecodeHuffman_buf_getb_exit9_45 = DecodeHuffman_buf_getb_exit9___i8 | DecodeHuffman__lr_ph_25_reg;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %45 = or i32 %..i8, %25*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_44)
begin
DecodeHuffman_buf_getb_exit9_45_reg <= DecodeHuffman_buf_getb_exit9_45;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_45_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %46 = load i32* %scevgep, align 4, !tbaa !0*/
begin
DecodeHuffman_buf_getb_exit9_46 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %47 = icmp sgt i32 %45, %46*/
begin
DecodeHuffman_buf_getb_exit9_47 = $signed(DecodeHuffman_buf_getb_exit9_45_reg) > $signed(DecodeHuffman_buf_getb_exit9_46);
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %indvar.next = add i32 %indvar, 1*/
begin
DecodeHuffman_buf_getb_exit9_indvar_next = DecodeHuffman__lr_ph_indvar_reg + 32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %indvar.next = add i32 %indvar, 1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_indvar_next_reg <= DecodeHuffman_buf_getb_exit9_indvar_next;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_indvar_next) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_indvar_next_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa = DecodeHuffman___crit_edge_l_0_lcssa_phi_temp;
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
else if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa = DecodeHuffman___crit_edge_l_0_lcssa_phi_temp;
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB15_46) */
begin
DecodeHuffman___crit_edge_l_0_lcssa = DecodeHuffman___crit_edge_l_0_lcssa_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa_reg <= DecodeHuffman___crit_edge_l_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_l_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa_reg <= DecodeHuffman___crit_edge_l_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_l_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa_reg <= DecodeHuffman___crit_edge_l_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_l_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa_reg <= DecodeHuffman___crit_edge_l_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_l_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa = DecodeHuffman___crit_edge_code_0_lcssa_phi_temp;
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
else if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa = DecodeHuffman___crit_edge_code_0_lcssa_phi_temp;
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB15_46) */
begin
DecodeHuffman___crit_edge_code_0_lcssa = DecodeHuffman___crit_edge_code_0_lcssa_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa_reg <= DecodeHuffman___crit_edge_code_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_code_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa_reg <= DecodeHuffman___crit_edge_code_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_code_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa_reg <= DecodeHuffman___crit_edge_code_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_code_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa_reg <= DecodeHuffman___crit_edge_code_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_code_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge*/
/* %48 = getelementptr inbounds i32* %Dhuff_maxcode, i32 %Dhuff_ml*/
begin
DecodeHuffman___crit_edge_48 = arg_Dhuff_maxcode + 4 * arg_Dhuff_ml;
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge*/
/* %49 = load i32* %48, align 4, !tbaa !0*/
begin
DecodeHuffman___crit_edge_49 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge*/
/* %50 = icmp slt i32 %code.0.lcssa, %49*/
begin
DecodeHuffman___crit_edge_50 = $signed(DecodeHuffman___crit_edge_code_0_lcssa_reg) < $signed(DecodeHuffman___crit_edge_49);
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %52 = load i32* @main_result, align 4, !tbaa !0*/
begin
DecodeHuffman_51_52 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %53 = add nsw i32 %52, 1*/
begin
DecodeHuffman_51_53 = DecodeHuffman_51_52 + 32'd1;
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %54 = getelementptr inbounds i32* %Dhuff_valptr, i32 %l.0.lcssa*/
begin
DecodeHuffman_51_54 = arg_Dhuff_valptr + 4 * DecodeHuffman___crit_edge_l_0_lcssa_reg;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %51*/
/* %54 = getelementptr inbounds i32* %Dhuff_valptr, i32 %l.0.lcssa*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
DecodeHuffman_51_54_reg <= DecodeHuffman_51_54;
if (^reset !== 1'bX && ^(DecodeHuffman_51_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_51_54_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %55 = load i32* %54, align 4, !tbaa !0*/
begin
DecodeHuffman_51_55 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %56 = getelementptr inbounds i32* %Dhuff_mincode, i32 %l.0.lcssa*/
begin
DecodeHuffman_51_56 = arg_Dhuff_mincode + 4 * DecodeHuffman___crit_edge_l_0_lcssa_reg;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %51*/
/* %56 = getelementptr inbounds i32* %Dhuff_mincode, i32 %l.0.lcssa*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
DecodeHuffman_51_56_reg <= DecodeHuffman_51_56;
if (^reset !== 1'bX && ^(DecodeHuffman_51_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_51_56_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %57 = load i32* %56, align 4, !tbaa !0*/
begin
DecodeHuffman_51_57 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %58 = add i32 %55, %code.0.lcssa*/
begin
DecodeHuffman_51_58 = DecodeHuffman_51_55 + DecodeHuffman___crit_edge_code_0_lcssa_reg;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %51*/
/* %58 = add i32 %55, %code.0.lcssa*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_54)
begin
DecodeHuffman_51_58_reg <= DecodeHuffman_51_58;
if (^reset !== 1'bX && ^(DecodeHuffman_51_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_51_58_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %59 = sub i32 %58, %57*/
begin
DecodeHuffman_51_59 = DecodeHuffman_51_58_reg - DecodeHuffman_51_57;
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %60 = getelementptr inbounds i32* %Xhuff_huffval, i32 %59*/
begin
DecodeHuffman_51_60 = arg_Xhuff_huffval + 4 * DecodeHuffman_51_59;
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %61 = load i32* %60, align 4, !tbaa !0*/
begin
DecodeHuffman_51_61 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_6 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit_15_phi_temp <= DecodeHuffman___crit_edge_i__pre_i;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_i__pre_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_phi_temp"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit_15_phi_temp <= DecodeHuffman_pgetc_exit_i__0_i_i_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i__0_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %16 = phi i32 [ 7, %pgetc.exit.i ], [ %1, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_6 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit_16_phi_temp <= DecodeHuffman_0_1_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_0_1_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_16_phi_temp"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit*/
/* %16 = phi i32 [ 7, %pgetc.exit.i ], [ %1, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit_16_phi_temp <= 32'd7;
if (^reset !== 1'bX && ^(32'd7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_16_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %14*/
/* %temp.0.in.i.i = phi i8 [ %10, %12 ], [ %6, %3 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_12 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_3_7 == 1'd0)
begin
DecodeHuffman_14_temp_0_in_i_i_phi_temp <= DecodeHuffman_3_6;
if (^reset !== 1'bX && ^(DecodeHuffman_3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_14_temp_0_in_i_i_phi_temp"); $finish; end
end
/* DecodeHuffman: %14*/
/* %temp.0.in.i.i = phi i8 [ %10, %12 ], [ %6, %3 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB4_17 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_14_temp_0_in_i_i_phi_temp <= DecodeHuffman_8_10_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_8_10_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_14_temp_0_in_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_16 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_8_11 == 1'd1)
begin
DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB5_18 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp <= DecodeHuffman_14_temp_0_i_i;
if (^reset !== 1'bX && ^(DecodeHuffman_14_temp_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %.pre.i1 = phi i32 [ %39, %buf_getb.exit9 ], [ %15, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd1)
begin
DecodeHuffman__lr_ph__pre_i1_phi_temp <= DecodeHuffman_buf_getb_exit_15_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_15_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph__pre_i1_phi_temp"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %.pre.i1 = phi i32 [ %39, %buf_getb.exit9 ], [ %15, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd1)
begin
DecodeHuffman__lr_ph__pre_i1_phi_temp <= DecodeHuffman_buf_getb_exit9_39_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_39_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph__pre_i1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %24 = phi i32 [ %41, %buf_getb.exit9 ], [ %17, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd1)
begin
DecodeHuffman__lr_ph_24_phi_temp <= DecodeHuffman_buf_getb_exit_17_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_17_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_24_phi_temp"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %24 = phi i32 [ %41, %buf_getb.exit9 ], [ %17, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd1)
begin
DecodeHuffman__lr_ph_24_phi_temp <= DecodeHuffman_buf_getb_exit9_41_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_41_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_24_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd1)
begin
DecodeHuffman__lr_ph_indvar_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_indvar_phi_temp"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd1)
begin
DecodeHuffman__lr_ph_indvar_phi_temp <= DecodeHuffman_buf_getb_exit9_indvar_next_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_indvar_next_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_indvar_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %code.010 = phi i32 [ %45, %buf_getb.exit9 ], [ %..i, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd1)
begin
DecodeHuffman__lr_ph_code_010_phi_temp <= DecodeHuffman_buf_getb_exit___i_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit___i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_code_010_phi_temp"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %code.010 = phi i32 [ %45, %buf_getb.exit9 ], [ %..i, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd1)
begin
DecodeHuffman__lr_ph_code_010_phi_temp <= DecodeHuffman_buf_getb_exit9_45_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_45_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_code_010_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd0)
begin
DecodeHuffman___crit_edge_l_0_lcssa_phi_temp <= 32'd1;
if (^reset !== 1'bX && ^(32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_phi_temp"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd0)
begin
DecodeHuffman___crit_edge_l_0_lcssa_phi_temp <= DecodeHuffman__lr_ph_tmp_reg;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_tmp_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd0)
begin
DecodeHuffman___crit_edge_code_0_lcssa_phi_temp <= DecodeHuffman_buf_getb_exit___i_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit___i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_phi_temp"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd0)
begin
DecodeHuffman___crit_edge_code_0_lcssa_phi_temp <= DecodeHuffman_buf_getb_exit9_45_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_45_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman__lr_ph_26 == 1'd0)
begin
DecodeHuffman_buf_getb_exit9_39_phi_temp <= DecodeHuffman__lr_ph__pre_i1;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph__pre_i1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_phi_temp"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit9_39_phi_temp <= DecodeHuffman_pgetc_exit_i6__0_i_i5_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i6__0_i_i5_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %40 = phi i32 [ 7, %pgetc.exit.i6 ], [ %24, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman__lr_ph_26 == 1'd0)
begin
DecodeHuffman_buf_getb_exit9_40_phi_temp <= DecodeHuffman__lr_ph_24;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_40_phi_temp"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %40 = phi i32 [ 7, %pgetc.exit.i6 ], [ %24, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit9_40_phi_temp <= 32'd7;
if (^reset !== 1'bX && ^(32'd7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_40_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %38*/
/* %temp.0.in.i.i3 = phi i8 [ %34, %36 ], [ %30, %27 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_32 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_27_31 == 1'd0)
begin
DecodeHuffman_38_temp_0_in_i_i3_phi_temp <= DecodeHuffman_27_30;
if (^reset !== 1'bX && ^(DecodeHuffman_27_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_38_temp_0_in_i_i3_phi_temp"); $finish; end
end
/* DecodeHuffman: %38*/
/* %temp.0.in.i.i3 = phi i8 [ %34, %36 ], [ %30, %27 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB11_37 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_38_temp_0_in_i_i3_phi_temp <= DecodeHuffman_32_34_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_32_34_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_38_temp_0_in_i_i3_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_36 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_32_35 == 1'd1)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB12_38 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp <= DecodeHuffman_38_temp_0_i_i4;
if (^reset !== 1'bX && ^(DecodeHuffman_38_temp_0_i_i4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* DecodeHuffman: %51*/
/* ret i32 %61*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_57)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
return_val <= 0;
if (^reset !== 1'bX && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
/* DecodeHuffman: %51*/
/* ret i32 %61*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_57)
begin
return_val <= DecodeHuffman_51_61;
if (^reset !== 1'bX && ^(DecodeHuffman_51_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* DecodeHuffman: %._crit_edge.i*/
/* %.pre.i = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %3*/
/* store i8* %5, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %3*/
/* %6 = load i8* %4, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10)
begin
memory_controller_address = DecodeHuffman_3_4_reg;
end
/* DecodeHuffman: %8*/
/* store i8* %9, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14)
begin
memory_controller_address = DecodeHuffman_3_5_reg;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 %.0.i.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* DecodeHuffman: %buf_getb.exit*/
/* store i32 %17, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %19 = load i32* %18, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22)
begin
memory_controller_address = DecodeHuffman_buf_getb_exit_18_reg;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %22 = load i32* %21, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23)
begin
memory_controller_address = DecodeHuffman_buf_getb_exit_21_reg;
end
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %27*/
/* store i8* %29, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %27*/
/* %30 = load i8* %28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30)
begin
memory_controller_address = DecodeHuffman_27_28_reg;
end
/* DecodeHuffman: %32*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34)
begin
memory_controller_address = DecodeHuffman_27_29_reg;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 %.0.i.i5, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* store i32 %41, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %43 = load i32* %42, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42)
begin
memory_controller_address = DecodeHuffman_buf_getb_exit9_42_reg;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %46 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43)
begin
memory_controller_address = DecodeHuffman__lr_ph_scevgep_reg;
end
/* DecodeHuffman: %._crit_edge*/
/* %49 = load i32* %48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
memory_controller_address = DecodeHuffman___crit_edge_48;
end
/* DecodeHuffman: %51*/
/* %52 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* DecodeHuffman: %51*/
/* store i32 %53, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* DecodeHuffman: %51*/
/* %55 = load i32* %54, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52)
begin
memory_controller_address = DecodeHuffman_51_54_reg;
end
/* DecodeHuffman: %51*/
/* %57 = load i32* %56, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53)
begin
memory_controller_address = DecodeHuffman_51_56_reg;
end
/* DecodeHuffman: %51*/
/* %61 = load i32* %60, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55)
begin
memory_controller_address = DecodeHuffman_51_60;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %._crit_edge.i*/
/* %.pre.i = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %3*/
/* store i8* %5, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %3*/
/* %6 = load i8* %4, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %8*/
/* store i8* %9, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 %.0.i.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit*/
/* store i32 %17, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %19 = load i32* %18, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %22 = load i32* %21, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %27*/
/* store i8* %29, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %27*/
/* %30 = load i8* %28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %32*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 %.0.i.i5, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* store i32 %41, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %43 = load i32* %42, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %46 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %._crit_edge*/
/* %49 = load i32* %48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* %52 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* store i32 %53, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* %55 = load i32* %54, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* %57 = load i32* %56, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* %61 = load i32* %60, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %._crit_edge.i*/
/* %.pre.i = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %3*/
/* store i8* %5, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %3*/
/* %6 = load i8* %4, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %8*/
/* store i8* %9, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 %.0.i.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit*/
/* store i32 %17, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %19 = load i32* %18, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %22 = load i32* %21, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %27*/
/* store i8* %29, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %27*/
/* %30 = load i8* %28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %32*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 %.0.i.i5, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* store i32 %41, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %43 = load i32* %42, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %46 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %._crit_edge*/
/* %49 = load i32* %48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %51*/
/* %52 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %51*/
/* store i32 %53, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* %55 = load i32* %54, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %51*/
/* %57 = load i32* %56, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %51*/
/* %61 = load i32* %60, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55)
begin
memory_controller_write_enable = 1'd0;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* DecodeHuffman: %3*/
/* store i8* %5, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
memory_controller_in = DecodeHuffman_3_5;
end
/* DecodeHuffman: %8*/
/* store i8* %9, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13)
begin
memory_controller_in = DecodeHuffman_8_9;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 %.0.i.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
memory_controller_in = DecodeHuffman_pgetc_exit_i__0_i_i;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20)
begin
memory_controller_in = 32'd7;
end
/* DecodeHuffman: %buf_getb.exit*/
/* store i32 %17, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
memory_controller_in = DecodeHuffman_buf_getb_exit_17;
end
/* DecodeHuffman: %27*/
/* store i8* %29, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
memory_controller_in = DecodeHuffman_27_29;
end
/* DecodeHuffman: %32*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33)
begin
memory_controller_in = DecodeHuffman_32_33;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 %.0.i.i5, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
memory_controller_in = DecodeHuffman_pgetc_exit_i6__0_i_i5;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40)
begin
memory_controller_in = 32'd7;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* store i32 %41, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
memory_controller_in = DecodeHuffman_buf_getb_exit9_41;
end
/* DecodeHuffman: %51*/
/* store i32 %53, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51)
begin
memory_controller_in = DecodeHuffman_51_53;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %._crit_edge.i*/
/* %.pre.i = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %3*/
/* store i8* %5, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %3*/
/* %6 = load i8* %4, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10)
begin
memory_controller_size = 2'd0;
end
/* DecodeHuffman: %8*/
/* store i8* %9, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14)
begin
memory_controller_size = 2'd0;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 %.0.i.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit*/
/* store i32 %17, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %19 = load i32* %18, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %22 = load i32* %21, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %27*/
/* store i8* %29, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %27*/
/* %30 = load i8* %28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30)
begin
memory_controller_size = 2'd0;
end
/* DecodeHuffman: %32*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34)
begin
memory_controller_size = 2'd0;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 %.0.i.i5, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* store i32 %41, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %43 = load i32* %42, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %46 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %._crit_edge*/
/* %49 = load i32* %48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %51*/
/* %52 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %51*/
/* store i32 %53, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %51*/
/* %55 = load i32* %54, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %51*/
/* %57 = load i32* %56, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %51*/
/* %61 = load i32* %60, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module main
(
clk,
reset,
start,
finish,
return_val,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [8:0] LEGUP_0 = 9'd0;
parameter [8:0] LEGUP_F_main_BB0_1 = 9'd1;
parameter [8:0] LEGUP_F_main_BB1_2 = 9'd2;
parameter [8:0] LEGUP_F_main_BB1_3 = 9'd3;
parameter [8:0] LEGUP_F_main_BB1_4 = 9'd4;
parameter [8:0] LEGUP_F_main_BB2_5 = 9'd5;
parameter [8:0] LEGUP_F_main_BB3_6 = 9'd6;
parameter [8:0] LEGUP_F_main_BB4_7 = 9'd7;
parameter [8:0] LEGUP_F_main_BB5_8 = 9'd8;
parameter [8:0] LEGUP_F_main_BB6_9 = 9'd9;
parameter [8:0] LEGUP_F_main_BB7_10 = 9'd10;
parameter [8:0] LEGUP_F_main_BB7_11 = 9'd11;
parameter [8:0] LEGUP_F_main_BB7_12 = 9'd12;
parameter [8:0] LEGUP_F_main_BB7_13 = 9'd13;
parameter [8:0] LEGUP_F_main_BB8_14 = 9'd14;
parameter [8:0] LEGUP_F_main_BB9_15 = 9'd15;
parameter [8:0] LEGUP_F_main_BB9_16 = 9'd16;
parameter [8:0] LEGUP_F_main_BB9_17 = 9'd17;
parameter [8:0] LEGUP_F_main_BB10_18 = 9'd18;
parameter [8:0] LEGUP_F_main_BB11_19 = 9'd19;
parameter [8:0] LEGUP_F_main_BB11_20 = 9'd20;
parameter [8:0] LEGUP_F_main_BB11_21 = 9'd21;
parameter [8:0] LEGUP_F_main_BB12_22 = 9'd22;
parameter [8:0] LEGUP_F_main_BB12_23 = 9'd23;
parameter [8:0] LEGUP_F_main_BB12_24 = 9'd24;
parameter [8:0] LEGUP_F_main_BB13_25 = 9'd25;
parameter [8:0] LEGUP_F_main_BB14_26 = 9'd26;
parameter [8:0] LEGUP_F_main_BB15_27 = 9'd27;
parameter [8:0] LEGUP_F_main_BB15_28 = 9'd28;
parameter [8:0] LEGUP_F_main_BB15_29 = 9'd29;
parameter [8:0] LEGUP_F_main_BB16_30 = 9'd30;
parameter [8:0] LEGUP_F_main_BB17_31 = 9'd31;
parameter [8:0] LEGUP_F_main_BB17_32 = 9'd32;
parameter [8:0] LEGUP_F_main_BB17_33 = 9'd33;
parameter [8:0] LEGUP_F_main_BB17_34 = 9'd34;
parameter [8:0] LEGUP_F_main_BB18_35 = 9'd35;
parameter [8:0] LEGUP_F_main_BB18_36 = 9'd36;
parameter [8:0] LEGUP_F_main_BB18_37 = 9'd37;
parameter [8:0] LEGUP_F_main_BB19_38 = 9'd38;
parameter [8:0] LEGUP_F_main_BB20_39 = 9'd39;
parameter [8:0] LEGUP_F_main_BB20_40 = 9'd40;
parameter [8:0] LEGUP_F_main_BB20_41 = 9'd41;
parameter [8:0] LEGUP_F_main_BB20_42 = 9'd42;
parameter [8:0] LEGUP_F_main_BB20_43 = 9'd43;
parameter [8:0] LEGUP_F_main_BB20_44 = 9'd44;
parameter [8:0] LEGUP_F_main_BB20_45 = 9'd45;
parameter [8:0] LEGUP_F_main_BB20_46 = 9'd46;
parameter [8:0] LEGUP_F_main_BB20_47 = 9'd47;
parameter [8:0] LEGUP_F_main_BB20_48 = 9'd48;
parameter [8:0] LEGUP_F_main_BB20_49 = 9'd49;
parameter [8:0] LEGUP_F_main_BB20_50 = 9'd50;
parameter [8:0] LEGUP_F_main_BB20_51 = 9'd51;
parameter [8:0] LEGUP_F_main_BB20_52 = 9'd52;
parameter [8:0] LEGUP_F_main_BB20_53 = 9'd53;
parameter [8:0] LEGUP_F_main_BB20_54 = 9'd54;
parameter [8:0] LEGUP_F_main_BB20_55 = 9'd55;
parameter [8:0] LEGUP_F_main_BB20_56 = 9'd56;
parameter [8:0] LEGUP_F_main_BB20_57 = 9'd57;
parameter [8:0] LEGUP_F_main_BB21_58 = 9'd58;
parameter [8:0] LEGUP_F_main_BB21_59 = 9'd59;
parameter [8:0] LEGUP_F_main_BB21_60 = 9'd60;
parameter [8:0] LEGUP_F_main_BB22_61 = 9'd61;
parameter [8:0] LEGUP_F_main_BB23_62 = 9'd62;
parameter [8:0] LEGUP_F_main_BB23_63 = 9'd63;
parameter [8:0] LEGUP_F_main_BB23_64 = 9'd64;
parameter [8:0] LEGUP_F_main_BB24_65 = 9'd65;
parameter [8:0] LEGUP_F_main_BB24_66 = 9'd66;
parameter [8:0] LEGUP_F_main_BB24_67 = 9'd67;
parameter [8:0] LEGUP_F_main_BB25_68 = 9'd68;
parameter [8:0] LEGUP_F_main_BB25_69 = 9'd69;
parameter [8:0] LEGUP_F_main_BB25_70 = 9'd70;
parameter [8:0] LEGUP_F_main_BB26_71 = 9'd71;
parameter [8:0] LEGUP_F_main_BB26_72 = 9'd72;
parameter [8:0] LEGUP_F_main_BB26_73 = 9'd73;
parameter [8:0] LEGUP_F_main_BB27_74 = 9'd74;
parameter [8:0] LEGUP_F_main_BB27_75 = 9'd75;
parameter [8:0] LEGUP_F_main_BB27_76 = 9'd76;
parameter [8:0] LEGUP_F_main_BB28_77 = 9'd77;
parameter [8:0] LEGUP_F_main_BB29_78 = 9'd78;
parameter [8:0] LEGUP_F_main_BB29_79 = 9'd79;
parameter [8:0] LEGUP_F_main_BB29_80 = 9'd80;
parameter [8:0] LEGUP_F_main_BB30_81 = 9'd81;
parameter [8:0] LEGUP_F_main_BB31_82 = 9'd82;
parameter [8:0] LEGUP_F_main_BB31_83 = 9'd83;
parameter [8:0] LEGUP_F_main_BB31_84 = 9'd84;
parameter [8:0] LEGUP_F_main_BB31_85 = 9'd85;
parameter [8:0] LEGUP_F_main_BB31_86 = 9'd86;
parameter [8:0] LEGUP_F_main_BB31_87 = 9'd87;
parameter [8:0] LEGUP_F_main_BB31_88 = 9'd88;
parameter [8:0] LEGUP_F_main_BB31_89 = 9'd89;
parameter [8:0] LEGUP_F_main_BB31_90 = 9'd90;
parameter [8:0] LEGUP_F_main_BB31_91 = 9'd91;
parameter [8:0] LEGUP_F_main_BB31_92 = 9'd92;
parameter [8:0] LEGUP_F_main_BB31_93 = 9'd93;
parameter [8:0] LEGUP_F_main_BB31_94 = 9'd94;
parameter [8:0] LEGUP_F_main_BB31_95 = 9'd95;
parameter [8:0] LEGUP_F_main_BB31_96 = 9'd96;
parameter [8:0] LEGUP_F_main_BB31_97 = 9'd97;
parameter [8:0] LEGUP_F_main_BB31_98 = 9'd98;
parameter [8:0] LEGUP_F_main_BB31_99 = 9'd99;
parameter [8:0] LEGUP_F_main_BB31_100 = 9'd100;
parameter [8:0] LEGUP_F_main_BB31_101 = 9'd101;
parameter [8:0] LEGUP_F_main_BB31_102 = 9'd102;
parameter [8:0] LEGUP_F_main_BB31_103 = 9'd103;
parameter [8:0] LEGUP_F_main_BB31_104 = 9'd104;
parameter [8:0] LEGUP_F_main_BB31_105 = 9'd105;
parameter [8:0] LEGUP_F_main_BB31_106 = 9'd106;
parameter [8:0] LEGUP_F_main_BB31_107 = 9'd107;
parameter [8:0] LEGUP_F_main_BB31_108 = 9'd108;
parameter [8:0] LEGUP_F_main_BB32_109 = 9'd109;
parameter [8:0] LEGUP_F_main_BB32_110 = 9'd110;
parameter [8:0] LEGUP_F_main_BB32_111 = 9'd111;
parameter [8:0] LEGUP_F_main_BB33_112 = 9'd112;
parameter [8:0] LEGUP_F_main_BB33_113 = 9'd113;
parameter [8:0] LEGUP_F_main_BB33_114 = 9'd114;
parameter [8:0] LEGUP_F_main_BB33_115 = 9'd115;
parameter [8:0] LEGUP_F_main_BB34_116 = 9'd116;
parameter [8:0] LEGUP_F_main_BB34_117 = 9'd117;
parameter [8:0] LEGUP_F_main_BB34_118 = 9'd118;
parameter [8:0] LEGUP_F_main_BB35_119 = 9'd119;
parameter [8:0] LEGUP_F_main_BB35_120 = 9'd120;
parameter [8:0] LEGUP_F_main_BB35_121 = 9'd121;
parameter [8:0] LEGUP_F_main_BB35_122 = 9'd122;
parameter [8:0] LEGUP_F_main_BB36_123 = 9'd123;
parameter [8:0] LEGUP_F_main_BB36_124 = 9'd124;
parameter [8:0] LEGUP_F_main_BB36_125 = 9'd125;
parameter [8:0] LEGUP_F_main_BB37_126 = 9'd126;
parameter [8:0] LEGUP_F_main_BB37_127 = 9'd127;
parameter [8:0] LEGUP_F_main_BB37_128 = 9'd128;
parameter [8:0] LEGUP_F_main_BB38_129 = 9'd129;
parameter [8:0] LEGUP_F_main_BB38_130 = 9'd130;
parameter [8:0] LEGUP_F_main_BB38_131 = 9'd131;
parameter [8:0] LEGUP_F_main_BB39_132 = 9'd132;
parameter [8:0] LEGUP_F_main_BB39_133 = 9'd133;
parameter [8:0] LEGUP_F_main_BB39_134 = 9'd134;
parameter [8:0] LEGUP_F_main_BB39_135 = 9'd135;
parameter [8:0] LEGUP_F_main_BB40_136 = 9'd136;
parameter [8:0] LEGUP_F_main_BB40_137 = 9'd137;
parameter [8:0] LEGUP_F_main_BB40_138 = 9'd138;
parameter [8:0] LEGUP_F_main_BB41_139 = 9'd139;
parameter [8:0] LEGUP_F_main_BB42_140 = 9'd140;
parameter [8:0] LEGUP_F_main_BB42_141 = 9'd141;
parameter [8:0] LEGUP_F_main_BB42_142 = 9'd142;
parameter [8:0] LEGUP_F_main_BB43_143 = 9'd143;
parameter [8:0] LEGUP_F_main_BB44_144 = 9'd144;
parameter [8:0] LEGUP_F_main_BB45_145 = 9'd145;
parameter [8:0] LEGUP_F_main_BB45_146 = 9'd146;
parameter [8:0] LEGUP_F_main_BB45_147 = 9'd147;
parameter [8:0] LEGUP_F_main_BB45_148 = 9'd148;
parameter [8:0] LEGUP_F_main_BB45_149 = 9'd149;
parameter [8:0] LEGUP_F_main_BB46_150 = 9'd150;
parameter [8:0] LEGUP_F_main_BB46_151 = 9'd151;
parameter [8:0] LEGUP_F_main_BB46_152 = 9'd152;
parameter [8:0] LEGUP_F_main_BB47_153 = 9'd153;
parameter [8:0] LEGUP_F_main_BB48_154 = 9'd154;
parameter [8:0] LEGUP_F_main_BB48_155 = 9'd155;
parameter [8:0] LEGUP_F_main_BB48_156 = 9'd156;
parameter [8:0] LEGUP_F_main_BB49_157 = 9'd157;
parameter [8:0] LEGUP_F_main_BB50_158 = 9'd158;
parameter [8:0] LEGUP_F_main_BB51_159 = 9'd159;
parameter [8:0] LEGUP_F_main_BB51_160 = 9'd160;
parameter [8:0] LEGUP_F_main_BB51_161 = 9'd161;
parameter [8:0] LEGUP_F_main_BB51_162 = 9'd162;
parameter [8:0] LEGUP_F_main_BB52_163 = 9'd163;
parameter [8:0] LEGUP_F_main_BB53_164 = 9'd164;
parameter [8:0] LEGUP_F_main_BB53_165 = 9'd165;
parameter [8:0] LEGUP_F_main_BB53_166 = 9'd166;
parameter [8:0] LEGUP_F_main_BB54_167 = 9'd167;
parameter [8:0] LEGUP_F_main_BB55_168 = 9'd168;
parameter [8:0] LEGUP_F_main_BB56_169 = 9'd169;
parameter [8:0] LEGUP_F_main_BB56_170 = 9'd170;
parameter [8:0] LEGUP_F_main_BB56_171 = 9'd171;
parameter [8:0] LEGUP_F_main_BB56_172 = 9'd172;
parameter [8:0] LEGUP_F_main_BB56_173 = 9'd173;
parameter [8:0] LEGUP_F_main_BB56_174 = 9'd174;
parameter [8:0] LEGUP_F_main_BB56_175 = 9'd175;
parameter [8:0] LEGUP_F_main_BB56_176 = 9'd176;
parameter [8:0] LEGUP_F_main_BB56_177 = 9'd177;
parameter [8:0] LEGUP_F_main_BB56_178 = 9'd178;
parameter [8:0] LEGUP_F_main_BB56_179 = 9'd179;
parameter [8:0] LEGUP_F_main_BB56_180 = 9'd180;
parameter [8:0] LEGUP_F_main_BB56_181 = 9'd181;
parameter [8:0] LEGUP_F_main_BB56_182 = 9'd182;
parameter [8:0] LEGUP_F_main_BB57_183 = 9'd183;
parameter [8:0] LEGUP_F_main_BB57_184 = 9'd184;
parameter [8:0] LEGUP_F_main_BB57_185 = 9'd185;
parameter [8:0] LEGUP_F_main_BB58_186 = 9'd186;
parameter [8:0] LEGUP_F_main_BB58_187 = 9'd187;
parameter [8:0] LEGUP_F_main_BB58_188 = 9'd188;
parameter [8:0] LEGUP_F_main_BB58_189 = 9'd189;
parameter [8:0] LEGUP_F_main_BB59_190 = 9'd190;
parameter [8:0] LEGUP_F_main_BB59_191 = 9'd191;
parameter [8:0] LEGUP_F_main_BB59_192 = 9'd192;
parameter [8:0] LEGUP_F_main_BB60_193 = 9'd193;
parameter [8:0] LEGUP_F_main_BB60_194 = 9'd194;
parameter [8:0] LEGUP_F_main_BB60_195 = 9'd195;
parameter [8:0] LEGUP_F_main_BB61_196 = 9'd196;
parameter [8:0] LEGUP_F_main_BB61_197 = 9'd197;
parameter [8:0] LEGUP_F_main_BB61_198 = 9'd198;
parameter [8:0] LEGUP_F_main_BB62_199 = 9'd199;
parameter [8:0] LEGUP_F_main_BB63_200 = 9'd200;
parameter [8:0] LEGUP_F_main_BB64_201 = 9'd201;
parameter [8:0] LEGUP_F_main_BB64_202 = 9'd202;
parameter [8:0] LEGUP_F_main_BB64_203 = 9'd203;
parameter [8:0] LEGUP_F_main_BB64_204 = 9'd204;
parameter [8:0] LEGUP_F_main_BB64_205 = 9'd205;
parameter [8:0] LEGUP_F_main_BB64_206 = 9'd206;
parameter [8:0] LEGUP_F_main_BB64_207 = 9'd207;
parameter [8:0] LEGUP_F_main_BB65_208 = 9'd208;
parameter [8:0] LEGUP_F_main_BB65_209 = 9'd209;
parameter [8:0] LEGUP_F_main_BB65_210 = 9'd210;
parameter [8:0] LEGUP_F_main_BB66_211 = 9'd211;
parameter [8:0] LEGUP_F_main_BB67_212 = 9'd212;
parameter [8:0] LEGUP_F_main_BB67_213 = 9'd213;
parameter [8:0] LEGUP_F_main_BB67_214 = 9'd214;
parameter [8:0] LEGUP_F_main_BB67_215 = 9'd215;
parameter [8:0] LEGUP_F_main_BB67_216 = 9'd216;
parameter [8:0] LEGUP_F_main_BB67_217 = 9'd217;
parameter [8:0] LEGUP_F_main_BB68_218 = 9'd218;
parameter [8:0] LEGUP_F_main_BB68_219 = 9'd219;
parameter [8:0] LEGUP_F_main_BB68_220 = 9'd220;
parameter [8:0] LEGUP_F_main_BB69_221 = 9'd221;
parameter [8:0] LEGUP_F_main_BB70_222 = 9'd222;
parameter [8:0] LEGUP_F_main_BB71_223 = 9'd223;
parameter [8:0] LEGUP_F_main_BB72_224 = 9'd224;
parameter [8:0] LEGUP_F_main_BB73_225 = 9'd225;
parameter [8:0] LEGUP_F_main_BB73_226 = 9'd226;
parameter [8:0] LEGUP_F_main_BB73_227 = 9'd227;
parameter [8:0] LEGUP_F_main_BB74_228 = 9'd228;
parameter [8:0] LEGUP_F_main_BB74_229 = 9'd229;
parameter [8:0] LEGUP_F_main_BB74_230 = 9'd230;
parameter [8:0] LEGUP_F_main_BB74_231 = 9'd231;
parameter [8:0] LEGUP_F_main_BB75_232 = 9'd232;
parameter [8:0] LEGUP_F_main_BB75_233 = 9'd233;
parameter [8:0] LEGUP_F_main_BB75_234 = 9'd234;
parameter [8:0] LEGUP_F_main_BB76_235 = 9'd235;
parameter [8:0] LEGUP_F_main_BB77_236 = 9'd236;
parameter [8:0] LEGUP_F_main_BB77_237 = 9'd237;
parameter [8:0] LEGUP_F_main_BB77_238 = 9'd238;
parameter [8:0] LEGUP_F_main_BB78_239 = 9'd239;
parameter [8:0] LEGUP_F_main_BB79_240 = 9'd240;
parameter [8:0] LEGUP_F_main_BB79_241 = 9'd241;
parameter [8:0] LEGUP_F_main_BB79_242 = 9'd242;
parameter [8:0] LEGUP_F_main_BB79_243 = 9'd243;
parameter [8:0] LEGUP_F_main_BB79_244 = 9'd244;
parameter [8:0] LEGUP_F_main_BB79_245 = 9'd245;
parameter [8:0] LEGUP_F_main_BB79_246 = 9'd246;
parameter [8:0] LEGUP_F_main_BB80_247 = 9'd247;
parameter [8:0] LEGUP_F_main_BB80_248 = 9'd248;
parameter [8:0] LEGUP_F_main_BB80_249 = 9'd249;
parameter [8:0] LEGUP_F_main_BB81_250 = 9'd250;
parameter [8:0] LEGUP_F_main_BB82_251 = 9'd251;
parameter [8:0] LEGUP_F_main_BB82_252 = 9'd252;
parameter [8:0] LEGUP_F_main_BB82_253 = 9'd253;
parameter [8:0] LEGUP_F_main_BB82_254 = 9'd254;
parameter [8:0] LEGUP_F_main_BB82_255 = 9'd255;
parameter [8:0] LEGUP_F_main_BB82_256 = 9'd256;
parameter [8:0] LEGUP_F_main_BB83_257 = 9'd257;
parameter [8:0] LEGUP_F_main_BB83_258 = 9'd258;
parameter [8:0] LEGUP_F_main_BB83_259 = 9'd259;
parameter [8:0] LEGUP_F_main_BB84_260 = 9'd260;
parameter [8:0] LEGUP_F_main_BB84_261 = 9'd261;
parameter [8:0] LEGUP_F_main_BB84_262 = 9'd262;
parameter [8:0] LEGUP_F_main_BB85_263 = 9'd263;
parameter [8:0] LEGUP_F_main_BB85_264 = 9'd264;
parameter [8:0] LEGUP_F_main_BB85_265 = 9'd265;
parameter [8:0] LEGUP_F_main_BB86_266 = 9'd266;
parameter [8:0] LEGUP_F_main_BB87_267 = 9'd267;
parameter [8:0] LEGUP_F_main_BB87_268 = 9'd268;
parameter [8:0] LEGUP_F_main_BB87_269 = 9'd269;
parameter [8:0] LEGUP_F_main_BB87_270 = 9'd270;
parameter [8:0] LEGUP_F_main_BB88_271 = 9'd271;
parameter [8:0] LEGUP_F_main_BB88_272 = 9'd272;
parameter [8:0] LEGUP_F_main_BB88_273 = 9'd273;
parameter [8:0] LEGUP_F_main_BB88_274 = 9'd274;
parameter [8:0] LEGUP_F_main_BB88_275 = 9'd275;
parameter [8:0] LEGUP_F_main_BB89_276 = 9'd276;
parameter [8:0] LEGUP_F_main_BB90_277 = 9'd277;
parameter [8:0] LEGUP_F_main_BB90_278 = 9'd278;
parameter [8:0] LEGUP_F_main_BB90_279 = 9'd279;
parameter [8:0] LEGUP_F_main_BB90_280 = 9'd280;
parameter [8:0] LEGUP_F_main_BB90_281 = 9'd281;
parameter [8:0] LEGUP_F_main_BB90_282 = 9'd282;
parameter [8:0] LEGUP_F_main_BB90_283 = 9'd283;
parameter [8:0] LEGUP_F_main_BB90_284 = 9'd284;
parameter [8:0] LEGUP_F_main_BB90_285 = 9'd285;
parameter [8:0] LEGUP_F_main_BB90_286 = 9'd286;
parameter [8:0] LEGUP_F_main_BB90_287 = 9'd287;
parameter [8:0] LEGUP_F_main_BB90_288 = 9'd288;
parameter [8:0] LEGUP_F_main_BB90_289 = 9'd289;
parameter [8:0] LEGUP_F_main_BB90_290 = 9'd290;
parameter [8:0] LEGUP_F_main_BB90_291 = 9'd291;
parameter [8:0] LEGUP_F_main_BB90_292 = 9'd292;
parameter [8:0] LEGUP_F_main_BB90_293 = 9'd293;
parameter [8:0] LEGUP_F_main_BB90_294 = 9'd294;
parameter [8:0] LEGUP_F_main_BB90_295 = 9'd295;
parameter [8:0] LEGUP_F_main_BB90_296 = 9'd296;
parameter [8:0] LEGUP_F_main_BB90_297 = 9'd297;
parameter [8:0] LEGUP_F_main_BB90_298 = 9'd298;
parameter [8:0] LEGUP_F_main_BB90_299 = 9'd299;
parameter [8:0] LEGUP_F_main_BB90_300 = 9'd300;
parameter [8:0] LEGUP_F_main_BB90_301 = 9'd301;
parameter [8:0] LEGUP_F_main_BB90_302 = 9'd302;
parameter [8:0] LEGUP_F_main_BB90_303 = 9'd303;
parameter [8:0] LEGUP_F_main_BB90_304 = 9'd304;
parameter [8:0] LEGUP_F_main_BB90_305 = 9'd305;
parameter [8:0] LEGUP_F_main_BB90_306 = 9'd306;
parameter [8:0] LEGUP_F_main_BB90_307 = 9'd307;
parameter [8:0] LEGUP_F_main_BB90_308 = 9'd308;
parameter [8:0] LEGUP_F_main_BB90_309 = 9'd309;
parameter [8:0] LEGUP_F_main_BB90_310 = 9'd310;
parameter [8:0] LEGUP_F_main_BB90_311 = 9'd311;
parameter [8:0] LEGUP_F_main_BB90_312 = 9'd312;
parameter [8:0] LEGUP_F_main_BB90_313 = 9'd313;
parameter [8:0] LEGUP_F_main_BB90_314 = 9'd314;
parameter [8:0] LEGUP_F_main_BB90_315 = 9'd315;
parameter [8:0] LEGUP_F_main_BB90_316 = 9'd316;
parameter [8:0] LEGUP_F_main_BB90_317 = 9'd317;
parameter [8:0] LEGUP_F_main_BB90_318 = 9'd318;
parameter [8:0] LEGUP_F_main_BB90_319 = 9'd319;
parameter [8:0] LEGUP_F_main_BB90_320 = 9'd320;
parameter [8:0] LEGUP_F_main_BB90_321 = 9'd321;
parameter [8:0] LEGUP_F_main_BB90_322 = 9'd322;
parameter [8:0] LEGUP_F_main_BB90_323 = 9'd323;
parameter [8:0] LEGUP_F_main_BB90_324 = 9'd324;
parameter [8:0] LEGUP_F_main_BB90_325 = 9'd325;
parameter [8:0] LEGUP_F_main_BB90_326 = 9'd326;
parameter [8:0] LEGUP_F_main_BB90_327 = 9'd327;
parameter [8:0] LEGUP_F_main_BB90_328 = 9'd328;
parameter [8:0] LEGUP_F_main_BB90_329 = 9'd329;
parameter [8:0] LEGUP_F_main_BB90_332 = 9'd332;
parameter [8:0] LEGUP_F_main_BB90_333 = 9'd333;
parameter [8:0] LEGUP_F_main_BB90_336 = 9'd336;
parameter [8:0] LEGUP_F_main_BB90_337 = 9'd337;
parameter [8:0] LEGUP_F_main_BB90_340 = 9'd340;
parameter [8:0] LEGUP_F_main_BB90_341 = 9'd341;
parameter [8:0] LEGUP_F_main_BB90_344 = 9'd344;
parameter [8:0] LEGUP_F_main_BB90_345 = 9'd345;
parameter [8:0] LEGUP_F_main_BB90_346 = 9'd346;
parameter [8:0] LEGUP_F_main_BB90_347 = 9'd347;
parameter [8:0] LEGUP_F_main_BB90_348 = 9'd348;
parameter [8:0] LEGUP_F_main_BB90_349 = 9'd349;
parameter [8:0] LEGUP_F_main_BB90_350 = 9'd350;
parameter [8:0] LEGUP_F_main_BB90_351 = 9'd351;
parameter [8:0] LEGUP_F_main_BB90_352 = 9'd352;
parameter [8:0] LEGUP_F_main_BB90_353 = 9'd353;
parameter [8:0] LEGUP_F_main_BB90_354 = 9'd354;
parameter [8:0] LEGUP_F_main_BB91_355 = 9'd355;
parameter [8:0] LEGUP_F_main_BB92_356 = 9'd356;
parameter [8:0] LEGUP_F_main_BB93_357 = 9'd357;
parameter [8:0] LEGUP_F_main_BB93_360 = 9'd360;
parameter [8:0] LEGUP_F_main_BB93_363 = 9'd363;
parameter [8:0] LEGUP_F_main_BB94_366 = 9'd366;
parameter [8:0] LEGUP_F_main_BB94_367 = 9'd367;
parameter [8:0] LEGUP_F_main_BB94_368 = 9'd368;
parameter [8:0] LEGUP_F_main_BB94_369 = 9'd369;
parameter [8:0] LEGUP_F_main_BB94_370 = 9'd370;
parameter [8:0] LEGUP_F_main_BB94_371 = 9'd371;
parameter [8:0] LEGUP_F_main_BB95_372 = 9'd372;
parameter [8:0] LEGUP_F_main_BB96_373 = 9'd373;
parameter [8:0] LEGUP_F_main_BB97_374 = 9'd374;
parameter [8:0] LEGUP_F_main_BB98_375 = 9'd375;
parameter [8:0] LEGUP_F_main_BB99_376 = 9'd376;
parameter [8:0] LEGUP_F_main_BB100_377 = 9'd377;
parameter [8:0] LEGUP_F_main_BB101_378 = 9'd378;
parameter [8:0] LEGUP_F_main_BB102_379 = 9'd379;
parameter [8:0] LEGUP_F_main_BB103_380 = 9'd380;
parameter [8:0] LEGUP_F_main_BB103_381 = 9'd381;
parameter [8:0] LEGUP_F_main_BB103_382 = 9'd382;
parameter [8:0] LEGUP_F_main_BB104_383 = 9'd383;
parameter [8:0] LEGUP_F_main_BB104_384 = 9'd384;
parameter [8:0] LEGUP_F_main_BB104_385 = 9'd385;
parameter [8:0] LEGUP_F_main_BB104_386 = 9'd386;
parameter [8:0] LEGUP_F_main_BB104_387 = 9'd387;
parameter [8:0] LEGUP_F_main_BB104_388 = 9'd388;
parameter [8:0] LEGUP_F_main_BB105_389 = 9'd389;
parameter [8:0] LEGUP_F_main_BB105_390 = 9'd390;
parameter [8:0] LEGUP_F_main_BB105_391 = 9'd391;
parameter [8:0] LEGUP_F_main_BB106_392 = 9'd392;
parameter [8:0] LEGUP_F_main_BB106_393 = 9'd393;
parameter [8:0] LEGUP_F_main_BB106_394 = 9'd394;
parameter [8:0] LEGUP_F_main_BB107_395 = 9'd395;
parameter [8:0] LEGUP_F_main_BB108_396 = 9'd396;
parameter [8:0] LEGUP_F_main_BB108_397 = 9'd397;
parameter [8:0] LEGUP_F_main_BB108_398 = 9'd398;
parameter [8:0] LEGUP_F_main_BB109_399 = 9'd399;
parameter [8:0] LEGUP_F_main_BB110_400 = 9'd400;
parameter [8:0] LEGUP_F_main_BB110_401 = 9'd401;
parameter [8:0] LEGUP_F_main_BB110_402 = 9'd402;
parameter [8:0] LEGUP_F_main_BB111_403 = 9'd403;
parameter [8:0] LEGUP_F_main_BB112_404 = 9'd404;
parameter [8:0] LEGUP_F_main_BB113_405 = 9'd405;
parameter [8:0] LEGUP_F_main_BB114_406 = 9'd406;
parameter [8:0] LEGUP_F_main_BB115_407 = 9'd407;
parameter [8:0] LEGUP_F_main_BB116_408 = 9'd408;
parameter [8:0] LEGUP_F_main_BB116_411 = 9'd411;
parameter [8:0] LEGUP_F_main_BB116_414 = 9'd414;
parameter [8:0] LEGUP_F_main_BB116_417 = 9'd417;
parameter [8:0] LEGUP_F_main_BB116_420 = 9'd420;
parameter [8:0] LEGUP_F_main_BB116_423 = 9'd423;
parameter [8:0] LEGUP_F_main_BB117_426 = 9'd426;
parameter [8:0] LEGUP_F_main_BB118_427 = 9'd427;
parameter [8:0] LEGUP_F_main_BB118_428 = 9'd428;
parameter [8:0] LEGUP_F_main_BB118_429 = 9'd429;
parameter [8:0] LEGUP_F_main_BB118_430 = 9'd430;
parameter [8:0] LEGUP_F_main_BB118_431 = 9'd431;
parameter [8:0] LEGUP_F_main_BB118_432 = 9'd432;
parameter [8:0] LEGUP_F_main_BB119_433 = 9'd433;
parameter [8:0] LEGUP_F_main_BB120_434 = 9'd434;
parameter [8:0] LEGUP_F_main_BB121_435 = 9'd435;
parameter [8:0] LEGUP_F_main_BB122_436 = 9'd436;
parameter [8:0] LEGUP_F_main_BB123_437 = 9'd437;
parameter [8:0] LEGUP_F_main_BB124_438 = 9'd438;
parameter [8:0] LEGUP_F_main_BB125_439 = 9'd439;
parameter [8:0] LEGUP_F_main_BB126_440 = 9'd440;
parameter [8:0] LEGUP_F_main_BB127_441 = 9'd441;
parameter [8:0] LEGUP_F_main_BB127_442 = 9'd442;
parameter [8:0] LEGUP_F_main_BB127_443 = 9'd443;
parameter [8:0] LEGUP_F_main_BB128_444 = 9'd444;
parameter [8:0] LEGUP_F_main_BB129_445 = 9'd445;
parameter [8:0] LEGUP_F_main_BB129_448 = 9'd448;
parameter [8:0] LEGUP_F_main_BB129_451 = 9'd451;
parameter [8:0] LEGUP_F_main_BB130_454 = 9'd454;
parameter [8:0] LEGUP_F_main_BB130_455 = 9'd455;
parameter [8:0] LEGUP_F_main_BB130_456 = 9'd456;
parameter [8:0] LEGUP_F_main_BB131_457 = 9'd457;
parameter [8:0] LEGUP_F_main_BB131_458 = 9'd458;
parameter [8:0] LEGUP_F_main_BB131_459 = 9'd459;
parameter [8:0] LEGUP_F_main_BB131_460 = 9'd460;
parameter [8:0] LEGUP_F_main_BB132_461 = 9'd461;
parameter [8:0] LEGUP_F_main_BB132_462 = 9'd462;
parameter [8:0] LEGUP_F_main_BB132_463 = 9'd463;
parameter [8:0] LEGUP_F_main_BB132_464 = 9'd464;
parameter [8:0] LEGUP_F_main_BB133_465 = 9'd465;
parameter [8:0] LEGUP_F_main_BB133_466 = 9'd466;
parameter [8:0] LEGUP_F_main_BB133_467 = 9'd467;
parameter [8:0] LEGUP_F_main_BB133_468 = 9'd468;
parameter [8:0] LEGUP_F_main_BB134_469 = 9'd469;
parameter [8:0] LEGUP_F_main_BB134_470 = 9'd470;
parameter [8:0] LEGUP_F_main_BB134_471 = 9'd471;
parameter [8:0] LEGUP_F_main_BB134_472 = 9'd472;
parameter [8:0] LEGUP_F_main_BB135_473 = 9'd473;
parameter [8:0] LEGUP_F_main_BB136_474 = 9'd474;
parameter [8:0] LEGUP_F_main_BB137_475 = 9'd475;
parameter [8:0] LEGUP_F_main_BB137_476 = 9'd476;
parameter [8:0] LEGUP_F_main_BB137_477 = 9'd477;
parameter [8:0] LEGUP_function_call_330 = 9'd330;
parameter [8:0] LEGUP_function_call_331 = 9'd331;
parameter [8:0] LEGUP_function_call_334 = 9'd334;
parameter [8:0] LEGUP_function_call_335 = 9'd335;
parameter [8:0] LEGUP_function_call_338 = 9'd338;
parameter [8:0] LEGUP_function_call_339 = 9'd339;
parameter [8:0] LEGUP_function_call_342 = 9'd342;
parameter [8:0] LEGUP_function_call_343 = 9'd343;
parameter [8:0] LEGUP_function_call_358 = 9'd358;
parameter [8:0] LEGUP_function_call_359 = 9'd359;
parameter [8:0] LEGUP_function_call_361 = 9'd361;
parameter [8:0] LEGUP_function_call_362 = 9'd362;
parameter [8:0] LEGUP_function_call_364 = 9'd364;
parameter [8:0] LEGUP_function_call_365 = 9'd365;
parameter [8:0] LEGUP_function_call_409 = 9'd409;
parameter [8:0] LEGUP_function_call_410 = 9'd410;
parameter [8:0] LEGUP_function_call_412 = 9'd412;
parameter [8:0] LEGUP_function_call_413 = 9'd413;
parameter [8:0] LEGUP_function_call_415 = 9'd415;
parameter [8:0] LEGUP_function_call_416 = 9'd416;
parameter [8:0] LEGUP_function_call_418 = 9'd418;
parameter [8:0] LEGUP_function_call_419 = 9'd419;
parameter [8:0] LEGUP_function_call_421 = 9'd421;
parameter [8:0] LEGUP_function_call_422 = 9'd422;
parameter [8:0] LEGUP_function_call_424 = 9'd424;
parameter [8:0] LEGUP_function_call_425 = 9'd425;
parameter [8:0] LEGUP_function_call_446 = 9'd446;
parameter [8:0] LEGUP_function_call_447 = 9'd447;
parameter [8:0] LEGUP_function_call_449 = 9'd449;
parameter [8:0] LEGUP_function_call_450 = 9'd450;
parameter [8:0] LEGUP_function_call_452 = 9'd452;
parameter [8:0] LEGUP_function_call_453 = 9'd453;
input clk;
input reset;
input start;
output reg finish;
output reg [31:0] return_val;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [8:0] cur_state;
reg [31:0] main_1_i_05_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_c_06_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_c_06_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_scevgep13_i;
reg [7:0] main_1_2;
reg [31:0] main_1_3;
reg [31:0] main_1_3_reg;
reg main_1_exitcond11_i;
reg main_1_exitcond11_i_reg;
reg [31:0] main__outer_i_i_i_marker_0;
reg [31:0] main__outer_i_i_i_get_dht_0;
reg [31:0] main__outer_i_i_i_get_dqt_0;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__outer_i_i_ReadBuf_0;
reg [7:0] main__outer_i_i_p_jinfo_num_components_0;
reg main__outer_i_i_p_jinfo_smp_fact_b_0;
reg main__outer_i_i_sow_SOI_0_ph_i_i;
reg main__outer_i_i_sow_SOI_0_ph_i_i_reg;
reg [31:0] main__backedge_i_i_outer_i_marker_1_ph;
reg [31:0] main__backedge_i_i_outer_i_get_dht_1_ph;
reg [31:0] main__backedge_i_i_outer_i_get_dht_1_ph_reg;
reg [31:0] main__backedge_i_i_outer_i_get_dqt_1_ph;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer_ReadBuf_1_ph;
reg [7:0] main__backedge_i_i_outer_p_jinfo_num_components_1_ph;
reg main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer_4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer_4_reg;
reg [31:0] main__backedge_i_i_outer4_i_marker_1_ph5;
reg [31:0] main__backedge_i_i_outer4_i_get_dqt_1_ph6;
reg [31:0] main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer4_ReadBuf_1_ph7;
reg [7:0] main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8;
reg main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer4_5;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer4_5_reg;
reg [31:0] main__backedge_i_i_outer10_i_marker_1_ph11;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer10_ReadBuf_1_ph12;
reg [7:0] main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
reg [7:0] main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg;
reg main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
reg main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg;
reg [31:0] main__backedge_i_i_i_marker_1;
reg [31:0] main__backedge_i_i_i_marker_1_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_ReadBuf_1;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_ReadBuf_1_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_6_7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_6_7_reg;
reg [7:0] main_6_8;
reg [7:0] main_6_9;
reg [7:0] main_6_9_reg;
reg main_6_10;
reg main_6_10_reg;
reg main_6_11;
reg main_6_or_cond_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_first_marker_exit_i_i_14;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_first_marker_exit_i_i_14_reg;
reg [31:0] main_first_marker_exit_i_i_15;
reg [31:0] main_first_marker_exit_i_i_15_reg;
reg [31:0] main_first_marker_exit_i_i_16;
reg [31:0] main_first_marker_exit_i_i_17;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_loopexit_scevgep13_i_i_le;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_18;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_18_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_storemerge1_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_storemerge1_i_i_i_reg;
reg [7:0] main__loopexit3_i_i_i_c_0_in2_i_i_i;
reg main__loopexit3_i_i_i_19;
reg [31:0] main__lr_ph_i_i_i_indvar_i_i;
reg [31:0] main__lr_ph_i_i_i_indvar_i_i_reg;
reg [31:0] main__lr_ph_i_i_i_tmp_i_i;
reg [31:0] main__lr_ph_i_i_i_tmp_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i_i_i_scevgep_i_i;
reg [7:0] main__lr_ph_i_i_i_c_0_in_i_i_i;
reg main__lr_ph_i_i_i_20;
reg [31:0] main__loopexit_i_preheader_i_i_loopexit_tmp4_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit_i_preheader_i_i_loopexit_storemerge_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit_i_preheader_i_i__ph_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit_i_preheader_i_i__ph_i_i_reg;
reg [31:0] main__loopexit_i_i_i_indvar9_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit_i_i_i_scevgep11_i_i;
reg [31:0] main__loopexit_i_i_i_tmp12_i_i;
reg [31:0] main__loopexit_i_i_i_tmp12_i_i_reg;
reg [7:0] main__loopexit_i_i_i_21;
reg [31:0] main__loopexit_i_i_i_22;
reg [31:0] main__loopexit_i_i_i_22_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_loopexit_scevgep13_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_ReadBuf_2;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_ReadBuf_2_reg;
reg [31:0] main_next_marker_exit_i_i_unread_marker_0_i_i;
reg [31:0] main_next_marker_exit_i_i_unread_marker_0_i_i_reg;
reg [31:0] main_next_marker_exit_i_i_24;
reg [31:0] main_next_marker_exit_i_i_24_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_25;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_25_reg;
reg [31:0] main_next_marker_exit_i_i_26;
reg main_next_marker_exit_i_i_27;
reg [31:0] main_28_29;
reg [31:0] main_28_30;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_33;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_33_reg;
reg [7:0] main_32_34;
reg [15:0] main_32_35;
reg [15:0] main_32_36;
reg [15:0] main_32_36_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_37;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_37_reg;
reg [7:0] main_32_38;
reg [15:0] main_32_39;
reg [15:0] main_32_40;
reg [31:0] main_32_41;
reg [31:0] main_32_41_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_42;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_42_reg;
reg [7:0] main_32_43;
reg [7:0] main_32_43_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_44;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_44_reg;
reg [7:0] main_32_45;
reg [15:0] main_32_46;
reg [15:0] main_32_47;
reg [15:0] main_32_47_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_48;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_48_reg;
reg [7:0] main_32_49;
reg [15:0] main_32_50;
reg [15:0] main_32_51;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_52;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_52_reg;
reg [7:0] main_32_53;
reg [15:0] main_32_54;
reg [15:0] main_32_55;
reg [15:0] main_32_55_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_56;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_56_reg;
reg [7:0] main_32_57;
reg [15:0] main_32_58;
reg [15:0] main_32_59;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_60;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_60_reg;
reg [7:0] main_32_61;
reg [7:0] main_32_61_reg;
reg [31:0] main_32_63;
reg [31:0] main_32_63_reg;
reg [15:0] main_32_65;
reg [31:0] main_32_66;
reg [15:0] main_32_68;
reg [31:0] main_32_69;
reg [31:0] main_32_71;
reg [31:0] main_32_71_reg;
reg main_32_73;
reg main_32_73_reg;
reg [31:0] main_74_75;
reg [31:0] main_74_76;
reg main_77_78;
reg [31:0] main_79_80;
reg [31:0] main_79_81;
reg [15:0] main_82_83;
reg main_82_84;
reg [31:0] main_85_86;
reg [31:0] main_85_87;
reg [15:0] main_88_89;
reg main_88_90;
reg [31:0] main_91_92;
reg [31:0] main_91_93;
reg main_94_95;
reg [31:0] main__preheader_i_i_i_thread_96;
reg [31:0] main__preheader_i_i_i_thread_97;
reg main__preheader_i_i_i_98;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_ReadBuf_3;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_ReadBuf_3_reg;
reg [31:0] main__lr_ph_i1_i_i_ci_02_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep3_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep3_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep4_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep4_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep5_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep5_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep6_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep6_i_i_i_reg;
reg [7:0] main__lr_ph_i1_i_i_tmp_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep7_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep7_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep8_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep8_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep9_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep9_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep11_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep11_i_i_i_reg;
reg [31:0] main__lr_ph_i1_i_i_tmp12_i_i_i;
reg [31:0] main__lr_ph_i1_i_i_tmp12_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_99;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_99_reg;
reg [7:0] main__lr_ph_i1_i_i_100;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_101;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_101_reg;
reg [7:0] main__lr_ph_i1_i_i_102;
reg [7:0] main__lr_ph_i1_i_i_103;
reg [7:0] main__lr_ph_i1_i_i_104;
reg [7:0] main__lr_ph_i1_i_i_104_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_105;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_105_reg;
reg [7:0] main__lr_ph_i1_i_i_106;
reg [31:0] main__lr_ph_i1_i_i_107;
reg [31:0] main__lr_ph_i1_i_i_107_reg;
reg [7:0] main__lr_ph_i1_i_i_109;
reg [31:0] main__lr_ph_i1_i_i_110;
reg [7:0] main__lr_ph_i1_i_i_112;
reg [31:0] main__lr_ph_i1_i_i_113;
reg [7:0] main__lr_ph_i1_i_i_115;
reg [31:0] main__lr_ph_i1_i_i_116;
reg [7:0] main__lr_ph_i1_i_i_118;
reg [31:0] main__lr_ph_i1_i_i_119;
reg [7:0] main__lr_ph_i1_i_i_121;
reg [31:0] main__lr_ph_i1_i_i_122;
reg [31:0] main__lr_ph_i1_i_i_122_reg;
reg [31:0] main__lr_ph_i1_i_i_123;
reg main__lr_ph_i1_i_i_124;
reg [31:0] main_125_126;
reg [31:0] main_125_127;
reg [7:0] main_128_129;
reg [31:0] main_128_130;
reg [31:0] main_128_130_reg;
reg [31:0] main_128_131;
reg main_128_132;
reg [31:0] main_133_134;
reg [31:0] main_133_135;
reg [7:0] main_136_137;
reg [31:0] main_136_138;
reg [31:0] main_136_138_reg;
reg [31:0] main_136_139;
reg [31:0] main_136_139_reg;
reg main_136_140;
reg [31:0] main_141_142;
reg [31:0] main_141_143;
reg [7:0] main_144_145;
reg [31:0] main_144_146;
reg main_144_147;
reg [31:0] main_148_149;
reg [31:0] main_148_150;
reg [7:0] main_151_152;
reg [31:0] main_151_153;
reg [31:0] main_151_153_reg;
reg [31:0] main_151_154;
reg main_151_155;
reg [31:0] main_156_157;
reg [31:0] main_156_158;
reg main_159_160;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___crit_edge_i_i_i_ReadBuf_4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___crit_edge_i_i_i_ReadBuf_4_reg;
reg [7:0] main___crit_edge_i_i_i_161;
reg main___crit_edge_i_i_i_162;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_168;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_168_reg;
reg [7:0] main_167_169;
reg [15:0] main_167_170;
reg [15:0] main_167_171;
reg [15:0] main_167_171_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_172;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_172_reg;
reg [7:0] main_167_173;
reg [15:0] main_167_174;
reg [15:0] main_167_175;
reg [31:0] main_167_176;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_177;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_177_reg;
reg [7:0] main_167_178;
reg [7:0] main_167_178_reg;
reg [31:0] main_167_179;
reg [31:0] main_167_179_reg;
reg main_167_182;
reg main_167_182_reg;
reg [31:0] main_183_184;
reg [31:0] main_183_185;
reg main_186_187;
reg [31:0] main_188_189;
reg [31:0] main_188_190;
reg [31:0] main__preheader5_i_i_i_preheader_191;
reg [31:0] main__preheader5_i_i_i_preheader_191_reg;
reg [31:0] main__preheader5_i_i_i_i_get_sos_0;
reg [31:0] main__preheader5_i_i_i_i_get_sos_0_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader5_i_i_i_ReadBuf_5;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader5_i_i_i_ReadBuf_5_reg;
reg [31:0] main__preheader5_i_i_i_192;
reg [31:0] main__preheader5_i_i_i_192_reg;
reg main__preheader5_i_i_i_193;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_194_195;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_194_195_reg;
reg [7:0] main_194_196;
reg [31:0] main_194_197;
reg [31:0] main_194_197_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_194_198;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_194_198_reg;
reg [7:0] main_194_199;
reg [7:0] main_194_199_reg;
reg [31:0] main_200_201;
reg [31:0] main_200_201_reg;
reg main_200_202;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_203_scevgep9_i4_i_i;
reg [7:0] main_203_204;
reg [31:0] main_203_205;
reg main_203_206;
reg [31:0] main_207_208;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_scevgep8_i5_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_scevgep8_i5_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_scevgep7_i6_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_scevgep7_i6_i_i_reg;
reg [31:0] main_211_212;
reg [31:0] main_211_213;
reg [7:0] main_211_214;
reg [7:0] main_211_214_reg;
reg [7:0] main_211_215;
reg [7:0] main_211_215_reg;
reg [7:0] main_211_217;
reg [31:0] main_211_218;
reg [7:0] main_211_220;
reg [31:0] main_211_221;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_223;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_223_reg;
reg [31:0] main_211_224;
reg main_211_225;
reg [31:0] main_226_227;
reg [31:0] main_226_228;
reg [7:0] main_229_230;
reg [31:0] main_229_231;
reg [31:0] main_229_231_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_229_232;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_229_232_reg;
reg [31:0] main_229_233;
reg [31:0] main_229_233_reg;
reg main_229_234;
reg [31:0] main_235_236;
reg [31:0] main_235_237;
reg [7:0] main_238_239;
reg [31:0] main_238_240;
reg main_238_241;
reg [31:0] main_242_243;
reg [31:0] main_242_244;
reg [31:0] main_245_246;
reg [31:0] main_245_247;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_sos_exit_i_i_scevgep_i2_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_248_249;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_248_249_reg;
reg [7:0] main_248_250;
reg [15:0] main_248_251;
reg [15:0] main_248_252;
reg [15:0] main_248_252_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_248_253;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_248_253_reg;
reg [7:0] main_248_254;
reg [15:0] main_248_255;
reg [15:0] main_248_256;
reg [31:0] main_248_257;
reg [31:0] main_248_258;
reg [31:0] main_248_258_reg;
reg [31:0] main_248_260;
reg main_248_261;
reg [31:0] main_262_263;
reg [31:0] main_262_264;
reg main__preheader_i7_i_i_265;
reg [31:0] main__lr_ph5_i_i_i_i_get_dht_2;
reg [31:0] main__lr_ph5_i_i_i_i_get_dht_2_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_ReadBuf_6;
reg [31:0] main__lr_ph5_i_i_i_length_04_i_i_i;
reg [31:0] main__lr_ph5_i_i_i_length_04_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_266;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_266_reg;
reg [7:0] main__lr_ph5_i_i_i_267;
reg [31:0] main__lr_ph5_i_i_i_268;
reg [31:0] main__lr_ph5_i_i_i_268_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_270;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_270_reg;
reg [31:0] main__lr_ph5_i_i_i_271;
reg main__lr_ph5_i_i_i_272;
reg [31:0] main_273_274;
reg [31:0] main_273_275;
reg [31:0] main_276_277;
reg main_276_278;
reg [31:0] main_279_280;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_279_281;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_279_282;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_283_284;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_283_285;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_huffval_0_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_huffval_0_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_bits_0_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_bits_0_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_288;
reg [31:0] main_287_indvar_i_i_i;
reg [31:0] main_287_count_01_i_i_i;
reg [31:0] main_287_count_01_i_i_i_reg;
reg [31:0] main_287_tmp_i8_i_i;
reg [31:0] main_287_tmp_i8_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_scevgep_i9_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_scevgep_i9_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_289;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_289_reg;
reg [7:0] main_287_290;
reg [31:0] main_287_291;
reg [31:0] main_287_292;
reg [31:0] main_287_292_reg;
reg main_287_exitcond_i_i_i;
reg main_287_exitcond_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_293_295;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_293_295_reg;
reg [31:0] main_293_296;
reg main_293_297;
reg [31:0] main_298_299;
reg [31:0] main_298_300;
reg [31:0] main_301_302;
reg [31:0] main_301_302_reg;
reg main_301_303;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_304;
reg [31:0] main__lr_ph_i10_i_i_i_13_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_scevgep8_i11_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_scevgep8_i11_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_305;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_305_reg;
reg [7:0] main__lr_ph_i10_i_i_306;
reg [31:0] main__lr_ph_i10_i_i_307;
reg [31:0] main__lr_ph_i10_i_i_308;
reg [31:0] main__lr_ph_i10_i_i_308_reg;
reg main__lr_ph_i10_i_i_exitcond7_i_i_i;
reg main__lr_ph_i10_i_i_exitcond7_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___crit_edge_i12_i_i_ReadBuf_7;
reg [31:0] main___crit_edge_i12_i_i_309;
reg [31:0] main___crit_edge_i12_i_i_310;
reg main___crit_edge_i12_i_i_311;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_312_313;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_312_313_reg;
reg [7:0] main_312_314;
reg [15:0] main_312_315;
reg [15:0] main_312_316;
reg [15:0] main_312_316_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_312_317;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_312_317_reg;
reg [7:0] main_312_318;
reg [15:0] main_312_319;
reg [15:0] main_312_320;
reg [31:0] main_312_321;
reg [31:0] main_312_322;
reg [31:0] main_312_322_reg;
reg [31:0] main_312_324;
reg main_312_325;
reg [31:0] main_326_327;
reg [31:0] main_326_328;
reg main__preheader_i13_i_i_329;
reg [31:0] main__lr_ph_i15_i_i_i_get_dqt_2;
reg [31:0] main__lr_ph_i15_i_i_i_get_dqt_2_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_330;
reg [31:0] main__lr_ph_i15_i_i_length_02_i_i_i;
reg [31:0] main__lr_ph_i15_i_i_length_02_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_331;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_331_reg;
reg [7:0] main__lr_ph_i15_i_i_332;
reg [31:0] main__lr_ph_i15_i_i_333;
reg [31:0] main__lr_ph_i15_i_i_334;
reg [31:0] main__lr_ph_i15_i_i_334_reg;
reg [31:0] main__lr_ph_i15_i_i_335;
reg [31:0] main__lr_ph_i15_i_i_335_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_338;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_338_reg;
reg [31:0] main__lr_ph_i15_i_i_339;
reg main__lr_ph_i15_i_i_340;
reg [31:0] main_341_342;
reg [31:0] main_341_343;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_344_345;
reg [31:0] main_344_346;
reg main_344_347;
reg [31:0] main_348_349;
reg [31:0] main_348_350;
reg [31:0] main_351_352;
reg [31:0] main_351_352_reg;
reg main_351_353;
reg main_351_353_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_354;
reg [31:0] main__split_us_i_i_i_i_01_us_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_scevgep_i16_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_scevgep_i16_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_355;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_355_reg;
reg [7:0] main__split_us_i_i_i_356;
reg [31:0] main__split_us_i_i_i_357;
reg [31:0] main__split_us_i_i_i_357_reg;
reg [31:0] main__split_us_i_i_i_358;
reg [31:0] main__split_us_i_i_i__sum_us_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_359;
reg [31:0] main__split_us_i_i_i_360;
reg [31:0] main__split_us_i_i_i_360_reg;
reg main__split_us_i_i_i_exitcond_i17_i_i;
reg main__split_us_i_i_i_exitcond_i17_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_361;
reg [31:0] main___split_crit_edge_i_i_i_i_01_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_scevgep4_i18_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_scevgep4_i18_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_362;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_362_reg;
reg [7:0] main___split_crit_edge_i_i_i_363;
reg [31:0] main___split_crit_edge_i_i_i_364;
reg [31:0] main___split_crit_edge_i_i_i_365;
reg [31:0] main___split_crit_edge_i_i_i_365_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_366;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_366_reg;
reg [7:0] main___split_crit_edge_i_i_i_367;
reg [31:0] main___split_crit_edge_i_i_i_368;
reg [31:0] main___split_crit_edge_i_i_i_369;
reg [31:0] main___split_crit_edge_i_i_i_369_reg;
reg [31:0] main___split_crit_edge_i_i_i_370;
reg [31:0] main___split_crit_edge_i_i_i__sum_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_371;
reg [31:0] main___split_crit_edge_i_i_i_372;
reg [31:0] main___split_crit_edge_i_i_i_372_reg;
reg main___split_crit_edge_i_i_i_exitcond3_i_i_i;
reg main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__us_lcssa_us_i_i_i_ReadBuf_8;
reg [31:0] main__us_lcssa_us_i_i_i___v_i_i_i;
reg [31:0] main__us_lcssa_us_i_i_i___i_i_i;
reg main__us_lcssa_us_i_i_i_373;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_p_jinfo_jpeg_data_0;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg;
reg [15:0] main_read_markers_exit_i_374;
reg [15:0] main_read_markers_exit_i_374_reg;
reg [31:0] main_read_markers_exit_i_375;
reg [31:0] main_read_markers_exit_i_376;
reg [31:0] main_read_markers_exit_i_376_reg;
reg [31:0] main_read_markers_exit_i_377;
reg [31:0] main_read_markers_exit_i_377_reg;
reg [31:0] main_read_markers_exit_i_378;
reg [31:0] main_read_markers_exit_i_378_reg;
reg [15:0] main_read_markers_exit_i_379;
reg [15:0] main_read_markers_exit_i_379_reg;
reg [31:0] main_read_markers_exit_i_380;
reg [31:0] main_read_markers_exit_i_381;
reg [31:0] main_read_markers_exit_i_381_reg;
reg [31:0] main_read_markers_exit_i_382;
reg [31:0] main_read_markers_exit_i_382_reg;
reg [31:0] main_read_markers_exit_i_383;
reg [31:0] main_read_markers_exit_i_384;
reg [31:0] main_read_markers_exit_i_384_reg;
reg [31:0] main_read_markers_exit_i_385;
reg [31:0] main_read_markers_exit_i_385_reg;
reg [31:0] main_read_markers_exit_i_386;
reg [31:0] main_read_markers_exit_i_386_reg;
reg [31:0] main_read_markers_exit_i_387;
reg [31:0] main_read_markers_exit_i_387_reg;
reg [31:0] main_read_markers_exit_i_388;
reg [31:0] main_read_markers_exit_i_388_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_1_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_1_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_2_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_2_i_i_reg;
reg main_389_391;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_1_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_1_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_2_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_2_i_i_reg;
reg [31:0] main__preheader21_i_i_CurrentMCU_026_i_i;
reg [31:0] main__preheader21_i_i_tmp143_i_i;
reg [31:0] main__preheader21_i_i_tmp143_i_i_reg;
reg [31:0] main_392_i_01_i_i1_i;
reg [31:0] main_392_i_01_i_i1_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep3_i_i2_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep3_i_i2_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep2_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep2_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep_i_i3_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep6_i_i4_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep6_i_i4_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep5_i_i5_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep5_i_i5_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep4_i_i6_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep4_i_i6_i_reg;
reg [31:0] main_392_393;
reg [31:0] main_392_394;
reg [31:0] main_392_395;
reg [31:0] main_392_396;
reg [31:0] main_392_397;
reg [31:0] main_392_398;
reg [31:0] main_392_399;
reg [31:0] main_392_400;
reg [31:0] main_392_400_reg;
reg [31:0] main_392_401;
reg [31:0] main_392_401_reg;
reg [31:0] main_392_402;
reg [31:0] main_392_402_reg;
reg [31:0] main_392_403;
reg [31:0] main_392_404;
reg [31:0] main_392_405;
reg [31:0] main_392_405_reg;
reg [31:0] main_392_406;
reg [31:0] main_392_406_reg;
reg [31:0] main_392_407;
reg [31:0] main_392_407_reg;
reg [31:0] main_392_408;
reg [31:0] main_392_409;
reg [31:0] main_392_409_reg;
reg [31:0] main_392_410;
reg [31:0] main_392_410_reg;
reg main_392_411;
reg main_412_413;
reg [31:0] main_415_r_0_i_i_i;
reg [31:0] main_415_r_0_i_i_i_reg;
reg main_415_416;
reg main_417_418;
reg [31:0] main_420_g_0_i_i_i;
reg [31:0] main_420_g_0_i_i_i_reg;
reg main_420_421;
reg main_422_423;
reg [31:0] main_425_b_0_i_i_i;
reg [31:0] main_425_b_0_i_i_i_reg;
reg [31:0] main_425_426;
reg [31:0] main_425_426_reg;
reg main_425_exitcond53_i_i;
reg main_425_exitcond53_i_i_reg;
reg [15:0] main_YuvToRgb_exit_loopexit_i_i_427;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_428;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_428_reg;
reg [15:0] main_YuvToRgb_exit_loopexit_i_i_429;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_430;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_430_reg;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i_reg;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i__pre_i_i;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i__pre_i_i_reg;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_431;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_431_reg;
reg [31:0] main_432_433;
reg [31:0] main_432_i_324_i_i;
reg [31:0] main_432_i_324_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_432_scevgep139_i_i;
reg [31:0] main_432_tmp141_i_i;
reg [31:0] main_432_tmp141_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_432_scevgep142_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_432_scevgep142_i_i_reg;
reg [31:0] main_432_434;
reg [31:0] main_432_434_reg;
reg [31:0] main_432_435;
reg [31:0] main_432_435_reg;
reg [31:0] main_432_436;
reg [31:0] main_432_436_reg;
reg main_432_437;
reg main_432_438;
reg main_432_438_reg;
reg main_432_or_cond_i_i_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp61_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp62149_i_i;
reg main__lr_ph8_split_us_i_i_i_i_tmp63_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_smax_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_smax_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp64_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp67_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp67_i_i_reg;
reg main__lr_ph8_split_us_i_i_i_i_tmp68_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_umax_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_umax_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp69_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp69_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp82_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp83150_i_i;
reg main__lr_ph8_split_us_i_i_i_i_tmp84_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_smax85_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_smax85_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp86_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp89_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp89_i_i_reg;
reg main__lr_ph8_split_us_i_i_i_i_tmp90_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_umax91_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_umax91_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp92_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp92_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp121_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp122_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp122_i_i_reg;
reg [31:0] main_439_indvar_next18_i_i_i_i;
reg main_439_exitcond93_i_i;
reg [31:0] main_440_indvar_i_i_i_i;
reg [31:0] main_440_tmp124_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_440_scevgep24_i_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_440_scevgep24_i_i_i_i_reg;
reg [31:0] main_440_tmp137_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_440__14_us_i_i_i_i;
reg [31:0] main_440_441;
reg [7:0] main_440_442;
reg [31:0] main_440_indvar_next_i_i_i_i;
reg [31:0] main_440_indvar_next_i_i_i_i_reg;
reg main_440_exitcond70_i_i;
reg main_440_exitcond70_i_i_reg;
reg [31:0] main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
reg [31:0] main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg;
reg [31:0] main__lr_ph_us_i_i_i_i_tmp118_i_i;
reg [31:0] main__lr_ph_us_i_i_i_i_tmp123_i_i;
reg [31:0] main__lr_ph_us_i_i_i_i_tmp123_i_i_reg;
reg [31:0] main__lr_ph_us_i_i_i_i_tmp136_i_i;
reg [31:0] main__lr_ph_us_i_i_i_i_tmp136_i_i_reg;
reg [31:0] main_WriteOneBlock_exit_i_i_i_443;
reg main_WriteOneBlock_exit_i_i_i_444;
reg [31:0] main_WriteBlock_exit_i_i_446;
reg main_WriteBlock_exit_i_i_exitcond116_i_i;
reg main_447_448;
reg main_449_451;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_452;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_452_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_453;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_453_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_i8_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_i8_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_1_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_1_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_2_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_2_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_3_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_3_i_i_reg;
reg [31:0] main__preheader_i_i_indvar_i7_i;
reg [31:0] main__preheader_i_i_indvar_i7_i_reg;
reg [31:0] main__preheader_i_i_tmp48_i_i;
reg [31:0] main__preheader_i_i_tmp49_i_i;
reg [31:0] main__preheader_i_i_tmp49_i_i_reg;
reg [31:0] main__preheader16_i_i_i_517_i_i;
reg [31:0] main__preheader16_i_i_i_517_i_i_reg;
reg [31:0] main_454_i_01_i2_i_i;
reg [31:0] main_454_i_01_i2_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep4_i6_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep4_i6_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep5_i7_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep5_i7_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep6_i8_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep6_i8_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep_i3_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep3_i5_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep3_i5_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep2_i4_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep2_i4_i_i_reg;
reg [31:0] main_454_455;
reg [31:0] main_454_456;
reg [31:0] main_454_457;
reg [31:0] main_454_458;
reg [31:0] main_454_459;
reg [31:0] main_454_460;
reg [31:0] main_454_461;
reg [31:0] main_454_462;
reg [31:0] main_454_462_reg;
reg [31:0] main_454_463;
reg [31:0] main_454_463_reg;
reg [31:0] main_454_464;
reg [31:0] main_454_464_reg;
reg [31:0] main_454_465;
reg [31:0] main_454_466;
reg [31:0] main_454_467;
reg [31:0] main_454_467_reg;
reg [31:0] main_454_468;
reg [31:0] main_454_468_reg;
reg [31:0] main_454_469;
reg [31:0] main_454_469_reg;
reg [31:0] main_454_470;
reg [31:0] main_454_471;
reg [31:0] main_454_471_reg;
reg [31:0] main_454_472;
reg [31:0] main_454_472_reg;
reg main_454_473;
reg main_474_475;
reg [31:0] main_477_r_0_i9_i_i;
reg [31:0] main_477_r_0_i9_i_i_reg;
reg main_477_478;
reg main_479_480;
reg [31:0] main_482_g_0_i10_i_i;
reg [31:0] main_482_g_0_i10_i_i_reg;
reg main_482_483;
reg main_484_485;
reg [31:0] main_487_b_0_i11_i_i;
reg [31:0] main_487_b_0_i11_i_i_reg;
reg [31:0] main_487_488;
reg [31:0] main_487_488_reg;
reg main_487_exitcond_i_i;
reg main_487_exitcond_i_i_reg;
reg [31:0] main_YuvToRgb_exit13_i_i_489;
reg main_YuvToRgb_exit13_i_i_exitcond35_i_i;
reg main__loopexit_i_i_490;
reg main__loopexit_i_i_490_reg;
reg [31:0] main__loopexit_i_i_indvar_next_i_i;
reg [31:0] main__loopexit_i_i_indvar_next_i_i_reg;
reg [31:0] main_decode_start_exit_i_main_result_promoted3_i;
reg [31:0] main_491_492;
reg [31:0] main_491_492_reg;
reg [31:0] main_491_j_01_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_491_scevgep7_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_491_scevgep7_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_491_scevgep_i;
reg [7:0] main_491_493;
reg [7:0] main_491_493_reg;
reg [7:0] main_491_494;
reg main_491_495;
reg [31:0] main_491_496;
reg [31:0] main_491_497;
reg [31:0] main_491_498;
reg [31:0] main_491_498_reg;
reg main_491_exitcond_i;
reg main_491_exitcond_i_reg;
reg [31:0] main__preheader_1_i_499;
reg [31:0] main__preheader_1_i_499_reg;
reg [31:0] main__preheader_1_i_j_01_1_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_1_i_scevgep7_1_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_1_i_scevgep7_1_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_1_i_scevgep_1_i;
reg [7:0] main__preheader_1_i_500;
reg [7:0] main__preheader_1_i_500_reg;
reg [7:0] main__preheader_1_i_501;
reg main__preheader_1_i_502;
reg [31:0] main__preheader_1_i_503;
reg [31:0] main__preheader_1_i_504;
reg [31:0] main__preheader_1_i_505;
reg [31:0] main__preheader_1_i_505_reg;
reg main__preheader_1_i_exitcond_1_i;
reg main__preheader_1_i_exitcond_1_i_reg;
reg main_jpeg2bmp_main_exit_506;
reg [31:0] main_jpeg2bmp_main_exit_507;
reg [31:0] main_jpeg2bmp_main_exit_storemerge;
reg main_jpeg2bmp_main_exit_508;
reg [31:0] main_jpeg2bmp_main_exit_509;
reg [31:0] main_jpeg2bmp_main_exit__storemerge;
reg [31:0] main_jpeg2bmp_main_exit_511;
reg main_jpeg2bmp_main_exit_512;
reg [31:0] main__preheader_2_i_513;
reg [31:0] main__preheader_2_i_513_reg;
reg [31:0] main__preheader_2_i_j_01_2_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_2_i_scevgep7_2_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_2_i_scevgep7_2_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_2_i_scevgep_2_i;
reg [7:0] main__preheader_2_i_514;
reg [7:0] main__preheader_2_i_514_reg;
reg [7:0] main__preheader_2_i_515;
reg main__preheader_2_i_516;
reg [31:0] main__preheader_2_i_517;
reg [31:0] main__preheader_2_i_518;
reg [31:0] main__preheader_2_i_518_reg;
reg [31:0] main__preheader_2_i_519;
reg [31:0] main__preheader_2_i_519_reg;
reg main__preheader_2_i_exitcond_2_i;
reg main__preheader_2_i_exitcond_2_i_reg;
reg [31:0] main_524_525;
reg huff_make_dhuff_tb_start;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_arg_p_xhtbl_bits;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_arg_p_dhtbl_maxcode;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_arg_p_dhtbl_mincode;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_arg_p_dhtbl_valptr;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_memory_controller_address;
wire huff_make_dhuff_tb_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] huff_make_dhuff_tb_memory_controller_in;
reg huff_make_dhuff_tb_memory_controller_waitrequest;
wire huff_make_dhuff_tb_memory_controller_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] huff_make_dhuff_tb_memory_controller_out;
wire [1:0] huff_make_dhuff_tb_memory_controller_size;
wire huff_make_dhuff_tb_finish;
wire [31:0] huff_make_dhuff_tb_return_val;
reg legup_function_call;
reg decode_block_start;
reg [31:0] decode_block_arg_comp_no;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_arg_out_buf;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_arg_HuffBuff;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_memory_controller_address;
wire decode_block_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] decode_block_memory_controller_in;
reg decode_block_memory_controller_waitrequest;
wire decode_block_memory_controller_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] decode_block_memory_controller_out;
wire [1:0] decode_block_memory_controller_size;
wire decode_block_finish;
reg Write4Blocks_start;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_store1;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_store2;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_store3;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_store4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_p_out_vpos;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_p_out_hpos;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_p_out_buf;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_memory_controller_address;
wire Write4Blocks_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] Write4Blocks_memory_controller_in;
reg Write4Blocks_memory_controller_waitrequest;
wire Write4Blocks_memory_controller_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] Write4Blocks_memory_controller_out;
wire [1:0] Write4Blocks_memory_controller_size;
wire Write4Blocks_finish;
reg [31:0] main_signed_multiply_32_1_op0;
reg [31:0] main_signed_multiply_32_1_op1;
reg [31:0] main_signed_multiply_32_1;
reg [31:0] main_signed_multiply_32_2_op0;
reg [31:0] main_signed_multiply_32_2_op1;
reg [31:0] main_signed_multiply_32_2;
reg [31:0] main_signed_multiply_32_0_op0;
reg [31:0] main_signed_multiply_32_0_op1;
reg [31:0] main_signed_multiply_32_0;
reg [31:0] main_signed_divide_32_0_op0;
reg [31:0] main_signed_divide_32_0_op1;
reg [31:0] main_signed_divide_32_0;
wire [31:0] lpm_divide_main_read_markers_exit_i_377_out;
wire [31:0] main_read_markers_exit_i_377_unused;
reg lpm_divide_main_read_markers_exit_i_377_en;
reg [31:0] main_1_i_05_i_phi_temp;
reg [31:0] main__outer_i_i_i_marker_0_phi_temp;
reg [31:0] main__outer_i_i_i_get_dht_0_phi_temp;
reg [31:0] main__outer_i_i_i_get_dqt_0_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__outer_i_i_ReadBuf_0_phi_temp;
reg [7:0] main__outer_i_i_p_jinfo_num_components_0_phi_temp;
reg main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp;
reg main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp;
reg [31:0] main__backedge_i_i_outer_i_marker_1_ph_phi_temp;
reg [31:0] main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp;
reg [31:0] main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp;
reg [7:0] main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp;
reg main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp;
reg [31:0] main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp;
reg [31:0] main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp;
reg [7:0] main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp;
reg main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp;
reg [31:0] main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp;
reg [7:0] main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
reg main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
reg [31:0] main__backedge_i_i_i_marker_1_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_ReadBuf_1_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_18_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
reg [31:0] main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit_i_preheader_i_i__ph_i_i_phi_temp;
reg [31:0] main__lr_ph_i_i_i_indvar_i_i_phi_temp;
reg [31:0] main__loopexit_i_i_i_indvar9_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_ReadBuf_3_phi_temp;
reg [31:0] main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___crit_edge_i_i_i_ReadBuf_4_phi_temp;
reg [31:0] main__preheader5_i_i_i_i_get_sos_0_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader5_i_i_i_ReadBuf_5_phi_temp;
reg [31:0] main__preheader5_i_i_i_192_phi_temp;
reg [31:0] main_200_201_phi_temp;
reg [31:0] main__lr_ph5_i_i_i_i_get_dht_2_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_ReadBuf_6_phi_temp;
reg [31:0] main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_huffval_0_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_bits_0_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_288_phi_temp;
reg [31:0] main_287_indvar_i_i_i_phi_temp;
reg [31:0] main_287_count_01_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_304_phi_temp;
reg [31:0] main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___crit_edge_i12_i_i_ReadBuf_7_phi_temp;
reg [31:0] main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_330_phi_temp;
reg [31:0] main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_354_phi_temp;
reg [31:0] main__split_us_i_i_i_i_01_us_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_361_phi_temp;
reg [31:0] main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp;
reg [31:0] main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp;
reg [31:0] main_392_i_01_i_i1_i_phi_temp;
reg [31:0] main_415_r_0_i_i_i_phi_temp;
reg [31:0] main_420_g_0_i_i_i_phi_temp;
reg [31:0] main_425_b_0_i_i_i_phi_temp;
reg [31:0] main_432_433_phi_temp;
reg [31:0] main_432_i_324_i_i_phi_temp;
reg [31:0] main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp;
reg [31:0] main_440_indvar_i_i_i_i_phi_temp;
reg [31:0] main_WriteBlock_exit_i_i_446_phi_temp;
reg [31:0] main__preheader_i_i_indvar_i7_i_phi_temp;
reg [31:0] main__preheader16_i_i_i_517_i_i_phi_temp;
reg [31:0] main_454_i_01_i2_i_i_phi_temp;
reg [31:0] main_477_r_0_i9_i_i_phi_temp;
reg [31:0] main_482_g_0_i10_i_i_phi_temp;
reg [31:0] main_487_b_0_i11_i_i_phi_temp;
reg [31:0] main_491_492_phi_temp;
reg [31:0] main_491_j_01_i_phi_temp;
reg [31:0] main__preheader_1_i_499_phi_temp;
reg [31:0] main__preheader_1_i_j_01_1_i_phi_temp;
reg [31:0] main__preheader_2_i_513_phi_temp;
reg [31:0] main__preheader_2_i_j_01_2_i_phi_temp;
/* %377 = sdiv i32 %376, 8*/
lpm_divide lpm_divide_main_read_markers_exit_i_377 (
.numer (main_signed_divide_32_0_op0),
.denom (main_signed_divide_32_0_op1),
.quotient (lpm_divide_main_read_markers_exit_i_377_out),
.remain (main_read_markers_exit_i_377_unused),
.clock (clk),
.aclr (1'd0),
.clken (lpm_divide_main_read_markers_exit_i_377_en)
);
defparam
lpm_divide_main_read_markers_exit_i_377.lpm_pipeline = 32,
lpm_divide_main_read_markers_exit_i_377.lpm_widthd = 32,
lpm_divide_main_read_markers_exit_i_377.lpm_widthn = 32,
lpm_divide_main_read_markers_exit_i_377.lpm_drepresentation = "SIGNED",
lpm_divide_main_read_markers_exit_i_377.lpm_nrepresentation = "SIGNED",
lpm_divide_main_read_markers_exit_i_377.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE";
huff_make_dhuff_tb huff_make_dhuff_tb_inst (
.clk (clk),
.reset (reset),
.start (huff_make_dhuff_tb_start),
.finish (huff_make_dhuff_tb_finish),
.return_val (huff_make_dhuff_tb_return_val),
.memory_controller_address (huff_make_dhuff_tb_memory_controller_address),
.memory_controller_write_enable (huff_make_dhuff_tb_memory_controller_write_enable),
.memory_controller_enable (huff_make_dhuff_tb_memory_controller_enable),
.memory_controller_in (huff_make_dhuff_tb_memory_controller_in),
.memory_controller_size (huff_make_dhuff_tb_memory_controller_size),
.memory_controller_waitrequest (huff_make_dhuff_tb_memory_controller_waitrequest),
.memory_controller_out (huff_make_dhuff_tb_memory_controller_out),
.arg_p_xhtbl_bits (huff_make_dhuff_tb_arg_p_xhtbl_bits),
.arg_p_dhtbl_maxcode (huff_make_dhuff_tb_arg_p_dhtbl_maxcode),
.arg_p_dhtbl_mincode (huff_make_dhuff_tb_arg_p_dhtbl_mincode),
.arg_p_dhtbl_valptr (huff_make_dhuff_tb_arg_p_dhtbl_valptr)
);
decode_block decode_block_inst (
.clk (clk),
.reset (reset),
.start (decode_block_start),
.finish (decode_block_finish),
.memory_controller_address (decode_block_memory_controller_address),
.memory_controller_write_enable (decode_block_memory_controller_write_enable),
.memory_controller_enable (decode_block_memory_controller_enable),
.memory_controller_in (decode_block_memory_controller_in),
.memory_controller_size (decode_block_memory_controller_size),
.memory_controller_waitrequest (decode_block_memory_controller_waitrequest),
.memory_controller_out (decode_block_memory_controller_out),
.arg_comp_no (decode_block_arg_comp_no),
.arg_out_buf (decode_block_arg_out_buf),
.arg_HuffBuff (decode_block_arg_HuffBuff)
);
Write4Blocks Write4Blocks_inst (
.clk (clk),
.reset (reset),
.start (Write4Blocks_start),
.finish (Write4Blocks_finish),
.memory_controller_address (Write4Blocks_memory_controller_address),
.memory_controller_write_enable (Write4Blocks_memory_controller_write_enable),
.memory_controller_enable (Write4Blocks_memory_controller_enable),
.memory_controller_in (Write4Blocks_memory_controller_in),
.memory_controller_size (Write4Blocks_memory_controller_size),
.memory_controller_waitrequest (Write4Blocks_memory_controller_waitrequest),
.memory_controller_out (Write4Blocks_memory_controller_out),
.arg_store1 (Write4Blocks_arg_store1),
.arg_store2 (Write4Blocks_arg_store2),
.arg_store3 (Write4Blocks_arg_store3),
.arg_store4 (Write4Blocks_arg_store4),
.arg_p_out_vpos (Write4Blocks_arg_p_out_vpos),
.arg_p_out_hpos (Write4Blocks_arg_p_out_hpos),
.arg_p_out_buf (Write4Blocks_arg_p_out_buf)
);
/* Unsynthesizable Statements */
always @(posedge clk) begin
/* main: %12*/
/* %13 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB8_14)
begin
$write("Not Jpeg File!\n");
end
/* main: %12*/
/* tail call void @exit(i32 0) noreturn nounwind*/
if (cur_state == LEGUP_F_main_BB8_14)
begin
$finish;
end
/* main: %next_marker.exit.i.i*/
/* %23 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str23, i32 0, i32 0), i32 %unread_marker.0.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
$write("\nmarker = 0x%0x\n", main_next_marker_exit_i_i_unread_marker_0_i_i);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) finish <= 0;
end
/* main: %32*/
/* %62 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str1, i32 0, i32 0), i32 %41) nounwind*/
if (cur_state == LEGUP_F_main_BB20_51)
begin
$write("length = %d\n", main_32_41_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_32_41_reg) === 1'bX) finish <= 0;
end
/* main: %32*/
/* %64 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str2, i32 0, i32 0), i32 %63) nounwind*/
if (cur_state == LEGUP_F_main_BB20_51)
begin
$write("data_precision = %d\n", main_32_63_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_32_63_reg) === 1'bX) finish <= 0;
end
/* main: %32*/
/* %67 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str3, i32 0, i32 0), i32 %66) nounwind*/
if (cur_state == LEGUP_F_main_BB20_54)
begin
$write("image_height = %d\n", main_32_66);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_32_66) === 1'bX) finish <= 0;
end
/* main: %32*/
/* %70 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str4, i32 0, i32 0), i32 %69) nounwind*/
if (cur_state == LEGUP_F_main_BB20_57)
begin
$write("image_width = %d\n", main_32_69);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_32_69) === 1'bX) finish <= 0;
end
/* main: %32*/
/* %72 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str5, i32 0, i32 0), i32 %71) nounwind*/
if (cur_state == LEGUP_F_main_BB20_57)
begin
$write("num_components = %d\n", main_32_71_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_32_71_reg) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i1.i.i*/
/* %108 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str6, i32 0, i32 0), i32 %107) nounwind*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
$write(" index = %d\n", main__lr_ph_i1_i_i_107_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_107_reg) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i1.i.i*/
/* %111 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str7, i32 0, i32 0), i32 %110) nounwind*/
if (cur_state == LEGUP_F_main_BB31_95)
begin
$write(" id = %d\n", main__lr_ph_i1_i_i_110);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_110) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i1.i.i*/
/* %114 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str8, i32 0, i32 0), i32 %113) nounwind*/
if (cur_state == LEGUP_F_main_BB31_98)
begin
$write(" h_samp_factor = %d\n", main__lr_ph_i1_i_i_113);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_113) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i1.i.i*/
/* %117 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str9, i32 0, i32 0), i32 %116) nounwind*/
if (cur_state == LEGUP_F_main_BB31_101)
begin
$write(" v_samp_factor = %d\n", main__lr_ph_i1_i_i_116);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_116) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i1.i.i*/
/* %120 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str10, i32 0, i32 0), i32 %119) nounwind*/
if (cur_state == LEGUP_F_main_BB31_104)
begin
$write(" quant_tbl_no = %d\n\n", main__lr_ph_i1_i_i_119);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_119) === 1'bX) finish <= 0;
end
/* main: %163*/
/* %164 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([27 x i8]* @.str11, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB43_143)
begin
$write("\nSampling Factor is 4:1:1\n");
end
/* main: %165*/
/* %166 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([27 x i8]* @.str12, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB44_144)
begin
$write("\nSampling Factor is 1:1:1\n");
end
/* main: %167*/
/* %180 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str13, i32 0, i32 0), i32 %176) nounwind*/
if (cur_state == LEGUP_F_main_BB45_148)
begin
$write(" length = %d\n", main_167_176);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_167_176) === 1'bX) finish <= 0;
end
/* main: %167*/
/* %181 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str14, i32 0, i32 0), i32 %179) nounwind*/
if (cur_state == LEGUP_F_main_BB45_149)
begin
$write(" num_comp = %d\n", main_167_179);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_167_179) === 1'bX) finish <= 0;
end
/* main: %209*/
/* %210 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([19 x i8]* @.str15, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB55_168)
begin
$write("Bad Component ID!\n");
end
/* main: %209*/
/* tail call void @exit(i32 0) noreturn nounwind*/
if (cur_state == LEGUP_F_main_BB55_168)
begin
$finish;
end
/* main: %211*/
/* %216 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str16, i32 0, i32 0), i32 %197) nounwind*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
$write(" comp_id = %d\n", main_194_197_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_194_197_reg) === 1'bX) finish <= 0;
end
/* main: %211*/
/* %219 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str17, i32 0, i32 0), i32 %218) nounwind*/
if (cur_state == LEGUP_F_main_BB56_176)
begin
$write(" dc_tbl_no = %d\n", main_211_218);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_211_218) === 1'bX) finish <= 0;
end
/* main: %211*/
/* %222 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str18, i32 0, i32 0), i32 %221) nounwind*/
if (cur_state == LEGUP_F_main_BB56_179)
begin
$write(" ac_tbl_no = %d\n", main_211_221);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_211_221) === 1'bX) finish <= 0;
end
/* main: %248*/
/* %259 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str13, i32 0, i32 0), i32 %258) nounwind*/
if (cur_state == LEGUP_F_main_BB64_204)
begin
$write(" length = %d\n", main_248_258);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_248_258) === 1'bX) finish <= 0;
end
/* main: %.lr.ph5.i.i.i*/
/* %269 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([15 x i8]* @.str19, i32 0, i32 0), i32 %268) nounwind*/
if (cur_state == LEGUP_F_main_BB67_214)
begin
$write(" index = 0x%0x\n", main__lr_ph5_i_i_i_268);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_268) === 1'bX) finish <= 0;
end
/* main: %293*/
/* %294 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str20, i32 0, i32 0), i32 %292) nounwind*/
if (cur_state == LEGUP_F_main_BB74_228)
begin
$write(" count = %d\n", main_287_292_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_287_292_reg) === 1'bX) finish <= 0;
end
/* main: %312*/
/* %323 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str13, i32 0, i32 0), i32 %322) nounwind*/
if (cur_state == LEGUP_F_main_BB79_243)
begin
$write(" length = %d\n", main_312_322);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_312_322) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i15.i.i*/
/* %336 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str21, i32 0, i32 0), i32 %334) nounwind*/
if (cur_state == LEGUP_F_main_BB82_253)
begin
$write(" prec = %d\n", main__lr_ph_i15_i_i_334);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_334) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i15.i.i*/
/* %337 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str22, i32 0, i32 0), i32 %335) nounwind*/
if (cur_state == LEGUP_F_main_BB82_253)
begin
$write(" num = %d\n", main__lr_ph_i15_i_i_335);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_335) === 1'bX) finish <= 0;
end
/* main: %389*/
/* %390 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([26 x i8]* @.str24, i32 0, i32 0), i32 %384) nounwind*/
if (cur_state == LEGUP_F_main_BB91_355)
begin
$write("Decode 1:1:1 NumMCU = %d\n", main_read_markers_exit_i_384_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_read_markers_exit_i_384_reg) === 1'bX) finish <= 0;
end
/* main: %449*/
/* %450 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([26 x i8]* @.str25, i32 0, i32 0), i32 %384) nounwind*/
if (cur_state == LEGUP_F_main_BB114_406)
begin
$write("Decode 4:1:1 NumMCU = %d\n", main_read_markers_exit_i_384_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_read_markers_exit_i_384_reg) === 1'bX) finish <= 0;
end
/* main: %jpeg2bmp_main.exit*/
/* %510 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str27, i32 0, i32 0), i32 %.storemerge) nounwind*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
$write("Result: %d\n", main_jpeg2bmp_main_exit__storemerge);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_jpeg2bmp_main_exit__storemerge) === 1'bX) finish <= 0;
end
/* main: %520*/
/* %521 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str28, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB135_473)
begin
$write("RESULT: PASS\n");
end
/* main: %522*/
/* %523 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str29, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB136_474)
begin
$write("RESULT: FAIL\n");
end
end
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 9'd0;
if (^reset !== 1'bX && ^(9'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_main_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB1_3;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB1_3;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_3 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB4_7;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB4_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB4_7;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB4_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB5_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB5_8 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB6_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB6_9 & memory_controller_waitrequest == 1'd0 & main__outer_i_i_sow_SOI_0_ph_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB7_10;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB6_9 & memory_controller_waitrequest == 1'd0 & main__outer_i_i_sow_SOI_0_ph_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB11_19;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB7_10;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_10 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB7_11;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB7_11;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB7_12;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB7_12;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_12 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB7_13;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB7_13;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_13 & memory_controller_waitrequest == 1'd0 & main_6_or_cond_i_i_i == 1'd1)
begin
cur_state <= LEGUP_F_main_BB9_15;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_13 & memory_controller_waitrequest == 1'd0 & main_6_or_cond_i_i_i == 1'd0)
begin
cur_state <= LEGUP_F_main_BB8_14;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB8_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB8_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB8_14;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB8_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB8_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB9_15;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_15 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB9_16;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB9_16;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_16 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB9_17;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB9_17;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_17 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB17_31;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB10_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB10_18;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB10_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB10_18 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB11_19;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB11_19;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB11_20;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB11_20;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_20 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB11_21;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB11_21;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_21 & memory_controller_waitrequest == 1'd0 & main__loopexit3_i_i_i_19 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB14_26;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB14_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_21 & memory_controller_waitrequest == 1'd0 & main__loopexit3_i_i_i_19 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB12_22;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB12_22;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_22 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB12_23;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB12_23;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_23 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB12_24;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB12_24;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_24 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i_i_i_20 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB13_25;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB13_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_24 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i_i_i_20 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB12_22;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB13_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB13_25;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB13_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB13_25 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB14_26;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB14_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB14_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB14_26;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB14_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB14_26 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB15_27;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB15_27;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_27 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB15_28;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB15_28;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_28 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB15_29;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB15_29;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_29 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_i_22 == 32'd255)
begin
cur_state <= LEGUP_F_main_BB15_27;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_29 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_i_22 == 32'd0)
begin
cur_state <= LEGUP_F_main_BB10_18;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB10_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_29 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_i_22 != 32'd255 & main__loopexit_i_i_i_22 != 32'd0)
begin
cur_state <= LEGUP_F_main_BB16_30;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB16_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB16_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB16_30;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB16_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB16_30 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB17_31;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB17_31;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB17_32;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB17_32;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_32 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB17_33;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB17_33;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB17_34;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB17_34;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_34 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_27 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB18_35;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_34 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_27 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB19_38;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB19_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB18_35;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_35 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB18_36;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB18_36;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_36 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB18_37;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB18_37;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB19_38;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB19_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB19_38;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB19_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
cur_state <= LEGUP_F_main_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd192)
begin
cur_state <= LEGUP_F_main_BB20_39;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd218)
begin
cur_state <= LEGUP_F_main_BB45_145;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_145) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd196)
begin
cur_state <= LEGUP_F_main_BB64_201;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd219)
begin
cur_state <= LEGUP_F_main_BB79_240;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_240) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd217)
begin
cur_state <= LEGUP_F_main_BB90_277;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_277) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd216 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd192 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd218 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd196 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd219 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd217)
begin
cur_state <= LEGUP_F_main_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_39 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_39;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_39 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_40;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_40 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_40;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_40 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_41;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_41 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_41;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_41 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_42;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_42 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_42;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_42 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_43;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_43 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_43;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_43 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_44;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_44 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_44;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_44 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_45;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_45 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_45;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_45 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_46;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_46 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_46;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_46 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_47;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_47 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_47;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_47 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_48;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_48 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_48;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_48 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_49;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_49 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_49;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_49 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_50;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_50 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_50;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_50 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_51;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_51 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_51;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_51 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_52;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_52 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_52;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_52 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_53;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_53 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_53;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_53 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_54;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_54 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_54;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_54 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_55;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_55 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_55;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_55 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_56;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_56 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_56;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_56 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_57;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_57 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_57;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_57 & memory_controller_waitrequest == 1'd0 & main_32_73_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB21_58;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_57 & memory_controller_waitrequest == 1'd0 & main_32_73_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB22_61;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB22_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_58 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB21_58;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_58 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB21_59;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_59) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_59 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB21_59;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_59) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_59 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB21_60;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_60 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB21_60;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_60 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB22_61;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB22_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB22_61 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB22_61;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB22_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB22_61 & memory_controller_waitrequest == 1'd0 & main_77_78 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB23_62;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_62) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB22_61 & memory_controller_waitrequest == 1'd0 & main_77_78 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB24_65;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_62 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB23_62;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_62) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_62 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB23_63;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_63) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_63 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB23_63;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_63) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_63 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB23_64;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_64) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_64 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB23_64;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_64) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_64 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB24_65;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_65 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB24_65;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_65 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB24_66;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_66) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_66 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB24_66;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_66) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_66 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB24_67;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_67) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_67 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB24_67;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_67) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_67 & memory_controller_waitrequest == 1'd0 & main_82_84 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB25_68;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_68) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_67 & memory_controller_waitrequest == 1'd0 & main_82_84 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB26_71;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_68 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB25_68;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_68) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_68 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB25_69;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_69 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB25_69;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_69 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB25_70;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_70) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_70 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB25_70;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_70) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_70 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB26_71;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_71 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB26_71;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_71 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB26_72;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_72 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB26_72;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_72 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB26_73;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_73 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB26_73;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_73 & memory_controller_waitrequest == 1'd0 & main_88_90 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB27_74;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_74) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_73 & memory_controller_waitrequest == 1'd0 & main_88_90 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB28_77;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB28_77) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_74 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB27_74;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_74) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_74 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB27_75;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_75) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_75 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB27_75;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_75) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_75 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB27_76;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_76) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_76 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB27_76;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_76) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_76 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB28_77;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB28_77) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB28_77 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB28_77;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB28_77) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB28_77 & memory_controller_waitrequest == 1'd0 & main_94_95 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB29_78;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_78) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB28_77 & memory_controller_waitrequest == 1'd0 & main_94_95 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB30_81;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB30_81) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_78 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB29_78;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_78) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_78 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB29_79;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_79) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_79 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB29_79;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_79) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_79 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB29_80;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_80) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_80 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB29_80;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_80) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_80 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_82;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB30_81;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB30_81) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd0 & main__preheader_i_i_i_98 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_82;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd0 & main__preheader_i_i_i_98 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB42_140;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_82 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_82;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_82 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_83;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_83) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_83 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_83;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_83) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_83 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_84;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_84) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_84 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_84;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_84) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_84 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_85;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_85) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_85 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_85;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_85) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_85 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_86;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_86) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_86 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_86;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_86) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_86 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_87;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_87) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_87 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_87;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_87) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_87 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_88;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_88) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_88 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_88;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_88) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_88 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_89;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_89) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_89 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_89;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_89) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_89 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_90;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_90 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_90;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_90 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_91;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_91) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_91 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_91;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_91) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_91 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_92;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_92) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_92 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_92;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_92) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_92 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_93;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_93) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_93 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_93;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_93) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_93 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_94;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_94) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_94 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_94;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_94) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_94 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_95;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_95) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_95 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_95;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_95) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_95 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_96;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_96) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_96 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_96;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_96) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_96 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_97;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_97) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_97 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_97;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_97) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_97 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_98;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_98 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_98;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_98 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_99;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_99 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_99;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_99 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_100;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_100 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_100;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_100 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_101;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_101 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_101;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_101 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_102;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_102) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_102 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_102;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_102) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_102 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_103;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_103 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_103;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_103 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_104;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_104 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_104;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_104 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_105;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_105 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_105;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_105 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_106;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_106 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_106;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_106 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_107;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_107) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_107 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_107;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_107) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_107 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_108;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_108) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_108 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_108;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_108) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_108 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i1_i_i_124 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB32_109;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_108 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i1_i_i_124 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB33_112;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_109 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB32_109;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_109 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB32_110;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_110) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_110 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB32_110;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_110) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_110 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB32_111;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_111) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_111 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB32_111;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_111) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_111 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB33_112;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_112 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB33_112;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_112 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB33_113;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_113) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_113 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB33_113;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_113) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_113 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB33_114;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_114 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB33_114;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_114 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB33_115;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_115) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_115 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB33_115;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_115) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_115 & memory_controller_waitrequest == 1'd0 & main_128_132 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB34_116;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_115 & memory_controller_waitrequest == 1'd0 & main_128_132 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB35_119;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_119) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_116 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB34_116;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_116 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB34_117;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_117) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_117 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB34_117;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_117) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_117 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB34_118;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_118) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_118 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB34_118;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_118) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_118 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB35_119;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_119) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_119 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB35_119;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_119) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_119 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB35_120;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_120) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_120 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB35_120;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_120) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_120 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB35_121;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_121) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_121 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB35_121;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_121) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_121 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB35_122;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_122 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB35_122;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_122 & memory_controller_waitrequest == 1'd0 & main_136_140 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB36_123;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_123) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_122 & memory_controller_waitrequest == 1'd0 & main_136_140 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB37_126;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_126) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_123 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB36_123;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_123) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_123 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB36_124;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_124) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_124 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB36_124;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_124) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_124 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB36_125;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_125) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_125 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB36_125;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_125) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_125 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB37_126;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_126) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_126 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB37_126;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_126) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_126 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB37_127;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_127) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_127 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB37_127;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_127) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_127 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB37_128;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_128) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_128 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB37_128;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_128) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_128 & memory_controller_waitrequest == 1'd0 & main_144_147 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB38_129;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_128 & memory_controller_waitrequest == 1'd0 & main_144_147 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB39_132;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_129 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB38_129;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_129 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB38_130;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_130 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB38_130;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_130 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB38_131;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_131 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB38_131;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_131 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB39_132;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_132 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB39_132;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_132 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB39_133;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_133 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB39_133;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_133 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB39_134;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_134 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB39_134;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_134 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB39_135;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_135 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB39_135;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_135 & memory_controller_waitrequest == 1'd0 & main_151_155 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB40_136;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_135 & memory_controller_waitrequest == 1'd0 & main_151_155 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB41_139;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB41_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_136 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB40_136;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_136 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB40_137;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_137) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_137 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB40_137;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_137) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_137 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB40_138;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_138) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_138 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB40_138;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_138) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_138 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB41_139;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB41_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB41_139;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB41_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd0 & main_159_160 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_82;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd0 & main_159_160 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB42_140;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_140 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB42_140;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_140 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB42_141;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_141) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_141 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB42_141;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_141) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_141 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB42_142;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_142) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_142 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB42_142;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_142) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_142 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i_i_i_162 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB43_143;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB43_143) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_142 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i_i_i_162 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB44_144;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB44_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB43_143;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB43_143) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB44_144;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB44_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_145 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB45_145;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_145) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_145 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB45_146;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_146) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_146 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB45_146;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_146) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_146 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB45_147;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_147 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB45_147;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_147 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB45_148;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_148) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_148 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB45_148;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_148) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_148 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB45_149;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_149) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_149 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB45_149;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_149) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_149 & memory_controller_waitrequest == 1'd0 & main_167_182_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB46_150;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_149 & memory_controller_waitrequest == 1'd0 & main_167_182_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB47_153;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB47_153) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_150 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB46_150;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_150 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB46_151;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_151 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB46_151;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_151 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB46_152;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_152) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_152 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB46_152;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_152) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_152 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB47_153;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB47_153) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB47_153 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB47_153;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB47_153) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB47_153 & memory_controller_waitrequest == 1'd0 & main_186_187 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB48_154;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_154) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB47_153 & memory_controller_waitrequest == 1'd0 & main_186_187 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB49_157;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB49_157) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_154 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB48_154;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_154) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_154 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB48_155;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_155) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_155 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB48_155;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_155) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_155 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB48_156;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_156) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_156 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB48_156;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_156) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_156 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB49_157;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB49_157) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB49_157 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB49_157;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB49_157) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB49_157 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB50_158;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB50_158) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB50_158 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB50_158;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB50_158) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB50_158 & memory_controller_waitrequest == 1'd0 & main__preheader5_i_i_i_193 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB51_159;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_159) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB50_158 & memory_controller_waitrequest == 1'd0 & main__preheader5_i_i_i_193 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB63_200;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB63_200) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_159 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB51_159;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_159) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_159 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB51_160;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_160) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_160 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB51_160;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_160) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_160 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB51_161;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_161) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_161 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB51_161;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_161) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_161 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB51_162;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_162) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_162 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB51_162;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_162) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_162 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB52_163;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB52_163) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB52_163 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB52_163;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB52_163) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB52_163 & memory_controller_waitrequest == 1'd0 & main_200_202 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB53_164;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_164) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB52_163 & memory_controller_waitrequest == 1'd0 & main_200_202 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB55_168;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB55_168) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_164 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB53_164;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_164) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_164 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB53_165;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_165) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_165 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB53_165;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_165) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_165 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB53_166;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_166) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_166 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB53_166;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_166) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_166 & memory_controller_waitrequest == 1'd0 & main_203_206 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_169;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_169) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_166 & memory_controller_waitrequest == 1'd0 & main_203_206 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB54_167;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB54_167) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB54_167 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB54_167;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB54_167) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB54_167 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB52_163;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB52_163) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB55_168 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB55_168;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB55_168) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB55_168 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_169 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_169;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_169) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_169 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_170;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_170) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_170 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_170;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_170) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_170 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_171;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_171) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_171 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_171;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_171) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_171 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_172;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_172) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_172 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_172;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_172) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_172 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_173;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_173) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_173 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_173;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_173) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_173 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_174;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_174) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_174 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_174;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_174) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_174 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_175;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_175) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_175 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_175;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_175) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_175 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_176;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_176) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_176 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_176;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_176) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_176 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_177;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_177) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_177 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_177;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_177) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_177 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_178;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_178) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_178 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_178;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_178) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_178 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_179;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_179) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_179 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_179;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_179) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_179 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_180;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_180) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_180 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_180;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_180) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_180 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_181;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_181) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_181 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_181;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_181) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_181 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_182;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_182) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_182 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_182;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_182) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_182 & memory_controller_waitrequest == 1'd0 & main_211_225 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB57_183;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_183) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_182 & memory_controller_waitrequest == 1'd0 & main_211_225 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB58_186;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_186) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_183 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB57_183;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_183) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_183 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB57_184;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_184) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_184 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB57_184;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_184) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_184 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB57_185;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_185) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_185 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB57_185;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_185) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_185 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB58_186;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_186) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_186 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB58_186;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_186) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_186 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB58_187;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_187) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_187 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB58_187;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_187) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_187 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB58_188;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_188) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_188 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB58_188;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_188) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_188 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB58_189;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_189) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_189 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB58_189;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_189) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_189 & memory_controller_waitrequest == 1'd0 & main_229_234 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB59_190;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_190) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_189 & memory_controller_waitrequest == 1'd0 & main_229_234 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB60_193;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_193) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_190 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB59_190;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_190) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_190 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB59_191;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_191) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_191 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB59_191;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_191) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_191 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB59_192;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_192 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB59_192;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_192 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB60_193;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_193) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_193 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB60_193;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_193) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_193 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB60_194;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_194) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_194 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB60_194;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_194) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_194 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB60_195;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_195) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_195 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB60_195;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_195) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_195 & memory_controller_waitrequest == 1'd0 & main_238_241 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB61_196;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_196) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_195 & memory_controller_waitrequest == 1'd0 & main_238_241 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB62_199;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB62_199) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_196 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB61_196;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_196) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_196 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB61_197;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_197) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_197 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB61_197;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_197) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_197 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB61_198;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_198) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_198 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB61_198;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_198) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_198 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB62_199;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB62_199) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB62_199 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB62_199;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB62_199) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB62_199 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB50_158;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB50_158) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB63_200 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB63_200;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB63_200) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB63_200 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_277;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_277) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_201 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_201;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_201 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_202;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_202) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_202 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_202;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_202) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_202 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_203;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_203) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_203 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_203;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_203) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_203 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_204;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_204) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_204 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_204;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_204) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_204 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_205;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_205) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_205 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_205;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_205) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_205 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_206;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_206) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_206 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_206;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_206) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_206 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_207;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_207) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_207 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_207;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_207) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_207 & memory_controller_waitrequest == 1'd0 & main_248_261 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB65_208;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_208) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_207 & memory_controller_waitrequest == 1'd0 & main_248_261 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB66_211;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB66_211) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_208 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB65_208;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_208) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_208 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB65_209;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_209) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_209 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB65_209;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_209) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_209 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB65_210;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_210) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_210 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB65_210;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_210) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_210 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB66_211;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB66_211) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB66_211;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB66_211) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_212;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_212) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_212 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_212;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_212) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_212 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB67_213;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_213) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_213 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_213;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_213) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_213 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB67_214;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_214) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_214 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_214;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_214) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_214 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB67_215;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_215) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_215 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_215;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_215) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_215 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB67_216;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_216) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_216 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_216;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_216) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_216 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB67_217;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_217) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_217 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_217;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_217) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_217 & memory_controller_waitrequest == 1'd0 & main__lr_ph5_i_i_i_272 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB68_218;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_218) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_217 & memory_controller_waitrequest == 1'd0 & main__lr_ph5_i_i_i_272 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB69_221;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB69_221) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_218 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB68_218;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_218) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_218 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB68_219;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_219) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_219 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB68_219;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_219) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_219 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB68_220;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_220) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_220 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB68_220;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_220) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_220 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB69_221;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB69_221) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB69_221 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB69_221;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB69_221) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB69_221 & memory_controller_waitrequest == 1'd0 & main_276_278 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB71_223;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB71_223) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB69_221 & memory_controller_waitrequest == 1'd0 & main_276_278 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB70_222;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB70_222) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB70_222 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB70_222;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB70_222) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB70_222 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB72_224;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB72_224) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB71_223 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB71_223;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB71_223) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB71_223 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB72_224;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB72_224) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB72_224 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB72_224;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB72_224) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB72_224 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB73_225;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_225) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_225 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB73_225;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_225) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_225 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB73_226;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_226) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_226 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB73_226;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_226) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_226 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB73_227;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_227) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB73_227;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_227) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd0 & main_287_exitcond_i_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB74_228;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_228) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd0 & main_287_exitcond_i_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB73_225;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_225) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_228 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB74_228;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_228) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_228 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB74_229;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_229) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_229 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB74_229;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_229) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_229 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB74_230;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_230) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_230 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB74_230;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_230) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_230 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB74_231;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_231) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_231 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB74_231;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_231) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_231 & memory_controller_waitrequest == 1'd0 & main_293_297 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB75_232;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_232) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_231 & memory_controller_waitrequest == 1'd0 & main_293_297 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB76_235;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB76_235) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_232 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB75_232;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_232) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_232 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB75_233;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_233) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_233 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB75_233;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_233) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_233 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB75_234;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_234) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_234 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB75_234;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_234) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_234 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB76_235;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB76_235) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB76_235;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB76_235) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd0 & main_301_303 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB77_236;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_236) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd0 & main_301_303 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB78_239;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB78_239) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_236 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB77_236;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_236) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_236 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB77_237;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_237) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_237 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB77_237;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_237) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_237 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB77_238;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_238) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB77_238;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_238) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i10_i_i_exitcond7_i_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB78_239;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB78_239) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i10_i_i_exitcond7_i_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB77_236;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_236) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB78_239;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB78_239) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_212;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_212) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_240 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_240;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_240) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_240 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_241;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_241) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_241 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_241;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_241) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_241 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_242;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_242) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_242 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_242;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_242) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_242 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_243;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_243) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_243 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_243;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_243) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_243 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_244;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_244) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_244 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_244;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_244) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_244 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_245;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_245) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_245 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_245;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_245) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_245 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_246;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_246) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_246 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_246;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_246) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_246 & memory_controller_waitrequest == 1'd0 & main_312_325 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB80_247;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_247) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_246 & memory_controller_waitrequest == 1'd0 & main_312_325 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB81_250;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB81_250) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_247 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB80_247;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_247) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_247 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB80_248;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_248) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_248 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB80_248;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_248) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_248 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB80_249;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_249) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_249 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB80_249;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_249) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_249 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB81_250;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB81_250) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB81_250;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB81_250) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_251;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_251) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_251 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_251;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_251) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_251 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB82_252;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_252) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_252 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_252;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_252) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_252 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB82_253;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_253) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_253 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_253;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_253) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_253 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB82_254;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_254) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_254 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_254;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_254) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_254 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB82_255;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_255 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_255;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_255 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB82_256;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_256) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_256 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_256;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_256) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_256 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i15_i_i_340 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB83_257;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_257) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_256 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i15_i_i_340 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB84_260;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_260) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_257 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB83_257;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_257) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_257 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB83_258;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_258) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_258 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB83_258;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_258) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_258 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB83_259;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_259) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_259 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB83_259;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_259) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_259 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB84_260;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_260) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_260 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB84_260;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_260) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_260 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB84_261;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_261) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_261 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB84_261;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_261) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_261 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB84_262;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_262) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_262 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB84_262;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_262) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_262 & memory_controller_waitrequest == 1'd0 & main_344_347 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB85_263;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_263) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_262 & memory_controller_waitrequest == 1'd0 & main_344_347 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB86_266;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB86_266) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_263 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB85_263;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_263) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_263 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB85_264;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_264) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_264 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB85_264;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_264) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_264 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB85_265;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_265) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_265 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB85_265;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_265) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_265 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB86_266;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB86_266) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB86_266;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB86_266) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB87_267;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_267) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_271;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_271) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_267 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB87_267;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_267) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_267 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB87_268;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_268) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_268 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB87_268;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_268) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_268 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB87_269;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_269) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_269 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB87_269;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_269) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_269 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB87_270;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_270) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB87_270;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_270) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd0 & main__split_us_i_i_i_exitcond_i17_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB89_276;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB89_276) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd0 & main__split_us_i_i_i_exitcond_i17_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB87_267;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_267) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_271 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB88_271;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_271) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_271 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_272;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_272) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_272 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB88_272;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_272) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_272 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_273;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_273) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_273 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB88_273;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_273) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_273 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_274;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_274) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_274 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB88_274;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_274) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_274 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_275;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_275) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB88_275;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_275) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd0 & main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB89_276;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB89_276) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd0 & main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_271;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_271) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB89_276;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB89_276) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_251;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_251) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB4_7;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB4_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_277 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_277;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_277) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_277 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_278;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_278) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_278 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_278;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_278) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_278 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_279;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_279) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_279 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_279;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_279) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_279 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_280;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_280) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_280 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_280;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_280) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_280 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_281;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_281) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_281 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_281;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_281) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_281 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_282;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_282) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_282 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_282;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_282) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_282 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_283;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_283) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_283 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_283;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_283) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_283 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_284;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_284) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_284 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_284;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_284) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_284 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_285;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_285) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_285 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_285;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_285) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_285 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_286;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_286) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_286 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_286;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_286) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_286 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_287;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_287) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_287 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_287;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_287) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_287 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_288;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_288) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_288 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_288;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_288) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_288 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_289;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_289) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_289 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_289;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_289) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_289 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_290;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_290) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_290 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_290;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_290) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_290 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_291;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_291) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_291 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_291;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_291) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_291 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_292;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_292) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_292 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_292;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_292) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_292 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_293;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_293) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_293 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_293;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_293) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_293 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_294;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_294) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_294 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_294;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_294) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_294 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_295;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_295) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_295 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_295;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_295) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_295 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_296;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_296) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_296 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_296;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_296) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_296 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_297;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_297) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_297 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_297;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_297) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_297 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_298;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_298) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_298 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_298;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_298) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_298 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_299;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_299) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_299 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_299;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_299) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_299 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_300;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_300) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_300 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_300;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_300) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_300 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_301;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_301) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_301 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_301;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_301) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_301 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_302;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_302) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_302 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_302;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_302) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_302 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_303;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_303) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_303 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_303;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_303) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_303 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_304;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_304) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_304 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_304;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_304) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_304 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_305;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_305) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_305 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_305;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_305) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_305 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_306;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_306) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_306 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_306;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_306) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_306 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_307;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_307) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_307 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_307;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_307) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_307 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_308;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_308) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_308 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_308;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_308) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_308 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_309;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_309) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_309 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_309;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_309) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_309 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_310;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_310) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_310 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_310;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_310) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_310 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_311;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_311) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_311 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_311;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_311) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_311 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_312;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_312) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_312 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_312;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_312) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_312 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_313;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_313) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_313 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_313;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_313) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_313 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_314;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_314) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_314 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_314;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_314) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_314 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_315;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_315) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_315 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_315;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_315) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_315 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_316;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_316) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_316 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_316;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_316) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_316 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_317;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_317) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_317 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_317;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_317) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_317 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_318;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_318) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_318 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_318;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_318) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_318 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_319;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_319) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_319 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_319;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_319) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_319 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_320;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_320) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_320 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_320;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_320) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_320 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_321;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_321) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_321 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_321;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_321) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_321 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_322;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_322) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_322 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_322;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_322) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_322 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_323;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_323) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_323 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_323;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_323) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_323 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_324;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_324) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_324 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_324;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_324) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_324 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_325;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_325) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_325 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_325;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_325) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_325 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_326;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_326) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_326 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_326;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_326) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_326 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_327;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_327) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_327 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_327;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_327) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_327 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_328;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_328) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_328 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_328;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_328) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_328 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_329;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_329) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_329 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_329;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_329) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_329 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_330;
if (^reset !== 1'bX && ^(LEGUP_function_call_330) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_330 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_330;
if (^reset !== 1'bX && ^(LEGUP_function_call_330) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_330 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_331;
if (^reset !== 1'bX && ^(LEGUP_function_call_331) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_330 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_330;
if (^reset !== 1'bX && ^(LEGUP_function_call_330) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_331 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_331;
if (^reset !== 1'bX && ^(LEGUP_function_call_331) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_331 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_332;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_332) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_332 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_332;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_332) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_332 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_333;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_333) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_333 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_333;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_333) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_333 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_334;
if (^reset !== 1'bX && ^(LEGUP_function_call_334) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_334 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_334;
if (^reset !== 1'bX && ^(LEGUP_function_call_334) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_334 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_335;
if (^reset !== 1'bX && ^(LEGUP_function_call_335) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_334 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_334;
if (^reset !== 1'bX && ^(LEGUP_function_call_334) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_335 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_335;
if (^reset !== 1'bX && ^(LEGUP_function_call_335) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_335 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_336;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_336) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_336 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_336;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_336) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_336 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_337;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_337) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_337 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_337;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_337) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_337 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_338;
if (^reset !== 1'bX && ^(LEGUP_function_call_338) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_338 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_338;
if (^reset !== 1'bX && ^(LEGUP_function_call_338) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_338 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_339;
if (^reset !== 1'bX && ^(LEGUP_function_call_339) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_338 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_338;
if (^reset !== 1'bX && ^(LEGUP_function_call_338) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_339 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_339;
if (^reset !== 1'bX && ^(LEGUP_function_call_339) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_339 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_340;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_340) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_340 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_340;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_340) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_340 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_341;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_341) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_341 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_341;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_341) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_341 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_342;
if (^reset !== 1'bX && ^(LEGUP_function_call_342) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_342 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_342;
if (^reset !== 1'bX && ^(LEGUP_function_call_342) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_342 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_343;
if (^reset !== 1'bX && ^(LEGUP_function_call_343) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_342 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_342;
if (^reset !== 1'bX && ^(LEGUP_function_call_342) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_343 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_343;
if (^reset !== 1'bX && ^(LEGUP_function_call_343) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_343 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_344;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_344) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_344 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_344;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_344) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_344 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_345;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_345) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_345 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_345;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_345) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_345 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_346;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_346) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_346 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_346;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_346) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_346 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_347;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_347) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_347 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_347;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_347) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_347 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_348;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_348) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_348 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_348;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_348) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_348 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_349;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_349) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_349 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_349;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_349) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_349 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_350;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_350 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_350;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_350 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_351;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_351) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_351 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_351;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_351) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_351 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_352;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_352) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_352 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_352;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_352) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_352 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_353;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_353) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_353 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_353;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_353) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_353 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_354;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_354) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_354 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_354;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_354) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_354 & memory_controller_waitrequest == 1'd0 & main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB114_406;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB114_406) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_354 & memory_controller_waitrequest == 1'd0 & main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB91_355;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB91_355) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB91_355 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB91_355;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB91_355) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB91_355 & memory_controller_waitrequest == 1'd0 & main_389_391 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB92_356;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB92_356) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB91_355 & memory_controller_waitrequest == 1'd0 & main_389_391 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_454;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_454) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB92_356 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB92_356;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB92_356) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB92_356 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB93_357;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_357) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_357 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB93_357;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_357) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_357 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_358;
if (^reset !== 1'bX && ^(LEGUP_function_call_358) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_358 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_358;
if (^reset !== 1'bX && ^(LEGUP_function_call_358) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_358 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_359;
if (^reset !== 1'bX && ^(LEGUP_function_call_359) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_358 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_358;
if (^reset !== 1'bX && ^(LEGUP_function_call_358) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_359 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_359;
if (^reset !== 1'bX && ^(LEGUP_function_call_359) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_359 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB93_360;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_360) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_360 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB93_360;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_360) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_360 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_361;
if (^reset !== 1'bX && ^(LEGUP_function_call_361) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_361 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_361;
if (^reset !== 1'bX && ^(LEGUP_function_call_361) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_361 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_362;
if (^reset !== 1'bX && ^(LEGUP_function_call_362) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_361 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_361;
if (^reset !== 1'bX && ^(LEGUP_function_call_361) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_362 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_362;
if (^reset !== 1'bX && ^(LEGUP_function_call_362) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_362 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB93_363;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_363) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_363 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB93_363;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_363) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_363 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_364;
if (^reset !== 1'bX && ^(LEGUP_function_call_364) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_364 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_364;
if (^reset !== 1'bX && ^(LEGUP_function_call_364) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_364 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_365;
if (^reset !== 1'bX && ^(LEGUP_function_call_365) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_364 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_364;
if (^reset !== 1'bX && ^(LEGUP_function_call_364) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_365 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_365;
if (^reset !== 1'bX && ^(LEGUP_function_call_365) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_365 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_366;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_366) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_366 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_366;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_366) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_366 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_367;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_367) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_367 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_367;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_367) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_367 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_368;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_368) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_368 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_368;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_368) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_368 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_369;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_369) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_369 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_369;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_369) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_369 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_370;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_370) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_370 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_370;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_370) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_370 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_371;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_371) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_371 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_371;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_371) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_371 & memory_controller_waitrequest == 1'd0 & main_392_411 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB97_374;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB97_374) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_371 & memory_controller_waitrequest == 1'd0 & main_392_411 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB95_372;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB95_372) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB95_372 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB95_372;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB95_372) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB95_372 & memory_controller_waitrequest == 1'd0 & main_412_413 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB96_373;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB96_373) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB95_372 & memory_controller_waitrequest == 1'd0 & main_412_413 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB97_374;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB97_374) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB96_373 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB96_373;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB96_373) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB96_373 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB97_374;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB97_374) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB97_374 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB97_374;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB97_374) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB97_374 & memory_controller_waitrequest == 1'd0 & main_415_416 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB100_377;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB100_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB97_374 & memory_controller_waitrequest == 1'd0 & main_415_416 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB98_375;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB98_375) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB98_375 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB98_375;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB98_375) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB98_375 & memory_controller_waitrequest == 1'd0 & main_417_418 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB99_376;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB99_376) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB98_375 & memory_controller_waitrequest == 1'd0 & main_417_418 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB100_377;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB100_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB99_376 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB99_376;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB99_376) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB99_376 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB100_377;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB100_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB100_377 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB100_377;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB100_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB100_377 & memory_controller_waitrequest == 1'd0 & main_420_421 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB103_380;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_380) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB100_377 & memory_controller_waitrequest == 1'd0 & main_420_421 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB101_378;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB101_378) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB101_378 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB101_378;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB101_378) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB101_378 & memory_controller_waitrequest == 1'd0 & main_422_423 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB102_379;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB102_379) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB101_378 & memory_controller_waitrequest == 1'd0 & main_422_423 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB103_380;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_380) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB102_379 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB102_379;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB102_379) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB102_379 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB103_380;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_380) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_380 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB103_380;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_380) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_380 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB103_381;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_381) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_381 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB103_381;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_381) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_381 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB103_382;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_382) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_382 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB103_382;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_382) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_382 & memory_controller_waitrequest == 1'd0 & main_425_exitcond53_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_383;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_383) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_382 & memory_controller_waitrequest == 1'd0 & main_425_exitcond53_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_366;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_366) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_383 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_383;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_383) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_383 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB104_384;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_384) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_384 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_384;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_384) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_384 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB104_385;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_385) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_385 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_385;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_385) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_385 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB104_386;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_386) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_386 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_386;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_386) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_386 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB104_387;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_387) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_387 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_387;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_387) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_387 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB104_388;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_388) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_388 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_388;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_388) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_388 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB105_389;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_389) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_389 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB105_389;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_389) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_389 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB105_390;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_390) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_390 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB105_390;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_390) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_390 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB105_391;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_391) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_391 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB105_391;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_391) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_391 & memory_controller_waitrequest == 1'd0 & main_432_or_cond_i_i_i_i == 1'd1)
begin
cur_state <= LEGUP_F_main_BB106_392;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_392) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_391 & memory_controller_waitrequest == 1'd0 & main_432_or_cond_i_i_i_i == 1'd0)
begin
cur_state <= LEGUP_F_main_BB110_400;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_400) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_392 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB106_392;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_392) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_392 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB106_393;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_393) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_393 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB106_393;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_393) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_393 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB106_394;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_394) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_394 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB106_394;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_394) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_394 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB109_399;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB109_399) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB107_395 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB107_395;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB107_395) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB107_395 & memory_controller_waitrequest == 1'd0 & main_439_exitcond93_i_i == 1'd1)
begin
cur_state <= LEGUP_F_main_BB110_400;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_400) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB107_395 & memory_controller_waitrequest == 1'd0 & main_439_exitcond93_i_i == 1'd0)
begin
cur_state <= LEGUP_F_main_BB109_399;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB109_399) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_396 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB108_396;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_396) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_396 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB108_397;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_397) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_397 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB108_397;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_397) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_397 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB108_398;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_398) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_398 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB108_398;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_398) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_398 & memory_controller_waitrequest == 1'd0 & main_440_exitcond70_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB107_395;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB107_395) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_398 & memory_controller_waitrequest == 1'd0 & main_440_exitcond70_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB108_396;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_396) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB109_399 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB109_399;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB109_399) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB109_399 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB108_396;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_396) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_400 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB110_400;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_400) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_400 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB110_401;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_401) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_401 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB110_401;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_401) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_401 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB110_402;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_402) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_402 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB110_402;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_402) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_402 & memory_controller_waitrequest == 1'd0 & main_WriteOneBlock_exit_i_i_i_444 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB112_404;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB112_404) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_402 & memory_controller_waitrequest == 1'd0 & main_WriteOneBlock_exit_i_i_i_444 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB111_403;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB111_403) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB111_403 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB111_403;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB111_403) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB111_403 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB112_404;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB112_404) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB112_404 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB112_404;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB112_404) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB112_404 & memory_controller_waitrequest == 1'd0 & main_WriteBlock_exit_i_i_exitcond116_i_i == 1'd1)
begin
cur_state <= LEGUP_F_main_BB113_405;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB113_405) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB112_404 & memory_controller_waitrequest == 1'd0 & main_WriteBlock_exit_i_i_exitcond116_i_i == 1'd0)
begin
cur_state <= LEGUP_F_main_BB105_389;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_389) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB113_405 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB113_405;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB113_405) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB113_405 & memory_controller_waitrequest == 1'd0 & main_447_448 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB93_357;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_357) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB113_405 & memory_controller_waitrequest == 1'd0 & main_447_448 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_454;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_454) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB114_406 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB114_406;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB114_406) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB114_406 & memory_controller_waitrequest == 1'd0 & main_449_451 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB115_407;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB115_407) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB114_406 & memory_controller_waitrequest == 1'd0 & main_449_451 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_454;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_454) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB115_407 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB115_407;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB115_407) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB115_407 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_408;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_408) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_408 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_408;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_408) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_408 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_409;
if (^reset !== 1'bX && ^(LEGUP_function_call_409) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_409 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_409;
if (^reset !== 1'bX && ^(LEGUP_function_call_409) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_409 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_410;
if (^reset !== 1'bX && ^(LEGUP_function_call_410) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_409 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_409;
if (^reset !== 1'bX && ^(LEGUP_function_call_409) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_410 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_410;
if (^reset !== 1'bX && ^(LEGUP_function_call_410) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_410 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_411;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_411) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_411 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_411;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_411) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_411 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_412;
if (^reset !== 1'bX && ^(LEGUP_function_call_412) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_412 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_412;
if (^reset !== 1'bX && ^(LEGUP_function_call_412) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_412 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_413;
if (^reset !== 1'bX && ^(LEGUP_function_call_413) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_412 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_412;
if (^reset !== 1'bX && ^(LEGUP_function_call_412) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_413 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_413;
if (^reset !== 1'bX && ^(LEGUP_function_call_413) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_413 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_414;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_414) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_414 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_414;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_414) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_414 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_415;
if (^reset !== 1'bX && ^(LEGUP_function_call_415) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_415 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_415;
if (^reset !== 1'bX && ^(LEGUP_function_call_415) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_415 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_416;
if (^reset !== 1'bX && ^(LEGUP_function_call_416) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_415 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_415;
if (^reset !== 1'bX && ^(LEGUP_function_call_415) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_416 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_416;
if (^reset !== 1'bX && ^(LEGUP_function_call_416) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_416 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_417;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_417) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_417 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_417;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_417) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_417 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_418;
if (^reset !== 1'bX && ^(LEGUP_function_call_418) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_418 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_418;
if (^reset !== 1'bX && ^(LEGUP_function_call_418) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_418 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_419;
if (^reset !== 1'bX && ^(LEGUP_function_call_419) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_418 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_418;
if (^reset !== 1'bX && ^(LEGUP_function_call_418) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_419 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_419;
if (^reset !== 1'bX && ^(LEGUP_function_call_419) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_419 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_420;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_420) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_420 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_420;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_420) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_420 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_421;
if (^reset !== 1'bX && ^(LEGUP_function_call_421) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_421 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_421;
if (^reset !== 1'bX && ^(LEGUP_function_call_421) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_421 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_422;
if (^reset !== 1'bX && ^(LEGUP_function_call_422) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_421 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_421;
if (^reset !== 1'bX && ^(LEGUP_function_call_421) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_422 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_422;
if (^reset !== 1'bX && ^(LEGUP_function_call_422) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_422 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_423;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_423) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_423 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_423;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_423) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_423 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_424;
if (^reset !== 1'bX && ^(LEGUP_function_call_424) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_424 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_424;
if (^reset !== 1'bX && ^(LEGUP_function_call_424) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_424 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_425;
if (^reset !== 1'bX && ^(LEGUP_function_call_425) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_424 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_424;
if (^reset !== 1'bX && ^(LEGUP_function_call_424) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_425 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_425;
if (^reset !== 1'bX && ^(LEGUP_function_call_425) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_425 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB117_426;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB117_426) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB117_426 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB117_426;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB117_426) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB117_426 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_427;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_427) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_427 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_427;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_427) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_427 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_428;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_428) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_428 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_428;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_428) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_428 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_429;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_429) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_429 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_429;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_429) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_429 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_430;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_430) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_430 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_430;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_430) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_430 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_431;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_431) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_431 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_431;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_431) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_431 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_432;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_432) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_432 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_432;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_432) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_432 & memory_controller_waitrequest == 1'd0 & main_454_473 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB121_435;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB121_435) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_432 & memory_controller_waitrequest == 1'd0 & main_454_473 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB119_433;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB119_433) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB119_433 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB119_433;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB119_433) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB119_433 & memory_controller_waitrequest == 1'd0 & main_474_475 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB120_434;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB120_434) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB119_433 & memory_controller_waitrequest == 1'd0 & main_474_475 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB121_435;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB121_435) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB120_434 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB120_434;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB120_434) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB120_434 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB121_435;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB121_435) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB121_435 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB121_435;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB121_435) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB121_435 & memory_controller_waitrequest == 1'd0 & main_477_478 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB124_438;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB124_438) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB121_435 & memory_controller_waitrequest == 1'd0 & main_477_478 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB122_436;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB122_436) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB122_436 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB122_436;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB122_436) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB122_436 & memory_controller_waitrequest == 1'd0 & main_479_480 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB123_437;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB123_437) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB122_436 & memory_controller_waitrequest == 1'd0 & main_479_480 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB124_438;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB124_438) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB123_437 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB123_437;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB123_437) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB123_437 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB124_438;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB124_438) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB124_438 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB124_438;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB124_438) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB124_438 & memory_controller_waitrequest == 1'd0 & main_482_483 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB127_441;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_441) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB124_438 & memory_controller_waitrequest == 1'd0 & main_482_483 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB125_439;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB125_439) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB125_439 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB125_439;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB125_439) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB125_439 & memory_controller_waitrequest == 1'd0 & main_484_485 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB126_440;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB126_440) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB125_439 & memory_controller_waitrequest == 1'd0 & main_484_485 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB127_441;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_441) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB126_440 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB126_440;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB126_440) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB126_440 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB127_441;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_441) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_441 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB127_441;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_441) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_441 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB127_442;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_442) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_442 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB127_442;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_442) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_442 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB127_443;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_443) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_443 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB127_443;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_443) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_443 & memory_controller_waitrequest == 1'd0 & main_487_exitcond_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB128_444;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB128_444) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_443 & memory_controller_waitrequest == 1'd0 & main_487_exitcond_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_427;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_427) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB128_444 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB128_444;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB128_444) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB128_444 & memory_controller_waitrequest == 1'd0 & main_YuvToRgb_exit13_i_i_exitcond35_i_i == 1'd1)
begin
cur_state <= LEGUP_F_main_BB129_445;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_445) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB128_444 & memory_controller_waitrequest == 1'd0 & main_YuvToRgb_exit13_i_i_exitcond35_i_i == 1'd0)
begin
cur_state <= LEGUP_F_main_BB117_426;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB117_426) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_445 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB129_445;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_445) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_445 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_446;
if (^reset !== 1'bX && ^(LEGUP_function_call_446) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_446 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_446;
if (^reset !== 1'bX && ^(LEGUP_function_call_446) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_446 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_447;
if (^reset !== 1'bX && ^(LEGUP_function_call_447) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_446 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_446;
if (^reset !== 1'bX && ^(LEGUP_function_call_446) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_447 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_447;
if (^reset !== 1'bX && ^(LEGUP_function_call_447) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_447 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB129_448;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_448) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_448 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB129_448;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_448) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_448 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_449;
if (^reset !== 1'bX && ^(LEGUP_function_call_449) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_449 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_449;
if (^reset !== 1'bX && ^(LEGUP_function_call_449) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_449 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_450;
if (^reset !== 1'bX && ^(LEGUP_function_call_450) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_449 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_449;
if (^reset !== 1'bX && ^(LEGUP_function_call_449) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_450 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_450;
if (^reset !== 1'bX && ^(LEGUP_function_call_450) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_450 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB129_451;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_451) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_451 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB129_451;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_451) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_451 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_452;
if (^reset !== 1'bX && ^(LEGUP_function_call_452) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_452 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_452;
if (^reset !== 1'bX && ^(LEGUP_function_call_452) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_452 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_453;
if (^reset !== 1'bX && ^(LEGUP_function_call_453) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_452 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_452;
if (^reset !== 1'bX && ^(LEGUP_function_call_452) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_453 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_453;
if (^reset !== 1'bX && ^(LEGUP_function_call_453) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_453 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_490_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_408;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_408) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_453 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_490_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_454;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_454) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_454 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB130_454;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_454) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_454 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_455;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_455) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_455 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB130_455;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_455) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_455 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_456;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_456) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_456 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB130_456;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_456) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_456 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB131_457;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_457) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_457 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB131_457;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_457) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_457 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB131_458;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_458) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_458 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB131_458;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_458) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_458 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB131_459;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_459) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_459 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB131_459;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_459) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_459 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB131_460;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_460) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB131_460;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_460) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB132_461;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_461) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB131_457;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_457) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_461 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB132_461;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_461) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_461 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB132_462;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_462) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_462 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB132_462;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_462) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_462 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB132_463;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_463) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_463 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB132_463;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_463) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_463 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB132_464;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_464) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB132_464;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_464) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB134_469;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_469) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB132_461;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_461) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_465 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB133_465;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_465) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_465 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB133_466;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_466) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_466 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB133_466;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_466) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_466 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB133_467;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_467) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_467 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB133_467;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_467) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_467 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB133_468;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_468) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_468 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB133_468;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_468) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_468 & memory_controller_waitrequest == 1'd0 & main_jpeg2bmp_main_exit_512 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB135_473;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB135_473) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_468 & memory_controller_waitrequest == 1'd0 & main_jpeg2bmp_main_exit_512 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB136_474;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB136_474) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_469 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB134_469;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_469) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_469 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB134_470;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_470) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_470 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB134_470;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_470) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_470 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB134_471;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_471) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_471 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB134_471;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_471) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_471 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB134_472;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_472) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_472 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB134_472;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_472) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_472 & memory_controller_waitrequest == 1'd0 & main__preheader_2_i_exitcond_2_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB133_465;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_465) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_472 & memory_controller_waitrequest == 1'd0 & main__preheader_2_i_exitcond_2_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB134_469;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_469) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB135_473 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB135_473;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB135_473) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB135_473 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB137_475;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_475) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB136_474 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB136_474;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB136_474) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB136_474 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB137_475;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_475) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_475 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB137_475;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_475) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_475 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB137_476;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_476) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_476 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB137_476;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_476) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_476 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB137_477;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_477) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_477 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB137_477;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_477) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_477 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* main: %1*/
/* %i.05.i = phi i32 [ 0, %0 ], [ %3, %1 ]*/
begin
main_1_i_05_i = main_1_i_05_i_phi_temp;
end
end
always @(*) begin
/* main: %1*/
/* %c.06.i = getelementptr [5310 x i8]* @JpegFileBuf, i32 0, i32 %i.05.i*/
begin
main_1_c_06_i = `TAG_g_JpegFileBuf_a + 1 * main_1_i_05_i;
end
end
always @(posedge clk) begin
/* main: %1*/
/* %c.06.i = getelementptr [5310 x i8]* @JpegFileBuf, i32 0, i32 %i.05.i*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
main_1_c_06_i_reg <= main_1_c_06_i;
if (^reset !== 1'bX && ^(main_1_c_06_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_c_06_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %1*/
/* %scevgep13.i = getelementptr [5207 x i8]* @hana_jpg, i32 0, i32 %i.05.i*/
begin
main_1_scevgep13_i = `TAG_g_hana_jpg_a + 1 * main_1_i_05_i;
end
end
always @(*) begin
/* main: %1*/
/* %2 = load i8* %scevgep13.i, align 1, !tbaa !1*/
begin
main_1_2 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %1*/
/* %3 = add nsw i32 %i.05.i, 1*/
begin
main_1_3 = main_1_i_05_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %1*/
/* %3 = add nsw i32 %i.05.i, 1*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
main_1_3_reg <= main_1_3;
if (^reset !== 1'bX && ^(main_1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_3_reg"); $finish; end
end
end
always @(*) begin
/* main: %1*/
/* %exitcond11.i = icmp eq i32 %3, 5207*/
begin
main_1_exitcond11_i = main_1_3 == 32'd5207;
end
end
always @(posedge clk) begin
/* main: %1*/
/* %exitcond11.i = icmp eq i32 %3, 5207*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
main_1_exitcond11_i_reg <= main_1_exitcond11_i;
if (^reset !== 1'bX && ^(main_1_exitcond11_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_exitcond11_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %i_marker.0 = phi i32 [ 0, %1 ], [ %24, %31 ]*/
begin
main__outer_i_i_i_marker_0 = main__outer_i_i_i_marker_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %i_get_dht.0 = phi i32 [ 0, %1 ], [ %i_get_dht.1.ph, %31 ]*/
begin
main__outer_i_i_i_get_dht_0 = main__outer_i_i_i_get_dht_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %i_get_dqt.0 = phi i32 [ 0, %1 ], [ %i_get_dqt.1.ph6, %31 ]*/
begin
main__outer_i_i_i_get_dqt_0 = main__outer_i_i_i_get_dqt_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %ReadBuf.0 = phi i8* [ getelementptr inbounds ([5310 x i8]* @JpegFileBuf, i32 0, i32 0), %1 ], [ %ReadBuf.2, %31 ]*/
begin
main__outer_i_i_ReadBuf_0 = main__outer_i_i_ReadBuf_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %p_jinfo_num_components.0 = phi i8 [ 0, %1 ], [ %p_jinfo_num_components.1.ph13, %31 ]*/
begin
main__outer_i_i_p_jinfo_num_components_0 = main__outer_i_i_p_jinfo_num_components_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %p_jinfo_smp_fact.b.0 = phi i1 [ false, %1 ], [ %p_jinfo_smp_fact.b.1.ph14, %31 ]*/
begin
main__outer_i_i_p_jinfo_smp_fact_b_0 = main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i = main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp;
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
else if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i = main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp;
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
else /* if (cur_state == LEGUP_F_main_BB2_5) */
begin
main__outer_i_i_sow_SOI_0_ph_i_i = main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_reg <= main__outer_i_i_sow_SOI_0_ph_i_i;
if (^reset !== 1'bX && ^(main__outer_i_i_sow_SOI_0_ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_reg"); $finish; end
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_reg <= main__outer_i_i_sow_SOI_0_ph_i_i;
if (^reset !== 1'bX && ^(main__outer_i_i_sow_SOI_0_ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_reg"); $finish; end
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_reg <= main__outer_i_i_sow_SOI_0_ph_i_i;
if (^reset !== 1'bX && ^(main__outer_i_i_sow_SOI_0_ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_reg"); $finish; end
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_reg <= main__outer_i_i_sow_SOI_0_ph_i_i;
if (^reset !== 1'bX && ^(main__outer_i_i_sow_SOI_0_ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %i_marker.1.ph = phi i32 [ %i_marker.0, %.outer.i.i ], [ %24, %._crit_edge.i12.i.i ]*/
begin
main__backedge_i_i_outer_i_marker_1_ph = main__backedge_i_i_outer_i_marker_1_ph_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph = main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp;
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
else if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph = main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp;
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB3_6) */
begin
main__backedge_i_i_outer_i_get_dht_1_ph = main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_reg <= main__backedge_i_i_outer_i_get_dht_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_reg"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_reg <= main__backedge_i_i_outer_i_get_dht_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_reg"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_reg <= main__backedge_i_i_outer_i_get_dht_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_reg"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_reg <= main__backedge_i_i_outer_i_get_dht_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %i_get_dqt.1.ph = phi i32 [ %i_get_dqt.0, %.outer.i.i ], [ %i_get_dqt.1.ph6, %._crit_edge.i12.i.i ]*/
begin
main__backedge_i_i_outer_i_get_dqt_1_ph = main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %ReadBuf.1.ph = phi i8* [ %ReadBuf.0, %.outer.i.i ], [ %ReadBuf.7, %._crit_edge.i12.i.i ]*/
begin
main__backedge_i_i_outer_ReadBuf_1_ph = main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_num_components.1.ph = phi i8 [ %p_jinfo_num_components.0, %.outer.i.i ], [ %p_jinfo_num_components.1.ph13, %._crit_edge.i12.i.i ]*/
begin
main__backedge_i_i_outer_p_jinfo_num_components_1_ph = main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_smp_fact.b.1.ph = phi i1 [ %p_jinfo_smp_fact.b.0, %.outer.i.i ], [ %p_jinfo_smp_fact.b.1.ph14, %._crit_edge.i12.i.i ]*/
begin
main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph = main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %4 = getelementptr inbounds [4 x i32]* @out_length_get_dht, i32 0, i32 %i_get_dht.1.ph*/
begin
main__backedge_i_i_outer_4 = `TAG_g_out_length_get_dht_a + 4 * main__backedge_i_i_outer_i_get_dht_1_ph;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %4 = getelementptr inbounds [4 x i32]* @out_length_get_dht, i32 0, i32 %i_get_dht.1.ph*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_4_reg <= main__backedge_i_i_outer_4;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_4_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %i_marker.1.ph5 = phi i32 [ %i_marker.1.ph, %.backedge.i.i.outer ], [ %24, %.us-lcssa.us.i.i.i ]*/
begin
main__backedge_i_i_outer4_i_marker_1_ph5 = main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6 = main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp;
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
else if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6 = main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp;
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
else if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6 = main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp;
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB4_7) */
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6 = main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg <= main__backedge_i_i_outer4_i_get_dqt_1_ph6;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg <= main__backedge_i_i_outer4_i_get_dqt_1_ph6;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg <= main__backedge_i_i_outer4_i_get_dqt_1_ph6;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg <= main__backedge_i_i_outer4_i_get_dqt_1_ph6;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg <= main__backedge_i_i_outer4_i_get_dqt_1_ph6;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %ReadBuf.1.ph7 = phi i8* [ %ReadBuf.1.ph, %.backedge.i.i.outer ], [ %ReadBuf.8, %.us-lcssa.us.i.i.i ]*/
begin
main__backedge_i_i_outer4_ReadBuf_1_ph7 = main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_num_components.1.ph8 = phi i8 [ %p_jinfo_num_components.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_num_components.1.ph13, %.us-lcssa.us.i.i.i ]*/
begin
main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8 = main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_smp_fact.b.1.ph9 = phi i1 [ %p_jinfo_smp_fact.b.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_smp_fact.b.1.ph14, %.us-lcssa.us.i.i.i ]*/
begin
main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9 = main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %5 = getelementptr inbounds [2 x i32]* @out_length_get_dqt, i32 0, i32 %i_get_dqt.1.ph6*/
begin
main__backedge_i_i_outer4_5 = `TAG_g_out_length_get_dqt_a + 4 * main__backedge_i_i_outer4_i_get_dqt_1_ph6;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %5 = getelementptr inbounds [2 x i32]* @out_length_get_dqt, i32 0, i32 %i_get_dqt.1.ph6*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_5_reg <= main__backedge_i_i_outer4_5;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_5_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer10*/
/* %i_marker.1.ph11 = phi i32 [ %i_marker.1.ph5, %.backedge.i.i.outer4 ], [ %24, %163 ], [ %24, %165 ]*/
begin
main__backedge_i_i_outer10_i_marker_1_ph11 = main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer10*/
/* %ReadBuf.1.ph12 = phi i8* [ %ReadBuf.1.ph7, %.backedge.i.i.outer4 ], [ %ReadBuf.4, %163 ], [ %ReadBuf.4, %165 ]*/
begin
main__backedge_i_i_outer10_ReadBuf_1_ph12 = main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13 = main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13 = main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13 = main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13 = main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
else /* if (cur_state == LEGUP_F_main_BB5_8) */
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13 = main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
else /* if (cur_state == LEGUP_F_main_BB5_8) */
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1 = main__backedge_i_i_i_marker_1_phi_temp;
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1 = main__backedge_i_i_i_marker_1_phi_temp;
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB6_9) */
begin
main__backedge_i_i_i_marker_1 = main__backedge_i_i_i_marker_1_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1_reg <= main__backedge_i_i_i_marker_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_i_marker_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1_reg <= main__backedge_i_i_i_marker_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_i_marker_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1_reg <= main__backedge_i_i_i_marker_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_i_marker_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1_reg <= main__backedge_i_i_i_marker_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_i_marker_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1 = main__backedge_i_i_ReadBuf_1_phi_temp;
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1 = main__backedge_i_i_ReadBuf_1_phi_temp;
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1 = main__backedge_i_i_ReadBuf_1_phi_temp;
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB6_9) */
begin
main__backedge_i_i_ReadBuf_1 = main__backedge_i_i_ReadBuf_1_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1_reg <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1_reg <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1_reg <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1_reg <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1_reg <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_reg"); $finish; end
end
end
always @(*) begin
/* main: %6*/
/* %7 = getelementptr inbounds i8* %ReadBuf.1, i32 1*/
begin
main_6_7 = main__backedge_i_i_ReadBuf_1_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %6*/
/* %7 = getelementptr inbounds i8* %ReadBuf.1, i32 1*/
if (cur_state == LEGUP_F_main_BB7_10)
begin
main_6_7_reg <= main_6_7;
if (^reset !== 1'bX && ^(main_6_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_7_reg"); $finish; end
end
end
always @(*) begin
/* main: %6*/
/* %8 = load i8* %ReadBuf.1, align 1, !tbaa !1*/
begin
main_6_8 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
begin
main_6_9 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_13)
begin
main_6_9_reg <= main_6_9;
if (^reset !== 1'bX && ^(main_6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_9_reg"); $finish; end
end
end
always @(*) begin
/* main: %6*/
/* %10 = icmp eq i8 %8, -1*/
begin
main_6_10 = main_6_8 == -8'd1;
end
end
always @(posedge clk) begin
/* main: %6*/
/* %10 = icmp eq i8 %8, -1*/
if (cur_state == LEGUP_F_main_BB7_12)
begin
main_6_10_reg <= main_6_10;
if (^reset !== 1'bX && ^(main_6_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_10_reg"); $finish; end
end
end
always @(*) begin
/* main: %6*/
/* %11 = icmp eq i8 %9, -40*/
begin
main_6_11 = main_6_9 == -8'd40;
end
end
always @(*) begin
/* main: %6*/
/* %or.cond.i.i.i = and i1 %10, %11*/
begin
main_6_or_cond_i_i_i = main_6_10_reg & main_6_11;
end
end
always @(*) begin
/* main: %first_marker.exit.i.i*/
/* %14 = getelementptr inbounds i8* %ReadBuf.1, i32 2*/
begin
main_first_marker_exit_i_i_14 = main__backedge_i_i_ReadBuf_1_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %first_marker.exit.i.i*/
/* %14 = getelementptr inbounds i8* %ReadBuf.1, i32 2*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
main_first_marker_exit_i_i_14_reg <= main_first_marker_exit_i_i_14;
if (^reset !== 1'bX && ^(main_first_marker_exit_i_i_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_first_marker_exit_i_i_14_reg"); $finish; end
end
end
always @(*) begin
/* main: %first_marker.exit.i.i*/
/* %15 = zext i8 %9 to i32*/
begin
main_first_marker_exit_i_i_15 = main_6_9_reg;
end
end
always @(posedge clk) begin
/* main: %first_marker.exit.i.i*/
/* %15 = zext i8 %9 to i32*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
main_first_marker_exit_i_i_15_reg <= main_first_marker_exit_i_i_15;
if (^reset !== 1'bX && ^(main_first_marker_exit_i_i_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_first_marker_exit_i_i_15_reg"); $finish; end
end
end
always @(*) begin
/* main: %first_marker.exit.i.i*/
/* %16 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_first_marker_exit_i_i_16 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %first_marker.exit.i.i*/
/* %17 = add nsw i32 %16, 1*/
begin
main_first_marker_exit_i_i_17 = main_first_marker_exit_i_i_16 + 32'd1;
end
end
always @(*) begin
/* main: %.loopexit3.i.i.i.loopexit*/
/* %scevgep13.i.i.le = getelementptr i8* %.ph.i.i, i32 %tmp12.i.i*/
begin
main__loopexit3_i_i_i_loopexit_scevgep13_i_i_le = main__loopexit_i_preheader_i_i__ph_i_i_reg + 1 * main__loopexit_i_i_i_tmp12_i_i_reg;
end
end
always @(*) begin
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18 = main__loopexit3_i_i_i_18_phi_temp;
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
else if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18 = main__loopexit3_i_i_i_18_phi_temp;
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB11_19) */
begin
main__loopexit3_i_i_i_18 = main__loopexit3_i_i_i_18_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18_reg <= main__loopexit3_i_i_i_18;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_reg"); $finish; end
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18_reg <= main__loopexit3_i_i_i_18;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_reg"); $finish; end
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18_reg <= main__loopexit3_i_i_i_18;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_reg"); $finish; end
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18_reg <= main__loopexit3_i_i_i_18;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_reg"); $finish; end
end
end
always @(*) begin
/* main: %.loopexit3.i.i.i*/
/* %storemerge1.i.i.i = getelementptr inbounds i8* %18, i32 1*/
begin
main__loopexit3_i_i_i_storemerge1_i_i_i = main__loopexit3_i_i_i_18 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.loopexit3.i.i.i*/
/* %storemerge1.i.i.i = getelementptr inbounds i8* %18, i32 1*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_storemerge1_i_i_i_reg <= main__loopexit3_i_i_i_storemerge1_i_i_i;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_storemerge1_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_storemerge1_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.loopexit3.i.i.i*/
/* %c.0.in2.i.i.i = load i8* %18, align 1*/
begin
main__loopexit3_i_i_i_c_0_in2_i_i_i = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.loopexit3.i.i.i*/
/* %19 = icmp eq i8 %c.0.in2.i.i.i, -1*/
begin
main__loopexit3_i_i_i_19 = main__loopexit3_i_i_i_c_0_in2_i_i_i == -8'd1;
end
end
always @(*) begin
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
main__lr_ph_i_i_i_indvar_i_i = main__lr_ph_i_i_i_indvar_i_i_phi_temp;
end
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB12_22) */
begin
main__lr_ph_i_i_i_indvar_i_i = main__lr_ph_i_i_i_indvar_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
main__lr_ph_i_i_i_indvar_i_i_reg <= main__lr_ph_i_i_i_indvar_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i_i_i_indvar_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_indvar_i_i_reg"); $finish; end
end
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
main__lr_ph_i_i_i_indvar_i_i_reg <= main__lr_ph_i_i_i_indvar_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i_i_i_indvar_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_indvar_i_i_reg"); $finish; end
end
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
main__lr_ph_i_i_i_indvar_i_i_reg <= main__lr_ph_i_i_i_indvar_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i_i_i_indvar_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_indvar_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i.i.i*/
/* %tmp.i.i = add i32 %indvar.i.i, 1*/
begin
main__lr_ph_i_i_i_tmp_i_i = main__lr_ph_i_i_i_indvar_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i.i.i*/
/* %tmp.i.i = add i32 %indvar.i.i, 1*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
main__lr_ph_i_i_i_tmp_i_i_reg <= main__lr_ph_i_i_i_tmp_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i_i_i_tmp_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_tmp_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i.i.i*/
/* %scevgep.i.i = getelementptr i8* %18, i32 %tmp.i.i*/
begin
main__lr_ph_i_i_i_scevgep_i_i = main__loopexit3_i_i_i_18_reg + 1 * main__lr_ph_i_i_i_tmp_i_i;
end
end
always @(*) begin
/* main: %.lr.ph.i.i.i*/
/* %c.0.in.i.i.i = load i8* %scevgep.i.i, align 1*/
begin
main__lr_ph_i_i_i_c_0_in_i_i_i = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i.i.i*/
/* %20 = icmp eq i8 %c.0.in.i.i.i, -1*/
begin
main__lr_ph_i_i_i_20 = main__lr_ph_i_i_i_c_0_in_i_i_i == -8'd1;
end
end
always @(*) begin
/* main: %.loopexit.i.preheader.i.i.loopexit*/
/* %tmp4.i.i = add i32 %indvar.i.i, 2*/
begin
main__loopexit_i_preheader_i_i_loopexit_tmp4_i_i = main__lr_ph_i_i_i_indvar_i_i_reg + 32'd2;
end
end
always @(*) begin
/* main: %.loopexit.i.preheader.i.i.loopexit*/
/* %storemerge.i.i.i = getelementptr i8* %18, i32 %tmp4.i.i*/
begin
main__loopexit_i_preheader_i_i_loopexit_storemerge_i_i_i = main__loopexit3_i_i_i_18_reg + 1 * main__loopexit_i_preheader_i_i_loopexit_tmp4_i_i;
end
end
always @(*) begin
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i = main__loopexit_i_preheader_i_i__ph_i_i_phi_temp;
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i = main__loopexit_i_preheader_i_i__ph_i_i_phi_temp;
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i = main__loopexit_i_preheader_i_i__ph_i_i_phi_temp;
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
else /* if (cur_state == LEGUP_F_main_BB14_26) */
begin
main__loopexit_i_preheader_i_i__ph_i_i = main__loopexit_i_preheader_i_i__ph_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i_reg <= main__loopexit_i_preheader_i_i__ph_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i__ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_reg"); $finish; end
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i_reg <= main__loopexit_i_preheader_i_i__ph_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i__ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_reg"); $finish; end
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i_reg <= main__loopexit_i_preheader_i_i__ph_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i__ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_reg"); $finish; end
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i_reg <= main__loopexit_i_preheader_i_i__ph_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i__ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_reg"); $finish; end
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i_reg <= main__loopexit_i_preheader_i_i__ph_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i__ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.loopexit.i.i.i*/
/* %indvar9.i.i = phi i32 [ 0, %.loopexit.i.preheader.i.i ], [ %tmp12.i.i, %.loopexit.i.i.i ]*/
begin
main__loopexit_i_i_i_indvar9_i_i = main__loopexit_i_i_i_indvar9_i_i_phi_temp;
end
end
always @(*) begin
/* main: %.loopexit.i.i.i*/
/* %scevgep11.i.i = getelementptr i8* %.ph.i.i, i32 %indvar9.i.i*/
begin
main__loopexit_i_i_i_scevgep11_i_i = main__loopexit_i_preheader_i_i__ph_i_i_reg + 1 * main__loopexit_i_i_i_indvar9_i_i;
end
end
always @(*) begin
/* main: %.loopexit.i.i.i*/
/* %tmp12.i.i = add i32 %indvar9.i.i, 1*/
begin
main__loopexit_i_i_i_tmp12_i_i = main__loopexit_i_i_i_indvar9_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i.i*/
/* %tmp12.i.i = add i32 %indvar9.i.i, 1*/
if (cur_state == LEGUP_F_main_BB15_27)
begin
main__loopexit_i_i_i_tmp12_i_i_reg <= main__loopexit_i_i_i_tmp12_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_i_i_tmp12_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_i_tmp12_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.loopexit.i.i.i*/
/* %21 = load i8* %scevgep11.i.i, align 1, !tbaa !1*/
begin
main__loopexit_i_i_i_21 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.loopexit.i.i.i*/
/* %22 = zext i8 %21 to i32*/
begin
main__loopexit_i_i_i_22 = main__loopexit_i_i_i_21;
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i.i*/
/* %22 = zext i8 %21 to i32*/
if (cur_state == LEGUP_F_main_BB15_29)
begin
main__loopexit_i_i_i_22_reg <= main__loopexit_i_i_i_22;
if (^reset !== 1'bX && ^(main__loopexit_i_i_i_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_i_22_reg"); $finish; end
end
end
always @(*) begin
/* main: %next_marker.exit.i.i.loopexit*/
/* %scevgep13.i.i = getelementptr i8* %.ph.i.i, i32 %tmp12.i.i*/
begin
main_next_marker_exit_i_i_loopexit_scevgep13_i_i = main__loopexit_i_preheader_i_i__ph_i_i_reg + 1 * main__loopexit_i_i_i_tmp12_i_i_reg;
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else /* if (cur_state == LEGUP_F_main_BB17_31) */
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else /* if (cur_state == LEGUP_F_main_BB17_31) */
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %24 = add nsw i32 %i_marker.1, 1*/
begin
main_next_marker_exit_i_i_24 = main__backedge_i_i_i_marker_1_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %24 = add nsw i32 %i_marker.1, 1*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_24_reg <= main_next_marker_exit_i_i_24;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_24_reg"); $finish; end
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %25 = getelementptr inbounds [10 x i32]* @out_unread_marker, i32 0, i32 %i_marker.1*/
begin
main_next_marker_exit_i_i_25 = `TAG_g_out_unread_marker_a + 4 * main__backedge_i_i_i_marker_1_reg;
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %25 = getelementptr inbounds [10 x i32]* @out_unread_marker, i32 0, i32 %i_marker.1*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_25_reg <= main_next_marker_exit_i_i_25;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_25_reg"); $finish; end
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
begin
main_next_marker_exit_i_i_26 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %27 = icmp eq i32 %unread_marker.0.i.i, %26*/
begin
main_next_marker_exit_i_i_27 = main_next_marker_exit_i_i_unread_marker_0_i_i_reg == main_next_marker_exit_i_i_26;
end
end
always @(*) begin
/* main: %28*/
/* %29 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_28_29 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %28*/
/* %30 = add nsw i32 %29, 1*/
begin
main_28_30 = main_28_29 + 32'd1;
end
end
always @(*) begin
/* main: %32*/
/* %33 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
begin
main_32_33 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %33 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_33_reg <= main_32_33;
if (^reset !== 1'bX && ^(main_32_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_33_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %34 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
begin
main_32_34 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %35 = zext i8 %34 to i16*/
begin
main_32_35 = main_32_34;
end
end
always @(*) begin
/* main: %32*/
/* %36 = shl nuw i16 %35, 8*/
begin
main_32_36 = main_32_35 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %36 = shl nuw i16 %35, 8*/
if (cur_state == LEGUP_F_main_BB20_41)
begin
main_32_36_reg <= main_32_36;
if (^reset !== 1'bX && ^(main_32_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_36_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %37 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
begin
main_32_37 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %37 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_37_reg <= main_32_37;
if (^reset !== 1'bX && ^(main_32_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_37_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
begin
main_32_38 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %39 = zext i8 %38 to i16*/
begin
main_32_39 = main_32_38;
end
end
always @(*) begin
/* main: %32*/
/* %40 = or i16 %36, %39*/
begin
main_32_40 = main_32_36_reg | main_32_39;
end
end
always @(*) begin
/* main: %32*/
/* %41 = sext i16 %40 to i32*/
begin
main_32_41 = $signed(main_32_40);
end
end
always @(posedge clk) begin
/* main: %32*/
/* %41 = sext i16 %40 to i32*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
main_32_41_reg <= main_32_41;
if (^reset !== 1'bX && ^(main_32_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_41_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %42 = getelementptr inbounds i8* %ReadBuf.2, i32 3*/
begin
main_32_42 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd3;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %42 = getelementptr inbounds i8* %ReadBuf.2, i32 3*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_42_reg <= main_32_42;
if (^reset !== 1'bX && ^(main_32_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_42_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
begin
main_32_43 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
main_32_43_reg <= main_32_43;
if (^reset !== 1'bX && ^(main_32_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_43_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %44 = getelementptr inbounds i8* %ReadBuf.2, i32 4*/
begin
main_32_44 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd4;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %44 = getelementptr inbounds i8* %ReadBuf.2, i32 4*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_44_reg <= main_32_44;
if (^reset !== 1'bX && ^(main_32_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_44_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %45 = load i8* %42, align 1, !tbaa !1*/
begin
main_32_45 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %46 = zext i8 %45 to i16*/
begin
main_32_46 = main_32_45;
end
end
always @(*) begin
/* main: %32*/
/* %47 = shl nuw i16 %46, 8*/
begin
main_32_47 = main_32_46 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %47 = shl nuw i16 %46, 8*/
if (cur_state == LEGUP_F_main_BB20_44)
begin
main_32_47_reg <= main_32_47;
if (^reset !== 1'bX && ^(main_32_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_47_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %48 = getelementptr inbounds i8* %ReadBuf.2, i32 5*/
begin
main_32_48 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd5;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %48 = getelementptr inbounds i8* %ReadBuf.2, i32 5*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_48_reg <= main_32_48;
if (^reset !== 1'bX && ^(main_32_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_48_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %49 = load i8* %44, align 1, !tbaa !1*/
begin
main_32_49 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %50 = zext i8 %49 to i16*/
begin
main_32_50 = main_32_49;
end
end
always @(*) begin
/* main: %32*/
/* %51 = or i16 %47, %50*/
begin
main_32_51 = main_32_47_reg | main_32_50;
end
end
always @(*) begin
/* main: %32*/
/* %52 = getelementptr inbounds i8* %ReadBuf.2, i32 6*/
begin
main_32_52 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd6;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %52 = getelementptr inbounds i8* %ReadBuf.2, i32 6*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_52_reg <= main_32_52;
if (^reset !== 1'bX && ^(main_32_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_52_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %53 = load i8* %48, align 1, !tbaa !1*/
begin
main_32_53 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %54 = zext i8 %53 to i16*/
begin
main_32_54 = main_32_53;
end
end
always @(*) begin
/* main: %32*/
/* %55 = shl nuw i16 %54, 8*/
begin
main_32_55 = main_32_54 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %55 = shl nuw i16 %54, 8*/
if (cur_state == LEGUP_F_main_BB20_48)
begin
main_32_55_reg <= main_32_55;
if (^reset !== 1'bX && ^(main_32_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_55_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %56 = getelementptr inbounds i8* %ReadBuf.2, i32 7*/
begin
main_32_56 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd7;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %56 = getelementptr inbounds i8* %ReadBuf.2, i32 7*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_56_reg <= main_32_56;
if (^reset !== 1'bX && ^(main_32_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_56_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %57 = load i8* %52, align 1, !tbaa !1*/
begin
main_32_57 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %58 = zext i8 %57 to i16*/
begin
main_32_58 = main_32_57;
end
end
always @(*) begin
/* main: %32*/
/* %59 = or i16 %55, %58*/
begin
main_32_59 = main_32_55_reg | main_32_58;
end
end
always @(*) begin
/* main: %32*/
/* %60 = getelementptr inbounds i8* %ReadBuf.2, i32 8*/
begin
main_32_60 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd8;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %60 = getelementptr inbounds i8* %ReadBuf.2, i32 8*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_60_reg <= main_32_60;
if (^reset !== 1'bX && ^(main_32_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_60_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
begin
main_32_61 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
main_32_61_reg <= main_32_61;
if (^reset !== 1'bX && ^(main_32_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_61_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %63 = sext i8 %43 to i32*/
begin
main_32_63 = $signed(main_32_43);
end
end
always @(posedge clk) begin
/* main: %32*/
/* %63 = sext i8 %43 to i32*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
main_32_63_reg <= main_32_63;
if (^reset !== 1'bX && ^(main_32_63) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_63_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %65 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
begin
main_32_65 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %32*/
/* %66 = sext i16 %65 to i32*/
begin
main_32_66 = $signed(main_32_65);
end
end
always @(*) begin
/* main: %32*/
/* %68 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
begin
main_32_68 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %32*/
/* %69 = sext i16 %68 to i32*/
begin
main_32_69 = $signed(main_32_68);
end
end
always @(*) begin
/* main: %32*/
/* %71 = sext i8 %61 to i32*/
begin
main_32_71 = $signed(main_32_61);
end
end
always @(posedge clk) begin
/* main: %32*/
/* %71 = sext i8 %61 to i32*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
main_32_71_reg <= main_32_71;
if (^reset !== 1'bX && ^(main_32_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_71_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %73 = icmp eq i16 %40, 17*/
begin
main_32_73 = main_32_40 == 16'd17;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %73 = icmp eq i16 %40, 17*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
main_32_73_reg <= main_32_73;
if (^reset !== 1'bX && ^(main_32_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_73_reg"); $finish; end
end
end
always @(*) begin
/* main: %74*/
/* %75 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_74_75 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %74*/
/* %76 = add nsw i32 %75, 1*/
begin
main_74_76 = main_74_75 + 32'd1;
end
end
always @(*) begin
/* main: %77*/
/* %78 = icmp eq i8 %43, 8*/
begin
main_77_78 = main_32_43_reg == 8'd8;
end
end
always @(*) begin
/* main: %79*/
/* %80 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_79_80 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %79*/
/* %81 = add nsw i32 %80, 1*/
begin
main_79_81 = main_79_80 + 32'd1;
end
end
always @(*) begin
/* main: %82*/
/* %83 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
begin
main_82_83 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %82*/
/* %84 = icmp eq i16 %83, 59*/
begin
main_82_84 = main_82_83 == 16'd59;
end
end
always @(*) begin
/* main: %85*/
/* %86 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_85_86 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %85*/
/* %87 = add nsw i32 %86, 1*/
begin
main_85_87 = main_85_86 + 32'd1;
end
end
always @(*) begin
/* main: %88*/
/* %89 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
begin
main_88_89 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %88*/
/* %90 = icmp eq i16 %89, 90*/
begin
main_88_90 = main_88_89 == 16'd90;
end
end
always @(*) begin
/* main: %91*/
/* %92 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_91_92 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %91*/
/* %93 = add nsw i32 %92, 1*/
begin
main_91_93 = main_91_92 + 32'd1;
end
end
always @(*) begin
/* main: %94*/
/* %95 = icmp eq i8 %61, 3*/
begin
main_94_95 = main_32_61_reg == 8'd3;
end
end
always @(*) begin
/* main: %.preheader.i.i.i.thread*/
/* %96 = load i32* @main_result, align 4, !tbaa !0*/
begin
main__preheader_i_i_i_thread_96 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %.preheader.i.i.i.thread*/
/* %97 = add nsw i32 %96, 1*/
begin
main__preheader_i_i_i_thread_97 = main__preheader_i_i_i_thread_96 + 32'd1;
end
end
always @(*) begin
/* main: %.preheader.i.i.i*/
/* %98 = icmp sgt i8 %61, 0*/
begin
main__preheader_i_i_i_98 = $signed(main_32_61_reg) > $signed(8'd0);
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_ReadBuf_3 = main__lr_ph_i1_i_i_ReadBuf_3_phi_temp;
end
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB31_82) */
begin
main__lr_ph_i1_i_i_ReadBuf_3 = main__lr_ph_i1_i_i_ReadBuf_3_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_ReadBuf_3_reg <= main__lr_ph_i1_i_i_ReadBuf_3;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_ReadBuf_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_reg"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_ReadBuf_3_reg <= main__lr_ph_i1_i_i_ReadBuf_3;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_ReadBuf_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_reg"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_ReadBuf_3_reg <= main__lr_ph_i1_i_i_ReadBuf_3;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_ReadBuf_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %ci.02.i.i.i = phi i32 [ %tmp12.i.i.i, %159 ], [ 0, %.preheader.i.i.i.thread ], [ 0, %.preheader.i.i.i ]*/
begin
main__lr_ph_i1_i_i_ci_02_i_i_i = main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_index, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep_i_i_i = `TAG_g_p_jinfo_comps_info_index_a + 1 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_index, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep3.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_id, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep3_i_i_i = `TAG_g_p_jinfo_comps_info_id_a + 1 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep3.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_id, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep3_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep3_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep3_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep3_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep4.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep4_i_i_i = `TAG_g_p_jinfo_comps_info_h_samp_factor_a + 1 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep4.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep4_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep4_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep4_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep4_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep5.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_v_samp_factor, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep5_i_i_i = `TAG_g_p_jinfo_comps_info_v_samp_factor_a + 1 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep5.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_v_samp_factor, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep5_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep5_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep5_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep5_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep6.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_quant_tbl_no, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep6_i_i_i = `TAG_g_p_jinfo_comps_info_quant_tbl_no_a + 1 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep6.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_quant_tbl_no, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep6_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep6_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep6_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep6_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %tmp.i.i.i = trunc i32 %ci.02.i.i.i to i8*/
begin
main__lr_ph_i1_i_i_tmp_i_i_i = main__lr_ph_i1_i_i_ci_02_i_i_i[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep7.i.i.i = getelementptr [3 x i32]* @out_index_get_sof, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep7_i_i_i = `TAG_g_out_index_get_sof_a + 4 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep7.i.i.i = getelementptr [3 x i32]* @out_index_get_sof, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep7_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep7_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep7_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep7_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep8.i.i.i = getelementptr [3 x i32]* @out_comp_id_get_sos, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep8_i_i_i = `TAG_g_out_comp_id_get_sos_a + 4 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep8.i.i.i = getelementptr [3 x i32]* @out_comp_id_get_sos, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep8_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep8_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep8_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep8_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep9.i.i.i = getelementptr [3 x i32]* @out_v_samp_factor_get_sof, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep9_i_i_i = `TAG_g_out_v_samp_factor_get_sof_a + 4 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep9.i.i.i = getelementptr [3 x i32]* @out_v_samp_factor_get_sof, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep9_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep9_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep9_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep9_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep11.i.i.i = getelementptr [3 x i32]* @out_ac_tbl_no_get_sos, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep11_i_i_i = `TAG_g_out_ac_tbl_no_get_sos_a + 4 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep11.i.i.i = getelementptr [3 x i32]* @out_ac_tbl_no_get_sos, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep11_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep11_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep11_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep11_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %tmp12.i.i.i = add i32 %ci.02.i.i.i, 1*/
begin
main__lr_ph_i1_i_i_tmp12_i_i_i = main__lr_ph_i1_i_i_ci_02_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %tmp12.i.i.i = add i32 %ci.02.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_tmp12_i_i_i_reg <= main__lr_ph_i1_i_i_tmp12_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_tmp12_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_tmp12_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %99 = getelementptr inbounds i8* %ReadBuf.3, i32 1*/
begin
main__lr_ph_i1_i_i_99 = main__lr_ph_i1_i_i_ReadBuf_3 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %99 = getelementptr inbounds i8* %ReadBuf.3, i32 1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_99_reg <= main__lr_ph_i1_i_i_99;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_99_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %100 = load i8* %ReadBuf.3, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_100 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %101 = getelementptr inbounds i8* %ReadBuf.3, i32 2*/
begin
main__lr_ph_i1_i_i_101 = main__lr_ph_i1_i_i_ReadBuf_3 + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %101 = getelementptr inbounds i8* %ReadBuf.3, i32 2*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_101_reg <= main__lr_ph_i1_i_i_101;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_101_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %102 = load i8* %99, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_102 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %103 = lshr i8 %102, 4*/
begin
main__lr_ph_i1_i_i_103 = main__lr_ph_i1_i_i_102 >>> 8'd4 % 8'd8;
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %104 = and i8 %102, 15*/
begin
main__lr_ph_i1_i_i_104 = main__lr_ph_i1_i_i_102 & 8'd15;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %104 = and i8 %102, 15*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
main__lr_ph_i1_i_i_104_reg <= main__lr_ph_i1_i_i_104;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_104_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %105 = getelementptr inbounds i8* %ReadBuf.3, i32 3*/
begin
main__lr_ph_i1_i_i_105 = main__lr_ph_i1_i_i_ReadBuf_3 + 1 * 32'd3;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %105 = getelementptr inbounds i8* %ReadBuf.3, i32 3*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_105_reg <= main__lr_ph_i1_i_i_105;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_105_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %106 = load i8* %101, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_106 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %107 = sext i8 %tmp.i.i.i to i32*/
begin
main__lr_ph_i1_i_i_107 = $signed(main__lr_ph_i1_i_i_tmp_i_i_i);
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %107 = sext i8 %tmp.i.i.i to i32*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_107_reg <= main__lr_ph_i1_i_i_107;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_107) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_107_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %109 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_109 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %110 = sext i8 %109 to i32*/
begin
main__lr_ph_i1_i_i_110 = $signed(main__lr_ph_i1_i_i_109);
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %112 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_112 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %113 = sext i8 %112 to i32*/
begin
main__lr_ph_i1_i_i_113 = $signed(main__lr_ph_i1_i_i_112);
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %115 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_115 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %116 = sext i8 %115 to i32*/
begin
main__lr_ph_i1_i_i_116 = $signed(main__lr_ph_i1_i_i_115);
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %118 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_118 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %119 = sext i8 %118 to i32*/
begin
main__lr_ph_i1_i_i_119 = $signed(main__lr_ph_i1_i_i_118);
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %121 = load i8* %scevgep.i.i.i, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_121 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %122 = sext i8 %121 to i32*/
begin
main__lr_ph_i1_i_i_122 = $signed(main__lr_ph_i1_i_i_121);
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %122 = sext i8 %121 to i32*/
if (cur_state == LEGUP_F_main_BB31_107)
begin
main__lr_ph_i1_i_i_122_reg <= main__lr_ph_i1_i_i_122;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_122_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %123 = load i32* %scevgep7.i.i.i, align 4, !tbaa !0*/
begin
main__lr_ph_i1_i_i_123 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %124 = icmp eq i32 %122, %123*/
begin
main__lr_ph_i1_i_i_124 = main__lr_ph_i1_i_i_122_reg == main__lr_ph_i1_i_i_123;
end
end
always @(*) begin
/* main: %125*/
/* %126 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_125_126 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %125*/
/* %127 = add nsw i32 %126, 1*/
begin
main_125_127 = main_125_126 + 32'd1;
end
end
always @(*) begin
/* main: %128*/
/* %129 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
begin
main_128_129 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %128*/
/* %130 = sext i8 %129 to i32*/
begin
main_128_130 = $signed(main_128_129);
end
end
always @(posedge clk) begin
/* main: %128*/
/* %130 = sext i8 %129 to i32*/
if (cur_state == LEGUP_F_main_BB33_114)
begin
main_128_130_reg <= main_128_130;
if (^reset !== 1'bX && ^(main_128_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_128_130_reg"); $finish; end
end
end
always @(*) begin
/* main: %128*/
/* %131 = load i32* %scevgep8.i.i.i, align 4, !tbaa !0*/
begin
main_128_131 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %128*/
/* %132 = icmp eq i32 %130, %131*/
begin
main_128_132 = main_128_130_reg == main_128_131;
end
end
always @(*) begin
/* main: %133*/
/* %134 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_133_134 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %133*/
/* %135 = add nsw i32 %134, 1*/
begin
main_133_135 = main_133_134 + 32'd1;
end
end
always @(*) begin
/* main: %136*/
/* %137 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
begin
main_136_137 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %136*/
/* %138 = sext i8 %137 to i32*/
begin
main_136_138 = $signed(main_136_137);
end
end
always @(posedge clk) begin
/* main: %136*/
/* %138 = sext i8 %137 to i32*/
if (cur_state == LEGUP_F_main_BB35_121)
begin
main_136_138_reg <= main_136_138;
if (^reset !== 1'bX && ^(main_136_138) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_136_138_reg"); $finish; end
end
end
always @(*) begin
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
begin
main_136_139 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB35_122)
begin
main_136_139_reg <= main_136_139;
if (^reset !== 1'bX && ^(main_136_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_136_139_reg"); $finish; end
end
end
always @(*) begin
/* main: %136*/
/* %140 = icmp eq i32 %138, %139*/
begin
main_136_140 = main_136_138_reg == main_136_139;
end
end
always @(*) begin
/* main: %141*/
/* %142 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_141_142 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %141*/
/* %143 = add nsw i32 %142, 1*/
begin
main_141_143 = main_141_142 + 32'd1;
end
end
always @(*) begin
/* main: %144*/
/* %145 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
begin
main_144_145 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %144*/
/* %146 = sext i8 %145 to i32*/
begin
main_144_146 = $signed(main_144_145);
end
end
always @(*) begin
/* main: %144*/
/* %147 = icmp eq i32 %146, %139*/
begin
main_144_147 = main_144_146 == main_136_139_reg;
end
end
always @(*) begin
/* main: %148*/
/* %149 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_148_149 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %148*/
/* %150 = add nsw i32 %149, 1*/
begin
main_148_150 = main_148_149 + 32'd1;
end
end
always @(*) begin
/* main: %151*/
/* %152 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
begin
main_151_152 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %151*/
/* %153 = sext i8 %152 to i32*/
begin
main_151_153 = $signed(main_151_152);
end
end
always @(posedge clk) begin
/* main: %151*/
/* %153 = sext i8 %152 to i32*/
if (cur_state == LEGUP_F_main_BB39_134)
begin
main_151_153_reg <= main_151_153;
if (^reset !== 1'bX && ^(main_151_153) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_151_153_reg"); $finish; end
end
end
always @(*) begin
/* main: %151*/
/* %154 = load i32* %scevgep11.i.i.i, align 4, !tbaa !0*/
begin
main_151_154 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %151*/
/* %155 = icmp eq i32 %153, %154*/
begin
main_151_155 = main_151_153_reg == main_151_154;
end
end
always @(*) begin
/* main: %156*/
/* %157 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_156_157 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %156*/
/* %158 = add nsw i32 %157, 1*/
begin
main_156_158 = main_156_157 + 32'd1;
end
end
always @(*) begin
/* main: %159*/
/* %160 = icmp slt i32 %tmp12.i.i.i, %71*/
begin
main_159_160 = $signed(main__lr_ph_i1_i_i_tmp12_i_i_i_reg) < $signed(main_32_71_reg);
end
end
always @(*) begin
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4 = main___crit_edge_i_i_i_ReadBuf_4_phi_temp;
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
else if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4 = main___crit_edge_i_i_i_ReadBuf_4_phi_temp;
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
else /* if (cur_state == LEGUP_F_main_BB42_140) */
begin
main___crit_edge_i_i_i_ReadBuf_4 = main___crit_edge_i_i_i_ReadBuf_4_phi_temp;
end
end
always @(posedge clk) begin
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4_reg <= main___crit_edge_i_i_i_ReadBuf_4;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_reg"); $finish; end
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4_reg <= main___crit_edge_i_i_i_ReadBuf_4;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_reg"); $finish; end
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4_reg <= main___crit_edge_i_i_i_ReadBuf_4;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_reg"); $finish; end
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4_reg <= main___crit_edge_i_i_i_ReadBuf_4;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_reg"); $finish; end
end
end
always @(*) begin
/* main: %._crit_edge.i.i.i*/
/* %161 = load i8* getelementptr inbounds ([3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 0), align 1, !tbaa !1*/
begin
main___crit_edge_i_i_i_161 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %._crit_edge.i.i.i*/
/* %162 = icmp eq i8 %161, 2*/
begin
main___crit_edge_i_i_i_162 = main___crit_edge_i_i_i_161 == 8'd2;
end
end
always @(*) begin
/* main: %167*/
/* %168 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
begin
main_167_168 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %168 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
main_167_168_reg <= main_167_168;
if (^reset !== 1'bX && ^(main_167_168) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_168_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %169 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
begin
main_167_169 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %167*/
/* %170 = zext i8 %169 to i16*/
begin
main_167_170 = main_167_169;
end
end
always @(*) begin
/* main: %167*/
/* %171 = shl nuw i16 %170, 8*/
begin
main_167_171 = main_167_170 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %171 = shl nuw i16 %170, 8*/
if (cur_state == LEGUP_F_main_BB45_147)
begin
main_167_171_reg <= main_167_171;
if (^reset !== 1'bX && ^(main_167_171) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_171_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %172 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
begin
main_167_172 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %172 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
main_167_172_reg <= main_167_172;
if (^reset !== 1'bX && ^(main_167_172) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_172_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %173 = load i8* %168, align 1, !tbaa !1*/
begin
main_167_173 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %167*/
/* %174 = zext i8 %173 to i16*/
begin
main_167_174 = main_167_173;
end
end
always @(*) begin
/* main: %167*/
/* %175 = or i16 %171, %174*/
begin
main_167_175 = main_167_171_reg | main_167_174;
end
end
always @(*) begin
/* main: %167*/
/* %176 = sext i16 %175 to i32*/
begin
main_167_176 = $signed(main_167_175);
end
end
always @(*) begin
/* main: %167*/
/* %177 = getelementptr inbounds i8* %ReadBuf.2, i32 3*/
begin
main_167_177 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd3;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %177 = getelementptr inbounds i8* %ReadBuf.2, i32 3*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
main_167_177_reg <= main_167_177;
if (^reset !== 1'bX && ^(main_167_177) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_177_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
begin
main_167_178 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_149)
begin
main_167_178_reg <= main_167_178;
if (^reset !== 1'bX && ^(main_167_178) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_178_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %179 = zext i8 %178 to i32*/
begin
main_167_179 = main_167_178;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %179 = zext i8 %178 to i32*/
if (cur_state == LEGUP_F_main_BB45_149)
begin
main_167_179_reg <= main_167_179;
if (^reset !== 1'bX && ^(main_167_179) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_179_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %182 = icmp eq i16 %175, 12*/
begin
main_167_182 = main_167_175 == 16'd12;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %182 = icmp eq i16 %175, 12*/
if (cur_state == LEGUP_F_main_BB45_148)
begin
main_167_182_reg <= main_167_182;
if (^reset !== 1'bX && ^(main_167_182) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_182_reg"); $finish; end
end
end
always @(*) begin
/* main: %183*/
/* %184 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_183_184 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %183*/
/* %185 = add nsw i32 %184, 1*/
begin
main_183_185 = main_183_184 + 32'd1;
end
end
always @(*) begin
/* main: %186*/
/* %187 = icmp eq i8 %178, 3*/
begin
main_186_187 = main_167_178_reg == 8'd3;
end
end
always @(*) begin
/* main: %188*/
/* %189 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_188_189 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %188*/
/* %190 = add nsw i32 %189, 1*/
begin
main_188_190 = main_188_189 + 32'd1;
end
end
always @(*) begin
/* main: %.preheader5.i.i.i.preheader*/
/* %191 = sext i8 %p_jinfo_num_components.1.ph13 to i32*/
begin
main__preheader5_i_i_i_preheader_191 = $signed(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg);
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i.preheader*/
/* %191 = sext i8 %p_jinfo_num_components.1.ph13 to i32*/
if (cur_state == LEGUP_F_main_BB49_157)
begin
main__preheader5_i_i_i_preheader_191_reg <= main__preheader5_i_i_i_preheader_191;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_preheader_191) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_preheader_191_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0 = main__preheader5_i_i_i_i_get_sos_0_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
else if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0 = main__preheader5_i_i_i_i_get_sos_0_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
else if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0 = main__preheader5_i_i_i_i_get_sos_0_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
else /* if (cur_state == LEGUP_F_main_BB50_158) */
begin
main__preheader5_i_i_i_i_get_sos_0 = main__preheader5_i_i_i_i_get_sos_0_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0_reg <= main__preheader5_i_i_i_i_get_sos_0;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_i_get_sos_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0_reg <= main__preheader5_i_i_i_i_get_sos_0;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_i_get_sos_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0_reg <= main__preheader5_i_i_i_i_get_sos_0;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_i_get_sos_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0_reg <= main__preheader5_i_i_i_i_get_sos_0;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_i_get_sos_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0_reg <= main__preheader5_i_i_i_i_get_sos_0;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_i_get_sos_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5 = main__preheader5_i_i_i_ReadBuf_5_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
else if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5 = main__preheader5_i_i_i_ReadBuf_5_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
else if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5 = main__preheader5_i_i_i_ReadBuf_5_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
else if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5 = main__preheader5_i_i_i_ReadBuf_5_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
else /* if (cur_state == LEGUP_F_main_BB50_158) */
begin
main__preheader5_i_i_i_ReadBuf_5 = main__preheader5_i_i_i_ReadBuf_5_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_192 = main__preheader5_i_i_i_192_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
else /* if (cur_state == LEGUP_F_main_BB50_158) */
begin
main__preheader5_i_i_i_192 = main__preheader5_i_i_i_192_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_192_reg <= main__preheader5_i_i_i_192;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_192_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_192_reg <= main__preheader5_i_i_i_192;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_192_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_192_reg <= main__preheader5_i_i_i_192;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_192_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader5.i.i.i*/
/* %193 = icmp slt i32 %192, %179*/
begin
main__preheader5_i_i_i_193 = $signed(main__preheader5_i_i_i_192) < $signed(main_167_179_reg);
end
end
always @(*) begin
/* main: %194*/
/* %195 = getelementptr inbounds i8* %ReadBuf.5, i32 1*/
begin
main_194_195 = main__preheader5_i_i_i_ReadBuf_5_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %194*/
/* %195 = getelementptr inbounds i8* %ReadBuf.5, i32 1*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
main_194_195_reg <= main_194_195;
if (^reset !== 1'bX && ^(main_194_195) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_194_195_reg"); $finish; end
end
end
always @(*) begin
/* main: %194*/
/* %196 = load i8* %ReadBuf.5, align 1, !tbaa !1*/
begin
main_194_196 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %194*/
/* %197 = zext i8 %196 to i32*/
begin
main_194_197 = main_194_196;
end
end
always @(posedge clk) begin
/* main: %194*/
/* %197 = zext i8 %196 to i32*/
if (cur_state == LEGUP_F_main_BB51_161)
begin
main_194_197_reg <= main_194_197;
if (^reset !== 1'bX && ^(main_194_197) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_194_197_reg"); $finish; end
end
end
always @(*) begin
/* main: %194*/
/* %198 = getelementptr inbounds i8* %ReadBuf.5, i32 2*/
begin
main_194_198 = main__preheader5_i_i_i_ReadBuf_5_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %194*/
/* %198 = getelementptr inbounds i8* %ReadBuf.5, i32 2*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
main_194_198_reg <= main_194_198;
if (^reset !== 1'bX && ^(main_194_198) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_194_198_reg"); $finish; end
end
end
always @(*) begin
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
begin
main_194_199 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_162)
begin
main_194_199_reg <= main_194_199;
if (^reset !== 1'bX && ^(main_194_199) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_194_199_reg"); $finish; end
end
end
always @(*) begin
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201 = main_200_201_phi_temp;
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
else if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201 = main_200_201_phi_temp;
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
else if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201 = main_200_201_phi_temp;
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
else if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201 = main_200_201_phi_temp;
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
else /* if (cur_state == LEGUP_F_main_BB52_163) */
begin
main_200_201 = main_200_201_phi_temp;
end
end
always @(posedge clk) begin
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
end
always @(*) begin
/* main: %200*/
/* %202 = icmp slt i32 %201, %191*/
begin
main_200_202 = $signed(main_200_201) < $signed(main__preheader5_i_i_i_preheader_191_reg);
end
end
always @(*) begin
/* main: %203*/
/* %scevgep9.i4.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_id, i32 0, i32 %201*/
begin
main_203_scevgep9_i4_i_i = `TAG_g_p_jinfo_comps_info_id_a + 1 * main_200_201_reg;
end
end
always @(*) begin
/* main: %203*/
/* %204 = load i8* %scevgep9.i4.i.i, align 1, !tbaa !1*/
begin
main_203_204 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %203*/
/* %205 = sext i8 %204 to i32*/
begin
main_203_205 = $signed(main_203_204);
end
end
always @(*) begin
/* main: %203*/
/* %206 = icmp eq i32 %197, %205*/
begin
main_203_206 = main_194_197_reg == main_203_205;
end
end
always @(*) begin
/* main: %207*/
/* %208 = add nsw i32 %201, 1*/
begin
main_207_208 = main_200_201_reg + 32'd1;
end
end
always @(*) begin
/* main: %211*/
/* %scevgep8.i5.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_dc_tbl_no, i32 0, i32 %201*/
begin
main_211_scevgep8_i5_i_i = `TAG_g_p_jinfo_comps_info_dc_tbl_no_a + 1 * main_200_201_reg;
end
end
always @(posedge clk) begin
/* main: %211*/
/* %scevgep8.i5.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_dc_tbl_no, i32 0, i32 %201*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
main_211_scevgep8_i5_i_i_reg <= main_211_scevgep8_i5_i_i;
if (^reset !== 1'bX && ^(main_211_scevgep8_i5_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_211_scevgep8_i5_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %211*/
/* %scevgep7.i6.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_ac_tbl_no, i32 0, i32 %201*/
begin
main_211_scevgep7_i6_i_i = `TAG_g_p_jinfo_comps_info_ac_tbl_no_a + 1 * main_200_201_reg;
end
end
always @(posedge clk) begin
/* main: %211*/
/* %scevgep7.i6.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_ac_tbl_no, i32 0, i32 %201*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
main_211_scevgep7_i6_i_i_reg <= main_211_scevgep7_i6_i_i;
if (^reset !== 1'bX && ^(main_211_scevgep7_i6_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_211_scevgep7_i6_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %211*/
/* %212 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_211_212 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %211*/
/* %213 = add nsw i32 %212, 1*/
begin
main_211_213 = main_211_212 + 32'd1;
end
end
always @(*) begin
/* main: %211*/
/* %214 = lshr i8 %199, 4*/
begin
main_211_214 = main_194_199_reg >>> 8'd4 % 8'd8;
end
end
always @(posedge clk) begin
/* main: %211*/
/* %214 = lshr i8 %199, 4*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
main_211_214_reg <= main_211_214;
if (^reset !== 1'bX && ^(main_211_214) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_211_214_reg"); $finish; end
end
end
always @(*) begin
/* main: %211*/
/* %215 = and i8 %199, 15*/
begin
main_211_215 = main_194_199_reg & 8'd15;
end
end
always @(posedge clk) begin
/* main: %211*/
/* %215 = and i8 %199, 15*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
main_211_215_reg <= main_211_215;
if (^reset !== 1'bX && ^(main_211_215) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_211_215_reg"); $finish; end
end
end
always @(*) begin
/* main: %211*/
/* %217 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
begin
main_211_217 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %211*/
/* %218 = sext i8 %217 to i32*/
begin
main_211_218 = $signed(main_211_217);
end
end
always @(*) begin
/* main: %211*/
/* %220 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
begin
main_211_220 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %211*/
/* %221 = sext i8 %220 to i32*/
begin
main_211_221 = $signed(main_211_220);
end
end
always @(*) begin
/* main: %211*/
/* %223 = getelementptr inbounds [3 x i32]* @out_comp_id_get_sos, i32 0, i32 %i_get_sos.0*/
begin
main_211_223 = `TAG_g_out_comp_id_get_sos_a + 4 * main__preheader5_i_i_i_i_get_sos_0_reg;
end
end
always @(posedge clk) begin
/* main: %211*/
/* %223 = getelementptr inbounds [3 x i32]* @out_comp_id_get_sos, i32 0, i32 %i_get_sos.0*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
main_211_223_reg <= main_211_223;
if (^reset !== 1'bX && ^(main_211_223) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_211_223_reg"); $finish; end
end
end
always @(*) begin
/* main: %211*/
/* %224 = load i32* %223, align 4, !tbaa !0*/
begin
main_211_224 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %211*/
/* %225 = icmp eq i32 %197, %224*/
begin
main_211_225 = main_194_197_reg == main_211_224;
end
end
always @(*) begin
/* main: %226*/
/* %227 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_226_227 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %226*/
/* %228 = add nsw i32 %227, 1*/
begin
main_226_228 = main_226_227 + 32'd1;
end
end
always @(*) begin
/* main: %229*/
/* %230 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
begin
main_229_230 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %229*/
/* %231 = sext i8 %230 to i32*/
begin
main_229_231 = $signed(main_229_230);
end
end
always @(posedge clk) begin
/* main: %229*/
/* %231 = sext i8 %230 to i32*/
if (cur_state == LEGUP_F_main_BB58_188)
begin
main_229_231_reg <= main_229_231;
if (^reset !== 1'bX && ^(main_229_231) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_229_231_reg"); $finish; end
end
end
always @(*) begin
/* main: %229*/
/* %232 = getelementptr inbounds [3 x i32]* @out_ac_tbl_no_get_sos, i32 0, i32 %i_get_sos.0*/
begin
main_229_232 = `TAG_g_out_ac_tbl_no_get_sos_a + 4 * main__preheader5_i_i_i_i_get_sos_0_reg;
end
end
always @(posedge clk) begin
/* main: %229*/
/* %232 = getelementptr inbounds [3 x i32]* @out_ac_tbl_no_get_sos, i32 0, i32 %i_get_sos.0*/
if (cur_state == LEGUP_F_main_BB58_186)
begin
main_229_232_reg <= main_229_232;
if (^reset !== 1'bX && ^(main_229_232) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_229_232_reg"); $finish; end
end
end
always @(*) begin
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
begin
main_229_233 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB58_189)
begin
main_229_233_reg <= main_229_233;
if (^reset !== 1'bX && ^(main_229_233) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_229_233_reg"); $finish; end
end
end
always @(*) begin
/* main: %229*/
/* %234 = icmp eq i32 %231, %233*/
begin
main_229_234 = main_229_231_reg == main_229_233;
end
end
always @(*) begin
/* main: %235*/
/* %236 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_235_236 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %235*/
/* %237 = add nsw i32 %236, 1*/
begin
main_235_237 = main_235_236 + 32'd1;
end
end
always @(*) begin
/* main: %238*/
/* %239 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
begin
main_238_239 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %238*/
/* %240 = sext i8 %239 to i32*/
begin
main_238_240 = $signed(main_238_239);
end
end
always @(*) begin
/* main: %238*/
/* %241 = icmp eq i32 %240, %233*/
begin
main_238_241 = main_238_240 == main_229_233_reg;
end
end
always @(*) begin
/* main: %242*/
/* %243 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_242_243 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %242*/
/* %244 = add nsw i32 %243, 1*/
begin
main_242_244 = main_242_243 + 32'd1;
end
end
always @(*) begin
/* main: %245*/
/* %246 = add nsw i32 %i_get_sos.0, 1*/
begin
main_245_246 = main__preheader5_i_i_i_i_get_sos_0_reg + 32'd1;
end
end
always @(*) begin
/* main: %245*/
/* %247 = add nsw i32 %192, 1*/
begin
main_245_247 = main__preheader5_i_i_i_192_reg + 32'd1;
end
end
always @(*) begin
/* main: %get_sos.exit.i.i*/
/* %scevgep.i2.i.i = getelementptr i8* %ReadBuf.5, i32 3*/
begin
main_get_sos_exit_i_i_scevgep_i2_i_i = main__preheader5_i_i_i_ReadBuf_5_reg + 1 * 32'd3;
end
end
always @(*) begin
/* main: %248*/
/* %249 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
begin
main_248_249 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %248*/
/* %249 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
main_248_249_reg <= main_248_249;
if (^reset !== 1'bX && ^(main_248_249) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_248_249_reg"); $finish; end
end
end
always @(*) begin
/* main: %248*/
/* %250 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
begin
main_248_250 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %248*/
/* %251 = zext i8 %250 to i16*/
begin
main_248_251 = main_248_250;
end
end
always @(*) begin
/* main: %248*/
/* %252 = shl nuw i16 %251, 8*/
begin
main_248_252 = main_248_251 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %248*/
/* %252 = shl nuw i16 %251, 8*/
if (cur_state == LEGUP_F_main_BB64_203)
begin
main_248_252_reg <= main_248_252;
if (^reset !== 1'bX && ^(main_248_252) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_248_252_reg"); $finish; end
end
end
always @(*) begin
/* main: %248*/
/* %253 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
begin
main_248_253 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %248*/
/* %253 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
main_248_253_reg <= main_248_253;
if (^reset !== 1'bX && ^(main_248_253) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_248_253_reg"); $finish; end
end
end
always @(*) begin
/* main: %248*/
/* %254 = load i8* %249, align 1, !tbaa !1*/
begin
main_248_254 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %248*/
/* %255 = zext i8 %254 to i16*/
begin
main_248_255 = main_248_254;
end
end
always @(*) begin
/* main: %248*/
/* %256 = or i16 %252, %255*/
begin
main_248_256 = main_248_252_reg | main_248_255;
end
end
always @(*) begin
/* main: %248*/
/* %257 = sext i16 %256 to i32*/
begin
main_248_257 = $signed(main_248_256);
end
end
always @(*) begin
/* main: %248*/
/* %258 = add nsw i32 %257, -2*/
begin
main_248_258 = main_248_257 + -32'd2;
end
end
always @(posedge clk) begin
/* main: %248*/
/* %258 = add nsw i32 %257, -2*/
if (cur_state == LEGUP_F_main_BB64_204)
begin
main_248_258_reg <= main_248_258;
if (^reset !== 1'bX && ^(main_248_258) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_248_258_reg"); $finish; end
end
end
always @(*) begin
/* main: %248*/
/* %260 = load i32* %4, align 4, !tbaa !0*/
begin
main_248_260 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %248*/
/* %261 = icmp eq i32 %258, %260*/
begin
main_248_261 = main_248_258_reg == main_248_260;
end
end
always @(*) begin
/* main: %262*/
/* %263 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_262_263 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %262*/
/* %264 = add nsw i32 %263, 1*/
begin
main_262_264 = main_262_263 + 32'd1;
end
end
always @(*) begin
/* main: %.preheader.i7.i.i*/
/* %265 = icmp sgt i32 %258, 16*/
begin
main__preheader_i7_i_i_265 = $signed(main_248_258_reg) > $signed(32'd16);
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2 = main__lr_ph5_i_i_i_i_get_dht_2_phi_temp;
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
else if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2 = main__lr_ph5_i_i_i_i_get_dht_2_phi_temp;
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB67_212) */
begin
main__lr_ph5_i_i_i_i_get_dht_2 = main__lr_ph5_i_i_i_i_get_dht_2_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2_reg <= main__lr_ph5_i_i_i_i_get_dht_2;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_i_get_dht_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_reg"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2_reg <= main__lr_ph5_i_i_i_i_get_dht_2;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_i_get_dht_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_reg"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2_reg <= main__lr_ph5_i_i_i_i_get_dht_2;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_i_get_dht_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_reg"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2_reg <= main__lr_ph5_i_i_i_i_get_dht_2;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_i_get_dht_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %ReadBuf.6 = phi i8* [ %ReadBuf.7, %._crit_edge.i12.i.i ], [ %253, %.preheader.i7.i.i ]*/
begin
main__lr_ph5_i_i_i_ReadBuf_6 = main__lr_ph5_i_i_i_ReadBuf_6_phi_temp;
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_length_04_i_i_i = main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp;
end
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB67_212) */
begin
main__lr_ph5_i_i_i_length_04_i_i_i = main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_length_04_i_i_i_reg <= main__lr_ph5_i_i_i_length_04_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_length_04_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_length_04_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_length_04_i_i_i_reg <= main__lr_ph5_i_i_i_length_04_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_length_04_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_length_04_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_length_04_i_i_i_reg <= main__lr_ph5_i_i_i_length_04_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_length_04_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_length_04_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %266 = getelementptr inbounds i8* %ReadBuf.6, i32 1*/
begin
main__lr_ph5_i_i_i_266 = main__lr_ph5_i_i_i_ReadBuf_6 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %266 = getelementptr inbounds i8* %ReadBuf.6, i32 1*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_266_reg <= main__lr_ph5_i_i_i_266;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_266) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_266_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %267 = load i8* %ReadBuf.6, align 1, !tbaa !1*/
begin
main__lr_ph5_i_i_i_267 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %268 = zext i8 %267 to i32*/
begin
main__lr_ph5_i_i_i_268 = main__lr_ph5_i_i_i_267;
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %268 = zext i8 %267 to i32*/
if (cur_state == LEGUP_F_main_BB67_214)
begin
main__lr_ph5_i_i_i_268_reg <= main__lr_ph5_i_i_i_268;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_268) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_268_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %270 = getelementptr inbounds [4 x i32]* @out_index_get_dht, i32 0, i32 %i_get_dht.2*/
begin
main__lr_ph5_i_i_i_270 = `TAG_g_out_index_get_dht_a + 4 * main__lr_ph5_i_i_i_i_get_dht_2;
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %270 = getelementptr inbounds [4 x i32]* @out_index_get_dht, i32 0, i32 %i_get_dht.2*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_270_reg <= main__lr_ph5_i_i_i_270;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_270) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_270_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %271 = load i32* %270, align 4, !tbaa !0*/
begin
main__lr_ph5_i_i_i_271 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %272 = icmp eq i32 %268, %271*/
begin
main__lr_ph5_i_i_i_272 = main__lr_ph5_i_i_i_268_reg == main__lr_ph5_i_i_i_271;
end
end
always @(*) begin
/* main: %273*/
/* %274 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_273_274 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %273*/
/* %275 = add nsw i32 %274, 1*/
begin
main_273_275 = main_273_274 + 32'd1;
end
end
always @(*) begin
/* main: %276*/
/* %277 = and i32 %268, 16*/
begin
main_276_277 = main__lr_ph5_i_i_i_268_reg & 32'd16;
end
end
always @(*) begin
/* main: %276*/
/* %278 = icmp eq i32 %277, 0*/
begin
main_276_278 = main_276_277 == 32'd0;
end
end
always @(*) begin
/* main: %279*/
/* %280 = add nsw i32 %268, -16*/
begin
main_279_280 = main__lr_ph5_i_i_i_268_reg + -32'd16;
end
end
always @(*) begin
/* main: %279*/
/* %281 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 %280, i32 0*/
begin
main_279_281 = `TAG_g_p_jinfo_ac_xhuff_tbl_bits_a + 144 * main_279_280;
end
end
always @(*) begin
/* main: %279*/
/* %282 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_ac_xhuff_tbl_huffval, i32 0, i32 %280, i32 0*/
begin
main_279_282 = `TAG_g_p_jinfo_ac_xhuff_tbl_huffval_a + 1028 * main_279_280;
end
end
always @(*) begin
/* main: %283*/
/* %284 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 %268, i32 0*/
begin
main_283_284 = `TAG_g_p_jinfo_dc_xhuff_tbl_bits_a + 144 * main__lr_ph5_i_i_i_268_reg;
end
end
always @(*) begin
/* main: %283*/
/* %285 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_dc_xhuff_tbl_huffval, i32 0, i32 %268, i32 0*/
begin
main_283_285 = `TAG_g_p_jinfo_dc_xhuff_tbl_huffval_a + 1028 * main__lr_ph5_i_i_i_268_reg;
end
end
always @(*) begin
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_huffval_0_i_i_i = main_286_p_xhtbl_huffval_0_i_i_i_phi_temp;
end
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
else /* if (cur_state == LEGUP_F_main_BB72_224) */
begin
main_286_p_xhtbl_huffval_0_i_i_i = main_286_p_xhtbl_huffval_0_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_huffval_0_i_i_i_reg <= main_286_p_xhtbl_huffval_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_huffval_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_huffval_0_i_i_i_reg"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_huffval_0_i_i_i_reg <= main_286_p_xhtbl_huffval_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_huffval_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_huffval_0_i_i_i_reg"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_huffval_0_i_i_i_reg <= main_286_p_xhtbl_huffval_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_huffval_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_huffval_0_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_bits_0_i_i_i = main_286_p_xhtbl_bits_0_i_i_i_phi_temp;
end
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
else /* if (cur_state == LEGUP_F_main_BB72_224) */
begin
main_286_p_xhtbl_bits_0_i_i_i = main_286_p_xhtbl_bits_0_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_bits_0_i_i_i_reg <= main_286_p_xhtbl_bits_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_bits_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_bits_0_i_i_i_reg"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_bits_0_i_i_i_reg <= main_286_p_xhtbl_bits_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_bits_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_bits_0_i_i_i_reg"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_bits_0_i_i_i_reg <= main_286_p_xhtbl_bits_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_bits_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_bits_0_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %288 = phi i8* [ %266, %286 ], [ %289, %287 ]*/
begin
main_287_288 = main_287_288_phi_temp;
end
end
always @(*) begin
/* main: %287*/
/* %indvar.i.i.i = phi i32 [ 0, %286 ], [ %tmp.i8.i.i, %287 ]*/
begin
main_287_indvar_i_i_i = main_287_indvar_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_count_01_i_i_i = main_287_count_01_i_i_i_phi_temp;
end
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
else /* if (cur_state == LEGUP_F_main_BB73_225) */
begin
main_287_count_01_i_i_i = main_287_count_01_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_count_01_i_i_i_reg <= main_287_count_01_i_i_i;
if (^reset !== 1'bX && ^(main_287_count_01_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_count_01_i_i_i_reg"); $finish; end
end
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_count_01_i_i_i_reg <= main_287_count_01_i_i_i;
if (^reset !== 1'bX && ^(main_287_count_01_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_count_01_i_i_i_reg"); $finish; end
end
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_count_01_i_i_i_reg <= main_287_count_01_i_i_i;
if (^reset !== 1'bX && ^(main_287_count_01_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_count_01_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %tmp.i8.i.i = add i32 %indvar.i.i.i, 1*/
begin
main_287_tmp_i8_i_i = main_287_indvar_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %tmp.i8.i.i = add i32 %indvar.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_tmp_i8_i_i_reg <= main_287_tmp_i8_i_i;
if (^reset !== 1'bX && ^(main_287_tmp_i8_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_tmp_i8_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %scevgep.i9.i.i = getelementptr i32* %p_xhtbl_bits.0.i.i.i, i32 %tmp.i8.i.i*/
begin
main_287_scevgep_i9_i_i = main_286_p_xhtbl_bits_0_i_i_i_reg + 4 * main_287_tmp_i8_i_i;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %scevgep.i9.i.i = getelementptr i32* %p_xhtbl_bits.0.i.i.i, i32 %tmp.i8.i.i*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_scevgep_i9_i_i_reg <= main_287_scevgep_i9_i_i;
if (^reset !== 1'bX && ^(main_287_scevgep_i9_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_scevgep_i9_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %289 = getelementptr inbounds i8* %288, i32 1*/
begin
main_287_289 = main_287_288 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %289 = getelementptr inbounds i8* %288, i32 1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_289_reg <= main_287_289;
if (^reset !== 1'bX && ^(main_287_289) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_289_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %290 = load i8* %288, align 1, !tbaa !1*/
begin
main_287_290 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %287*/
/* %291 = zext i8 %290 to i32*/
begin
main_287_291 = main_287_290;
end
end
always @(*) begin
/* main: %287*/
/* %292 = add nsw i32 %291, %count.01.i.i.i*/
begin
main_287_292 = main_287_291 + main_287_count_01_i_i_i_reg;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %292 = add nsw i32 %291, %count.01.i.i.i*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
main_287_292_reg <= main_287_292;
if (^reset !== 1'bX && ^(main_287_292) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_292_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %exitcond.i.i.i = icmp eq i32 %tmp.i8.i.i, 16*/
begin
main_287_exitcond_i_i_i = main_287_tmp_i8_i_i == 32'd16;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %exitcond.i.i.i = icmp eq i32 %tmp.i8.i.i, 16*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_exitcond_i_i_i_reg <= main_287_exitcond_i_i_i;
if (^reset !== 1'bX && ^(main_287_exitcond_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_exitcond_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %293*/
/* %295 = getelementptr inbounds [4 x i32]* @out_count_get_dht, i32 0, i32 %i_get_dht.2*/
begin
main_293_295 = `TAG_g_out_count_get_dht_a + 4 * main__lr_ph5_i_i_i_i_get_dht_2_reg;
end
end
always @(posedge clk) begin
/* main: %293*/
/* %295 = getelementptr inbounds [4 x i32]* @out_count_get_dht, i32 0, i32 %i_get_dht.2*/
if (cur_state == LEGUP_F_main_BB74_228)
begin
main_293_295_reg <= main_293_295;
if (^reset !== 1'bX && ^(main_293_295) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_293_295_reg"); $finish; end
end
end
always @(*) begin
/* main: %293*/
/* %296 = load i32* %295, align 4, !tbaa !0*/
begin
main_293_296 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %293*/
/* %297 = icmp eq i32 %292, %296*/
begin
main_293_297 = main_287_292_reg == main_293_296;
end
end
always @(*) begin
/* main: %298*/
/* %299 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_298_299 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %298*/
/* %300 = add nsw i32 %299, 1*/
begin
main_298_300 = main_298_299 + 32'd1;
end
end
always @(*) begin
/* main: %301*/
/* %302 = add nsw i32 %i_get_dht.2, 1*/
begin
main_301_302 = main__lr_ph5_i_i_i_i_get_dht_2_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %301*/
/* %302 = add nsw i32 %i_get_dht.2, 1*/
if (cur_state == LEGUP_F_main_BB76_235)
begin
main_301_302_reg <= main_301_302;
if (^reset !== 1'bX && ^(main_301_302) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_301_302_reg"); $finish; end
end
end
always @(*) begin
/* main: %301*/
/* %303 = icmp sgt i32 %292, 0*/
begin
main_301_303 = $signed(main_287_292_reg) > $signed(32'd0);
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %304 = phi i8* [ %305, %.lr.ph.i10.i.i ], [ %289, %301 ]*/
begin
main__lr_ph_i10_i_i_304 = main__lr_ph_i10_i_i_304_phi_temp;
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %i.13.i.i.i = phi i32 [ %308, %.lr.ph.i10.i.i ], [ 0, %301 ]*/
begin
main__lr_ph_i10_i_i_i_13_i_i_i = main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %scevgep8.i11.i.i = getelementptr i32* %p_xhtbl_huffval.0.i.i.i, i32 %i.13.i.i.i*/
begin
main__lr_ph_i10_i_i_scevgep8_i11_i_i = main_286_p_xhtbl_huffval_0_i_i_i_reg + 4 * main__lr_ph_i10_i_i_i_13_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %scevgep8.i11.i.i = getelementptr i32* %p_xhtbl_huffval.0.i.i.i, i32 %i.13.i.i.i*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
main__lr_ph_i10_i_i_scevgep8_i11_i_i_reg <= main__lr_ph_i10_i_i_scevgep8_i11_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_scevgep8_i11_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_scevgep8_i11_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %305 = getelementptr inbounds i8* %304, i32 1*/
begin
main__lr_ph_i10_i_i_305 = main__lr_ph_i10_i_i_304 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %305 = getelementptr inbounds i8* %304, i32 1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
main__lr_ph_i10_i_i_305_reg <= main__lr_ph_i10_i_i_305;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_305) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_305_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %306 = load i8* %304, align 1, !tbaa !1*/
begin
main__lr_ph_i10_i_i_306 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %307 = zext i8 %306 to i32*/
begin
main__lr_ph_i10_i_i_307 = main__lr_ph_i10_i_i_306;
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %308 = add nsw i32 %i.13.i.i.i, 1*/
begin
main__lr_ph_i10_i_i_308 = main__lr_ph_i10_i_i_i_13_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %308 = add nsw i32 %i.13.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
main__lr_ph_i10_i_i_308_reg <= main__lr_ph_i10_i_i_308;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_308) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_308_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %exitcond7.i.i.i = icmp eq i32 %308, %292*/
begin
main__lr_ph_i10_i_i_exitcond7_i_i_i = main__lr_ph_i10_i_i_308 == main_287_292_reg;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %exitcond7.i.i.i = icmp eq i32 %308, %292*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
main__lr_ph_i10_i_i_exitcond7_i_i_i_reg <= main__lr_ph_i10_i_i_exitcond7_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_exitcond7_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_exitcond7_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %._crit_edge.i12.i.i*/
/* %ReadBuf.7 = phi i8* [ %289, %301 ], [ %305, %.lr.ph.i10.i.i ]*/
begin
main___crit_edge_i12_i_i_ReadBuf_7 = main___crit_edge_i12_i_i_ReadBuf_7_phi_temp;
end
end
always @(*) begin
/* main: %._crit_edge.i12.i.i*/
/* %309 = add i32 %length.04.i.i.i, -17*/
begin
main___crit_edge_i12_i_i_309 = main__lr_ph5_i_i_i_length_04_i_i_i_reg + -32'd17;
end
end
always @(*) begin
/* main: %._crit_edge.i12.i.i*/
/* %310 = sub i32 %309, %292*/
begin
main___crit_edge_i12_i_i_310 = main___crit_edge_i12_i_i_309 - main_287_292_reg;
end
end
always @(*) begin
/* main: %._crit_edge.i12.i.i*/
/* %311 = icmp sgt i32 %310, 16*/
begin
main___crit_edge_i12_i_i_311 = $signed(main___crit_edge_i12_i_i_310) > $signed(32'd16);
end
end
always @(*) begin
/* main: %312*/
/* %313 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
begin
main_312_313 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %312*/
/* %313 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
main_312_313_reg <= main_312_313;
if (^reset !== 1'bX && ^(main_312_313) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_312_313_reg"); $finish; end
end
end
always @(*) begin
/* main: %312*/
/* %314 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
begin
main_312_314 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %312*/
/* %315 = zext i8 %314 to i16*/
begin
main_312_315 = main_312_314;
end
end
always @(*) begin
/* main: %312*/
/* %316 = shl nuw i16 %315, 8*/
begin
main_312_316 = main_312_315 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %312*/
/* %316 = shl nuw i16 %315, 8*/
if (cur_state == LEGUP_F_main_BB79_242)
begin
main_312_316_reg <= main_312_316;
if (^reset !== 1'bX && ^(main_312_316) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_312_316_reg"); $finish; end
end
end
always @(*) begin
/* main: %312*/
/* %317 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
begin
main_312_317 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %312*/
/* %317 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
main_312_317_reg <= main_312_317;
if (^reset !== 1'bX && ^(main_312_317) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_312_317_reg"); $finish; end
end
end
always @(*) begin
/* main: %312*/
/* %318 = load i8* %313, align 1, !tbaa !1*/
begin
main_312_318 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %312*/
/* %319 = zext i8 %318 to i16*/
begin
main_312_319 = main_312_318;
end
end
always @(*) begin
/* main: %312*/
/* %320 = or i16 %316, %319*/
begin
main_312_320 = main_312_316_reg | main_312_319;
end
end
always @(*) begin
/* main: %312*/
/* %321 = sext i16 %320 to i32*/
begin
main_312_321 = $signed(main_312_320);
end
end
always @(*) begin
/* main: %312*/
/* %322 = add nsw i32 %321, -2*/
begin
main_312_322 = main_312_321 + -32'd2;
end
end
always @(posedge clk) begin
/* main: %312*/
/* %322 = add nsw i32 %321, -2*/
if (cur_state == LEGUP_F_main_BB79_243)
begin
main_312_322_reg <= main_312_322;
if (^reset !== 1'bX && ^(main_312_322) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_312_322_reg"); $finish; end
end
end
always @(*) begin
/* main: %312*/
/* %324 = load i32* %5, align 4, !tbaa !0*/
begin
main_312_324 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %312*/
/* %325 = icmp eq i32 %322, %324*/
begin
main_312_325 = main_312_322_reg == main_312_324;
end
end
always @(*) begin
/* main: %326*/
/* %327 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_326_327 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %326*/
/* %328 = add nsw i32 %327, 1*/
begin
main_326_328 = main_326_327 + 32'd1;
end
end
always @(*) begin
/* main: %.preheader.i13.i.i*/
/* %329 = icmp sgt i32 %322, 0*/
begin
main__preheader_i13_i_i_329 = $signed(main_312_322_reg) > $signed(32'd0);
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2 = main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp;
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2 = main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp;
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB82_251) */
begin
main__lr_ph_i15_i_i_i_get_dqt_2 = main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_reg <= main__lr_ph_i15_i_i_i_get_dqt_2;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_i_get_dqt_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_reg"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_reg <= main__lr_ph_i15_i_i_i_get_dqt_2;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_i_get_dqt_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_reg"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_reg <= main__lr_ph_i15_i_i_i_get_dqt_2;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_i_get_dqt_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_reg"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_reg <= main__lr_ph_i15_i_i_i_get_dqt_2;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_i_get_dqt_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %330 = phi i8* [ %ReadBuf.8, %.us-lcssa.us.i.i.i ], [ %317, %.preheader.i13.i.i ]*/
begin
main__lr_ph_i15_i_i_330 = main__lr_ph_i15_i_i_330_phi_temp;
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_length_02_i_i_i = main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp;
end
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB82_251) */
begin
main__lr_ph_i15_i_i_length_02_i_i_i = main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_length_02_i_i_i_reg <= main__lr_ph_i15_i_i_length_02_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_length_02_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_length_02_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_length_02_i_i_i_reg <= main__lr_ph_i15_i_i_length_02_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_length_02_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_length_02_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_length_02_i_i_i_reg <= main__lr_ph_i15_i_i_length_02_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_length_02_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_length_02_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %331 = getelementptr inbounds i8* %330, i32 1*/
begin
main__lr_ph_i15_i_i_331 = main__lr_ph_i15_i_i_330 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %331 = getelementptr inbounds i8* %330, i32 1*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_331_reg <= main__lr_ph_i15_i_i_331;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_331) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_331_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %332 = load i8* %330, align 1, !tbaa !1*/
begin
main__lr_ph_i15_i_i_332 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %333 = zext i8 %332 to i32*/
begin
main__lr_ph_i15_i_i_333 = main__lr_ph_i15_i_i_332;
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %334 = lshr i32 %333, 4*/
begin
main__lr_ph_i15_i_i_334 = main__lr_ph_i15_i_i_333 >>> 32'd4 % 32;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %334 = lshr i32 %333, 4*/
if (cur_state == LEGUP_F_main_BB82_253)
begin
main__lr_ph_i15_i_i_334_reg <= main__lr_ph_i15_i_i_334;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_334) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_334_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %335 = and i32 %333, 15*/
begin
main__lr_ph_i15_i_i_335 = main__lr_ph_i15_i_i_333 & 32'd15;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %335 = and i32 %333, 15*/
if (cur_state == LEGUP_F_main_BB82_253)
begin
main__lr_ph_i15_i_i_335_reg <= main__lr_ph_i15_i_i_335;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_335) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_335_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %338 = getelementptr inbounds [2 x i32]* @out_prec_get_dht, i32 0, i32 %i_get_dqt.2*/
begin
main__lr_ph_i15_i_i_338 = `TAG_g_out_prec_get_dht_a + 4 * main__lr_ph_i15_i_i_i_get_dqt_2;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %338 = getelementptr inbounds [2 x i32]* @out_prec_get_dht, i32 0, i32 %i_get_dqt.2*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_338_reg <= main__lr_ph_i15_i_i_338;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_338) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_338_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %339 = load i32* %338, align 4, !tbaa !0*/
begin
main__lr_ph_i15_i_i_339 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %340 = icmp eq i32 %334, %339*/
begin
main__lr_ph_i15_i_i_340 = main__lr_ph_i15_i_i_334_reg == main__lr_ph_i15_i_i_339;
end
end
always @(*) begin
/* main: %341*/
/* %342 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_341_342 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %341*/
/* %343 = add nsw i32 %342, 1*/
begin
main_341_343 = main_341_342 + 32'd1;
end
end
always @(*) begin
/* main: %344*/
/* %345 = getelementptr inbounds [2 x i32]* @out_num_get_dht, i32 0, i32 %i_get_dqt.2*/
begin
main_344_345 = `TAG_g_out_num_get_dht_a + 4 * main__lr_ph_i15_i_i_i_get_dqt_2_reg;
end
end
always @(*) begin
/* main: %344*/
/* %346 = load i32* %345, align 4, !tbaa !0*/
begin
main_344_346 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %344*/
/* %347 = icmp eq i32 %335, %346*/
begin
main_344_347 = main__lr_ph_i15_i_i_335_reg == main_344_346;
end
end
always @(*) begin
/* main: %348*/
/* %349 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_348_349 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %348*/
/* %350 = add nsw i32 %349, 1*/
begin
main_348_350 = main_348_349 + 32'd1;
end
end
always @(*) begin
/* main: %351*/
/* %352 = add nsw i32 %i_get_dqt.2, 1*/
begin
main_351_352 = main__lr_ph_i15_i_i_i_get_dqt_2_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %351*/
/* %352 = add nsw i32 %i_get_dqt.2, 1*/
if (cur_state == LEGUP_F_main_BB86_266)
begin
main_351_352_reg <= main_351_352;
if (^reset !== 1'bX && ^(main_351_352) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_351_352_reg"); $finish; end
end
end
always @(*) begin
/* main: %351*/
/* %353 = icmp eq i32 %334, 0*/
begin
main_351_353 = main__lr_ph_i15_i_i_334_reg == 32'd0;
end
end
always @(posedge clk) begin
/* main: %351*/
/* %353 = icmp eq i32 %334, 0*/
if (cur_state == LEGUP_F_main_BB86_266)
begin
main_351_353_reg <= main_351_353;
if (^reset !== 1'bX && ^(main_351_353) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_351_353_reg"); $finish; end
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %354 = phi i8* [ %355, %.split.us.i.i.i ], [ %331, %351 ]*/
begin
main__split_us_i_i_i_354 = main__split_us_i_i_i_354_phi_temp;
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %i.01.us.i.i.i = phi i32 [ %360, %.split.us.i.i.i ], [ 0, %351 ]*/
begin
main__split_us_i_i_i_i_01_us_i_i_i = main__split_us_i_i_i_i_01_us_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %scevgep.i16.i.i = getelementptr [64 x i32]* @izigzag_index, i32 0, i32 %i.01.us.i.i.i*/
begin
main__split_us_i_i_i_scevgep_i16_i_i = `TAG_g_izigzag_index_a + 4 * main__split_us_i_i_i_i_01_us_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %scevgep.i16.i.i = getelementptr [64 x i32]* @izigzag_index, i32 0, i32 %i.01.us.i.i.i*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
main__split_us_i_i_i_scevgep_i16_i_i_reg <= main__split_us_i_i_i_scevgep_i16_i_i;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_scevgep_i16_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_scevgep_i16_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %355 = getelementptr inbounds i8* %354, i32 1*/
begin
main__split_us_i_i_i_355 = main__split_us_i_i_i_354 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %355 = getelementptr inbounds i8* %354, i32 1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
main__split_us_i_i_i_355_reg <= main__split_us_i_i_i_355;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_355) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_355_reg"); $finish; end
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %356 = load i8* %354, align 1, !tbaa !1*/
begin
main__split_us_i_i_i_356 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %357 = zext i8 %356 to i32*/
begin
main__split_us_i_i_i_357 = main__split_us_i_i_i_356;
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %357 = zext i8 %356 to i32*/
if (cur_state == LEGUP_F_main_BB87_269)
begin
main__split_us_i_i_i_357_reg <= main__split_us_i_i_i_357;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_357) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_357_reg"); $finish; end
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %358 = load i32* %scevgep.i16.i.i, align 4, !tbaa !0*/
begin
main__split_us_i_i_i_358 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %.sum.us.i.i.i = add i32 %358, 64*/
begin
main__split_us_i_i_i__sum_us_i_i_i = main__split_us_i_i_i_358 + 32'd64;
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %359 = getelementptr inbounds [4 x [64 x i32]]* @p_jinfo_quant_tbl_quantval, i32 0, i32 %335, i32 %.sum.us.i.i.i*/
begin
main__split_us_i_i_i_359 = `TAG_g_p_jinfo_quant_tbl_quantval_a + 256 * main__lr_ph_i15_i_i_335_reg + 4 * main__split_us_i_i_i__sum_us_i_i_i;
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %360 = add nsw i32 %i.01.us.i.i.i, 1*/
begin
main__split_us_i_i_i_360 = main__split_us_i_i_i_i_01_us_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %360 = add nsw i32 %i.01.us.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
main__split_us_i_i_i_360_reg <= main__split_us_i_i_i_360;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_360) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_360_reg"); $finish; end
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %exitcond.i17.i.i = icmp eq i32 %360, 64*/
begin
main__split_us_i_i_i_exitcond_i17_i_i = main__split_us_i_i_i_360 == 32'd64;
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %exitcond.i17.i.i = icmp eq i32 %360, 64*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
main__split_us_i_i_i_exitcond_i17_i_i_reg <= main__split_us_i_i_i_exitcond_i17_i_i;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_exitcond_i17_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_exitcond_i17_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %361 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %331, %351 ]*/
begin
main___split_crit_edge_i_i_i_361 = main___split_crit_edge_i_i_i_361_phi_temp;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %i.01.i.i.i = phi i32 [ %372, %..split_crit_edge.i.i.i ], [ 0, %351 ]*/
begin
main___split_crit_edge_i_i_i_i_01_i_i_i = main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %scevgep4.i18.i.i = getelementptr [64 x i32]* @izigzag_index, i32 0, i32 %i.01.i.i.i*/
begin
main___split_crit_edge_i_i_i_scevgep4_i18_i_i = `TAG_g_izigzag_index_a + 4 * main___split_crit_edge_i_i_i_i_01_i_i_i;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %scevgep4.i18.i.i = getelementptr [64 x i32]* @izigzag_index, i32 0, i32 %i.01.i.i.i*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
main___split_crit_edge_i_i_i_scevgep4_i18_i_i_reg <= main___split_crit_edge_i_i_i_scevgep4_i18_i_i;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_scevgep4_i18_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_scevgep4_i18_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %362 = getelementptr inbounds i8* %361, i32 1*/
begin
main___split_crit_edge_i_i_i_362 = main___split_crit_edge_i_i_i_361 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %362 = getelementptr inbounds i8* %361, i32 1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
main___split_crit_edge_i_i_i_362_reg <= main___split_crit_edge_i_i_i_362;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_362) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_362_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %363 = load i8* %361, align 1, !tbaa !1*/
begin
main___split_crit_edge_i_i_i_363 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %364 = zext i8 %363 to i32*/
begin
main___split_crit_edge_i_i_i_364 = main___split_crit_edge_i_i_i_363;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %365 = shl nuw nsw i32 %364, 8*/
begin
main___split_crit_edge_i_i_i_365 = main___split_crit_edge_i_i_i_364 <<< 32'd8 % 32;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %365 = shl nuw nsw i32 %364, 8*/
if (cur_state == LEGUP_F_main_BB88_273)
begin
main___split_crit_edge_i_i_i_365_reg <= main___split_crit_edge_i_i_i_365;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_365) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_365_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %366 = getelementptr inbounds i8* %361, i32 2*/
begin
main___split_crit_edge_i_i_i_366 = main___split_crit_edge_i_i_i_361 + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %366 = getelementptr inbounds i8* %361, i32 2*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
main___split_crit_edge_i_i_i_366_reg <= main___split_crit_edge_i_i_i_366;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_366) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_366_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %367 = load i8* %362, align 1, !tbaa !1*/
begin
main___split_crit_edge_i_i_i_367 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %368 = zext i8 %367 to i32*/
begin
main___split_crit_edge_i_i_i_368 = main___split_crit_edge_i_i_i_367;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %369 = or i32 %368, %365*/
begin
main___split_crit_edge_i_i_i_369 = main___split_crit_edge_i_i_i_368 | main___split_crit_edge_i_i_i_365_reg;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %369 = or i32 %368, %365*/
if (cur_state == LEGUP_F_main_BB88_274)
begin
main___split_crit_edge_i_i_i_369_reg <= main___split_crit_edge_i_i_i_369;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_369) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_369_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %370 = load i32* %scevgep4.i18.i.i, align 4, !tbaa !0*/
begin
main___split_crit_edge_i_i_i_370 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %.sum.i.i.i = add i32 %370, 64*/
begin
main___split_crit_edge_i_i_i__sum_i_i_i = main___split_crit_edge_i_i_i_370 + 32'd64;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %371 = getelementptr inbounds [4 x [64 x i32]]* @p_jinfo_quant_tbl_quantval, i32 0, i32 %335, i32 %.sum.i.i.i*/
begin
main___split_crit_edge_i_i_i_371 = `TAG_g_p_jinfo_quant_tbl_quantval_a + 256 * main__lr_ph_i15_i_i_335_reg + 4 * main___split_crit_edge_i_i_i__sum_i_i_i;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %372 = add nsw i32 %i.01.i.i.i, 1*/
begin
main___split_crit_edge_i_i_i_372 = main___split_crit_edge_i_i_i_i_01_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %372 = add nsw i32 %i.01.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
main___split_crit_edge_i_i_i_372_reg <= main___split_crit_edge_i_i_i_372;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_372) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_372_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %exitcond3.i.i.i = icmp eq i32 %372, 64*/
begin
main___split_crit_edge_i_i_i_exitcond3_i_i_i = main___split_crit_edge_i_i_i_372 == 32'd64;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %exitcond3.i.i.i = icmp eq i32 %372, 64*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg <= main___split_crit_edge_i_i_i_exitcond3_i_i_i;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_exitcond3_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.us-lcssa.us.i.i.i*/
/* %ReadBuf.8 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %355, %.split.us.i.i.i ]*/
begin
main__us_lcssa_us_i_i_i_ReadBuf_8 = main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp;
end
end
always @(*) begin
/* main: %.us-lcssa.us.i.i.i*/
/* %..v.i.i.i = select i1 %353, i32 -65, i32 -129*/
begin
main__us_lcssa_us_i_i_i___v_i_i_i = (main_351_353_reg ? -32'd65 : -32'd129);
end
end
always @(*) begin
/* main: %.us-lcssa.us.i.i.i*/
/* %..i.i.i = add i32 %..v.i.i.i, %length.02.i.i.i*/
begin
main__us_lcssa_us_i_i_i___i_i_i = main__us_lcssa_us_i_i_i___v_i_i_i + main__lr_ph_i15_i_i_length_02_i_i_i_reg;
end
end
always @(*) begin
/* main: %.us-lcssa.us.i.i.i*/
/* %373 = icmp sgt i32 %..i.i.i, 0*/
begin
main__us_lcssa_us_i_i_i_373 = $signed(main__us_lcssa_us_i_i_i___i_i_i) > $signed(32'd0);
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0 = main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp;
end
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
else /* if (cur_state == LEGUP_F_main_BB90_277) */
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0 = main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg <= main_read_markers_exit_i_p_jinfo_jpeg_data_0;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_p_jinfo_jpeg_data_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg <= main_read_markers_exit_i_p_jinfo_jpeg_data_0;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_p_jinfo_jpeg_data_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg <= main_read_markers_exit_i_p_jinfo_jpeg_data_0;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_p_jinfo_jpeg_data_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
begin
main_read_markers_exit_i_374 = memory_controller_out[15:0];
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_279)
begin
main_read_markers_exit_i_374_reg <= main_read_markers_exit_i_374;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_374) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_374_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %375 = sext i16 %374 to i32*/
begin
main_read_markers_exit_i_375 = $signed(main_read_markers_exit_i_374);
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %376 = add nsw i32 %375, -1*/
begin
main_read_markers_exit_i_376 = main_read_markers_exit_i_375 + -32'd1;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %376 = add nsw i32 %375, -1*/
if (cur_state == LEGUP_F_main_BB90_279)
begin
main_read_markers_exit_i_376_reg <= main_read_markers_exit_i_376;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_376) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_376_reg"); $finish; end
end
end
always @(*) begin
main_read_markers_exit_i_377 = main_signed_divide_32_0;
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %377 = sdiv i32 %376, 8*/
if (cur_state == LEGUP_F_main_BB90_319)
begin
main_read_markers_exit_i_377_reg <= main_read_markers_exit_i_377;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_377_reg"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %377 = sdiv i32 %376, 8*/
if (cur_state == LEGUP_F_main_BB90_319)
begin
main_read_markers_exit_i_377_reg <= main_read_markers_exit_i_377;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_377_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %378 = add nsw i32 %377, 1*/
begin
main_read_markers_exit_i_378 = main_read_markers_exit_i_377_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %378 = add nsw i32 %377, 1*/
if (cur_state == LEGUP_F_main_BB90_327)
begin
main_read_markers_exit_i_378_reg <= main_read_markers_exit_i_378;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_378) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_378_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
begin
main_read_markers_exit_i_379 = memory_controller_out[15:0];
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_280)
begin
main_read_markers_exit_i_379_reg <= main_read_markers_exit_i_379;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_379) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_379_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %380 = sext i16 %379 to i32*/
begin
main_read_markers_exit_i_380 = $signed(main_read_markers_exit_i_379);
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %381 = add nsw i32 %380, -1*/
begin
main_read_markers_exit_i_381 = main_read_markers_exit_i_380 + -32'd1;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %381 = add nsw i32 %380, -1*/
if (cur_state == LEGUP_F_main_BB90_280)
begin
main_read_markers_exit_i_381_reg <= main_read_markers_exit_i_381;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_381) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_381_reg"); $finish; end
end
end
always @(*) begin
main_read_markers_exit_i_382 = main_signed_divide_32_0;
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %382 = sdiv i32 %381, 8*/
if (cur_state == LEGUP_F_main_BB90_320)
begin
main_read_markers_exit_i_382_reg <= main_read_markers_exit_i_382;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_382) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_382_reg"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %382 = sdiv i32 %381, 8*/
if (cur_state == LEGUP_F_main_BB90_320)
begin
main_read_markers_exit_i_382_reg <= main_read_markers_exit_i_382;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_382) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_382_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %383 = add nsw i32 %382, 1*/
begin
main_read_markers_exit_i_383 = main_read_markers_exit_i_382_reg + 32'd1;
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %384 = mul nsw i32 %383, %378*/
begin
main_read_markers_exit_i_384 = main_signed_multiply_32_0;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %384 = mul nsw i32 %383, %378*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
main_read_markers_exit_i_384_reg <= main_read_markers_exit_i_384;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_384) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_384_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
begin
main_read_markers_exit_i_385 = huff_make_dhuff_tb_return_val;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
main_read_markers_exit_i_385_reg <= main_read_markers_exit_i_385;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_385) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_385_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
begin
main_read_markers_exit_i_386 = huff_make_dhuff_tb_return_val;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
main_read_markers_exit_i_386_reg <= main_read_markers_exit_i_386;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_386) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_386_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
begin
main_read_markers_exit_i_387 = huff_make_dhuff_tb_return_val;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
main_read_markers_exit_i_387_reg <= main_read_markers_exit_i_387;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_387) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_387_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
begin
main_read_markers_exit_i_388 = huff_make_dhuff_tb_return_val;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
main_read_markers_exit_i_388_reg <= main_read_markers_exit_i_388;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_388) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_388_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 0, i32 0*/
if (reset) begin main_read_markers_exit_i_scevgep148_i_i = 0; end
begin
main_read_markers_exit_i_scevgep148_i_i = `TAG_main_0_HuffBuff_i_i_a;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 0, i32 0*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_scevgep148_i_i_reg <= main_read_markers_exit_i_scevgep148_i_i;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_scevgep148_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.1.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 1, i32 0*/
if (reset) begin main_read_markers_exit_i_scevgep148_1_i_i = 0; end
begin
main_read_markers_exit_i_scevgep148_1_i_i = `TAG_main_0_HuffBuff_i_i_a + 256 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.1.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 1, i32 0*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_scevgep148_1_i_i_reg <= main_read_markers_exit_i_scevgep148_1_i_i;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_1_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_scevgep148_1_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.2.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 2, i32 0*/
if (reset) begin main_read_markers_exit_i_scevgep148_2_i_i = 0; end
begin
main_read_markers_exit_i_scevgep148_2_i_i = `TAG_main_0_HuffBuff_i_i_a + 256 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.2.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 2, i32 0*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_scevgep148_2_i_i_reg <= main_read_markers_exit_i_scevgep148_2_i_i;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_scevgep148_2_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %389*/
/* %391 = icmp sgt i32 %384, 0*/
begin
main_389_391 = $signed(main_read_markers_exit_i_384_reg) > $signed(32'd0);
end
end
always @(*) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 0, i32 0*/
if (reset) begin main__preheader21_i_i_preheader_scevgep51_i_i = 0; end
begin
main__preheader21_i_i_preheader_scevgep51_i_i = `TAG_main_0_IDCTBuff_i_i_a;
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 0, i32 0*/
if (cur_state == LEGUP_F_main_BB92_356)
begin
main__preheader21_i_i_preheader_scevgep51_i_i_reg <= main__preheader21_i_i_preheader_scevgep51_i_i;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_preheader_scevgep51_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.1.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 0*/
if (reset) begin main__preheader21_i_i_preheader_scevgep51_1_i_i = 0; end
begin
main__preheader21_i_i_preheader_scevgep51_1_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.1.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 0*/
if (cur_state == LEGUP_F_main_BB92_356)
begin
main__preheader21_i_i_preheader_scevgep51_1_i_i_reg <= main__preheader21_i_i_preheader_scevgep51_1_i_i;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_1_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_preheader_scevgep51_1_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.2.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 0*/
if (reset) begin main__preheader21_i_i_preheader_scevgep51_2_i_i = 0; end
begin
main__preheader21_i_i_preheader_scevgep51_2_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.2.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 0*/
if (cur_state == LEGUP_F_main_BB92_356)
begin
main__preheader21_i_i_preheader_scevgep51_2_i_i_reg <= main__preheader21_i_i_preheader_scevgep51_2_i_i;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_preheader_scevgep51_2_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader21.i.i*/
/* %CurrentMCU.026.i.i = phi i32 [ %tmp143.i.i, %447 ], [ 0, %.preheader21.i.i.preheader ]*/
begin
main__preheader21_i_i_CurrentMCU_026_i_i = main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp;
end
end
always @(*) begin
/* main: %.preheader21.i.i*/
/* %tmp143.i.i = add i32 %CurrentMCU.026.i.i, 1*/
begin
main__preheader21_i_i_tmp143_i_i = main__preheader21_i_i_CurrentMCU_026_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* %tmp143.i.i = add i32 %CurrentMCU.026.i.i, 1*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
main__preheader21_i_i_tmp143_i_i_reg <= main__preheader21_i_i_tmp143_i_i;
if (^reset !== 1'bX && ^(main__preheader21_i_i_tmp143_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_tmp143_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_i_01_i_i1_i = main_392_i_01_i_i1_i_phi_temp;
end
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB94_366) */
begin
main_392_i_01_i_i1_i = main_392_i_01_i_i1_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_i_01_i_i1_i_reg <= main_392_i_01_i_i1_i;
if (^reset !== 1'bX && ^(main_392_i_01_i_i1_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_i_01_i_i1_i_reg"); $finish; end
end
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_i_01_i_i1_i_reg <= main_392_i_01_i_i1_i;
if (^reset !== 1'bX && ^(main_392_i_01_i_i1_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_i_01_i_i1_i_reg"); $finish; end
end
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_i_01_i_i1_i_reg <= main_392_i_01_i_i1_i;
if (^reset !== 1'bX && ^(main_392_i_01_i_i1_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_i_01_i_i1_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %scevgep3.i.i2.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 %i.01.i.i1.i*/
begin
main_392_scevgep3_i_i2_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd2 + 4 * main_392_i_01_i_i1_i;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %scevgep3.i.i2.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 %i.01.i.i1.i*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_scevgep3_i_i2_i_reg <= main_392_scevgep3_i_i2_i;
if (^reset !== 1'bX && ^(main_392_scevgep3_i_i2_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_scevgep3_i_i2_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %scevgep2.i.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 %i.01.i.i1.i*/
begin
main_392_scevgep2_i_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd1 + 4 * main_392_i_01_i_i1_i;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %scevgep2.i.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 %i.01.i.i1.i*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_scevgep2_i_i_i_reg <= main_392_scevgep2_i_i_i;
if (^reset !== 1'bX && ^(main_392_scevgep2_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_scevgep2_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %scevgep.i.i3.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 0, i32 %i.01.i.i1.i*/
begin
main_392_scevgep_i_i3_i = `TAG_main_0_IDCTBuff_i_i_a + 4 * main_392_i_01_i_i1_i;
end
end
always @(*) begin
/* main: %392*/
/* %scevgep6.i.i4.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 %i.01.i.i1.i*/
begin
main_392_scevgep6_i_i4_i = `TAG_g_rgb_buf_a + 256 * 32'd2 + 4 * main_392_i_01_i_i1_i;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %scevgep6.i.i4.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 %i.01.i.i1.i*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_scevgep6_i_i4_i_reg <= main_392_scevgep6_i_i4_i;
if (^reset !== 1'bX && ^(main_392_scevgep6_i_i4_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_scevgep6_i_i4_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %scevgep5.i.i5.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 %i.01.i.i1.i*/
begin
main_392_scevgep5_i_i5_i = `TAG_g_rgb_buf_a + 256 * 32'd1 + 4 * main_392_i_01_i_i1_i;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %scevgep5.i.i5.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 %i.01.i.i1.i*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_scevgep5_i_i5_i_reg <= main_392_scevgep5_i_i5_i;
if (^reset !== 1'bX && ^(main_392_scevgep5_i_i5_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_scevgep5_i_i5_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %scevgep4.i.i6.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 %i.01.i.i1.i*/
begin
main_392_scevgep4_i_i6_i = `TAG_g_rgb_buf_a + 4 * main_392_i_01_i_i1_i;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %scevgep4.i.i6.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 %i.01.i.i1.i*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_scevgep4_i_i6_i_reg <= main_392_scevgep4_i_i6_i;
if (^reset !== 1'bX && ^(main_392_scevgep4_i_i6_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_scevgep4_i_i6_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %393 = load i32* %scevgep.i.i3.i, align 4, !tbaa !0*/
begin
main_392_393 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %392*/
/* %394 = load i32* %scevgep2.i.i.i, align 4, !tbaa !0*/
begin
main_392_394 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %392*/
/* %395 = add nsw i32 %394, -128*/
begin
main_392_395 = main_392_394 + -32'd128;
end
end
always @(*) begin
/* main: %392*/
/* %396 = load i32* %scevgep3.i.i2.i, align 4, !tbaa !0*/
begin
main_392_396 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %392*/
/* %397 = add nsw i32 %396, -128*/
begin
main_392_397 = main_392_396 + -32'd128;
end
end
always @(*) begin
/* main: %392*/
/* %398 = shl nsw i32 %393, 8*/
begin
main_392_398 = main_392_393 <<< 32'd8 % 32;
end
end
always @(*) begin
/* main: %392*/
/* %399 = mul nsw i32 %397, 359*/
begin
main_392_399 = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %392*/
/* %400 = or i32 %398, 128*/
begin
main_392_400 = main_392_398 | 32'd128;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %400 = or i32 %398, 128*/
if (cur_state == LEGUP_F_main_BB94_368)
begin
main_392_400_reg <= main_392_400;
if (^reset !== 1'bX && ^(main_392_400) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_400_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %401 = add i32 %399, %400*/
begin
main_392_401 = main_392_399 + main_392_400_reg;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %401 = add i32 %399, %400*/
if (cur_state == LEGUP_F_main_BB94_370)
begin
main_392_401_reg <= main_392_401;
if (^reset !== 1'bX && ^(main_392_401) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_401_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %402 = ashr i32 %401, 8*/
begin
main_392_402 = $signed(main_392_401_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %402 = ashr i32 %401, 8*/
if (cur_state == LEGUP_F_main_BB94_371)
begin
main_392_402_reg <= main_392_402;
if (^reset !== 1'bX && ^(main_392_402) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_402_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %403 = mul i32 %395, -88*/
begin
main_392_403 = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %392*/
/* %404 = mul i32 %397, -182*/
begin
main_392_404 = main_signed_multiply_32_2;
end
end
always @(*) begin
/* main: %392*/
/* %405 = add i32 %403, %400*/
begin
main_392_405 = main_392_403 + main_392_400_reg;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %405 = add i32 %403, %400*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_392_405_reg <= main_392_405;
if (^reset !== 1'bX && ^(main_392_405) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_405_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %406 = add i32 %405, %404*/
begin
main_392_406 = main_392_405_reg + main_392_404;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %406 = add i32 %405, %404*/
if (cur_state == LEGUP_F_main_BB94_370)
begin
main_392_406_reg <= main_392_406;
if (^reset !== 1'bX && ^(main_392_406) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_406_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %407 = ashr i32 %406, 8*/
begin
main_392_407 = $signed(main_392_406_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %407 = ashr i32 %406, 8*/
if (cur_state == LEGUP_F_main_BB94_371)
begin
main_392_407_reg <= main_392_407;
if (^reset !== 1'bX && ^(main_392_407) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_407_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %408 = mul nsw i32 %395, 454*/
begin
main_392_408 = main_signed_multiply_32_2;
end
end
always @(*) begin
/* main: %392*/
/* %409 = add i32 %408, %400*/
begin
main_392_409 = main_392_408 + main_392_400_reg;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %409 = add i32 %408, %400*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_392_409_reg <= main_392_409;
if (^reset !== 1'bX && ^(main_392_409) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_409_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %410 = ashr i32 %409, 8*/
begin
main_392_410 = $signed(main_392_409_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %410 = ashr i32 %409, 8*/
if (cur_state == LEGUP_F_main_BB94_370)
begin
main_392_410_reg <= main_392_410;
if (^reset !== 1'bX && ^(main_392_410) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_410_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %411 = icmp slt i32 %402, 0*/
begin
main_392_411 = $signed(main_392_402) < $signed(32'd0);
end
end
always @(*) begin
/* main: %412*/
/* %413 = icmp sgt i32 %402, 255*/
begin
main_412_413 = $signed(main_392_402_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB97_374)
begin
main_415_r_0_i_i_i = main_415_r_0_i_i_i_phi_temp;
end
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
else /* if (cur_state == LEGUP_F_main_BB97_374) */
begin
main_415_r_0_i_i_i = main_415_r_0_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB97_374)
begin
main_415_r_0_i_i_i_reg <= main_415_r_0_i_i_i;
if (^reset !== 1'bX && ^(main_415_r_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_reg"); $finish; end
end
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB97_374)
begin
main_415_r_0_i_i_i_reg <= main_415_r_0_i_i_i;
if (^reset !== 1'bX && ^(main_415_r_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_reg"); $finish; end
end
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB97_374)
begin
main_415_r_0_i_i_i_reg <= main_415_r_0_i_i_i;
if (^reset !== 1'bX && ^(main_415_r_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %415*/
/* %416 = icmp slt i32 %407, 0*/
begin
main_415_416 = $signed(main_392_407_reg) < $signed(32'd0);
end
end
always @(*) begin
/* main: %417*/
/* %418 = icmp sgt i32 %407, 255*/
begin
main_417_418 = $signed(main_392_407_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB100_377)
begin
main_420_g_0_i_i_i = main_420_g_0_i_i_i_phi_temp;
end
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
else /* if (cur_state == LEGUP_F_main_BB100_377) */
begin
main_420_g_0_i_i_i = main_420_g_0_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB100_377)
begin
main_420_g_0_i_i_i_reg <= main_420_g_0_i_i_i;
if (^reset !== 1'bX && ^(main_420_g_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_reg"); $finish; end
end
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB100_377)
begin
main_420_g_0_i_i_i_reg <= main_420_g_0_i_i_i;
if (^reset !== 1'bX && ^(main_420_g_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_reg"); $finish; end
end
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB100_377)
begin
main_420_g_0_i_i_i_reg <= main_420_g_0_i_i_i;
if (^reset !== 1'bX && ^(main_420_g_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %420*/
/* %421 = icmp slt i32 %410, 0*/
begin
main_420_421 = $signed(main_392_410_reg) < $signed(32'd0);
end
end
always @(*) begin
/* main: %422*/
/* %423 = icmp sgt i32 %410, 255*/
begin
main_422_423 = $signed(main_392_410_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_b_0_i_i_i = main_425_b_0_i_i_i_phi_temp;
end
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
else /* if (cur_state == LEGUP_F_main_BB103_380) */
begin
main_425_b_0_i_i_i = main_425_b_0_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_b_0_i_i_i_reg <= main_425_b_0_i_i_i;
if (^reset !== 1'bX && ^(main_425_b_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_reg"); $finish; end
end
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_b_0_i_i_i_reg <= main_425_b_0_i_i_i;
if (^reset !== 1'bX && ^(main_425_b_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_reg"); $finish; end
end
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_b_0_i_i_i_reg <= main_425_b_0_i_i_i;
if (^reset !== 1'bX && ^(main_425_b_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %425*/
/* %426 = add nsw i32 %i.01.i.i1.i, 1*/
begin
main_425_426 = main_392_i_01_i_i1_i_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %425*/
/* %426 = add nsw i32 %i.01.i.i1.i, 1*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_426_reg <= main_425_426;
if (^reset !== 1'bX && ^(main_425_426) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_426_reg"); $finish; end
end
end
always @(*) begin
/* main: %425*/
/* %exitcond53.i.i = icmp eq i32 %426, 64*/
begin
main_425_exitcond53_i_i = main_425_426 == 32'd64;
end
end
always @(posedge clk) begin
/* main: %425*/
/* %exitcond53.i.i = icmp eq i32 %426, 64*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_exitcond53_i_i_reg <= main_425_exitcond53_i_i;
if (^reset !== 1'bX && ^(main_425_exitcond53_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_exitcond53_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %427 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
begin
main_YuvToRgb_exit_loopexit_i_i_427 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %428 = sext i16 %427 to i32*/
begin
main_YuvToRgb_exit_loopexit_i_i_428 = $signed(main_YuvToRgb_exit_loopexit_i_i_427);
end
end
always @(posedge clk) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %428 = sext i16 %427 to i32*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
main_YuvToRgb_exit_loopexit_i_i_428_reg <= main_YuvToRgb_exit_loopexit_i_i_428;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i_428) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_YuvToRgb_exit_loopexit_i_i_428_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %429 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
begin
main_YuvToRgb_exit_loopexit_i_i_429 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %430 = sext i16 %429 to i32*/
begin
main_YuvToRgb_exit_loopexit_i_i_430 = $signed(main_YuvToRgb_exit_loopexit_i_i_429);
end
end
always @(posedge clk) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %430 = sext i16 %429 to i32*/
if (cur_state == LEGUP_F_main_BB104_386)
begin
main_YuvToRgb_exit_loopexit_i_i_430_reg <= main_YuvToRgb_exit_loopexit_i_i_430;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i_430) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_YuvToRgb_exit_loopexit_i_i_430_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %tmp120.i.i = shl nsw i32 %428, 3*/
begin
main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i = main_YuvToRgb_exit_loopexit_i_i_428 <<< 32'd3 % 32;
end
end
always @(posedge clk) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %tmp120.i.i = shl nsw i32 %428, 3*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i_reg <= main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
begin
main_YuvToRgb_exit_loopexit_i_i__pre_i_i = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_387)
begin
main_YuvToRgb_exit_loopexit_i_i__pre_i_i_reg <= main_YuvToRgb_exit_loopexit_i_i__pre_i_i;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i__pre_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_YuvToRgb_exit_loopexit_i_i__pre_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
begin
main_YuvToRgb_exit_loopexit_i_i_431 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_388)
begin
main_YuvToRgb_exit_loopexit_i_i_431_reg <= main_YuvToRgb_exit_loopexit_i_i_431;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i_431) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_YuvToRgb_exit_loopexit_i_i_431_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %433 = phi i32 [ %.pre.i.i, %YuvToRgb.exit.loopexit.i.i ], [ %446, %WriteBlock.exit.i.i ]*/
begin
main_432_433 = main_432_433_phi_temp;
end
end
always @(*) begin
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i = main_432_i_324_i_i_phi_temp;
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
else if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i = main_432_i_324_i_i_phi_temp;
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB105_389) */
begin
main_432_i_324_i_i = main_432_i_324_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i_reg <= main_432_i_324_i_i;
if (^reset !== 1'bX && ^(main_432_i_324_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_reg"); $finish; end
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i_reg <= main_432_i_324_i_i;
if (^reset !== 1'bX && ^(main_432_i_324_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_reg"); $finish; end
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i_reg <= main_432_i_324_i_i;
if (^reset !== 1'bX && ^(main_432_i_324_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_reg"); $finish; end
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i_reg <= main_432_i_324_i_i;
if (^reset !== 1'bX && ^(main_432_i_324_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %scevgep139.i.i = getelementptr [3 x i32]* @OutData_comp_vpos, i32 0, i32 %i.324.i.i*/
begin
main_432_scevgep139_i_i = `TAG_g_OutData_comp_vpos_a + 4 * main_432_i_324_i_i;
end
end
always @(*) begin
/* main: %432*/
/* %tmp141.i.i = add i32 %i.324.i.i, 1*/
begin
main_432_tmp141_i_i = main_432_i_324_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %432*/
/* %tmp141.i.i = add i32 %i.324.i.i, 1*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_tmp141_i_i_reg <= main_432_tmp141_i_i;
if (^reset !== 1'bX && ^(main_432_tmp141_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_tmp141_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %scevgep142.i.i = getelementptr [3 x i32]* @OutData_comp_hpos, i32 0, i32 %tmp141.i.i*/
begin
main_432_scevgep142_i_i = `TAG_g_OutData_comp_hpos_a + 4 * main_432_tmp141_i_i;
end
end
always @(posedge clk) begin
/* main: %432*/
/* %scevgep142.i.i = getelementptr [3 x i32]* @OutData_comp_hpos, i32 0, i32 %tmp141.i.i*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_scevgep142_i_i_reg <= main_432_scevgep142_i_i;
if (^reset !== 1'bX && ^(main_432_scevgep142_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_scevgep142_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
begin
main_432_434 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB105_391)
begin
main_432_434_reg <= main_432_434;
if (^reset !== 1'bX && ^(main_432_434) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_434_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %435 = shl nsw i32 %434, 3*/
begin
main_432_435 = main_432_434 <<< 32'd3 % 32;
end
end
always @(posedge clk) begin
/* main: %432*/
/* %435 = shl nsw i32 %434, 3*/
if (cur_state == LEGUP_F_main_BB105_391)
begin
main_432_435_reg <= main_432_435;
if (^reset !== 1'bX && ^(main_432_435) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_435_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %436 = shl nsw i32 %433, 3*/
begin
main_432_436 = main_432_433 <<< 32'd3 % 32;
end
end
always @(posedge clk) begin
/* main: %432*/
/* %436 = shl nsw i32 %433, 3*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_436_reg <= main_432_436;
if (^reset !== 1'bX && ^(main_432_436) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_436_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %437 = icmp slt i32 %435, %430*/
begin
main_432_437 = $signed(main_432_435) < $signed(main_YuvToRgb_exit_loopexit_i_i_430_reg);
end
end
always @(*) begin
/* main: %432*/
/* %438 = icmp slt i32 %436, %428*/
begin
main_432_438 = $signed(main_432_436) < $signed(main_YuvToRgb_exit_loopexit_i_i_428_reg);
end
end
always @(posedge clk) begin
/* main: %432*/
/* %438 = icmp slt i32 %436, %428*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_438_reg <= main_432_438;
if (^reset !== 1'bX && ^(main_432_438) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_438_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %or.cond.i.i.i.i = and i1 %437, %438*/
begin
main_432_or_cond_i_i_i_i = main_432_437 & main_432_438_reg;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp61.i.i = add i32 %436, 8*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp61_i_i = main_432_436_reg + 32'd8;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp62149.i.i = or i32 %436, 1*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp62149_i_i = main_432_436_reg | 32'd1;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp63.i.i = icmp sgt i32 %tmp61.i.i, %tmp62149.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp63_i_i = $signed(main__lr_ph8_split_us_i_i_i_i_tmp61_i_i) > $signed(main__lr_ph8_split_us_i_i_i_i_tmp62149_i_i);
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %smax.i.i = select i1 %tmp63.i.i, i32 %tmp61.i.i, i32 %tmp62149.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_smax_i_i = (main__lr_ph8_split_us_i_i_i_i_tmp63_i_i ? main__lr_ph8_split_us_i_i_i_i_tmp61_i_i : main__lr_ph8_split_us_i_i_i_i_tmp62149_i_i);
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %smax.i.i = select i1 %tmp63.i.i, i32 %tmp61.i.i, i32 %tmp62149.i.i*/
if (cur_state == LEGUP_F_main_BB106_392)
begin
main__lr_ph8_split_us_i_i_i_i_smax_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_smax_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_smax_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_smax_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp64.i.i = sub i32 %436, %smax.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp64_i_i = main_432_436_reg - main__lr_ph8_split_us_i_i_i_i_smax_i_i_reg;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp67.i.i = sub i32 %436, %428*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp67_i_i = main_432_436_reg - main_YuvToRgb_exit_loopexit_i_i_428_reg;
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp67.i.i = sub i32 %436, %428*/
if (cur_state == LEGUP_F_main_BB106_392)
begin
main__lr_ph8_split_us_i_i_i_i_tmp67_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_tmp67_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_tmp67_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_tmp67_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp68.i.i = icmp ugt i32 %tmp64.i.i, %tmp67.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp68_i_i = main__lr_ph8_split_us_i_i_i_i_tmp64_i_i > main__lr_ph8_split_us_i_i_i_i_tmp67_i_i_reg;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %umax.i.i = select i1 %tmp68.i.i, i32 %tmp64.i.i, i32 %tmp67.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_umax_i_i = (main__lr_ph8_split_us_i_i_i_i_tmp68_i_i ? main__lr_ph8_split_us_i_i_i_i_tmp64_i_i : main__lr_ph8_split_us_i_i_i_i_tmp67_i_i_reg);
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %umax.i.i = select i1 %tmp68.i.i, i32 %tmp64.i.i, i32 %tmp67.i.i*/
if (cur_state == LEGUP_F_main_BB106_393)
begin
main__lr_ph8_split_us_i_i_i_i_umax_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_umax_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_umax_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_umax_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp69.i.i = sub i32 0, %umax.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp69_i_i = 32'd0 - main__lr_ph8_split_us_i_i_i_i_umax_i_i_reg;
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp69.i.i = sub i32 0, %umax.i.i*/
if (cur_state == LEGUP_F_main_BB106_394)
begin
main__lr_ph8_split_us_i_i_i_i_tmp69_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_tmp69_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_tmp69_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_tmp69_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp82.i.i = add i32 %435, 8*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp82_i_i = main_432_435_reg + 32'd8;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp83150.i.i = or i32 %435, 1*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp83150_i_i = main_432_435_reg | 32'd1;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp84.i.i = icmp sgt i32 %tmp82.i.i, %tmp83150.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp84_i_i = $signed(main__lr_ph8_split_us_i_i_i_i_tmp82_i_i) > $signed(main__lr_ph8_split_us_i_i_i_i_tmp83150_i_i);
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %smax85.i.i = select i1 %tmp84.i.i, i32 %tmp82.i.i, i32 %tmp83150.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_smax85_i_i = (main__lr_ph8_split_us_i_i_i_i_tmp84_i_i ? main__lr_ph8_split_us_i_i_i_i_tmp82_i_i : main__lr_ph8_split_us_i_i_i_i_tmp83150_i_i);
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %smax85.i.i = select i1 %tmp84.i.i, i32 %tmp82.i.i, i32 %tmp83150.i.i*/
if (cur_state == LEGUP_F_main_BB106_392)
begin
main__lr_ph8_split_us_i_i_i_i_smax85_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_smax85_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_smax85_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_smax85_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp86.i.i = sub i32 %435, %smax85.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp86_i_i = main_432_435_reg - main__lr_ph8_split_us_i_i_i_i_smax85_i_i_reg;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp89.i.i = sub i32 %435, %430*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp89_i_i = main_432_435_reg - main_YuvToRgb_exit_loopexit_i_i_430_reg;
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp89.i.i = sub i32 %435, %430*/
if (cur_state == LEGUP_F_main_BB106_392)
begin
main__lr_ph8_split_us_i_i_i_i_tmp89_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_tmp89_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_tmp89_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_tmp89_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp90.i.i = icmp ugt i32 %tmp86.i.i, %tmp89.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp90_i_i = main__lr_ph8_split_us_i_i_i_i_tmp86_i_i > main__lr_ph8_split_us_i_i_i_i_tmp89_i_i_reg;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %umax91.i.i = select i1 %tmp90.i.i, i32 %tmp86.i.i, i32 %tmp89.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_umax91_i_i = (main__lr_ph8_split_us_i_i_i_i_tmp90_i_i ? main__lr_ph8_split_us_i_i_i_i_tmp86_i_i : main__lr_ph8_split_us_i_i_i_i_tmp89_i_i_reg);
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %umax91.i.i = select i1 %tmp90.i.i, i32 %tmp86.i.i, i32 %tmp89.i.i*/
if (cur_state == LEGUP_F_main_BB106_393)
begin
main__lr_ph8_split_us_i_i_i_i_umax91_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_umax91_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_umax91_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_umax91_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp92.i.i = sub i32 0, %umax91.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp92_i_i = 32'd0 - main__lr_ph8_split_us_i_i_i_i_umax91_i_i_reg;
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp92.i.i = sub i32 0, %umax91.i.i*/
if (cur_state == LEGUP_F_main_BB106_394)
begin
main__lr_ph8_split_us_i_i_i_i_tmp92_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_tmp92_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_tmp92_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_tmp92_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp121.i.i = mul i32 %tmp120.i.i, %434*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp121_i_i = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp122.i.i = add i32 %436, %tmp121.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp122_i_i = main_432_436_reg + main__lr_ph8_split_us_i_i_i_i_tmp121_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp122.i.i = add i32 %436, %tmp121.i.i*/
if (cur_state == LEGUP_F_main_BB106_392)
begin
main__lr_ph8_split_us_i_i_i_i_tmp122_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_tmp122_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_tmp122_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_tmp122_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %439*/
/* %indvar.next18.i.i.i.i = add i32 %indvar17.i.i.i.i, 1*/
begin
main_439_indvar_next18_i_i_i_i = main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg + 32'd1;
end
end
always @(*) begin
/* main: %439*/
/* %exitcond93.i.i = icmp eq i32 %indvar.next18.i.i.i.i, %tmp92.i.i*/
begin
main_439_exitcond93_i_i = main_439_indvar_next18_i_i_i_i == main__lr_ph8_split_us_i_i_i_i_tmp92_i_i_reg;
end
end
always @(*) begin
/* main: %440*/
/* %indvar.i.i.i.i = phi i32 [ 0, %.lr.ph.us.i.i.i.i ], [ %indvar.next.i.i.i.i, %440 ]*/
begin
main_440_indvar_i_i_i_i = main_440_indvar_i_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %440*/
/* %tmp124.i.i = add i32 %tmp123.i.i, %indvar.i.i.i.i*/
begin
main_440_tmp124_i_i = main__lr_ph_us_i_i_i_i_tmp123_i_i_reg + main_440_indvar_i_i_i_i;
end
end
always @(*) begin
/* main: %440*/
/* %scevgep24.i.i.i.i = getelementptr [3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 %i.324.i.i, i32 %tmp124.i.i*/
begin
main_440_scevgep24_i_i_i_i = `TAG_g_OutData_comp_buf_a + 5310 * main_432_i_324_i_i_reg + 1 * main_440_tmp124_i_i;
end
end
always @(posedge clk) begin
/* main: %440*/
/* %scevgep24.i.i.i.i = getelementptr [3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 %i.324.i.i, i32 %tmp124.i.i*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
main_440_scevgep24_i_i_i_i_reg <= main_440_scevgep24_i_i_i_i;
if (^reset !== 1'bX && ^(main_440_scevgep24_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_440_scevgep24_i_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %440*/
/* %tmp137.i.i = add i32 %tmp136.i.i, %indvar.i.i.i.i*/
begin
main_440_tmp137_i_i = main__lr_ph_us_i_i_i_i_tmp136_i_i_reg + main_440_indvar_i_i_i_i;
end
end
always @(*) begin
/* main: %440*/
/* %.14.us.i.i.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 %i.324.i.i, i32 %tmp137.i.i*/
begin
main_440__14_us_i_i_i_i = `TAG_g_rgb_buf_a + 256 * main_432_i_324_i_i_reg + 4 * main_440_tmp137_i_i;
end
end
always @(*) begin
/* main: %440*/
/* %441 = load i32* %.14.us.i.i.i.i, align 4, !tbaa !0*/
begin
main_440_441 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %440*/
/* %442 = trunc i32 %441 to i8*/
begin
main_440_442 = main_440_441[7:0];
end
end
always @(*) begin
/* main: %440*/
/* %indvar.next.i.i.i.i = add i32 %indvar.i.i.i.i, 1*/
begin
main_440_indvar_next_i_i_i_i = main_440_indvar_i_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %440*/
/* %indvar.next.i.i.i.i = add i32 %indvar.i.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
main_440_indvar_next_i_i_i_i_reg <= main_440_indvar_next_i_i_i_i;
if (^reset !== 1'bX && ^(main_440_indvar_next_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_440_indvar_next_i_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %440*/
/* %exitcond70.i.i = icmp eq i32 %indvar.next.i.i.i.i, %tmp69.i.i*/
begin
main_440_exitcond70_i_i = main_440_indvar_next_i_i_i_i == main__lr_ph8_split_us_i_i_i_i_tmp69_i_i_reg;
end
end
always @(posedge clk) begin
/* main: %440*/
/* %exitcond70.i.i = icmp eq i32 %indvar.next.i.i.i.i, %tmp69.i.i*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
main_440_exitcond70_i_i_reg <= main_440_exitcond70_i_i;
if (^reset !== 1'bX && ^(main_440_exitcond70_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_440_exitcond70_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i = main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp;
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB109_399) */
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i = main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg <= main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg <= main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg <= main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp118.i.i = mul i32 %428, %indvar17.i.i.i.i*/
begin
main__lr_ph_us_i_i_i_i_tmp118_i_i = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp123.i.i = add i32 %tmp122.i.i, %tmp118.i.i*/
begin
main__lr_ph_us_i_i_i_i_tmp123_i_i = main__lr_ph8_split_us_i_i_i_i_tmp122_i_i_reg + main__lr_ph_us_i_i_i_i_tmp118_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp123.i.i = add i32 %tmp122.i.i, %tmp118.i.i*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_tmp123_i_i_reg <= main__lr_ph_us_i_i_i_i_tmp123_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_us_i_i_i_i_tmp123_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_tmp123_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp136.i.i = mul i32 %indvar17.i.i.i.i, %tmp69.i.i*/
begin
main__lr_ph_us_i_i_i_i_tmp136_i_i = main_signed_multiply_32_0;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp136.i.i = mul i32 %indvar17.i.i.i.i, %tmp69.i.i*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_tmp136_i_i_reg <= main__lr_ph_us_i_i_i_i_tmp136_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_us_i_i_i_i_tmp136_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_tmp136_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %WriteOneBlock.exit.i.i.i*/
/* %443 = load i32* %scevgep142.i.i, align 4, !tbaa !0*/
begin
main_WriteOneBlock_exit_i_i_i_443 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %WriteOneBlock.exit.i.i.i*/
/* %444 = icmp slt i32 %443, %431*/
begin
main_WriteOneBlock_exit_i_i_i_444 = $signed(main_WriteOneBlock_exit_i_i_i_443) < $signed(main_YuvToRgb_exit_loopexit_i_i_431_reg);
end
end
always @(*) begin
/* main: %WriteBlock.exit.i.i*/
/* %446 = phi i32 [ %443, %WriteOneBlock.exit.i.i.i ], [ 0, %445 ]*/
begin
main_WriteBlock_exit_i_i_446 = main_WriteBlock_exit_i_i_446_phi_temp;
end
end
always @(*) begin
/* main: %WriteBlock.exit.i.i*/
/* %exitcond116.i.i = icmp eq i32 %tmp141.i.i, 3*/
begin
main_WriteBlock_exit_i_i_exitcond116_i_i = main_432_tmp141_i_i_reg == 32'd3;
end
end
always @(*) begin
/* main: %447*/
/* %448 = icmp slt i32 %tmp143.i.i, %384*/
begin
main_447_448 = $signed(main__preheader21_i_i_tmp143_i_i_reg) < $signed(main_read_markers_exit_i_384_reg);
end
end
always @(*) begin
/* main: %449*/
/* %451 = icmp sgt i32 %384, 0*/
begin
main_449_451 = $signed(main_read_markers_exit_i_384_reg) > $signed(32'd0);
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %452 = getelementptr inbounds [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 4, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_452 = 0; end
begin
main__preheader_lr_ph_i_i_452 = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd4;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %452 = getelementptr inbounds [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 4, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_452_reg <= main__preheader_lr_ph_i_i_452;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_452) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_452_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %453 = getelementptr inbounds [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 5, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_453 = 0; end
begin
main__preheader_lr_ph_i_i_453 = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd5;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %453 = getelementptr inbounds [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 5, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_453_reg <= main__preheader_lr_ph_i_i_453;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_453) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_453_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.i8.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 0, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_scevgep_i8_i = 0; end
begin
main__preheader_lr_ph_i_i_scevgep_i8_i = `TAG_main_0_IDCTBuff_i_i_a;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.i8.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 0, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_scevgep_i8_i_reg <= main__preheader_lr_ph_i_i_scevgep_i8_i;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_i8_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_scevgep_i8_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.1.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_scevgep_1_i_i = 0; end
begin
main__preheader_lr_ph_i_i_scevgep_1_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.1.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_scevgep_1_i_i_reg <= main__preheader_lr_ph_i_i_scevgep_1_i_i;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_1_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_scevgep_1_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.2.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_scevgep_2_i_i = 0; end
begin
main__preheader_lr_ph_i_i_scevgep_2_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.2.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_scevgep_2_i_i_reg <= main__preheader_lr_ph_i_i_scevgep_2_i_i;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_scevgep_2_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.3.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 3, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_scevgep_3_i_i = 0; end
begin
main__preheader_lr_ph_i_i_scevgep_3_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd3;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.3.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 3, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_scevgep_3_i_i_reg <= main__preheader_lr_ph_i_i_scevgep_3_i_i;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_3_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_scevgep_3_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
main__preheader_i_i_indvar_i7_i = main__preheader_i_i_indvar_i7_i_phi_temp;
end
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB116_408) */
begin
main__preheader_i_i_indvar_i7_i = main__preheader_i_i_indvar_i7_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
main__preheader_i_i_indvar_i7_i_reg <= main__preheader_i_i_indvar_i7_i;
if (^reset !== 1'bX && ^(main__preheader_i_i_indvar_i7_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_indvar_i7_i_reg"); $finish; end
end
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
main__preheader_i_i_indvar_i7_i_reg <= main__preheader_i_i_indvar_i7_i;
if (^reset !== 1'bX && ^(main__preheader_i_i_indvar_i7_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_indvar_i7_i_reg"); $finish; end
end
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
main__preheader_i_i_indvar_i7_i_reg <= main__preheader_i_i_indvar_i7_i;
if (^reset !== 1'bX && ^(main__preheader_i_i_indvar_i7_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_indvar_i7_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.i.i*/
/* %tmp48.i.i = shl i32 %indvar.i7.i, 2*/
begin
main__preheader_i_i_tmp48_i_i = main__preheader_i_i_indvar_i7_i <<< 32'd2 % 32;
end
end
always @(*) begin
/* main: %.preheader.i.i*/
/* %tmp49.i.i = add i32 %tmp48.i.i, 4*/
begin
main__preheader_i_i_tmp49_i_i = main__preheader_i_i_tmp48_i_i + 32'd4;
end
end
always @(posedge clk) begin
/* main: %.preheader.i.i*/
/* %tmp49.i.i = add i32 %tmp48.i.i, 4*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
main__preheader_i_i_tmp49_i_i_reg <= main__preheader_i_i_tmp49_i_i;
if (^reset !== 1'bX && ^(main__preheader_i_i_tmp49_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_tmp49_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB117_426) */
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_i_01_i2_i_i = main_454_i_01_i2_i_i_phi_temp;
end
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB118_427) */
begin
main_454_i_01_i2_i_i = main_454_i_01_i2_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_i_01_i2_i_i_reg <= main_454_i_01_i2_i_i;
if (^reset !== 1'bX && ^(main_454_i_01_i2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_i_01_i2_i_i_reg"); $finish; end
end
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_i_01_i2_i_i_reg <= main_454_i_01_i2_i_i;
if (^reset !== 1'bX && ^(main_454_i_01_i2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_i_01_i2_i_i_reg"); $finish; end
end
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_i_01_i2_i_i_reg <= main_454_i_01_i2_i_i;
if (^reset !== 1'bX && ^(main_454_i_01_i2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_i_01_i2_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %scevgep4.i6.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 0, i32 %i.01.i2.i.i*/
begin
main_454_scevgep4_i6_i_i = `TAG_g_rgb_buf_a + 768 * main__preheader16_i_i_i_517_i_i_reg + 4 * main_454_i_01_i2_i_i;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %scevgep4.i6.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 0, i32 %i.01.i2.i.i*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_scevgep4_i6_i_i_reg <= main_454_scevgep4_i6_i_i;
if (^reset !== 1'bX && ^(main_454_scevgep4_i6_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_scevgep4_i6_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %scevgep5.i7.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 1, i32 %i.01.i2.i.i*/
begin
main_454_scevgep5_i7_i_i = `TAG_g_rgb_buf_a + 768 * main__preheader16_i_i_i_517_i_i_reg + 256 * 32'd1 + 4 * main_454_i_01_i2_i_i;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %scevgep5.i7.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 1, i32 %i.01.i2.i.i*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_scevgep5_i7_i_i_reg <= main_454_scevgep5_i7_i_i;
if (^reset !== 1'bX && ^(main_454_scevgep5_i7_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_scevgep5_i7_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %scevgep6.i8.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 2, i32 %i.01.i2.i.i*/
begin
main_454_scevgep6_i8_i_i = `TAG_g_rgb_buf_a + 768 * main__preheader16_i_i_i_517_i_i_reg + 256 * 32'd2 + 4 * main_454_i_01_i2_i_i;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %scevgep6.i8.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 2, i32 %i.01.i2.i.i*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_scevgep6_i8_i_i_reg <= main_454_scevgep6_i8_i_i;
if (^reset !== 1'bX && ^(main_454_scevgep6_i8_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_scevgep6_i8_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %scevgep.i3.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 %i.517.i.i, i32 %i.01.i2.i.i*/
begin
main_454_scevgep_i3_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * main__preheader16_i_i_i_517_i_i_reg + 4 * main_454_i_01_i2_i_i;
end
end
always @(*) begin
/* main: %454*/
/* %scevgep3.i5.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 5, i32 %i.01.i2.i.i*/
begin
main_454_scevgep3_i5_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd5 + 4 * main_454_i_01_i2_i_i;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %scevgep3.i5.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 5, i32 %i.01.i2.i.i*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_scevgep3_i5_i_i_reg <= main_454_scevgep3_i5_i_i;
if (^reset !== 1'bX && ^(main_454_scevgep3_i5_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_scevgep3_i5_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %scevgep2.i4.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 4, i32 %i.01.i2.i.i*/
begin
main_454_scevgep2_i4_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd4 + 4 * main_454_i_01_i2_i_i;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %scevgep2.i4.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 4, i32 %i.01.i2.i.i*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_scevgep2_i4_i_i_reg <= main_454_scevgep2_i4_i_i;
if (^reset !== 1'bX && ^(main_454_scevgep2_i4_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_scevgep2_i4_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %455 = load i32* %scevgep.i3.i.i, align 4, !tbaa !0*/
begin
main_454_455 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %454*/
/* %456 = load i32* %scevgep2.i4.i.i, align 4, !tbaa !0*/
begin
main_454_456 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %454*/
/* %457 = add nsw i32 %456, -128*/
begin
main_454_457 = main_454_456 + -32'd128;
end
end
always @(*) begin
/* main: %454*/
/* %458 = load i32* %scevgep3.i5.i.i, align 4, !tbaa !0*/
begin
main_454_458 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %454*/
/* %459 = add nsw i32 %458, -128*/
begin
main_454_459 = main_454_458 + -32'd128;
end
end
always @(*) begin
/* main: %454*/
/* %460 = shl nsw i32 %455, 8*/
begin
main_454_460 = main_454_455 <<< 32'd8 % 32;
end
end
always @(*) begin
/* main: %454*/
/* %461 = mul nsw i32 %459, 359*/
begin
main_454_461 = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %454*/
/* %462 = or i32 %460, 128*/
begin
main_454_462 = main_454_460 | 32'd128;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %462 = or i32 %460, 128*/
if (cur_state == LEGUP_F_main_BB118_429)
begin
main_454_462_reg <= main_454_462;
if (^reset !== 1'bX && ^(main_454_462) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_462_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %463 = add i32 %461, %462*/
begin
main_454_463 = main_454_461 + main_454_462_reg;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %463 = add i32 %461, %462*/
if (cur_state == LEGUP_F_main_BB118_431)
begin
main_454_463_reg <= main_454_463;
if (^reset !== 1'bX && ^(main_454_463) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_463_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %464 = ashr i32 %463, 8*/
begin
main_454_464 = $signed(main_454_463_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %464 = ashr i32 %463, 8*/
if (cur_state == LEGUP_F_main_BB118_432)
begin
main_454_464_reg <= main_454_464;
if (^reset !== 1'bX && ^(main_454_464) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_464_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %465 = mul i32 %457, -88*/
begin
main_454_465 = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %454*/
/* %466 = mul i32 %459, -182*/
begin
main_454_466 = main_signed_multiply_32_2;
end
end
always @(*) begin
/* main: %454*/
/* %467 = add i32 %465, %462*/
begin
main_454_467 = main_454_465 + main_454_462_reg;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %467 = add i32 %465, %462*/
if (cur_state == LEGUP_F_main_BB118_430)
begin
main_454_467_reg <= main_454_467;
if (^reset !== 1'bX && ^(main_454_467) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_467_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %468 = add i32 %467, %466*/
begin
main_454_468 = main_454_467_reg + main_454_466;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %468 = add i32 %467, %466*/
if (cur_state == LEGUP_F_main_BB118_431)
begin
main_454_468_reg <= main_454_468;
if (^reset !== 1'bX && ^(main_454_468) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_468_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %469 = ashr i32 %468, 8*/
begin
main_454_469 = $signed(main_454_468_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %469 = ashr i32 %468, 8*/
if (cur_state == LEGUP_F_main_BB118_432)
begin
main_454_469_reg <= main_454_469;
if (^reset !== 1'bX && ^(main_454_469) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_469_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %470 = mul nsw i32 %457, 454*/
begin
main_454_470 = main_signed_multiply_32_2;
end
end
always @(*) begin
/* main: %454*/
/* %471 = add i32 %470, %462*/
begin
main_454_471 = main_454_470 + main_454_462_reg;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %471 = add i32 %470, %462*/
if (cur_state == LEGUP_F_main_BB118_430)
begin
main_454_471_reg <= main_454_471;
if (^reset !== 1'bX && ^(main_454_471) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_471_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %472 = ashr i32 %471, 8*/
begin
main_454_472 = $signed(main_454_471_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %472 = ashr i32 %471, 8*/
if (cur_state == LEGUP_F_main_BB118_431)
begin
main_454_472_reg <= main_454_472;
if (^reset !== 1'bX && ^(main_454_472) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_472_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %473 = icmp slt i32 %464, 0*/
begin
main_454_473 = $signed(main_454_464) < $signed(32'd0);
end
end
always @(*) begin
/* main: %474*/
/* %475 = icmp sgt i32 %464, 255*/
begin
main_474_475 = $signed(main_454_464_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB121_435)
begin
main_477_r_0_i9_i_i = main_477_r_0_i9_i_i_phi_temp;
end
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
else /* if (cur_state == LEGUP_F_main_BB121_435) */
begin
main_477_r_0_i9_i_i = main_477_r_0_i9_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB121_435)
begin
main_477_r_0_i9_i_i_reg <= main_477_r_0_i9_i_i;
if (^reset !== 1'bX && ^(main_477_r_0_i9_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_reg"); $finish; end
end
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB121_435)
begin
main_477_r_0_i9_i_i_reg <= main_477_r_0_i9_i_i;
if (^reset !== 1'bX && ^(main_477_r_0_i9_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_reg"); $finish; end
end
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB121_435)
begin
main_477_r_0_i9_i_i_reg <= main_477_r_0_i9_i_i;
if (^reset !== 1'bX && ^(main_477_r_0_i9_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %477*/
/* %478 = icmp slt i32 %469, 0*/
begin
main_477_478 = $signed(main_454_469_reg) < $signed(32'd0);
end
end
always @(*) begin
/* main: %479*/
/* %480 = icmp sgt i32 %469, 255*/
begin
main_479_480 = $signed(main_454_469_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB124_438)
begin
main_482_g_0_i10_i_i = main_482_g_0_i10_i_i_phi_temp;
end
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
else /* if (cur_state == LEGUP_F_main_BB124_438) */
begin
main_482_g_0_i10_i_i = main_482_g_0_i10_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB124_438)
begin
main_482_g_0_i10_i_i_reg <= main_482_g_0_i10_i_i;
if (^reset !== 1'bX && ^(main_482_g_0_i10_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_reg"); $finish; end
end
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB124_438)
begin
main_482_g_0_i10_i_i_reg <= main_482_g_0_i10_i_i;
if (^reset !== 1'bX && ^(main_482_g_0_i10_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_reg"); $finish; end
end
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB124_438)
begin
main_482_g_0_i10_i_i_reg <= main_482_g_0_i10_i_i;
if (^reset !== 1'bX && ^(main_482_g_0_i10_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %482*/
/* %483 = icmp slt i32 %472, 0*/
begin
main_482_483 = $signed(main_454_472_reg) < $signed(32'd0);
end
end
always @(*) begin
/* main: %484*/
/* %485 = icmp sgt i32 %472, 255*/
begin
main_484_485 = $signed(main_454_472_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_b_0_i11_i_i = main_487_b_0_i11_i_i_phi_temp;
end
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
else /* if (cur_state == LEGUP_F_main_BB127_441) */
begin
main_487_b_0_i11_i_i = main_487_b_0_i11_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_b_0_i11_i_i_reg <= main_487_b_0_i11_i_i;
if (^reset !== 1'bX && ^(main_487_b_0_i11_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_reg"); $finish; end
end
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_b_0_i11_i_i_reg <= main_487_b_0_i11_i_i;
if (^reset !== 1'bX && ^(main_487_b_0_i11_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_reg"); $finish; end
end
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_b_0_i11_i_i_reg <= main_487_b_0_i11_i_i;
if (^reset !== 1'bX && ^(main_487_b_0_i11_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %487*/
/* %488 = add nsw i32 %i.01.i2.i.i, 1*/
begin
main_487_488 = main_454_i_01_i2_i_i_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %487*/
/* %488 = add nsw i32 %i.01.i2.i.i, 1*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_488_reg <= main_487_488;
if (^reset !== 1'bX && ^(main_487_488) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_488_reg"); $finish; end
end
end
always @(*) begin
/* main: %487*/
/* %exitcond.i.i = icmp eq i32 %488, 64*/
begin
main_487_exitcond_i_i = main_487_488 == 32'd64;
end
end
always @(posedge clk) begin
/* main: %487*/
/* %exitcond.i.i = icmp eq i32 %488, 64*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_exitcond_i_i_reg <= main_487_exitcond_i_i;
if (^reset !== 1'bX && ^(main_487_exitcond_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_exitcond_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit13.i.i*/
/* %489 = add nsw i32 %i.517.i.i, 1*/
begin
main_YuvToRgb_exit13_i_i_489 = main__preheader16_i_i_i_517_i_i_reg + 32'd1;
end
end
always @(*) begin
/* main: %YuvToRgb.exit13.i.i*/
/* %exitcond35.i.i = icmp eq i32 %489, 4*/
begin
main_YuvToRgb_exit13_i_i_exitcond35_i_i = main_YuvToRgb_exit13_i_i_489 == 32'd4;
end
end
always @(*) begin
/* main: %.loopexit.i.i*/
/* %490 = icmp slt i32 %tmp49.i.i, %384*/
begin
main__loopexit_i_i_490 = $signed(main__preheader_i_i_tmp49_i_i_reg) < $signed(main_read_markers_exit_i_384_reg);
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* %490 = icmp slt i32 %tmp49.i.i, %384*/
if (cur_state == LEGUP_function_call_447)
begin
main__loopexit_i_i_490_reg <= main__loopexit_i_i_490;
if (^reset !== 1'bX && ^(main__loopexit_i_i_490) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_490_reg"); $finish; end
end
end
always @(*) begin
/* main: %.loopexit.i.i*/
/* %indvar.next.i.i = add i32 %indvar.i7.i, 1*/
begin
main__loopexit_i_i_indvar_next_i_i = main__preheader_i_i_indvar_i7_i_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* %indvar.next.i.i = add i32 %indvar.i7.i, 1*/
if (cur_state == LEGUP_function_call_447)
begin
main__loopexit_i_i_indvar_next_i_i_reg <= main__loopexit_i_i_indvar_next_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_i_indvar_next_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_indvar_next_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %decode_start.exit.i*/
/* %main_result.promoted3.i = load i32* @main_result, align 4*/
begin
main_decode_start_exit_i_main_result_promoted3_i = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_492 = main_491_492_phi_temp;
end
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
else /* if (cur_state == LEGUP_F_main_BB131_457) */
begin
main_491_492 = main_491_492_phi_temp;
end
end
always @(posedge clk) begin
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_492_reg <= main_491_492;
if (^reset !== 1'bX && ^(main_491_492) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_492_reg"); $finish; end
end
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_492_reg <= main_491_492;
if (^reset !== 1'bX && ^(main_491_492) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_492_reg"); $finish; end
end
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_492_reg <= main_491_492;
if (^reset !== 1'bX && ^(main_491_492) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_492_reg"); $finish; end
end
end
always @(*) begin
/* main: %491*/
/* %j.01.i = phi i32 [ 0, %decode_start.exit.i ], [ %498, %491 ]*/
begin
main_491_j_01_i = main_491_j_01_i_phi_temp;
end
end
always @(*) begin
/* main: %491*/
/* %scevgep7.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 0, i32 %j.01.i*/
begin
main_491_scevgep7_i = `TAG_g_hana_bmp_a + 1 * main_491_j_01_i;
end
end
always @(posedge clk) begin
/* main: %491*/
/* %scevgep7.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 0, i32 %j.01.i*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_scevgep7_i_reg <= main_491_scevgep7_i;
if (^reset !== 1'bX && ^(main_491_scevgep7_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_scevgep7_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %491*/
/* %scevgep.i = getelementptr [3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 %j.01.i*/
begin
main_491_scevgep_i = `TAG_g_OutData_comp_buf_a + 1 * main_491_j_01_i;
end
end
always @(*) begin
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
begin
main_491_493 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_459)
begin
main_491_493_reg <= main_491_493;
if (^reset !== 1'bX && ^(main_491_493) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_493_reg"); $finish; end
end
end
always @(*) begin
/* main: %491*/
/* %494 = load i8* %scevgep7.i, align 1, !tbaa !1*/
begin
main_491_494 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %491*/
/* %495 = icmp eq i8 %493, %494*/
begin
main_491_495 = main_491_493_reg == main_491_494;
end
end
always @(*) begin
/* main: %491*/
/* %496 = zext i1 %495 to i32*/
begin
main_491_496 = main_491_495;
end
end
always @(*) begin
/* main: %491*/
/* %497 = add nsw i32 %492, %496*/
begin
main_491_497 = main_491_492_reg + main_491_496;
end
end
always @(*) begin
/* main: %491*/
/* %498 = add nsw i32 %j.01.i, 1*/
begin
main_491_498 = main_491_j_01_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %491*/
/* %498 = add nsw i32 %j.01.i, 1*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_498_reg <= main_491_498;
if (^reset !== 1'bX && ^(main_491_498) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_498_reg"); $finish; end
end
end
always @(*) begin
/* main: %491*/
/* %exitcond.i = icmp eq i32 %498, 5310*/
begin
main_491_exitcond_i = main_491_498 == 32'd5310;
end
end
always @(posedge clk) begin
/* main: %491*/
/* %exitcond.i = icmp eq i32 %498, 5310*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_exitcond_i_reg <= main_491_exitcond_i;
if (^reset !== 1'bX && ^(main_491_exitcond_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_exitcond_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_499 = main__preheader_1_i_499_phi_temp;
end
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
else /* if (cur_state == LEGUP_F_main_BB132_461) */
begin
main__preheader_1_i_499 = main__preheader_1_i_499_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_499_reg <= main__preheader_1_i_499;
if (^reset !== 1'bX && ^(main__preheader_1_i_499) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_499_reg"); $finish; end
end
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_499_reg <= main__preheader_1_i_499;
if (^reset !== 1'bX && ^(main__preheader_1_i_499) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_499_reg"); $finish; end
end
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_499_reg <= main__preheader_1_i_499;
if (^reset !== 1'bX && ^(main__preheader_1_i_499) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_499_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %j.01.1.i = phi i32 [ %505, %.preheader.1.i ], [ 0, %491 ]*/
begin
main__preheader_1_i_j_01_1_i = main__preheader_1_i_j_01_1_i_phi_temp;
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %scevgep7.1.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 1, i32 %j.01.1.i*/
begin
main__preheader_1_i_scevgep7_1_i = `TAG_g_hana_bmp_a + 5310 * 32'd1 + 1 * main__preheader_1_i_j_01_1_i;
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %scevgep7.1.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 1, i32 %j.01.1.i*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_scevgep7_1_i_reg <= main__preheader_1_i_scevgep7_1_i;
if (^reset !== 1'bX && ^(main__preheader_1_i_scevgep7_1_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_scevgep7_1_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %scevgep.1.i = getelementptr [3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 %j.01.1.i*/
begin
main__preheader_1_i_scevgep_1_i = `TAG_g_OutData_comp_buf_a + 5310 * 32'd1 + 1 * main__preheader_1_i_j_01_1_i;
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
begin
main__preheader_1_i_500 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_463)
begin
main__preheader_1_i_500_reg <= main__preheader_1_i_500;
if (^reset !== 1'bX && ^(main__preheader_1_i_500) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_500_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %501 = load i8* %scevgep7.1.i, align 1, !tbaa !1*/
begin
main__preheader_1_i_501 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %502 = icmp eq i8 %500, %501*/
begin
main__preheader_1_i_502 = main__preheader_1_i_500_reg == main__preheader_1_i_501;
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %503 = zext i1 %502 to i32*/
begin
main__preheader_1_i_503 = main__preheader_1_i_502;
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %504 = add nsw i32 %499, %503*/
begin
main__preheader_1_i_504 = main__preheader_1_i_499_reg + main__preheader_1_i_503;
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %505 = add nsw i32 %j.01.1.i, 1*/
begin
main__preheader_1_i_505 = main__preheader_1_i_j_01_1_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %505 = add nsw i32 %j.01.1.i, 1*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_505_reg <= main__preheader_1_i_505;
if (^reset !== 1'bX && ^(main__preheader_1_i_505) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_505_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %exitcond.1.i = icmp eq i32 %505, 5310*/
begin
main__preheader_1_i_exitcond_1_i = main__preheader_1_i_505 == 32'd5310;
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %exitcond.1.i = icmp eq i32 %505, 5310*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_exitcond_1_i_reg <= main__preheader_1_i_exitcond_1_i;
if (^reset !== 1'bX && ^(main__preheader_1_i_exitcond_1_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_exitcond_1_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %506 = icmp eq i16 %379, 90*/
begin
main_jpeg2bmp_main_exit_506 = main_read_markers_exit_i_379_reg == 16'd90;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %507 = zext i1 %506 to i32*/
begin
main_jpeg2bmp_main_exit_507 = main_jpeg2bmp_main_exit_506;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %storemerge = add nsw i32 %518, %507*/
begin
main_jpeg2bmp_main_exit_storemerge = main__preheader_2_i_518_reg + main_jpeg2bmp_main_exit_507;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %508 = icmp eq i16 %374, 59*/
begin
main_jpeg2bmp_main_exit_508 = main_read_markers_exit_i_374_reg == 16'd59;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %509 = zext i1 %508 to i32*/
begin
main_jpeg2bmp_main_exit_509 = main_jpeg2bmp_main_exit_508;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %.storemerge = add nsw i32 %storemerge, %509*/
begin
main_jpeg2bmp_main_exit__storemerge = main_jpeg2bmp_main_exit_storemerge + main_jpeg2bmp_main_exit_509;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %511 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_jpeg2bmp_main_exit_511 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %512 = icmp eq i32 %511, 21745*/
begin
main_jpeg2bmp_main_exit_512 = main_jpeg2bmp_main_exit_511 == 32'd21745;
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_513 = main__preheader_2_i_513_phi_temp;
end
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
else /* if (cur_state == LEGUP_F_main_BB134_469) */
begin
main__preheader_2_i_513 = main__preheader_2_i_513_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_513_reg <= main__preheader_2_i_513;
if (^reset !== 1'bX && ^(main__preheader_2_i_513) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_513_reg"); $finish; end
end
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_513_reg <= main__preheader_2_i_513;
if (^reset !== 1'bX && ^(main__preheader_2_i_513) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_513_reg"); $finish; end
end
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_513_reg <= main__preheader_2_i_513;
if (^reset !== 1'bX && ^(main__preheader_2_i_513) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_513_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %j.01.2.i = phi i32 [ %519, %.preheader.2.i ], [ 0, %.preheader.1.i ]*/
begin
main__preheader_2_i_j_01_2_i = main__preheader_2_i_j_01_2_i_phi_temp;
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %scevgep7.2.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 2, i32 %j.01.2.i*/
begin
main__preheader_2_i_scevgep7_2_i = `TAG_g_hana_bmp_a + 5310 * 32'd2 + 1 * main__preheader_2_i_j_01_2_i;
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %scevgep7.2.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 2, i32 %j.01.2.i*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_scevgep7_2_i_reg <= main__preheader_2_i_scevgep7_2_i;
if (^reset !== 1'bX && ^(main__preheader_2_i_scevgep7_2_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_scevgep7_2_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %scevgep.2.i = getelementptr [3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 %j.01.2.i*/
begin
main__preheader_2_i_scevgep_2_i = `TAG_g_OutData_comp_buf_a + 5310 * 32'd2 + 1 * main__preheader_2_i_j_01_2_i;
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
begin
main__preheader_2_i_514 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_471)
begin
main__preheader_2_i_514_reg <= main__preheader_2_i_514;
if (^reset !== 1'bX && ^(main__preheader_2_i_514) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_514_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %515 = load i8* %scevgep7.2.i, align 1, !tbaa !1*/
begin
main__preheader_2_i_515 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %516 = icmp eq i8 %514, %515*/
begin
main__preheader_2_i_516 = main__preheader_2_i_514_reg == main__preheader_2_i_515;
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %517 = zext i1 %516 to i32*/
begin
main__preheader_2_i_517 = main__preheader_2_i_516;
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %518 = add nsw i32 %513, %517*/
begin
main__preheader_2_i_518 = main__preheader_2_i_513_reg + main__preheader_2_i_517;
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %518 = add nsw i32 %513, %517*/
if (cur_state == LEGUP_F_main_BB134_472)
begin
main__preheader_2_i_518_reg <= main__preheader_2_i_518;
if (^reset !== 1'bX && ^(main__preheader_2_i_518) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_518_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %519 = add nsw i32 %j.01.2.i, 1*/
begin
main__preheader_2_i_519 = main__preheader_2_i_j_01_2_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %519 = add nsw i32 %j.01.2.i, 1*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_519_reg <= main__preheader_2_i_519;
if (^reset !== 1'bX && ^(main__preheader_2_i_519) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_519_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %exitcond.2.i = icmp eq i32 %519, 5310*/
begin
main__preheader_2_i_exitcond_2_i = main__preheader_2_i_519 == 32'd5310;
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %exitcond.2.i = icmp eq i32 %519, 5310*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_exitcond_2_i_reg <= main__preheader_2_i_exitcond_2_i;
if (^reset !== 1'bX && ^(main__preheader_2_i_exitcond_2_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_exitcond_2_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %524*/
/* %525 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_524_525 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
huff_make_dhuff_tb_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
huff_make_dhuff_tb_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
huff_make_dhuff_tb_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
huff_make_dhuff_tb_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
huff_make_dhuff_tb_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
huff_make_dhuff_tb_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
huff_make_dhuff_tb_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
huff_make_dhuff_tb_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
huff_make_dhuff_tb_arg_p_xhtbl_bits <= `TAG_g_p_jinfo_dc_xhuff_tbl_bits_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_xhuff_tbl_bits_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_xhtbl_bits"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
huff_make_dhuff_tb_arg_p_xhtbl_bits <= `TAG_g_p_jinfo_dc_xhuff_tbl_bits_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_xhuff_tbl_bits_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_xhtbl_bits"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
huff_make_dhuff_tb_arg_p_xhtbl_bits <= `TAG_g_p_jinfo_ac_xhuff_tbl_bits_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_xhuff_tbl_bits_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_xhtbl_bits"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
huff_make_dhuff_tb_arg_p_xhtbl_bits <= `TAG_g_p_jinfo_ac_xhuff_tbl_bits_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_xhuff_tbl_bits_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_xhtbl_bits"); $finish; end
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
huff_make_dhuff_tb_arg_p_dhtbl_maxcode <= `TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_maxcode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
huff_make_dhuff_tb_arg_p_dhtbl_maxcode <= `TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_maxcode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
huff_make_dhuff_tb_arg_p_dhtbl_maxcode <= `TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_maxcode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
huff_make_dhuff_tb_arg_p_dhtbl_maxcode <= `TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_maxcode"); $finish; end
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
huff_make_dhuff_tb_arg_p_dhtbl_mincode <= `TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_mincode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
huff_make_dhuff_tb_arg_p_dhtbl_mincode <= `TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_mincode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
huff_make_dhuff_tb_arg_p_dhtbl_mincode <= `TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_mincode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
huff_make_dhuff_tb_arg_p_dhtbl_mincode <= `TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_mincode"); $finish; end
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
huff_make_dhuff_tb_arg_p_dhtbl_valptr <= `TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_valptr"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
huff_make_dhuff_tb_arg_p_dhtbl_valptr <= `TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_valptr"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
huff_make_dhuff_tb_arg_p_dhtbl_valptr <= `TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_valptr"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
huff_make_dhuff_tb_arg_p_dhtbl_valptr <= `TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_valptr"); $finish; end
end
end
always @(*) begin
huff_make_dhuff_tb_memory_controller_waitrequest = 1'd0;
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
huff_make_dhuff_tb_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
huff_make_dhuff_tb_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
huff_make_dhuff_tb_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
huff_make_dhuff_tb_memory_controller_waitrequest = memory_controller_waitrequest;
end
end
always @(*) begin
huff_make_dhuff_tb_memory_controller_out = 1'd0;
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
huff_make_dhuff_tb_memory_controller_out = memory_controller_out;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
huff_make_dhuff_tb_memory_controller_out = memory_controller_out;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
huff_make_dhuff_tb_memory_controller_out = memory_controller_out;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
huff_make_dhuff_tb_memory_controller_out = memory_controller_out;
end
end
always @(*) begin
legup_function_call = 1'd0;
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_360)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_363)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_411)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_414)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_417)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_420)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_423)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
legup_function_call = 1'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_360)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_363)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_411)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_414)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_417)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_420)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_423)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
decode_block_arg_comp_no <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_360)
begin
decode_block_arg_comp_no <= 32'd1;
if (^reset !== 1'bX && ^(32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_363)
begin
decode_block_arg_comp_no <= 32'd2;
if (^reset !== 1'bX && ^(32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
decode_block_arg_comp_no <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_411)
begin
decode_block_arg_comp_no <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_414)
begin
decode_block_arg_comp_no <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_417)
begin
decode_block_arg_comp_no <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_420)
begin
decode_block_arg_comp_no <= 32'd1;
if (^reset !== 1'bX && ^(32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_423)
begin
decode_block_arg_comp_no <= 32'd2;
if (^reset !== 1'bX && ^(32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
decode_block_arg_out_buf <= main__preheader21_i_i_preheader_scevgep51_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_360)
begin
decode_block_arg_out_buf <= main__preheader21_i_i_preheader_scevgep51_1_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_1_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_363)
begin
decode_block_arg_out_buf <= main__preheader21_i_i_preheader_scevgep51_2_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_2_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_scevgep_i8_i_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_i8_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_411)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_scevgep_1_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_1_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_414)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_scevgep_2_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_2_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_417)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_scevgep_3_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_3_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_420)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_452_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_452_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_423)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_453_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_453_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_360)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_1_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_1_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_363)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_2_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_2_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_411)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_414)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_417)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_420)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_1_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_1_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_423)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_2_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_2_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
end
always @(*) begin
decode_block_memory_controller_waitrequest = 1'd0;
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
end
always @(*) begin
decode_block_memory_controller_out = 1'd0;
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
decode_block_memory_controller_out = memory_controller_out;
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
Write4Blocks_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
Write4Blocks_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
Write4Blocks_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_store1 <= `TAG_g_rgb_buf_a;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store1"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_store1 <= `TAG_g_rgb_buf_a + 256 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 256 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store1"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_store1 <= `TAG_g_rgb_buf_a + 256 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 256 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store1"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_store2 <= `TAG_g_rgb_buf_a + 768 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store2"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_store2 <= `TAG_g_rgb_buf_a + 768 * 32'd1 + 256 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd1 + 256 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store2"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_store2 <= `TAG_g_rgb_buf_a + 768 * 32'd1 + 256 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd1 + 256 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store2"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_store3 <= `TAG_g_rgb_buf_a + 768 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store3"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_store3 <= `TAG_g_rgb_buf_a + 768 * 32'd2 + 256 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd2 + 256 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store3"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_store3 <= `TAG_g_rgb_buf_a + 768 * 32'd2 + 256 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd2 + 256 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store3"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_store4 <= `TAG_g_rgb_buf_a + 768 * 32'd3;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store4"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_store4 <= `TAG_g_rgb_buf_a + 768 * 32'd3 + 256 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd3 + 256 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store4"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_store4 <= `TAG_g_rgb_buf_a + 768 * 32'd3 + 256 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd3 + 256 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store4"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_p_out_vpos <= `TAG_g_OutData_comp_vpos_a;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_vpos_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_vpos"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_p_out_vpos <= `TAG_g_OutData_comp_vpos_a + 4 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_vpos_a + 4 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_vpos"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_p_out_vpos <= `TAG_g_OutData_comp_vpos_a + 4 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_vpos_a + 4 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_vpos"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_p_out_hpos <= `TAG_g_OutData_comp_hpos_a;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_hpos_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_hpos"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_p_out_hpos <= `TAG_g_OutData_comp_hpos_a + 4 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_hpos_a + 4 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_hpos"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_p_out_hpos <= `TAG_g_OutData_comp_hpos_a + 4 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_hpos_a + 4 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_hpos"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_p_out_buf <= `TAG_g_OutData_comp_buf_a;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_buf_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_buf"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_p_out_buf <= `TAG_g_OutData_comp_buf_a + 5310 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_buf_a + 5310 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_buf"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_p_out_buf <= `TAG_g_OutData_comp_buf_a + 5310 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_buf_a + 5310 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_buf"); $finish; end
end
end
always @(*) begin
Write4Blocks_memory_controller_waitrequest = 1'd0;
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
Write4Blocks_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
Write4Blocks_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
Write4Blocks_memory_controller_waitrequest = memory_controller_waitrequest;
end
end
always @(*) begin
Write4Blocks_memory_controller_out = 1'd0;
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
Write4Blocks_memory_controller_out = memory_controller_out;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
Write4Blocks_memory_controller_out = memory_controller_out;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
Write4Blocks_memory_controller_out = memory_controller_out;
end
end
always @(*) begin
/* main: %392*/
/* %403 = mul i32 %395, -88*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_signed_multiply_32_1_op0 = main_392_395;
end
/* main: %392*/
/* %399 = mul nsw i32 %397, 359*/
else if (cur_state == LEGUP_F_main_BB94_370)
begin
main_signed_multiply_32_1_op0 = main_392_397;
end
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp121.i.i = mul i32 %tmp120.i.i, %434*/
else if (cur_state == LEGUP_F_main_BB106_392)
begin
main_signed_multiply_32_1_op0 = main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i_reg;
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp118.i.i = mul i32 %428, %indvar17.i.i.i.i*/
else if (cur_state == LEGUP_F_main_BB109_399)
begin
main_signed_multiply_32_1_op0 = main_YuvToRgb_exit_loopexit_i_i_428_reg;
end
/* main: %454*/
/* %465 = mul i32 %457, -88*/
else if (cur_state == LEGUP_F_main_BB118_430)
begin
main_signed_multiply_32_1_op0 = main_454_457;
end
/* main: %454*/
/* %461 = mul nsw i32 %459, 359*/
else /* if (cur_state == LEGUP_F_main_BB118_431) */
begin
main_signed_multiply_32_1_op0 = main_454_459;
end
end
always @(*) begin
/* main: %392*/
/* %403 = mul i32 %395, -88*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_signed_multiply_32_1_op1 = -32'd88;
end
/* main: %392*/
/* %399 = mul nsw i32 %397, 359*/
else if (cur_state == LEGUP_F_main_BB94_370)
begin
main_signed_multiply_32_1_op1 = 32'd359;
end
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp121.i.i = mul i32 %tmp120.i.i, %434*/
else if (cur_state == LEGUP_F_main_BB106_392)
begin
main_signed_multiply_32_1_op1 = main_432_434_reg;
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp118.i.i = mul i32 %428, %indvar17.i.i.i.i*/
else if (cur_state == LEGUP_F_main_BB109_399)
begin
main_signed_multiply_32_1_op1 = main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
end
/* main: %454*/
/* %465 = mul i32 %457, -88*/
else if (cur_state == LEGUP_F_main_BB118_430)
begin
main_signed_multiply_32_1_op1 = -32'd88;
end
/* main: %454*/
/* %461 = mul nsw i32 %459, 359*/
else /* if (cur_state == LEGUP_F_main_BB118_431) */
begin
main_signed_multiply_32_1_op1 = 32'd359;
end
end
always @(*) begin
main_signed_multiply_32_1 = main_signed_multiply_32_1_op0 * main_signed_multiply_32_1_op1;
end
always @(*) begin
/* main: %392*/
/* %408 = mul nsw i32 %395, 454*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_signed_multiply_32_2_op0 = main_392_395;
end
/* main: %392*/
/* %404 = mul i32 %397, -182*/
else if (cur_state == LEGUP_F_main_BB94_370)
begin
main_signed_multiply_32_2_op0 = main_392_397;
end
/* main: %454*/
/* %470 = mul nsw i32 %457, 454*/
else if (cur_state == LEGUP_F_main_BB118_430)
begin
main_signed_multiply_32_2_op0 = main_454_457;
end
/* main: %454*/
/* %466 = mul i32 %459, -182*/
else /* if (cur_state == LEGUP_F_main_BB118_431) */
begin
main_signed_multiply_32_2_op0 = main_454_459;
end
end
always @(*) begin
/* main: %392*/
/* %408 = mul nsw i32 %395, 454*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_signed_multiply_32_2_op1 = 32'd454;
end
/* main: %392*/
/* %404 = mul i32 %397, -182*/
else if (cur_state == LEGUP_F_main_BB94_370)
begin
main_signed_multiply_32_2_op1 = -32'd182;
end
/* main: %454*/
/* %470 = mul nsw i32 %457, 454*/
else if (cur_state == LEGUP_F_main_BB118_430)
begin
main_signed_multiply_32_2_op1 = 32'd454;
end
/* main: %454*/
/* %466 = mul i32 %459, -182*/
else /* if (cur_state == LEGUP_F_main_BB118_431) */
begin
main_signed_multiply_32_2_op1 = -32'd182;
end
end
always @(*) begin
main_signed_multiply_32_2 = main_signed_multiply_32_2_op0 * main_signed_multiply_32_2_op1;
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %384 = mul nsw i32 %383, %378*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
main_signed_multiply_32_0_op0 = main_read_markers_exit_i_383;
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp136.i.i = mul i32 %indvar17.i.i.i.i, %tmp69.i.i*/
else /* if (cur_state == LEGUP_F_main_BB109_399) */
begin
main_signed_multiply_32_0_op0 = main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %384 = mul nsw i32 %383, %378*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
main_signed_multiply_32_0_op1 = main_read_markers_exit_i_378_reg;
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp136.i.i = mul i32 %indvar17.i.i.i.i, %tmp69.i.i*/
else /* if (cur_state == LEGUP_F_main_BB109_399) */
begin
main_signed_multiply_32_0_op1 = main__lr_ph8_split_us_i_i_i_i_tmp69_i_i_reg;
end
end
always @(*) begin
main_signed_multiply_32_0 = main_signed_multiply_32_0_op0 * main_signed_multiply_32_0_op1;
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %377 = sdiv i32 %376, 8*/
if (cur_state == LEGUP_F_main_BB90_287)
begin
main_signed_divide_32_0_op0 = main_read_markers_exit_i_376_reg;
end
/* main: %read_markers.exit.i*/
/* %382 = sdiv i32 %381, 8*/
else /* if (cur_state == LEGUP_F_main_BB90_288) */
begin
main_signed_divide_32_0_op0 = main_read_markers_exit_i_381_reg;
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %377 = sdiv i32 %376, 8*/
if (cur_state == LEGUP_F_main_BB90_287)
begin
main_signed_divide_32_0_op1 = 32'd8;
end
/* main: %read_markers.exit.i*/
/* %382 = sdiv i32 %381, 8*/
else /* if (cur_state == LEGUP_F_main_BB90_288) */
begin
main_signed_divide_32_0_op1 = 32'd8;
end
end
always @(*) begin
main_signed_divide_32_0 = lpm_divide_main_read_markers_exit_i_377_out;
end
always @(*) begin
lpm_divide_main_read_markers_exit_i_377_en = memory_controller_waitrequest == 1'd0 & legup_function_call == 1'd0;
end
always @(posedge clk) begin
/* main: %1*/
/* %i.05.i = phi i32 [ 0, %0 ], [ %3, %1 ]*/
if (cur_state == LEGUP_F_main_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
main_1_i_05_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_i_05_i_phi_temp"); $finish; end
end
/* main: %1*/
/* %i.05.i = phi i32 [ 0, %0 ], [ %3, %1 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd0)
begin
main_1_i_05_i_phi_temp <= main_1_3_reg;
if (^reset !== 1'bX && ^(main_1_3_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_i_05_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %i_marker.0 = phi i32 [ 0, %1 ], [ %24, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_i_marker_0_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_marker_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %i_marker.0 = phi i32 [ 0, %1 ], [ %24, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_i_marker_0_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_marker_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %i_get_dht.0 = phi i32 [ 0, %1 ], [ %i_get_dht.1.ph, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_i_get_dht_0_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_get_dht_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %i_get_dht.0 = phi i32 [ 0, %1 ], [ %i_get_dht.1.ph, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_i_get_dht_0_phi_temp <= main__backedge_i_i_outer_i_get_dht_1_ph_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_get_dht_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %i_get_dqt.0 = phi i32 [ 0, %1 ], [ %i_get_dqt.1.ph6, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_i_get_dqt_0_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_get_dqt_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %i_get_dqt.0 = phi i32 [ 0, %1 ], [ %i_get_dqt.1.ph6, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_i_get_dqt_0_phi_temp <= main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_get_dqt_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %ReadBuf.0 = phi i8* [ getelementptr inbounds ([5310 x i8]* @JpegFileBuf, i32 0, i32 0), %1 ], [ %ReadBuf.2, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_ReadBuf_0_phi_temp <= `TAG_g_JpegFileBuf_a;
if (^reset !== 1'bX && ^(`TAG_g_JpegFileBuf_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_ReadBuf_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %ReadBuf.0 = phi i8* [ getelementptr inbounds ([5310 x i8]* @JpegFileBuf, i32 0, i32 0), %1 ], [ %ReadBuf.2, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_ReadBuf_0_phi_temp <= main_next_marker_exit_i_i_ReadBuf_2_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_ReadBuf_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %p_jinfo_num_components.0 = phi i8 [ 0, %1 ], [ %p_jinfo_num_components.1.ph13, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_p_jinfo_num_components_0_phi_temp <= 8'd0;
if (^reset !== 1'bX && ^(8'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_p_jinfo_num_components_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %p_jinfo_num_components.0 = phi i8 [ 0, %1 ], [ %p_jinfo_num_components.1.ph13, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_p_jinfo_num_components_0_phi_temp <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_p_jinfo_num_components_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %p_jinfo_smp_fact.b.0 = phi i1 [ false, %1 ], [ %p_jinfo_smp_fact.b.1.ph14, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %p_jinfo_smp_fact.b.0 = phi i1 [ false, %1 ], [ %p_jinfo_smp_fact.b.1.ph14, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp <= -1'd1;
if (^reset !== 1'bX && ^(-1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %i_marker.1.ph = phi i32 [ %i_marker.0, %.outer.i.i ], [ %24, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_i_marker_1_ph_phi_temp <= main__outer_i_i_i_marker_0;
if (^reset !== 1'bX && ^(main__outer_i_i_i_marker_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_marker_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_marker.1.ph = phi i32 [ %i_marker.0, %.outer.i.i ], [ %24, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_i_marker_1_ph_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_marker_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp <= main__outer_i_i_i_get_dht_0;
if (^reset !== 1'bX && ^(main__outer_i_i_i_get_dht_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp <= main_301_302_reg;
if (^reset !== 1'bX && ^(main_301_302_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %i_get_dqt.1.ph = phi i32 [ %i_get_dqt.0, %.outer.i.i ], [ %i_get_dqt.1.ph6, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp <= main__outer_i_i_i_get_dqt_0;
if (^reset !== 1'bX && ^(main__outer_i_i_i_get_dqt_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dqt.1.ph = phi i32 [ %i_get_dqt.0, %.outer.i.i ], [ %i_get_dqt.1.ph6, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp <= main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %ReadBuf.1.ph = phi i8* [ %ReadBuf.0, %.outer.i.i ], [ %ReadBuf.7, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp <= main__outer_i_i_ReadBuf_0;
if (^reset !== 1'bX && ^(main__outer_i_i_ReadBuf_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %ReadBuf.1.ph = phi i8* [ %ReadBuf.0, %.outer.i.i ], [ %ReadBuf.7, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp <= main___crit_edge_i12_i_i_ReadBuf_7;
if (^reset !== 1'bX && ^(main___crit_edge_i12_i_i_ReadBuf_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_num_components.1.ph = phi i8 [ %p_jinfo_num_components.0, %.outer.i.i ], [ %p_jinfo_num_components.1.ph13, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp <= main__outer_i_i_p_jinfo_num_components_0;
if (^reset !== 1'bX && ^(main__outer_i_i_p_jinfo_num_components_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_num_components.1.ph = phi i8 [ %p_jinfo_num_components.0, %.outer.i.i ], [ %p_jinfo_num_components.1.ph13, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_smp_fact.b.1.ph = phi i1 [ %p_jinfo_smp_fact.b.0, %.outer.i.i ], [ %p_jinfo_smp_fact.b.1.ph14, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp <= main__outer_i_i_p_jinfo_smp_fact_b_0;
if (^reset !== 1'bX && ^(main__outer_i_i_p_jinfo_smp_fact_b_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_smp_fact.b.1.ph = phi i1 [ %p_jinfo_smp_fact.b.0, %.outer.i.i ], [ %p_jinfo_smp_fact.b.1.ph14, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %i_marker.1.ph5 = phi i32 [ %i_marker.1.ph, %.backedge.i.i.outer ], [ %24, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp <= main__backedge_i_i_outer_i_marker_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_marker_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_marker.1.ph5 = phi i32 [ %i_marker.1.ph, %.backedge.i.i.outer ], [ %24, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp <= main__backedge_i_i_outer_i_get_dqt_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dqt_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp <= main_351_352_reg;
if (^reset !== 1'bX && ^(main_351_352_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %ReadBuf.1.ph7 = phi i8* [ %ReadBuf.1.ph, %.backedge.i.i.outer ], [ %ReadBuf.8, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp <= main__backedge_i_i_outer_ReadBuf_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_ReadBuf_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %ReadBuf.1.ph7 = phi i8* [ %ReadBuf.1.ph, %.backedge.i.i.outer ], [ %ReadBuf.8, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp <= main__us_lcssa_us_i_i_i_ReadBuf_8;
if (^reset !== 1'bX && ^(main__us_lcssa_us_i_i_i_ReadBuf_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_num_components.1.ph8 = phi i8 [ %p_jinfo_num_components.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_num_components.1.ph13, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp <= main__backedge_i_i_outer_p_jinfo_num_components_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_p_jinfo_num_components_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_num_components.1.ph8 = phi i8 [ %p_jinfo_num_components.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_num_components.1.ph13, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_smp_fact.b.1.ph9 = phi i1 [ %p_jinfo_smp_fact.b.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_smp_fact.b.1.ph14, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp <= main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_smp_fact.b.1.ph9 = phi i1 [ %p_jinfo_smp_fact.b.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_smp_fact.b.1.ph14, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %i_marker.1.ph11 = phi i32 [ %i_marker.1.ph5, %.backedge.i.i.outer4 ], [ %24, %163 ], [ %24, %165 ]*/
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp <= main__backedge_i_i_outer4_i_marker_1_ph5;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_marker_1_ph5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %i_marker.1.ph11 = phi i32 [ %i_marker.1.ph5, %.backedge.i.i.outer4 ], [ %24, %163 ], [ %24, %165 ]*/
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %i_marker.1.ph11 = phi i32 [ %i_marker.1.ph5, %.backedge.i.i.outer4 ], [ %24, %163 ], [ %24, %165 ]*/
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %ReadBuf.1.ph12 = phi i8* [ %ReadBuf.1.ph7, %.backedge.i.i.outer4 ], [ %ReadBuf.4, %163 ], [ %ReadBuf.4, %165 ]*/
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp <= main__backedge_i_i_outer4_ReadBuf_1_ph7;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_ReadBuf_1_ph7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %ReadBuf.1.ph12 = phi i8* [ %ReadBuf.1.ph7, %.backedge.i.i.outer4 ], [ %ReadBuf.4, %163 ], [ %ReadBuf.4, %165 ]*/
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp <= main___crit_edge_i_i_i_ReadBuf_4_reg;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %ReadBuf.1.ph12 = phi i8* [ %ReadBuf.1.ph7, %.backedge.i.i.outer4 ], [ %ReadBuf.4, %163 ], [ %ReadBuf.4, %165 ]*/
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp <= main___crit_edge_i_i_i_ReadBuf_4_reg;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp <= main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp <= main_32_61_reg;
if (^reset !== 1'bX && ^(main_32_61_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp <= main_32_61_reg;
if (^reset !== 1'bX && ^(main_32_61_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp <= main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp <= -1'd1;
if (^reset !== 1'bX && ^(-1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB5_8 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_i_marker_1_phi_temp <= main__backedge_i_i_outer10_i_marker_1_ph11;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_i_marker_1_ph11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd216 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd192 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd218 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd196 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd219 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd217)
begin
main__backedge_i_i_i_marker_1_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd0)
begin
main__backedge_i_i_i_marker_1_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd0)
begin
main__backedge_i_i_i_marker_1_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB5_8 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_ReadBuf_1_phi_temp <= main__backedge_i_i_outer10_ReadBuf_1_ph12;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_ReadBuf_1_ph12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd216 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd192 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd218 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd196 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd219 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd217)
begin
main__backedge_i_i_ReadBuf_1_phi_temp <= main_next_marker_exit_i_i_ReadBuf_2_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd0)
begin
main__backedge_i_i_ReadBuf_1_phi_temp <= main_248_253_reg;
if (^reset !== 1'bX && ^(main_248_253_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd0)
begin
main__backedge_i_i_ReadBuf_1_phi_temp <= main_312_317_reg;
if (^reset !== 1'bX && ^(main_312_317_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9 & memory_controller_waitrequest == 1'd0 & main__outer_i_i_sow_SOI_0_ph_i_i_reg == 1'd0)
begin
main__loopexit3_i_i_i_18_phi_temp <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_phi_temp"); $finish; end
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB10_18 & memory_controller_waitrequest == 1'd0)
begin
main__loopexit3_i_i_i_18_phi_temp <= main__loopexit3_i_i_i_loopexit_scevgep13_i_i_le;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_loopexit_scevgep13_i_i_le) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB9_17 & memory_controller_waitrequest == 1'd0)
begin
main_next_marker_exit_i_i_ReadBuf_2_phi_temp <= main_first_marker_exit_i_i_14_reg;
if (^reset !== 1'bX && ^(main_first_marker_exit_i_i_14_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_phi_temp"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB16_30 & memory_controller_waitrequest == 1'd0)
begin
main_next_marker_exit_i_i_ReadBuf_2_phi_temp <= main_next_marker_exit_i_i_loopexit_scevgep13_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_loopexit_scevgep13_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB9_17 & memory_controller_waitrequest == 1'd0)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp <= main_first_marker_exit_i_i_15_reg;
if (^reset !== 1'bX && ^(main_first_marker_exit_i_i_15_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB16_30 & memory_controller_waitrequest == 1'd0)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp <= main__loopexit_i_i_i_22_reg;
if (^reset !== 1'bX && ^(main__loopexit_i_i_i_22_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB11_21 & memory_controller_waitrequest == 1'd0 & main__loopexit3_i_i_i_19 == 1'd1)
begin
main__loopexit_i_preheader_i_i__ph_i_i_phi_temp <= main__loopexit3_i_i_i_storemerge1_i_i_i_reg;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_storemerge1_i_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_phi_temp"); $finish; end
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB13_25 & memory_controller_waitrequest == 1'd0)
begin
main__loopexit_i_preheader_i_i__ph_i_i_phi_temp <= main__loopexit_i_preheader_i_i_loopexit_storemerge_i_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i_loopexit_storemerge_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_21 & memory_controller_waitrequest == 1'd0 & main__loopexit3_i_i_i_19 == 1'd0)
begin
main__lr_ph_i_i_i_indvar_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_indvar_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB12_24 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i_i_i_20 == 1'd0)
begin
main__lr_ph_i_i_i_indvar_i_i_phi_temp <= main__lr_ph_i_i_i_tmp_i_i_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i_i_i_tmp_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_indvar_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i.i*/
/* %indvar9.i.i = phi i32 [ 0, %.loopexit.i.preheader.i.i ], [ %tmp12.i.i, %.loopexit.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB14_26 & memory_controller_waitrequest == 1'd0)
begin
main__loopexit_i_i_i_indvar9_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_i_indvar9_i_i_phi_temp"); $finish; end
end
/* main: %.loopexit.i.i.i*/
/* %indvar9.i.i = phi i32 [ 0, %.loopexit.i.preheader.i.i ], [ %tmp12.i.i, %.loopexit.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB15_29 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_i_22 == 32'd255)
begin
main__loopexit_i_i_i_indvar9_i_i_phi_temp <= main__loopexit_i_i_i_tmp12_i_i_reg;
if (^reset !== 1'bX && ^(main__loopexit_i_i_i_tmp12_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_i_indvar9_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd217)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp <= 0;
if (^reset !== 1'bX && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB63_200 & memory_controller_waitrequest == 1'd0)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp <= main_get_sos_exit_i_i_scevgep_i2_i_i;
if (^reset !== 1'bX && ^(main_get_sos_exit_i_i_scevgep_i2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB29_80 & memory_controller_waitrequest == 1'd0)
begin
main__lr_ph_i1_i_i_ReadBuf_3_phi_temp <= main_32_60_reg;
if (^reset !== 1'bX && ^(main_32_60_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_phi_temp"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd0 & main__preheader_i_i_i_98 == 1'd1)
begin
main__lr_ph_i1_i_i_ReadBuf_3_phi_temp <= main_32_60_reg;
if (^reset !== 1'bX && ^(main_32_60_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_phi_temp"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd0 & main_159_160 == 1'd1)
begin
main__lr_ph_i1_i_i_ReadBuf_3_phi_temp <= main__lr_ph_i1_i_i_105_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_105_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %ci.02.i.i.i = phi i32 [ %tmp12.i.i.i, %159 ], [ 0, %.preheader.i.i.i.thread ], [ 0, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB29_80 & memory_controller_waitrequest == 1'd0)
begin
main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ci.02.i.i.i = phi i32 [ %tmp12.i.i.i, %159 ], [ 0, %.preheader.i.i.i.thread ], [ 0, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd0 & main__preheader_i_i_i_98 == 1'd1)
begin
main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ci.02.i.i.i = phi i32 [ %tmp12.i.i.i, %159 ], [ 0, %.preheader.i.i.i.thread ], [ 0, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd0 & main_159_160 == 1'd1)
begin
main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp <= main__lr_ph_i1_i_i_tmp12_i_i_i_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_tmp12_i_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd0 & main__preheader_i_i_i_98 == 1'd0)
begin
main___crit_edge_i_i_i_ReadBuf_4_phi_temp <= main_32_60_reg;
if (^reset !== 1'bX && ^(main_32_60_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_phi_temp"); $finish; end
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd0 & main_159_160 == 1'd0)
begin
main___crit_edge_i_i_i_ReadBuf_4_phi_temp <= main__lr_ph_i1_i_i_105_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_105_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB49_157 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_i_get_sos_0_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_phi_temp"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB62_199 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_i_get_sos_0_phi_temp <= main_245_246;
if (^reset !== 1'bX && ^(main_245_246) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB49_157 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_ReadBuf_5_phi_temp <= main_167_177_reg;
if (^reset !== 1'bX && ^(main_167_177_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_phi_temp"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB62_199 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_ReadBuf_5_phi_temp <= main_194_198_reg;
if (^reset !== 1'bX && ^(main_194_198_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB49_157 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_192_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_192_phi_temp"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB62_199 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_192_phi_temp <= main_245_247;
if (^reset !== 1'bX && ^(main_245_247) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_192_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB51_162 & memory_controller_waitrequest == 1'd0)
begin
main_200_201_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_phi_temp"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB54_167 & memory_controller_waitrequest == 1'd0)
begin
main_200_201_phi_temp <= main_207_208;
if (^reset !== 1'bX && ^(main_207_208) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd1)
begin
main__lr_ph5_i_i_i_i_get_dht_2_phi_temp <= main__backedge_i_i_outer_i_get_dht_1_ph_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_phi_temp"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd1)
begin
main__lr_ph5_i_i_i_i_get_dht_2_phi_temp <= main_301_302_reg;
if (^reset !== 1'bX && ^(main_301_302_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %ReadBuf.6 = phi i8* [ %ReadBuf.7, %._crit_edge.i12.i.i ], [ %253, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd1)
begin
main__lr_ph5_i_i_i_ReadBuf_6_phi_temp <= main_248_253_reg;
if (^reset !== 1'bX && ^(main_248_253_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_ReadBuf_6_phi_temp"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %ReadBuf.6 = phi i8* [ %ReadBuf.7, %._crit_edge.i12.i.i ], [ %253, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd1)
begin
main__lr_ph5_i_i_i_ReadBuf_6_phi_temp <= main___crit_edge_i12_i_i_ReadBuf_7;
if (^reset !== 1'bX && ^(main___crit_edge_i12_i_i_ReadBuf_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_ReadBuf_6_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd1)
begin
main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp <= main_248_258_reg;
if (^reset !== 1'bX && ^(main_248_258_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd1)
begin
main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp <= main___crit_edge_i12_i_i_310;
if (^reset !== 1'bX && ^(main___crit_edge_i12_i_i_310) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB70_222 & memory_controller_waitrequest == 1'd0)
begin
main_286_p_xhtbl_huffval_0_i_i_i_phi_temp <= main_279_282;
if (^reset !== 1'bX && ^(main_279_282) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_huffval_0_i_i_i_phi_temp"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB71_223 & memory_controller_waitrequest == 1'd0)
begin
main_286_p_xhtbl_huffval_0_i_i_i_phi_temp <= main_283_285;
if (^reset !== 1'bX && ^(main_283_285) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_huffval_0_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB70_222 & memory_controller_waitrequest == 1'd0)
begin
main_286_p_xhtbl_bits_0_i_i_i_phi_temp <= main_279_281;
if (^reset !== 1'bX && ^(main_279_281) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_bits_0_i_i_i_phi_temp"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB71_223 & memory_controller_waitrequest == 1'd0)
begin
main_286_p_xhtbl_bits_0_i_i_i_phi_temp <= main_283_284;
if (^reset !== 1'bX && ^(main_283_284) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_bits_0_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %287*/
/* %288 = phi i8* [ %266, %286 ], [ %289, %287 ]*/
if (cur_state == LEGUP_F_main_BB72_224 & memory_controller_waitrequest == 1'd0)
begin
main_287_288_phi_temp <= main__lr_ph5_i_i_i_266_reg;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_266_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_288_phi_temp"); $finish; end
end
/* main: %287*/
/* %288 = phi i8* [ %266, %286 ], [ %289, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd0 & main_287_exitcond_i_i_i_reg == 1'd0)
begin
main_287_288_phi_temp <= main_287_289_reg;
if (^reset !== 1'bX && ^(main_287_289_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_288_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %287*/
/* %indvar.i.i.i = phi i32 [ 0, %286 ], [ %tmp.i8.i.i, %287 ]*/
if (cur_state == LEGUP_F_main_BB72_224 & memory_controller_waitrequest == 1'd0)
begin
main_287_indvar_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_indvar_i_i_i_phi_temp"); $finish; end
end
/* main: %287*/
/* %indvar.i.i.i = phi i32 [ 0, %286 ], [ %tmp.i8.i.i, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd0 & main_287_exitcond_i_i_i_reg == 1'd0)
begin
main_287_indvar_i_i_i_phi_temp <= main_287_tmp_i8_i_i_reg;
if (^reset !== 1'bX && ^(main_287_tmp_i8_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_indvar_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB72_224 & memory_controller_waitrequest == 1'd0)
begin
main_287_count_01_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_count_01_i_i_i_phi_temp"); $finish; end
end
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd0 & main_287_exitcond_i_i_i_reg == 1'd0)
begin
main_287_count_01_i_i_i_phi_temp <= main_287_292;
if (^reset !== 1'bX && ^(main_287_292) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_count_01_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %304 = phi i8* [ %305, %.lr.ph.i10.i.i ], [ %289, %301 ]*/
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd0 & main_301_303 == 1'd1)
begin
main__lr_ph_i10_i_i_304_phi_temp <= main_287_289_reg;
if (^reset !== 1'bX && ^(main_287_289_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_304_phi_temp"); $finish; end
end
/* main: %.lr.ph.i10.i.i*/
/* %304 = phi i8* [ %305, %.lr.ph.i10.i.i ], [ %289, %301 ]*/
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i10_i_i_exitcond7_i_i_i_reg == 1'd0)
begin
main__lr_ph_i10_i_i_304_phi_temp <= main__lr_ph_i10_i_i_305_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_305_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_304_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %i.13.i.i.i = phi i32 [ %308, %.lr.ph.i10.i.i ], [ 0, %301 ]*/
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd0 & main_301_303 == 1'd1)
begin
main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.i10.i.i*/
/* %i.13.i.i.i = phi i32 [ %308, %.lr.ph.i10.i.i ], [ 0, %301 ]*/
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i10_i_i_exitcond7_i_i_i_reg == 1'd0)
begin
main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp <= main__lr_ph_i10_i_i_308_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_308_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %._crit_edge.i12.i.i*/
/* %ReadBuf.7 = phi i8* [ %289, %301 ], [ %305, %.lr.ph.i10.i.i ]*/
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd0 & main_301_303 == 1'd0)
begin
main___crit_edge_i12_i_i_ReadBuf_7_phi_temp <= main_287_289_reg;
if (^reset !== 1'bX && ^(main_287_289_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i12_i_i_ReadBuf_7_phi_temp"); $finish; end
end
/* main: %._crit_edge.i12.i.i*/
/* %ReadBuf.7 = phi i8* [ %289, %301 ], [ %305, %.lr.ph.i10.i.i ]*/
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i10_i_i_exitcond7_i_i_i_reg == 1'd1)
begin
main___crit_edge_i12_i_i_ReadBuf_7_phi_temp <= main__lr_ph_i10_i_i_305_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_305_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i12_i_i_ReadBuf_7_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd1)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp <= main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd1)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp <= main_351_352_reg;
if (^reset !== 1'bX && ^(main_351_352_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %330 = phi i8* [ %ReadBuf.8, %.us-lcssa.us.i.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd1)
begin
main__lr_ph_i15_i_i_330_phi_temp <= main_312_317_reg;
if (^reset !== 1'bX && ^(main_312_317_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_330_phi_temp"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %330 = phi i8* [ %ReadBuf.8, %.us-lcssa.us.i.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd1)
begin
main__lr_ph_i15_i_i_330_phi_temp <= main__us_lcssa_us_i_i_i_ReadBuf_8;
if (^reset !== 1'bX && ^(main__us_lcssa_us_i_i_i_ReadBuf_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_330_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd1)
begin
main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp <= main_312_322_reg;
if (^reset !== 1'bX && ^(main_312_322_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd1)
begin
main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp <= main__us_lcssa_us_i_i_i___i_i_i;
if (^reset !== 1'bX && ^(main__us_lcssa_us_i_i_i___i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %354 = phi i8* [ %355, %.split.us.i.i.i ], [ %331, %351 ]*/
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd1)
begin
main__split_us_i_i_i_354_phi_temp <= main__lr_ph_i15_i_i_331_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_331_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_354_phi_temp"); $finish; end
end
/* main: %.split.us.i.i.i*/
/* %354 = phi i8* [ %355, %.split.us.i.i.i ], [ %331, %351 ]*/
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd0 & main__split_us_i_i_i_exitcond_i17_i_i_reg == 1'd0)
begin
main__split_us_i_i_i_354_phi_temp <= main__split_us_i_i_i_355_reg;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_355_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_354_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %i.01.us.i.i.i = phi i32 [ %360, %.split.us.i.i.i ], [ 0, %351 ]*/
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd1)
begin
main__split_us_i_i_i_i_01_us_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_i_01_us_i_i_i_phi_temp"); $finish; end
end
/* main: %.split.us.i.i.i*/
/* %i.01.us.i.i.i = phi i32 [ %360, %.split.us.i.i.i ], [ 0, %351 ]*/
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd0 & main__split_us_i_i_i_exitcond_i17_i_i_reg == 1'd0)
begin
main__split_us_i_i_i_i_01_us_i_i_i_phi_temp <= main__split_us_i_i_i_360_reg;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_360_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_i_01_us_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %361 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %331, %351 ]*/
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd0)
begin
main___split_crit_edge_i_i_i_361_phi_temp <= main__lr_ph_i15_i_i_331_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_331_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_361_phi_temp"); $finish; end
end
/* main: %..split_crit_edge.i.i.i*/
/* %361 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %331, %351 ]*/
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd0 & main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg == 1'd0)
begin
main___split_crit_edge_i_i_i_361_phi_temp <= main___split_crit_edge_i_i_i_366_reg;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_366_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_361_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %i.01.i.i.i = phi i32 [ %372, %..split_crit_edge.i.i.i ], [ 0, %351 ]*/
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd0)
begin
main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp"); $finish; end
end
/* main: %..split_crit_edge.i.i.i*/
/* %i.01.i.i.i = phi i32 [ %372, %..split_crit_edge.i.i.i ], [ 0, %351 ]*/
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd0 & main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg == 1'd0)
begin
main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp <= main___split_crit_edge_i_i_i_372_reg;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_372_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.us-lcssa.us.i.i.i*/
/* %ReadBuf.8 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %355, %.split.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd0 & main__split_us_i_i_i_exitcond_i17_i_i_reg == 1'd1)
begin
main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp <= main__split_us_i_i_i_355_reg;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_355_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp"); $finish; end
end
/* main: %.us-lcssa.us.i.i.i*/
/* %ReadBuf.8 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %355, %.split.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd0 & main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg == 1'd1)
begin
main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp <= main___split_crit_edge_i_i_i_366_reg;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_366_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* %CurrentMCU.026.i.i = phi i32 [ %tmp143.i.i, %447 ], [ 0, %.preheader21.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB92_356 & memory_controller_waitrequest == 1'd0)
begin
main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp"); $finish; end
end
/* main: %.preheader21.i.i*/
/* %CurrentMCU.026.i.i = phi i32 [ %tmp143.i.i, %447 ], [ 0, %.preheader21.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB113_405 & memory_controller_waitrequest == 1'd0 & main_447_448 == 1'd1)
begin
main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp <= main__preheader21_i_i_tmp143_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader21_i_i_tmp143_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_function_call_365 & memory_controller_waitrequest == 1'd0)
begin
main_392_i_01_i_i1_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_i_01_i_i1_i_phi_temp"); $finish; end
end
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_F_main_BB103_382 & memory_controller_waitrequest == 1'd0 & main_425_exitcond53_i_i_reg == 1'd0)
begin
main_392_i_01_i_i1_i_phi_temp <= main_425_426_reg;
if (^reset !== 1'bX && ^(main_425_426_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_i_01_i_i1_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB94_371 & memory_controller_waitrequest == 1'd0 & main_392_411 == 1'd1)
begin
main_415_r_0_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_phi_temp"); $finish; end
end
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB95_372 & memory_controller_waitrequest == 1'd0 & main_412_413 == 1'd0)
begin
main_415_r_0_i_i_i_phi_temp <= main_392_402_reg;
if (^reset !== 1'bX && ^(main_392_402_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_phi_temp"); $finish; end
end
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB96_373 & memory_controller_waitrequest == 1'd0)
begin
main_415_r_0_i_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB97_374 & memory_controller_waitrequest == 1'd0 & main_415_416 == 1'd1)
begin
main_420_g_0_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_phi_temp"); $finish; end
end
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB98_375 & memory_controller_waitrequest == 1'd0 & main_417_418 == 1'd0)
begin
main_420_g_0_i_i_i_phi_temp <= main_392_407_reg;
if (^reset !== 1'bX && ^(main_392_407_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_phi_temp"); $finish; end
end
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB99_376 & memory_controller_waitrequest == 1'd0)
begin
main_420_g_0_i_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB100_377 & memory_controller_waitrequest == 1'd0 & main_420_421 == 1'd1)
begin
main_425_b_0_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_phi_temp"); $finish; end
end
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB101_378 & memory_controller_waitrequest == 1'd0 & main_422_423 == 1'd0)
begin
main_425_b_0_i_i_i_phi_temp <= main_392_410_reg;
if (^reset !== 1'bX && ^(main_392_410_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_phi_temp"); $finish; end
end
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB102_379 & memory_controller_waitrequest == 1'd0)
begin
main_425_b_0_i_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %432*/
/* %433 = phi i32 [ %.pre.i.i, %YuvToRgb.exit.loopexit.i.i ], [ %446, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB104_388 & memory_controller_waitrequest == 1'd0)
begin
main_432_433_phi_temp <= main_YuvToRgb_exit_loopexit_i_i__pre_i_i_reg;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i__pre_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_433_phi_temp"); $finish; end
end
/* main: %432*/
/* %433 = phi i32 [ %.pre.i.i, %YuvToRgb.exit.loopexit.i.i ], [ %446, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB112_404 & memory_controller_waitrequest == 1'd0 & main_WriteBlock_exit_i_i_exitcond116_i_i == 1'd0)
begin
main_432_433_phi_temp <= main_WriteBlock_exit_i_i_446;
if (^reset !== 1'bX && ^(main_WriteBlock_exit_i_i_446) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_433_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB104_388 & memory_controller_waitrequest == 1'd0)
begin
main_432_i_324_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_phi_temp"); $finish; end
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB112_404 & memory_controller_waitrequest == 1'd0 & main_WriteBlock_exit_i_i_exitcond116_i_i == 1'd0)
begin
main_432_i_324_i_i_phi_temp <= main_432_tmp141_i_i_reg;
if (^reset !== 1'bX && ^(main_432_tmp141_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB106_394 & memory_controller_waitrequest == 1'd0)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB107_395 & memory_controller_waitrequest == 1'd0 & main_439_exitcond93_i_i == 1'd0)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp <= main_439_indvar_next18_i_i_i_i;
if (^reset !== 1'bX && ^(main_439_indvar_next18_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %440*/
/* %indvar.i.i.i.i = phi i32 [ 0, %.lr.ph.us.i.i.i.i ], [ %indvar.next.i.i.i.i, %440 ]*/
if (cur_state == LEGUP_F_main_BB108_398 & memory_controller_waitrequest == 1'd0 & main_440_exitcond70_i_i_reg == 1'd0)
begin
main_440_indvar_i_i_i_i_phi_temp <= main_440_indvar_next_i_i_i_i_reg;
if (^reset !== 1'bX && ^(main_440_indvar_next_i_i_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_440_indvar_i_i_i_i_phi_temp"); $finish; end
end
/* main: %440*/
/* %indvar.i.i.i.i = phi i32 [ 0, %.lr.ph.us.i.i.i.i ], [ %indvar.next.i.i.i.i, %440 ]*/
if (cur_state == LEGUP_F_main_BB109_399 & memory_controller_waitrequest == 1'd0)
begin
main_440_indvar_i_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_440_indvar_i_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %WriteBlock.exit.i.i*/
/* %446 = phi i32 [ %443, %WriteOneBlock.exit.i.i.i ], [ 0, %445 ]*/
if (cur_state == LEGUP_F_main_BB110_402 & memory_controller_waitrequest == 1'd0 & main_WriteOneBlock_exit_i_i_i_444 == 1'd1)
begin
main_WriteBlock_exit_i_i_446_phi_temp <= main_WriteOneBlock_exit_i_i_i_443;
if (^reset !== 1'bX && ^(main_WriteOneBlock_exit_i_i_i_443) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_WriteBlock_exit_i_i_446_phi_temp"); $finish; end
end
/* main: %WriteBlock.exit.i.i*/
/* %446 = phi i32 [ %443, %WriteOneBlock.exit.i.i.i ], [ 0, %445 ]*/
if (cur_state == LEGUP_F_main_BB111_403 & memory_controller_waitrequest == 1'd0)
begin
main_WriteBlock_exit_i_i_446_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_WriteBlock_exit_i_i_446_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_F_main_BB115_407 & memory_controller_waitrequest == 1'd0)
begin
main__preheader_i_i_indvar_i7_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_indvar_i7_i_phi_temp"); $finish; end
end
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_function_call_453 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_490_reg == 1'd1)
begin
main__preheader_i_i_indvar_i7_i_phi_temp <= main__loopexit_i_i_indvar_next_i_i_reg;
if (^reset !== 1'bX && ^(main__loopexit_i_i_indvar_next_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_indvar_i7_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_function_call_425 & memory_controller_waitrequest == 1'd0)
begin
main__preheader16_i_i_i_517_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_phi_temp"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB128_444 & memory_controller_waitrequest == 1'd0 & main_YuvToRgb_exit13_i_i_exitcond35_i_i == 1'd0)
begin
main__preheader16_i_i_i_517_i_i_phi_temp <= main_YuvToRgb_exit13_i_i_489;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit13_i_i_489) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426 & memory_controller_waitrequest == 1'd0)
begin
main_454_i_01_i2_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_i_01_i2_i_i_phi_temp"); $finish; end
end
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB127_443 & memory_controller_waitrequest == 1'd0 & main_487_exitcond_i_i_reg == 1'd0)
begin
main_454_i_01_i2_i_i_phi_temp <= main_487_488_reg;
if (^reset !== 1'bX && ^(main_487_488_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_i_01_i2_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB118_432 & memory_controller_waitrequest == 1'd0 & main_454_473 == 1'd1)
begin
main_477_r_0_i9_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_phi_temp"); $finish; end
end
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB119_433 & memory_controller_waitrequest == 1'd0 & main_474_475 == 1'd0)
begin
main_477_r_0_i9_i_i_phi_temp <= main_454_464_reg;
if (^reset !== 1'bX && ^(main_454_464_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_phi_temp"); $finish; end
end
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB120_434 & memory_controller_waitrequest == 1'd0)
begin
main_477_r_0_i9_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB121_435 & memory_controller_waitrequest == 1'd0 & main_477_478 == 1'd1)
begin
main_482_g_0_i10_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_phi_temp"); $finish; end
end
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB122_436 & memory_controller_waitrequest == 1'd0 & main_479_480 == 1'd0)
begin
main_482_g_0_i10_i_i_phi_temp <= main_454_469_reg;
if (^reset !== 1'bX && ^(main_454_469_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_phi_temp"); $finish; end
end
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB123_437 & memory_controller_waitrequest == 1'd0)
begin
main_482_g_0_i10_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB124_438 & memory_controller_waitrequest == 1'd0 & main_482_483 == 1'd1)
begin
main_487_b_0_i11_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_phi_temp"); $finish; end
end
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB125_439 & memory_controller_waitrequest == 1'd0 & main_484_485 == 1'd0)
begin
main_487_b_0_i11_i_i_phi_temp <= main_454_472_reg;
if (^reset !== 1'bX && ^(main_454_472_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_phi_temp"); $finish; end
end
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB126_440 & memory_controller_waitrequest == 1'd0)
begin
main_487_b_0_i11_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB130_456 & memory_controller_waitrequest == 1'd0)
begin
main_491_492_phi_temp <= main_decode_start_exit_i_main_result_promoted3_i;
if (^reset !== 1'bX && ^(main_decode_start_exit_i_main_result_promoted3_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_492_phi_temp"); $finish; end
end
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd0)
begin
main_491_492_phi_temp <= main_491_497;
if (^reset !== 1'bX && ^(main_491_497) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_492_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %491*/
/* %j.01.i = phi i32 [ 0, %decode_start.exit.i ], [ %498, %491 ]*/
if (cur_state == LEGUP_F_main_BB130_456 & memory_controller_waitrequest == 1'd0)
begin
main_491_j_01_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_j_01_i_phi_temp"); $finish; end
end
/* main: %491*/
/* %j.01.i = phi i32 [ 0, %decode_start.exit.i ], [ %498, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd0)
begin
main_491_j_01_i_phi_temp <= main_491_498_reg;
if (^reset !== 1'bX && ^(main_491_498_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_j_01_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd1)
begin
main__preheader_1_i_499_phi_temp <= main_491_497;
if (^reset !== 1'bX && ^(main_491_497) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_499_phi_temp"); $finish; end
end
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd0)
begin
main__preheader_1_i_499_phi_temp <= main__preheader_1_i_504;
if (^reset !== 1'bX && ^(main__preheader_1_i_504) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_499_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %j.01.1.i = phi i32 [ %505, %.preheader.1.i ], [ 0, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd1)
begin
main__preheader_1_i_j_01_1_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_j_01_1_i_phi_temp"); $finish; end
end
/* main: %.preheader.1.i*/
/* %j.01.1.i = phi i32 [ %505, %.preheader.1.i ], [ 0, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd0)
begin
main__preheader_1_i_j_01_1_i_phi_temp <= main__preheader_1_i_505_reg;
if (^reset !== 1'bX && ^(main__preheader_1_i_505_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_j_01_1_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd1)
begin
main__preheader_2_i_513_phi_temp <= main__preheader_1_i_504;
if (^reset !== 1'bX && ^(main__preheader_1_i_504) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_513_phi_temp"); $finish; end
end
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_472 & memory_controller_waitrequest == 1'd0 & main__preheader_2_i_exitcond_2_i_reg == 1'd0)
begin
main__preheader_2_i_513_phi_temp <= main__preheader_2_i_518;
if (^reset !== 1'bX && ^(main__preheader_2_i_518) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_513_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %j.01.2.i = phi i32 [ %519, %.preheader.2.i ], [ 0, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd1)
begin
main__preheader_2_i_j_01_2_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_j_01_2_i_phi_temp"); $finish; end
end
/* main: %.preheader.2.i*/
/* %j.01.2.i = phi i32 [ %519, %.preheader.2.i ], [ 0, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_472 & memory_controller_waitrequest == 1'd0 & main__preheader_2_i_exitcond_2_i_reg == 1'd0)
begin
main__preheader_2_i_j_01_2_i_phi_temp <= main__preheader_2_i_519_reg;
if (^reset !== 1'bX && ^(main__preheader_2_i_519_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_j_01_2_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* main: %524*/
/* ret i32 %525*/
if (cur_state == LEGUP_F_main_BB137_477)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
return_val <= 0;
if (^reset !== 1'bX && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
/* main: %524*/
/* ret i32 %525*/
if (cur_state == LEGUP_F_main_BB137_477)
begin
return_val <= main_524_525;
if (^reset !== 1'bX && ^(main_524_525) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
memory_controller_address = huff_make_dhuff_tb_memory_controller_address;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
memory_controller_address = huff_make_dhuff_tb_memory_controller_address;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
memory_controller_address = huff_make_dhuff_tb_memory_controller_address;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
memory_controller_address = huff_make_dhuff_tb_memory_controller_address;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
memory_controller_address = Write4Blocks_memory_controller_address;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
memory_controller_address = Write4Blocks_memory_controller_address;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
memory_controller_address = Write4Blocks_memory_controller_address;
end
/* main: %0*/
/* store i32 0, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB0_1)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %1*/
/* %2 = load i8* %scevgep13.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
memory_controller_address = main_1_scevgep13_i;
end
/* main: %1*/
/* store i8 %2, i8* %c.06.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_4)
begin
memory_controller_address = main_1_c_06_i_reg;
end
/* main: %6*/
/* %8 = load i8* %ReadBuf.1, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_10)
begin
memory_controller_address = main__backedge_i_i_ReadBuf_1_reg;
end
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_11)
begin
memory_controller_address = main_6_7_reg;
end
/* main: %first_marker.exit.i.i*/
/* %16 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %first_marker.exit.i.i*/
/* store i32 %17, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_17)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.loopexit3.i.i.i*/
/* %c.0.in2.i.i.i = load i8* %18, align 1*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
memory_controller_address = main__loopexit3_i_i_i_18;
end
/* main: %.lr.ph.i.i.i*/
/* %c.0.in.i.i.i = load i8* %scevgep.i.i, align 1*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
memory_controller_address = main__lr_ph_i_i_i_scevgep_i_i;
end
/* main: %.loopexit.i.i.i*/
/* %21 = load i8* %scevgep11.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB15_27)
begin
memory_controller_address = main__loopexit_i_i_i_scevgep11_i_i;
end
/* main: %next_marker.exit.i.i*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB17_32)
begin
memory_controller_address = main_next_marker_exit_i_i_25_reg;
end
/* main: %28*/
/* %29 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_35)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %28*/
/* store i32 %30, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_37)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %32*/
/* %34 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
memory_controller_address = main_next_marker_exit_i_i_ReadBuf_2_reg;
end
/* main: %32*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_40)
begin
memory_controller_address = main_32_33_reg;
end
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_41)
begin
memory_controller_address = main_32_37_reg;
end
/* main: %32*/
/* %45 = load i8* %42, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
memory_controller_address = main_32_42_reg;
end
/* main: %32*/
/* %49 = load i8* %44, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
memory_controller_address = main_32_44_reg;
end
/* main: %32*/
/* store i16 %51, i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_45)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* main: %32*/
/* %53 = load i8* %48, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_46)
begin
memory_controller_address = main_32_48_reg;
end
/* main: %32*/
/* %57 = load i8* %52, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_47)
begin
memory_controller_address = main_32_52_reg;
end
/* main: %32*/
/* store i16 %59, i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_49)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_50)
begin
memory_controller_address = main_32_56_reg;
end
/* main: %32*/
/* %65 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* main: %32*/
/* %68 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_55)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* main: %74*/
/* %75 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_58)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %74*/
/* store i32 %76, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_60)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %79*/
/* %80 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_62)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %79*/
/* store i32 %81, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_64)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %82*/
/* %83 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB24_65)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* main: %85*/
/* %86 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_68)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %85*/
/* store i32 %87, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_70)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %88*/
/* %89 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB26_71)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* main: %91*/
/* %92 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_74)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %91*/
/* store i32 %93, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_76)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.preheader.i.i.i.thread*/
/* %96 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_78)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.preheader.i.i.i.thread*/
/* store i32 %97, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_80)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %tmp.i.i.i, i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep_i_i_i;
end
/* main: %.lr.ph.i1.i.i*/
/* %100 = load i8* %ReadBuf.3, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_83)
begin
memory_controller_address = main__lr_ph_i1_i_i_ReadBuf_3_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %100, i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_85)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep3_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %102 = load i8* %99, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_86)
begin
memory_controller_address = main__lr_ph_i1_i_i_99_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %103, i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep4_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %104, i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_89)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep5_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %106 = load i8* %101, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_90)
begin
memory_controller_address = main__lr_ph_i1_i_i_101_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %106, i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep6_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %109 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_93)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep3_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %112 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_96)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep4_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %115 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_99)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep5_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %118 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_102)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep6_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %121 = load i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_105)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %123 = load i32* %scevgep7.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB31_106)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep7_i_i_i_reg;
end
/* main: %125*/
/* %126 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_109)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %125*/
/* store i32 %127, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_111)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %128*/
/* %129 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB33_112)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep3_i_i_i_reg;
end
/* main: %128*/
/* %131 = load i32* %scevgep8.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB33_113)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep8_i_i_i_reg;
end
/* main: %133*/
/* %134 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_116)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %133*/
/* store i32 %135, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_118)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %136*/
/* %137 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB35_119)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep4_i_i_i_reg;
end
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB35_120)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep9_i_i_i_reg;
end
/* main: %141*/
/* %142 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_123)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %141*/
/* store i32 %143, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_125)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %144*/
/* %145 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB37_126)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep5_i_i_i_reg;
end
/* main: %148*/
/* %149 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_129)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %148*/
/* store i32 %150, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_131)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %151*/
/* %152 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB39_132)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep6_i_i_i_reg;
end
/* main: %151*/
/* %154 = load i32* %scevgep11.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB39_133)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep11_i_i_i_reg;
end
/* main: %156*/
/* %157 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_136)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %156*/
/* store i32 %158, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_138)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %._crit_edge.i.i.i*/
/* %161 = load i8* getelementptr inbounds ([3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 0), align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
memory_controller_address = `TAG_g_p_jinfo_comps_info_h_samp_factor_a;
end
/* main: %167*/
/* %169 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
memory_controller_address = main_next_marker_exit_i_i_ReadBuf_2_reg;
end
/* main: %167*/
/* %173 = load i8* %168, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_146)
begin
memory_controller_address = main_167_168_reg;
end
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_147)
begin
memory_controller_address = main_167_172_reg;
end
/* main: %183*/
/* %184 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_150)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %183*/
/* store i32 %185, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_152)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %188*/
/* %189 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_154)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %188*/
/* store i32 %190, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_156)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %194*/
/* %196 = load i8* %ReadBuf.5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
memory_controller_address = main__preheader5_i_i_i_ReadBuf_5_reg;
end
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_160)
begin
memory_controller_address = main_194_195_reg;
end
/* main: %203*/
/* %204 = load i8* %scevgep9.i4.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB53_164)
begin
memory_controller_address = main_203_scevgep9_i4_i_i;
end
/* main: %211*/
/* %212 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %211*/
/* store i32 %213, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_171)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %211*/
/* store i8 %214, i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_172)
begin
memory_controller_address = main_211_scevgep8_i5_i_i_reg;
end
/* main: %211*/
/* store i8 %215, i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
memory_controller_address = main_211_scevgep7_i6_i_i_reg;
end
/* main: %211*/
/* %217 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_174)
begin
memory_controller_address = main_211_scevgep8_i5_i_i_reg;
end
/* main: %211*/
/* %220 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_177)
begin
memory_controller_address = main_211_scevgep7_i6_i_i_reg;
end
/* main: %211*/
/* %224 = load i32* %223, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_180)
begin
memory_controller_address = main_211_223_reg;
end
/* main: %226*/
/* %227 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_183)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %226*/
/* store i32 %228, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_185)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %229*/
/* %230 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB58_186)
begin
memory_controller_address = main_211_scevgep8_i5_i_i_reg;
end
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB58_187)
begin
memory_controller_address = main_229_232_reg;
end
/* main: %235*/
/* %236 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_190)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %235*/
/* store i32 %237, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_192)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %238*/
/* %239 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB60_193)
begin
memory_controller_address = main_211_scevgep7_i6_i_i_reg;
end
/* main: %242*/
/* %243 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_196)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %242*/
/* store i32 %244, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_198)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %248*/
/* %250 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
memory_controller_address = main_next_marker_exit_i_i_ReadBuf_2_reg;
end
/* main: %248*/
/* %254 = load i8* %249, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_202)
begin
memory_controller_address = main_248_249_reg;
end
/* main: %248*/
/* %260 = load i32* %4, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB64_205)
begin
memory_controller_address = main__backedge_i_i_outer_4_reg;
end
/* main: %262*/
/* %263 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_208)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %262*/
/* store i32 %264, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_210)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.lr.ph5.i.i.i*/
/* %267 = load i8* %ReadBuf.6, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
memory_controller_address = main__lr_ph5_i_i_i_ReadBuf_6;
end
/* main: %.lr.ph5.i.i.i*/
/* %271 = load i32* %270, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB67_215)
begin
memory_controller_address = main__lr_ph5_i_i_i_270_reg;
end
/* main: %273*/
/* %274 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_218)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %273*/
/* store i32 %275, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_220)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %287*/
/* %290 = load i8* %288, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
memory_controller_address = main_287_288;
end
/* main: %287*/
/* store i32 %291, i32* %scevgep.i9.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
memory_controller_address = main_287_scevgep_i9_i_i_reg;
end
/* main: %293*/
/* %296 = load i32* %295, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB74_229)
begin
memory_controller_address = main_293_295_reg;
end
/* main: %298*/
/* %299 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_232)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %298*/
/* store i32 %300, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_234)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.lr.ph.i10.i.i*/
/* %306 = load i8* %304, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
memory_controller_address = main__lr_ph_i10_i_i_304;
end
/* main: %.lr.ph.i10.i.i*/
/* store i32 %307, i32* %scevgep8.i11.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB77_238)
begin
memory_controller_address = main__lr_ph_i10_i_i_scevgep8_i11_i_i_reg;
end
/* main: %312*/
/* %314 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
memory_controller_address = main_next_marker_exit_i_i_ReadBuf_2_reg;
end
/* main: %312*/
/* %318 = load i8* %313, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_241)
begin
memory_controller_address = main_312_313_reg;
end
/* main: %312*/
/* %324 = load i32* %5, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB79_244)
begin
memory_controller_address = main__backedge_i_i_outer4_5_reg;
end
/* main: %326*/
/* %327 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_247)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %326*/
/* store i32 %328, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_249)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.lr.ph.i15.i.i*/
/* %332 = load i8* %330, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
memory_controller_address = main__lr_ph_i15_i_i_330;
end
/* main: %.lr.ph.i15.i.i*/
/* %339 = load i32* %338, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB82_254)
begin
memory_controller_address = main__lr_ph_i15_i_i_338_reg;
end
/* main: %341*/
/* %342 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_257)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %341*/
/* store i32 %343, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_259)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %344*/
/* %346 = load i32* %345, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB84_260)
begin
memory_controller_address = main_344_345;
end
/* main: %348*/
/* %349 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_263)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %348*/
/* store i32 %350, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_265)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.split.us.i.i.i*/
/* %356 = load i8* %354, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
memory_controller_address = main__split_us_i_i_i_354;
end
/* main: %.split.us.i.i.i*/
/* %358 = load i32* %scevgep.i16.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_268)
begin
memory_controller_address = main__split_us_i_i_i_scevgep_i16_i_i_reg;
end
/* main: %.split.us.i.i.i*/
/* store i32 %357, i32* %359, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_270)
begin
memory_controller_address = main__split_us_i_i_i_359;
end
/* main: %..split_crit_edge.i.i.i*/
/* %363 = load i8* %361, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
memory_controller_address = main___split_crit_edge_i_i_i_361;
end
/* main: %..split_crit_edge.i.i.i*/
/* %367 = load i8* %362, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_272)
begin
memory_controller_address = main___split_crit_edge_i_i_i_362_reg;
end
/* main: %..split_crit_edge.i.i.i*/
/* %370 = load i32* %scevgep4.i18.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_273)
begin
memory_controller_address = main___split_crit_edge_i_i_i_scevgep4_i18_i_i_reg;
end
/* main: %..split_crit_edge.i.i.i*/
/* store i32 %369, i32* %371, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_275)
begin
memory_controller_address = main___split_crit_edge_i_i_i_371;
end
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_278)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* main: %read_markers.exit.i*/
/* store i32 %383, i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
memory_controller_address = `TAG_g_p_jinfo_MCUWidth_a;
end
/* main: %read_markers.exit.i*/
/* store i32 %385, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_332)
begin
memory_controller_address = `TAG_g_p_jinfo_dc_dhuff_tbl_ml_a;
end
/* main: %read_markers.exit.i*/
/* store i32 %386, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_336)
begin
memory_controller_address = `TAG_g_p_jinfo_dc_dhuff_tbl_ml_a + 4 * 32'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %387, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_340)
begin
memory_controller_address = `TAG_g_p_jinfo_ac_dhuff_tbl_ml_a;
end
/* main: %read_markers.exit.i*/
/* store i32 %388, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_344)
begin
memory_controller_address = `TAG_g_p_jinfo_ac_dhuff_tbl_ml_a + 4 * 32'd1;
end
/* main: %read_markers.exit.i*/
/* store i8* %p_jinfo_jpeg_data.0, i8** @CurHuffReadBuf, align 4, !tbaa !4*/
if (cur_state == LEGUP_F_main_BB90_345)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_346)
begin
memory_controller_address = main_read_markers_exit_i_scevgep148_i_i_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.1.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_347)
begin
memory_controller_address = main_read_markers_exit_i_scevgep148_1_i_i_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.2.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_348)
begin
memory_controller_address = main_read_markers_exit_i_scevgep148_2_i_i_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_349)
begin
memory_controller_address = `TAG_g_OutData_comp_vpos_a;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_350)
begin
memory_controller_address = `TAG_g_OutData_comp_hpos_a;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_351)
begin
memory_controller_address = `TAG_g_OutData_comp_vpos_a + 4 * 32'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_352)
begin
memory_controller_address = `TAG_g_OutData_comp_hpos_a + 4 * 32'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_353)
begin
memory_controller_address = `TAG_g_OutData_comp_vpos_a + 4 * 32'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_354)
begin
memory_controller_address = `TAG_g_OutData_comp_hpos_a + 4 * 32'd2;
end
/* main: %392*/
/* %393 = load i32* %scevgep.i.i3.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
memory_controller_address = main_392_scevgep_i_i3_i;
end
/* main: %392*/
/* %394 = load i32* %scevgep2.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_367)
begin
memory_controller_address = main_392_scevgep2_i_i_i_reg;
end
/* main: %392*/
/* %396 = load i32* %scevgep3.i.i2.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_368)
begin
memory_controller_address = main_392_scevgep3_i_i2_i_reg;
end
/* main: %425*/
/* store i32 %r.0.i.i.i, i32* %scevgep4.i.i6.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
memory_controller_address = main_392_scevgep4_i_i6_i_reg;
end
/* main: %425*/
/* store i32 %g.0.i.i.i, i32* %scevgep5.i.i5.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_381)
begin
memory_controller_address = main_392_scevgep5_i_i5_i_reg;
end
/* main: %425*/
/* store i32 %b.0.i.i.i, i32* %scevgep6.i.i4.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_382)
begin
memory_controller_address = main_392_scevgep6_i_i4_i_reg;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %427 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_383)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %429 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_384)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
memory_controller_address = `TAG_g_OutData_comp_hpos_a;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_386)
begin
memory_controller_address = `TAG_g_p_jinfo_MCUWidth_a;
end
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
memory_controller_address = main_432_scevgep139_i_i;
end
/* main: %440*/
/* %441 = load i32* %.14.us.i.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
memory_controller_address = main_440__14_us_i_i_i_i;
end
/* main: %440*/
/* store i8 %442, i8* %scevgep24.i.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB108_398)
begin
memory_controller_address = main_440_scevgep24_i_i_i_i_reg;
end
/* main: %WriteOneBlock.exit.i.i.i*/
/* %443 = load i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB110_400)
begin
memory_controller_address = main_432_scevgep142_i_i_reg;
end
/* main: %445*/
/* store i32 0, i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB111_403)
begin
memory_controller_address = main_432_scevgep142_i_i_reg;
end
/* main: %454*/
/* %455 = load i32* %scevgep.i3.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
memory_controller_address = main_454_scevgep_i3_i_i;
end
/* main: %454*/
/* %456 = load i32* %scevgep2.i4.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_428)
begin
memory_controller_address = main_454_scevgep2_i4_i_i_reg;
end
/* main: %454*/
/* %458 = load i32* %scevgep3.i5.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_429)
begin
memory_controller_address = main_454_scevgep3_i5_i_i_reg;
end
/* main: %487*/
/* store i32 %r.0.i9.i.i, i32* %scevgep4.i6.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
memory_controller_address = main_454_scevgep4_i6_i_i_reg;
end
/* main: %487*/
/* store i32 %g.0.i10.i.i, i32* %scevgep5.i7.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_442)
begin
memory_controller_address = main_454_scevgep5_i7_i_i_reg;
end
/* main: %487*/
/* store i32 %b.0.i11.i.i, i32* %scevgep6.i8.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_443)
begin
memory_controller_address = main_454_scevgep6_i8_i_i_reg;
end
/* main: %decode_start.exit.i*/
/* %main_result.promoted3.i = load i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB130_454)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
memory_controller_address = main_491_scevgep_i;
end
/* main: %491*/
/* %494 = load i8* %scevgep7.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_458)
begin
memory_controller_address = main_491_scevgep7_i_reg;
end
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
memory_controller_address = main__preheader_1_i_scevgep_1_i;
end
/* main: %.preheader.1.i*/
/* %501 = load i8* %scevgep7.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_462)
begin
memory_controller_address = main__preheader_1_i_scevgep7_1_i_reg;
end
/* main: %jpeg2bmp_main.exit*/
/* store i32 %.storemerge, i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %jpeg2bmp_main.exit*/
/* %511 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB133_466)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
memory_controller_address = main__preheader_2_i_scevgep_2_i;
end
/* main: %.preheader.2.i*/
/* %515 = load i8* %scevgep7.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_470)
begin
memory_controller_address = main__preheader_2_i_scevgep7_2_i_reg;
end
/* main: %524*/
/* %525 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB137_475)
begin
memory_controller_address = `TAG_g_main_result_a;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
memory_controller_enable = huff_make_dhuff_tb_memory_controller_enable;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
memory_controller_enable = huff_make_dhuff_tb_memory_controller_enable;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
memory_controller_enable = huff_make_dhuff_tb_memory_controller_enable;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
memory_controller_enable = huff_make_dhuff_tb_memory_controller_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
memory_controller_enable = Write4Blocks_memory_controller_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
memory_controller_enable = Write4Blocks_memory_controller_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
memory_controller_enable = Write4Blocks_memory_controller_enable;
end
/* main: %0*/
/* store i32 0, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB0_1)
begin
memory_controller_enable = 1'd1;
end
/* main: %1*/
/* %2 = load i8* %scevgep13.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
memory_controller_enable = 1'd1;
end
/* main: %1*/
/* store i8 %2, i8* %c.06.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_4)
begin
memory_controller_enable = 1'd1;
end
/* main: %6*/
/* %8 = load i8* %ReadBuf.1, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_10)
begin
memory_controller_enable = 1'd1;
end
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_11)
begin
memory_controller_enable = 1'd1;
end
/* main: %first_marker.exit.i.i*/
/* %16 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
memory_controller_enable = 1'd1;
end
/* main: %first_marker.exit.i.i*/
/* store i32 %17, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_17)
begin
memory_controller_enable = 1'd1;
end
/* main: %.loopexit3.i.i.i*/
/* %c.0.in2.i.i.i = load i8* %18, align 1*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i.i.i*/
/* %c.0.in.i.i.i = load i8* %scevgep.i.i, align 1*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
memory_controller_enable = 1'd1;
end
/* main: %.loopexit.i.i.i*/
/* %21 = load i8* %scevgep11.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB15_27)
begin
memory_controller_enable = 1'd1;
end
/* main: %next_marker.exit.i.i*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB17_32)
begin
memory_controller_enable = 1'd1;
end
/* main: %28*/
/* %29 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_35)
begin
memory_controller_enable = 1'd1;
end
/* main: %28*/
/* store i32 %30, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_37)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %34 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_40)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_41)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %45 = load i8* %42, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %49 = load i8* %44, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* store i16 %51, i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_45)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %53 = load i8* %48, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_46)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %57 = load i8* %52, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_47)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* store i16 %59, i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_49)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_50)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %65 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %68 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_55)
begin
memory_controller_enable = 1'd1;
end
/* main: %74*/
/* %75 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_58)
begin
memory_controller_enable = 1'd1;
end
/* main: %74*/
/* store i32 %76, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_60)
begin
memory_controller_enable = 1'd1;
end
/* main: %79*/
/* %80 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_62)
begin
memory_controller_enable = 1'd1;
end
/* main: %79*/
/* store i32 %81, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_64)
begin
memory_controller_enable = 1'd1;
end
/* main: %82*/
/* %83 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB24_65)
begin
memory_controller_enable = 1'd1;
end
/* main: %85*/
/* %86 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_68)
begin
memory_controller_enable = 1'd1;
end
/* main: %85*/
/* store i32 %87, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_70)
begin
memory_controller_enable = 1'd1;
end
/* main: %88*/
/* %89 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB26_71)
begin
memory_controller_enable = 1'd1;
end
/* main: %91*/
/* %92 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_74)
begin
memory_controller_enable = 1'd1;
end
/* main: %91*/
/* store i32 %93, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_76)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.i.i.i.thread*/
/* %96 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_78)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.i.i.i.thread*/
/* store i32 %97, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_80)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %tmp.i.i.i, i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %100 = load i8* %ReadBuf.3, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_83)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %100, i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_85)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %102 = load i8* %99, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_86)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %103, i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %104, i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_89)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %106 = load i8* %101, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_90)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %106, i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %109 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_93)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %112 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_96)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %115 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_99)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %118 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_102)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %121 = load i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_105)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %123 = load i32* %scevgep7.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB31_106)
begin
memory_controller_enable = 1'd1;
end
/* main: %125*/
/* %126 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_109)
begin
memory_controller_enable = 1'd1;
end
/* main: %125*/
/* store i32 %127, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_111)
begin
memory_controller_enable = 1'd1;
end
/* main: %128*/
/* %129 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB33_112)
begin
memory_controller_enable = 1'd1;
end
/* main: %128*/
/* %131 = load i32* %scevgep8.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB33_113)
begin
memory_controller_enable = 1'd1;
end
/* main: %133*/
/* %134 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_116)
begin
memory_controller_enable = 1'd1;
end
/* main: %133*/
/* store i32 %135, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_118)
begin
memory_controller_enable = 1'd1;
end
/* main: %136*/
/* %137 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB35_119)
begin
memory_controller_enable = 1'd1;
end
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB35_120)
begin
memory_controller_enable = 1'd1;
end
/* main: %141*/
/* %142 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_123)
begin
memory_controller_enable = 1'd1;
end
/* main: %141*/
/* store i32 %143, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_125)
begin
memory_controller_enable = 1'd1;
end
/* main: %144*/
/* %145 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB37_126)
begin
memory_controller_enable = 1'd1;
end
/* main: %148*/
/* %149 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_129)
begin
memory_controller_enable = 1'd1;
end
/* main: %148*/
/* store i32 %150, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_131)
begin
memory_controller_enable = 1'd1;
end
/* main: %151*/
/* %152 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB39_132)
begin
memory_controller_enable = 1'd1;
end
/* main: %151*/
/* %154 = load i32* %scevgep11.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB39_133)
begin
memory_controller_enable = 1'd1;
end
/* main: %156*/
/* %157 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_136)
begin
memory_controller_enable = 1'd1;
end
/* main: %156*/
/* store i32 %158, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_138)
begin
memory_controller_enable = 1'd1;
end
/* main: %._crit_edge.i.i.i*/
/* %161 = load i8* getelementptr inbounds ([3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 0), align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
memory_controller_enable = 1'd1;
end
/* main: %167*/
/* %169 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
memory_controller_enable = 1'd1;
end
/* main: %167*/
/* %173 = load i8* %168, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_146)
begin
memory_controller_enable = 1'd1;
end
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_147)
begin
memory_controller_enable = 1'd1;
end
/* main: %183*/
/* %184 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_150)
begin
memory_controller_enable = 1'd1;
end
/* main: %183*/
/* store i32 %185, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_152)
begin
memory_controller_enable = 1'd1;
end
/* main: %188*/
/* %189 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_154)
begin
memory_controller_enable = 1'd1;
end
/* main: %188*/
/* store i32 %190, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_156)
begin
memory_controller_enable = 1'd1;
end
/* main: %194*/
/* %196 = load i8* %ReadBuf.5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
memory_controller_enable = 1'd1;
end
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_160)
begin
memory_controller_enable = 1'd1;
end
/* main: %203*/
/* %204 = load i8* %scevgep9.i4.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB53_164)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* %212 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* store i32 %213, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_171)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* store i8 %214, i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_172)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* store i8 %215, i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* %217 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_174)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* %220 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_177)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* %224 = load i32* %223, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_180)
begin
memory_controller_enable = 1'd1;
end
/* main: %226*/
/* %227 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_183)
begin
memory_controller_enable = 1'd1;
end
/* main: %226*/
/* store i32 %228, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_185)
begin
memory_controller_enable = 1'd1;
end
/* main: %229*/
/* %230 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB58_186)
begin
memory_controller_enable = 1'd1;
end
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB58_187)
begin
memory_controller_enable = 1'd1;
end
/* main: %235*/
/* %236 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_190)
begin
memory_controller_enable = 1'd1;
end
/* main: %235*/
/* store i32 %237, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_192)
begin
memory_controller_enable = 1'd1;
end
/* main: %238*/
/* %239 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB60_193)
begin
memory_controller_enable = 1'd1;
end
/* main: %242*/
/* %243 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_196)
begin
memory_controller_enable = 1'd1;
end
/* main: %242*/
/* store i32 %244, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_198)
begin
memory_controller_enable = 1'd1;
end
/* main: %248*/
/* %250 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
memory_controller_enable = 1'd1;
end
/* main: %248*/
/* %254 = load i8* %249, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_202)
begin
memory_controller_enable = 1'd1;
end
/* main: %248*/
/* %260 = load i32* %4, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB64_205)
begin
memory_controller_enable = 1'd1;
end
/* main: %262*/
/* %263 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_208)
begin
memory_controller_enable = 1'd1;
end
/* main: %262*/
/* store i32 %264, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_210)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph5.i.i.i*/
/* %267 = load i8* %ReadBuf.6, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph5.i.i.i*/
/* %271 = load i32* %270, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB67_215)
begin
memory_controller_enable = 1'd1;
end
/* main: %273*/
/* %274 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_218)
begin
memory_controller_enable = 1'd1;
end
/* main: %273*/
/* store i32 %275, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_220)
begin
memory_controller_enable = 1'd1;
end
/* main: %287*/
/* %290 = load i8* %288, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
memory_controller_enable = 1'd1;
end
/* main: %287*/
/* store i32 %291, i32* %scevgep.i9.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
memory_controller_enable = 1'd1;
end
/* main: %293*/
/* %296 = load i32* %295, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB74_229)
begin
memory_controller_enable = 1'd1;
end
/* main: %298*/
/* %299 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_232)
begin
memory_controller_enable = 1'd1;
end
/* main: %298*/
/* store i32 %300, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_234)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i10.i.i*/
/* %306 = load i8* %304, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i10.i.i*/
/* store i32 %307, i32* %scevgep8.i11.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB77_238)
begin
memory_controller_enable = 1'd1;
end
/* main: %312*/
/* %314 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
memory_controller_enable = 1'd1;
end
/* main: %312*/
/* %318 = load i8* %313, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_241)
begin
memory_controller_enable = 1'd1;
end
/* main: %312*/
/* %324 = load i32* %5, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB79_244)
begin
memory_controller_enable = 1'd1;
end
/* main: %326*/
/* %327 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_247)
begin
memory_controller_enable = 1'd1;
end
/* main: %326*/
/* store i32 %328, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_249)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i15.i.i*/
/* %332 = load i8* %330, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i15.i.i*/
/* %339 = load i32* %338, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB82_254)
begin
memory_controller_enable = 1'd1;
end
/* main: %341*/
/* %342 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_257)
begin
memory_controller_enable = 1'd1;
end
/* main: %341*/
/* store i32 %343, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_259)
begin
memory_controller_enable = 1'd1;
end
/* main: %344*/
/* %346 = load i32* %345, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB84_260)
begin
memory_controller_enable = 1'd1;
end
/* main: %348*/
/* %349 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_263)
begin
memory_controller_enable = 1'd1;
end
/* main: %348*/
/* store i32 %350, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_265)
begin
memory_controller_enable = 1'd1;
end
/* main: %.split.us.i.i.i*/
/* %356 = load i8* %354, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
memory_controller_enable = 1'd1;
end
/* main: %.split.us.i.i.i*/
/* %358 = load i32* %scevgep.i16.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_268)
begin
memory_controller_enable = 1'd1;
end
/* main: %.split.us.i.i.i*/
/* store i32 %357, i32* %359, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_270)
begin
memory_controller_enable = 1'd1;
end
/* main: %..split_crit_edge.i.i.i*/
/* %363 = load i8* %361, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
memory_controller_enable = 1'd1;
end
/* main: %..split_crit_edge.i.i.i*/
/* %367 = load i8* %362, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_272)
begin
memory_controller_enable = 1'd1;
end
/* main: %..split_crit_edge.i.i.i*/
/* %370 = load i32* %scevgep4.i18.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_273)
begin
memory_controller_enable = 1'd1;
end
/* main: %..split_crit_edge.i.i.i*/
/* store i32 %369, i32* %371, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_275)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_278)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %383, i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %385, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_332)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %386, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_336)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %387, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_340)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %388, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_344)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i8* %p_jinfo_jpeg_data.0, i8** @CurHuffReadBuf, align 4, !tbaa !4*/
if (cur_state == LEGUP_F_main_BB90_345)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_346)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.1.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_347)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.2.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_348)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_349)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_350)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_351)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_352)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_353)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_354)
begin
memory_controller_enable = 1'd1;
end
/* main: %392*/
/* %393 = load i32* %scevgep.i.i3.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
memory_controller_enable = 1'd1;
end
/* main: %392*/
/* %394 = load i32* %scevgep2.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_367)
begin
memory_controller_enable = 1'd1;
end
/* main: %392*/
/* %396 = load i32* %scevgep3.i.i2.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_368)
begin
memory_controller_enable = 1'd1;
end
/* main: %425*/
/* store i32 %r.0.i.i.i, i32* %scevgep4.i.i6.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
memory_controller_enable = 1'd1;
end
/* main: %425*/
/* store i32 %g.0.i.i.i, i32* %scevgep5.i.i5.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_381)
begin
memory_controller_enable = 1'd1;
end
/* main: %425*/
/* store i32 %b.0.i.i.i, i32* %scevgep6.i.i4.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_382)
begin
memory_controller_enable = 1'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %427 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_383)
begin
memory_controller_enable = 1'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %429 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_384)
begin
memory_controller_enable = 1'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
memory_controller_enable = 1'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_386)
begin
memory_controller_enable = 1'd1;
end
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
memory_controller_enable = 1'd1;
end
/* main: %440*/
/* %441 = load i32* %.14.us.i.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
memory_controller_enable = 1'd1;
end
/* main: %440*/
/* store i8 %442, i8* %scevgep24.i.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB108_398)
begin
memory_controller_enable = 1'd1;
end
/* main: %WriteOneBlock.exit.i.i.i*/
/* %443 = load i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB110_400)
begin
memory_controller_enable = 1'd1;
end
/* main: %445*/
/* store i32 0, i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB111_403)
begin
memory_controller_enable = 1'd1;
end
/* main: %454*/
/* %455 = load i32* %scevgep.i3.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
memory_controller_enable = 1'd1;
end
/* main: %454*/
/* %456 = load i32* %scevgep2.i4.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_428)
begin
memory_controller_enable = 1'd1;
end
/* main: %454*/
/* %458 = load i32* %scevgep3.i5.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_429)
begin
memory_controller_enable = 1'd1;
end
/* main: %487*/
/* store i32 %r.0.i9.i.i, i32* %scevgep4.i6.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
memory_controller_enable = 1'd1;
end
/* main: %487*/
/* store i32 %g.0.i10.i.i, i32* %scevgep5.i7.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_442)
begin
memory_controller_enable = 1'd1;
end
/* main: %487*/
/* store i32 %b.0.i11.i.i, i32* %scevgep6.i8.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_443)
begin
memory_controller_enable = 1'd1;
end
/* main: %decode_start.exit.i*/
/* %main_result.promoted3.i = load i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB130_454)
begin
memory_controller_enable = 1'd1;
end
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
memory_controller_enable = 1'd1;
end
/* main: %491*/
/* %494 = load i8* %scevgep7.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_458)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.1.i*/
/* %501 = load i8* %scevgep7.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_462)
begin
memory_controller_enable = 1'd1;
end
/* main: %jpeg2bmp_main.exit*/
/* store i32 %.storemerge, i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
memory_controller_enable = 1'd1;
end
/* main: %jpeg2bmp_main.exit*/
/* %511 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB133_466)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.2.i*/
/* %515 = load i8* %scevgep7.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_470)
begin
memory_controller_enable = 1'd1;
end
/* main: %524*/
/* %525 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB137_475)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
memory_controller_write_enable = huff_make_dhuff_tb_memory_controller_write_enable;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
memory_controller_write_enable = huff_make_dhuff_tb_memory_controller_write_enable;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
memory_controller_write_enable = huff_make_dhuff_tb_memory_controller_write_enable;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
memory_controller_write_enable = huff_make_dhuff_tb_memory_controller_write_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
memory_controller_write_enable = Write4Blocks_memory_controller_write_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
memory_controller_write_enable = Write4Blocks_memory_controller_write_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
memory_controller_write_enable = Write4Blocks_memory_controller_write_enable;
end
/* main: %0*/
/* store i32 0, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB0_1)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %1*/
/* %2 = load i8* %scevgep13.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %1*/
/* store i8 %2, i8* %c.06.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_4)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %6*/
/* %8 = load i8* %ReadBuf.1, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_10)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_11)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %first_marker.exit.i.i*/
/* %16 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %first_marker.exit.i.i*/
/* store i32 %17, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_17)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.loopexit3.i.i.i*/
/* %c.0.in2.i.i.i = load i8* %18, align 1*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i.i.i*/
/* %c.0.in.i.i.i = load i8* %scevgep.i.i, align 1*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.loopexit.i.i.i*/
/* %21 = load i8* %scevgep11.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB15_27)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %next_marker.exit.i.i*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB17_32)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %28*/
/* %29 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_35)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %28*/
/* store i32 %30, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_37)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %32*/
/* %34 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_40)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_41)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %45 = load i8* %42, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %49 = load i8* %44, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* store i16 %51, i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_45)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %32*/
/* %53 = load i8* %48, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_46)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %57 = load i8* %52, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_47)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* store i16 %59, i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_49)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_50)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %65 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %68 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_55)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %74*/
/* %75 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_58)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %74*/
/* store i32 %76, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_60)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %79*/
/* %80 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_62)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %79*/
/* store i32 %81, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_64)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %82*/
/* %83 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB24_65)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %85*/
/* %86 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_68)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %85*/
/* store i32 %87, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_70)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %88*/
/* %89 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB26_71)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %91*/
/* %92 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_74)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %91*/
/* store i32 %93, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_76)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.preheader.i.i.i.thread*/
/* %96 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_78)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.preheader.i.i.i.thread*/
/* store i32 %97, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_80)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %tmp.i.i.i, i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %100 = load i8* %ReadBuf.3, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_83)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %100, i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_85)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %102 = load i8* %99, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_86)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %103, i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %104, i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_89)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %106 = load i8* %101, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_90)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %106, i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %109 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_93)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %112 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_96)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %115 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_99)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %118 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_102)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %121 = load i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_105)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %123 = load i32* %scevgep7.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB31_106)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %125*/
/* %126 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_109)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %125*/
/* store i32 %127, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_111)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %128*/
/* %129 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB33_112)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %128*/
/* %131 = load i32* %scevgep8.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB33_113)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %133*/
/* %134 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_116)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %133*/
/* store i32 %135, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_118)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %136*/
/* %137 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB35_119)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB35_120)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %141*/
/* %142 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_123)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %141*/
/* store i32 %143, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_125)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %144*/
/* %145 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB37_126)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %148*/
/* %149 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_129)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %148*/
/* store i32 %150, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_131)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %151*/
/* %152 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB39_132)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %151*/
/* %154 = load i32* %scevgep11.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB39_133)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %156*/
/* %157 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_136)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %156*/
/* store i32 %158, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_138)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %._crit_edge.i.i.i*/
/* %161 = load i8* getelementptr inbounds ([3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 0), align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %167*/
/* %169 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %167*/
/* %173 = load i8* %168, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_146)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_147)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %183*/
/* %184 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_150)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %183*/
/* store i32 %185, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_152)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %188*/
/* %189 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_154)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %188*/
/* store i32 %190, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_156)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %194*/
/* %196 = load i8* %ReadBuf.5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_160)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %203*/
/* %204 = load i8* %scevgep9.i4.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB53_164)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %211*/
/* %212 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %211*/
/* store i32 %213, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_171)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %211*/
/* store i8 %214, i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_172)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %211*/
/* store i8 %215, i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %211*/
/* %217 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_174)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %211*/
/* %220 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_177)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %211*/
/* %224 = load i32* %223, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_180)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %226*/
/* %227 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_183)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %226*/
/* store i32 %228, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_185)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %229*/
/* %230 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB58_186)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB58_187)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %235*/
/* %236 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_190)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %235*/
/* store i32 %237, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_192)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %238*/
/* %239 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB60_193)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %242*/
/* %243 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_196)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %242*/
/* store i32 %244, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_198)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %248*/
/* %250 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %248*/
/* %254 = load i8* %249, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_202)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %248*/
/* %260 = load i32* %4, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB64_205)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %262*/
/* %263 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_208)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %262*/
/* store i32 %264, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_210)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph5.i.i.i*/
/* %267 = load i8* %ReadBuf.6, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph5.i.i.i*/
/* %271 = load i32* %270, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB67_215)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %273*/
/* %274 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_218)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %273*/
/* store i32 %275, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_220)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %287*/
/* %290 = load i8* %288, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %287*/
/* store i32 %291, i32* %scevgep.i9.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %293*/
/* %296 = load i32* %295, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB74_229)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %298*/
/* %299 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_232)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %298*/
/* store i32 %300, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_234)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i10.i.i*/
/* %306 = load i8* %304, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i10.i.i*/
/* store i32 %307, i32* %scevgep8.i11.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB77_238)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %312*/
/* %314 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %312*/
/* %318 = load i8* %313, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_241)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %312*/
/* %324 = load i32* %5, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB79_244)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %326*/
/* %327 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_247)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %326*/
/* store i32 %328, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_249)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i15.i.i*/
/* %332 = load i8* %330, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i15.i.i*/
/* %339 = load i32* %338, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB82_254)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %341*/
/* %342 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_257)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %341*/
/* store i32 %343, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_259)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %344*/
/* %346 = load i32* %345, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB84_260)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %348*/
/* %349 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_263)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %348*/
/* store i32 %350, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_265)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.split.us.i.i.i*/
/* %356 = load i8* %354, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.split.us.i.i.i*/
/* %358 = load i32* %scevgep.i16.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_268)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.split.us.i.i.i*/
/* store i32 %357, i32* %359, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_270)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %..split_crit_edge.i.i.i*/
/* %363 = load i8* %361, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %..split_crit_edge.i.i.i*/
/* %367 = load i8* %362, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_272)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %..split_crit_edge.i.i.i*/
/* %370 = load i32* %scevgep4.i18.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_273)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %..split_crit_edge.i.i.i*/
/* store i32 %369, i32* %371, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_275)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_278)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 %383, i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %385, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_332)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %386, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_336)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %387, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_340)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %388, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_344)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i8* %p_jinfo_jpeg_data.0, i8** @CurHuffReadBuf, align 4, !tbaa !4*/
if (cur_state == LEGUP_F_main_BB90_345)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_346)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.1.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_347)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.2.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_348)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_349)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_350)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_351)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_352)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_353)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_354)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %392*/
/* %393 = load i32* %scevgep.i.i3.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %392*/
/* %394 = load i32* %scevgep2.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_367)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %392*/
/* %396 = load i32* %scevgep3.i.i2.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_368)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %425*/
/* store i32 %r.0.i.i.i, i32* %scevgep4.i.i6.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %425*/
/* store i32 %g.0.i.i.i, i32* %scevgep5.i.i5.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_381)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %425*/
/* store i32 %b.0.i.i.i, i32* %scevgep6.i.i4.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_382)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %427 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_383)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %429 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_384)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_386)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %440*/
/* %441 = load i32* %.14.us.i.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %440*/
/* store i8 %442, i8* %scevgep24.i.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB108_398)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %WriteOneBlock.exit.i.i.i*/
/* %443 = load i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB110_400)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %445*/
/* store i32 0, i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB111_403)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %454*/
/* %455 = load i32* %scevgep.i3.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %454*/
/* %456 = load i32* %scevgep2.i4.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_428)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %454*/
/* %458 = load i32* %scevgep3.i5.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_429)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %487*/
/* store i32 %r.0.i9.i.i, i32* %scevgep4.i6.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %487*/
/* store i32 %g.0.i10.i.i, i32* %scevgep5.i7.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_442)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %487*/
/* store i32 %b.0.i11.i.i, i32* %scevgep6.i8.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_443)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %decode_start.exit.i*/
/* %main_result.promoted3.i = load i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB130_454)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %491*/
/* %494 = load i8* %scevgep7.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_458)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.preheader.1.i*/
/* %501 = load i8* %scevgep7.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_462)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %jpeg2bmp_main.exit*/
/* store i32 %.storemerge, i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %jpeg2bmp_main.exit*/
/* %511 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB133_466)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.preheader.2.i*/
/* %515 = load i8* %scevgep7.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_470)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %524*/
/* %525 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB137_475)
begin
memory_controller_write_enable = 1'd0;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
memory_controller_in = huff_make_dhuff_tb_memory_controller_in;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
memory_controller_in = huff_make_dhuff_tb_memory_controller_in;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
memory_controller_in = huff_make_dhuff_tb_memory_controller_in;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
memory_controller_in = huff_make_dhuff_tb_memory_controller_in;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
memory_controller_in = Write4Blocks_memory_controller_in;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
memory_controller_in = Write4Blocks_memory_controller_in;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
memory_controller_in = Write4Blocks_memory_controller_in;
end
/* main: %0*/
/* store i32 0, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB0_1)
begin
memory_controller_in = 32'd0;
end
/* main: %1*/
/* store i8 %2, i8* %c.06.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_4)
begin
memory_controller_in = main_1_2;
end
/* main: %first_marker.exit.i.i*/
/* store i32 %17, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_17)
begin
memory_controller_in = main_first_marker_exit_i_i_17;
end
/* main: %28*/
/* store i32 %30, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_37)
begin
memory_controller_in = main_28_30;
end
/* main: %32*/
/* store i16 %51, i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_45)
begin
memory_controller_in = main_32_51;
end
/* main: %32*/
/* store i16 %59, i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_49)
begin
memory_controller_in = main_32_59;
end
/* main: %74*/
/* store i32 %76, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_60)
begin
memory_controller_in = main_74_76;
end
/* main: %79*/
/* store i32 %81, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_64)
begin
memory_controller_in = main_79_81;
end
/* main: %85*/
/* store i32 %87, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_70)
begin
memory_controller_in = main_85_87;
end
/* main: %91*/
/* store i32 %93, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_76)
begin
memory_controller_in = main_91_93;
end
/* main: %.preheader.i.i.i.thread*/
/* store i32 %97, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_80)
begin
memory_controller_in = main__preheader_i_i_i_thread_97;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %tmp.i.i.i, i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
memory_controller_in = main__lr_ph_i1_i_i_tmp_i_i_i;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %100, i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_85)
begin
memory_controller_in = main__lr_ph_i1_i_i_100;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %103, i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
memory_controller_in = main__lr_ph_i1_i_i_103;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %104, i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_89)
begin
memory_controller_in = main__lr_ph_i1_i_i_104_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %106, i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
memory_controller_in = main__lr_ph_i1_i_i_106;
end
/* main: %125*/
/* store i32 %127, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_111)
begin
memory_controller_in = main_125_127;
end
/* main: %133*/
/* store i32 %135, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_118)
begin
memory_controller_in = main_133_135;
end
/* main: %141*/
/* store i32 %143, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_125)
begin
memory_controller_in = main_141_143;
end
/* main: %148*/
/* store i32 %150, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_131)
begin
memory_controller_in = main_148_150;
end
/* main: %156*/
/* store i32 %158, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_138)
begin
memory_controller_in = main_156_158;
end
/* main: %183*/
/* store i32 %185, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_152)
begin
memory_controller_in = main_183_185;
end
/* main: %188*/
/* store i32 %190, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_156)
begin
memory_controller_in = main_188_190;
end
/* main: %211*/
/* store i32 %213, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_171)
begin
memory_controller_in = main_211_213;
end
/* main: %211*/
/* store i8 %214, i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_172)
begin
memory_controller_in = main_211_214_reg;
end
/* main: %211*/
/* store i8 %215, i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
memory_controller_in = main_211_215_reg;
end
/* main: %226*/
/* store i32 %228, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_185)
begin
memory_controller_in = main_226_228;
end
/* main: %235*/
/* store i32 %237, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_192)
begin
memory_controller_in = main_235_237;
end
/* main: %242*/
/* store i32 %244, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_198)
begin
memory_controller_in = main_242_244;
end
/* main: %262*/
/* store i32 %264, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_210)
begin
memory_controller_in = main_262_264;
end
/* main: %273*/
/* store i32 %275, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_220)
begin
memory_controller_in = main_273_275;
end
/* main: %287*/
/* store i32 %291, i32* %scevgep.i9.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
memory_controller_in = main_287_291;
end
/* main: %298*/
/* store i32 %300, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_234)
begin
memory_controller_in = main_298_300;
end
/* main: %.lr.ph.i10.i.i*/
/* store i32 %307, i32* %scevgep8.i11.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB77_238)
begin
memory_controller_in = main__lr_ph_i10_i_i_307;
end
/* main: %326*/
/* store i32 %328, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_249)
begin
memory_controller_in = main_326_328;
end
/* main: %341*/
/* store i32 %343, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_259)
begin
memory_controller_in = main_341_343;
end
/* main: %348*/
/* store i32 %350, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_265)
begin
memory_controller_in = main_348_350;
end
/* main: %.split.us.i.i.i*/
/* store i32 %357, i32* %359, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_270)
begin
memory_controller_in = main__split_us_i_i_i_357_reg;
end
/* main: %..split_crit_edge.i.i.i*/
/* store i32 %369, i32* %371, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_275)
begin
memory_controller_in = main___split_crit_edge_i_i_i_369_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 %383, i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
memory_controller_in = main_read_markers_exit_i_383;
end
/* main: %read_markers.exit.i*/
/* store i32 %385, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_332)
begin
memory_controller_in = main_read_markers_exit_i_385_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 %386, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_336)
begin
memory_controller_in = main_read_markers_exit_i_386_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 %387, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_340)
begin
memory_controller_in = main_read_markers_exit_i_387_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 %388, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_344)
begin
memory_controller_in = main_read_markers_exit_i_388_reg;
end
/* main: %read_markers.exit.i*/
/* store i8* %p_jinfo_jpeg_data.0, i8** @CurHuffReadBuf, align 4, !tbaa !4*/
if (cur_state == LEGUP_F_main_BB90_345)
begin
memory_controller_in = main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_346)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.1.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_347)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.2.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_348)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_349)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_350)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_351)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_352)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_353)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_354)
begin
memory_controller_in = 32'd0;
end
/* main: %425*/
/* store i32 %r.0.i.i.i, i32* %scevgep4.i.i6.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
memory_controller_in = main_415_r_0_i_i_i_reg;
end
/* main: %425*/
/* store i32 %g.0.i.i.i, i32* %scevgep5.i.i5.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_381)
begin
memory_controller_in = main_420_g_0_i_i_i_reg;
end
/* main: %425*/
/* store i32 %b.0.i.i.i, i32* %scevgep6.i.i4.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_382)
begin
memory_controller_in = main_425_b_0_i_i_i_reg;
end
/* main: %440*/
/* store i8 %442, i8* %scevgep24.i.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB108_398)
begin
memory_controller_in = main_440_442;
end
/* main: %445*/
/* store i32 0, i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB111_403)
begin
memory_controller_in = 32'd0;
end
/* main: %487*/
/* store i32 %r.0.i9.i.i, i32* %scevgep4.i6.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
memory_controller_in = main_477_r_0_i9_i_i_reg;
end
/* main: %487*/
/* store i32 %g.0.i10.i.i, i32* %scevgep5.i7.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_442)
begin
memory_controller_in = main_482_g_0_i10_i_i_reg;
end
/* main: %487*/
/* store i32 %b.0.i11.i.i, i32* %scevgep6.i8.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_443)
begin
memory_controller_in = main_487_b_0_i11_i_i_reg;
end
/* main: %jpeg2bmp_main.exit*/
/* store i32 %.storemerge, i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
memory_controller_in = main_jpeg2bmp_main_exit__storemerge;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
memory_controller_size = huff_make_dhuff_tb_memory_controller_size;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
memory_controller_size = huff_make_dhuff_tb_memory_controller_size;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
memory_controller_size = huff_make_dhuff_tb_memory_controller_size;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
memory_controller_size = huff_make_dhuff_tb_memory_controller_size;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
memory_controller_size = Write4Blocks_memory_controller_size;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
memory_controller_size = Write4Blocks_memory_controller_size;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
memory_controller_size = Write4Blocks_memory_controller_size;
end
/* main: %0*/
/* store i32 0, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB0_1)
begin
memory_controller_size = 2'd2;
end
/* main: %1*/
/* %2 = load i8* %scevgep13.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
memory_controller_size = 2'd0;
end
/* main: %1*/
/* store i8 %2, i8* %c.06.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_4)
begin
memory_controller_size = 2'd0;
end
/* main: %6*/
/* %8 = load i8* %ReadBuf.1, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_10)
begin
memory_controller_size = 2'd0;
end
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_11)
begin
memory_controller_size = 2'd0;
end
/* main: %first_marker.exit.i.i*/
/* %16 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
memory_controller_size = 2'd2;
end
/* main: %first_marker.exit.i.i*/
/* store i32 %17, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_17)
begin
memory_controller_size = 2'd2;
end
/* main: %.loopexit3.i.i.i*/
/* %c.0.in2.i.i.i = load i8* %18, align 1*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i.i.i*/
/* %c.0.in.i.i.i = load i8* %scevgep.i.i, align 1*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
memory_controller_size = 2'd0;
end
/* main: %.loopexit.i.i.i*/
/* %21 = load i8* %scevgep11.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB15_27)
begin
memory_controller_size = 2'd0;
end
/* main: %next_marker.exit.i.i*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB17_32)
begin
memory_controller_size = 2'd2;
end
/* main: %28*/
/* %29 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_35)
begin
memory_controller_size = 2'd2;
end
/* main: %28*/
/* store i32 %30, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_37)
begin
memory_controller_size = 2'd2;
end
/* main: %32*/
/* %34 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_40)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_41)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %45 = load i8* %42, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %49 = load i8* %44, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* store i16 %51, i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_45)
begin
memory_controller_size = 2'd1;
end
/* main: %32*/
/* %53 = load i8* %48, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_46)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %57 = load i8* %52, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_47)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* store i16 %59, i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_49)
begin
memory_controller_size = 2'd1;
end
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_50)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %65 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
memory_controller_size = 2'd1;
end
/* main: %32*/
/* %68 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_55)
begin
memory_controller_size = 2'd1;
end
/* main: %74*/
/* %75 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_58)
begin
memory_controller_size = 2'd2;
end
/* main: %74*/
/* store i32 %76, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_60)
begin
memory_controller_size = 2'd2;
end
/* main: %79*/
/* %80 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_62)
begin
memory_controller_size = 2'd2;
end
/* main: %79*/
/* store i32 %81, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_64)
begin
memory_controller_size = 2'd2;
end
/* main: %82*/
/* %83 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB24_65)
begin
memory_controller_size = 2'd1;
end
/* main: %85*/
/* %86 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_68)
begin
memory_controller_size = 2'd2;
end
/* main: %85*/
/* store i32 %87, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_70)
begin
memory_controller_size = 2'd2;
end
/* main: %88*/
/* %89 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB26_71)
begin
memory_controller_size = 2'd1;
end
/* main: %91*/
/* %92 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_74)
begin
memory_controller_size = 2'd2;
end
/* main: %91*/
/* store i32 %93, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_76)
begin
memory_controller_size = 2'd2;
end
/* main: %.preheader.i.i.i.thread*/
/* %96 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_78)
begin
memory_controller_size = 2'd2;
end
/* main: %.preheader.i.i.i.thread*/
/* store i32 %97, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_80)
begin
memory_controller_size = 2'd2;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %tmp.i.i.i, i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %100 = load i8* %ReadBuf.3, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_83)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %100, i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_85)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %102 = load i8* %99, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_86)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %103, i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %104, i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_89)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %106 = load i8* %101, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_90)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %106, i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %109 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_93)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %112 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_96)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %115 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_99)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %118 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_102)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %121 = load i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_105)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %123 = load i32* %scevgep7.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB31_106)
begin
memory_controller_size = 2'd2;
end
/* main: %125*/
/* %126 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_109)
begin
memory_controller_size = 2'd2;
end
/* main: %125*/
/* store i32 %127, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_111)
begin
memory_controller_size = 2'd2;
end
/* main: %128*/
/* %129 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB33_112)
begin
memory_controller_size = 2'd0;
end
/* main: %128*/
/* %131 = load i32* %scevgep8.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB33_113)
begin
memory_controller_size = 2'd2;
end
/* main: %133*/
/* %134 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_116)
begin
memory_controller_size = 2'd2;
end
/* main: %133*/
/* store i32 %135, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_118)
begin
memory_controller_size = 2'd2;
end
/* main: %136*/
/* %137 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB35_119)
begin
memory_controller_size = 2'd0;
end
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB35_120)
begin
memory_controller_size = 2'd2;
end
/* main: %141*/
/* %142 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_123)
begin
memory_controller_size = 2'd2;
end
/* main: %141*/
/* store i32 %143, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_125)
begin
memory_controller_size = 2'd2;
end
/* main: %144*/
/* %145 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB37_126)
begin
memory_controller_size = 2'd0;
end
/* main: %148*/
/* %149 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_129)
begin
memory_controller_size = 2'd2;
end
/* main: %148*/
/* store i32 %150, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_131)
begin
memory_controller_size = 2'd2;
end
/* main: %151*/
/* %152 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB39_132)
begin
memory_controller_size = 2'd0;
end
/* main: %151*/
/* %154 = load i32* %scevgep11.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB39_133)
begin
memory_controller_size = 2'd2;
end
/* main: %156*/
/* %157 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_136)
begin
memory_controller_size = 2'd2;
end
/* main: %156*/
/* store i32 %158, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_138)
begin
memory_controller_size = 2'd2;
end
/* main: %._crit_edge.i.i.i*/
/* %161 = load i8* getelementptr inbounds ([3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 0), align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
memory_controller_size = 2'd0;
end
/* main: %167*/
/* %169 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
memory_controller_size = 2'd0;
end
/* main: %167*/
/* %173 = load i8* %168, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_146)
begin
memory_controller_size = 2'd0;
end
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_147)
begin
memory_controller_size = 2'd0;
end
/* main: %183*/
/* %184 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_150)
begin
memory_controller_size = 2'd2;
end
/* main: %183*/
/* store i32 %185, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_152)
begin
memory_controller_size = 2'd2;
end
/* main: %188*/
/* %189 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_154)
begin
memory_controller_size = 2'd2;
end
/* main: %188*/
/* store i32 %190, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_156)
begin
memory_controller_size = 2'd2;
end
/* main: %194*/
/* %196 = load i8* %ReadBuf.5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
memory_controller_size = 2'd0;
end
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_160)
begin
memory_controller_size = 2'd0;
end
/* main: %203*/
/* %204 = load i8* %scevgep9.i4.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB53_164)
begin
memory_controller_size = 2'd0;
end
/* main: %211*/
/* %212 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
memory_controller_size = 2'd2;
end
/* main: %211*/
/* store i32 %213, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_171)
begin
memory_controller_size = 2'd2;
end
/* main: %211*/
/* store i8 %214, i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_172)
begin
memory_controller_size = 2'd0;
end
/* main: %211*/
/* store i8 %215, i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
memory_controller_size = 2'd0;
end
/* main: %211*/
/* %217 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_174)
begin
memory_controller_size = 2'd0;
end
/* main: %211*/
/* %220 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_177)
begin
memory_controller_size = 2'd0;
end
/* main: %211*/
/* %224 = load i32* %223, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_180)
begin
memory_controller_size = 2'd2;
end
/* main: %226*/
/* %227 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_183)
begin
memory_controller_size = 2'd2;
end
/* main: %226*/
/* store i32 %228, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_185)
begin
memory_controller_size = 2'd2;
end
/* main: %229*/
/* %230 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB58_186)
begin
memory_controller_size = 2'd0;
end
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB58_187)
begin
memory_controller_size = 2'd2;
end
/* main: %235*/
/* %236 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_190)
begin
memory_controller_size = 2'd2;
end
/* main: %235*/
/* store i32 %237, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_192)
begin
memory_controller_size = 2'd2;
end
/* main: %238*/
/* %239 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB60_193)
begin
memory_controller_size = 2'd0;
end
/* main: %242*/
/* %243 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_196)
begin
memory_controller_size = 2'd2;
end
/* main: %242*/
/* store i32 %244, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_198)
begin
memory_controller_size = 2'd2;
end
/* main: %248*/
/* %250 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
memory_controller_size = 2'd0;
end
/* main: %248*/
/* %254 = load i8* %249, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_202)
begin
memory_controller_size = 2'd0;
end
/* main: %248*/
/* %260 = load i32* %4, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB64_205)
begin
memory_controller_size = 2'd2;
end
/* main: %262*/
/* %263 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_208)
begin
memory_controller_size = 2'd2;
end
/* main: %262*/
/* store i32 %264, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_210)
begin
memory_controller_size = 2'd2;
end
/* main: %.lr.ph5.i.i.i*/
/* %267 = load i8* %ReadBuf.6, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph5.i.i.i*/
/* %271 = load i32* %270, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB67_215)
begin
memory_controller_size = 2'd2;
end
/* main: %273*/
/* %274 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_218)
begin
memory_controller_size = 2'd2;
end
/* main: %273*/
/* store i32 %275, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_220)
begin
memory_controller_size = 2'd2;
end
/* main: %287*/
/* %290 = load i8* %288, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
memory_controller_size = 2'd0;
end
/* main: %287*/
/* store i32 %291, i32* %scevgep.i9.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
memory_controller_size = 2'd2;
end
/* main: %293*/
/* %296 = load i32* %295, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB74_229)
begin
memory_controller_size = 2'd2;
end
/* main: %298*/
/* %299 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_232)
begin
memory_controller_size = 2'd2;
end
/* main: %298*/
/* store i32 %300, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_234)
begin
memory_controller_size = 2'd2;
end
/* main: %.lr.ph.i10.i.i*/
/* %306 = load i8* %304, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i10.i.i*/
/* store i32 %307, i32* %scevgep8.i11.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB77_238)
begin
memory_controller_size = 2'd2;
end
/* main: %312*/
/* %314 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
memory_controller_size = 2'd0;
end
/* main: %312*/
/* %318 = load i8* %313, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_241)
begin
memory_controller_size = 2'd0;
end
/* main: %312*/
/* %324 = load i32* %5, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB79_244)
begin
memory_controller_size = 2'd2;
end
/* main: %326*/
/* %327 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_247)
begin
memory_controller_size = 2'd2;
end
/* main: %326*/
/* store i32 %328, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_249)
begin
memory_controller_size = 2'd2;
end
/* main: %.lr.ph.i15.i.i*/
/* %332 = load i8* %330, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i15.i.i*/
/* %339 = load i32* %338, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB82_254)
begin
memory_controller_size = 2'd2;
end
/* main: %341*/
/* %342 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_257)
begin
memory_controller_size = 2'd2;
end
/* main: %341*/
/* store i32 %343, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_259)
begin
memory_controller_size = 2'd2;
end
/* main: %344*/
/* %346 = load i32* %345, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB84_260)
begin
memory_controller_size = 2'd2;
end
/* main: %348*/
/* %349 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_263)
begin
memory_controller_size = 2'd2;
end
/* main: %348*/
/* store i32 %350, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_265)
begin
memory_controller_size = 2'd2;
end
/* main: %.split.us.i.i.i*/
/* %356 = load i8* %354, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
memory_controller_size = 2'd0;
end
/* main: %.split.us.i.i.i*/
/* %358 = load i32* %scevgep.i16.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_268)
begin
memory_controller_size = 2'd2;
end
/* main: %.split.us.i.i.i*/
/* store i32 %357, i32* %359, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_270)
begin
memory_controller_size = 2'd2;
end
/* main: %..split_crit_edge.i.i.i*/
/* %363 = load i8* %361, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
memory_controller_size = 2'd0;
end
/* main: %..split_crit_edge.i.i.i*/
/* %367 = load i8* %362, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_272)
begin
memory_controller_size = 2'd0;
end
/* main: %..split_crit_edge.i.i.i*/
/* %370 = load i32* %scevgep4.i18.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_273)
begin
memory_controller_size = 2'd2;
end
/* main: %..split_crit_edge.i.i.i*/
/* store i32 %369, i32* %371, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_275)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
memory_controller_size = 2'd1;
end
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_278)
begin
memory_controller_size = 2'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %383, i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 %385, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_332)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 %386, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_336)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 %387, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_340)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 %388, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_344)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i8* %p_jinfo_jpeg_data.0, i8** @CurHuffReadBuf, align 4, !tbaa !4*/
if (cur_state == LEGUP_F_main_BB90_345)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_346)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.1.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_347)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.2.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_348)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_349)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_350)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_351)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_352)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_353)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_354)
begin
memory_controller_size = 2'd2;
end
/* main: %392*/
/* %393 = load i32* %scevgep.i.i3.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
memory_controller_size = 2'd2;
end
/* main: %392*/
/* %394 = load i32* %scevgep2.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_367)
begin
memory_controller_size = 2'd2;
end
/* main: %392*/
/* %396 = load i32* %scevgep3.i.i2.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_368)
begin
memory_controller_size = 2'd2;
end
/* main: %425*/
/* store i32 %r.0.i.i.i, i32* %scevgep4.i.i6.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
memory_controller_size = 2'd2;
end
/* main: %425*/
/* store i32 %g.0.i.i.i, i32* %scevgep5.i.i5.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_381)
begin
memory_controller_size = 2'd2;
end
/* main: %425*/
/* store i32 %b.0.i.i.i, i32* %scevgep6.i.i4.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_382)
begin
memory_controller_size = 2'd2;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %427 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_383)
begin
memory_controller_size = 2'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %429 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_384)
begin
memory_controller_size = 2'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
memory_controller_size = 2'd2;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_386)
begin
memory_controller_size = 2'd2;
end
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
memory_controller_size = 2'd2;
end
/* main: %440*/
/* %441 = load i32* %.14.us.i.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
memory_controller_size = 2'd2;
end
/* main: %440*/
/* store i8 %442, i8* %scevgep24.i.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB108_398)
begin
memory_controller_size = 2'd0;
end
/* main: %WriteOneBlock.exit.i.i.i*/
/* %443 = load i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB110_400)
begin
memory_controller_size = 2'd2;
end
/* main: %445*/
/* store i32 0, i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB111_403)
begin
memory_controller_size = 2'd2;
end
/* main: %454*/
/* %455 = load i32* %scevgep.i3.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
memory_controller_size = 2'd2;
end
/* main: %454*/
/* %456 = load i32* %scevgep2.i4.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_428)
begin
memory_controller_size = 2'd2;
end
/* main: %454*/
/* %458 = load i32* %scevgep3.i5.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_429)
begin
memory_controller_size = 2'd2;
end
/* main: %487*/
/* store i32 %r.0.i9.i.i, i32* %scevgep4.i6.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
memory_controller_size = 2'd2;
end
/* main: %487*/
/* store i32 %g.0.i10.i.i, i32* %scevgep5.i7.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_442)
begin
memory_controller_size = 2'd2;
end
/* main: %487*/
/* store i32 %b.0.i11.i.i, i32* %scevgep6.i8.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_443)
begin
memory_controller_size = 2'd2;
end
/* main: %decode_start.exit.i*/
/* %main_result.promoted3.i = load i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB130_454)
begin
memory_controller_size = 2'd2;
end
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
memory_controller_size = 2'd0;
end
/* main: %491*/
/* %494 = load i8* %scevgep7.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_458)
begin
memory_controller_size = 2'd0;
end
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
memory_controller_size = 2'd0;
end
/* main: %.preheader.1.i*/
/* %501 = load i8* %scevgep7.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_462)
begin
memory_controller_size = 2'd0;
end
/* main: %jpeg2bmp_main.exit*/
/* store i32 %.storemerge, i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
memory_controller_size = 2'd2;
end
/* main: %jpeg2bmp_main.exit*/
/* %511 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB133_466)
begin
memory_controller_size = 2'd2;
end
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
memory_controller_size = 2'd0;
end
/* main: %.preheader.2.i*/
/* %515 = load i8* %scevgep7.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_470)
begin
memory_controller_size = 2'd0;
end
/* main: %524*/
/* %525 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB137_475)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module ram_two_ports
(
clk,
address_a,
wren_a,
data_a,
q_a,
address_b,
wren_b,
data_b,
q_b,
byteena_a,
byteena_b
);
parameter width_a = 1'd0;
parameter widthad_a = 1'd0;
parameter numwords_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED";
parameter width_be_a = 1'd0;
parameter width_be_b = 1'd0;
input clk;
input [(widthad_a-1):0] address_a;
input wren_a;
input [(width_a-1):0] data_a;
output [(width_a-1):0] q_a;
input [(widthad_b-1):0] address_b;
input wren_b;
input [(width_b-1):0] data_b;
output [(width_b-1):0] q_b;
input [width_be_a-1:0] byteena_a;
input [width_be_b-1:0] byteena_b;
reg clk_wire;
altsyncram altsyncram_component (
.byteena_a (byteena_a),
.byteena_b (byteena_b),
.wren_a (wren_a),
.wren_b (wren_b),
.clock0 (clk_wire),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.aclr0 (1'd0),
.aclr1 (1'd0),
.addressstall_a (1'd0),
.addressstall_b (1'd0),
.clock1 (1'd1),
.clocken0 (1'd1),
.clocken1 (1'd1),
.clocken2 (1'd1),
.clocken3 (1'd1),
.eccstatus (),
.rden_a (1'd1),
.rden_b (1'd1)
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = init_file,
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = numwords_a,
altsyncram_component.numwords_b = numwords_b,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.widthad_a = widthad_a,
altsyncram_component.widthad_b = widthad_b,
altsyncram_component.width_a = width_a,
altsyncram_component.width_b = width_b,
altsyncram_component.width_byteena_a = width_be_a,
altsyncram_component.width_byteena_b = width_be_b;
always @(*) begin
clk_wire = clk;
end
endmodule
`timescale 1 ns / 1 ns
module main_tb
(
);
reg clk;
reg reset;
reg start;
wire [31:0] return_val;
wire finish;
top top_inst (
.clk (clk),
.reset (reset),
.start (start),
.finish (finish),
.return_val (return_val)
);
initial
clk <= #0 0;
always @(clk)
clk <= #1 ~clk;
initial begin
//$monitor("At t=%t clk=%b %b %b %b %d", $time, clk, reset, start, finish, return_val);
@(negedge clk);
reset <= 1;
@(negedge clk);
reset <= 0;
start <= 1;
end
always@(finish) begin
if (finish == 1) begin
$display("At t=%t clk=%b finish=%b return_val=%d", $time, clk, finish, return_val);
$finish;
end
end
endmodule
|
//----------------------------------------------------------------------------//
// Generated by LegUp High-Level Synthesis Tool Version 2.0 (http://legup.org)
// University of Toronto
// Date: Fri Jul 6 17:21:11 2012
// For research and academic purposes only. Commercial use is prohibited.
// Please send bugs to: [email protected]
//----------------------------------------------------------------------------//
`define MEMORY_CONTROLLER_ADDR_SIZE 32
`define MEMORY_CONTROLLER_DATA_SIZE 64
// Number of RAM elements: 55
`define MEMORY_CONTROLLER_TAG_SIZE 9
`define TAG_NULL `MEMORY_CONTROLLER_TAG_SIZE'd0
`define TAG_PROCESSOR `MEMORY_CONTROLLER_TAG_SIZE'd1
// %QuantBuff = alloca [64 x i32], align 4
`define TAG_decode_block_0_QuantBuff `MEMORY_CONTROLLER_TAG_SIZE'd52
`define TAG_decode_block_0_QuantBuff_a {`TAG_decode_block_0_QuantBuff, 23'b0}
// @CurHuffReadBuf = internal unnamed_addr global i8* null, align 4
`define TAG_g_CurHuffReadBuf `MEMORY_CONTROLLER_TAG_SIZE'd34
`define TAG_g_CurHuffReadBuf_a {`TAG_g_CurHuffReadBuf, 23'b0}
// @JpegFileBuf = internal global [5310 x i8] zeroinitializer, align 1
`define TAG_g_JpegFileBuf `MEMORY_CONTROLLER_TAG_SIZE'd51
`define TAG_g_JpegFileBuf_a {`TAG_g_JpegFileBuf, 23'b0}
// @OutData_comp_buf = internal global [3 x [5310 x i8]] zeroinitializer, align 1
`define TAG_g_OutData_comp_buf `MEMORY_CONTROLLER_TAG_SIZE'd35
`define TAG_g_OutData_comp_buf_a {`TAG_g_OutData_comp_buf, 23'b0}
// @OutData_comp_hpos = internal global [3 x i32] zeroinitializer, align 4
`define TAG_g_OutData_comp_hpos `MEMORY_CONTROLLER_TAG_SIZE'd50
`define TAG_g_OutData_comp_hpos_a {`TAG_g_OutData_comp_hpos, 23'b0}
// @OutData_comp_vpos = internal global [3 x i32] zeroinitializer, align 4
`define TAG_g_OutData_comp_vpos `MEMORY_CONTROLLER_TAG_SIZE'd49
`define TAG_g_OutData_comp_vpos_a {`TAG_g_OutData_comp_vpos, 23'b0}
// @bit_set_mask = internal unnamed_addr constant [32 x i32] [i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 512, i32 1024, i32 2048, i32 4096, i32 8192, i32 16384, i32 32768, i32 65536, i32 131072, i32 262144, i32 524288, i32 1048576, i32 2097152, i32 4194304, i32 8388608, i32 16777216, i32 33554432, i32 67108864, i32 134217728, i32 268435456, i32 536870912, i32 1073741824, i32 -2147483648], align 4
`define TAG_g_bit_set_mask `MEMORY_CONTROLLER_TAG_SIZE'd36
`define TAG_g_bit_set_mask_a {`TAG_g_bit_set_mask, 23'b0}
// @current_read_byte = internal unnamed_addr global i32 0, align 4
`define TAG_g_current_read_byte `MEMORY_CONTROLLER_TAG_SIZE'd39
`define TAG_g_current_read_byte_a {`TAG_g_current_read_byte, 23'b0}
// @extend_mask = internal unnamed_addr constant [20 x i32] [i32 -2, i32 -4, i32 -8, i32 -16, i32 -32, i32 -64, i32 -128, i32 -256, i32 -512, i32 -1024, i32 -2048, i32 -4096, i32 -8192, i32 -16384, i32 -32768, i32 -65536, i32 -131072, i32 -262144, i32 -524288, i32 -1048576], align 4
`define TAG_g_extend_mask `MEMORY_CONTROLLER_TAG_SIZE'd44
`define TAG_g_extend_mask_a {`TAG_g_extend_mask, 23'b0}
// @hana_bmp = internal unnamed_addr constant [3 x [5310 x i8]] [[5310 x i8] c"\BC\D1\BE\99\8Fg\95\C0\AC\9D\BD\C0\A4\C3\BC\B5\C1\A7\BC\D2\B1\8E%\0A\1F('4 \1D\22\0E\0A\12\0E\1A\07l\B5\BE\B5\7F[cI$\0B$B]ZA3 $#&58#\19\19 1)6 \1F\1F\22\18\19&+ \0B\09\0D\14\19\17\11\10\12\1E\19!-$\1D\A6\C1eZ\AA\81\92\D5\A9X\91\C7\CF\A5\89q\C9\9B\8B\D1\BF\C9\ABg3\1D\11\09\1D+!$\18\0E\18\18\04l\B9\B4\BA\BC\B7\C3\C0l0KgUE1.7,*23)\1E\12\0E\1E006\22(&$\1F\1C47-\0F\0E\10\17\15\0F\0B\11\19\1F\1A,I\22'\91\84.\B5\CD\D1\BB\AA\8C84\8Ez\B0\C6S\9A\D7\C8\D1\B8\A4\C4\AE\807YL\1C&/.#\1B'\1F\10:t\89\A9\B8\B4\AF\A6xI[aT $>:()0- \14\0F\10\0C\1B\18$(\10\22\18\16!=A7\12\15\16\1D\13\12\0F\15\1C!\1D0K$&o\0F>\E2\CF\BB\CD\BC=\02\0D\1F\09i\8C1\18\BF\D1\C6\BA\B8\93uY:\8A\B3\87>43\17\14\22\1C\1A\0A*p\97\9D\8Bzq6OT`.\13 5:(('&\15\15\11\17\06ne\0E\12\07\0F\1B\07\1B@F?\16\1E &\16\08\0A\12\14\1A\1B+:,(\8B\8C\81\9Cq\B1\D7\AEoe$\0E\14\8BbjQ%a\DF\C8\D9\95\99\94\83F\92\B2\AC\83P\0D\11+\10\12\14\18b\82\A3\90UGQNXD\1D'8;1()'\14\0B?P\01Y\B3\BA`\00%\0F\15\14\1B@LI\1D\1F!+\22\0D\0C\13\10\10\0E\1C&<2\B3\C4\D9\847y\D5\B4\B1\B7\AEf\A1\B6\8C\93\C5\CE\A4\D6\D9\AF(\8D\AE\B7{Daw{~1\15'\11\17\1C\0E{\95\C2\C1_KIF?;207:*06 $\0CU\9Fn}\B1\BB\89\196:7\12\13;ML\22\1E 0/\22\12\0D\0D\0C\05\0C\1249\88\86\AF\D6\86\A1\BE\8D\B1\BD\8D\A4\CB\B3\B9\90I\8D\CE\94\B5\C0qE\95\B0\8DtS.epO\1F\19(\1E\1A\0Cb\A2\C3\[email protected]$,/\1B7\B1\C8\AF\A9\B2\9Cr~k=.2<NL.*0;:-\19\14\16\1A\13\13\0F8:)r\C4\C3\D0\C5\BA\B0\AE\CCy\88\D0\CD\C9V\0C\BE\B4\B1\94\B2\DD\91a\92\88\99\A9\8A\93\BF\A79/\A8|!\056\BD\B4\C5\BC\88D6?2NSJPZ:,<-,\12\80\C2\B0\C9\CB\C4\AF\8Ek=,=JVS>@GH??7941'$\18=9\13K\C2\A5\A8\BA\C4\BB\CB\CFVA\82\C0\D6\B8\90\AE\B4\D1\93Llt\9B\9A\BB\AC\B3\B4\BB\C7\CC96\A5\7F/ZC\BD\B3\AA\D6\C3\9Fg( @aB55CM./'\0A5z\97\CA\D5\D6\BC\A1\91j<:N]aefVUG927664+(\15\16q\0B.Bh\8C\A4\A7\B1\D2Gsi\BE\A3\B5\BB\B8\8E\B1k\CF\80qy\9C\99\8F\A1\9A\A5\B6\B67-t*4x^}\B4\BB\BA\C7\BF\BAN\00+`vR\13LLG7\1D\09\08;o\A8\BD\CD\BB\A6\8Ao2)7L^kte\5CH32/'+%\1D(\19\1BdD3.8Q\5C\98\B0\CAG\8E\CF\C4\C5\90\B5\B5ixO@\B3pfa@?3^\B4\A4\93%D\A9^da\8A\01D\B2\B5\AD\A6\B6\A33w\A5\BB\BBA'ORG\0F\0E\0A\0C@\90\B9\B0tF<)'\19\17+?VnndK1\1B \1B\12\15$%\1D ]>\22\1FG>f\AF\90j:\C9\AA\BF\BD\A7n\AA\AE\86yT\A1xU>@+\09N\BA\B9\AA\14d\B4\9F\B0\AC\BDdj\A9\AA\99\B4\BD\BB\BF\96g\8A\9B}1M=>H\17\12\15\1B'RP55GT:!\04\12#?exkF'\1C\1D\19\1C\18 !\22\1Fb; \11\22\1CEy\1A.L\ACk\13\8E\99\88\92\D6\A5\BB\CF\B3~?Q&-&a\AD\B8\9B\18d\CE\B0\C6\CE\E2\98k\81\99\92\BC\BB\AA\B3\B3|\9B\B3\9A]IAQB9\14:<$/8\191JZU,\08\0C\180SzxW%\1D\1C\17\17\14\1D\1F\17\14a3\09\0F\0E\10\17X %K0\12\11\18\C5\C8\AA\C4\BF\CA\CD\B6d8#\1Cq\5CG]VV\22N\BA\C2\B6\C1\B4\A5NVz@i\C3\A3\94\BC\94\96\96vx_IMKF?O_@R;\1F\14+F]T\1D\1D,>Npx],\22\22#\11\11\1C\14\17\1AU:\15\18\1D\11\0D\1F\0D\15Y\1F-\13\15\92\E1\D2\CE\B9B\A4\B7\BF\95<Bw4J7\8E\9E\14K\9A\A1\C9\93\8A\B6\8FzT\15t\AE\AE\A8\C6\80IN\A6\9FNI5$q|X\80\7FjB\09\17\14)JYA4>I?[ob6F=?<2\1D\16\19\1C%P\19\17\10\04\0B\16\0D\16V\1D\122\19\08w\A3\A0\B9\A1\9E\BD\B3\84wt'\81\AB\89\B4\AE\13u\C2\C0\C1\AE\9Fw\A5\B1\A8,y\A1\B9\C8\C2\A7RR\A2\A2J37\0Fc\9Cv\7F\B1\A3H\09\0D\0A\05%GMFm\8D{\85\89uIOESPRC/\1C\1A\0DM\17\12\0F\10\10\22!\15U\0E\00%,\00\B3\E1\BB\CE\D1\8D\95N9?H\81\9F\A4mas\1F$[\19]\D7ld\B4\B5xDR\A8\C3\C2\95\B9\B3\83H\83K7. =\90\96\81\C4\B6yWQ\06\05\14&8d\99\AC\CC\CC\C6\D4V A3;9;43,+\1E \142F1\13\1A(EdK2(\12d\C0hdiv\83\81*L#I|\92h\01\1CKb\C5\A6\B1\D4\C9\AF\AE\C0\8Ec!W\D8\BD\C1\D1\B9\BC~~\5CV:#\1Ct\AE\B5\BC\B4\A6\88V\10\01\00\06\17?g\88\AE\C0\9B\C6\AD#\10*3(&:+,\1A\1D\19\0E%K#;\13;=e7QO\1D0VmQB\BB\8F\B6\8E\0D\02'N\90i\1C\22T\1B]\FD\A9\F2]\D8\A1\9B\C2\E7\8B\07[\CD\CC\E2\B8\DF\EA\BEp\5C+%\14\84\C2\C6\CB\AE\8A:\07\00\1Afn[yx\84m\AB\A7\A5\D9\B0RMD3\16&,,\05\16\1D\1D\07c\1E\8Be5<d\87L@ $36Wo\93\F0\BA\AC\CD.\00.\15\0B>%-\1A\00.\C2\BA<\EFb\8C\C0y\13\B2\A4^\B7CW\C2\C2\C4\BES\22 8U\AB\B6\AF\CE\99=\01\06@\A1\C6\B3\AC\B3\AAp\A2\DD\BF\B9\B5\88ZV9\1D\1B,+5\14\0C\12!`8\9C\8B\84=/uqe$\1B\05?\A6{\15\A3\CF\E0\B4\81\D4\9F\C1\CD*\143\17\1B\110\F04\B1\B1\95@\01\8C\BA\B4\CC\D3\D5e\BB\C6\96:p\81V7?MJf\92\9Ac50\1CW\B3\B1\AF\B2\AFt\86\9D\B2\C1\B4\94}U\1C\14\12:;\1F+\0AG\B1\92-\99v\B8\8D3\1B8M-\1EH\91\9FZX\A8\8E\B7\D4V\AD\CC\C9\84\00!1\15\09\00}\BE=Q\B1_H\17\0F`\AD\D6\B4\E5\DA\BA\B9\DFH\92\A0\81V>NB]oqZIRJ\03B\96\BF\B5hxZtr}\ABz\84B\15\19\1B;<%!\0D\1A\C9\BF4\AA\89\BD\D9\D0\98\1Ao(\0A\94\A9\A2\99\86\CC\CB\AB\92=e\CA\8E\00\09,6\13\0C\00$\A7R\1C\D9{f\0C5\17\00/\00\C3\C2\BC\AC\B0\AE=e\9D\88m(,}\92\93\80MaqS6\AC\BE\A5\9F\BFUA?!-?<!\15\13\10?=\22390$\89\18zZ\E6\C2\D2\BEP*3\12\95\D3\9F'{\AC`?\09J*\94\E0w\0054\1E\00+\BDu^%\9F\9D\D6g\16\1E\0D:<,Cd\A8\A3\B36\8B\DB\C1qD\8C\8F\8D\A5y~W\92|_\A6\A7\82\9C\BDl*+)\11(\1E\1D\17\13\12=<\0D#^z2u\CD\AC\93l\DD\BA\B7\89&%\1Fj\D0\9C\12\AF\E5\8B\00irc\0C\92\8D\A24*\00>\B1\BA\88^ {\92\D2\C1l\A8\91\08\C1$=E=\A6\9C\CB\7F\C3\E4\92\A9\8DZ\88m_bZ\99\8FVRa`c\7F\84&.$\1E\18#\17\19\1B\0C\10\1E\0E\00\04\16r\99\9E\AD\BC\BC/p\F8m\CD.\22O\B5j,\B6\C9\8D\00\96\AC~\AA\A0\86zk7\CCm>\98\EB\5C&\86e\B7\D9\94\98\9Fs\BF\B0\9B\90_>4\BA\92\D8\B2\FB`I~\8A8a7gx~I0\2290\8D\8A9!\22#\17\16\1F\1C\14\17!\1E.\01\13\1D\1B|\A4\AC\CA\DA\B0d\18n\BD2,%c\1D\1Fb\A40G\C5\99\CA\A7\9C\C4\C08\80\D9\AF}\991j\0F\80\EF\B6\C3\AB\5C%nVv\94b7\22\1E\150\E8\D1jWk\AC\1EGVXH>1B.@PDLo-*#\22\1C\1A1+\16\1D \90)\00\15\02\00X\A0\A7\C0\A8W\00\A9\EB2#\16\0Cb\00\17=\00G5\F0\90\CE\B2\BC\E1\C8\A7\CE\DFv\0CKm$Q\E1\C2\90\B6I p\A7]2,\1E\113+]uqI\D2\A2cWWA\22\22\16\15#Hgc:8/-(\1A\1E\22>9 %\1E\1E\B7p\00\08\0B\1A\00w\CD\94\D2\00<\E1S:#\1E\06%=\07i\1F$\07Y\E5\AB\AC\C3\DB\D3\AF\B1\DB\90J/j%2\C2\BCdS\19@1\BB\AF\84\19+\19 0\1EJlZ\8B\D2\C5\83jO*V@#$&D]Wg6W))\15\18\1D=:&7\14\1E\91L\05\0A\02#\00\91\BF\D7;\05\96\B3\89.,\18\09\18F>\15\0BA\8DW\7F\AD\8B\A9l\D4\B5\96\C2\CA\9AR:P<Y\8DT\00hh\1AR\A1U\0C\10<LH\02R|a\A2\F1\B9t\91*1XD*\14\1BAUdO]:L\1E\16\15\1C=:%A \1Cc(\05\09\0B\17*\DC\C4\FF\00\1A\E2\A4\82n\1D\1F\00\1FF)%'f~\9C\D1\9E\D7\F9\E2\DE\C3\E8\E2\CA\A3]?T3\83\9D\00\8BKr;\0B|^\1CEna/,\91hc'\B5\BC\B9\B76\12'.C-\07g\A3\86mMK(\1A\16\18#>@%2 \1F\87h\0A\02\14\14\1A\00\1E\0E\15O\88le&8\16\19\1FA=\0E\16;w:RbJ)\9D\C8HR\DA\9D\A6yRq\11\9E\D1\92\7F>~8\07FbaIIb\04\A6ju*%\01\B6\CB\B2<\1E\19-7)\16@\B7\C5\B4aB'\22\15\16(8D,\1F\1F!U >\00\14\11#,\13\17\00\93\D0IU\0EF\09$%:N\17/\04\0B\14\03>A\12\92\C5\86o\C0\DF\BA\A0\7F}<\AB\D2\D4\CF\A8\AE\90\BF\00\94x#B\1DO\B6_G\19^rG\A6\BF\93`\18\14/\1F'(p\A8\D1\98M'\11\0C\1D3AJ,\0F\07\15QB\0C(\00\0DZ\18\13#\01\95/\5C[\07D\0A,\1C\1C_\00\A0j\0E\1D\0CE+\15\F5\BFz\C3\E5\D1\CF\9Ba\8A\FE\AFv\F7\D9\D9\B7^ksBf\8A\0D\10\9C\80/\16\0F,\A2\8A\9B\A5\A7\ACX\03#\1F\87\86\B4\9B\C0\BE\A55\09\11\1C5KNF7\1E&9q\07!\0A\1FE\17*\0D\1C\08\017\1B;=\1B)!\0D%(\84\8F\08\16\10,XTH\98\A8\AC\C1\93\C9\B2e\00\E0\E7\FA0\03\C1\E9<N!\9F\8F\D4\002\00\09\0BK'AC\C6\C8\918RO\142S'i3F\B9\D2\D0\BD9\0F\19);HPp\1F$@ra\00\18X\95\1C\0F.\10\096>\01\00n?\10\1B!8\17\11\00+.B>\0C\7F\A7\BD9\FB\E3z\02\00\07D6_P\F7\A5\D4@o>\DB2\7F+S8$\111B{oy\91\7F\AF\BBT`_\0F!8\82\82\CE\A8\BB\CE\B3\90-+\1B\18Knz#\1D^IK\86\0D\22PJ\0Byo-3\1D\22\BE\D5z\11\19\19\0Bns!,B\0A+\05Bs\859J\F4\82\00#\10\14Y*<\E6\DBN\C5\EB\8B\93.\0AzuoZ68CR:\10\8B\91\9E\D2g\12%0# %\09!#x\A1\AFyD.\0E\168gzG\5CWS\00\5C\7F\14,\0Fv|yP/S\95\8C\B6A\11\1A1Af\BAt\16\82\0D\00?(7\18e\0A\1C\82\02\15.\08/:z\FB\13j\D0\B4\D4e\067\5C>}AY'\22\1E\02!oVw\D5\00\A3]\11\19#\1B\1B%#?i\AA}2\18\02\10+RNbaX\12\1B\00o|\17\22\8F\D7\9C\B9\9F|n\5C\A1@\16\0F;BAN9#\16*\0CX\00\17!wS+\00\12 6\1627\03%\9D@\00\0B\92\16BcD\5CNF\A7\1A\18\07\0C,<\05W\904\C2\AAU\19\1C\1E\0F\19\16\155|~R6\0C\1C$8=gk\87\0D\19)\18\8E-\1C\13\F3\CA\BA\AA\EB`o\8CP,\08#\15d\14\0F\09\00\0B%\00\1F\01g\8Ed\00\0CV(h>\0C\14023\135\8E\13<TdC?]X\02)\16\16\1C*2(,#Vx\8Bw9\12\14\08\02\12\16\07&3C:<[&0Gjr\A8\F8F\14)\00\138m0\D1\BD\9Cy\FB\AC\CAu\82s>\11Q\10+\BF\A5C\02\120\B2\A0r\00\8F\CC\BB\A9+($.#N9\06\11V\B4\1Eg\1C\17sb>\14A:7HVRQPA\179\5C\9A@aN:(!+['\19\0A IH!18\0C\00N\8C\BE\00\5Cl\12\0D\8B\C4\C7\D7:J]\D7\AD`:U_\151R\00f\DB\BE\96\03\97\7F\9E\9D\00\CD\DD\AD\BCg+0$H[{k8\09]\02X\0EQ`I<\14>-6D)9\1F\18<Z\084S\81\C3\81]NX\83lh4\1D/YM34T\01\03ZF\82\01\8A\C1\CC\85\9F\AF\B8\DCMg\B6\B9\D1\83h,0-\1AJ\16\00\88\DF\BB\B4\A2D\E291\A9\98\D6\D6\B2\152,<5Qg=& \162\02C\AC\B7\B1\1B#\17\0F\0ErP(-\1C\0C\09V\AC\AF\B7\B7}W}X\82Z;\12AoN%\22<\01\05\0C\1E\08\11\17|\C4\DF\D4\92y\C6\E6\E6\A2\D4\83C#'\0E\1E\11&+\BA\C0\B3\DA\B8\D8\F9\1E\16\05+\AD\A5\9C\005\05:4Dg\1F)\0E\10P \0Ec\F8\C3Vh\BC\CAWR\B6\8CY\14\12\12/0l\E1\B0\C6\CEbauZG)\0E*c5\1D\1C)\07\00\1Ff\1A6\09\00\9C\C5\E3\C7\CB\C8\EB\C2\8A\CA\9F\0E/ \004$\0Cl\96\A4\B3\B3b\9D\CF\01\0E\00gv\98\9F\00\22\99`M\7F\12\04g\13\1AN@\A1\E54\00\00D\A9\82\E7H\D0\C5|\05.]/GT7\E5\CA\CCaq\96\9A\88\8A\84}4I\16K)\16\00YK8IL\88q\E2\B5\86\B0\D6\D6g\96\87\D5\00/\12\05\0F5\18\1C?\7F\C6\C5\AB\A1\DB\CC\1E\00u]n\9A4\95^g\8F\91\00\7F\92}C\B3\B4k\00\09Y\C3\00\D1\9A\8C\C3\97\EB\A9\02-1G\9A\94\B0\BD\DAkG\BC\C7\97K5PJ2D\15D8\04\0B !M\87\C5\C0\B4\93\CF[\93\8D\C3\B6ad\93\01,\14\0C\0D\08! \19\1ERs\96\D2\C0\DF\D6\00-\C6\B1\B9\DCW\5C\844\A9\BA\9A\A6:)X-\14\18W\FFR\A2\BE\E6\D4\C0\C1\F1S\13.>\81\B4\A8\B6\E4\EDe\07\AE\BF\AB\A4mC\0A;<\1B\1F6\0F\0CU\1F\89\5C\AD\CA\C0\BC\EB\1A[\DD\9F\D0\B5\18\0B\13\0C\12\04\0EA\19(\1AnL\86m\CB\C0\A0\ABC\00\F7\C7\D4\F1\A6\8D\8DJ\1C\D9\CE\BF\0B@0gd<<\E6{1\83z\AE\D7\00wh\00k\88W\5Ct\82Ob\F9\82\CF\D5\A0\00\00\13!:M)'?\11\12WHxYJ\DE\DD\AF\B6\D3\DF\AB\E1\C1\88\08\0C\0B\0F\00\0D\01R\19\22-\AFP\9B>\A3\A2\85\00\8D\AC\C0\C8G\92\F8\C3\8C\B5\F0\9D\D8\D3\02UqY\1A\A0\E0\A8\99aQ\C1*\C9\03\D1\BEZG\81Y??j\04\04\D2\B1\D6\9C\EC&\0B\07\19_`)1=@\816|g`_\B9\12\93\D0\B8\A0\B9\A8\D1\00\0F\16\07\15\1A\1B\15\04\1E\18\8D\A5\BCm-~y\8F\B4\BA\C1\E7\A4D\08\A4\C1q|\8D\AF\A8\E3~$4\00\A0\88\BB\CBj\AAR;8\CB\E8\AA\98b*,Ob\849\0BX\C6\C1\ADV\A5\F6?!\0CI8*)1z|miQT\16HA\94\C3\DC\B8\D3\87\CA4\00\0E ./,\19#\1D\19&D\089NY\87,\8B\A5\BE\AA\CAY\C7\C1\C8\88\80\9Bb$\C5\EA:\00%Hr\EF\A15\00\13\00?\A3\9A\B8\96Ybhf{J\07Y\06~\E88\11>\C6uiC%\1C+2\1C\83\8D/\1C#[F#\10\16\CE\BCAT\C8\8Em\1A%\15\06\1D\05\1E\0F\11\1F\0B\0B+>&\08\14^f\B2\A1\9C\92\EB\AD\9D\87ob\18'#&\D4s\000?\14\EE\00\05\0C\01\12\22\86\8F\CF>Ua}\9A@\004\09#:d\16\13\19f\D61. 74.1\8C\89;\17\08Wn\00\17\02\1A\A2%Y1\BEvO\03\0B\11\15\15\0B\15\04.\11\17-3.\1A6\00\0D\FE\E9\B8\D0\96\F0\A8\90S\08\04\EC\CC\06\B8\00\22;4\0F\00\19-\03\0B7\1Chv\B6\1BD^\9E\82\0Av;\1E)?\15\12+,\0B`\07,33-35m\93D\00\01\00[A\07\0AKoJ\18\C7\8F\8Dc\00\0A/\0C\16\19\10\10&\0A\05<Y\08\15D\127\EB\DB\FF\C3k\FF\D3\C0z\0B\A3\A6\B2\17L#!O\190\0E,\0D\0D\13\07\1A<GS\1B3\85{\00]h\13' \1F\00\02\15h\06\8C+# *!6\88\90\13\18\06\00\02/\04\13EXb\84\DB\C7atS\00\12\12\08\14\1B\0C\0E\0D\14C\04\0C/\09\19\10L\ACU\17\19b\C4\B8J\13\B1\8D\DA\F2[\BB\80Uk\D8\5C\00\10\0F\0B9U\125\92\17VU\03X: 3\1D\10\0A*\C8\9B\A8$a\15\16\1B\1D1*\1D\98\9D\1A\0B\0F\0A\0C\0C\0A\19PPM\1B_\A1sh\15\11\0C\0F(\0E\12\0D\04s\D4m\C0!\1E7.\1B\0FO \DE>\08\06\8F\A8\A0\AC\B2\B3UUA\CDx7\89\D1\0B\0E\00Mx\22'K1)4\12+[C\0E\0F\06\16\1Ak?\1C\00' \18\1D\14 \1F'-\98\9B\0F\0D\00\00\0E\0C\04\22>5]8I\06'xn\00\10\00\00\09\0D\00 \BC(\CF\F3\E2\00\06\0E\14`/\18\B3\F8+\06V\DC\96\B3\CF\A3\A2\8A\CC\D2J+\C6\A6\BE\D3\AE\074'\228\1E\1F\0B3?7;WSF,2\1B \22# &\1F!\1A;9-4CI\00\00\06\03\0B\08\02\05,#\AA3L:\8DR\0F\00\00\10!<\05\00<\AE\C5i\E2\F4\F2\00\00RA\1B\10-\A4\00\00\83qqH\D7\BF\CD\AE\C7\D0\89\00\CF\AF\EA\D2\F0:#\1A\22\19\14\0C8<\12\16\16\1A.B^OV\1E\10\12\1D\16PM9\1E8&-FL[\02\04\09\12\01\03\04\00\00}c\1A\02\00\00\07\06\06\1C`>\04\16\1F\1D\F9\F9\D1\A4\EC\EF\A4\CE\AE\07B\A8\00\07\8C\00\C1\EF2\DA\B9\97\CF\D8\AD\BDK\DC\CB\A8\E0\CD\80\00'\14\03*34,\17\0C\0A\0A\14)\0A!\22>D\19\12NVUEQ1%#S[", [5310 x i8] c"\BF\D5\C2\9B\8Fc\93\BC\AF\A1\C1\C2\A4\BF\BA\B1\C1\A5\B9\D3\BC\92/\12\1F&$5+!,\16\13\1A\11\18\08k\BB\D2\BE\87^aJ#\118TjbMC.( 8B@/)'$.*7!!%&\1E$',!\0D\0F\11\1A$$\1B\15\13\1C\15\1B&1'\A7\BFbW\AC\88\96\D4\AAV\8E\C4\D1\AC\8Dp\C8\97\88\CF\BE\C6\ADj2\19\0E\07\1C(#'!\18\1D\18\01j\C1\C7\C3\C6\BC\C3\BDj8^vZI=?F4-A8-*#\1D&36;$/2-&&:</\16\1A\19\1E\1F\18\12\13\17\1B\13%A'(\8D\81/\AF\CA\D9\C2\AB\8855\88w\B8\CDT\9A\D6\C7\D0\B6\A2\BE\AA\806XK\1A$)*.&/!\0D?\83\A0\B4\C3\BC\B1\A3}XrjZ'0NH.)93' \1F\1E\12\1B\1B*/\1A0&!*@G>\1C#$(\1C\15\12\16\1A\1F\19.H\22\22p\0C=\DE\CE\C5\D2\BC>\00\0C\1B\08s\911\17\BF\D4\C5\B9\B6\8DnX:\8D\B2\86<.,\22\1E' \1B\109\85\A2\A7\90~r<^ik; /EF)#23\22$!#\07id\10\17\10\19&\11%?HD\1F(+0 \0E\0F\17\18\1E\1F/@&!\96\8C\7F\96q\BB\DB\A7ze\22\08\14\95fcQ$e\DC\C2\D1\8F\95\94\82J\8F\AC\A4}L\19\18.\12\14\14\1Bj\8E\AA\93WIQQ`W,7IH5'':#\1BP]\05X\B1\BC`\00,\19\1D\1C\22BLH$))3)\13\14\1A\19\1B\19'1E9\C7\CA\DB\88:|\D3\AD\C5\BD\B0j\A4\B9\8A\8C\C4\C9\A5\D1\D8\A7#\8D\AD\B2|?`ov~=\1B(\13\19\1C\0E}\A1\C8\C2aMIFA?4>JG022$&\1Ah\ACt\7F\AD\BC\8D >@A\1C\18<QS*$*:4'\19\16\17\18\11\19\1F67\9D\90\B5\DC\8C\AB\C6\8B\C6\C7\93\AA\D1\BD\C1\8EJ\8C\CB\92\B7\BFsE\96\AF\8ArU-gp\5C%\1A*\1F\1A\0Db\AF\C9\D8|8A>DB3OKGQ8#.4&A\B5\C9\AF\A8\B2\A5\83\8CtH:9<W]<3;GA1\1E\1A\1F$\1D\1D\19438v\C6\CC\DD\D6\CB\BB\BD\D0{\91\DD\DE\DAa\0B\C0\B3\AD\90\B5\E5\92`\94\87\95\A5\8D\9B\C0\B5@2\A9v\1C\053\CB\BB\C8\BD\82?6<'MYU_a?61,2\1D\8F\C9\B5\D3\CC\CB\BE\A2{J8IK]bRPTTK@9=;81+\1F61\16O\C6\A7\A8\B6\C2\B7\CE\D3ZC\82\BC\D4\B4\90\AC\B1\D2\9EPv|\9B\98\B8\AD\BE\B8\C5\CF\D5A9\A3\80.`W\C6\BB\AD\D4\C4\9Em<2MiNECGJ@</\16E\88\9B\C7\D6\D7\BD\A3\97nBEO^bglZ[RF<<740%!\22 r\09+?j\93\A8\A6\B2\D0Dpk\C5\A7\B4\BA\B4\8B\AFj\CC\82tx\98\96\8D\A0\97\A7\B9\BFA2t'2\80q\86\BE\C0\BA\C4\BD\C2a\0F0d\82c\22TOV<!\15\19Jw\AB\C3\D2\BD\AD\96x93=Q`r\80ncR<91%'\1E\16 \1E\1C`A4(5Yc\99\AC\C7H\88\CC\CC\CC\91\B5\B4hwM>\ADlf`?>1\5C\AE\A0\9E0L\AB[ip\A1\0CO\BA\B7\AA\AB\C5\BA<}\AC\C7\CBO-O[M\16\1A\1A\1AF\90\BC\B6{PJ72\22\1A1F`||oT4\1E!\19\10\11\22\22\1B\1C^;!\1BFHk\AF\91g9\C5\A9\C9\C2\A7m\AA\B1\85xR\9BqT>C*\08L\B4\B2\B5\1Ei\B8\A0\B6\BB\D2ot\AE\AE\9A\BA\CC\D0\CA\A3t\99\AB\892HHKU&\22!\1C\22QR:>Q_D+\03\14(Ho\83uP-!\22\1D \1C$'\1C\18m;\1E\0B\22&Ir%.J\A6k\1D\92\92\88\91\DA\A2\B5\C7\ADz?P** Y\A7\B4\A7\1Fg\D0\B2\C6\D1\EA\A4r\84\9B\94\BC\BE\B2\C6\C2\8C\AC\C0\9E\5CGT`RJ!>;\2218\188Tb]3\0A\0C\177]\82\80^+%# \22\1F(* \1Bu9\0B\13\11\13\15Q4+M4\15\14\16\BE\C7\A5\C5\BA\C9\C5\B1d7\1E\1Dl[?XVb(O\BC\C4\B6\C1\B6\B1TW|Bi\C3\A5\98\BE\A2\A9\A3|z[MOYYLUa<S?&\1C1PgY\1E!3FTz\82b1)+-\1D\1D)!\19\18jD\1B\1E#\1B\15\1D\22\1F_%3\1D\1D\90\E2\D1\CB\B7D\A3\B9\BF\96;?u6I9\8E\AB\1AL\9C\A2\C9\94\8A\C3\95{V\16t\AF\AE\AA\CB\8BSR\A7\9FMK:/{\80Y\80~jK\1A%\1D4V`A=OWHf{i:KCHF<' \15\154T\1B \1D\15\1C!\1C\1AX&\1FC*\13v\A5\9F\B5\9D\A1\C5\B4\83ys#}\AE\91\B5\BC\1Ax\C3\BA\BC\AE\9C\85\AC\B4\A9&t\A1\B6\BD\C1\AD]a\A9\A7T(6\15n\AB}\84\BB\A4O\18!\1A\121SNM|\A1\8B\92\95\81JQIZW\5CJ6\15\12\16[\22%\1B\1B\182*#`!\0B04\09\B4\E2\BC\D0\DD\95\98T:@I\83\AB\ACpg\85!\22W\1Cd\D9cv\B6\B3tGY\AA\BA\BF\94\BA\B7\89P\82J4-!A\96\9E\80\C3\B6y]X\0E\06\13%8d\9F\B3\D4\CD\C5\D3_'I:BAD@<36.'\1B9P4\1D%8LkR<+\1Ck\C0gcj|\8D\891L\22H}\98r\09,Ob\C6\AB\B4\D4\C5\BF\B2\C0\8Fh$W\D4\BD\C8\D2\BA\BF\8A\80\5CVA$\1Dw\BA\B7\BC\B7\AA\8CZ\15\03\00\07\1ACk\8C\B3\C2\9B\C7\AE&\14.5.,@33'+!\14&P)I IEk8VU+8^pNE\C1\8E\B6\96\15\05$Q\96h\1C6_\19[\FE\A7\F4Y\EC\AC\99\C0\E8\89\09W\C8\CE\E5\B7\E2\F0\C6xW-(\13\87\C8\CE\D3\AF\90>\08\00\1Cfl\5C\7F|\85n\AD\A7\A3\D6\AFRNE5\18(34\14#$!\03`!\9AtBCh\83IC/)6:Xr\9F\F3\C2\B1\D02\001!\0EF<;\1F\010\C0\BE<\FFp\91\C1{\11\B6\A4^\B5CU\C8\C3\CD\C5S 6[\AC\BF\B6\CB\9E=\00\04D\A2\CB\B0\B1\B3\A9n\A6\DE\C4\C1\BC\8E]V6\1A\1757?\19\0C\0E\1F`8\A9\95\89=+sqe1%\0AD\AC|\1A\A3\CF\EA\B9\86\DA\A0\C6\CD*$9\1A \1B3\F38\C1\B7\98E\0B\8F\BD\B8\C9\D4\D4f\C2\C9\9FCm\82U8FPSo\97\A2c40\1EY\BF\B6\B7\B2\AEt\88\9F\BE\CF\C1\9F\86Y\1F\18\17;>&2\12H\B1\93/\A1}\BF\954\1B9O5,U\95\A3ZV\A7\91\C5\E1Z\B1\CC\C7\83\00$5 \16\07\80\C5JT\B5jU$\12g\BA\D6\B0\E8\E0\BF\BD\ECR\92\9C\84\5CCROgw{^JTQ\0BL\9E\C9\B9iza||\91\BD\89\8FJ\1D\22&?@& \16!\CA\C27\B0\8A\BC\E2\D7\99\1Dr.\1A\A4\B6\AB\9C\86\D1\CF\BB\A2Jn\CD\8E\03\0D$8\19\18\0C&\AEZ\14\DB\81r\1A7\1E\027\00\C8\C5\C2\B1\BC\B0Eb\A2\8Bs-8\7F\95\99\87Oex]A\AF\C4\AC\A1\C3\5CKJ/;KH-!#\22AC$3A8,\8E\16}\5C\E6\CA\DA\C6U(6#\A1\E3\A1\22y\AFfP\15Z,\8F\DEz\02+4$\09?\BEwa\1B\9F\A3\E9{\17 \108@/?e\B1\A8\B74\8F\DE\BDrM\91\93\95\A9\81\84V\8A}k\AE\AB\8A\A2\BCd+72\1C4*)$\22\22CB\161i\8D>\80\D5\BC\9Cz\E8\CD\C3\94.5 k\D1\9E\1E\B7\E8\91\00jse\18\9A\90\A8F,\00:\B4\C1\8AU2}\90\CE\C4s\AA\88\05\C0%AKE\A5\9B\C8~\C4\E8\98\B1\8CY\88meib\9A\8EURafj\87\85%--% *\1E!$\18\19%\19\10\0B\1Dy\A3\A1\B7\C7\CC6w\FFw\D08)O\B4i-\BC\D3\95\04\96\AB}\AB\A6\90\82{;\CCnC\9B\EBX6\8Ae\B8\DE\97\98\9Bs\C6\B1\9C\93k@4\BA\99\D9\B3\FElK~\8D<e;lz~J3&=4\92\8C9\22#&\1B\1A!\22\1A\1D)%;\0F\1B#\1C\81\AA\BA\D7\E8\B8j\19s\C3@4-f\1A\22h\A30O\CD\9C\C7\AA\A2\C3\C0L\8B\D7\AD~\973f#\8B\ED\B4\C4\A9^!iXy\93e=*&\102\EB\D0m]s\B4\1FMZYI@1@/FTEMq-( !\1C\1B2-\18\1F'(\9F6\00\19\00\00[\AF\B6\CD\AF[\00\A6\EEA(\19\10c\02#@\04L8\F4\91\D1\BE\BF\E9\DF\B5\D3\E0x\0AOm;_\E6\C3\92\B4M n\A7[8-'\183)]swJ\DB\A9`\5CW@ &\17\1A Mgb8<020!$%>6\1D!'*\C1u\00\04\09\1A\00\84\D7\99\D2\00:\E1SG-#\0B+>\0Ci\1F.\0C^\EB\AC\B1\C3\DB\E3\B5\B4\E0\9AM2n58\C5\C1nV\1CD.\BC\AE\85 .\22)-\1FIma\8E\DB\CE\88rO)VB%0+L]Vg8Y57\22#&A=*<\15!\98S\0D\0B\02$\00\99\C6\DEC\06\96\B4\8B6:%\0D\1CF<\14\0EO\9A[\83\AD\89\A8o\D7\B9\A1\CF\D7\9DYGS@d\9Aa\01ou\1AN\A4[\11\14IVH\00U\82f\A6\FE\C3|\9B.2ZK2\1E#KYeQdBV2($'EB.L$ d'\0E\10\0C\1A-\E2\C5\FE\09!\E3\A7\85t-/\0D(I)*+v\8E\A9\DA\A1\D7\FE\E6\D6\C5\EE\EE\D8\A5dGL5\89\A9\0A\8DRzC\08\81a\22Jzc7)\96ki,\C1\BE\BC\BD=\14+5M8\0Am\AA\88qTU3($$/JL5D\22%\89h\12\0A\1C\19\18\00 \0E\1DW\90qc)I\22)!<;\11\1CL\83JT]H,\A3\BEHX\ED\B1\A7{Ug\11\A4\E4\A6\80@\816\0BI^bRNf\02\AAmq+.\06\BA\D3\B6D$\18%85\1ED\BF\CB\B3YC3+ \224DQ;/%'a+G\0E\1D\13#-\1F\22\09\A1\D9KU\0F[\1A2(;S\1A0\19\1C\22\06?F\15\93\C9\86m\C2\E3\BD\A0|\81<\A9\D4\D8\D2\A8\AB\8C\BD\00\99\81*?\17K\B4^L\22eoA\A2\B7\94j \15.&# q\B2\D9\99L.!#*6FP4\16\17,VN\1A9\08\1Ae\1E\18/\0F\A6<if\0DW\1F:\22!g\03\A3}#+\12J3\1B\F8\BE}\C5\EE\D9\D2\A0c\89\FF\B1\7F\FF\DC\DE\B9^kqGu\95\13\0B\9C\80-\1B\1E7\A8\85\9C\A6\AB\B3X\00\19\11\88\87\B8\A2\C0\B8\9B'\15!&9II>-+)?~\15.\12-T\1F0\1A*\15\09E*CJ-8+\16+/\87\9C\1A%\1A5^[K\9B\AA\B2\CB\9E\D2\B7f\03\E2\ED\FF;\0C\C6\EA7O&\A7\A0\E3\070\00\0A\10S8PM\C4\C9\96>ZQ\0E'>(n9N\BB\CC\C5\A89\0F\1F5DOZv$*G\7Ft\0D\1E\5C\9B\1C\16;#\18<B\07\00}O!(*? \19\0B;?OG\13\88\AF\BC>\FF\ED\85\0A\05\0DC;cZ\FF\AD\DCFqA\E0C\92<]<&\146S\8E\80\83\95\8B\B8\BEVbZ\08\15D\8B\85\D0\AA\B6\C7\A7\8B$--'X\82\8B+$iUY\91\14 PF\16\85}8:\1B\22\BA\DC\84\22) \0Eqs(6S\1A2\08Es\84:J\FA\8C\0A2\1A\13Z*B\F0\E7]\CF\EF\90\9B>\19\8B\84\7F^;@SaK\1F\9B\9F\A8\DBo\17(/$./\12)({\A0\B0{7.\1F\17,`nSle_\07]\80\11*\07\84\88\82Q0P\93\84\BCO!.<Bk\B6z$\92!\0A@-3\1Bf\0A\1F\8B\10\228\0B0:}\FF!w\DA\BC\DCj\0CAdIzIa,((\0A,l\5C\81\E0\00\A4`\13\1F)%&($Bk\B0\82 \17\1A\14#UJlea $\03ox\12 \98\E5\A5\BC\9FxiZ\AAP!\1DC?AKB3!8\14U\00\14#}U0\01\16(9\1889\08*\A1H\00\0F\95\18FgC\5CEJ\AA\1C\1C\0B\0B,3\0Ad\9D:\C6\AEW\1A!+\1C\1F\1A\197}}40('%LOef\97\1E\1C-\1C\95/##\FF\CD\BE\AE\F2bv\94`;\161\17_\0E\17\19\08\193\00\1A\00i\92f\00\0EX*f@\10\16145\153\8F\13=XdB=ZY\02*\1A\16\1B(/1<,Xy\8Dw4\1B$\11\04\13\18\07!B-5TV\131Fbh\B4\FFO\222\00\139y;\DA\CB\A5{\FB\AD\DF\86\90v?\16T\11@\D0\B3F\03\173\B3\A4r\00\91\D0\BE\A9(,$,%R<\06\0ER\B2\1Dl%\1Ep\5C:\12@?@OSLMHB!A]\99G]F;2),Z.)!-LM'9?\1C\0DS\98\CC\0Aiy\1D\13\90\D0\D5\E8GWh\DD\C0uH[d\1D7U\0D{\E9\C4\9B\0B\9D\82\9D\A0\00\D6\E5\B0\C1i*3&Qc~p:\09]\00]\1D\5CfD<\14<2EO/4 \19@a\08.Is\C4\82aUX}bZ@-9]K.,J\0E\06`S\90\0E\92\CF\DB\8D\A5\BC\C6\E9Uu\C5\C1\DE\95w693!M#\0A\97\E9\C4\BA\A9G\E5;7\B3\A3\DF\DB\B3\1842F@Zl>!!\1B:\13R\B6\B5\AC\1C(\1F \1D|N)2\22\14\0BP\A1\9A\B8\BC\83_\7FRwE;\12G{W,,B\06\0B\13+\1B \1D\80\CA\DF\DB\9F\8C\D5\EC\EA\A8\D4\92S44\17%\1A.:\CA\D1\C0\E3\BF\E1\FF\1D\1B\095\B8\AD\A4\034\0A>>Oo'/\10\13U1!t\FF\C7Xk\C1\DBjc\C0\90e\1D\15\141+e\D5\BC\CF\D1dcpS;$\05,uD*0:\0F\06*r(A\10\00\9C\C1\EE\D3\D9\D3\F2\C0\8A\C6\A6\18@0\077'\0Cs\A0\B5\C3\BAe\A0\CF\00\0F\00m\80\A4\AE\07!\9A`S\89\1E\13q\17\1FVP\B0\F6C\0C\00I\B1\92\F6Y\DF\D5\8A\0F7e4JS8\F3\D4\D5iv\99\99\89\8Cw}EJ\0AD\1D\22\0DgWAJM\85o\DA\C3\92\B9\D7\D7d\94\7F\DB\0D?&\10\10:\14\22M\8F\DA\D0\AC\A6\D7\CF\1F\00xf|\A7>\98_g\92\9A\0A\8C\9C\85K\B8\BAu\05\14V\CB\08\D6\A0\96\CB\A2\E8\AF\0C84H\9D\96\B6\C3\E4vJ\BD\CA\99Q:>IJH\0DG4\0E\0F)/V\8A\C5\BC\AF\91\D8i\9C\90\C3\B2\5Cb\9C\117\22\14\0A\08\1E)))`{\93\D2\BD\E1\DC\002\CB\B5\C1\DFYb\869\AE\BE\A2\A9>,Z1\18\17W\F6V\A5\C0\EA\D8\BF\C1\E8X ;D\85\B8\AA\B7\E9\FAr\0D\B2\C3\AD\A5l%\04WG\1C3H\0D\07e0\8C`\B1\D1\C2\C3\FB+^\E1\A3\D7\B7\1F\13#\1B \12\10<\130*}Z\94o\C6\BA\A2\AFE\00\F9\C9\D6\EF\A8\91\8FK\1E\DB\D0\BD\0C@1kd;:\E3|1\84~\AE\D6\00tq\0Et\8AX^t}Xr\FF\84\D0\D7\A0\00\09\00\1CRH\16(>\09\08j[\84_G\DD\DA\BB\C9\E6\EB\B1\DE\C0\85\14\15\18\1F\0C\17\00[!+:\BF^\A5:\AC\AA\89\00\84\AB\BE\C7F\8E\FC\C2\83\B4\EE\9C\D7\CF\03WpT\12\9F\DB\A2\9AcP\BC\22\C8\00\CB\C8jR\8Da??h\0E\14\DD\BD\DE\9C\EC$\00\02\19[U\17\1D+0|E\8DucZ\BA\13\98\DF\C9\AE\BC\A3\D2\00\14 \12!'%\16\0C%\22\98\B1\C9w.\86\80\97\B5\B5\C2\E8\A8H\06\AC\C2l}\8E\B3\AC\E1\82)9\03\9F\8C\BB\C9n\AFW>7\CF\E8\A8\A0n27Zj\8CA\13d\CE\CC\B8^\AD\FE:'\19Q8#!,zxtt`]\16OG\97\CA\E7\C7\DC\87\D1:\00\14+982\1C)&\1F1O\11?Q_\90:\8E\A4\C0\AF\D3_\C8\CF\CB\87\82\A0k*\C6\F3E\06/P}\F3\A2>\05\1F\04G\AE\9E\B9\A1emtt\89X\15d\12\89\F4F\1FL\D4yyY6&,1\1Ex{8%-aC\22\14\19\D7\C5KZ\C5\8Dq\1D+\1E\10$\09!\10\1A%\14\152B)\09\1Dlm\B6\A6\9F\96\EC\AA\AB\8Esg\1B+$#\D4x\089J$\FA\08\05\11\0B\1B-\96\9B\D9Pcm\8A\ABT\07B\1B1Fq'''t\DDCF7I@8<xw?\1D\11_o\00\1A\0F\1E\A8.a2\BCy\5C\0B\14\1A\18\15\0D\13\076\1A 030\189\03\12\FF\EC\B6\CB\92\E9\AB\95V\0B\02\E7\C8\00\B4\00)?;\1B\07\22)\03\12;#t\80\BF-Pi\AC\92 \87K05J#\22A=\1B_\12>DA5:>h\99B\04\09\04]:\05\0EItR \C9\88\8Bg\05\139\0D\13\16\0B\10/\13\0F=V\05\10D\0D:\F1\DE\FD\B7h\FA\CE\C3\80\0E\A0\9A\AF\0FG\22%Q\1D7\164\08\0C\17\09\1ECO[-?\92\88\08sz!9,-,\0C\18'v\05\96=4*,\227\95\98\10\1C\0D\03\04*\06\1AB\5Ci\89\DD\C2c{Z\05\1F\15\03\0A\18\0C\15\16!F\00\02,\09\11\11U\B3R\0C\14]\BC\B9S\1A\AE\82\D5\EDV\BA\84Vo\E1f\07\0B\0E\0F:Y\1B?\9B+cb\11jN0>1\1D\178\DA\AF\B8/^ ),*7.\22\98\96\19\0D\15\10\0F\06\0A\1BORS!b\9Bsj \1C\1A\11$\04\11\0B\0F~\E2o\BC\17\1D5(\1D\1DX\1E\D68\01\00\91\B6\A9\AA\AA\ADNP@\D4{=\93\DD\15\09\00T{(1W;>A\1F:mW \1B\1B#'zQ0\0F3\22'4).',3\90\96\22 \0A\03\0B\0B\01.QHi>F\05$\84w\07 \09\09\05\16\06)\C98\DD\FD\DE\03\0E\12\13W.\16\B2\F7'\0AU\D3\95\B1\CE\A2\9E\8B\CE\D1E#\C5\A1\B8\D4\B0\06/\1F!3\18)\1B>K?;WQP<='(\22#\1E\16\1A!\160'\19\223D\0A\0A\14\06\06\09\03\0A;4\B86G;\8EW\19\09\0C\1D+=\0D\01F\B9\D1v\EC\F5\FA\01\02S<\1C\111\A8\00\06\84lrI\DB\C3\CB\B2\CC\D5\8C\00\D3\AF\E8\D6\F5?&\19&\19\12\14DD\1D!\1E\226JjWa)\18\1A%\11VZA\1E1\1E(FHb\0D\13\12\12\08\09\07\03\08\8Cl\1A\09\03\00\0D\11\11%fA\0A\1F%(\FF\FF\D7\A7\F2\F8\B2\D1\AD\09G\B1\00\08\9A\03\C0\F17\E3\BF\98\D8\E3\B9\C7S\E7\CF\A9\E9\D8\8C\06/\1F\07+>@7#\1A\18\18\224\16,.LR' RfkV[2$%HI", [5310 x i8] c"\EC\DE\B4\96\A9\95\BB\D4\DC\AA\B3\BD\BE\F1\E2\C9\C1\BD\D8\E7\9E\93\0C\00\1F>CI\0D\22\09\00\00\03\180\1C\93\D3\9F\A9pey^K)\05 ?=%\1F\13\19\19\04\17\1B\07\05\0C\15'.2\1B\0A\00\15\14\00+'\1B\00\00\00\10\00\09\03\00\01\0D\09\0F\1C\16\0F\B9\CCkh\B9\8E\AF\FE\BCc\97\D5\DE\B2\A6\9A\DA\BC\B3\F4\DD\F5\BCaD>9,;W2\1E\0C\00\170.\99\CB\99\AE\AC\B6\DB\EA\99B0=B1\0F\153'\1C\08 \15\00\00\0A\19\22*4\1F\0E\00\02\14\0E.5*\00\00\00\0C\07\05\02\05\0B\12\0D\1F>\11\16\A8z\0F\C9\F7\DB\D4\D7\A3.\15\A2\A4\BA\DF\80\B6\F8\E7\F0\DE\C7\EC\CD\9CXxkBIWM \15 .8UbX\A6\B2\AD\BE\CE\937*=4\06\0C*;<A\0C\0D\06\00\00\11 3.&\1D\00\00\00\00\0FSC,\00\00\00\00\01\00\00\06\0D\12\0E\22?\13\16r\1F9\F9\ED\BD\E7\E0@\12\086'k\A6U6\D9\D9\E4\DB\CD\BB\A4wT\92\D1\A8S\5Cb\1C\1D*,7\1C\1CL\9C\A6\93\8A\8EHA0C\05\00\08\142EK\0A\00\00\00\00\0F#\91\8E'\13\00\00\00\00\00i_@\00\00\00\00\00\00\00\00\00\05\06\16&\1A\17\92\AE\94\C2\89\98\DC\D3v\8774,rg\8FwLh\FF\F2\FF\BF\B6\BA\AAM\BE\DC\DF\ADm\15(M+*6<u\8A\BA\B2p_srk\1F\0D\1D\1D\1A$,*\02\04\01$/\00]\B4\C9|\0C\0B\00\00\00\00OhV\03\00\00\00\00\00\00\00\00\00\00\09\132)\A2\E2\E7\89C\81\EB\CC\A0\D5\BCk\AD\BE\A2\AB\E3\FF\BB\F9\EA\E0K\A9\CC\E8\92gr\A8\9E\9A95T,%>@\A4\9D\E2\EEzYkxhdmI\1D\1B\0C\1AAI_%;\80Pg\BC\C1\7F\00\17\1A\05\00\00AC1\03\00\00\00\00\07\00\00\00\00\00\00\04(+e\88\AB\CE\8A\A2\C8\B3\8E\BF\89\9C\CF\B4\C3\B6`\AB\E6\AA\B2\CD\80k\AC\CE\A5\8AP;t\96U=9912)\86\A8\E1\F7\8BJYZhNPeURUBM:Q<K\C0\CD\B9\D2\CC\8A;[a\1E\00\0FV<\15\0B \11\07\17\10\00\00\04\0A\03\03\00+-\0Fw\C5\AF\C2\B6\A9\BF\94\D1zt\C2\BE\B8e*\BB\C3\D0\B1\BA\DA\B0\7F\8F\97\B8\C6\92\90\DE\A4RA\BB\A6D\1Fj\BA\CD\D7\CF\B2gPsOm{W4QU@YLT\1Fd\B9\CB\DD\E8\D3\97eW/\12#ge;\15,9.%\16\12\1A\19\17\0F\09\000.CX\B8\A2\C2\E8\EA\CF\FB\DCL>\9C\EE\FC\CC\90\C4\D0\E6\80QSc\9B\B0\D7\C1\A0\B9\A2\B6\C0*@\BB\94Vx$\B1\A4\B4\EC\D8\C6\85\09\00\22D&!(8C\0C\11\0A\00!m\8C\C0\DA\D2\B7\8Cq]8\1DSY\5CPFIQ*+$&%%$\19\17\07\08\84\164Pw\99\C1\D0\C4\DDM\81x\CB\C0\DE\CC\D9\B6\D4\89\FB\91k\8A\BD\C1\B2\BF\C6\B6\B0\AA',\8CTa\8ACq\A4\BA\D2\F1\EC\CC3\00\18LT9\0FG>\1D$\09\00\007j\9A\B7\CB\B8\8CXM'\1B1J[QBCQ:))#\19\1E\18\10\1D\08\0A{:\14Bb[u\C5\C7\C0(\A2\F9\CE\DE\BD\D1\D6\88\97uc\DB\8F\82\82_^Y\81\DC\C3\90\1F=\B8\86\7FOY\00>\AB\C4\D5\C1\A4r\0FW\8B\A3\A7B;g.'\00\00\00\0DT\A8\CF\B2i-\0F\00\0A\07--4=AAG9\1F\0B\11\0C\03\06\16\19\0C\10`N\1D6e@\80\D3\93z5\E0\C8\C1\D7\CB\8C\C4\B6\A4\9Ai\C9\A7sXHI*c\E2\E8\AF\1Dl\C4\BC\C2\9E\99is\B1\BA\B6\C6\AF\97\A2mHrzuNp \15)\00\00\0D8J{i6\1F\1D%\0F\00-+$);I@\1B\0B\01\04\02\07\03\0B\0D\10\0Ei]37:\03J\9E!P_\D2\83\00\93\BE\AE\B9\DD\D1\E5\FF\DD\9Bex-YP\94\D7\D5\A3/\86\E9\C8\E8\F2\F5\A0\82\A3\B4\AA\DE\DF\BD\8E\A3r\80\92\8DaJ\1CA8\1E\00-@%>T&\17\18'!\00\17(%\16!GD\1B\05\00\01\01\04\01\0A\0C\0D\0BPQ\17\14\1A\18-p\0FCY5\1E\19.\DD\E6\DB\DB\E2\DB\FE\D9\80VT3\94mx\80r^B{\D5\D0\D8\F3\DD\ADn\83\95N\8B\F5\CC\BD\F7\AD|wXbjr\88d, 1IKX1\04\00\0B\14 !#\13\11\1F.>;*\11\0A\0E\13\05\05\0E\06\0B\0C2<\11\10!\12\17E\00\17U\171\14\1F\B8\F8\F0\E6\CF?\B1\C6\E5\ACZZ\8D1WF\B4\A42k\AB\B4\E1\B0\AE\BC\AD\9Ae(\8C\CB\D2\B6\E8\A1]]\AB\A9wWWE\85\8B]\8A\A8\840\00\00\0A\0A\166[\22\07&5<;?\19+'-,\22\0D\05\0C\0F\0BU\1A\03\02\00\00%\00\1BW\09\04#\08\17\95\A0\AF\D8\BE\A6\BA\D2\A2t\83F\9E\B3\86\D3\AB,\87\D5\EA\E4\C8\D3t\BE\C3\BBV\9C\BB\ED\E5\E1\CF_6\99\BD^PV7p\80m\9A\C5\C0W\00\00\00\00\0B-jUUdgwo[ *&86:(\14\0F\0F\007(\08\0D\0D#\15\0B\00f\04\00\22?\00\C8\F8\D0\E7\B7\88\ABTNV]\9A\85\9F\83g_77\89G\81\FF\A2P\CC\C8\A6rv\D1\F9\EA\BE\D6\C3\877\92\5C_W=M\94\85\90\D5\D8\9D]P\00\18\18!Z\88\9F\AB\C5\DF\CA\CFD\06\22\11\19\18\17\0E!\12%\09D5AH_)\14\13i\85Z4V([\DA\89\8D\88|s~!fDr\9B\98X\00\0FXb\C0\AE\D7\EC\DE\A2\BB\C0\89kGo\ED\D9\C1\EE\D9\D0d\8Cvr:@<\88\94\C3\D6\BE\B6\97e\18\12\09\01!Ov\97\B6\D1\A5\C1\B2\1D\00\0B\0D\02\00\10\0C\0A\13\12. 8J7<\0C0RwJPc\1E+O\7F{X\BD\BA\DC\89\06\14Qd\92\94B\10Q$`\F9\BE\F3r\C6\9E\A4\C5\E3\A0\08p\F0\DD\F6\DF\F5\FC\B9m\7F<9;\9A\D4\C1\C8\C5\82?\1C\13(~\81rq}\99\82\B9\BF\B8\F5\BDH/\1D\06\00\00\0A\0B\00\1C4,&}D\97S;Ss\A6ff,-IFn{w\FF\C5\B5\E3>\14:\00!I\10 \1B\00\22\CB\B0D\DAU\8D\BCm\1C\A8\ACj\CC[\86\C6\EF\CC\CB_78gY\D8\BE\BC\F8\97G\12\19G\B6\C5\DD\AA\BD\BB\83\A9\F2\BE\B6\AAt><#\0B\0B\08\056.>@7l^\A0\8C\9Eo]\8B}\8B(\1C\1FJ\9E\90\1E\C7\FF\E1\CE\8C\CC\B4\CA\F1\5C\1A]E&\008\FFQ\B7\DB\C3K\00\94\D0\D1\DA\D6\E2|\BA\DC\9EJ~\84cN>cRv\91\8Bo:2\1Be\9B\B0\A0\BE\B4v\85\AB\9A\B4\A5\81kA\0A\00\00?5\04+\15f\C9\97E\A3[\B8\98R3=e7\11:\A0\A6r\88\D3\B4\AA\C6e\B4\E4\F9\AF E[4\0F\00\91\CF8u\DB~N\08#q\A8\D6\C9\D5\C6\AB\C0\C1G\92\B5qB/U$\5ChVMB<(\001\8F\A4\A8ab8ca^\8D^o1\06\07\06&\1D\04%\05+\E9\CB@\AEh\C1\D1\E1\B8&{,\00\80\88\8C\A1\A8\E6\E8\96~\1CO\D2\B0\18&9G;$\00<\B6d)\EA\A3~\03M&\0C\08\12\AA\B2\9E\9B\8E\C6\16w\84xO\17\0A\95\B8\95f7@L+\17\D2\C0\8B\89\9E0\19 \0E\18% \07\00\00\00\19\17\00)6B.\92;\84\1B\DC\BF\E4\C8YM=\00\97\A5\AEX\A1\D0t,\0B\1C9\C5\FF\9B\10\1F(>\00\00\DD\90\84\0F\93\BD\C9<693C(\14PUx\90\BA?w\C3\CEb\14y\96\A2\B2XXD\B1\7F9\BB\B4av\AA\8B-\05\13\00\04\00\00\00\00\00\15\12\00\0Dop0r\E0\9F}V\EE\B0\B5\869\184\81\E5\B5\00\AA\FB\91\12\80\87|\00\8D\A3\A8 B\12l\DF\DE\B1\94\0C\93\A5\FF\EF\90\D1\C70\EAAMI,\B5\AD\F3\A8\E0\F4\96\98\9Ck\AA\91eaS\AC\93Qt\85fbx\97*)\12\04\00\01\00\00\00\00\00\04\08\00(7\81\9B\CC\C3\B6\A7S\91\FFo\FBD\19i\D6\93K\BC\B9\8A\00\B0\CD\A7\C9\A6vw^D\CChF\BE\FFq\19\93e\B2\E1\BA\B0\B4\8F\BF\CD\BB\A4ELN\D6\92\F5\D2\FFFW\98\94HpFo\89\88D:2H?\95\9BC\1C'\1D\02\00\00\00\00\00\02\00'\00(/.{\B8\AD\C3\CF\C5v+m\D13'\1EuG5d\CFVB\BE\AB\F4\BD\9E\EF\E6&}\E2\B2y\AE2\7F\00}\F8\B9\BF\C0]:\91g\8A\BBxI\1D\1B8A\FC\F8\80if\A95?[m]LIUE8UYa}E=?/\12\00\0A\00\00\00\00\00~/\10$!\19~\AC\95\C6\BFf\1E\C3\FF>,,\1Cy\0B\00S\07PK\FF\A7\DA\96\D2\EC\B3\9A\CF\DBj\15Au\0FD\E2\BE\84\BF?(,\85\BF\8C6Y&\1E?@u\A4uv\DA\AF\8DUaR5)+\14MFqtM?D,%\0F\0A\06$#\0E\15\00\00\B8\8A06!&\22{\CE\AE\FF+R\EDy>$8\11\1DR\10\8DQ%!d\DD\C0\B5\E7\FF\D9\D9\DF\E6wRE\87+\5C\F0\C7K[/]?\BE\BC\9B\18A!0>!W\83Y\A1\DA\D5\82[[/X?1\0C%5i\5Ci5e\11\1C\06\05\0B)(\11\1E\19\18vL\10)\1A(\14\9B\A4\D7F$\AE\B8\A18\1F\0A\18\1F^n@14\7Ff\86\C5\BB\D4\92\F8\DF\B5\C8\BB\AEc5tfx\93E\12yc\1Ag\91A\00\17\1EKH\17BhR\A9\D3\B8mv\1D*B\22\19\03\14&H]9;);\00\00\00\07,+\13,\0B\00B,\00\1A+#6\E0\A3\FF\00+\FF\B0\8Er\08\0B\00\09NK?DQj{\BB\A6\F9\FF\FF\EB\D4\FF\FA\C1\BBlQaD\AB\B5\00\A3Z\84\14\1DcN\004Ly\08>xXE\16\93\D4\DF\B9\1C\00\06\09\1B\0E-i\89pL(#\09\07\01\00\07$$\06\10\00\00H^\07\14\1E\1D=\07\00\04\12a\92u\880%\18\00.rc2*(y\0Ca\93pM\B1\B2<r\CDr\C6\94x[\05\BE\C4g\9FY\A4A\00.oR\196i\0D\92R\82\1B\00\00\BD\E0\BF\1B\00\06L:\03+M\96\9F\A1\80E\01\0C\00\00\02\16&\12\08\00\001\096\00\0A\22%\1D\00\00\00~\C6ZW\002\00\0F-?=#O\00\00\00\0BC0\1E\B2\B1\90\92\D9\EE\D0\B8\9BiF\CE\EB\E3\E5\C0\CA\A5\C0\04\85b\096\01d\B7c8\03Df+\A3\E6\99G\13)<\04$Ov\8F\CC\ADZ\0C\04\00\00\0B\1E*\05\00\00\00P(\00\0F\00\00C\12\12\09\00|*MD\01:\00\17\14\0DR\00\B4`\00\08\046\1E\11\FF\C4v\D2\DD\CC\E5\99b\8F\FA\BEn\F2\EF\D7\B8fk\86C>w\00\05\A4\80B\17\00\19\86\7F\A0\AB\9C\94Z\1942\8C\8C\A9\83\C2\D4\B6H\07\00\00\00\0C\0F\00\00\00\005P\00\1D&\1E5,&\00\06\04\1D6\0BPP\07\17\11\01!(\96\A2\00\04\00 TTZ\92\A9\A8\B1\80\BD\B3h\00\E1\E3\EA\1D\00\C2\ECoS \9As\C4\00;2\0E\0AF\0B1(\CF\E5\9A43,\00\11QDr/'\96\B4\AF\BB;\00\00\07\17&&R\00\04Oc<\00,y\994\1E\1F\00\00J_\05\15v3\00\0C%7\0F\0A\04\1F\123B\0Bw\A0\CC:\FE\D2g\00\00\01S7b?\E4\A0\C3:~F\D9\0Fb\1A\5C;3\19/\1F^^\82\94s\B5\D1UMD\00\05,\88\98\CF\95\A0\AA\97x\00\06\05\06:O_\00\03oU>\83\04-8G\1C\85b**(\0A\BB\F8\8D\02\05*!v\8BD?3\00<\1BJ\8B\A4Ld\F6q\00\00\003lD>\D5\C3$\AA\F8\8A\84\0D\02xe>g5)\22J8\00Zn\8E\C6Z\00\15-\14\00\15\00\14\10h\9E\A0T\00\00\00\090XrE?f]\0C|\82\1A\13\04\85\86\87p2Y|\81\D4B\07\004ag\D9\92\17x\00\02_)V z&0v\00\00 \10DV\8E\EF\00K\C2\A3\B5V\0CBq;\A50:\18()\17\1E\97Ri\C2\0E\C2q*\1D\1F\0D\087BS\82\AEl\00\00\00\00\18DK8(p\05!\14\89\9D0.\A7\CA\A2\CD\B9\9D\87h\A9+\1D\10NtM^A\0E\1D+\1F\8A\0B'0ob4\05\22\1BH%*F\0C.\AD;\0F\0E\8A\0B8r}x~I\9F\0F\0E\16EHl\108o8\D2\B7n9'\00\00\1D&\22N\9C\A9>\1A\00\00\05\19%(,j\00?H5\9DV5\00\CD\F0\D9\C7\FA\89\88\973\1E\00\180\88*\1A\00\00\00\1A\17C\17\7F\9Bs\14%nA\95V\19#GKK,b\91\11/@\80bTe[\00\1C\022;?:,\0D\1Bd}\8CyR\16\00\00\10\17\17\09?I\18\0D\18,\00\00\10!7\84\E1>\00\1F\0E\15)I\19\C9\A8\92\8A\FD\9D\B6bm{C\00]0\17\AC\90K\07\01<\D2\8C|!\A8\DB\D1\C1G\14.Q<]O\1E-k\B5\22X\06\00gFS\15E+!.J6NwG\004q\A7%^u@\0F\1C@h\0C\0C\00\01!%\01\0A\1E\00\00Mr\A8\00W]\00\07\8A\AA\B1\BE5;F\D1\A3=%MP\08-f\00C\C6\B6\87\00\93\93\A3\99\0C\C5\D8\C3\BAh0,3@V\91i9\11]\15Y\00>D>D\14Q.\0E1\0D.$\1E1B\0AJd\94\C8\87R6Z\99}{2\00\05 \0E\00\00\19\00\00V%l\00\A6\C0\BC\9A\9B\8E\A2\D8if\A6\CE\E4oV\1C$)\1A\5C)\00v\CF\AF\B0\A2V\DC:-\99\85\CA\D7\B5\0F3(,\22Eh@Y%\15-\003\91\C0\E4 \22\12\00\00WYE6\18\00\008\8B\AD\D4\C0y8Z:aX=\00#M*\03\00\1E\00\00\1B\0F\00\00+\9D\C8\F7\E3\83T\B4\FA\FF\A6\EC\8B7\07\18\12\1D\09\1F3\AE\A4\A4\DE\B7\D0\F2-\17\08\1A\9A\A0\8B\00D\06=#1b\0E#\1D\18N\00\00R\FF\C6ep\BA\A7:A\BF\8FM\1A(\13\1C\15H\C5\A4\CC\E4cNZ6+\11\00\05M#\0C\00\0E\00\000r\0D3\00\0B\84\C2\F4\D3\BE\C5\E2\CDr\C7\C2! \0C\11J,$\8F\A9\95\9F\C4x\A5\E7 !\17ie\80u\00A\ACzOn\00\00L \19?\1F\99\E3$\00\09C\9Aa\DFF\C0\94Y\00\22P\1C7Q(\C2\BA\C0T^\86\97ye@K\1B<\0E<!\14\00hUFiO\8EX\D7\C4\90\BE\F6\D9m}|\F3\00%\00\08/67:@u\A5\C8\CB\A2\FA\D43\1B\89QG{&\9Ds\83\A3\85\00`\84l$\A4\BAv\12\06\81\B2\00\C2\A0\97\D8\94\FF\A5\00\1ACf\AE\AD\B4\B9\CCXY\DB\DB\B0O$\0E\10\0C%\0265\00\008\14S\9B\DF\E1\CD\9F\E7N\99\A1\DD\D7zp\9B\003\15\1F?\141(\04%S\86\C8\DE\D0\EE\CE\0C6\CF\C1\B4\EEfT\93=\B2\CA\95\B8=!M##Qs\FFU\9A\B3\DC\E3\F9\DD\FF^\00\0DB\91\C1\C1\D6\EF\CED\0B\BE\CC\C4\C4\98/\00&\1F\00\00\1E\00\008\00\AF{\CA\D9\E9\D5\CE\00\81\FC\BC\DF\DE1\16\00\00\05\00)e/3\00`?{\88\EF\D6\B8\B8R\14\FF\DF\ED\FF\BE\9A\9Ca5\F1\E7\EC\0E>#S\80[Q\EE~/vf\CA\F6\15\7Fl\00c\96\5C]v\9BSC\F1\90\D4\D6\A2\19\10\00\00\16\1E\00\00\08\00\002$vod\EF\FF\A3\91\AF\DD\C1\FB\D2\B0\00\00\04\05\00\0E8V.\16&\A5G\9Cu\A7\B7\A2\07\97\8D\C9\E9X\A6\FF\CA\96\96\F9\BE\E9\E7\00Luj7\9B\F1\BE\94XU\D2G\C4\14\E7\E1=*]JeW\7F'\00\B5\8D\C7\C2\FF;\00\00\006\1F\00\00\000_\1Ca\5Cr\82\BC)\AD\B6\9D\95\CB\CB\D4\14)\05\02\17\16\0D(\00-\07\88\A7\B8_@y\88\A4\C9\CD\B2\ED\B1T\1B\B9\D6\84m\93\BC\B8\F6\8B%5\0A\B1{\C7\E1w\ABSEI\BE\F4\C0\C4Z\19\0F:l\7F,7P\B5\A4\98`\A0\E9$\00\00 \00\00\00\00VSlfAJ .9\B8\C2\D9\A8\C9\91\B0,\1E\06\1A(%\18\13\1D\11\11 >\00%HS{-\9D\B6\BB\B3\CEo\E6\C2\DA\99}\A4f:\E4\F25\00$So\FF\D0=\00\07\00J\A0\B7\E7\A3OMPPpA\00f\00i\D0\22\065\B3^H+\16\03\0C\1B\09B;\1B\22%]`2\17(\BA\C2CV\E2\9Dt,!\0D\00\12\00\06\0B\00\1B\03\00 )\0E\04\00Ke\B9\A2\A6\A1\FF\D7\8A\86vc\226:P\FF\96\0A>D\00\E4\009/\0D 'o\85\CE&@El\89/\00+\00\0E\1ES\05\02\16]\BE\0F\12\09\0F\00\00\00;70\1B\0CTs\12\0F\00\0F\A6)V6\D1n0\00\03\09\11\00\00\14\00\1F\09\0F)\19\08\190\00\00\FA\E3\C3\EC\A0\FF\98}O\02\0F\FF\D6)\E6\1E3XE\03\00\0F[%\1CT-\5Ch\AC\008I\95u\00g'\00\1D*\0C\05\10\1D\00M\00\16 \10\00\04\05RiO\00\00\00Zc\1C\0DVmC\15\C6\B1\A2f\00\02\17\05\04\03\0F\12\1E\02\005G\00\14F\14)\E5\D5\FF\DFc\FF\D5\B2t\05\AB\C2\AA(pD1z6/\00\1B1.#27;8B\00+wt\00BR\00\05\18\12\18\00\00\00R\00W\03\08\00\00\00\0B`g\17\0E\05\06\01H\03\0AINa\8C\DA\E0`kS\00\00\04\00\13\13\0E\0E\05\005\00\0B'\0B \0B@\AC],\10s\CB\B3>\13\B9\A2\D1\FF~\DA\8F\86\8C\E0N\003.\1Ajv\1A'\80\00EF\00T(\09 \00\00\00\1F\C4\89\91\11;\00\00\00\00\00\00\00ZR\15\0A\13\0E\08*\14'KOQ\1F[\BF}v\10\0E\00\04\18\0C\00\19\00p\B1b\B0\1F\0BC,\18\00U)\EFB\22\04\8C\93\A6\B5\C3\B7ox`\DC\A8U\92\C5\001\1F\5C\A8@0?!\05#\04\1DU1\00\00\00\05\0C]9\0A\00\0F\00\00\00\00\00\00\00\00PU\00\00\00\13(\1D,\16\19\11[Nc\17Olb\00\06\00\00@\11\13\14\B5\1E\C6\F4\FF\00\1B+\1Bj\10!\D4\FF?#]\E6w\BC\F0\B4\B6\85\C3\D6[H\C1\B7\D4\CE\A5\0BED\1DI4B\00\16\1B(aohi\0F\15\00\11H;5\16\00\00\00\00\00\00\003'\00\00\00\15.\0B\19\1F\12\08\9FEo=\A4l\00\00\02\0C\13O\00\09+\A9\C7e\D4\FF\ED\09\0FgT\0C\16:\B4\13\13\98\84bN\E4\CF\E0\BB\C8\D1\93\10\C2\BB\FF\DF\F1;-+\15%*80+\00\01 \15!nV>9\09\1A\0D\10\00&%\10\00\00\00\00\22#Z\00\00\00\1C\00\00(\00\00mY$\00\00\1F\00\00\00\12L8\00\0A\17\17\F3\EF\BD\9E\E6\E3\A5\E0\BF\04K\AC\10&\8D\12\D2\EC;\DE\CF\B6\D7\D3\A1\BCV\D9\E8\D7\E8\C8t\002\11 Y@*\17\00\00\00\01\016\00\0C\0A(9\10\0075=68\12\0E\10\12\09"], align 1
`define TAG_g_hana_bmp `MEMORY_CONTROLLER_TAG_SIZE'd3
`define TAG_g_hana_bmp_a {`TAG_g_hana_bmp, 23'b0}
// @hana_jpg = internal unnamed_addr constant [5207 x i8] c"\FF\D8\FF\E0\00\10JFIF\00\01\01\00\00\01\00\01\00\00\FF\DB\00C\00\03\02\02\02\02\02\03\02\02\02\03\03\03\03\04\06\04\04\04\04\04\08\06\06\05\06\09\08\0A\0A\09\08\09\09\0A\0C\0F\0C\0A\0B\0E\0B\09\09\0D\11\0D\0E\0F\10\10\11\10\0A\0C\12\13\12\10\13\0F\10\10\10\FF\DB\00C\01\03\03\03\04\03\04\08\04\04\08\10\0B\09\0B\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\FF\C0\00\11\08\00;\00Z\03\01\22\00\02\11\01\03\11\01\FF\C4\00\1F\00\00\01\05\01\01\01\01\01\01\00\00\00\00\00\00\00\00\01\02\03\04\05\06\07\08\09\0A\0B\FF\C4\00\B5\10\00\02\01\03\03\02\04\03\05\05\04\04\00\00\01}\01\02\03\00\04\11\05\12!1A\06\13Qa\07\22q\142\81\91\A1\08#B\B1\C1\15R\D1\F0$3br\82\09\0A\16\17\18\19\1A%&'()*456789:CDEFGHIJSTUVWXYZcdefghijstuvwxyz\83\84\85\86\87\88\89\8A\92\93\94\95\96\97\98\99\9A\A2\A3\A4\A5\A6\A7\A8\A9\AA\B2\B3\B4\B5\B6\B7\B8\B9\BA\C2\C3\C4\C5\C6\C7\C8\C9\CA\D2\D3\D4\D5\D6\D7\D8\D9\DA\E1\E2\E3\E4\E5\E6\E7\E8\E9\EA\F1\F2\F3\F4\F5\F6\F7\F8\F9\FA\FF\C4\00\1F\01\00\03\01\01\01\01\01\01\01\01\01\00\00\00\00\00\00\01\02\03\04\05\06\07\08\09\0A\0B\FF\C4\00\B5\11\00\02\01\02\04\04\03\04\07\05\04\04\00\01\02w\00\01\02\03\11\04\05!1\06\12AQ\07aq\13\222\81\08\14B\91\A1\B1\C1\09#3R\F0\15br\D1\0A\16$4\E1%\F1\17\18\19\1A&'()*56789:CDEFGHIJSTUVWXYZcdefghijstuvwxyz\82\83\84\85\86\87\88\89\8A\92\93\94\95\96\97\98\99\9A\A2\A3\A4\A5\A6\A7\A8\A9\AA\B2\B3\B4\B5\B6\B7\B8\B9\BA\C2\C3\C4\C5\C6\C7\C8\C9\CA\D2\D3\D4\D5\D6\D7\D8\D9\DA\E2\E3\E4\E5\E6\E7\E8\E9\EA\F2\F3\F4\F5\F6\F7\F8\F9\FA\FF\DA\00\0C\03\01\00\02\11\03\11\00?\00\F5\AF\00Z\EA\17\B3\AF\8A<O1\F1\A4z\9B\CF\A9\E9\BE\22\B0g\16zlV\F1*[\DA\AC\0CI,\C7\CC&@\19d,x\E3\0B\C0\E8\BA7\ED;\A3M\E3M;[\F1\7F\855M\06\D2\D6\E2\F6;\B8D\F0\DDXKr\04\883\90V(\90<\98,U\BEQ\EC\BF*x3\F6\8B\F1\0F\C2_\88m\A4E\AC\EAg\C2\D1\DE,q\DA\C3u\98#\B6\91\8C\8C!\8D\B7\04C\BF \00\02p:W\B0\F8\17\F6\C6\F0\C0\F1a\F1G\88\FC1,\1A\BF\8E\AE#\B6\BA\D5\12\FF\00\CB\B6\D2t\F5\8E;h\A4r\DC\C8\04\B0\B3HY@\0A\C4\8E\A5\1F\B7\0D\8E\A5\CF\19)k6\9B\BE\9A5\B7\9E\BD\FE\F3\17$\D2\E8}\0B\A9j\16\1E5\F8\18&\F1N\81\A4x\96MF\DA;\E9-t\EBi\EF\EDu\0ByD[\AF\E3\8Au\8EH\90\0D\D3\18\93,\81AR\E1\81?(\F8\93\F6a\F0\AB\93\A6\E8\CF\ACK\7Fs1k;\AB\0By/t\BB\A8\E5]\E9\11\5C\97\B7u\1F.r\C1\80\1DI\C0\FA\AB\C5\9E\0A\BA\D7\BE\C9\1B\F8\AA\D6\EEAcu5\BE\95gk\1D\C5\94\93\88\D53\05\C7\DD\B7<C\22\92\E1\882/(^\BC'\E1\87\C5O\8C\B0|G\82\D3\C4cV\9FE\B4i-f\D2\ACm\12[\95s\84\86m\EB\F2\ACFV`\1D\9F\0EU\8F@q\EA\CA\18Z\8B\92\B2Ml\B4\F4\D2\FD\1D\FF\00\22\BC\D9\F3O\C2\CDC\C7\1F\03\BE%\E9^+\83E}(C\A8\BF\87\EFn\AE\AD\9F\EC\F1\C9$\8A\B2\C5\B9\86\03\AA\ECoP;W\D6\1F\B5d+`\9AE\97\88\FC\09\A0\9B]P\C5\A8\B6\A5\16\9E\0C\DFhRCB\D2\E0a\F2\01 \9EGn\E3c\E1o\C3/\09|E\B6\F1/\8A|u>\BFn\D6~6\D7\E6\B8\85T\BA1i\96#\94\19\8D\DC(d%y\04\B1\07\1C\8E\B7\C3\FE(]Am>\0A|J\B5\D4\B5\D3\A9\D9\DF\ED\D4.\ED\A11j\91\C5\B5D\DEd` fY\10\02\83vv\93\8E\B5\E7R\C0\CA\AE\0EXjS\B7:\DE\D7\B5\FA|\CC\B5\94O\84<I\06\B3\ACG}\AB\5C\DA\AC\96\9206\A8\17\E4\B7\80\1C\02=s\EC;\F1\C5i|!\F8\07\E2\AF\8E\1A\F3\BE\9D\AC\DB\DA\C3\A4_Z\A6\A1n\087\11\D9I\9F\DFD\87\87;\94\A6\DE\C4\E7\9C`\FD\11\F1\13\E0\9F\82</\E1\F7\F0W\87m\AE\13Y\F0\ED\BCz\C5\AD\C5\C9\95\EE\1BO\09\FB\D5\B8\91\9B\CB~Y\86\11r\18\02\00\C1\AF\09\F8}\E1o\88V\9E;\8F\E2\0F\C2-@K<\12\AD\AC\D0)>K\DC\05\12$\05A\07k\0EA\CF^\87\9C\0F\03\0F\95\D5\C1b\A1N\B2RMtv\FC\EC\F4\EA\EC4\EF-t\B1\CE\FCm\F8\0B\F1\13\E1\7F\89\B5K{\AB5\B9\D2\22\BC[}>\EAX\D6)o\22\C2\95m\99\E0\E0\95=\06S#\AE+\99\F1w\81g\9B[\82\E6\C3M\91U\EC\95\B7\05\C0F\F9\BA\FE\95\EC?\17>>\F8\EB\E2\B7\8Auo\02\F8\DBQ\B7\D1om\8A\DB\C3k\0C*\B1\F9\E8\A0\EDgpd\CE}\FF\00\A8\A6|.\B6\F1\CE\B1\E1{\CB\1F\16\E8\B33\08d\FB-\D2[\B3)t\18 \B0\18\EF\EB^fsVP\C5?\AB\A7\EE\E8\D3\F3\FC\D7\99\A2i\E8\D9\F3v\9Bm\A8h\B7\D1\DDj\9AD\B3$3n\90\94;[\19\F5\EA+\AA\7F\11\F8vWi\17E\DA\1C\96\03j\F0\0F\E3Qj\BA7\8C[u\F5\D5\B5\CB\DA),\E2<\10\07Q\909\EE?\ADr\0F\1D\E1v)m1RN8#\8A\BAx\87k\E8_;\A7\A2G\AF\FC$\F8u\17\8En\AFo\F5\DD[K\83O\B3\B8\D2\AC^9\E4Xo$\8A\E2\EE\18D\D6\CA\E3\1B\11X\A3\15c\B0\B4}\B1\9FL\F8\A1\FB?M\F0\EF\C1V\97\FA\C6\89\F6\BD\13S\B3?\D8\BA\EA\98\18:\CD\03M\F6y\C0a\221\C6\E5#1\B9s\80K(\AE+\E1\BF\C4\8D[\E0g\ED\10\FE\13\F0\D6\A6\97^\16\83V\1Ar?\88\A5\FB'\D9,\AE\1E0\F2y\B20[`\AA\CC\CC\DC#\A2|\C3\A1\1FP|F\F1\EE\81\E3Mc\E2.\91\E1\BDoC\D4\FC\05\A0\F8j56\F1_\DB\CDay\AF\DD\C3!\86KI\1C\C8\B1\A5\BC,\F3J\B1\15_\B50\0F\B5\D0M_K\83\8E\1ExX\CA\1A\BB>\8B\AAo\CE\EB_\91\CE\E1k\A7\B8\BF\095_\88^)\B0\F0\96\A1\F1\93Z}WL\F1N\995\C8\B1\93X[x\E3\D3\E1\B6\1E]\E1Y\08Y\1C\80\B1\BA\E1T,\8D\B9\C3\90k\85\F1?\83\FC-\E1O\07\FC]\D5\FE\19\FCn\BB\D4|)\A4[\A3\C9\A5A\A5\BD\F4\F1\86\8D\02\B4\170L\825\F3\83\C4fua\09\8C\97iO\CD^%\E0\FF\00\DA\03\E2\87\84\ED\CC\9An\AF\0CI\E1\BD\1E\FF\00\C3\16\8B=\A2\C8#\B5\BC\1B\C6\C0\C5p\C2eP\C5\9B\05B\8CeJ\BF\D8\BF\00a\F8j\9E\11\F0\D6\9D\E2M\1F\C3\1An\B3\A6\DAG\A4\A0\B3\D7\AD\22\96{P\88\D0\A4r\CF,r,\B2\0F \14$o\957+H\85V-\B0S\86c\15\DA\1B\B6\9D\F5[][\C9\EF\AA\DCw\BA\B9\F3\AF\EC\CD\F1sT\D3<K\E2\AF\0C\CD\E1\0D\0A\FEC\E1\8DOS\B6\D6g\D2\FC\EB\BB\1B\B7\B21\ED\92l\11$w\12\98\D5\84\D8\05\C0\C3\1C\98d\F5\EF\8B\1F\17\BC-\A5x\A7\C0\9E,\BC\D2u?\0DxN\E8\8D[I\F1n\9Fl\D2KglaI\A1\D3\84 \B4N\A1'A6\E4\95\C8VU\89>\FAu\DF\13~\1Bh_\0B~\1D\CD\AB|\1A\9FH\16\F0\DE\DD\E8\FE'h\A4\82\E2}R\01 .\CF\1C_\BB\17Q\F9\9B7H\81\A3B\A2?/\E4e\E1\AC\BE x\93J\FD\9D\FC!\E1\7F\08xr\E2\0DN\E6K\9B\09u\B9F\FB;k\BBY\96\D7\CE]\E1\97sG\22\C2a\0A\A5\9F-\B7j\C8\E1a\E7W\0D(Q\A5S\9B\DD\BE\9EM-\15\FEW\D0\13\E5\F7d\B5G\B4\BF\8A\BE\1C|a\F0\A6\A6\DAn\A3\E1?\17\E2\C2V\D2\EDm#\B8\D2\B5\18o\17\CE\8E\7F1&gh\C4\CCG\96\EE\9BJ\C8\BB\81\18\91\BEx\F8Q\1E\B1\F03\C4\F1\F8\A2?\0E\1F\15\E8\9E<\10\BE\92\D1\C5-\B4k\229`\E8\85I\F9\06\EC\B9\00aA\CA\F7\E0\BCY\E3}O\C4>\1F\F0P\F8h\B6\B6z\A4\FAy\B7\D45Km>\0B\09,.-\94[\0BQ,gv\C5\8D\0Ch2Y\91W\92\0E\17\D9\FE\16\FC\5C\D4\FE%i>\09\F0?\C6\AF\14Xi\16\BA\AD\DD\ED\C4\17-\1A\C1>\BB$\8D$\96\CA\E5\00UY\DAH\F0\AA#YT\C2\18\16h\98c\88\CCiT\94SO\9A\FA?7m5\EC\9B\BA{|\8B\94Z\D5\1E[\F1\BF\C0\E3\C6?\1Dc\F1W\8C\FC=\ABj\1E\10\B5E\B8\9BJ\D3\9A+{\D8\92M\A2I\96h\F1\E6\95%\18\82A#\1E\A0\1F\A3\93[\D0?g=6\D2\185\1Dt\F8V\DDc\B7\BBcz\935\BD\C3\8D\F0\0C\9C\B6F\C6\DC1\B4\EF\03<\F1\F2\8F\C5}\7F\C6\BF\0E<c\AFx k\8E\9A\CC\16\E8/\05\CCj\EFw\1C\CB\E6\B8\CA\91\1A`0\04.9\C0\18\0A\B4\DB\9D\1F\C5\91\FC\1A\B7\D7\AE~\D6\BA\1F\89m\A32\DD\5C\93<l\D1\B9u\D8\D9&&\0C\A4\15\EB\80x\CA\A8<\F5\F3\08\C2SS\83rW\BF[.\97k\A6\DA\8D-9\91\8B\FBE\EB\7F\08d\D6f\F1\0F\C1\8DFE\8FW\BB72Z\012Gj\C7\E6\90\04\93;T\B9a\B0p\0E\ECq\8A\E2\AD\F5M-\E0\8D\E7K3+ .A\1F{\1C\FE\B5\CD\D8\E8v\FA\CC\1A\84\CF+F\22\965\0EO\0A\A5\B0\C4\8F\A63]:\F8#\C1\B1\01\19\F1\CD\BEPm\E0\8Cq_5\88\9D\1CD\DC\9A\E5\F2_\D3\1Cj$\BD\E4hx\8BD\F0\EC\DA\FE\BD\AF\DB\C7}v\FA\143\D9j6\80,r\C1; \84]\C6\1CbH\C5\C3\10\F1\FC\AD\1C\8F\B86\D9\03/\A7\FF\00\C33\FCg\F0\B7\84-\B4\81\AFF<\0B\AF\DB\DBk\17\D70D\B761}\A6(Q\AE\15#o2\E3t-\1Cp\BE\E8\C7\EFH\DC\8C\ECOU\F0\9B\C0^$\F8\EF\E3s\E2?\8A\DE\0F\D2\BCg\E1\D1\A7Z\E9W\DA\9F\9Fqc\A9\D8\8Bv\91b\B9\83\0Cf\95\D1\DAHK0\C9\8A\DD\17\92\BE[}W\A9\DD|=\D0t%\F1&\9Fq\AC}\8F\E1\D6\B5\A9Y\BD\B6\96\A2\CE\0Bx\84\9B/\8D\EA\A1+9B\AF\BB\04\0C\DC\B1\95v;\13\F4X\5C\05\E3*\94\FD\E8\B7\A5\9D\B4OU\D9\AD\F6\ECe\0Fy\DD\BB\1F\9D\BA\97\86\F4\AF\0F\FCo\D6\FC1m\E2KX\B4m3V.\D7\9A\B5\A1x\A6\8E9\BE\D1\E6\CBn\84\99#\DF\13n\0A\C3\F7{\B3\91\95<\FF\00\85\BCY\E1/\05x\F6\DF\C5.\FAu\C5\AD\B6\A3\1E\A7x4\DD\AB\05\B4\B0\DC\BB\C5\1D\BC2\A3\06\0A\C69U$\12!\87pq\94ll|r\F8\BBs\E3/\8A\1A\CC\B6\B7\16\17\F6\10\EA\DA\8C\B6\8Dnd\B8\B7\9DRi\13z\97fa\14\D1nc\FC;]I\1DZ\BE\BF\F8\11c\F0[\E2\AF\82\FC\03\A7^[j:\B7\88\FC*~\CBk\ACjJ\B6\BA\B5\94+\14\A0\B43\08\1A)\92\22\1B\CAG2\15\F2\B2K\BCjB\C0a\AF^q\A3-\22\EE\BE\FB=/}?\22i\DF\E18?\89\DF\B5\E7\88\AD|\14\9F\0F\BC\15\E0\AF\B0x\A3]\BF\9A\F7Q\83T\B33,\FAu\D8\DDmv\AD\03\A4\91\5C#\14\81\D6BWq&0\CAvG\B3\F0\83\F6\BE\D1\87\81c\B4\F1v\AB\A7\F8~\EBF6\16\B3XY\E9A\AD\F5%x\A5\8E\E2\F3P\88!\CC\B1Lb\90\C7\A7\B47\13\CA\E4\BAl;\E0\D1\F8E\1F\C6\FB\F7\F8\EB\F0\DA\F7\E1\F7\855\9F\12\DCj\0F4\96v,[M\92{\BD8%\893\19U\E4\B6\95 (\9F0e\F2\E52\FE\F0\92\BE5\E1\BF\D9\E7\C5\B7\82o\05\E8\B0iz\D6\A5v\91I\7Fk\7Ff\22kK=\CC\B2^\88\E4\1Ed\8B\1C\8A\B1\AE\C0\AD\BEdwX\95\B1]\15\E1\8B\A7(\FDV\F2[[kk\FDm\F9\1A7\AD\CB\BE?\93\C2^ \9F\5C\F0-\B6\B1u\AEi\B7\9Fek\8F\14\DD\DB\C9\0D\D2\DE\86P\B0\A5\B9(c\91mb\86\09\8B\87\91v\CF\08'1\AC\1E{\A1\F8\FF\00O\D0\BE%Z]x\F3P\BB\F1F\A4\B3Ci,\AA\D0%\8Ai\EC\88\B2C$1)\8Cl\8DB\18\D0++\AB.U\94\14\E8\BE\12\E9\16\13\F8\8B\C3\BA\A6\BD}w\F1\17[\D6$m\17J\D1,\EE%\B4\B7\96\F2e\8E\D2\07\B8\D5.\15E\ACB\08`+\B0K#\83\82\109a\EB\7F\0F\BFf\0F\01k\DAF\9F\E3\0Dg\C7\11\F8v\DAk\FB\AB}b\DE=z\D9\ACmZ{\B9\A0\B7\F2\DEEK\88\97\CFkr\AB1\DE\EB!G\D9*\18_\9AXj\D9\8E!\D4\82IG\A3v\DD\F5z\E9\F7\BB\5Cm\CDI4p\9F\B4L\D6\DF\1A4K\7F\1D\F8\1Et\D5-4=:\DBQ\BB\8AV\8A\19\ED\1Eg\9A'\B5D\00O*,P\A4\8E\8F&\E8\FC\E8\88/\92\AA\9F\06\FF\00i\EF\86\F3\E9\93\FC!\F8\89\E1\8BX\BC?\AC\A2[L\EDq\04V\B0\CAT\01(\8A\0Bx\8Ce\9D\E4b\E6F#\E5\0B\B7\15\85\F0W\C0z\CD\FF\00\C4\AB\9DM\F5K[\BD\17N\BC\D44\D5\8FV\BD{\08\B5;t\9C\C2TO\83$\8C@$\AB#,`\B0(w\15\AF\A0\FE*|\19\F06\A1\E2O\16x\97\C2\16\DAe\96\8F\A5h\10jW\1A\B4\D6\90\B6\9Fr&3\AB\B5\AC\FB\85\BF\96\BES,\9F\BD\01\1D\19I\DB\90j\8F\B6\C5M\D4\83I\FC-=S\B7Eu\B7M\CB\A74\9D\E4\AE|i\A2\D9h>\1F\F1\C6\A3\E1\9DKN\B9\BC\F0\A4\B7\93\C0\93\99\95\84\A03\18\D0H\BC6U}\89\EB\C5t\D2\F8\AB\C1\91J\F1\DA|9\F0B\C0\8CV%\97Q\888@x\0C3\D7\18\CDrwShv\DAe\AD\87\87\B5\18o\D2=jb\F7\A2\DDbF\90\A32\C4\02I\222\8C*\EFV \EF?\DD9\E6W\E0\ACZ\8A\8DA$\D5Qn\87\9C\15lr\00np\0Ey\1C\D7\CB\D5\A3\05^q\C4>F\9FGu\BF\935\E5\E4v\86\D6Ok\EEwZ\7F\EDC\E2\CF\0E\FD\A2\FB\C2z\80\D3u;9\A3\B3[x\96H\A1\D44\FF\00:96\F9\8A\DEnL\B0\A7\98\85\D7zH\FB\B7|\CB_[x\EB\E2\B6\BB\FBA\FC9\F1\F7\86$6>\1E\D3\A7\D2\B4\F5\86;m\5C\BD\E24\862\C8b$3\C4\B3G*\17\09\1Al\94\A9F\12\B9\87\F3W\C5\96\D0\E9\1E(\D5\EC\F4\E0\F1Ei\AB\5C\C1\0F\CE\CC\CA\91\CA\E1\06\E2I8\00rNx\AFG\F1W\8E<K\A3|(\F8i\E2\CD>\F6\14\D5\A7]G}\D3\D9\C3#\16\8E\F2\E1Q\F0\E8@u\120\0E\06\E1\C6\0F\CA\B8\FA\DC\1C\1E\1E\94\A9\D3\D9kn\8F\A3[7gs\99F\D7G\0E\F7\EF\A7\B2\88l\A0\86\E2\13\22;\A4\8CX\1F\99J\19\14\ED`F\FF\00\BB\F2\B2\B7\19\19\07\DC\B4\9F\8A_\19\FC#\E1\8F\0Cj\B3i\D7v\9A5\95\C4phS\CB\A0\BC\16\F2\DB\B2\CF\89\8C\B1*4\DB\D5\AEB\E6BY\BC\D2\8A[\CCj\F1\ED*\CA\DBV\F07\89|A\A9\C6n\B5/\ED\0B47R\B1i\08\9AW2\FC\C4\E7,FI\EB\C9\F55\FA\F1\FB.x3\C2\9F\13\7Fd\AF\87:'\8E\F4\0B=_O\F8\85\15\FE\99\E2;ic\0B\1D\F46R\5C\C3h\DBS\02)\A2\8E\DE\DDRx\F6\CA<\88\8E\FC\C6\A4pP\9DE7\1AN\DD\1F\E0\D7\AE\B6*\14\D4\93g\8B|3\F8\BB\F0?\C4\BF\B3\DE\8D\1F\8F<O\06\90\DA\95\EE\FF\00\14\E9\BAN\9Ds\15\C6\9B\22j)\9B\D9\EEm\22O.<\CB\04\D2\CB\88\F7<\FBQ\BC\C2\AE\9BZ\BF\8D>5k>?\F1>\B7\F0\E7\C4Z4zM\96\9Bm\E2\1B\0DRG{\8D?\C4\17\82&h\AD\C4\F7\12\C7o\1C/\14R,\D7^c\15\F3\90\0Cob<\07\F6\8F\F0\AE\8D\F0C^\F1\85\9F\C2\A8\EE\FC;\0D\B7\C2\FD*(\D6\DA\FAv\F95\0DS\EC\97\AA\DB\DD\B7\89afR\1B8c\BCa\C0j\FAO\E05\85\BE\8D\E0-%4\FF\005!\B7\D3|oa\15\BC\93<\B0,\1An\BFg\05\92\F9NJf8\DEA\BB\1B\98\BB\B3\96f$\FB8:\8E\A5G*\9B\AB'n\BA\FF\00\C1\B9J-\FB\B7\D8\F9\CBE\D6\FE#|$\F1\B7\8B~(|=\F8qi7\87d\B0\D5\AF\F4m*\EBQ\8AX\F4\DD\08$\91\A3\C3\E5\B1w\8E\19dYf\B6\8F'm\BBE!\1EZ\C8\BC\B7\EC\E7\F1\C3\C4\B6\9E9O\16\FCK\8EMkE\D5dkKa-\9D\B4p\C7*\5C[L\D3\C4\1B\08\B2\A9\B5\85\9As\CA<0\B1\93x\DD_\A1\BA\BF\86\B4+O\8CV\DA\AD\BE\9B\12\5C\E9\DE\0D\D4-m\9B\92\AB\14wZd\88\85O\CA\C1]\98\8D\C0\E3s\0E\84\8A\F8\03\FE\0A\0Fikc\FBTj\90X\C0\96\C9\A8Yi3\5C\88F\CF2G\0F\0B\B1\C7s\1C1\A9=N\DFRI\BCm9e\EB\DA\D2w\8A\96\CF\D3\CA\DD\CC\B9\A4\9D\AEV\F1/\C4-/[\F0\DD\F7\89\A5\BC6\DE\22\D5$}CR\98\EE\9E\DFMiT\ECX\D5\DBj\DDJ\C0\05n\91\A8\DF!\DD\B1Y>\1D|~\F8\A1\A3\F8\07\C3~\1F\F0\D4^\1A\B7\F0\7F\84o\AE\BE\DD\1D\FC\B6\B6\F6\BA\A4W\1B\D9\AC$\86w\DFu\0E\C9n\01\11$\B27\DA0\E1\D9\93w\85\F8\8FR\D44-Z\DA\1D\1E\FA\E2\CE8\D4\00\B0\C8Ts\C9'\D4\9C\9C\93\C9\EFW\EE/&\D7t=kR\D4\84oua0H%\8E%\84\80f*wl\03\7F\03\F8\B3\DC\F5&\BER8\BA\91\93\C4\C5\D9\CF{i\BE\BF\99\973VH\B5\E2\1B\9F\09=\ED\CD\8F\86t\D3\A5\E8\E6\F1\EE\ED\AC-\E73-\B9n\06\E7 \09%U\C2\B1\8Cye\95\CAnR\09\F5\1B\1F\DA?\C4\96VV\F6v\FF\00\0D\B4\C6\8A\08\92$;\E3\5C\AA\80\07\1B\B8\E0t\AE7\E2/\86t\1D\1FA\B4\9BL\D3\22\B7p\96\E8Y3\96\049\CBs\F3\1C\A8\E4\E4\F5\E7\93^\CD\E1\8F\02xZ\F3\C3zM\DD\CE\9A\EF4\F60I#}\A6Q\B9\9A5$\E06:\9A\F01R\85G\CD5}^\F7\FD\19\DDJ\B5X\D4\92R?\FF\D9", align 1
`define TAG_g_hana_jpg `MEMORY_CONTROLLER_TAG_SIZE'd2
`define TAG_g_hana_jpg_a {`TAG_g_hana_jpg, 23'b0}
// @izigzag_index = internal unnamed_addr constant [64 x i32] [i32 0, i32 1, i32 8, i32 16, i32 9, i32 2, i32 3, i32 10, i32 17, i32 24, i32 32, i32 25, i32 18, i32 11, i32 4, i32 5, i32 12, i32 19, i32 26, i32 33, i32 40, i32 48, i32 41, i32 34, i32 27, i32 20, i32 13, i32 6, i32 7, i32 14, i32 21, i32 28, i32 35, i32 42, i32 49, i32 56, i32 57, i32 50, i32 43, i32 36, i32 29, i32 22, i32 15, i32 23, i32 30, i32 37, i32 44, i32 51, i32 58, i32 59, i32 52, i32 45, i32 38, i32 31, i32 39, i32 46, i32 53, i32 60, i32 61, i32 54, i32 47, i32 55, i32 62, i32 63], align 4
`define TAG_g_izigzag_index `MEMORY_CONTROLLER_TAG_SIZE'd15
`define TAG_g_izigzag_index_a {`TAG_g_izigzag_index, 23'b0}
// @lmask = internal unnamed_addr constant [32 x i32] [i32 1, i32 3, i32 7, i32 15, i32 31, i32 63, i32 127, i32 255, i32 511, i32 1023, i32 2047, i32 4095, i32 8191, i32 16383, i32 32767, i32 65535, i32 131071, i32 262143, i32 524287, i32 1048575, i32 2097151, i32 4194303, i32 8388607, i32 16777215, i32 33554431, i32 67108863, i32 134217727, i32 268435455, i32 536870911, i32 1073741823, i32 2147483647, i32 -1], align 4
`define TAG_g_lmask `MEMORY_CONTROLLER_TAG_SIZE'd37
`define TAG_g_lmask_a {`TAG_g_lmask, 23'b0}
// @main_result = internal unnamed_addr global i32 0, align 4
`define TAG_g_main_result `MEMORY_CONTROLLER_TAG_SIZE'd16
`define TAG_g_main_result_a {`TAG_g_main_result, 23'b0}
// @out_ac_tbl_no_get_sos = internal unnamed_addr constant [3 x i32] [i32 0, i32 1, i32 1], align 4
`define TAG_g_out_ac_tbl_no_get_sos `MEMORY_CONTROLLER_TAG_SIZE'd8
`define TAG_g_out_ac_tbl_no_get_sos_a {`TAG_g_out_ac_tbl_no_get_sos, 23'b0}
// @out_comp_id_get_sos = internal unnamed_addr constant [3 x i32] [i32 1, i32 2, i32 3], align 4
`define TAG_g_out_comp_id_get_sos `MEMORY_CONTROLLER_TAG_SIZE'd7
`define TAG_g_out_comp_id_get_sos_a {`TAG_g_out_comp_id_get_sos, 23'b0}
// @out_count_get_dht = internal unnamed_addr constant [4 x i32] [i32 12, i32 162, i32 12, i32 162], align 4
`define TAG_g_out_count_get_dht `MEMORY_CONTROLLER_TAG_SIZE'd11
`define TAG_g_out_count_get_dht_a {`TAG_g_out_count_get_dht, 23'b0}
// @out_index_get_dht = internal unnamed_addr constant [4 x i32] [i32 0, i32 16, i32 1, i32 17], align 4
`define TAG_g_out_index_get_dht `MEMORY_CONTROLLER_TAG_SIZE'd10
`define TAG_g_out_index_get_dht_a {`TAG_g_out_index_get_dht, 23'b0}
// @out_index_get_sof = internal unnamed_addr constant [3 x i32] [i32 0, i32 1, i32 2], align 4
`define TAG_g_out_index_get_sof `MEMORY_CONTROLLER_TAG_SIZE'd5
`define TAG_g_out_index_get_sof_a {`TAG_g_out_index_get_sof, 23'b0}
// @out_length_get_dht = internal unnamed_addr constant [4 x i32] [i32 29, i32 179, i32 29, i32 179], align 4
`define TAG_g_out_length_get_dht `MEMORY_CONTROLLER_TAG_SIZE'd9
`define TAG_g_out_length_get_dht_a {`TAG_g_out_length_get_dht, 23'b0}
// @out_length_get_dqt = internal unnamed_addr constant [2 x i32] [i32 65, i32 65], align 4
`define TAG_g_out_length_get_dqt `MEMORY_CONTROLLER_TAG_SIZE'd12
`define TAG_g_out_length_get_dqt_a {`TAG_g_out_length_get_dqt, 23'b0}
// @out_num_get_dht = internal unnamed_addr constant [2 x i32] [i32 0, i32 1], align 4
`define TAG_g_out_num_get_dht `MEMORY_CONTROLLER_TAG_SIZE'd14
`define TAG_g_out_num_get_dht_a {`TAG_g_out_num_get_dht, 23'b0}
// @out_prec_get_dht = internal unnamed_addr constant [2 x i32] zeroinitializer, align 4
`define TAG_g_out_prec_get_dht `MEMORY_CONTROLLER_TAG_SIZE'd13
`define TAG_g_out_prec_get_dht_a {`TAG_g_out_prec_get_dht, 23'b0}
// @out_unread_marker = internal unnamed_addr constant [10 x i32] [i32 216, i32 224, i32 219, i32 219, i32 192, i32 196, i32 196, i32 196, i32 196, i32 218], align 4
`define TAG_g_out_unread_marker `MEMORY_CONTROLLER_TAG_SIZE'd4
`define TAG_g_out_unread_marker_a {`TAG_g_out_unread_marker, 23'b0}
// @out_v_samp_factor_get_sof = internal unnamed_addr constant [3 x i32] [i32 2, i32 1, i32 1], align 4
`define TAG_g_out_v_samp_factor_get_sof `MEMORY_CONTROLLER_TAG_SIZE'd6
`define TAG_g_out_v_samp_factor_get_sof_a {`TAG_g_out_v_samp_factor_get_sof, 23'b0}
// @p_jinfo_MCUWidth = internal unnamed_addr global i32 0, align 4
`define TAG_g_p_jinfo_MCUWidth `MEMORY_CONTROLLER_TAG_SIZE'd32
`define TAG_g_p_jinfo_MCUWidth_a {`TAG_g_p_jinfo_MCUWidth, 23'b0}
// @p_jinfo_ac_dhuff_tbl_maxcode = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_dhuff_tbl_maxcode `MEMORY_CONTROLLER_TAG_SIZE'd46
`define TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a {`TAG_g_p_jinfo_ac_dhuff_tbl_maxcode, 23'b0}
// @p_jinfo_ac_dhuff_tbl_mincode = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_dhuff_tbl_mincode `MEMORY_CONTROLLER_TAG_SIZE'd47
`define TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a {`TAG_g_p_jinfo_ac_dhuff_tbl_mincode, 23'b0}
// @p_jinfo_ac_dhuff_tbl_ml = internal unnamed_addr global [2 x i32] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_dhuff_tbl_ml `MEMORY_CONTROLLER_TAG_SIZE'd45
`define TAG_g_p_jinfo_ac_dhuff_tbl_ml_a {`TAG_g_p_jinfo_ac_dhuff_tbl_ml, 23'b0}
// @p_jinfo_ac_dhuff_tbl_valptr = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_dhuff_tbl_valptr `MEMORY_CONTROLLER_TAG_SIZE'd48
`define TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a {`TAG_g_p_jinfo_ac_dhuff_tbl_valptr, 23'b0}
// @p_jinfo_ac_xhuff_tbl_bits = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_xhuff_tbl_bits `MEMORY_CONTROLLER_TAG_SIZE'd26
`define TAG_g_p_jinfo_ac_xhuff_tbl_bits_a {`TAG_g_p_jinfo_ac_xhuff_tbl_bits, 23'b0}
// @p_jinfo_ac_xhuff_tbl_huffval = internal global [2 x [257 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_ac_xhuff_tbl_huffval `MEMORY_CONTROLLER_TAG_SIZE'd27
`define TAG_g_p_jinfo_ac_xhuff_tbl_huffval_a {`TAG_g_p_jinfo_ac_xhuff_tbl_huffval, 23'b0}
// @p_jinfo_comps_info_ac_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_ac_tbl_no `MEMORY_CONTROLLER_TAG_SIZE'd25
`define TAG_g_p_jinfo_comps_info_ac_tbl_no_a {`TAG_g_p_jinfo_comps_info_ac_tbl_no, 23'b0}
// @p_jinfo_comps_info_dc_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_dc_tbl_no `MEMORY_CONTROLLER_TAG_SIZE'd24
`define TAG_g_p_jinfo_comps_info_dc_tbl_no_a {`TAG_g_p_jinfo_comps_info_dc_tbl_no, 23'b0}
// @p_jinfo_comps_info_h_samp_factor = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_h_samp_factor `MEMORY_CONTROLLER_TAG_SIZE'd21
`define TAG_g_p_jinfo_comps_info_h_samp_factor_a {`TAG_g_p_jinfo_comps_info_h_samp_factor, 23'b0}
// @p_jinfo_comps_info_id = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_id `MEMORY_CONTROLLER_TAG_SIZE'd20
`define TAG_g_p_jinfo_comps_info_id_a {`TAG_g_p_jinfo_comps_info_id, 23'b0}
// @p_jinfo_comps_info_index = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_index `MEMORY_CONTROLLER_TAG_SIZE'd19
`define TAG_g_p_jinfo_comps_info_index_a {`TAG_g_p_jinfo_comps_info_index, 23'b0}
// @p_jinfo_comps_info_quant_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_quant_tbl_no `MEMORY_CONTROLLER_TAG_SIZE'd23
`define TAG_g_p_jinfo_comps_info_quant_tbl_no_a {`TAG_g_p_jinfo_comps_info_quant_tbl_no, 23'b0}
// @p_jinfo_comps_info_v_samp_factor = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
`define TAG_g_p_jinfo_comps_info_v_samp_factor `MEMORY_CONTROLLER_TAG_SIZE'd22
`define TAG_g_p_jinfo_comps_info_v_samp_factor_a {`TAG_g_p_jinfo_comps_info_v_samp_factor, 23'b0}
// @p_jinfo_dc_dhuff_tbl_maxcode = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_dhuff_tbl_maxcode `MEMORY_CONTROLLER_TAG_SIZE'd41
`define TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a {`TAG_g_p_jinfo_dc_dhuff_tbl_maxcode, 23'b0}
// @p_jinfo_dc_dhuff_tbl_mincode = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_dhuff_tbl_mincode `MEMORY_CONTROLLER_TAG_SIZE'd42
`define TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a {`TAG_g_p_jinfo_dc_dhuff_tbl_mincode, 23'b0}
// @p_jinfo_dc_dhuff_tbl_ml = internal unnamed_addr global [2 x i32] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_dhuff_tbl_ml `MEMORY_CONTROLLER_TAG_SIZE'd40
`define TAG_g_p_jinfo_dc_dhuff_tbl_ml_a {`TAG_g_p_jinfo_dc_dhuff_tbl_ml, 23'b0}
// @p_jinfo_dc_dhuff_tbl_valptr = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_dhuff_tbl_valptr `MEMORY_CONTROLLER_TAG_SIZE'd43
`define TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a {`TAG_g_p_jinfo_dc_dhuff_tbl_valptr, 23'b0}
// @p_jinfo_dc_xhuff_tbl_bits = internal global [2 x [36 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_xhuff_tbl_bits `MEMORY_CONTROLLER_TAG_SIZE'd28
`define TAG_g_p_jinfo_dc_xhuff_tbl_bits_a {`TAG_g_p_jinfo_dc_xhuff_tbl_bits, 23'b0}
// @p_jinfo_dc_xhuff_tbl_huffval = internal global [2 x [257 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_dc_xhuff_tbl_huffval `MEMORY_CONTROLLER_TAG_SIZE'd29
`define TAG_g_p_jinfo_dc_xhuff_tbl_huffval_a {`TAG_g_p_jinfo_dc_xhuff_tbl_huffval, 23'b0}
// @p_jinfo_image_height = internal unnamed_addr global i16 0, align 2
`define TAG_g_p_jinfo_image_height `MEMORY_CONTROLLER_TAG_SIZE'd17
`define TAG_g_p_jinfo_image_height_a {`TAG_g_p_jinfo_image_height, 23'b0}
// @p_jinfo_image_width = internal unnamed_addr global i16 0, align 2
`define TAG_g_p_jinfo_image_width `MEMORY_CONTROLLER_TAG_SIZE'd18
`define TAG_g_p_jinfo_image_width_a {`TAG_g_p_jinfo_image_width, 23'b0}
// @p_jinfo_quant_tbl_quantval = internal unnamed_addr global [4 x [64 x i32]] zeroinitializer, align 4
`define TAG_g_p_jinfo_quant_tbl_quantval `MEMORY_CONTROLLER_TAG_SIZE'd30
`define TAG_g_p_jinfo_quant_tbl_quantval_a {`TAG_g_p_jinfo_quant_tbl_quantval, 23'b0}
// @read_position = internal unnamed_addr global i32 -1, align 4
`define TAG_g_read_position `MEMORY_CONTROLLER_TAG_SIZE'd38
`define TAG_g_read_position_a {`TAG_g_read_position, 23'b0}
// @rgb_buf = internal global [4 x [3 x [64 x i32]]] zeroinitializer, align 4
`define TAG_g_rgb_buf `MEMORY_CONTROLLER_TAG_SIZE'd33
`define TAG_g_rgb_buf_a {`TAG_g_rgb_buf, 23'b0}
// @zigzag_index = internal unnamed_addr constant [64 x i32] [i32 0, i32 1, i32 5, i32 6, i32 14, i32 15, i32 27, i32 28, i32 2, i32 4, i32 7, i32 13, i32 16, i32 26, i32 29, i32 42, i32 3, i32 8, i32 12, i32 17, i32 25, i32 30, i32 41, i32 43, i32 9, i32 11, i32 18, i32 24, i32 31, i32 40, i32 44, i32 53, i32 10, i32 19, i32 23, i32 32, i32 39, i32 45, i32 52, i32 54, i32 20, i32 22, i32 33, i32 38, i32 46, i32 51, i32 55, i32 60, i32 21, i32 34, i32 37, i32 47, i32 50, i32 56, i32 59, i32 61, i32 35, i32 36, i32 48, i32 49, i32 57, i32 58, i32 62, i32 63], align 4
`define TAG_g_zigzag_index `MEMORY_CONTROLLER_TAG_SIZE'd31
`define TAG_g_zigzag_index_a {`TAG_g_zigzag_index, 23'b0}
// %huffcode = alloca [257 x i32], align 4
`define TAG_huff_make_dhuff_tb_0_huffcode `MEMORY_CONTROLLER_TAG_SIZE'd54
`define TAG_huff_make_dhuff_tb_0_huffcode_a {`TAG_huff_make_dhuff_tb_0_huffcode, 23'b0}
// %huffsize = alloca [257 x i32], align 4
`define TAG_huff_make_dhuff_tb_0_huffsize `MEMORY_CONTROLLER_TAG_SIZE'd53
`define TAG_huff_make_dhuff_tb_0_huffsize_a {`TAG_huff_make_dhuff_tb_0_huffsize, 23'b0}
// %HuffBuff.i.i = alloca [3 x [64 x i32]], align 4
`define TAG_main_0_HuffBuff_i_i `MEMORY_CONTROLLER_TAG_SIZE'd55
`define TAG_main_0_HuffBuff_i_i_a {`TAG_main_0_HuffBuff_i_i, 23'b0}
// %IDCTBuff.i.i = alloca [6 x [64 x i32]], align 4
`define TAG_main_0_IDCTBuff_i_i `MEMORY_CONTROLLER_TAG_SIZE'd56
`define TAG_main_0_IDCTBuff_i_i_a {`TAG_main_0_IDCTBuff_i_i, 23'b0}
// Turn off warning 'ignoring unsupported system task'
// altera message_off 10175
module top
(
clk,
reset,
start,
finish,
return_val
);
input clk;
input reset;
input start;
output wire finish;
output wire [31:0] return_val;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
wire memory_controller_enable;
wire memory_controller_write_enable;
wire memory_controller_waitrequest;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
wire [1:0] memory_controller_size;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
assign memory_controller_waitrequest = 0;
memory_controller memory_controller_inst (
.clk( clk ),
.memory_controller_address_a( memory_controller_address ),
.memory_controller_address_b( memory_controller_address ),
.memory_controller_enable( memory_controller_enable ),
.memory_controller_write_enable_a( 1'd0 ),
.memory_controller_write_enable_b( memory_controller_write_enable ),
.memory_controller_in_a( memory_controller_in ),
.memory_controller_in_b( memory_controller_in ),
.memory_controller_size_a( memory_controller_size ),
.memory_controller_size_b( memory_controller_size ),
.memory_controller_out_reg_a( ),
.memory_controller_out_reg_b( memory_controller_out )
);
main main_inst(
.clk( clk ),
.reset( reset ),
.start( start ),
.finish( finish ),
.return_val( return_val ),
.memory_controller_address( memory_controller_address ),
.memory_controller_enable( memory_controller_enable ),
.memory_controller_write_enable( memory_controller_write_enable ),
.memory_controller_waitrequest( memory_controller_waitrequest ),
.memory_controller_in( memory_controller_in ),
.memory_controller_size( memory_controller_size ),
.memory_controller_out( memory_controller_out )
);
endmodule
`timescale 1 ns / 1 ns
module memory_controller
(
clk,
memory_controller_address_a,
memory_controller_address_b,
memory_controller_enable,
memory_controller_write_enable_a,
memory_controller_write_enable_b,
memory_controller_in_a,
memory_controller_in_b,
memory_controller_size_a,
memory_controller_size_b,
memory_controller_out_reg_a,
memory_controller_out_reg_b
);
input clk;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_a;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address_b;
input memory_controller_enable;
input memory_controller_write_enable_a;
input memory_controller_write_enable_b;
input [64-1:0] memory_controller_in_a;
input [1:0] memory_controller_size_a;
output reg [64-1:0] memory_controller_out_reg_a;
reg [64-1:0] memory_controller_out_a;
input [64-1:0] memory_controller_in_b;
input [1:0] memory_controller_size_b;
output reg [64-1:0] memory_controller_out_reg_b;
reg [64-1:0] memory_controller_out_b;
reg [12:0] hana_jpg_address_a;
reg hana_jpg_write_enable_a;
reg [7:0] hana_jpg_in_a;
wire [7:0] hana_jpg_out_a;
reg [12:0] hana_jpg_address_b;
reg hana_jpg_write_enable_b;
reg [7:0] hana_jpg_in_b;
wire [7:0] hana_jpg_out_b;
// @hana_jpg = internal unnamed_addr constant [5207 x i8] c"\FF\D8\FF\E0\00\10JFIF\00\01\01\00\00\01\00\01\00\00\FF\DB\00C\00\03\02\02\02\02\02\03\02\02\02\03\03\03\03\04\06\04\04\04\04\04\08\06\06\05\06\09\08\0A\0A\09\08\09\09\0A\0C\0F\0C\0A\0B\0E\0B\09\09\0D\11\0D\0E\0F\10\10\11\10\0A\0C\12\13\12\10\13\0F\10\10\10\FF\DB\00C\01\03\03\03\04\03\04\08\04\04\08\10\0B\09\0B\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\10\FF\C0\00\11\08\00;\00Z\03\01\22\00\02\11\01\03\11\01\FF\C4\00\1F\00\00\01\05\01\01\01\01\01\01\00\00\00\00\00\00\00\00\01\02\03\04\05\06\07\08\09\0A\0B\FF\C4\00\B5\10\00\02\01\03\03\02\04\03\05\05\04\04\00\00\01}\01\02\03\00\04\11\05\12!1A\06\13Qa\07\22q\142\81\91\A1\08#B\B1\C1\15R\D1\F0$3br\82\09\0A\16\17\18\19\1A%&'()*456789:CDEFGHIJSTUVWXYZcdefghijstuvwxyz\83\84\85\86\87\88\89\8A\92\93\94\95\96\97\98\99\9A\A2\A3\A4\A5\A6\A7\A8\A9\AA\B2\B3\B4\B5\B6\B7\B8\B9\BA\C2\C3\C4\C5\C6\C7\C8\C9\CA\D2\D3\D4\D5\D6\D7\D8\D9\DA\E1\E2\E3\E4\E5\E6\E7\E8\E9\EA\F1\F2\F3\F4\F5\F6\F7\F8\F9\FA\FF\C4\00\1F\01\00\03\01\01\01\01\01\01\01\01\01\00\00\00\00\00\00\01\02\03\04\05\06\07\08\09\0A\0B\FF\C4\00\B5\11\00\02\01\02\04\04\03\04\07\05\04\04\00\01\02w\00\01\02\03\11\04\05!1\06\12AQ\07aq\13\222\81\08\14B\91\A1\B1\C1\09#3R\F0\15br\D1\0A\16$4\E1%\F1\17\18\19\1A&'()*56789:CDEFGHIJSTUVWXYZcdefghijstuvwxyz\82\83\84\85\86\87\88\89\8A\92\93\94\95\96\97\98\99\9A\A2\A3\A4\A5\A6\A7\A8\A9\AA\B2\B3\B4\B5\B6\B7\B8\B9\BA\C2\C3\C4\C5\C6\C7\C8\C9\CA\D2\D3\D4\D5\D6\D7\D8\D9\DA\E2\E3\E4\E5\E6\E7\E8\E9\EA\F2\F3\F4\F5\F6\F7\F8\F9\FA\FF\DA\00\0C\03\01\00\02\11\03\11\00?\00\F5\AF\00Z\EA\17\B3\AF\8A<O1\F1\A4z\9B\CF\A9\E9\BE\22\B0g\16zlV\F1*[\DA\AC\0CI,\C7\CC&@\19d,x\E3\0B\C0\E8\BA7\ED;\A3M\E3M;[\F1\7F\855M\06\D2\D6\E2\F6;\B8D\F0\DDXKr\04\883\90V(\90<\98,U\BEQ\EC\BF*x3\F6\8B\F1\0F\C2_\88m\A4E\AC\EAg\C2\D1\DE,q\DA\C3u\98#\B6\91\8C\8C!\8D\B7\04C\BF \00\02p:W\B0\F8\17\F6\C6\F0\C0\F1a\F1G\88\FC1,\1A\BF\8E\AE#\B6\BA\D5\12\FF\00\CB\B6\D2t\F5\8E;h\A4r\DC\C8\04\B0\B3HY@\0A\C4\8E\A5\1F\B7\0D\8E\A5\CF\19)k6\9B\BE\9A5\B7\9E\BD\FE\F3\17$\D2\E8}\0B\A9j\16\1E5\F8\18&\F1N\81\A4x\96MF\DA;\E9-t\EBi\EF\EDu\0ByD[\AF\E3\8Au\8EH\90\0D\D3\18\93,\81AR\E1\81?(\F8\93\F6a\F0\AB\93\A6\E8\CF\ACK\7Fs1k;\AB\0By/t\BB\A8\E5]\E9\11\5C\97\B7u\1F.r\C1\80\1DI\C0\FA\AB\C5\9E\0A\BA\D7\BE\C9\1B\F8\AA\D6\EEAcu5\BE\95gk\1D\C5\94\93\88\D53\05\C7\DD\B7<C\22\92\E1\882/(^\BC'\E1\87\C5O\8C\B0|G\82\D3\C4cV\9FE\B4i-f\D2\ACm\12[\95s\84\86m\EB\F2\ACFV`\1D\9F\0EU\8F@q\EA\CA\18Z\8B\92\B2Ml\B4\F4\D2\FD\1D\FF\00\22\BC\D9\F3O\C2\CDC\C7\1F\03\BE%\E9^+\83E}(C\A8\BF\87\EFn\AE\AD\9F\EC\F1\C9$\8A\B2\C5\B9\86\03\AA\ECoP;W\D6\1F\B5d+`\9AE\97\88\FC\09\A0\9B]P\C5\A8\B6\A5\16\9E\0C\DFhRCB\D2\E0a\F2\01 \9EGn\E3c\E1o\C3/\09|E\B6\F1/\8A|u>\BFn\D6~6\D7\E6\B8\85T\BA1i\96#\94\19\8D\DC(d%y\04\B1\07\1C\8E\B7\C3\FE(]Am>\0A|J\B5\D4\B5\D3\A9\D9\DF\ED\D4.\ED\A11j\91\C5\B5D\DEd` fY\10\02\83vv\93\8E\B5\E7R\C0\CA\AE\0EXjS\B7:\DE\D7\B5\FA|\CC\B5\94O\84<I\06\B3\ACG}\AB\5C\DA\AC\96\9206\A8\17\E4\B7\80\1C\02=s\EC;\F1\C5i|!\F8\07\E2\AF\8E\1A\F3\BE\9D\AC\DB\DA\C3\A4_Z\A6\A1n\087\11\D9I\9F\DFD\87\87;\94\A6\DE\C4\E7\9C`\FD\11\F1\13\E0\9F\82</\E1\F7\F0W\87m\AE\13Y\F0\ED\BCz\C5\AD\C5\C9\95\EE\1BO\09\FB\D5\B8\91\9B\CB~Y\86\11r\18\02\00\C1\AF\09\F8}\E1o\88V\9E;\8F\E2\0F\C2-@K<\12\AD\AC\D0)>K\DC\05\12$\05A\07k\0EA\CF^\87\9C\0F\03\0F\95\D5\C1b\A1N\B2RMtv\FC\EC\F4\EA\EC4\EF-t\B1\CE\FCm\F8\0B\F1\13\E1\7F\89\B5K{\AB5\B9\D2\22\BC[}>\EAX\D6)o\22\C2\95m\99\E0\E0\95=\06S#\AE+\99\F1w\81g\9B[\82\E6\C3M\91U\EC\95\B7\05\C0F\F9\BA\FE\95\EC?\17>>\F8\EB\E2\B7\8Auo\02\F8\DBQ\B7\D1om\8A\DB\C3k\0C*\B1\F9\E8\A0\EDgpd\CE}\FF\00\A8\A6|.\B6\F1\CE\B1\E1{\CB\1F\16\E8\B33\08d\FB-\D2[\B3)t\18 \B0\18\EF\EB^fsVP\C5?\AB\A7\EE\E8\D3\F3\FC\D7\99\A2i\E8\D9\F3v\9Bm\A8h\B7\D1\DDj\9AD\B3$3n\90\94;[\19\F5\EA+\AA\7F\11\F8vWi\17E\DA\1C\96\03j\F0\0F\E3Qj\BA7\8C[u\F5\D5\B5\CB\DA),\E2<\10\07Q\909\EE?\ADr\0F\1D\E1v)m1RN8#\8A\BAx\87k\E8_;\A7\A2G\AF\FC$\F8u\17\8En\AFo\F5\DD[K\83O\B3\B8\D2\AC^9\E4Xo$\8A\E2\EE\18D\D6\CA\E3\1B\11X\A3\15c\B0\B4}\B1\9FL\F8\A1\FB?M\F0\EF\C1V\97\FA\C6\89\F6\BD\13S\B3?\D8\BA\EA\98\18:\CD\03M\F6y\C0a\221\C6\E5#1\B9s\80K(\AE+\E1\BF\C4\8D[\E0g\ED\10\FE\13\F0\D6\A6\97^\16\83V\1Ar?\88\A5\FB'\D9,\AE\1E0\F2y\B20[`\AA\CC\CC\DC#\A2|\C3\A1\1FP|F\F1\EE\81\E3Mc\E2.\91\E1\BDoC\D4\FC\05\A0\F8j56\F1_\DB\CDay\AF\DD\C3!\86KI\1C\C8\B1\A5\BC,\F3J\B1\15_\B50\0F\B5\D0M_K\83\8E\1ExX\CA\1A\BB>\8B\AAo\CE\EB_\91\CE\E1k\A7\B8\BF\095_\88^)\B0\F0\96\A1\F1\93Z}WL\F1N\995\C8\B1\93X[x\E3\D3\E1\B6\1E]\E1Y\08Y\1C\80\B1\BA\E1T,\8D\B9\C3\90k\85\F1?\83\FC-\E1O\07\FC]\D5\FE\19\FCn\BB\D4|)\A4[\A3\C9\A5A\A5\BD\F4\F1\86\8D\02\B4\170L\825\F3\83\C4fua\09\8C\97iO\CD^%\E0\FF\00\DA\03\E2\87\84\ED\CC\9An\AF\0CI\E1\BD\1E\FF\00\C3\16\8B=\A2\C8#\B5\BC\1B\C6\C0\C5p\C2eP\C5\9B\05B\8CeJ\BF\D8\BF\00a\F8j\9E\11\F0\D6\9D\E2M\1F\C3\1An\B3\A6\DAG\A4\A0\B3\D7\AD\22\96{P\88\D0\A4r\CF,r,\B2\0F \14$o\957+H\85V-\B0S\86c\15\DA\1B\B6\9D\F5[][\C9\EF\AA\DCw\BA\B9\F3\AF\EC\CD\F1sT\D3<K\E2\AF\0C\CD\E1\0D\0A\FEC\E1\8DOS\B6\D6g\D2\FC\EB\BB\1B\B7\B21\ED\92l\11$w\12\98\D5\84\D8\05\C0\C3\1C\98d\F5\EF\8B\1F\17\BC-\A5x\A7\C0\9E,\BC\D2u?\0DxN\E8\8D[I\F1n\9Fl\D2KglaI\A1\D3\84 \B4N\A1'A6\E4\95\C8VU\89>\FAu\DF\13~\1Bh_\0B~\1D\CD\AB|\1A\9FH\16\F0\DE\DD\E8\FE'h\A4\82\E2}R\01 .\CF\1C_\BB\17Q\F9\9B7H\81\A3B\A2?/\E4e\E1\AC\BE x\93J\FD\9D\FC!\E1\7F\08xr\E2\0DN\E6K\9B\09u\B9F\FB;k\BBY\96\D7\CE]\E1\97sG\22\C2a\0A\A5\9F-\B7j\C8\E1a\E7W\0D(Q\A5S\9B\DD\BE\9EM-\15\FEW\D0\13\E5\F7d\B5G\B4\BF\8A\BE\1C|a\F0\A6\A6\DAn\A3\E1?\17\E2\C2V\D2\EDm#\B8\D2\B5\18o\17\CE\8E\7F1&gh\C4\CCG\96\EE\9BJ\C8\BB\81\18\91\BEx\F8Q\1E\B1\F03\C4\F1\F8\A2?\0E\1F\15\E8\9E<\10\BE\92\D1\C5-\B4k\229`\E8\85I\F9\06\EC\B9\00aA\CA\F7\E0\BCY\E3}O\C4>\1F\F0P\F8h\B6\B6z\A4\FAy\B7\D45Km>\0B\09,.-\94[\0BQ,gv\C5\8D\0Ch2Y\91W\92\0E\17\D9\FE\16\FC\5C\D4\FE%i>\09\F0?\C6\AF\14Xi\16\BA\AD\DD\ED\C4\17-\1A\C1>\BB$\8D$\96\CA\E5\00UY\DAH\F0\AA#YT\C2\18\16h\98c\88\CCiT\94SO\9A\FA?7m5\EC\9B\BA{|\8B\94Z\D5\1E[\F1\BF\C0\E3\C6?\1Dc\F1W\8C\FC=\ABj\1E\10\B5E\B8\9BJ\D3\9A+{\D8\92M\A2I\96h\F1\E6\95%\18\82A#\1E\A0\1F\A3\93[\D0?g=6\D2\185\1Dt\F8V\DDc\B7\BBcz\935\BD\C3\8D\F0\0C\9C\B6F\C6\DC1\B4\EF\03<\F1\F2\8F\C5}\7F\C6\BF\0E<c\AFx k\8E\9A\CC\16\E8/\05\CCj\EFw\1C\CB\E6\B8\CA\91\1A`0\04.9\C0\18\0A\B4\DB\9D\1F\C5\91\FC\1A\B7\D7\AE~\D6\BA\1F\89m\A32\DD\5C\93<l\D1\B9u\D8\D9&&\0C\A4\15\EB\80x\CA\A8<\F5\F3\08\C2SS\83rW\BF[.\97k\A6\DA\8D-9\91\8B\FBE\EB\7F\08d\D6f\F1\0F\C1\8DFE\8FW\BB72Z\012Gj\C7\E6\90\04\93;T\B9a\B0p\0E\ECq\8A\E2\AD\F5M-\E0\8D\E7K3+ .A\1F{\1C\FE\B5\CD\D8\E8v\FA\CC\1A\84\CF+F\22\965\0EO\0A\A5\B0\C4\8F\A63]:\F8#\C1\B1\01\19\F1\CD\BEPm\E0\8Cq_5\88\9D\1CD\DC\9A\E5\F2_\D3\1Cj$\BD\E4hx\8BD\F0\EC\DA\FE\BD\AF\DB\C7}v\FA\143\D9j6\80,r\C1; \84]\C6\1CbH\C5\C3\10\F1\FC\AD\1C\8F\B86\D9\03/\A7\FF\00\C33\FCg\F0\B7\84-\B4\81\AFF<\0B\AF\DB\DBk\17\D70D\B761}\A6(Q\AE\15#o2\E3t-\1Cp\BE\E8\C7\EFH\DC\8C\ECOU\F0\9B\C0^$\F8\EF\E3s\E2?\8A\DE\0F\D2\BCg\E1\D1\A7Z\E9W\DA\9F\9Fqc\A9\D8\8Bv\91b\B9\83\0Cf\95\D1\DAHK0\C9\8A\DD\17\92\BE[}W\A9\DD|=\D0t%\F1&\9Fq\AC}\8F\E1\D6\B5\A9Y\BD\B6\96\A2\CE\0Bx\84\9B/\8D\EA\A1+9B\AF\BB\04\0C\DC\B1\95v;\13\F4X\5C\05\E3*\94\FD\E8\B7\A5\9D\B4OU\D9\AD\F6\ECe\0Fy\DD\BB\1F\9D\BA\97\86\F4\AF\0F\FCo\D6\FC1m\E2KX\B4m3V.\D7\9A\B5\A1x\A6\8E9\BE\D1\E6\CBn\84\99#\DF\13n\0A\C3\F7{\B3\91\95<\FF\00\85\BCY\E1/\05x\F6\DF\C5.\FAu\C5\AD\B6\A3\1E\A7x4\DD\AB\05\B4\B0\DC\BB\C5\1D\BC2\A3\06\0A\C69U$\12!\87pq\94ll|r\F8\BBs\E3/\8A\1A\CC\B6\B7\16\17\F6\10\EA\DA\8C\B6\8Dnd\B8\B7\9DRi\13z\97fa\14\D1nc\FC;]I\1DZ\BE\BF\F8\11c\F0[\E2\AF\82\FC\03\A7^[j:\B7\88\FC*~\CBk\ACjJ\B6\BA\B5\94+\14\A0\B43\08\1A)\92\22\1B\CAG2\15\F2\B2K\BCjB\C0a\AF^q\A3-\22\EE\BE\FB=/}?\22i\DF\E18?\89\DF\B5\E7\88\AD|\14\9F\0F\BC\15\E0\AF\B0x\A3]\BF\9A\F7Q\83T\B33,\FAu\D8\DDmv\AD\03\A4\91\5C#\14\81\D6BWq&0\CAvG\B3\F0\83\F6\BE\D1\87\81c\B4\F1v\AB\A7\F8~\EBF6\16\B3XY\E9A\AD\F5%x\A5\8E\E2\F3P\88!\CC\B1Lb\90\C7\A7\B47\13\CA\E4\BAl;\E0\D1\F8E\1F\C6\FB\F7\F8\EB\F0\DA\F7\E1\F7\855\9F\12\DCj\0F4\96v,[M\92{\BD8%\893\19U\E4\B6\95 (\9F0e\F2\E52\FE\F0\92\BE5\E1\BF\D9\E7\C5\B7\82o\05\E8\B0iz\D6\A5v\91I\7Fk\7Ff\22kK=\CC\B2^\88\E4\1Ed\8B\1C\8A\B1\AE\C0\AD\BEdwX\95\B1]\15\E1\8B\A7(\FDV\F2[[kk\FDm\F9\1A7\AD\CB\BE?\93\C2^ \9F\5C\F0-\B6\B1u\AEi\B7\9Fek\8F\14\DD\DB\C9\0D\D2\DE\86P\B0\A5\B9(c\91mb\86\09\8B\87\91v\CF\08'1\AC\1E{\A1\F8\FF\00O\D0\BE%Z]x\F3P\BB\F1F\A4\B3Ci,\AA\D0%\8Ai\EC\88\B2C$1)\8Cl\8DB\18\D0++\AB.U\94\14\E8\BE\12\E9\16\13\F8\8B\C3\BA\A6\BD}w\F1\17[\D6$m\17J\D1,\EE%\B4\B7\96\F2e\8E\D2\07\B8\D5.\15E\ACB\08`+\B0K#\83\82\109a\EB\7F\0F\BFf\0F\01k\DAF\9F\E3\0Dg\C7\11\F8v\DAk\FB\AB}b\DE=z\D9\ACmZ{\B9\A0\B7\F2\DEEK\88\97\CFkr\AB1\DE\EB!G\D9*\18_\9AXj\D9\8E!\D4\82IG\A3v\DD\F5z\E9\F7\BB\5Cm\CDI4p\9F\B4L\D6\DF\1A4K\7F\1D\F8\1Et\D5-4=:\DBQ\BB\8AV\8A\19\ED\1Eg\9A'\B5D\00O*,P\A4\8E\8F&\E8\FC\E8\88/\92\AA\9F\06\FF\00i\EF\86\F3\E9\93\FC!\F8\89\E1\8BX\BC?\AC\A2[L\EDq\04V\B0\CAT\01(\8A\0Bx\8Ce\9D\E4b\E6F#\E5\0B\B7\15\85\F0W\C0z\CD\FF\00\C4\AB\9DM\F5K[\BD\17N\BC\D44\D5\8FV\BD{\08\B5;t\9C\C2TO\83$\8C@$\AB#,`\B0(w\15\AF\A0\FE*|\19\F06\A1\E2O\16x\97\C2\16\DAe\96\8F\A5h\10jW\1A\B4\D6\90\B6\9Fr&3\AB\B5\AC\FB\85\BF\96\BES,\9F\BD\01\1D\19I\DB\90j\8F\B6\C5M\D4\83I\FC-=S\B7Eu\B7M\CB\A74\9D\E4\AE|i\A2\D9h>\1F\F1\C6\A3\E1\9DKN\B9\BC\F0\A4\B7\93\C0\93\99\95\84\A03\18\D0H\BC6U}\89\EB\C5t\D2\F8\AB\C1\91J\F1\DA|9\F0B\C0\8CV%\97Q\888@x\0C3\D7\18\CDrwShv\DAe\AD\87\87\B5\18o\D2=jb\F7\A2\DDbF\90\A32\C4\02I\222\8C*\EFV \EF?\DD9\E6W\E0\ACZ\8A\8DA$\D5Qn\87\9C\15lr\00np\0Ey\1C\D7\CB\D5\A3\05^q\C4>F\9FGu\BF\935\E5\E4v\86\D6Ok\EEwZ\7F\EDC\E2\CF\0E\FD\A2\FB\C2z\80\D3u;9\A3\B3[x\96H\A1\D44\FF\00:96\F9\8A\DEnL\B0\A7\98\85\D7zH\FB\B7|\CB_[x\EB\E2\B6\BB\FBA\FC9\F1\F7\86$6>\1E\D3\A7\D2\B4\F5\86;m\5C\BD\E24\862\C8b$3\C4\B3G*\17\09\1Al\94\A9F\12\B9\87\F3W\C5\96\D0\E9\1E(\D5\EC\F4\E0\F1Ei\AB\5C\C1\0F\CE\CC\CA\91\CA\E1\06\E2I8\00rNx\AFG\F1W\8E<K\A3|(\F8i\E2\CD>\F6\14\D5\A7]G}\D3\D9\C3#\16\8E\F2\E1Q\F0\E8@u\120\0E\06\E1\C6\0F\CA\B8\FA\DC\1C\1E\1E\94\A9\D3\D9kn\8F\A3[7gs\99F\D7G\0E\F7\EF\A7\B2\88l\A0\86\E2\13\22;\A4\8CX\1F\99J\19\14\ED`F\FF\00\BB\F2\B2\B7\19\19\07\DC\B4\9F\8A_\19\FC#\E1\8F\0Cj\B3i\D7v\9A5\95\C4phS\CB\A0\BC\16\F2\DB\B2\CF\89\8C\B1*4\DB\D5\AEB\E6BY\BC\D2\8A[\CCj\F1\ED*\CA\DBV\F07\89|A\A9\C6n\B5/\ED\0B47R\B1i\08\9AW2\FC\C4\E7,FI\EB\C9\F55\FA\F1\FB.x3\C2\9F\13\7Fd\AF\87:'\8E\F4\0B=_O\F8\85\15\FE\99\E2;ic\0B\1D\F46R\5C\C3h\DBS\02)\A2\8E\DE\DDRx\F6\CA<\88\8E\FC\C6\A4pP\9DE7\1AN\DD\1F\E0\D7\AE\B6*\14\D4\93g\8B|3\F8\BB\F0?\C4\BF\B3\DE\8D\1F\8F<O\06\90\DA\95\EE\FF\00\14\E9\BAN\9Ds\15\C6\9B\22j)\9B\D9\EEm\22O.<\CB\04\D2\CB\88\F7<\FBQ\BC\C2\AE\9BZ\BF\8D>5k>?\F1>\B7\F0\E7\C4Z4zM\96\9Bm\E2\1B\0DRG{\8D?\C4\17\82&h\AD\C4\F7\12\C7o\1C/\14R,\D7^c\15\F3\90\0Cob<\07\F6\8F\F0\AE\8D\F0C^\F1\85\9F\C2\A8\EE\FC;\0D\B7\C2\FD*(\D6\DA\FAv\F95\0DS\EC\97\AA\DB\DD\B7\89afR\1B8c\BCa\C0j\FAO\E05\85\BE\8D\E0-%4\FF\005!\B7\D3|oa\15\BC\93<\B0,\1An\BFg\05\92\F9NJf8\DEA\BB\1B\98\BB\B3\96f$\FB8:\8E\A5G*\9B\AB'n\BA\FF\00\C1\B9J-\FB\B7\D8\F9\CBE\D6\FE#|$\F1\B7\8B~(|=\F8qi7\87d\B0\D5\AF\F4m*\EBQ\8AX\F4\DD\08$\91\A3\C3\E5\B1w\8E\19dYf\B6\8F'm\BBE!\1EZ\C8\BC\B7\EC\E7\F1\C3\C4\B6\9E9O\16\FCK\8EMkE\D5dkKa-\9D\B4p\C7*\5C[L\D3\C4\1B\08\B2\A9\B5\85\9As\CA<0\B1\93x\DD_\A1\BA\BF\86\B4+O\8CV\DA\AD\BE\9B\12\5C\E9\DE\0D\D4-m\9B\92\AB\14wZd\88\85O\CA\C1]\98\8D\C0\E3s\0E\84\8A\F8\03\FE\0A\0Fikc\FBTj\90X\C0\96\C9\A8Yi3\5C\88F\CF2G\0F\0B\B1\C7s\1C1\A9=N\DFRI\BCm9e\EB\DA\D2w\8A\96\CF\D3\CA\DD\CC\B9\A4\9D\AEV\F1/\C4-/[\F0\DD\F7\89\A5\BC6\DE\22\D5$}CR\98\EE\9E\DFMiT\ECX\D5\DBj\DDJ\C0\05n\91\A8\DF!\DD\B1Y>\1D|~\F8\A1\A3\F8\07\C3~\1F\F0\D4^\1A\B7\F0\7F\84o\AE\BE\DD\1D\FC\B6\B6\F6\BA\A4W\1B\D9\AC$\86w\DFu\0E\C9n\01\11$\B27\DA0\E1\D9\93w\85\F8\8FR\D44-Z\DA\1D\1E\FA\E2\CE8\D4\00\B0\C8Ts\C9'\D4\9C\9C\93\C9\EFW\EE/&\D7t=kR\D4\84oua0H%\8E%\84\80f*wl\03\7F\03\F8\B3\DC\F5&\BER8\BA\91\93\C4\C5\D9\CF{i\BE\BF\99\973VH\B5\E2\1B\9F\09=\ED\CD\8F\86t\D3\A5\E8\E6\F1\EE\ED\AC-\E73-\B9n\06\E7 \09%U\C2\B1\8Cye\95\CAnR\09\F5\1B\1F\DA?\C4\96VV\F6v\FF\00\0D\B4\C6\8A\08\92$;\E3\5C\AA\80\07\1B\B8\E0t\AE7\E2/\86t\1D\1FA\B4\9BL\D3\22\B7p\96\E8Y3\96\049\CBs\F3\1C\A8\E4\E4\F5\E7\93^\CD\E1\8F\02xZ\F3\C3zM\DD\CE\9A\EF4\F60I#}\A6Q\B9\9A5$\E06:\9A\F01R\85G\CD5}^\F7\FD\19\DDJ\B5X\D4\92R?\FF\D9", align 1
ram_two_ports hana_jpg (
.clk( clk ),
.address_a( hana_jpg_address_a ),
.wren_a( hana_jpg_write_enable_a ),
.data_a( hana_jpg_in_a ),
.address_b( hana_jpg_address_b ),
.wren_b( hana_jpg_write_enable_b ),
.data_b( hana_jpg_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( hana_jpg_out_a ),
.q_b( hana_jpg_out_b)
);
defparam hana_jpg.width_a = 8;
defparam hana_jpg.widthad_a = 13;
defparam hana_jpg.width_b = 8;
defparam hana_jpg.widthad_b = 13;
defparam hana_jpg.width_be_a = 1;
defparam hana_jpg.width_be_b = 1;
defparam hana_jpg.numwords_a = 5207;
defparam hana_jpg.numwords_b = 5207;
defparam hana_jpg.init_file = "hana_jpg.mif";
reg [13:0] hana_bmp_address_a;
reg hana_bmp_write_enable_a;
reg [7:0] hana_bmp_in_a;
wire [7:0] hana_bmp_out_a;
reg [13:0] hana_bmp_address_b;
reg hana_bmp_write_enable_b;
reg [7:0] hana_bmp_in_b;
wire [7:0] hana_bmp_out_b;
// @hana_bmp = internal unnamed_addr constant [3 x [5310 x i8]] [[5310 x i8] c"\BC\D1\BE\99\8Fg\95\C0\AC\9D\BD\C0\A4\C3\BC\B5\C1\A7\BC\D2\B1\8E%\0A\1F('4 \1D\22\0E\0A\12\0E\1A\07l\B5\BE\B5\7F[cI$\0B$B]ZA3 $#&58#\19\19 1)6 \1F\1F\22\18\19&+ \0B\09\0D\14\19\17\11\10\12\1E\19!-$\1D\A6\C1eZ\AA\81\92\D5\A9X\91\C7\CF\A5\89q\C9\9B\8B\D1\BF\C9\ABg3\1D\11\09\1D+!$\18\0E\18\18\04l\B9\B4\BA\BC\B7\C3\C0l0KgUE1.7,*23)\1E\12\0E\1E006\22(&$\1F\1C47-\0F\0E\10\17\15\0F\0B\11\19\1F\1A,I\22'\91\84.\B5\CD\D1\BB\AA\8C84\8Ez\B0\C6S\9A\D7\C8\D1\B8\A4\C4\AE\807YL\1C&/.#\1B'\1F\10:t\89\A9\B8\B4\AF\A6xI[aT $>:()0- \14\0F\10\0C\1B\18$(\10\22\18\16!=A7\12\15\16\1D\13\12\0F\15\1C!\1D0K$&o\0F>\E2\CF\BB\CD\BC=\02\0D\1F\09i\8C1\18\BF\D1\C6\BA\B8\93uY:\8A\B3\87>43\17\14\22\1C\1A\0A*p\97\9D\8Bzq6OT`.\13 5:(('&\15\15\11\17\06ne\0E\12\07\0F\1B\07\1B@F?\16\1E &\16\08\0A\12\14\1A\1B+:,(\8B\8C\81\9Cq\B1\D7\AEoe$\0E\14\8BbjQ%a\DF\C8\D9\95\99\94\83F\92\B2\AC\83P\0D\11+\10\12\14\18b\82\A3\90UGQNXD\1D'8;1()'\14\0B?P\01Y\B3\BA`\00%\0F\15\14\1B@LI\1D\1F!+\22\0D\0C\13\10\10\0E\1C&<2\B3\C4\D9\847y\D5\B4\B1\B7\AEf\A1\B6\8C\93\C5\CE\A4\D6\D9\AF(\8D\AE\B7{Daw{~1\15'\11\17\1C\0E{\95\C2\C1_KIF?;207:*06 $\0CU\9Fn}\B1\BB\89\196:7\12\13;ML\22\1E 0/\22\12\0D\0D\0C\05\0C\1249\88\86\AF\D6\86\A1\BE\8D\B1\BD\8D\A4\CB\B3\B9\90I\8D\CE\94\B5\C0qE\95\B0\8DtS.epO\1F\19(\1E\1A\0Cb\A2\C3\[email protected]$,/\1B7\B1\C8\AF\A9\B2\9Cr~k=.2<NL.*0;:-\19\14\16\1A\13\13\0F8:)r\C4\C3\D0\C5\BA\B0\AE\CCy\88\D0\CD\C9V\0C\BE\B4\B1\94\B2\DD\91a\92\88\99\A9\8A\93\BF\A79/\A8|!\056\BD\B4\C5\BC\88D6?2NSJPZ:,<-,\12\80\C2\B0\C9\CB\C4\AF\8Ek=,=JVS>@GH??7941'$\18=9\13K\C2\A5\A8\BA\C4\BB\CB\CFVA\82\C0\D6\B8\90\AE\B4\D1\93Llt\9B\9A\BB\AC\B3\B4\BB\C7\CC96\A5\7F/ZC\BD\B3\AA\D6\C3\9Fg( @aB55CM./'\0A5z\97\CA\D5\D6\BC\A1\91j<:N]aefVUG927664+(\15\16q\0B.Bh\8C\A4\A7\B1\D2Gsi\BE\A3\B5\BB\B8\8E\B1k\CF\80qy\9C\99\8F\A1\9A\A5\B6\B67-t*4x^}\B4\BB\BA\C7\BF\BAN\00+`vR\13LLG7\1D\09\08;o\A8\BD\CD\BB\A6\8Ao2)7L^kte\5CH32/'+%\1D(\19\1BdD3.8Q\5C\98\B0\CAG\8E\CF\C4\C5\90\B5\B5ixO@\B3pfa@?3^\B4\A4\93%D\A9^da\8A\01D\B2\B5\AD\A6\B6\A33w\A5\BB\BBA'ORG\0F\0E\0A\0C@\90\B9\B0tF<)'\19\17+?VnndK1\1B \1B\12\15$%\1D ]>\22\1FG>f\AF\90j:\C9\AA\BF\BD\A7n\AA\AE\86yT\A1xU>@+\09N\BA\B9\AA\14d\B4\9F\B0\AC\BDdj\A9\AA\99\B4\BD\BB\BF\96g\8A\9B}1M=>H\17\12\15\1B'RP55GT:!\04\12#?exkF'\1C\1D\19\1C\18 !\22\1Fb; \11\22\1CEy\1A.L\ACk\13\8E\99\88\92\D6\A5\BB\CF\B3~?Q&-&a\AD\B8\9B\18d\CE\B0\C6\CE\E2\98k\81\99\92\BC\BB\AA\B3\B3|\9B\B3\9A]IAQB9\14:<$/8\191JZU,\08\0C\180SzxW%\1D\1C\17\17\14\1D\1F\17\14a3\09\0F\0E\10\17X %K0\12\11\18\C5\C8\AA\C4\BF\CA\CD\B6d8#\1Cq\5CG]VV\22N\BA\C2\B6\C1\B4\A5NVz@i\C3\A3\94\BC\94\96\96vx_IMKF?O_@R;\1F\14+F]T\1D\1D,>Npx],\22\22#\11\11\1C\14\17\1AU:\15\18\1D\11\0D\1F\0D\15Y\1F-\13\15\92\E1\D2\CE\B9B\A4\B7\BF\95<Bw4J7\8E\9E\14K\9A\A1\C9\93\8A\B6\8FzT\15t\AE\AE\A8\C6\80IN\A6\9FNI5$q|X\80\7FjB\09\17\14)JYA4>I?[ob6F=?<2\1D\16\19\1C%P\19\17\10\04\0B\16\0D\16V\1D\122\19\08w\A3\A0\B9\A1\9E\BD\B3\84wt'\81\AB\89\B4\AE\13u\C2\C0\C1\AE\9Fw\A5\B1\A8,y\A1\B9\C8\C2\A7RR\A2\A2J37\0Fc\9Cv\7F\B1\A3H\09\0D\0A\05%GMFm\8D{\85\89uIOESPRC/\1C\1A\0DM\17\12\0F\10\10\22!\15U\0E\00%,\00\B3\E1\BB\CE\D1\8D\95N9?H\81\9F\A4mas\1F$[\19]\D7ld\B4\B5xDR\A8\C3\C2\95\B9\B3\83H\83K7. =\90\96\81\C4\B6yWQ\06\05\14&8d\99\AC\CC\CC\C6\D4V A3;9;43,+\1E \142F1\13\1A(EdK2(\12d\C0hdiv\83\81*L#I|\92h\01\1CKb\C5\A6\B1\D4\C9\AF\AE\C0\8Ec!W\D8\BD\C1\D1\B9\BC~~\5CV:#\1Ct\AE\B5\BC\B4\A6\88V\10\01\00\06\17?g\88\AE\C0\9B\C6\AD#\10*3(&:+,\1A\1D\19\0E%K#;\13;=e7QO\1D0VmQB\BB\8F\B6\8E\0D\02'N\90i\1C\22T\1B]\FD\A9\F2]\D8\A1\9B\C2\E7\8B\07[\CD\CC\E2\B8\DF\EA\BEp\5C+%\14\84\C2\C6\CB\AE\8A:\07\00\1Afn[yx\84m\AB\A7\A5\D9\B0RMD3\16&,,\05\16\1D\1D\07c\1E\8Be5<d\87L@ $36Wo\93\F0\BA\AC\CD.\00.\15\0B>%-\1A\00.\C2\BA<\EFb\8C\C0y\13\B2\A4^\B7CW\C2\C2\C4\BES\22 8U\AB\B6\AF\CE\99=\01\06@\A1\C6\B3\AC\B3\AAp\A2\DD\BF\B9\B5\88ZV9\1D\1B,+5\14\0C\12!`8\9C\8B\84=/uqe$\1B\05?\A6{\15\A3\CF\E0\B4\81\D4\9F\C1\CD*\143\17\1B\110\F04\B1\B1\95@\01\8C\BA\B4\CC\D3\D5e\BB\C6\96:p\81V7?MJf\92\9Ac50\1CW\B3\B1\AF\B2\AFt\86\9D\B2\C1\B4\94}U\1C\14\12:;\1F+\0AG\B1\92-\99v\B8\8D3\1B8M-\1EH\91\9FZX\A8\8E\B7\D4V\AD\CC\C9\84\00!1\15\09\00}\BE=Q\B1_H\17\0F`\AD\D6\B4\E5\DA\BA\B9\DFH\92\A0\81V>NB]oqZIRJ\03B\96\BF\B5hxZtr}\ABz\84B\15\19\1B;<%!\0D\1A\C9\BF4\AA\89\BD\D9\D0\98\1Ao(\0A\94\A9\A2\99\86\CC\CB\AB\92=e\CA\8E\00\09,6\13\0C\00$\A7R\1C\D9{f\0C5\17\00/\00\C3\C2\BC\AC\B0\AE=e\9D\88m(,}\92\93\80MaqS6\AC\BE\A5\9F\BFUA?!-?<!\15\13\10?=\22390$\89\18zZ\E6\C2\D2\BEP*3\12\95\D3\9F'{\AC`?\09J*\94\E0w\0054\1E\00+\BDu^%\9F\9D\D6g\16\1E\0D:<,Cd\A8\A3\B36\8B\DB\C1qD\8C\8F\8D\A5y~W\92|_\A6\A7\82\9C\BDl*+)\11(\1E\1D\17\13\12=<\0D#^z2u\CD\AC\93l\DD\BA\B7\89&%\1Fj\D0\9C\12\AF\E5\8B\00irc\0C\92\8D\A24*\00>\B1\BA\88^ {\92\D2\C1l\A8\91\08\C1$=E=\A6\9C\CB\7F\C3\E4\92\A9\8DZ\88m_bZ\99\8FVRa`c\7F\84&.$\1E\18#\17\19\1B\0C\10\1E\0E\00\04\16r\99\9E\AD\BC\BC/p\F8m\CD.\22O\B5j,\B6\C9\8D\00\96\AC~\AA\A0\86zk7\CCm>\98\EB\5C&\86e\B7\D9\94\98\9Fs\BF\B0\9B\90_>4\BA\92\D8\B2\FB`I~\8A8a7gx~I0\2290\8D\8A9!\22#\17\16\1F\1C\14\17!\1E.\01\13\1D\1B|\A4\AC\CA\DA\B0d\18n\BD2,%c\1D\1Fb\A40G\C5\99\CA\A7\9C\C4\C08\80\D9\AF}\991j\0F\80\EF\B6\C3\AB\5C%nVv\94b7\22\1E\150\E8\D1jWk\AC\1EGVXH>1B.@PDLo-*#\22\1C\1A1+\16\1D \90)\00\15\02\00X\A0\A7\C0\A8W\00\A9\EB2#\16\0Cb\00\17=\00G5\F0\90\CE\B2\BC\E1\C8\A7\CE\DFv\0CKm$Q\E1\C2\90\B6I p\A7]2,\1E\113+]uqI\D2\A2cWWA\22\22\16\15#Hgc:8/-(\1A\1E\22>9 %\1E\1E\B7p\00\08\0B\1A\00w\CD\94\D2\00<\E1S:#\1E\06%=\07i\1F$\07Y\E5\AB\AC\C3\DB\D3\AF\B1\DB\90J/j%2\C2\BCdS\19@1\BB\AF\84\19+\19 0\1EJlZ\8B\D2\C5\83jO*V@#$&D]Wg6W))\15\18\1D=:&7\14\1E\91L\05\0A\02#\00\91\BF\D7;\05\96\B3\89.,\18\09\18F>\15\0BA\8DW\7F\AD\8B\A9l\D4\B5\96\C2\CA\9AR:P<Y\8DT\00hh\1AR\A1U\0C\10<LH\02R|a\A2\F1\B9t\91*1XD*\14\1BAUdO]:L\1E\16\15\1C=:%A \1Cc(\05\09\0B\17*\DC\C4\FF\00\1A\E2\A4\82n\1D\1F\00\1FF)%'f~\9C\D1\9E\D7\F9\E2\DE\C3\E8\E2\CA\A3]?T3\83\9D\00\8BKr;\0B|^\1CEna/,\91hc'\B5\BC\B9\B76\12'.C-\07g\A3\86mMK(\1A\16\18#>@%2 \1F\87h\0A\02\14\14\1A\00\1E\0E\15O\88le&8\16\19\1FA=\0E\16;w:RbJ)\9D\C8HR\DA\9D\A6yRq\11\9E\D1\92\7F>~8\07FbaIIb\04\A6ju*%\01\B6\CB\B2<\1E\19-7)\16@\B7\C5\B4aB'\22\15\16(8D,\1F\1F!U >\00\14\11#,\13\17\00\93\D0IU\0EF\09$%:N\17/\04\0B\14\03>A\12\92\C5\86o\C0\DF\BA\A0\7F}<\AB\D2\D4\CF\A8\AE\90\BF\00\94x#B\1DO\B6_G\19^rG\A6\BF\93`\18\14/\1F'(p\A8\D1\98M'\11\0C\1D3AJ,\0F\07\15QB\0C(\00\0DZ\18\13#\01\95/\5C[\07D\0A,\1C\1C_\00\A0j\0E\1D\0CE+\15\F5\BFz\C3\E5\D1\CF\9Ba\8A\FE\AFv\F7\D9\D9\B7^ksBf\8A\0D\10\9C\80/\16\0F,\A2\8A\9B\A5\A7\ACX\03#\1F\87\86\B4\9B\C0\BE\A55\09\11\1C5KNF7\1E&9q\07!\0A\1FE\17*\0D\1C\08\017\1B;=\1B)!\0D%(\84\8F\08\16\10,XTH\98\A8\AC\C1\93\C9\B2e\00\E0\E7\FA0\03\C1\E9<N!\9F\8F\D4\002\00\09\0BK'AC\C6\C8\918RO\142S'i3F\B9\D2\D0\BD9\0F\19);HPp\1F$@ra\00\18X\95\1C\0F.\10\096>\01\00n?\10\1B!8\17\11\00+.B>\0C\7F\A7\BD9\FB\E3z\02\00\07D6_P\F7\A5\D4@o>\DB2\7F+S8$\111B{oy\91\7F\AF\BBT`_\0F!8\82\82\CE\A8\BB\CE\B3\90-+\1B\18Knz#\1D^IK\86\0D\22PJ\0Byo-3\1D\22\BE\D5z\11\19\19\0Bns!,B\0A+\05Bs\859J\F4\82\00#\10\14Y*<\E6\DBN\C5\EB\8B\93.\0AzuoZ68CR:\10\8B\91\9E\D2g\12%0# %\09!#x\A1\AFyD.\0E\168gzG\5CWS\00\5C\7F\14,\0Fv|yP/S\95\8C\B6A\11\1A1Af\BAt\16\82\0D\00?(7\18e\0A\1C\82\02\15.\08/:z\FB\13j\D0\B4\D4e\067\5C>}AY'\22\1E\02!oVw\D5\00\A3]\11\19#\1B\1B%#?i\AA}2\18\02\10+RNbaX\12\1B\00o|\17\22\8F\D7\9C\B9\9F|n\5C\A1@\16\0F;BAN9#\16*\0CX\00\17!wS+\00\12 6\1627\03%\9D@\00\0B\92\16BcD\5CNF\A7\1A\18\07\0C,<\05W\904\C2\AAU\19\1C\1E\0F\19\16\155|~R6\0C\1C$8=gk\87\0D\19)\18\8E-\1C\13\F3\CA\BA\AA\EB`o\8CP,\08#\15d\14\0F\09\00\0B%\00\1F\01g\8Ed\00\0CV(h>\0C\14023\135\8E\13<TdC?]X\02)\16\16\1C*2(,#Vx\8Bw9\12\14\08\02\12\16\07&3C:<[&0Gjr\A8\F8F\14)\00\138m0\D1\BD\9Cy\FB\AC\CAu\82s>\11Q\10+\BF\A5C\02\120\B2\A0r\00\8F\CC\BB\A9+($.#N9\06\11V\B4\1Eg\1C\17sb>\14A:7HVRQPA\179\5C\9A@aN:(!+['\19\0A IH!18\0C\00N\8C\BE\00\5Cl\12\0D\8B\C4\C7\D7:J]\D7\AD`:U_\151R\00f\DB\BE\96\03\97\7F\9E\9D\00\CD\DD\AD\BCg+0$H[{k8\09]\02X\0EQ`I<\14>-6D)9\1F\18<Z\084S\81\C3\81]NX\83lh4\1D/YM34T\01\03ZF\82\01\8A\C1\CC\85\9F\AF\B8\DCMg\B6\B9\D1\83h,0-\1AJ\16\00\88\DF\BB\B4\A2D\E291\A9\98\D6\D6\B2\152,<5Qg=& \162\02C\AC\B7\B1\1B#\17\0F\0ErP(-\1C\0C\09V\AC\AF\B7\B7}W}X\82Z;\12AoN%\22<\01\05\0C\1E\08\11\17|\C4\DF\D4\92y\C6\E6\E6\A2\D4\83C#'\0E\1E\11&+\BA\C0\B3\DA\B8\D8\F9\1E\16\05+\AD\A5\9C\005\05:4Dg\1F)\0E\10P \0Ec\F8\C3Vh\BC\CAWR\B6\8CY\14\12\12/0l\E1\B0\C6\CEbauZG)\0E*c5\1D\1C)\07\00\1Ff\1A6\09\00\9C\C5\E3\C7\CB\C8\EB\C2\8A\CA\9F\0E/ \004$\0Cl\96\A4\B3\B3b\9D\CF\01\0E\00gv\98\9F\00\22\99`M\7F\12\04g\13\1AN@\A1\E54\00\00D\A9\82\E7H\D0\C5|\05.]/GT7\E5\CA\CCaq\96\9A\88\8A\84}4I\16K)\16\00YK8IL\88q\E2\B5\86\B0\D6\D6g\96\87\D5\00/\12\05\0F5\18\1C?\7F\C6\C5\AB\A1\DB\CC\1E\00u]n\9A4\95^g\8F\91\00\7F\92}C\B3\B4k\00\09Y\C3\00\D1\9A\8C\C3\97\EB\A9\02-1G\9A\94\B0\BD\DAkG\BC\C7\97K5PJ2D\15D8\04\0B !M\87\C5\C0\B4\93\CF[\93\8D\C3\B6ad\93\01,\14\0C\0D\08! \19\1ERs\96\D2\C0\DF\D6\00-\C6\B1\B9\DCW\5C\844\A9\BA\9A\A6:)X-\14\18W\FFR\A2\BE\E6\D4\C0\C1\F1S\13.>\81\B4\A8\B6\E4\EDe\07\AE\BF\AB\A4mC\0A;<\1B\1F6\0F\0CU\1F\89\5C\AD\CA\C0\BC\EB\1A[\DD\9F\D0\B5\18\0B\13\0C\12\04\0EA\19(\1AnL\86m\CB\C0\A0\ABC\00\F7\C7\D4\F1\A6\8D\8DJ\1C\D9\CE\BF\0B@0gd<<\E6{1\83z\AE\D7\00wh\00k\88W\5Ct\82Ob\F9\82\CF\D5\A0\00\00\13!:M)'?\11\12WHxYJ\DE\DD\AF\B6\D3\DF\AB\E1\C1\88\08\0C\0B\0F\00\0D\01R\19\22-\AFP\9B>\A3\A2\85\00\8D\AC\C0\C8G\92\F8\C3\8C\B5\F0\9D\D8\D3\02UqY\1A\A0\E0\A8\99aQ\C1*\C9\03\D1\BEZG\81Y??j\04\04\D2\B1\D6\9C\EC&\0B\07\19_`)1=@\816|g`_\B9\12\93\D0\B8\A0\B9\A8\D1\00\0F\16\07\15\1A\1B\15\04\1E\18\8D\A5\BCm-~y\8F\B4\BA\C1\E7\A4D\08\A4\C1q|\8D\AF\A8\E3~$4\00\A0\88\BB\CBj\AAR;8\CB\E8\AA\98b*,Ob\849\0BX\C6\C1\ADV\A5\F6?!\0CI8*)1z|miQT\16HA\94\C3\DC\B8\D3\87\CA4\00\0E ./,\19#\1D\19&D\089NY\87,\8B\A5\BE\AA\CAY\C7\C1\C8\88\80\9Bb$\C5\EA:\00%Hr\EF\A15\00\13\00?\A3\9A\B8\96Ybhf{J\07Y\06~\E88\11>\C6uiC%\1C+2\1C\83\8D/\1C#[F#\10\16\CE\BCAT\C8\8Em\1A%\15\06\1D\05\1E\0F\11\1F\0B\0B+>&\08\14^f\B2\A1\9C\92\EB\AD\9D\87ob\18'#&\D4s\000?\14\EE\00\05\0C\01\12\22\86\8F\CF>Ua}\9A@\004\09#:d\16\13\19f\D61. 74.1\8C\89;\17\08Wn\00\17\02\1A\A2%Y1\BEvO\03\0B\11\15\15\0B\15\04.\11\17-3.\1A6\00\0D\FE\E9\B8\D0\96\F0\A8\90S\08\04\EC\CC\06\B8\00\22;4\0F\00\19-\03\0B7\1Chv\B6\1BD^\9E\82\0Av;\1E)?\15\12+,\0B`\07,33-35m\93D\00\01\00[A\07\0AKoJ\18\C7\8F\8Dc\00\0A/\0C\16\19\10\10&\0A\05<Y\08\15D\127\EB\DB\FF\C3k\FF\D3\C0z\0B\A3\A6\B2\17L#!O\190\0E,\0D\0D\13\07\1A<GS\1B3\85{\00]h\13' \1F\00\02\15h\06\8C+# *!6\88\90\13\18\06\00\02/\04\13EXb\84\DB\C7atS\00\12\12\08\14\1B\0C\0E\0D\14C\04\0C/\09\19\10L\ACU\17\19b\C4\B8J\13\B1\8D\DA\F2[\BB\80Uk\D8\5C\00\10\0F\0B9U\125\92\17VU\03X: 3\1D\10\0A*\C8\9B\A8$a\15\16\1B\1D1*\1D\98\9D\1A\0B\0F\0A\0C\0C\0A\19PPM\1B_\A1sh\15\11\0C\0F(\0E\12\0D\04s\D4m\C0!\1E7.\1B\0FO \DE>\08\06\8F\A8\A0\AC\B2\B3UUA\CDx7\89\D1\0B\0E\00Mx\22'K1)4\12+[C\0E\0F\06\16\1Ak?\1C\00' \18\1D\14 \1F'-\98\9B\0F\0D\00\00\0E\0C\04\22>5]8I\06'xn\00\10\00\00\09\0D\00 \BC(\CF\F3\E2\00\06\0E\14`/\18\B3\F8+\06V\DC\96\B3\CF\A3\A2\8A\CC\D2J+\C6\A6\BE\D3\AE\074'\228\1E\1F\0B3?7;WSF,2\1B \22# &\1F!\1A;9-4CI\00\00\06\03\0B\08\02\05,#\AA3L:\8DR\0F\00\00\10!<\05\00<\AE\C5i\E2\F4\F2\00\00RA\1B\10-\A4\00\00\83qqH\D7\BF\CD\AE\C7\D0\89\00\CF\AF\EA\D2\F0:#\1A\22\19\14\0C8<\12\16\16\1A.B^OV\1E\10\12\1D\16PM9\1E8&-FL[\02\04\09\12\01\03\04\00\00}c\1A\02\00\00\07\06\06\1C`>\04\16\1F\1D\F9\F9\D1\A4\EC\EF\A4\CE\AE\07B\A8\00\07\8C\00\C1\EF2\DA\B9\97\CF\D8\AD\BDK\DC\CB\A8\E0\CD\80\00'\14\03*34,\17\0C\0A\0A\14)\0A!\22>D\19\12NVUEQ1%#S[", [5310 x i8] c"\BF\D5\C2\9B\8Fc\93\BC\AF\A1\C1\C2\A4\BF\BA\B1\C1\A5\B9\D3\BC\92/\12\1F&$5+!,\16\13\1A\11\18\08k\BB\D2\BE\87^aJ#\118TjbMC.( 8B@/)'$.*7!!%&\1E$',!\0D\0F\11\1A$$\1B\15\13\1C\15\1B&1'\A7\BFbW\AC\88\96\D4\AAV\8E\C4\D1\AC\8Dp\C8\97\88\CF\BE\C6\ADj2\19\0E\07\1C(#'!\18\1D\18\01j\C1\C7\C3\C6\BC\C3\BDj8^vZI=?F4-A8-*#\1D&36;$/2-&&:</\16\1A\19\1E\1F\18\12\13\17\1B\13%A'(\8D\81/\AF\CA\D9\C2\AB\8855\88w\B8\CDT\9A\D6\C7\D0\B6\A2\BE\AA\806XK\1A$)*.&/!\0D?\83\A0\B4\C3\BC\B1\A3}XrjZ'0NH.)93' \1F\1E\12\1B\1B*/\1A0&!*@G>\1C#$(\1C\15\12\16\1A\1F\19.H\22\22p\0C=\DE\CE\C5\D2\BC>\00\0C\1B\08s\911\17\BF\D4\C5\B9\B6\8DnX:\8D\B2\86<.,\22\1E' \1B\109\85\A2\A7\90~r<^ik; /EF)#23\22$!#\07id\10\17\10\19&\11%?HD\1F(+0 \0E\0F\17\18\1E\1F/@&!\96\8C\7F\96q\BB\DB\A7ze\22\08\14\95fcQ$e\DC\C2\D1\8F\95\94\82J\8F\AC\A4}L\19\18.\12\14\14\1Bj\8E\AA\93WIQQ`W,7IH5'':#\1BP]\05X\B1\BC`\00,\19\1D\1C\22BLH$))3)\13\14\1A\19\1B\19'1E9\C7\CA\DB\88:|\D3\AD\C5\BD\B0j\A4\B9\8A\8C\C4\C9\A5\D1\D8\A7#\8D\AD\B2|?`ov~=\1B(\13\19\1C\0E}\A1\C8\C2aMIFA?4>JG022$&\1Ah\ACt\7F\AD\BC\8D >@A\1C\18<QS*$*:4'\19\16\17\18\11\19\1F67\9D\90\B5\DC\8C\AB\C6\8B\C6\C7\93\AA\D1\BD\C1\8EJ\8C\CB\92\B7\BFsE\96\AF\8ArU-gp\5C%\1A*\1F\1A\0Db\AF\C9\D8|8A>DB3OKGQ8#.4&A\B5\C9\AF\A8\B2\A5\83\8CtH:9<W]<3;GA1\1E\1A\1F$\1D\1D\19438v\C6\CC\DD\D6\CB\BB\BD\D0{\91\DD\DE\DAa\0B\C0\B3\AD\90\B5\E5\92`\94\87\95\A5\8D\9B\C0\B5@2\A9v\1C\053\CB\BB\C8\BD\82?6<'MYU_a?61,2\1D\8F\C9\B5\D3\CC\CB\BE\A2{J8IK]bRPTTK@9=;81+\1F61\16O\C6\A7\A8\B6\C2\B7\CE\D3ZC\82\BC\D4\B4\90\AC\B1\D2\9EPv|\9B\98\B8\AD\BE\B8\C5\CF\D5A9\A3\80.`W\C6\BB\AD\D4\C4\9Em<2MiNECGJ@</\16E\88\9B\C7\D6\D7\BD\A3\97nBEO^bglZ[RF<<740%!\22 r\09+?j\93\A8\A6\B2\D0Dpk\C5\A7\B4\BA\B4\8B\AFj\CC\82tx\98\96\8D\A0\97\A7\B9\BFA2t'2\80q\86\BE\C0\BA\C4\BD\C2a\0F0d\82c\22TOV<!\15\19Jw\AB\C3\D2\BD\AD\96x93=Q`r\80ncR<91%'\1E\16 \1E\1C`A4(5Yc\99\AC\C7H\88\CC\CC\CC\91\B5\B4hwM>\ADlf`?>1\5C\AE\A0\9E0L\AB[ip\A1\0CO\BA\B7\AA\AB\C5\BA<}\AC\C7\CBO-O[M\16\1A\1A\1AF\90\BC\B6{PJ72\22\1A1F`||oT4\1E!\19\10\11\22\22\1B\1C^;!\1BFHk\AF\91g9\C5\A9\C9\C2\A7m\AA\B1\85xR\9BqT>C*\08L\B4\B2\B5\1Ei\B8\A0\B6\BB\D2ot\AE\AE\9A\BA\CC\D0\CA\A3t\99\AB\892HHKU&\22!\1C\22QR:>Q_D+\03\14(Ho\83uP-!\22\1D \1C$'\1C\18m;\1E\0B\22&Ir%.J\A6k\1D\92\92\88\91\DA\A2\B5\C7\ADz?P** Y\A7\B4\A7\1Fg\D0\B2\C6\D1\EA\A4r\84\9B\94\BC\BE\B2\C6\C2\8C\AC\C0\9E\5CGT`RJ!>;\2218\188Tb]3\0A\0C\177]\82\80^+%# \22\1F(* \1Bu9\0B\13\11\13\15Q4+M4\15\14\16\BE\C7\A5\C5\BA\C9\C5\B1d7\1E\1Dl[?XVb(O\BC\C4\B6\C1\B6\B1TW|Bi\C3\A5\98\BE\A2\A9\A3|z[MOYYLUa<S?&\1C1PgY\1E!3FTz\82b1)+-\1D\1D)!\19\18jD\1B\1E#\1B\15\1D\22\1F_%3\1D\1D\90\E2\D1\CB\B7D\A3\B9\BF\96;?u6I9\8E\AB\1AL\9C\A2\C9\94\8A\C3\95{V\16t\AF\AE\AA\CB\8BSR\A7\9FMK:/{\80Y\80~jK\1A%\1D4V`A=OWHf{i:KCHF<' \15\154T\1B \1D\15\1C!\1C\1AX&\1FC*\13v\A5\9F\B5\9D\A1\C5\B4\83ys#}\AE\91\B5\BC\1Ax\C3\BA\BC\AE\9C\85\AC\B4\A9&t\A1\B6\BD\C1\AD]a\A9\A7T(6\15n\AB}\84\BB\A4O\18!\1A\121SNM|\A1\8B\92\95\81JQIZW\5CJ6\15\12\16[\22%\1B\1B\182*#`!\0B04\09\B4\E2\BC\D0\DD\95\98T:@I\83\AB\ACpg\85!\22W\1Cd\D9cv\B6\B3tGY\AA\BA\BF\94\BA\B7\89P\82J4-!A\96\9E\80\C3\B6y]X\0E\06\13%8d\9F\B3\D4\CD\C5\D3_'I:BAD@<36.'\1B9P4\1D%8LkR<+\1Ck\C0gcj|\8D\891L\22H}\98r\09,Ob\C6\AB\B4\D4\C5\BF\B2\C0\8Fh$W\D4\BD\C8\D2\BA\BF\8A\80\5CVA$\1Dw\BA\B7\BC\B7\AA\8CZ\15\03\00\07\1ACk\8C\B3\C2\9B\C7\AE&\14.5.,@33'+!\14&P)I IEk8VU+8^pNE\C1\8E\B6\96\15\05$Q\96h\1C6_\19[\FE\A7\F4Y\EC\AC\99\C0\E8\89\09W\C8\CE\E5\B7\E2\F0\C6xW-(\13\87\C8\CE\D3\AF\90>\08\00\1Cfl\5C\7F|\85n\AD\A7\A3\D6\AFRNE5\18(34\14#$!\03`!\9AtBCh\83IC/)6:Xr\9F\F3\C2\B1\D02\001!\0EF<;\1F\010\C0\BE<\FFp\91\C1{\11\B6\A4^\B5CU\C8\C3\CD\C5S 6[\AC\BF\B6\CB\9E=\00\04D\A2\CB\B0\B1\B3\A9n\A6\DE\C4\C1\BC\8E]V6\1A\1757?\19\0C\0E\1F`8\A9\95\89=+sqe1%\0AD\AC|\1A\A3\CF\EA\B9\86\DA\A0\C6\CD*$9\1A \1B3\F38\C1\B7\98E\0B\8F\BD\B8\C9\D4\D4f\C2\C9\9FCm\82U8FPSo\97\A2c40\1EY\BF\B6\B7\B2\AEt\88\9F\BE\CF\C1\9F\86Y\1F\18\17;>&2\12H\B1\93/\A1}\BF\954\1B9O5,U\95\A3ZV\A7\91\C5\E1Z\B1\CC\C7\83\00$5 \16\07\80\C5JT\B5jU$\12g\BA\D6\B0\E8\E0\BF\BD\ECR\92\9C\84\5CCROgw{^JTQ\0BL\9E\C9\B9iza||\91\BD\89\8FJ\1D\22&?@& \16!\CA\C27\B0\8A\BC\E2\D7\99\1Dr.\1A\A4\B6\AB\9C\86\D1\CF\BB\A2Jn\CD\8E\03\0D$8\19\18\0C&\AEZ\14\DB\81r\1A7\1E\027\00\C8\C5\C2\B1\BC\B0Eb\A2\8Bs-8\7F\95\99\87Oex]A\AF\C4\AC\A1\C3\5CKJ/;KH-!#\22AC$3A8,\8E\16}\5C\E6\CA\DA\C6U(6#\A1\E3\A1\22y\AFfP\15Z,\8F\DEz\02+4$\09?\BEwa\1B\9F\A3\E9{\17 \108@/?e\B1\A8\B74\8F\DE\BDrM\91\93\95\A9\81\84V\8A}k\AE\AB\8A\A2\BCd+72\1C4*)$\22\22CB\161i\8D>\80\D5\BC\9Cz\E8\CD\C3\94.5 k\D1\9E\1E\B7\E8\91\00jse\18\9A\90\A8F,\00:\B4\C1\8AU2}\90\CE\C4s\AA\88\05\C0%AKE\A5\9B\C8~\C4\E8\98\B1\8CY\88meib\9A\8EURafj\87\85%--% *\1E!$\18\19%\19\10\0B\1Dy\A3\A1\B7\C7\CC6w\FFw\D08)O\B4i-\BC\D3\95\04\96\AB}\AB\A6\90\82{;\CCnC\9B\EBX6\8Ae\B8\DE\97\98\9Bs\C6\B1\9C\93k@4\BA\99\D9\B3\FElK~\8D<e;lz~J3&=4\92\8C9\22#&\1B\1A!\22\1A\1D)%;\0F\1B#\1C\81\AA\BA\D7\E8\B8j\19s\C3@4-f\1A\22h\A30O\CD\9C\C7\AA\A2\C3\C0L\8B\D7\AD~\973f#\8B\ED\B4\C4\A9^!iXy\93e=*&\102\EB\D0m]s\B4\1FMZYI@1@/FTEMq-( !\1C\1B2-\18\1F'(\9F6\00\19\00\00[\AF\B6\CD\AF[\00\A6\EEA(\19\10c\02#@\04L8\F4\91\D1\BE\BF\E9\DF\B5\D3\E0x\0AOm;_\E6\C3\92\B4M n\A7[8-'\183)]swJ\DB\A9`\5CW@ &\17\1A Mgb8<020!$%>6\1D!'*\C1u\00\04\09\1A\00\84\D7\99\D2\00:\E1SG-#\0B+>\0Ci\1F.\0C^\EB\AC\B1\C3\DB\E3\B5\B4\E0\9AM2n58\C5\C1nV\1CD.\BC\AE\85 .\22)-\1FIma\8E\DB\CE\88rO)VB%0+L]Vg8Y57\22#&A=*<\15!\98S\0D\0B\02$\00\99\C6\DEC\06\96\B4\8B6:%\0D\1CF<\14\0EO\9A[\83\AD\89\A8o\D7\B9\A1\CF\D7\9DYGS@d\9Aa\01ou\1AN\A4[\11\14IVH\00U\82f\A6\FE\C3|\9B.2ZK2\1E#KYeQdBV2($'EB.L$ d'\0E\10\0C\1A-\E2\C5\FE\09!\E3\A7\85t-/\0D(I)*+v\8E\A9\DA\A1\D7\FE\E6\D6\C5\EE\EE\D8\A5dGL5\89\A9\0A\8DRzC\08\81a\22Jzc7)\96ki,\C1\BE\BC\BD=\14+5M8\0Am\AA\88qTU3($$/JL5D\22%\89h\12\0A\1C\19\18\00 \0E\1DW\90qc)I\22)!<;\11\1CL\83JT]H,\A3\BEHX\ED\B1\A7{Ug\11\A4\E4\A6\80@\816\0BI^bRNf\02\AAmq+.\06\BA\D3\B6D$\18%85\1ED\BF\CB\B3YC3+ \224DQ;/%'a+G\0E\1D\13#-\1F\22\09\A1\D9KU\0F[\1A2(;S\1A0\19\1C\22\06?F\15\93\C9\86m\C2\E3\BD\A0|\81<\A9\D4\D8\D2\A8\AB\8C\BD\00\99\81*?\17K\B4^L\22eoA\A2\B7\94j \15.&# q\B2\D9\99L.!#*6FP4\16\17,VN\1A9\08\1Ae\1E\18/\0F\A6<if\0DW\1F:\22!g\03\A3}#+\12J3\1B\F8\BE}\C5\EE\D9\D2\A0c\89\FF\B1\7F\FF\DC\DE\B9^kqGu\95\13\0B\9C\80-\1B\1E7\A8\85\9C\A6\AB\B3X\00\19\11\88\87\B8\A2\C0\B8\9B'\15!&9II>-+)?~\15.\12-T\1F0\1A*\15\09E*CJ-8+\16+/\87\9C\1A%\1A5^[K\9B\AA\B2\CB\9E\D2\B7f\03\E2\ED\FF;\0C\C6\EA7O&\A7\A0\E3\070\00\0A\10S8PM\C4\C9\96>ZQ\0E'>(n9N\BB\CC\C5\A89\0F\1F5DOZv$*G\7Ft\0D\1E\5C\9B\1C\16;#\18<B\07\00}O!(*? \19\0B;?OG\13\88\AF\BC>\FF\ED\85\0A\05\0DC;cZ\FF\AD\DCFqA\E0C\92<]<&\146S\8E\80\83\95\8B\B8\BEVbZ\08\15D\8B\85\D0\AA\B6\C7\A7\8B$--'X\82\8B+$iUY\91\14 PF\16\85}8:\1B\22\BA\DC\84\22) \0Eqs(6S\1A2\08Es\84:J\FA\8C\0A2\1A\13Z*B\F0\E7]\CF\EF\90\9B>\19\8B\84\7F^;@SaK\1F\9B\9F\A8\DBo\17(/$./\12)({\A0\B0{7.\1F\17,`nSle_\07]\80\11*\07\84\88\82Q0P\93\84\BCO!.<Bk\B6z$\92!\0A@-3\1Bf\0A\1F\8B\10\228\0B0:}\FF!w\DA\BC\DCj\0CAdIzIa,((\0A,l\5C\81\E0\00\A4`\13\1F)%&($Bk\B0\82 \17\1A\14#UJlea $\03ox\12 \98\E5\A5\BC\9FxiZ\AAP!\1DC?AKB3!8\14U\00\14#}U0\01\16(9\1889\08*\A1H\00\0F\95\18FgC\5CEJ\AA\1C\1C\0B\0B,3\0Ad\9D:\C6\AEW\1A!+\1C\1F\1A\197}}40('%LOef\97\1E\1C-\1C\95/##\FF\CD\BE\AE\F2bv\94`;\161\17_\0E\17\19\08\193\00\1A\00i\92f\00\0EX*f@\10\16145\153\8F\13=XdB=ZY\02*\1A\16\1B(/1<,Xy\8Dw4\1B$\11\04\13\18\07!B-5TV\131Fbh\B4\FFO\222\00\139y;\DA\CB\A5{\FB\AD\DF\86\90v?\16T\11@\D0\B3F\03\173\B3\A4r\00\91\D0\BE\A9(,$,%R<\06\0ER\B2\1Dl%\1Ep\5C:\12@?@OSLMHB!A]\99G]F;2),Z.)!-LM'9?\1C\0DS\98\CC\0Aiy\1D\13\90\D0\D5\E8GWh\DD\C0uH[d\1D7U\0D{\E9\C4\9B\0B\9D\82\9D\A0\00\D6\E5\B0\C1i*3&Qc~p:\09]\00]\1D\5CfD<\14<2EO/4 \19@a\08.Is\C4\82aUX}bZ@-9]K.,J\0E\06`S\90\0E\92\CF\DB\8D\A5\BC\C6\E9Uu\C5\C1\DE\95w693!M#\0A\97\E9\C4\BA\A9G\E5;7\B3\A3\DF\DB\B3\1842F@Zl>!!\1B:\13R\B6\B5\AC\1C(\1F \1D|N)2\22\14\0BP\A1\9A\B8\BC\83_\7FRwE;\12G{W,,B\06\0B\13+\1B \1D\80\CA\DF\DB\9F\8C\D5\EC\EA\A8\D4\92S44\17%\1A.:\CA\D1\C0\E3\BF\E1\FF\1D\1B\095\B8\AD\A4\034\0A>>Oo'/\10\13U1!t\FF\C7Xk\C1\DBjc\C0\90e\1D\15\141+e\D5\BC\CF\D1dcpS;$\05,uD*0:\0F\06*r(A\10\00\9C\C1\EE\D3\D9\D3\F2\C0\8A\C6\A6\18@0\077'\0Cs\A0\B5\C3\BAe\A0\CF\00\0F\00m\80\A4\AE\07!\9A`S\89\1E\13q\17\1FVP\B0\F6C\0C\00I\B1\92\F6Y\DF\D5\8A\0F7e4JS8\F3\D4\D5iv\99\99\89\8Cw}EJ\0AD\1D\22\0DgWAJM\85o\DA\C3\92\B9\D7\D7d\94\7F\DB\0D?&\10\10:\14\22M\8F\DA\D0\AC\A6\D7\CF\1F\00xf|\A7>\98_g\92\9A\0A\8C\9C\85K\B8\BAu\05\14V\CB\08\D6\A0\96\CB\A2\E8\AF\0C84H\9D\96\B6\C3\E4vJ\BD\CA\99Q:>IJH\0DG4\0E\0F)/V\8A\C5\BC\AF\91\D8i\9C\90\C3\B2\5Cb\9C\117\22\14\0A\08\1E)))`{\93\D2\BD\E1\DC\002\CB\B5\C1\DFYb\869\AE\BE\A2\A9>,Z1\18\17W\F6V\A5\C0\EA\D8\BF\C1\E8X ;D\85\B8\AA\B7\E9\FAr\0D\B2\C3\AD\A5l%\04WG\1C3H\0D\07e0\8C`\B1\D1\C2\C3\FB+^\E1\A3\D7\B7\1F\13#\1B \12\10<\130*}Z\94o\C6\BA\A2\AFE\00\F9\C9\D6\EF\A8\91\8FK\1E\DB\D0\BD\0C@1kd;:\E3|1\84~\AE\D6\00tq\0Et\8AX^t}Xr\FF\84\D0\D7\A0\00\09\00\1CRH\16(>\09\08j[\84_G\DD\DA\BB\C9\E6\EB\B1\DE\C0\85\14\15\18\1F\0C\17\00[!+:\BF^\A5:\AC\AA\89\00\84\AB\BE\C7F\8E\FC\C2\83\B4\EE\9C\D7\CF\03WpT\12\9F\DB\A2\9AcP\BC\22\C8\00\CB\C8jR\8Da??h\0E\14\DD\BD\DE\9C\EC$\00\02\19[U\17\1D+0|E\8DucZ\BA\13\98\DF\C9\AE\BC\A3\D2\00\14 \12!'%\16\0C%\22\98\B1\C9w.\86\80\97\B5\B5\C2\E8\A8H\06\AC\C2l}\8E\B3\AC\E1\82)9\03\9F\8C\BB\C9n\AFW>7\CF\E8\A8\A0n27Zj\8CA\13d\CE\CC\B8^\AD\FE:'\19Q8#!,zxtt`]\16OG\97\CA\E7\C7\DC\87\D1:\00\14+982\1C)&\1F1O\11?Q_\90:\8E\A4\C0\AF\D3_\C8\CF\CB\87\82\A0k*\C6\F3E\06/P}\F3\A2>\05\1F\04G\AE\9E\B9\A1emtt\89X\15d\12\89\F4F\1FL\D4yyY6&,1\1Ex{8%-aC\22\14\19\D7\C5KZ\C5\8Dq\1D+\1E\10$\09!\10\1A%\14\152B)\09\1Dlm\B6\A6\9F\96\EC\AA\AB\8Esg\1B+$#\D4x\089J$\FA\08\05\11\0B\1B-\96\9B\D9Pcm\8A\ABT\07B\1B1Fq'''t\DDCF7I@8<xw?\1D\11_o\00\1A\0F\1E\A8.a2\BCy\5C\0B\14\1A\18\15\0D\13\076\1A 030\189\03\12\FF\EC\B6\CB\92\E9\AB\95V\0B\02\E7\C8\00\B4\00)?;\1B\07\22)\03\12;#t\80\BF-Pi\AC\92 \87K05J#\22A=\1B_\12>DA5:>h\99B\04\09\04]:\05\0EItR \C9\88\8Bg\05\139\0D\13\16\0B\10/\13\0F=V\05\10D\0D:\F1\DE\FD\B7h\FA\CE\C3\80\0E\A0\9A\AF\0FG\22%Q\1D7\164\08\0C\17\09\1ECO[-?\92\88\08sz!9,-,\0C\18'v\05\96=4*,\227\95\98\10\1C\0D\03\04*\06\1AB\5Ci\89\DD\C2c{Z\05\1F\15\03\0A\18\0C\15\16!F\00\02,\09\11\11U\B3R\0C\14]\BC\B9S\1A\AE\82\D5\EDV\BA\84Vo\E1f\07\0B\0E\0F:Y\1B?\9B+cb\11jN0>1\1D\178\DA\AF\B8/^ ),*7.\22\98\96\19\0D\15\10\0F\06\0A\1BORS!b\9Bsj \1C\1A\11$\04\11\0B\0F~\E2o\BC\17\1D5(\1D\1DX\1E\D68\01\00\91\B6\A9\AA\AA\ADNP@\D4{=\93\DD\15\09\00T{(1W;>A\1F:mW \1B\1B#'zQ0\0F3\22'4).',3\90\96\22 \0A\03\0B\0B\01.QHi>F\05$\84w\07 \09\09\05\16\06)\C98\DD\FD\DE\03\0E\12\13W.\16\B2\F7'\0AU\D3\95\B1\CE\A2\9E\8B\CE\D1E#\C5\A1\B8\D4\B0\06/\1F!3\18)\1B>K?;WQP<='(\22#\1E\16\1A!\160'\19\223D\0A\0A\14\06\06\09\03\0A;4\B86G;\8EW\19\09\0C\1D+=\0D\01F\B9\D1v\EC\F5\FA\01\02S<\1C\111\A8\00\06\84lrI\DB\C3\CB\B2\CC\D5\8C\00\D3\AF\E8\D6\F5?&\19&\19\12\14DD\1D!\1E\226JjWa)\18\1A%\11VZA\1E1\1E(FHb\0D\13\12\12\08\09\07\03\08\8Cl\1A\09\03\00\0D\11\11%fA\0A\1F%(\FF\FF\D7\A7\F2\F8\B2\D1\AD\09G\B1\00\08\9A\03\C0\F17\E3\BF\98\D8\E3\B9\C7S\E7\CF\A9\E9\D8\8C\06/\1F\07+>@7#\1A\18\18\224\16,.LR' RfkV[2$%HI", [5310 x i8] c"\EC\DE\B4\96\A9\95\BB\D4\DC\AA\B3\BD\BE\F1\E2\C9\C1\BD\D8\E7\9E\93\0C\00\1F>CI\0D\22\09\00\00\03\180\1C\93\D3\9F\A9pey^K)\05 ?=%\1F\13\19\19\04\17\1B\07\05\0C\15'.2\1B\0A\00\15\14\00+'\1B\00\00\00\10\00\09\03\00\01\0D\09\0F\1C\16\0F\B9\CCkh\B9\8E\AF\FE\BCc\97\D5\DE\B2\A6\9A\DA\BC\B3\F4\DD\F5\BCaD>9,;W2\1E\0C\00\170.\99\CB\99\AE\AC\B6\DB\EA\99B0=B1\0F\153'\1C\08 \15\00\00\0A\19\22*4\1F\0E\00\02\14\0E.5*\00\00\00\0C\07\05\02\05\0B\12\0D\1F>\11\16\A8z\0F\C9\F7\DB\D4\D7\A3.\15\A2\A4\BA\DF\80\B6\F8\E7\F0\DE\C7\EC\CD\9CXxkBIWM \15 .8UbX\A6\B2\AD\BE\CE\937*=4\06\0C*;<A\0C\0D\06\00\00\11 3.&\1D\00\00\00\00\0FSC,\00\00\00\00\01\00\00\06\0D\12\0E\22?\13\16r\1F9\F9\ED\BD\E7\E0@\12\086'k\A6U6\D9\D9\E4\DB\CD\BB\A4wT\92\D1\A8S\5Cb\1C\1D*,7\1C\1CL\9C\A6\93\8A\8EHA0C\05\00\08\142EK\0A\00\00\00\00\0F#\91\8E'\13\00\00\00\00\00i_@\00\00\00\00\00\00\00\00\00\05\06\16&\1A\17\92\AE\94\C2\89\98\DC\D3v\8774,rg\8FwLh\FF\F2\FF\BF\B6\BA\AAM\BE\DC\DF\ADm\15(M+*6<u\8A\BA\B2p_srk\1F\0D\1D\1D\1A$,*\02\04\01$/\00]\B4\C9|\0C\0B\00\00\00\00OhV\03\00\00\00\00\00\00\00\00\00\00\09\132)\A2\E2\E7\89C\81\EB\CC\A0\D5\BCk\AD\BE\A2\AB\E3\FF\BB\F9\EA\E0K\A9\CC\E8\92gr\A8\9E\9A95T,%>@\A4\9D\E2\EEzYkxhdmI\1D\1B\0C\1AAI_%;\80Pg\BC\C1\7F\00\17\1A\05\00\00AC1\03\00\00\00\00\07\00\00\00\00\00\00\04(+e\88\AB\CE\8A\A2\C8\B3\8E\BF\89\9C\CF\B4\C3\B6`\AB\E6\AA\B2\CD\80k\AC\CE\A5\8AP;t\96U=9912)\86\A8\E1\F7\8BJYZhNPeURUBM:Q<K\C0\CD\B9\D2\CC\8A;[a\1E\00\0FV<\15\0B \11\07\17\10\00\00\04\0A\03\03\00+-\0Fw\C5\AF\C2\B6\A9\BF\94\D1zt\C2\BE\B8e*\BB\C3\D0\B1\BA\DA\B0\7F\8F\97\B8\C6\92\90\DE\A4RA\BB\A6D\1Fj\BA\CD\D7\CF\B2gPsOm{W4QU@YLT\1Fd\B9\CB\DD\E8\D3\97eW/\12#ge;\15,9.%\16\12\1A\19\17\0F\09\000.CX\B8\A2\C2\E8\EA\CF\FB\DCL>\9C\EE\FC\CC\90\C4\D0\E6\80QSc\9B\B0\D7\C1\A0\B9\A2\B6\C0*@\BB\94Vx$\B1\A4\B4\EC\D8\C6\85\09\00\22D&!(8C\0C\11\0A\00!m\8C\C0\DA\D2\B7\8Cq]8\1DSY\5CPFIQ*+$&%%$\19\17\07\08\84\164Pw\99\C1\D0\C4\DDM\81x\CB\C0\DE\CC\D9\B6\D4\89\FB\91k\8A\BD\C1\B2\BF\C6\B6\B0\AA',\8CTa\8ACq\A4\BA\D2\F1\EC\CC3\00\18LT9\0FG>\1D$\09\00\007j\9A\B7\CB\B8\8CXM'\1B1J[QBCQ:))#\19\1E\18\10\1D\08\0A{:\14Bb[u\C5\C7\C0(\A2\F9\CE\DE\BD\D1\D6\88\97uc\DB\8F\82\82_^Y\81\DC\C3\90\1F=\B8\86\7FOY\00>\AB\C4\D5\C1\A4r\0FW\8B\A3\A7B;g.'\00\00\00\0DT\A8\CF\B2i-\0F\00\0A\07--4=AAG9\1F\0B\11\0C\03\06\16\19\0C\10`N\1D6e@\80\D3\93z5\E0\C8\C1\D7\CB\8C\C4\B6\A4\9Ai\C9\A7sXHI*c\E2\E8\AF\1Dl\C4\BC\C2\9E\99is\B1\BA\B6\C6\AF\97\A2mHrzuNp \15)\00\00\0D8J{i6\1F\1D%\0F\00-+$);I@\1B\0B\01\04\02\07\03\0B\0D\10\0Ei]37:\03J\9E!P_\D2\83\00\93\BE\AE\B9\DD\D1\E5\FF\DD\9Bex-YP\94\D7\D5\A3/\86\E9\C8\E8\F2\F5\A0\82\A3\B4\AA\DE\DF\BD\8E\A3r\80\92\8DaJ\1CA8\1E\00-@%>T&\17\18'!\00\17(%\16!GD\1B\05\00\01\01\04\01\0A\0C\0D\0BPQ\17\14\1A\18-p\0FCY5\1E\19.\DD\E6\DB\DB\E2\DB\FE\D9\80VT3\94mx\80r^B{\D5\D0\D8\F3\DD\ADn\83\95N\8B\F5\CC\BD\F7\AD|wXbjr\88d, 1IKX1\04\00\0B\14 !#\13\11\1F.>;*\11\0A\0E\13\05\05\0E\06\0B\0C2<\11\10!\12\17E\00\17U\171\14\1F\B8\F8\F0\E6\CF?\B1\C6\E5\ACZZ\8D1WF\B4\A42k\AB\B4\E1\B0\AE\BC\AD\9Ae(\8C\CB\D2\B6\E8\A1]]\AB\A9wWWE\85\8B]\8A\A8\840\00\00\0A\0A\166[\22\07&5<;?\19+'-,\22\0D\05\0C\0F\0BU\1A\03\02\00\00%\00\1BW\09\04#\08\17\95\A0\AF\D8\BE\A6\BA\D2\A2t\83F\9E\B3\86\D3\AB,\87\D5\EA\E4\C8\D3t\BE\C3\BBV\9C\BB\ED\E5\E1\CF_6\99\BD^PV7p\80m\9A\C5\C0W\00\00\00\00\0B-jUUdgwo[ *&86:(\14\0F\0F\007(\08\0D\0D#\15\0B\00f\04\00\22?\00\C8\F8\D0\E7\B7\88\ABTNV]\9A\85\9F\83g_77\89G\81\FF\A2P\CC\C8\A6rv\D1\F9\EA\BE\D6\C3\877\92\5C_W=M\94\85\90\D5\D8\9D]P\00\18\18!Z\88\9F\AB\C5\DF\CA\CFD\06\22\11\19\18\17\0E!\12%\09D5AH_)\14\13i\85Z4V([\DA\89\8D\88|s~!fDr\9B\98X\00\0FXb\C0\AE\D7\EC\DE\A2\BB\C0\89kGo\ED\D9\C1\EE\D9\D0d\8Cvr:@<\88\94\C3\D6\BE\B6\97e\18\12\09\01!Ov\97\B6\D1\A5\C1\B2\1D\00\0B\0D\02\00\10\0C\0A\13\12. 8J7<\0C0RwJPc\1E+O\7F{X\BD\BA\DC\89\06\14Qd\92\94B\10Q$`\F9\BE\F3r\C6\9E\A4\C5\E3\A0\08p\F0\DD\F6\DF\F5\FC\B9m\7F<9;\9A\D4\C1\C8\C5\82?\1C\13(~\81rq}\99\82\B9\BF\B8\F5\BDH/\1D\06\00\00\0A\0B\00\1C4,&}D\97S;Ss\A6ff,-IFn{w\FF\C5\B5\E3>\14:\00!I\10 \1B\00\22\CB\B0D\DAU\8D\BCm\1C\A8\ACj\CC[\86\C6\EF\CC\CB_78gY\D8\BE\BC\F8\97G\12\19G\B6\C5\DD\AA\BD\BB\83\A9\F2\BE\B6\AAt><#\0B\0B\08\056.>@7l^\A0\8C\9Eo]\8B}\8B(\1C\1FJ\9E\90\1E\C7\FF\E1\CE\8C\CC\B4\CA\F1\5C\1A]E&\008\FFQ\B7\DB\C3K\00\94\D0\D1\DA\D6\E2|\BA\DC\9EJ~\84cN>cRv\91\8Bo:2\1Be\9B\B0\A0\BE\B4v\85\AB\9A\B4\A5\81kA\0A\00\00?5\04+\15f\C9\97E\A3[\B8\98R3=e7\11:\A0\A6r\88\D3\B4\AA\C6e\B4\E4\F9\AF E[4\0F\00\91\CF8u\DB~N\08#q\A8\D6\C9\D5\C6\AB\C0\C1G\92\B5qB/U$\5ChVMB<(\001\8F\A4\A8ab8ca^\8D^o1\06\07\06&\1D\04%\05+\E9\CB@\AEh\C1\D1\E1\B8&{,\00\80\88\8C\A1\A8\E6\E8\96~\1CO\D2\B0\18&9G;$\00<\B6d)\EA\A3~\03M&\0C\08\12\AA\B2\9E\9B\8E\C6\16w\84xO\17\0A\95\B8\95f7@L+\17\D2\C0\8B\89\9E0\19 \0E\18% \07\00\00\00\19\17\00)6B.\92;\84\1B\DC\BF\E4\C8YM=\00\97\A5\AEX\A1\D0t,\0B\1C9\C5\FF\9B\10\1F(>\00\00\DD\90\84\0F\93\BD\C9<693C(\14PUx\90\BA?w\C3\CEb\14y\96\A2\B2XXD\B1\7F9\BB\B4av\AA\8B-\05\13\00\04\00\00\00\00\00\15\12\00\0Dop0r\E0\9F}V\EE\B0\B5\869\184\81\E5\B5\00\AA\FB\91\12\80\87|\00\8D\A3\A8 B\12l\DF\DE\B1\94\0C\93\A5\FF\EF\90\D1\C70\EAAMI,\B5\AD\F3\A8\E0\F4\96\98\9Ck\AA\91eaS\AC\93Qt\85fbx\97*)\12\04\00\01\00\00\00\00\00\04\08\00(7\81\9B\CC\C3\B6\A7S\91\FFo\FBD\19i\D6\93K\BC\B9\8A\00\B0\CD\A7\C9\A6vw^D\CChF\BE\FFq\19\93e\B2\E1\BA\B0\B4\8F\BF\CD\BB\A4ELN\D6\92\F5\D2\FFFW\98\94HpFo\89\88D:2H?\95\9BC\1C'\1D\02\00\00\00\00\00\02\00'\00(/.{\B8\AD\C3\CF\C5v+m\D13'\1EuG5d\CFVB\BE\AB\F4\BD\9E\EF\E6&}\E2\B2y\AE2\7F\00}\F8\B9\BF\C0]:\91g\8A\BBxI\1D\1B8A\FC\F8\80if\A95?[m]LIUE8UYa}E=?/\12\00\0A\00\00\00\00\00~/\10$!\19~\AC\95\C6\BFf\1E\C3\FF>,,\1Cy\0B\00S\07PK\FF\A7\DA\96\D2\EC\B3\9A\CF\DBj\15Au\0FD\E2\BE\84\BF?(,\85\BF\8C6Y&\1E?@u\A4uv\DA\AF\8DUaR5)+\14MFqtM?D,%\0F\0A\06$#\0E\15\00\00\B8\8A06!&\22{\CE\AE\FF+R\EDy>$8\11\1DR\10\8DQ%!d\DD\C0\B5\E7\FF\D9\D9\DF\E6wRE\87+\5C\F0\C7K[/]?\BE\BC\9B\18A!0>!W\83Y\A1\DA\D5\82[[/X?1\0C%5i\5Ci5e\11\1C\06\05\0B)(\11\1E\19\18vL\10)\1A(\14\9B\A4\D7F$\AE\B8\A18\1F\0A\18\1F^n@14\7Ff\86\C5\BB\D4\92\F8\DF\B5\C8\BB\AEc5tfx\93E\12yc\1Ag\91A\00\17\1EKH\17BhR\A9\D3\B8mv\1D*B\22\19\03\14&H]9;);\00\00\00\07,+\13,\0B\00B,\00\1A+#6\E0\A3\FF\00+\FF\B0\8Er\08\0B\00\09NK?DQj{\BB\A6\F9\FF\FF\EB\D4\FF\FA\C1\BBlQaD\AB\B5\00\A3Z\84\14\1DcN\004Ly\08>xXE\16\93\D4\DF\B9\1C\00\06\09\1B\0E-i\89pL(#\09\07\01\00\07$$\06\10\00\00H^\07\14\1E\1D=\07\00\04\12a\92u\880%\18\00.rc2*(y\0Ca\93pM\B1\B2<r\CDr\C6\94x[\05\BE\C4g\9FY\A4A\00.oR\196i\0D\92R\82\1B\00\00\BD\E0\BF\1B\00\06L:\03+M\96\9F\A1\80E\01\0C\00\00\02\16&\12\08\00\001\096\00\0A\22%\1D\00\00\00~\C6ZW\002\00\0F-?=#O\00\00\00\0BC0\1E\B2\B1\90\92\D9\EE\D0\B8\9BiF\CE\EB\E3\E5\C0\CA\A5\C0\04\85b\096\01d\B7c8\03Df+\A3\E6\99G\13)<\04$Ov\8F\CC\ADZ\0C\04\00\00\0B\1E*\05\00\00\00P(\00\0F\00\00C\12\12\09\00|*MD\01:\00\17\14\0DR\00\B4`\00\08\046\1E\11\FF\C4v\D2\DD\CC\E5\99b\8F\FA\BEn\F2\EF\D7\B8fk\86C>w\00\05\A4\80B\17\00\19\86\7F\A0\AB\9C\94Z\1942\8C\8C\A9\83\C2\D4\B6H\07\00\00\00\0C\0F\00\00\00\005P\00\1D&\1E5,&\00\06\04\1D6\0BPP\07\17\11\01!(\96\A2\00\04\00 TTZ\92\A9\A8\B1\80\BD\B3h\00\E1\E3\EA\1D\00\C2\ECoS \9As\C4\00;2\0E\0AF\0B1(\CF\E5\9A43,\00\11QDr/'\96\B4\AF\BB;\00\00\07\17&&R\00\04Oc<\00,y\994\1E\1F\00\00J_\05\15v3\00\0C%7\0F\0A\04\1F\123B\0Bw\A0\CC:\FE\D2g\00\00\01S7b?\E4\A0\C3:~F\D9\0Fb\1A\5C;3\19/\1F^^\82\94s\B5\D1UMD\00\05,\88\98\CF\95\A0\AA\97x\00\06\05\06:O_\00\03oU>\83\04-8G\1C\85b**(\0A\BB\F8\8D\02\05*!v\8BD?3\00<\1BJ\8B\A4Ld\F6q\00\00\003lD>\D5\C3$\AA\F8\8A\84\0D\02xe>g5)\22J8\00Zn\8E\C6Z\00\15-\14\00\15\00\14\10h\9E\A0T\00\00\00\090XrE?f]\0C|\82\1A\13\04\85\86\87p2Y|\81\D4B\07\004ag\D9\92\17x\00\02_)V z&0v\00\00 \10DV\8E\EF\00K\C2\A3\B5V\0CBq;\A50:\18()\17\1E\97Ri\C2\0E\C2q*\1D\1F\0D\087BS\82\AEl\00\00\00\00\18DK8(p\05!\14\89\9D0.\A7\CA\A2\CD\B9\9D\87h\A9+\1D\10NtM^A\0E\1D+\1F\8A\0B'0ob4\05\22\1BH%*F\0C.\AD;\0F\0E\8A\0B8r}x~I\9F\0F\0E\16EHl\108o8\D2\B7n9'\00\00\1D&\22N\9C\A9>\1A\00\00\05\19%(,j\00?H5\9DV5\00\CD\F0\D9\C7\FA\89\88\973\1E\00\180\88*\1A\00\00\00\1A\17C\17\7F\9Bs\14%nA\95V\19#GKK,b\91\11/@\80bTe[\00\1C\022;?:,\0D\1Bd}\8CyR\16\00\00\10\17\17\09?I\18\0D\18,\00\00\10!7\84\E1>\00\1F\0E\15)I\19\C9\A8\92\8A\FD\9D\B6bm{C\00]0\17\AC\90K\07\01<\D2\8C|!\A8\DB\D1\C1G\14.Q<]O\1E-k\B5\22X\06\00gFS\15E+!.J6NwG\004q\A7%^u@\0F\1C@h\0C\0C\00\01!%\01\0A\1E\00\00Mr\A8\00W]\00\07\8A\AA\B1\BE5;F\D1\A3=%MP\08-f\00C\C6\B6\87\00\93\93\A3\99\0C\C5\D8\C3\BAh0,3@V\91i9\11]\15Y\00>D>D\14Q.\0E1\0D.$\1E1B\0AJd\94\C8\87R6Z\99}{2\00\05 \0E\00\00\19\00\00V%l\00\A6\C0\BC\9A\9B\8E\A2\D8if\A6\CE\E4oV\1C$)\1A\5C)\00v\CF\AF\B0\A2V\DC:-\99\85\CA\D7\B5\0F3(,\22Eh@Y%\15-\003\91\C0\E4 \22\12\00\00WYE6\18\00\008\8B\AD\D4\C0y8Z:aX=\00#M*\03\00\1E\00\00\1B\0F\00\00+\9D\C8\F7\E3\83T\B4\FA\FF\A6\EC\8B7\07\18\12\1D\09\1F3\AE\A4\A4\DE\B7\D0\F2-\17\08\1A\9A\A0\8B\00D\06=#1b\0E#\1D\18N\00\00R\FF\C6ep\BA\A7:A\BF\8FM\1A(\13\1C\15H\C5\A4\CC\E4cNZ6+\11\00\05M#\0C\00\0E\00\000r\0D3\00\0B\84\C2\F4\D3\BE\C5\E2\CDr\C7\C2! \0C\11J,$\8F\A9\95\9F\C4x\A5\E7 !\17ie\80u\00A\ACzOn\00\00L \19?\1F\99\E3$\00\09C\9Aa\DFF\C0\94Y\00\22P\1C7Q(\C2\BA\C0T^\86\97ye@K\1B<\0E<!\14\00hUFiO\8EX\D7\C4\90\BE\F6\D9m}|\F3\00%\00\08/67:@u\A5\C8\CB\A2\FA\D43\1B\89QG{&\9Ds\83\A3\85\00`\84l$\A4\BAv\12\06\81\B2\00\C2\A0\97\D8\94\FF\A5\00\1ACf\AE\AD\B4\B9\CCXY\DB\DB\B0O$\0E\10\0C%\0265\00\008\14S\9B\DF\E1\CD\9F\E7N\99\A1\DD\D7zp\9B\003\15\1F?\141(\04%S\86\C8\DE\D0\EE\CE\0C6\CF\C1\B4\EEfT\93=\B2\CA\95\B8=!M##Qs\FFU\9A\B3\DC\E3\F9\DD\FF^\00\0DB\91\C1\C1\D6\EF\CED\0B\BE\CC\C4\C4\98/\00&\1F\00\00\1E\00\008\00\AF{\CA\D9\E9\D5\CE\00\81\FC\BC\DF\DE1\16\00\00\05\00)e/3\00`?{\88\EF\D6\B8\B8R\14\FF\DF\ED\FF\BE\9A\9Ca5\F1\E7\EC\0E>#S\80[Q\EE~/vf\CA\F6\15\7Fl\00c\96\5C]v\9BSC\F1\90\D4\D6\A2\19\10\00\00\16\1E\00\00\08\00\002$vod\EF\FF\A3\91\AF\DD\C1\FB\D2\B0\00\00\04\05\00\0E8V.\16&\A5G\9Cu\A7\B7\A2\07\97\8D\C9\E9X\A6\FF\CA\96\96\F9\BE\E9\E7\00Luj7\9B\F1\BE\94XU\D2G\C4\14\E7\E1=*]JeW\7F'\00\B5\8D\C7\C2\FF;\00\00\006\1F\00\00\000_\1Ca\5Cr\82\BC)\AD\B6\9D\95\CB\CB\D4\14)\05\02\17\16\0D(\00-\07\88\A7\B8_@y\88\A4\C9\CD\B2\ED\B1T\1B\B9\D6\84m\93\BC\B8\F6\8B%5\0A\B1{\C7\E1w\ABSEI\BE\F4\C0\C4Z\19\0F:l\7F,7P\B5\A4\98`\A0\E9$\00\00 \00\00\00\00VSlfAJ .9\B8\C2\D9\A8\C9\91\B0,\1E\06\1A(%\18\13\1D\11\11 >\00%HS{-\9D\B6\BB\B3\CEo\E6\C2\DA\99}\A4f:\E4\F25\00$So\FF\D0=\00\07\00J\A0\B7\E7\A3OMPPpA\00f\00i\D0\22\065\B3^H+\16\03\0C\1B\09B;\1B\22%]`2\17(\BA\C2CV\E2\9Dt,!\0D\00\12\00\06\0B\00\1B\03\00 )\0E\04\00Ke\B9\A2\A6\A1\FF\D7\8A\86vc\226:P\FF\96\0A>D\00\E4\009/\0D 'o\85\CE&@El\89/\00+\00\0E\1ES\05\02\16]\BE\0F\12\09\0F\00\00\00;70\1B\0CTs\12\0F\00\0F\A6)V6\D1n0\00\03\09\11\00\00\14\00\1F\09\0F)\19\08\190\00\00\FA\E3\C3\EC\A0\FF\98}O\02\0F\FF\D6)\E6\1E3XE\03\00\0F[%\1CT-\5Ch\AC\008I\95u\00g'\00\1D*\0C\05\10\1D\00M\00\16 \10\00\04\05RiO\00\00\00Zc\1C\0DVmC\15\C6\B1\A2f\00\02\17\05\04\03\0F\12\1E\02\005G\00\14F\14)\E5\D5\FF\DFc\FF\D5\B2t\05\AB\C2\AA(pD1z6/\00\1B1.#27;8B\00+wt\00BR\00\05\18\12\18\00\00\00R\00W\03\08\00\00\00\0B`g\17\0E\05\06\01H\03\0AINa\8C\DA\E0`kS\00\00\04\00\13\13\0E\0E\05\005\00\0B'\0B \0B@\AC],\10s\CB\B3>\13\B9\A2\D1\FF~\DA\8F\86\8C\E0N\003.\1Ajv\1A'\80\00EF\00T(\09 \00\00\00\1F\C4\89\91\11;\00\00\00\00\00\00\00ZR\15\0A\13\0E\08*\14'KOQ\1F[\BF}v\10\0E\00\04\18\0C\00\19\00p\B1b\B0\1F\0BC,\18\00U)\EFB\22\04\8C\93\A6\B5\C3\B7ox`\DC\A8U\92\C5\001\1F\5C\A8@0?!\05#\04\1DU1\00\00\00\05\0C]9\0A\00\0F\00\00\00\00\00\00\00\00PU\00\00\00\13(\1D,\16\19\11[Nc\17Olb\00\06\00\00@\11\13\14\B5\1E\C6\F4\FF\00\1B+\1Bj\10!\D4\FF?#]\E6w\BC\F0\B4\B6\85\C3\D6[H\C1\B7\D4\CE\A5\0BED\1DI4B\00\16\1B(aohi\0F\15\00\11H;5\16\00\00\00\00\00\00\003'\00\00\00\15.\0B\19\1F\12\08\9FEo=\A4l\00\00\02\0C\13O\00\09+\A9\C7e\D4\FF\ED\09\0FgT\0C\16:\B4\13\13\98\84bN\E4\CF\E0\BB\C8\D1\93\10\C2\BB\FF\DF\F1;-+\15%*80+\00\01 \15!nV>9\09\1A\0D\10\00&%\10\00\00\00\00\22#Z\00\00\00\1C\00\00(\00\00mY$\00\00\1F\00\00\00\12L8\00\0A\17\17\F3\EF\BD\9E\E6\E3\A5\E0\BF\04K\AC\10&\8D\12\D2\EC;\DE\CF\B6\D7\D3\A1\BCV\D9\E8\D7\E8\C8t\002\11 Y@*\17\00\00\00\01\016\00\0C\0A(9\10\0075=68\12\0E\10\12\09"], align 1
ram_two_ports hana_bmp (
.clk( clk ),
.address_a( hana_bmp_address_a ),
.wren_a( hana_bmp_write_enable_a ),
.data_a( hana_bmp_in_a ),
.address_b( hana_bmp_address_b ),
.wren_b( hana_bmp_write_enable_b ),
.data_b( hana_bmp_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( hana_bmp_out_a ),
.q_b( hana_bmp_out_b)
);
defparam hana_bmp.width_a = 8;
defparam hana_bmp.widthad_a = 14;
defparam hana_bmp.width_b = 8;
defparam hana_bmp.widthad_b = 14;
defparam hana_bmp.width_be_a = 1;
defparam hana_bmp.width_be_b = 1;
defparam hana_bmp.numwords_a = 15930;
defparam hana_bmp.numwords_b = 15930;
defparam hana_bmp.init_file = "hana_bmp.mif";
reg [3:0] out_unread_marker_address_a;
reg out_unread_marker_write_enable_a;
reg [31:0] out_unread_marker_in_a;
wire [31:0] out_unread_marker_out_a;
reg [3:0] out_unread_marker_address_b;
reg out_unread_marker_write_enable_b;
reg [31:0] out_unread_marker_in_b;
wire [31:0] out_unread_marker_out_b;
// @out_unread_marker = internal unnamed_addr constant [10 x i32] [i32 216, i32 224, i32 219, i32 219, i32 192, i32 196, i32 196, i32 196, i32 196, i32 218], align 4
ram_two_ports out_unread_marker (
.clk( clk ),
.address_a( out_unread_marker_address_a ),
.wren_a( out_unread_marker_write_enable_a ),
.data_a( out_unread_marker_in_a ),
.address_b( out_unread_marker_address_b ),
.wren_b( out_unread_marker_write_enable_b ),
.data_b( out_unread_marker_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_unread_marker_out_a ),
.q_b( out_unread_marker_out_b)
);
defparam out_unread_marker.width_a = 32;
defparam out_unread_marker.widthad_a = 4;
defparam out_unread_marker.width_b = 32;
defparam out_unread_marker.widthad_b = 4;
defparam out_unread_marker.width_be_a = 1;
defparam out_unread_marker.width_be_b = 1;
defparam out_unread_marker.numwords_a = 10;
defparam out_unread_marker.numwords_b = 10;
defparam out_unread_marker.init_file = "out_unread_marker.mif";
reg [1:0] out_index_get_sof_address_a;
reg out_index_get_sof_write_enable_a;
reg [31:0] out_index_get_sof_in_a;
wire [31:0] out_index_get_sof_out_a;
reg [1:0] out_index_get_sof_address_b;
reg out_index_get_sof_write_enable_b;
reg [31:0] out_index_get_sof_in_b;
wire [31:0] out_index_get_sof_out_b;
// @out_index_get_sof = internal unnamed_addr constant [3 x i32] [i32 0, i32 1, i32 2], align 4
ram_two_ports out_index_get_sof (
.clk( clk ),
.address_a( out_index_get_sof_address_a ),
.wren_a( out_index_get_sof_write_enable_a ),
.data_a( out_index_get_sof_in_a ),
.address_b( out_index_get_sof_address_b ),
.wren_b( out_index_get_sof_write_enable_b ),
.data_b( out_index_get_sof_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_index_get_sof_out_a ),
.q_b( out_index_get_sof_out_b)
);
defparam out_index_get_sof.width_a = 32;
defparam out_index_get_sof.widthad_a = 2;
defparam out_index_get_sof.width_b = 32;
defparam out_index_get_sof.widthad_b = 2;
defparam out_index_get_sof.width_be_a = 1;
defparam out_index_get_sof.width_be_b = 1;
defparam out_index_get_sof.numwords_a = 3;
defparam out_index_get_sof.numwords_b = 3;
defparam out_index_get_sof.init_file = "out_index_get_sof.mif";
reg [1:0] out_v_samp_factor_get_sof_address_a;
reg out_v_samp_factor_get_sof_write_enable_a;
reg [31:0] out_v_samp_factor_get_sof_in_a;
wire [31:0] out_v_samp_factor_get_sof_out_a;
reg [1:0] out_v_samp_factor_get_sof_address_b;
reg out_v_samp_factor_get_sof_write_enable_b;
reg [31:0] out_v_samp_factor_get_sof_in_b;
wire [31:0] out_v_samp_factor_get_sof_out_b;
// @out_v_samp_factor_get_sof = internal unnamed_addr constant [3 x i32] [i32 2, i32 1, i32 1], align 4
ram_two_ports out_v_samp_factor_get_sof (
.clk( clk ),
.address_a( out_v_samp_factor_get_sof_address_a ),
.wren_a( out_v_samp_factor_get_sof_write_enable_a ),
.data_a( out_v_samp_factor_get_sof_in_a ),
.address_b( out_v_samp_factor_get_sof_address_b ),
.wren_b( out_v_samp_factor_get_sof_write_enable_b ),
.data_b( out_v_samp_factor_get_sof_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_v_samp_factor_get_sof_out_a ),
.q_b( out_v_samp_factor_get_sof_out_b)
);
defparam out_v_samp_factor_get_sof.width_a = 32;
defparam out_v_samp_factor_get_sof.widthad_a = 2;
defparam out_v_samp_factor_get_sof.width_b = 32;
defparam out_v_samp_factor_get_sof.widthad_b = 2;
defparam out_v_samp_factor_get_sof.width_be_a = 1;
defparam out_v_samp_factor_get_sof.width_be_b = 1;
defparam out_v_samp_factor_get_sof.numwords_a = 3;
defparam out_v_samp_factor_get_sof.numwords_b = 3;
defparam out_v_samp_factor_get_sof.init_file = "out_v_samp_factor_get_sof.mif";
reg [1:0] out_comp_id_get_sos_address_a;
reg out_comp_id_get_sos_write_enable_a;
reg [31:0] out_comp_id_get_sos_in_a;
wire [31:0] out_comp_id_get_sos_out_a;
reg [1:0] out_comp_id_get_sos_address_b;
reg out_comp_id_get_sos_write_enable_b;
reg [31:0] out_comp_id_get_sos_in_b;
wire [31:0] out_comp_id_get_sos_out_b;
// @out_comp_id_get_sos = internal unnamed_addr constant [3 x i32] [i32 1, i32 2, i32 3], align 4
ram_two_ports out_comp_id_get_sos (
.clk( clk ),
.address_a( out_comp_id_get_sos_address_a ),
.wren_a( out_comp_id_get_sos_write_enable_a ),
.data_a( out_comp_id_get_sos_in_a ),
.address_b( out_comp_id_get_sos_address_b ),
.wren_b( out_comp_id_get_sos_write_enable_b ),
.data_b( out_comp_id_get_sos_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_comp_id_get_sos_out_a ),
.q_b( out_comp_id_get_sos_out_b)
);
defparam out_comp_id_get_sos.width_a = 32;
defparam out_comp_id_get_sos.widthad_a = 2;
defparam out_comp_id_get_sos.width_b = 32;
defparam out_comp_id_get_sos.widthad_b = 2;
defparam out_comp_id_get_sos.width_be_a = 1;
defparam out_comp_id_get_sos.width_be_b = 1;
defparam out_comp_id_get_sos.numwords_a = 3;
defparam out_comp_id_get_sos.numwords_b = 3;
defparam out_comp_id_get_sos.init_file = "out_comp_id_get_sos.mif";
reg [1:0] out_ac_tbl_no_get_sos_address_a;
reg out_ac_tbl_no_get_sos_write_enable_a;
reg [31:0] out_ac_tbl_no_get_sos_in_a;
wire [31:0] out_ac_tbl_no_get_sos_out_a;
reg [1:0] out_ac_tbl_no_get_sos_address_b;
reg out_ac_tbl_no_get_sos_write_enable_b;
reg [31:0] out_ac_tbl_no_get_sos_in_b;
wire [31:0] out_ac_tbl_no_get_sos_out_b;
// @out_ac_tbl_no_get_sos = internal unnamed_addr constant [3 x i32] [i32 0, i32 1, i32 1], align 4
ram_two_ports out_ac_tbl_no_get_sos (
.clk( clk ),
.address_a( out_ac_tbl_no_get_sos_address_a ),
.wren_a( out_ac_tbl_no_get_sos_write_enable_a ),
.data_a( out_ac_tbl_no_get_sos_in_a ),
.address_b( out_ac_tbl_no_get_sos_address_b ),
.wren_b( out_ac_tbl_no_get_sos_write_enable_b ),
.data_b( out_ac_tbl_no_get_sos_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_ac_tbl_no_get_sos_out_a ),
.q_b( out_ac_tbl_no_get_sos_out_b)
);
defparam out_ac_tbl_no_get_sos.width_a = 32;
defparam out_ac_tbl_no_get_sos.widthad_a = 2;
defparam out_ac_tbl_no_get_sos.width_b = 32;
defparam out_ac_tbl_no_get_sos.widthad_b = 2;
defparam out_ac_tbl_no_get_sos.width_be_a = 1;
defparam out_ac_tbl_no_get_sos.width_be_b = 1;
defparam out_ac_tbl_no_get_sos.numwords_a = 3;
defparam out_ac_tbl_no_get_sos.numwords_b = 3;
defparam out_ac_tbl_no_get_sos.init_file = "out_ac_tbl_no_get_sos.mif";
reg [1:0] out_length_get_dht_address_a;
reg out_length_get_dht_write_enable_a;
reg [31:0] out_length_get_dht_in_a;
wire [31:0] out_length_get_dht_out_a;
reg [1:0] out_length_get_dht_address_b;
reg out_length_get_dht_write_enable_b;
reg [31:0] out_length_get_dht_in_b;
wire [31:0] out_length_get_dht_out_b;
// @out_length_get_dht = internal unnamed_addr constant [4 x i32] [i32 29, i32 179, i32 29, i32 179], align 4
ram_two_ports out_length_get_dht (
.clk( clk ),
.address_a( out_length_get_dht_address_a ),
.wren_a( out_length_get_dht_write_enable_a ),
.data_a( out_length_get_dht_in_a ),
.address_b( out_length_get_dht_address_b ),
.wren_b( out_length_get_dht_write_enable_b ),
.data_b( out_length_get_dht_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_length_get_dht_out_a ),
.q_b( out_length_get_dht_out_b)
);
defparam out_length_get_dht.width_a = 32;
defparam out_length_get_dht.widthad_a = 2;
defparam out_length_get_dht.width_b = 32;
defparam out_length_get_dht.widthad_b = 2;
defparam out_length_get_dht.width_be_a = 1;
defparam out_length_get_dht.width_be_b = 1;
defparam out_length_get_dht.numwords_a = 4;
defparam out_length_get_dht.numwords_b = 4;
defparam out_length_get_dht.init_file = "out_length_get_dht.mif";
reg [1:0] out_index_get_dht_address_a;
reg out_index_get_dht_write_enable_a;
reg [31:0] out_index_get_dht_in_a;
wire [31:0] out_index_get_dht_out_a;
reg [1:0] out_index_get_dht_address_b;
reg out_index_get_dht_write_enable_b;
reg [31:0] out_index_get_dht_in_b;
wire [31:0] out_index_get_dht_out_b;
// @out_index_get_dht = internal unnamed_addr constant [4 x i32] [i32 0, i32 16, i32 1, i32 17], align 4
ram_two_ports out_index_get_dht (
.clk( clk ),
.address_a( out_index_get_dht_address_a ),
.wren_a( out_index_get_dht_write_enable_a ),
.data_a( out_index_get_dht_in_a ),
.address_b( out_index_get_dht_address_b ),
.wren_b( out_index_get_dht_write_enable_b ),
.data_b( out_index_get_dht_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_index_get_dht_out_a ),
.q_b( out_index_get_dht_out_b)
);
defparam out_index_get_dht.width_a = 32;
defparam out_index_get_dht.widthad_a = 2;
defparam out_index_get_dht.width_b = 32;
defparam out_index_get_dht.widthad_b = 2;
defparam out_index_get_dht.width_be_a = 1;
defparam out_index_get_dht.width_be_b = 1;
defparam out_index_get_dht.numwords_a = 4;
defparam out_index_get_dht.numwords_b = 4;
defparam out_index_get_dht.init_file = "out_index_get_dht.mif";
reg [1:0] out_count_get_dht_address_a;
reg out_count_get_dht_write_enable_a;
reg [31:0] out_count_get_dht_in_a;
wire [31:0] out_count_get_dht_out_a;
reg [1:0] out_count_get_dht_address_b;
reg out_count_get_dht_write_enable_b;
reg [31:0] out_count_get_dht_in_b;
wire [31:0] out_count_get_dht_out_b;
// @out_count_get_dht = internal unnamed_addr constant [4 x i32] [i32 12, i32 162, i32 12, i32 162], align 4
ram_two_ports out_count_get_dht (
.clk( clk ),
.address_a( out_count_get_dht_address_a ),
.wren_a( out_count_get_dht_write_enable_a ),
.data_a( out_count_get_dht_in_a ),
.address_b( out_count_get_dht_address_b ),
.wren_b( out_count_get_dht_write_enable_b ),
.data_b( out_count_get_dht_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_count_get_dht_out_a ),
.q_b( out_count_get_dht_out_b)
);
defparam out_count_get_dht.width_a = 32;
defparam out_count_get_dht.widthad_a = 2;
defparam out_count_get_dht.width_b = 32;
defparam out_count_get_dht.widthad_b = 2;
defparam out_count_get_dht.width_be_a = 1;
defparam out_count_get_dht.width_be_b = 1;
defparam out_count_get_dht.numwords_a = 4;
defparam out_count_get_dht.numwords_b = 4;
defparam out_count_get_dht.init_file = "out_count_get_dht.mif";
reg [0:0] out_length_get_dqt_address_a;
reg out_length_get_dqt_write_enable_a;
reg [31:0] out_length_get_dqt_in_a;
wire [31:0] out_length_get_dqt_out_a;
reg [0:0] out_length_get_dqt_address_b;
reg out_length_get_dqt_write_enable_b;
reg [31:0] out_length_get_dqt_in_b;
wire [31:0] out_length_get_dqt_out_b;
// @out_length_get_dqt = internal unnamed_addr constant [2 x i32] [i32 65, i32 65], align 4
ram_two_ports out_length_get_dqt (
.clk( clk ),
.address_a( out_length_get_dqt_address_a ),
.wren_a( out_length_get_dqt_write_enable_a ),
.data_a( out_length_get_dqt_in_a ),
.address_b( out_length_get_dqt_address_b ),
.wren_b( out_length_get_dqt_write_enable_b ),
.data_b( out_length_get_dqt_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_length_get_dqt_out_a ),
.q_b( out_length_get_dqt_out_b)
);
defparam out_length_get_dqt.width_a = 32;
defparam out_length_get_dqt.widthad_a = 1;
defparam out_length_get_dqt.width_b = 32;
defparam out_length_get_dqt.widthad_b = 1;
defparam out_length_get_dqt.width_be_a = 1;
defparam out_length_get_dqt.width_be_b = 1;
defparam out_length_get_dqt.numwords_a = 2;
defparam out_length_get_dqt.numwords_b = 2;
defparam out_length_get_dqt.init_file = "out_length_get_dqt.mif";
reg [0:0] out_prec_get_dht_address_a;
reg out_prec_get_dht_write_enable_a;
reg [31:0] out_prec_get_dht_in_a;
wire [31:0] out_prec_get_dht_out_a;
reg [0:0] out_prec_get_dht_address_b;
reg out_prec_get_dht_write_enable_b;
reg [31:0] out_prec_get_dht_in_b;
wire [31:0] out_prec_get_dht_out_b;
// @out_prec_get_dht = internal unnamed_addr constant [2 x i32] zeroinitializer, align 4
ram_two_ports out_prec_get_dht (
.clk( clk ),
.address_a( out_prec_get_dht_address_a ),
.wren_a( out_prec_get_dht_write_enable_a ),
.data_a( out_prec_get_dht_in_a ),
.address_b( out_prec_get_dht_address_b ),
.wren_b( out_prec_get_dht_write_enable_b ),
.data_b( out_prec_get_dht_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_prec_get_dht_out_a ),
.q_b( out_prec_get_dht_out_b)
);
defparam out_prec_get_dht.width_a = 32;
defparam out_prec_get_dht.widthad_a = 1;
defparam out_prec_get_dht.width_b = 32;
defparam out_prec_get_dht.widthad_b = 1;
defparam out_prec_get_dht.width_be_a = 1;
defparam out_prec_get_dht.width_be_b = 1;
defparam out_prec_get_dht.numwords_a = 2;
defparam out_prec_get_dht.numwords_b = 2;
defparam out_prec_get_dht.init_file = "out_prec_get_dht.mif";
reg [0:0] out_num_get_dht_address_a;
reg out_num_get_dht_write_enable_a;
reg [31:0] out_num_get_dht_in_a;
wire [31:0] out_num_get_dht_out_a;
reg [0:0] out_num_get_dht_address_b;
reg out_num_get_dht_write_enable_b;
reg [31:0] out_num_get_dht_in_b;
wire [31:0] out_num_get_dht_out_b;
// @out_num_get_dht = internal unnamed_addr constant [2 x i32] [i32 0, i32 1], align 4
ram_two_ports out_num_get_dht (
.clk( clk ),
.address_a( out_num_get_dht_address_a ),
.wren_a( out_num_get_dht_write_enable_a ),
.data_a( out_num_get_dht_in_a ),
.address_b( out_num_get_dht_address_b ),
.wren_b( out_num_get_dht_write_enable_b ),
.data_b( out_num_get_dht_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( out_num_get_dht_out_a ),
.q_b( out_num_get_dht_out_b)
);
defparam out_num_get_dht.width_a = 32;
defparam out_num_get_dht.widthad_a = 1;
defparam out_num_get_dht.width_b = 32;
defparam out_num_get_dht.widthad_b = 1;
defparam out_num_get_dht.width_be_a = 1;
defparam out_num_get_dht.width_be_b = 1;
defparam out_num_get_dht.numwords_a = 2;
defparam out_num_get_dht.numwords_b = 2;
defparam out_num_get_dht.init_file = "out_num_get_dht.mif";
reg [5:0] izigzag_index_address_a;
reg izigzag_index_write_enable_a;
reg [31:0] izigzag_index_in_a;
wire [31:0] izigzag_index_out_a;
reg [5:0] izigzag_index_address_b;
reg izigzag_index_write_enable_b;
reg [31:0] izigzag_index_in_b;
wire [31:0] izigzag_index_out_b;
// @izigzag_index = internal unnamed_addr constant [64 x i32] [i32 0, i32 1, i32 8, i32 16, i32 9, i32 2, i32 3, i32 10, i32 17, i32 24, i32 32, i32 25, i32 18, i32 11, i32 4, i32 5, i32 12, i32 19, i32 26, i32 33, i32 40, i32 48, i32 41, i32 34, i32 27, i32 20, i32 13, i32 6, i32 7, i32 14, i32 21, i32 28, i32 35, i32 42, i32 49, i32 56, i32 57, i32 50, i32 43, i32 36, i32 29, i32 22, i32 15, i32 23, i32 30, i32 37, i32 44, i32 51, i32 58, i32 59, i32 52, i32 45, i32 38, i32 31, i32 39, i32 46, i32 53, i32 60, i32 61, i32 54, i32 47, i32 55, i32 62, i32 63], align 4
ram_two_ports izigzag_index (
.clk( clk ),
.address_a( izigzag_index_address_a ),
.wren_a( izigzag_index_write_enable_a ),
.data_a( izigzag_index_in_a ),
.address_b( izigzag_index_address_b ),
.wren_b( izigzag_index_write_enable_b ),
.data_b( izigzag_index_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( izigzag_index_out_a ),
.q_b( izigzag_index_out_b)
);
defparam izigzag_index.width_a = 32;
defparam izigzag_index.widthad_a = 6;
defparam izigzag_index.width_b = 32;
defparam izigzag_index.widthad_b = 6;
defparam izigzag_index.width_be_a = 1;
defparam izigzag_index.width_be_b = 1;
defparam izigzag_index.numwords_a = 64;
defparam izigzag_index.numwords_b = 64;
defparam izigzag_index.init_file = "izigzag_index.mif";
reg [0:0] main_result_address_a;
reg main_result_write_enable_a;
reg [31:0] main_result_in_a;
wire [31:0] main_result_out_a;
reg [0:0] main_result_address_b;
reg main_result_write_enable_b;
reg [31:0] main_result_in_b;
wire [31:0] main_result_out_b;
// @main_result = internal unnamed_addr global i32 0, align 4
ram_two_ports main_result (
.clk( clk ),
.address_a( main_result_address_a ),
.wren_a( main_result_write_enable_a ),
.data_a( main_result_in_a ),
.address_b( main_result_address_b ),
.wren_b( main_result_write_enable_b ),
.data_b( main_result_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( main_result_out_a ),
.q_b( main_result_out_b)
);
defparam main_result.width_a = 32;
defparam main_result.widthad_a = 1;
defparam main_result.width_b = 32;
defparam main_result.widthad_b = 1;
defparam main_result.width_be_a = 1;
defparam main_result.width_be_b = 1;
defparam main_result.numwords_a = 1;
defparam main_result.numwords_b = 1;
defparam main_result.init_file = "main_result.mif";
reg [0:0] p_jinfo_image_height_address_a;
reg p_jinfo_image_height_write_enable_a;
reg [15:0] p_jinfo_image_height_in_a;
wire [15:0] p_jinfo_image_height_out_a;
reg [0:0] p_jinfo_image_height_address_b;
reg p_jinfo_image_height_write_enable_b;
reg [15:0] p_jinfo_image_height_in_b;
wire [15:0] p_jinfo_image_height_out_b;
// @p_jinfo_image_height = internal unnamed_addr global i16 0, align 2
ram_two_ports p_jinfo_image_height (
.clk( clk ),
.address_a( p_jinfo_image_height_address_a ),
.wren_a( p_jinfo_image_height_write_enable_a ),
.data_a( p_jinfo_image_height_in_a ),
.address_b( p_jinfo_image_height_address_b ),
.wren_b( p_jinfo_image_height_write_enable_b ),
.data_b( p_jinfo_image_height_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_image_height_out_a ),
.q_b( p_jinfo_image_height_out_b)
);
defparam p_jinfo_image_height.width_a = 16;
defparam p_jinfo_image_height.widthad_a = 1;
defparam p_jinfo_image_height.width_b = 16;
defparam p_jinfo_image_height.widthad_b = 1;
defparam p_jinfo_image_height.width_be_a = 1;
defparam p_jinfo_image_height.width_be_b = 1;
defparam p_jinfo_image_height.numwords_a = 1;
defparam p_jinfo_image_height.numwords_b = 1;
defparam p_jinfo_image_height.init_file = "p_jinfo_image_height.mif";
reg [0:0] p_jinfo_image_width_address_a;
reg p_jinfo_image_width_write_enable_a;
reg [15:0] p_jinfo_image_width_in_a;
wire [15:0] p_jinfo_image_width_out_a;
reg [0:0] p_jinfo_image_width_address_b;
reg p_jinfo_image_width_write_enable_b;
reg [15:0] p_jinfo_image_width_in_b;
wire [15:0] p_jinfo_image_width_out_b;
// @p_jinfo_image_width = internal unnamed_addr global i16 0, align 2
ram_two_ports p_jinfo_image_width (
.clk( clk ),
.address_a( p_jinfo_image_width_address_a ),
.wren_a( p_jinfo_image_width_write_enable_a ),
.data_a( p_jinfo_image_width_in_a ),
.address_b( p_jinfo_image_width_address_b ),
.wren_b( p_jinfo_image_width_write_enable_b ),
.data_b( p_jinfo_image_width_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_image_width_out_a ),
.q_b( p_jinfo_image_width_out_b)
);
defparam p_jinfo_image_width.width_a = 16;
defparam p_jinfo_image_width.widthad_a = 1;
defparam p_jinfo_image_width.width_b = 16;
defparam p_jinfo_image_width.widthad_b = 1;
defparam p_jinfo_image_width.width_be_a = 1;
defparam p_jinfo_image_width.width_be_b = 1;
defparam p_jinfo_image_width.numwords_a = 1;
defparam p_jinfo_image_width.numwords_b = 1;
defparam p_jinfo_image_width.init_file = "p_jinfo_image_width.mif";
reg [1:0] p_jinfo_comps_info_index_address_a;
reg p_jinfo_comps_info_index_write_enable_a;
reg [7:0] p_jinfo_comps_info_index_in_a;
wire [7:0] p_jinfo_comps_info_index_out_a;
reg [1:0] p_jinfo_comps_info_index_address_b;
reg p_jinfo_comps_info_index_write_enable_b;
reg [7:0] p_jinfo_comps_info_index_in_b;
wire [7:0] p_jinfo_comps_info_index_out_b;
// @p_jinfo_comps_info_index = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_index (
.clk( clk ),
.address_a( p_jinfo_comps_info_index_address_a ),
.wren_a( p_jinfo_comps_info_index_write_enable_a ),
.data_a( p_jinfo_comps_info_index_in_a ),
.address_b( p_jinfo_comps_info_index_address_b ),
.wren_b( p_jinfo_comps_info_index_write_enable_b ),
.data_b( p_jinfo_comps_info_index_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_index_out_a ),
.q_b( p_jinfo_comps_info_index_out_b)
);
defparam p_jinfo_comps_info_index.width_a = 8;
defparam p_jinfo_comps_info_index.widthad_a = 2;
defparam p_jinfo_comps_info_index.width_b = 8;
defparam p_jinfo_comps_info_index.widthad_b = 2;
defparam p_jinfo_comps_info_index.width_be_a = 1;
defparam p_jinfo_comps_info_index.width_be_b = 1;
defparam p_jinfo_comps_info_index.numwords_a = 3;
defparam p_jinfo_comps_info_index.numwords_b = 3;
defparam p_jinfo_comps_info_index.init_file = "p_jinfo_comps_info_index.mif";
reg [1:0] p_jinfo_comps_info_id_address_a;
reg p_jinfo_comps_info_id_write_enable_a;
reg [7:0] p_jinfo_comps_info_id_in_a;
wire [7:0] p_jinfo_comps_info_id_out_a;
reg [1:0] p_jinfo_comps_info_id_address_b;
reg p_jinfo_comps_info_id_write_enable_b;
reg [7:0] p_jinfo_comps_info_id_in_b;
wire [7:0] p_jinfo_comps_info_id_out_b;
// @p_jinfo_comps_info_id = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_id (
.clk( clk ),
.address_a( p_jinfo_comps_info_id_address_a ),
.wren_a( p_jinfo_comps_info_id_write_enable_a ),
.data_a( p_jinfo_comps_info_id_in_a ),
.address_b( p_jinfo_comps_info_id_address_b ),
.wren_b( p_jinfo_comps_info_id_write_enable_b ),
.data_b( p_jinfo_comps_info_id_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_id_out_a ),
.q_b( p_jinfo_comps_info_id_out_b)
);
defparam p_jinfo_comps_info_id.width_a = 8;
defparam p_jinfo_comps_info_id.widthad_a = 2;
defparam p_jinfo_comps_info_id.width_b = 8;
defparam p_jinfo_comps_info_id.widthad_b = 2;
defparam p_jinfo_comps_info_id.width_be_a = 1;
defparam p_jinfo_comps_info_id.width_be_b = 1;
defparam p_jinfo_comps_info_id.numwords_a = 3;
defparam p_jinfo_comps_info_id.numwords_b = 3;
defparam p_jinfo_comps_info_id.init_file = "p_jinfo_comps_info_id.mif";
reg [1:0] p_jinfo_comps_info_h_samp_factor_address_a;
reg p_jinfo_comps_info_h_samp_factor_write_enable_a;
reg [7:0] p_jinfo_comps_info_h_samp_factor_in_a;
wire [7:0] p_jinfo_comps_info_h_samp_factor_out_a;
reg [1:0] p_jinfo_comps_info_h_samp_factor_address_b;
reg p_jinfo_comps_info_h_samp_factor_write_enable_b;
reg [7:0] p_jinfo_comps_info_h_samp_factor_in_b;
wire [7:0] p_jinfo_comps_info_h_samp_factor_out_b;
// @p_jinfo_comps_info_h_samp_factor = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_h_samp_factor (
.clk( clk ),
.address_a( p_jinfo_comps_info_h_samp_factor_address_a ),
.wren_a( p_jinfo_comps_info_h_samp_factor_write_enable_a ),
.data_a( p_jinfo_comps_info_h_samp_factor_in_a ),
.address_b( p_jinfo_comps_info_h_samp_factor_address_b ),
.wren_b( p_jinfo_comps_info_h_samp_factor_write_enable_b ),
.data_b( p_jinfo_comps_info_h_samp_factor_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_h_samp_factor_out_a ),
.q_b( p_jinfo_comps_info_h_samp_factor_out_b)
);
defparam p_jinfo_comps_info_h_samp_factor.width_a = 8;
defparam p_jinfo_comps_info_h_samp_factor.widthad_a = 2;
defparam p_jinfo_comps_info_h_samp_factor.width_b = 8;
defparam p_jinfo_comps_info_h_samp_factor.widthad_b = 2;
defparam p_jinfo_comps_info_h_samp_factor.width_be_a = 1;
defparam p_jinfo_comps_info_h_samp_factor.width_be_b = 1;
defparam p_jinfo_comps_info_h_samp_factor.numwords_a = 3;
defparam p_jinfo_comps_info_h_samp_factor.numwords_b = 3;
defparam p_jinfo_comps_info_h_samp_factor.init_file = "p_jinfo_comps_info_h_samp_factor.mif";
reg [1:0] p_jinfo_comps_info_v_samp_factor_address_a;
reg p_jinfo_comps_info_v_samp_factor_write_enable_a;
reg [7:0] p_jinfo_comps_info_v_samp_factor_in_a;
wire [7:0] p_jinfo_comps_info_v_samp_factor_out_a;
reg [1:0] p_jinfo_comps_info_v_samp_factor_address_b;
reg p_jinfo_comps_info_v_samp_factor_write_enable_b;
reg [7:0] p_jinfo_comps_info_v_samp_factor_in_b;
wire [7:0] p_jinfo_comps_info_v_samp_factor_out_b;
// @p_jinfo_comps_info_v_samp_factor = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_v_samp_factor (
.clk( clk ),
.address_a( p_jinfo_comps_info_v_samp_factor_address_a ),
.wren_a( p_jinfo_comps_info_v_samp_factor_write_enable_a ),
.data_a( p_jinfo_comps_info_v_samp_factor_in_a ),
.address_b( p_jinfo_comps_info_v_samp_factor_address_b ),
.wren_b( p_jinfo_comps_info_v_samp_factor_write_enable_b ),
.data_b( p_jinfo_comps_info_v_samp_factor_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_v_samp_factor_out_a ),
.q_b( p_jinfo_comps_info_v_samp_factor_out_b)
);
defparam p_jinfo_comps_info_v_samp_factor.width_a = 8;
defparam p_jinfo_comps_info_v_samp_factor.widthad_a = 2;
defparam p_jinfo_comps_info_v_samp_factor.width_b = 8;
defparam p_jinfo_comps_info_v_samp_factor.widthad_b = 2;
defparam p_jinfo_comps_info_v_samp_factor.width_be_a = 1;
defparam p_jinfo_comps_info_v_samp_factor.width_be_b = 1;
defparam p_jinfo_comps_info_v_samp_factor.numwords_a = 3;
defparam p_jinfo_comps_info_v_samp_factor.numwords_b = 3;
defparam p_jinfo_comps_info_v_samp_factor.init_file = "p_jinfo_comps_info_v_samp_factor.mif";
reg [1:0] p_jinfo_comps_info_quant_tbl_no_address_a;
reg p_jinfo_comps_info_quant_tbl_no_write_enable_a;
reg [7:0] p_jinfo_comps_info_quant_tbl_no_in_a;
wire [7:0] p_jinfo_comps_info_quant_tbl_no_out_a;
reg [1:0] p_jinfo_comps_info_quant_tbl_no_address_b;
reg p_jinfo_comps_info_quant_tbl_no_write_enable_b;
reg [7:0] p_jinfo_comps_info_quant_tbl_no_in_b;
wire [7:0] p_jinfo_comps_info_quant_tbl_no_out_b;
// @p_jinfo_comps_info_quant_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_quant_tbl_no (
.clk( clk ),
.address_a( p_jinfo_comps_info_quant_tbl_no_address_a ),
.wren_a( p_jinfo_comps_info_quant_tbl_no_write_enable_a ),
.data_a( p_jinfo_comps_info_quant_tbl_no_in_a ),
.address_b( p_jinfo_comps_info_quant_tbl_no_address_b ),
.wren_b( p_jinfo_comps_info_quant_tbl_no_write_enable_b ),
.data_b( p_jinfo_comps_info_quant_tbl_no_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_quant_tbl_no_out_a ),
.q_b( p_jinfo_comps_info_quant_tbl_no_out_b)
);
defparam p_jinfo_comps_info_quant_tbl_no.width_a = 8;
defparam p_jinfo_comps_info_quant_tbl_no.widthad_a = 2;
defparam p_jinfo_comps_info_quant_tbl_no.width_b = 8;
defparam p_jinfo_comps_info_quant_tbl_no.widthad_b = 2;
defparam p_jinfo_comps_info_quant_tbl_no.width_be_a = 1;
defparam p_jinfo_comps_info_quant_tbl_no.width_be_b = 1;
defparam p_jinfo_comps_info_quant_tbl_no.numwords_a = 3;
defparam p_jinfo_comps_info_quant_tbl_no.numwords_b = 3;
defparam p_jinfo_comps_info_quant_tbl_no.init_file = "p_jinfo_comps_info_quant_tbl_no.mif";
reg [1:0] p_jinfo_comps_info_dc_tbl_no_address_a;
reg p_jinfo_comps_info_dc_tbl_no_write_enable_a;
reg [7:0] p_jinfo_comps_info_dc_tbl_no_in_a;
wire [7:0] p_jinfo_comps_info_dc_tbl_no_out_a;
reg [1:0] p_jinfo_comps_info_dc_tbl_no_address_b;
reg p_jinfo_comps_info_dc_tbl_no_write_enable_b;
reg [7:0] p_jinfo_comps_info_dc_tbl_no_in_b;
wire [7:0] p_jinfo_comps_info_dc_tbl_no_out_b;
// @p_jinfo_comps_info_dc_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_dc_tbl_no (
.clk( clk ),
.address_a( p_jinfo_comps_info_dc_tbl_no_address_a ),
.wren_a( p_jinfo_comps_info_dc_tbl_no_write_enable_a ),
.data_a( p_jinfo_comps_info_dc_tbl_no_in_a ),
.address_b( p_jinfo_comps_info_dc_tbl_no_address_b ),
.wren_b( p_jinfo_comps_info_dc_tbl_no_write_enable_b ),
.data_b( p_jinfo_comps_info_dc_tbl_no_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_dc_tbl_no_out_a ),
.q_b( p_jinfo_comps_info_dc_tbl_no_out_b)
);
defparam p_jinfo_comps_info_dc_tbl_no.width_a = 8;
defparam p_jinfo_comps_info_dc_tbl_no.widthad_a = 2;
defparam p_jinfo_comps_info_dc_tbl_no.width_b = 8;
defparam p_jinfo_comps_info_dc_tbl_no.widthad_b = 2;
defparam p_jinfo_comps_info_dc_tbl_no.width_be_a = 1;
defparam p_jinfo_comps_info_dc_tbl_no.width_be_b = 1;
defparam p_jinfo_comps_info_dc_tbl_no.numwords_a = 3;
defparam p_jinfo_comps_info_dc_tbl_no.numwords_b = 3;
defparam p_jinfo_comps_info_dc_tbl_no.init_file = "p_jinfo_comps_info_dc_tbl_no.mif";
reg [1:0] p_jinfo_comps_info_ac_tbl_no_address_a;
reg p_jinfo_comps_info_ac_tbl_no_write_enable_a;
reg [7:0] p_jinfo_comps_info_ac_tbl_no_in_a;
wire [7:0] p_jinfo_comps_info_ac_tbl_no_out_a;
reg [1:0] p_jinfo_comps_info_ac_tbl_no_address_b;
reg p_jinfo_comps_info_ac_tbl_no_write_enable_b;
reg [7:0] p_jinfo_comps_info_ac_tbl_no_in_b;
wire [7:0] p_jinfo_comps_info_ac_tbl_no_out_b;
// @p_jinfo_comps_info_ac_tbl_no = internal unnamed_addr global [3 x i8] zeroinitializer, align 1
ram_two_ports p_jinfo_comps_info_ac_tbl_no (
.clk( clk ),
.address_a( p_jinfo_comps_info_ac_tbl_no_address_a ),
.wren_a( p_jinfo_comps_info_ac_tbl_no_write_enable_a ),
.data_a( p_jinfo_comps_info_ac_tbl_no_in_a ),
.address_b( p_jinfo_comps_info_ac_tbl_no_address_b ),
.wren_b( p_jinfo_comps_info_ac_tbl_no_write_enable_b ),
.data_b( p_jinfo_comps_info_ac_tbl_no_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_comps_info_ac_tbl_no_out_a ),
.q_b( p_jinfo_comps_info_ac_tbl_no_out_b)
);
defparam p_jinfo_comps_info_ac_tbl_no.width_a = 8;
defparam p_jinfo_comps_info_ac_tbl_no.widthad_a = 2;
defparam p_jinfo_comps_info_ac_tbl_no.width_b = 8;
defparam p_jinfo_comps_info_ac_tbl_no.widthad_b = 2;
defparam p_jinfo_comps_info_ac_tbl_no.width_be_a = 1;
defparam p_jinfo_comps_info_ac_tbl_no.width_be_b = 1;
defparam p_jinfo_comps_info_ac_tbl_no.numwords_a = 3;
defparam p_jinfo_comps_info_ac_tbl_no.numwords_b = 3;
defparam p_jinfo_comps_info_ac_tbl_no.init_file = "p_jinfo_comps_info_ac_tbl_no.mif";
reg [6:0] p_jinfo_ac_xhuff_tbl_bits_address_a;
reg p_jinfo_ac_xhuff_tbl_bits_write_enable_a;
reg [31:0] p_jinfo_ac_xhuff_tbl_bits_in_a;
wire [31:0] p_jinfo_ac_xhuff_tbl_bits_out_a;
reg [6:0] p_jinfo_ac_xhuff_tbl_bits_address_b;
reg p_jinfo_ac_xhuff_tbl_bits_write_enable_b;
reg [31:0] p_jinfo_ac_xhuff_tbl_bits_in_b;
wire [31:0] p_jinfo_ac_xhuff_tbl_bits_out_b;
// @p_jinfo_ac_xhuff_tbl_bits = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_xhuff_tbl_bits (
.clk( clk ),
.address_a( p_jinfo_ac_xhuff_tbl_bits_address_a ),
.wren_a( p_jinfo_ac_xhuff_tbl_bits_write_enable_a ),
.data_a( p_jinfo_ac_xhuff_tbl_bits_in_a ),
.address_b( p_jinfo_ac_xhuff_tbl_bits_address_b ),
.wren_b( p_jinfo_ac_xhuff_tbl_bits_write_enable_b ),
.data_b( p_jinfo_ac_xhuff_tbl_bits_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_xhuff_tbl_bits_out_a ),
.q_b( p_jinfo_ac_xhuff_tbl_bits_out_b)
);
defparam p_jinfo_ac_xhuff_tbl_bits.width_a = 32;
defparam p_jinfo_ac_xhuff_tbl_bits.widthad_a = 7;
defparam p_jinfo_ac_xhuff_tbl_bits.width_b = 32;
defparam p_jinfo_ac_xhuff_tbl_bits.widthad_b = 7;
defparam p_jinfo_ac_xhuff_tbl_bits.width_be_a = 1;
defparam p_jinfo_ac_xhuff_tbl_bits.width_be_b = 1;
defparam p_jinfo_ac_xhuff_tbl_bits.numwords_a = 72;
defparam p_jinfo_ac_xhuff_tbl_bits.numwords_b = 72;
defparam p_jinfo_ac_xhuff_tbl_bits.init_file = "p_jinfo_ac_xhuff_tbl_bits.mif";
reg [9:0] p_jinfo_ac_xhuff_tbl_huffval_address_a;
reg p_jinfo_ac_xhuff_tbl_huffval_write_enable_a;
reg [31:0] p_jinfo_ac_xhuff_tbl_huffval_in_a;
wire [31:0] p_jinfo_ac_xhuff_tbl_huffval_out_a;
reg [9:0] p_jinfo_ac_xhuff_tbl_huffval_address_b;
reg p_jinfo_ac_xhuff_tbl_huffval_write_enable_b;
reg [31:0] p_jinfo_ac_xhuff_tbl_huffval_in_b;
wire [31:0] p_jinfo_ac_xhuff_tbl_huffval_out_b;
// @p_jinfo_ac_xhuff_tbl_huffval = internal global [2 x [257 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_xhuff_tbl_huffval (
.clk( clk ),
.address_a( p_jinfo_ac_xhuff_tbl_huffval_address_a ),
.wren_a( p_jinfo_ac_xhuff_tbl_huffval_write_enable_a ),
.data_a( p_jinfo_ac_xhuff_tbl_huffval_in_a ),
.address_b( p_jinfo_ac_xhuff_tbl_huffval_address_b ),
.wren_b( p_jinfo_ac_xhuff_tbl_huffval_write_enable_b ),
.data_b( p_jinfo_ac_xhuff_tbl_huffval_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_xhuff_tbl_huffval_out_a ),
.q_b( p_jinfo_ac_xhuff_tbl_huffval_out_b)
);
defparam p_jinfo_ac_xhuff_tbl_huffval.width_a = 32;
defparam p_jinfo_ac_xhuff_tbl_huffval.widthad_a = 10;
defparam p_jinfo_ac_xhuff_tbl_huffval.width_b = 32;
defparam p_jinfo_ac_xhuff_tbl_huffval.widthad_b = 10;
defparam p_jinfo_ac_xhuff_tbl_huffval.width_be_a = 1;
defparam p_jinfo_ac_xhuff_tbl_huffval.width_be_b = 1;
defparam p_jinfo_ac_xhuff_tbl_huffval.numwords_a = 514;
defparam p_jinfo_ac_xhuff_tbl_huffval.numwords_b = 514;
defparam p_jinfo_ac_xhuff_tbl_huffval.init_file = "p_jinfo_ac_xhuff_tbl_huffval.mif";
reg [6:0] p_jinfo_dc_xhuff_tbl_bits_address_a;
reg p_jinfo_dc_xhuff_tbl_bits_write_enable_a;
reg [31:0] p_jinfo_dc_xhuff_tbl_bits_in_a;
wire [31:0] p_jinfo_dc_xhuff_tbl_bits_out_a;
reg [6:0] p_jinfo_dc_xhuff_tbl_bits_address_b;
reg p_jinfo_dc_xhuff_tbl_bits_write_enable_b;
reg [31:0] p_jinfo_dc_xhuff_tbl_bits_in_b;
wire [31:0] p_jinfo_dc_xhuff_tbl_bits_out_b;
// @p_jinfo_dc_xhuff_tbl_bits = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_xhuff_tbl_bits (
.clk( clk ),
.address_a( p_jinfo_dc_xhuff_tbl_bits_address_a ),
.wren_a( p_jinfo_dc_xhuff_tbl_bits_write_enable_a ),
.data_a( p_jinfo_dc_xhuff_tbl_bits_in_a ),
.address_b( p_jinfo_dc_xhuff_tbl_bits_address_b ),
.wren_b( p_jinfo_dc_xhuff_tbl_bits_write_enable_b ),
.data_b( p_jinfo_dc_xhuff_tbl_bits_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_xhuff_tbl_bits_out_a ),
.q_b( p_jinfo_dc_xhuff_tbl_bits_out_b)
);
defparam p_jinfo_dc_xhuff_tbl_bits.width_a = 32;
defparam p_jinfo_dc_xhuff_tbl_bits.widthad_a = 7;
defparam p_jinfo_dc_xhuff_tbl_bits.width_b = 32;
defparam p_jinfo_dc_xhuff_tbl_bits.widthad_b = 7;
defparam p_jinfo_dc_xhuff_tbl_bits.width_be_a = 1;
defparam p_jinfo_dc_xhuff_tbl_bits.width_be_b = 1;
defparam p_jinfo_dc_xhuff_tbl_bits.numwords_a = 72;
defparam p_jinfo_dc_xhuff_tbl_bits.numwords_b = 72;
defparam p_jinfo_dc_xhuff_tbl_bits.init_file = "p_jinfo_dc_xhuff_tbl_bits.mif";
reg [9:0] p_jinfo_dc_xhuff_tbl_huffval_address_a;
reg p_jinfo_dc_xhuff_tbl_huffval_write_enable_a;
reg [31:0] p_jinfo_dc_xhuff_tbl_huffval_in_a;
wire [31:0] p_jinfo_dc_xhuff_tbl_huffval_out_a;
reg [9:0] p_jinfo_dc_xhuff_tbl_huffval_address_b;
reg p_jinfo_dc_xhuff_tbl_huffval_write_enable_b;
reg [31:0] p_jinfo_dc_xhuff_tbl_huffval_in_b;
wire [31:0] p_jinfo_dc_xhuff_tbl_huffval_out_b;
// @p_jinfo_dc_xhuff_tbl_huffval = internal global [2 x [257 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_xhuff_tbl_huffval (
.clk( clk ),
.address_a( p_jinfo_dc_xhuff_tbl_huffval_address_a ),
.wren_a( p_jinfo_dc_xhuff_tbl_huffval_write_enable_a ),
.data_a( p_jinfo_dc_xhuff_tbl_huffval_in_a ),
.address_b( p_jinfo_dc_xhuff_tbl_huffval_address_b ),
.wren_b( p_jinfo_dc_xhuff_tbl_huffval_write_enable_b ),
.data_b( p_jinfo_dc_xhuff_tbl_huffval_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_xhuff_tbl_huffval_out_a ),
.q_b( p_jinfo_dc_xhuff_tbl_huffval_out_b)
);
defparam p_jinfo_dc_xhuff_tbl_huffval.width_a = 32;
defparam p_jinfo_dc_xhuff_tbl_huffval.widthad_a = 10;
defparam p_jinfo_dc_xhuff_tbl_huffval.width_b = 32;
defparam p_jinfo_dc_xhuff_tbl_huffval.widthad_b = 10;
defparam p_jinfo_dc_xhuff_tbl_huffval.width_be_a = 1;
defparam p_jinfo_dc_xhuff_tbl_huffval.width_be_b = 1;
defparam p_jinfo_dc_xhuff_tbl_huffval.numwords_a = 514;
defparam p_jinfo_dc_xhuff_tbl_huffval.numwords_b = 514;
defparam p_jinfo_dc_xhuff_tbl_huffval.init_file = "p_jinfo_dc_xhuff_tbl_huffval.mif";
reg [7:0] p_jinfo_quant_tbl_quantval_address_a;
reg p_jinfo_quant_tbl_quantval_write_enable_a;
reg [31:0] p_jinfo_quant_tbl_quantval_in_a;
wire [31:0] p_jinfo_quant_tbl_quantval_out_a;
reg [7:0] p_jinfo_quant_tbl_quantval_address_b;
reg p_jinfo_quant_tbl_quantval_write_enable_b;
reg [31:0] p_jinfo_quant_tbl_quantval_in_b;
wire [31:0] p_jinfo_quant_tbl_quantval_out_b;
// @p_jinfo_quant_tbl_quantval = internal unnamed_addr global [4 x [64 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_quant_tbl_quantval (
.clk( clk ),
.address_a( p_jinfo_quant_tbl_quantval_address_a ),
.wren_a( p_jinfo_quant_tbl_quantval_write_enable_a ),
.data_a( p_jinfo_quant_tbl_quantval_in_a ),
.address_b( p_jinfo_quant_tbl_quantval_address_b ),
.wren_b( p_jinfo_quant_tbl_quantval_write_enable_b ),
.data_b( p_jinfo_quant_tbl_quantval_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_quant_tbl_quantval_out_a ),
.q_b( p_jinfo_quant_tbl_quantval_out_b)
);
defparam p_jinfo_quant_tbl_quantval.width_a = 32;
defparam p_jinfo_quant_tbl_quantval.widthad_a = 8;
defparam p_jinfo_quant_tbl_quantval.width_b = 32;
defparam p_jinfo_quant_tbl_quantval.widthad_b = 8;
defparam p_jinfo_quant_tbl_quantval.width_be_a = 1;
defparam p_jinfo_quant_tbl_quantval.width_be_b = 1;
defparam p_jinfo_quant_tbl_quantval.numwords_a = 256;
defparam p_jinfo_quant_tbl_quantval.numwords_b = 256;
defparam p_jinfo_quant_tbl_quantval.init_file = "p_jinfo_quant_tbl_quantval.mif";
reg [5:0] zigzag_index_address_a;
reg zigzag_index_write_enable_a;
reg [31:0] zigzag_index_in_a;
wire [31:0] zigzag_index_out_a;
reg [5:0] zigzag_index_address_b;
reg zigzag_index_write_enable_b;
reg [31:0] zigzag_index_in_b;
wire [31:0] zigzag_index_out_b;
// @zigzag_index = internal unnamed_addr constant [64 x i32] [i32 0, i32 1, i32 5, i32 6, i32 14, i32 15, i32 27, i32 28, i32 2, i32 4, i32 7, i32 13, i32 16, i32 26, i32 29, i32 42, i32 3, i32 8, i32 12, i32 17, i32 25, i32 30, i32 41, i32 43, i32 9, i32 11, i32 18, i32 24, i32 31, i32 40, i32 44, i32 53, i32 10, i32 19, i32 23, i32 32, i32 39, i32 45, i32 52, i32 54, i32 20, i32 22, i32 33, i32 38, i32 46, i32 51, i32 55, i32 60, i32 21, i32 34, i32 37, i32 47, i32 50, i32 56, i32 59, i32 61, i32 35, i32 36, i32 48, i32 49, i32 57, i32 58, i32 62, i32 63], align 4
ram_two_ports zigzag_index (
.clk( clk ),
.address_a( zigzag_index_address_a ),
.wren_a( zigzag_index_write_enable_a ),
.data_a( zigzag_index_in_a ),
.address_b( zigzag_index_address_b ),
.wren_b( zigzag_index_write_enable_b ),
.data_b( zigzag_index_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( zigzag_index_out_a ),
.q_b( zigzag_index_out_b)
);
defparam zigzag_index.width_a = 32;
defparam zigzag_index.widthad_a = 6;
defparam zigzag_index.width_b = 32;
defparam zigzag_index.widthad_b = 6;
defparam zigzag_index.width_be_a = 1;
defparam zigzag_index.width_be_b = 1;
defparam zigzag_index.numwords_a = 64;
defparam zigzag_index.numwords_b = 64;
defparam zigzag_index.init_file = "zigzag_index.mif";
reg [0:0] p_jinfo_MCUWidth_address_a;
reg p_jinfo_MCUWidth_write_enable_a;
reg [31:0] p_jinfo_MCUWidth_in_a;
wire [31:0] p_jinfo_MCUWidth_out_a;
reg [0:0] p_jinfo_MCUWidth_address_b;
reg p_jinfo_MCUWidth_write_enable_b;
reg [31:0] p_jinfo_MCUWidth_in_b;
wire [31:0] p_jinfo_MCUWidth_out_b;
// @p_jinfo_MCUWidth = internal unnamed_addr global i32 0, align 4
ram_two_ports p_jinfo_MCUWidth (
.clk( clk ),
.address_a( p_jinfo_MCUWidth_address_a ),
.wren_a( p_jinfo_MCUWidth_write_enable_a ),
.data_a( p_jinfo_MCUWidth_in_a ),
.address_b( p_jinfo_MCUWidth_address_b ),
.wren_b( p_jinfo_MCUWidth_write_enable_b ),
.data_b( p_jinfo_MCUWidth_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_MCUWidth_out_a ),
.q_b( p_jinfo_MCUWidth_out_b)
);
defparam p_jinfo_MCUWidth.width_a = 32;
defparam p_jinfo_MCUWidth.widthad_a = 1;
defparam p_jinfo_MCUWidth.width_b = 32;
defparam p_jinfo_MCUWidth.widthad_b = 1;
defparam p_jinfo_MCUWidth.width_be_a = 1;
defparam p_jinfo_MCUWidth.width_be_b = 1;
defparam p_jinfo_MCUWidth.numwords_a = 1;
defparam p_jinfo_MCUWidth.numwords_b = 1;
defparam p_jinfo_MCUWidth.init_file = "p_jinfo_MCUWidth.mif";
reg [9:0] rgb_buf_address_a;
reg rgb_buf_write_enable_a;
reg [31:0] rgb_buf_in_a;
wire [31:0] rgb_buf_out_a;
reg [9:0] rgb_buf_address_b;
reg rgb_buf_write_enable_b;
reg [31:0] rgb_buf_in_b;
wire [31:0] rgb_buf_out_b;
// @rgb_buf = internal global [4 x [3 x [64 x i32]]] zeroinitializer, align 4
ram_two_ports rgb_buf (
.clk( clk ),
.address_a( rgb_buf_address_a ),
.wren_a( rgb_buf_write_enable_a ),
.data_a( rgb_buf_in_a ),
.address_b( rgb_buf_address_b ),
.wren_b( rgb_buf_write_enable_b ),
.data_b( rgb_buf_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( rgb_buf_out_a ),
.q_b( rgb_buf_out_b)
);
defparam rgb_buf.width_a = 32;
defparam rgb_buf.widthad_a = 10;
defparam rgb_buf.width_b = 32;
defparam rgb_buf.widthad_b = 10;
defparam rgb_buf.width_be_a = 1;
defparam rgb_buf.width_be_b = 1;
defparam rgb_buf.numwords_a = 768;
defparam rgb_buf.numwords_b = 768;
defparam rgb_buf.init_file = "rgb_buf.mif";
reg [0:0] CurHuffReadBuf_address_a;
reg CurHuffReadBuf_write_enable_a;
reg [31:0] CurHuffReadBuf_in_a;
wire [31:0] CurHuffReadBuf_out_a;
reg [0:0] CurHuffReadBuf_address_b;
reg CurHuffReadBuf_write_enable_b;
reg [31:0] CurHuffReadBuf_in_b;
wire [31:0] CurHuffReadBuf_out_b;
// @CurHuffReadBuf = internal unnamed_addr global i8* null, align 4
ram_two_ports CurHuffReadBuf (
.clk( clk ),
.address_a( CurHuffReadBuf_address_a ),
.wren_a( CurHuffReadBuf_write_enable_a ),
.data_a( CurHuffReadBuf_in_a ),
.address_b( CurHuffReadBuf_address_b ),
.wren_b( CurHuffReadBuf_write_enable_b ),
.data_b( CurHuffReadBuf_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( CurHuffReadBuf_out_a ),
.q_b( CurHuffReadBuf_out_b)
);
defparam CurHuffReadBuf.width_a = 32;
defparam CurHuffReadBuf.widthad_a = 1;
defparam CurHuffReadBuf.width_b = 32;
defparam CurHuffReadBuf.widthad_b = 1;
defparam CurHuffReadBuf.width_be_a = 1;
defparam CurHuffReadBuf.width_be_b = 1;
defparam CurHuffReadBuf.numwords_a = 1;
defparam CurHuffReadBuf.numwords_b = 1;
defparam CurHuffReadBuf.init_file = "CurHuffReadBuf.mif";
reg [13:0] OutData_comp_buf_address_a;
reg OutData_comp_buf_write_enable_a;
reg [7:0] OutData_comp_buf_in_a;
wire [7:0] OutData_comp_buf_out_a;
reg [13:0] OutData_comp_buf_address_b;
reg OutData_comp_buf_write_enable_b;
reg [7:0] OutData_comp_buf_in_b;
wire [7:0] OutData_comp_buf_out_b;
// @OutData_comp_buf = internal global [3 x [5310 x i8]] zeroinitializer, align 1
ram_two_ports OutData_comp_buf (
.clk( clk ),
.address_a( OutData_comp_buf_address_a ),
.wren_a( OutData_comp_buf_write_enable_a ),
.data_a( OutData_comp_buf_in_a ),
.address_b( OutData_comp_buf_address_b ),
.wren_b( OutData_comp_buf_write_enable_b ),
.data_b( OutData_comp_buf_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( OutData_comp_buf_out_a ),
.q_b( OutData_comp_buf_out_b)
);
defparam OutData_comp_buf.width_a = 8;
defparam OutData_comp_buf.widthad_a = 14;
defparam OutData_comp_buf.width_b = 8;
defparam OutData_comp_buf.widthad_b = 14;
defparam OutData_comp_buf.width_be_a = 1;
defparam OutData_comp_buf.width_be_b = 1;
defparam OutData_comp_buf.numwords_a = 15930;
defparam OutData_comp_buf.numwords_b = 15930;
defparam OutData_comp_buf.init_file = "OutData_comp_buf.mif";
reg [4:0] bit_set_mask_address_a;
reg bit_set_mask_write_enable_a;
reg [31:0] bit_set_mask_in_a;
wire [31:0] bit_set_mask_out_a;
reg [4:0] bit_set_mask_address_b;
reg bit_set_mask_write_enable_b;
reg [31:0] bit_set_mask_in_b;
wire [31:0] bit_set_mask_out_b;
// @bit_set_mask = internal unnamed_addr constant [32 x i32] [i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 512, i32 1024, i32 2048, i32 4096, i32 8192, i32 16384, i32 32768, i32 65536, i32 131072, i32 262144, i32 524288, i32 1048576, i32 2097152, i32 4194304, i32 8388608, i32 16777216, i32 33554432, i32 67108864, i32 134217728, i32 268435456, i32 536870912, i32 1073741824, i32 -2147483648], align 4
ram_two_ports bit_set_mask (
.clk( clk ),
.address_a( bit_set_mask_address_a ),
.wren_a( bit_set_mask_write_enable_a ),
.data_a( bit_set_mask_in_a ),
.address_b( bit_set_mask_address_b ),
.wren_b( bit_set_mask_write_enable_b ),
.data_b( bit_set_mask_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( bit_set_mask_out_a ),
.q_b( bit_set_mask_out_b)
);
defparam bit_set_mask.width_a = 32;
defparam bit_set_mask.widthad_a = 5;
defparam bit_set_mask.width_b = 32;
defparam bit_set_mask.widthad_b = 5;
defparam bit_set_mask.width_be_a = 1;
defparam bit_set_mask.width_be_b = 1;
defparam bit_set_mask.numwords_a = 32;
defparam bit_set_mask.numwords_b = 32;
defparam bit_set_mask.init_file = "bit_set_mask.mif";
reg [4:0] lmask_address_a;
reg lmask_write_enable_a;
reg [31:0] lmask_in_a;
wire [31:0] lmask_out_a;
reg [4:0] lmask_address_b;
reg lmask_write_enable_b;
reg [31:0] lmask_in_b;
wire [31:0] lmask_out_b;
// @lmask = internal unnamed_addr constant [32 x i32] [i32 1, i32 3, i32 7, i32 15, i32 31, i32 63, i32 127, i32 255, i32 511, i32 1023, i32 2047, i32 4095, i32 8191, i32 16383, i32 32767, i32 65535, i32 131071, i32 262143, i32 524287, i32 1048575, i32 2097151, i32 4194303, i32 8388607, i32 16777215, i32 33554431, i32 67108863, i32 134217727, i32 268435455, i32 536870911, i32 1073741823, i32 2147483647, i32 -1], align 4
ram_two_ports lmask (
.clk( clk ),
.address_a( lmask_address_a ),
.wren_a( lmask_write_enable_a ),
.data_a( lmask_in_a ),
.address_b( lmask_address_b ),
.wren_b( lmask_write_enable_b ),
.data_b( lmask_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( lmask_out_a ),
.q_b( lmask_out_b)
);
defparam lmask.width_a = 32;
defparam lmask.widthad_a = 5;
defparam lmask.width_b = 32;
defparam lmask.widthad_b = 5;
defparam lmask.width_be_a = 1;
defparam lmask.width_be_b = 1;
defparam lmask.numwords_a = 32;
defparam lmask.numwords_b = 32;
defparam lmask.init_file = "lmask.mif";
reg [0:0] read_position_address_a;
reg read_position_write_enable_a;
reg [31:0] read_position_in_a;
wire [31:0] read_position_out_a;
reg [0:0] read_position_address_b;
reg read_position_write_enable_b;
reg [31:0] read_position_in_b;
wire [31:0] read_position_out_b;
// @read_position = internal unnamed_addr global i32 -1, align 4
ram_two_ports read_position (
.clk( clk ),
.address_a( read_position_address_a ),
.wren_a( read_position_write_enable_a ),
.data_a( read_position_in_a ),
.address_b( read_position_address_b ),
.wren_b( read_position_write_enable_b ),
.data_b( read_position_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( read_position_out_a ),
.q_b( read_position_out_b)
);
defparam read_position.width_a = 32;
defparam read_position.widthad_a = 1;
defparam read_position.width_b = 32;
defparam read_position.widthad_b = 1;
defparam read_position.width_be_a = 1;
defparam read_position.width_be_b = 1;
defparam read_position.numwords_a = 1;
defparam read_position.numwords_b = 1;
defparam read_position.init_file = "read_position.mif";
reg [0:0] current_read_byte_address_a;
reg current_read_byte_write_enable_a;
reg [31:0] current_read_byte_in_a;
wire [31:0] current_read_byte_out_a;
reg [0:0] current_read_byte_address_b;
reg current_read_byte_write_enable_b;
reg [31:0] current_read_byte_in_b;
wire [31:0] current_read_byte_out_b;
// @current_read_byte = internal unnamed_addr global i32 0, align 4
ram_two_ports current_read_byte (
.clk( clk ),
.address_a( current_read_byte_address_a ),
.wren_a( current_read_byte_write_enable_a ),
.data_a( current_read_byte_in_a ),
.address_b( current_read_byte_address_b ),
.wren_b( current_read_byte_write_enable_b ),
.data_b( current_read_byte_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( current_read_byte_out_a ),
.q_b( current_read_byte_out_b)
);
defparam current_read_byte.width_a = 32;
defparam current_read_byte.widthad_a = 1;
defparam current_read_byte.width_b = 32;
defparam current_read_byte.widthad_b = 1;
defparam current_read_byte.width_be_a = 1;
defparam current_read_byte.width_be_b = 1;
defparam current_read_byte.numwords_a = 1;
defparam current_read_byte.numwords_b = 1;
defparam current_read_byte.init_file = "current_read_byte.mif";
reg [0:0] p_jinfo_dc_dhuff_tbl_ml_address_a;
reg p_jinfo_dc_dhuff_tbl_ml_write_enable_a;
reg [31:0] p_jinfo_dc_dhuff_tbl_ml_in_a;
wire [31:0] p_jinfo_dc_dhuff_tbl_ml_out_a;
reg [0:0] p_jinfo_dc_dhuff_tbl_ml_address_b;
reg p_jinfo_dc_dhuff_tbl_ml_write_enable_b;
reg [31:0] p_jinfo_dc_dhuff_tbl_ml_in_b;
wire [31:0] p_jinfo_dc_dhuff_tbl_ml_out_b;
// @p_jinfo_dc_dhuff_tbl_ml = internal unnamed_addr global [2 x i32] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_dhuff_tbl_ml (
.clk( clk ),
.address_a( p_jinfo_dc_dhuff_tbl_ml_address_a ),
.wren_a( p_jinfo_dc_dhuff_tbl_ml_write_enable_a ),
.data_a( p_jinfo_dc_dhuff_tbl_ml_in_a ),
.address_b( p_jinfo_dc_dhuff_tbl_ml_address_b ),
.wren_b( p_jinfo_dc_dhuff_tbl_ml_write_enable_b ),
.data_b( p_jinfo_dc_dhuff_tbl_ml_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_dhuff_tbl_ml_out_a ),
.q_b( p_jinfo_dc_dhuff_tbl_ml_out_b)
);
defparam p_jinfo_dc_dhuff_tbl_ml.width_a = 32;
defparam p_jinfo_dc_dhuff_tbl_ml.widthad_a = 1;
defparam p_jinfo_dc_dhuff_tbl_ml.width_b = 32;
defparam p_jinfo_dc_dhuff_tbl_ml.widthad_b = 1;
defparam p_jinfo_dc_dhuff_tbl_ml.width_be_a = 1;
defparam p_jinfo_dc_dhuff_tbl_ml.width_be_b = 1;
defparam p_jinfo_dc_dhuff_tbl_ml.numwords_a = 2;
defparam p_jinfo_dc_dhuff_tbl_ml.numwords_b = 2;
defparam p_jinfo_dc_dhuff_tbl_ml.init_file = "p_jinfo_dc_dhuff_tbl_ml.mif";
reg [6:0] p_jinfo_dc_dhuff_tbl_maxcode_address_a;
reg p_jinfo_dc_dhuff_tbl_maxcode_write_enable_a;
reg [31:0] p_jinfo_dc_dhuff_tbl_maxcode_in_a;
wire [31:0] p_jinfo_dc_dhuff_tbl_maxcode_out_a;
reg [6:0] p_jinfo_dc_dhuff_tbl_maxcode_address_b;
reg p_jinfo_dc_dhuff_tbl_maxcode_write_enable_b;
reg [31:0] p_jinfo_dc_dhuff_tbl_maxcode_in_b;
wire [31:0] p_jinfo_dc_dhuff_tbl_maxcode_out_b;
// @p_jinfo_dc_dhuff_tbl_maxcode = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_dhuff_tbl_maxcode (
.clk( clk ),
.address_a( p_jinfo_dc_dhuff_tbl_maxcode_address_a ),
.wren_a( p_jinfo_dc_dhuff_tbl_maxcode_write_enable_a ),
.data_a( p_jinfo_dc_dhuff_tbl_maxcode_in_a ),
.address_b( p_jinfo_dc_dhuff_tbl_maxcode_address_b ),
.wren_b( p_jinfo_dc_dhuff_tbl_maxcode_write_enable_b ),
.data_b( p_jinfo_dc_dhuff_tbl_maxcode_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_dhuff_tbl_maxcode_out_a ),
.q_b( p_jinfo_dc_dhuff_tbl_maxcode_out_b)
);
defparam p_jinfo_dc_dhuff_tbl_maxcode.width_a = 32;
defparam p_jinfo_dc_dhuff_tbl_maxcode.widthad_a = 7;
defparam p_jinfo_dc_dhuff_tbl_maxcode.width_b = 32;
defparam p_jinfo_dc_dhuff_tbl_maxcode.widthad_b = 7;
defparam p_jinfo_dc_dhuff_tbl_maxcode.width_be_a = 1;
defparam p_jinfo_dc_dhuff_tbl_maxcode.width_be_b = 1;
defparam p_jinfo_dc_dhuff_tbl_maxcode.numwords_a = 72;
defparam p_jinfo_dc_dhuff_tbl_maxcode.numwords_b = 72;
defparam p_jinfo_dc_dhuff_tbl_maxcode.init_file = "p_jinfo_dc_dhuff_tbl_maxcode.mif";
reg [6:0] p_jinfo_dc_dhuff_tbl_mincode_address_a;
reg p_jinfo_dc_dhuff_tbl_mincode_write_enable_a;
reg [31:0] p_jinfo_dc_dhuff_tbl_mincode_in_a;
wire [31:0] p_jinfo_dc_dhuff_tbl_mincode_out_a;
reg [6:0] p_jinfo_dc_dhuff_tbl_mincode_address_b;
reg p_jinfo_dc_dhuff_tbl_mincode_write_enable_b;
reg [31:0] p_jinfo_dc_dhuff_tbl_mincode_in_b;
wire [31:0] p_jinfo_dc_dhuff_tbl_mincode_out_b;
// @p_jinfo_dc_dhuff_tbl_mincode = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_dhuff_tbl_mincode (
.clk( clk ),
.address_a( p_jinfo_dc_dhuff_tbl_mincode_address_a ),
.wren_a( p_jinfo_dc_dhuff_tbl_mincode_write_enable_a ),
.data_a( p_jinfo_dc_dhuff_tbl_mincode_in_a ),
.address_b( p_jinfo_dc_dhuff_tbl_mincode_address_b ),
.wren_b( p_jinfo_dc_dhuff_tbl_mincode_write_enable_b ),
.data_b( p_jinfo_dc_dhuff_tbl_mincode_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_dhuff_tbl_mincode_out_a ),
.q_b( p_jinfo_dc_dhuff_tbl_mincode_out_b)
);
defparam p_jinfo_dc_dhuff_tbl_mincode.width_a = 32;
defparam p_jinfo_dc_dhuff_tbl_mincode.widthad_a = 7;
defparam p_jinfo_dc_dhuff_tbl_mincode.width_b = 32;
defparam p_jinfo_dc_dhuff_tbl_mincode.widthad_b = 7;
defparam p_jinfo_dc_dhuff_tbl_mincode.width_be_a = 1;
defparam p_jinfo_dc_dhuff_tbl_mincode.width_be_b = 1;
defparam p_jinfo_dc_dhuff_tbl_mincode.numwords_a = 72;
defparam p_jinfo_dc_dhuff_tbl_mincode.numwords_b = 72;
defparam p_jinfo_dc_dhuff_tbl_mincode.init_file = "p_jinfo_dc_dhuff_tbl_mincode.mif";
reg [6:0] p_jinfo_dc_dhuff_tbl_valptr_address_a;
reg p_jinfo_dc_dhuff_tbl_valptr_write_enable_a;
reg [31:0] p_jinfo_dc_dhuff_tbl_valptr_in_a;
wire [31:0] p_jinfo_dc_dhuff_tbl_valptr_out_a;
reg [6:0] p_jinfo_dc_dhuff_tbl_valptr_address_b;
reg p_jinfo_dc_dhuff_tbl_valptr_write_enable_b;
reg [31:0] p_jinfo_dc_dhuff_tbl_valptr_in_b;
wire [31:0] p_jinfo_dc_dhuff_tbl_valptr_out_b;
// @p_jinfo_dc_dhuff_tbl_valptr = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_dc_dhuff_tbl_valptr (
.clk( clk ),
.address_a( p_jinfo_dc_dhuff_tbl_valptr_address_a ),
.wren_a( p_jinfo_dc_dhuff_tbl_valptr_write_enable_a ),
.data_a( p_jinfo_dc_dhuff_tbl_valptr_in_a ),
.address_b( p_jinfo_dc_dhuff_tbl_valptr_address_b ),
.wren_b( p_jinfo_dc_dhuff_tbl_valptr_write_enable_b ),
.data_b( p_jinfo_dc_dhuff_tbl_valptr_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_dc_dhuff_tbl_valptr_out_a ),
.q_b( p_jinfo_dc_dhuff_tbl_valptr_out_b)
);
defparam p_jinfo_dc_dhuff_tbl_valptr.width_a = 32;
defparam p_jinfo_dc_dhuff_tbl_valptr.widthad_a = 7;
defparam p_jinfo_dc_dhuff_tbl_valptr.width_b = 32;
defparam p_jinfo_dc_dhuff_tbl_valptr.widthad_b = 7;
defparam p_jinfo_dc_dhuff_tbl_valptr.width_be_a = 1;
defparam p_jinfo_dc_dhuff_tbl_valptr.width_be_b = 1;
defparam p_jinfo_dc_dhuff_tbl_valptr.numwords_a = 72;
defparam p_jinfo_dc_dhuff_tbl_valptr.numwords_b = 72;
defparam p_jinfo_dc_dhuff_tbl_valptr.init_file = "p_jinfo_dc_dhuff_tbl_valptr.mif";
reg [4:0] extend_mask_address_a;
reg extend_mask_write_enable_a;
reg [31:0] extend_mask_in_a;
wire [31:0] extend_mask_out_a;
reg [4:0] extend_mask_address_b;
reg extend_mask_write_enable_b;
reg [31:0] extend_mask_in_b;
wire [31:0] extend_mask_out_b;
// @extend_mask = internal unnamed_addr constant [20 x i32] [i32 -2, i32 -4, i32 -8, i32 -16, i32 -32, i32 -64, i32 -128, i32 -256, i32 -512, i32 -1024, i32 -2048, i32 -4096, i32 -8192, i32 -16384, i32 -32768, i32 -65536, i32 -131072, i32 -262144, i32 -524288, i32 -1048576], align 4
ram_two_ports extend_mask (
.clk( clk ),
.address_a( extend_mask_address_a ),
.wren_a( extend_mask_write_enable_a ),
.data_a( extend_mask_in_a ),
.address_b( extend_mask_address_b ),
.wren_b( extend_mask_write_enable_b ),
.data_b( extend_mask_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( extend_mask_out_a ),
.q_b( extend_mask_out_b)
);
defparam extend_mask.width_a = 32;
defparam extend_mask.widthad_a = 5;
defparam extend_mask.width_b = 32;
defparam extend_mask.widthad_b = 5;
defparam extend_mask.width_be_a = 1;
defparam extend_mask.width_be_b = 1;
defparam extend_mask.numwords_a = 20;
defparam extend_mask.numwords_b = 20;
defparam extend_mask.init_file = "extend_mask.mif";
reg [0:0] p_jinfo_ac_dhuff_tbl_ml_address_a;
reg p_jinfo_ac_dhuff_tbl_ml_write_enable_a;
reg [31:0] p_jinfo_ac_dhuff_tbl_ml_in_a;
wire [31:0] p_jinfo_ac_dhuff_tbl_ml_out_a;
reg [0:0] p_jinfo_ac_dhuff_tbl_ml_address_b;
reg p_jinfo_ac_dhuff_tbl_ml_write_enable_b;
reg [31:0] p_jinfo_ac_dhuff_tbl_ml_in_b;
wire [31:0] p_jinfo_ac_dhuff_tbl_ml_out_b;
// @p_jinfo_ac_dhuff_tbl_ml = internal unnamed_addr global [2 x i32] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_dhuff_tbl_ml (
.clk( clk ),
.address_a( p_jinfo_ac_dhuff_tbl_ml_address_a ),
.wren_a( p_jinfo_ac_dhuff_tbl_ml_write_enable_a ),
.data_a( p_jinfo_ac_dhuff_tbl_ml_in_a ),
.address_b( p_jinfo_ac_dhuff_tbl_ml_address_b ),
.wren_b( p_jinfo_ac_dhuff_tbl_ml_write_enable_b ),
.data_b( p_jinfo_ac_dhuff_tbl_ml_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_dhuff_tbl_ml_out_a ),
.q_b( p_jinfo_ac_dhuff_tbl_ml_out_b)
);
defparam p_jinfo_ac_dhuff_tbl_ml.width_a = 32;
defparam p_jinfo_ac_dhuff_tbl_ml.widthad_a = 1;
defparam p_jinfo_ac_dhuff_tbl_ml.width_b = 32;
defparam p_jinfo_ac_dhuff_tbl_ml.widthad_b = 1;
defparam p_jinfo_ac_dhuff_tbl_ml.width_be_a = 1;
defparam p_jinfo_ac_dhuff_tbl_ml.width_be_b = 1;
defparam p_jinfo_ac_dhuff_tbl_ml.numwords_a = 2;
defparam p_jinfo_ac_dhuff_tbl_ml.numwords_b = 2;
defparam p_jinfo_ac_dhuff_tbl_ml.init_file = "p_jinfo_ac_dhuff_tbl_ml.mif";
reg [6:0] p_jinfo_ac_dhuff_tbl_maxcode_address_a;
reg p_jinfo_ac_dhuff_tbl_maxcode_write_enable_a;
reg [31:0] p_jinfo_ac_dhuff_tbl_maxcode_in_a;
wire [31:0] p_jinfo_ac_dhuff_tbl_maxcode_out_a;
reg [6:0] p_jinfo_ac_dhuff_tbl_maxcode_address_b;
reg p_jinfo_ac_dhuff_tbl_maxcode_write_enable_b;
reg [31:0] p_jinfo_ac_dhuff_tbl_maxcode_in_b;
wire [31:0] p_jinfo_ac_dhuff_tbl_maxcode_out_b;
// @p_jinfo_ac_dhuff_tbl_maxcode = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_dhuff_tbl_maxcode (
.clk( clk ),
.address_a( p_jinfo_ac_dhuff_tbl_maxcode_address_a ),
.wren_a( p_jinfo_ac_dhuff_tbl_maxcode_write_enable_a ),
.data_a( p_jinfo_ac_dhuff_tbl_maxcode_in_a ),
.address_b( p_jinfo_ac_dhuff_tbl_maxcode_address_b ),
.wren_b( p_jinfo_ac_dhuff_tbl_maxcode_write_enable_b ),
.data_b( p_jinfo_ac_dhuff_tbl_maxcode_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_dhuff_tbl_maxcode_out_a ),
.q_b( p_jinfo_ac_dhuff_tbl_maxcode_out_b)
);
defparam p_jinfo_ac_dhuff_tbl_maxcode.width_a = 32;
defparam p_jinfo_ac_dhuff_tbl_maxcode.widthad_a = 7;
defparam p_jinfo_ac_dhuff_tbl_maxcode.width_b = 32;
defparam p_jinfo_ac_dhuff_tbl_maxcode.widthad_b = 7;
defparam p_jinfo_ac_dhuff_tbl_maxcode.width_be_a = 1;
defparam p_jinfo_ac_dhuff_tbl_maxcode.width_be_b = 1;
defparam p_jinfo_ac_dhuff_tbl_maxcode.numwords_a = 72;
defparam p_jinfo_ac_dhuff_tbl_maxcode.numwords_b = 72;
defparam p_jinfo_ac_dhuff_tbl_maxcode.init_file = "p_jinfo_ac_dhuff_tbl_maxcode.mif";
reg [6:0] p_jinfo_ac_dhuff_tbl_mincode_address_a;
reg p_jinfo_ac_dhuff_tbl_mincode_write_enable_a;
reg [31:0] p_jinfo_ac_dhuff_tbl_mincode_in_a;
wire [31:0] p_jinfo_ac_dhuff_tbl_mincode_out_a;
reg [6:0] p_jinfo_ac_dhuff_tbl_mincode_address_b;
reg p_jinfo_ac_dhuff_tbl_mincode_write_enable_b;
reg [31:0] p_jinfo_ac_dhuff_tbl_mincode_in_b;
wire [31:0] p_jinfo_ac_dhuff_tbl_mincode_out_b;
// @p_jinfo_ac_dhuff_tbl_mincode = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_dhuff_tbl_mincode (
.clk( clk ),
.address_a( p_jinfo_ac_dhuff_tbl_mincode_address_a ),
.wren_a( p_jinfo_ac_dhuff_tbl_mincode_write_enable_a ),
.data_a( p_jinfo_ac_dhuff_tbl_mincode_in_a ),
.address_b( p_jinfo_ac_dhuff_tbl_mincode_address_b ),
.wren_b( p_jinfo_ac_dhuff_tbl_mincode_write_enable_b ),
.data_b( p_jinfo_ac_dhuff_tbl_mincode_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_dhuff_tbl_mincode_out_a ),
.q_b( p_jinfo_ac_dhuff_tbl_mincode_out_b)
);
defparam p_jinfo_ac_dhuff_tbl_mincode.width_a = 32;
defparam p_jinfo_ac_dhuff_tbl_mincode.widthad_a = 7;
defparam p_jinfo_ac_dhuff_tbl_mincode.width_b = 32;
defparam p_jinfo_ac_dhuff_tbl_mincode.widthad_b = 7;
defparam p_jinfo_ac_dhuff_tbl_mincode.width_be_a = 1;
defparam p_jinfo_ac_dhuff_tbl_mincode.width_be_b = 1;
defparam p_jinfo_ac_dhuff_tbl_mincode.numwords_a = 72;
defparam p_jinfo_ac_dhuff_tbl_mincode.numwords_b = 72;
defparam p_jinfo_ac_dhuff_tbl_mincode.init_file = "p_jinfo_ac_dhuff_tbl_mincode.mif";
reg [6:0] p_jinfo_ac_dhuff_tbl_valptr_address_a;
reg p_jinfo_ac_dhuff_tbl_valptr_write_enable_a;
reg [31:0] p_jinfo_ac_dhuff_tbl_valptr_in_a;
wire [31:0] p_jinfo_ac_dhuff_tbl_valptr_out_a;
reg [6:0] p_jinfo_ac_dhuff_tbl_valptr_address_b;
reg p_jinfo_ac_dhuff_tbl_valptr_write_enable_b;
reg [31:0] p_jinfo_ac_dhuff_tbl_valptr_in_b;
wire [31:0] p_jinfo_ac_dhuff_tbl_valptr_out_b;
// @p_jinfo_ac_dhuff_tbl_valptr = internal global [2 x [36 x i32]] zeroinitializer, align 4
ram_two_ports p_jinfo_ac_dhuff_tbl_valptr (
.clk( clk ),
.address_a( p_jinfo_ac_dhuff_tbl_valptr_address_a ),
.wren_a( p_jinfo_ac_dhuff_tbl_valptr_write_enable_a ),
.data_a( p_jinfo_ac_dhuff_tbl_valptr_in_a ),
.address_b( p_jinfo_ac_dhuff_tbl_valptr_address_b ),
.wren_b( p_jinfo_ac_dhuff_tbl_valptr_write_enable_b ),
.data_b( p_jinfo_ac_dhuff_tbl_valptr_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( p_jinfo_ac_dhuff_tbl_valptr_out_a ),
.q_b( p_jinfo_ac_dhuff_tbl_valptr_out_b)
);
defparam p_jinfo_ac_dhuff_tbl_valptr.width_a = 32;
defparam p_jinfo_ac_dhuff_tbl_valptr.widthad_a = 7;
defparam p_jinfo_ac_dhuff_tbl_valptr.width_b = 32;
defparam p_jinfo_ac_dhuff_tbl_valptr.widthad_b = 7;
defparam p_jinfo_ac_dhuff_tbl_valptr.width_be_a = 1;
defparam p_jinfo_ac_dhuff_tbl_valptr.width_be_b = 1;
defparam p_jinfo_ac_dhuff_tbl_valptr.numwords_a = 72;
defparam p_jinfo_ac_dhuff_tbl_valptr.numwords_b = 72;
defparam p_jinfo_ac_dhuff_tbl_valptr.init_file = "p_jinfo_ac_dhuff_tbl_valptr.mif";
reg [1:0] OutData_comp_vpos_address_a;
reg OutData_comp_vpos_write_enable_a;
reg [31:0] OutData_comp_vpos_in_a;
wire [31:0] OutData_comp_vpos_out_a;
reg [1:0] OutData_comp_vpos_address_b;
reg OutData_comp_vpos_write_enable_b;
reg [31:0] OutData_comp_vpos_in_b;
wire [31:0] OutData_comp_vpos_out_b;
// @OutData_comp_vpos = internal global [3 x i32] zeroinitializer, align 4
ram_two_ports OutData_comp_vpos (
.clk( clk ),
.address_a( OutData_comp_vpos_address_a ),
.wren_a( OutData_comp_vpos_write_enable_a ),
.data_a( OutData_comp_vpos_in_a ),
.address_b( OutData_comp_vpos_address_b ),
.wren_b( OutData_comp_vpos_write_enable_b ),
.data_b( OutData_comp_vpos_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( OutData_comp_vpos_out_a ),
.q_b( OutData_comp_vpos_out_b)
);
defparam OutData_comp_vpos.width_a = 32;
defparam OutData_comp_vpos.widthad_a = 2;
defparam OutData_comp_vpos.width_b = 32;
defparam OutData_comp_vpos.widthad_b = 2;
defparam OutData_comp_vpos.width_be_a = 1;
defparam OutData_comp_vpos.width_be_b = 1;
defparam OutData_comp_vpos.numwords_a = 3;
defparam OutData_comp_vpos.numwords_b = 3;
defparam OutData_comp_vpos.init_file = "OutData_comp_vpos.mif";
reg [1:0] OutData_comp_hpos_address_a;
reg OutData_comp_hpos_write_enable_a;
reg [31:0] OutData_comp_hpos_in_a;
wire [31:0] OutData_comp_hpos_out_a;
reg [1:0] OutData_comp_hpos_address_b;
reg OutData_comp_hpos_write_enable_b;
reg [31:0] OutData_comp_hpos_in_b;
wire [31:0] OutData_comp_hpos_out_b;
// @OutData_comp_hpos = internal global [3 x i32] zeroinitializer, align 4
ram_two_ports OutData_comp_hpos (
.clk( clk ),
.address_a( OutData_comp_hpos_address_a ),
.wren_a( OutData_comp_hpos_write_enable_a ),
.data_a( OutData_comp_hpos_in_a ),
.address_b( OutData_comp_hpos_address_b ),
.wren_b( OutData_comp_hpos_write_enable_b ),
.data_b( OutData_comp_hpos_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( OutData_comp_hpos_out_a ),
.q_b( OutData_comp_hpos_out_b)
);
defparam OutData_comp_hpos.width_a = 32;
defparam OutData_comp_hpos.widthad_a = 2;
defparam OutData_comp_hpos.width_b = 32;
defparam OutData_comp_hpos.widthad_b = 2;
defparam OutData_comp_hpos.width_be_a = 1;
defparam OutData_comp_hpos.width_be_b = 1;
defparam OutData_comp_hpos.numwords_a = 3;
defparam OutData_comp_hpos.numwords_b = 3;
defparam OutData_comp_hpos.init_file = "OutData_comp_hpos.mif";
reg [12:0] JpegFileBuf_address_a;
reg JpegFileBuf_write_enable_a;
reg [7:0] JpegFileBuf_in_a;
wire [7:0] JpegFileBuf_out_a;
reg [12:0] JpegFileBuf_address_b;
reg JpegFileBuf_write_enable_b;
reg [7:0] JpegFileBuf_in_b;
wire [7:0] JpegFileBuf_out_b;
// @JpegFileBuf = internal global [5310 x i8] zeroinitializer, align 1
ram_two_ports JpegFileBuf (
.clk( clk ),
.address_a( JpegFileBuf_address_a ),
.wren_a( JpegFileBuf_write_enable_a ),
.data_a( JpegFileBuf_in_a ),
.address_b( JpegFileBuf_address_b ),
.wren_b( JpegFileBuf_write_enable_b ),
.data_b( JpegFileBuf_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( JpegFileBuf_out_a ),
.q_b( JpegFileBuf_out_b)
);
defparam JpegFileBuf.width_a = 8;
defparam JpegFileBuf.widthad_a = 13;
defparam JpegFileBuf.width_b = 8;
defparam JpegFileBuf.widthad_b = 13;
defparam JpegFileBuf.width_be_a = 1;
defparam JpegFileBuf.width_be_b = 1;
defparam JpegFileBuf.numwords_a = 5310;
defparam JpegFileBuf.numwords_b = 5310;
defparam JpegFileBuf.init_file = "JpegFileBuf.mif";
reg [5:0] decode_block_0_QuantBuff_address_a;
reg decode_block_0_QuantBuff_write_enable_a;
reg [31:0] decode_block_0_QuantBuff_in_a;
wire [31:0] decode_block_0_QuantBuff_out_a;
reg [5:0] decode_block_0_QuantBuff_address_b;
reg decode_block_0_QuantBuff_write_enable_b;
reg [31:0] decode_block_0_QuantBuff_in_b;
wire [31:0] decode_block_0_QuantBuff_out_b;
// %QuantBuff = alloca [64 x i32], align 4
ram_two_ports decode_block_0_QuantBuff (
.clk( clk ),
.address_a( decode_block_0_QuantBuff_address_a ),
.wren_a( decode_block_0_QuantBuff_write_enable_a ),
.data_a( decode_block_0_QuantBuff_in_a ),
.address_b( decode_block_0_QuantBuff_address_b ),
.wren_b( decode_block_0_QuantBuff_write_enable_b ),
.data_b( decode_block_0_QuantBuff_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( decode_block_0_QuantBuff_out_a ),
.q_b( decode_block_0_QuantBuff_out_b)
);
defparam decode_block_0_QuantBuff.width_a = 32;
defparam decode_block_0_QuantBuff.widthad_a = 6;
defparam decode_block_0_QuantBuff.width_b = 32;
defparam decode_block_0_QuantBuff.widthad_b = 6;
defparam decode_block_0_QuantBuff.width_be_a = 1;
defparam decode_block_0_QuantBuff.width_be_b = 1;
defparam decode_block_0_QuantBuff.numwords_a = 64;
defparam decode_block_0_QuantBuff.numwords_b = 64;
reg [8:0] huff_make_dhuff_tb_0_huffsize_address_a;
reg huff_make_dhuff_tb_0_huffsize_write_enable_a;
reg [31:0] huff_make_dhuff_tb_0_huffsize_in_a;
wire [31:0] huff_make_dhuff_tb_0_huffsize_out_a;
reg [8:0] huff_make_dhuff_tb_0_huffsize_address_b;
reg huff_make_dhuff_tb_0_huffsize_write_enable_b;
reg [31:0] huff_make_dhuff_tb_0_huffsize_in_b;
wire [31:0] huff_make_dhuff_tb_0_huffsize_out_b;
// %huffsize = alloca [257 x i32], align 4
ram_two_ports huff_make_dhuff_tb_0_huffsize (
.clk( clk ),
.address_a( huff_make_dhuff_tb_0_huffsize_address_a ),
.wren_a( huff_make_dhuff_tb_0_huffsize_write_enable_a ),
.data_a( huff_make_dhuff_tb_0_huffsize_in_a ),
.address_b( huff_make_dhuff_tb_0_huffsize_address_b ),
.wren_b( huff_make_dhuff_tb_0_huffsize_write_enable_b ),
.data_b( huff_make_dhuff_tb_0_huffsize_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( huff_make_dhuff_tb_0_huffsize_out_a ),
.q_b( huff_make_dhuff_tb_0_huffsize_out_b)
);
defparam huff_make_dhuff_tb_0_huffsize.width_a = 32;
defparam huff_make_dhuff_tb_0_huffsize.widthad_a = 9;
defparam huff_make_dhuff_tb_0_huffsize.width_b = 32;
defparam huff_make_dhuff_tb_0_huffsize.widthad_b = 9;
defparam huff_make_dhuff_tb_0_huffsize.width_be_a = 1;
defparam huff_make_dhuff_tb_0_huffsize.width_be_b = 1;
defparam huff_make_dhuff_tb_0_huffsize.numwords_a = 257;
defparam huff_make_dhuff_tb_0_huffsize.numwords_b = 257;
reg [8:0] huff_make_dhuff_tb_0_huffcode_address_a;
reg huff_make_dhuff_tb_0_huffcode_write_enable_a;
reg [31:0] huff_make_dhuff_tb_0_huffcode_in_a;
wire [31:0] huff_make_dhuff_tb_0_huffcode_out_a;
reg [8:0] huff_make_dhuff_tb_0_huffcode_address_b;
reg huff_make_dhuff_tb_0_huffcode_write_enable_b;
reg [31:0] huff_make_dhuff_tb_0_huffcode_in_b;
wire [31:0] huff_make_dhuff_tb_0_huffcode_out_b;
// %huffcode = alloca [257 x i32], align 4
ram_two_ports huff_make_dhuff_tb_0_huffcode (
.clk( clk ),
.address_a( huff_make_dhuff_tb_0_huffcode_address_a ),
.wren_a( huff_make_dhuff_tb_0_huffcode_write_enable_a ),
.data_a( huff_make_dhuff_tb_0_huffcode_in_a ),
.address_b( huff_make_dhuff_tb_0_huffcode_address_b ),
.wren_b( huff_make_dhuff_tb_0_huffcode_write_enable_b ),
.data_b( huff_make_dhuff_tb_0_huffcode_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( huff_make_dhuff_tb_0_huffcode_out_a ),
.q_b( huff_make_dhuff_tb_0_huffcode_out_b)
);
defparam huff_make_dhuff_tb_0_huffcode.width_a = 32;
defparam huff_make_dhuff_tb_0_huffcode.widthad_a = 9;
defparam huff_make_dhuff_tb_0_huffcode.width_b = 32;
defparam huff_make_dhuff_tb_0_huffcode.widthad_b = 9;
defparam huff_make_dhuff_tb_0_huffcode.width_be_a = 1;
defparam huff_make_dhuff_tb_0_huffcode.width_be_b = 1;
defparam huff_make_dhuff_tb_0_huffcode.numwords_a = 257;
defparam huff_make_dhuff_tb_0_huffcode.numwords_b = 257;
reg [7:0] main_0_HuffBuff_i_i_address_a;
reg main_0_HuffBuff_i_i_write_enable_a;
reg [31:0] main_0_HuffBuff_i_i_in_a;
wire [31:0] main_0_HuffBuff_i_i_out_a;
reg [7:0] main_0_HuffBuff_i_i_address_b;
reg main_0_HuffBuff_i_i_write_enable_b;
reg [31:0] main_0_HuffBuff_i_i_in_b;
wire [31:0] main_0_HuffBuff_i_i_out_b;
// %HuffBuff.i.i = alloca [3 x [64 x i32]], align 4
ram_two_ports main_0_HuffBuff_i_i (
.clk( clk ),
.address_a( main_0_HuffBuff_i_i_address_a ),
.wren_a( main_0_HuffBuff_i_i_write_enable_a ),
.data_a( main_0_HuffBuff_i_i_in_a ),
.address_b( main_0_HuffBuff_i_i_address_b ),
.wren_b( main_0_HuffBuff_i_i_write_enable_b ),
.data_b( main_0_HuffBuff_i_i_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( main_0_HuffBuff_i_i_out_a ),
.q_b( main_0_HuffBuff_i_i_out_b)
);
defparam main_0_HuffBuff_i_i.width_a = 32;
defparam main_0_HuffBuff_i_i.widthad_a = 8;
defparam main_0_HuffBuff_i_i.width_b = 32;
defparam main_0_HuffBuff_i_i.widthad_b = 8;
defparam main_0_HuffBuff_i_i.width_be_a = 1;
defparam main_0_HuffBuff_i_i.width_be_b = 1;
defparam main_0_HuffBuff_i_i.numwords_a = 192;
defparam main_0_HuffBuff_i_i.numwords_b = 192;
reg [8:0] main_0_IDCTBuff_i_i_address_a;
reg main_0_IDCTBuff_i_i_write_enable_a;
reg [31:0] main_0_IDCTBuff_i_i_in_a;
wire [31:0] main_0_IDCTBuff_i_i_out_a;
reg [8:0] main_0_IDCTBuff_i_i_address_b;
reg main_0_IDCTBuff_i_i_write_enable_b;
reg [31:0] main_0_IDCTBuff_i_i_in_b;
wire [31:0] main_0_IDCTBuff_i_i_out_b;
// %IDCTBuff.i.i = alloca [6 x [64 x i32]], align 4
ram_two_ports main_0_IDCTBuff_i_i (
.clk( clk ),
.address_a( main_0_IDCTBuff_i_i_address_a ),
.wren_a( main_0_IDCTBuff_i_i_write_enable_a ),
.data_a( main_0_IDCTBuff_i_i_in_a ),
.address_b( main_0_IDCTBuff_i_i_address_b ),
.wren_b( main_0_IDCTBuff_i_i_write_enable_b ),
.data_b( main_0_IDCTBuff_i_i_in_b ),
.byteena_a( 1'b1 ),
.byteena_b( 1'b1 ),
.q_a( main_0_IDCTBuff_i_i_out_a ),
.q_b( main_0_IDCTBuff_i_i_out_b)
);
defparam main_0_IDCTBuff_i_i.width_a = 32;
defparam main_0_IDCTBuff_i_i.widthad_a = 9;
defparam main_0_IDCTBuff_i_i.width_b = 32;
defparam main_0_IDCTBuff_i_i.widthad_b = 9;
defparam main_0_IDCTBuff_i_i.width_be_a = 1;
defparam main_0_IDCTBuff_i_i.width_be_b = 1;
defparam main_0_IDCTBuff_i_i.numwords_a = 384;
defparam main_0_IDCTBuff_i_i.numwords_b = 384;
wire [`MEMORY_CONTROLLER_TAG_SIZE-1:0] tag_a = memory_controller_address_a[`MEMORY_CONTROLLER_ADDR_SIZE-1:`MEMORY_CONTROLLER_ADDR_SIZE-`MEMORY_CONTROLLER_TAG_SIZE];
wire [`MEMORY_CONTROLLER_TAG_SIZE-1:0] tag_b = memory_controller_address_b[`MEMORY_CONTROLLER_ADDR_SIZE-1:`MEMORY_CONTROLLER_ADDR_SIZE-`MEMORY_CONTROLLER_TAG_SIZE];
reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag_a;
reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag_b;
reg [2:0] prevAddr_a;
reg [2:0] prevAddr_b;
reg [1:0] prevSize_a;
reg [1:0] prevSize_b;
reg [2:0] prevSize_a_and;
reg [2:0] prevSize_b_and;
always @(posedge clk)
begin
prevTag_a <= tag_a;
prevTag_b <= tag_b;
prevAddr_a <= memory_controller_address_a[2:0];
prevAddr_b <= memory_controller_address_b[2:0];
prevSize_a <= memory_controller_size_a;
prevSize_b <= memory_controller_size_b;
end
reg [2:0] select_not_struct_a;
reg [2:0] select_not_struct_b;
wire select_hana_jpg_a = (tag_a ==`TAG_g_hana_jpg);
wire select_hana_jpg_b = (tag_b ==`TAG_g_hana_jpg);
reg select_hana_jpg_reg_a;
reg select_hana_jpg_reg_b;
wire [7:0] memory_controller_hana_jpg_out_a = {8{ select_hana_jpg_reg_a}} & hana_jpg_out_a;
wire [7:0] memory_controller_hana_jpg_out_b = {8{ select_hana_jpg_reg_b}} & hana_jpg_out_b;
wire select_hana_bmp_a = (tag_a ==`TAG_g_hana_bmp);
wire select_hana_bmp_b = (tag_b ==`TAG_g_hana_bmp);
reg select_hana_bmp_reg_a;
reg select_hana_bmp_reg_b;
wire [7:0] memory_controller_hana_bmp_out_a = {8{ select_hana_bmp_reg_a}} & hana_bmp_out_a;
wire [7:0] memory_controller_hana_bmp_out_b = {8{ select_hana_bmp_reg_b}} & hana_bmp_out_b;
wire select_out_unread_marker_a = (tag_a ==`TAG_g_out_unread_marker);
wire select_out_unread_marker_b = (tag_b ==`TAG_g_out_unread_marker);
reg select_out_unread_marker_reg_a;
reg select_out_unread_marker_reg_b;
wire [31:0] memory_controller_out_unread_marker_out_a = {32{ select_out_unread_marker_reg_a}} & out_unread_marker_out_a;
wire [31:0] memory_controller_out_unread_marker_out_b = {32{ select_out_unread_marker_reg_b}} & out_unread_marker_out_b;
wire select_out_index_get_sof_a = (tag_a ==`TAG_g_out_index_get_sof);
wire select_out_index_get_sof_b = (tag_b ==`TAG_g_out_index_get_sof);
reg select_out_index_get_sof_reg_a;
reg select_out_index_get_sof_reg_b;
wire [31:0] memory_controller_out_index_get_sof_out_a = {32{ select_out_index_get_sof_reg_a}} & out_index_get_sof_out_a;
wire [31:0] memory_controller_out_index_get_sof_out_b = {32{ select_out_index_get_sof_reg_b}} & out_index_get_sof_out_b;
wire select_out_v_samp_factor_get_sof_a = (tag_a ==`TAG_g_out_v_samp_factor_get_sof);
wire select_out_v_samp_factor_get_sof_b = (tag_b ==`TAG_g_out_v_samp_factor_get_sof);
reg select_out_v_samp_factor_get_sof_reg_a;
reg select_out_v_samp_factor_get_sof_reg_b;
wire [31:0] memory_controller_out_v_samp_factor_get_sof_out_a = {32{ select_out_v_samp_factor_get_sof_reg_a}} & out_v_samp_factor_get_sof_out_a;
wire [31:0] memory_controller_out_v_samp_factor_get_sof_out_b = {32{ select_out_v_samp_factor_get_sof_reg_b}} & out_v_samp_factor_get_sof_out_b;
wire select_out_comp_id_get_sos_a = (tag_a ==`TAG_g_out_comp_id_get_sos);
wire select_out_comp_id_get_sos_b = (tag_b ==`TAG_g_out_comp_id_get_sos);
reg select_out_comp_id_get_sos_reg_a;
reg select_out_comp_id_get_sos_reg_b;
wire [31:0] memory_controller_out_comp_id_get_sos_out_a = {32{ select_out_comp_id_get_sos_reg_a}} & out_comp_id_get_sos_out_a;
wire [31:0] memory_controller_out_comp_id_get_sos_out_b = {32{ select_out_comp_id_get_sos_reg_b}} & out_comp_id_get_sos_out_b;
wire select_out_ac_tbl_no_get_sos_a = (tag_a ==`TAG_g_out_ac_tbl_no_get_sos);
wire select_out_ac_tbl_no_get_sos_b = (tag_b ==`TAG_g_out_ac_tbl_no_get_sos);
reg select_out_ac_tbl_no_get_sos_reg_a;
reg select_out_ac_tbl_no_get_sos_reg_b;
wire [31:0] memory_controller_out_ac_tbl_no_get_sos_out_a = {32{ select_out_ac_tbl_no_get_sos_reg_a}} & out_ac_tbl_no_get_sos_out_a;
wire [31:0] memory_controller_out_ac_tbl_no_get_sos_out_b = {32{ select_out_ac_tbl_no_get_sos_reg_b}} & out_ac_tbl_no_get_sos_out_b;
wire select_out_length_get_dht_a = (tag_a ==`TAG_g_out_length_get_dht);
wire select_out_length_get_dht_b = (tag_b ==`TAG_g_out_length_get_dht);
reg select_out_length_get_dht_reg_a;
reg select_out_length_get_dht_reg_b;
wire [31:0] memory_controller_out_length_get_dht_out_a = {32{ select_out_length_get_dht_reg_a}} & out_length_get_dht_out_a;
wire [31:0] memory_controller_out_length_get_dht_out_b = {32{ select_out_length_get_dht_reg_b}} & out_length_get_dht_out_b;
wire select_out_index_get_dht_a = (tag_a ==`TAG_g_out_index_get_dht);
wire select_out_index_get_dht_b = (tag_b ==`TAG_g_out_index_get_dht);
reg select_out_index_get_dht_reg_a;
reg select_out_index_get_dht_reg_b;
wire [31:0] memory_controller_out_index_get_dht_out_a = {32{ select_out_index_get_dht_reg_a}} & out_index_get_dht_out_a;
wire [31:0] memory_controller_out_index_get_dht_out_b = {32{ select_out_index_get_dht_reg_b}} & out_index_get_dht_out_b;
wire select_out_count_get_dht_a = (tag_a ==`TAG_g_out_count_get_dht);
wire select_out_count_get_dht_b = (tag_b ==`TAG_g_out_count_get_dht);
reg select_out_count_get_dht_reg_a;
reg select_out_count_get_dht_reg_b;
wire [31:0] memory_controller_out_count_get_dht_out_a = {32{ select_out_count_get_dht_reg_a}} & out_count_get_dht_out_a;
wire [31:0] memory_controller_out_count_get_dht_out_b = {32{ select_out_count_get_dht_reg_b}} & out_count_get_dht_out_b;
wire select_out_length_get_dqt_a = (tag_a ==`TAG_g_out_length_get_dqt);
wire select_out_length_get_dqt_b = (tag_b ==`TAG_g_out_length_get_dqt);
reg select_out_length_get_dqt_reg_a;
reg select_out_length_get_dqt_reg_b;
wire [31:0] memory_controller_out_length_get_dqt_out_a = {32{ select_out_length_get_dqt_reg_a}} & out_length_get_dqt_out_a;
wire [31:0] memory_controller_out_length_get_dqt_out_b = {32{ select_out_length_get_dqt_reg_b}} & out_length_get_dqt_out_b;
wire select_out_prec_get_dht_a = (tag_a ==`TAG_g_out_prec_get_dht);
wire select_out_prec_get_dht_b = (tag_b ==`TAG_g_out_prec_get_dht);
reg select_out_prec_get_dht_reg_a;
reg select_out_prec_get_dht_reg_b;
wire [31:0] memory_controller_out_prec_get_dht_out_a = {32{ select_out_prec_get_dht_reg_a}} & out_prec_get_dht_out_a;
wire [31:0] memory_controller_out_prec_get_dht_out_b = {32{ select_out_prec_get_dht_reg_b}} & out_prec_get_dht_out_b;
wire select_out_num_get_dht_a = (tag_a ==`TAG_g_out_num_get_dht);
wire select_out_num_get_dht_b = (tag_b ==`TAG_g_out_num_get_dht);
reg select_out_num_get_dht_reg_a;
reg select_out_num_get_dht_reg_b;
wire [31:0] memory_controller_out_num_get_dht_out_a = {32{ select_out_num_get_dht_reg_a}} & out_num_get_dht_out_a;
wire [31:0] memory_controller_out_num_get_dht_out_b = {32{ select_out_num_get_dht_reg_b}} & out_num_get_dht_out_b;
wire select_izigzag_index_a = (tag_a ==`TAG_g_izigzag_index);
wire select_izigzag_index_b = (tag_b ==`TAG_g_izigzag_index);
reg select_izigzag_index_reg_a;
reg select_izigzag_index_reg_b;
wire [31:0] memory_controller_izigzag_index_out_a = {32{ select_izigzag_index_reg_a}} & izigzag_index_out_a;
wire [31:0] memory_controller_izigzag_index_out_b = {32{ select_izigzag_index_reg_b}} & izigzag_index_out_b;
wire select_main_result_a = (tag_a ==`TAG_g_main_result);
wire select_main_result_b = (tag_b ==`TAG_g_main_result);
reg select_main_result_reg_a;
reg select_main_result_reg_b;
wire [31:0] memory_controller_main_result_out_a = {32{ select_main_result_reg_a}} & main_result_out_a;
wire [31:0] memory_controller_main_result_out_b = {32{ select_main_result_reg_b}} & main_result_out_b;
wire select_p_jinfo_image_height_a = (tag_a ==`TAG_g_p_jinfo_image_height);
wire select_p_jinfo_image_height_b = (tag_b ==`TAG_g_p_jinfo_image_height);
reg select_p_jinfo_image_height_reg_a;
reg select_p_jinfo_image_height_reg_b;
wire [15:0] memory_controller_p_jinfo_image_height_out_a = {16{ select_p_jinfo_image_height_reg_a}} & p_jinfo_image_height_out_a;
wire [15:0] memory_controller_p_jinfo_image_height_out_b = {16{ select_p_jinfo_image_height_reg_b}} & p_jinfo_image_height_out_b;
wire select_p_jinfo_image_width_a = (tag_a ==`TAG_g_p_jinfo_image_width);
wire select_p_jinfo_image_width_b = (tag_b ==`TAG_g_p_jinfo_image_width);
reg select_p_jinfo_image_width_reg_a;
reg select_p_jinfo_image_width_reg_b;
wire [15:0] memory_controller_p_jinfo_image_width_out_a = {16{ select_p_jinfo_image_width_reg_a}} & p_jinfo_image_width_out_a;
wire [15:0] memory_controller_p_jinfo_image_width_out_b = {16{ select_p_jinfo_image_width_reg_b}} & p_jinfo_image_width_out_b;
wire select_p_jinfo_comps_info_index_a = (tag_a ==`TAG_g_p_jinfo_comps_info_index);
wire select_p_jinfo_comps_info_index_b = (tag_b ==`TAG_g_p_jinfo_comps_info_index);
reg select_p_jinfo_comps_info_index_reg_a;
reg select_p_jinfo_comps_info_index_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_index_out_a = {8{ select_p_jinfo_comps_info_index_reg_a}} & p_jinfo_comps_info_index_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_index_out_b = {8{ select_p_jinfo_comps_info_index_reg_b}} & p_jinfo_comps_info_index_out_b;
wire select_p_jinfo_comps_info_id_a = (tag_a ==`TAG_g_p_jinfo_comps_info_id);
wire select_p_jinfo_comps_info_id_b = (tag_b ==`TAG_g_p_jinfo_comps_info_id);
reg select_p_jinfo_comps_info_id_reg_a;
reg select_p_jinfo_comps_info_id_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_id_out_a = {8{ select_p_jinfo_comps_info_id_reg_a}} & p_jinfo_comps_info_id_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_id_out_b = {8{ select_p_jinfo_comps_info_id_reg_b}} & p_jinfo_comps_info_id_out_b;
wire select_p_jinfo_comps_info_h_samp_factor_a = (tag_a ==`TAG_g_p_jinfo_comps_info_h_samp_factor);
wire select_p_jinfo_comps_info_h_samp_factor_b = (tag_b ==`TAG_g_p_jinfo_comps_info_h_samp_factor);
reg select_p_jinfo_comps_info_h_samp_factor_reg_a;
reg select_p_jinfo_comps_info_h_samp_factor_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_h_samp_factor_out_a = {8{ select_p_jinfo_comps_info_h_samp_factor_reg_a}} & p_jinfo_comps_info_h_samp_factor_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_h_samp_factor_out_b = {8{ select_p_jinfo_comps_info_h_samp_factor_reg_b}} & p_jinfo_comps_info_h_samp_factor_out_b;
wire select_p_jinfo_comps_info_v_samp_factor_a = (tag_a ==`TAG_g_p_jinfo_comps_info_v_samp_factor);
wire select_p_jinfo_comps_info_v_samp_factor_b = (tag_b ==`TAG_g_p_jinfo_comps_info_v_samp_factor);
reg select_p_jinfo_comps_info_v_samp_factor_reg_a;
reg select_p_jinfo_comps_info_v_samp_factor_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_v_samp_factor_out_a = {8{ select_p_jinfo_comps_info_v_samp_factor_reg_a}} & p_jinfo_comps_info_v_samp_factor_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_v_samp_factor_out_b = {8{ select_p_jinfo_comps_info_v_samp_factor_reg_b}} & p_jinfo_comps_info_v_samp_factor_out_b;
wire select_p_jinfo_comps_info_quant_tbl_no_a = (tag_a ==`TAG_g_p_jinfo_comps_info_quant_tbl_no);
wire select_p_jinfo_comps_info_quant_tbl_no_b = (tag_b ==`TAG_g_p_jinfo_comps_info_quant_tbl_no);
reg select_p_jinfo_comps_info_quant_tbl_no_reg_a;
reg select_p_jinfo_comps_info_quant_tbl_no_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_quant_tbl_no_out_a = {8{ select_p_jinfo_comps_info_quant_tbl_no_reg_a}} & p_jinfo_comps_info_quant_tbl_no_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_quant_tbl_no_out_b = {8{ select_p_jinfo_comps_info_quant_tbl_no_reg_b}} & p_jinfo_comps_info_quant_tbl_no_out_b;
wire select_p_jinfo_comps_info_dc_tbl_no_a = (tag_a ==`TAG_g_p_jinfo_comps_info_dc_tbl_no);
wire select_p_jinfo_comps_info_dc_tbl_no_b = (tag_b ==`TAG_g_p_jinfo_comps_info_dc_tbl_no);
reg select_p_jinfo_comps_info_dc_tbl_no_reg_a;
reg select_p_jinfo_comps_info_dc_tbl_no_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_dc_tbl_no_out_a = {8{ select_p_jinfo_comps_info_dc_tbl_no_reg_a}} & p_jinfo_comps_info_dc_tbl_no_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_dc_tbl_no_out_b = {8{ select_p_jinfo_comps_info_dc_tbl_no_reg_b}} & p_jinfo_comps_info_dc_tbl_no_out_b;
wire select_p_jinfo_comps_info_ac_tbl_no_a = (tag_a ==`TAG_g_p_jinfo_comps_info_ac_tbl_no);
wire select_p_jinfo_comps_info_ac_tbl_no_b = (tag_b ==`TAG_g_p_jinfo_comps_info_ac_tbl_no);
reg select_p_jinfo_comps_info_ac_tbl_no_reg_a;
reg select_p_jinfo_comps_info_ac_tbl_no_reg_b;
wire [7:0] memory_controller_p_jinfo_comps_info_ac_tbl_no_out_a = {8{ select_p_jinfo_comps_info_ac_tbl_no_reg_a}} & p_jinfo_comps_info_ac_tbl_no_out_a;
wire [7:0] memory_controller_p_jinfo_comps_info_ac_tbl_no_out_b = {8{ select_p_jinfo_comps_info_ac_tbl_no_reg_b}} & p_jinfo_comps_info_ac_tbl_no_out_b;
wire select_p_jinfo_ac_xhuff_tbl_bits_a = (tag_a ==`TAG_g_p_jinfo_ac_xhuff_tbl_bits);
wire select_p_jinfo_ac_xhuff_tbl_bits_b = (tag_b ==`TAG_g_p_jinfo_ac_xhuff_tbl_bits);
reg select_p_jinfo_ac_xhuff_tbl_bits_reg_a;
reg select_p_jinfo_ac_xhuff_tbl_bits_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_xhuff_tbl_bits_out_a = {32{ select_p_jinfo_ac_xhuff_tbl_bits_reg_a}} & p_jinfo_ac_xhuff_tbl_bits_out_a;
wire [31:0] memory_controller_p_jinfo_ac_xhuff_tbl_bits_out_b = {32{ select_p_jinfo_ac_xhuff_tbl_bits_reg_b}} & p_jinfo_ac_xhuff_tbl_bits_out_b;
wire select_p_jinfo_ac_xhuff_tbl_huffval_a = (tag_a ==`TAG_g_p_jinfo_ac_xhuff_tbl_huffval);
wire select_p_jinfo_ac_xhuff_tbl_huffval_b = (tag_b ==`TAG_g_p_jinfo_ac_xhuff_tbl_huffval);
reg select_p_jinfo_ac_xhuff_tbl_huffval_reg_a;
reg select_p_jinfo_ac_xhuff_tbl_huffval_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_xhuff_tbl_huffval_out_a = {32{ select_p_jinfo_ac_xhuff_tbl_huffval_reg_a}} & p_jinfo_ac_xhuff_tbl_huffval_out_a;
wire [31:0] memory_controller_p_jinfo_ac_xhuff_tbl_huffval_out_b = {32{ select_p_jinfo_ac_xhuff_tbl_huffval_reg_b}} & p_jinfo_ac_xhuff_tbl_huffval_out_b;
wire select_p_jinfo_dc_xhuff_tbl_bits_a = (tag_a ==`TAG_g_p_jinfo_dc_xhuff_tbl_bits);
wire select_p_jinfo_dc_xhuff_tbl_bits_b = (tag_b ==`TAG_g_p_jinfo_dc_xhuff_tbl_bits);
reg select_p_jinfo_dc_xhuff_tbl_bits_reg_a;
reg select_p_jinfo_dc_xhuff_tbl_bits_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_xhuff_tbl_bits_out_a = {32{ select_p_jinfo_dc_xhuff_tbl_bits_reg_a}} & p_jinfo_dc_xhuff_tbl_bits_out_a;
wire [31:0] memory_controller_p_jinfo_dc_xhuff_tbl_bits_out_b = {32{ select_p_jinfo_dc_xhuff_tbl_bits_reg_b}} & p_jinfo_dc_xhuff_tbl_bits_out_b;
wire select_p_jinfo_dc_xhuff_tbl_huffval_a = (tag_a ==`TAG_g_p_jinfo_dc_xhuff_tbl_huffval);
wire select_p_jinfo_dc_xhuff_tbl_huffval_b = (tag_b ==`TAG_g_p_jinfo_dc_xhuff_tbl_huffval);
reg select_p_jinfo_dc_xhuff_tbl_huffval_reg_a;
reg select_p_jinfo_dc_xhuff_tbl_huffval_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_xhuff_tbl_huffval_out_a = {32{ select_p_jinfo_dc_xhuff_tbl_huffval_reg_a}} & p_jinfo_dc_xhuff_tbl_huffval_out_a;
wire [31:0] memory_controller_p_jinfo_dc_xhuff_tbl_huffval_out_b = {32{ select_p_jinfo_dc_xhuff_tbl_huffval_reg_b}} & p_jinfo_dc_xhuff_tbl_huffval_out_b;
wire select_p_jinfo_quant_tbl_quantval_a = (tag_a ==`TAG_g_p_jinfo_quant_tbl_quantval);
wire select_p_jinfo_quant_tbl_quantval_b = (tag_b ==`TAG_g_p_jinfo_quant_tbl_quantval);
reg select_p_jinfo_quant_tbl_quantval_reg_a;
reg select_p_jinfo_quant_tbl_quantval_reg_b;
wire [31:0] memory_controller_p_jinfo_quant_tbl_quantval_out_a = {32{ select_p_jinfo_quant_tbl_quantval_reg_a}} & p_jinfo_quant_tbl_quantval_out_a;
wire [31:0] memory_controller_p_jinfo_quant_tbl_quantval_out_b = {32{ select_p_jinfo_quant_tbl_quantval_reg_b}} & p_jinfo_quant_tbl_quantval_out_b;
wire select_zigzag_index_a = (tag_a ==`TAG_g_zigzag_index);
wire select_zigzag_index_b = (tag_b ==`TAG_g_zigzag_index);
reg select_zigzag_index_reg_a;
reg select_zigzag_index_reg_b;
wire [31:0] memory_controller_zigzag_index_out_a = {32{ select_zigzag_index_reg_a}} & zigzag_index_out_a;
wire [31:0] memory_controller_zigzag_index_out_b = {32{ select_zigzag_index_reg_b}} & zigzag_index_out_b;
wire select_p_jinfo_MCUWidth_a = (tag_a ==`TAG_g_p_jinfo_MCUWidth);
wire select_p_jinfo_MCUWidth_b = (tag_b ==`TAG_g_p_jinfo_MCUWidth);
reg select_p_jinfo_MCUWidth_reg_a;
reg select_p_jinfo_MCUWidth_reg_b;
wire [31:0] memory_controller_p_jinfo_MCUWidth_out_a = {32{ select_p_jinfo_MCUWidth_reg_a}} & p_jinfo_MCUWidth_out_a;
wire [31:0] memory_controller_p_jinfo_MCUWidth_out_b = {32{ select_p_jinfo_MCUWidth_reg_b}} & p_jinfo_MCUWidth_out_b;
wire select_rgb_buf_a = (tag_a ==`TAG_g_rgb_buf);
wire select_rgb_buf_b = (tag_b ==`TAG_g_rgb_buf);
reg select_rgb_buf_reg_a;
reg select_rgb_buf_reg_b;
wire [31:0] memory_controller_rgb_buf_out_a = {32{ select_rgb_buf_reg_a}} & rgb_buf_out_a;
wire [31:0] memory_controller_rgb_buf_out_b = {32{ select_rgb_buf_reg_b}} & rgb_buf_out_b;
wire select_CurHuffReadBuf_a = (tag_a ==`TAG_g_CurHuffReadBuf);
wire select_CurHuffReadBuf_b = (tag_b ==`TAG_g_CurHuffReadBuf);
reg select_CurHuffReadBuf_reg_a;
reg select_CurHuffReadBuf_reg_b;
wire [31:0] memory_controller_CurHuffReadBuf_out_a = {32{ select_CurHuffReadBuf_reg_a}} & CurHuffReadBuf_out_a;
wire [31:0] memory_controller_CurHuffReadBuf_out_b = {32{ select_CurHuffReadBuf_reg_b}} & CurHuffReadBuf_out_b;
wire select_OutData_comp_buf_a = (tag_a ==`TAG_g_OutData_comp_buf);
wire select_OutData_comp_buf_b = (tag_b ==`TAG_g_OutData_comp_buf);
reg select_OutData_comp_buf_reg_a;
reg select_OutData_comp_buf_reg_b;
wire [7:0] memory_controller_OutData_comp_buf_out_a = {8{ select_OutData_comp_buf_reg_a}} & OutData_comp_buf_out_a;
wire [7:0] memory_controller_OutData_comp_buf_out_b = {8{ select_OutData_comp_buf_reg_b}} & OutData_comp_buf_out_b;
wire select_bit_set_mask_a = (tag_a ==`TAG_g_bit_set_mask);
wire select_bit_set_mask_b = (tag_b ==`TAG_g_bit_set_mask);
reg select_bit_set_mask_reg_a;
reg select_bit_set_mask_reg_b;
wire [31:0] memory_controller_bit_set_mask_out_a = {32{ select_bit_set_mask_reg_a}} & bit_set_mask_out_a;
wire [31:0] memory_controller_bit_set_mask_out_b = {32{ select_bit_set_mask_reg_b}} & bit_set_mask_out_b;
wire select_lmask_a = (tag_a ==`TAG_g_lmask);
wire select_lmask_b = (tag_b ==`TAG_g_lmask);
reg select_lmask_reg_a;
reg select_lmask_reg_b;
wire [31:0] memory_controller_lmask_out_a = {32{ select_lmask_reg_a}} & lmask_out_a;
wire [31:0] memory_controller_lmask_out_b = {32{ select_lmask_reg_b}} & lmask_out_b;
wire select_read_position_a = (tag_a ==`TAG_g_read_position);
wire select_read_position_b = (tag_b ==`TAG_g_read_position);
reg select_read_position_reg_a;
reg select_read_position_reg_b;
wire [31:0] memory_controller_read_position_out_a = {32{ select_read_position_reg_a}} & read_position_out_a;
wire [31:0] memory_controller_read_position_out_b = {32{ select_read_position_reg_b}} & read_position_out_b;
wire select_current_read_byte_a = (tag_a ==`TAG_g_current_read_byte);
wire select_current_read_byte_b = (tag_b ==`TAG_g_current_read_byte);
reg select_current_read_byte_reg_a;
reg select_current_read_byte_reg_b;
wire [31:0] memory_controller_current_read_byte_out_a = {32{ select_current_read_byte_reg_a}} & current_read_byte_out_a;
wire [31:0] memory_controller_current_read_byte_out_b = {32{ select_current_read_byte_reg_b}} & current_read_byte_out_b;
wire select_p_jinfo_dc_dhuff_tbl_ml_a = (tag_a ==`TAG_g_p_jinfo_dc_dhuff_tbl_ml);
wire select_p_jinfo_dc_dhuff_tbl_ml_b = (tag_b ==`TAG_g_p_jinfo_dc_dhuff_tbl_ml);
reg select_p_jinfo_dc_dhuff_tbl_ml_reg_a;
reg select_p_jinfo_dc_dhuff_tbl_ml_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_ml_out_a = {32{ select_p_jinfo_dc_dhuff_tbl_ml_reg_a}} & p_jinfo_dc_dhuff_tbl_ml_out_a;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_ml_out_b = {32{ select_p_jinfo_dc_dhuff_tbl_ml_reg_b}} & p_jinfo_dc_dhuff_tbl_ml_out_b;
wire select_p_jinfo_dc_dhuff_tbl_maxcode_a = (tag_a ==`TAG_g_p_jinfo_dc_dhuff_tbl_maxcode);
wire select_p_jinfo_dc_dhuff_tbl_maxcode_b = (tag_b ==`TAG_g_p_jinfo_dc_dhuff_tbl_maxcode);
reg select_p_jinfo_dc_dhuff_tbl_maxcode_reg_a;
reg select_p_jinfo_dc_dhuff_tbl_maxcode_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_maxcode_out_a = {32{ select_p_jinfo_dc_dhuff_tbl_maxcode_reg_a}} & p_jinfo_dc_dhuff_tbl_maxcode_out_a;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_maxcode_out_b = {32{ select_p_jinfo_dc_dhuff_tbl_maxcode_reg_b}} & p_jinfo_dc_dhuff_tbl_maxcode_out_b;
wire select_p_jinfo_dc_dhuff_tbl_mincode_a = (tag_a ==`TAG_g_p_jinfo_dc_dhuff_tbl_mincode);
wire select_p_jinfo_dc_dhuff_tbl_mincode_b = (tag_b ==`TAG_g_p_jinfo_dc_dhuff_tbl_mincode);
reg select_p_jinfo_dc_dhuff_tbl_mincode_reg_a;
reg select_p_jinfo_dc_dhuff_tbl_mincode_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_mincode_out_a = {32{ select_p_jinfo_dc_dhuff_tbl_mincode_reg_a}} & p_jinfo_dc_dhuff_tbl_mincode_out_a;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_mincode_out_b = {32{ select_p_jinfo_dc_dhuff_tbl_mincode_reg_b}} & p_jinfo_dc_dhuff_tbl_mincode_out_b;
wire select_p_jinfo_dc_dhuff_tbl_valptr_a = (tag_a ==`TAG_g_p_jinfo_dc_dhuff_tbl_valptr);
wire select_p_jinfo_dc_dhuff_tbl_valptr_b = (tag_b ==`TAG_g_p_jinfo_dc_dhuff_tbl_valptr);
reg select_p_jinfo_dc_dhuff_tbl_valptr_reg_a;
reg select_p_jinfo_dc_dhuff_tbl_valptr_reg_b;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_valptr_out_a = {32{ select_p_jinfo_dc_dhuff_tbl_valptr_reg_a}} & p_jinfo_dc_dhuff_tbl_valptr_out_a;
wire [31:0] memory_controller_p_jinfo_dc_dhuff_tbl_valptr_out_b = {32{ select_p_jinfo_dc_dhuff_tbl_valptr_reg_b}} & p_jinfo_dc_dhuff_tbl_valptr_out_b;
wire select_extend_mask_a = (tag_a ==`TAG_g_extend_mask);
wire select_extend_mask_b = (tag_b ==`TAG_g_extend_mask);
reg select_extend_mask_reg_a;
reg select_extend_mask_reg_b;
wire [31:0] memory_controller_extend_mask_out_a = {32{ select_extend_mask_reg_a}} & extend_mask_out_a;
wire [31:0] memory_controller_extend_mask_out_b = {32{ select_extend_mask_reg_b}} & extend_mask_out_b;
wire select_p_jinfo_ac_dhuff_tbl_ml_a = (tag_a ==`TAG_g_p_jinfo_ac_dhuff_tbl_ml);
wire select_p_jinfo_ac_dhuff_tbl_ml_b = (tag_b ==`TAG_g_p_jinfo_ac_dhuff_tbl_ml);
reg select_p_jinfo_ac_dhuff_tbl_ml_reg_a;
reg select_p_jinfo_ac_dhuff_tbl_ml_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_ml_out_a = {32{ select_p_jinfo_ac_dhuff_tbl_ml_reg_a}} & p_jinfo_ac_dhuff_tbl_ml_out_a;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_ml_out_b = {32{ select_p_jinfo_ac_dhuff_tbl_ml_reg_b}} & p_jinfo_ac_dhuff_tbl_ml_out_b;
wire select_p_jinfo_ac_dhuff_tbl_maxcode_a = (tag_a ==`TAG_g_p_jinfo_ac_dhuff_tbl_maxcode);
wire select_p_jinfo_ac_dhuff_tbl_maxcode_b = (tag_b ==`TAG_g_p_jinfo_ac_dhuff_tbl_maxcode);
reg select_p_jinfo_ac_dhuff_tbl_maxcode_reg_a;
reg select_p_jinfo_ac_dhuff_tbl_maxcode_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_maxcode_out_a = {32{ select_p_jinfo_ac_dhuff_tbl_maxcode_reg_a}} & p_jinfo_ac_dhuff_tbl_maxcode_out_a;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_maxcode_out_b = {32{ select_p_jinfo_ac_dhuff_tbl_maxcode_reg_b}} & p_jinfo_ac_dhuff_tbl_maxcode_out_b;
wire select_p_jinfo_ac_dhuff_tbl_mincode_a = (tag_a ==`TAG_g_p_jinfo_ac_dhuff_tbl_mincode);
wire select_p_jinfo_ac_dhuff_tbl_mincode_b = (tag_b ==`TAG_g_p_jinfo_ac_dhuff_tbl_mincode);
reg select_p_jinfo_ac_dhuff_tbl_mincode_reg_a;
reg select_p_jinfo_ac_dhuff_tbl_mincode_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_mincode_out_a = {32{ select_p_jinfo_ac_dhuff_tbl_mincode_reg_a}} & p_jinfo_ac_dhuff_tbl_mincode_out_a;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_mincode_out_b = {32{ select_p_jinfo_ac_dhuff_tbl_mincode_reg_b}} & p_jinfo_ac_dhuff_tbl_mincode_out_b;
wire select_p_jinfo_ac_dhuff_tbl_valptr_a = (tag_a ==`TAG_g_p_jinfo_ac_dhuff_tbl_valptr);
wire select_p_jinfo_ac_dhuff_tbl_valptr_b = (tag_b ==`TAG_g_p_jinfo_ac_dhuff_tbl_valptr);
reg select_p_jinfo_ac_dhuff_tbl_valptr_reg_a;
reg select_p_jinfo_ac_dhuff_tbl_valptr_reg_b;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_valptr_out_a = {32{ select_p_jinfo_ac_dhuff_tbl_valptr_reg_a}} & p_jinfo_ac_dhuff_tbl_valptr_out_a;
wire [31:0] memory_controller_p_jinfo_ac_dhuff_tbl_valptr_out_b = {32{ select_p_jinfo_ac_dhuff_tbl_valptr_reg_b}} & p_jinfo_ac_dhuff_tbl_valptr_out_b;
wire select_OutData_comp_vpos_a = (tag_a ==`TAG_g_OutData_comp_vpos);
wire select_OutData_comp_vpos_b = (tag_b ==`TAG_g_OutData_comp_vpos);
reg select_OutData_comp_vpos_reg_a;
reg select_OutData_comp_vpos_reg_b;
wire [31:0] memory_controller_OutData_comp_vpos_out_a = {32{ select_OutData_comp_vpos_reg_a}} & OutData_comp_vpos_out_a;
wire [31:0] memory_controller_OutData_comp_vpos_out_b = {32{ select_OutData_comp_vpos_reg_b}} & OutData_comp_vpos_out_b;
wire select_OutData_comp_hpos_a = (tag_a ==`TAG_g_OutData_comp_hpos);
wire select_OutData_comp_hpos_b = (tag_b ==`TAG_g_OutData_comp_hpos);
reg select_OutData_comp_hpos_reg_a;
reg select_OutData_comp_hpos_reg_b;
wire [31:0] memory_controller_OutData_comp_hpos_out_a = {32{ select_OutData_comp_hpos_reg_a}} & OutData_comp_hpos_out_a;
wire [31:0] memory_controller_OutData_comp_hpos_out_b = {32{ select_OutData_comp_hpos_reg_b}} & OutData_comp_hpos_out_b;
wire select_JpegFileBuf_a = (tag_a ==`TAG_g_JpegFileBuf);
wire select_JpegFileBuf_b = (tag_b ==`TAG_g_JpegFileBuf);
reg select_JpegFileBuf_reg_a;
reg select_JpegFileBuf_reg_b;
wire [7:0] memory_controller_JpegFileBuf_out_a = {8{ select_JpegFileBuf_reg_a}} & JpegFileBuf_out_a;
wire [7:0] memory_controller_JpegFileBuf_out_b = {8{ select_JpegFileBuf_reg_b}} & JpegFileBuf_out_b;
wire select_decode_block_0_QuantBuff_a = (tag_a ==`TAG_decode_block_0_QuantBuff);
wire select_decode_block_0_QuantBuff_b = (tag_b ==`TAG_decode_block_0_QuantBuff);
reg select_decode_block_0_QuantBuff_reg_a;
reg select_decode_block_0_QuantBuff_reg_b;
wire [31:0] memory_controller_decode_block_0_QuantBuff_out_a = {32{ select_decode_block_0_QuantBuff_reg_a}} & decode_block_0_QuantBuff_out_a;
wire [31:0] memory_controller_decode_block_0_QuantBuff_out_b = {32{ select_decode_block_0_QuantBuff_reg_b}} & decode_block_0_QuantBuff_out_b;
wire select_huff_make_dhuff_tb_0_huffsize_a = (tag_a ==`TAG_huff_make_dhuff_tb_0_huffsize);
wire select_huff_make_dhuff_tb_0_huffsize_b = (tag_b ==`TAG_huff_make_dhuff_tb_0_huffsize);
reg select_huff_make_dhuff_tb_0_huffsize_reg_a;
reg select_huff_make_dhuff_tb_0_huffsize_reg_b;
wire [31:0] memory_controller_huff_make_dhuff_tb_0_huffsize_out_a = {32{ select_huff_make_dhuff_tb_0_huffsize_reg_a}} & huff_make_dhuff_tb_0_huffsize_out_a;
wire [31:0] memory_controller_huff_make_dhuff_tb_0_huffsize_out_b = {32{ select_huff_make_dhuff_tb_0_huffsize_reg_b}} & huff_make_dhuff_tb_0_huffsize_out_b;
wire select_huff_make_dhuff_tb_0_huffcode_a = (tag_a ==`TAG_huff_make_dhuff_tb_0_huffcode);
wire select_huff_make_dhuff_tb_0_huffcode_b = (tag_b ==`TAG_huff_make_dhuff_tb_0_huffcode);
reg select_huff_make_dhuff_tb_0_huffcode_reg_a;
reg select_huff_make_dhuff_tb_0_huffcode_reg_b;
wire [31:0] memory_controller_huff_make_dhuff_tb_0_huffcode_out_a = {32{ select_huff_make_dhuff_tb_0_huffcode_reg_a}} & huff_make_dhuff_tb_0_huffcode_out_a;
wire [31:0] memory_controller_huff_make_dhuff_tb_0_huffcode_out_b = {32{ select_huff_make_dhuff_tb_0_huffcode_reg_b}} & huff_make_dhuff_tb_0_huffcode_out_b;
wire select_main_0_HuffBuff_i_i_a = (tag_a ==`TAG_main_0_HuffBuff_i_i);
wire select_main_0_HuffBuff_i_i_b = (tag_b ==`TAG_main_0_HuffBuff_i_i);
reg select_main_0_HuffBuff_i_i_reg_a;
reg select_main_0_HuffBuff_i_i_reg_b;
wire [31:0] memory_controller_main_0_HuffBuff_i_i_out_a = {32{ select_main_0_HuffBuff_i_i_reg_a}} & main_0_HuffBuff_i_i_out_a;
wire [31:0] memory_controller_main_0_HuffBuff_i_i_out_b = {32{ select_main_0_HuffBuff_i_i_reg_b}} & main_0_HuffBuff_i_i_out_b;
wire select_main_0_IDCTBuff_i_i_a = (tag_a ==`TAG_main_0_IDCTBuff_i_i);
wire select_main_0_IDCTBuff_i_i_b = (tag_b ==`TAG_main_0_IDCTBuff_i_i);
reg select_main_0_IDCTBuff_i_i_reg_a;
reg select_main_0_IDCTBuff_i_i_reg_b;
wire [31:0] memory_controller_main_0_IDCTBuff_i_i_out_a = {32{ select_main_0_IDCTBuff_i_i_reg_a}} & main_0_IDCTBuff_i_i_out_a;
wire [31:0] memory_controller_main_0_IDCTBuff_i_i_out_b = {32{ select_main_0_IDCTBuff_i_i_reg_b}} & main_0_IDCTBuff_i_i_out_b;
always @(*)
begin
hana_jpg_address_a = memory_controller_address_a [13-1+0:0] & {13{select_hana_jpg_a}};
hana_jpg_address_b = memory_controller_address_b [13-1+0:0] & {13{select_hana_jpg_b}};
hana_jpg_write_enable_a = memory_controller_write_enable_a & select_hana_jpg_a;
hana_jpg_write_enable_b = memory_controller_write_enable_b & select_hana_jpg_b;
hana_jpg_in_a [8-1:0] = memory_controller_in_a[8-1:0];
hana_jpg_in_b [8-1:0] = memory_controller_in_b[8-1:0];
hana_bmp_address_a = memory_controller_address_a [14-1+0:0] & {14{select_hana_bmp_a}};
hana_bmp_address_b = memory_controller_address_b [14-1+0:0] & {14{select_hana_bmp_b}};
hana_bmp_write_enable_a = memory_controller_write_enable_a & select_hana_bmp_a;
hana_bmp_write_enable_b = memory_controller_write_enable_b & select_hana_bmp_b;
hana_bmp_in_a [8-1:0] = memory_controller_in_a[8-1:0];
hana_bmp_in_b [8-1:0] = memory_controller_in_b[8-1:0];
out_unread_marker_address_a = memory_controller_address_a [4-1+2:2] & {4{select_out_unread_marker_a}};
out_unread_marker_address_b = memory_controller_address_b [4-1+2:2] & {4{select_out_unread_marker_b}};
out_unread_marker_write_enable_a = memory_controller_write_enable_a & select_out_unread_marker_a;
out_unread_marker_write_enable_b = memory_controller_write_enable_b & select_out_unread_marker_b;
out_unread_marker_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_unread_marker_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_index_get_sof_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_index_get_sof_a}};
out_index_get_sof_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_index_get_sof_b}};
out_index_get_sof_write_enable_a = memory_controller_write_enable_a & select_out_index_get_sof_a;
out_index_get_sof_write_enable_b = memory_controller_write_enable_b & select_out_index_get_sof_b;
out_index_get_sof_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_index_get_sof_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_v_samp_factor_get_sof_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_v_samp_factor_get_sof_a}};
out_v_samp_factor_get_sof_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_v_samp_factor_get_sof_b}};
out_v_samp_factor_get_sof_write_enable_a = memory_controller_write_enable_a & select_out_v_samp_factor_get_sof_a;
out_v_samp_factor_get_sof_write_enable_b = memory_controller_write_enable_b & select_out_v_samp_factor_get_sof_b;
out_v_samp_factor_get_sof_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_v_samp_factor_get_sof_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_comp_id_get_sos_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_comp_id_get_sos_a}};
out_comp_id_get_sos_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_comp_id_get_sos_b}};
out_comp_id_get_sos_write_enable_a = memory_controller_write_enable_a & select_out_comp_id_get_sos_a;
out_comp_id_get_sos_write_enable_b = memory_controller_write_enable_b & select_out_comp_id_get_sos_b;
out_comp_id_get_sos_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_comp_id_get_sos_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_ac_tbl_no_get_sos_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_ac_tbl_no_get_sos_a}};
out_ac_tbl_no_get_sos_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_ac_tbl_no_get_sos_b}};
out_ac_tbl_no_get_sos_write_enable_a = memory_controller_write_enable_a & select_out_ac_tbl_no_get_sos_a;
out_ac_tbl_no_get_sos_write_enable_b = memory_controller_write_enable_b & select_out_ac_tbl_no_get_sos_b;
out_ac_tbl_no_get_sos_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_ac_tbl_no_get_sos_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_length_get_dht_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_length_get_dht_a}};
out_length_get_dht_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_length_get_dht_b}};
out_length_get_dht_write_enable_a = memory_controller_write_enable_a & select_out_length_get_dht_a;
out_length_get_dht_write_enable_b = memory_controller_write_enable_b & select_out_length_get_dht_b;
out_length_get_dht_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_length_get_dht_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_index_get_dht_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_index_get_dht_a}};
out_index_get_dht_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_index_get_dht_b}};
out_index_get_dht_write_enable_a = memory_controller_write_enable_a & select_out_index_get_dht_a;
out_index_get_dht_write_enable_b = memory_controller_write_enable_b & select_out_index_get_dht_b;
out_index_get_dht_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_index_get_dht_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_count_get_dht_address_a = memory_controller_address_a [2-1+2:2] & {2{select_out_count_get_dht_a}};
out_count_get_dht_address_b = memory_controller_address_b [2-1+2:2] & {2{select_out_count_get_dht_b}};
out_count_get_dht_write_enable_a = memory_controller_write_enable_a & select_out_count_get_dht_a;
out_count_get_dht_write_enable_b = memory_controller_write_enable_b & select_out_count_get_dht_b;
out_count_get_dht_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_count_get_dht_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_length_get_dqt_address_a = memory_controller_address_a [1-1+2:2] & {1{select_out_length_get_dqt_a}};
out_length_get_dqt_address_b = memory_controller_address_b [1-1+2:2] & {1{select_out_length_get_dqt_b}};
out_length_get_dqt_write_enable_a = memory_controller_write_enable_a & select_out_length_get_dqt_a;
out_length_get_dqt_write_enable_b = memory_controller_write_enable_b & select_out_length_get_dqt_b;
out_length_get_dqt_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_length_get_dqt_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_prec_get_dht_address_a = memory_controller_address_a [1-1+2:2] & {1{select_out_prec_get_dht_a}};
out_prec_get_dht_address_b = memory_controller_address_b [1-1+2:2] & {1{select_out_prec_get_dht_b}};
out_prec_get_dht_write_enable_a = memory_controller_write_enable_a & select_out_prec_get_dht_a;
out_prec_get_dht_write_enable_b = memory_controller_write_enable_b & select_out_prec_get_dht_b;
out_prec_get_dht_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_prec_get_dht_in_b [32-1:0] = memory_controller_in_b[32-1:0];
out_num_get_dht_address_a = memory_controller_address_a [1-1+2:2] & {1{select_out_num_get_dht_a}};
out_num_get_dht_address_b = memory_controller_address_b [1-1+2:2] & {1{select_out_num_get_dht_b}};
out_num_get_dht_write_enable_a = memory_controller_write_enable_a & select_out_num_get_dht_a;
out_num_get_dht_write_enable_b = memory_controller_write_enable_b & select_out_num_get_dht_b;
out_num_get_dht_in_a [32-1:0] = memory_controller_in_a[32-1:0];
out_num_get_dht_in_b [32-1:0] = memory_controller_in_b[32-1:0];
izigzag_index_address_a = memory_controller_address_a [6-1+2:2] & {6{select_izigzag_index_a}};
izigzag_index_address_b = memory_controller_address_b [6-1+2:2] & {6{select_izigzag_index_b}};
izigzag_index_write_enable_a = memory_controller_write_enable_a & select_izigzag_index_a;
izigzag_index_write_enable_b = memory_controller_write_enable_b & select_izigzag_index_b;
izigzag_index_in_a [32-1:0] = memory_controller_in_a[32-1:0];
izigzag_index_in_b [32-1:0] = memory_controller_in_b[32-1:0];
main_result_address_a = memory_controller_address_a [1-1+2:2] & {1{select_main_result_a}};
main_result_address_b = memory_controller_address_b [1-1+2:2] & {1{select_main_result_b}};
main_result_write_enable_a = memory_controller_write_enable_a & select_main_result_a;
main_result_write_enable_b = memory_controller_write_enable_b & select_main_result_b;
main_result_in_a [32-1:0] = memory_controller_in_a[32-1:0];
main_result_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_image_height_address_a = memory_controller_address_a [1-1+1:1] & {1{select_p_jinfo_image_height_a}};
p_jinfo_image_height_address_b = memory_controller_address_b [1-1+1:1] & {1{select_p_jinfo_image_height_b}};
p_jinfo_image_height_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_image_height_a;
p_jinfo_image_height_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_image_height_b;
p_jinfo_image_height_in_a [16-1:0] = memory_controller_in_a[16-1:0];
p_jinfo_image_height_in_b [16-1:0] = memory_controller_in_b[16-1:0];
p_jinfo_image_width_address_a = memory_controller_address_a [1-1+1:1] & {1{select_p_jinfo_image_width_a}};
p_jinfo_image_width_address_b = memory_controller_address_b [1-1+1:1] & {1{select_p_jinfo_image_width_b}};
p_jinfo_image_width_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_image_width_a;
p_jinfo_image_width_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_image_width_b;
p_jinfo_image_width_in_a [16-1:0] = memory_controller_in_a[16-1:0];
p_jinfo_image_width_in_b [16-1:0] = memory_controller_in_b[16-1:0];
p_jinfo_comps_info_index_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_index_a}};
p_jinfo_comps_info_index_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_index_b}};
p_jinfo_comps_info_index_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_index_a;
p_jinfo_comps_info_index_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_index_b;
p_jinfo_comps_info_index_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_index_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_id_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_id_a}};
p_jinfo_comps_info_id_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_id_b}};
p_jinfo_comps_info_id_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_id_a;
p_jinfo_comps_info_id_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_id_b;
p_jinfo_comps_info_id_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_id_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_h_samp_factor_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_h_samp_factor_a}};
p_jinfo_comps_info_h_samp_factor_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_h_samp_factor_b}};
p_jinfo_comps_info_h_samp_factor_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_h_samp_factor_a;
p_jinfo_comps_info_h_samp_factor_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_h_samp_factor_b;
p_jinfo_comps_info_h_samp_factor_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_h_samp_factor_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_v_samp_factor_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_v_samp_factor_a}};
p_jinfo_comps_info_v_samp_factor_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_v_samp_factor_b}};
p_jinfo_comps_info_v_samp_factor_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_v_samp_factor_a;
p_jinfo_comps_info_v_samp_factor_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_v_samp_factor_b;
p_jinfo_comps_info_v_samp_factor_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_v_samp_factor_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_quant_tbl_no_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_quant_tbl_no_a}};
p_jinfo_comps_info_quant_tbl_no_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_quant_tbl_no_b}};
p_jinfo_comps_info_quant_tbl_no_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_quant_tbl_no_a;
p_jinfo_comps_info_quant_tbl_no_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_quant_tbl_no_b;
p_jinfo_comps_info_quant_tbl_no_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_quant_tbl_no_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_dc_tbl_no_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_dc_tbl_no_a}};
p_jinfo_comps_info_dc_tbl_no_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_dc_tbl_no_b}};
p_jinfo_comps_info_dc_tbl_no_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_dc_tbl_no_a;
p_jinfo_comps_info_dc_tbl_no_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_dc_tbl_no_b;
p_jinfo_comps_info_dc_tbl_no_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_dc_tbl_no_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_comps_info_ac_tbl_no_address_a = memory_controller_address_a [2-1+0:0] & {2{select_p_jinfo_comps_info_ac_tbl_no_a}};
p_jinfo_comps_info_ac_tbl_no_address_b = memory_controller_address_b [2-1+0:0] & {2{select_p_jinfo_comps_info_ac_tbl_no_b}};
p_jinfo_comps_info_ac_tbl_no_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_comps_info_ac_tbl_no_a;
p_jinfo_comps_info_ac_tbl_no_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_comps_info_ac_tbl_no_b;
p_jinfo_comps_info_ac_tbl_no_in_a [8-1:0] = memory_controller_in_a[8-1:0];
p_jinfo_comps_info_ac_tbl_no_in_b [8-1:0] = memory_controller_in_b[8-1:0];
p_jinfo_ac_xhuff_tbl_bits_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_ac_xhuff_tbl_bits_a}};
p_jinfo_ac_xhuff_tbl_bits_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_ac_xhuff_tbl_bits_b}};
p_jinfo_ac_xhuff_tbl_bits_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_xhuff_tbl_bits_a;
p_jinfo_ac_xhuff_tbl_bits_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_xhuff_tbl_bits_b;
p_jinfo_ac_xhuff_tbl_bits_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_xhuff_tbl_bits_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_ac_xhuff_tbl_huffval_address_a = memory_controller_address_a [10-1+2:2] & {10{select_p_jinfo_ac_xhuff_tbl_huffval_a}};
p_jinfo_ac_xhuff_tbl_huffval_address_b = memory_controller_address_b [10-1+2:2] & {10{select_p_jinfo_ac_xhuff_tbl_huffval_b}};
p_jinfo_ac_xhuff_tbl_huffval_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_xhuff_tbl_huffval_a;
p_jinfo_ac_xhuff_tbl_huffval_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_xhuff_tbl_huffval_b;
p_jinfo_ac_xhuff_tbl_huffval_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_xhuff_tbl_huffval_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_xhuff_tbl_bits_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_dc_xhuff_tbl_bits_a}};
p_jinfo_dc_xhuff_tbl_bits_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_dc_xhuff_tbl_bits_b}};
p_jinfo_dc_xhuff_tbl_bits_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_xhuff_tbl_bits_a;
p_jinfo_dc_xhuff_tbl_bits_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_xhuff_tbl_bits_b;
p_jinfo_dc_xhuff_tbl_bits_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_xhuff_tbl_bits_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_xhuff_tbl_huffval_address_a = memory_controller_address_a [10-1+2:2] & {10{select_p_jinfo_dc_xhuff_tbl_huffval_a}};
p_jinfo_dc_xhuff_tbl_huffval_address_b = memory_controller_address_b [10-1+2:2] & {10{select_p_jinfo_dc_xhuff_tbl_huffval_b}};
p_jinfo_dc_xhuff_tbl_huffval_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_xhuff_tbl_huffval_a;
p_jinfo_dc_xhuff_tbl_huffval_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_xhuff_tbl_huffval_b;
p_jinfo_dc_xhuff_tbl_huffval_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_xhuff_tbl_huffval_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_quant_tbl_quantval_address_a = memory_controller_address_a [8-1+2:2] & {8{select_p_jinfo_quant_tbl_quantval_a}};
p_jinfo_quant_tbl_quantval_address_b = memory_controller_address_b [8-1+2:2] & {8{select_p_jinfo_quant_tbl_quantval_b}};
p_jinfo_quant_tbl_quantval_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_quant_tbl_quantval_a;
p_jinfo_quant_tbl_quantval_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_quant_tbl_quantval_b;
p_jinfo_quant_tbl_quantval_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_quant_tbl_quantval_in_b [32-1:0] = memory_controller_in_b[32-1:0];
zigzag_index_address_a = memory_controller_address_a [6-1+2:2] & {6{select_zigzag_index_a}};
zigzag_index_address_b = memory_controller_address_b [6-1+2:2] & {6{select_zigzag_index_b}};
zigzag_index_write_enable_a = memory_controller_write_enable_a & select_zigzag_index_a;
zigzag_index_write_enable_b = memory_controller_write_enable_b & select_zigzag_index_b;
zigzag_index_in_a [32-1:0] = memory_controller_in_a[32-1:0];
zigzag_index_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_MCUWidth_address_a = memory_controller_address_a [1-1+2:2] & {1{select_p_jinfo_MCUWidth_a}};
p_jinfo_MCUWidth_address_b = memory_controller_address_b [1-1+2:2] & {1{select_p_jinfo_MCUWidth_b}};
p_jinfo_MCUWidth_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_MCUWidth_a;
p_jinfo_MCUWidth_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_MCUWidth_b;
p_jinfo_MCUWidth_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_MCUWidth_in_b [32-1:0] = memory_controller_in_b[32-1:0];
rgb_buf_address_a = memory_controller_address_a [10-1+2:2] & {10{select_rgb_buf_a}};
rgb_buf_address_b = memory_controller_address_b [10-1+2:2] & {10{select_rgb_buf_b}};
rgb_buf_write_enable_a = memory_controller_write_enable_a & select_rgb_buf_a;
rgb_buf_write_enable_b = memory_controller_write_enable_b & select_rgb_buf_b;
rgb_buf_in_a [32-1:0] = memory_controller_in_a[32-1:0];
rgb_buf_in_b [32-1:0] = memory_controller_in_b[32-1:0];
CurHuffReadBuf_address_a = memory_controller_address_a [1-1+2:2] & {1{select_CurHuffReadBuf_a}};
CurHuffReadBuf_address_b = memory_controller_address_b [1-1+2:2] & {1{select_CurHuffReadBuf_b}};
CurHuffReadBuf_write_enable_a = memory_controller_write_enable_a & select_CurHuffReadBuf_a;
CurHuffReadBuf_write_enable_b = memory_controller_write_enable_b & select_CurHuffReadBuf_b;
CurHuffReadBuf_in_a [32-1:0] = memory_controller_in_a[32-1:0];
CurHuffReadBuf_in_b [32-1:0] = memory_controller_in_b[32-1:0];
OutData_comp_buf_address_a = memory_controller_address_a [14-1+0:0] & {14{select_OutData_comp_buf_a}};
OutData_comp_buf_address_b = memory_controller_address_b [14-1+0:0] & {14{select_OutData_comp_buf_b}};
OutData_comp_buf_write_enable_a = memory_controller_write_enable_a & select_OutData_comp_buf_a;
OutData_comp_buf_write_enable_b = memory_controller_write_enable_b & select_OutData_comp_buf_b;
OutData_comp_buf_in_a [8-1:0] = memory_controller_in_a[8-1:0];
OutData_comp_buf_in_b [8-1:0] = memory_controller_in_b[8-1:0];
bit_set_mask_address_a = memory_controller_address_a [5-1+2:2] & {5{select_bit_set_mask_a}};
bit_set_mask_address_b = memory_controller_address_b [5-1+2:2] & {5{select_bit_set_mask_b}};
bit_set_mask_write_enable_a = memory_controller_write_enable_a & select_bit_set_mask_a;
bit_set_mask_write_enable_b = memory_controller_write_enable_b & select_bit_set_mask_b;
bit_set_mask_in_a [32-1:0] = memory_controller_in_a[32-1:0];
bit_set_mask_in_b [32-1:0] = memory_controller_in_b[32-1:0];
lmask_address_a = memory_controller_address_a [5-1+2:2] & {5{select_lmask_a}};
lmask_address_b = memory_controller_address_b [5-1+2:2] & {5{select_lmask_b}};
lmask_write_enable_a = memory_controller_write_enable_a & select_lmask_a;
lmask_write_enable_b = memory_controller_write_enable_b & select_lmask_b;
lmask_in_a [32-1:0] = memory_controller_in_a[32-1:0];
lmask_in_b [32-1:0] = memory_controller_in_b[32-1:0];
read_position_address_a = memory_controller_address_a [1-1+2:2] & {1{select_read_position_a}};
read_position_address_b = memory_controller_address_b [1-1+2:2] & {1{select_read_position_b}};
read_position_write_enable_a = memory_controller_write_enable_a & select_read_position_a;
read_position_write_enable_b = memory_controller_write_enable_b & select_read_position_b;
read_position_in_a [32-1:0] = memory_controller_in_a[32-1:0];
read_position_in_b [32-1:0] = memory_controller_in_b[32-1:0];
current_read_byte_address_a = memory_controller_address_a [1-1+2:2] & {1{select_current_read_byte_a}};
current_read_byte_address_b = memory_controller_address_b [1-1+2:2] & {1{select_current_read_byte_b}};
current_read_byte_write_enable_a = memory_controller_write_enable_a & select_current_read_byte_a;
current_read_byte_write_enable_b = memory_controller_write_enable_b & select_current_read_byte_b;
current_read_byte_in_a [32-1:0] = memory_controller_in_a[32-1:0];
current_read_byte_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_dhuff_tbl_ml_address_a = memory_controller_address_a [1-1+2:2] & {1{select_p_jinfo_dc_dhuff_tbl_ml_a}};
p_jinfo_dc_dhuff_tbl_ml_address_b = memory_controller_address_b [1-1+2:2] & {1{select_p_jinfo_dc_dhuff_tbl_ml_b}};
p_jinfo_dc_dhuff_tbl_ml_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_dhuff_tbl_ml_a;
p_jinfo_dc_dhuff_tbl_ml_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_dhuff_tbl_ml_b;
p_jinfo_dc_dhuff_tbl_ml_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_dhuff_tbl_ml_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_dhuff_tbl_maxcode_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_maxcode_a}};
p_jinfo_dc_dhuff_tbl_maxcode_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_maxcode_b}};
p_jinfo_dc_dhuff_tbl_maxcode_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_dhuff_tbl_maxcode_a;
p_jinfo_dc_dhuff_tbl_maxcode_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_dhuff_tbl_maxcode_b;
p_jinfo_dc_dhuff_tbl_maxcode_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_dhuff_tbl_maxcode_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_dhuff_tbl_mincode_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_mincode_a}};
p_jinfo_dc_dhuff_tbl_mincode_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_mincode_b}};
p_jinfo_dc_dhuff_tbl_mincode_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_dhuff_tbl_mincode_a;
p_jinfo_dc_dhuff_tbl_mincode_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_dhuff_tbl_mincode_b;
p_jinfo_dc_dhuff_tbl_mincode_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_dhuff_tbl_mincode_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_dc_dhuff_tbl_valptr_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_valptr_a}};
p_jinfo_dc_dhuff_tbl_valptr_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_dc_dhuff_tbl_valptr_b}};
p_jinfo_dc_dhuff_tbl_valptr_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_dc_dhuff_tbl_valptr_a;
p_jinfo_dc_dhuff_tbl_valptr_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_dc_dhuff_tbl_valptr_b;
p_jinfo_dc_dhuff_tbl_valptr_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_dc_dhuff_tbl_valptr_in_b [32-1:0] = memory_controller_in_b[32-1:0];
extend_mask_address_a = memory_controller_address_a [5-1+2:2] & {5{select_extend_mask_a}};
extend_mask_address_b = memory_controller_address_b [5-1+2:2] & {5{select_extend_mask_b}};
extend_mask_write_enable_a = memory_controller_write_enable_a & select_extend_mask_a;
extend_mask_write_enable_b = memory_controller_write_enable_b & select_extend_mask_b;
extend_mask_in_a [32-1:0] = memory_controller_in_a[32-1:0];
extend_mask_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_ac_dhuff_tbl_ml_address_a = memory_controller_address_a [1-1+2:2] & {1{select_p_jinfo_ac_dhuff_tbl_ml_a}};
p_jinfo_ac_dhuff_tbl_ml_address_b = memory_controller_address_b [1-1+2:2] & {1{select_p_jinfo_ac_dhuff_tbl_ml_b}};
p_jinfo_ac_dhuff_tbl_ml_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_dhuff_tbl_ml_a;
p_jinfo_ac_dhuff_tbl_ml_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_dhuff_tbl_ml_b;
p_jinfo_ac_dhuff_tbl_ml_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_dhuff_tbl_ml_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_ac_dhuff_tbl_maxcode_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_maxcode_a}};
p_jinfo_ac_dhuff_tbl_maxcode_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_maxcode_b}};
p_jinfo_ac_dhuff_tbl_maxcode_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_dhuff_tbl_maxcode_a;
p_jinfo_ac_dhuff_tbl_maxcode_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_dhuff_tbl_maxcode_b;
p_jinfo_ac_dhuff_tbl_maxcode_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_dhuff_tbl_maxcode_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_ac_dhuff_tbl_mincode_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_mincode_a}};
p_jinfo_ac_dhuff_tbl_mincode_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_mincode_b}};
p_jinfo_ac_dhuff_tbl_mincode_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_dhuff_tbl_mincode_a;
p_jinfo_ac_dhuff_tbl_mincode_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_dhuff_tbl_mincode_b;
p_jinfo_ac_dhuff_tbl_mincode_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_dhuff_tbl_mincode_in_b [32-1:0] = memory_controller_in_b[32-1:0];
p_jinfo_ac_dhuff_tbl_valptr_address_a = memory_controller_address_a [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_valptr_a}};
p_jinfo_ac_dhuff_tbl_valptr_address_b = memory_controller_address_b [7-1+2:2] & {7{select_p_jinfo_ac_dhuff_tbl_valptr_b}};
p_jinfo_ac_dhuff_tbl_valptr_write_enable_a = memory_controller_write_enable_a & select_p_jinfo_ac_dhuff_tbl_valptr_a;
p_jinfo_ac_dhuff_tbl_valptr_write_enable_b = memory_controller_write_enable_b & select_p_jinfo_ac_dhuff_tbl_valptr_b;
p_jinfo_ac_dhuff_tbl_valptr_in_a [32-1:0] = memory_controller_in_a[32-1:0];
p_jinfo_ac_dhuff_tbl_valptr_in_b [32-1:0] = memory_controller_in_b[32-1:0];
OutData_comp_vpos_address_a = memory_controller_address_a [2-1+2:2] & {2{select_OutData_comp_vpos_a}};
OutData_comp_vpos_address_b = memory_controller_address_b [2-1+2:2] & {2{select_OutData_comp_vpos_b}};
OutData_comp_vpos_write_enable_a = memory_controller_write_enable_a & select_OutData_comp_vpos_a;
OutData_comp_vpos_write_enable_b = memory_controller_write_enable_b & select_OutData_comp_vpos_b;
OutData_comp_vpos_in_a [32-1:0] = memory_controller_in_a[32-1:0];
OutData_comp_vpos_in_b [32-1:0] = memory_controller_in_b[32-1:0];
OutData_comp_hpos_address_a = memory_controller_address_a [2-1+2:2] & {2{select_OutData_comp_hpos_a}};
OutData_comp_hpos_address_b = memory_controller_address_b [2-1+2:2] & {2{select_OutData_comp_hpos_b}};
OutData_comp_hpos_write_enable_a = memory_controller_write_enable_a & select_OutData_comp_hpos_a;
OutData_comp_hpos_write_enable_b = memory_controller_write_enable_b & select_OutData_comp_hpos_b;
OutData_comp_hpos_in_a [32-1:0] = memory_controller_in_a[32-1:0];
OutData_comp_hpos_in_b [32-1:0] = memory_controller_in_b[32-1:0];
JpegFileBuf_address_a = memory_controller_address_a [13-1+0:0] & {13{select_JpegFileBuf_a}};
JpegFileBuf_address_b = memory_controller_address_b [13-1+0:0] & {13{select_JpegFileBuf_b}};
JpegFileBuf_write_enable_a = memory_controller_write_enable_a & select_JpegFileBuf_a;
JpegFileBuf_write_enable_b = memory_controller_write_enable_b & select_JpegFileBuf_b;
JpegFileBuf_in_a [8-1:0] = memory_controller_in_a[8-1:0];
JpegFileBuf_in_b [8-1:0] = memory_controller_in_b[8-1:0];
decode_block_0_QuantBuff_address_a = memory_controller_address_a [6-1+2:2] & {6{select_decode_block_0_QuantBuff_a}};
decode_block_0_QuantBuff_address_b = memory_controller_address_b [6-1+2:2] & {6{select_decode_block_0_QuantBuff_b}};
decode_block_0_QuantBuff_write_enable_a = memory_controller_write_enable_a & select_decode_block_0_QuantBuff_a;
decode_block_0_QuantBuff_write_enable_b = memory_controller_write_enable_b & select_decode_block_0_QuantBuff_b;
decode_block_0_QuantBuff_in_a [32-1:0] = memory_controller_in_a[32-1:0];
decode_block_0_QuantBuff_in_b [32-1:0] = memory_controller_in_b[32-1:0];
huff_make_dhuff_tb_0_huffsize_address_a = memory_controller_address_a [9-1+2:2] & {9{select_huff_make_dhuff_tb_0_huffsize_a}};
huff_make_dhuff_tb_0_huffsize_address_b = memory_controller_address_b [9-1+2:2] & {9{select_huff_make_dhuff_tb_0_huffsize_b}};
huff_make_dhuff_tb_0_huffsize_write_enable_a = memory_controller_write_enable_a & select_huff_make_dhuff_tb_0_huffsize_a;
huff_make_dhuff_tb_0_huffsize_write_enable_b = memory_controller_write_enable_b & select_huff_make_dhuff_tb_0_huffsize_b;
huff_make_dhuff_tb_0_huffsize_in_a [32-1:0] = memory_controller_in_a[32-1:0];
huff_make_dhuff_tb_0_huffsize_in_b [32-1:0] = memory_controller_in_b[32-1:0];
huff_make_dhuff_tb_0_huffcode_address_a = memory_controller_address_a [9-1+2:2] & {9{select_huff_make_dhuff_tb_0_huffcode_a}};
huff_make_dhuff_tb_0_huffcode_address_b = memory_controller_address_b [9-1+2:2] & {9{select_huff_make_dhuff_tb_0_huffcode_b}};
huff_make_dhuff_tb_0_huffcode_write_enable_a = memory_controller_write_enable_a & select_huff_make_dhuff_tb_0_huffcode_a;
huff_make_dhuff_tb_0_huffcode_write_enable_b = memory_controller_write_enable_b & select_huff_make_dhuff_tb_0_huffcode_b;
huff_make_dhuff_tb_0_huffcode_in_a [32-1:0] = memory_controller_in_a[32-1:0];
huff_make_dhuff_tb_0_huffcode_in_b [32-1:0] = memory_controller_in_b[32-1:0];
main_0_HuffBuff_i_i_address_a = memory_controller_address_a [8-1+2:2] & {8{select_main_0_HuffBuff_i_i_a}};
main_0_HuffBuff_i_i_address_b = memory_controller_address_b [8-1+2:2] & {8{select_main_0_HuffBuff_i_i_b}};
main_0_HuffBuff_i_i_write_enable_a = memory_controller_write_enable_a & select_main_0_HuffBuff_i_i_a;
main_0_HuffBuff_i_i_write_enable_b = memory_controller_write_enable_b & select_main_0_HuffBuff_i_i_b;
main_0_HuffBuff_i_i_in_a [32-1:0] = memory_controller_in_a[32-1:0];
main_0_HuffBuff_i_i_in_b [32-1:0] = memory_controller_in_b[32-1:0];
main_0_IDCTBuff_i_i_address_a = memory_controller_address_a [9-1+2:2] & {9{select_main_0_IDCTBuff_i_i_a}};
main_0_IDCTBuff_i_i_address_b = memory_controller_address_b [9-1+2:2] & {9{select_main_0_IDCTBuff_i_i_b}};
main_0_IDCTBuff_i_i_write_enable_a = memory_controller_write_enable_a & select_main_0_IDCTBuff_i_i_a;
main_0_IDCTBuff_i_i_write_enable_b = memory_controller_write_enable_b & select_main_0_IDCTBuff_i_i_b;
main_0_IDCTBuff_i_i_in_a [32-1:0] = memory_controller_in_a[32-1:0];
main_0_IDCTBuff_i_i_in_b [32-1:0] = memory_controller_in_b[32-1:0];
end
always @(*)
begin
select_not_struct_a [2:0] = 3'b0 | {2{select_out_unread_marker_reg_a}} | {2{select_out_index_get_sof_reg_a}} | {2{select_out_v_samp_factor_get_sof_reg_a}} | {2{select_out_comp_id_get_sos_reg_a}} | {2{select_out_ac_tbl_no_get_sos_reg_a}} | {2{select_out_length_get_dht_reg_a}} | {2{select_out_index_get_dht_reg_a}} | {2{select_out_count_get_dht_reg_a}} | {2{select_out_length_get_dqt_reg_a}} | {2{select_out_prec_get_dht_reg_a}} | {2{select_out_num_get_dht_reg_a}} | {2{select_izigzag_index_reg_a}} | {2{select_main_result_reg_a}} | {1{select_p_jinfo_image_height_reg_a}} | {1{select_p_jinfo_image_width_reg_a}} | {2{select_p_jinfo_ac_xhuff_tbl_bits_reg_a}} | {2{select_p_jinfo_ac_xhuff_tbl_huffval_reg_a}} | {2{select_p_jinfo_dc_xhuff_tbl_bits_reg_a}} | {2{select_p_jinfo_dc_xhuff_tbl_huffval_reg_a}} | {2{select_p_jinfo_quant_tbl_quantval_reg_a}} | {2{select_zigzag_index_reg_a}} | {2{select_p_jinfo_MCUWidth_reg_a}} | {2{select_rgb_buf_reg_a}} | {2{select_CurHuffReadBuf_reg_a}} | {2{select_bit_set_mask_reg_a}} | {2{select_lmask_reg_a}} | {2{select_read_position_reg_a}} | {2{select_current_read_byte_reg_a}} | {2{select_p_jinfo_dc_dhuff_tbl_ml_reg_a}} | {2{select_p_jinfo_dc_dhuff_tbl_maxcode_reg_a}} | {2{select_p_jinfo_dc_dhuff_tbl_mincode_reg_a}} | {2{select_p_jinfo_dc_dhuff_tbl_valptr_reg_a}} | {2{select_extend_mask_reg_a}} | {2{select_p_jinfo_ac_dhuff_tbl_ml_reg_a}} | {2{select_p_jinfo_ac_dhuff_tbl_maxcode_reg_a}} | {2{select_p_jinfo_ac_dhuff_tbl_mincode_reg_a}} | {2{select_p_jinfo_ac_dhuff_tbl_valptr_reg_a}} | {2{select_OutData_comp_vpos_reg_a}} | {2{select_OutData_comp_hpos_reg_a}} | {2{select_decode_block_0_QuantBuff_reg_a}} | {2{select_huff_make_dhuff_tb_0_huffsize_reg_a}} | {2{select_huff_make_dhuff_tb_0_huffcode_reg_a}} | {2{select_main_0_HuffBuff_i_i_reg_a}} | {2{select_main_0_IDCTBuff_i_i_reg_a}};
select_not_struct_b[2:0] = 3'b0 | {2{select_out_unread_marker_reg_b}} | {2{select_out_index_get_sof_reg_b}} | {2{select_out_v_samp_factor_get_sof_reg_b}} | {2{select_out_comp_id_get_sos_reg_b}} | {2{select_out_ac_tbl_no_get_sos_reg_b}} | {2{select_out_length_get_dht_reg_b}} | {2{select_out_index_get_dht_reg_b}} | {2{select_out_count_get_dht_reg_b}} | {2{select_out_length_get_dqt_reg_b}} | {2{select_out_prec_get_dht_reg_b}} | {2{select_out_num_get_dht_reg_b}} | {2{select_izigzag_index_reg_b}} | {2{select_main_result_reg_b}} | {1{select_p_jinfo_image_height_reg_b}} | {1{select_p_jinfo_image_width_reg_b}} | {2{select_p_jinfo_ac_xhuff_tbl_bits_reg_b}} | {2{select_p_jinfo_ac_xhuff_tbl_huffval_reg_b}} | {2{select_p_jinfo_dc_xhuff_tbl_bits_reg_b}} | {2{select_p_jinfo_dc_xhuff_tbl_huffval_reg_b}} | {2{select_p_jinfo_quant_tbl_quantval_reg_b}} | {2{select_zigzag_index_reg_b}} | {2{select_p_jinfo_MCUWidth_reg_b}} | {2{select_rgb_buf_reg_b}} | {2{select_CurHuffReadBuf_reg_b}} | {2{select_bit_set_mask_reg_b}} | {2{select_lmask_reg_b}} | {2{select_read_position_reg_b}} | {2{select_current_read_byte_reg_b}} | {2{select_p_jinfo_dc_dhuff_tbl_ml_reg_b}} | {2{select_p_jinfo_dc_dhuff_tbl_maxcode_reg_b}} | {2{select_p_jinfo_dc_dhuff_tbl_mincode_reg_b}} | {2{select_p_jinfo_dc_dhuff_tbl_valptr_reg_b}} | {2{select_extend_mask_reg_b}} | {2{select_p_jinfo_ac_dhuff_tbl_ml_reg_b}} | {2{select_p_jinfo_ac_dhuff_tbl_maxcode_reg_b}} | {2{select_p_jinfo_ac_dhuff_tbl_mincode_reg_b}} | {2{select_p_jinfo_ac_dhuff_tbl_valptr_reg_b}} | {2{select_OutData_comp_vpos_reg_b}} | {2{select_OutData_comp_hpos_reg_b}} | {2{select_decode_block_0_QuantBuff_reg_b}} | {2{select_huff_make_dhuff_tb_0_huffsize_reg_b}} | {2{select_huff_make_dhuff_tb_0_huffcode_reg_b}} | {2{select_main_0_HuffBuff_i_i_reg_b}} | {2{select_main_0_IDCTBuff_i_i_reg_b}};
if (prevAddr_a[2:0] & select_not_struct_a[2:0] != 0)
begin
$display("Error: memory address not aligned to ram word size!");
$finish;
end
if (prevAddr_b[2:0] & select_not_struct_b[2:0] != 0)
begin
$display("Error: memory address not aligned to ram word size!");
$finish;
end
prevSize_a_and[0] = prevSize_a[1] | prevSize_a[0];
prevSize_a_and[1] = prevSize_a[1];
prevSize_a_and[2] = prevSize_a[1] & prevSize_a[0];
if ((prevAddr_a & prevSize_a_and) != 0)
begin
$display("Error: memory address not aligned to ram size!");
$finish;
end
prevSize_b_and[0] = prevSize_b[1] | prevSize_b[0];
prevSize_b_and[1] = prevSize_b[1];
prevSize_b_and[2] = prevSize_b[1] & prevSize_b[0];
if ((prevAddr_b & prevSize_b_and) != 0)
begin
$display("Error: memory address not aligned to ram size!");
$finish;
end
memory_controller_out_a = 1'b0 | memory_controller_hana_jpg_out_a | memory_controller_hana_bmp_out_a | memory_controller_out_unread_marker_out_a | memory_controller_out_index_get_sof_out_a | memory_controller_out_v_samp_factor_get_sof_out_a | memory_controller_out_comp_id_get_sos_out_a | memory_controller_out_ac_tbl_no_get_sos_out_a | memory_controller_out_length_get_dht_out_a | memory_controller_out_index_get_dht_out_a | memory_controller_out_count_get_dht_out_a | memory_controller_out_length_get_dqt_out_a | memory_controller_out_prec_get_dht_out_a | memory_controller_out_num_get_dht_out_a | memory_controller_izigzag_index_out_a | memory_controller_main_result_out_a | memory_controller_p_jinfo_image_height_out_a | memory_controller_p_jinfo_image_width_out_a | memory_controller_p_jinfo_comps_info_index_out_a | memory_controller_p_jinfo_comps_info_id_out_a | memory_controller_p_jinfo_comps_info_h_samp_factor_out_a | memory_controller_p_jinfo_comps_info_v_samp_factor_out_a | memory_controller_p_jinfo_comps_info_quant_tbl_no_out_a | memory_controller_p_jinfo_comps_info_dc_tbl_no_out_a | memory_controller_p_jinfo_comps_info_ac_tbl_no_out_a | memory_controller_p_jinfo_ac_xhuff_tbl_bits_out_a | memory_controller_p_jinfo_ac_xhuff_tbl_huffval_out_a | memory_controller_p_jinfo_dc_xhuff_tbl_bits_out_a | memory_controller_p_jinfo_dc_xhuff_tbl_huffval_out_a | memory_controller_p_jinfo_quant_tbl_quantval_out_a | memory_controller_zigzag_index_out_a | memory_controller_p_jinfo_MCUWidth_out_a | memory_controller_rgb_buf_out_a | memory_controller_CurHuffReadBuf_out_a | memory_controller_OutData_comp_buf_out_a | memory_controller_bit_set_mask_out_a | memory_controller_lmask_out_a | memory_controller_read_position_out_a | memory_controller_current_read_byte_out_a | memory_controller_p_jinfo_dc_dhuff_tbl_ml_out_a | memory_controller_p_jinfo_dc_dhuff_tbl_maxcode_out_a | memory_controller_p_jinfo_dc_dhuff_tbl_mincode_out_a | memory_controller_p_jinfo_dc_dhuff_tbl_valptr_out_a | memory_controller_extend_mask_out_a | memory_controller_p_jinfo_ac_dhuff_tbl_ml_out_a | memory_controller_p_jinfo_ac_dhuff_tbl_maxcode_out_a | memory_controller_p_jinfo_ac_dhuff_tbl_mincode_out_a | memory_controller_p_jinfo_ac_dhuff_tbl_valptr_out_a | memory_controller_OutData_comp_vpos_out_a | memory_controller_OutData_comp_hpos_out_a | memory_controller_JpegFileBuf_out_a | memory_controller_decode_block_0_QuantBuff_out_a | memory_controller_huff_make_dhuff_tb_0_huffsize_out_a | memory_controller_huff_make_dhuff_tb_0_huffcode_out_a | memory_controller_main_0_HuffBuff_i_i_out_a | memory_controller_main_0_IDCTBuff_i_i_out_a;
memory_controller_out_b = 1'b0 | memory_controller_hana_jpg_out_b | memory_controller_hana_bmp_out_b | memory_controller_out_unread_marker_out_b | memory_controller_out_index_get_sof_out_b | memory_controller_out_v_samp_factor_get_sof_out_b | memory_controller_out_comp_id_get_sos_out_b | memory_controller_out_ac_tbl_no_get_sos_out_b | memory_controller_out_length_get_dht_out_b | memory_controller_out_index_get_dht_out_b | memory_controller_out_count_get_dht_out_b | memory_controller_out_length_get_dqt_out_b | memory_controller_out_prec_get_dht_out_b | memory_controller_out_num_get_dht_out_b | memory_controller_izigzag_index_out_b | memory_controller_main_result_out_b | memory_controller_p_jinfo_image_height_out_b | memory_controller_p_jinfo_image_width_out_b | memory_controller_p_jinfo_comps_info_index_out_b | memory_controller_p_jinfo_comps_info_id_out_b | memory_controller_p_jinfo_comps_info_h_samp_factor_out_b | memory_controller_p_jinfo_comps_info_v_samp_factor_out_b | memory_controller_p_jinfo_comps_info_quant_tbl_no_out_b | memory_controller_p_jinfo_comps_info_dc_tbl_no_out_b | memory_controller_p_jinfo_comps_info_ac_tbl_no_out_b | memory_controller_p_jinfo_ac_xhuff_tbl_bits_out_b | memory_controller_p_jinfo_ac_xhuff_tbl_huffval_out_b | memory_controller_p_jinfo_dc_xhuff_tbl_bits_out_b | memory_controller_p_jinfo_dc_xhuff_tbl_huffval_out_b | memory_controller_p_jinfo_quant_tbl_quantval_out_b | memory_controller_zigzag_index_out_b | memory_controller_p_jinfo_MCUWidth_out_b | memory_controller_rgb_buf_out_b | memory_controller_CurHuffReadBuf_out_b | memory_controller_OutData_comp_buf_out_b | memory_controller_bit_set_mask_out_b | memory_controller_lmask_out_b | memory_controller_read_position_out_b | memory_controller_current_read_byte_out_b | memory_controller_p_jinfo_dc_dhuff_tbl_ml_out_b | memory_controller_p_jinfo_dc_dhuff_tbl_maxcode_out_b | memory_controller_p_jinfo_dc_dhuff_tbl_mincode_out_b | memory_controller_p_jinfo_dc_dhuff_tbl_valptr_out_b | memory_controller_extend_mask_out_b | memory_controller_p_jinfo_ac_dhuff_tbl_ml_out_b | memory_controller_p_jinfo_ac_dhuff_tbl_maxcode_out_b | memory_controller_p_jinfo_ac_dhuff_tbl_mincode_out_b | memory_controller_p_jinfo_ac_dhuff_tbl_valptr_out_b | memory_controller_OutData_comp_vpos_out_b | memory_controller_OutData_comp_hpos_out_b | memory_controller_JpegFileBuf_out_b | memory_controller_decode_block_0_QuantBuff_out_b | memory_controller_huff_make_dhuff_tb_0_huffsize_out_b | memory_controller_huff_make_dhuff_tb_0_huffcode_out_b | memory_controller_main_0_HuffBuff_i_i_out_b | memory_controller_main_0_IDCTBuff_i_i_out_b;
end
always @(posedge clk)
begin
memory_controller_out_reg_a <= memory_controller_out_a;
memory_controller_out_reg_b <= memory_controller_out_b;
select_hana_jpg_reg_a <= select_hana_jpg_a;
select_hana_jpg_reg_b <= select_hana_jpg_b;
select_hana_bmp_reg_a <= select_hana_bmp_a;
select_hana_bmp_reg_b <= select_hana_bmp_b;
select_out_unread_marker_reg_a <= select_out_unread_marker_a;
select_out_unread_marker_reg_b <= select_out_unread_marker_b;
select_out_index_get_sof_reg_a <= select_out_index_get_sof_a;
select_out_index_get_sof_reg_b <= select_out_index_get_sof_b;
select_out_v_samp_factor_get_sof_reg_a <= select_out_v_samp_factor_get_sof_a;
select_out_v_samp_factor_get_sof_reg_b <= select_out_v_samp_factor_get_sof_b;
select_out_comp_id_get_sos_reg_a <= select_out_comp_id_get_sos_a;
select_out_comp_id_get_sos_reg_b <= select_out_comp_id_get_sos_b;
select_out_ac_tbl_no_get_sos_reg_a <= select_out_ac_tbl_no_get_sos_a;
select_out_ac_tbl_no_get_sos_reg_b <= select_out_ac_tbl_no_get_sos_b;
select_out_length_get_dht_reg_a <= select_out_length_get_dht_a;
select_out_length_get_dht_reg_b <= select_out_length_get_dht_b;
select_out_index_get_dht_reg_a <= select_out_index_get_dht_a;
select_out_index_get_dht_reg_b <= select_out_index_get_dht_b;
select_out_count_get_dht_reg_a <= select_out_count_get_dht_a;
select_out_count_get_dht_reg_b <= select_out_count_get_dht_b;
select_out_length_get_dqt_reg_a <= select_out_length_get_dqt_a;
select_out_length_get_dqt_reg_b <= select_out_length_get_dqt_b;
select_out_prec_get_dht_reg_a <= select_out_prec_get_dht_a;
select_out_prec_get_dht_reg_b <= select_out_prec_get_dht_b;
select_out_num_get_dht_reg_a <= select_out_num_get_dht_a;
select_out_num_get_dht_reg_b <= select_out_num_get_dht_b;
select_izigzag_index_reg_a <= select_izigzag_index_a;
select_izigzag_index_reg_b <= select_izigzag_index_b;
select_main_result_reg_a <= select_main_result_a;
select_main_result_reg_b <= select_main_result_b;
select_p_jinfo_image_height_reg_a <= select_p_jinfo_image_height_a;
select_p_jinfo_image_height_reg_b <= select_p_jinfo_image_height_b;
select_p_jinfo_image_width_reg_a <= select_p_jinfo_image_width_a;
select_p_jinfo_image_width_reg_b <= select_p_jinfo_image_width_b;
select_p_jinfo_comps_info_index_reg_a <= select_p_jinfo_comps_info_index_a;
select_p_jinfo_comps_info_index_reg_b <= select_p_jinfo_comps_info_index_b;
select_p_jinfo_comps_info_id_reg_a <= select_p_jinfo_comps_info_id_a;
select_p_jinfo_comps_info_id_reg_b <= select_p_jinfo_comps_info_id_b;
select_p_jinfo_comps_info_h_samp_factor_reg_a <= select_p_jinfo_comps_info_h_samp_factor_a;
select_p_jinfo_comps_info_h_samp_factor_reg_b <= select_p_jinfo_comps_info_h_samp_factor_b;
select_p_jinfo_comps_info_v_samp_factor_reg_a <= select_p_jinfo_comps_info_v_samp_factor_a;
select_p_jinfo_comps_info_v_samp_factor_reg_b <= select_p_jinfo_comps_info_v_samp_factor_b;
select_p_jinfo_comps_info_quant_tbl_no_reg_a <= select_p_jinfo_comps_info_quant_tbl_no_a;
select_p_jinfo_comps_info_quant_tbl_no_reg_b <= select_p_jinfo_comps_info_quant_tbl_no_b;
select_p_jinfo_comps_info_dc_tbl_no_reg_a <= select_p_jinfo_comps_info_dc_tbl_no_a;
select_p_jinfo_comps_info_dc_tbl_no_reg_b <= select_p_jinfo_comps_info_dc_tbl_no_b;
select_p_jinfo_comps_info_ac_tbl_no_reg_a <= select_p_jinfo_comps_info_ac_tbl_no_a;
select_p_jinfo_comps_info_ac_tbl_no_reg_b <= select_p_jinfo_comps_info_ac_tbl_no_b;
select_p_jinfo_ac_xhuff_tbl_bits_reg_a <= select_p_jinfo_ac_xhuff_tbl_bits_a;
select_p_jinfo_ac_xhuff_tbl_bits_reg_b <= select_p_jinfo_ac_xhuff_tbl_bits_b;
select_p_jinfo_ac_xhuff_tbl_huffval_reg_a <= select_p_jinfo_ac_xhuff_tbl_huffval_a;
select_p_jinfo_ac_xhuff_tbl_huffval_reg_b <= select_p_jinfo_ac_xhuff_tbl_huffval_b;
select_p_jinfo_dc_xhuff_tbl_bits_reg_a <= select_p_jinfo_dc_xhuff_tbl_bits_a;
select_p_jinfo_dc_xhuff_tbl_bits_reg_b <= select_p_jinfo_dc_xhuff_tbl_bits_b;
select_p_jinfo_dc_xhuff_tbl_huffval_reg_a <= select_p_jinfo_dc_xhuff_tbl_huffval_a;
select_p_jinfo_dc_xhuff_tbl_huffval_reg_b <= select_p_jinfo_dc_xhuff_tbl_huffval_b;
select_p_jinfo_quant_tbl_quantval_reg_a <= select_p_jinfo_quant_tbl_quantval_a;
select_p_jinfo_quant_tbl_quantval_reg_b <= select_p_jinfo_quant_tbl_quantval_b;
select_zigzag_index_reg_a <= select_zigzag_index_a;
select_zigzag_index_reg_b <= select_zigzag_index_b;
select_p_jinfo_MCUWidth_reg_a <= select_p_jinfo_MCUWidth_a;
select_p_jinfo_MCUWidth_reg_b <= select_p_jinfo_MCUWidth_b;
select_rgb_buf_reg_a <= select_rgb_buf_a;
select_rgb_buf_reg_b <= select_rgb_buf_b;
select_CurHuffReadBuf_reg_a <= select_CurHuffReadBuf_a;
select_CurHuffReadBuf_reg_b <= select_CurHuffReadBuf_b;
select_OutData_comp_buf_reg_a <= select_OutData_comp_buf_a;
select_OutData_comp_buf_reg_b <= select_OutData_comp_buf_b;
select_bit_set_mask_reg_a <= select_bit_set_mask_a;
select_bit_set_mask_reg_b <= select_bit_set_mask_b;
select_lmask_reg_a <= select_lmask_a;
select_lmask_reg_b <= select_lmask_b;
select_read_position_reg_a <= select_read_position_a;
select_read_position_reg_b <= select_read_position_b;
select_current_read_byte_reg_a <= select_current_read_byte_a;
select_current_read_byte_reg_b <= select_current_read_byte_b;
select_p_jinfo_dc_dhuff_tbl_ml_reg_a <= select_p_jinfo_dc_dhuff_tbl_ml_a;
select_p_jinfo_dc_dhuff_tbl_ml_reg_b <= select_p_jinfo_dc_dhuff_tbl_ml_b;
select_p_jinfo_dc_dhuff_tbl_maxcode_reg_a <= select_p_jinfo_dc_dhuff_tbl_maxcode_a;
select_p_jinfo_dc_dhuff_tbl_maxcode_reg_b <= select_p_jinfo_dc_dhuff_tbl_maxcode_b;
select_p_jinfo_dc_dhuff_tbl_mincode_reg_a <= select_p_jinfo_dc_dhuff_tbl_mincode_a;
select_p_jinfo_dc_dhuff_tbl_mincode_reg_b <= select_p_jinfo_dc_dhuff_tbl_mincode_b;
select_p_jinfo_dc_dhuff_tbl_valptr_reg_a <= select_p_jinfo_dc_dhuff_tbl_valptr_a;
select_p_jinfo_dc_dhuff_tbl_valptr_reg_b <= select_p_jinfo_dc_dhuff_tbl_valptr_b;
select_extend_mask_reg_a <= select_extend_mask_a;
select_extend_mask_reg_b <= select_extend_mask_b;
select_p_jinfo_ac_dhuff_tbl_ml_reg_a <= select_p_jinfo_ac_dhuff_tbl_ml_a;
select_p_jinfo_ac_dhuff_tbl_ml_reg_b <= select_p_jinfo_ac_dhuff_tbl_ml_b;
select_p_jinfo_ac_dhuff_tbl_maxcode_reg_a <= select_p_jinfo_ac_dhuff_tbl_maxcode_a;
select_p_jinfo_ac_dhuff_tbl_maxcode_reg_b <= select_p_jinfo_ac_dhuff_tbl_maxcode_b;
select_p_jinfo_ac_dhuff_tbl_mincode_reg_a <= select_p_jinfo_ac_dhuff_tbl_mincode_a;
select_p_jinfo_ac_dhuff_tbl_mincode_reg_b <= select_p_jinfo_ac_dhuff_tbl_mincode_b;
select_p_jinfo_ac_dhuff_tbl_valptr_reg_a <= select_p_jinfo_ac_dhuff_tbl_valptr_a;
select_p_jinfo_ac_dhuff_tbl_valptr_reg_b <= select_p_jinfo_ac_dhuff_tbl_valptr_b;
select_OutData_comp_vpos_reg_a <= select_OutData_comp_vpos_a;
select_OutData_comp_vpos_reg_b <= select_OutData_comp_vpos_b;
select_OutData_comp_hpos_reg_a <= select_OutData_comp_hpos_a;
select_OutData_comp_hpos_reg_b <= select_OutData_comp_hpos_b;
select_JpegFileBuf_reg_a <= select_JpegFileBuf_a;
select_JpegFileBuf_reg_b <= select_JpegFileBuf_b;
select_decode_block_0_QuantBuff_reg_a <= select_decode_block_0_QuantBuff_a;
select_decode_block_0_QuantBuff_reg_b <= select_decode_block_0_QuantBuff_b;
select_huff_make_dhuff_tb_0_huffsize_reg_a <= select_huff_make_dhuff_tb_0_huffsize_a;
select_huff_make_dhuff_tb_0_huffsize_reg_b <= select_huff_make_dhuff_tb_0_huffsize_b;
select_huff_make_dhuff_tb_0_huffcode_reg_a <= select_huff_make_dhuff_tb_0_huffcode_a;
select_huff_make_dhuff_tb_0_huffcode_reg_b <= select_huff_make_dhuff_tb_0_huffcode_b;
select_main_0_HuffBuff_i_i_reg_a <= select_main_0_HuffBuff_i_i_a;
select_main_0_HuffBuff_i_i_reg_b <= select_main_0_HuffBuff_i_i_b;
select_main_0_IDCTBuff_i_i_reg_a <= select_main_0_IDCTBuff_i_i_a;
select_main_0_IDCTBuff_i_i_reg_b <= select_main_0_IDCTBuff_i_i_b;
end
endmodule
`timescale 1 ns / 1 ns
module Write4Blocks
(
clk,
reset,
start,
finish,
arg_store1,
arg_store2,
arg_store3,
arg_store4,
arg_p_out_vpos,
arg_p_out_hpos,
arg_p_out_buf,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [5:0] LEGUP_0 = 6'd0;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_1 = 6'd1;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_2 = 6'd2;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_3 = 6'd3;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_4 = 6'd4;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_5 = 6'd5;
parameter [5:0] LEGUP_F_Write4Blocks_BB0_6 = 6'd6;
parameter [5:0] LEGUP_F_Write4Blocks_BB1_7 = 6'd7;
parameter [5:0] LEGUP_F_Write4Blocks_BB1_8 = 6'd8;
parameter [5:0] LEGUP_F_Write4Blocks_BB1_9 = 6'd9;
parameter [5:0] LEGUP_F_Write4Blocks_BB2_10 = 6'd10;
parameter [5:0] LEGUP_F_Write4Blocks_BB3_11 = 6'd11;
parameter [5:0] LEGUP_F_Write4Blocks_BB3_12 = 6'd12;
parameter [5:0] LEGUP_F_Write4Blocks_BB3_13 = 6'd13;
parameter [5:0] LEGUP_F_Write4Blocks_BB4_14 = 6'd14;
parameter [5:0] LEGUP_F_Write4Blocks_BB5_15 = 6'd15;
parameter [5:0] LEGUP_F_Write4Blocks_BB6_16 = 6'd16;
parameter [5:0] LEGUP_F_Write4Blocks_BB7_17 = 6'd17;
parameter [5:0] LEGUP_F_Write4Blocks_BB7_18 = 6'd18;
parameter [5:0] LEGUP_F_Write4Blocks_BB7_19 = 6'd19;
parameter [5:0] LEGUP_F_Write4Blocks_BB8_20 = 6'd20;
parameter [5:0] LEGUP_F_Write4Blocks_BB9_21 = 6'd21;
parameter [5:0] LEGUP_F_Write4Blocks_BB9_22 = 6'd22;
parameter [5:0] LEGUP_F_Write4Blocks_BB9_23 = 6'd23;
parameter [5:0] LEGUP_F_Write4Blocks_BB10_24 = 6'd24;
parameter [5:0] LEGUP_F_Write4Blocks_BB11_25 = 6'd25;
parameter [5:0] LEGUP_F_Write4Blocks_BB12_26 = 6'd26;
parameter [5:0] LEGUP_F_Write4Blocks_BB12_27 = 6'd27;
parameter [5:0] LEGUP_F_Write4Blocks_BB12_28 = 6'd28;
parameter [5:0] LEGUP_F_Write4Blocks_BB13_29 = 6'd29;
parameter [5:0] LEGUP_F_Write4Blocks_BB14_30 = 6'd30;
parameter [5:0] LEGUP_F_Write4Blocks_BB14_31 = 6'd31;
parameter [5:0] LEGUP_F_Write4Blocks_BB14_32 = 6'd32;
parameter [5:0] LEGUP_F_Write4Blocks_BB15_33 = 6'd33;
parameter [5:0] LEGUP_F_Write4Blocks_BB16_34 = 6'd34;
parameter [5:0] LEGUP_F_Write4Blocks_BB17_35 = 6'd35;
parameter [5:0] LEGUP_F_Write4Blocks_BB17_36 = 6'd36;
parameter [5:0] LEGUP_F_Write4Blocks_BB17_37 = 6'd37;
parameter [5:0] LEGUP_F_Write4Blocks_BB18_38 = 6'd38;
parameter [5:0] LEGUP_F_Write4Blocks_BB19_39 = 6'd39;
parameter [5:0] LEGUP_F_Write4Blocks_BB19_40 = 6'd40;
parameter [5:0] LEGUP_F_Write4Blocks_BB19_41 = 6'd41;
parameter [5:0] LEGUP_F_Write4Blocks_BB20_42 = 6'd42;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_43 = 6'd43;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_44 = 6'd44;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_45 = 6'd45;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_46 = 6'd46;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_47 = 6'd47;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_48 = 6'd48;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_49 = 6'd49;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_50 = 6'd50;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_51 = 6'd51;
parameter [5:0] LEGUP_F_Write4Blocks_BB21_52 = 6'd52;
parameter [5:0] LEGUP_F_Write4Blocks_BB22_53 = 6'd53;
parameter [5:0] LEGUP_F_Write4Blocks_BB23_54 = 6'd54;
parameter [5:0] LEGUP_F_Write4Blocks_BB24_55 = 6'd55;
input clk;
input reset;
input start;
output reg finish;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_store1;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_store2;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_store3;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_store4;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_out_vpos;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_out_hpos;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_out_buf;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [5:0] cur_state;
reg [31:0] Write4Blocks_0_1;
reg [31:0] Write4Blocks_0_1_reg;
reg [31:0] Write4Blocks_0_2;
reg [31:0] Write4Blocks_0_2_reg;
reg [31:0] Write4Blocks_0_3;
reg [31:0] Write4Blocks_0_4;
reg [31:0] Write4Blocks_0_4_reg;
reg [15:0] Write4Blocks_0_5;
reg [31:0] Write4Blocks_0_6;
reg [31:0] Write4Blocks_0_6_reg;
reg [15:0] Write4Blocks_0_7;
reg [31:0] Write4Blocks_0_8;
reg [31:0] Write4Blocks_0_8_reg;
reg Write4Blocks_0_9;
reg Write4Blocks_0_9_reg;
reg Write4Blocks_0_10;
reg Write4Blocks_0_10_reg;
reg Write4Blocks_0_or_cond_i;
reg [31:0] Write4Blocks_0_tmp287;
reg [31:0] Write4Blocks_0_tmp287_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp288340;
reg Write4Blocks__lr_ph8_split_us_i_tmp289;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_smax290;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp291;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp291_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp293;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp293_reg;
reg Write4Blocks__lr_ph8_split_us_i_tmp294;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_umax295;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp296;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp296_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp307;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp308341;
reg Write4Blocks__lr_ph8_split_us_i_tmp309;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_smax310;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_smax310_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp311;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp313;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp313_reg;
reg Write4Blocks__lr_ph8_split_us_i_tmp314;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_umax315;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_umax315_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp316;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp316_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp332;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp333;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp334;
reg [31:0] Write4Blocks__lr_ph8_split_us_i_tmp334_reg;
reg [31:0] Write4Blocks_11_indvar_next18_i;
reg Write4Blocks_11_exitcond317;
reg [31:0] Write4Blocks_12_indvar_i;
reg [31:0] Write4Blocks_12_tmp330;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_12__14_us_i;
reg [31:0] Write4Blocks_12_tmp336;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_12_scevgep24_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_12_scevgep24_i_reg;
reg [31:0] Write4Blocks_12_13;
reg [7:0] Write4Blocks_12_14;
reg [31:0] Write4Blocks_12_indvar_next_i;
reg [31:0] Write4Blocks_12_indvar_next_i_reg;
reg Write4Blocks_12_exitcond297;
reg Write4Blocks_12_exitcond297_reg;
reg [31:0] Write4Blocks__lr_ph_us_i_indvar17_i;
reg [31:0] Write4Blocks__lr_ph_us_i_indvar17_i_reg;
reg [31:0] Write4Blocks__lr_ph_us_i_tmp329;
reg [31:0] Write4Blocks__lr_ph_us_i_tmp329_reg;
reg [31:0] Write4Blocks__lr_ph_us_i_tmp331;
reg [31:0] Write4Blocks__lr_ph_us_i_tmp335;
reg [31:0] Write4Blocks__lr_ph_us_i_tmp335_reg;
reg Write4Blocks_WriteOneBlock_exit_15;
reg Write4Blocks_WriteOneBlock_exit_15_reg;
reg Write4Blocks_WriteOneBlock_exit_or_cond_i75;
reg [31:0] Write4Blocks_WriteOneBlock_exit_WriteOneBlock_exit111_crit_edge__pre349;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp232;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp233;
reg Write4Blocks__lr_ph8_split_us_i96_tmp234;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_smax235;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_smax235_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp236;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp238;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp238_reg;
reg Write4Blocks__lr_ph8_split_us_i96_tmp239;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_umax240;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_umax240_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp241;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp241_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp254;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp254_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp255339;
reg Write4Blocks__lr_ph8_split_us_i96_tmp256;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_smax257;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_smax257_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp258;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp260;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp260_reg;
reg Write4Blocks__lr_ph8_split_us_i96_tmp261;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_umax262;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_umax262_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp263;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp263_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp280;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp281;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp282;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp282_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp283;
reg [31:0] Write4Blocks__lr_ph8_split_us_i96_tmp283_reg;
reg [31:0] Write4Blocks_16_indvar_next18_i98;
reg Write4Blocks_16_exitcond264;
reg [31:0] Write4Blocks_17_indvar_i100;
reg [31:0] Write4Blocks_17_tmp278;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_17__14_us_i103;
reg [31:0] Write4Blocks_17_tmp285;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_17_scevgep24_i102;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_17_scevgep24_i102_reg;
reg [31:0] Write4Blocks_17_18;
reg [7:0] Write4Blocks_17_19;
reg [31:0] Write4Blocks_17_indvar_next_i104;
reg [31:0] Write4Blocks_17_indvar_next_i104_reg;
reg Write4Blocks_17_exitcond242;
reg Write4Blocks_17_exitcond242_reg;
reg [31:0] Write4Blocks__lr_ph_us_i110_indvar17_i106;
reg [31:0] Write4Blocks__lr_ph_us_i110_indvar17_i106_reg;
reg [31:0] Write4Blocks__lr_ph_us_i110_tmp277;
reg [31:0] Write4Blocks__lr_ph_us_i110_tmp277_reg;
reg [31:0] Write4Blocks__lr_ph_us_i110_tmp279;
reg [31:0] Write4Blocks__lr_ph_us_i110_tmp284;
reg [31:0] Write4Blocks__lr_ph_us_i110_tmp284_reg;
reg [31:0] Write4Blocks_WriteOneBlock_exit111__pre_phi350;
reg [31:0] Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg;
reg Write4Blocks_WriteOneBlock_exit111_20;
reg Write4Blocks_WriteOneBlock_exit111_20_reg;
reg Write4Blocks_WriteOneBlock_exit111_or_cond_i38;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp179337;
reg Write4Blocks__lr_ph8_split_us_i59_tmp180;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_smax181;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp182;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp182_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp184;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp184_reg;
reg Write4Blocks__lr_ph8_split_us_i59_tmp185;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_umax186;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp187;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp187_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp199;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp200;
reg Write4Blocks__lr_ph8_split_us_i59_tmp201;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_smax202;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_smax202_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp203;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp206;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp206_reg;
reg Write4Blocks__lr_ph8_split_us_i59_tmp207;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_umax208;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_umax208_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp209;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp209_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp226;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp227;
reg [31:0] Write4Blocks__lr_ph8_split_us_i59_tmp227_reg;
reg [31:0] Write4Blocks_21_indvar_next18_i61;
reg Write4Blocks_21_exitcond210;
reg [31:0] Write4Blocks_22_indvar_i63;
reg [31:0] Write4Blocks_22_tmp223;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_22__14_us_i66;
reg [31:0] Write4Blocks_22_tmp229;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_22_scevgep24_i65;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_22_scevgep24_i65_reg;
reg [31:0] Write4Blocks_22_23;
reg [7:0] Write4Blocks_22_24;
reg [31:0] Write4Blocks_22_indvar_next_i67;
reg [31:0] Write4Blocks_22_indvar_next_i67_reg;
reg Write4Blocks_22_exitcond188;
reg Write4Blocks_22_exitcond188_reg;
reg [31:0] Write4Blocks__lr_ph_us_i73_indvar17_i69;
reg [31:0] Write4Blocks__lr_ph_us_i73_indvar17_i69_reg;
reg [31:0] Write4Blocks__lr_ph_us_i73_tmp222;
reg [31:0] Write4Blocks__lr_ph_us_i73_tmp222_reg;
reg [31:0] Write4Blocks__lr_ph_us_i73_tmp224;
reg [31:0] Write4Blocks__lr_ph_us_i73_tmp228;
reg [31:0] Write4Blocks__lr_ph_us_i73_tmp228_reg;
reg Write4Blocks_WriteOneBlock_exit74_or_cond_i1;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp125;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp126;
reg Write4Blocks__lr_ph8_split_us_i22_tmp127;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_smax;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_smax_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp128;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp130;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp130_reg;
reg Write4Blocks__lr_ph8_split_us_i22_tmp131;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_umax;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_umax_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp132;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp132_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp144;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp145;
reg Write4Blocks__lr_ph8_split_us_i22_tmp146;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_smax147;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_smax147_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp148;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp151;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp151_reg;
reg Write4Blocks__lr_ph8_split_us_i22_tmp152;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_umax153;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_umax153_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp154;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp154_reg;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp172;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp173;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp174;
reg [31:0] Write4Blocks__lr_ph8_split_us_i22_tmp174_reg;
reg [31:0] Write4Blocks_25_indvar_next18_i24;
reg Write4Blocks_25_exitcond155;
reg [31:0] Write4Blocks_26_indvar_i26;
reg [31:0] Write4Blocks_26_tmp169;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_26__14_us_i29;
reg [31:0] Write4Blocks_26_tmp176;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_26_scevgep24_i28;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_26_scevgep24_i28_reg;
reg [31:0] Write4Blocks_26_27;
reg [7:0] Write4Blocks_26_28;
reg [31:0] Write4Blocks_26_indvar_next_i30;
reg [31:0] Write4Blocks_26_indvar_next_i30_reg;
reg Write4Blocks_26_exitcond;
reg Write4Blocks_26_exitcond_reg;
reg [31:0] Write4Blocks__lr_ph_us_i36_indvar17_i32;
reg [31:0] Write4Blocks__lr_ph_us_i36_indvar17_i32_reg;
reg [31:0] Write4Blocks__lr_ph_us_i36_tmp168;
reg [31:0] Write4Blocks__lr_ph_us_i36_tmp168_reg;
reg [31:0] Write4Blocks__lr_ph_us_i36_tmp170;
reg [31:0] Write4Blocks__lr_ph_us_i36_tmp175;
reg [31:0] Write4Blocks__lr_ph_us_i36_tmp175_reg;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_29;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_30;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_31;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_31_reg;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_32;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_33;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_33_reg;
reg [31:0] Write4Blocks_WriteOneBlock_exit37_34;
reg Write4Blocks_WriteOneBlock_exit37_35;
reg [31:0] Write4Blocks_signed_multiply_32_0_op0;
reg [31:0] Write4Blocks_signed_multiply_32_0_op1;
reg [31:0] Write4Blocks_signed_multiply_32_0;
reg [31:0] Write4Blocks_signed_multiply_32_1_op0;
reg [31:0] Write4Blocks_signed_multiply_32_1_op1;
reg [31:0] Write4Blocks_signed_multiply_32_1;
reg [31:0] Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp;
reg [31:0] Write4Blocks_12_indvar_i_phi_temp;
reg [31:0] Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
reg [31:0] Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp;
reg [31:0] Write4Blocks_17_indvar_i100_phi_temp;
reg [31:0] Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp;
reg [31:0] Write4Blocks_22_indvar_i63_phi_temp;
reg [31:0] Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp;
reg [31:0] Write4Blocks_26_indvar_i26_phi_temp;
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 6'd0;
if (^reset !== 1'bX && ^(6'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_3 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_4;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_4;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_4 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_5;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_5;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_6;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB0_6;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB0_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_6 & memory_controller_waitrequest == 1'd0 & Write4Blocks_0_or_cond_i == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_7;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB0_6 & memory_controller_waitrequest == 1'd0 & Write4Blocks_0_or_cond_i == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB5_15;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB5_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_7;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_7 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_8;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_8;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_8 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_9;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB1_9;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB1_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB1_9 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB4_14;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB4_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB2_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB2_10;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB2_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB2_10 & memory_controller_waitrequest == 1'd0 & Write4Blocks_11_exitcond317 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB5_15;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB5_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB2_10 & memory_controller_waitrequest == 1'd0 & Write4Blocks_11_exitcond317 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB4_14;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB4_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_11;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_12;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_12;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_12 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_13 & memory_controller_waitrequest == 1'd0 & Write4Blocks_12_exitcond297_reg == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB2_10;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB2_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB3_13 & memory_controller_waitrequest == 1'd0 & Write4Blocks_12_exitcond297_reg == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_11;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB4_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB4_14;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB4_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB4_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB3_11;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB3_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB5_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB5_15;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB5_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB5_15 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit_or_cond_i75 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_17;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB5_15 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit_or_cond_i75 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB6_16;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB6_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB6_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB6_16;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB6_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB6_16 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB11_25;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB11_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_17;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_17 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_18;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_18;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_18 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_19;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB7_19;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB7_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB7_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB10_24;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB10_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB8_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB8_20;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB8_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB8_20 & memory_controller_waitrequest == 1'd0 & Write4Blocks_16_exitcond264 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB11_25;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB11_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB8_20 & memory_controller_waitrequest == 1'd0 & Write4Blocks_16_exitcond264 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB10_24;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB10_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_21;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_21 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_22;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_22;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_22 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_23;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_23;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_23 & memory_controller_waitrequest == 1'd0 & Write4Blocks_17_exitcond242_reg == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB8_20;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB8_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB9_23 & memory_controller_waitrequest == 1'd0 & Write4Blocks_17_exitcond242_reg == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_21;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB10_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB10_24;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB10_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB10_24 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB9_21;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB9_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB11_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB11_25;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB11_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB11_25 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit111_or_cond_i38 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_26;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB11_25 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit111_or_cond_i38 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB16_34;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB16_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_26;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_26 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_27;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_27;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_27 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_28;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB12_28;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB12_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB12_28 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB15_33;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB15_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB13_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB13_29;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB13_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB13_29 & memory_controller_waitrequest == 1'd0 & Write4Blocks_21_exitcond210 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB16_34;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB16_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB13_29 & memory_controller_waitrequest == 1'd0 & Write4Blocks_21_exitcond210 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB15_33;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB15_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_30;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_30 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_31;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_31;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_32;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_32;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_32 & memory_controller_waitrequest == 1'd0 & Write4Blocks_22_exitcond188_reg == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB13_29;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB13_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB14_32 & memory_controller_waitrequest == 1'd0 & Write4Blocks_22_exitcond188_reg == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_30;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB15_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB15_33;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB15_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB15_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB14_30;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB14_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB16_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB16_34;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB16_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB16_34 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit74_or_cond_i1 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_35;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB16_34 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit74_or_cond_i1 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_43;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_35;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_35 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_36;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_36;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_36 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_37;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB17_37;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB17_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB17_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB20_42;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB20_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB18_38 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB18_38;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB18_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB18_38 & memory_controller_waitrequest == 1'd0 & Write4Blocks_25_exitcond155 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_43;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB18_38 & memory_controller_waitrequest == 1'd0 & Write4Blocks_25_exitcond155 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB20_42;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB20_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_39 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_39;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_39 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_40;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_40 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_40;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_40 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_41;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_41 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_41;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_41 & memory_controller_waitrequest == 1'd0 & Write4Blocks_26_exitcond_reg == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB18_38;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB18_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB19_41 & memory_controller_waitrequest == 1'd0 & Write4Blocks_26_exitcond_reg == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_39;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB20_42 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB20_42;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB20_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB20_42 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB19_39;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB19_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_43 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_43;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_43 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_44;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_44 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_44;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_44 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_45;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_45 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_45;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_45 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_46;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_46 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_46;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_46 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_47;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_47 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_47;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_47 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_48;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_48 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_48;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_48 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_49;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_49 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_49;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_49 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_50;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_50 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_50;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_50 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_51;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_51 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_51;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_51 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_52;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_52 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB21_52;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB21_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_52 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit37_35 == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB22_53;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB22_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB21_52 & memory_controller_waitrequest == 1'd0 & Write4Blocks_WriteOneBlock_exit37_35 == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB23_54;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB23_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB22_53 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB22_53;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB22_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB22_53 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB24_55;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB24_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB23_54 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB23_54;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB23_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB23_54 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_Write4Blocks_BB24_55;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB24_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB24_55 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_Write4Blocks_BB24_55;
if (^reset !== 1'bX && ^(LEGUP_F_Write4Blocks_BB24_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_Write4Blocks_BB24_55 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
begin
Write4Blocks_0_1 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
Write4Blocks_0_1_reg <= Write4Blocks_0_1;
if (^reset !== 1'bX && ^(Write4Blocks_0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_1_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %2 = shl nsw i32 %1, 3*/
begin
Write4Blocks_0_2 = Write4Blocks_0_1 <<< 32'd3 % 32;
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %2 = shl nsw i32 %1, 3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
Write4Blocks_0_2_reg <= Write4Blocks_0_2;
if (^reset !== 1'bX && ^(Write4Blocks_0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_2_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %3 = load i32* %p_out_hpos, align 4, !tbaa !0*/
begin
Write4Blocks_0_3 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %4 = shl nsw i32 %3, 3*/
begin
Write4Blocks_0_4 = Write4Blocks_0_3 <<< 32'd3 % 32;
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %4 = shl nsw i32 %3, 3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
Write4Blocks_0_4_reg <= Write4Blocks_0_4;
if (^reset !== 1'bX && ^(Write4Blocks_0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_4_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %5 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
begin
Write4Blocks_0_5 = memory_controller_out[15:0];
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %6 = sext i16 %5 to i32*/
begin
Write4Blocks_0_6 = $signed(Write4Blocks_0_5);
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %6 = sext i16 %5 to i32*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_5)
begin
Write4Blocks_0_6_reg <= Write4Blocks_0_6;
if (^reset !== 1'bX && ^(Write4Blocks_0_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_6_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %7 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
begin
Write4Blocks_0_7 = memory_controller_out[15:0];
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %8 = sext i16 %7 to i32*/
begin
Write4Blocks_0_8 = $signed(Write4Blocks_0_7);
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %8 = sext i16 %7 to i32*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_6)
begin
Write4Blocks_0_8_reg <= Write4Blocks_0_8;
if (^reset !== 1'bX && ^(Write4Blocks_0_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_8_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %9 = icmp slt i32 %2, %8*/
begin
Write4Blocks_0_9 = $signed(Write4Blocks_0_2_reg) < $signed(Write4Blocks_0_8);
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %9 = icmp slt i32 %2, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_6)
begin
Write4Blocks_0_9_reg <= Write4Blocks_0_9;
if (^reset !== 1'bX && ^(Write4Blocks_0_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_9_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %10 = icmp slt i32 %4, %6*/
begin
Write4Blocks_0_10 = $signed(Write4Blocks_0_4_reg) < $signed(Write4Blocks_0_6);
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %10 = icmp slt i32 %4, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_5)
begin
Write4Blocks_0_10_reg <= Write4Blocks_0_10;
if (^reset !== 1'bX && ^(Write4Blocks_0_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_10_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %or.cond.i = and i1 %9, %10*/
begin
Write4Blocks_0_or_cond_i = Write4Blocks_0_9 & Write4Blocks_0_10_reg;
end
end
always @(*) begin
/* Write4Blocks: %0*/
/* %tmp287 = add i32 %4, 8*/
begin
Write4Blocks_0_tmp287 = Write4Blocks_0_4 + 32'd8;
end
end
always @(posedge clk) begin
/* Write4Blocks: %0*/
/* %tmp287 = add i32 %4, 8*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
Write4Blocks_0_tmp287_reg <= Write4Blocks_0_tmp287;
if (^reset !== 1'bX && ^(Write4Blocks_0_tmp287) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_0_tmp287_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp288340 = or i32 %4, 1*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp288340 = Write4Blocks_0_4_reg | 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp289 = icmp sgt i32 %tmp287, %tmp288340*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp289 = $signed(Write4Blocks_0_tmp287_reg) > $signed(Write4Blocks__lr_ph8_split_us_i_tmp288340);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %smax290 = select i1 %tmp289, i32 %tmp287, i32 %tmp288340*/
begin
Write4Blocks__lr_ph8_split_us_i_smax290 = (Write4Blocks__lr_ph8_split_us_i_tmp289 ? Write4Blocks_0_tmp287_reg : Write4Blocks__lr_ph8_split_us_i_tmp288340);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp291 = sub i32 %4, %smax290*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp291 = Write4Blocks_0_4_reg - Write4Blocks__lr_ph8_split_us_i_smax290;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp291 = sub i32 %4, %smax290*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks__lr_ph8_split_us_i_tmp291_reg <= Write4Blocks__lr_ph8_split_us_i_tmp291;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp291) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp291_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp293 = sub i32 %4, %6*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp293 = Write4Blocks_0_4_reg - Write4Blocks_0_6_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp293 = sub i32 %4, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks__lr_ph8_split_us_i_tmp293_reg <= Write4Blocks__lr_ph8_split_us_i_tmp293;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp293) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp293_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp294 = icmp ugt i32 %tmp291, %tmp293*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp294 = Write4Blocks__lr_ph8_split_us_i_tmp291_reg > Write4Blocks__lr_ph8_split_us_i_tmp293_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %umax295 = select i1 %tmp294, i32 %tmp291, i32 %tmp293*/
begin
Write4Blocks__lr_ph8_split_us_i_umax295 = (Write4Blocks__lr_ph8_split_us_i_tmp294 ? Write4Blocks__lr_ph8_split_us_i_tmp291_reg : Write4Blocks__lr_ph8_split_us_i_tmp293_reg);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp296 = sub i32 0, %umax295*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp296 = 32'd0 - Write4Blocks__lr_ph8_split_us_i_umax295;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp296 = sub i32 0, %umax295*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_8)
begin
Write4Blocks__lr_ph8_split_us_i_tmp296_reg <= Write4Blocks__lr_ph8_split_us_i_tmp296;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp296) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp296_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp307 = add i32 %2, 8*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp307 = Write4Blocks_0_2_reg + 32'd8;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp308341 = or i32 %2, 1*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp308341 = Write4Blocks_0_2_reg | 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp309 = icmp sgt i32 %tmp307, %tmp308341*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp309 = $signed(Write4Blocks__lr_ph8_split_us_i_tmp307) > $signed(Write4Blocks__lr_ph8_split_us_i_tmp308341);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %smax310 = select i1 %tmp309, i32 %tmp307, i32 %tmp308341*/
begin
Write4Blocks__lr_ph8_split_us_i_smax310 = (Write4Blocks__lr_ph8_split_us_i_tmp309 ? Write4Blocks__lr_ph8_split_us_i_tmp307 : Write4Blocks__lr_ph8_split_us_i_tmp308341);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %smax310 = select i1 %tmp309, i32 %tmp307, i32 %tmp308341*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks__lr_ph8_split_us_i_smax310_reg <= Write4Blocks__lr_ph8_split_us_i_smax310;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_smax310) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_smax310_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp311 = sub i32 %2, %smax310*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp311 = Write4Blocks_0_2_reg - Write4Blocks__lr_ph8_split_us_i_smax310_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp313 = sub i32 %2, %8*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp313 = Write4Blocks_0_2_reg - Write4Blocks_0_8_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp313 = sub i32 %2, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks__lr_ph8_split_us_i_tmp313_reg <= Write4Blocks__lr_ph8_split_us_i_tmp313;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp313) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp313_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp314 = icmp ugt i32 %tmp311, %tmp313*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp314 = Write4Blocks__lr_ph8_split_us_i_tmp311 > Write4Blocks__lr_ph8_split_us_i_tmp313_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %umax315 = select i1 %tmp314, i32 %tmp311, i32 %tmp313*/
begin
Write4Blocks__lr_ph8_split_us_i_umax315 = (Write4Blocks__lr_ph8_split_us_i_tmp314 ? Write4Blocks__lr_ph8_split_us_i_tmp311 : Write4Blocks__lr_ph8_split_us_i_tmp313_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %umax315 = select i1 %tmp314, i32 %tmp311, i32 %tmp313*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_8)
begin
Write4Blocks__lr_ph8_split_us_i_umax315_reg <= Write4Blocks__lr_ph8_split_us_i_umax315;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_umax315) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_umax315_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp316 = sub i32 0, %umax315*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp316 = 32'd0 - Write4Blocks__lr_ph8_split_us_i_umax315_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp316 = sub i32 0, %umax315*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_9)
begin
Write4Blocks__lr_ph8_split_us_i_tmp316_reg <= Write4Blocks__lr_ph8_split_us_i_tmp316;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp316) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp316_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp332 = mul i32 %1, %6*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp332 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp333 = shl i32 %tmp332, 3*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp333 = Write4Blocks__lr_ph8_split_us_i_tmp332 <<< 32'd3 % 32;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp334 = add i32 %4, %tmp333*/
begin
Write4Blocks__lr_ph8_split_us_i_tmp334 = Write4Blocks_0_4_reg + Write4Blocks__lr_ph8_split_us_i_tmp333;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp334 = add i32 %4, %tmp333*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks__lr_ph8_split_us_i_tmp334_reg <= Write4Blocks__lr_ph8_split_us_i_tmp334;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i_tmp334) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i_tmp334_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %11*/
/* %indvar.next18.i = add i32 %indvar17.i, 1*/
begin
Write4Blocks_11_indvar_next18_i = Write4Blocks__lr_ph_us_i_indvar17_i_reg + 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %11*/
/* %exitcond317 = icmp eq i32 %indvar.next18.i, %tmp316*/
begin
Write4Blocks_11_exitcond317 = Write4Blocks_11_indvar_next18_i == Write4Blocks__lr_ph8_split_us_i_tmp316_reg;
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %indvar.i = phi i32 [ 0, %.lr.ph.us.i ], [ %indvar.next.i, %12 ]*/
begin
Write4Blocks_12_indvar_i = Write4Blocks_12_indvar_i_phi_temp;
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %tmp330 = add i32 %tmp329, %indvar.i*/
begin
Write4Blocks_12_tmp330 = Write4Blocks__lr_ph_us_i_tmp329_reg + Write4Blocks_12_indvar_i;
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %.14.us.i = getelementptr i32* %store1, i32 %tmp330*/
begin
Write4Blocks_12__14_us_i = arg_store1 + 4 * Write4Blocks_12_tmp330;
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %tmp336 = add i32 %tmp335, %indvar.i*/
begin
Write4Blocks_12_tmp336 = Write4Blocks__lr_ph_us_i_tmp335_reg + Write4Blocks_12_indvar_i;
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %scevgep24.i = getelementptr i8* %p_out_buf, i32 %tmp336*/
begin
Write4Blocks_12_scevgep24_i = arg_p_out_buf + 1 * Write4Blocks_12_tmp336;
end
end
always @(posedge clk) begin
/* Write4Blocks: %12*/
/* %scevgep24.i = getelementptr i8* %p_out_buf, i32 %tmp336*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
Write4Blocks_12_scevgep24_i_reg <= Write4Blocks_12_scevgep24_i;
if (^reset !== 1'bX && ^(Write4Blocks_12_scevgep24_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_12_scevgep24_i_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %13 = load i32* %.14.us.i, align 4, !tbaa !0*/
begin
Write4Blocks_12_13 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %14 = trunc i32 %13 to i8*/
begin
Write4Blocks_12_14 = Write4Blocks_12_13[7:0];
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %indvar.next.i = add i32 %indvar.i, 1*/
begin
Write4Blocks_12_indvar_next_i = Write4Blocks_12_indvar_i + 32'd1;
end
end
always @(posedge clk) begin
/* Write4Blocks: %12*/
/* %indvar.next.i = add i32 %indvar.i, 1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
Write4Blocks_12_indvar_next_i_reg <= Write4Blocks_12_indvar_next_i;
if (^reset !== 1'bX && ^(Write4Blocks_12_indvar_next_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_12_indvar_next_i_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %12*/
/* %exitcond297 = icmp eq i32 %indvar.next.i, %tmp296*/
begin
Write4Blocks_12_exitcond297 = Write4Blocks_12_indvar_next_i == Write4Blocks__lr_ph8_split_us_i_tmp296_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %12*/
/* %exitcond297 = icmp eq i32 %indvar.next.i, %tmp296*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
Write4Blocks_12_exitcond297_reg <= Write4Blocks_12_exitcond297;
if (^reset !== 1'bX && ^(Write4Blocks_12_exitcond297) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_12_exitcond297_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i_indvar17_i = Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp;
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB4_14) */
begin
Write4Blocks__lr_ph_us_i_indvar17_i = Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i_indvar17_i_reg <= Write4Blocks__lr_ph_us_i_indvar17_i;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i_indvar17_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_indvar17_i_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i_indvar17_i_reg <= Write4Blocks__lr_ph_us_i_indvar17_i;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i_indvar17_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_indvar17_i_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i_indvar17_i_reg <= Write4Blocks__lr_ph_us_i_indvar17_i;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i_indvar17_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_indvar17_i_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp329 = mul i32 %indvar17.i, %tmp296*/
begin
Write4Blocks__lr_ph_us_i_tmp329 = Write4Blocks_signed_multiply_32_1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp329 = mul i32 %indvar17.i, %tmp296*/
Write4Blocks__lr_ph_us_i_tmp329_reg = Write4Blocks__lr_ph_us_i36_tmp168_reg;
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp331 = mul i32 %6, %indvar17.i*/
begin
Write4Blocks__lr_ph_us_i_tmp331 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp335 = add i32 %tmp334, %tmp331*/
begin
Write4Blocks__lr_ph_us_i_tmp335 = Write4Blocks__lr_ph8_split_us_i_tmp334_reg + Write4Blocks__lr_ph_us_i_tmp331;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp335 = add i32 %tmp334, %tmp331*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i_tmp335_reg <= Write4Blocks__lr_ph_us_i_tmp335;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i_tmp335) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_tmp335_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit*/
/* %15 = icmp slt i32 %tmp287, %6*/
begin
Write4Blocks_WriteOneBlock_exit_15 = $signed(Write4Blocks_0_tmp287_reg) < $signed(Write4Blocks_0_6_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit*/
/* %15 = icmp slt i32 %tmp287, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB5_15)
begin
Write4Blocks_WriteOneBlock_exit_15_reg <= Write4Blocks_WriteOneBlock_exit_15;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit_15_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit*/
/* %or.cond.i75 = and i1 %9, %15*/
begin
Write4Blocks_WriteOneBlock_exit_or_cond_i75 = Write4Blocks_0_9_reg & Write4Blocks_WriteOneBlock_exit_15;
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge*/
/* %.pre349 = add nsw i32 %2, 8*/
begin
Write4Blocks_WriteOneBlock_exit_WriteOneBlock_exit111_crit_edge__pre349 = Write4Blocks_0_2_reg + 32'd8;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp232 = add i32 %4, 16*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp232 = Write4Blocks_0_4_reg + 32'd16;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp233 = add i32 %4, 9*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp233 = Write4Blocks_0_4_reg + 32'd9;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp234 = icmp sgt i32 %tmp232, %tmp233*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp234 = $signed(Write4Blocks__lr_ph8_split_us_i96_tmp232) > $signed(Write4Blocks__lr_ph8_split_us_i96_tmp233);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %smax235 = select i1 %tmp234, i32 %tmp232, i32 %tmp233*/
begin
Write4Blocks__lr_ph8_split_us_i96_smax235 = (Write4Blocks__lr_ph8_split_us_i96_tmp234 ? Write4Blocks__lr_ph8_split_us_i96_tmp232 : Write4Blocks__lr_ph8_split_us_i96_tmp233);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %smax235 = select i1 %tmp234, i32 %tmp232, i32 %tmp233*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_smax235_reg <= Write4Blocks__lr_ph8_split_us_i96_smax235;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_smax235) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_smax235_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp236 = sub i32 %tmp287, %smax235*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp236 = Write4Blocks_0_tmp287_reg - Write4Blocks__lr_ph8_split_us_i96_smax235_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp238 = sub i32 %tmp287, %6*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp238 = Write4Blocks_0_tmp287_reg - Write4Blocks_0_6_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp238 = sub i32 %tmp287, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp238_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp238;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp238) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp238_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp239 = icmp ugt i32 %tmp236, %tmp238*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp239 = Write4Blocks__lr_ph8_split_us_i96_tmp236 > Write4Blocks__lr_ph8_split_us_i96_tmp238_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %umax240 = select i1 %tmp239, i32 %tmp236, i32 %tmp238*/
begin
Write4Blocks__lr_ph8_split_us_i96_umax240 = (Write4Blocks__lr_ph8_split_us_i96_tmp239 ? Write4Blocks__lr_ph8_split_us_i96_tmp236 : Write4Blocks__lr_ph8_split_us_i96_tmp238_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %umax240 = select i1 %tmp239, i32 %tmp236, i32 %tmp238*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_18)
begin
Write4Blocks__lr_ph8_split_us_i96_umax240_reg <= Write4Blocks__lr_ph8_split_us_i96_umax240;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_umax240) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_umax240_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp241 = sub i32 0, %umax240*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp241 = 32'd0 - Write4Blocks__lr_ph8_split_us_i96_umax240_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp241 = sub i32 0, %umax240*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_19)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp241_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp241;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp241) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp241_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp254 = add i32 %2, 8*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp254 = Write4Blocks_0_2_reg + 32'd8;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp254 = add i32 %2, 8*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp254_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp254;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp254) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp254_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp255339 = or i32 %2, 1*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp255339 = Write4Blocks_0_2_reg | 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp256 = icmp sgt i32 %tmp254, %tmp255339*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp256 = $signed(Write4Blocks__lr_ph8_split_us_i96_tmp254) > $signed(Write4Blocks__lr_ph8_split_us_i96_tmp255339);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %smax257 = select i1 %tmp256, i32 %tmp254, i32 %tmp255339*/
begin
Write4Blocks__lr_ph8_split_us_i96_smax257 = (Write4Blocks__lr_ph8_split_us_i96_tmp256 ? Write4Blocks__lr_ph8_split_us_i96_tmp254 : Write4Blocks__lr_ph8_split_us_i96_tmp255339);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %smax257 = select i1 %tmp256, i32 %tmp254, i32 %tmp255339*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_smax257_reg <= Write4Blocks__lr_ph8_split_us_i96_smax257;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_smax257) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_smax257_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp258 = sub i32 %2, %smax257*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp258 = Write4Blocks_0_2_reg - Write4Blocks__lr_ph8_split_us_i96_smax257_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp260 = sub i32 %2, %8*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp260 = Write4Blocks_0_2_reg - Write4Blocks_0_8_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp260 = sub i32 %2, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp260_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp260;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp260) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp260_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp261 = icmp ugt i32 %tmp258, %tmp260*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp261 = Write4Blocks__lr_ph8_split_us_i96_tmp258 > Write4Blocks__lr_ph8_split_us_i96_tmp260_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %umax262 = select i1 %tmp261, i32 %tmp258, i32 %tmp260*/
begin
Write4Blocks__lr_ph8_split_us_i96_umax262 = (Write4Blocks__lr_ph8_split_us_i96_tmp261 ? Write4Blocks__lr_ph8_split_us_i96_tmp258 : Write4Blocks__lr_ph8_split_us_i96_tmp260_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %umax262 = select i1 %tmp261, i32 %tmp258, i32 %tmp260*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_18)
begin
Write4Blocks__lr_ph8_split_us_i96_umax262_reg <= Write4Blocks__lr_ph8_split_us_i96_umax262;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_umax262) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_umax262_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp263 = sub i32 0, %umax262*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp263 = 32'd0 - Write4Blocks__lr_ph8_split_us_i96_umax262_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp263 = sub i32 0, %umax262*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_19)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp263_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp263;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp263) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp263_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp280 = mul i32 %1, %6*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp280 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp281 = shl i32 %tmp280, 3*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp281 = Write4Blocks__lr_ph8_split_us_i96_tmp280 <<< 32'd3 % 32;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp282 = add i32 %4, %tmp281*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp282 = Write4Blocks_0_4_reg + Write4Blocks__lr_ph8_split_us_i96_tmp281;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp282 = add i32 %4, %tmp281*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp282_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp282;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp282) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp282_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp283 = add i32 %tmp282, 8*/
begin
Write4Blocks__lr_ph8_split_us_i96_tmp283 = Write4Blocks__lr_ph8_split_us_i96_tmp282_reg + 32'd8;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp283 = add i32 %tmp282, 8*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_18)
begin
Write4Blocks__lr_ph8_split_us_i96_tmp283_reg <= Write4Blocks__lr_ph8_split_us_i96_tmp283;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp283) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i96_tmp283_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %16*/
/* %indvar.next18.i98 = add i32 %indvar17.i106, 1*/
begin
Write4Blocks_16_indvar_next18_i98 = Write4Blocks__lr_ph_us_i110_indvar17_i106_reg + 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %16*/
/* %exitcond264 = icmp eq i32 %indvar.next18.i98, %tmp263*/
begin
Write4Blocks_16_exitcond264 = Write4Blocks_16_indvar_next18_i98 == Write4Blocks__lr_ph8_split_us_i96_tmp263_reg;
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %indvar.i100 = phi i32 [ 0, %.lr.ph.us.i110 ], [ %indvar.next.i104, %17 ]*/
begin
Write4Blocks_17_indvar_i100 = Write4Blocks_17_indvar_i100_phi_temp;
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %tmp278 = add i32 %tmp277, %indvar.i100*/
begin
Write4Blocks_17_tmp278 = Write4Blocks__lr_ph_us_i110_tmp277_reg + Write4Blocks_17_indvar_i100;
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %.14.us.i103 = getelementptr i32* %store2, i32 %tmp278*/
begin
Write4Blocks_17__14_us_i103 = arg_store2 + 4 * Write4Blocks_17_tmp278;
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %tmp285 = add i32 %tmp284, %indvar.i100*/
begin
Write4Blocks_17_tmp285 = Write4Blocks__lr_ph_us_i110_tmp284_reg + Write4Blocks_17_indvar_i100;
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %scevgep24.i102 = getelementptr i8* %p_out_buf, i32 %tmp285*/
begin
Write4Blocks_17_scevgep24_i102 = arg_p_out_buf + 1 * Write4Blocks_17_tmp285;
end
end
always @(posedge clk) begin
/* Write4Blocks: %17*/
/* %scevgep24.i102 = getelementptr i8* %p_out_buf, i32 %tmp285*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
Write4Blocks_17_scevgep24_i102_reg <= Write4Blocks_17_scevgep24_i102;
if (^reset !== 1'bX && ^(Write4Blocks_17_scevgep24_i102) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_17_scevgep24_i102_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %18 = load i32* %.14.us.i103, align 4, !tbaa !0*/
begin
Write4Blocks_17_18 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %19 = trunc i32 %18 to i8*/
begin
Write4Blocks_17_19 = Write4Blocks_17_18[7:0];
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %indvar.next.i104 = add i32 %indvar.i100, 1*/
begin
Write4Blocks_17_indvar_next_i104 = Write4Blocks_17_indvar_i100 + 32'd1;
end
end
always @(posedge clk) begin
/* Write4Blocks: %17*/
/* %indvar.next.i104 = add i32 %indvar.i100, 1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
Write4Blocks_17_indvar_next_i104_reg <= Write4Blocks_17_indvar_next_i104;
if (^reset !== 1'bX && ^(Write4Blocks_17_indvar_next_i104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_17_indvar_next_i104_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %17*/
/* %exitcond242 = icmp eq i32 %indvar.next.i104, %tmp241*/
begin
Write4Blocks_17_exitcond242 = Write4Blocks_17_indvar_next_i104 == Write4Blocks__lr_ph8_split_us_i96_tmp241_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %17*/
/* %exitcond242 = icmp eq i32 %indvar.next.i104, %tmp241*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
Write4Blocks_17_exitcond242_reg <= Write4Blocks_17_exitcond242;
if (^reset !== 1'bX && ^(Write4Blocks_17_exitcond242) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_17_exitcond242_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106 = Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp;
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB10_24) */
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106 = Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106_reg <= Write4Blocks__lr_ph_us_i110_indvar17_i106;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i110_indvar17_i106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_indvar17_i106_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106_reg <= Write4Blocks__lr_ph_us_i110_indvar17_i106;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i110_indvar17_i106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_indvar17_i106_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106_reg <= Write4Blocks__lr_ph_us_i110_indvar17_i106;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i110_indvar17_i106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_indvar17_i106_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp277 = mul i32 %indvar17.i106, %tmp241*/
begin
Write4Blocks__lr_ph_us_i110_tmp277 = Write4Blocks_signed_multiply_32_1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp277 = mul i32 %indvar17.i106, %tmp241*/
Write4Blocks__lr_ph_us_i110_tmp277_reg = Write4Blocks__lr_ph_us_i36_tmp168_reg;
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp279 = mul i32 %6, %indvar17.i106*/
begin
Write4Blocks__lr_ph_us_i110_tmp279 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp284 = add i32 %tmp283, %tmp279*/
begin
Write4Blocks__lr_ph_us_i110_tmp284 = Write4Blocks__lr_ph8_split_us_i96_tmp283_reg + Write4Blocks__lr_ph_us_i110_tmp279;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp284 = add i32 %tmp283, %tmp279*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i110_tmp284_reg <= Write4Blocks__lr_ph_us_i110_tmp284;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i110_tmp284) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_tmp284_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB11_25) */
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp;
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg <= Write4Blocks_WriteOneBlock_exit111__pre_phi350;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111__pre_phi350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %20 = icmp slt i32 %.pre-phi350, %8*/
begin
Write4Blocks_WriteOneBlock_exit111_20 = $signed(Write4Blocks_WriteOneBlock_exit111__pre_phi350) < $signed(Write4Blocks_0_8_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %20 = icmp slt i32 %.pre-phi350, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB11_25)
begin
Write4Blocks_WriteOneBlock_exit111_20_reg <= Write4Blocks_WriteOneBlock_exit111_20;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit111_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111_20_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %or.cond.i38 = and i1 %20, %10*/
begin
Write4Blocks_WriteOneBlock_exit111_or_cond_i38 = Write4Blocks_WriteOneBlock_exit111_20 & Write4Blocks_0_10_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp179337 = or i32 %4, 1*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp179337 = Write4Blocks_0_4_reg | 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp180 = icmp sgt i32 %tmp287, %tmp179337*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp180 = $signed(Write4Blocks_0_tmp287_reg) > $signed(Write4Blocks__lr_ph8_split_us_i59_tmp179337);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %smax181 = select i1 %tmp180, i32 %tmp287, i32 %tmp179337*/
begin
Write4Blocks__lr_ph8_split_us_i59_smax181 = (Write4Blocks__lr_ph8_split_us_i59_tmp180 ? Write4Blocks_0_tmp287_reg : Write4Blocks__lr_ph8_split_us_i59_tmp179337);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp182 = sub i32 %4, %smax181*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp182 = Write4Blocks_0_4_reg - Write4Blocks__lr_ph8_split_us_i59_smax181;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp182 = sub i32 %4, %smax181*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp182_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp182;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp182) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp182_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp184 = sub i32 %4, %6*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp184 = Write4Blocks_0_4_reg - Write4Blocks_0_6_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp184 = sub i32 %4, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp184_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp184;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp184) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp184_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp185 = icmp ugt i32 %tmp182, %tmp184*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp185 = Write4Blocks__lr_ph8_split_us_i59_tmp182_reg > Write4Blocks__lr_ph8_split_us_i59_tmp184_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %umax186 = select i1 %tmp185, i32 %tmp182, i32 %tmp184*/
begin
Write4Blocks__lr_ph8_split_us_i59_umax186 = (Write4Blocks__lr_ph8_split_us_i59_tmp185 ? Write4Blocks__lr_ph8_split_us_i59_tmp182_reg : Write4Blocks__lr_ph8_split_us_i59_tmp184_reg);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp187 = sub i32 0, %umax186*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp187 = 32'd0 - Write4Blocks__lr_ph8_split_us_i59_umax186;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp187 = sub i32 0, %umax186*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_27)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp187_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp187;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp187) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp187_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp199 = add i32 %2, 16*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp199 = Write4Blocks_0_2_reg + 32'd16;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp200 = add i32 %2, 9*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp200 = Write4Blocks_0_2_reg + 32'd9;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp201 = icmp sgt i32 %tmp199, %tmp200*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp201 = $signed(Write4Blocks__lr_ph8_split_us_i59_tmp199) > $signed(Write4Blocks__lr_ph8_split_us_i59_tmp200);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %smax202 = select i1 %tmp201, i32 %tmp199, i32 %tmp200*/
begin
Write4Blocks__lr_ph8_split_us_i59_smax202 = (Write4Blocks__lr_ph8_split_us_i59_tmp201 ? Write4Blocks__lr_ph8_split_us_i59_tmp199 : Write4Blocks__lr_ph8_split_us_i59_tmp200);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %smax202 = select i1 %tmp201, i32 %tmp199, i32 %tmp200*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks__lr_ph8_split_us_i59_smax202_reg <= Write4Blocks__lr_ph8_split_us_i59_smax202;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_smax202) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_smax202_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp203 = sub i32 %.pre-phi350, %smax202*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp203 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg - Write4Blocks__lr_ph8_split_us_i59_smax202_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp206 = sub i32 %.pre-phi350, %8*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp206 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg - Write4Blocks_0_8_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp206 = sub i32 %.pre-phi350, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp206_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp206;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp206) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp206_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp207 = icmp ugt i32 %tmp203, %tmp206*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp207 = Write4Blocks__lr_ph8_split_us_i59_tmp203 > Write4Blocks__lr_ph8_split_us_i59_tmp206_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %umax208 = select i1 %tmp207, i32 %tmp203, i32 %tmp206*/
begin
Write4Blocks__lr_ph8_split_us_i59_umax208 = (Write4Blocks__lr_ph8_split_us_i59_tmp207 ? Write4Blocks__lr_ph8_split_us_i59_tmp203 : Write4Blocks__lr_ph8_split_us_i59_tmp206_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %umax208 = select i1 %tmp207, i32 %tmp203, i32 %tmp206*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_27)
begin
Write4Blocks__lr_ph8_split_us_i59_umax208_reg <= Write4Blocks__lr_ph8_split_us_i59_umax208;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_umax208) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_umax208_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp209 = sub i32 0, %umax208*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp209 = 32'd0 - Write4Blocks__lr_ph8_split_us_i59_umax208_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp209 = sub i32 0, %umax208*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_28)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp209_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp209;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp209) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp209_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp226 = mul i32 %.pre-phi350, %6*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp226 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp227 = add i32 %tmp226, %4*/
begin
Write4Blocks__lr_ph8_split_us_i59_tmp227 = Write4Blocks__lr_ph8_split_us_i59_tmp226 + Write4Blocks_0_4_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp227 = add i32 %tmp226, %4*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks__lr_ph8_split_us_i59_tmp227_reg <= Write4Blocks__lr_ph8_split_us_i59_tmp227;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i59_tmp227) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i59_tmp227_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %21*/
/* %indvar.next18.i61 = add i32 %indvar17.i69, 1*/
begin
Write4Blocks_21_indvar_next18_i61 = Write4Blocks__lr_ph_us_i73_indvar17_i69_reg + 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %21*/
/* %exitcond210 = icmp eq i32 %indvar.next18.i61, %tmp209*/
begin
Write4Blocks_21_exitcond210 = Write4Blocks_21_indvar_next18_i61 == Write4Blocks__lr_ph8_split_us_i59_tmp209_reg;
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %indvar.i63 = phi i32 [ 0, %.lr.ph.us.i73 ], [ %indvar.next.i67, %22 ]*/
begin
Write4Blocks_22_indvar_i63 = Write4Blocks_22_indvar_i63_phi_temp;
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %tmp223 = add i32 %tmp222, %indvar.i63*/
begin
Write4Blocks_22_tmp223 = Write4Blocks__lr_ph_us_i73_tmp222_reg + Write4Blocks_22_indvar_i63;
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %.14.us.i66 = getelementptr i32* %store3, i32 %tmp223*/
begin
Write4Blocks_22__14_us_i66 = arg_store3 + 4 * Write4Blocks_22_tmp223;
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %tmp229 = add i32 %tmp228, %indvar.i63*/
begin
Write4Blocks_22_tmp229 = Write4Blocks__lr_ph_us_i73_tmp228_reg + Write4Blocks_22_indvar_i63;
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %scevgep24.i65 = getelementptr i8* %p_out_buf, i32 %tmp229*/
begin
Write4Blocks_22_scevgep24_i65 = arg_p_out_buf + 1 * Write4Blocks_22_tmp229;
end
end
always @(posedge clk) begin
/* Write4Blocks: %22*/
/* %scevgep24.i65 = getelementptr i8* %p_out_buf, i32 %tmp229*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
Write4Blocks_22_scevgep24_i65_reg <= Write4Blocks_22_scevgep24_i65;
if (^reset !== 1'bX && ^(Write4Blocks_22_scevgep24_i65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_22_scevgep24_i65_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %23 = load i32* %.14.us.i66, align 4, !tbaa !0*/
begin
Write4Blocks_22_23 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %24 = trunc i32 %23 to i8*/
begin
Write4Blocks_22_24 = Write4Blocks_22_23[7:0];
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %indvar.next.i67 = add i32 %indvar.i63, 1*/
begin
Write4Blocks_22_indvar_next_i67 = Write4Blocks_22_indvar_i63 + 32'd1;
end
end
always @(posedge clk) begin
/* Write4Blocks: %22*/
/* %indvar.next.i67 = add i32 %indvar.i63, 1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
Write4Blocks_22_indvar_next_i67_reg <= Write4Blocks_22_indvar_next_i67;
if (^reset !== 1'bX && ^(Write4Blocks_22_indvar_next_i67) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_22_indvar_next_i67_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %22*/
/* %exitcond188 = icmp eq i32 %indvar.next.i67, %tmp187*/
begin
Write4Blocks_22_exitcond188 = Write4Blocks_22_indvar_next_i67 == Write4Blocks__lr_ph8_split_us_i59_tmp187_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %22*/
/* %exitcond188 = icmp eq i32 %indvar.next.i67, %tmp187*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
Write4Blocks_22_exitcond188_reg <= Write4Blocks_22_exitcond188;
if (^reset !== 1'bX && ^(Write4Blocks_22_exitcond188) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_22_exitcond188_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69 = Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp;
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB15_33) */
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69 = Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69_reg <= Write4Blocks__lr_ph_us_i73_indvar17_i69;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i73_indvar17_i69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_indvar17_i69_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69_reg <= Write4Blocks__lr_ph_us_i73_indvar17_i69;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i73_indvar17_i69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_indvar17_i69_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69_reg <= Write4Blocks__lr_ph_us_i73_indvar17_i69;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i73_indvar17_i69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_indvar17_i69_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp222 = mul i32 %indvar17.i69, %tmp187*/
begin
Write4Blocks__lr_ph_us_i73_tmp222 = Write4Blocks_signed_multiply_32_1;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp222 = mul i32 %indvar17.i69, %tmp187*/
Write4Blocks__lr_ph_us_i73_tmp222_reg = Write4Blocks__lr_ph_us_i36_tmp168_reg;
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp224 = mul i32 %6, %indvar17.i69*/
begin
Write4Blocks__lr_ph_us_i73_tmp224 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp228 = add i32 %tmp227, %tmp224*/
begin
Write4Blocks__lr_ph_us_i73_tmp228 = Write4Blocks__lr_ph8_split_us_i59_tmp227_reg + Write4Blocks__lr_ph_us_i73_tmp224;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp228 = add i32 %tmp227, %tmp224*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i73_tmp228_reg <= Write4Blocks__lr_ph_us_i73_tmp228;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i73_tmp228) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_tmp228_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit74*/
/* %or.cond.i1 = and i1 %20, %15*/
begin
Write4Blocks_WriteOneBlock_exit74_or_cond_i1 = Write4Blocks_WriteOneBlock_exit111_20_reg & Write4Blocks_WriteOneBlock_exit_15_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp125 = add i32 %4, 16*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp125 = Write4Blocks_0_4_reg + 32'd16;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp126 = add i32 %4, 9*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp126 = Write4Blocks_0_4_reg + 32'd9;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp127 = icmp sgt i32 %tmp125, %tmp126*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp127 = $signed(Write4Blocks__lr_ph8_split_us_i22_tmp125) > $signed(Write4Blocks__lr_ph8_split_us_i22_tmp126);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %smax = select i1 %tmp127, i32 %tmp125, i32 %tmp126*/
begin
Write4Blocks__lr_ph8_split_us_i22_smax = (Write4Blocks__lr_ph8_split_us_i22_tmp127 ? Write4Blocks__lr_ph8_split_us_i22_tmp125 : Write4Blocks__lr_ph8_split_us_i22_tmp126);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %smax = select i1 %tmp127, i32 %tmp125, i32 %tmp126*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks__lr_ph8_split_us_i22_smax_reg <= Write4Blocks__lr_ph8_split_us_i22_smax;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_smax) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_smax_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp128 = sub i32 %tmp287, %smax*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp128 = Write4Blocks_0_tmp287_reg - Write4Blocks__lr_ph8_split_us_i22_smax_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp130 = sub i32 %tmp287, %6*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp130 = Write4Blocks_0_tmp287_reg - Write4Blocks_0_6_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp130 = sub i32 %tmp287, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks__lr_ph8_split_us_i22_tmp130_reg <= Write4Blocks__lr_ph8_split_us_i22_tmp130;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_tmp130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_tmp130_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp131 = icmp ugt i32 %tmp128, %tmp130*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp131 = Write4Blocks__lr_ph8_split_us_i22_tmp128 > Write4Blocks__lr_ph8_split_us_i22_tmp130_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %umax = select i1 %tmp131, i32 %tmp128, i32 %tmp130*/
begin
Write4Blocks__lr_ph8_split_us_i22_umax = (Write4Blocks__lr_ph8_split_us_i22_tmp131 ? Write4Blocks__lr_ph8_split_us_i22_tmp128 : Write4Blocks__lr_ph8_split_us_i22_tmp130_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %umax = select i1 %tmp131, i32 %tmp128, i32 %tmp130*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_36)
begin
Write4Blocks__lr_ph8_split_us_i22_umax_reg <= Write4Blocks__lr_ph8_split_us_i22_umax;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_umax) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_umax_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp132 = sub i32 0, %umax*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp132 = 32'd0 - Write4Blocks__lr_ph8_split_us_i22_umax_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp132 = sub i32 0, %umax*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_37)
begin
Write4Blocks__lr_ph8_split_us_i22_tmp132_reg <= Write4Blocks__lr_ph8_split_us_i22_tmp132;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_tmp132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_tmp132_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp144 = add i32 %2, 16*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp144 = Write4Blocks_0_2_reg + 32'd16;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp145 = add i32 %2, 9*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp145 = Write4Blocks_0_2_reg + 32'd9;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp146 = icmp sgt i32 %tmp144, %tmp145*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp146 = $signed(Write4Blocks__lr_ph8_split_us_i22_tmp144) > $signed(Write4Blocks__lr_ph8_split_us_i22_tmp145);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %smax147 = select i1 %tmp146, i32 %tmp144, i32 %tmp145*/
begin
Write4Blocks__lr_ph8_split_us_i22_smax147 = (Write4Blocks__lr_ph8_split_us_i22_tmp146 ? Write4Blocks__lr_ph8_split_us_i22_tmp144 : Write4Blocks__lr_ph8_split_us_i22_tmp145);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %smax147 = select i1 %tmp146, i32 %tmp144, i32 %tmp145*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks__lr_ph8_split_us_i22_smax147_reg <= Write4Blocks__lr_ph8_split_us_i22_smax147;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_smax147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_smax147_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp148 = sub i32 %.pre-phi350, %smax147*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp148 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg - Write4Blocks__lr_ph8_split_us_i22_smax147_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp151 = sub i32 %.pre-phi350, %8*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp151 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg - Write4Blocks_0_8_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp151 = sub i32 %.pre-phi350, %8*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks__lr_ph8_split_us_i22_tmp151_reg <= Write4Blocks__lr_ph8_split_us_i22_tmp151;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_tmp151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_tmp151_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp152 = icmp ugt i32 %tmp148, %tmp151*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp152 = Write4Blocks__lr_ph8_split_us_i22_tmp148 > Write4Blocks__lr_ph8_split_us_i22_tmp151_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %umax153 = select i1 %tmp152, i32 %tmp148, i32 %tmp151*/
begin
Write4Blocks__lr_ph8_split_us_i22_umax153 = (Write4Blocks__lr_ph8_split_us_i22_tmp152 ? Write4Blocks__lr_ph8_split_us_i22_tmp148 : Write4Blocks__lr_ph8_split_us_i22_tmp151_reg);
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %umax153 = select i1 %tmp152, i32 %tmp148, i32 %tmp151*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_36)
begin
Write4Blocks__lr_ph8_split_us_i22_umax153_reg <= Write4Blocks__lr_ph8_split_us_i22_umax153;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_umax153) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_umax153_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp154 = sub i32 0, %umax153*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp154 = 32'd0 - Write4Blocks__lr_ph8_split_us_i22_umax153_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp154 = sub i32 0, %umax153*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_37)
begin
Write4Blocks__lr_ph8_split_us_i22_tmp154_reg <= Write4Blocks__lr_ph8_split_us_i22_tmp154;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_tmp154) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_tmp154_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp172 = mul i32 %.pre-phi350, %6*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp172 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp173 = add i32 %tmp172, %4*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp173 = Write4Blocks__lr_ph8_split_us_i22_tmp172 + Write4Blocks_0_4_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp174 = add i32 %tmp173, 8*/
begin
Write4Blocks__lr_ph8_split_us_i22_tmp174 = Write4Blocks__lr_ph8_split_us_i22_tmp173 + 32'd8;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp174 = add i32 %tmp173, 8*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks__lr_ph8_split_us_i22_tmp174_reg <= Write4Blocks__lr_ph8_split_us_i22_tmp174;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i22_tmp174) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph8_split_us_i22_tmp174_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %25*/
/* %indvar.next18.i24 = add i32 %indvar17.i32, 1*/
begin
Write4Blocks_25_indvar_next18_i24 = Write4Blocks__lr_ph_us_i36_indvar17_i32_reg + 32'd1;
end
end
always @(*) begin
/* Write4Blocks: %25*/
/* %exitcond155 = icmp eq i32 %indvar.next18.i24, %tmp154*/
begin
Write4Blocks_25_exitcond155 = Write4Blocks_25_indvar_next18_i24 == Write4Blocks__lr_ph8_split_us_i22_tmp154_reg;
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %indvar.i26 = phi i32 [ 0, %.lr.ph.us.i36 ], [ %indvar.next.i30, %26 ]*/
begin
Write4Blocks_26_indvar_i26 = Write4Blocks_26_indvar_i26_phi_temp;
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %tmp169 = add i32 %tmp168, %indvar.i26*/
begin
Write4Blocks_26_tmp169 = Write4Blocks__lr_ph_us_i36_tmp168_reg + Write4Blocks_26_indvar_i26;
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %.14.us.i29 = getelementptr i32* %store4, i32 %tmp169*/
begin
Write4Blocks_26__14_us_i29 = arg_store4 + 4 * Write4Blocks_26_tmp169;
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %tmp176 = add i32 %tmp175, %indvar.i26*/
begin
Write4Blocks_26_tmp176 = Write4Blocks__lr_ph_us_i36_tmp175_reg + Write4Blocks_26_indvar_i26;
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %scevgep24.i28 = getelementptr i8* %p_out_buf, i32 %tmp176*/
begin
Write4Blocks_26_scevgep24_i28 = arg_p_out_buf + 1 * Write4Blocks_26_tmp176;
end
end
always @(posedge clk) begin
/* Write4Blocks: %26*/
/* %scevgep24.i28 = getelementptr i8* %p_out_buf, i32 %tmp176*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
Write4Blocks_26_scevgep24_i28_reg <= Write4Blocks_26_scevgep24_i28;
if (^reset !== 1'bX && ^(Write4Blocks_26_scevgep24_i28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_26_scevgep24_i28_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %27 = load i32* %.14.us.i29, align 4, !tbaa !0*/
begin
Write4Blocks_26_27 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %28 = trunc i32 %27 to i8*/
begin
Write4Blocks_26_28 = Write4Blocks_26_27[7:0];
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %indvar.next.i30 = add i32 %indvar.i26, 1*/
begin
Write4Blocks_26_indvar_next_i30 = Write4Blocks_26_indvar_i26 + 32'd1;
end
end
always @(posedge clk) begin
/* Write4Blocks: %26*/
/* %indvar.next.i30 = add i32 %indvar.i26, 1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
Write4Blocks_26_indvar_next_i30_reg <= Write4Blocks_26_indvar_next_i30;
if (^reset !== 1'bX && ^(Write4Blocks_26_indvar_next_i30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_26_indvar_next_i30_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %26*/
/* %exitcond = icmp eq i32 %indvar.next.i30, %tmp132*/
begin
Write4Blocks_26_exitcond = Write4Blocks_26_indvar_next_i30 == Write4Blocks__lr_ph8_split_us_i22_tmp132_reg;
end
end
always @(posedge clk) begin
/* Write4Blocks: %26*/
/* %exitcond = icmp eq i32 %indvar.next.i30, %tmp132*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
Write4Blocks_26_exitcond_reg <= Write4Blocks_26_exitcond;
if (^reset !== 1'bX && ^(Write4Blocks_26_exitcond) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_26_exitcond_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32 = Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp;
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB20_42) */
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32 = Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32_reg <= Write4Blocks__lr_ph_us_i36_indvar17_i32;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i36_indvar17_i32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_indvar17_i32_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32_reg <= Write4Blocks__lr_ph_us_i36_indvar17_i32;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i36_indvar17_i32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_indvar17_i32_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32_reg <= Write4Blocks__lr_ph_us_i36_indvar17_i32;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i36_indvar17_i32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_indvar17_i32_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp168 = mul i32 %indvar17.i32, %tmp132*/
begin
Write4Blocks__lr_ph_us_i36_tmp168 = Write4Blocks_signed_multiply_32_1;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp168 = mul i32 %indvar17.i32, %tmp132*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_tmp168_reg <= Write4Blocks__lr_ph_us_i36_tmp168;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i36_tmp168) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_tmp168_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp329 = mul i32 %indvar17.i, %tmp296*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks__lr_ph_us_i36_tmp168_reg <= Write4Blocks__lr_ph_us_i_tmp329;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i_tmp329) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_tmp168_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp222 = mul i32 %indvar17.i69, %tmp187*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks__lr_ph_us_i36_tmp168_reg <= Write4Blocks__lr_ph_us_i73_tmp222;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i73_tmp222) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_tmp168_reg"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp277 = mul i32 %indvar17.i106, %tmp241*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks__lr_ph_us_i36_tmp168_reg <= Write4Blocks__lr_ph_us_i110_tmp277;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i110_tmp277) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_tmp168_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp170 = mul i32 %6, %indvar17.i32*/
begin
Write4Blocks__lr_ph_us_i36_tmp170 = Write4Blocks_signed_multiply_32_0;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp175 = add i32 %tmp174, %tmp170*/
begin
Write4Blocks__lr_ph_us_i36_tmp175 = Write4Blocks__lr_ph8_split_us_i22_tmp174_reg + Write4Blocks__lr_ph_us_i36_tmp170;
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp175 = add i32 %tmp174, %tmp170*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42)
begin
Write4Blocks__lr_ph_us_i36_tmp175_reg <= Write4Blocks__lr_ph_us_i36_tmp175;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph_us_i36_tmp175) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_tmp175_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %29 = load i32* %p_out_hpos, align 4, !tbaa !0*/
begin
Write4Blocks_WriteOneBlock_exit37_29 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %30 = add nsw i32 %29, 2*/
begin
Write4Blocks_WriteOneBlock_exit37_30 = Write4Blocks_WriteOneBlock_exit37_29 + 32'd2;
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
begin
Write4Blocks_WriteOneBlock_exit37_31 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
Write4Blocks_WriteOneBlock_exit37_31_reg <= Write4Blocks_WriteOneBlock_exit37_31;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit37_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit37_31_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %32 = add nsw i32 %31, 2*/
begin
Write4Blocks_WriteOneBlock_exit37_32 = Write4Blocks_WriteOneBlock_exit37_31 + 32'd2;
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
begin
Write4Blocks_WriteOneBlock_exit37_33 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_51)
begin
Write4Blocks_WriteOneBlock_exit37_33_reg <= Write4Blocks_WriteOneBlock_exit37_33;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit37_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit37_33_reg"); $finish; end
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %34 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
begin
Write4Blocks_WriteOneBlock_exit37_34 = memory_controller_out[31:0];
end
end
always @(*) begin
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %35 = icmp slt i32 %33, %34*/
begin
Write4Blocks_WriteOneBlock_exit37_35 = $signed(Write4Blocks_WriteOneBlock_exit37_33_reg) < $signed(Write4Blocks_WriteOneBlock_exit37_34);
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp332 = mul i32 %1, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_1_reg;
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp331 = mul i32 %6, %indvar17.i*/
else if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp280 = mul i32 %1, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_1_reg;
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp279 = mul i32 %6, %indvar17.i106*/
else if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp226 = mul i32 %.pre-phi350, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg;
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp224 = mul i32 %6, %indvar17.i69*/
else if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp172 = mul i32 %.pre-phi350, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_WriteOneBlock_exit111__pre_phi350_reg;
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp170 = mul i32 %6, %indvar17.i32*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB20_42) */
begin
Write4Blocks_signed_multiply_32_0_op0 = Write4Blocks_0_6_reg;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph8.split.us.i*/
/* %tmp332 = mul i32 %1, %6*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_7)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp331 = mul i32 %6, %indvar17.i*/
else if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks__lr_ph_us_i_indvar17_i;
end
/* Write4Blocks: %.lr.ph8.split.us.i96*/
/* %tmp280 = mul i32 %1, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB7_17)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp279 = mul i32 %6, %indvar17.i106*/
else if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks__lr_ph_us_i110_indvar17_i106;
end
/* Write4Blocks: %.lr.ph8.split.us.i59*/
/* %tmp226 = mul i32 %.pre-phi350, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB12_26)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp224 = mul i32 %6, %indvar17.i69*/
else if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks__lr_ph_us_i73_indvar17_i69;
end
/* Write4Blocks: %.lr.ph8.split.us.i22*/
/* %tmp172 = mul i32 %.pre-phi350, %6*/
else if (cur_state == LEGUP_F_Write4Blocks_BB17_35)
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks_0_6_reg;
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp170 = mul i32 %6, %indvar17.i32*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB20_42) */
begin
Write4Blocks_signed_multiply_32_0_op1 = Write4Blocks__lr_ph_us_i36_indvar17_i32;
end
end
always @(*) begin
Write4Blocks_signed_multiply_32_0 = Write4Blocks_signed_multiply_32_0_op0 * Write4Blocks_signed_multiply_32_0_op1;
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp329 = mul i32 %indvar17.i, %tmp296*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks_signed_multiply_32_1_op0 = Write4Blocks__lr_ph_us_i_indvar17_i;
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp277 = mul i32 %indvar17.i106, %tmp241*/
else if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks_signed_multiply_32_1_op0 = Write4Blocks__lr_ph_us_i110_indvar17_i106;
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp222 = mul i32 %indvar17.i69, %tmp187*/
else if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks_signed_multiply_32_1_op0 = Write4Blocks__lr_ph_us_i73_indvar17_i69;
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp168 = mul i32 %indvar17.i32, %tmp132*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB20_42) */
begin
Write4Blocks_signed_multiply_32_1_op0 = Write4Blocks__lr_ph_us_i36_indvar17_i32;
end
end
always @(*) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %tmp329 = mul i32 %indvar17.i, %tmp296*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14)
begin
Write4Blocks_signed_multiply_32_1_op1 = Write4Blocks__lr_ph8_split_us_i_tmp296_reg;
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %tmp277 = mul i32 %indvar17.i106, %tmp241*/
else if (cur_state == LEGUP_F_Write4Blocks_BB10_24)
begin
Write4Blocks_signed_multiply_32_1_op1 = Write4Blocks__lr_ph8_split_us_i96_tmp241_reg;
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %tmp222 = mul i32 %indvar17.i69, %tmp187*/
else if (cur_state == LEGUP_F_Write4Blocks_BB15_33)
begin
Write4Blocks_signed_multiply_32_1_op1 = Write4Blocks__lr_ph8_split_us_i59_tmp187_reg;
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %tmp168 = mul i32 %indvar17.i32, %tmp132*/
else /* if (cur_state == LEGUP_F_Write4Blocks_BB20_42) */
begin
Write4Blocks_signed_multiply_32_1_op1 = Write4Blocks__lr_ph8_split_us_i22_tmp132_reg;
end
end
always @(*) begin
Write4Blocks_signed_multiply_32_1 = Write4Blocks_signed_multiply_32_1_op0 * Write4Blocks_signed_multiply_32_1_op1;
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB1_9 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i*/
/* %indvar17.i = phi i32 [ %indvar.next18.i, %11 ], [ 0, %.lr.ph8.split.us.i ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB2_10 & memory_controller_waitrequest == 1'd0 & Write4Blocks_11_exitcond317 == 1'd0)
begin
Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp <= Write4Blocks_11_indvar_next18_i;
if (^reset !== 1'bX && ^(Write4Blocks_11_indvar_next18_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i_indvar17_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %12*/
/* %indvar.i = phi i32 [ 0, %.lr.ph.us.i ], [ %indvar.next.i, %12 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13 & memory_controller_waitrequest == 1'd0 & Write4Blocks_12_exitcond297_reg == 1'd0)
begin
Write4Blocks_12_indvar_i_phi_temp <= Write4Blocks_12_indvar_next_i_reg;
if (^reset !== 1'bX && ^(Write4Blocks_12_indvar_next_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_12_indvar_i_phi_temp"); $finish; end
end
/* Write4Blocks: %12*/
/* %indvar.i = phi i32 [ 0, %.lr.ph.us.i ], [ %indvar.next.i, %12 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB4_14 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks_12_indvar_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_12_indvar_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB6_16 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp <= Write4Blocks_WriteOneBlock_exit_WriteOneBlock_exit111_crit_edge__pre349;
if (^reset !== 1'bX && ^(Write4Blocks_WriteOneBlock_exit_WriteOneBlock_exit111_crit_edge__pre349) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp"); $finish; end
end
/* Write4Blocks: %WriteOneBlock.exit111*/
/* %.pre-phi350 = phi i32 [ %.pre349, %WriteOneBlock.exit.WriteOneBlock.exit111_crit_edge ], [ %tmp254, %16 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB8_20 & memory_controller_waitrequest == 1'd0 & Write4Blocks_16_exitcond264 == 1'd1)
begin
Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp <= Write4Blocks__lr_ph8_split_us_i96_tmp254_reg;
if (^reset !== 1'bX && ^(Write4Blocks__lr_ph8_split_us_i96_tmp254_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_WriteOneBlock_exit111__pre_phi350_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB7_19 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i110*/
/* %indvar17.i106 = phi i32 [ %indvar.next18.i98, %16 ], [ 0, %.lr.ph8.split.us.i96 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB8_20 & memory_controller_waitrequest == 1'd0 & Write4Blocks_16_exitcond264 == 1'd0)
begin
Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp <= Write4Blocks_16_indvar_next18_i98;
if (^reset !== 1'bX && ^(Write4Blocks_16_indvar_next18_i98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i110_indvar17_i106_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %17*/
/* %indvar.i100 = phi i32 [ 0, %.lr.ph.us.i110 ], [ %indvar.next.i104, %17 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23 & memory_controller_waitrequest == 1'd0 & Write4Blocks_17_exitcond242_reg == 1'd0)
begin
Write4Blocks_17_indvar_i100_phi_temp <= Write4Blocks_17_indvar_next_i104_reg;
if (^reset !== 1'bX && ^(Write4Blocks_17_indvar_next_i104_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_17_indvar_i100_phi_temp"); $finish; end
end
/* Write4Blocks: %17*/
/* %indvar.i100 = phi i32 [ 0, %.lr.ph.us.i110 ], [ %indvar.next.i104, %17 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB10_24 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks_17_indvar_i100_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_17_indvar_i100_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB12_28 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i73*/
/* %indvar17.i69 = phi i32 [ %indvar.next18.i61, %21 ], [ 0, %.lr.ph8.split.us.i59 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB13_29 & memory_controller_waitrequest == 1'd0 & Write4Blocks_21_exitcond210 == 1'd0)
begin
Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp <= Write4Blocks_21_indvar_next18_i61;
if (^reset !== 1'bX && ^(Write4Blocks_21_indvar_next18_i61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i73_indvar17_i69_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %22*/
/* %indvar.i63 = phi i32 [ 0, %.lr.ph.us.i73 ], [ %indvar.next.i67, %22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32 & memory_controller_waitrequest == 1'd0 & Write4Blocks_22_exitcond188_reg == 1'd0)
begin
Write4Blocks_22_indvar_i63_phi_temp <= Write4Blocks_22_indvar_next_i67_reg;
if (^reset !== 1'bX && ^(Write4Blocks_22_indvar_next_i67_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_22_indvar_i63_phi_temp"); $finish; end
end
/* Write4Blocks: %22*/
/* %indvar.i63 = phi i32 [ 0, %.lr.ph.us.i73 ], [ %indvar.next.i67, %22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB15_33 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks_22_indvar_i63_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_22_indvar_i63_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB17_37 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp"); $finish; end
end
/* Write4Blocks: %.lr.ph.us.i36*/
/* %indvar17.i32 = phi i32 [ %indvar.next18.i24, %25 ], [ 0, %.lr.ph8.split.us.i22 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB18_38 & memory_controller_waitrequest == 1'd0 & Write4Blocks_25_exitcond155 == 1'd0)
begin
Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp <= Write4Blocks_25_indvar_next18_i24;
if (^reset !== 1'bX && ^(Write4Blocks_25_indvar_next18_i24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks__lr_ph_us_i36_indvar17_i32_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* Write4Blocks: %26*/
/* %indvar.i26 = phi i32 [ 0, %.lr.ph.us.i36 ], [ %indvar.next.i30, %26 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41 & memory_controller_waitrequest == 1'd0 & Write4Blocks_26_exitcond_reg == 1'd0)
begin
Write4Blocks_26_indvar_i26_phi_temp <= Write4Blocks_26_indvar_next_i30_reg;
if (^reset !== 1'bX && ^(Write4Blocks_26_indvar_next_i30_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_26_indvar_i26_phi_temp"); $finish; end
end
/* Write4Blocks: %26*/
/* %indvar.i26 = phi i32 [ 0, %.lr.ph.us.i36 ], [ %indvar.next.i30, %26 ]*/
if (cur_state == LEGUP_F_Write4Blocks_BB20_42 & memory_controller_waitrequest == 1'd0)
begin
Write4Blocks_26_indvar_i26_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_26_indvar_i26_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* Write4Blocks: %38*/
/* ret void*/
if (cur_state == LEGUP_F_Write4Blocks_BB24_55)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_1)
begin
memory_controller_address = arg_p_out_vpos;
end
/* Write4Blocks: %0*/
/* %3 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_2)
begin
memory_controller_address = arg_p_out_hpos;
end
/* Write4Blocks: %0*/
/* %5 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* Write4Blocks: %0*/
/* %7 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* Write4Blocks: %12*/
/* %13 = load i32* %.14.us.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
memory_controller_address = Write4Blocks_12__14_us_i;
end
/* Write4Blocks: %12*/
/* store i8 %14, i8* %scevgep24.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13)
begin
memory_controller_address = Write4Blocks_12_scevgep24_i_reg;
end
/* Write4Blocks: %17*/
/* %18 = load i32* %.14.us.i103, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
memory_controller_address = Write4Blocks_17__14_us_i103;
end
/* Write4Blocks: %17*/
/* store i8 %19, i8* %scevgep24.i102, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23)
begin
memory_controller_address = Write4Blocks_17_scevgep24_i102_reg;
end
/* Write4Blocks: %22*/
/* %23 = load i32* %.14.us.i66, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
memory_controller_address = Write4Blocks_22__14_us_i66;
end
/* Write4Blocks: %22*/
/* store i8 %24, i8* %scevgep24.i65, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32)
begin
memory_controller_address = Write4Blocks_22_scevgep24_i65_reg;
end
/* Write4Blocks: %26*/
/* %27 = load i32* %.14.us.i29, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
memory_controller_address = Write4Blocks_26__14_us_i29;
end
/* Write4Blocks: %26*/
/* store i8 %28, i8* %scevgep24.i28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41)
begin
memory_controller_address = Write4Blocks_26_scevgep24_i28_reg;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %29 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_43)
begin
memory_controller_address = arg_p_out_hpos;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %30, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_45)
begin
memory_controller_address = arg_p_out_hpos;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_46)
begin
memory_controller_address = arg_p_out_vpos;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %32, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
memory_controller_address = arg_p_out_vpos;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_49)
begin
memory_controller_address = arg_p_out_hpos;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %34 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_50)
begin
memory_controller_address = `TAG_g_p_jinfo_MCUWidth_a;
end
/* Write4Blocks: %36*/
/* store i32 %31, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB22_53)
begin
memory_controller_address = arg_p_out_vpos;
end
/* Write4Blocks: %37*/
/* store i32 0, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB23_54)
begin
memory_controller_address = arg_p_out_hpos;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_1)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %0*/
/* %3 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_2)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %0*/
/* %5 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %0*/
/* %7 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %12*/
/* %13 = load i32* %.14.us.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %12*/
/* store i8 %14, i8* %scevgep24.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %17*/
/* %18 = load i32* %.14.us.i103, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %17*/
/* store i8 %19, i8* %scevgep24.i102, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %22*/
/* %23 = load i32* %.14.us.i66, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %22*/
/* store i8 %24, i8* %scevgep24.i65, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %26*/
/* %27 = load i32* %.14.us.i29, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %26*/
/* store i8 %28, i8* %scevgep24.i28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %29 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_43)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %30, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_45)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_46)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %32, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_49)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %34 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_50)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %36*/
/* store i32 %31, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB22_53)
begin
memory_controller_enable = 1'd1;
end
/* Write4Blocks: %37*/
/* store i32 0, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB23_54)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_1)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %0*/
/* %3 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_2)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %0*/
/* %5 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %0*/
/* %7 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %12*/
/* %13 = load i32* %.14.us.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %12*/
/* store i8 %14, i8* %scevgep24.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %17*/
/* %18 = load i32* %.14.us.i103, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %17*/
/* store i8 %19, i8* %scevgep24.i102, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %22*/
/* %23 = load i32* %.14.us.i66, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %22*/
/* store i8 %24, i8* %scevgep24.i65, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %26*/
/* %27 = load i32* %.14.us.i29, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %26*/
/* store i8 %28, i8* %scevgep24.i28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %29 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_43)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %30, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_45)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_46)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %32, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_49)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %34 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_50)
begin
memory_controller_write_enable = 1'd0;
end
/* Write4Blocks: %36*/
/* store i32 %31, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB22_53)
begin
memory_controller_write_enable = 1'd1;
end
/* Write4Blocks: %37*/
/* store i32 0, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB23_54)
begin
memory_controller_write_enable = 1'd1;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* Write4Blocks: %12*/
/* store i8 %14, i8* %scevgep24.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13)
begin
memory_controller_in = Write4Blocks_12_14;
end
/* Write4Blocks: %17*/
/* store i8 %19, i8* %scevgep24.i102, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23)
begin
memory_controller_in = Write4Blocks_17_19;
end
/* Write4Blocks: %22*/
/* store i8 %24, i8* %scevgep24.i65, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32)
begin
memory_controller_in = Write4Blocks_22_24;
end
/* Write4Blocks: %26*/
/* store i8 %28, i8* %scevgep24.i28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41)
begin
memory_controller_in = Write4Blocks_26_28;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %30, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_45)
begin
memory_controller_in = Write4Blocks_WriteOneBlock_exit37_30;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %32, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
memory_controller_in = Write4Blocks_WriteOneBlock_exit37_32;
end
/* Write4Blocks: %36*/
/* store i32 %31, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB22_53)
begin
memory_controller_in = Write4Blocks_WriteOneBlock_exit37_31_reg;
end
/* Write4Blocks: %37*/
/* store i32 0, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB23_54)
begin
memory_controller_in = 32'd0;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* Write4Blocks: %0*/
/* %1 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_1)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %0*/
/* %3 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_2)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %0*/
/* %5 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_3)
begin
memory_controller_size = 2'd1;
end
/* Write4Blocks: %0*/
/* %7 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_Write4Blocks_BB0_4)
begin
memory_controller_size = 2'd1;
end
/* Write4Blocks: %12*/
/* %13 = load i32* %.14.us.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_11)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %12*/
/* store i8 %14, i8* %scevgep24.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB3_13)
begin
memory_controller_size = 2'd0;
end
/* Write4Blocks: %17*/
/* %18 = load i32* %.14.us.i103, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_21)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %17*/
/* store i8 %19, i8* %scevgep24.i102, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB9_23)
begin
memory_controller_size = 2'd0;
end
/* Write4Blocks: %22*/
/* %23 = load i32* %.14.us.i66, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_30)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %22*/
/* store i8 %24, i8* %scevgep24.i65, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB14_32)
begin
memory_controller_size = 2'd0;
end
/* Write4Blocks: %26*/
/* %27 = load i32* %.14.us.i29, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_39)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %26*/
/* store i8 %28, i8* %scevgep24.i28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_Write4Blocks_BB19_41)
begin
memory_controller_size = 2'd0;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %29 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_43)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %30, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_45)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %31 = load i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_46)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* store i32 %32, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_48)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %33 = load i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_49)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %WriteOneBlock.exit37*/
/* %34 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB21_50)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %36*/
/* store i32 %31, i32* %p_out_vpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB22_53)
begin
memory_controller_size = 2'd2;
end
/* Write4Blocks: %37*/
/* store i32 0, i32* %p_out_hpos, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_Write4Blocks_BB23_54)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module decode_block
(
clk,
reset,
start,
finish,
arg_comp_no,
arg_out_buf,
arg_HuffBuff,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [7:0] LEGUP_0 = 8'd0;
parameter [7:0] LEGUP_F_decode_block_BB0_1 = 8'd1;
parameter [7:0] LEGUP_F_decode_block_BB0_2 = 8'd2;
parameter [7:0] LEGUP_F_decode_block_BB0_3 = 8'd3;
parameter [7:0] LEGUP_F_decode_block_BB0_4 = 8'd4;
parameter [7:0] LEGUP_F_decode_block_BB0_5 = 8'd5;
parameter [7:0] LEGUP_F_decode_block_BB1_8 = 8'd8;
parameter [7:0] LEGUP_F_decode_block_BB1_11 = 8'd11;
parameter [7:0] LEGUP_F_decode_block_BB1_12 = 8'd12;
parameter [7:0] LEGUP_F_decode_block_BB1_13 = 8'd13;
parameter [7:0] LEGUP_F_decode_block_BB2_14 = 8'd14;
parameter [7:0] LEGUP_F_decode_block_BB2_15 = 8'd15;
parameter [7:0] LEGUP_F_decode_block_BB2_16 = 8'd16;
parameter [7:0] LEGUP_F_decode_block_BB3_17 = 8'd17;
parameter [7:0] LEGUP_F_decode_block_BB3_18 = 8'd18;
parameter [7:0] LEGUP_F_decode_block_BB3_19 = 8'd19;
parameter [7:0] LEGUP_F_decode_block_BB4_20 = 8'd20;
parameter [7:0] LEGUP_F_decode_block_BB5_21 = 8'd21;
parameter [7:0] LEGUP_F_decode_block_BB6_22 = 8'd22;
parameter [7:0] LEGUP_F_decode_block_BB7_23 = 8'd23;
parameter [7:0] LEGUP_F_decode_block_BB7_24 = 8'd24;
parameter [7:0] LEGUP_F_decode_block_BB7_25 = 8'd25;
parameter [7:0] LEGUP_F_decode_block_BB8_28 = 8'd28;
parameter [7:0] LEGUP_F_decode_block_BB9_29 = 8'd29;
parameter [7:0] LEGUP_F_decode_block_BB9_32 = 8'd32;
parameter [7:0] LEGUP_F_decode_block_BB9_33 = 8'd33;
parameter [7:0] LEGUP_F_decode_block_BB9_34 = 8'd34;
parameter [7:0] LEGUP_F_decode_block_BB9_35 = 8'd35;
parameter [7:0] LEGUP_F_decode_block_BB10_36 = 8'd36;
parameter [7:0] LEGUP_F_decode_block_BB10_37 = 8'd37;
parameter [7:0] LEGUP_F_decode_block_BB10_38 = 8'd38;
parameter [7:0] LEGUP_F_decode_block_BB11_39 = 8'd39;
parameter [7:0] LEGUP_F_decode_block_BB12_40 = 8'd40;
parameter [7:0] LEGUP_F_decode_block_BB13_41 = 8'd41;
parameter [7:0] LEGUP_F_decode_block_BB14_42 = 8'd42;
parameter [7:0] LEGUP_F_decode_block_BB14_43 = 8'd43;
parameter [7:0] LEGUP_F_decode_block_BB14_44 = 8'd44;
parameter [7:0] LEGUP_F_decode_block_BB14_45 = 8'd45;
parameter [7:0] LEGUP_F_decode_block_BB14_46 = 8'd46;
parameter [7:0] LEGUP_F_decode_block_BB15_47 = 8'd47;
parameter [7:0] LEGUP_F_decode_block_BB15_48 = 8'd48;
parameter [7:0] LEGUP_F_decode_block_BB15_49 = 8'd49;
parameter [7:0] LEGUP_F_decode_block_BB16_50 = 8'd50;
parameter [7:0] LEGUP_F_decode_block_BB16_51 = 8'd51;
parameter [7:0] LEGUP_F_decode_block_BB16_52 = 8'd52;
parameter [7:0] LEGUP_F_decode_block_BB16_53 = 8'd53;
parameter [7:0] LEGUP_F_decode_block_BB17_54 = 8'd54;
parameter [7:0] LEGUP_F_decode_block_BB17_55 = 8'd55;
parameter [7:0] LEGUP_F_decode_block_BB17_56 = 8'd56;
parameter [7:0] LEGUP_F_decode_block_BB17_57 = 8'd57;
parameter [7:0] LEGUP_F_decode_block_BB17_58 = 8'd58;
parameter [7:0] LEGUP_F_decode_block_BB17_59 = 8'd59;
parameter [7:0] LEGUP_F_decode_block_BB17_60 = 8'd60;
parameter [7:0] LEGUP_F_decode_block_BB17_61 = 8'd61;
parameter [7:0] LEGUP_F_decode_block_BB17_62 = 8'd62;
parameter [7:0] LEGUP_F_decode_block_BB17_63 = 8'd63;
parameter [7:0] LEGUP_F_decode_block_BB17_64 = 8'd64;
parameter [7:0] LEGUP_F_decode_block_BB17_65 = 8'd65;
parameter [7:0] LEGUP_F_decode_block_BB17_66 = 8'd66;
parameter [7:0] LEGUP_F_decode_block_BB17_67 = 8'd67;
parameter [7:0] LEGUP_F_decode_block_BB17_68 = 8'd68;
parameter [7:0] LEGUP_F_decode_block_BB17_69 = 8'd69;
parameter [7:0] LEGUP_F_decode_block_BB17_70 = 8'd70;
parameter [7:0] LEGUP_F_decode_block_BB17_71 = 8'd71;
parameter [7:0] LEGUP_F_decode_block_BB18_72 = 8'd72;
parameter [7:0] LEGUP_F_decode_block_BB18_73 = 8'd73;
parameter [7:0] LEGUP_F_decode_block_BB18_74 = 8'd74;
parameter [7:0] LEGUP_F_decode_block_BB18_75 = 8'd75;
parameter [7:0] LEGUP_F_decode_block_BB18_76 = 8'd76;
parameter [7:0] LEGUP_F_decode_block_BB18_77 = 8'd77;
parameter [7:0] LEGUP_F_decode_block_BB18_78 = 8'd78;
parameter [7:0] LEGUP_F_decode_block_BB18_79 = 8'd79;
parameter [7:0] LEGUP_F_decode_block_BB18_80 = 8'd80;
parameter [7:0] LEGUP_F_decode_block_BB18_81 = 8'd81;
parameter [7:0] LEGUP_F_decode_block_BB18_82 = 8'd82;
parameter [7:0] LEGUP_F_decode_block_BB18_83 = 8'd83;
parameter [7:0] LEGUP_F_decode_block_BB18_84 = 8'd84;
parameter [7:0] LEGUP_F_decode_block_BB18_85 = 8'd85;
parameter [7:0] LEGUP_F_decode_block_BB18_86 = 8'd86;
parameter [7:0] LEGUP_F_decode_block_BB18_87 = 8'd87;
parameter [7:0] LEGUP_F_decode_block_BB18_88 = 8'd88;
parameter [7:0] LEGUP_F_decode_block_BB18_89 = 8'd89;
parameter [7:0] LEGUP_F_decode_block_BB19_90 = 8'd90;
parameter [7:0] LEGUP_F_decode_block_BB19_91 = 8'd91;
parameter [7:0] LEGUP_F_decode_block_BB19_92 = 8'd92;
parameter [7:0] LEGUP_F_decode_block_BB19_93 = 8'd93;
parameter [7:0] LEGUP_F_decode_block_BB19_94 = 8'd94;
parameter [7:0] LEGUP_F_decode_block_BB19_95 = 8'd95;
parameter [7:0] LEGUP_F_decode_block_BB19_96 = 8'd96;
parameter [7:0] LEGUP_F_decode_block_BB19_97 = 8'd97;
parameter [7:0] LEGUP_F_decode_block_BB19_98 = 8'd98;
parameter [7:0] LEGUP_F_decode_block_BB19_99 = 8'd99;
parameter [7:0] LEGUP_F_decode_block_BB19_100 = 8'd100;
parameter [7:0] LEGUP_F_decode_block_BB19_101 = 8'd101;
parameter [7:0] LEGUP_F_decode_block_BB19_102 = 8'd102;
parameter [7:0] LEGUP_F_decode_block_BB19_103 = 8'd103;
parameter [7:0] LEGUP_F_decode_block_BB19_104 = 8'd104;
parameter [7:0] LEGUP_F_decode_block_BB19_105 = 8'd105;
parameter [7:0] LEGUP_F_decode_block_BB19_106 = 8'd106;
parameter [7:0] LEGUP_F_decode_block_BB19_107 = 8'd107;
parameter [7:0] LEGUP_F_decode_block_BB19_108 = 8'd108;
parameter [7:0] LEGUP_F_decode_block_BB19_109 = 8'd109;
parameter [7:0] LEGUP_F_decode_block_BB19_110 = 8'd110;
parameter [7:0] LEGUP_F_decode_block_BB19_111 = 8'd111;
parameter [7:0] LEGUP_F_decode_block_BB19_112 = 8'd112;
parameter [7:0] LEGUP_F_decode_block_BB19_113 = 8'd113;
parameter [7:0] LEGUP_F_decode_block_BB19_114 = 8'd114;
parameter [7:0] LEGUP_F_decode_block_BB19_115 = 8'd115;
parameter [7:0] LEGUP_F_decode_block_BB19_116 = 8'd116;
parameter [7:0] LEGUP_F_decode_block_BB19_117 = 8'd117;
parameter [7:0] LEGUP_F_decode_block_BB19_118 = 8'd118;
parameter [7:0] LEGUP_F_decode_block_BB19_119 = 8'd119;
parameter [7:0] LEGUP_F_decode_block_BB19_120 = 8'd120;
parameter [7:0] LEGUP_F_decode_block_BB19_121 = 8'd121;
parameter [7:0] LEGUP_F_decode_block_BB19_122 = 8'd122;
parameter [7:0] LEGUP_F_decode_block_BB19_123 = 8'd123;
parameter [7:0] LEGUP_F_decode_block_BB19_124 = 8'd124;
parameter [7:0] LEGUP_F_decode_block_BB19_125 = 8'd125;
parameter [7:0] LEGUP_F_decode_block_BB19_126 = 8'd126;
parameter [7:0] LEGUP_F_decode_block_BB19_127 = 8'd127;
parameter [7:0] LEGUP_F_decode_block_BB19_128 = 8'd128;
parameter [7:0] LEGUP_F_decode_block_BB19_129 = 8'd129;
parameter [7:0] LEGUP_F_decode_block_BB19_130 = 8'd130;
parameter [7:0] LEGUP_F_decode_block_BB19_131 = 8'd131;
parameter [7:0] LEGUP_F_decode_block_BB19_132 = 8'd132;
parameter [7:0] LEGUP_F_decode_block_BB19_133 = 8'd133;
parameter [7:0] LEGUP_F_decode_block_BB19_134 = 8'd134;
parameter [7:0] LEGUP_F_decode_block_BB19_135 = 8'd135;
parameter [7:0] LEGUP_F_decode_block_BB19_136 = 8'd136;
parameter [7:0] LEGUP_F_decode_block_BB19_137 = 8'd137;
parameter [7:0] LEGUP_F_decode_block_BB19_138 = 8'd138;
parameter [7:0] LEGUP_F_decode_block_BB19_139 = 8'd139;
parameter [7:0] LEGUP_F_decode_block_BB19_140 = 8'd140;
parameter [7:0] LEGUP_F_decode_block_BB20_141 = 8'd141;
parameter [7:0] LEGUP_F_decode_block_BB20_142 = 8'd142;
parameter [7:0] LEGUP_F_decode_block_BB20_143 = 8'd143;
parameter [7:0] LEGUP_F_decode_block_BB21_144 = 8'd144;
parameter [7:0] LEGUP_F_decode_block_BB21_145 = 8'd145;
parameter [7:0] LEGUP_F_decode_block_BB21_146 = 8'd146;
parameter [7:0] LEGUP_F_decode_block_BB22_147 = 8'd147;
parameter [7:0] LEGUP_F_decode_block_BB23_148 = 8'd148;
parameter [7:0] LEGUP_F_decode_block_BB24_149 = 8'd149;
parameter [7:0] LEGUP_F_decode_block_BB25_150 = 8'd150;
parameter [7:0] LEGUP_F_decode_block_BB26_151 = 8'd151;
parameter [7:0] LEGUP_function_call_6 = 8'd6;
parameter [7:0] LEGUP_function_call_7 = 8'd7;
parameter [7:0] LEGUP_function_call_9 = 8'd9;
parameter [7:0] LEGUP_function_call_10 = 8'd10;
parameter [7:0] LEGUP_function_call_26 = 8'd26;
parameter [7:0] LEGUP_function_call_27 = 8'd27;
parameter [7:0] LEGUP_function_call_30 = 8'd30;
parameter [7:0] LEGUP_function_call_31 = 8'd31;
input clk;
input reset;
input start;
output reg finish;
input [31:0] arg_comp_no;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_out_buf;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_HuffBuff;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [7:0] cur_state;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_1;
reg [7:0] decode_block_0_2;
reg [31:0] decode_block_0_3;
reg [31:0] decode_block_0_3_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_4_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_5;
reg [31:0] decode_block_0_6;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_7_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_8;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_8_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_9;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_0_9_reg;
reg [31:0] decode_block_0_10;
reg [31:0] decode_block_0_10_reg;
reg decode_block_0_11;
reg [31:0] decode_block_12_13;
reg [31:0] decode_block_12_13_reg;
reg [31:0] decode_block_12_14;
reg [31:0] decode_block_12_14_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_12_15;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_12_15_reg;
reg [31:0] decode_block_12_16;
reg [31:0] decode_block_12_17;
reg decode_block_12_18;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_19_20;
reg [31:0] decode_block_19_21;
reg [31:0] decode_block_19_22;
reg [31:0] decode_block_19_23;
reg [31:0] decode_block_24_diff_0_i;
reg [31:0] decode_block_24_diff_0_i_reg;
reg [31:0] decode_block_24_25;
reg [31:0] decode_block_24_26;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_27;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_27_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_28;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_28_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_29;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_29_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_30;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_30_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_31;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i_31_reg;
reg [31:0] decode_block__lr_ph_i_indvar_i2;
reg [31:0] decode_block__lr_ph_i_tmp_i4;
reg [31:0] decode_block__lr_ph_i_tmp4_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__lr_ph_i_mptr_03_i;
reg decode_block__lr_ph_i_32;
reg [31:0] decode_block__backedge_i_k_0_i;
reg [31:0] decode_block__backedge_i_k_0_i_reg;
reg decode_block__backedge_i_33;
reg [31:0] decode_block_34_35;
reg [31:0] decode_block_34_36;
reg [31:0] decode_block_34_36_reg;
reg [31:0] decode_block_34_37;
reg [31:0] decode_block_34_37_reg;
reg [31:0] decode_block_34_38;
reg [31:0] decode_block_34_39;
reg [31:0] decode_block_34_39_reg;
reg decode_block_34_40;
reg [31:0] decode_block_41_42;
reg [31:0] decode_block_41_42_reg;
reg decode_block_41_43;
reg [31:0] decode_block_44_45;
reg [31:0] decode_block_44_45_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_44_46;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_44_46_reg;
reg [31:0] decode_block_44_47;
reg [31:0] decode_block_44_47_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_44_48;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_44_48_reg;
reg [31:0] decode_block_44_49;
reg [31:0] decode_block_44_50;
reg decode_block_44_51;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_52_53;
reg [31:0] decode_block_52_54;
reg [31:0] decode_block_52_55;
reg [31:0] decode_block_52_56;
reg [31:0] decode_block_57_58;
reg decode_block_59_60;
reg [31:0] decode_block_61_62;
reg [31:0] decode_block_DecodeHuffMCU_exit_i_02_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_DecodeHuffMCU_exit__01_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_DecodeHuffMCU_exit__01_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_DecodeHuffMCU_exit_scevgep_i;
reg [31:0] decode_block_DecodeHuffMCU_exit_63;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_DecodeHuffMCU_exit_64;
reg [31:0] decode_block_DecodeHuffMCU_exit_65;
reg [31:0] decode_block_DecodeHuffMCU_exit_66;
reg [31:0] decode_block_DecodeHuffMCU_exit_66_reg;
reg decode_block_DecodeHuffMCU_exit_exitcond10;
reg decode_block_DecodeHuffMCU_exit_exitcond10_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IZigzagMatrix_exit_67;
reg [7:0] decode_block_IZigzagMatrix_exit_68;
reg [31:0] decode_block_IZigzagMatrix_exit_tmp;
reg [31:0] decode_block_IZigzagMatrix_exit_tmp9;
reg [31:0] decode_block_IZigzagMatrix_exit_tmp9_reg;
reg [31:0] decode_block_69_indvar_i4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_69__01_i6;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_69__01_i6_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_69_mptr_02_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_69_mptr_02_i_reg;
reg [31:0] decode_block_69_tmp_i5;
reg [31:0] decode_block_69_tmp_i5_reg;
reg [31:0] decode_block_69_70;
reg [31:0] decode_block_69_70_reg;
reg [31:0] decode_block_69_71;
reg [31:0] decode_block_69_72;
reg decode_block_69_exitcond8;
reg decode_block_69_exitcond8_reg;
reg [31:0] decode_block_IQuantize_exit_i_027_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep44_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep45_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep45_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp46_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep47_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep47_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep48_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep48_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp49_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep50_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep50_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep51_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep51_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp52_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep53_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep53_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep54_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep54_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp55_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep56_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep56_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep57_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep57_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp58_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep59_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep59_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep60_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep60_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp61_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep62_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep62_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep63_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep63_i_reg;
reg [31:0] decode_block_IQuantize_exit_tmp64_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep65_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep65_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep66_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_IQuantize_exit_scevgep66_i_reg;
reg [31:0] decode_block_IQuantize_exit_73;
reg [31:0] decode_block_IQuantize_exit_74;
reg [31:0] decode_block_IQuantize_exit_74_reg;
reg [31:0] decode_block_IQuantize_exit_75;
reg [31:0] decode_block_IQuantize_exit_76;
reg [31:0] decode_block_IQuantize_exit_77;
reg [31:0] decode_block_IQuantize_exit_78;
reg [31:0] decode_block_IQuantize_exit_79;
reg [31:0] decode_block_IQuantize_exit_80;
reg [31:0] decode_block_IQuantize_exit_81;
reg [31:0] decode_block_IQuantize_exit_82;
reg [31:0] decode_block_IQuantize_exit_83;
reg [31:0] decode_block_IQuantize_exit_83_reg;
reg [31:0] decode_block_IQuantize_exit_84;
reg [31:0] decode_block_IQuantize_exit_85;
reg [31:0] decode_block_IQuantize_exit_86;
reg [31:0] decode_block_IQuantize_exit_86_reg;
reg [31:0] decode_block_IQuantize_exit_87;
reg [31:0] decode_block_IQuantize_exit_88;
reg [31:0] decode_block_IQuantize_exit_88_reg;
reg [31:0] decode_block_IQuantize_exit_89;
reg [31:0] decode_block_IQuantize_exit_90;
reg [31:0] decode_block_IQuantize_exit_90_reg;
reg [31:0] decode_block_IQuantize_exit_91;
reg [31:0] decode_block_IQuantize_exit_91_reg;
reg [31:0] decode_block_IQuantize_exit_92;
reg [31:0] decode_block_IQuantize_exit_93;
reg [31:0] decode_block_IQuantize_exit_94;
reg [31:0] decode_block_IQuantize_exit_94_reg;
reg [31:0] decode_block_IQuantize_exit_95;
reg [31:0] decode_block_IQuantize_exit_95_reg;
reg [31:0] decode_block_IQuantize_exit_96;
reg [31:0] decode_block_IQuantize_exit_97;
reg [31:0] decode_block_IQuantize_exit_98;
reg [31:0] decode_block_IQuantize_exit_98_reg;
reg [31:0] decode_block_IQuantize_exit_99;
reg [31:0] decode_block_IQuantize_exit_100;
reg [31:0] decode_block_IQuantize_exit_100_reg;
reg [31:0] decode_block_IQuantize_exit_101;
reg [31:0] decode_block_IQuantize_exit_101_reg;
reg [31:0] decode_block_IQuantize_exit_102;
reg [31:0] decode_block_IQuantize_exit_103;
reg [31:0] decode_block_IQuantize_exit_103_reg;
reg [31:0] decode_block_IQuantize_exit_104;
reg [31:0] decode_block_IQuantize_exit_104_reg;
reg [31:0] decode_block_IQuantize_exit_105;
reg [31:0] decode_block_IQuantize_exit_105_reg;
reg [31:0] decode_block_IQuantize_exit_106;
reg [31:0] decode_block_IQuantize_exit_107;
reg [31:0] decode_block_IQuantize_exit_108;
reg [31:0] decode_block_IQuantize_exit_108_reg;
reg [31:0] decode_block_IQuantize_exit_109;
reg [31:0] decode_block_IQuantize_exit_109_reg;
reg [31:0] decode_block_IQuantize_exit_110;
reg [31:0] decode_block_IQuantize_exit_111;
reg [31:0] decode_block_IQuantize_exit_112;
reg [31:0] decode_block_IQuantize_exit_112_reg;
reg [31:0] decode_block_IQuantize_exit_113;
reg [31:0] decode_block_IQuantize_exit_113_reg;
reg [31:0] decode_block_IQuantize_exit_114;
reg [31:0] decode_block_IQuantize_exit_114_reg;
reg [31:0] decode_block_IQuantize_exit_115;
reg [31:0] decode_block_IQuantize_exit_115_reg;
reg [31:0] decode_block_IQuantize_exit_116;
reg [31:0] decode_block_IQuantize_exit_116_reg;
reg [31:0] decode_block_IQuantize_exit_117;
reg [31:0] decode_block_IQuantize_exit_118;
reg [31:0] decode_block_IQuantize_exit_119;
reg [31:0] decode_block_IQuantize_exit_120;
reg [31:0] decode_block_IQuantize_exit_121;
reg [31:0] decode_block_IQuantize_exit_122;
reg [31:0] decode_block_IQuantize_exit_122_reg;
reg [31:0] decode_block_IQuantize_exit_123;
reg [31:0] decode_block_IQuantize_exit_124;
reg [31:0] decode_block_IQuantize_exit_125;
reg [31:0] decode_block_IQuantize_exit_125_reg;
reg [31:0] decode_block_IQuantize_exit_126;
reg [31:0] decode_block_IQuantize_exit_127;
reg [31:0] decode_block_IQuantize_exit_128;
reg [31:0] decode_block_IQuantize_exit_129;
reg [31:0] decode_block_IQuantize_exit_129_reg;
reg [31:0] decode_block_IQuantize_exit_130;
reg [31:0] decode_block_IQuantize_exit_130_reg;
reg [31:0] decode_block_IQuantize_exit_131;
reg [31:0] decode_block_IQuantize_exit_131_reg;
reg [31:0] decode_block_IQuantize_exit_132;
reg [31:0] decode_block_IQuantize_exit_132_reg;
reg [31:0] decode_block_IQuantize_exit_133;
reg [31:0] decode_block_IQuantize_exit_133_reg;
reg [31:0] decode_block_IQuantize_exit_134;
reg [31:0] decode_block_IQuantize_exit_134_reg;
reg [31:0] decode_block_IQuantize_exit_135;
reg [31:0] decode_block_IQuantize_exit_135_reg;
reg decode_block_IQuantize_exit_exitcond43_i;
reg decode_block_IQuantize_exit_exitcond43_i_reg;
reg [31:0] decode_block__preheader25_i_i_126_i;
reg [31:0] decode_block__preheader25_i_tmp_i6;
reg [31:0] decode_block__preheader25_i_tmp2967_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep_i7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep_i7_reg;
reg [31:0] decode_block__preheader25_i_tmp3068_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep31_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep31_i_reg;
reg [31:0] decode_block__preheader25_i_tmp3269_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep33_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep33_i_reg;
reg [31:0] decode_block__preheader25_i_tmp3470_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep35_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep35_i_reg;
reg [31:0] decode_block__preheader25_i_tmp3671_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep37_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep37_i_reg;
reg [31:0] decode_block__preheader25_i_tmp3872_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep39_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep39_i_reg;
reg [31:0] decode_block__preheader25_i_tmp4073_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep41_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep41_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep42_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader25_i_scevgep42_i_reg;
reg [31:0] decode_block__preheader25_i_136;
reg [31:0] decode_block__preheader25_i_136_reg;
reg [31:0] decode_block__preheader25_i_137;
reg [31:0] decode_block__preheader25_i_138;
reg [31:0] decode_block__preheader25_i_139;
reg [31:0] decode_block__preheader25_i_140;
reg [31:0] decode_block__preheader25_i_141;
reg [31:0] decode_block__preheader25_i_142;
reg [31:0] decode_block__preheader25_i_143;
reg [31:0] decode_block__preheader25_i_144;
reg [31:0] decode_block__preheader25_i_144_reg;
reg [31:0] decode_block__preheader25_i_145;
reg [31:0] decode_block__preheader25_i_146;
reg [31:0] decode_block__preheader25_i_147;
reg [31:0] decode_block__preheader25_i_147_reg;
reg [31:0] decode_block__preheader25_i_148;
reg [31:0] decode_block__preheader25_i_149;
reg [31:0] decode_block__preheader25_i_149_reg;
reg [31:0] decode_block__preheader25_i_150;
reg [31:0] decode_block__preheader25_i_151;
reg [31:0] decode_block__preheader25_i_151_reg;
reg [31:0] decode_block__preheader25_i_152;
reg [31:0] decode_block__preheader25_i_152_reg;
reg [31:0] decode_block__preheader25_i_153;
reg [31:0] decode_block__preheader25_i_154;
reg [31:0] decode_block__preheader25_i_155;
reg [31:0] decode_block__preheader25_i_155_reg;
reg [31:0] decode_block__preheader25_i_156;
reg [31:0] decode_block__preheader25_i_156_reg;
reg [31:0] decode_block__preheader25_i_157;
reg [31:0] decode_block__preheader25_i_158;
reg [31:0] decode_block__preheader25_i_159;
reg [31:0] decode_block__preheader25_i_159_reg;
reg [31:0] decode_block__preheader25_i_160;
reg [31:0] decode_block__preheader25_i_161;
reg [31:0] decode_block__preheader25_i_162;
reg [31:0] decode_block__preheader25_i_162_reg;
reg [31:0] decode_block__preheader25_i_163;
reg [31:0] decode_block__preheader25_i_164;
reg [31:0] decode_block__preheader25_i_165;
reg [31:0] decode_block__preheader25_i_165_reg;
reg [31:0] decode_block__preheader25_i_166;
reg [31:0] decode_block__preheader25_i_166_reg;
reg [31:0] decode_block__preheader25_i_167;
reg [31:0] decode_block__preheader25_i_168;
reg [31:0] decode_block__preheader25_i_169;
reg [31:0] decode_block__preheader25_i_169_reg;
reg [31:0] decode_block__preheader25_i_170;
reg [31:0] decode_block__preheader25_i_170_reg;
reg [31:0] decode_block__preheader25_i_171;
reg [31:0] decode_block__preheader25_i_172;
reg [31:0] decode_block__preheader25_i_173;
reg [31:0] decode_block__preheader25_i_173_reg;
reg [31:0] decode_block__preheader25_i_174;
reg [31:0] decode_block__preheader25_i_174_reg;
reg [31:0] decode_block__preheader25_i_175;
reg [31:0] decode_block__preheader25_i_175_reg;
reg [31:0] decode_block__preheader25_i_176;
reg [31:0] decode_block__preheader25_i_176_reg;
reg [31:0] decode_block__preheader25_i_177;
reg [31:0] decode_block__preheader25_i_177_reg;
reg [31:0] decode_block__preheader25_i_178;
reg [31:0] decode_block__preheader25_i_179;
reg [31:0] decode_block__preheader25_i_180;
reg [31:0] decode_block__preheader25_i_181;
reg [31:0] decode_block__preheader25_i_182;
reg [31:0] decode_block__preheader25_i_183;
reg [31:0] decode_block__preheader25_i_183_reg;
reg [31:0] decode_block__preheader25_i_184;
reg [31:0] decode_block__preheader25_i_185;
reg [31:0] decode_block__preheader25_i_186;
reg [31:0] decode_block__preheader25_i_186_reg;
reg [31:0] decode_block__preheader25_i_187;
reg [31:0] decode_block__preheader25_i_188;
reg [31:0] decode_block__preheader25_i_189;
reg [31:0] decode_block__preheader25_i_190;
reg [31:0] decode_block__preheader25_i_190_reg;
reg [31:0] decode_block__preheader25_i_191;
reg [31:0] decode_block__preheader25_i_191_reg;
reg [31:0] decode_block__preheader25_i_192;
reg [31:0] decode_block__preheader25_i_192_reg;
reg [31:0] decode_block__preheader25_i_193;
reg [31:0] decode_block__preheader25_i_193_reg;
reg [31:0] decode_block__preheader25_i_194;
reg [31:0] decode_block__preheader25_i_194_reg;
reg [31:0] decode_block__preheader25_i_195;
reg [31:0] decode_block__preheader25_i_195_reg;
reg [31:0] decode_block__preheader25_i_196;
reg [31:0] decode_block__preheader25_i_196_reg;
reg decode_block__preheader25_i_exitcond28_i;
reg decode_block__preheader25_i_exitcond28_i_reg;
reg [31:0] decode_block__preheader_i8_i_224_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i8_aptr_023_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block__preheader_i8_aptr_023_i_reg;
reg [31:0] decode_block__preheader_i8_197;
reg [31:0] decode_block__preheader_i8_198;
reg [31:0] decode_block__preheader_i8_199;
reg [31:0] decode_block__preheader_i8_200;
reg [31:0] decode_block__preheader_i8_201;
reg [31:0] decode_block__preheader_i8_201_reg;
reg [31:0] decode_block__preheader_i8_202;
reg [31:0] decode_block__preheader_i8_202_reg;
reg [31:0] decode_block__preheader_i8_203;
reg [31:0] decode_block__preheader_i8_203_reg;
reg decode_block__preheader_i8_exitcond_i;
reg decode_block__preheader_i8_exitcond_i_reg;
reg [31:0] decode_block_ChenIDct_exit_indvar_i1;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_ChenIDct_exit_mptr_01_i2;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_ChenIDct_exit_mptr_01_i2_reg;
reg [31:0] decode_block_ChenIDct_exit_tmp_i3;
reg [31:0] decode_block_ChenIDct_exit_tmp_i3_reg;
reg [31:0] decode_block_ChenIDct_exit_204;
reg [31:0] decode_block_ChenIDct_exit_205;
reg decode_block_ChenIDct_exit_exitcond7;
reg decode_block_ChenIDct_exit_exitcond7_reg;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_indvar_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_PostshiftIDctMatrix_exit_mptr_01_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_PostshiftIDctMatrix_exit_mptr_01_i_reg;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_tmp_i;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_tmp_i_reg;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_206;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_206_reg;
reg decode_block_PostshiftIDctMatrix_exit_207;
reg decode_block_209_210;
reg decode_block_212_exitcond;
reg DecodeHuffman_start;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_arg_Xhuff_huffval;
reg [31:0] DecodeHuffman_arg_Dhuff_ml;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_arg_Dhuff_maxcode;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_arg_Dhuff_mincode;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_arg_Dhuff_valptr;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_memory_controller_address;
wire DecodeHuffman_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] DecodeHuffman_memory_controller_in;
reg DecodeHuffman_memory_controller_waitrequest;
wire DecodeHuffman_memory_controller_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] DecodeHuffman_memory_controller_out;
wire [1:0] DecodeHuffman_memory_controller_size;
wire DecodeHuffman_finish;
wire [31:0] DecodeHuffman_return_val;
reg legup_function_call;
reg buf_getv_start;
reg [31:0] buf_getv_arg_n;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_memory_controller_address;
wire buf_getv_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] buf_getv_memory_controller_in;
reg buf_getv_memory_controller_waitrequest;
wire buf_getv_memory_controller_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] buf_getv_memory_controller_out;
wire [1:0] buf_getv_memory_controller_size;
wire buf_getv_finish;
wire [31:0] buf_getv_return_val;
reg [31:0] decode_block_signed_multiply_32_1_op0;
reg [31:0] decode_block_signed_multiply_32_1_op1;
reg [31:0] decode_block_signed_multiply_32_1;
reg [31:0] decode_block_signed_multiply_32_0_op0;
reg [31:0] decode_block_signed_multiply_32_0_op1;
reg [31:0] decode_block_signed_multiply_32_0;
reg [31:0] decode_block_signed_multiply_32_2_op0;
reg [31:0] decode_block_signed_multiply_32_2_op1;
reg [31:0] decode_block_signed_multiply_32_2;
reg [31:0] decode_block_signed_multiply_32_3_op0;
reg [31:0] decode_block_signed_multiply_32_3_op1;
reg [31:0] decode_block_signed_multiply_32_3;
reg [31:0] decode_block_signed_divide_32_0_op0;
reg [31:0] decode_block_signed_divide_32_0_op1;
reg [31:0] decode_block_signed_divide_32_0;
wire [31:0] lpm_divide_decode_block__preheader_i8_202_out;
wire [31:0] decode_block__preheader_i8_202_unused;
reg lpm_divide_decode_block__preheader_i8_202_en;
reg [31:0] decode_block__lr_ph_i_indvar_i2_phi_temp;
reg [31:0] decode_block_24_diff_0_i_phi_temp;
reg [31:0] decode_block__backedge_i_k_0_i_phi_temp;
reg [31:0] decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp;
reg [31:0] decode_block_69_indvar_i4_phi_temp;
reg [31:0] decode_block_IQuantize_exit_i_027_i_phi_temp;
reg [31:0] decode_block__preheader25_i_i_126_i_phi_temp;
reg [31:0] decode_block__preheader_i8_i_224_i_phi_temp;
reg [31:0] decode_block_ChenIDct_exit_indvar_i1_phi_temp;
reg [31:0] decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp;
/* %202 = sdiv i32 %201, 16*/
lpm_divide lpm_divide_decode_block__preheader_i8_202 (
.numer (decode_block_signed_divide_32_0_op0),
.denom (decode_block_signed_divide_32_0_op1),
.quotient (lpm_divide_decode_block__preheader_i8_202_out),
.remain (decode_block__preheader_i8_202_unused),
.clock (clk),
.aclr (1'd0),
.clken (lpm_divide_decode_block__preheader_i8_202_en)
);
defparam
lpm_divide_decode_block__preheader_i8_202.lpm_pipeline = 32,
lpm_divide_decode_block__preheader_i8_202.lpm_widthd = 32,
lpm_divide_decode_block__preheader_i8_202.lpm_widthn = 32,
lpm_divide_decode_block__preheader_i8_202.lpm_drepresentation = "SIGNED",
lpm_divide_decode_block__preheader_i8_202.lpm_nrepresentation = "SIGNED",
lpm_divide_decode_block__preheader_i8_202.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE";
DecodeHuffman DecodeHuffman_inst (
.clk (clk),
.reset (reset),
.start (DecodeHuffman_start),
.finish (DecodeHuffman_finish),
.return_val (DecodeHuffman_return_val),
.memory_controller_address (DecodeHuffman_memory_controller_address),
.memory_controller_write_enable (DecodeHuffman_memory_controller_write_enable),
.memory_controller_enable (DecodeHuffman_memory_controller_enable),
.memory_controller_in (DecodeHuffman_memory_controller_in),
.memory_controller_size (DecodeHuffman_memory_controller_size),
.memory_controller_waitrequest (DecodeHuffman_memory_controller_waitrequest),
.memory_controller_out (DecodeHuffman_memory_controller_out),
.arg_Xhuff_huffval (DecodeHuffman_arg_Xhuff_huffval),
.arg_Dhuff_ml (DecodeHuffman_arg_Dhuff_ml),
.arg_Dhuff_maxcode (DecodeHuffman_arg_Dhuff_maxcode),
.arg_Dhuff_mincode (DecodeHuffman_arg_Dhuff_mincode),
.arg_Dhuff_valptr (DecodeHuffman_arg_Dhuff_valptr)
);
buf_getv buf_getv_inst (
.clk (clk),
.reset (reset),
.start (buf_getv_start),
.finish (buf_getv_finish),
.return_val (buf_getv_return_val),
.memory_controller_address (buf_getv_memory_controller_address),
.memory_controller_write_enable (buf_getv_memory_controller_write_enable),
.memory_controller_enable (buf_getv_memory_controller_enable),
.memory_controller_in (buf_getv_memory_controller_in),
.memory_controller_size (buf_getv_memory_controller_size),
.memory_controller_waitrequest (buf_getv_memory_controller_waitrequest),
.memory_controller_out (buf_getv_memory_controller_out),
.arg_n (buf_getv_arg_n)
);
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 8'd0;
if (^reset !== 1'bX && ^(8'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_3 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB0_4;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_4;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_4 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB0_5;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB0_5;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB0_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB0_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_6;
if (^reset !== 1'bX && ^(LEGUP_function_call_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_6;
if (^reset !== 1'bX && ^(LEGUP_function_call_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_6 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_7;
if (^reset !== 1'bX && ^(LEGUP_function_call_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_6 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_6;
if (^reset !== 1'bX && ^(LEGUP_function_call_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_7;
if (^reset !== 1'bX && ^(LEGUP_function_call_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_7 & memory_controller_waitrequest == 1'd0 & decode_block_0_11 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB5_21;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB5_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_7 & memory_controller_waitrequest == 1'd0 & decode_block_0_11 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB1_8;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB1_8;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_8 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_9;
if (^reset !== 1'bX && ^(LEGUP_function_call_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_9;
if (^reset !== 1'bX && ^(LEGUP_function_call_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_9 & memory_controller_waitrequest == 1'd0 & buf_getv_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_10;
if (^reset !== 1'bX && ^(LEGUP_function_call_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_9 & memory_controller_waitrequest == 1'd0 & buf_getv_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_9;
if (^reset !== 1'bX && ^(LEGUP_function_call_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_10;
if (^reset !== 1'bX && ^(LEGUP_function_call_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_10 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB1_11;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB1_11;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB1_12;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB1_12;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_12 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB1_13;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB1_13;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB1_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_13 & memory_controller_waitrequest == 1'd0 & decode_block_12_18 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB2_14;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB1_13 & memory_controller_waitrequest == 1'd0 & decode_block_12_18 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB3_17;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB2_14;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB2_15;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB2_15;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_15 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB2_16;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB2_16;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB2_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB2_16 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB3_17;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB3_17;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_17 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB3_18;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB3_18;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_18 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB3_19;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB3_19;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB3_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB3_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB5_21;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB5_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB4_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB4_20;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB4_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB4_20 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB6_22;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB6_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB5_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB5_21;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB5_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB5_21 & memory_controller_waitrequest == 1'd0 & decode_block__lr_ph_i_32 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB5_21;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB5_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB5_21 & memory_controller_waitrequest == 1'd0 & decode_block__lr_ph_i_32 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB4_20;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB4_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB6_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB6_22;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB6_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB6_22 & memory_controller_waitrequest == 1'd0 & decode_block__backedge_i_33 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB6_22 & memory_controller_waitrequest == 1'd0 & decode_block__backedge_i_33 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_23 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_24 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB7_25;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB7_25;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB7_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB7_25 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_26;
if (^reset !== 1'bX && ^(LEGUP_function_call_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_26;
if (^reset !== 1'bX && ^(LEGUP_function_call_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_27;
if (^reset !== 1'bX && ^(LEGUP_function_call_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_26;
if (^reset !== 1'bX && ^(LEGUP_function_call_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_27;
if (^reset !== 1'bX && ^(LEGUP_function_call_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_27 & memory_controller_waitrequest == 1'd0 & decode_block_34_40 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB12_40;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB12_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_27 & memory_controller_waitrequest == 1'd0 & decode_block_34_40 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB8_28;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB8_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB8_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB8_28;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB8_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB8_28 & memory_controller_waitrequest == 1'd0 & decode_block_41_43 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB8_28 & memory_controller_waitrequest == 1'd0 & decode_block_41_43 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB9_29;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB9_29;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_29 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_30;
if (^reset !== 1'bX && ^(LEGUP_function_call_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_30;
if (^reset !== 1'bX && ^(LEGUP_function_call_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_30 & memory_controller_waitrequest == 1'd0 & buf_getv_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_31;
if (^reset !== 1'bX && ^(LEGUP_function_call_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_30 & memory_controller_waitrequest == 1'd0 & buf_getv_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_30;
if (^reset !== 1'bX && ^(LEGUP_function_call_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_31;
if (^reset !== 1'bX && ^(LEGUP_function_call_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_32 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB9_33;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB9_33;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB9_34;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB9_34;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_34 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB9_35;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB9_35;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB9_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_35 & memory_controller_waitrequest == 1'd0 & decode_block_44_51 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB9_35 & memory_controller_waitrequest == 1'd0 & decode_block_44_51 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_36 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB10_37;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB10_37;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB10_38;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_38 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB10_38;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB10_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB10_38 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB11_39 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB11_39 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB6_22;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB6_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB12_40 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB12_40;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB12_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB12_40 & memory_controller_waitrequest == 1'd0 & decode_block_59_60 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB13_41;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB13_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB12_40 & memory_controller_waitrequest == 1'd0 & decode_block_59_60 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB13_41 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB13_41;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB13_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB13_41 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB6_22;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB6_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_42 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_42 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_43 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_43 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_44 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_44 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_45 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_45 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_46;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_46 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB14_46;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_46 & memory_controller_waitrequest == 1'd0 & decode_block_DecodeHuffMCU_exit_exitcond10_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB15_47;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB14_46 & memory_controller_waitrequest == 1'd0 & decode_block_DecodeHuffMCU_exit_exitcond10_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_47 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB15_47;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_47 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_48 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_48 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB15_49;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_49 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB15_49;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB15_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB15_49 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB16_50;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_50 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB16_50;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_50 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB16_51;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_51 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB16_51;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_51 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB16_52;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_52 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB16_52;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_52 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_53 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_53 & memory_controller_waitrequest == 1'd0 & decode_block_69_exitcond8_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_54;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB16_53 & memory_controller_waitrequest == 1'd0 & decode_block_69_exitcond8_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB16_50;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB16_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_54 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_54;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_54 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_55;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_55 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_55;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_55 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_56;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_56 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_56;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_56 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_57;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_57 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_57;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_57 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_58;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_58 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_58;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_58 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_59;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_59) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_59 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_59;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_59) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_59 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_60;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_60 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_60;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_60 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_61;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_61 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_61;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_61 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_62;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_62) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_62 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_62;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_62) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_62 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_63;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_63) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_63 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_63;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_63) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_63 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_64;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_64) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_64 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_64;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_64) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_64 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_65;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_65 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_65;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_65 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_66;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_66) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_66 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_66;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_66) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_66 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_67;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_67) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_67 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_67;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_67) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_67 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_68;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_68) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_68 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_68;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_68) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_68 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_69;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_69 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_69;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_69 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_70;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_70) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_70 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_70;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_70) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_70 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_71;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_71 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB17_71;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_71 & memory_controller_waitrequest == 1'd0 & decode_block_IQuantize_exit_exitcond43_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_72;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB17_71 & memory_controller_waitrequest == 1'd0 & decode_block_IQuantize_exit_exitcond43_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB17_54;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB17_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_72 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_72;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_72 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_73;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_73 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_73;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_73 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_74;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_74) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_74 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_74;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_74) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_74 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_75;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_75) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_75 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_75;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_75) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_75 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_76;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_76) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_76 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_76;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_76) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_76 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_77;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_77) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_77 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_77;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_77) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_77 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_78;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_78) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_78 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_78;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_78) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_78 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_79;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_79) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_79 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_79;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_79) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_79 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_80;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_80) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_80 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_80;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_80) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_80 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_81;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_81) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_81 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_81;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_81) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_81 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_82;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_82 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_82;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_82 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_83;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_83) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_83 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_83;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_83) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_83 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_84;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_84) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_84 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_84;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_84) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_84 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_85;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_85) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_85 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_85;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_85) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_85 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_86;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_86) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_86 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_86;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_86) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_86 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_87;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_87) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_87 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_87;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_87) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_87 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_88;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_88) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_88 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_88;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_88) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_88 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_89;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_89) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_89 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB18_89;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_89) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_89 & memory_controller_waitrequest == 1'd0 & decode_block__preheader25_i_exitcond28_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_90;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB18_89 & memory_controller_waitrequest == 1'd0 & decode_block__preheader25_i_exitcond28_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB18_72;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB18_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_90 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_90;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_90 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_91;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_91) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_91 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_91;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_91) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_91 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_92;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_92) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_92 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_92;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_92) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_92 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_93;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_93) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_93 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_93;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_93) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_93 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_94;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_94) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_94 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_94;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_94) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_94 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_95;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_95) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_95 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_95;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_95) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_95 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_96;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_96) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_96 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_96;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_96) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_96 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_97;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_97) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_97 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_97;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_97) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_97 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_98;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_98 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_98;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_98 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_99;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_99 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_99;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_99 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_100;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_100 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_100;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_100 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_101;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_101 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_101;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_101 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_102;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_102) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_102 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_102;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_102) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_102 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_103;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_103 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_103;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_103 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_104;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_104 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_104;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_104 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_105;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_105 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_105;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_105 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_106;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_106 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_106;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_106 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_107;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_107) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_107 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_107;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_107) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_107 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_108;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_108) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_108 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_108;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_108) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_108 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_109;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_109 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_109;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_109 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_110;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_110) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_110 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_110;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_110) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_110 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_111;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_111) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_111 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_111;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_111) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_111 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_112;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_112 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_112;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_112 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_113;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_113) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_113 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_113;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_113) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_113 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_114;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_114 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_114;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_114 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_115;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_115) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_115 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_115;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_115) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_115 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_116;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_116 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_116;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_116 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_117;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_117) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_117 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_117;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_117) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_117 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_118;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_118) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_118 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_118;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_118) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_118 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_119;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_119) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_119 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_119;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_119) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_119 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_120;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_120) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_120 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_120;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_120) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_120 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_121;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_121) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_121 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_121;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_121) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_121 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_122;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_122 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_122;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_122 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_123;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_123) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_123 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_123;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_123) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_123 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_124;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_124) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_124 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_124;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_124) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_124 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_125;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_125) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_125 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_125;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_125) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_125 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_126;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_126) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_126 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_126;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_126) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_126 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_127;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_127) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_127 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_127;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_127) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_127 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_128;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_128) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_128 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_128;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_128) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_128 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_129;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_129 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_129;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_129 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_130;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_130 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_130;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_130 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_131;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_131 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_131;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_131 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_132;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_132 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_132;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_132 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_133;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_133 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_133;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_133 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_134;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_134 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_134;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_134 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_135;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_135 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_135;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_135 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_136;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_136 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_136;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_136 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_137;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_137) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_137 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_137;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_137) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_137 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_138;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_138) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_138 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_138;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_138) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_138 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_139;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_139 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_139;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_139 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_140;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_140 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB19_140;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_140 & memory_controller_waitrequest == 1'd0 & decode_block__preheader_i8_exitcond_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB20_141;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_141) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB19_140 & memory_controller_waitrequest == 1'd0 & decode_block__preheader_i8_exitcond_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB19_90;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB19_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_141 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB20_141;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_141) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_141 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB20_142;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_142) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_142 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB20_142;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_142) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_142 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB20_143;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_143) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_143 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB20_143;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_143) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_143 & memory_controller_waitrequest == 1'd0 & decode_block_ChenIDct_exit_exitcond7_reg == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB21_144;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB20_143 & memory_controller_waitrequest == 1'd0 & decode_block_ChenIDct_exit_exitcond7_reg == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB20_141;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB20_141) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_144 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB21_144;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_144 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB21_145;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_145) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_145 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB21_145;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_145) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_145 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB21_146;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_146) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_146 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB21_146;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_146) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_146 & memory_controller_waitrequest == 1'd0 & decode_block_PostshiftIDctMatrix_exit_207 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB22_147;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB22_147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB21_146 & memory_controller_waitrequest == 1'd0 & decode_block_PostshiftIDctMatrix_exit_207 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB23_148;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB23_148) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB22_147 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB22_147;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB22_147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB22_147 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB25_150;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB25_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB23_148 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB23_148;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB23_148) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB23_148 & memory_controller_waitrequest == 1'd0 & decode_block_209_210 == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB24_149;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB24_149) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB23_148 & memory_controller_waitrequest == 1'd0 & decode_block_209_210 == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB25_150;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB25_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB24_149 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB24_149;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB24_149) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB24_149 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB25_150;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB25_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB25_150 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB25_150;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB25_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB25_150 & memory_controller_waitrequest == 1'd0 & decode_block_212_exitcond == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB26_151;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB26_151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB25_150 & memory_controller_waitrequest == 1'd0 & decode_block_212_exitcond == 1'd0)
begin
cur_state <= LEGUP_F_decode_block_BB21_144;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB21_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB26_151 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_decode_block_BB26_151;
if (^reset !== 1'bX && ^(LEGUP_F_decode_block_BB26_151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_decode_block_BB26_151 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %1 = getelementptr inbounds [3 x i8]* @p_jinfo_comps_info_dc_tbl_no, i32 0, i32 %comp_no*/
begin
decode_block_0_1 = `TAG_g_p_jinfo_comps_info_dc_tbl_no_a + 1 * arg_comp_no;
end
end
always @(*) begin
/* decode_block: %0*/
/* %2 = load i8* %1, align 1, !tbaa !0*/
begin
decode_block_0_2 = memory_controller_out[7:0];
end
end
always @(*) begin
/* decode_block: %0*/
/* %3 = sext i8 %2 to i32*/
begin
decode_block_0_3 = $signed(decode_block_0_2);
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %3 = sext i8 %2 to i32*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
decode_block_0_3_reg <= decode_block_0_3;
if (^reset !== 1'bX && ^(decode_block_0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_3_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %4 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_dc_xhuff_tbl_huffval, i32 0, i32 %3, i32 0*/
begin
decode_block_0_4 = `TAG_g_p_jinfo_dc_xhuff_tbl_huffval_a + 1028 * decode_block_0_3;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %4 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_dc_xhuff_tbl_huffval, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
decode_block_0_4_reg <= decode_block_0_4;
if (^reset !== 1'bX && ^(decode_block_0_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_4_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %5 = getelementptr inbounds [2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 %3*/
begin
decode_block_0_5 = `TAG_g_p_jinfo_dc_dhuff_tbl_ml_a + 4 * decode_block_0_3;
end
end
always @(*) begin
/* decode_block: %0*/
/* %6 = load i32* %5, align 4, !tbaa !2*/
begin
decode_block_0_6 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %0*/
/* %7 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 %3, i32 0*/
begin
decode_block_0_7 = `TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a + 144 * decode_block_0_3;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %7 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
decode_block_0_7_reg <= decode_block_0_7;
if (^reset !== 1'bX && ^(decode_block_0_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_7_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %8 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 %3, i32 0*/
begin
decode_block_0_8 = `TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a + 144 * decode_block_0_3;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %8 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
decode_block_0_8_reg <= decode_block_0_8;
if (^reset !== 1'bX && ^(decode_block_0_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_8_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %9 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 %3, i32 0*/
begin
decode_block_0_9 = `TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a + 144 * decode_block_0_3;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %9 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
decode_block_0_9_reg <= decode_block_0_9;
if (^reset !== 1'bX && ^(decode_block_0_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_9_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
begin
decode_block_0_10 = DecodeHuffman_return_val;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
decode_block_0_10_reg <= decode_block_0_10;
if (^reset !== 1'bX && ^(decode_block_0_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_0_10_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %0*/
/* %11 = icmp eq i32 %10, 0*/
begin
decode_block_0_11 = decode_block_0_10_reg == 32'd0;
end
end
always @(*) begin
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
begin
decode_block_12_13 = buf_getv_return_val;
end
end
always @(posedge clk) begin
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
decode_block_12_13_reg <= decode_block_12_13;
if (^reset !== 1'bX && ^(decode_block_12_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_12_13_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %12*/
/* %14 = add nsw i32 %10, -1*/
begin
decode_block_12_14 = decode_block_0_10_reg + -32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %12*/
/* %14 = add nsw i32 %10, -1*/
if (cur_state == LEGUP_function_call_10)
begin
decode_block_12_14_reg <= decode_block_12_14;
if (^reset !== 1'bX && ^(decode_block_12_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_12_14_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %12*/
/* %15 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %14*/
begin
decode_block_12_15 = `TAG_g_bit_set_mask_a + 4 * decode_block_12_14;
end
end
always @(posedge clk) begin
/* decode_block: %12*/
/* %15 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %14*/
if (cur_state == LEGUP_function_call_10)
begin
decode_block_12_15_reg <= decode_block_12_15;
if (^reset !== 1'bX && ^(decode_block_12_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_12_15_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %12*/
/* %16 = load i32* %15, align 4, !tbaa !2*/
begin
decode_block_12_16 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %12*/
/* %17 = and i32 %16, %13*/
begin
decode_block_12_17 = decode_block_12_16 & decode_block_12_13_reg;
end
end
always @(*) begin
/* decode_block: %12*/
/* %18 = icmp eq i32 %17, 0*/
begin
decode_block_12_18 = decode_block_12_17 == 32'd0;
end
end
always @(*) begin
/* decode_block: %19*/
/* %20 = getelementptr inbounds [20 x i32]* @extend_mask, i32 0, i32 %14*/
begin
decode_block_19_20 = `TAG_g_extend_mask_a + 4 * decode_block_12_14_reg;
end
end
always @(*) begin
/* decode_block: %19*/
/* %21 = load i32* %20, align 4, !tbaa !2*/
begin
decode_block_19_21 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %19*/
/* %22 = or i32 %21, %13*/
begin
decode_block_19_22 = decode_block_19_21 | decode_block_12_13_reg;
end
end
always @(*) begin
/* decode_block: %19*/
/* %23 = add nsw i32 %22, 1*/
begin
decode_block_19_23 = decode_block_19_22 + 32'd1;
end
end
always @(*) begin
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
decode_block_24_diff_0_i = decode_block_24_diff_0_i_phi_temp;
end
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
else /* if (cur_state == LEGUP_F_decode_block_BB3_17) */
begin
decode_block_24_diff_0_i = decode_block_24_diff_0_i_phi_temp;
end
end
always @(posedge clk) begin
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
decode_block_24_diff_0_i_reg <= decode_block_24_diff_0_i;
if (^reset !== 1'bX && ^(decode_block_24_diff_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_24_diff_0_i_reg"); $finish; end
end
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
decode_block_24_diff_0_i_reg <= decode_block_24_diff_0_i;
if (^reset !== 1'bX && ^(decode_block_24_diff_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_24_diff_0_i_reg"); $finish; end
end
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
decode_block_24_diff_0_i_reg <= decode_block_24_diff_0_i;
if (^reset !== 1'bX && ^(decode_block_24_diff_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_24_diff_0_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %24*/
/* %25 = load i32* %HuffBuff, align 4, !tbaa !2*/
begin
decode_block_24_25 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %24*/
/* %26 = add nsw i32 %25, %diff.0.i*/
begin
decode_block_24_26 = decode_block_24_25 + decode_block_24_diff_0_i_reg;
end
end
always @(*) begin
/* decode_block: %.preheader.i*/
/* %27 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_ac_xhuff_tbl_huffval, i32 0, i32 %3, i32 0*/
begin
decode_block__preheader_i_27 = `TAG_g_p_jinfo_ac_xhuff_tbl_huffval_a + 1028 * decode_block_0_3_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i*/
/* %27 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_ac_xhuff_tbl_huffval, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB4_20)
begin
decode_block__preheader_i_27_reg <= decode_block__preheader_i_27;
if (^reset !== 1'bX && ^(decode_block__preheader_i_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i_27_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i*/
/* %28 = getelementptr inbounds [2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 %3*/
begin
decode_block__preheader_i_28 = `TAG_g_p_jinfo_ac_dhuff_tbl_ml_a + 4 * decode_block_0_3_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i*/
/* %28 = getelementptr inbounds [2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 %3*/
if (cur_state == LEGUP_F_decode_block_BB4_20)
begin
decode_block__preheader_i_28_reg <= decode_block__preheader_i_28;
if (^reset !== 1'bX && ^(decode_block__preheader_i_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i_28_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i*/
/* %29 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 %3, i32 0*/
begin
decode_block__preheader_i_29 = `TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a + 144 * decode_block_0_3_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i*/
/* %29 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB4_20)
begin
decode_block__preheader_i_29_reg <= decode_block__preheader_i_29;
if (^reset !== 1'bX && ^(decode_block__preheader_i_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i_29_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i*/
/* %30 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 %3, i32 0*/
begin
decode_block__preheader_i_30 = `TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a + 144 * decode_block_0_3_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i*/
/* %30 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB4_20)
begin
decode_block__preheader_i_30_reg <= decode_block__preheader_i_30;
if (^reset !== 1'bX && ^(decode_block__preheader_i_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i_30_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i*/
/* %31 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 %3, i32 0*/
begin
decode_block__preheader_i_31 = `TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a + 144 * decode_block_0_3_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i*/
/* %31 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 %3, i32 0*/
if (cur_state == LEGUP_F_decode_block_BB4_20)
begin
decode_block__preheader_i_31_reg <= decode_block__preheader_i_31;
if (^reset !== 1'bX && ^(decode_block__preheader_i_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i_31_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.lr.ph.i*/
/* %indvar.i2 = phi i32 [ %tmp4.i, %.lr.ph.i ], [ 0, %0 ], [ 0, %24 ]*/
begin
decode_block__lr_ph_i_indvar_i2 = decode_block__lr_ph_i_indvar_i2_phi_temp;
end
end
always @(*) begin
/* decode_block: %.lr.ph.i*/
/* %tmp.i4 = add i32 %indvar.i2, 2*/
begin
decode_block__lr_ph_i_tmp_i4 = decode_block__lr_ph_i_indvar_i2 + 32'd2;
end
end
always @(*) begin
/* decode_block: %.lr.ph.i*/
/* %tmp4.i = add i32 %indvar.i2, 1*/
begin
decode_block__lr_ph_i_tmp4_i = decode_block__lr_ph_i_indvar_i2 + 32'd1;
end
end
always @(*) begin
/* decode_block: %.lr.ph.i*/
/* %mptr.03.i = getelementptr i32* %HuffBuff, i32 %tmp4.i*/
begin
decode_block__lr_ph_i_mptr_03_i = arg_HuffBuff + 4 * decode_block__lr_ph_i_tmp4_i;
end
end
always @(*) begin
/* decode_block: %.lr.ph.i*/
/* %32 = icmp slt i32 %tmp.i4, 64*/
begin
decode_block__lr_ph_i_32 = $signed(decode_block__lr_ph_i_tmp_i4) < $signed(32'd64);
end
end
always @(*) begin
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i = decode_block__backedge_i_k_0_i_phi_temp;
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
else if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i = decode_block__backedge_i_k_0_i_phi_temp;
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
else /* if (cur_state == LEGUP_F_decode_block_BB6_22) */
begin
decode_block__backedge_i_k_0_i = decode_block__backedge_i_k_0_i_phi_temp;
end
end
always @(posedge clk) begin
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i_reg <= decode_block__backedge_i_k_0_i;
if (^reset !== 1'bX && ^(decode_block__backedge_i_k_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_reg"); $finish; end
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i_reg <= decode_block__backedge_i_k_0_i;
if (^reset !== 1'bX && ^(decode_block__backedge_i_k_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_reg"); $finish; end
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i_reg <= decode_block__backedge_i_k_0_i;
if (^reset !== 1'bX && ^(decode_block__backedge_i_k_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_reg"); $finish; end
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22)
begin
decode_block__backedge_i_k_0_i_reg <= decode_block__backedge_i_k_0_i;
if (^reset !== 1'bX && ^(decode_block__backedge_i_k_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.backedge.i*/
/* %33 = icmp slt i32 %k.0.i, 64*/
begin
decode_block__backedge_i_33 = $signed(decode_block__backedge_i_k_0_i) < $signed(32'd64);
end
end
always @(*) begin
/* decode_block: %34*/
/* %35 = load i32* %28, align 4, !tbaa !2*/
begin
decode_block_34_35 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
begin
decode_block_34_36 = DecodeHuffman_return_val;
end
end
always @(posedge clk) begin
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
decode_block_34_36_reg <= decode_block_34_36;
if (^reset !== 1'bX && ^(decode_block_34_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_34_36_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %34*/
/* %37 = and i32 %36, 15*/
begin
decode_block_34_37 = decode_block_34_36_reg & 32'd15;
end
end
always @(posedge clk) begin
/* decode_block: %34*/
/* %37 = and i32 %36, 15*/
if (cur_state == LEGUP_function_call_27)
begin
decode_block_34_37_reg <= decode_block_34_37;
if (^reset !== 1'bX && ^(decode_block_34_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_34_37_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %34*/
/* %38 = lshr i32 %36, 4*/
begin
decode_block_34_38 = decode_block_34_36_reg >>> 32'd4 % 32;
end
end
always @(*) begin
/* decode_block: %34*/
/* %39 = and i32 %38, 15*/
begin
decode_block_34_39 = decode_block_34_38 & 32'd15;
end
end
always @(posedge clk) begin
/* decode_block: %34*/
/* %39 = and i32 %38, 15*/
if (cur_state == LEGUP_function_call_27)
begin
decode_block_34_39_reg <= decode_block_34_39;
if (^reset !== 1'bX && ^(decode_block_34_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_34_39_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %34*/
/* %40 = icmp eq i32 %37, 0*/
begin
decode_block_34_40 = decode_block_34_37 == 32'd0;
end
end
always @(*) begin
/* decode_block: %41*/
/* %42 = add nsw i32 %39, %k.0.i*/
begin
decode_block_41_42 = decode_block_34_39_reg + decode_block__backedge_i_k_0_i_reg;
end
end
always @(posedge clk) begin
/* decode_block: %41*/
/* %42 = add nsw i32 %39, %k.0.i*/
if (cur_state == LEGUP_F_decode_block_BB8_28)
begin
decode_block_41_42_reg <= decode_block_41_42;
if (^reset !== 1'bX && ^(decode_block_41_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_41_42_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %41*/
/* %43 = icmp sgt i32 %42, 63*/
begin
decode_block_41_43 = $signed(decode_block_41_42) > $signed(32'd63);
end
end
always @(*) begin
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
begin
decode_block_44_45 = buf_getv_return_val;
end
end
always @(posedge clk) begin
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
decode_block_44_45_reg <= decode_block_44_45;
if (^reset !== 1'bX && ^(decode_block_44_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_44_45_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %44*/
/* %46 = getelementptr inbounds i32* %HuffBuff, i32 %42*/
begin
decode_block_44_46 = arg_HuffBuff + 4 * decode_block_41_42_reg;
end
end
always @(posedge clk) begin
/* decode_block: %44*/
/* %46 = getelementptr inbounds i32* %HuffBuff, i32 %42*/
if (cur_state == LEGUP_function_call_31)
begin
decode_block_44_46_reg <= decode_block_44_46;
if (^reset !== 1'bX && ^(decode_block_44_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_44_46_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %44*/
/* %47 = add nsw i32 %37, -1*/
begin
decode_block_44_47 = decode_block_34_37_reg + -32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %44*/
/* %47 = add nsw i32 %37, -1*/
if (cur_state == LEGUP_function_call_31)
begin
decode_block_44_47_reg <= decode_block_44_47;
if (^reset !== 1'bX && ^(decode_block_44_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_44_47_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %44*/
/* %48 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %47*/
begin
decode_block_44_48 = `TAG_g_bit_set_mask_a + 4 * decode_block_44_47;
end
end
always @(posedge clk) begin
/* decode_block: %44*/
/* %48 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %47*/
if (cur_state == LEGUP_function_call_31)
begin
decode_block_44_48_reg <= decode_block_44_48;
if (^reset !== 1'bX && ^(decode_block_44_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_44_48_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %44*/
/* %49 = load i32* %48, align 4, !tbaa !2*/
begin
decode_block_44_49 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %44*/
/* %50 = and i32 %49, %45*/
begin
decode_block_44_50 = decode_block_44_49 & decode_block_44_45_reg;
end
end
always @(*) begin
/* decode_block: %44*/
/* %51 = icmp eq i32 %50, 0*/
begin
decode_block_44_51 = decode_block_44_50 == 32'd0;
end
end
always @(*) begin
/* decode_block: %52*/
/* %53 = getelementptr inbounds [20 x i32]* @extend_mask, i32 0, i32 %47*/
begin
decode_block_52_53 = `TAG_g_extend_mask_a + 4 * decode_block_44_47_reg;
end
end
always @(*) begin
/* decode_block: %52*/
/* %54 = load i32* %53, align 4, !tbaa !2*/
begin
decode_block_52_54 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %52*/
/* %55 = or i32 %54, %45*/
begin
decode_block_52_55 = decode_block_52_54 | decode_block_44_45_reg;
end
end
always @(*) begin
/* decode_block: %52*/
/* %56 = add nsw i32 %55, 1*/
begin
decode_block_52_56 = decode_block_52_55 + 32'd1;
end
end
always @(*) begin
/* decode_block: %57*/
/* %58 = add nsw i32 %42, 1*/
begin
decode_block_57_58 = decode_block_41_42_reg + 32'd1;
end
end
always @(*) begin
/* decode_block: %59*/
/* %60 = icmp eq i32 %39, 15*/
begin
decode_block_59_60 = decode_block_34_39_reg == 32'd15;
end
end
always @(*) begin
/* decode_block: %61*/
/* %62 = add nsw i32 %k.0.i, 16*/
begin
decode_block_61_62 = decode_block__backedge_i_k_0_i_reg + 32'd16;
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %i.02.i = phi i32 [ %66, %DecodeHuffMCU.exit ], [ 0, %.backedge.i ], [ 0, %41 ], [ 0, %59 ]*/
begin
decode_block_DecodeHuffMCU_exit_i_02_i = decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp;
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %.01.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %i.02.i*/
begin
decode_block_DecodeHuffMCU_exit__01_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_DecodeHuffMCU_exit_i_02_i;
end
end
always @(posedge clk) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %.01.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %i.02.i*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
decode_block_DecodeHuffMCU_exit__01_i_reg <= decode_block_DecodeHuffMCU_exit__01_i;
if (^reset !== 1'bX && ^(decode_block_DecodeHuffMCU_exit__01_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit__01_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %scevgep.i = getelementptr [64 x i32]* @zigzag_index, i32 0, i32 %i.02.i*/
begin
decode_block_DecodeHuffMCU_exit_scevgep_i = `TAG_g_zigzag_index_a + 4 * decode_block_DecodeHuffMCU_exit_i_02_i;
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %63 = load i32* %scevgep.i, align 4, !tbaa !2*/
begin
decode_block_DecodeHuffMCU_exit_63 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %64 = getelementptr inbounds i32* %HuffBuff, i32 %63*/
begin
decode_block_DecodeHuffMCU_exit_64 = arg_HuffBuff + 4 * decode_block_DecodeHuffMCU_exit_63;
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %65 = load i32* %64, align 4, !tbaa !2*/
begin
decode_block_DecodeHuffMCU_exit_65 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %66 = add nsw i32 %i.02.i, 1*/
begin
decode_block_DecodeHuffMCU_exit_66 = decode_block_DecodeHuffMCU_exit_i_02_i + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %66 = add nsw i32 %i.02.i, 1*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
decode_block_DecodeHuffMCU_exit_66_reg <= decode_block_DecodeHuffMCU_exit_66;
if (^reset !== 1'bX && ^(decode_block_DecodeHuffMCU_exit_66) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_66_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %exitcond10 = icmp eq i32 %66, 64*/
begin
decode_block_DecodeHuffMCU_exit_exitcond10 = decode_block_DecodeHuffMCU_exit_66 == 32'd64;
end
end
always @(posedge clk) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %exitcond10 = icmp eq i32 %66, 64*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
decode_block_DecodeHuffMCU_exit_exitcond10_reg <= decode_block_DecodeHuffMCU_exit_exitcond10;
if (^reset !== 1'bX && ^(decode_block_DecodeHuffMCU_exit_exitcond10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_exitcond10_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IZigzagMatrix.exit*/
/* %67 = getelementptr inbounds [3 x i8]* @p_jinfo_comps_info_quant_tbl_no, i32 0, i32 %comp_no*/
begin
decode_block_IZigzagMatrix_exit_67 = `TAG_g_p_jinfo_comps_info_quant_tbl_no_a + 1 * arg_comp_no;
end
end
always @(*) begin
/* decode_block: %IZigzagMatrix.exit*/
/* %68 = load i8* %67, align 1, !tbaa !0*/
begin
decode_block_IZigzagMatrix_exit_68 = memory_controller_out[7:0];
end
end
always @(*) begin
/* decode_block: %IZigzagMatrix.exit*/
/* %tmp = sext i8 %68 to i32*/
begin
decode_block_IZigzagMatrix_exit_tmp = $signed(decode_block_IZigzagMatrix_exit_68);
end
end
always @(*) begin
/* decode_block: %IZigzagMatrix.exit*/
/* %tmp9 = add i32 %tmp, 1*/
begin
decode_block_IZigzagMatrix_exit_tmp9 = decode_block_IZigzagMatrix_exit_tmp + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %IZigzagMatrix.exit*/
/* %tmp9 = add i32 %tmp, 1*/
if (cur_state == LEGUP_F_decode_block_BB15_49)
begin
decode_block_IZigzagMatrix_exit_tmp9_reg <= decode_block_IZigzagMatrix_exit_tmp9;
if (^reset !== 1'bX && ^(decode_block_IZigzagMatrix_exit_tmp9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IZigzagMatrix_exit_tmp9_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %69*/
/* %indvar.i4 = phi i32 [ 0, %IZigzagMatrix.exit ], [ %tmp.i5, %69 ]*/
begin
decode_block_69_indvar_i4 = decode_block_69_indvar_i4_phi_temp;
end
end
always @(*) begin
/* decode_block: %69*/
/* %.01.i6 = getelementptr [4 x [64 x i32]]* @p_jinfo_quant_tbl_quantval, i32 0, i32 %tmp9, i32 %indvar.i4*/
begin
decode_block_69__01_i6 = `TAG_g_p_jinfo_quant_tbl_quantval_a + 256 * decode_block_IZigzagMatrix_exit_tmp9_reg + 4 * decode_block_69_indvar_i4;
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %.01.i6 = getelementptr [4 x [64 x i32]]* @p_jinfo_quant_tbl_quantval, i32 0, i32 %tmp9, i32 %indvar.i4*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
decode_block_69__01_i6_reg <= decode_block_69__01_i6;
if (^reset !== 1'bX && ^(decode_block_69__01_i6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69__01_i6_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %69*/
/* %mptr.02.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %indvar.i4*/
begin
decode_block_69_mptr_02_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_69_indvar_i4;
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %mptr.02.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %indvar.i4*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
decode_block_69_mptr_02_i_reg <= decode_block_69_mptr_02_i;
if (^reset !== 1'bX && ^(decode_block_69_mptr_02_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_mptr_02_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %69*/
/* %tmp.i5 = add i32 %indvar.i4, 1*/
begin
decode_block_69_tmp_i5 = decode_block_69_indvar_i4 + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %tmp.i5 = add i32 %indvar.i4, 1*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
decode_block_69_tmp_i5_reg <= decode_block_69_tmp_i5;
if (^reset !== 1'bX && ^(decode_block_69_tmp_i5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_tmp_i5_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
begin
decode_block_69_70 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_52)
begin
decode_block_69_70_reg <= decode_block_69_70;
if (^reset !== 1'bX && ^(decode_block_69_70) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_70_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %69*/
/* %71 = load i32* %.01.i6, align 4, !tbaa !2*/
begin
decode_block_69_71 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %69*/
/* %72 = mul nsw i32 %71, %70*/
begin
decode_block_69_72 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %69*/
/* %exitcond8 = icmp eq i32 %tmp.i5, 64*/
begin
decode_block_69_exitcond8 = decode_block_69_tmp_i5 == 32'd64;
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %exitcond8 = icmp eq i32 %tmp.i5, 64*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
decode_block_69_exitcond8_reg <= decode_block_69_exitcond8;
if (^reset !== 1'bX && ^(decode_block_69_exitcond8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_exitcond8_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %i.027.i = phi i32 [ %135, %IQuantize.exit ], [ 0, %69 ]*/
begin
decode_block_IQuantize_exit_i_027_i = decode_block_IQuantize_exit_i_027_i_phi_temp;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep44.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %i.027.i*/
begin
decode_block_IQuantize_exit_scevgep44_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_i_027_i;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep45.i = getelementptr i32* %out_buf, i32 %i.027.i*/
begin
decode_block_IQuantize_exit_scevgep45_i = arg_out_buf + 4 * decode_block_IQuantize_exit_i_027_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep45.i = getelementptr i32* %out_buf, i32 %i.027.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep45_i_reg <= decode_block_IQuantize_exit_scevgep45_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep45_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep45_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp46.i = add i32 %i.027.i, 8*/
begin
decode_block_IQuantize_exit_tmp46_i = decode_block_IQuantize_exit_i_027_i + 32'd8;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep47.i = getelementptr i32* %out_buf, i32 %tmp46.i*/
begin
decode_block_IQuantize_exit_scevgep47_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp46_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep47.i = getelementptr i32* %out_buf, i32 %tmp46.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep47_i_reg <= decode_block_IQuantize_exit_scevgep47_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep47_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep47_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep48.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp46.i*/
begin
decode_block_IQuantize_exit_scevgep48_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp46_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep48.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp46.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep48_i_reg <= decode_block_IQuantize_exit_scevgep48_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep48_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep48_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp49.i = add i32 %i.027.i, 16*/
begin
decode_block_IQuantize_exit_tmp49_i = decode_block_IQuantize_exit_i_027_i + 32'd16;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep50.i = getelementptr i32* %out_buf, i32 %tmp49.i*/
begin
decode_block_IQuantize_exit_scevgep50_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp49_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep50.i = getelementptr i32* %out_buf, i32 %tmp49.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep50_i_reg <= decode_block_IQuantize_exit_scevgep50_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep50_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep50_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep51.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp49.i*/
begin
decode_block_IQuantize_exit_scevgep51_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp49_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep51.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp49.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep51_i_reg <= decode_block_IQuantize_exit_scevgep51_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep51_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep51_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp52.i = add i32 %i.027.i, 24*/
begin
decode_block_IQuantize_exit_tmp52_i = decode_block_IQuantize_exit_i_027_i + 32'd24;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep53.i = getelementptr i32* %out_buf, i32 %tmp52.i*/
begin
decode_block_IQuantize_exit_scevgep53_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp52_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep53.i = getelementptr i32* %out_buf, i32 %tmp52.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep53_i_reg <= decode_block_IQuantize_exit_scevgep53_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep53_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep53_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep54.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp52.i*/
begin
decode_block_IQuantize_exit_scevgep54_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp52_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep54.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp52.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep54_i_reg <= decode_block_IQuantize_exit_scevgep54_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep54_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep54_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp55.i = add i32 %i.027.i, 32*/
begin
decode_block_IQuantize_exit_tmp55_i = decode_block_IQuantize_exit_i_027_i + 32'd32;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep56.i = getelementptr i32* %out_buf, i32 %tmp55.i*/
begin
decode_block_IQuantize_exit_scevgep56_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp55_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep56.i = getelementptr i32* %out_buf, i32 %tmp55.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep56_i_reg <= decode_block_IQuantize_exit_scevgep56_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep56_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep56_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep57.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp55.i*/
begin
decode_block_IQuantize_exit_scevgep57_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp55_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep57.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp55.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep57_i_reg <= decode_block_IQuantize_exit_scevgep57_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep57_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep57_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp58.i = add i32 %i.027.i, 40*/
begin
decode_block_IQuantize_exit_tmp58_i = decode_block_IQuantize_exit_i_027_i + 32'd40;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep59.i = getelementptr i32* %out_buf, i32 %tmp58.i*/
begin
decode_block_IQuantize_exit_scevgep59_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp58_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep59.i = getelementptr i32* %out_buf, i32 %tmp58.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep59_i_reg <= decode_block_IQuantize_exit_scevgep59_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep59_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep59_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep60.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp58.i*/
begin
decode_block_IQuantize_exit_scevgep60_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp58_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep60.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp58.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep60_i_reg <= decode_block_IQuantize_exit_scevgep60_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep60_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep60_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp61.i = add i32 %i.027.i, 48*/
begin
decode_block_IQuantize_exit_tmp61_i = decode_block_IQuantize_exit_i_027_i + 32'd48;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep62.i = getelementptr i32* %out_buf, i32 %tmp61.i*/
begin
decode_block_IQuantize_exit_scevgep62_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp61_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep62.i = getelementptr i32* %out_buf, i32 %tmp61.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep62_i_reg <= decode_block_IQuantize_exit_scevgep62_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep62_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep62_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep63.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp61.i*/
begin
decode_block_IQuantize_exit_scevgep63_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp61_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep63.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp61.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep63_i_reg <= decode_block_IQuantize_exit_scevgep63_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep63_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep63_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %tmp64.i = add i32 %i.027.i, 56*/
begin
decode_block_IQuantize_exit_tmp64_i = decode_block_IQuantize_exit_i_027_i + 32'd56;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep65.i = getelementptr i32* %out_buf, i32 %tmp64.i*/
begin
decode_block_IQuantize_exit_scevgep65_i = arg_out_buf + 4 * decode_block_IQuantize_exit_tmp64_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep65.i = getelementptr i32* %out_buf, i32 %tmp64.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep65_i_reg <= decode_block_IQuantize_exit_scevgep65_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep65_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep65_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep66.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp64.i*/
begin
decode_block_IQuantize_exit_scevgep66_i = `TAG_decode_block_0_QuantBuff_a + 4 * decode_block_IQuantize_exit_tmp64_i;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %scevgep66.i = getelementptr [64 x i32]* %QuantBuff, i32 0, i32 %tmp64.i*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_scevgep66_i_reg <= decode_block_IQuantize_exit_scevgep66_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_scevgep66_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_scevgep66_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %73 = load i32* %scevgep44.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_73 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %74 = shl i32 %73, 2*/
begin
decode_block_IQuantize_exit_74 = decode_block_IQuantize_exit_73 <<< 32'd2 % 32;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %74 = shl i32 %73, 2*/
if (cur_state == LEGUP_F_decode_block_BB17_56)
begin
decode_block_IQuantize_exit_74_reg <= decode_block_IQuantize_exit_74;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_74) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_74_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %75 = load i32* %scevgep48.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_75 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %76 = load i32* %scevgep51.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_76 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %77 = load i32* %scevgep54.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_77 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %78 = load i32* %scevgep57.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_78 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %79 = shl i32 %78, 2*/
begin
decode_block_IQuantize_exit_79 = decode_block_IQuantize_exit_78 <<< 32'd2 % 32;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %80 = load i32* %scevgep60.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_80 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %81 = load i32* %scevgep63.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_81 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %82 = load i32* %scevgep66.i, align 4, !tbaa !2*/
begin
decode_block_IQuantize_exit_82 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %83 = mul i32 %75, 400*/
begin
decode_block_IQuantize_exit_83 = decode_block_signed_multiply_32_1;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %83 = mul i32 %75, 400*/
decode_block_IQuantize_exit_83_reg = decode_block__preheader25_i_144_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %84 = mul i32 %82, -2008*/
begin
decode_block_IQuantize_exit_84 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %85 = add i32 %84, %83*/
begin
decode_block_IQuantize_exit_85 = decode_block_IQuantize_exit_84 + decode_block_IQuantize_exit_83_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %86 = ashr i32 %85, 9*/
begin
decode_block_IQuantize_exit_86 = $signed(decode_block_IQuantize_exit_85) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %86 = ashr i32 %85, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_86_reg <= decode_block_IQuantize_exit_86;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_86) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_86_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %87 = mul i32 %80, 1704*/
begin
decode_block_IQuantize_exit_87 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %88 = mul i32 %77, -1136*/
begin
decode_block_IQuantize_exit_88 = decode_block_signed_multiply_32_1;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %88 = mul i32 %77, -1136*/
decode_block_IQuantize_exit_88_reg = decode_block__preheader25_i_149_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %89 = add i32 %87, %88*/
begin
decode_block_IQuantize_exit_89 = decode_block_IQuantize_exit_87 + decode_block_IQuantize_exit_88_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %90 = ashr i32 %89, 9*/
begin
decode_block_IQuantize_exit_90 = $signed(decode_block_IQuantize_exit_89) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %90 = ashr i32 %89, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_IQuantize_exit_90_reg <= decode_block_IQuantize_exit_90;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_90_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %91 = mul i32 %77, 1704*/
begin
decode_block_IQuantize_exit_91 = decode_block_signed_multiply_32_3;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %91 = mul i32 %77, 1704*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block_IQuantize_exit_91_reg <= decode_block_IQuantize_exit_91;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_91) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_91_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %92 = mul i32 %80, 1136*/
begin
decode_block_IQuantize_exit_92 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %93 = add nsw i32 %92, %91*/
begin
decode_block_IQuantize_exit_93 = decode_block_IQuantize_exit_92 + decode_block_IQuantize_exit_91_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %94 = ashr i32 %93, 9*/
begin
decode_block_IQuantize_exit_94 = $signed(decode_block_IQuantize_exit_93) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %94 = ashr i32 %93, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_IQuantize_exit_94_reg <= decode_block_IQuantize_exit_94;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_94) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_94_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %95 = mul i32 %75, 2008*/
begin
decode_block_IQuantize_exit_95 = decode_block_signed_multiply_32_2;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %95 = mul i32 %75, 2008*/
decode_block_IQuantize_exit_95_reg = decode_block__preheader25_i_152_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %96 = mul i32 %82, 400*/
begin
decode_block_IQuantize_exit_96 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %97 = add nsw i32 %96, %95*/
begin
decode_block_IQuantize_exit_97 = decode_block_IQuantize_exit_96 + decode_block_IQuantize_exit_95_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %98 = ashr i32 %97, 9*/
begin
decode_block_IQuantize_exit_98 = $signed(decode_block_IQuantize_exit_97) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %98 = ashr i32 %97, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_98_reg <= decode_block_IQuantize_exit_98;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_98_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %99 = add nsw i32 %79, %74*/
begin
decode_block_IQuantize_exit_99 = decode_block_IQuantize_exit_79 + decode_block_IQuantize_exit_74_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %100 = mul nsw i32 %99, 362*/
begin
decode_block_IQuantize_exit_100 = decode_block_signed_multiply_32_0;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %100 = mul nsw i32 %99, 362*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block_IQuantize_exit_100_reg <= decode_block_IQuantize_exit_100;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_100_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %101 = ashr i32 %100, 9*/
begin
decode_block_IQuantize_exit_101 = $signed(decode_block_IQuantize_exit_100_reg) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %101 = ashr i32 %100, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_IQuantize_exit_101_reg <= decode_block_IQuantize_exit_101;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_101_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %102 = sub nsw i32 %74, %79*/
begin
decode_block_IQuantize_exit_102 = decode_block_IQuantize_exit_74_reg - decode_block_IQuantize_exit_79;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %103 = mul nsw i32 %102, 362*/
begin
decode_block_IQuantize_exit_103 = decode_block_signed_multiply_32_1;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %103 = mul nsw i32 %102, 362*/
decode_block_IQuantize_exit_103_reg = decode_block__preheader25_i_166_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %104 = ashr i32 %103, 9*/
begin
decode_block_IQuantize_exit_104 = $signed(decode_block_IQuantize_exit_103_reg) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %104 = ashr i32 %103, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_IQuantize_exit_104_reg <= decode_block_IQuantize_exit_104;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_104_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %105 = mul i32 %76, 784*/
begin
decode_block_IQuantize_exit_105 = decode_block_signed_multiply_32_3;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %105 = mul i32 %76, 784*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block_IQuantize_exit_105_reg <= decode_block_IQuantize_exit_105;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_105_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %106 = mul i32 %81, -1892*/
begin
decode_block_IQuantize_exit_106 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %107 = add i32 %106, %105*/
begin
decode_block_IQuantize_exit_107 = decode_block_IQuantize_exit_106 + decode_block_IQuantize_exit_105_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %108 = ashr i32 %107, 9*/
begin
decode_block_IQuantize_exit_108 = $signed(decode_block_IQuantize_exit_107) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %108 = ashr i32 %107, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_IQuantize_exit_108_reg <= decode_block_IQuantize_exit_108;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_108) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_108_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %109 = mul i32 %76, 1892*/
begin
decode_block_IQuantize_exit_109 = decode_block_signed_multiply_32_2;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %109 = mul i32 %76, 1892*/
decode_block_IQuantize_exit_109_reg = decode_block__preheader25_i_156_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %110 = mul i32 %81, 784*/
begin
decode_block_IQuantize_exit_110 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %111 = add nsw i32 %110, %109*/
begin
decode_block_IQuantize_exit_111 = decode_block_IQuantize_exit_110 + decode_block_IQuantize_exit_109_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %112 = ashr i32 %111, 9*/
begin
decode_block_IQuantize_exit_112 = $signed(decode_block_IQuantize_exit_111) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %112 = ashr i32 %111, 9*/
if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_IQuantize_exit_112_reg <= decode_block_IQuantize_exit_112;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_112_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %113 = add nsw i32 %112, %101*/
begin
decode_block_IQuantize_exit_113 = decode_block_IQuantize_exit_112_reg + decode_block_IQuantize_exit_101_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %113 = add nsw i32 %112, %101*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_113_reg <= decode_block_IQuantize_exit_113;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_113) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_113_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %114 = add nsw i32 %108, %104*/
begin
decode_block_IQuantize_exit_114 = decode_block_IQuantize_exit_108_reg + decode_block_IQuantize_exit_104_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %114 = add nsw i32 %108, %104*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_114_reg <= decode_block_IQuantize_exit_114;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_114_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %115 = sub nsw i32 %104, %108*/
begin
decode_block_IQuantize_exit_115 = decode_block_IQuantize_exit_104_reg - decode_block_IQuantize_exit_108_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %115 = sub nsw i32 %104, %108*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_115_reg <= decode_block_IQuantize_exit_115;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_115) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_115_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %116 = sub nsw i32 %101, %112*/
begin
decode_block_IQuantize_exit_116 = decode_block_IQuantize_exit_101_reg - decode_block_IQuantize_exit_112_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %116 = sub nsw i32 %101, %112*/
if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_IQuantize_exit_116_reg <= decode_block_IQuantize_exit_116;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_116_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %117 = add nsw i32 %86, %90*/
begin
decode_block_IQuantize_exit_117 = decode_block_IQuantize_exit_86_reg + decode_block_IQuantize_exit_90_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %118 = sub nsw i32 %86, %90*/
begin
decode_block_IQuantize_exit_118 = decode_block_IQuantize_exit_86_reg - decode_block_IQuantize_exit_90_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %119 = sub nsw i32 %98, %94*/
begin
decode_block_IQuantize_exit_119 = decode_block_IQuantize_exit_98_reg - decode_block_IQuantize_exit_94_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %120 = add nsw i32 %98, %94*/
begin
decode_block_IQuantize_exit_120 = decode_block_IQuantize_exit_98_reg + decode_block_IQuantize_exit_94_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %121 = sub nsw i32 %119, %118*/
begin
decode_block_IQuantize_exit_121 = decode_block_IQuantize_exit_119 - decode_block_IQuantize_exit_118;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %122 = mul nsw i32 %121, 362*/
begin
decode_block_IQuantize_exit_122 = decode_block_signed_multiply_32_1;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %122 = mul nsw i32 %121, 362*/
decode_block_IQuantize_exit_122_reg = decode_block__preheader25_i_144_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %123 = ashr i32 %122, 9*/
begin
decode_block_IQuantize_exit_123 = $signed(decode_block_IQuantize_exit_122_reg) >>> 32'd9;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %124 = add nsw i32 %119, %118*/
begin
decode_block_IQuantize_exit_124 = decode_block_IQuantize_exit_119 + decode_block_IQuantize_exit_118;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %125 = mul nsw i32 %124, 362*/
begin
decode_block_IQuantize_exit_125 = decode_block_signed_multiply_32_2;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %125 = mul nsw i32 %124, 362*/
decode_block_IQuantize_exit_125_reg = decode_block__preheader25_i_152_reg;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %126 = ashr i32 %125, 9*/
begin
decode_block_IQuantize_exit_126 = $signed(decode_block_IQuantize_exit_125_reg) >>> 32'd9;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %127 = add nsw i32 %120, %113*/
begin
decode_block_IQuantize_exit_127 = decode_block_IQuantize_exit_120 + decode_block_IQuantize_exit_113_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %128 = add nsw i32 %126, %114*/
begin
decode_block_IQuantize_exit_128 = decode_block_IQuantize_exit_126 + decode_block_IQuantize_exit_114_reg;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %129 = add nsw i32 %123, %115*/
begin
decode_block_IQuantize_exit_129 = decode_block_IQuantize_exit_123 + decode_block_IQuantize_exit_115_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %129 = add nsw i32 %123, %115*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
decode_block_IQuantize_exit_129_reg <= decode_block_IQuantize_exit_129;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_129_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %130 = add nsw i32 %117, %116*/
begin
decode_block_IQuantize_exit_130 = decode_block_IQuantize_exit_117 + decode_block_IQuantize_exit_116_reg;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %130 = add nsw i32 %117, %116*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_IQuantize_exit_130_reg <= decode_block_IQuantize_exit_130;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_130_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %131 = sub nsw i32 %116, %117*/
begin
decode_block_IQuantize_exit_131 = decode_block_IQuantize_exit_116_reg - decode_block_IQuantize_exit_117;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %131 = sub nsw i32 %116, %117*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_IQuantize_exit_131_reg <= decode_block_IQuantize_exit_131;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_131_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %132 = sub nsw i32 %115, %123*/
begin
decode_block_IQuantize_exit_132 = decode_block_IQuantize_exit_115_reg - decode_block_IQuantize_exit_123;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %132 = sub nsw i32 %115, %123*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
decode_block_IQuantize_exit_132_reg <= decode_block_IQuantize_exit_132;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_132_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %133 = sub nsw i32 %114, %126*/
begin
decode_block_IQuantize_exit_133 = decode_block_IQuantize_exit_114_reg - decode_block_IQuantize_exit_126;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %133 = sub nsw i32 %114, %126*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
decode_block_IQuantize_exit_133_reg <= decode_block_IQuantize_exit_133;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_133_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %134 = sub nsw i32 %113, %120*/
begin
decode_block_IQuantize_exit_134 = decode_block_IQuantize_exit_113_reg - decode_block_IQuantize_exit_120;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %134 = sub nsw i32 %113, %120*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_IQuantize_exit_134_reg <= decode_block_IQuantize_exit_134;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_134_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %135 = add nsw i32 %i.027.i, 1*/
begin
decode_block_IQuantize_exit_135 = decode_block_IQuantize_exit_i_027_i + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %135 = add nsw i32 %i.027.i, 1*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_135_reg <= decode_block_IQuantize_exit_135;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_135_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %exitcond43.i = icmp eq i32 %135, 8*/
begin
decode_block_IQuantize_exit_exitcond43_i = decode_block_IQuantize_exit_135 == 32'd8;
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %exitcond43.i = icmp eq i32 %135, 8*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
decode_block_IQuantize_exit_exitcond43_i_reg <= decode_block_IQuantize_exit_exitcond43_i;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_exitcond43_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_exitcond43_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %i.126.i = phi i32 [ %196, %.preheader25.i ], [ 0, %IQuantize.exit ]*/
begin
decode_block__preheader25_i_i_126_i = decode_block__preheader25_i_i_126_i_phi_temp;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp.i6 = shl i32 %i.126.i, 3*/
begin
decode_block__preheader25_i_tmp_i6 = decode_block__preheader25_i_i_126_i <<< 32'd3 % 32;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp2967.i = or i32 %tmp.i6, 7*/
begin
decode_block__preheader25_i_tmp2967_i = decode_block__preheader25_i_tmp_i6 | 32'd7;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep.i7 = getelementptr i32* %out_buf, i32 %tmp2967.i*/
begin
decode_block__preheader25_i_scevgep_i7 = arg_out_buf + 4 * decode_block__preheader25_i_tmp2967_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep.i7 = getelementptr i32* %out_buf, i32 %tmp2967.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep_i7_reg <= decode_block__preheader25_i_scevgep_i7;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep_i7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep_i7_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp3068.i = or i32 %tmp.i6, 6*/
begin
decode_block__preheader25_i_tmp3068_i = decode_block__preheader25_i_tmp_i6 | 32'd6;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep31.i = getelementptr i32* %out_buf, i32 %tmp3068.i*/
begin
decode_block__preheader25_i_scevgep31_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp3068_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep31.i = getelementptr i32* %out_buf, i32 %tmp3068.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep31_i_reg <= decode_block__preheader25_i_scevgep31_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep31_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep31_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp3269.i = or i32 %tmp.i6, 5*/
begin
decode_block__preheader25_i_tmp3269_i = decode_block__preheader25_i_tmp_i6 | 32'd5;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep33.i = getelementptr i32* %out_buf, i32 %tmp3269.i*/
begin
decode_block__preheader25_i_scevgep33_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp3269_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep33.i = getelementptr i32* %out_buf, i32 %tmp3269.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep33_i_reg <= decode_block__preheader25_i_scevgep33_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep33_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep33_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp3470.i = or i32 %tmp.i6, 4*/
begin
decode_block__preheader25_i_tmp3470_i = decode_block__preheader25_i_tmp_i6 | 32'd4;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep35.i = getelementptr i32* %out_buf, i32 %tmp3470.i*/
begin
decode_block__preheader25_i_scevgep35_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp3470_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep35.i = getelementptr i32* %out_buf, i32 %tmp3470.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep35_i_reg <= decode_block__preheader25_i_scevgep35_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep35_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep35_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp3671.i = or i32 %tmp.i6, 3*/
begin
decode_block__preheader25_i_tmp3671_i = decode_block__preheader25_i_tmp_i6 | 32'd3;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep37.i = getelementptr i32* %out_buf, i32 %tmp3671.i*/
begin
decode_block__preheader25_i_scevgep37_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp3671_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep37.i = getelementptr i32* %out_buf, i32 %tmp3671.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep37_i_reg <= decode_block__preheader25_i_scevgep37_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep37_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep37_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp3872.i = or i32 %tmp.i6, 2*/
begin
decode_block__preheader25_i_tmp3872_i = decode_block__preheader25_i_tmp_i6 | 32'd2;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep39.i = getelementptr i32* %out_buf, i32 %tmp3872.i*/
begin
decode_block__preheader25_i_scevgep39_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp3872_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep39.i = getelementptr i32* %out_buf, i32 %tmp3872.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep39_i_reg <= decode_block__preheader25_i_scevgep39_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep39_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep39_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %tmp4073.i = or i32 %tmp.i6, 1*/
begin
decode_block__preheader25_i_tmp4073_i = decode_block__preheader25_i_tmp_i6 | 32'd1;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep41.i = getelementptr i32* %out_buf, i32 %tmp4073.i*/
begin
decode_block__preheader25_i_scevgep41_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp4073_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep41.i = getelementptr i32* %out_buf, i32 %tmp4073.i*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep41_i_reg <= decode_block__preheader25_i_scevgep41_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep41_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep41_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %scevgep42.i = getelementptr i32* %out_buf, i32 %tmp.i6*/
begin
decode_block__preheader25_i_scevgep42_i = arg_out_buf + 4 * decode_block__preheader25_i_tmp_i6;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %scevgep42.i = getelementptr i32* %out_buf, i32 %tmp.i6*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_scevgep42_i_reg <= decode_block__preheader25_i_scevgep42_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_scevgep42_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_scevgep42_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_136 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_74)
begin
decode_block__preheader25_i_136_reg <= decode_block__preheader25_i_136;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_136_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %137 = load i32* %scevgep41.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_137 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %138 = load i32* %scevgep39.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_138 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %139 = load i32* %scevgep37.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_139 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %140 = load i32* %scevgep35.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_140 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %141 = load i32* %scevgep33.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_141 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %142 = load i32* %scevgep31.i, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_142 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %143 = load i32* %scevgep.i7, align 4, !tbaa !2*/
begin
decode_block__preheader25_i_143 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %144 = mul nsw i32 %137, 100*/
begin
decode_block__preheader25_i_144 = decode_block_signed_multiply_32_1;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %144 = mul nsw i32 %137, 100*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block__preheader25_i_144_reg <= decode_block__preheader25_i_144;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_144_reg"); $finish; end
end
/* decode_block: %.preheader25.i*/
/* %183 = mul nsw i32 %182, 362*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
decode_block__preheader25_i_144_reg <= decode_block__preheader25_i_183;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_183) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_144_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %83 = mul i32 %75, 400*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block__preheader25_i_144_reg <= decode_block_IQuantize_exit_83;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_83) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_144_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %122 = mul nsw i32 %121, 362*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block__preheader25_i_144_reg <= decode_block_IQuantize_exit_122;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_144_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %145 = mul i32 %143, -502*/
begin
decode_block__preheader25_i_145 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %146 = add i32 %145, %144*/
begin
decode_block__preheader25_i_146 = decode_block__preheader25_i_145 + decode_block__preheader25_i_144_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %147 = ashr i32 %146, 9*/
begin
decode_block__preheader25_i_147 = $signed(decode_block__preheader25_i_146) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %147 = ashr i32 %146, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_147_reg <= decode_block__preheader25_i_147;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_147_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %148 = mul nsw i32 %141, 426*/
begin
decode_block__preheader25_i_148 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %149 = mul i32 %139, -284*/
begin
decode_block__preheader25_i_149 = decode_block_signed_multiply_32_1;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %149 = mul i32 %139, -284*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block__preheader25_i_149_reg <= decode_block__preheader25_i_149;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_149) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_149_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %88 = mul i32 %77, -1136*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block__preheader25_i_149_reg <= decode_block_IQuantize_exit_88;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_88) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_149_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %150 = add i32 %148, %149*/
begin
decode_block__preheader25_i_150 = decode_block__preheader25_i_148 + decode_block__preheader25_i_149_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %151 = ashr i32 %150, 9*/
begin
decode_block__preheader25_i_151 = $signed(decode_block__preheader25_i_150) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %151 = ashr i32 %150, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block__preheader25_i_151_reg <= decode_block__preheader25_i_151;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_151_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %152 = mul nsw i32 %139, 426*/
begin
decode_block__preheader25_i_152 = decode_block_signed_multiply_32_2;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %152 = mul nsw i32 %139, 426*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block__preheader25_i_152_reg <= decode_block__preheader25_i_152;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_152) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_152_reg"); $finish; end
end
/* decode_block: %.preheader25.i*/
/* %186 = mul nsw i32 %185, 362*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
decode_block__preheader25_i_152_reg <= decode_block__preheader25_i_186;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_186) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_152_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %95 = mul i32 %75, 2008*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block__preheader25_i_152_reg <= decode_block_IQuantize_exit_95;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_95) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_152_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %125 = mul nsw i32 %124, 362*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block__preheader25_i_152_reg <= decode_block_IQuantize_exit_125;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_125) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_152_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %153 = mul nsw i32 %141, 284*/
begin
decode_block__preheader25_i_153 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %154 = add nsw i32 %153, %152*/
begin
decode_block__preheader25_i_154 = decode_block__preheader25_i_153 + decode_block__preheader25_i_152_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %155 = ashr i32 %154, 9*/
begin
decode_block__preheader25_i_155 = $signed(decode_block__preheader25_i_154) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %155 = ashr i32 %154, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block__preheader25_i_155_reg <= decode_block__preheader25_i_155;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_155) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_155_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %156 = mul nsw i32 %137, 502*/
begin
decode_block__preheader25_i_156 = decode_block_signed_multiply_32_2;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %156 = mul nsw i32 %137, 502*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block__preheader25_i_156_reg <= decode_block__preheader25_i_156;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_156) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_156_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %109 = mul i32 %76, 1892*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block__preheader25_i_156_reg <= decode_block_IQuantize_exit_109;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_156_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %157 = mul nsw i32 %143, 100*/
begin
decode_block__preheader25_i_157 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %158 = add nsw i32 %157, %156*/
begin
decode_block__preheader25_i_158 = decode_block__preheader25_i_157 + decode_block__preheader25_i_156_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %159 = ashr i32 %158, 9*/
begin
decode_block__preheader25_i_159 = $signed(decode_block__preheader25_i_158) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %159 = ashr i32 %158, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_159_reg <= decode_block__preheader25_i_159;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_159) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_159_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %160 = add nsw i32 %140, %136*/
begin
decode_block__preheader25_i_160 = decode_block__preheader25_i_140 + decode_block__preheader25_i_136_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %161 = mul nsw i32 %160, 362*/
begin
decode_block__preheader25_i_161 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %162 = ashr i32 %161, 9*/
begin
decode_block__preheader25_i_162 = $signed(decode_block__preheader25_i_161) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %162 = ashr i32 %161, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block__preheader25_i_162_reg <= decode_block__preheader25_i_162;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_162) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_162_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %163 = sub nsw i32 %136, %140*/
begin
decode_block__preheader25_i_163 = decode_block__preheader25_i_136_reg - decode_block__preheader25_i_140;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %164 = mul nsw i32 %163, 362*/
begin
decode_block__preheader25_i_164 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %165 = ashr i32 %164, 9*/
begin
decode_block__preheader25_i_165 = $signed(decode_block__preheader25_i_164) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %165 = ashr i32 %164, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block__preheader25_i_165_reg <= decode_block__preheader25_i_165;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_165) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_165_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %166 = mul nsw i32 %138, 196*/
begin
decode_block__preheader25_i_166 = decode_block_signed_multiply_32_1;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %166 = mul nsw i32 %138, 196*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block__preheader25_i_166_reg <= decode_block__preheader25_i_166;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_166) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_166_reg"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %103 = mul nsw i32 %102, 362*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block__preheader25_i_166_reg <= decode_block_IQuantize_exit_103;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_166_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %167 = mul i32 %142, -473*/
begin
decode_block__preheader25_i_167 = decode_block_signed_multiply_32_0;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %168 = add i32 %167, %166*/
begin
decode_block__preheader25_i_168 = decode_block__preheader25_i_167 + decode_block__preheader25_i_166_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %169 = ashr i32 %168, 9*/
begin
decode_block__preheader25_i_169 = $signed(decode_block__preheader25_i_168) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %169 = ashr i32 %168, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block__preheader25_i_169_reg <= decode_block__preheader25_i_169;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_169) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_169_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %170 = mul nsw i32 %138, 473*/
begin
decode_block__preheader25_i_170 = decode_block_signed_multiply_32_2;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %170 = mul nsw i32 %138, 473*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block__preheader25_i_170_reg <= decode_block__preheader25_i_170;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_170) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_170_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %171 = mul nsw i32 %142, 196*/
begin
decode_block__preheader25_i_171 = decode_block_signed_multiply_32_3;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %172 = add nsw i32 %171, %170*/
begin
decode_block__preheader25_i_172 = decode_block__preheader25_i_171 + decode_block__preheader25_i_170_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %173 = ashr i32 %172, 9*/
begin
decode_block__preheader25_i_173 = $signed(decode_block__preheader25_i_172) >>> 32'd9;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %173 = ashr i32 %172, 9*/
if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block__preheader25_i_173_reg <= decode_block__preheader25_i_173;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_173) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_173_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %174 = add nsw i32 %173, %162*/
begin
decode_block__preheader25_i_174 = decode_block__preheader25_i_173_reg + decode_block__preheader25_i_162_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %174 = add nsw i32 %173, %162*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_174_reg <= decode_block__preheader25_i_174;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_174) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_174_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %175 = add nsw i32 %169, %165*/
begin
decode_block__preheader25_i_175 = decode_block__preheader25_i_169_reg + decode_block__preheader25_i_165_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %175 = add nsw i32 %169, %165*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_175_reg <= decode_block__preheader25_i_175;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_175) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_175_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %176 = sub nsw i32 %165, %169*/
begin
decode_block__preheader25_i_176 = decode_block__preheader25_i_165_reg - decode_block__preheader25_i_169_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %176 = sub nsw i32 %165, %169*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_176_reg <= decode_block__preheader25_i_176;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_176) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_176_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %177 = sub nsw i32 %162, %173*/
begin
decode_block__preheader25_i_177 = decode_block__preheader25_i_162_reg - decode_block__preheader25_i_173_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %177 = sub nsw i32 %162, %173*/
if (cur_state == LEGUP_F_decode_block_BB18_81)
begin
decode_block__preheader25_i_177_reg <= decode_block__preheader25_i_177;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_177) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_177_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %178 = add nsw i32 %147, %151*/
begin
decode_block__preheader25_i_178 = decode_block__preheader25_i_147_reg + decode_block__preheader25_i_151_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %179 = sub nsw i32 %147, %151*/
begin
decode_block__preheader25_i_179 = decode_block__preheader25_i_147_reg - decode_block__preheader25_i_151_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %180 = sub nsw i32 %159, %155*/
begin
decode_block__preheader25_i_180 = decode_block__preheader25_i_159_reg - decode_block__preheader25_i_155_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %181 = add nsw i32 %159, %155*/
begin
decode_block__preheader25_i_181 = decode_block__preheader25_i_159_reg + decode_block__preheader25_i_155_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %182 = sub nsw i32 %180, %179*/
begin
decode_block__preheader25_i_182 = decode_block__preheader25_i_180 - decode_block__preheader25_i_179;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %183 = mul nsw i32 %182, 362*/
begin
decode_block__preheader25_i_183 = decode_block_signed_multiply_32_1;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %183 = mul nsw i32 %182, 362*/
decode_block__preheader25_i_183_reg = decode_block__preheader25_i_144_reg;
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %184 = ashr i32 %183, 9*/
begin
decode_block__preheader25_i_184 = $signed(decode_block__preheader25_i_183_reg) >>> 32'd9;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %185 = add nsw i32 %180, %179*/
begin
decode_block__preheader25_i_185 = decode_block__preheader25_i_180 + decode_block__preheader25_i_179;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %186 = mul nsw i32 %185, 362*/
begin
decode_block__preheader25_i_186 = decode_block_signed_multiply_32_2;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %186 = mul nsw i32 %185, 362*/
decode_block__preheader25_i_186_reg = decode_block__preheader25_i_152_reg;
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %187 = ashr i32 %186, 9*/
begin
decode_block__preheader25_i_187 = $signed(decode_block__preheader25_i_186_reg) >>> 32'd9;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %188 = add nsw i32 %181, %174*/
begin
decode_block__preheader25_i_188 = decode_block__preheader25_i_181 + decode_block__preheader25_i_174_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %189 = add nsw i32 %187, %175*/
begin
decode_block__preheader25_i_189 = decode_block__preheader25_i_187 + decode_block__preheader25_i_175_reg;
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %190 = add nsw i32 %184, %176*/
begin
decode_block__preheader25_i_190 = decode_block__preheader25_i_184 + decode_block__preheader25_i_176_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %190 = add nsw i32 %184, %176*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
decode_block__preheader25_i_190_reg <= decode_block__preheader25_i_190;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_190) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_190_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %191 = add nsw i32 %178, %177*/
begin
decode_block__preheader25_i_191 = decode_block__preheader25_i_178 + decode_block__preheader25_i_177_reg;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %191 = add nsw i32 %178, %177*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
decode_block__preheader25_i_191_reg <= decode_block__preheader25_i_191;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_191) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_191_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %192 = sub nsw i32 %177, %178*/
begin
decode_block__preheader25_i_192 = decode_block__preheader25_i_177_reg - decode_block__preheader25_i_178;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %192 = sub nsw i32 %177, %178*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
decode_block__preheader25_i_192_reg <= decode_block__preheader25_i_192;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_192_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %193 = sub nsw i32 %176, %184*/
begin
decode_block__preheader25_i_193 = decode_block__preheader25_i_176_reg - decode_block__preheader25_i_184;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %193 = sub nsw i32 %176, %184*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
decode_block__preheader25_i_193_reg <= decode_block__preheader25_i_193;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_193) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_193_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %194 = sub nsw i32 %175, %187*/
begin
decode_block__preheader25_i_194 = decode_block__preheader25_i_175_reg - decode_block__preheader25_i_187;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %194 = sub nsw i32 %175, %187*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
decode_block__preheader25_i_194_reg <= decode_block__preheader25_i_194;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_194) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_194_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %195 = sub nsw i32 %174, %181*/
begin
decode_block__preheader25_i_195 = decode_block__preheader25_i_174_reg - decode_block__preheader25_i_181;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %195 = sub nsw i32 %174, %181*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
decode_block__preheader25_i_195_reg <= decode_block__preheader25_i_195;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_195) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_195_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %196 = add nsw i32 %i.126.i, 1*/
begin
decode_block__preheader25_i_196 = decode_block__preheader25_i_i_126_i + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %196 = add nsw i32 %i.126.i, 1*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_196_reg <= decode_block__preheader25_i_196;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_196) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_196_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader25.i*/
/* %exitcond28.i = icmp eq i32 %196, 8*/
begin
decode_block__preheader25_i_exitcond28_i = decode_block__preheader25_i_196 == 32'd8;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %exitcond28.i = icmp eq i32 %196, 8*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
decode_block__preheader25_i_exitcond28_i_reg <= decode_block__preheader25_i_exitcond28_i;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_exitcond28_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_exitcond28_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %i.224.i = phi i32 [ %203, %.preheader.i8 ], [ 0, %.preheader25.i ]*/
begin
decode_block__preheader_i8_i_224_i = decode_block__preheader_i8_i_224_i_phi_temp;
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %aptr.023.i = getelementptr i32* %out_buf, i32 %i.224.i*/
begin
decode_block__preheader_i8_aptr_023_i = arg_out_buf + 4 * decode_block__preheader_i8_i_224_i;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %aptr.023.i = getelementptr i32* %out_buf, i32 %i.224.i*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
decode_block__preheader_i8_aptr_023_i_reg <= decode_block__preheader_i8_aptr_023_i;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_aptr_023_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_aptr_023_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %197 = load i32* %aptr.023.i, align 4, !tbaa !2*/
begin
decode_block__preheader_i8_197 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %198 = ashr i32 %197, 31*/
begin
decode_block__preheader_i8_198 = $signed(decode_block__preheader_i8_197) >>> 32'd31;
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %199 = and i32 %198, -16*/
begin
decode_block__preheader_i8_199 = decode_block__preheader_i8_198 & -32'd16;
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %200 = or i32 %199, 8*/
begin
decode_block__preheader_i8_200 = decode_block__preheader_i8_199 | 32'd8;
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %201 = add i32 %200, %197*/
begin
decode_block__preheader_i8_201 = decode_block__preheader_i8_200 + decode_block__preheader_i8_197;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %201 = add i32 %200, %197*/
if (cur_state == LEGUP_F_decode_block_BB19_92)
begin
decode_block__preheader_i8_201_reg <= decode_block__preheader_i8_201;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_201_reg"); $finish; end
end
end
always @(*) begin
decode_block__preheader_i8_202 = decode_block_signed_divide_32_0;
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %202 = sdiv i32 %201, 16*/
if (cur_state == LEGUP_F_decode_block_BB19_132)
begin
decode_block__preheader_i8_202_reg <= decode_block__preheader_i8_202;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_202) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_202_reg"); $finish; end
end
/* decode_block: %.preheader.i8*/
/* %202 = sdiv i32 %201, 16*/
if (cur_state == LEGUP_F_decode_block_BB19_132)
begin
decode_block__preheader_i8_202_reg <= decode_block__preheader_i8_202;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_202) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_202_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %203 = add nsw i32 %i.224.i, 1*/
begin
decode_block__preheader_i8_203 = decode_block__preheader_i8_i_224_i + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %203 = add nsw i32 %i.224.i, 1*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
decode_block__preheader_i8_203_reg <= decode_block__preheader_i8_203;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_203) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_203_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %exitcond.i = icmp eq i32 %203, 64*/
begin
decode_block__preheader_i8_exitcond_i = decode_block__preheader_i8_203 == 32'd64;
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %exitcond.i = icmp eq i32 %203, 64*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
decode_block__preheader_i8_exitcond_i_reg <= decode_block__preheader_i8_exitcond_i;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_exitcond_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_exitcond_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %indvar.i1 = phi i32 [ %tmp.i3, %ChenIDct.exit ], [ 0, %.preheader.i8 ]*/
begin
decode_block_ChenIDct_exit_indvar_i1 = decode_block_ChenIDct_exit_indvar_i1_phi_temp;
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %mptr.01.i2 = getelementptr i32* %out_buf, i32 %indvar.i1*/
begin
decode_block_ChenIDct_exit_mptr_01_i2 = arg_out_buf + 4 * decode_block_ChenIDct_exit_indvar_i1;
end
end
always @(posedge clk) begin
/* decode_block: %ChenIDct.exit*/
/* %mptr.01.i2 = getelementptr i32* %out_buf, i32 %indvar.i1*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
decode_block_ChenIDct_exit_mptr_01_i2_reg <= decode_block_ChenIDct_exit_mptr_01_i2;
if (^reset !== 1'bX && ^(decode_block_ChenIDct_exit_mptr_01_i2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_ChenIDct_exit_mptr_01_i2_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %tmp.i3 = add i32 %indvar.i1, 1*/
begin
decode_block_ChenIDct_exit_tmp_i3 = decode_block_ChenIDct_exit_indvar_i1 + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %ChenIDct.exit*/
/* %tmp.i3 = add i32 %indvar.i1, 1*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
decode_block_ChenIDct_exit_tmp_i3_reg <= decode_block_ChenIDct_exit_tmp_i3;
if (^reset !== 1'bX && ^(decode_block_ChenIDct_exit_tmp_i3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_ChenIDct_exit_tmp_i3_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %204 = load i32* %mptr.01.i2, align 4, !tbaa !2*/
begin
decode_block_ChenIDct_exit_204 = memory_controller_out[31:0];
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %205 = add nsw i32 %204, 128*/
begin
decode_block_ChenIDct_exit_205 = decode_block_ChenIDct_exit_204 + 32'd128;
end
end
always @(*) begin
/* decode_block: %ChenIDct.exit*/
/* %exitcond7 = icmp eq i32 %tmp.i3, 64*/
begin
decode_block_ChenIDct_exit_exitcond7 = decode_block_ChenIDct_exit_tmp_i3 == 32'd64;
end
end
always @(posedge clk) begin
/* decode_block: %ChenIDct.exit*/
/* %exitcond7 = icmp eq i32 %tmp.i3, 64*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
decode_block_ChenIDct_exit_exitcond7_reg <= decode_block_ChenIDct_exit_exitcond7;
if (^reset !== 1'bX && ^(decode_block_ChenIDct_exit_exitcond7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_ChenIDct_exit_exitcond7_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %indvar.i = phi i32 [ %tmp.i, %212 ], [ 0, %ChenIDct.exit ]*/
begin
decode_block_PostshiftIDctMatrix_exit_indvar_i = decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp;
end
end
always @(*) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %mptr.01.i = getelementptr i32* %out_buf, i32 %indvar.i*/
begin
decode_block_PostshiftIDctMatrix_exit_mptr_01_i = arg_out_buf + 4 * decode_block_PostshiftIDctMatrix_exit_indvar_i;
end
end
always @(posedge clk) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %mptr.01.i = getelementptr i32* %out_buf, i32 %indvar.i*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
decode_block_PostshiftIDctMatrix_exit_mptr_01_i_reg <= decode_block_PostshiftIDctMatrix_exit_mptr_01_i;
if (^reset !== 1'bX && ^(decode_block_PostshiftIDctMatrix_exit_mptr_01_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_PostshiftIDctMatrix_exit_mptr_01_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %tmp.i = add i32 %indvar.i, 1*/
begin
decode_block_PostshiftIDctMatrix_exit_tmp_i = decode_block_PostshiftIDctMatrix_exit_indvar_i + 32'd1;
end
end
always @(posedge clk) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %tmp.i = add i32 %indvar.i, 1*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
decode_block_PostshiftIDctMatrix_exit_tmp_i_reg <= decode_block_PostshiftIDctMatrix_exit_tmp_i;
if (^reset !== 1'bX && ^(decode_block_PostshiftIDctMatrix_exit_tmp_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_PostshiftIDctMatrix_exit_tmp_i_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
begin
decode_block_PostshiftIDctMatrix_exit_206 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB21_146)
begin
decode_block_PostshiftIDctMatrix_exit_206_reg <= decode_block_PostshiftIDctMatrix_exit_206;
if (^reset !== 1'bX && ^(decode_block_PostshiftIDctMatrix_exit_206) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_PostshiftIDctMatrix_exit_206_reg"); $finish; end
end
end
always @(*) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %207 = icmp slt i32 %206, 0*/
begin
decode_block_PostshiftIDctMatrix_exit_207 = $signed(decode_block_PostshiftIDctMatrix_exit_206) < $signed(32'd0);
end
end
always @(*) begin
/* decode_block: %209*/
/* %210 = icmp sgt i32 %206, 255*/
begin
decode_block_209_210 = $signed(decode_block_PostshiftIDctMatrix_exit_206_reg) > $signed(32'd255);
end
end
always @(*) begin
/* decode_block: %212*/
/* %exitcond = icmp eq i32 %tmp.i, 64*/
begin
decode_block_212_exitcond = decode_block_PostshiftIDctMatrix_exit_tmp_i_reg == 32'd64;
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_start"); $finish; end
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
DecodeHuffman_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_start"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_start"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
DecodeHuffman_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_start"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_arg_Xhuff_huffval <= decode_block_0_4_reg;
if (^reset !== 1'bX && ^(decode_block_0_4_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Xhuff_huffval"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_arg_Xhuff_huffval <= decode_block__preheader_i_27_reg;
if (^reset !== 1'bX && ^(decode_block__preheader_i_27_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Xhuff_huffval"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_arg_Dhuff_ml <= decode_block_0_6;
if (^reset !== 1'bX && ^(decode_block_0_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_ml"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_arg_Dhuff_ml <= decode_block_34_35;
if (^reset !== 1'bX && ^(decode_block_34_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_ml"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_arg_Dhuff_maxcode <= decode_block_0_7_reg;
if (^reset !== 1'bX && ^(decode_block_0_7_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_maxcode"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_arg_Dhuff_maxcode <= decode_block__preheader_i_29_reg;
if (^reset !== 1'bX && ^(decode_block__preheader_i_29_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_maxcode"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_arg_Dhuff_mincode <= decode_block_0_8_reg;
if (^reset !== 1'bX && ^(decode_block_0_8_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_mincode"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_arg_Dhuff_mincode <= decode_block__preheader_i_30_reg;
if (^reset !== 1'bX && ^(decode_block__preheader_i_30_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_mincode"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
DecodeHuffman_arg_Dhuff_valptr <= decode_block_0_9_reg;
if (^reset !== 1'bX && ^(decode_block_0_9_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_valptr"); $finish; end
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
DecodeHuffman_arg_Dhuff_valptr <= decode_block__preheader_i_31_reg;
if (^reset !== 1'bX && ^(decode_block__preheader_i_31_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_arg_Dhuff_valptr"); $finish; end
end
end
always @(*) begin
DecodeHuffman_memory_controller_waitrequest = 1'd0;
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
DecodeHuffman_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
DecodeHuffman_memory_controller_waitrequest = memory_controller_waitrequest;
end
end
always @(*) begin
DecodeHuffman_memory_controller_out = 1'd0;
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
DecodeHuffman_memory_controller_out = memory_controller_out;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
DecodeHuffman_memory_controller_out = memory_controller_out;
end
end
always @(*) begin
legup_function_call = 1'd0;
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB0_5)
begin
legup_function_call = 1'd1;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
legup_function_call = 1'd1;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB1_8)
begin
legup_function_call = 1'd1;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
legup_function_call = 1'd1;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB7_25)
begin
legup_function_call = 1'd1;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
legup_function_call = 1'd1;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB9_29)
begin
legup_function_call = 1'd1;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
legup_function_call = 1'd1;
end
end
always @(posedge clk) begin
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB1_8)
begin
buf_getv_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_start"); $finish; end
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
buf_getv_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_start"); $finish; end
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB9_29)
begin
buf_getv_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_start"); $finish; end
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
buf_getv_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_start"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB1_8)
begin
buf_getv_arg_n <= decode_block_0_10_reg;
if (^reset !== 1'bX && ^(decode_block_0_10_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_arg_n"); $finish; end
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_F_decode_block_BB9_29)
begin
buf_getv_arg_n <= decode_block_34_37_reg;
if (^reset !== 1'bX && ^(decode_block_34_37_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_arg_n"); $finish; end
end
end
always @(*) begin
buf_getv_memory_controller_waitrequest = 1'd0;
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
buf_getv_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
buf_getv_memory_controller_waitrequest = memory_controller_waitrequest;
end
end
always @(*) begin
buf_getv_memory_controller_out = 1'd0;
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
buf_getv_memory_controller_out = memory_controller_out;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
buf_getv_memory_controller_out = memory_controller_out;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %83 = mul i32 %75, 400*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block_signed_multiply_32_1_op0 = decode_block_IQuantize_exit_75;
end
/* decode_block: %IQuantize.exit*/
/* %88 = mul i32 %77, -1136*/
else if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block_signed_multiply_32_1_op0 = decode_block_IQuantize_exit_77;
end
/* decode_block: %IQuantize.exit*/
/* %103 = mul nsw i32 %102, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block_signed_multiply_32_1_op0 = decode_block_IQuantize_exit_102;
end
/* decode_block: %IQuantize.exit*/
/* %122 = mul nsw i32 %121, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_signed_multiply_32_1_op0 = decode_block_IQuantize_exit_121;
end
/* decode_block: %.preheader25.i*/
/* %144 = mul nsw i32 %137, 100*/
else if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block_signed_multiply_32_1_op0 = decode_block__preheader25_i_137;
end
/* decode_block: %.preheader25.i*/
/* %166 = mul nsw i32 %138, 196*/
else if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block_signed_multiply_32_1_op0 = decode_block__preheader25_i_138;
end
/* decode_block: %.preheader25.i*/
/* %149 = mul i32 %139, -284*/
else if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block_signed_multiply_32_1_op0 = decode_block__preheader25_i_139;
end
/* decode_block: %.preheader25.i*/
/* %183 = mul nsw i32 %182, 362*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_82) */
begin
decode_block_signed_multiply_32_1_op0 = decode_block__preheader25_i_182;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %83 = mul i32 %75, 400*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block_signed_multiply_32_1_op1 = 32'd400;
end
/* decode_block: %IQuantize.exit*/
/* %88 = mul i32 %77, -1136*/
else if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block_signed_multiply_32_1_op1 = -32'd1136;
end
/* decode_block: %IQuantize.exit*/
/* %103 = mul nsw i32 %102, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block_signed_multiply_32_1_op1 = 32'd362;
end
/* decode_block: %IQuantize.exit*/
/* %122 = mul nsw i32 %121, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_signed_multiply_32_1_op1 = 32'd362;
end
/* decode_block: %.preheader25.i*/
/* %144 = mul nsw i32 %137, 100*/
else if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block_signed_multiply_32_1_op1 = 32'd100;
end
/* decode_block: %.preheader25.i*/
/* %166 = mul nsw i32 %138, 196*/
else if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block_signed_multiply_32_1_op1 = 32'd196;
end
/* decode_block: %.preheader25.i*/
/* %149 = mul i32 %139, -284*/
else if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block_signed_multiply_32_1_op1 = -32'd284;
end
/* decode_block: %.preheader25.i*/
/* %183 = mul nsw i32 %182, 362*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_82) */
begin
decode_block_signed_multiply_32_1_op1 = 32'd362;
end
end
always @(*) begin
decode_block_signed_multiply_32_1 = decode_block_signed_multiply_32_1_op0 * decode_block_signed_multiply_32_1_op1;
end
always @(*) begin
/* decode_block: %69*/
/* %72 = mul nsw i32 %71, %70*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
decode_block_signed_multiply_32_0_op0 = decode_block_69_71;
end
/* decode_block: %IQuantize.exit*/
/* %100 = mul nsw i32 %99, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block_signed_multiply_32_0_op0 = decode_block_IQuantize_exit_99;
end
/* decode_block: %IQuantize.exit*/
/* %87 = mul i32 %80, 1704*/
else if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_signed_multiply_32_0_op0 = decode_block_IQuantize_exit_80;
end
/* decode_block: %IQuantize.exit*/
/* %106 = mul i32 %81, -1892*/
else if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_signed_multiply_32_0_op0 = decode_block_IQuantize_exit_81;
end
/* decode_block: %IQuantize.exit*/
/* %84 = mul i32 %82, -2008*/
else if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_signed_multiply_32_0_op0 = decode_block_IQuantize_exit_82;
end
/* decode_block: %.preheader25.i*/
/* %161 = mul nsw i32 %160, 362*/
else if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block_signed_multiply_32_0_op0 = decode_block__preheader25_i_160;
end
/* decode_block: %.preheader25.i*/
/* %148 = mul nsw i32 %141, 426*/
else if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block_signed_multiply_32_0_op0 = decode_block__preheader25_i_141;
end
/* decode_block: %.preheader25.i*/
/* %167 = mul i32 %142, -473*/
else if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block_signed_multiply_32_0_op0 = decode_block__preheader25_i_142;
end
/* decode_block: %.preheader25.i*/
/* %145 = mul i32 %143, -502*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_81) */
begin
decode_block_signed_multiply_32_0_op0 = decode_block__preheader25_i_143;
end
end
always @(*) begin
/* decode_block: %69*/
/* %72 = mul nsw i32 %71, %70*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
decode_block_signed_multiply_32_0_op1 = decode_block_69_70_reg;
end
/* decode_block: %IQuantize.exit*/
/* %100 = mul nsw i32 %99, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
decode_block_signed_multiply_32_0_op1 = 32'd362;
end
/* decode_block: %IQuantize.exit*/
/* %87 = mul i32 %80, 1704*/
else if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_signed_multiply_32_0_op1 = 32'd1704;
end
/* decode_block: %IQuantize.exit*/
/* %106 = mul i32 %81, -1892*/
else if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_signed_multiply_32_0_op1 = -32'd1892;
end
/* decode_block: %IQuantize.exit*/
/* %84 = mul i32 %82, -2008*/
else if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_signed_multiply_32_0_op1 = -32'd2008;
end
/* decode_block: %.preheader25.i*/
/* %161 = mul nsw i32 %160, 362*/
else if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block_signed_multiply_32_0_op1 = 32'd362;
end
/* decode_block: %.preheader25.i*/
/* %148 = mul nsw i32 %141, 426*/
else if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block_signed_multiply_32_0_op1 = 32'd426;
end
/* decode_block: %.preheader25.i*/
/* %167 = mul i32 %142, -473*/
else if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block_signed_multiply_32_0_op1 = -32'd473;
end
/* decode_block: %.preheader25.i*/
/* %145 = mul i32 %143, -502*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_81) */
begin
decode_block_signed_multiply_32_0_op1 = -32'd502;
end
end
always @(*) begin
decode_block_signed_multiply_32_0 = decode_block_signed_multiply_32_0_op0 * decode_block_signed_multiply_32_0_op1;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %95 = mul i32 %75, 2008*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block_signed_multiply_32_2_op0 = decode_block_IQuantize_exit_75;
end
/* decode_block: %IQuantize.exit*/
/* %109 = mul i32 %76, 1892*/
else if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block_signed_multiply_32_2_op0 = decode_block_IQuantize_exit_76;
end
/* decode_block: %IQuantize.exit*/
/* %125 = mul nsw i32 %124, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_signed_multiply_32_2_op0 = decode_block_IQuantize_exit_124;
end
/* decode_block: %.preheader25.i*/
/* %156 = mul nsw i32 %137, 502*/
else if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block_signed_multiply_32_2_op0 = decode_block__preheader25_i_137;
end
/* decode_block: %.preheader25.i*/
/* %170 = mul nsw i32 %138, 473*/
else if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block_signed_multiply_32_2_op0 = decode_block__preheader25_i_138;
end
/* decode_block: %.preheader25.i*/
/* %152 = mul nsw i32 %139, 426*/
else if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block_signed_multiply_32_2_op0 = decode_block__preheader25_i_139;
end
/* decode_block: %.preheader25.i*/
/* %186 = mul nsw i32 %185, 362*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_82) */
begin
decode_block_signed_multiply_32_2_op0 = decode_block__preheader25_i_185;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %95 = mul i32 %75, 2008*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
decode_block_signed_multiply_32_2_op1 = 32'd2008;
end
/* decode_block: %IQuantize.exit*/
/* %109 = mul i32 %76, 1892*/
else if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block_signed_multiply_32_2_op1 = 32'd1892;
end
/* decode_block: %IQuantize.exit*/
/* %125 = mul nsw i32 %124, 362*/
else if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
decode_block_signed_multiply_32_2_op1 = 32'd362;
end
/* decode_block: %.preheader25.i*/
/* %156 = mul nsw i32 %137, 502*/
else if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
decode_block_signed_multiply_32_2_op1 = 32'd502;
end
/* decode_block: %.preheader25.i*/
/* %170 = mul nsw i32 %138, 473*/
else if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
decode_block_signed_multiply_32_2_op1 = 32'd473;
end
/* decode_block: %.preheader25.i*/
/* %152 = mul nsw i32 %139, 426*/
else if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
decode_block_signed_multiply_32_2_op1 = 32'd426;
end
/* decode_block: %.preheader25.i*/
/* %186 = mul nsw i32 %185, 362*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_82) */
begin
decode_block_signed_multiply_32_2_op1 = 32'd362;
end
end
always @(*) begin
decode_block_signed_multiply_32_2 = decode_block_signed_multiply_32_2_op0 * decode_block_signed_multiply_32_2_op1;
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %105 = mul i32 %76, 784*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block_signed_multiply_32_3_op0 = decode_block_IQuantize_exit_76;
end
/* decode_block: %IQuantize.exit*/
/* %91 = mul i32 %77, 1704*/
else if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block_signed_multiply_32_3_op0 = decode_block_IQuantize_exit_77;
end
/* decode_block: %IQuantize.exit*/
/* %92 = mul i32 %80, 1136*/
else if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_signed_multiply_32_3_op0 = decode_block_IQuantize_exit_80;
end
/* decode_block: %IQuantize.exit*/
/* %110 = mul i32 %81, 784*/
else if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_signed_multiply_32_3_op0 = decode_block_IQuantize_exit_81;
end
/* decode_block: %IQuantize.exit*/
/* %96 = mul i32 %82, 400*/
else if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_signed_multiply_32_3_op0 = decode_block_IQuantize_exit_82;
end
/* decode_block: %.preheader25.i*/
/* %164 = mul nsw i32 %163, 362*/
else if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block_signed_multiply_32_3_op0 = decode_block__preheader25_i_163;
end
/* decode_block: %.preheader25.i*/
/* %153 = mul nsw i32 %141, 284*/
else if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block_signed_multiply_32_3_op0 = decode_block__preheader25_i_141;
end
/* decode_block: %.preheader25.i*/
/* %171 = mul nsw i32 %142, 196*/
else if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block_signed_multiply_32_3_op0 = decode_block__preheader25_i_142;
end
/* decode_block: %.preheader25.i*/
/* %157 = mul nsw i32 %143, 100*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_81) */
begin
decode_block_signed_multiply_32_3_op0 = decode_block__preheader25_i_143;
end
end
always @(*) begin
/* decode_block: %IQuantize.exit*/
/* %105 = mul i32 %76, 784*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
decode_block_signed_multiply_32_3_op1 = 32'd784;
end
/* decode_block: %IQuantize.exit*/
/* %91 = mul i32 %77, 1704*/
else if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
decode_block_signed_multiply_32_3_op1 = 32'd1704;
end
/* decode_block: %IQuantize.exit*/
/* %92 = mul i32 %80, 1136*/
else if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
decode_block_signed_multiply_32_3_op1 = 32'd1136;
end
/* decode_block: %IQuantize.exit*/
/* %110 = mul i32 %81, 784*/
else if (cur_state == LEGUP_F_decode_block_BB17_62)
begin
decode_block_signed_multiply_32_3_op1 = 32'd784;
end
/* decode_block: %IQuantize.exit*/
/* %96 = mul i32 %82, 400*/
else if (cur_state == LEGUP_F_decode_block_BB17_63)
begin
decode_block_signed_multiply_32_3_op1 = 32'd400;
end
/* decode_block: %.preheader25.i*/
/* %164 = mul nsw i32 %163, 362*/
else if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
decode_block_signed_multiply_32_3_op1 = 32'd362;
end
/* decode_block: %.preheader25.i*/
/* %153 = mul nsw i32 %141, 284*/
else if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
decode_block_signed_multiply_32_3_op1 = 32'd284;
end
/* decode_block: %.preheader25.i*/
/* %171 = mul nsw i32 %142, 196*/
else if (cur_state == LEGUP_F_decode_block_BB18_80)
begin
decode_block_signed_multiply_32_3_op1 = 32'd196;
end
/* decode_block: %.preheader25.i*/
/* %157 = mul nsw i32 %143, 100*/
else /* if (cur_state == LEGUP_F_decode_block_BB18_81) */
begin
decode_block_signed_multiply_32_3_op1 = 32'd100;
end
end
always @(*) begin
decode_block_signed_multiply_32_3 = decode_block_signed_multiply_32_3_op0 * decode_block_signed_multiply_32_3_op1;
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %202 = sdiv i32 %201, 16*/
begin
decode_block_signed_divide_32_0_op0 = decode_block__preheader_i8_201_reg;
end
end
always @(*) begin
/* decode_block: %.preheader.i8*/
/* %202 = sdiv i32 %201, 16*/
if (reset) begin decode_block_signed_divide_32_0_op1 = 0; end
begin
decode_block_signed_divide_32_0_op1 = 32'd16;
end
end
always @(*) begin
decode_block_signed_divide_32_0 = lpm_divide_decode_block__preheader_i8_202_out;
end
always @(*) begin
lpm_divide_decode_block__preheader_i8_202_en = memory_controller_waitrequest == 1'd0 & legup_function_call == 1'd0;
end
always @(posedge clk) begin
/* decode_block: %.lr.ph.i*/
/* %indvar.i2 = phi i32 [ %tmp4.i, %.lr.ph.i ], [ 0, %0 ], [ 0, %24 ]*/
if (cur_state == LEGUP_function_call_7 & memory_controller_waitrequest == 1'd0 & decode_block_0_11 == 1'd1)
begin
decode_block__lr_ph_i_indvar_i2_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__lr_ph_i_indvar_i2_phi_temp"); $finish; end
end
/* decode_block: %.lr.ph.i*/
/* %indvar.i2 = phi i32 [ %tmp4.i, %.lr.ph.i ], [ 0, %0 ], [ 0, %24 ]*/
if (cur_state == LEGUP_F_decode_block_BB3_19 & memory_controller_waitrequest == 1'd0)
begin
decode_block__lr_ph_i_indvar_i2_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__lr_ph_i_indvar_i2_phi_temp"); $finish; end
end
/* decode_block: %.lr.ph.i*/
/* %indvar.i2 = phi i32 [ %tmp4.i, %.lr.ph.i ], [ 0, %0 ], [ 0, %24 ]*/
if (cur_state == LEGUP_F_decode_block_BB5_21 & memory_controller_waitrequest == 1'd0 & decode_block__lr_ph_i_32 == 1'd1)
begin
decode_block__lr_ph_i_indvar_i2_phi_temp <= decode_block__lr_ph_i_tmp4_i;
if (^reset !== 1'bX && ^(decode_block__lr_ph_i_tmp4_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__lr_ph_i_indvar_i2_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB1_13 & memory_controller_waitrequest == 1'd0 & decode_block_12_18 == 1'd0)
begin
decode_block_24_diff_0_i_phi_temp <= decode_block_12_13_reg;
if (^reset !== 1'bX && ^(decode_block_12_13_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_24_diff_0_i_phi_temp"); $finish; end
end
/* decode_block: %24*/
/* %diff.0.i = phi i32 [ %23, %19 ], [ %13, %12 ]*/
if (cur_state == LEGUP_F_decode_block_BB2_16 & memory_controller_waitrequest == 1'd0)
begin
decode_block_24_diff_0_i_phi_temp <= decode_block_19_23;
if (^reset !== 1'bX && ^(decode_block_19_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_24_diff_0_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB4_20 & memory_controller_waitrequest == 1'd0)
begin
decode_block__backedge_i_k_0_i_phi_temp <= 32'd1;
if (^reset !== 1'bX && ^(32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_phi_temp"); $finish; end
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB11_39 & memory_controller_waitrequest == 1'd0)
begin
decode_block__backedge_i_k_0_i_phi_temp <= decode_block_57_58;
if (^reset !== 1'bX && ^(decode_block_57_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_phi_temp"); $finish; end
end
/* decode_block: %.backedge.i*/
/* %k.0.i = phi i32 [ 1, %.preheader.i ], [ %58, %57 ], [ %62, %61 ]*/
if (cur_state == LEGUP_F_decode_block_BB13_41 & memory_controller_waitrequest == 1'd0)
begin
decode_block__backedge_i_k_0_i_phi_temp <= decode_block_61_62;
if (^reset !== 1'bX && ^(decode_block_61_62) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__backedge_i_k_0_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %DecodeHuffMCU.exit*/
/* %i.02.i = phi i32 [ %66, %DecodeHuffMCU.exit ], [ 0, %.backedge.i ], [ 0, %41 ], [ 0, %59 ]*/
if (cur_state == LEGUP_F_decode_block_BB6_22 & memory_controller_waitrequest == 1'd0 & decode_block__backedge_i_33 == 1'd0)
begin
decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp"); $finish; end
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %i.02.i = phi i32 [ %66, %DecodeHuffMCU.exit ], [ 0, %.backedge.i ], [ 0, %41 ], [ 0, %59 ]*/
if (cur_state == LEGUP_F_decode_block_BB8_28 & memory_controller_waitrequest == 1'd0 & decode_block_41_43 == 1'd1)
begin
decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp"); $finish; end
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %i.02.i = phi i32 [ %66, %DecodeHuffMCU.exit ], [ 0, %.backedge.i ], [ 0, %41 ], [ 0, %59 ]*/
if (cur_state == LEGUP_F_decode_block_BB12_40 & memory_controller_waitrequest == 1'd0 & decode_block_59_60 == 1'd0)
begin
decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp"); $finish; end
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %i.02.i = phi i32 [ %66, %DecodeHuffMCU.exit ], [ 0, %.backedge.i ], [ 0, %41 ], [ 0, %59 ]*/
if (cur_state == LEGUP_F_decode_block_BB14_46 & memory_controller_waitrequest == 1'd0 & decode_block_DecodeHuffMCU_exit_exitcond10_reg == 1'd0)
begin
decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp <= decode_block_DecodeHuffMCU_exit_66_reg;
if (^reset !== 1'bX && ^(decode_block_DecodeHuffMCU_exit_66_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_DecodeHuffMCU_exit_i_02_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %69*/
/* %indvar.i4 = phi i32 [ 0, %IZigzagMatrix.exit ], [ %tmp.i5, %69 ]*/
if (cur_state == LEGUP_F_decode_block_BB15_49 & memory_controller_waitrequest == 1'd0)
begin
decode_block_69_indvar_i4_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_indvar_i4_phi_temp"); $finish; end
end
/* decode_block: %69*/
/* %indvar.i4 = phi i32 [ 0, %IZigzagMatrix.exit ], [ %tmp.i5, %69 ]*/
if (cur_state == LEGUP_F_decode_block_BB16_53 & memory_controller_waitrequest == 1'd0 & decode_block_69_exitcond8_reg == 1'd0)
begin
decode_block_69_indvar_i4_phi_temp <= decode_block_69_tmp_i5_reg;
if (^reset !== 1'bX && ^(decode_block_69_tmp_i5_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_69_indvar_i4_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %IQuantize.exit*/
/* %i.027.i = phi i32 [ %135, %IQuantize.exit ], [ 0, %69 ]*/
if (cur_state == LEGUP_F_decode_block_BB16_53 & memory_controller_waitrequest == 1'd0 & decode_block_69_exitcond8_reg == 1'd1)
begin
decode_block_IQuantize_exit_i_027_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_i_027_i_phi_temp"); $finish; end
end
/* decode_block: %IQuantize.exit*/
/* %i.027.i = phi i32 [ %135, %IQuantize.exit ], [ 0, %69 ]*/
if (cur_state == LEGUP_F_decode_block_BB17_71 & memory_controller_waitrequest == 1'd0 & decode_block_IQuantize_exit_exitcond43_i_reg == 1'd0)
begin
decode_block_IQuantize_exit_i_027_i_phi_temp <= decode_block_IQuantize_exit_135_reg;
if (^reset !== 1'bX && ^(decode_block_IQuantize_exit_135_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_IQuantize_exit_i_027_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %.preheader25.i*/
/* %i.126.i = phi i32 [ %196, %.preheader25.i ], [ 0, %IQuantize.exit ]*/
if (cur_state == LEGUP_F_decode_block_BB17_71 & memory_controller_waitrequest == 1'd0 & decode_block_IQuantize_exit_exitcond43_i_reg == 1'd1)
begin
decode_block__preheader25_i_i_126_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_i_126_i_phi_temp"); $finish; end
end
/* decode_block: %.preheader25.i*/
/* %i.126.i = phi i32 [ %196, %.preheader25.i ], [ 0, %IQuantize.exit ]*/
if (cur_state == LEGUP_F_decode_block_BB18_89 & memory_controller_waitrequest == 1'd0 & decode_block__preheader25_i_exitcond28_i_reg == 1'd0)
begin
decode_block__preheader25_i_i_126_i_phi_temp <= decode_block__preheader25_i_196_reg;
if (^reset !== 1'bX && ^(decode_block__preheader25_i_196_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader25_i_i_126_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %.preheader.i8*/
/* %i.224.i = phi i32 [ %203, %.preheader.i8 ], [ 0, %.preheader25.i ]*/
if (cur_state == LEGUP_F_decode_block_BB18_89 & memory_controller_waitrequest == 1'd0 & decode_block__preheader25_i_exitcond28_i_reg == 1'd1)
begin
decode_block__preheader_i8_i_224_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_i_224_i_phi_temp"); $finish; end
end
/* decode_block: %.preheader.i8*/
/* %i.224.i = phi i32 [ %203, %.preheader.i8 ], [ 0, %.preheader25.i ]*/
if (cur_state == LEGUP_F_decode_block_BB19_140 & memory_controller_waitrequest == 1'd0 & decode_block__preheader_i8_exitcond_i_reg == 1'd0)
begin
decode_block__preheader_i8_i_224_i_phi_temp <= decode_block__preheader_i8_203_reg;
if (^reset !== 1'bX && ^(decode_block__preheader_i8_203_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block__preheader_i8_i_224_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %ChenIDct.exit*/
/* %indvar.i1 = phi i32 [ %tmp.i3, %ChenIDct.exit ], [ 0, %.preheader.i8 ]*/
if (cur_state == LEGUP_F_decode_block_BB19_140 & memory_controller_waitrequest == 1'd0 & decode_block__preheader_i8_exitcond_i_reg == 1'd1)
begin
decode_block_ChenIDct_exit_indvar_i1_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_ChenIDct_exit_indvar_i1_phi_temp"); $finish; end
end
/* decode_block: %ChenIDct.exit*/
/* %indvar.i1 = phi i32 [ %tmp.i3, %ChenIDct.exit ], [ 0, %.preheader.i8 ]*/
if (cur_state == LEGUP_F_decode_block_BB20_143 & memory_controller_waitrequest == 1'd0 & decode_block_ChenIDct_exit_exitcond7_reg == 1'd0)
begin
decode_block_ChenIDct_exit_indvar_i1_phi_temp <= decode_block_ChenIDct_exit_tmp_i3_reg;
if (^reset !== 1'bX && ^(decode_block_ChenIDct_exit_tmp_i3_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_ChenIDct_exit_indvar_i1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %indvar.i = phi i32 [ %tmp.i, %212 ], [ 0, %ChenIDct.exit ]*/
if (cur_state == LEGUP_F_decode_block_BB20_143 & memory_controller_waitrequest == 1'd0 & decode_block_ChenIDct_exit_exitcond7_reg == 1'd1)
begin
decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp"); $finish; end
end
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %indvar.i = phi i32 [ %tmp.i, %212 ], [ 0, %ChenIDct.exit ]*/
if (cur_state == LEGUP_F_decode_block_BB25_150 & memory_controller_waitrequest == 1'd0 & decode_block_212_exitcond == 1'd0)
begin
decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp <= decode_block_PostshiftIDctMatrix_exit_tmp_i_reg;
if (^reset !== 1'bX && ^(decode_block_PostshiftIDctMatrix_exit_tmp_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_PostshiftIDctMatrix_exit_indvar_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* decode_block: %BoundIDctMatrix.exit*/
/* ret void*/
if (cur_state == LEGUP_F_decode_block_BB26_151)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
memory_controller_address = DecodeHuffman_memory_controller_address;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
memory_controller_address = buf_getv_memory_controller_address;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
memory_controller_address = DecodeHuffman_memory_controller_address;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
memory_controller_address = buf_getv_memory_controller_address;
end
/* decode_block: %0*/
/* %2 = load i8* %1, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB0_1)
begin
memory_controller_address = decode_block_0_1;
end
/* decode_block: %0*/
/* %6 = load i32* %5, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
memory_controller_address = decode_block_0_5;
end
/* decode_block: %12*/
/* %16 = load i32* %15, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB1_11)
begin
memory_controller_address = decode_block_12_15_reg;
end
/* decode_block: %19*/
/* %21 = load i32* %20, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB2_14)
begin
memory_controller_address = decode_block_19_20;
end
/* decode_block: %24*/
/* %25 = load i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
memory_controller_address = arg_HuffBuff;
end
/* decode_block: %24*/
/* store i32 %26, i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_19)
begin
memory_controller_address = arg_HuffBuff;
end
/* decode_block: %.lr.ph.i*/
/* store i32 0, i32* %mptr.03.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB5_21)
begin
memory_controller_address = decode_block__lr_ph_i_mptr_03_i;
end
/* decode_block: %34*/
/* %35 = load i32* %28, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB7_23)
begin
memory_controller_address = decode_block__preheader_i_28_reg;
end
/* decode_block: %44*/
/* store i32 %45, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_32)
begin
memory_controller_address = decode_block_44_46_reg;
end
/* decode_block: %44*/
/* %49 = load i32* %48, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_33)
begin
memory_controller_address = decode_block_44_48_reg;
end
/* decode_block: %52*/
/* %54 = load i32* %53, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_36)
begin
memory_controller_address = decode_block_52_53;
end
/* decode_block: %52*/
/* store i32 %56, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_38)
begin
memory_controller_address = decode_block_44_46_reg;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %63 = load i32* %scevgep.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
memory_controller_address = decode_block_DecodeHuffMCU_exit_scevgep_i;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %65 = load i32* %64, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_44)
begin
memory_controller_address = decode_block_DecodeHuffMCU_exit_64;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* store i32 %65, i32* %.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_46)
begin
memory_controller_address = decode_block_DecodeHuffMCU_exit__01_i_reg;
end
/* decode_block: %IZigzagMatrix.exit*/
/* %68 = load i8* %67, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB15_47)
begin
memory_controller_address = decode_block_IZigzagMatrix_exit_67;
end
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
memory_controller_address = decode_block_69_mptr_02_i;
end
/* decode_block: %69*/
/* %71 = load i32* %.01.i6, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_51)
begin
memory_controller_address = decode_block_69__01_i6_reg;
end
/* decode_block: %69*/
/* store i32 %72, i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
memory_controller_address = decode_block_69_mptr_02_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %73 = load i32* %scevgep44.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep44_i;
end
/* decode_block: %IQuantize.exit*/
/* %75 = load i32* %scevgep48.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_55)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep48_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %76 = load i32* %scevgep51.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_56)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep51_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %77 = load i32* %scevgep54.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep54_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %78 = load i32* %scevgep57.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep57_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %80 = load i32* %scevgep60.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep60_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %81 = load i32* %scevgep63.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep63_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* %82 = load i32* %scevgep66.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep66_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %127, i32* %scevgep45.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep45_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %128, i32* %scevgep47.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep47_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %129, i32* %scevgep50.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_66)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep50_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %130, i32* %scevgep53.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_67)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep53_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %131, i32* %scevgep56.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_68)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep56_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %132, i32* %scevgep59.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_69)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep59_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %133, i32* %scevgep62.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_70)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep62_i_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %134, i32* %scevgep65.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_71)
begin
memory_controller_address = decode_block_IQuantize_exit_scevgep65_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
memory_controller_address = decode_block__preheader25_i_scevgep42_i;
end
/* decode_block: %.preheader25.i*/
/* %137 = load i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_73)
begin
memory_controller_address = decode_block__preheader25_i_scevgep41_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %138 = load i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_74)
begin
memory_controller_address = decode_block__preheader25_i_scevgep39_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %139 = load i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
memory_controller_address = decode_block__preheader25_i_scevgep37_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %140 = load i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
memory_controller_address = decode_block__preheader25_i_scevgep35_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %141 = load i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
memory_controller_address = decode_block__preheader25_i_scevgep33_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %142 = load i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
memory_controller_address = decode_block__preheader25_i_scevgep31_i_reg;
end
/* decode_block: %.preheader25.i*/
/* %143 = load i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
memory_controller_address = decode_block__preheader25_i_scevgep_i7_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %188, i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
memory_controller_address = decode_block__preheader25_i_scevgep42_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %189, i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
memory_controller_address = decode_block__preheader25_i_scevgep41_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %190, i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_84)
begin
memory_controller_address = decode_block__preheader25_i_scevgep39_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %191, i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_85)
begin
memory_controller_address = decode_block__preheader25_i_scevgep37_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %192, i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_86)
begin
memory_controller_address = decode_block__preheader25_i_scevgep35_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %193, i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_87)
begin
memory_controller_address = decode_block__preheader25_i_scevgep33_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %194, i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_88)
begin
memory_controller_address = decode_block__preheader25_i_scevgep31_i_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %195, i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_89)
begin
memory_controller_address = decode_block__preheader25_i_scevgep_i7_reg;
end
/* decode_block: %.preheader.i8*/
/* %197 = load i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
memory_controller_address = decode_block__preheader_i8_aptr_023_i;
end
/* decode_block: %.preheader.i8*/
/* store i32 %202, i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_140)
begin
memory_controller_address = decode_block__preheader_i8_aptr_023_i_reg;
end
/* decode_block: %ChenIDct.exit*/
/* %204 = load i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
memory_controller_address = decode_block_ChenIDct_exit_mptr_01_i2;
end
/* decode_block: %ChenIDct.exit*/
/* store i32 %205, i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_143)
begin
memory_controller_address = decode_block_ChenIDct_exit_mptr_01_i2_reg;
end
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
memory_controller_address = decode_block_PostshiftIDctMatrix_exit_mptr_01_i;
end
/* decode_block: %208*/
/* store i32 0, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB22_147)
begin
memory_controller_address = decode_block_PostshiftIDctMatrix_exit_mptr_01_i_reg;
end
/* decode_block: %211*/
/* store i32 255, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB24_149)
begin
memory_controller_address = decode_block_PostshiftIDctMatrix_exit_mptr_01_i_reg;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
memory_controller_enable = DecodeHuffman_memory_controller_enable;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
memory_controller_enable = buf_getv_memory_controller_enable;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
memory_controller_enable = DecodeHuffman_memory_controller_enable;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
memory_controller_enable = buf_getv_memory_controller_enable;
end
/* decode_block: %0*/
/* %2 = load i8* %1, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB0_1)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %0*/
/* %6 = load i32* %5, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %12*/
/* %16 = load i32* %15, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB1_11)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %19*/
/* %21 = load i32* %20, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB2_14)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %24*/
/* %25 = load i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %24*/
/* store i32 %26, i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_19)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.lr.ph.i*/
/* store i32 0, i32* %mptr.03.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB5_21)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %34*/
/* %35 = load i32* %28, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB7_23)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %44*/
/* store i32 %45, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_32)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %44*/
/* %49 = load i32* %48, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_33)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %52*/
/* %54 = load i32* %53, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_36)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %52*/
/* store i32 %56, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_38)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %63 = load i32* %scevgep.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %65 = load i32* %64, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_44)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* store i32 %65, i32* %.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_46)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IZigzagMatrix.exit*/
/* %68 = load i8* %67, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB15_47)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %69*/
/* %71 = load i32* %.01.i6, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_51)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %69*/
/* store i32 %72, i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %73 = load i32* %scevgep44.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %75 = load i32* %scevgep48.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_55)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %76 = load i32* %scevgep51.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_56)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %77 = load i32* %scevgep54.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %78 = load i32* %scevgep57.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %80 = load i32* %scevgep60.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %81 = load i32* %scevgep63.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %82 = load i32* %scevgep66.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %127, i32* %scevgep45.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %128, i32* %scevgep47.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %129, i32* %scevgep50.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_66)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %130, i32* %scevgep53.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_67)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %131, i32* %scevgep56.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_68)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %132, i32* %scevgep59.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_69)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %133, i32* %scevgep62.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_70)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %134, i32* %scevgep65.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_71)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %137 = load i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_73)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %138 = load i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_74)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %139 = load i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %140 = load i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %141 = load i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %142 = load i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %143 = load i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %188, i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %189, i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %190, i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_84)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %191, i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_85)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %192, i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_86)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %193, i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_87)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %194, i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_88)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %195, i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_89)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader.i8*/
/* %197 = load i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %.preheader.i8*/
/* store i32 %202, i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_140)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %ChenIDct.exit*/
/* %204 = load i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %ChenIDct.exit*/
/* store i32 %205, i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_143)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %208*/
/* store i32 0, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB22_147)
begin
memory_controller_enable = 1'd1;
end
/* decode_block: %211*/
/* store i32 255, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB24_149)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
memory_controller_write_enable = DecodeHuffman_memory_controller_write_enable;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
memory_controller_write_enable = buf_getv_memory_controller_write_enable;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
memory_controller_write_enable = DecodeHuffman_memory_controller_write_enable;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
memory_controller_write_enable = buf_getv_memory_controller_write_enable;
end
/* decode_block: %0*/
/* %2 = load i8* %1, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB0_1)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %0*/
/* %6 = load i32* %5, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %12*/
/* %16 = load i32* %15, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB1_11)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %19*/
/* %21 = load i32* %20, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB2_14)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %24*/
/* %25 = load i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %24*/
/* store i32 %26, i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_19)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.lr.ph.i*/
/* store i32 0, i32* %mptr.03.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB5_21)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %34*/
/* %35 = load i32* %28, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB7_23)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %44*/
/* store i32 %45, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_32)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %44*/
/* %49 = load i32* %48, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_33)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %52*/
/* %54 = load i32* %53, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_36)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %52*/
/* store i32 %56, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_38)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %63 = load i32* %scevgep.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %65 = load i32* %64, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_44)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* store i32 %65, i32* %.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_46)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IZigzagMatrix.exit*/
/* %68 = load i8* %67, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB15_47)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %69*/
/* %71 = load i32* %.01.i6, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_51)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %69*/
/* store i32 %72, i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* %73 = load i32* %scevgep44.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %75 = load i32* %scevgep48.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_55)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %76 = load i32* %scevgep51.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_56)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %77 = load i32* %scevgep54.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %78 = load i32* %scevgep57.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %80 = load i32* %scevgep60.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %81 = load i32* %scevgep63.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* %82 = load i32* %scevgep66.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %127, i32* %scevgep45.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %128, i32* %scevgep47.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %129, i32* %scevgep50.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_66)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %130, i32* %scevgep53.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_67)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %131, i32* %scevgep56.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_68)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %132, i32* %scevgep59.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_69)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %133, i32* %scevgep62.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_70)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %134, i32* %scevgep65.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_71)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %137 = load i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_73)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %138 = load i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_74)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %139 = load i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %140 = load i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %141 = load i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %142 = load i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* %143 = load i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader25.i*/
/* store i32 %188, i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %189, i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %190, i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_84)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %191, i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_85)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %192, i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_86)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %193, i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_87)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %194, i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_88)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader25.i*/
/* store i32 %195, i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_89)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %.preheader.i8*/
/* %197 = load i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %.preheader.i8*/
/* store i32 %202, i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_140)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %ChenIDct.exit*/
/* %204 = load i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %ChenIDct.exit*/
/* store i32 %205, i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_143)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
memory_controller_write_enable = 1'd0;
end
/* decode_block: %208*/
/* store i32 0, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB22_147)
begin
memory_controller_write_enable = 1'd1;
end
/* decode_block: %211*/
/* store i32 255, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB24_149)
begin
memory_controller_write_enable = 1'd1;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
memory_controller_in = DecodeHuffman_memory_controller_in;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
memory_controller_in = buf_getv_memory_controller_in;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
memory_controller_in = DecodeHuffman_memory_controller_in;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
memory_controller_in = buf_getv_memory_controller_in;
end
/* decode_block: %24*/
/* store i32 %26, i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_19)
begin
memory_controller_in = decode_block_24_26;
end
/* decode_block: %.lr.ph.i*/
/* store i32 0, i32* %mptr.03.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB5_21)
begin
memory_controller_in = 32'd0;
end
/* decode_block: %44*/
/* store i32 %45, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_32)
begin
memory_controller_in = decode_block_44_45_reg;
end
/* decode_block: %52*/
/* store i32 %56, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_38)
begin
memory_controller_in = decode_block_52_56;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* store i32 %65, i32* %.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_46)
begin
memory_controller_in = decode_block_DecodeHuffMCU_exit_65;
end
/* decode_block: %69*/
/* store i32 %72, i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
memory_controller_in = decode_block_69_72;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %127, i32* %scevgep45.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
memory_controller_in = decode_block_IQuantize_exit_127;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %128, i32* %scevgep47.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
memory_controller_in = decode_block_IQuantize_exit_128;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %129, i32* %scevgep50.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_66)
begin
memory_controller_in = decode_block_IQuantize_exit_129_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %130, i32* %scevgep53.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_67)
begin
memory_controller_in = decode_block_IQuantize_exit_130_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %131, i32* %scevgep56.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_68)
begin
memory_controller_in = decode_block_IQuantize_exit_131_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %132, i32* %scevgep59.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_69)
begin
memory_controller_in = decode_block_IQuantize_exit_132_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %133, i32* %scevgep62.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_70)
begin
memory_controller_in = decode_block_IQuantize_exit_133_reg;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %134, i32* %scevgep65.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_71)
begin
memory_controller_in = decode_block_IQuantize_exit_134_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %188, i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
memory_controller_in = decode_block__preheader25_i_188;
end
/* decode_block: %.preheader25.i*/
/* store i32 %189, i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
memory_controller_in = decode_block__preheader25_i_189;
end
/* decode_block: %.preheader25.i*/
/* store i32 %190, i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_84)
begin
memory_controller_in = decode_block__preheader25_i_190_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %191, i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_85)
begin
memory_controller_in = decode_block__preheader25_i_191_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %192, i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_86)
begin
memory_controller_in = decode_block__preheader25_i_192_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %193, i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_87)
begin
memory_controller_in = decode_block__preheader25_i_193_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %194, i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_88)
begin
memory_controller_in = decode_block__preheader25_i_194_reg;
end
/* decode_block: %.preheader25.i*/
/* store i32 %195, i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_89)
begin
memory_controller_in = decode_block__preheader25_i_195_reg;
end
/* decode_block: %.preheader.i8*/
/* store i32 %202, i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_140)
begin
memory_controller_in = decode_block__preheader_i8_202_reg;
end
/* decode_block: %ChenIDct.exit*/
/* store i32 %205, i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_143)
begin
memory_controller_in = decode_block_ChenIDct_exit_205;
end
/* decode_block: %208*/
/* store i32 0, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB22_147)
begin
memory_controller_in = 32'd0;
end
/* decode_block: %211*/
/* store i32 255, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB24_149)
begin
memory_controller_in = 32'd255;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* decode_block: %0*/
/* %10 = call fastcc i32 @DecodeHuffman(i32* %4, i32 %6, i32* %7, i32* %8, i32* %9) nounwind*/
if (cur_state == LEGUP_function_call_6)
begin
memory_controller_size = DecodeHuffman_memory_controller_size;
end
/* decode_block: %12*/
/* %13 = call fastcc i32 @buf_getv(i32 %10) nounwind*/
if (cur_state == LEGUP_function_call_9)
begin
memory_controller_size = buf_getv_memory_controller_size;
end
/* decode_block: %34*/
/* %36 = call fastcc i32 @DecodeHuffman(i32* %27, i32 %35, i32* %29, i32* %30, i32* %31) nounwind*/
if (cur_state == LEGUP_function_call_26)
begin
memory_controller_size = DecodeHuffman_memory_controller_size;
end
/* decode_block: %44*/
/* %45 = call fastcc i32 @buf_getv(i32 %37) nounwind*/
if (cur_state == LEGUP_function_call_30)
begin
memory_controller_size = buf_getv_memory_controller_size;
end
/* decode_block: %0*/
/* %2 = load i8* %1, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB0_1)
begin
memory_controller_size = 2'd0;
end
/* decode_block: %0*/
/* %6 = load i32* %5, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB0_3)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %12*/
/* %16 = load i32* %15, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB1_11)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %19*/
/* %21 = load i32* %20, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB2_14)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %24*/
/* %25 = load i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_17)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %24*/
/* store i32 %26, i32* %HuffBuff, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB3_19)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.lr.ph.i*/
/* store i32 0, i32* %mptr.03.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB5_21)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %34*/
/* %35 = load i32* %28, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB7_23)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %44*/
/* store i32 %45, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_32)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %44*/
/* %49 = load i32* %48, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB9_33)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %52*/
/* %54 = load i32* %53, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_36)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %52*/
/* store i32 %56, i32* %46, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB10_38)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %63 = load i32* %scevgep.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_42)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* %65 = load i32* %64, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_44)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %DecodeHuffMCU.exit*/
/* store i32 %65, i32* %.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB14_46)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IZigzagMatrix.exit*/
/* %68 = load i8* %67, align 1, !tbaa !0*/
if (cur_state == LEGUP_F_decode_block_BB15_47)
begin
memory_controller_size = 2'd0;
end
/* decode_block: %69*/
/* %70 = load i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_50)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %69*/
/* %71 = load i32* %.01.i6, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_51)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %69*/
/* store i32 %72, i32* %mptr.02.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB16_53)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %73 = load i32* %scevgep44.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_54)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %75 = load i32* %scevgep48.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_55)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %76 = load i32* %scevgep51.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_56)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %77 = load i32* %scevgep54.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_57)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %78 = load i32* %scevgep57.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_58)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %80 = load i32* %scevgep60.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_59)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %81 = load i32* %scevgep63.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_60)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* %82 = load i32* %scevgep66.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_61)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %127, i32* %scevgep45.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_64)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %128, i32* %scevgep47.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_65)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %129, i32* %scevgep50.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_66)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %130, i32* %scevgep53.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_67)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %131, i32* %scevgep56.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_68)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %132, i32* %scevgep59.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_69)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %133, i32* %scevgep62.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_70)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %IQuantize.exit*/
/* store i32 %134, i32* %scevgep65.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB17_71)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %136 = load i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_72)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %137 = load i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_73)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %138 = load i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_74)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %139 = load i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_75)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %140 = load i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_76)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %141 = load i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_77)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %142 = load i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_78)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* %143 = load i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_79)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %188, i32* %scevgep42.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_82)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %189, i32* %scevgep41.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_83)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %190, i32* %scevgep39.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_84)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %191, i32* %scevgep37.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_85)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %192, i32* %scevgep35.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_86)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %193, i32* %scevgep33.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_87)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %194, i32* %scevgep31.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_88)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader25.i*/
/* store i32 %195, i32* %scevgep.i7, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB18_89)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader.i8*/
/* %197 = load i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_90)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %.preheader.i8*/
/* store i32 %202, i32* %aptr.023.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB19_140)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %ChenIDct.exit*/
/* %204 = load i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_141)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %ChenIDct.exit*/
/* store i32 %205, i32* %mptr.01.i2, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB20_143)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %PostshiftIDctMatrix.exit*/
/* %206 = load i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB21_144)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %208*/
/* store i32 0, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB22_147)
begin
memory_controller_size = 2'd2;
end
/* decode_block: %211*/
/* store i32 255, i32* %mptr.01.i, align 4, !tbaa !2*/
if (cur_state == LEGUP_F_decode_block_BB24_149)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module buf_getv
(
clk,
reset,
start,
finish,
return_val,
arg_n,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [5:0] LEGUP_0 = 6'd0;
parameter [5:0] LEGUP_F_buf_getv_BB0_1 = 6'd1;
parameter [5:0] LEGUP_F_buf_getv_BB0_2 = 6'd2;
parameter [5:0] LEGUP_F_buf_getv_BB0_3 = 6'd3;
parameter [5:0] LEGUP_F_buf_getv_BB1_4 = 6'd4;
parameter [5:0] LEGUP_F_buf_getv_BB2_5 = 6'd5;
parameter [5:0] LEGUP_F_buf_getv_BB2_6 = 6'd6;
parameter [5:0] LEGUP_F_buf_getv_BB2_7 = 6'd7;
parameter [5:0] LEGUP_F_buf_getv_BB3_8 = 6'd8;
parameter [5:0] LEGUP_F_buf_getv_BB3_9 = 6'd9;
parameter [5:0] LEGUP_F_buf_getv_BB3_10 = 6'd10;
parameter [5:0] LEGUP_F_buf_getv_BB3_11 = 6'd11;
parameter [5:0] LEGUP_F_buf_getv_BB3_12 = 6'd12;
parameter [5:0] LEGUP_F_buf_getv_BB3_13 = 6'd13;
parameter [5:0] LEGUP_F_buf_getv_BB4_14 = 6'd14;
parameter [5:0] LEGUP_F_buf_getv_BB4_15 = 6'd15;
parameter [5:0] LEGUP_F_buf_getv_BB4_16 = 6'd16;
parameter [5:0] LEGUP_F_buf_getv_BB4_17 = 6'd17;
parameter [5:0] LEGUP_F_buf_getv_BB5_18 = 6'd18;
parameter [5:0] LEGUP_F_buf_getv_BB6_19 = 6'd19;
parameter [5:0] LEGUP_F_buf_getv_BB7_20 = 6'd20;
parameter [5:0] LEGUP_F_buf_getv_BB7_21 = 6'd21;
parameter [5:0] LEGUP_F_buf_getv_BB7_22 = 6'd22;
parameter [5:0] LEGUP_F_buf_getv_BB7_23 = 6'd23;
parameter [5:0] LEGUP_F_buf_getv_BB7_24 = 6'd24;
parameter [5:0] LEGUP_F_buf_getv_BB8_25 = 6'd25;
parameter [5:0] LEGUP_F_buf_getv_BB8_26 = 6'd26;
parameter [5:0] LEGUP_F_buf_getv_BB8_27 = 6'd27;
parameter [5:0] LEGUP_F_buf_getv_BB8_28 = 6'd28;
parameter [5:0] LEGUP_F_buf_getv_BB8_29 = 6'd29;
parameter [5:0] LEGUP_F_buf_getv_BB8_30 = 6'd30;
parameter [5:0] LEGUP_F_buf_getv_BB9_31 = 6'd31;
parameter [5:0] LEGUP_F_buf_getv_BB9_32 = 6'd32;
parameter [5:0] LEGUP_F_buf_getv_BB9_33 = 6'd33;
parameter [5:0] LEGUP_F_buf_getv_BB9_34 = 6'd34;
parameter [5:0] LEGUP_F_buf_getv_BB10_35 = 6'd35;
parameter [5:0] LEGUP_F_buf_getv_BB10_36 = 6'd36;
parameter [5:0] LEGUP_F_buf_getv_BB10_37 = 6'd37;
parameter [5:0] LEGUP_F_buf_getv_BB10_38 = 6'd38;
parameter [5:0] LEGUP_F_buf_getv_BB11_39 = 6'd39;
parameter [5:0] LEGUP_F_buf_getv_BB12_40 = 6'd40;
parameter [5:0] LEGUP_F_buf_getv_BB12_41 = 6'd41;
parameter [5:0] LEGUP_F_buf_getv_BB13_42 = 6'd42;
parameter [5:0] LEGUP_F_buf_getv_BB14_43 = 6'd43;
parameter [5:0] LEGUP_F_buf_getv_BB14_44 = 6'd44;
parameter [5:0] LEGUP_F_buf_getv_BB14_45 = 6'd45;
parameter [5:0] LEGUP_F_buf_getv_BB14_46 = 6'd46;
parameter [5:0] LEGUP_F_buf_getv_BB14_47 = 6'd47;
parameter [5:0] LEGUP_F_buf_getv_BB15_48 = 6'd48;
parameter [5:0] LEGUP_F_buf_getv_BB15_49 = 6'd49;
parameter [5:0] LEGUP_F_buf_getv_BB15_50 = 6'd50;
parameter [5:0] LEGUP_F_buf_getv_BB15_51 = 6'd51;
parameter [5:0] LEGUP_F_buf_getv_BB15_52 = 6'd52;
parameter [5:0] LEGUP_F_buf_getv_BB16_53 = 6'd53;
input clk;
input reset;
input start;
output reg finish;
output reg [31:0] return_val;
input [31:0] arg_n;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [5:0] cur_state;
reg [31:0] buf_getv_0_1;
reg [31:0] buf_getv_0_1_reg;
reg [31:0] buf_getv_0_2;
reg [31:0] buf_getv_0_3;
reg [31:0] buf_getv_0_3_reg;
reg [31:0] buf_getv_4_5;
reg [31:0] buf_getv_4_5_reg;
reg [31:0] buf_getv_4_indvar;
reg [31:0] buf_getv_4_indvar_reg;
reg [31:0] buf_getv_4_tmp;
reg [31:0] buf_getv_4_p_0;
reg [31:0] buf_getv_4_p_0_reg;
reg buf_getv_4_6;
reg buf_getv_7_8;
reg buf_getv_7_8_reg;
reg [31:0] buf_getv_7_9;
reg [31:0] buf_getv_7_9_reg;
reg [31:0] buf_getv_10_11;
reg [31:0] buf_getv_10_11_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_10_12;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_10_12_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_10_13;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_10_13_reg;
reg [7:0] buf_getv_10_14;
reg buf_getv_10_15;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_16_17;
reg [7:0] buf_getv_16_18;
reg [7:0] buf_getv_16_18_reg;
reg buf_getv_16_19;
reg [7:0] buf_getv_22_temp_0_in_i;
reg [31:0] buf_getv_22_temp_0_i;
reg [31:0] buf_getv_pgetc_exit__0_i;
reg [31:0] buf_getv_pgetc_exit_23;
reg [31:0] buf_getv_pgetc_exit_24;
reg [31:0] buf_getv_pgetc_exit_25;
reg [31:0] buf_getv_pgetc_exit_25_reg;
reg [31:0] buf_getv_pgetc_exit_26;
reg [31:0] buf_getv_pgetc_exit_26_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_pgetc_exit_27;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_pgetc_exit_27_reg;
reg [31:0] buf_getv_pgetc_exit_28;
reg [31:0] buf_getv_pgetc_exit_29;
reg [31:0] buf_getv_30_31;
reg [31:0] buf_getv_30_31_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_30_32;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_30_32_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_30_33;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_30_33_reg;
reg [7:0] buf_getv_30_34;
reg buf_getv_30_35;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_36_37;
reg [7:0] buf_getv_36_38;
reg [7:0] buf_getv_36_38_reg;
reg buf_getv_36_39;
reg [31:0] buf_getv_40__pre_pre;
reg [31:0] buf_getv_42__pre;
reg [7:0] buf_getv_42_temp_0_in_i1;
reg [31:0] buf_getv_42_temp_0_i2;
reg [31:0] buf_getv_pgetc_exit4_43;
reg [31:0] buf_getv_pgetc_exit4__0_i3;
reg [31:0] buf_getv_pgetc_exit4_44;
reg [31:0] buf_getv_pgetc_exit4_45;
reg [31:0] buf_getv_pgetc_exit4_45_reg;
reg [31:0] buf_getv_pgetc_exit4_indvar_next;
reg [31:0] buf_getv_pgetc_exit4_indvar_next_reg;
reg buf_getv_46_47;
reg [31:0] buf_getv_48_49;
reg [31:0] buf_getv_48_49_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_48_50;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_48_50_reg;
reg [31:0] buf_getv_48_51;
reg [31:0] buf_getv_48_52;
reg [31:0] buf_getv_53_54;
reg [31:0] buf_getv_53_54_reg;
reg [31:0] buf_getv_53_55;
reg [31:0] buf_getv_53_56;
reg [31:0] buf_getv_53_57;
reg [31:0] buf_getv_53_57_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_53_58;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] buf_getv_53_58_reg;
reg [31:0] buf_getv_53_59;
reg [31:0] buf_getv_53_60;
reg [31:0] buf_getv_61__0;
reg [31:0] buf_getv_signed_multiply_32_0_op0;
reg [31:0] buf_getv_signed_multiply_32_0_op1;
reg [31:0] buf_getv_signed_multiply_32_0;
reg [31:0] buf_getv_4_5_phi_temp;
reg [31:0] buf_getv_4_indvar_phi_temp;
reg [7:0] buf_getv_22_temp_0_in_i_phi_temp;
reg [31:0] buf_getv_pgetc_exit__0_i_phi_temp;
reg [31:0] buf_getv_61__0_phi_temp;
reg [31:0] buf_getv_42__pre_phi_temp;
reg [7:0] buf_getv_42_temp_0_in_i1_phi_temp;
reg [31:0] buf_getv_pgetc_exit4_43_phi_temp;
reg [31:0] buf_getv_pgetc_exit4__0_i3_phi_temp;
/* Unsynthesizable Statements */
always @(posedge clk) begin
/* buf_getv: %20*/
/* %21 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str30, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_buf_getv_BB5_18)
begin
$write("Unanticipated marker detected.\n");
end
/* buf_getv: %40*/
/* %41 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str30, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_buf_getv_BB10_35)
begin
$write("Unanticipated marker detected.\n");
end
end
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 6'd0;
if (^reset !== 1'bX && ^(6'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB0_3 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB1_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB1_4 & memory_controller_waitrequest == 1'd0 & buf_getv_4_6 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB1_4 & memory_controller_waitrequest == 1'd0 & buf_getv_4_6 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB13_42;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB13_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB2_6;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB2_6;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_6 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB2_7;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB2_7;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB2_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_7 & memory_controller_waitrequest == 1'd0 & buf_getv_7_8_reg == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_8;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB2_7 & memory_controller_waitrequest == 1'd0 & buf_getv_7_8_reg == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_25;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_8;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_8 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB3_9;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_9;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_9 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB3_10;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_10;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_10 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB3_11;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_11;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB3_12;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_12;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_12 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_13 & memory_controller_waitrequest == 1'd0 & buf_getv_10_15 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB4_14;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB3_13 & memory_controller_waitrequest == 1'd0 & buf_getv_10_15 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB4_14;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB4_15;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB4_15;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_15 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB4_16;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB4_16;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_16 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB4_17;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB4_17;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB4_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_17 & memory_controller_waitrequest == 1'd0 & buf_getv_16_19 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_20;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB4_17 & memory_controller_waitrequest == 1'd0 & buf_getv_16_19 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB5_18;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB5_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB5_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB5_18;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB5_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB5_18 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB6_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB6_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB7_20;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_20;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_20 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB7_21;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_21;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_21 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB7_22;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_22;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_22 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_23 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB7_24 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_25;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_25 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_26;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_26;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_26 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_27;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_27;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_27 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_28;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_28;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_28 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_29;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_29;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_29 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB8_30;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB8_30;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB8_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_30 & memory_controller_waitrequest == 1'd0 & buf_getv_30_35 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB9_31;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB8_30 & memory_controller_waitrequest == 1'd0 & buf_getv_30_35 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB9_31;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_32 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB9_33;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB9_33;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB9_34;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB9_34;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB9_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_34 & memory_controller_waitrequest == 1'd0 & buf_getv_36_39 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB12_40;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB12_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB9_34 & memory_controller_waitrequest == 1'd0 & buf_getv_36_39 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB10_35;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB10_35;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_35 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_36 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB10_37;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB10_37;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB10_38;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_38 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB10_38;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB10_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB10_38 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB11_39 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB11_39;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB11_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB11_39 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB12_40;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB12_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB12_40 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB12_40;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB12_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB12_40 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB12_41;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB12_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB12_41 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB12_41;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB12_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB12_41 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB13_42 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB13_42;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB13_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB13_42 & memory_controller_waitrequest == 1'd0 & buf_getv_46_47 == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB13_42 & memory_controller_waitrequest == 1'd0 & buf_getv_46_47 == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_43 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_43 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_44 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_44 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_45 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_45 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB14_46;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_46 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_46;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_46 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB14_47;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_47 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB14_47;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB14_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB14_47 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_48 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_48 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB15_49;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_49 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB15_49;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_49 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB15_50;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_50 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB15_50;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_50 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB15_51;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_51 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB15_51;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_51 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB15_52;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_52 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB15_52;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB15_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB15_52 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_buf_getv_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB16_53 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_buf_getv_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_buf_getv_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_buf_getv_BB16_53 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* buf_getv: %0*/
/* %1 = add nsw i32 %n, -1*/
begin
buf_getv_0_1 = arg_n + -32'd1;
end
end
always @(posedge clk) begin
/* buf_getv: %0*/
/* %1 = add nsw i32 %n, -1*/
if (cur_state == LEGUP_F_buf_getv_BB0_1)
begin
buf_getv_0_1_reg <= buf_getv_0_1;
if (^reset !== 1'bX && ^(buf_getv_0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_0_1_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %0*/
/* %2 = load i32* @read_position, align 4, !tbaa !0*/
begin
buf_getv_0_2 = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %0*/
/* %3 = sub nsw i32 %1, %2*/
begin
buf_getv_0_3 = buf_getv_0_1_reg - buf_getv_0_2;
end
end
always @(posedge clk) begin
/* buf_getv: %0*/
/* %3 = sub nsw i32 %1, %2*/
if (cur_state == LEGUP_F_buf_getv_BB0_3)
begin
buf_getv_0_3_reg <= buf_getv_0_3;
if (^reset !== 1'bX && ^(buf_getv_0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_0_3_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5 = buf_getv_4_5_phi_temp;
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
else if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5 = buf_getv_4_5_phi_temp;
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
else if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5 = buf_getv_4_5_phi_temp;
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
else /* if (cur_state == LEGUP_F_buf_getv_BB1_4) */
begin
buf_getv_4_5 = buf_getv_4_5_phi_temp;
end
end
always @(posedge clk) begin
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5_reg <= buf_getv_4_5;
if (^reset !== 1'bX && ^(buf_getv_4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_reg"); $finish; end
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5_reg <= buf_getv_4_5;
if (^reset !== 1'bX && ^(buf_getv_4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_reg"); $finish; end
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5_reg <= buf_getv_4_5;
if (^reset !== 1'bX && ^(buf_getv_4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_reg"); $finish; end
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5_reg <= buf_getv_4_5;
if (^reset !== 1'bX && ^(buf_getv_4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_reg"); $finish; end
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_5_reg <= buf_getv_4_5;
if (^reset !== 1'bX && ^(buf_getv_4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_indvar = buf_getv_4_indvar_phi_temp;
end
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
else /* if (cur_state == LEGUP_F_buf_getv_BB1_4) */
begin
buf_getv_4_indvar = buf_getv_4_indvar_phi_temp;
end
end
always @(posedge clk) begin
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_indvar_reg <= buf_getv_4_indvar;
if (^reset !== 1'bX && ^(buf_getv_4_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_indvar_reg"); $finish; end
end
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_indvar_reg <= buf_getv_4_indvar;
if (^reset !== 1'bX && ^(buf_getv_4_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_indvar_reg"); $finish; end
end
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_indvar_reg <= buf_getv_4_indvar;
if (^reset !== 1'bX && ^(buf_getv_4_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_indvar_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %4*/
/* %tmp = mul i32 %indvar, -8*/
begin
buf_getv_4_tmp = buf_getv_signed_multiply_32_0;
end
end
always @(*) begin
/* buf_getv: %4*/
/* %p.0 = add i32 %3, %tmp*/
begin
buf_getv_4_p_0 = buf_getv_0_3_reg + buf_getv_4_tmp;
end
end
always @(posedge clk) begin
/* buf_getv: %4*/
/* %p.0 = add i32 %3, %tmp*/
if (cur_state == LEGUP_F_buf_getv_BB1_4)
begin
buf_getv_4_p_0_reg <= buf_getv_4_p_0;
if (^reset !== 1'bX && ^(buf_getv_4_p_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_p_0_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %4*/
/* %6 = icmp sgt i32 %p.0, 0*/
begin
buf_getv_4_6 = $signed(buf_getv_4_p_0) > $signed(32'd0);
end
end
always @(*) begin
/* buf_getv: %7*/
/* %8 = icmp sgt i32 %5, 23*/
begin
buf_getv_7_8 = $signed(buf_getv_4_5_reg) > $signed(32'd23);
end
end
always @(posedge clk) begin
/* buf_getv: %7*/
/* %8 = icmp sgt i32 %5, 23*/
if (cur_state == LEGUP_F_buf_getv_BB2_5)
begin
buf_getv_7_8_reg <= buf_getv_7_8;
if (^reset !== 1'bX && ^(buf_getv_7_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_7_8_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
begin
buf_getv_7_9 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB2_7)
begin
buf_getv_7_9_reg <= buf_getv_7_9;
if (^reset !== 1'bX && ^(buf_getv_7_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_7_9_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %10*/
/* %11 = shl i32 %9, %p.0*/
begin
buf_getv_10_11 = buf_getv_7_9_reg <<< buf_getv_4_p_0_reg % 32;
end
end
always @(posedge clk) begin
/* buf_getv: %10*/
/* %11 = shl i32 %9, %p.0*/
if (cur_state == LEGUP_F_buf_getv_BB3_8)
begin
buf_getv_10_11_reg <= buf_getv_10_11;
if (^reset !== 1'bX && ^(buf_getv_10_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_10_11_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
begin
buf_getv_10_12 = memory_controller_out[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
end
always @(posedge clk) begin
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
buf_getv_10_12_reg <= buf_getv_10_12;
if (^reset !== 1'bX && ^(buf_getv_10_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_10_12_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %10*/
/* %13 = getelementptr inbounds i8* %12, i32 1*/
begin
buf_getv_10_13 = buf_getv_10_12 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* buf_getv: %10*/
/* %13 = getelementptr inbounds i8* %12, i32 1*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
buf_getv_10_13_reg <= buf_getv_10_13;
if (^reset !== 1'bX && ^(buf_getv_10_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_10_13_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %10*/
/* %14 = load i8* %12, align 1, !tbaa !1*/
begin
buf_getv_10_14 = memory_controller_out[7:0];
end
end
always @(*) begin
/* buf_getv: %10*/
/* %15 = icmp eq i8 %14, -1*/
begin
buf_getv_10_15 = buf_getv_10_14 == -8'd1;
end
end
always @(*) begin
/* buf_getv: %16*/
/* %17 = getelementptr inbounds i8* %12, i32 2*/
begin
buf_getv_16_17 = buf_getv_10_12_reg + 1 * 32'd2;
end
end
always @(*) begin
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
begin
buf_getv_16_18 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB4_17)
begin
buf_getv_16_18_reg <= buf_getv_16_18;
if (^reset !== 1'bX && ^(buf_getv_16_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_16_18_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %16*/
/* %19 = icmp eq i8 %18, 0*/
begin
buf_getv_16_19 = buf_getv_16_18 == 8'd0;
end
end
always @(*) begin
/* buf_getv: %22*/
/* %temp.0.in.i = phi i8 [ %18, %20 ], [ %14, %10 ]*/
begin
buf_getv_22_temp_0_in_i = buf_getv_22_temp_0_in_i_phi_temp;
end
end
always @(*) begin
/* buf_getv: %22*/
/* %temp.0.i = zext i8 %temp.0.in.i to i32*/
begin
buf_getv_22_temp_0_i = buf_getv_22_temp_0_in_i;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %.0.i = phi i32 [ %temp.0.i, %22 ], [ 255, %16 ]*/
begin
buf_getv_pgetc_exit__0_i = buf_getv_pgetc_exit__0_i_phi_temp;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %23 = sub nsw i32 8, %p.0*/
begin
buf_getv_pgetc_exit_23 = 32'd8 - buf_getv_4_p_0_reg;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %24 = lshr i32 %.0.i, %23*/
begin
buf_getv_pgetc_exit_24 = buf_getv_pgetc_exit__0_i >>> buf_getv_pgetc_exit_23 % 32;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %25 = or i32 %24, %11*/
begin
buf_getv_pgetc_exit_25 = buf_getv_pgetc_exit_24 | buf_getv_10_11_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit*/
/* %25 = or i32 %24, %11*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
buf_getv_pgetc_exit_25_reg <= buf_getv_pgetc_exit_25;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit_25_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %26 = sub nsw i32 7, %p.0*/
begin
buf_getv_pgetc_exit_26 = 32'd7 - buf_getv_4_p_0_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit*/
/* %26 = sub nsw i32 7, %p.0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
buf_getv_pgetc_exit_26_reg <= buf_getv_pgetc_exit_26;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit_26_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %27 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
begin
buf_getv_pgetc_exit_27 = `TAG_g_lmask_a + 4 * buf_getv_0_1_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit*/
/* %27 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
buf_getv_pgetc_exit_27_reg <= buf_getv_pgetc_exit_27;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit_27_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %28 = load i32* %27, align 4, !tbaa !0*/
begin
buf_getv_pgetc_exit_28 = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %pgetc.exit*/
/* %29 = and i32 %25, %28*/
begin
buf_getv_pgetc_exit_29 = buf_getv_pgetc_exit_25_reg & buf_getv_pgetc_exit_28;
end
end
always @(*) begin
/* buf_getv: %30*/
/* %31 = shl i32 %9, 8*/
begin
buf_getv_30_31 = buf_getv_7_9_reg <<< 32'd8 % 32;
end
end
always @(posedge clk) begin
/* buf_getv: %30*/
/* %31 = shl i32 %9, 8*/
if (cur_state == LEGUP_F_buf_getv_BB8_25)
begin
buf_getv_30_31_reg <= buf_getv_30_31;
if (^reset !== 1'bX && ^(buf_getv_30_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_30_31_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
begin
buf_getv_30_32 = memory_controller_out[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
end
always @(posedge clk) begin
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
buf_getv_30_32_reg <= buf_getv_30_32;
if (^reset !== 1'bX && ^(buf_getv_30_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_30_32_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %30*/
/* %33 = getelementptr inbounds i8* %32, i32 1*/
begin
buf_getv_30_33 = buf_getv_30_32 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* buf_getv: %30*/
/* %33 = getelementptr inbounds i8* %32, i32 1*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
buf_getv_30_33_reg <= buf_getv_30_33;
if (^reset !== 1'bX && ^(buf_getv_30_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_30_33_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %30*/
/* %34 = load i8* %32, align 1, !tbaa !1*/
begin
buf_getv_30_34 = memory_controller_out[7:0];
end
end
always @(*) begin
/* buf_getv: %30*/
/* %35 = icmp eq i8 %34, -1*/
begin
buf_getv_30_35 = buf_getv_30_34 == -8'd1;
end
end
always @(*) begin
/* buf_getv: %36*/
/* %37 = getelementptr inbounds i8* %32, i32 2*/
begin
buf_getv_36_37 = buf_getv_30_32_reg + 1 * 32'd2;
end
end
always @(*) begin
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
begin
buf_getv_36_38 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB9_34)
begin
buf_getv_36_38_reg <= buf_getv_36_38;
if (^reset !== 1'bX && ^(buf_getv_36_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_36_38_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %36*/
/* %39 = icmp eq i8 %38, 0*/
begin
buf_getv_36_39 = buf_getv_36_38 == 8'd0;
end
end
always @(*) begin
/* buf_getv: %40*/
/* %.pre.pre = load i32* @read_position, align 4, !tbaa !0*/
begin
buf_getv_40__pre_pre = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %42*/
/* %.pre = phi i32 [ %.pre.pre, %40 ], [ %5, %30 ]*/
begin
buf_getv_42__pre = buf_getv_42__pre_phi_temp;
end
end
always @(*) begin
/* buf_getv: %42*/
/* %temp.0.in.i1 = phi i8 [ %38, %40 ], [ %34, %30 ]*/
begin
buf_getv_42_temp_0_in_i1 = buf_getv_42_temp_0_in_i1_phi_temp;
end
end
always @(*) begin
/* buf_getv: %42*/
/* %temp.0.i2 = zext i8 %temp.0.in.i1 to i32*/
begin
buf_getv_42_temp_0_i2 = buf_getv_42_temp_0_in_i1;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit4*/
/* %43 = phi i32 [ %.pre, %42 ], [ %5, %36 ]*/
begin
buf_getv_pgetc_exit4_43 = buf_getv_pgetc_exit4_43_phi_temp;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit4*/
/* %.0.i3 = phi i32 [ %temp.0.i2, %42 ], [ 255, %36 ]*/
begin
buf_getv_pgetc_exit4__0_i3 = buf_getv_pgetc_exit4__0_i3_phi_temp;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit4*/
/* %44 = or i32 %.0.i3, %31*/
begin
buf_getv_pgetc_exit4_44 = buf_getv_pgetc_exit4__0_i3 | buf_getv_30_31_reg;
end
end
always @(*) begin
/* buf_getv: %pgetc.exit4*/
/* %45 = add nsw i32 %43, 8*/
begin
buf_getv_pgetc_exit4_45 = buf_getv_pgetc_exit4_43 + 32'd8;
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit4*/
/* %45 = add nsw i32 %43, 8*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
buf_getv_pgetc_exit4_45_reg <= buf_getv_pgetc_exit4_45;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit4_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4_45_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %pgetc.exit4*/
/* %indvar.next = add i32 %indvar, 1*/
begin
buf_getv_pgetc_exit4_indvar_next = buf_getv_4_indvar_reg + 32'd1;
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit4*/
/* %indvar.next = add i32 %indvar, 1*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
buf_getv_pgetc_exit4_indvar_next_reg <= buf_getv_pgetc_exit4_indvar_next;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit4_indvar_next) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4_indvar_next_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %46*/
/* %47 = icmp eq i32 %p.0, 0*/
begin
buf_getv_46_47 = buf_getv_4_p_0_reg == 32'd0;
end
end
always @(*) begin
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
begin
buf_getv_48_49 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_46)
begin
buf_getv_48_49_reg <= buf_getv_48_49;
if (^reset !== 1'bX && ^(buf_getv_48_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_48_49_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %48*/
/* %50 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
begin
buf_getv_48_50 = `TAG_g_lmask_a + 4 * buf_getv_0_1_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %48*/
/* %50 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
buf_getv_48_50_reg <= buf_getv_48_50;
if (^reset !== 1'bX && ^(buf_getv_48_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_48_50_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %48*/
/* %51 = load i32* %50, align 4, !tbaa !0*/
begin
buf_getv_48_51 = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %48*/
/* %52 = and i32 %51, %49*/
begin
buf_getv_48_52 = buf_getv_48_51 & buf_getv_48_49_reg;
end
end
always @(*) begin
/* buf_getv: %53*/
/* %54 = sub nsw i32 0, %p.0*/
begin
buf_getv_53_54 = 32'd0 - buf_getv_4_p_0_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %53*/
/* %54 = sub nsw i32 0, %p.0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
buf_getv_53_54_reg <= buf_getv_53_54;
if (^reset !== 1'bX && ^(buf_getv_53_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_53_54_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %53*/
/* %55 = xor i32 %p.0, -1*/
begin
buf_getv_53_55 = buf_getv_4_p_0_reg ^ -32'd1;
end
end
always @(*) begin
/* buf_getv: %53*/
/* %56 = load i32* @current_read_byte, align 4, !tbaa !0*/
begin
buf_getv_53_56 = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %53*/
/* %57 = lshr i32 %56, %54*/
begin
buf_getv_53_57 = buf_getv_53_56 >>> buf_getv_53_54_reg % 32;
end
end
always @(posedge clk) begin
/* buf_getv: %53*/
/* %57 = lshr i32 %56, %54*/
if (cur_state == LEGUP_F_buf_getv_BB15_51)
begin
buf_getv_53_57_reg <= buf_getv_53_57;
if (^reset !== 1'bX && ^(buf_getv_53_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_53_57_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %53*/
/* %58 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
begin
buf_getv_53_58 = `TAG_g_lmask_a + 4 * buf_getv_0_1_reg;
end
end
always @(posedge clk) begin
/* buf_getv: %53*/
/* %58 = getelementptr inbounds [32 x i32]* @lmask, i32 0, i32 %1*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
buf_getv_53_58_reg <= buf_getv_53_58;
if (^reset !== 1'bX && ^(buf_getv_53_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_53_58_reg"); $finish; end
end
end
always @(*) begin
/* buf_getv: %53*/
/* %59 = load i32* %58, align 4, !tbaa !0*/
begin
buf_getv_53_59 = memory_controller_out[31:0];
end
end
always @(*) begin
/* buf_getv: %53*/
/* %60 = and i32 %57, %59*/
begin
buf_getv_53_60 = buf_getv_53_57_reg & buf_getv_53_59;
end
end
always @(*) begin
/* buf_getv: %61*/
/* %.0 = phi i32 [ %29, %pgetc.exit ], [ %60, %53 ], [ %52, %48 ]*/
begin
buf_getv_61__0 = buf_getv_61__0_phi_temp;
end
end
always @(*) begin
/* buf_getv: %4*/
/* %tmp = mul i32 %indvar, -8*/
begin
buf_getv_signed_multiply_32_0_op0 = buf_getv_4_indvar;
end
end
always @(*) begin
/* buf_getv: %4*/
/* %tmp = mul i32 %indvar, -8*/
if (reset) begin buf_getv_signed_multiply_32_0_op1 = 0; end
begin
buf_getv_signed_multiply_32_0_op1 = -32'd8;
end
end
always @(*) begin
buf_getv_signed_multiply_32_0 = buf_getv_signed_multiply_32_0_op0 * buf_getv_signed_multiply_32_0_op1;
end
always @(posedge clk) begin
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB0_3 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_4_5_phi_temp <= buf_getv_0_2;
if (^reset !== 1'bX && ^(buf_getv_0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_phi_temp"); $finish; end
end
/* buf_getv: %4*/
/* %5 = phi i32 [ %45, %pgetc.exit4 ], [ %2, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB12_41 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_4_5_phi_temp <= buf_getv_pgetc_exit4_45_reg;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit4_45_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_5_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB0_3 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_4_indvar_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_indvar_phi_temp"); $finish; end
end
/* buf_getv: %4*/
/* %indvar = phi i32 [ %indvar.next, %pgetc.exit4 ], [ 0, %0 ]*/
if (cur_state == LEGUP_F_buf_getv_BB12_41 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_4_indvar_phi_temp <= buf_getv_pgetc_exit4_indvar_next_reg;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit4_indvar_next_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_4_indvar_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %22*/
/* %temp.0.in.i = phi i8 [ %18, %20 ], [ %14, %10 ]*/
if (cur_state == LEGUP_F_buf_getv_BB3_13 & memory_controller_waitrequest == 1'd0 & buf_getv_10_15 == 1'd0)
begin
buf_getv_22_temp_0_in_i_phi_temp <= buf_getv_10_14;
if (^reset !== 1'bX && ^(buf_getv_10_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_22_temp_0_in_i_phi_temp"); $finish; end
end
/* buf_getv: %22*/
/* %temp.0.in.i = phi i8 [ %18, %20 ], [ %14, %10 ]*/
if (cur_state == LEGUP_F_buf_getv_BB5_18 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_22_temp_0_in_i_phi_temp <= buf_getv_16_18_reg;
if (^reset !== 1'bX && ^(buf_getv_16_18_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_22_temp_0_in_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit*/
/* %.0.i = phi i32 [ %temp.0.i, %22 ], [ 255, %16 ]*/
if (cur_state == LEGUP_F_buf_getv_BB4_17 & memory_controller_waitrequest == 1'd0 & buf_getv_16_19 == 1'd1)
begin
buf_getv_pgetc_exit__0_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit__0_i_phi_temp"); $finish; end
end
/* buf_getv: %pgetc.exit*/
/* %.0.i = phi i32 [ %temp.0.i, %22 ], [ 255, %16 ]*/
if (cur_state == LEGUP_F_buf_getv_BB6_19 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_pgetc_exit__0_i_phi_temp <= buf_getv_22_temp_0_i;
if (^reset !== 1'bX && ^(buf_getv_22_temp_0_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit__0_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %61*/
/* %.0 = phi i32 [ %29, %pgetc.exit ], [ %60, %53 ], [ %52, %48 ]*/
if (cur_state == LEGUP_F_buf_getv_BB7_24 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_61__0_phi_temp <= buf_getv_pgetc_exit_29;
if (^reset !== 1'bX && ^(buf_getv_pgetc_exit_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_61__0_phi_temp"); $finish; end
end
/* buf_getv: %61*/
/* %.0 = phi i32 [ %29, %pgetc.exit ], [ %60, %53 ], [ %52, %48 ]*/
if (cur_state == LEGUP_F_buf_getv_BB14_47 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_61__0_phi_temp <= buf_getv_48_52;
if (^reset !== 1'bX && ^(buf_getv_48_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_61__0_phi_temp"); $finish; end
end
/* buf_getv: %61*/
/* %.0 = phi i32 [ %29, %pgetc.exit ], [ %60, %53 ], [ %52, %48 ]*/
if (cur_state == LEGUP_F_buf_getv_BB15_52 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_61__0_phi_temp <= buf_getv_53_60;
if (^reset !== 1'bX && ^(buf_getv_53_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_61__0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %42*/
/* %.pre = phi i32 [ %.pre.pre, %40 ], [ %5, %30 ]*/
if (cur_state == LEGUP_F_buf_getv_BB8_30 & memory_controller_waitrequest == 1'd0 & buf_getv_30_35 == 1'd0)
begin
buf_getv_42__pre_phi_temp <= buf_getv_4_5_reg;
if (^reset !== 1'bX && ^(buf_getv_4_5_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_42__pre_phi_temp"); $finish; end
end
/* buf_getv: %42*/
/* %.pre = phi i32 [ %.pre.pre, %40 ], [ %5, %30 ]*/
if (cur_state == LEGUP_F_buf_getv_BB10_38 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_42__pre_phi_temp <= buf_getv_40__pre_pre;
if (^reset !== 1'bX && ^(buf_getv_40__pre_pre) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_42__pre_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %42*/
/* %temp.0.in.i1 = phi i8 [ %38, %40 ], [ %34, %30 ]*/
if (cur_state == LEGUP_F_buf_getv_BB8_30 & memory_controller_waitrequest == 1'd0 & buf_getv_30_35 == 1'd0)
begin
buf_getv_42_temp_0_in_i1_phi_temp <= buf_getv_30_34;
if (^reset !== 1'bX && ^(buf_getv_30_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_42_temp_0_in_i1_phi_temp"); $finish; end
end
/* buf_getv: %42*/
/* %temp.0.in.i1 = phi i8 [ %38, %40 ], [ %34, %30 ]*/
if (cur_state == LEGUP_F_buf_getv_BB10_38 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_42_temp_0_in_i1_phi_temp <= buf_getv_36_38_reg;
if (^reset !== 1'bX && ^(buf_getv_36_38_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_42_temp_0_in_i1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit4*/
/* %43 = phi i32 [ %.pre, %42 ], [ %5, %36 ]*/
if (cur_state == LEGUP_F_buf_getv_BB9_34 & memory_controller_waitrequest == 1'd0 & buf_getv_36_39 == 1'd1)
begin
buf_getv_pgetc_exit4_43_phi_temp <= buf_getv_4_5_reg;
if (^reset !== 1'bX && ^(buf_getv_4_5_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4_43_phi_temp"); $finish; end
end
/* buf_getv: %pgetc.exit4*/
/* %43 = phi i32 [ %.pre, %42 ], [ %5, %36 ]*/
if (cur_state == LEGUP_F_buf_getv_BB11_39 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_pgetc_exit4_43_phi_temp <= buf_getv_42__pre;
if (^reset !== 1'bX && ^(buf_getv_42__pre) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4_43_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* buf_getv: %pgetc.exit4*/
/* %.0.i3 = phi i32 [ %temp.0.i2, %42 ], [ 255, %36 ]*/
if (cur_state == LEGUP_F_buf_getv_BB9_34 & memory_controller_waitrequest == 1'd0 & buf_getv_36_39 == 1'd1)
begin
buf_getv_pgetc_exit4__0_i3_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4__0_i3_phi_temp"); $finish; end
end
/* buf_getv: %pgetc.exit4*/
/* %.0.i3 = phi i32 [ %temp.0.i2, %42 ], [ 255, %36 ]*/
if (cur_state == LEGUP_F_buf_getv_BB11_39 & memory_controller_waitrequest == 1'd0)
begin
buf_getv_pgetc_exit4__0_i3_phi_temp <= buf_getv_42_temp_0_i2;
if (^reset !== 1'bX && ^(buf_getv_42_temp_0_i2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to buf_getv_pgetc_exit4__0_i3_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* buf_getv: %61*/
/* ret i32 %.0*/
if (cur_state == LEGUP_F_buf_getv_BB16_53)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
return_val <= 0;
if (^reset !== 1'bX && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
/* buf_getv: %61*/
/* ret i32 %.0*/
if (cur_state == LEGUP_F_buf_getv_BB16_53)
begin
return_val <= buf_getv_61__0;
if (^reset !== 1'bX && ^(buf_getv_61__0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* buf_getv: %0*/
/* %2 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB0_1)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB2_5)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_8)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %10*/
/* store i8* %13, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %10*/
/* %14 = load i8* %12, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB3_11)
begin
memory_controller_address = buf_getv_10_12_reg;
end
/* buf_getv: %16*/
/* store i8* %17, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB4_14)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB4_15)
begin
memory_controller_address = buf_getv_10_13_reg;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %.0.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %26, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_21)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %pgetc.exit*/
/* %28 = load i32* %27, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_22)
begin
memory_controller_address = buf_getv_pgetc_exit_27_reg;
end
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_25)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %30*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %30*/
/* %34 = load i8* %32, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB8_28)
begin
memory_controller_address = buf_getv_30_32_reg;
end
/* buf_getv: %36*/
/* store i8* %37, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB9_31)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB9_32)
begin
memory_controller_address = buf_getv_30_33_reg;
end
/* buf_getv: %40*/
/* %.pre.pre = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB10_36)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %44, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %45, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_41)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %48*/
/* store i32 -1, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_44)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* buf_getv: %48*/
/* %51 = load i32* %50, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_45)
begin
memory_controller_address = buf_getv_48_50_reg;
end
/* buf_getv: %53*/
/* store i32 %55, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* buf_getv: %53*/
/* %56 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_49)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* buf_getv: %53*/
/* %59 = load i32* %58, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_50)
begin
memory_controller_address = buf_getv_53_58_reg;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* buf_getv: %0*/
/* %2 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB0_1)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB2_5)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_8)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %10*/
/* store i8* %13, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %10*/
/* %14 = load i8* %12, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB3_11)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %16*/
/* store i8* %17, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB4_14)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB4_15)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %.0.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %26, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_21)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %pgetc.exit*/
/* %28 = load i32* %27, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_22)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_25)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %30*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %30*/
/* %34 = load i8* %32, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB8_28)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %36*/
/* store i8* %37, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB9_31)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB9_32)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %40*/
/* %.pre.pre = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB10_36)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %44, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %45, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_41)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %48*/
/* store i32 -1, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_44)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %48*/
/* %51 = load i32* %50, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_45)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %53*/
/* store i32 %55, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %53*/
/* %56 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_49)
begin
memory_controller_enable = 1'd1;
end
/* buf_getv: %53*/
/* %59 = load i32* %58, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_50)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %0*/
/* %2 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB0_1)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB2_5)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_8)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %10*/
/* store i8* %13, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %10*/
/* %14 = load i8* %12, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB3_11)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %16*/
/* store i8* %17, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB4_14)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB4_15)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %.0.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %26, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_21)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %pgetc.exit*/
/* %28 = load i32* %27, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_22)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_25)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %30*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %30*/
/* %34 = load i8* %32, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB8_28)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %36*/
/* store i8* %37, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB9_31)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB9_32)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %40*/
/* %.pre.pre = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB10_36)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %44, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %45, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_41)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %48*/
/* store i32 -1, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_44)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %48*/
/* %51 = load i32* %50, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_45)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %53*/
/* store i32 %55, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
memory_controller_write_enable = 1'd1;
end
/* buf_getv: %53*/
/* %56 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_49)
begin
memory_controller_write_enable = 1'd0;
end
/* buf_getv: %53*/
/* %59 = load i32* %58, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_50)
begin
memory_controller_write_enable = 1'd0;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* buf_getv: %10*/
/* store i8* %13, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
memory_controller_in = buf_getv_10_13;
end
/* buf_getv: %16*/
/* store i8* %17, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB4_14)
begin
memory_controller_in = buf_getv_16_17;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %.0.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
memory_controller_in = buf_getv_pgetc_exit__0_i;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %26, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_21)
begin
memory_controller_in = buf_getv_pgetc_exit_26_reg;
end
/* buf_getv: %30*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
memory_controller_in = buf_getv_30_33;
end
/* buf_getv: %36*/
/* store i8* %37, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB9_31)
begin
memory_controller_in = buf_getv_36_37;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %44, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
memory_controller_in = buf_getv_pgetc_exit4_44;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %45, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_41)
begin
memory_controller_in = buf_getv_pgetc_exit4_45_reg;
end
/* buf_getv: %48*/
/* store i32 -1, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
memory_controller_in = -32'd1;
end
/* buf_getv: %53*/
/* store i32 %55, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
memory_controller_in = buf_getv_53_55;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* buf_getv: %0*/
/* %2 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB0_1)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %7*/
/* %9 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB2_5)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %10*/
/* %12 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_8)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %10*/
/* store i8* %13, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB3_10)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %10*/
/* %14 = load i8* %12, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB3_11)
begin
memory_controller_size = 2'd0;
end
/* buf_getv: %16*/
/* store i8* %17, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB4_14)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %16*/
/* %18 = load i8* %13, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB4_15)
begin
memory_controller_size = 2'd0;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %.0.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_20)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %pgetc.exit*/
/* store i32 %26, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_21)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %pgetc.exit*/
/* %28 = load i32* %27, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB7_22)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %30*/
/* %32 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_25)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %30*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB8_27)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %30*/
/* %34 = load i8* %32, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB8_28)
begin
memory_controller_size = 2'd0;
end
/* buf_getv: %36*/
/* store i8* %37, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_buf_getv_BB9_31)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %36*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_buf_getv_BB9_32)
begin
memory_controller_size = 2'd0;
end
/* buf_getv: %40*/
/* %.pre.pre = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB10_36)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %44, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_40)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %pgetc.exit4*/
/* store i32 %45, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB12_41)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %48*/
/* store i32 -1, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_43)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %48*/
/* %49 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_44)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %48*/
/* %51 = load i32* %50, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB14_45)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %53*/
/* store i32 %55, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_48)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %53*/
/* %56 = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_49)
begin
memory_controller_size = 2'd2;
end
/* buf_getv: %53*/
/* %59 = load i32* %58, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_buf_getv_BB15_50)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module huff_make_dhuff_tb
(
clk,
reset,
start,
finish,
return_val,
arg_p_xhtbl_bits,
arg_p_dhtbl_maxcode,
arg_p_dhtbl_mincode,
arg_p_dhtbl_valptr,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [5:0] LEGUP_0 = 6'd0;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB0_1 = 6'd1;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB1_2 = 6'd2;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB1_3 = 6'd3;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB1_4 = 6'd4;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB2_5 = 6'd5;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB3_6 = 6'd6;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB4_7 = 6'd7;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB5_8 = 6'd8;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB6_9 = 6'd9;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB6_10 = 6'd10;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB6_11 = 6'd11;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB6_12 = 6'd12;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB7_13 = 6'd13;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB8_14 = 6'd14;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB8_15 = 6'd15;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB8_16 = 6'd16;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB8_17 = 6'd17;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB9_18 = 6'd18;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB10_19 = 6'd19;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB11_20 = 6'd20;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB12_21 = 6'd21;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB12_22 = 6'd22;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB12_23 = 6'd23;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB13_24 = 6'd24;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_25 = 6'd25;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_26 = 6'd26;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_27 = 6'd27;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_28 = 6'd28;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_29 = 6'd29;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_30 = 6'd30;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_31 = 6'd31;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_32 = 6'd32;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB14_33 = 6'd33;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB15_34 = 6'd34;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB16_35 = 6'd35;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB16_36 = 6'd36;
parameter [5:0] LEGUP_F_huff_make_dhuff_tb_BB16_37 = 6'd37;
input clk;
input reset;
input start;
output reg finish;
output reg [31:0] return_val;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_xhtbl_bits;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_dhtbl_maxcode;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_dhtbl_mincode;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_p_dhtbl_valptr;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [5:0] cur_state;
reg [31:0] huff_make_dhuff_tb__preheader10_indvar44;
reg [31:0] huff_make_dhuff_tb__preheader10_p_013;
reg [31:0] huff_make_dhuff_tb__preheader10_p_013_reg;
reg [31:0] huff_make_dhuff_tb__preheader10_i_014;
reg [31:0] huff_make_dhuff_tb__preheader10_i_014_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb__preheader10_scevgep48;
reg [31:0] huff_make_dhuff_tb__preheader10_1;
reg [31:0] huff_make_dhuff_tb__preheader10_1_reg;
reg huff_make_dhuff_tb__preheader10_2;
reg huff_make_dhuff_tb__lr_ph_tmp37;
reg [31:0] huff_make_dhuff_tb__lr_ph_smax;
reg [31:0] huff_make_dhuff_tb__lr_ph_smax_reg;
reg [31:0] huff_make_dhuff_tb_3_indvar39;
reg [31:0] huff_make_dhuff_tb_3_tmp42;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_3_scevgep43;
reg [31:0] huff_make_dhuff_tb_3_indvar_next40;
reg huff_make_dhuff_tb_3_exitcond41;
reg [31:0] huff_make_dhuff_tb___crit_edge_tmp38;
reg [31:0] huff_make_dhuff_tb_4_p_1_lcssa;
reg [31:0] huff_make_dhuff_tb_4_p_1_lcssa_reg;
reg huff_make_dhuff_tb_4_exitcond46;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_5_6;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_5_7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_5_7_reg;
reg [31:0] huff_make_dhuff_tb_5_8;
reg [31:0] huff_make_dhuff_tb__outer_p_2_ph;
reg [31:0] huff_make_dhuff_tb__outer_p_2_ph_reg;
reg [31:0] huff_make_dhuff_tb__outer_code_0_ph;
reg [31:0] huff_make_dhuff_tb__outer_code_0_ph_reg;
reg [31:0] huff_make_dhuff_tb__outer_size_0_ph;
reg [31:0] huff_make_dhuff_tb__outer_size_0_ph_reg;
reg [31:0] huff_make_dhuff_tb__outer_tmp28;
reg [31:0] huff_make_dhuff_tb__outer_tmp28_reg;
reg [31:0] huff_make_dhuff_tb__outer_tmp3349;
reg [31:0] huff_make_dhuff_tb__outer_tmp3349_reg;
reg [31:0] huff_make_dhuff_tb_9_indvar26;
reg [31:0] huff_make_dhuff_tb_9_indvar26_reg;
reg [31:0] huff_make_dhuff_tb_9_tmp29;
reg [31:0] huff_make_dhuff_tb_9_tmp29_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_9_scevgep30;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_9_scevgep30_reg;
reg [31:0] huff_make_dhuff_tb_9_tmp31;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_9_scevgep32;
reg [31:0] huff_make_dhuff_tb_9_code_0;
reg [31:0] huff_make_dhuff_tb_9_10;
reg [31:0] huff_make_dhuff_tb_9_10_reg;
reg huff_make_dhuff_tb_9_11;
reg huff_make_dhuff_tb_9_12;
reg huff_make_dhuff_tb_9_12_reg;
reg huff_make_dhuff_tb_9_or_cond;
reg [31:0] huff_make_dhuff_tb_9_indvar_next27;
reg [31:0] huff_make_dhuff_tb_9_indvar_next27_reg;
reg huff_make_dhuff_tb__critedge_13;
reg [31:0] huff_make_dhuff_tb__preheader4_tmp34;
reg [31:0] huff_make_dhuff_tb__preheader4_tmp;
reg [31:0] huff_make_dhuff_tb__preheader4_tmp_reg;
reg [31:0] huff_make_dhuff_tb_14_indvar19;
reg [31:0] huff_make_dhuff_tb_14_code_1;
reg [31:0] huff_make_dhuff_tb_14_15;
reg [31:0] huff_make_dhuff_tb_14_indvar_next20;
reg huff_make_dhuff_tb_14_exitcond21;
reg [31:0] huff_make_dhuff_tb__preheader_indvar;
reg [31:0] huff_make_dhuff_tb__preheader_p_dhtbl_ml_03;
reg [31:0] huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg;
reg [31:0] huff_make_dhuff_tb__preheader_p_31;
reg [31:0] huff_make_dhuff_tb__preheader_p_31_reg;
reg [31:0] huff_make_dhuff_tb__preheader_l_02;
reg [31:0] huff_make_dhuff_tb__preheader_l_02_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb__preheader_scevgep;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb__preheader_scevgep_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb__preheader_scevgep15;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb__preheader_scevgep15_reg;
reg [31:0] huff_make_dhuff_tb__preheader_16;
reg huff_make_dhuff_tb__preheader_17;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_scevgep17;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_scevgep17_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_scevgep16;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_20;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_20_reg;
reg [31:0] huff_make_dhuff_tb_19_21;
reg [31:0] huff_make_dhuff_tb_19_22;
reg [31:0] huff_make_dhuff_tb_19_23;
reg [31:0] huff_make_dhuff_tb_19_23_reg;
reg [31:0] huff_make_dhuff_tb_19_24;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_19_25;
reg [31:0] huff_make_dhuff_tb_19_26;
reg [31:0] huff_make_dhuff_tb_19_27;
reg [31:0] huff_make_dhuff_tb_19_27_reg;
reg [31:0] huff_make_dhuff_tb_28_p_4;
reg [31:0] huff_make_dhuff_tb_28_p_dhtbl_ml_1;
reg [31:0] huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg;
reg huff_make_dhuff_tb_28_exitcond;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_29_30;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_29_30_reg;
reg [31:0] huff_make_dhuff_tb_29_31;
reg [31:0] huff_make_dhuff_tb_29_32;
reg [31:0] huff_make_dhuff_tb__preheader10_indvar44_phi_temp;
reg [31:0] huff_make_dhuff_tb__preheader10_p_013_phi_temp;
reg [31:0] huff_make_dhuff_tb_4_p_1_lcssa_phi_temp;
reg [31:0] huff_make_dhuff_tb_3_indvar39_phi_temp;
reg [31:0] huff_make_dhuff_tb__outer_p_2_ph_phi_temp;
reg [31:0] huff_make_dhuff_tb__outer_code_0_ph_phi_temp;
reg [31:0] huff_make_dhuff_tb__outer_size_0_ph_phi_temp;
reg [31:0] huff_make_dhuff_tb_9_indvar26_phi_temp;
reg [31:0] huff_make_dhuff_tb__preheader_indvar_phi_temp;
reg [31:0] huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp;
reg [31:0] huff_make_dhuff_tb__preheader_p_31_phi_temp;
reg [31:0] huff_make_dhuff_tb_14_indvar19_phi_temp;
reg [31:0] huff_make_dhuff_tb_14_code_1_phi_temp;
reg [31:0] huff_make_dhuff_tb_28_p_4_phi_temp;
reg [31:0] huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp;
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 6'd0;
if (^reset !== 1'bX && ^(6'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_3;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_3;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_3 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_4 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__preheader10_2 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_4 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__preheader10_2 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB2_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_3_exitcond41 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB4_7;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB4_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_3_exitcond41 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB4_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB4_7;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB4_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_4_exitcond46 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_4_exitcond46 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_10;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_10;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_11;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_11;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_12;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB6_12;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB6_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_12 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB7_13;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB7_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB7_13;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB7_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_14;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_14;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_15;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_15;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_16;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_16;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_16 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_17;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_17;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_17 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_9_or_cond == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB8_14;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB8_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_17 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_9_or_cond == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB9_18;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB9_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB9_18;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB9_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__critedge_13 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_21;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__critedge_13 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB10_19;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB10_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB10_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB10_19;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB10_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB10_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB11_20;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB11_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB11_20;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB11_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB7_13;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB7_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB11_20;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB11_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_21;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_22;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_22;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_22 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_23;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_23;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_23 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__preheader_17 == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB13_24;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB13_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_23 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__preheader_17 == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_25;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB13_24;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB13_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB15_34;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB15_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_25;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_26;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_26;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_27;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_27;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_27 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_28;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_28;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_29;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_29;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_30;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_30;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_30 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_31;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_31;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_32;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_32;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_32 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_33;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB14_33;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB14_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB15_34;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB15_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB15_34;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB15_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_28_exitcond == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_35;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_28_exitcond == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB12_21;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB12_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_35;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_36;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_36;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_36 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_37;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_huff_make_dhuff_tb_BB16_37;
if (^reset !== 1'bX && ^(LEGUP_F_huff_make_dhuff_tb_BB16_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %indvar44 = phi i32 [ 0, %0 ], [ %i.014, %4 ]*/
begin
huff_make_dhuff_tb__preheader10_indvar44 = huff_make_dhuff_tb__preheader10_indvar44_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013 = huff_make_dhuff_tb__preheader10_p_013_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013 = huff_make_dhuff_tb__preheader10_p_013_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013 = huff_make_dhuff_tb__preheader10_p_013_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2) */
begin
huff_make_dhuff_tb__preheader10_p_013 = huff_make_dhuff_tb__preheader10_p_013_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013_reg <= huff_make_dhuff_tb__preheader10_p_013;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013_reg <= huff_make_dhuff_tb__preheader10_p_013;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013_reg <= huff_make_dhuff_tb__preheader10_p_013;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013_reg <= huff_make_dhuff_tb__preheader10_p_013;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_p_013_reg <= huff_make_dhuff_tb__preheader10_p_013;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %i.014 = add i32 %indvar44, 1*/
begin
huff_make_dhuff_tb__preheader10_i_014 = huff_make_dhuff_tb__preheader10_indvar44 + 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %i.014 = add i32 %indvar44, 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
huff_make_dhuff_tb__preheader10_i_014_reg <= huff_make_dhuff_tb__preheader10_i_014;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_i_014) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_i_014_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %scevgep48 = getelementptr i32* %p_xhtbl_bits, i32 %i.014*/
begin
huff_make_dhuff_tb__preheader10_scevgep48 = arg_p_xhtbl_bits + 4 * huff_make_dhuff_tb__preheader10_i_014;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb__preheader10_1 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_4)
begin
huff_make_dhuff_tb__preheader10_1_reg <= huff_make_dhuff_tb__preheader10_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_1_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %2 = icmp slt i32 %1, 1*/
begin
huff_make_dhuff_tb__preheader10_2 = $signed(huff_make_dhuff_tb__preheader10_1) < $signed(32'd1);
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.lr.ph*/
/* %tmp37 = icmp sgt i32 %1, 1*/
begin
huff_make_dhuff_tb__lr_ph_tmp37 = $signed(huff_make_dhuff_tb__preheader10_1_reg) > $signed(32'd1);
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.lr.ph*/
/* %smax = select i1 %tmp37, i32 %1, i32 1*/
begin
huff_make_dhuff_tb__lr_ph_smax = (huff_make_dhuff_tb__lr_ph_tmp37 ? huff_make_dhuff_tb__preheader10_1_reg : 32'd1);
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.lr.ph*/
/* %smax = select i1 %tmp37, i32 %1, i32 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB2_5)
begin
huff_make_dhuff_tb__lr_ph_smax_reg <= huff_make_dhuff_tb__lr_ph_smax;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__lr_ph_smax) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__lr_ph_smax_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %3*/
/* %indvar39 = phi i32 [ 0, %.lr.ph ], [ %indvar.next40, %3 ]*/
begin
huff_make_dhuff_tb_3_indvar39 = huff_make_dhuff_tb_3_indvar39_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %3*/
/* %tmp42 = add i32 %p.013, %indvar39*/
begin
huff_make_dhuff_tb_3_tmp42 = huff_make_dhuff_tb__preheader10_p_013_reg + huff_make_dhuff_tb_3_indvar39;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %3*/
/* %scevgep43 = getelementptr [257 x i32]* %huffsize, i32 0, i32 %tmp42*/
begin
huff_make_dhuff_tb_3_scevgep43 = `TAG_huff_make_dhuff_tb_0_huffsize_a + 4 * huff_make_dhuff_tb_3_tmp42;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %3*/
/* %indvar.next40 = add i32 %indvar39, 1*/
begin
huff_make_dhuff_tb_3_indvar_next40 = huff_make_dhuff_tb_3_indvar39 + 32'd1;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %3*/
/* %exitcond41 = icmp eq i32 %indvar.next40, %smax*/
begin
huff_make_dhuff_tb_3_exitcond41 = huff_make_dhuff_tb_3_indvar_next40 == huff_make_dhuff_tb__lr_ph_smax_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %._crit_edge*/
/* %tmp38 = add i32 %p.013, %smax*/
begin
huff_make_dhuff_tb___crit_edge_tmp38 = huff_make_dhuff_tb__preheader10_p_013_reg + huff_make_dhuff_tb__lr_ph_smax_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8)
begin
huff_make_dhuff_tb_4_p_1_lcssa = huff_make_dhuff_tb_4_p_1_lcssa_phi_temp;
end
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8) */
begin
huff_make_dhuff_tb_4_p_1_lcssa = huff_make_dhuff_tb_4_p_1_lcssa_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8)
begin
huff_make_dhuff_tb_4_p_1_lcssa_reg <= huff_make_dhuff_tb_4_p_1_lcssa;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_4_p_1_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_4_p_1_lcssa_reg"); $finish; end
end
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8)
begin
huff_make_dhuff_tb_4_p_1_lcssa_reg <= huff_make_dhuff_tb_4_p_1_lcssa;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_4_p_1_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_4_p_1_lcssa_reg"); $finish; end
end
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8)
begin
huff_make_dhuff_tb_4_p_1_lcssa_reg <= huff_make_dhuff_tb_4_p_1_lcssa;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_4_p_1_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_4_p_1_lcssa_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %4*/
/* %exitcond46 = icmp eq i32 %i.014, 16*/
begin
huff_make_dhuff_tb_4_exitcond46 = huff_make_dhuff_tb__preheader10_i_014_reg == 32'd16;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %5*/
/* %6 = getelementptr inbounds [257 x i32]* %huffsize, i32 0, i32 %p.1.lcssa*/
begin
huff_make_dhuff_tb_5_6 = `TAG_huff_make_dhuff_tb_0_huffsize_a + 4 * huff_make_dhuff_tb_4_p_1_lcssa_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %5*/
/* %7 = getelementptr inbounds [257 x i32]* %huffsize, i32 0, i32 0*/
if (reset) begin huff_make_dhuff_tb_5_7 = 0; end
begin
huff_make_dhuff_tb_5_7 = `TAG_huff_make_dhuff_tb_0_huffsize_a;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %5*/
/* %7 = getelementptr inbounds [257 x i32]* %huffsize, i32 0, i32 0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
huff_make_dhuff_tb_5_7_reg <= huff_make_dhuff_tb_5_7;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_5_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_5_7_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %5*/
/* %8 = load i32* %7, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_5_8 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_p_2_ph = huff_make_dhuff_tb__outer_p_2_ph_phi_temp;
end
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13) */
begin
huff_make_dhuff_tb__outer_p_2_ph = huff_make_dhuff_tb__outer_p_2_ph_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_p_2_ph_reg <= huff_make_dhuff_tb__outer_p_2_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_p_2_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_p_2_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_p_2_ph_reg <= huff_make_dhuff_tb__outer_p_2_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_p_2_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_p_2_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_p_2_ph_reg <= huff_make_dhuff_tb__outer_p_2_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_p_2_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_p_2_ph_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_code_0_ph = huff_make_dhuff_tb__outer_code_0_ph_phi_temp;
end
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13) */
begin
huff_make_dhuff_tb__outer_code_0_ph = huff_make_dhuff_tb__outer_code_0_ph_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_code_0_ph_reg <= huff_make_dhuff_tb__outer_code_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_code_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_code_0_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_code_0_ph_reg <= huff_make_dhuff_tb__outer_code_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_code_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_code_0_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_code_0_ph_reg <= huff_make_dhuff_tb__outer_code_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_code_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_code_0_ph_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph = huff_make_dhuff_tb__outer_size_0_ph_phi_temp;
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph = huff_make_dhuff_tb__outer_size_0_ph_phi_temp;
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13) */
begin
huff_make_dhuff_tb__outer_size_0_ph = huff_make_dhuff_tb__outer_size_0_ph_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph_reg <= huff_make_dhuff_tb__outer_size_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_size_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph_reg <= huff_make_dhuff_tb__outer_size_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_size_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph_reg <= huff_make_dhuff_tb__outer_size_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_size_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_size_0_ph_reg <= huff_make_dhuff_tb__outer_size_0_ph;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_size_0_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.outer*/
/* %tmp28 = add i32 %p.2.ph, 1*/
begin
huff_make_dhuff_tb__outer_tmp28 = huff_make_dhuff_tb__outer_p_2_ph + 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %tmp28 = add i32 %p.2.ph, 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_tmp28_reg <= huff_make_dhuff_tb__outer_tmp28;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_tmp28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_tmp28_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.outer*/
/* %tmp3349 = or i32 %code.0.ph, 1*/
begin
huff_make_dhuff_tb__outer_tmp3349 = huff_make_dhuff_tb__outer_code_0_ph | 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %tmp3349 = or i32 %code.0.ph, 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13)
begin
huff_make_dhuff_tb__outer_tmp3349_reg <= huff_make_dhuff_tb__outer_tmp3349;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__outer_tmp3349) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_tmp3349_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_indvar26 = huff_make_dhuff_tb_9_indvar26_phi_temp;
end
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14) */
begin
huff_make_dhuff_tb_9_indvar26 = huff_make_dhuff_tb_9_indvar26_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_indvar26_reg <= huff_make_dhuff_tb_9_indvar26;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_indvar26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar26_reg"); $finish; end
end
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_indvar26_reg <= huff_make_dhuff_tb_9_indvar26;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_indvar26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar26_reg"); $finish; end
end
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_indvar26_reg <= huff_make_dhuff_tb_9_indvar26;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_indvar26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar26_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %tmp29 = add i32 %tmp28, %indvar26*/
begin
huff_make_dhuff_tb_9_tmp29 = huff_make_dhuff_tb__outer_tmp28_reg + huff_make_dhuff_tb_9_indvar26;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %tmp29 = add i32 %tmp28, %indvar26*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_tmp29_reg <= huff_make_dhuff_tb_9_tmp29;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_tmp29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_tmp29_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %scevgep30 = getelementptr [257 x i32]* %huffsize, i32 0, i32 %tmp29*/
begin
huff_make_dhuff_tb_9_scevgep30 = `TAG_huff_make_dhuff_tb_0_huffsize_a + 4 * huff_make_dhuff_tb_9_tmp29;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %scevgep30 = getelementptr [257 x i32]* %huffsize, i32 0, i32 %tmp29*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_scevgep30_reg <= huff_make_dhuff_tb_9_scevgep30;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_scevgep30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_scevgep30_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %tmp31 = add i32 %p.2.ph, %indvar26*/
begin
huff_make_dhuff_tb_9_tmp31 = huff_make_dhuff_tb__outer_p_2_ph_reg + huff_make_dhuff_tb_9_indvar26;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %scevgep32 = getelementptr [257 x i32]* %huffcode, i32 0, i32 %tmp31*/
begin
huff_make_dhuff_tb_9_scevgep32 = `TAG_huff_make_dhuff_tb_0_huffcode_a + 4 * huff_make_dhuff_tb_9_tmp31;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %code.0 = add i32 %code.0.ph, %indvar26*/
begin
huff_make_dhuff_tb_9_code_0 = huff_make_dhuff_tb__outer_code_0_ph_reg + huff_make_dhuff_tb_9_indvar26;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_9_10 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_17)
begin
huff_make_dhuff_tb_9_10_reg <= huff_make_dhuff_tb_9_10;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_10_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %11 = icmp eq i32 %10, %size.0.ph*/
begin
huff_make_dhuff_tb_9_11 = huff_make_dhuff_tb_9_10 == huff_make_dhuff_tb__outer_size_0_ph_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %12 = icmp slt i32 %tmp29, 257*/
begin
huff_make_dhuff_tb_9_12 = $signed(huff_make_dhuff_tb_9_tmp29) < $signed(32'd257);
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %12 = icmp slt i32 %tmp29, 257*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_12_reg <= huff_make_dhuff_tb_9_12;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_12_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %or.cond = and i1 %11, %12*/
begin
huff_make_dhuff_tb_9_or_cond = huff_make_dhuff_tb_9_11 & huff_make_dhuff_tb_9_12_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %9*/
/* %indvar.next27 = add i32 %indvar26, 1*/
begin
huff_make_dhuff_tb_9_indvar_next27 = huff_make_dhuff_tb_9_indvar26 + 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %indvar.next27 = add i32 %indvar26, 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
huff_make_dhuff_tb_9_indvar_next27_reg <= huff_make_dhuff_tb_9_indvar_next27;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_indvar_next27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar_next27_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.critedge*/
/* %13 = icmp eq i32 %10, 0*/
begin
huff_make_dhuff_tb__critedge_13 = huff_make_dhuff_tb_9_10_reg == 32'd0;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader4*/
/* %tmp34 = add i32 %tmp3349, %indvar26*/
begin
huff_make_dhuff_tb__preheader4_tmp34 = huff_make_dhuff_tb__outer_tmp3349_reg + huff_make_dhuff_tb_9_indvar26_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader4*/
/* %tmp = sub i32 %10, %size.0.ph*/
begin
huff_make_dhuff_tb__preheader4_tmp = huff_make_dhuff_tb_9_10_reg - huff_make_dhuff_tb__outer_size_0_ph_reg;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader4*/
/* %tmp = sub i32 %10, %size.0.ph*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB10_19)
begin
huff_make_dhuff_tb__preheader4_tmp_reg <= huff_make_dhuff_tb__preheader4_tmp;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader4_tmp) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader4_tmp_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %14*/
/* %indvar19 = phi i32 [ 0, %.preheader4 ], [ %indvar.next20, %14 ]*/
begin
huff_make_dhuff_tb_14_indvar19 = huff_make_dhuff_tb_14_indvar19_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %14*/
/* %code.1 = phi i32 [ %tmp34, %.preheader4 ], [ %15, %14 ]*/
begin
huff_make_dhuff_tb_14_code_1 = huff_make_dhuff_tb_14_code_1_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %14*/
/* %15 = shl i32 %code.1, 1*/
begin
huff_make_dhuff_tb_14_15 = huff_make_dhuff_tb_14_code_1 <<< 32'd1 % 32;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %14*/
/* %indvar.next20 = add i32 %indvar19, 1*/
begin
huff_make_dhuff_tb_14_indvar_next20 = huff_make_dhuff_tb_14_indvar19 + 32'd1;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %14*/
/* %exitcond21 = icmp eq i32 %indvar.next20, %tmp*/
begin
huff_make_dhuff_tb_14_exitcond21 = huff_make_dhuff_tb_14_indvar_next20 == huff_make_dhuff_tb__preheader4_tmp_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %indvar = phi i32 [ %l.02, %28 ], [ 0, %.critedge ]*/
begin
huff_make_dhuff_tb__preheader_indvar = huff_make_dhuff_tb__preheader_indvar_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03 = huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21) */
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03 = huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg <= huff_make_dhuff_tb__preheader_p_dhtbl_ml_03;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_dhtbl_ml_03) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg <= huff_make_dhuff_tb__preheader_p_dhtbl_ml_03;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_dhtbl_ml_03) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg <= huff_make_dhuff_tb__preheader_p_dhtbl_ml_03;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_dhtbl_ml_03) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21) */
begin
huff_make_dhuff_tb__preheader_p_31 = huff_make_dhuff_tb__preheader_p_31_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_p_31_reg <= huff_make_dhuff_tb__preheader_p_31;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %l.02 = add i32 %indvar, 1*/
begin
huff_make_dhuff_tb__preheader_l_02 = huff_make_dhuff_tb__preheader_indvar + 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %l.02 = add i32 %indvar, 1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_l_02_reg <= huff_make_dhuff_tb__preheader_l_02;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_l_02) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_l_02_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %scevgep = getelementptr i32* %p_xhtbl_bits, i32 %l.02*/
begin
huff_make_dhuff_tb__preheader_scevgep = arg_p_xhtbl_bits + 4 * huff_make_dhuff_tb__preheader_l_02;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %scevgep = getelementptr i32* %p_xhtbl_bits, i32 %l.02*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_scevgep_reg <= huff_make_dhuff_tb__preheader_scevgep;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_scevgep) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_scevgep_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %scevgep15 = getelementptr i32* %p_dhtbl_maxcode, i32 %l.02*/
begin
huff_make_dhuff_tb__preheader_scevgep15 = arg_p_dhtbl_maxcode + 4 * huff_make_dhuff_tb__preheader_l_02;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %scevgep15 = getelementptr i32* %p_dhtbl_maxcode, i32 %l.02*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
huff_make_dhuff_tb__preheader_scevgep15_reg <= huff_make_dhuff_tb__preheader_scevgep15;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_scevgep15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_scevgep15_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %16 = load i32* %scevgep, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb__preheader_16 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %17 = icmp eq i32 %16, 0*/
begin
huff_make_dhuff_tb__preheader_17 = huff_make_dhuff_tb__preheader_16 == 32'd0;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %scevgep17 = getelementptr i32* %p_dhtbl_mincode, i32 %l.02*/
begin
huff_make_dhuff_tb_19_scevgep17 = arg_p_dhtbl_mincode + 4 * huff_make_dhuff_tb__preheader_l_02_reg;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %19*/
/* %scevgep17 = getelementptr i32* %p_dhtbl_mincode, i32 %l.02*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
huff_make_dhuff_tb_19_scevgep17_reg <= huff_make_dhuff_tb_19_scevgep17;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_19_scevgep17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_19_scevgep17_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %scevgep16 = getelementptr i32* %p_dhtbl_valptr, i32 %l.02*/
begin
huff_make_dhuff_tb_19_scevgep16 = arg_p_dhtbl_valptr + 4 * huff_make_dhuff_tb__preheader_l_02_reg;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %20 = getelementptr inbounds [257 x i32]* %huffcode, i32 0, i32 %p.31*/
begin
huff_make_dhuff_tb_19_20 = `TAG_huff_make_dhuff_tb_0_huffcode_a + 4 * huff_make_dhuff_tb__preheader_p_31_reg;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %19*/
/* %20 = getelementptr inbounds [257 x i32]* %huffcode, i32 0, i32 %p.31*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
huff_make_dhuff_tb_19_20_reg <= huff_make_dhuff_tb_19_20;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_19_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_19_20_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %21 = load i32* %20, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_19_21 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %22 = load i32* %scevgep, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_19_22 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %23 = add i32 %p.31, -1*/
begin
huff_make_dhuff_tb_19_23 = huff_make_dhuff_tb__preheader_p_31_reg + -32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %19*/
/* %23 = add i32 %p.31, -1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
huff_make_dhuff_tb_19_23_reg <= huff_make_dhuff_tb_19_23;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_19_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_19_23_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %24 = add i32 %23, %22*/
begin
huff_make_dhuff_tb_19_24 = huff_make_dhuff_tb_19_23_reg + huff_make_dhuff_tb_19_22;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %25 = getelementptr inbounds [257 x i32]* %huffcode, i32 0, i32 %24*/
begin
huff_make_dhuff_tb_19_25 = `TAG_huff_make_dhuff_tb_0_huffcode_a + 4 * huff_make_dhuff_tb_19_24;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_19_26 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %19*/
/* %27 = add i32 %22, %p.31*/
begin
huff_make_dhuff_tb_19_27 = huff_make_dhuff_tb_19_22 + huff_make_dhuff_tb__preheader_p_31_reg;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %19*/
/* %27 = add i32 %22, %p.31*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31)
begin
huff_make_dhuff_tb_19_27_reg <= huff_make_dhuff_tb_19_27;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_19_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_19_27_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %28*/
/* %p.4 = phi i32 [ %p.31, %18 ], [ %27, %19 ]*/
begin
huff_make_dhuff_tb_28_p_4 = huff_make_dhuff_tb_28_p_4_phi_temp;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1 = huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp;
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
else if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1 = huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp;
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
else /* if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34) */
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1 = huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg <= huff_make_dhuff_tb_28_p_dhtbl_ml_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg"); $finish; end
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg <= huff_make_dhuff_tb_28_p_dhtbl_ml_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg"); $finish; end
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg <= huff_make_dhuff_tb_28_p_dhtbl_ml_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg"); $finish; end
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg <= huff_make_dhuff_tb_28_p_dhtbl_ml_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %28*/
/* %exitcond = icmp eq i32 %l.02, 16*/
begin
huff_make_dhuff_tb_28_exitcond = huff_make_dhuff_tb__preheader_l_02_reg == 32'd16;
end
end
always @(*) begin
/* huff_make_dhuff_tb: %29*/
/* %30 = getelementptr inbounds i32* %p_dhtbl_maxcode, i32 %p_dhtbl_ml.1*/
begin
huff_make_dhuff_tb_29_30 = arg_p_dhtbl_maxcode + 4 * huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %29*/
/* %30 = getelementptr inbounds i32* %p_dhtbl_maxcode, i32 %p_dhtbl_ml.1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35)
begin
huff_make_dhuff_tb_29_30_reg <= huff_make_dhuff_tb_29_30;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_29_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_29_30_reg"); $finish; end
end
end
always @(*) begin
/* huff_make_dhuff_tb: %29*/
/* %31 = load i32* %30, align 4, !tbaa !0*/
begin
huff_make_dhuff_tb_29_31 = memory_controller_out[31:0];
end
end
always @(*) begin
/* huff_make_dhuff_tb: %29*/
/* %32 = add nsw i32 %31, 1*/
begin
huff_make_dhuff_tb_29_32 = huff_make_dhuff_tb_29_31 + 32'd1;
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %indvar44 = phi i32 [ 0, %0 ], [ %i.014, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb__preheader10_indvar44_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_indvar44_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %indvar44 = phi i32 [ 0, %0 ], [ %i.014, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_4_exitcond46 == 1'd0)
begin
huff_make_dhuff_tb__preheader10_indvar44_phi_temp <= huff_make_dhuff_tb__preheader10_i_014_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_i_014_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_indvar44_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb__preheader10_p_013_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %p.013 = phi i32 [ 0, %0 ], [ %p.1.lcssa, %4 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB5_8 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_4_exitcond46 == 1'd0)
begin
huff_make_dhuff_tb__preheader10_p_013_phi_temp <= huff_make_dhuff_tb_4_p_1_lcssa;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_4_p_1_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader10_p_013_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_4 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__preheader10_2 == 1'd1)
begin
huff_make_dhuff_tb_4_p_1_lcssa_phi_temp <= huff_make_dhuff_tb__preheader10_p_013_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader10_p_013_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_4_p_1_lcssa_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %4*/
/* %p.1.lcssa = phi i32 [ %tmp38, %._crit_edge ], [ %p.013, %.preheader10 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_4_p_1_lcssa_phi_temp <= huff_make_dhuff_tb___crit_edge_tmp38;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb___crit_edge_tmp38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_4_p_1_lcssa_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %3*/
/* %indvar39 = phi i32 [ 0, %.lr.ph ], [ %indvar.next40, %3 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_3_indvar39_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_3_indvar39_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %3*/
/* %indvar39 = phi i32 [ 0, %.lr.ph ], [ %indvar.next40, %3 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_3_exitcond41 == 1'd0)
begin
huff_make_dhuff_tb_3_indvar39_phi_temp <= huff_make_dhuff_tb_3_indvar_next40;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_3_indvar_next40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_3_indvar39_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_12 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb__outer_p_2_ph_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_p_2_ph_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %p.2.ph = phi i32 [ 0, %5 ], [ %tmp29, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd1)
begin
huff_make_dhuff_tb__outer_p_2_ph_phi_temp <= huff_make_dhuff_tb_9_tmp29_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_tmp29_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_p_2_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_12 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb__outer_code_0_ph_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_code_0_ph_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %code.0.ph = phi i32 [ 0, %5 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd1)
begin
huff_make_dhuff_tb__outer_code_0_ph_phi_temp <= huff_make_dhuff_tb_14_15;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_14_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_code_0_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_12 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb__outer_size_0_ph_phi_temp <= huff_make_dhuff_tb_5_8;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.outer*/
/* %size.0.ph = phi i32 [ %8, %5 ], [ %10, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd1)
begin
huff_make_dhuff_tb__outer_size_0_ph_phi_temp <= huff_make_dhuff_tb_9_10_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_10_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__outer_size_0_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB7_13 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_9_indvar26_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar26_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %9*/
/* %indvar26 = phi i32 [ 0, %.outer ], [ %indvar.next27, %9 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_17 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_9_or_cond == 1'd1)
begin
huff_make_dhuff_tb_9_indvar26_phi_temp <= huff_make_dhuff_tb_9_indvar_next27_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_9_indvar_next27_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_9_indvar26_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %indvar = phi i32 [ %l.02, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__critedge_13 == 1'd1)
begin
huff_make_dhuff_tb__preheader_indvar_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_indvar_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %indvar = phi i32 [ %l.02, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_28_exitcond == 1'd0)
begin
huff_make_dhuff_tb__preheader_indvar_phi_temp <= huff_make_dhuff_tb__preheader_l_02_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_l_02_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_indvar_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__critedge_13 == 1'd1)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp <= 32'd1;
if (^reset !== 1'bX && ^(32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p_dhtbl_ml.03 = phi i32 [ %p_dhtbl_ml.1, %28 ], [ 1, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_28_exitcond == 1'd0)
begin
huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp <= huff_make_dhuff_tb_28_p_dhtbl_ml_1;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB9_18 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb__critedge_13 == 1'd1)
begin
huff_make_dhuff_tb__preheader_p_31_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %.preheader*/
/* %p.31 = phi i32 [ %p.4, %28 ], [ 0, %.critedge ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB15_34 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_28_exitcond == 1'd0)
begin
huff_make_dhuff_tb__preheader_p_31_phi_temp <= huff_make_dhuff_tb_28_p_4;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb__preheader_p_31_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %14*/
/* %indvar19 = phi i32 [ 0, %.preheader4 ], [ %indvar.next20, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB10_19 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_14_indvar19_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_14_indvar19_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %14*/
/* %indvar19 = phi i32 [ 0, %.preheader4 ], [ %indvar.next20, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd0)
begin
huff_make_dhuff_tb_14_indvar19_phi_temp <= huff_make_dhuff_tb_14_indvar_next20;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_14_indvar_next20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_14_indvar19_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %14*/
/* %code.1 = phi i32 [ %tmp34, %.preheader4 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB10_19 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_14_code_1_phi_temp <= huff_make_dhuff_tb__preheader4_tmp34;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader4_tmp34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_14_code_1_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %14*/
/* %code.1 = phi i32 [ %tmp34, %.preheader4 ], [ %15, %14 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB11_20 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_14_exitcond21 == 1'd0)
begin
huff_make_dhuff_tb_14_code_1_phi_temp <= huff_make_dhuff_tb_14_15;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_14_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_14_code_1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %28*/
/* %p.4 = phi i32 [ %p.31, %18 ], [ %27, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_28_p_4_phi_temp <= huff_make_dhuff_tb__preheader_p_31_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_31_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_4_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %28*/
/* %p.4 = phi i32 [ %p.31, %18 ], [ %27, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_28_p_4_phi_temp <= huff_make_dhuff_tb_19_27_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_19_27_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_4_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp <= huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_p_dhtbl_ml_03_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp"); $finish; end
end
/* huff_make_dhuff_tb: %28*/
/* %p_dhtbl_ml.1 = phi i32 [ %p_dhtbl_ml.03, %18 ], [ %l.02, %19 ]*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33 & memory_controller_waitrequest == 1'd0)
begin
huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp <= huff_make_dhuff_tb__preheader_l_02_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb__preheader_l_02_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_28_p_dhtbl_ml_1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* huff_make_dhuff_tb: %29*/
/* ret i32 %p_dhtbl_ml.1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
return_val <= 0;
if (^reset !== 1'bX && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
/* huff_make_dhuff_tb: %29*/
/* ret i32 %p_dhtbl_ml.1*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
return_val <= huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg;
if (^reset !== 1'bX && ^(huff_make_dhuff_tb_28_p_dhtbl_ml_1_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
memory_controller_address = huff_make_dhuff_tb__preheader10_scevgep48;
end
/* huff_make_dhuff_tb: %3*/
/* store i32 %i.014, i32* %scevgep43, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6)
begin
memory_controller_address = huff_make_dhuff_tb_3_scevgep43;
end
/* huff_make_dhuff_tb: %5*/
/* store i32 0, i32* %6, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
memory_controller_address = huff_make_dhuff_tb_5_6;
end
/* huff_make_dhuff_tb: %5*/
/* %8 = load i32* %7, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10)
begin
memory_controller_address = huff_make_dhuff_tb_5_7_reg;
end
/* huff_make_dhuff_tb: %9*/
/* store i32 %code.0, i32* %scevgep32, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
memory_controller_address = huff_make_dhuff_tb_9_scevgep32;
end
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15)
begin
memory_controller_address = huff_make_dhuff_tb_9_scevgep30_reg;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %16 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
memory_controller_address = huff_make_dhuff_tb__preheader_scevgep;
end
/* huff_make_dhuff_tb: %18*/
/* store i32 -1, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24)
begin
memory_controller_address = huff_make_dhuff_tb__preheader_scevgep15_reg;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %p.31, i32* %scevgep16, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
memory_controller_address = huff_make_dhuff_tb_19_scevgep16;
end
/* huff_make_dhuff_tb: %19*/
/* %21 = load i32* %20, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26)
begin
memory_controller_address = huff_make_dhuff_tb_19_20_reg;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %21, i32* %scevgep17, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28)
begin
memory_controller_address = huff_make_dhuff_tb_19_scevgep17_reg;
end
/* huff_make_dhuff_tb: %19*/
/* %22 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29)
begin
memory_controller_address = huff_make_dhuff_tb__preheader_scevgep_reg;
end
/* huff_make_dhuff_tb: %19*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31)
begin
memory_controller_address = huff_make_dhuff_tb_19_25;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %26, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33)
begin
memory_controller_address = huff_make_dhuff_tb__preheader_scevgep15_reg;
end
/* huff_make_dhuff_tb: %29*/
/* %31 = load i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35)
begin
memory_controller_address = huff_make_dhuff_tb_29_30;
end
/* huff_make_dhuff_tb: %29*/
/* store i32 %32, i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
memory_controller_address = huff_make_dhuff_tb_29_30_reg;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %3*/
/* store i32 %i.014, i32* %scevgep43, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %5*/
/* store i32 0, i32* %6, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %5*/
/* %8 = load i32* %7, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %9*/
/* store i32 %code.0, i32* %scevgep32, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %16 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %18*/
/* store i32 -1, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %p.31, i32* %scevgep16, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* %21 = load i32* %20, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %21, i32* %scevgep17, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* %22 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %26, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %29*/
/* %31 = load i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35)
begin
memory_controller_enable = 1'd1;
end
/* huff_make_dhuff_tb: %29*/
/* store i32 %32, i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %3*/
/* store i32 %i.014, i32* %scevgep43, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %5*/
/* store i32 0, i32* %6, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %5*/
/* %8 = load i32* %7, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %9*/
/* store i32 %code.0, i32* %scevgep32, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %16 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %18*/
/* store i32 -1, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %p.31, i32* %scevgep16, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* %21 = load i32* %20, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %21, i32* %scevgep17, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %19*/
/* %22 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %19*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %26, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33)
begin
memory_controller_write_enable = 1'd1;
end
/* huff_make_dhuff_tb: %29*/
/* %31 = load i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35)
begin
memory_controller_write_enable = 1'd0;
end
/* huff_make_dhuff_tb: %29*/
/* store i32 %32, i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
memory_controller_write_enable = 1'd1;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* huff_make_dhuff_tb: %3*/
/* store i32 %i.014, i32* %scevgep43, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6)
begin
memory_controller_in = huff_make_dhuff_tb__preheader10_i_014_reg;
end
/* huff_make_dhuff_tb: %5*/
/* store i32 0, i32* %6, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
memory_controller_in = 32'd0;
end
/* huff_make_dhuff_tb: %9*/
/* store i32 %code.0, i32* %scevgep32, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
memory_controller_in = huff_make_dhuff_tb_9_code_0;
end
/* huff_make_dhuff_tb: %18*/
/* store i32 -1, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24)
begin
memory_controller_in = -32'd1;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %p.31, i32* %scevgep16, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
memory_controller_in = huff_make_dhuff_tb__preheader_p_31_reg;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %21, i32* %scevgep17, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28)
begin
memory_controller_in = huff_make_dhuff_tb_19_21;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %26, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33)
begin
memory_controller_in = huff_make_dhuff_tb_19_26;
end
/* huff_make_dhuff_tb: %29*/
/* store i32 %32, i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
memory_controller_in = huff_make_dhuff_tb_29_32;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* huff_make_dhuff_tb: %.preheader10*/
/* %1 = load i32* %scevgep48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB1_2)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %3*/
/* store i32 %i.014, i32* %scevgep43, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB3_6)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %5*/
/* store i32 0, i32* %6, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_9)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %5*/
/* %8 = load i32* %7, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB6_10)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %9*/
/* store i32 %code.0, i32* %scevgep32, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_14)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %9*/
/* %10 = load i32* %scevgep30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB8_15)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %.preheader*/
/* %16 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB12_21)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %18*/
/* store i32 -1, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB13_24)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %p.31, i32* %scevgep16, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_25)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* %21 = load i32* %20, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_26)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %21, i32* %scevgep17, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_28)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* %22 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_29)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_31)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %19*/
/* store i32 %26, i32* %scevgep15, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB14_33)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %29*/
/* %31 = load i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_35)
begin
memory_controller_size = 2'd2;
end
/* huff_make_dhuff_tb: %29*/
/* store i32 %32, i32* %30, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_huff_make_dhuff_tb_BB16_37)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module DecodeHuffman
(
clk,
reset,
start,
finish,
return_val,
arg_Xhuff_huffval,
arg_Dhuff_ml,
arg_Dhuff_maxcode,
arg_Dhuff_mincode,
arg_Dhuff_valptr,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [5:0] LEGUP_0 = 6'd0;
parameter [5:0] LEGUP_F_DecodeHuffman_BB0_1 = 6'd1;
parameter [5:0] LEGUP_F_DecodeHuffman_BB0_2 = 6'd2;
parameter [5:0] LEGUP_F_DecodeHuffman_BB0_3 = 6'd3;
parameter [5:0] LEGUP_F_DecodeHuffman_BB1_4 = 6'd4;
parameter [5:0] LEGUP_F_DecodeHuffman_BB1_5 = 6'd5;
parameter [5:0] LEGUP_F_DecodeHuffman_BB1_6 = 6'd6;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_7 = 6'd7;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_8 = 6'd8;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_9 = 6'd9;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_10 = 6'd10;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_11 = 6'd11;
parameter [5:0] LEGUP_F_DecodeHuffman_BB2_12 = 6'd12;
parameter [5:0] LEGUP_F_DecodeHuffman_BB3_13 = 6'd13;
parameter [5:0] LEGUP_F_DecodeHuffman_BB3_14 = 6'd14;
parameter [5:0] LEGUP_F_DecodeHuffman_BB3_15 = 6'd15;
parameter [5:0] LEGUP_F_DecodeHuffman_BB3_16 = 6'd16;
parameter [5:0] LEGUP_F_DecodeHuffman_BB4_17 = 6'd17;
parameter [5:0] LEGUP_F_DecodeHuffman_BB5_18 = 6'd18;
parameter [5:0] LEGUP_F_DecodeHuffman_BB6_19 = 6'd19;
parameter [5:0] LEGUP_F_DecodeHuffman_BB6_20 = 6'd20;
parameter [5:0] LEGUP_F_DecodeHuffman_BB7_21 = 6'd21;
parameter [5:0] LEGUP_F_DecodeHuffman_BB7_22 = 6'd22;
parameter [5:0] LEGUP_F_DecodeHuffman_BB7_23 = 6'd23;
parameter [5:0] LEGUP_F_DecodeHuffman_BB7_24 = 6'd24;
parameter [5:0] LEGUP_F_DecodeHuffman_BB7_25 = 6'd25;
parameter [5:0] LEGUP_F_DecodeHuffman_BB8_26 = 6'd26;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_27 = 6'd27;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_28 = 6'd28;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_29 = 6'd29;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_30 = 6'd30;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_31 = 6'd31;
parameter [5:0] LEGUP_F_DecodeHuffman_BB9_32 = 6'd32;
parameter [5:0] LEGUP_F_DecodeHuffman_BB10_33 = 6'd33;
parameter [5:0] LEGUP_F_DecodeHuffman_BB10_34 = 6'd34;
parameter [5:0] LEGUP_F_DecodeHuffman_BB10_35 = 6'd35;
parameter [5:0] LEGUP_F_DecodeHuffman_BB10_36 = 6'd36;
parameter [5:0] LEGUP_F_DecodeHuffman_BB11_37 = 6'd37;
parameter [5:0] LEGUP_F_DecodeHuffman_BB12_38 = 6'd38;
parameter [5:0] LEGUP_F_DecodeHuffman_BB13_39 = 6'd39;
parameter [5:0] LEGUP_F_DecodeHuffman_BB13_40 = 6'd40;
parameter [5:0] LEGUP_F_DecodeHuffman_BB14_41 = 6'd41;
parameter [5:0] LEGUP_F_DecodeHuffman_BB14_42 = 6'd42;
parameter [5:0] LEGUP_F_DecodeHuffman_BB14_43 = 6'd43;
parameter [5:0] LEGUP_F_DecodeHuffman_BB14_44 = 6'd44;
parameter [5:0] LEGUP_F_DecodeHuffman_BB14_45 = 6'd45;
parameter [5:0] LEGUP_F_DecodeHuffman_BB15_46 = 6'd46;
parameter [5:0] LEGUP_F_DecodeHuffman_BB15_47 = 6'd47;
parameter [5:0] LEGUP_F_DecodeHuffman_BB15_48 = 6'd48;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_49 = 6'd49;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_50 = 6'd50;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_51 = 6'd51;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_52 = 6'd52;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_53 = 6'd53;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_54 = 6'd54;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_55 = 6'd55;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_56 = 6'd56;
parameter [5:0] LEGUP_F_DecodeHuffman_BB16_57 = 6'd57;
parameter [5:0] LEGUP_F_DecodeHuffman_BB17_58 = 6'd58;
input clk;
input reset;
input start;
output reg finish;
output reg [31:0] return_val;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_Xhuff_huffval;
input [31:0] arg_Dhuff_ml;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_Dhuff_maxcode;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_Dhuff_mincode;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] arg_Dhuff_valptr;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [5:0] cur_state;
reg [31:0] DecodeHuffman_0_1;
reg [31:0] DecodeHuffman_0_1_reg;
reg DecodeHuffman_0_2;
reg [31:0] DecodeHuffman___crit_edge_i__pre_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_3_4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_3_4_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_3_5;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_3_5_reg;
reg [7:0] DecodeHuffman_3_6;
reg DecodeHuffman_3_7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_8_9;
reg [7:0] DecodeHuffman_8_10;
reg [7:0] DecodeHuffman_8_10_reg;
reg DecodeHuffman_8_11;
reg [7:0] DecodeHuffman_14_temp_0_in_i_i;
reg [31:0] DecodeHuffman_14_temp_0_i_i;
reg [31:0] DecodeHuffman_pgetc_exit_i__0_i_i;
reg [31:0] DecodeHuffman_pgetc_exit_i__0_i_i_reg;
reg [31:0] DecodeHuffman_buf_getb_exit_15;
reg [31:0] DecodeHuffman_buf_getb_exit_15_reg;
reg [31:0] DecodeHuffman_buf_getb_exit_16;
reg [31:0] DecodeHuffman_buf_getb_exit_17;
reg [31:0] DecodeHuffman_buf_getb_exit_17_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit_18;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit_18_reg;
reg [31:0] DecodeHuffman_buf_getb_exit_19;
reg [31:0] DecodeHuffman_buf_getb_exit_20;
reg DecodeHuffman_buf_getb_exit_not__i;
reg [31:0] DecodeHuffman_buf_getb_exit___i;
reg [31:0] DecodeHuffman_buf_getb_exit___i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit_21;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit_21_reg;
reg [31:0] DecodeHuffman_buf_getb_exit_22;
reg DecodeHuffman_buf_getb_exit_23;
reg [31:0] DecodeHuffman__lr_ph__pre_i1;
reg [31:0] DecodeHuffman__lr_ph_24;
reg [31:0] DecodeHuffman__lr_ph_indvar;
reg [31:0] DecodeHuffman__lr_ph_indvar_reg;
reg [31:0] DecodeHuffman__lr_ph_code_010;
reg [31:0] DecodeHuffman__lr_ph_tmp;
reg [31:0] DecodeHuffman__lr_ph_tmp_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman__lr_ph_scevgep;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman__lr_ph_scevgep_reg;
reg [31:0] DecodeHuffman__lr_ph_25;
reg [31:0] DecodeHuffman__lr_ph_25_reg;
reg DecodeHuffman__lr_ph_26;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_27_28;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_27_28_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_27_29;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_27_29_reg;
reg [7:0] DecodeHuffman_27_30;
reg DecodeHuffman_27_31;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_32_33;
reg [7:0] DecodeHuffman_32_34;
reg [7:0] DecodeHuffman_32_34_reg;
reg DecodeHuffman_32_35;
reg [7:0] DecodeHuffman_38_temp_0_in_i_i3;
reg [31:0] DecodeHuffman_38_temp_0_i_i4;
reg [31:0] DecodeHuffman_pgetc_exit_i6__0_i_i5;
reg [31:0] DecodeHuffman_pgetc_exit_i6__0_i_i5_reg;
reg [31:0] DecodeHuffman_buf_getb_exit9_39;
reg [31:0] DecodeHuffman_buf_getb_exit9_39_reg;
reg [31:0] DecodeHuffman_buf_getb_exit9_40;
reg [31:0] DecodeHuffman_buf_getb_exit9_41;
reg [31:0] DecodeHuffman_buf_getb_exit9_41_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit9_42;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_buf_getb_exit9_42_reg;
reg [31:0] DecodeHuffman_buf_getb_exit9_43;
reg [31:0] DecodeHuffman_buf_getb_exit9_44;
reg DecodeHuffman_buf_getb_exit9_not__i7;
reg [31:0] DecodeHuffman_buf_getb_exit9___i8;
reg [31:0] DecodeHuffman_buf_getb_exit9_45;
reg [31:0] DecodeHuffman_buf_getb_exit9_45_reg;
reg [31:0] DecodeHuffman_buf_getb_exit9_46;
reg DecodeHuffman_buf_getb_exit9_47;
reg [31:0] DecodeHuffman_buf_getb_exit9_indvar_next;
reg [31:0] DecodeHuffman_buf_getb_exit9_indvar_next_reg;
reg [31:0] DecodeHuffman___crit_edge_l_0_lcssa;
reg [31:0] DecodeHuffman___crit_edge_l_0_lcssa_reg;
reg [31:0] DecodeHuffman___crit_edge_code_0_lcssa;
reg [31:0] DecodeHuffman___crit_edge_code_0_lcssa_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman___crit_edge_48;
reg [31:0] DecodeHuffman___crit_edge_49;
reg DecodeHuffman___crit_edge_50;
reg [31:0] DecodeHuffman_51_52;
reg [31:0] DecodeHuffman_51_53;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_51_54;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_51_54_reg;
reg [31:0] DecodeHuffman_51_55;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_51_56;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_51_56_reg;
reg [31:0] DecodeHuffman_51_57;
reg [31:0] DecodeHuffman_51_58;
reg [31:0] DecodeHuffman_51_58_reg;
reg [31:0] DecodeHuffman_51_59;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] DecodeHuffman_51_60;
reg [31:0] DecodeHuffman_51_61;
reg [31:0] DecodeHuffman_buf_getb_exit_15_phi_temp;
reg [31:0] DecodeHuffman_buf_getb_exit_16_phi_temp;
reg [7:0] DecodeHuffman_14_temp_0_in_i_i_phi_temp;
reg [31:0] DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp;
reg [31:0] DecodeHuffman__lr_ph__pre_i1_phi_temp;
reg [31:0] DecodeHuffman__lr_ph_24_phi_temp;
reg [31:0] DecodeHuffman__lr_ph_indvar_phi_temp;
reg [31:0] DecodeHuffman__lr_ph_code_010_phi_temp;
reg [31:0] DecodeHuffman___crit_edge_l_0_lcssa_phi_temp;
reg [31:0] DecodeHuffman___crit_edge_code_0_lcssa_phi_temp;
reg [31:0] DecodeHuffman_buf_getb_exit9_39_phi_temp;
reg [31:0] DecodeHuffman_buf_getb_exit9_40_phi_temp;
reg [7:0] DecodeHuffman_38_temp_0_in_i_i3_phi_temp;
reg [31:0] DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp;
/* Unsynthesizable Statements */
always @(posedge clk) begin
/* DecodeHuffman: %12*/
/* %13 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str30, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_DecodeHuffman_BB4_17)
begin
$write("Unanticipated marker detected.\n");
end
/* DecodeHuffman: %36*/
/* %37 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str30, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_DecodeHuffman_BB11_37)
begin
$write("Unanticipated marker detected.\n");
end
/* DecodeHuffman: %62*/
/* %63 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([20 x i8]* @.str26, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_DecodeHuffman_BB17_58)
begin
$write("Huffman read error\n");
end
/* DecodeHuffman: %62*/
/* tail call void @exit(i32 0) noreturn nounwind*/
if (cur_state == LEGUP_F_DecodeHuffman_BB17_58)
begin
$finish;
end
end
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 6'd0;
if (^reset !== 1'bX && ^(6'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_2;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB0_3;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB0_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_3 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_0_2 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_7;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB0_3 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_0_2 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_5;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_5;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_6;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB1_6;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB1_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB1_6 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_21;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_7;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_8;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_8;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_8 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_9;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_9;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_10;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_10;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_11;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_11;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_12;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB2_12;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB2_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_12 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_3_7 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB2_12 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_3_7 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB5_18;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB5_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_13;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_14;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_14;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_15;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_15;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_15 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_16;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB3_16;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB3_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_16 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_8_11 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB3_16 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_8_11 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB4_17;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB4_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB4_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB4_17;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB4_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB4_17 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB5_18;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB5_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB5_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB5_18;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB5_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB5_18 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB6_19;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB6_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB6_20;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB6_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB6_20;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB6_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_21;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_21;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_22;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_22;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_23;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_24;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_24 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_25;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB7_25;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB7_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB8_26;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB8_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_46;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB8_26;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB8_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman__lr_ph_26 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_27;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman__lr_ph_26 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_41;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_27;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_28;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_28;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_28 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_29;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_29;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_30;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_30;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_31;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_31;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB9_32;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB9_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_32 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_27_31 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_33;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB9_32 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_27_31 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB12_38;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB12_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_33;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_34;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_34;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_35;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_35;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_35 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB10_36;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB10_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_36 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_32_35 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB13_39;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB13_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB10_36 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_32_35 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB11_37;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB11_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB11_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB11_37;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB11_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB11_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB12_38;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB12_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB12_38 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB12_38;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB12_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB12_38 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB13_39;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB13_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB13_39;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB13_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB13_40;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB13_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB13_40;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB13_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_41;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_41;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_42;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_43;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_44 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_44;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_44 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB14_45;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB14_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB8_26;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB8_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_46;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_46;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_47;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_47 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_47;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_47 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_48 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB15_48;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB15_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_48 & memory_controller_waitrequest == 1'd0 & DecodeHuffman___crit_edge_50 == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_49;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB15_48 & memory_controller_waitrequest == 1'd0 & DecodeHuffman___crit_edge_50 == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB17_58;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB17_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_49;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_50;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_50 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_50;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_50 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_51;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_51;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_52;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_52;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_53;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_54;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_54 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_54;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_54 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_55;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_55;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_56;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_56 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_56;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_56 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_57;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_57 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB16_57;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB16_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB16_57 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB17_58 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_DecodeHuffman_BB17_58;
if (^reset !== 1'bX && ^(LEGUP_F_DecodeHuffman_BB17_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_DecodeHuffman_BB17_58 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
begin
DecodeHuffman_0_1 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB0_3)
begin
DecodeHuffman_0_1_reg <= DecodeHuffman_0_1;
if (^reset !== 1'bX && ^(DecodeHuffman_0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_0_1_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %0*/
/* %2 = icmp slt i32 %1, 0*/
begin
DecodeHuffman_0_2 = $signed(DecodeHuffman_0_1) < $signed(32'd0);
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge.i*/
/* %.pre.i = load i32* @current_read_byte, align 4, !tbaa !0*/
begin
DecodeHuffman___crit_edge_i__pre_i = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
begin
DecodeHuffman_3_4 = memory_controller_out[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
DecodeHuffman_3_4_reg <= DecodeHuffman_3_4;
if (^reset !== 1'bX && ^(DecodeHuffman_3_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_3_4_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %3*/
/* %5 = getelementptr inbounds i8* %4, i32 1*/
begin
DecodeHuffman_3_5 = DecodeHuffman_3_4 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %3*/
/* %5 = getelementptr inbounds i8* %4, i32 1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
DecodeHuffman_3_5_reg <= DecodeHuffman_3_5;
if (^reset !== 1'bX && ^(DecodeHuffman_3_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_3_5_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %3*/
/* %6 = load i8* %4, align 1, !tbaa !1*/
begin
DecodeHuffman_3_6 = memory_controller_out[7:0];
end
end
always @(*) begin
/* DecodeHuffman: %3*/
/* %7 = icmp eq i8 %6, -1*/
begin
DecodeHuffman_3_7 = DecodeHuffman_3_6 == -8'd1;
end
end
always @(*) begin
/* DecodeHuffman: %8*/
/* %9 = getelementptr inbounds i8* %4, i32 2*/
begin
DecodeHuffman_8_9 = DecodeHuffman_3_4_reg + 1 * 32'd2;
end
end
always @(*) begin
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
begin
DecodeHuffman_8_10 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_16)
begin
DecodeHuffman_8_10_reg <= DecodeHuffman_8_10;
if (^reset !== 1'bX && ^(DecodeHuffman_8_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_8_10_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %8*/
/* %11 = icmp eq i8 %10, 0*/
begin
DecodeHuffman_8_11 = DecodeHuffman_8_10 == 8'd0;
end
end
always @(*) begin
/* DecodeHuffman: %14*/
/* %temp.0.in.i.i = phi i8 [ %10, %12 ], [ %6, %3 ]*/
begin
DecodeHuffman_14_temp_0_in_i_i = DecodeHuffman_14_temp_0_in_i_i_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %14*/
/* %temp.0.i.i = zext i8 %temp.0.in.i.i to i32*/
begin
DecodeHuffman_14_temp_0_i_i = DecodeHuffman_14_temp_0_in_i_i;
end
end
always @(*) begin
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
DecodeHuffman_pgetc_exit_i__0_i_i = DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB6_19) */
begin
DecodeHuffman_pgetc_exit_i__0_i_i = DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
DecodeHuffman_pgetc_exit_i__0_i_i_reg <= DecodeHuffman_pgetc_exit_i__0_i_i;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i__0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i__0_i_i_reg"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
DecodeHuffman_pgetc_exit_i__0_i_i_reg <= DecodeHuffman_pgetc_exit_i__0_i_i;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i__0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i__0_i_i_reg"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
DecodeHuffman_pgetc_exit_i__0_i_i_reg <= DecodeHuffman_pgetc_exit_i__0_i_i;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i__0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i__0_i_i_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15 = DecodeHuffman_buf_getb_exit_15_phi_temp;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
else if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15 = DecodeHuffman_buf_getb_exit_15_phi_temp;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB7_21) */
begin
DecodeHuffman_buf_getb_exit_15 = DecodeHuffman_buf_getb_exit_15_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15_reg <= DecodeHuffman_buf_getb_exit_15;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15_reg <= DecodeHuffman_buf_getb_exit_15;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15_reg <= DecodeHuffman_buf_getb_exit_15;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_15_reg <= DecodeHuffman_buf_getb_exit_15;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %16 = phi i32 [ 7, %pgetc.exit.i ], [ %1, %._crit_edge.i ]*/
begin
DecodeHuffman_buf_getb_exit_16 = DecodeHuffman_buf_getb_exit_16_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %17 = add nsw i32 %16, -1*/
begin
DecodeHuffman_buf_getb_exit_17 = DecodeHuffman_buf_getb_exit_16 + -32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %17 = add nsw i32 %16, -1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_17_reg <= DecodeHuffman_buf_getb_exit_17;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_17_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %18 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %16*/
begin
DecodeHuffman_buf_getb_exit_18 = `TAG_g_bit_set_mask_a + 4 * DecodeHuffman_buf_getb_exit_16;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %18 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %16*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_18_reg <= DecodeHuffman_buf_getb_exit_18;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_18_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %19 = load i32* %18, align 4, !tbaa !0*/
begin
DecodeHuffman_buf_getb_exit_19 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %20 = and i32 %19, %15*/
begin
DecodeHuffman_buf_getb_exit_20 = DecodeHuffman_buf_getb_exit_19 & DecodeHuffman_buf_getb_exit_15_reg;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %not..i = icmp ne i32 %20, 0*/
begin
DecodeHuffman_buf_getb_exit_not__i = DecodeHuffman_buf_getb_exit_20 != 32'd0;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %..i = zext i1 %not..i to i32*/
begin
DecodeHuffman_buf_getb_exit___i = DecodeHuffman_buf_getb_exit_not__i;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %..i = zext i1 %not..i to i32*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_24)
begin
DecodeHuffman_buf_getb_exit___i_reg <= DecodeHuffman_buf_getb_exit___i;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit___i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit___i_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %21 = getelementptr inbounds i32* %Dhuff_maxcode, i32 1*/
begin
DecodeHuffman_buf_getb_exit_21 = arg_Dhuff_maxcode + 4 * 32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %21 = getelementptr inbounds i32* %Dhuff_maxcode, i32 1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
DecodeHuffman_buf_getb_exit_21_reg <= DecodeHuffman_buf_getb_exit_21;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_21_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %22 = load i32* %21, align 4, !tbaa !0*/
begin
DecodeHuffman_buf_getb_exit_22 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %23 = icmp sgt i32 %..i, %22*/
begin
DecodeHuffman_buf_getb_exit_23 = $signed(DecodeHuffman_buf_getb_exit___i_reg) > $signed(DecodeHuffman_buf_getb_exit_22);
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %.pre.i1 = phi i32 [ %39, %buf_getb.exit9 ], [ %15, %buf_getb.exit ]*/
begin
DecodeHuffman__lr_ph__pre_i1 = DecodeHuffman__lr_ph__pre_i1_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %24 = phi i32 [ %41, %buf_getb.exit9 ], [ %17, %buf_getb.exit ]*/
begin
DecodeHuffman__lr_ph_24 = DecodeHuffman__lr_ph_24_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_indvar = DecodeHuffman__lr_ph_indvar_phi_temp;
end
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB8_26) */
begin
DecodeHuffman__lr_ph_indvar = DecodeHuffman__lr_ph_indvar_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_indvar_reg <= DecodeHuffman__lr_ph_indvar;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_indvar_reg"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_indvar_reg <= DecodeHuffman__lr_ph_indvar;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_indvar_reg"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_indvar_reg <= DecodeHuffman__lr_ph_indvar;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_indvar) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_indvar_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %code.010 = phi i32 [ %45, %buf_getb.exit9 ], [ %..i, %buf_getb.exit ]*/
begin
DecodeHuffman__lr_ph_code_010 = DecodeHuffman__lr_ph_code_010_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %tmp = add i32 %indvar, 2*/
begin
DecodeHuffman__lr_ph_tmp = DecodeHuffman__lr_ph_indvar + 32'd2;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %tmp = add i32 %indvar, 2*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_tmp_reg <= DecodeHuffman__lr_ph_tmp;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_tmp) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_tmp_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %scevgep = getelementptr i32* %Dhuff_maxcode, i32 %tmp*/
begin
DecodeHuffman__lr_ph_scevgep = arg_Dhuff_maxcode + 4 * DecodeHuffman__lr_ph_tmp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %scevgep = getelementptr i32* %Dhuff_maxcode, i32 %tmp*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_scevgep_reg <= DecodeHuffman__lr_ph_scevgep;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_scevgep) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_scevgep_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %25 = shl i32 %code.010, 1*/
begin
DecodeHuffman__lr_ph_25 = DecodeHuffman__lr_ph_code_010 <<< 32'd1 % 32;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %25 = shl i32 %code.010, 1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26)
begin
DecodeHuffman__lr_ph_25_reg <= DecodeHuffman__lr_ph_25;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_25_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %.lr.ph*/
/* %26 = icmp slt i32 %24, 0*/
begin
DecodeHuffman__lr_ph_26 = $signed(DecodeHuffman__lr_ph_24) < $signed(32'd0);
end
end
always @(*) begin
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
begin
DecodeHuffman_27_28 = memory_controller_out[`MEMORY_CONTROLLER_ADDR_SIZE-1:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
DecodeHuffman_27_28_reg <= DecodeHuffman_27_28;
if (^reset !== 1'bX && ^(DecodeHuffman_27_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_27_28_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %27*/
/* %29 = getelementptr inbounds i8* %28, i32 1*/
begin
DecodeHuffman_27_29 = DecodeHuffman_27_28 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %27*/
/* %29 = getelementptr inbounds i8* %28, i32 1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
DecodeHuffman_27_29_reg <= DecodeHuffman_27_29;
if (^reset !== 1'bX && ^(DecodeHuffman_27_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_27_29_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %27*/
/* %30 = load i8* %28, align 1, !tbaa !1*/
begin
DecodeHuffman_27_30 = memory_controller_out[7:0];
end
end
always @(*) begin
/* DecodeHuffman: %27*/
/* %31 = icmp eq i8 %30, -1*/
begin
DecodeHuffman_27_31 = DecodeHuffman_27_30 == -8'd1;
end
end
always @(*) begin
/* DecodeHuffman: %32*/
/* %33 = getelementptr inbounds i8* %28, i32 2*/
begin
DecodeHuffman_32_33 = DecodeHuffman_27_28_reg + 1 * 32'd2;
end
end
always @(*) begin
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
begin
DecodeHuffman_32_34 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_36)
begin
DecodeHuffman_32_34_reg <= DecodeHuffman_32_34;
if (^reset !== 1'bX && ^(DecodeHuffman_32_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_32_34_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %32*/
/* %35 = icmp eq i8 %34, 0*/
begin
DecodeHuffman_32_35 = DecodeHuffman_32_34 == 8'd0;
end
end
always @(*) begin
/* DecodeHuffman: %38*/
/* %temp.0.in.i.i3 = phi i8 [ %34, %36 ], [ %30, %27 ]*/
begin
DecodeHuffman_38_temp_0_in_i_i3 = DecodeHuffman_38_temp_0_in_i_i3_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %38*/
/* %temp.0.i.i4 = zext i8 %temp.0.in.i.i3 to i32*/
begin
DecodeHuffman_38_temp_0_i_i4 = DecodeHuffman_38_temp_0_in_i_i3;
end
end
always @(*) begin
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5 = DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB13_39) */
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5 = DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5_reg <= DecodeHuffman_pgetc_exit_i6__0_i_i5;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i6__0_i_i5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i6__0_i_i5_reg"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5_reg <= DecodeHuffman_pgetc_exit_i6__0_i_i5;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i6__0_i_i5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i6__0_i_i5_reg"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5_reg <= DecodeHuffman_pgetc_exit_i6__0_i_i5;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i6__0_i_i5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i6__0_i_i5_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39 = DecodeHuffman_buf_getb_exit9_39_phi_temp;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
else if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39 = DecodeHuffman_buf_getb_exit9_39_phi_temp;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB14_41) */
begin
DecodeHuffman_buf_getb_exit9_39 = DecodeHuffman_buf_getb_exit9_39_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39_reg <= DecodeHuffman_buf_getb_exit9_39;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39_reg <= DecodeHuffman_buf_getb_exit9_39;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39_reg <= DecodeHuffman_buf_getb_exit9_39;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_reg"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_39_reg <= DecodeHuffman_buf_getb_exit9_39;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %40 = phi i32 [ 7, %pgetc.exit.i6 ], [ %24, %.lr.ph ]*/
begin
DecodeHuffman_buf_getb_exit9_40 = DecodeHuffman_buf_getb_exit9_40_phi_temp;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %41 = add nsw i32 %40, -1*/
begin
DecodeHuffman_buf_getb_exit9_41 = DecodeHuffman_buf_getb_exit9_40 + -32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %41 = add nsw i32 %40, -1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_41_reg <= DecodeHuffman_buf_getb_exit9_41;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_41_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %42 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %40*/
begin
DecodeHuffman_buf_getb_exit9_42 = `TAG_g_bit_set_mask_a + 4 * DecodeHuffman_buf_getb_exit9_40;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %42 = getelementptr inbounds [32 x i32]* @bit_set_mask, i32 0, i32 %40*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_42_reg <= DecodeHuffman_buf_getb_exit9_42;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_42_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %43 = load i32* %42, align 4, !tbaa !0*/
begin
DecodeHuffman_buf_getb_exit9_43 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %44 = and i32 %43, %39*/
begin
DecodeHuffman_buf_getb_exit9_44 = DecodeHuffman_buf_getb_exit9_43 & DecodeHuffman_buf_getb_exit9_39_reg;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %not..i7 = icmp ne i32 %44, 0*/
begin
DecodeHuffman_buf_getb_exit9_not__i7 = DecodeHuffman_buf_getb_exit9_44 != 32'd0;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %..i8 = zext i1 %not..i7 to i32*/
begin
DecodeHuffman_buf_getb_exit9___i8 = DecodeHuffman_buf_getb_exit9_not__i7;
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %45 = or i32 %..i8, %25*/
begin
DecodeHuffman_buf_getb_exit9_45 = DecodeHuffman_buf_getb_exit9___i8 | DecodeHuffman__lr_ph_25_reg;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %45 = or i32 %..i8, %25*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_44)
begin
DecodeHuffman_buf_getb_exit9_45_reg <= DecodeHuffman_buf_getb_exit9_45;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_45_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %46 = load i32* %scevgep, align 4, !tbaa !0*/
begin
DecodeHuffman_buf_getb_exit9_46 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %47 = icmp sgt i32 %45, %46*/
begin
DecodeHuffman_buf_getb_exit9_47 = $signed(DecodeHuffman_buf_getb_exit9_45_reg) > $signed(DecodeHuffman_buf_getb_exit9_46);
end
end
always @(*) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %indvar.next = add i32 %indvar, 1*/
begin
DecodeHuffman_buf_getb_exit9_indvar_next = DecodeHuffman__lr_ph_indvar_reg + 32'd1;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %indvar.next = add i32 %indvar, 1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
DecodeHuffman_buf_getb_exit9_indvar_next_reg <= DecodeHuffman_buf_getb_exit9_indvar_next;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_indvar_next) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_indvar_next_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa = DecodeHuffman___crit_edge_l_0_lcssa_phi_temp;
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
else if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa = DecodeHuffman___crit_edge_l_0_lcssa_phi_temp;
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB15_46) */
begin
DecodeHuffman___crit_edge_l_0_lcssa = DecodeHuffman___crit_edge_l_0_lcssa_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa_reg <= DecodeHuffman___crit_edge_l_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_l_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa_reg <= DecodeHuffman___crit_edge_l_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_l_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa_reg <= DecodeHuffman___crit_edge_l_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_l_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_l_0_lcssa_reg <= DecodeHuffman___crit_edge_l_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_l_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa = DecodeHuffman___crit_edge_code_0_lcssa_phi_temp;
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
else if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa = DecodeHuffman___crit_edge_code_0_lcssa_phi_temp;
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
else /* if (cur_state == LEGUP_F_DecodeHuffman_BB15_46) */
begin
DecodeHuffman___crit_edge_code_0_lcssa = DecodeHuffman___crit_edge_code_0_lcssa_phi_temp;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa_reg <= DecodeHuffman___crit_edge_code_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_code_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa_reg <= DecodeHuffman___crit_edge_code_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_code_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa_reg <= DecodeHuffman___crit_edge_code_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_code_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_reg"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
DecodeHuffman___crit_edge_code_0_lcssa_reg <= DecodeHuffman___crit_edge_code_0_lcssa;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_code_0_lcssa) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge*/
/* %48 = getelementptr inbounds i32* %Dhuff_maxcode, i32 %Dhuff_ml*/
begin
DecodeHuffman___crit_edge_48 = arg_Dhuff_maxcode + 4 * arg_Dhuff_ml;
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge*/
/* %49 = load i32* %48, align 4, !tbaa !0*/
begin
DecodeHuffman___crit_edge_49 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %._crit_edge*/
/* %50 = icmp slt i32 %code.0.lcssa, %49*/
begin
DecodeHuffman___crit_edge_50 = $signed(DecodeHuffman___crit_edge_code_0_lcssa_reg) < $signed(DecodeHuffman___crit_edge_49);
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %52 = load i32* @main_result, align 4, !tbaa !0*/
begin
DecodeHuffman_51_52 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %53 = add nsw i32 %52, 1*/
begin
DecodeHuffman_51_53 = DecodeHuffman_51_52 + 32'd1;
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %54 = getelementptr inbounds i32* %Dhuff_valptr, i32 %l.0.lcssa*/
begin
DecodeHuffman_51_54 = arg_Dhuff_valptr + 4 * DecodeHuffman___crit_edge_l_0_lcssa_reg;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %51*/
/* %54 = getelementptr inbounds i32* %Dhuff_valptr, i32 %l.0.lcssa*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
DecodeHuffman_51_54_reg <= DecodeHuffman_51_54;
if (^reset !== 1'bX && ^(DecodeHuffman_51_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_51_54_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %55 = load i32* %54, align 4, !tbaa !0*/
begin
DecodeHuffman_51_55 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %56 = getelementptr inbounds i32* %Dhuff_mincode, i32 %l.0.lcssa*/
begin
DecodeHuffman_51_56 = arg_Dhuff_mincode + 4 * DecodeHuffman___crit_edge_l_0_lcssa_reg;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %51*/
/* %56 = getelementptr inbounds i32* %Dhuff_mincode, i32 %l.0.lcssa*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
DecodeHuffman_51_56_reg <= DecodeHuffman_51_56;
if (^reset !== 1'bX && ^(DecodeHuffman_51_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_51_56_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %57 = load i32* %56, align 4, !tbaa !0*/
begin
DecodeHuffman_51_57 = memory_controller_out[31:0];
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %58 = add i32 %55, %code.0.lcssa*/
begin
DecodeHuffman_51_58 = DecodeHuffman_51_55 + DecodeHuffman___crit_edge_code_0_lcssa_reg;
end
end
always @(posedge clk) begin
/* DecodeHuffman: %51*/
/* %58 = add i32 %55, %code.0.lcssa*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_54)
begin
DecodeHuffman_51_58_reg <= DecodeHuffman_51_58;
if (^reset !== 1'bX && ^(DecodeHuffman_51_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_51_58_reg"); $finish; end
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %59 = sub i32 %58, %57*/
begin
DecodeHuffman_51_59 = DecodeHuffman_51_58_reg - DecodeHuffman_51_57;
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %60 = getelementptr inbounds i32* %Xhuff_huffval, i32 %59*/
begin
DecodeHuffman_51_60 = arg_Xhuff_huffval + 4 * DecodeHuffman_51_59;
end
end
always @(*) begin
/* DecodeHuffman: %51*/
/* %61 = load i32* %60, align 4, !tbaa !0*/
begin
DecodeHuffman_51_61 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_6 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit_15_phi_temp <= DecodeHuffman___crit_edge_i__pre_i;
if (^reset !== 1'bX && ^(DecodeHuffman___crit_edge_i__pre_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_phi_temp"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit*/
/* %15 = phi i32 [ %.0.i.i, %pgetc.exit.i ], [ %.pre.i, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit_15_phi_temp <= DecodeHuffman_pgetc_exit_i__0_i_i_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i__0_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_15_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit*/
/* %16 = phi i32 [ 7, %pgetc.exit.i ], [ %1, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_6 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit_16_phi_temp <= DecodeHuffman_0_1_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_0_1_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_16_phi_temp"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit*/
/* %16 = phi i32 [ 7, %pgetc.exit.i ], [ %1, %._crit_edge.i ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit_16_phi_temp <= 32'd7;
if (^reset !== 1'bX && ^(32'd7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit_16_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %14*/
/* %temp.0.in.i.i = phi i8 [ %10, %12 ], [ %6, %3 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_12 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_3_7 == 1'd0)
begin
DecodeHuffman_14_temp_0_in_i_i_phi_temp <= DecodeHuffman_3_6;
if (^reset !== 1'bX && ^(DecodeHuffman_3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_14_temp_0_in_i_i_phi_temp"); $finish; end
end
/* DecodeHuffman: %14*/
/* %temp.0.in.i.i = phi i8 [ %10, %12 ], [ %6, %3 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB4_17 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_14_temp_0_in_i_i_phi_temp <= DecodeHuffman_8_10_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_8_10_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_14_temp_0_in_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_16 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_8_11 == 1'd1)
begin
DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i*/
/* %.0.i.i = phi i32 [ %temp.0.i.i, %14 ], [ 255, %8 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB5_18 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp <= DecodeHuffman_14_temp_0_i_i;
if (^reset !== 1'bX && ^(DecodeHuffman_14_temp_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i__0_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %.pre.i1 = phi i32 [ %39, %buf_getb.exit9 ], [ %15, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd1)
begin
DecodeHuffman__lr_ph__pre_i1_phi_temp <= DecodeHuffman_buf_getb_exit_15_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_15_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph__pre_i1_phi_temp"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %.pre.i1 = phi i32 [ %39, %buf_getb.exit9 ], [ %15, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd1)
begin
DecodeHuffman__lr_ph__pre_i1_phi_temp <= DecodeHuffman_buf_getb_exit9_39_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_39_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph__pre_i1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %24 = phi i32 [ %41, %buf_getb.exit9 ], [ %17, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd1)
begin
DecodeHuffman__lr_ph_24_phi_temp <= DecodeHuffman_buf_getb_exit_17_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit_17_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_24_phi_temp"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %24 = phi i32 [ %41, %buf_getb.exit9 ], [ %17, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd1)
begin
DecodeHuffman__lr_ph_24_phi_temp <= DecodeHuffman_buf_getb_exit9_41_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_41_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_24_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd1)
begin
DecodeHuffman__lr_ph_indvar_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_indvar_phi_temp"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %indvar = phi i32 [ %indvar.next, %buf_getb.exit9 ], [ 0, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd1)
begin
DecodeHuffman__lr_ph_indvar_phi_temp <= DecodeHuffman_buf_getb_exit9_indvar_next_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_indvar_next_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_indvar_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %.lr.ph*/
/* %code.010 = phi i32 [ %45, %buf_getb.exit9 ], [ %..i, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd1)
begin
DecodeHuffman__lr_ph_code_010_phi_temp <= DecodeHuffman_buf_getb_exit___i_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit___i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_code_010_phi_temp"); $finish; end
end
/* DecodeHuffman: %.lr.ph*/
/* %code.010 = phi i32 [ %45, %buf_getb.exit9 ], [ %..i, %buf_getb.exit ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd1)
begin
DecodeHuffman__lr_ph_code_010_phi_temp <= DecodeHuffman_buf_getb_exit9_45_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_45_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman__lr_ph_code_010_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd0)
begin
DecodeHuffman___crit_edge_l_0_lcssa_phi_temp <= 32'd1;
if (^reset !== 1'bX && ^(32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_phi_temp"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %l.0.lcssa = phi i32 [ 1, %buf_getb.exit ], [ %tmp, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd0)
begin
DecodeHuffman___crit_edge_l_0_lcssa_phi_temp <= DecodeHuffman__lr_ph_tmp_reg;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_tmp_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_l_0_lcssa_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_25 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit_23 == 1'd0)
begin
DecodeHuffman___crit_edge_code_0_lcssa_phi_temp <= DecodeHuffman_buf_getb_exit___i_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit___i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_phi_temp"); $finish; end
end
/* DecodeHuffman: %._crit_edge*/
/* %code.0.lcssa = phi i32 [ %..i, %buf_getb.exit ], [ %45, %buf_getb.exit9 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_45 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_buf_getb_exit9_47 == 1'd0)
begin
DecodeHuffman___crit_edge_code_0_lcssa_phi_temp <= DecodeHuffman_buf_getb_exit9_45_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_buf_getb_exit9_45_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman___crit_edge_code_0_lcssa_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman__lr_ph_26 == 1'd0)
begin
DecodeHuffman_buf_getb_exit9_39_phi_temp <= DecodeHuffman__lr_ph__pre_i1;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph__pre_i1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_phi_temp"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %39 = phi i32 [ %.0.i.i5, %pgetc.exit.i6 ], [ %.pre.i1, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit9_39_phi_temp <= DecodeHuffman_pgetc_exit_i6__0_i_i5_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_pgetc_exit_i6__0_i_i5_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_39_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %buf_getb.exit9*/
/* %40 = phi i32 [ 7, %pgetc.exit.i6 ], [ %24, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB8_26 & memory_controller_waitrequest == 1'd0 & DecodeHuffman__lr_ph_26 == 1'd0)
begin
DecodeHuffman_buf_getb_exit9_40_phi_temp <= DecodeHuffman__lr_ph_24;
if (^reset !== 1'bX && ^(DecodeHuffman__lr_ph_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_40_phi_temp"); $finish; end
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %40 = phi i32 [ 7, %pgetc.exit.i6 ], [ %24, %.lr.ph ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_buf_getb_exit9_40_phi_temp <= 32'd7;
if (^reset !== 1'bX && ^(32'd7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_buf_getb_exit9_40_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %38*/
/* %temp.0.in.i.i3 = phi i8 [ %34, %36 ], [ %30, %27 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_32 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_27_31 == 1'd0)
begin
DecodeHuffman_38_temp_0_in_i_i3_phi_temp <= DecodeHuffman_27_30;
if (^reset !== 1'bX && ^(DecodeHuffman_27_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_38_temp_0_in_i_i3_phi_temp"); $finish; end
end
/* DecodeHuffman: %38*/
/* %temp.0.in.i.i3 = phi i8 [ %34, %36 ], [ %30, %27 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB11_37 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_38_temp_0_in_i_i3_phi_temp <= DecodeHuffman_32_34_reg;
if (^reset !== 1'bX && ^(DecodeHuffman_32_34_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_38_temp_0_in_i_i3_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_36 & memory_controller_waitrequest == 1'd0 & DecodeHuffman_32_35 == 1'd1)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp"); $finish; end
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* %.0.i.i5 = phi i32 [ %temp.0.i.i4, %38 ], [ 255, %32 ]*/
if (cur_state == LEGUP_F_DecodeHuffman_BB12_38 & memory_controller_waitrequest == 1'd0)
begin
DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp <= DecodeHuffman_38_temp_0_i_i4;
if (^reset !== 1'bX && ^(DecodeHuffman_38_temp_0_i_i4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to DecodeHuffman_pgetc_exit_i6__0_i_i5_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* DecodeHuffman: %51*/
/* ret i32 %61*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_57)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
return_val <= 0;
if (^reset !== 1'bX && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
/* DecodeHuffman: %51*/
/* ret i32 %61*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_57)
begin
return_val <= DecodeHuffman_51_61;
if (^reset !== 1'bX && ^(DecodeHuffman_51_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* DecodeHuffman: %._crit_edge.i*/
/* %.pre.i = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %3*/
/* store i8* %5, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %3*/
/* %6 = load i8* %4, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10)
begin
memory_controller_address = DecodeHuffman_3_4_reg;
end
/* DecodeHuffman: %8*/
/* store i8* %9, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14)
begin
memory_controller_address = DecodeHuffman_3_5_reg;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 %.0.i.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* DecodeHuffman: %buf_getb.exit*/
/* store i32 %17, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %19 = load i32* %18, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22)
begin
memory_controller_address = DecodeHuffman_buf_getb_exit_18_reg;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %22 = load i32* %21, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23)
begin
memory_controller_address = DecodeHuffman_buf_getb_exit_21_reg;
end
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %27*/
/* store i8* %29, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %27*/
/* %30 = load i8* %28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30)
begin
memory_controller_address = DecodeHuffman_27_28_reg;
end
/* DecodeHuffman: %32*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34)
begin
memory_controller_address = DecodeHuffman_27_29_reg;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 %.0.i.i5, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
memory_controller_address = `TAG_g_current_read_byte_a;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* store i32 %41, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
memory_controller_address = `TAG_g_read_position_a;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %43 = load i32* %42, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42)
begin
memory_controller_address = DecodeHuffman_buf_getb_exit9_42_reg;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %46 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43)
begin
memory_controller_address = DecodeHuffman__lr_ph_scevgep_reg;
end
/* DecodeHuffman: %._crit_edge*/
/* %49 = load i32* %48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
memory_controller_address = DecodeHuffman___crit_edge_48;
end
/* DecodeHuffman: %51*/
/* %52 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* DecodeHuffman: %51*/
/* store i32 %53, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* DecodeHuffman: %51*/
/* %55 = load i32* %54, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52)
begin
memory_controller_address = DecodeHuffman_51_54_reg;
end
/* DecodeHuffman: %51*/
/* %57 = load i32* %56, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53)
begin
memory_controller_address = DecodeHuffman_51_56_reg;
end
/* DecodeHuffman: %51*/
/* %61 = load i32* %60, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55)
begin
memory_controller_address = DecodeHuffman_51_60;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %._crit_edge.i*/
/* %.pre.i = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %3*/
/* store i8* %5, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %3*/
/* %6 = load i8* %4, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %8*/
/* store i8* %9, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 %.0.i.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit*/
/* store i32 %17, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %19 = load i32* %18, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %22 = load i32* %21, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %27*/
/* store i8* %29, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %27*/
/* %30 = load i8* %28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %32*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 %.0.i.i5, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* store i32 %41, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %43 = load i32* %42, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %46 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %._crit_edge*/
/* %49 = load i32* %48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* %52 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* store i32 %53, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* %55 = load i32* %54, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* %57 = load i32* %56, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53)
begin
memory_controller_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* %61 = load i32* %60, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %._crit_edge.i*/
/* %.pre.i = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %3*/
/* store i8* %5, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %3*/
/* %6 = load i8* %4, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %8*/
/* store i8* %9, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 %.0.i.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit*/
/* store i32 %17, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %19 = load i32* %18, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %22 = load i32* %21, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %27*/
/* store i8* %29, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %27*/
/* %30 = load i8* %28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %32*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 %.0.i.i5, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* store i32 %41, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %43 = load i32* %42, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %46 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %._crit_edge*/
/* %49 = load i32* %48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %51*/
/* %52 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %51*/
/* store i32 %53, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51)
begin
memory_controller_write_enable = 1'd1;
end
/* DecodeHuffman: %51*/
/* %55 = load i32* %54, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %51*/
/* %57 = load i32* %56, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53)
begin
memory_controller_write_enable = 1'd0;
end
/* DecodeHuffman: %51*/
/* %61 = load i32* %60, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55)
begin
memory_controller_write_enable = 1'd0;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* DecodeHuffman: %3*/
/* store i8* %5, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
memory_controller_in = DecodeHuffman_3_5;
end
/* DecodeHuffman: %8*/
/* store i8* %9, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13)
begin
memory_controller_in = DecodeHuffman_8_9;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 %.0.i.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
memory_controller_in = DecodeHuffman_pgetc_exit_i__0_i_i;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20)
begin
memory_controller_in = 32'd7;
end
/* DecodeHuffman: %buf_getb.exit*/
/* store i32 %17, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
memory_controller_in = DecodeHuffman_buf_getb_exit_17;
end
/* DecodeHuffman: %27*/
/* store i8* %29, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
memory_controller_in = DecodeHuffman_27_29;
end
/* DecodeHuffman: %32*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33)
begin
memory_controller_in = DecodeHuffman_32_33;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 %.0.i.i5, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
memory_controller_in = DecodeHuffman_pgetc_exit_i6__0_i_i5;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40)
begin
memory_controller_in = 32'd7;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* store i32 %41, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
memory_controller_in = DecodeHuffman_buf_getb_exit9_41;
end
/* DecodeHuffman: %51*/
/* store i32 %53, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51)
begin
memory_controller_in = DecodeHuffman_51_53;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* DecodeHuffman: %0*/
/* %1 = load i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB0_1)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %._crit_edge.i*/
/* %.pre.i = load i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB1_4)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %3*/
/* %4 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_7)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %3*/
/* store i8* %5, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_9)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %3*/
/* %6 = load i8* %4, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB2_10)
begin
memory_controller_size = 2'd0;
end
/* DecodeHuffman: %8*/
/* store i8* %9, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_13)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %8*/
/* %10 = load i8* %5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB3_14)
begin
memory_controller_size = 2'd0;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 %.0.i.i, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_19)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %pgetc.exit.i*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB6_20)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit*/
/* store i32 %17, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_21)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %19 = load i32* %18, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_22)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit*/
/* %22 = load i32* %21, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB7_23)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %27*/
/* %28 = load i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_27)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %27*/
/* store i8* %29, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_29)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %27*/
/* %30 = load i8* %28, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB9_30)
begin
memory_controller_size = 2'd0;
end
/* DecodeHuffman: %32*/
/* store i8* %33, i8** @CurHuffReadBuf, align 4, !tbaa !3*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_33)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %32*/
/* %34 = load i8* %29, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_DecodeHuffman_BB10_34)
begin
memory_controller_size = 2'd0;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 %.0.i.i5, i32* @current_read_byte, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_39)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %pgetc.exit.i6*/
/* store i32 7, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB13_40)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* store i32 %41, i32* @read_position, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_41)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %43 = load i32* %42, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_42)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %buf_getb.exit9*/
/* %46 = load i32* %scevgep, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB14_43)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %._crit_edge*/
/* %49 = load i32* %48, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB15_46)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %51*/
/* %52 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_49)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %51*/
/* store i32 %53, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_51)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %51*/
/* %55 = load i32* %54, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_52)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %51*/
/* %57 = load i32* %56, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_53)
begin
memory_controller_size = 2'd2;
end
/* DecodeHuffman: %51*/
/* %61 = load i32* %60, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_DecodeHuffman_BB16_55)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module main
(
clk,
reset,
start,
finish,
return_val,
memory_controller_address,
memory_controller_enable,
memory_controller_write_enable,
memory_controller_waitrequest,
memory_controller_in,
memory_controller_size,
memory_controller_out
);
parameter [8:0] LEGUP_0 = 9'd0;
parameter [8:0] LEGUP_F_main_BB0_1 = 9'd1;
parameter [8:0] LEGUP_F_main_BB1_2 = 9'd2;
parameter [8:0] LEGUP_F_main_BB1_3 = 9'd3;
parameter [8:0] LEGUP_F_main_BB1_4 = 9'd4;
parameter [8:0] LEGUP_F_main_BB2_5 = 9'd5;
parameter [8:0] LEGUP_F_main_BB3_6 = 9'd6;
parameter [8:0] LEGUP_F_main_BB4_7 = 9'd7;
parameter [8:0] LEGUP_F_main_BB5_8 = 9'd8;
parameter [8:0] LEGUP_F_main_BB6_9 = 9'd9;
parameter [8:0] LEGUP_F_main_BB7_10 = 9'd10;
parameter [8:0] LEGUP_F_main_BB7_11 = 9'd11;
parameter [8:0] LEGUP_F_main_BB7_12 = 9'd12;
parameter [8:0] LEGUP_F_main_BB7_13 = 9'd13;
parameter [8:0] LEGUP_F_main_BB8_14 = 9'd14;
parameter [8:0] LEGUP_F_main_BB9_15 = 9'd15;
parameter [8:0] LEGUP_F_main_BB9_16 = 9'd16;
parameter [8:0] LEGUP_F_main_BB9_17 = 9'd17;
parameter [8:0] LEGUP_F_main_BB10_18 = 9'd18;
parameter [8:0] LEGUP_F_main_BB11_19 = 9'd19;
parameter [8:0] LEGUP_F_main_BB11_20 = 9'd20;
parameter [8:0] LEGUP_F_main_BB11_21 = 9'd21;
parameter [8:0] LEGUP_F_main_BB12_22 = 9'd22;
parameter [8:0] LEGUP_F_main_BB12_23 = 9'd23;
parameter [8:0] LEGUP_F_main_BB12_24 = 9'd24;
parameter [8:0] LEGUP_F_main_BB13_25 = 9'd25;
parameter [8:0] LEGUP_F_main_BB14_26 = 9'd26;
parameter [8:0] LEGUP_F_main_BB15_27 = 9'd27;
parameter [8:0] LEGUP_F_main_BB15_28 = 9'd28;
parameter [8:0] LEGUP_F_main_BB15_29 = 9'd29;
parameter [8:0] LEGUP_F_main_BB16_30 = 9'd30;
parameter [8:0] LEGUP_F_main_BB17_31 = 9'd31;
parameter [8:0] LEGUP_F_main_BB17_32 = 9'd32;
parameter [8:0] LEGUP_F_main_BB17_33 = 9'd33;
parameter [8:0] LEGUP_F_main_BB17_34 = 9'd34;
parameter [8:0] LEGUP_F_main_BB18_35 = 9'd35;
parameter [8:0] LEGUP_F_main_BB18_36 = 9'd36;
parameter [8:0] LEGUP_F_main_BB18_37 = 9'd37;
parameter [8:0] LEGUP_F_main_BB19_38 = 9'd38;
parameter [8:0] LEGUP_F_main_BB20_39 = 9'd39;
parameter [8:0] LEGUP_F_main_BB20_40 = 9'd40;
parameter [8:0] LEGUP_F_main_BB20_41 = 9'd41;
parameter [8:0] LEGUP_F_main_BB20_42 = 9'd42;
parameter [8:0] LEGUP_F_main_BB20_43 = 9'd43;
parameter [8:0] LEGUP_F_main_BB20_44 = 9'd44;
parameter [8:0] LEGUP_F_main_BB20_45 = 9'd45;
parameter [8:0] LEGUP_F_main_BB20_46 = 9'd46;
parameter [8:0] LEGUP_F_main_BB20_47 = 9'd47;
parameter [8:0] LEGUP_F_main_BB20_48 = 9'd48;
parameter [8:0] LEGUP_F_main_BB20_49 = 9'd49;
parameter [8:0] LEGUP_F_main_BB20_50 = 9'd50;
parameter [8:0] LEGUP_F_main_BB20_51 = 9'd51;
parameter [8:0] LEGUP_F_main_BB20_52 = 9'd52;
parameter [8:0] LEGUP_F_main_BB20_53 = 9'd53;
parameter [8:0] LEGUP_F_main_BB20_54 = 9'd54;
parameter [8:0] LEGUP_F_main_BB20_55 = 9'd55;
parameter [8:0] LEGUP_F_main_BB20_56 = 9'd56;
parameter [8:0] LEGUP_F_main_BB20_57 = 9'd57;
parameter [8:0] LEGUP_F_main_BB21_58 = 9'd58;
parameter [8:0] LEGUP_F_main_BB21_59 = 9'd59;
parameter [8:0] LEGUP_F_main_BB21_60 = 9'd60;
parameter [8:0] LEGUP_F_main_BB22_61 = 9'd61;
parameter [8:0] LEGUP_F_main_BB23_62 = 9'd62;
parameter [8:0] LEGUP_F_main_BB23_63 = 9'd63;
parameter [8:0] LEGUP_F_main_BB23_64 = 9'd64;
parameter [8:0] LEGUP_F_main_BB24_65 = 9'd65;
parameter [8:0] LEGUP_F_main_BB24_66 = 9'd66;
parameter [8:0] LEGUP_F_main_BB24_67 = 9'd67;
parameter [8:0] LEGUP_F_main_BB25_68 = 9'd68;
parameter [8:0] LEGUP_F_main_BB25_69 = 9'd69;
parameter [8:0] LEGUP_F_main_BB25_70 = 9'd70;
parameter [8:0] LEGUP_F_main_BB26_71 = 9'd71;
parameter [8:0] LEGUP_F_main_BB26_72 = 9'd72;
parameter [8:0] LEGUP_F_main_BB26_73 = 9'd73;
parameter [8:0] LEGUP_F_main_BB27_74 = 9'd74;
parameter [8:0] LEGUP_F_main_BB27_75 = 9'd75;
parameter [8:0] LEGUP_F_main_BB27_76 = 9'd76;
parameter [8:0] LEGUP_F_main_BB28_77 = 9'd77;
parameter [8:0] LEGUP_F_main_BB29_78 = 9'd78;
parameter [8:0] LEGUP_F_main_BB29_79 = 9'd79;
parameter [8:0] LEGUP_F_main_BB29_80 = 9'd80;
parameter [8:0] LEGUP_F_main_BB30_81 = 9'd81;
parameter [8:0] LEGUP_F_main_BB31_82 = 9'd82;
parameter [8:0] LEGUP_F_main_BB31_83 = 9'd83;
parameter [8:0] LEGUP_F_main_BB31_84 = 9'd84;
parameter [8:0] LEGUP_F_main_BB31_85 = 9'd85;
parameter [8:0] LEGUP_F_main_BB31_86 = 9'd86;
parameter [8:0] LEGUP_F_main_BB31_87 = 9'd87;
parameter [8:0] LEGUP_F_main_BB31_88 = 9'd88;
parameter [8:0] LEGUP_F_main_BB31_89 = 9'd89;
parameter [8:0] LEGUP_F_main_BB31_90 = 9'd90;
parameter [8:0] LEGUP_F_main_BB31_91 = 9'd91;
parameter [8:0] LEGUP_F_main_BB31_92 = 9'd92;
parameter [8:0] LEGUP_F_main_BB31_93 = 9'd93;
parameter [8:0] LEGUP_F_main_BB31_94 = 9'd94;
parameter [8:0] LEGUP_F_main_BB31_95 = 9'd95;
parameter [8:0] LEGUP_F_main_BB31_96 = 9'd96;
parameter [8:0] LEGUP_F_main_BB31_97 = 9'd97;
parameter [8:0] LEGUP_F_main_BB31_98 = 9'd98;
parameter [8:0] LEGUP_F_main_BB31_99 = 9'd99;
parameter [8:0] LEGUP_F_main_BB31_100 = 9'd100;
parameter [8:0] LEGUP_F_main_BB31_101 = 9'd101;
parameter [8:0] LEGUP_F_main_BB31_102 = 9'd102;
parameter [8:0] LEGUP_F_main_BB31_103 = 9'd103;
parameter [8:0] LEGUP_F_main_BB31_104 = 9'd104;
parameter [8:0] LEGUP_F_main_BB31_105 = 9'd105;
parameter [8:0] LEGUP_F_main_BB31_106 = 9'd106;
parameter [8:0] LEGUP_F_main_BB31_107 = 9'd107;
parameter [8:0] LEGUP_F_main_BB31_108 = 9'd108;
parameter [8:0] LEGUP_F_main_BB32_109 = 9'd109;
parameter [8:0] LEGUP_F_main_BB32_110 = 9'd110;
parameter [8:0] LEGUP_F_main_BB32_111 = 9'd111;
parameter [8:0] LEGUP_F_main_BB33_112 = 9'd112;
parameter [8:0] LEGUP_F_main_BB33_113 = 9'd113;
parameter [8:0] LEGUP_F_main_BB33_114 = 9'd114;
parameter [8:0] LEGUP_F_main_BB33_115 = 9'd115;
parameter [8:0] LEGUP_F_main_BB34_116 = 9'd116;
parameter [8:0] LEGUP_F_main_BB34_117 = 9'd117;
parameter [8:0] LEGUP_F_main_BB34_118 = 9'd118;
parameter [8:0] LEGUP_F_main_BB35_119 = 9'd119;
parameter [8:0] LEGUP_F_main_BB35_120 = 9'd120;
parameter [8:0] LEGUP_F_main_BB35_121 = 9'd121;
parameter [8:0] LEGUP_F_main_BB35_122 = 9'd122;
parameter [8:0] LEGUP_F_main_BB36_123 = 9'd123;
parameter [8:0] LEGUP_F_main_BB36_124 = 9'd124;
parameter [8:0] LEGUP_F_main_BB36_125 = 9'd125;
parameter [8:0] LEGUP_F_main_BB37_126 = 9'd126;
parameter [8:0] LEGUP_F_main_BB37_127 = 9'd127;
parameter [8:0] LEGUP_F_main_BB37_128 = 9'd128;
parameter [8:0] LEGUP_F_main_BB38_129 = 9'd129;
parameter [8:0] LEGUP_F_main_BB38_130 = 9'd130;
parameter [8:0] LEGUP_F_main_BB38_131 = 9'd131;
parameter [8:0] LEGUP_F_main_BB39_132 = 9'd132;
parameter [8:0] LEGUP_F_main_BB39_133 = 9'd133;
parameter [8:0] LEGUP_F_main_BB39_134 = 9'd134;
parameter [8:0] LEGUP_F_main_BB39_135 = 9'd135;
parameter [8:0] LEGUP_F_main_BB40_136 = 9'd136;
parameter [8:0] LEGUP_F_main_BB40_137 = 9'd137;
parameter [8:0] LEGUP_F_main_BB40_138 = 9'd138;
parameter [8:0] LEGUP_F_main_BB41_139 = 9'd139;
parameter [8:0] LEGUP_F_main_BB42_140 = 9'd140;
parameter [8:0] LEGUP_F_main_BB42_141 = 9'd141;
parameter [8:0] LEGUP_F_main_BB42_142 = 9'd142;
parameter [8:0] LEGUP_F_main_BB43_143 = 9'd143;
parameter [8:0] LEGUP_F_main_BB44_144 = 9'd144;
parameter [8:0] LEGUP_F_main_BB45_145 = 9'd145;
parameter [8:0] LEGUP_F_main_BB45_146 = 9'd146;
parameter [8:0] LEGUP_F_main_BB45_147 = 9'd147;
parameter [8:0] LEGUP_F_main_BB45_148 = 9'd148;
parameter [8:0] LEGUP_F_main_BB45_149 = 9'd149;
parameter [8:0] LEGUP_F_main_BB46_150 = 9'd150;
parameter [8:0] LEGUP_F_main_BB46_151 = 9'd151;
parameter [8:0] LEGUP_F_main_BB46_152 = 9'd152;
parameter [8:0] LEGUP_F_main_BB47_153 = 9'd153;
parameter [8:0] LEGUP_F_main_BB48_154 = 9'd154;
parameter [8:0] LEGUP_F_main_BB48_155 = 9'd155;
parameter [8:0] LEGUP_F_main_BB48_156 = 9'd156;
parameter [8:0] LEGUP_F_main_BB49_157 = 9'd157;
parameter [8:0] LEGUP_F_main_BB50_158 = 9'd158;
parameter [8:0] LEGUP_F_main_BB51_159 = 9'd159;
parameter [8:0] LEGUP_F_main_BB51_160 = 9'd160;
parameter [8:0] LEGUP_F_main_BB51_161 = 9'd161;
parameter [8:0] LEGUP_F_main_BB51_162 = 9'd162;
parameter [8:0] LEGUP_F_main_BB52_163 = 9'd163;
parameter [8:0] LEGUP_F_main_BB53_164 = 9'd164;
parameter [8:0] LEGUP_F_main_BB53_165 = 9'd165;
parameter [8:0] LEGUP_F_main_BB53_166 = 9'd166;
parameter [8:0] LEGUP_F_main_BB54_167 = 9'd167;
parameter [8:0] LEGUP_F_main_BB55_168 = 9'd168;
parameter [8:0] LEGUP_F_main_BB56_169 = 9'd169;
parameter [8:0] LEGUP_F_main_BB56_170 = 9'd170;
parameter [8:0] LEGUP_F_main_BB56_171 = 9'd171;
parameter [8:0] LEGUP_F_main_BB56_172 = 9'd172;
parameter [8:0] LEGUP_F_main_BB56_173 = 9'd173;
parameter [8:0] LEGUP_F_main_BB56_174 = 9'd174;
parameter [8:0] LEGUP_F_main_BB56_175 = 9'd175;
parameter [8:0] LEGUP_F_main_BB56_176 = 9'd176;
parameter [8:0] LEGUP_F_main_BB56_177 = 9'd177;
parameter [8:0] LEGUP_F_main_BB56_178 = 9'd178;
parameter [8:0] LEGUP_F_main_BB56_179 = 9'd179;
parameter [8:0] LEGUP_F_main_BB56_180 = 9'd180;
parameter [8:0] LEGUP_F_main_BB56_181 = 9'd181;
parameter [8:0] LEGUP_F_main_BB56_182 = 9'd182;
parameter [8:0] LEGUP_F_main_BB57_183 = 9'd183;
parameter [8:0] LEGUP_F_main_BB57_184 = 9'd184;
parameter [8:0] LEGUP_F_main_BB57_185 = 9'd185;
parameter [8:0] LEGUP_F_main_BB58_186 = 9'd186;
parameter [8:0] LEGUP_F_main_BB58_187 = 9'd187;
parameter [8:0] LEGUP_F_main_BB58_188 = 9'd188;
parameter [8:0] LEGUP_F_main_BB58_189 = 9'd189;
parameter [8:0] LEGUP_F_main_BB59_190 = 9'd190;
parameter [8:0] LEGUP_F_main_BB59_191 = 9'd191;
parameter [8:0] LEGUP_F_main_BB59_192 = 9'd192;
parameter [8:0] LEGUP_F_main_BB60_193 = 9'd193;
parameter [8:0] LEGUP_F_main_BB60_194 = 9'd194;
parameter [8:0] LEGUP_F_main_BB60_195 = 9'd195;
parameter [8:0] LEGUP_F_main_BB61_196 = 9'd196;
parameter [8:0] LEGUP_F_main_BB61_197 = 9'd197;
parameter [8:0] LEGUP_F_main_BB61_198 = 9'd198;
parameter [8:0] LEGUP_F_main_BB62_199 = 9'd199;
parameter [8:0] LEGUP_F_main_BB63_200 = 9'd200;
parameter [8:0] LEGUP_F_main_BB64_201 = 9'd201;
parameter [8:0] LEGUP_F_main_BB64_202 = 9'd202;
parameter [8:0] LEGUP_F_main_BB64_203 = 9'd203;
parameter [8:0] LEGUP_F_main_BB64_204 = 9'd204;
parameter [8:0] LEGUP_F_main_BB64_205 = 9'd205;
parameter [8:0] LEGUP_F_main_BB64_206 = 9'd206;
parameter [8:0] LEGUP_F_main_BB64_207 = 9'd207;
parameter [8:0] LEGUP_F_main_BB65_208 = 9'd208;
parameter [8:0] LEGUP_F_main_BB65_209 = 9'd209;
parameter [8:0] LEGUP_F_main_BB65_210 = 9'd210;
parameter [8:0] LEGUP_F_main_BB66_211 = 9'd211;
parameter [8:0] LEGUP_F_main_BB67_212 = 9'd212;
parameter [8:0] LEGUP_F_main_BB67_213 = 9'd213;
parameter [8:0] LEGUP_F_main_BB67_214 = 9'd214;
parameter [8:0] LEGUP_F_main_BB67_215 = 9'd215;
parameter [8:0] LEGUP_F_main_BB67_216 = 9'd216;
parameter [8:0] LEGUP_F_main_BB67_217 = 9'd217;
parameter [8:0] LEGUP_F_main_BB68_218 = 9'd218;
parameter [8:0] LEGUP_F_main_BB68_219 = 9'd219;
parameter [8:0] LEGUP_F_main_BB68_220 = 9'd220;
parameter [8:0] LEGUP_F_main_BB69_221 = 9'd221;
parameter [8:0] LEGUP_F_main_BB70_222 = 9'd222;
parameter [8:0] LEGUP_F_main_BB71_223 = 9'd223;
parameter [8:0] LEGUP_F_main_BB72_224 = 9'd224;
parameter [8:0] LEGUP_F_main_BB73_225 = 9'd225;
parameter [8:0] LEGUP_F_main_BB73_226 = 9'd226;
parameter [8:0] LEGUP_F_main_BB73_227 = 9'd227;
parameter [8:0] LEGUP_F_main_BB74_228 = 9'd228;
parameter [8:0] LEGUP_F_main_BB74_229 = 9'd229;
parameter [8:0] LEGUP_F_main_BB74_230 = 9'd230;
parameter [8:0] LEGUP_F_main_BB74_231 = 9'd231;
parameter [8:0] LEGUP_F_main_BB75_232 = 9'd232;
parameter [8:0] LEGUP_F_main_BB75_233 = 9'd233;
parameter [8:0] LEGUP_F_main_BB75_234 = 9'd234;
parameter [8:0] LEGUP_F_main_BB76_235 = 9'd235;
parameter [8:0] LEGUP_F_main_BB77_236 = 9'd236;
parameter [8:0] LEGUP_F_main_BB77_237 = 9'd237;
parameter [8:0] LEGUP_F_main_BB77_238 = 9'd238;
parameter [8:0] LEGUP_F_main_BB78_239 = 9'd239;
parameter [8:0] LEGUP_F_main_BB79_240 = 9'd240;
parameter [8:0] LEGUP_F_main_BB79_241 = 9'd241;
parameter [8:0] LEGUP_F_main_BB79_242 = 9'd242;
parameter [8:0] LEGUP_F_main_BB79_243 = 9'd243;
parameter [8:0] LEGUP_F_main_BB79_244 = 9'd244;
parameter [8:0] LEGUP_F_main_BB79_245 = 9'd245;
parameter [8:0] LEGUP_F_main_BB79_246 = 9'd246;
parameter [8:0] LEGUP_F_main_BB80_247 = 9'd247;
parameter [8:0] LEGUP_F_main_BB80_248 = 9'd248;
parameter [8:0] LEGUP_F_main_BB80_249 = 9'd249;
parameter [8:0] LEGUP_F_main_BB81_250 = 9'd250;
parameter [8:0] LEGUP_F_main_BB82_251 = 9'd251;
parameter [8:0] LEGUP_F_main_BB82_252 = 9'd252;
parameter [8:0] LEGUP_F_main_BB82_253 = 9'd253;
parameter [8:0] LEGUP_F_main_BB82_254 = 9'd254;
parameter [8:0] LEGUP_F_main_BB82_255 = 9'd255;
parameter [8:0] LEGUP_F_main_BB82_256 = 9'd256;
parameter [8:0] LEGUP_F_main_BB83_257 = 9'd257;
parameter [8:0] LEGUP_F_main_BB83_258 = 9'd258;
parameter [8:0] LEGUP_F_main_BB83_259 = 9'd259;
parameter [8:0] LEGUP_F_main_BB84_260 = 9'd260;
parameter [8:0] LEGUP_F_main_BB84_261 = 9'd261;
parameter [8:0] LEGUP_F_main_BB84_262 = 9'd262;
parameter [8:0] LEGUP_F_main_BB85_263 = 9'd263;
parameter [8:0] LEGUP_F_main_BB85_264 = 9'd264;
parameter [8:0] LEGUP_F_main_BB85_265 = 9'd265;
parameter [8:0] LEGUP_F_main_BB86_266 = 9'd266;
parameter [8:0] LEGUP_F_main_BB87_267 = 9'd267;
parameter [8:0] LEGUP_F_main_BB87_268 = 9'd268;
parameter [8:0] LEGUP_F_main_BB87_269 = 9'd269;
parameter [8:0] LEGUP_F_main_BB87_270 = 9'd270;
parameter [8:0] LEGUP_F_main_BB88_271 = 9'd271;
parameter [8:0] LEGUP_F_main_BB88_272 = 9'd272;
parameter [8:0] LEGUP_F_main_BB88_273 = 9'd273;
parameter [8:0] LEGUP_F_main_BB88_274 = 9'd274;
parameter [8:0] LEGUP_F_main_BB88_275 = 9'd275;
parameter [8:0] LEGUP_F_main_BB89_276 = 9'd276;
parameter [8:0] LEGUP_F_main_BB90_277 = 9'd277;
parameter [8:0] LEGUP_F_main_BB90_278 = 9'd278;
parameter [8:0] LEGUP_F_main_BB90_279 = 9'd279;
parameter [8:0] LEGUP_F_main_BB90_280 = 9'd280;
parameter [8:0] LEGUP_F_main_BB90_281 = 9'd281;
parameter [8:0] LEGUP_F_main_BB90_282 = 9'd282;
parameter [8:0] LEGUP_F_main_BB90_283 = 9'd283;
parameter [8:0] LEGUP_F_main_BB90_284 = 9'd284;
parameter [8:0] LEGUP_F_main_BB90_285 = 9'd285;
parameter [8:0] LEGUP_F_main_BB90_286 = 9'd286;
parameter [8:0] LEGUP_F_main_BB90_287 = 9'd287;
parameter [8:0] LEGUP_F_main_BB90_288 = 9'd288;
parameter [8:0] LEGUP_F_main_BB90_289 = 9'd289;
parameter [8:0] LEGUP_F_main_BB90_290 = 9'd290;
parameter [8:0] LEGUP_F_main_BB90_291 = 9'd291;
parameter [8:0] LEGUP_F_main_BB90_292 = 9'd292;
parameter [8:0] LEGUP_F_main_BB90_293 = 9'd293;
parameter [8:0] LEGUP_F_main_BB90_294 = 9'd294;
parameter [8:0] LEGUP_F_main_BB90_295 = 9'd295;
parameter [8:0] LEGUP_F_main_BB90_296 = 9'd296;
parameter [8:0] LEGUP_F_main_BB90_297 = 9'd297;
parameter [8:0] LEGUP_F_main_BB90_298 = 9'd298;
parameter [8:0] LEGUP_F_main_BB90_299 = 9'd299;
parameter [8:0] LEGUP_F_main_BB90_300 = 9'd300;
parameter [8:0] LEGUP_F_main_BB90_301 = 9'd301;
parameter [8:0] LEGUP_F_main_BB90_302 = 9'd302;
parameter [8:0] LEGUP_F_main_BB90_303 = 9'd303;
parameter [8:0] LEGUP_F_main_BB90_304 = 9'd304;
parameter [8:0] LEGUP_F_main_BB90_305 = 9'd305;
parameter [8:0] LEGUP_F_main_BB90_306 = 9'd306;
parameter [8:0] LEGUP_F_main_BB90_307 = 9'd307;
parameter [8:0] LEGUP_F_main_BB90_308 = 9'd308;
parameter [8:0] LEGUP_F_main_BB90_309 = 9'd309;
parameter [8:0] LEGUP_F_main_BB90_310 = 9'd310;
parameter [8:0] LEGUP_F_main_BB90_311 = 9'd311;
parameter [8:0] LEGUP_F_main_BB90_312 = 9'd312;
parameter [8:0] LEGUP_F_main_BB90_313 = 9'd313;
parameter [8:0] LEGUP_F_main_BB90_314 = 9'd314;
parameter [8:0] LEGUP_F_main_BB90_315 = 9'd315;
parameter [8:0] LEGUP_F_main_BB90_316 = 9'd316;
parameter [8:0] LEGUP_F_main_BB90_317 = 9'd317;
parameter [8:0] LEGUP_F_main_BB90_318 = 9'd318;
parameter [8:0] LEGUP_F_main_BB90_319 = 9'd319;
parameter [8:0] LEGUP_F_main_BB90_320 = 9'd320;
parameter [8:0] LEGUP_F_main_BB90_321 = 9'd321;
parameter [8:0] LEGUP_F_main_BB90_322 = 9'd322;
parameter [8:0] LEGUP_F_main_BB90_323 = 9'd323;
parameter [8:0] LEGUP_F_main_BB90_324 = 9'd324;
parameter [8:0] LEGUP_F_main_BB90_325 = 9'd325;
parameter [8:0] LEGUP_F_main_BB90_326 = 9'd326;
parameter [8:0] LEGUP_F_main_BB90_327 = 9'd327;
parameter [8:0] LEGUP_F_main_BB90_328 = 9'd328;
parameter [8:0] LEGUP_F_main_BB90_329 = 9'd329;
parameter [8:0] LEGUP_F_main_BB90_332 = 9'd332;
parameter [8:0] LEGUP_F_main_BB90_333 = 9'd333;
parameter [8:0] LEGUP_F_main_BB90_336 = 9'd336;
parameter [8:0] LEGUP_F_main_BB90_337 = 9'd337;
parameter [8:0] LEGUP_F_main_BB90_340 = 9'd340;
parameter [8:0] LEGUP_F_main_BB90_341 = 9'd341;
parameter [8:0] LEGUP_F_main_BB90_344 = 9'd344;
parameter [8:0] LEGUP_F_main_BB90_345 = 9'd345;
parameter [8:0] LEGUP_F_main_BB90_346 = 9'd346;
parameter [8:0] LEGUP_F_main_BB90_347 = 9'd347;
parameter [8:0] LEGUP_F_main_BB90_348 = 9'd348;
parameter [8:0] LEGUP_F_main_BB90_349 = 9'd349;
parameter [8:0] LEGUP_F_main_BB90_350 = 9'd350;
parameter [8:0] LEGUP_F_main_BB90_351 = 9'd351;
parameter [8:0] LEGUP_F_main_BB90_352 = 9'd352;
parameter [8:0] LEGUP_F_main_BB90_353 = 9'd353;
parameter [8:0] LEGUP_F_main_BB90_354 = 9'd354;
parameter [8:0] LEGUP_F_main_BB91_355 = 9'd355;
parameter [8:0] LEGUP_F_main_BB92_356 = 9'd356;
parameter [8:0] LEGUP_F_main_BB93_357 = 9'd357;
parameter [8:0] LEGUP_F_main_BB93_360 = 9'd360;
parameter [8:0] LEGUP_F_main_BB93_363 = 9'd363;
parameter [8:0] LEGUP_F_main_BB94_366 = 9'd366;
parameter [8:0] LEGUP_F_main_BB94_367 = 9'd367;
parameter [8:0] LEGUP_F_main_BB94_368 = 9'd368;
parameter [8:0] LEGUP_F_main_BB94_369 = 9'd369;
parameter [8:0] LEGUP_F_main_BB94_370 = 9'd370;
parameter [8:0] LEGUP_F_main_BB94_371 = 9'd371;
parameter [8:0] LEGUP_F_main_BB95_372 = 9'd372;
parameter [8:0] LEGUP_F_main_BB96_373 = 9'd373;
parameter [8:0] LEGUP_F_main_BB97_374 = 9'd374;
parameter [8:0] LEGUP_F_main_BB98_375 = 9'd375;
parameter [8:0] LEGUP_F_main_BB99_376 = 9'd376;
parameter [8:0] LEGUP_F_main_BB100_377 = 9'd377;
parameter [8:0] LEGUP_F_main_BB101_378 = 9'd378;
parameter [8:0] LEGUP_F_main_BB102_379 = 9'd379;
parameter [8:0] LEGUP_F_main_BB103_380 = 9'd380;
parameter [8:0] LEGUP_F_main_BB103_381 = 9'd381;
parameter [8:0] LEGUP_F_main_BB103_382 = 9'd382;
parameter [8:0] LEGUP_F_main_BB104_383 = 9'd383;
parameter [8:0] LEGUP_F_main_BB104_384 = 9'd384;
parameter [8:0] LEGUP_F_main_BB104_385 = 9'd385;
parameter [8:0] LEGUP_F_main_BB104_386 = 9'd386;
parameter [8:0] LEGUP_F_main_BB104_387 = 9'd387;
parameter [8:0] LEGUP_F_main_BB104_388 = 9'd388;
parameter [8:0] LEGUP_F_main_BB105_389 = 9'd389;
parameter [8:0] LEGUP_F_main_BB105_390 = 9'd390;
parameter [8:0] LEGUP_F_main_BB105_391 = 9'd391;
parameter [8:0] LEGUP_F_main_BB106_392 = 9'd392;
parameter [8:0] LEGUP_F_main_BB106_393 = 9'd393;
parameter [8:0] LEGUP_F_main_BB106_394 = 9'd394;
parameter [8:0] LEGUP_F_main_BB107_395 = 9'd395;
parameter [8:0] LEGUP_F_main_BB108_396 = 9'd396;
parameter [8:0] LEGUP_F_main_BB108_397 = 9'd397;
parameter [8:0] LEGUP_F_main_BB108_398 = 9'd398;
parameter [8:0] LEGUP_F_main_BB109_399 = 9'd399;
parameter [8:0] LEGUP_F_main_BB110_400 = 9'd400;
parameter [8:0] LEGUP_F_main_BB110_401 = 9'd401;
parameter [8:0] LEGUP_F_main_BB110_402 = 9'd402;
parameter [8:0] LEGUP_F_main_BB111_403 = 9'd403;
parameter [8:0] LEGUP_F_main_BB112_404 = 9'd404;
parameter [8:0] LEGUP_F_main_BB113_405 = 9'd405;
parameter [8:0] LEGUP_F_main_BB114_406 = 9'd406;
parameter [8:0] LEGUP_F_main_BB115_407 = 9'd407;
parameter [8:0] LEGUP_F_main_BB116_408 = 9'd408;
parameter [8:0] LEGUP_F_main_BB116_411 = 9'd411;
parameter [8:0] LEGUP_F_main_BB116_414 = 9'd414;
parameter [8:0] LEGUP_F_main_BB116_417 = 9'd417;
parameter [8:0] LEGUP_F_main_BB116_420 = 9'd420;
parameter [8:0] LEGUP_F_main_BB116_423 = 9'd423;
parameter [8:0] LEGUP_F_main_BB117_426 = 9'd426;
parameter [8:0] LEGUP_F_main_BB118_427 = 9'd427;
parameter [8:0] LEGUP_F_main_BB118_428 = 9'd428;
parameter [8:0] LEGUP_F_main_BB118_429 = 9'd429;
parameter [8:0] LEGUP_F_main_BB118_430 = 9'd430;
parameter [8:0] LEGUP_F_main_BB118_431 = 9'd431;
parameter [8:0] LEGUP_F_main_BB118_432 = 9'd432;
parameter [8:0] LEGUP_F_main_BB119_433 = 9'd433;
parameter [8:0] LEGUP_F_main_BB120_434 = 9'd434;
parameter [8:0] LEGUP_F_main_BB121_435 = 9'd435;
parameter [8:0] LEGUP_F_main_BB122_436 = 9'd436;
parameter [8:0] LEGUP_F_main_BB123_437 = 9'd437;
parameter [8:0] LEGUP_F_main_BB124_438 = 9'd438;
parameter [8:0] LEGUP_F_main_BB125_439 = 9'd439;
parameter [8:0] LEGUP_F_main_BB126_440 = 9'd440;
parameter [8:0] LEGUP_F_main_BB127_441 = 9'd441;
parameter [8:0] LEGUP_F_main_BB127_442 = 9'd442;
parameter [8:0] LEGUP_F_main_BB127_443 = 9'd443;
parameter [8:0] LEGUP_F_main_BB128_444 = 9'd444;
parameter [8:0] LEGUP_F_main_BB129_445 = 9'd445;
parameter [8:0] LEGUP_F_main_BB129_448 = 9'd448;
parameter [8:0] LEGUP_F_main_BB129_451 = 9'd451;
parameter [8:0] LEGUP_F_main_BB130_454 = 9'd454;
parameter [8:0] LEGUP_F_main_BB130_455 = 9'd455;
parameter [8:0] LEGUP_F_main_BB130_456 = 9'd456;
parameter [8:0] LEGUP_F_main_BB131_457 = 9'd457;
parameter [8:0] LEGUP_F_main_BB131_458 = 9'd458;
parameter [8:0] LEGUP_F_main_BB131_459 = 9'd459;
parameter [8:0] LEGUP_F_main_BB131_460 = 9'd460;
parameter [8:0] LEGUP_F_main_BB132_461 = 9'd461;
parameter [8:0] LEGUP_F_main_BB132_462 = 9'd462;
parameter [8:0] LEGUP_F_main_BB132_463 = 9'd463;
parameter [8:0] LEGUP_F_main_BB132_464 = 9'd464;
parameter [8:0] LEGUP_F_main_BB133_465 = 9'd465;
parameter [8:0] LEGUP_F_main_BB133_466 = 9'd466;
parameter [8:0] LEGUP_F_main_BB133_467 = 9'd467;
parameter [8:0] LEGUP_F_main_BB133_468 = 9'd468;
parameter [8:0] LEGUP_F_main_BB134_469 = 9'd469;
parameter [8:0] LEGUP_F_main_BB134_470 = 9'd470;
parameter [8:0] LEGUP_F_main_BB134_471 = 9'd471;
parameter [8:0] LEGUP_F_main_BB134_472 = 9'd472;
parameter [8:0] LEGUP_F_main_BB135_473 = 9'd473;
parameter [8:0] LEGUP_F_main_BB136_474 = 9'd474;
parameter [8:0] LEGUP_F_main_BB137_475 = 9'd475;
parameter [8:0] LEGUP_F_main_BB137_476 = 9'd476;
parameter [8:0] LEGUP_F_main_BB137_477 = 9'd477;
parameter [8:0] LEGUP_function_call_330 = 9'd330;
parameter [8:0] LEGUP_function_call_331 = 9'd331;
parameter [8:0] LEGUP_function_call_334 = 9'd334;
parameter [8:0] LEGUP_function_call_335 = 9'd335;
parameter [8:0] LEGUP_function_call_338 = 9'd338;
parameter [8:0] LEGUP_function_call_339 = 9'd339;
parameter [8:0] LEGUP_function_call_342 = 9'd342;
parameter [8:0] LEGUP_function_call_343 = 9'd343;
parameter [8:0] LEGUP_function_call_358 = 9'd358;
parameter [8:0] LEGUP_function_call_359 = 9'd359;
parameter [8:0] LEGUP_function_call_361 = 9'd361;
parameter [8:0] LEGUP_function_call_362 = 9'd362;
parameter [8:0] LEGUP_function_call_364 = 9'd364;
parameter [8:0] LEGUP_function_call_365 = 9'd365;
parameter [8:0] LEGUP_function_call_409 = 9'd409;
parameter [8:0] LEGUP_function_call_410 = 9'd410;
parameter [8:0] LEGUP_function_call_412 = 9'd412;
parameter [8:0] LEGUP_function_call_413 = 9'd413;
parameter [8:0] LEGUP_function_call_415 = 9'd415;
parameter [8:0] LEGUP_function_call_416 = 9'd416;
parameter [8:0] LEGUP_function_call_418 = 9'd418;
parameter [8:0] LEGUP_function_call_419 = 9'd419;
parameter [8:0] LEGUP_function_call_421 = 9'd421;
parameter [8:0] LEGUP_function_call_422 = 9'd422;
parameter [8:0] LEGUP_function_call_424 = 9'd424;
parameter [8:0] LEGUP_function_call_425 = 9'd425;
parameter [8:0] LEGUP_function_call_446 = 9'd446;
parameter [8:0] LEGUP_function_call_447 = 9'd447;
parameter [8:0] LEGUP_function_call_449 = 9'd449;
parameter [8:0] LEGUP_function_call_450 = 9'd450;
parameter [8:0] LEGUP_function_call_452 = 9'd452;
parameter [8:0] LEGUP_function_call_453 = 9'd453;
input clk;
input reset;
input start;
output reg finish;
output reg [31:0] return_val;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_enable;
output reg memory_controller_write_enable;
input memory_controller_waitrequest;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [1:0] memory_controller_size;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [8:0] cur_state;
reg [31:0] main_1_i_05_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_c_06_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_c_06_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_1_scevgep13_i;
reg [7:0] main_1_2;
reg [31:0] main_1_3;
reg [31:0] main_1_3_reg;
reg main_1_exitcond11_i;
reg main_1_exitcond11_i_reg;
reg [31:0] main__outer_i_i_i_marker_0;
reg [31:0] main__outer_i_i_i_get_dht_0;
reg [31:0] main__outer_i_i_i_get_dqt_0;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__outer_i_i_ReadBuf_0;
reg [7:0] main__outer_i_i_p_jinfo_num_components_0;
reg main__outer_i_i_p_jinfo_smp_fact_b_0;
reg main__outer_i_i_sow_SOI_0_ph_i_i;
reg main__outer_i_i_sow_SOI_0_ph_i_i_reg;
reg [31:0] main__backedge_i_i_outer_i_marker_1_ph;
reg [31:0] main__backedge_i_i_outer_i_get_dht_1_ph;
reg [31:0] main__backedge_i_i_outer_i_get_dht_1_ph_reg;
reg [31:0] main__backedge_i_i_outer_i_get_dqt_1_ph;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer_ReadBuf_1_ph;
reg [7:0] main__backedge_i_i_outer_p_jinfo_num_components_1_ph;
reg main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer_4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer_4_reg;
reg [31:0] main__backedge_i_i_outer4_i_marker_1_ph5;
reg [31:0] main__backedge_i_i_outer4_i_get_dqt_1_ph6;
reg [31:0] main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer4_ReadBuf_1_ph7;
reg [7:0] main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8;
reg main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer4_5;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer4_5_reg;
reg [31:0] main__backedge_i_i_outer10_i_marker_1_ph11;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer10_ReadBuf_1_ph12;
reg [7:0] main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
reg [7:0] main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg;
reg main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
reg main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg;
reg [31:0] main__backedge_i_i_i_marker_1;
reg [31:0] main__backedge_i_i_i_marker_1_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_ReadBuf_1;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_ReadBuf_1_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_6_7;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_6_7_reg;
reg [7:0] main_6_8;
reg [7:0] main_6_9;
reg [7:0] main_6_9_reg;
reg main_6_10;
reg main_6_10_reg;
reg main_6_11;
reg main_6_or_cond_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_first_marker_exit_i_i_14;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_first_marker_exit_i_i_14_reg;
reg [31:0] main_first_marker_exit_i_i_15;
reg [31:0] main_first_marker_exit_i_i_15_reg;
reg [31:0] main_first_marker_exit_i_i_16;
reg [31:0] main_first_marker_exit_i_i_17;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_loopexit_scevgep13_i_i_le;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_18;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_18_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_storemerge1_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_storemerge1_i_i_i_reg;
reg [7:0] main__loopexit3_i_i_i_c_0_in2_i_i_i;
reg main__loopexit3_i_i_i_19;
reg [31:0] main__lr_ph_i_i_i_indvar_i_i;
reg [31:0] main__lr_ph_i_i_i_indvar_i_i_reg;
reg [31:0] main__lr_ph_i_i_i_tmp_i_i;
reg [31:0] main__lr_ph_i_i_i_tmp_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i_i_i_scevgep_i_i;
reg [7:0] main__lr_ph_i_i_i_c_0_in_i_i_i;
reg main__lr_ph_i_i_i_20;
reg [31:0] main__loopexit_i_preheader_i_i_loopexit_tmp4_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit_i_preheader_i_i_loopexit_storemerge_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit_i_preheader_i_i__ph_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit_i_preheader_i_i__ph_i_i_reg;
reg [31:0] main__loopexit_i_i_i_indvar9_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit_i_i_i_scevgep11_i_i;
reg [31:0] main__loopexit_i_i_i_tmp12_i_i;
reg [31:0] main__loopexit_i_i_i_tmp12_i_i_reg;
reg [7:0] main__loopexit_i_i_i_21;
reg [31:0] main__loopexit_i_i_i_22;
reg [31:0] main__loopexit_i_i_i_22_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_loopexit_scevgep13_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_ReadBuf_2;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_ReadBuf_2_reg;
reg [31:0] main_next_marker_exit_i_i_unread_marker_0_i_i;
reg [31:0] main_next_marker_exit_i_i_unread_marker_0_i_i_reg;
reg [31:0] main_next_marker_exit_i_i_24;
reg [31:0] main_next_marker_exit_i_i_24_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_25;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_25_reg;
reg [31:0] main_next_marker_exit_i_i_26;
reg main_next_marker_exit_i_i_27;
reg [31:0] main_28_29;
reg [31:0] main_28_30;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_33;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_33_reg;
reg [7:0] main_32_34;
reg [15:0] main_32_35;
reg [15:0] main_32_36;
reg [15:0] main_32_36_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_37;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_37_reg;
reg [7:0] main_32_38;
reg [15:0] main_32_39;
reg [15:0] main_32_40;
reg [31:0] main_32_41;
reg [31:0] main_32_41_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_42;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_42_reg;
reg [7:0] main_32_43;
reg [7:0] main_32_43_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_44;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_44_reg;
reg [7:0] main_32_45;
reg [15:0] main_32_46;
reg [15:0] main_32_47;
reg [15:0] main_32_47_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_48;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_48_reg;
reg [7:0] main_32_49;
reg [15:0] main_32_50;
reg [15:0] main_32_51;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_52;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_52_reg;
reg [7:0] main_32_53;
reg [15:0] main_32_54;
reg [15:0] main_32_55;
reg [15:0] main_32_55_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_56;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_56_reg;
reg [7:0] main_32_57;
reg [15:0] main_32_58;
reg [15:0] main_32_59;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_60;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_32_60_reg;
reg [7:0] main_32_61;
reg [7:0] main_32_61_reg;
reg [31:0] main_32_63;
reg [31:0] main_32_63_reg;
reg [15:0] main_32_65;
reg [31:0] main_32_66;
reg [15:0] main_32_68;
reg [31:0] main_32_69;
reg [31:0] main_32_71;
reg [31:0] main_32_71_reg;
reg main_32_73;
reg main_32_73_reg;
reg [31:0] main_74_75;
reg [31:0] main_74_76;
reg main_77_78;
reg [31:0] main_79_80;
reg [31:0] main_79_81;
reg [15:0] main_82_83;
reg main_82_84;
reg [31:0] main_85_86;
reg [31:0] main_85_87;
reg [15:0] main_88_89;
reg main_88_90;
reg [31:0] main_91_92;
reg [31:0] main_91_93;
reg main_94_95;
reg [31:0] main__preheader_i_i_i_thread_96;
reg [31:0] main__preheader_i_i_i_thread_97;
reg main__preheader_i_i_i_98;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_ReadBuf_3;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_ReadBuf_3_reg;
reg [31:0] main__lr_ph_i1_i_i_ci_02_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep3_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep3_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep4_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep4_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep5_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep5_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep6_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep6_i_i_i_reg;
reg [7:0] main__lr_ph_i1_i_i_tmp_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep7_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep7_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep8_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep8_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep9_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep9_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep11_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_scevgep11_i_i_i_reg;
reg [31:0] main__lr_ph_i1_i_i_tmp12_i_i_i;
reg [31:0] main__lr_ph_i1_i_i_tmp12_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_99;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_99_reg;
reg [7:0] main__lr_ph_i1_i_i_100;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_101;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_101_reg;
reg [7:0] main__lr_ph_i1_i_i_102;
reg [7:0] main__lr_ph_i1_i_i_103;
reg [7:0] main__lr_ph_i1_i_i_104;
reg [7:0] main__lr_ph_i1_i_i_104_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_105;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_105_reg;
reg [7:0] main__lr_ph_i1_i_i_106;
reg [31:0] main__lr_ph_i1_i_i_107;
reg [31:0] main__lr_ph_i1_i_i_107_reg;
reg [7:0] main__lr_ph_i1_i_i_109;
reg [31:0] main__lr_ph_i1_i_i_110;
reg [7:0] main__lr_ph_i1_i_i_112;
reg [31:0] main__lr_ph_i1_i_i_113;
reg [7:0] main__lr_ph_i1_i_i_115;
reg [31:0] main__lr_ph_i1_i_i_116;
reg [7:0] main__lr_ph_i1_i_i_118;
reg [31:0] main__lr_ph_i1_i_i_119;
reg [7:0] main__lr_ph_i1_i_i_121;
reg [31:0] main__lr_ph_i1_i_i_122;
reg [31:0] main__lr_ph_i1_i_i_122_reg;
reg [31:0] main__lr_ph_i1_i_i_123;
reg main__lr_ph_i1_i_i_124;
reg [31:0] main_125_126;
reg [31:0] main_125_127;
reg [7:0] main_128_129;
reg [31:0] main_128_130;
reg [31:0] main_128_130_reg;
reg [31:0] main_128_131;
reg main_128_132;
reg [31:0] main_133_134;
reg [31:0] main_133_135;
reg [7:0] main_136_137;
reg [31:0] main_136_138;
reg [31:0] main_136_138_reg;
reg [31:0] main_136_139;
reg [31:0] main_136_139_reg;
reg main_136_140;
reg [31:0] main_141_142;
reg [31:0] main_141_143;
reg [7:0] main_144_145;
reg [31:0] main_144_146;
reg main_144_147;
reg [31:0] main_148_149;
reg [31:0] main_148_150;
reg [7:0] main_151_152;
reg [31:0] main_151_153;
reg [31:0] main_151_153_reg;
reg [31:0] main_151_154;
reg main_151_155;
reg [31:0] main_156_157;
reg [31:0] main_156_158;
reg main_159_160;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___crit_edge_i_i_i_ReadBuf_4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___crit_edge_i_i_i_ReadBuf_4_reg;
reg [7:0] main___crit_edge_i_i_i_161;
reg main___crit_edge_i_i_i_162;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_168;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_168_reg;
reg [7:0] main_167_169;
reg [15:0] main_167_170;
reg [15:0] main_167_171;
reg [15:0] main_167_171_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_172;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_172_reg;
reg [7:0] main_167_173;
reg [15:0] main_167_174;
reg [15:0] main_167_175;
reg [31:0] main_167_176;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_177;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_167_177_reg;
reg [7:0] main_167_178;
reg [7:0] main_167_178_reg;
reg [31:0] main_167_179;
reg [31:0] main_167_179_reg;
reg main_167_182;
reg main_167_182_reg;
reg [31:0] main_183_184;
reg [31:0] main_183_185;
reg main_186_187;
reg [31:0] main_188_189;
reg [31:0] main_188_190;
reg [31:0] main__preheader5_i_i_i_preheader_191;
reg [31:0] main__preheader5_i_i_i_preheader_191_reg;
reg [31:0] main__preheader5_i_i_i_i_get_sos_0;
reg [31:0] main__preheader5_i_i_i_i_get_sos_0_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader5_i_i_i_ReadBuf_5;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader5_i_i_i_ReadBuf_5_reg;
reg [31:0] main__preheader5_i_i_i_192;
reg [31:0] main__preheader5_i_i_i_192_reg;
reg main__preheader5_i_i_i_193;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_194_195;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_194_195_reg;
reg [7:0] main_194_196;
reg [31:0] main_194_197;
reg [31:0] main_194_197_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_194_198;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_194_198_reg;
reg [7:0] main_194_199;
reg [7:0] main_194_199_reg;
reg [31:0] main_200_201;
reg [31:0] main_200_201_reg;
reg main_200_202;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_203_scevgep9_i4_i_i;
reg [7:0] main_203_204;
reg [31:0] main_203_205;
reg main_203_206;
reg [31:0] main_207_208;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_scevgep8_i5_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_scevgep8_i5_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_scevgep7_i6_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_scevgep7_i6_i_i_reg;
reg [31:0] main_211_212;
reg [31:0] main_211_213;
reg [7:0] main_211_214;
reg [7:0] main_211_214_reg;
reg [7:0] main_211_215;
reg [7:0] main_211_215_reg;
reg [7:0] main_211_217;
reg [31:0] main_211_218;
reg [7:0] main_211_220;
reg [31:0] main_211_221;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_223;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_211_223_reg;
reg [31:0] main_211_224;
reg main_211_225;
reg [31:0] main_226_227;
reg [31:0] main_226_228;
reg [7:0] main_229_230;
reg [31:0] main_229_231;
reg [31:0] main_229_231_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_229_232;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_229_232_reg;
reg [31:0] main_229_233;
reg [31:0] main_229_233_reg;
reg main_229_234;
reg [31:0] main_235_236;
reg [31:0] main_235_237;
reg [7:0] main_238_239;
reg [31:0] main_238_240;
reg main_238_241;
reg [31:0] main_242_243;
reg [31:0] main_242_244;
reg [31:0] main_245_246;
reg [31:0] main_245_247;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_get_sos_exit_i_i_scevgep_i2_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_248_249;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_248_249_reg;
reg [7:0] main_248_250;
reg [15:0] main_248_251;
reg [15:0] main_248_252;
reg [15:0] main_248_252_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_248_253;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_248_253_reg;
reg [7:0] main_248_254;
reg [15:0] main_248_255;
reg [15:0] main_248_256;
reg [31:0] main_248_257;
reg [31:0] main_248_258;
reg [31:0] main_248_258_reg;
reg [31:0] main_248_260;
reg main_248_261;
reg [31:0] main_262_263;
reg [31:0] main_262_264;
reg main__preheader_i7_i_i_265;
reg [31:0] main__lr_ph5_i_i_i_i_get_dht_2;
reg [31:0] main__lr_ph5_i_i_i_i_get_dht_2_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_ReadBuf_6;
reg [31:0] main__lr_ph5_i_i_i_length_04_i_i_i;
reg [31:0] main__lr_ph5_i_i_i_length_04_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_266;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_266_reg;
reg [7:0] main__lr_ph5_i_i_i_267;
reg [31:0] main__lr_ph5_i_i_i_268;
reg [31:0] main__lr_ph5_i_i_i_268_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_270;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_270_reg;
reg [31:0] main__lr_ph5_i_i_i_271;
reg main__lr_ph5_i_i_i_272;
reg [31:0] main_273_274;
reg [31:0] main_273_275;
reg [31:0] main_276_277;
reg main_276_278;
reg [31:0] main_279_280;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_279_281;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_279_282;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_283_284;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_283_285;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_huffval_0_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_huffval_0_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_bits_0_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_bits_0_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_288;
reg [31:0] main_287_indvar_i_i_i;
reg [31:0] main_287_count_01_i_i_i;
reg [31:0] main_287_count_01_i_i_i_reg;
reg [31:0] main_287_tmp_i8_i_i;
reg [31:0] main_287_tmp_i8_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_scevgep_i9_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_scevgep_i9_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_289;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_289_reg;
reg [7:0] main_287_290;
reg [31:0] main_287_291;
reg [31:0] main_287_292;
reg [31:0] main_287_292_reg;
reg main_287_exitcond_i_i_i;
reg main_287_exitcond_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_293_295;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_293_295_reg;
reg [31:0] main_293_296;
reg main_293_297;
reg [31:0] main_298_299;
reg [31:0] main_298_300;
reg [31:0] main_301_302;
reg [31:0] main_301_302_reg;
reg main_301_303;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_304;
reg [31:0] main__lr_ph_i10_i_i_i_13_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_scevgep8_i11_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_scevgep8_i11_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_305;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_305_reg;
reg [7:0] main__lr_ph_i10_i_i_306;
reg [31:0] main__lr_ph_i10_i_i_307;
reg [31:0] main__lr_ph_i10_i_i_308;
reg [31:0] main__lr_ph_i10_i_i_308_reg;
reg main__lr_ph_i10_i_i_exitcond7_i_i_i;
reg main__lr_ph_i10_i_i_exitcond7_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___crit_edge_i12_i_i_ReadBuf_7;
reg [31:0] main___crit_edge_i12_i_i_309;
reg [31:0] main___crit_edge_i12_i_i_310;
reg main___crit_edge_i12_i_i_311;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_312_313;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_312_313_reg;
reg [7:0] main_312_314;
reg [15:0] main_312_315;
reg [15:0] main_312_316;
reg [15:0] main_312_316_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_312_317;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_312_317_reg;
reg [7:0] main_312_318;
reg [15:0] main_312_319;
reg [15:0] main_312_320;
reg [31:0] main_312_321;
reg [31:0] main_312_322;
reg [31:0] main_312_322_reg;
reg [31:0] main_312_324;
reg main_312_325;
reg [31:0] main_326_327;
reg [31:0] main_326_328;
reg main__preheader_i13_i_i_329;
reg [31:0] main__lr_ph_i15_i_i_i_get_dqt_2;
reg [31:0] main__lr_ph_i15_i_i_i_get_dqt_2_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_330;
reg [31:0] main__lr_ph_i15_i_i_length_02_i_i_i;
reg [31:0] main__lr_ph_i15_i_i_length_02_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_331;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_331_reg;
reg [7:0] main__lr_ph_i15_i_i_332;
reg [31:0] main__lr_ph_i15_i_i_333;
reg [31:0] main__lr_ph_i15_i_i_334;
reg [31:0] main__lr_ph_i15_i_i_334_reg;
reg [31:0] main__lr_ph_i15_i_i_335;
reg [31:0] main__lr_ph_i15_i_i_335_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_338;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_338_reg;
reg [31:0] main__lr_ph_i15_i_i_339;
reg main__lr_ph_i15_i_i_340;
reg [31:0] main_341_342;
reg [31:0] main_341_343;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_344_345;
reg [31:0] main_344_346;
reg main_344_347;
reg [31:0] main_348_349;
reg [31:0] main_348_350;
reg [31:0] main_351_352;
reg [31:0] main_351_352_reg;
reg main_351_353;
reg main_351_353_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_354;
reg [31:0] main__split_us_i_i_i_i_01_us_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_scevgep_i16_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_scevgep_i16_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_355;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_355_reg;
reg [7:0] main__split_us_i_i_i_356;
reg [31:0] main__split_us_i_i_i_357;
reg [31:0] main__split_us_i_i_i_357_reg;
reg [31:0] main__split_us_i_i_i_358;
reg [31:0] main__split_us_i_i_i__sum_us_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_359;
reg [31:0] main__split_us_i_i_i_360;
reg [31:0] main__split_us_i_i_i_360_reg;
reg main__split_us_i_i_i_exitcond_i17_i_i;
reg main__split_us_i_i_i_exitcond_i17_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_361;
reg [31:0] main___split_crit_edge_i_i_i_i_01_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_scevgep4_i18_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_scevgep4_i18_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_362;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_362_reg;
reg [7:0] main___split_crit_edge_i_i_i_363;
reg [31:0] main___split_crit_edge_i_i_i_364;
reg [31:0] main___split_crit_edge_i_i_i_365;
reg [31:0] main___split_crit_edge_i_i_i_365_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_366;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_366_reg;
reg [7:0] main___split_crit_edge_i_i_i_367;
reg [31:0] main___split_crit_edge_i_i_i_368;
reg [31:0] main___split_crit_edge_i_i_i_369;
reg [31:0] main___split_crit_edge_i_i_i_369_reg;
reg [31:0] main___split_crit_edge_i_i_i_370;
reg [31:0] main___split_crit_edge_i_i_i__sum_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_371;
reg [31:0] main___split_crit_edge_i_i_i_372;
reg [31:0] main___split_crit_edge_i_i_i_372_reg;
reg main___split_crit_edge_i_i_i_exitcond3_i_i_i;
reg main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__us_lcssa_us_i_i_i_ReadBuf_8;
reg [31:0] main__us_lcssa_us_i_i_i___v_i_i_i;
reg [31:0] main__us_lcssa_us_i_i_i___i_i_i;
reg main__us_lcssa_us_i_i_i_373;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_p_jinfo_jpeg_data_0;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg;
reg [15:0] main_read_markers_exit_i_374;
reg [15:0] main_read_markers_exit_i_374_reg;
reg [31:0] main_read_markers_exit_i_375;
reg [31:0] main_read_markers_exit_i_376;
reg [31:0] main_read_markers_exit_i_376_reg;
reg [31:0] main_read_markers_exit_i_377;
reg [31:0] main_read_markers_exit_i_377_reg;
reg [31:0] main_read_markers_exit_i_378;
reg [31:0] main_read_markers_exit_i_378_reg;
reg [15:0] main_read_markers_exit_i_379;
reg [15:0] main_read_markers_exit_i_379_reg;
reg [31:0] main_read_markers_exit_i_380;
reg [31:0] main_read_markers_exit_i_381;
reg [31:0] main_read_markers_exit_i_381_reg;
reg [31:0] main_read_markers_exit_i_382;
reg [31:0] main_read_markers_exit_i_382_reg;
reg [31:0] main_read_markers_exit_i_383;
reg [31:0] main_read_markers_exit_i_384;
reg [31:0] main_read_markers_exit_i_384_reg;
reg [31:0] main_read_markers_exit_i_385;
reg [31:0] main_read_markers_exit_i_385_reg;
reg [31:0] main_read_markers_exit_i_386;
reg [31:0] main_read_markers_exit_i_386_reg;
reg [31:0] main_read_markers_exit_i_387;
reg [31:0] main_read_markers_exit_i_387_reg;
reg [31:0] main_read_markers_exit_i_388;
reg [31:0] main_read_markers_exit_i_388_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_1_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_1_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_2_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_scevgep148_2_i_i_reg;
reg main_389_391;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_1_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_1_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_2_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader21_i_i_preheader_scevgep51_2_i_i_reg;
reg [31:0] main__preheader21_i_i_CurrentMCU_026_i_i;
reg [31:0] main__preheader21_i_i_tmp143_i_i;
reg [31:0] main__preheader21_i_i_tmp143_i_i_reg;
reg [31:0] main_392_i_01_i_i1_i;
reg [31:0] main_392_i_01_i_i1_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep3_i_i2_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep3_i_i2_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep2_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep2_i_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep_i_i3_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep6_i_i4_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep6_i_i4_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep5_i_i5_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep5_i_i5_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep4_i_i6_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_392_scevgep4_i_i6_i_reg;
reg [31:0] main_392_393;
reg [31:0] main_392_394;
reg [31:0] main_392_395;
reg [31:0] main_392_396;
reg [31:0] main_392_397;
reg [31:0] main_392_398;
reg [31:0] main_392_399;
reg [31:0] main_392_400;
reg [31:0] main_392_400_reg;
reg [31:0] main_392_401;
reg [31:0] main_392_401_reg;
reg [31:0] main_392_402;
reg [31:0] main_392_402_reg;
reg [31:0] main_392_403;
reg [31:0] main_392_404;
reg [31:0] main_392_405;
reg [31:0] main_392_405_reg;
reg [31:0] main_392_406;
reg [31:0] main_392_406_reg;
reg [31:0] main_392_407;
reg [31:0] main_392_407_reg;
reg [31:0] main_392_408;
reg [31:0] main_392_409;
reg [31:0] main_392_409_reg;
reg [31:0] main_392_410;
reg [31:0] main_392_410_reg;
reg main_392_411;
reg main_412_413;
reg [31:0] main_415_r_0_i_i_i;
reg [31:0] main_415_r_0_i_i_i_reg;
reg main_415_416;
reg main_417_418;
reg [31:0] main_420_g_0_i_i_i;
reg [31:0] main_420_g_0_i_i_i_reg;
reg main_420_421;
reg main_422_423;
reg [31:0] main_425_b_0_i_i_i;
reg [31:0] main_425_b_0_i_i_i_reg;
reg [31:0] main_425_426;
reg [31:0] main_425_426_reg;
reg main_425_exitcond53_i_i;
reg main_425_exitcond53_i_i_reg;
reg [15:0] main_YuvToRgb_exit_loopexit_i_i_427;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_428;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_428_reg;
reg [15:0] main_YuvToRgb_exit_loopexit_i_i_429;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_430;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_430_reg;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i_reg;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i__pre_i_i;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i__pre_i_i_reg;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_431;
reg [31:0] main_YuvToRgb_exit_loopexit_i_i_431_reg;
reg [31:0] main_432_433;
reg [31:0] main_432_i_324_i_i;
reg [31:0] main_432_i_324_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_432_scevgep139_i_i;
reg [31:0] main_432_tmp141_i_i;
reg [31:0] main_432_tmp141_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_432_scevgep142_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_432_scevgep142_i_i_reg;
reg [31:0] main_432_434;
reg [31:0] main_432_434_reg;
reg [31:0] main_432_435;
reg [31:0] main_432_435_reg;
reg [31:0] main_432_436;
reg [31:0] main_432_436_reg;
reg main_432_437;
reg main_432_438;
reg main_432_438_reg;
reg main_432_or_cond_i_i_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp61_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp62149_i_i;
reg main__lr_ph8_split_us_i_i_i_i_tmp63_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_smax_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_smax_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp64_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp67_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp67_i_i_reg;
reg main__lr_ph8_split_us_i_i_i_i_tmp68_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_umax_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_umax_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp69_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp69_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp82_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp83150_i_i;
reg main__lr_ph8_split_us_i_i_i_i_tmp84_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_smax85_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_smax85_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp86_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp89_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp89_i_i_reg;
reg main__lr_ph8_split_us_i_i_i_i_tmp90_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_umax91_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_umax91_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp92_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp92_i_i_reg;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp121_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp122_i_i;
reg [31:0] main__lr_ph8_split_us_i_i_i_i_tmp122_i_i_reg;
reg [31:0] main_439_indvar_next18_i_i_i_i;
reg main_439_exitcond93_i_i;
reg [31:0] main_440_indvar_i_i_i_i;
reg [31:0] main_440_tmp124_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_440_scevgep24_i_i_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_440_scevgep24_i_i_i_i_reg;
reg [31:0] main_440_tmp137_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_440__14_us_i_i_i_i;
reg [31:0] main_440_441;
reg [7:0] main_440_442;
reg [31:0] main_440_indvar_next_i_i_i_i;
reg [31:0] main_440_indvar_next_i_i_i_i_reg;
reg main_440_exitcond70_i_i;
reg main_440_exitcond70_i_i_reg;
reg [31:0] main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
reg [31:0] main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg;
reg [31:0] main__lr_ph_us_i_i_i_i_tmp118_i_i;
reg [31:0] main__lr_ph_us_i_i_i_i_tmp123_i_i;
reg [31:0] main__lr_ph_us_i_i_i_i_tmp123_i_i_reg;
reg [31:0] main__lr_ph_us_i_i_i_i_tmp136_i_i;
reg [31:0] main__lr_ph_us_i_i_i_i_tmp136_i_i_reg;
reg [31:0] main_WriteOneBlock_exit_i_i_i_443;
reg main_WriteOneBlock_exit_i_i_i_444;
reg [31:0] main_WriteBlock_exit_i_i_446;
reg main_WriteBlock_exit_i_i_exitcond116_i_i;
reg main_447_448;
reg main_449_451;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_452;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_452_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_453;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_453_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_i8_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_i8_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_1_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_1_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_2_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_2_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_3_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_lr_ph_i_i_scevgep_3_i_i_reg;
reg [31:0] main__preheader_i_i_indvar_i7_i;
reg [31:0] main__preheader_i_i_indvar_i7_i_reg;
reg [31:0] main__preheader_i_i_tmp48_i_i;
reg [31:0] main__preheader_i_i_tmp49_i_i;
reg [31:0] main__preheader_i_i_tmp49_i_i_reg;
reg [31:0] main__preheader16_i_i_i_517_i_i;
reg [31:0] main__preheader16_i_i_i_517_i_i_reg;
reg [31:0] main_454_i_01_i2_i_i;
reg [31:0] main_454_i_01_i2_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep4_i6_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep4_i6_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep5_i7_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep5_i7_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep6_i8_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep6_i8_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep_i3_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep3_i5_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep3_i5_i_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep2_i4_i_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_454_scevgep2_i4_i_i_reg;
reg [31:0] main_454_455;
reg [31:0] main_454_456;
reg [31:0] main_454_457;
reg [31:0] main_454_458;
reg [31:0] main_454_459;
reg [31:0] main_454_460;
reg [31:0] main_454_461;
reg [31:0] main_454_462;
reg [31:0] main_454_462_reg;
reg [31:0] main_454_463;
reg [31:0] main_454_463_reg;
reg [31:0] main_454_464;
reg [31:0] main_454_464_reg;
reg [31:0] main_454_465;
reg [31:0] main_454_466;
reg [31:0] main_454_467;
reg [31:0] main_454_467_reg;
reg [31:0] main_454_468;
reg [31:0] main_454_468_reg;
reg [31:0] main_454_469;
reg [31:0] main_454_469_reg;
reg [31:0] main_454_470;
reg [31:0] main_454_471;
reg [31:0] main_454_471_reg;
reg [31:0] main_454_472;
reg [31:0] main_454_472_reg;
reg main_454_473;
reg main_474_475;
reg [31:0] main_477_r_0_i9_i_i;
reg [31:0] main_477_r_0_i9_i_i_reg;
reg main_477_478;
reg main_479_480;
reg [31:0] main_482_g_0_i10_i_i;
reg [31:0] main_482_g_0_i10_i_i_reg;
reg main_482_483;
reg main_484_485;
reg [31:0] main_487_b_0_i11_i_i;
reg [31:0] main_487_b_0_i11_i_i_reg;
reg [31:0] main_487_488;
reg [31:0] main_487_488_reg;
reg main_487_exitcond_i_i;
reg main_487_exitcond_i_i_reg;
reg [31:0] main_YuvToRgb_exit13_i_i_489;
reg main_YuvToRgb_exit13_i_i_exitcond35_i_i;
reg main__loopexit_i_i_490;
reg main__loopexit_i_i_490_reg;
reg [31:0] main__loopexit_i_i_indvar_next_i_i;
reg [31:0] main__loopexit_i_i_indvar_next_i_i_reg;
reg [31:0] main_decode_start_exit_i_main_result_promoted3_i;
reg [31:0] main_491_492;
reg [31:0] main_491_492_reg;
reg [31:0] main_491_j_01_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_491_scevgep7_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_491_scevgep7_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_491_scevgep_i;
reg [7:0] main_491_493;
reg [7:0] main_491_493_reg;
reg [7:0] main_491_494;
reg main_491_495;
reg [31:0] main_491_496;
reg [31:0] main_491_497;
reg [31:0] main_491_498;
reg [31:0] main_491_498_reg;
reg main_491_exitcond_i;
reg main_491_exitcond_i_reg;
reg [31:0] main__preheader_1_i_499;
reg [31:0] main__preheader_1_i_499_reg;
reg [31:0] main__preheader_1_i_j_01_1_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_1_i_scevgep7_1_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_1_i_scevgep7_1_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_1_i_scevgep_1_i;
reg [7:0] main__preheader_1_i_500;
reg [7:0] main__preheader_1_i_500_reg;
reg [7:0] main__preheader_1_i_501;
reg main__preheader_1_i_502;
reg [31:0] main__preheader_1_i_503;
reg [31:0] main__preheader_1_i_504;
reg [31:0] main__preheader_1_i_505;
reg [31:0] main__preheader_1_i_505_reg;
reg main__preheader_1_i_exitcond_1_i;
reg main__preheader_1_i_exitcond_1_i_reg;
reg main_jpeg2bmp_main_exit_506;
reg [31:0] main_jpeg2bmp_main_exit_507;
reg [31:0] main_jpeg2bmp_main_exit_storemerge;
reg main_jpeg2bmp_main_exit_508;
reg [31:0] main_jpeg2bmp_main_exit_509;
reg [31:0] main_jpeg2bmp_main_exit__storemerge;
reg [31:0] main_jpeg2bmp_main_exit_511;
reg main_jpeg2bmp_main_exit_512;
reg [31:0] main__preheader_2_i_513;
reg [31:0] main__preheader_2_i_513_reg;
reg [31:0] main__preheader_2_i_j_01_2_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_2_i_scevgep7_2_i;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_2_i_scevgep7_2_i_reg;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader_2_i_scevgep_2_i;
reg [7:0] main__preheader_2_i_514;
reg [7:0] main__preheader_2_i_514_reg;
reg [7:0] main__preheader_2_i_515;
reg main__preheader_2_i_516;
reg [31:0] main__preheader_2_i_517;
reg [31:0] main__preheader_2_i_518;
reg [31:0] main__preheader_2_i_518_reg;
reg [31:0] main__preheader_2_i_519;
reg [31:0] main__preheader_2_i_519_reg;
reg main__preheader_2_i_exitcond_2_i;
reg main__preheader_2_i_exitcond_2_i_reg;
reg [31:0] main_524_525;
reg huff_make_dhuff_tb_start;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_arg_p_xhtbl_bits;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_arg_p_dhtbl_maxcode;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_arg_p_dhtbl_mincode;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_arg_p_dhtbl_valptr;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] huff_make_dhuff_tb_memory_controller_address;
wire huff_make_dhuff_tb_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] huff_make_dhuff_tb_memory_controller_in;
reg huff_make_dhuff_tb_memory_controller_waitrequest;
wire huff_make_dhuff_tb_memory_controller_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] huff_make_dhuff_tb_memory_controller_out;
wire [1:0] huff_make_dhuff_tb_memory_controller_size;
wire huff_make_dhuff_tb_finish;
wire [31:0] huff_make_dhuff_tb_return_val;
reg legup_function_call;
reg decode_block_start;
reg [31:0] decode_block_arg_comp_no;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_arg_out_buf;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_arg_HuffBuff;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] decode_block_memory_controller_address;
wire decode_block_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] decode_block_memory_controller_in;
reg decode_block_memory_controller_waitrequest;
wire decode_block_memory_controller_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] decode_block_memory_controller_out;
wire [1:0] decode_block_memory_controller_size;
wire decode_block_finish;
reg Write4Blocks_start;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_store1;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_store2;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_store3;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_store4;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_p_out_vpos;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_p_out_hpos;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_arg_p_out_buf;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] Write4Blocks_memory_controller_address;
wire Write4Blocks_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] Write4Blocks_memory_controller_in;
reg Write4Blocks_memory_controller_waitrequest;
wire Write4Blocks_memory_controller_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] Write4Blocks_memory_controller_out;
wire [1:0] Write4Blocks_memory_controller_size;
wire Write4Blocks_finish;
reg [31:0] main_signed_multiply_32_1_op0;
reg [31:0] main_signed_multiply_32_1_op1;
reg [31:0] main_signed_multiply_32_1;
reg [31:0] main_signed_multiply_32_2_op0;
reg [31:0] main_signed_multiply_32_2_op1;
reg [31:0] main_signed_multiply_32_2;
reg [31:0] main_signed_multiply_32_0_op0;
reg [31:0] main_signed_multiply_32_0_op1;
reg [31:0] main_signed_multiply_32_0;
reg [31:0] main_signed_divide_32_0_op0;
reg [31:0] main_signed_divide_32_0_op1;
reg [31:0] main_signed_divide_32_0;
wire [31:0] lpm_divide_main_read_markers_exit_i_377_out;
wire [31:0] main_read_markers_exit_i_377_unused;
reg lpm_divide_main_read_markers_exit_i_377_en;
reg [31:0] main_1_i_05_i_phi_temp;
reg [31:0] main__outer_i_i_i_marker_0_phi_temp;
reg [31:0] main__outer_i_i_i_get_dht_0_phi_temp;
reg [31:0] main__outer_i_i_i_get_dqt_0_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__outer_i_i_ReadBuf_0_phi_temp;
reg [7:0] main__outer_i_i_p_jinfo_num_components_0_phi_temp;
reg main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp;
reg main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp;
reg [31:0] main__backedge_i_i_outer_i_marker_1_ph_phi_temp;
reg [31:0] main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp;
reg [31:0] main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp;
reg [7:0] main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp;
reg main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp;
reg [31:0] main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp;
reg [31:0] main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp;
reg [7:0] main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp;
reg main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp;
reg [31:0] main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp;
reg [7:0] main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
reg main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
reg [31:0] main__backedge_i_i_i_marker_1_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__backedge_i_i_ReadBuf_1_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit3_i_i_i_18_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
reg [31:0] main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__loopexit_i_preheader_i_i__ph_i_i_phi_temp;
reg [31:0] main__lr_ph_i_i_i_indvar_i_i_phi_temp;
reg [31:0] main__loopexit_i_i_i_indvar9_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i1_i_i_ReadBuf_3_phi_temp;
reg [31:0] main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___crit_edge_i_i_i_ReadBuf_4_phi_temp;
reg [31:0] main__preheader5_i_i_i_i_get_sos_0_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__preheader5_i_i_i_ReadBuf_5_phi_temp;
reg [31:0] main__preheader5_i_i_i_192_phi_temp;
reg [31:0] main_200_201_phi_temp;
reg [31:0] main__lr_ph5_i_i_i_i_get_dht_2_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph5_i_i_i_ReadBuf_6_phi_temp;
reg [31:0] main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_huffval_0_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_286_p_xhtbl_bits_0_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main_287_288_phi_temp;
reg [31:0] main_287_indvar_i_i_i_phi_temp;
reg [31:0] main_287_count_01_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i10_i_i_304_phi_temp;
reg [31:0] main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___crit_edge_i12_i_i_ReadBuf_7_phi_temp;
reg [31:0] main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__lr_ph_i15_i_i_330_phi_temp;
reg [31:0] main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__split_us_i_i_i_354_phi_temp;
reg [31:0] main__split_us_i_i_i_i_01_us_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main___split_crit_edge_i_i_i_361_phi_temp;
reg [31:0] main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp;
reg [31:0] main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp;
reg [31:0] main_392_i_01_i_i1_i_phi_temp;
reg [31:0] main_415_r_0_i_i_i_phi_temp;
reg [31:0] main_420_g_0_i_i_i_phi_temp;
reg [31:0] main_425_b_0_i_i_i_phi_temp;
reg [31:0] main_432_433_phi_temp;
reg [31:0] main_432_i_324_i_i_phi_temp;
reg [31:0] main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp;
reg [31:0] main_440_indvar_i_i_i_i_phi_temp;
reg [31:0] main_WriteBlock_exit_i_i_446_phi_temp;
reg [31:0] main__preheader_i_i_indvar_i7_i_phi_temp;
reg [31:0] main__preheader16_i_i_i_517_i_i_phi_temp;
reg [31:0] main_454_i_01_i2_i_i_phi_temp;
reg [31:0] main_477_r_0_i9_i_i_phi_temp;
reg [31:0] main_482_g_0_i10_i_i_phi_temp;
reg [31:0] main_487_b_0_i11_i_i_phi_temp;
reg [31:0] main_491_492_phi_temp;
reg [31:0] main_491_j_01_i_phi_temp;
reg [31:0] main__preheader_1_i_499_phi_temp;
reg [31:0] main__preheader_1_i_j_01_1_i_phi_temp;
reg [31:0] main__preheader_2_i_513_phi_temp;
reg [31:0] main__preheader_2_i_j_01_2_i_phi_temp;
/* %377 = sdiv i32 %376, 8*/
lpm_divide lpm_divide_main_read_markers_exit_i_377 (
.numer (main_signed_divide_32_0_op0),
.denom (main_signed_divide_32_0_op1),
.quotient (lpm_divide_main_read_markers_exit_i_377_out),
.remain (main_read_markers_exit_i_377_unused),
.clock (clk),
.aclr (1'd0),
.clken (lpm_divide_main_read_markers_exit_i_377_en)
);
defparam
lpm_divide_main_read_markers_exit_i_377.lpm_pipeline = 32,
lpm_divide_main_read_markers_exit_i_377.lpm_widthd = 32,
lpm_divide_main_read_markers_exit_i_377.lpm_widthn = 32,
lpm_divide_main_read_markers_exit_i_377.lpm_drepresentation = "SIGNED",
lpm_divide_main_read_markers_exit_i_377.lpm_nrepresentation = "SIGNED",
lpm_divide_main_read_markers_exit_i_377.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE";
huff_make_dhuff_tb huff_make_dhuff_tb_inst (
.clk (clk),
.reset (reset),
.start (huff_make_dhuff_tb_start),
.finish (huff_make_dhuff_tb_finish),
.return_val (huff_make_dhuff_tb_return_val),
.memory_controller_address (huff_make_dhuff_tb_memory_controller_address),
.memory_controller_write_enable (huff_make_dhuff_tb_memory_controller_write_enable),
.memory_controller_enable (huff_make_dhuff_tb_memory_controller_enable),
.memory_controller_in (huff_make_dhuff_tb_memory_controller_in),
.memory_controller_size (huff_make_dhuff_tb_memory_controller_size),
.memory_controller_waitrequest (huff_make_dhuff_tb_memory_controller_waitrequest),
.memory_controller_out (huff_make_dhuff_tb_memory_controller_out),
.arg_p_xhtbl_bits (huff_make_dhuff_tb_arg_p_xhtbl_bits),
.arg_p_dhtbl_maxcode (huff_make_dhuff_tb_arg_p_dhtbl_maxcode),
.arg_p_dhtbl_mincode (huff_make_dhuff_tb_arg_p_dhtbl_mincode),
.arg_p_dhtbl_valptr (huff_make_dhuff_tb_arg_p_dhtbl_valptr)
);
decode_block decode_block_inst (
.clk (clk),
.reset (reset),
.start (decode_block_start),
.finish (decode_block_finish),
.memory_controller_address (decode_block_memory_controller_address),
.memory_controller_write_enable (decode_block_memory_controller_write_enable),
.memory_controller_enable (decode_block_memory_controller_enable),
.memory_controller_in (decode_block_memory_controller_in),
.memory_controller_size (decode_block_memory_controller_size),
.memory_controller_waitrequest (decode_block_memory_controller_waitrequest),
.memory_controller_out (decode_block_memory_controller_out),
.arg_comp_no (decode_block_arg_comp_no),
.arg_out_buf (decode_block_arg_out_buf),
.arg_HuffBuff (decode_block_arg_HuffBuff)
);
Write4Blocks Write4Blocks_inst (
.clk (clk),
.reset (reset),
.start (Write4Blocks_start),
.finish (Write4Blocks_finish),
.memory_controller_address (Write4Blocks_memory_controller_address),
.memory_controller_write_enable (Write4Blocks_memory_controller_write_enable),
.memory_controller_enable (Write4Blocks_memory_controller_enable),
.memory_controller_in (Write4Blocks_memory_controller_in),
.memory_controller_size (Write4Blocks_memory_controller_size),
.memory_controller_waitrequest (Write4Blocks_memory_controller_waitrequest),
.memory_controller_out (Write4Blocks_memory_controller_out),
.arg_store1 (Write4Blocks_arg_store1),
.arg_store2 (Write4Blocks_arg_store2),
.arg_store3 (Write4Blocks_arg_store3),
.arg_store4 (Write4Blocks_arg_store4),
.arg_p_out_vpos (Write4Blocks_arg_p_out_vpos),
.arg_p_out_hpos (Write4Blocks_arg_p_out_hpos),
.arg_p_out_buf (Write4Blocks_arg_p_out_buf)
);
/* Unsynthesizable Statements */
always @(posedge clk) begin
/* main: %12*/
/* %13 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB8_14)
begin
$write("Not Jpeg File!\n");
end
/* main: %12*/
/* tail call void @exit(i32 0) noreturn nounwind*/
if (cur_state == LEGUP_F_main_BB8_14)
begin
$finish;
end
/* main: %next_marker.exit.i.i*/
/* %23 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str23, i32 0, i32 0), i32 %unread_marker.0.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
$write("\nmarker = 0x%0x\n", main_next_marker_exit_i_i_unread_marker_0_i_i);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) finish <= 0;
end
/* main: %32*/
/* %62 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str1, i32 0, i32 0), i32 %41) nounwind*/
if (cur_state == LEGUP_F_main_BB20_51)
begin
$write("length = %d\n", main_32_41_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_32_41_reg) === 1'bX) finish <= 0;
end
/* main: %32*/
/* %64 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str2, i32 0, i32 0), i32 %63) nounwind*/
if (cur_state == LEGUP_F_main_BB20_51)
begin
$write("data_precision = %d\n", main_32_63_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_32_63_reg) === 1'bX) finish <= 0;
end
/* main: %32*/
/* %67 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str3, i32 0, i32 0), i32 %66) nounwind*/
if (cur_state == LEGUP_F_main_BB20_54)
begin
$write("image_height = %d\n", main_32_66);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_32_66) === 1'bX) finish <= 0;
end
/* main: %32*/
/* %70 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str4, i32 0, i32 0), i32 %69) nounwind*/
if (cur_state == LEGUP_F_main_BB20_57)
begin
$write("image_width = %d\n", main_32_69);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_32_69) === 1'bX) finish <= 0;
end
/* main: %32*/
/* %72 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str5, i32 0, i32 0), i32 %71) nounwind*/
if (cur_state == LEGUP_F_main_BB20_57)
begin
$write("num_components = %d\n", main_32_71_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_32_71_reg) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i1.i.i*/
/* %108 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str6, i32 0, i32 0), i32 %107) nounwind*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
$write(" index = %d\n", main__lr_ph_i1_i_i_107_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_107_reg) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i1.i.i*/
/* %111 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str7, i32 0, i32 0), i32 %110) nounwind*/
if (cur_state == LEGUP_F_main_BB31_95)
begin
$write(" id = %d\n", main__lr_ph_i1_i_i_110);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_110) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i1.i.i*/
/* %114 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str8, i32 0, i32 0), i32 %113) nounwind*/
if (cur_state == LEGUP_F_main_BB31_98)
begin
$write(" h_samp_factor = %d\n", main__lr_ph_i1_i_i_113);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_113) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i1.i.i*/
/* %117 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str9, i32 0, i32 0), i32 %116) nounwind*/
if (cur_state == LEGUP_F_main_BB31_101)
begin
$write(" v_samp_factor = %d\n", main__lr_ph_i1_i_i_116);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_116) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i1.i.i*/
/* %120 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str10, i32 0, i32 0), i32 %119) nounwind*/
if (cur_state == LEGUP_F_main_BB31_104)
begin
$write(" quant_tbl_no = %d\n\n", main__lr_ph_i1_i_i_119);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_119) === 1'bX) finish <= 0;
end
/* main: %163*/
/* %164 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([27 x i8]* @.str11, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB43_143)
begin
$write("\nSampling Factor is 4:1:1\n");
end
/* main: %165*/
/* %166 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([27 x i8]* @.str12, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB44_144)
begin
$write("\nSampling Factor is 1:1:1\n");
end
/* main: %167*/
/* %180 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str13, i32 0, i32 0), i32 %176) nounwind*/
if (cur_state == LEGUP_F_main_BB45_148)
begin
$write(" length = %d\n", main_167_176);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_167_176) === 1'bX) finish <= 0;
end
/* main: %167*/
/* %181 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str14, i32 0, i32 0), i32 %179) nounwind*/
if (cur_state == LEGUP_F_main_BB45_149)
begin
$write(" num_comp = %d\n", main_167_179);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_167_179) === 1'bX) finish <= 0;
end
/* main: %209*/
/* %210 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([19 x i8]* @.str15, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB55_168)
begin
$write("Bad Component ID!\n");
end
/* main: %209*/
/* tail call void @exit(i32 0) noreturn nounwind*/
if (cur_state == LEGUP_F_main_BB55_168)
begin
$finish;
end
/* main: %211*/
/* %216 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str16, i32 0, i32 0), i32 %197) nounwind*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
$write(" comp_id = %d\n", main_194_197_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_194_197_reg) === 1'bX) finish <= 0;
end
/* main: %211*/
/* %219 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str17, i32 0, i32 0), i32 %218) nounwind*/
if (cur_state == LEGUP_F_main_BB56_176)
begin
$write(" dc_tbl_no = %d\n", main_211_218);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_211_218) === 1'bX) finish <= 0;
end
/* main: %211*/
/* %222 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([21 x i8]* @.str18, i32 0, i32 0), i32 %221) nounwind*/
if (cur_state == LEGUP_F_main_BB56_179)
begin
$write(" ac_tbl_no = %d\n", main_211_221);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_211_221) === 1'bX) finish <= 0;
end
/* main: %248*/
/* %259 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str13, i32 0, i32 0), i32 %258) nounwind*/
if (cur_state == LEGUP_F_main_BB64_204)
begin
$write(" length = %d\n", main_248_258);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_248_258) === 1'bX) finish <= 0;
end
/* main: %.lr.ph5.i.i.i*/
/* %269 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([15 x i8]* @.str19, i32 0, i32 0), i32 %268) nounwind*/
if (cur_state == LEGUP_F_main_BB67_214)
begin
$write(" index = 0x%0x\n", main__lr_ph5_i_i_i_268);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_268) === 1'bX) finish <= 0;
end
/* main: %293*/
/* %294 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str20, i32 0, i32 0), i32 %292) nounwind*/
if (cur_state == LEGUP_F_main_BB74_228)
begin
$write(" count = %d\n", main_287_292_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_287_292_reg) === 1'bX) finish <= 0;
end
/* main: %312*/
/* %323 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str13, i32 0, i32 0), i32 %322) nounwind*/
if (cur_state == LEGUP_F_main_BB79_243)
begin
$write(" length = %d\n", main_312_322);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_312_322) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i15.i.i*/
/* %336 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str21, i32 0, i32 0), i32 %334) nounwind*/
if (cur_state == LEGUP_F_main_BB82_253)
begin
$write(" prec = %d\n", main__lr_ph_i15_i_i_334);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_334) === 1'bX) finish <= 0;
end
/* main: %.lr.ph.i15.i.i*/
/* %337 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str22, i32 0, i32 0), i32 %335) nounwind*/
if (cur_state == LEGUP_F_main_BB82_253)
begin
$write(" num = %d\n", main__lr_ph_i15_i_i_335);
// to fix quartus warning
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_335) === 1'bX) finish <= 0;
end
/* main: %389*/
/* %390 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([26 x i8]* @.str24, i32 0, i32 0), i32 %384) nounwind*/
if (cur_state == LEGUP_F_main_BB91_355)
begin
$write("Decode 1:1:1 NumMCU = %d\n", main_read_markers_exit_i_384_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_read_markers_exit_i_384_reg) === 1'bX) finish <= 0;
end
/* main: %449*/
/* %450 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([26 x i8]* @.str25, i32 0, i32 0), i32 %384) nounwind*/
if (cur_state == LEGUP_F_main_BB114_406)
begin
$write("Decode 4:1:1 NumMCU = %d\n", main_read_markers_exit_i_384_reg);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_read_markers_exit_i_384_reg) === 1'bX) finish <= 0;
end
/* main: %jpeg2bmp_main.exit*/
/* %510 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str27, i32 0, i32 0), i32 %.storemerge) nounwind*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
$write("Result: %d\n", main_jpeg2bmp_main_exit__storemerge);
// to fix quartus warning
if (^reset !== 1'bX && ^(main_jpeg2bmp_main_exit__storemerge) === 1'bX) finish <= 0;
end
/* main: %520*/
/* %521 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str28, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB135_473)
begin
$write("RESULT: PASS\n");
end
/* main: %522*/
/* %523 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str29, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB136_474)
begin
$write("RESULT: FAIL\n");
end
end
always @(posedge clk) begin
if (reset == 1'd1)
begin
cur_state <= 9'd0;
if (^reset !== 1'bX && ^(9'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd1)
begin
cur_state <= LEGUP_F_main_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_0 & start == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB0_1 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB0_1;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB0_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_2 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_2 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB1_3;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_3 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB1_3;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_3 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB1_4;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB1_2;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB1_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB4_7;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB4_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB4_7;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB4_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB5_8 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB5_8 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB6_9 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB6_9 & memory_controller_waitrequest == 1'd0 & main__outer_i_i_sow_SOI_0_ph_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB7_10;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB6_9 & memory_controller_waitrequest == 1'd0 & main__outer_i_i_sow_SOI_0_ph_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB11_19;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_10 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB7_10;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_10 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB7_11;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_11 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB7_11;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_11 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB7_12;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_12 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB7_12;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_12 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB7_13;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_13 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB7_13;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB7_13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_13 & memory_controller_waitrequest == 1'd0 & main_6_or_cond_i_i_i == 1'd1)
begin
cur_state <= LEGUP_F_main_BB9_15;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB7_13 & memory_controller_waitrequest == 1'd0 & main_6_or_cond_i_i_i == 1'd0)
begin
cur_state <= LEGUP_F_main_BB8_14;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB8_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB8_14 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB8_14;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB8_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB8_14 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_15 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB9_15;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_15 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB9_16;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_16 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB9_16;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_16) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_16 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB9_17;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_17 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB9_17;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB9_17) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB9_17 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB17_31;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB10_18 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB10_18;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB10_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB10_18 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB11_19;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_19 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB11_19;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_19) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_19 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB11_20;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_20 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB11_20;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_20) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_20 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB11_21;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_21 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB11_21;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB11_21) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_21 & memory_controller_waitrequest == 1'd0 & main__loopexit3_i_i_i_19 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB14_26;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB14_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB11_21 & memory_controller_waitrequest == 1'd0 & main__loopexit3_i_i_i_19 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB12_22;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_22 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB12_22;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_22 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB12_23;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_23 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB12_23;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_23) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_23 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB12_24;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_24 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB12_24;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_24 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i_i_i_20 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB13_25;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB13_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB12_24 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i_i_i_20 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB12_22;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB12_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB13_25 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB13_25;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB13_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB13_25 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB14_26;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB14_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB14_26 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB14_26;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB14_26) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB14_26 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB15_27;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_27 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB15_27;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_27 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB15_28;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_28 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB15_28;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_28) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_28 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB15_29;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_29 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB15_29;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_29) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_29 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_i_22 == 32'd255)
begin
cur_state <= LEGUP_F_main_BB15_27;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB15_27) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_29 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_i_22 == 32'd0)
begin
cur_state <= LEGUP_F_main_BB10_18;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB10_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB15_29 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_i_22 != 32'd255 & main__loopexit_i_i_i_22 != 32'd0)
begin
cur_state <= LEGUP_F_main_BB16_30;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB16_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB16_30 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB16_30;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB16_30) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB16_30 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB17_31;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_31 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB17_31;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_31) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_31 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB17_32;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_32 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB17_32;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_32) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_32 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB17_33;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_33 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB17_33;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_33 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB17_34;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_34 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB17_34;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB17_34) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_34 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_27 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB18_35;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB17_34 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_27 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB19_38;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB19_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_35 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB18_35;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_35) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_35 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB18_36;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_36 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB18_36;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_36 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB18_37;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_37 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB18_37;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB18_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB18_37 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB19_38;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB19_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB19_38;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB19_38) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
cur_state <= LEGUP_F_main_BB2_5;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB2_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd192)
begin
cur_state <= LEGUP_F_main_BB20_39;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd218)
begin
cur_state <= LEGUP_F_main_BB45_145;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_145) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd196)
begin
cur_state <= LEGUP_F_main_BB64_201;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd219)
begin
cur_state <= LEGUP_F_main_BB79_240;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_240) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd217)
begin
cur_state <= LEGUP_F_main_BB90_277;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_277) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd216 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd192 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd218 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd196 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd219 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd217)
begin
cur_state <= LEGUP_F_main_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_39 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_39;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_39) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_39 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_40;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_40 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_40;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_40) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_40 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_41;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_41 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_41;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_41 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_42;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_42 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_42;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_42 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_43;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_43 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_43;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_43 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_44;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_44 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_44;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_44 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_45;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_45 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_45;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_45) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_45 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_46;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_46 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_46;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_46) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_46 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_47;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_47 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_47;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_47 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_48;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_48 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_48;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_48 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_49;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_49 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_49;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_49) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_49 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_50;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_50 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_50;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_50) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_50 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_51;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_51 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_51;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_51) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_51 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_52;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_52 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_52;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_52 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_53;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_53 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_53;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_53) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_53 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_54;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_54 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_54;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_54) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_54 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_55;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_55 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_55;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_55 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_56;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_56 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_56;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_56 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB20_57;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_57 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB20_57;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB20_57) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_57 & memory_controller_waitrequest == 1'd0 & main_32_73_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB21_58;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB20_57 & memory_controller_waitrequest == 1'd0 & main_32_73_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB22_61;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB22_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_58 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB21_58;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_58) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_58 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB21_59;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_59) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_59 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB21_59;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_59) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_59 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB21_60;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_60 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB21_60;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB21_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB21_60 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB22_61;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB22_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB22_61 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB22_61;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB22_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB22_61 & memory_controller_waitrequest == 1'd0 & main_77_78 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB23_62;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_62) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB22_61 & memory_controller_waitrequest == 1'd0 & main_77_78 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB24_65;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_62 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB23_62;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_62) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_62 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB23_63;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_63) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_63 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB23_63;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_63) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_63 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB23_64;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_64) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_64 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB23_64;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB23_64) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB23_64 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB24_65;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_65 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB24_65;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_65) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_65 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB24_66;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_66) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_66 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB24_66;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_66) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_66 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB24_67;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_67) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_67 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB24_67;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB24_67) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_67 & memory_controller_waitrequest == 1'd0 & main_82_84 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB25_68;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_68) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB24_67 & memory_controller_waitrequest == 1'd0 & main_82_84 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB26_71;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_68 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB25_68;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_68) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_68 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB25_69;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_69 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB25_69;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_69) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_69 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB25_70;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_70) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_70 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB25_70;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB25_70) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB25_70 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB26_71;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_71 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB26_71;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_71 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB26_72;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_72 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB26_72;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_72) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_72 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB26_73;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_73 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB26_73;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB26_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_73 & memory_controller_waitrequest == 1'd0 & main_88_90 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB27_74;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_74) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB26_73 & memory_controller_waitrequest == 1'd0 & main_88_90 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB28_77;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB28_77) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_74 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB27_74;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_74) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_74 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB27_75;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_75) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_75 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB27_75;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_75) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_75 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB27_76;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_76) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_76 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB27_76;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB27_76) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB27_76 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB28_77;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB28_77) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB28_77 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB28_77;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB28_77) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB28_77 & memory_controller_waitrequest == 1'd0 & main_94_95 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB29_78;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_78) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB28_77 & memory_controller_waitrequest == 1'd0 & main_94_95 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB30_81;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB30_81) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_78 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB29_78;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_78) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_78 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB29_79;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_79) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_79 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB29_79;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_79) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_79 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB29_80;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_80) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_80 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB29_80;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB29_80) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB29_80 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_82;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB30_81;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB30_81) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd0 & main__preheader_i_i_i_98 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_82;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd0 & main__preheader_i_i_i_98 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB42_140;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_82 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_82;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_82 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_83;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_83) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_83 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_83;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_83) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_83 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_84;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_84) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_84 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_84;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_84) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_84 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_85;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_85) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_85 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_85;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_85) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_85 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_86;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_86) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_86 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_86;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_86) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_86 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_87;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_87) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_87 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_87;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_87) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_87 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_88;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_88) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_88 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_88;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_88) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_88 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_89;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_89) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_89 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_89;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_89) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_89 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_90;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_90 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_90;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_90) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_90 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_91;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_91) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_91 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_91;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_91) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_91 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_92;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_92) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_92 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_92;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_92) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_92 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_93;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_93) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_93 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_93;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_93) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_93 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_94;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_94) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_94 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_94;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_94) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_94 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_95;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_95) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_95 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_95;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_95) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_95 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_96;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_96) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_96 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_96;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_96) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_96 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_97;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_97) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_97 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_97;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_97) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_97 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_98;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_98 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_98;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_98) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_98 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_99;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_99 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_99;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_99 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_100;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_100 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_100;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_100) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_100 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_101;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_101 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_101;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_101 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_102;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_102) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_102 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_102;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_102) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_102 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_103;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_103 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_103;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_103) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_103 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_104;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_104 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_104;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_104 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_105;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_105 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_105;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_105 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_106;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_106 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_106;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_106) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_106 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_107;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_107) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_107 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_107;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_107) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_107 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB31_108;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_108) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_108 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_108;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_108) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_108 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i1_i_i_124 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB32_109;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB31_108 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i1_i_i_124 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB33_112;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_109 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB32_109;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_109) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_109 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB32_110;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_110) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_110 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB32_110;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_110) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_110 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB32_111;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_111) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_111 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB32_111;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB32_111) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB32_111 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB33_112;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_112 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB33_112;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_112) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_112 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB33_113;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_113) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_113 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB33_113;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_113) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_113 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB33_114;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_114 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB33_114;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_114) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_114 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB33_115;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_115) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_115 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB33_115;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB33_115) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_115 & memory_controller_waitrequest == 1'd0 & main_128_132 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB34_116;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB33_115 & memory_controller_waitrequest == 1'd0 & main_128_132 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB35_119;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_119) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_116 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB34_116;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_116) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_116 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB34_117;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_117) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_117 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB34_117;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_117) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_117 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB34_118;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_118) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_118 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB34_118;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB34_118) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB34_118 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB35_119;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_119) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_119 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB35_119;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_119) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_119 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB35_120;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_120) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_120 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB35_120;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_120) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_120 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB35_121;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_121) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_121 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB35_121;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_121) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_121 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB35_122;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_122 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB35_122;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB35_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_122 & memory_controller_waitrequest == 1'd0 & main_136_140 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB36_123;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_123) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB35_122 & memory_controller_waitrequest == 1'd0 & main_136_140 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB37_126;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_126) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_123 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB36_123;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_123) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_123 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB36_124;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_124) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_124 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB36_124;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_124) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_124 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB36_125;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_125) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_125 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB36_125;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB36_125) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB36_125 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB37_126;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_126) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_126 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB37_126;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_126) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_126 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB37_127;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_127) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_127 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB37_127;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_127) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_127 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB37_128;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_128) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_128 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB37_128;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB37_128) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_128 & memory_controller_waitrequest == 1'd0 & main_144_147 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB38_129;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB37_128 & memory_controller_waitrequest == 1'd0 & main_144_147 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB39_132;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_129 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB38_129;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_129) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_129 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB38_130;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_130 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB38_130;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_130 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB38_131;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_131 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB38_131;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB38_131) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB38_131 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB39_132;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_132 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB39_132;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_132) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_132 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB39_133;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_133 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB39_133;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_133) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_133 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB39_134;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_134 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB39_134;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_134) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_134 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB39_135;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_135 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB39_135;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB39_135) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_135 & memory_controller_waitrequest == 1'd0 & main_151_155 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB40_136;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB39_135 & memory_controller_waitrequest == 1'd0 & main_151_155 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB41_139;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB41_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_136 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB40_136;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_136) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_136 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB40_137;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_137) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_137 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB40_137;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_137) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_137 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB40_138;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_138) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_138 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB40_138;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB40_138) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB40_138 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB41_139;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB41_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB41_139;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB41_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd0 & main_159_160 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB31_82;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB31_82) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd0 & main_159_160 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB42_140;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_140 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB42_140;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_140) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_140 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB42_141;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_141) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_141 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB42_141;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_141) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_141 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB42_142;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_142) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_142 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB42_142;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB42_142) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_142 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i_i_i_162 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB43_143;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB43_143) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB42_142 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i_i_i_162 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB44_144;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB44_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB43_143;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB43_143) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB44_144;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB44_144) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB5_8;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB5_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_145 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB45_145;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_145) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_145 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB45_146;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_146) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_146 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB45_146;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_146) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_146 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB45_147;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_147 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB45_147;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_147) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_147 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB45_148;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_148) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_148 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB45_148;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_148) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_148 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB45_149;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_149) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_149 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB45_149;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB45_149) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_149 & memory_controller_waitrequest == 1'd0 & main_167_182_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB46_150;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB45_149 & memory_controller_waitrequest == 1'd0 & main_167_182_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB47_153;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB47_153) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_150 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB46_150;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_150) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_150 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB46_151;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_151 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB46_151;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_151) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_151 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB46_152;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_152) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_152 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB46_152;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB46_152) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB46_152 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB47_153;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB47_153) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB47_153 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB47_153;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB47_153) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB47_153 & memory_controller_waitrequest == 1'd0 & main_186_187 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB48_154;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_154) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB47_153 & memory_controller_waitrequest == 1'd0 & main_186_187 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB49_157;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB49_157) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_154 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB48_154;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_154) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_154 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB48_155;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_155) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_155 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB48_155;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_155) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_155 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB48_156;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_156) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_156 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB48_156;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB48_156) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB48_156 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB49_157;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB49_157) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB49_157 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB49_157;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB49_157) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB49_157 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB50_158;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB50_158) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB50_158 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB50_158;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB50_158) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB50_158 & memory_controller_waitrequest == 1'd0 & main__preheader5_i_i_i_193 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB51_159;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_159) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB50_158 & memory_controller_waitrequest == 1'd0 & main__preheader5_i_i_i_193 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB63_200;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB63_200) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_159 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB51_159;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_159) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_159 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB51_160;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_160) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_160 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB51_160;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_160) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_160 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB51_161;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_161) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_161 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB51_161;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_161) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_161 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB51_162;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_162) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_162 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB51_162;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB51_162) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB51_162 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB52_163;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB52_163) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB52_163 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB52_163;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB52_163) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB52_163 & memory_controller_waitrequest == 1'd0 & main_200_202 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB53_164;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_164) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB52_163 & memory_controller_waitrequest == 1'd0 & main_200_202 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB55_168;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB55_168) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_164 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB53_164;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_164) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_164 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB53_165;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_165) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_165 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB53_165;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_165) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_165 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB53_166;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_166) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_166 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB53_166;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB53_166) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_166 & memory_controller_waitrequest == 1'd0 & main_203_206 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_169;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_169) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB53_166 & memory_controller_waitrequest == 1'd0 & main_203_206 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB54_167;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB54_167) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB54_167 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB54_167;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB54_167) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB54_167 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB52_163;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB52_163) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB55_168 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB55_168;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB55_168) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB55_168 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_169 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_169;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_169) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_169 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_170;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_170) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_170 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_170;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_170) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_170 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_171;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_171) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_171 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_171;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_171) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_171 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_172;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_172) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_172 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_172;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_172) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_172 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_173;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_173) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_173 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_173;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_173) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_173 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_174;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_174) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_174 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_174;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_174) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_174 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_175;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_175) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_175 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_175;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_175) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_175 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_176;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_176) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_176 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_176;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_176) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_176 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_177;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_177) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_177 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_177;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_177) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_177 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_178;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_178) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_178 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_178;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_178) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_178 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_179;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_179) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_179 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_179;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_179) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_179 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_180;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_180) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_180 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_180;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_180) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_180 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_181;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_181) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_181 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_181;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_181) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_181 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB56_182;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_182) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_182 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB56_182;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB56_182) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_182 & memory_controller_waitrequest == 1'd0 & main_211_225 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB57_183;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_183) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB56_182 & memory_controller_waitrequest == 1'd0 & main_211_225 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB58_186;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_186) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_183 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB57_183;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_183) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_183 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB57_184;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_184) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_184 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB57_184;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_184) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_184 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB57_185;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_185) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_185 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB57_185;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB57_185) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB57_185 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB58_186;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_186) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_186 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB58_186;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_186) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_186 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB58_187;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_187) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_187 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB58_187;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_187) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_187 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB58_188;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_188) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_188 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB58_188;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_188) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_188 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB58_189;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_189) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_189 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB58_189;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB58_189) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_189 & memory_controller_waitrequest == 1'd0 & main_229_234 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB59_190;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_190) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB58_189 & memory_controller_waitrequest == 1'd0 & main_229_234 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB60_193;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_193) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_190 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB59_190;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_190) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_190 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB59_191;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_191) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_191 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB59_191;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_191) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_191 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB59_192;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_192 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB59_192;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB59_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB59_192 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB60_193;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_193) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_193 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB60_193;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_193) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_193 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB60_194;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_194) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_194 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB60_194;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_194) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_194 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB60_195;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_195) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_195 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB60_195;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB60_195) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_195 & memory_controller_waitrequest == 1'd0 & main_238_241 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB61_196;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_196) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB60_195 & memory_controller_waitrequest == 1'd0 & main_238_241 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB62_199;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB62_199) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_196 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB61_196;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_196) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_196 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB61_197;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_197) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_197 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB61_197;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_197) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_197 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB61_198;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_198) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_198 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB61_198;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB61_198) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB61_198 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB62_199;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB62_199) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB62_199 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB62_199;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB62_199) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB62_199 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB50_158;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB50_158) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB63_200 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB63_200;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB63_200) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB63_200 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_277;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_277) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_201 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_201;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_201 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_202;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_202) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_202 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_202;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_202) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_202 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_203;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_203) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_203 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_203;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_203) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_203 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_204;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_204) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_204 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_204;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_204) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_204 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_205;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_205) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_205 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_205;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_205) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_205 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_206;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_206) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_206 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_206;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_206) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_206 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB64_207;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_207) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_207 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB64_207;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB64_207) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_207 & memory_controller_waitrequest == 1'd0 & main_248_261 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB65_208;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_208) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB64_207 & memory_controller_waitrequest == 1'd0 & main_248_261 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB66_211;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB66_211) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_208 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB65_208;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_208) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_208 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB65_209;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_209) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_209 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB65_209;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_209) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_209 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB65_210;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_210) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_210 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB65_210;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB65_210) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB65_210 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB66_211;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB66_211) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB66_211;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB66_211) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_212;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_212) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_212 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_212;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_212) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_212 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB67_213;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_213) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_213 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_213;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_213) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_213 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB67_214;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_214) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_214 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_214;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_214) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_214 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB67_215;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_215) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_215 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_215;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_215) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_215 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB67_216;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_216) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_216 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_216;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_216) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_216 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB67_217;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_217) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_217 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_217;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_217) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_217 & memory_controller_waitrequest == 1'd0 & main__lr_ph5_i_i_i_272 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB68_218;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_218) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB67_217 & memory_controller_waitrequest == 1'd0 & main__lr_ph5_i_i_i_272 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB69_221;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB69_221) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_218 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB68_218;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_218) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_218 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB68_219;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_219) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_219 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB68_219;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_219) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_219 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB68_220;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_220) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_220 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB68_220;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB68_220) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB68_220 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB69_221;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB69_221) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB69_221 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB69_221;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB69_221) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB69_221 & memory_controller_waitrequest == 1'd0 & main_276_278 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB71_223;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB71_223) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB69_221 & memory_controller_waitrequest == 1'd0 & main_276_278 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB70_222;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB70_222) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB70_222 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB70_222;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB70_222) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB70_222 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB72_224;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB72_224) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB71_223 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB71_223;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB71_223) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB71_223 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB72_224;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB72_224) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB72_224 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB72_224;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB72_224) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB72_224 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB73_225;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_225) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_225 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB73_225;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_225) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_225 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB73_226;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_226) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_226 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB73_226;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_226) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_226 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB73_227;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_227) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB73_227;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_227) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd0 & main_287_exitcond_i_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB74_228;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_228) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd0 & main_287_exitcond_i_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB73_225;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB73_225) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_228 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB74_228;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_228) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_228 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB74_229;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_229) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_229 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB74_229;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_229) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_229 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB74_230;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_230) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_230 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB74_230;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_230) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_230 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB74_231;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_231) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_231 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB74_231;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB74_231) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_231 & memory_controller_waitrequest == 1'd0 & main_293_297 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB75_232;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_232) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB74_231 & memory_controller_waitrequest == 1'd0 & main_293_297 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB76_235;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB76_235) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_232 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB75_232;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_232) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_232 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB75_233;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_233) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_233 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB75_233;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_233) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_233 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB75_234;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_234) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_234 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB75_234;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB75_234) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB75_234 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB76_235;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB76_235) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB76_235;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB76_235) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd0 & main_301_303 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB77_236;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_236) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd0 & main_301_303 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB78_239;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB78_239) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_236 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB77_236;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_236) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_236 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB77_237;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_237) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_237 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB77_237;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_237) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_237 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB77_238;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_238) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB77_238;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_238) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i10_i_i_exitcond7_i_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB78_239;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB78_239) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i10_i_i_exitcond7_i_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB77_236;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB77_236) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB78_239;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB78_239) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB67_212;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB67_212) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB3_6;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB3_6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_240 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_240;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_240) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_240 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_241;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_241) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_241 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_241;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_241) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_241 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_242;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_242) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_242 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_242;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_242) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_242 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_243;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_243) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_243 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_243;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_243) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_243 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_244;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_244) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_244 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_244;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_244) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_244 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_245;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_245) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_245 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_245;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_245) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_245 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB79_246;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_246) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_246 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB79_246;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB79_246) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_246 & memory_controller_waitrequest == 1'd0 & main_312_325 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB80_247;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_247) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB79_246 & memory_controller_waitrequest == 1'd0 & main_312_325 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB81_250;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB81_250) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_247 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB80_247;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_247) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_247 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB80_248;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_248) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_248 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB80_248;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_248) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_248 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB80_249;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_249) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_249 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB80_249;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB80_249) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB80_249 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB81_250;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB81_250) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB81_250;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB81_250) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_251;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_251) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB6_9;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_251 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_251;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_251) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_251 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB82_252;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_252) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_252 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_252;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_252) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_252 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB82_253;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_253) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_253 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_253;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_253) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_253 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB82_254;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_254) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_254 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_254;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_254) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_254 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB82_255;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_255 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_255;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_255 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB82_256;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_256) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_256 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_256;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_256) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_256 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i15_i_i_340 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB83_257;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_257) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB82_256 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i15_i_i_340 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB84_260;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_260) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_257 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB83_257;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_257) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_257 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB83_258;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_258) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_258 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB83_258;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_258) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_258 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB83_259;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_259) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_259 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB83_259;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB83_259) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB83_259 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB84_260;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_260) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_260 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB84_260;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_260) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_260 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB84_261;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_261) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_261 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB84_261;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_261) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_261 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB84_262;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_262) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_262 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB84_262;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB84_262) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_262 & memory_controller_waitrequest == 1'd0 & main_344_347 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB85_263;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_263) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB84_262 & memory_controller_waitrequest == 1'd0 & main_344_347 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB86_266;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB86_266) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_263 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB85_263;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_263) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_263 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB85_264;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_264) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_264 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB85_264;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_264) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_264 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB85_265;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_265) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_265 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB85_265;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB85_265) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB85_265 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB86_266;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB86_266) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB86_266;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB86_266) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB87_267;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_267) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_271;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_271) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_267 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB87_267;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_267) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_267 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB87_268;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_268) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_268 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB87_268;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_268) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_268 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB87_269;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_269) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_269 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB87_269;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_269) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_269 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB87_270;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_270) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB87_270;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_270) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd0 & main__split_us_i_i_i_exitcond_i17_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB89_276;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB89_276) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd0 & main__split_us_i_i_i_exitcond_i17_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB87_267;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB87_267) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_271 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB88_271;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_271) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_271 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_272;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_272) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_272 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB88_272;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_272) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_272 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_273;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_273) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_273 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB88_273;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_273) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_273 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_274;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_274) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_274 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB88_274;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_274) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_274 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_275;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_275) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB88_275;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_275) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd0 & main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB89_276;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB89_276) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd0 & main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB88_271;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB88_271) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB89_276;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB89_276) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB82_251;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB82_251) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB4_7;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB4_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_277 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_277;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_277) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_277 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_278;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_278) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_278 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_278;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_278) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_278 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_279;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_279) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_279 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_279;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_279) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_279 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_280;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_280) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_280 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_280;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_280) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_280 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_281;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_281) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_281 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_281;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_281) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_281 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_282;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_282) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_282 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_282;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_282) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_282 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_283;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_283) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_283 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_283;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_283) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_283 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_284;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_284) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_284 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_284;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_284) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_284 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_285;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_285) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_285 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_285;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_285) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_285 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_286;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_286) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_286 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_286;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_286) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_286 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_287;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_287) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_287 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_287;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_287) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_287 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_288;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_288) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_288 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_288;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_288) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_288 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_289;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_289) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_289 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_289;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_289) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_289 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_290;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_290) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_290 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_290;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_290) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_290 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_291;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_291) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_291 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_291;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_291) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_291 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_292;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_292) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_292 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_292;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_292) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_292 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_293;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_293) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_293 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_293;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_293) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_293 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_294;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_294) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_294 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_294;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_294) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_294 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_295;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_295) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_295 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_295;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_295) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_295 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_296;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_296) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_296 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_296;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_296) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_296 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_297;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_297) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_297 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_297;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_297) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_297 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_298;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_298) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_298 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_298;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_298) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_298 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_299;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_299) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_299 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_299;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_299) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_299 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_300;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_300) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_300 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_300;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_300) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_300 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_301;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_301) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_301 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_301;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_301) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_301 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_302;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_302) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_302 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_302;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_302) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_302 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_303;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_303) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_303 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_303;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_303) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_303 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_304;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_304) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_304 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_304;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_304) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_304 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_305;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_305) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_305 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_305;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_305) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_305 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_306;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_306) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_306 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_306;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_306) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_306 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_307;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_307) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_307 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_307;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_307) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_307 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_308;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_308) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_308 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_308;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_308) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_308 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_309;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_309) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_309 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_309;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_309) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_309 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_310;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_310) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_310 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_310;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_310) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_310 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_311;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_311) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_311 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_311;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_311) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_311 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_312;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_312) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_312 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_312;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_312) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_312 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_313;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_313) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_313 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_313;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_313) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_313 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_314;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_314) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_314 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_314;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_314) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_314 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_315;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_315) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_315 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_315;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_315) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_315 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_316;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_316) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_316 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_316;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_316) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_316 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_317;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_317) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_317 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_317;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_317) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_317 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_318;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_318) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_318 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_318;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_318) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_318 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_319;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_319) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_319 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_319;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_319) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_319 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_320;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_320) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_320 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_320;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_320) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_320 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_321;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_321) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_321 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_321;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_321) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_321 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_322;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_322) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_322 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_322;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_322) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_322 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_323;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_323) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_323 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_323;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_323) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_323 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_324;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_324) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_324 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_324;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_324) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_324 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_325;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_325) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_325 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_325;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_325) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_325 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_326;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_326) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_326 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_326;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_326) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_326 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_327;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_327) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_327 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_327;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_327) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_327 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_328;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_328) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_328 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_328;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_328) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_328 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_329;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_329) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_329 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_329;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_329) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_329 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_330;
if (^reset !== 1'bX && ^(LEGUP_function_call_330) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_330 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_330;
if (^reset !== 1'bX && ^(LEGUP_function_call_330) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_330 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_331;
if (^reset !== 1'bX && ^(LEGUP_function_call_331) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_330 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_330;
if (^reset !== 1'bX && ^(LEGUP_function_call_330) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_331 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_331;
if (^reset !== 1'bX && ^(LEGUP_function_call_331) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_331 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_332;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_332) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_332 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_332;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_332) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_332 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_333;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_333) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_333 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_333;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_333) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_333 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_334;
if (^reset !== 1'bX && ^(LEGUP_function_call_334) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_334 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_334;
if (^reset !== 1'bX && ^(LEGUP_function_call_334) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_334 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_335;
if (^reset !== 1'bX && ^(LEGUP_function_call_335) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_334 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_334;
if (^reset !== 1'bX && ^(LEGUP_function_call_334) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_335 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_335;
if (^reset !== 1'bX && ^(LEGUP_function_call_335) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_335 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_336;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_336) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_336 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_336;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_336) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_336 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_337;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_337) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_337 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_337;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_337) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_337 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_338;
if (^reset !== 1'bX && ^(LEGUP_function_call_338) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_338 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_338;
if (^reset !== 1'bX && ^(LEGUP_function_call_338) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_338 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_339;
if (^reset !== 1'bX && ^(LEGUP_function_call_339) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_338 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_338;
if (^reset !== 1'bX && ^(LEGUP_function_call_338) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_339 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_339;
if (^reset !== 1'bX && ^(LEGUP_function_call_339) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_339 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_340;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_340) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_340 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_340;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_340) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_340 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_341;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_341) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_341 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_341;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_341) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_341 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_342;
if (^reset !== 1'bX && ^(LEGUP_function_call_342) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_342 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_342;
if (^reset !== 1'bX && ^(LEGUP_function_call_342) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_342 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_343;
if (^reset !== 1'bX && ^(LEGUP_function_call_343) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_342 & memory_controller_waitrequest == 1'd0 & huff_make_dhuff_tb_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_342;
if (^reset !== 1'bX && ^(LEGUP_function_call_342) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_343 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_343;
if (^reset !== 1'bX && ^(LEGUP_function_call_343) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_343 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_344;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_344) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_344 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_344;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_344) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_344 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_345;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_345) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_345 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_345;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_345) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_345 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_346;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_346) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_346 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_346;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_346) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_346 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_347;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_347) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_347 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_347;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_347) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_347 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_348;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_348) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_348 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_348;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_348) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_348 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_349;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_349) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_349 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_349;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_349) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_349 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_350;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_350 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_350;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_350) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_350 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_351;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_351) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_351 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_351;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_351) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_351 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_352;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_352) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_352 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_352;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_352) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_352 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_353;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_353) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_353 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_353;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_353) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_353 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB90_354;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_354) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_354 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB90_354;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB90_354) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_354 & memory_controller_waitrequest == 1'd0 & main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB114_406;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB114_406) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB90_354 & memory_controller_waitrequest == 1'd0 & main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB91_355;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB91_355) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB91_355 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB91_355;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB91_355) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB91_355 & memory_controller_waitrequest == 1'd0 & main_389_391 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB92_356;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB92_356) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB91_355 & memory_controller_waitrequest == 1'd0 & main_389_391 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_454;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_454) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB92_356 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB92_356;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB92_356) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB92_356 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB93_357;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_357) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_357 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB93_357;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_357) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_357 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_358;
if (^reset !== 1'bX && ^(LEGUP_function_call_358) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_358 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_358;
if (^reset !== 1'bX && ^(LEGUP_function_call_358) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_358 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_359;
if (^reset !== 1'bX && ^(LEGUP_function_call_359) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_358 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_358;
if (^reset !== 1'bX && ^(LEGUP_function_call_358) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_359 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_359;
if (^reset !== 1'bX && ^(LEGUP_function_call_359) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_359 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB93_360;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_360) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_360 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB93_360;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_360) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_360 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_361;
if (^reset !== 1'bX && ^(LEGUP_function_call_361) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_361 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_361;
if (^reset !== 1'bX && ^(LEGUP_function_call_361) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_361 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_362;
if (^reset !== 1'bX && ^(LEGUP_function_call_362) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_361 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_361;
if (^reset !== 1'bX && ^(LEGUP_function_call_361) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_362 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_362;
if (^reset !== 1'bX && ^(LEGUP_function_call_362) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_362 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB93_363;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_363) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_363 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB93_363;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_363) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB93_363 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_364;
if (^reset !== 1'bX && ^(LEGUP_function_call_364) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_364 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_364;
if (^reset !== 1'bX && ^(LEGUP_function_call_364) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_364 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_365;
if (^reset !== 1'bX && ^(LEGUP_function_call_365) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_364 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_364;
if (^reset !== 1'bX && ^(LEGUP_function_call_364) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_365 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_365;
if (^reset !== 1'bX && ^(LEGUP_function_call_365) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_365 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_366;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_366) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_366 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_366;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_366) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_366 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_367;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_367) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_367 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_367;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_367) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_367 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_368;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_368) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_368 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_368;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_368) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_368 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_369;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_369) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_369 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_369;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_369) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_369 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_370;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_370) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_370 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_370;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_370) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_370 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_371;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_371) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_371 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB94_371;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_371) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_371 & memory_controller_waitrequest == 1'd0 & main_392_411 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB97_374;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB97_374) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB94_371 & memory_controller_waitrequest == 1'd0 & main_392_411 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB95_372;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB95_372) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB95_372 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB95_372;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB95_372) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB95_372 & memory_controller_waitrequest == 1'd0 & main_412_413 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB96_373;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB96_373) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB95_372 & memory_controller_waitrequest == 1'd0 & main_412_413 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB97_374;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB97_374) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB96_373 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB96_373;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB96_373) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB96_373 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB97_374;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB97_374) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB97_374 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB97_374;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB97_374) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB97_374 & memory_controller_waitrequest == 1'd0 & main_415_416 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB100_377;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB100_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB97_374 & memory_controller_waitrequest == 1'd0 & main_415_416 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB98_375;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB98_375) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB98_375 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB98_375;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB98_375) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB98_375 & memory_controller_waitrequest == 1'd0 & main_417_418 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB99_376;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB99_376) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB98_375 & memory_controller_waitrequest == 1'd0 & main_417_418 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB100_377;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB100_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB99_376 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB99_376;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB99_376) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB99_376 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB100_377;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB100_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB100_377 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB100_377;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB100_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB100_377 & memory_controller_waitrequest == 1'd0 & main_420_421 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB103_380;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_380) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB100_377 & memory_controller_waitrequest == 1'd0 & main_420_421 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB101_378;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB101_378) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB101_378 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB101_378;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB101_378) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB101_378 & memory_controller_waitrequest == 1'd0 & main_422_423 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB102_379;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB102_379) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB101_378 & memory_controller_waitrequest == 1'd0 & main_422_423 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB103_380;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_380) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB102_379 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB102_379;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB102_379) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB102_379 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB103_380;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_380) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_380 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB103_380;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_380) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_380 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB103_381;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_381) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_381 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB103_381;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_381) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_381 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB103_382;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_382) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_382 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB103_382;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB103_382) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_382 & memory_controller_waitrequest == 1'd0 & main_425_exitcond53_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_383;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_383) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB103_382 & memory_controller_waitrequest == 1'd0 & main_425_exitcond53_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB94_366;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB94_366) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_383 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_383;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_383) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_383 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB104_384;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_384) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_384 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_384;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_384) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_384 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB104_385;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_385) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_385 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_385;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_385) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_385 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB104_386;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_386) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_386 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_386;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_386) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_386 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB104_387;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_387) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_387 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_387;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_387) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_387 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB104_388;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_388) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_388 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB104_388;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB104_388) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB104_388 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB105_389;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_389) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_389 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB105_389;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_389) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_389 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB105_390;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_390) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_390 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB105_390;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_390) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_390 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB105_391;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_391) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_391 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB105_391;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_391) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_391 & memory_controller_waitrequest == 1'd0 & main_432_or_cond_i_i_i_i == 1'd1)
begin
cur_state <= LEGUP_F_main_BB106_392;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_392) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB105_391 & memory_controller_waitrequest == 1'd0 & main_432_or_cond_i_i_i_i == 1'd0)
begin
cur_state <= LEGUP_F_main_BB110_400;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_400) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_392 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB106_392;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_392) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_392 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB106_393;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_393) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_393 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB106_393;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_393) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_393 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB106_394;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_394) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_394 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB106_394;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB106_394) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB106_394 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB109_399;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB109_399) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB107_395 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB107_395;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB107_395) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB107_395 & memory_controller_waitrequest == 1'd0 & main_439_exitcond93_i_i == 1'd1)
begin
cur_state <= LEGUP_F_main_BB110_400;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_400) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB107_395 & memory_controller_waitrequest == 1'd0 & main_439_exitcond93_i_i == 1'd0)
begin
cur_state <= LEGUP_F_main_BB109_399;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB109_399) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_396 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB108_396;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_396) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_396 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB108_397;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_397) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_397 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB108_397;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_397) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_397 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB108_398;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_398) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_398 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB108_398;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_398) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_398 & memory_controller_waitrequest == 1'd0 & main_440_exitcond70_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB107_395;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB107_395) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB108_398 & memory_controller_waitrequest == 1'd0 & main_440_exitcond70_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB108_396;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_396) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB109_399 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB109_399;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB109_399) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB109_399 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB108_396;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB108_396) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_400 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB110_400;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_400) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_400 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB110_401;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_401) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_401 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB110_401;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_401) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_401 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB110_402;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_402) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_402 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB110_402;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB110_402) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_402 & memory_controller_waitrequest == 1'd0 & main_WriteOneBlock_exit_i_i_i_444 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB112_404;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB112_404) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB110_402 & memory_controller_waitrequest == 1'd0 & main_WriteOneBlock_exit_i_i_i_444 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB111_403;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB111_403) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB111_403 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB111_403;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB111_403) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB111_403 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB112_404;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB112_404) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB112_404 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB112_404;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB112_404) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB112_404 & memory_controller_waitrequest == 1'd0 & main_WriteBlock_exit_i_i_exitcond116_i_i == 1'd1)
begin
cur_state <= LEGUP_F_main_BB113_405;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB113_405) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB112_404 & memory_controller_waitrequest == 1'd0 & main_WriteBlock_exit_i_i_exitcond116_i_i == 1'd0)
begin
cur_state <= LEGUP_F_main_BB105_389;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB105_389) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB113_405 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB113_405;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB113_405) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB113_405 & memory_controller_waitrequest == 1'd0 & main_447_448 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB93_357;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB93_357) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB113_405 & memory_controller_waitrequest == 1'd0 & main_447_448 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_454;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_454) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB114_406 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB114_406;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB114_406) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB114_406 & memory_controller_waitrequest == 1'd0 & main_449_451 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB115_407;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB115_407) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB114_406 & memory_controller_waitrequest == 1'd0 & main_449_451 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_454;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_454) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB115_407 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB115_407;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB115_407) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB115_407 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_408;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_408) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_408 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_408;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_408) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_408 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_409;
if (^reset !== 1'bX && ^(LEGUP_function_call_409) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_409 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_409;
if (^reset !== 1'bX && ^(LEGUP_function_call_409) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_409 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_410;
if (^reset !== 1'bX && ^(LEGUP_function_call_410) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_409 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_409;
if (^reset !== 1'bX && ^(LEGUP_function_call_409) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_410 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_410;
if (^reset !== 1'bX && ^(LEGUP_function_call_410) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_410 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_411;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_411) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_411 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_411;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_411) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_411 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_412;
if (^reset !== 1'bX && ^(LEGUP_function_call_412) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_412 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_412;
if (^reset !== 1'bX && ^(LEGUP_function_call_412) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_412 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_413;
if (^reset !== 1'bX && ^(LEGUP_function_call_413) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_412 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_412;
if (^reset !== 1'bX && ^(LEGUP_function_call_412) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_413 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_413;
if (^reset !== 1'bX && ^(LEGUP_function_call_413) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_413 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_414;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_414) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_414 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_414;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_414) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_414 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_415;
if (^reset !== 1'bX && ^(LEGUP_function_call_415) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_415 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_415;
if (^reset !== 1'bX && ^(LEGUP_function_call_415) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_415 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_416;
if (^reset !== 1'bX && ^(LEGUP_function_call_416) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_415 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_415;
if (^reset !== 1'bX && ^(LEGUP_function_call_415) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_416 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_416;
if (^reset !== 1'bX && ^(LEGUP_function_call_416) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_416 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_417;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_417) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_417 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_417;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_417) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_417 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_418;
if (^reset !== 1'bX && ^(LEGUP_function_call_418) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_418 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_418;
if (^reset !== 1'bX && ^(LEGUP_function_call_418) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_418 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_419;
if (^reset !== 1'bX && ^(LEGUP_function_call_419) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_418 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_418;
if (^reset !== 1'bX && ^(LEGUP_function_call_418) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_419 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_419;
if (^reset !== 1'bX && ^(LEGUP_function_call_419) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_419 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_420;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_420) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_420 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_420;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_420) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_420 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_421;
if (^reset !== 1'bX && ^(LEGUP_function_call_421) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_421 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_421;
if (^reset !== 1'bX && ^(LEGUP_function_call_421) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_421 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_422;
if (^reset !== 1'bX && ^(LEGUP_function_call_422) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_421 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_421;
if (^reset !== 1'bX && ^(LEGUP_function_call_421) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_422 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_422;
if (^reset !== 1'bX && ^(LEGUP_function_call_422) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_422 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB116_423;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_423) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_423 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_423;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_423) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB116_423 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_424;
if (^reset !== 1'bX && ^(LEGUP_function_call_424) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_424 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_424;
if (^reset !== 1'bX && ^(LEGUP_function_call_424) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_424 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_425;
if (^reset !== 1'bX && ^(LEGUP_function_call_425) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_424 & memory_controller_waitrequest == 1'd0 & decode_block_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_424;
if (^reset !== 1'bX && ^(LEGUP_function_call_424) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_425 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_425;
if (^reset !== 1'bX && ^(LEGUP_function_call_425) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_425 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB117_426;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB117_426) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB117_426 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB117_426;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB117_426) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB117_426 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_427;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_427) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_427 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_427;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_427) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_427 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_428;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_428) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_428 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_428;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_428) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_428 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_429;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_429) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_429 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_429;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_429) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_429 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_430;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_430) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_430 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_430;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_430) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_430 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_431;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_431) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_431 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_431;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_431) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_431 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_432;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_432) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_432 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB118_432;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_432) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_432 & memory_controller_waitrequest == 1'd0 & main_454_473 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB121_435;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB121_435) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB118_432 & memory_controller_waitrequest == 1'd0 & main_454_473 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB119_433;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB119_433) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB119_433 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB119_433;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB119_433) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB119_433 & memory_controller_waitrequest == 1'd0 & main_474_475 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB120_434;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB120_434) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB119_433 & memory_controller_waitrequest == 1'd0 & main_474_475 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB121_435;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB121_435) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB120_434 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB120_434;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB120_434) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB120_434 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB121_435;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB121_435) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB121_435 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB121_435;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB121_435) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB121_435 & memory_controller_waitrequest == 1'd0 & main_477_478 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB124_438;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB124_438) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB121_435 & memory_controller_waitrequest == 1'd0 & main_477_478 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB122_436;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB122_436) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB122_436 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB122_436;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB122_436) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB122_436 & memory_controller_waitrequest == 1'd0 & main_479_480 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB123_437;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB123_437) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB122_436 & memory_controller_waitrequest == 1'd0 & main_479_480 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB124_438;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB124_438) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB123_437 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB123_437;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB123_437) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB123_437 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB124_438;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB124_438) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB124_438 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB124_438;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB124_438) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB124_438 & memory_controller_waitrequest == 1'd0 & main_482_483 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB127_441;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_441) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB124_438 & memory_controller_waitrequest == 1'd0 & main_482_483 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB125_439;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB125_439) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB125_439 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB125_439;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB125_439) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB125_439 & memory_controller_waitrequest == 1'd0 & main_484_485 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB126_440;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB126_440) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB125_439 & memory_controller_waitrequest == 1'd0 & main_484_485 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB127_441;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_441) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB126_440 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB126_440;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB126_440) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB126_440 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB127_441;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_441) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_441 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB127_441;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_441) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_441 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB127_442;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_442) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_442 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB127_442;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_442) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_442 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB127_443;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_443) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_443 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB127_443;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB127_443) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_443 & memory_controller_waitrequest == 1'd0 & main_487_exitcond_i_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB128_444;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB128_444) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB127_443 & memory_controller_waitrequest == 1'd0 & main_487_exitcond_i_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB118_427;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB118_427) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB128_444 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB128_444;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB128_444) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB128_444 & memory_controller_waitrequest == 1'd0 & main_YuvToRgb_exit13_i_i_exitcond35_i_i == 1'd1)
begin
cur_state <= LEGUP_F_main_BB129_445;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_445) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB128_444 & memory_controller_waitrequest == 1'd0 & main_YuvToRgb_exit13_i_i_exitcond35_i_i == 1'd0)
begin
cur_state <= LEGUP_F_main_BB117_426;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB117_426) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_445 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB129_445;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_445) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_445 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_446;
if (^reset !== 1'bX && ^(LEGUP_function_call_446) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_446 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_446;
if (^reset !== 1'bX && ^(LEGUP_function_call_446) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_446 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_447;
if (^reset !== 1'bX && ^(LEGUP_function_call_447) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_446 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_446;
if (^reset !== 1'bX && ^(LEGUP_function_call_446) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_447 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_447;
if (^reset !== 1'bX && ^(LEGUP_function_call_447) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_447 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB129_448;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_448) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_448 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB129_448;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_448) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_448 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_449;
if (^reset !== 1'bX && ^(LEGUP_function_call_449) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_449 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_449;
if (^reset !== 1'bX && ^(LEGUP_function_call_449) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_449 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_450;
if (^reset !== 1'bX && ^(LEGUP_function_call_450) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_449 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_449;
if (^reset !== 1'bX && ^(LEGUP_function_call_449) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_450 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_450;
if (^reset !== 1'bX && ^(LEGUP_function_call_450) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_450 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB129_451;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_451) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_451 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB129_451;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB129_451) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB129_451 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_function_call_452;
if (^reset !== 1'bX && ^(LEGUP_function_call_452) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_452 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_452;
if (^reset !== 1'bX && ^(LEGUP_function_call_452) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_452 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd1)
begin
cur_state <= LEGUP_function_call_453;
if (^reset !== 1'bX && ^(LEGUP_function_call_453) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_452 & memory_controller_waitrequest == 1'd0 & Write4Blocks_finish == 1'd0)
begin
cur_state <= LEGUP_function_call_452;
if (^reset !== 1'bX && ^(LEGUP_function_call_452) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_453 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_function_call_453;
if (^reset !== 1'bX && ^(LEGUP_function_call_453) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_453 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_490_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB116_408;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB116_408) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_function_call_453 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_490_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_454;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_454) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_454 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB130_454;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_454) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_454 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_455;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_455) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_455 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB130_455;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_455) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_455 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB130_456;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_456) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_456 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB130_456;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB130_456) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB130_456 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB131_457;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_457) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_457 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB131_457;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_457) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_457 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB131_458;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_458) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_458 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB131_458;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_458) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_458 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB131_459;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_459) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_459 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB131_459;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_459) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_459 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB131_460;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_460) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB131_460;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_460) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB132_461;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_461) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB131_457;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB131_457) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_461 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB132_461;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_461) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_461 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB132_462;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_462) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_462 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB132_462;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_462) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_462 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB132_463;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_463) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_463 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB132_463;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_463) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_463 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB132_464;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_464) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB132_464;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_464) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB134_469;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_469) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB132_461;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB132_461) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_465 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB133_465;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_465) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_465 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB133_466;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_466) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_466 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB133_466;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_466) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_466 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB133_467;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_467) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_467 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB133_467;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_467) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_467 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB133_468;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_468) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_468 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB133_468;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_468) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_468 & memory_controller_waitrequest == 1'd0 & main_jpeg2bmp_main_exit_512 == 1'd1)
begin
cur_state <= LEGUP_F_main_BB135_473;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB135_473) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB133_468 & memory_controller_waitrequest == 1'd0 & main_jpeg2bmp_main_exit_512 == 1'd0)
begin
cur_state <= LEGUP_F_main_BB136_474;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB136_474) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_469 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB134_469;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_469) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_469 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB134_470;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_470) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_470 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB134_470;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_470) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_470 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB134_471;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_471) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_471 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB134_471;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_471) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_471 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB134_472;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_472) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_472 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB134_472;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_472) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_472 & memory_controller_waitrequest == 1'd0 & main__preheader_2_i_exitcond_2_i_reg == 1'd1)
begin
cur_state <= LEGUP_F_main_BB133_465;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB133_465) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB134_472 & memory_controller_waitrequest == 1'd0 & main__preheader_2_i_exitcond_2_i_reg == 1'd0)
begin
cur_state <= LEGUP_F_main_BB134_469;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB134_469) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB135_473 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB135_473;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB135_473) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB135_473 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB137_475;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_475) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB136_474 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB136_474;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB136_474) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB136_474 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB137_475;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_475) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_475 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB137_475;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_475) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_475 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB137_476;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_476) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_476 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB137_476;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_476) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_476 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_F_main_BB137_477;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_477) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_477 & memory_controller_waitrequest == 1'd1)
begin
cur_state <= LEGUP_F_main_BB137_477;
if (^reset !== 1'bX && ^(LEGUP_F_main_BB137_477) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
if (cur_state == LEGUP_F_main_BB137_477 & memory_controller_waitrequest == 1'd0)
begin
cur_state <= LEGUP_0;
if (^reset !== 1'bX && ^(LEGUP_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to cur_state"); $finish; end
end
end
always @(*) begin
/* main: %1*/
/* %i.05.i = phi i32 [ 0, %0 ], [ %3, %1 ]*/
begin
main_1_i_05_i = main_1_i_05_i_phi_temp;
end
end
always @(*) begin
/* main: %1*/
/* %c.06.i = getelementptr [5310 x i8]* @JpegFileBuf, i32 0, i32 %i.05.i*/
begin
main_1_c_06_i = `TAG_g_JpegFileBuf_a + 1 * main_1_i_05_i;
end
end
always @(posedge clk) begin
/* main: %1*/
/* %c.06.i = getelementptr [5310 x i8]* @JpegFileBuf, i32 0, i32 %i.05.i*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
main_1_c_06_i_reg <= main_1_c_06_i;
if (^reset !== 1'bX && ^(main_1_c_06_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_c_06_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %1*/
/* %scevgep13.i = getelementptr [5207 x i8]* @hana_jpg, i32 0, i32 %i.05.i*/
begin
main_1_scevgep13_i = `TAG_g_hana_jpg_a + 1 * main_1_i_05_i;
end
end
always @(*) begin
/* main: %1*/
/* %2 = load i8* %scevgep13.i, align 1, !tbaa !1*/
begin
main_1_2 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %1*/
/* %3 = add nsw i32 %i.05.i, 1*/
begin
main_1_3 = main_1_i_05_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %1*/
/* %3 = add nsw i32 %i.05.i, 1*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
main_1_3_reg <= main_1_3;
if (^reset !== 1'bX && ^(main_1_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_3_reg"); $finish; end
end
end
always @(*) begin
/* main: %1*/
/* %exitcond11.i = icmp eq i32 %3, 5207*/
begin
main_1_exitcond11_i = main_1_3 == 32'd5207;
end
end
always @(posedge clk) begin
/* main: %1*/
/* %exitcond11.i = icmp eq i32 %3, 5207*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
main_1_exitcond11_i_reg <= main_1_exitcond11_i;
if (^reset !== 1'bX && ^(main_1_exitcond11_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_exitcond11_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %i_marker.0 = phi i32 [ 0, %1 ], [ %24, %31 ]*/
begin
main__outer_i_i_i_marker_0 = main__outer_i_i_i_marker_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %i_get_dht.0 = phi i32 [ 0, %1 ], [ %i_get_dht.1.ph, %31 ]*/
begin
main__outer_i_i_i_get_dht_0 = main__outer_i_i_i_get_dht_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %i_get_dqt.0 = phi i32 [ 0, %1 ], [ %i_get_dqt.1.ph6, %31 ]*/
begin
main__outer_i_i_i_get_dqt_0 = main__outer_i_i_i_get_dqt_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %ReadBuf.0 = phi i8* [ getelementptr inbounds ([5310 x i8]* @JpegFileBuf, i32 0, i32 0), %1 ], [ %ReadBuf.2, %31 ]*/
begin
main__outer_i_i_ReadBuf_0 = main__outer_i_i_ReadBuf_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %p_jinfo_num_components.0 = phi i8 [ 0, %1 ], [ %p_jinfo_num_components.1.ph13, %31 ]*/
begin
main__outer_i_i_p_jinfo_num_components_0 = main__outer_i_i_p_jinfo_num_components_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %p_jinfo_smp_fact.b.0 = phi i1 [ false, %1 ], [ %p_jinfo_smp_fact.b.1.ph14, %31 ]*/
begin
main__outer_i_i_p_jinfo_smp_fact_b_0 = main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp;
end
end
always @(*) begin
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i = main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp;
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
else if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i = main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp;
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
else /* if (cur_state == LEGUP_F_main_BB2_5) */
begin
main__outer_i_i_sow_SOI_0_ph_i_i = main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_reg <= main__outer_i_i_sow_SOI_0_ph_i_i;
if (^reset !== 1'bX && ^(main__outer_i_i_sow_SOI_0_ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_reg"); $finish; end
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_reg <= main__outer_i_i_sow_SOI_0_ph_i_i;
if (^reset !== 1'bX && ^(main__outer_i_i_sow_SOI_0_ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_reg"); $finish; end
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_reg <= main__outer_i_i_sow_SOI_0_ph_i_i;
if (^reset !== 1'bX && ^(main__outer_i_i_sow_SOI_0_ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_reg"); $finish; end
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB2_5)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_reg <= main__outer_i_i_sow_SOI_0_ph_i_i;
if (^reset !== 1'bX && ^(main__outer_i_i_sow_SOI_0_ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %i_marker.1.ph = phi i32 [ %i_marker.0, %.outer.i.i ], [ %24, %._crit_edge.i12.i.i ]*/
begin
main__backedge_i_i_outer_i_marker_1_ph = main__backedge_i_i_outer_i_marker_1_ph_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph = main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp;
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
else if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph = main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp;
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB3_6) */
begin
main__backedge_i_i_outer_i_get_dht_1_ph = main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_reg <= main__backedge_i_i_outer_i_get_dht_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_reg"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_reg <= main__backedge_i_i_outer_i_get_dht_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_reg"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_reg <= main__backedge_i_i_outer_i_get_dht_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_reg"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_reg <= main__backedge_i_i_outer_i_get_dht_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %i_get_dqt.1.ph = phi i32 [ %i_get_dqt.0, %.outer.i.i ], [ %i_get_dqt.1.ph6, %._crit_edge.i12.i.i ]*/
begin
main__backedge_i_i_outer_i_get_dqt_1_ph = main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %ReadBuf.1.ph = phi i8* [ %ReadBuf.0, %.outer.i.i ], [ %ReadBuf.7, %._crit_edge.i12.i.i ]*/
begin
main__backedge_i_i_outer_ReadBuf_1_ph = main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_num_components.1.ph = phi i8 [ %p_jinfo_num_components.0, %.outer.i.i ], [ %p_jinfo_num_components.1.ph13, %._crit_edge.i12.i.i ]*/
begin
main__backedge_i_i_outer_p_jinfo_num_components_1_ph = main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_smp_fact.b.1.ph = phi i1 [ %p_jinfo_smp_fact.b.0, %.outer.i.i ], [ %p_jinfo_smp_fact.b.1.ph14, %._crit_edge.i12.i.i ]*/
begin
main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph = main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer*/
/* %4 = getelementptr inbounds [4 x i32]* @out_length_get_dht, i32 0, i32 %i_get_dht.1.ph*/
begin
main__backedge_i_i_outer_4 = `TAG_g_out_length_get_dht_a + 4 * main__backedge_i_i_outer_i_get_dht_1_ph;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %4 = getelementptr inbounds [4 x i32]* @out_length_get_dht, i32 0, i32 %i_get_dht.1.ph*/
if (cur_state == LEGUP_F_main_BB3_6)
begin
main__backedge_i_i_outer_4_reg <= main__backedge_i_i_outer_4;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_4_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %i_marker.1.ph5 = phi i32 [ %i_marker.1.ph, %.backedge.i.i.outer ], [ %24, %.us-lcssa.us.i.i.i ]*/
begin
main__backedge_i_i_outer4_i_marker_1_ph5 = main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6 = main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp;
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
else if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6 = main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp;
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
else if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6 = main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp;
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB4_7) */
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6 = main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg <= main__backedge_i_i_outer4_i_get_dqt_1_ph6;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg <= main__backedge_i_i_outer4_i_get_dqt_1_ph6;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg <= main__backedge_i_i_outer4_i_get_dqt_1_ph6;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg <= main__backedge_i_i_outer4_i_get_dqt_1_ph6;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg <= main__backedge_i_i_outer4_i_get_dqt_1_ph6;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %ReadBuf.1.ph7 = phi i8* [ %ReadBuf.1.ph, %.backedge.i.i.outer ], [ %ReadBuf.8, %.us-lcssa.us.i.i.i ]*/
begin
main__backedge_i_i_outer4_ReadBuf_1_ph7 = main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_num_components.1.ph8 = phi i8 [ %p_jinfo_num_components.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_num_components.1.ph13, %.us-lcssa.us.i.i.i ]*/
begin
main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8 = main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_smp_fact.b.1.ph9 = phi i1 [ %p_jinfo_smp_fact.b.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_smp_fact.b.1.ph14, %.us-lcssa.us.i.i.i ]*/
begin
main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9 = main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer4*/
/* %5 = getelementptr inbounds [2 x i32]* @out_length_get_dqt, i32 0, i32 %i_get_dqt.1.ph6*/
begin
main__backedge_i_i_outer4_5 = `TAG_g_out_length_get_dqt_a + 4 * main__backedge_i_i_outer4_i_get_dqt_1_ph6;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %5 = getelementptr inbounds [2 x i32]* @out_length_get_dqt, i32 0, i32 %i_get_dqt.1.ph6*/
if (cur_state == LEGUP_F_main_BB4_7)
begin
main__backedge_i_i_outer4_5_reg <= main__backedge_i_i_outer4_5;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_5_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer10*/
/* %i_marker.1.ph11 = phi i32 [ %i_marker.1.ph5, %.backedge.i.i.outer4 ], [ %24, %163 ], [ %24, %165 ]*/
begin
main__backedge_i_i_outer10_i_marker_1_ph11 = main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer10*/
/* %ReadBuf.1.ph12 = phi i8* [ %ReadBuf.1.ph7, %.backedge.i.i.outer4 ], [ %ReadBuf.4, %163 ], [ %ReadBuf.4, %165 ]*/
begin
main__backedge_i_i_outer10_ReadBuf_1_ph12 = main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp;
end
end
always @(*) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13 = main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13 = main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13 = main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13 = main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
else /* if (cur_state == LEGUP_F_main_BB5_8) */
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13 = main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
else if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
else /* if (cur_state == LEGUP_F_main_BB5_8) */
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14 = main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB5_8)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1 = main__backedge_i_i_i_marker_1_phi_temp;
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1 = main__backedge_i_i_i_marker_1_phi_temp;
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB6_9) */
begin
main__backedge_i_i_i_marker_1 = main__backedge_i_i_i_marker_1_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1_reg <= main__backedge_i_i_i_marker_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_i_marker_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1_reg <= main__backedge_i_i_i_marker_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_i_marker_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1_reg <= main__backedge_i_i_i_marker_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_i_marker_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_i_marker_1_reg <= main__backedge_i_i_i_marker_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_i_marker_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_reg"); $finish; end
end
end
always @(*) begin
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1 = main__backedge_i_i_ReadBuf_1_phi_temp;
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1 = main__backedge_i_i_ReadBuf_1_phi_temp;
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1 = main__backedge_i_i_ReadBuf_1_phi_temp;
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB6_9) */
begin
main__backedge_i_i_ReadBuf_1 = main__backedge_i_i_ReadBuf_1_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1_reg <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1_reg <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1_reg <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1_reg <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_reg"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9)
begin
main__backedge_i_i_ReadBuf_1_reg <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_reg"); $finish; end
end
end
always @(*) begin
/* main: %6*/
/* %7 = getelementptr inbounds i8* %ReadBuf.1, i32 1*/
begin
main_6_7 = main__backedge_i_i_ReadBuf_1_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %6*/
/* %7 = getelementptr inbounds i8* %ReadBuf.1, i32 1*/
if (cur_state == LEGUP_F_main_BB7_10)
begin
main_6_7_reg <= main_6_7;
if (^reset !== 1'bX && ^(main_6_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_7_reg"); $finish; end
end
end
always @(*) begin
/* main: %6*/
/* %8 = load i8* %ReadBuf.1, align 1, !tbaa !1*/
begin
main_6_8 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
begin
main_6_9 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_13)
begin
main_6_9_reg <= main_6_9;
if (^reset !== 1'bX && ^(main_6_9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_9_reg"); $finish; end
end
end
always @(*) begin
/* main: %6*/
/* %10 = icmp eq i8 %8, -1*/
begin
main_6_10 = main_6_8 == -8'd1;
end
end
always @(posedge clk) begin
/* main: %6*/
/* %10 = icmp eq i8 %8, -1*/
if (cur_state == LEGUP_F_main_BB7_12)
begin
main_6_10_reg <= main_6_10;
if (^reset !== 1'bX && ^(main_6_10) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_6_10_reg"); $finish; end
end
end
always @(*) begin
/* main: %6*/
/* %11 = icmp eq i8 %9, -40*/
begin
main_6_11 = main_6_9 == -8'd40;
end
end
always @(*) begin
/* main: %6*/
/* %or.cond.i.i.i = and i1 %10, %11*/
begin
main_6_or_cond_i_i_i = main_6_10_reg & main_6_11;
end
end
always @(*) begin
/* main: %first_marker.exit.i.i*/
/* %14 = getelementptr inbounds i8* %ReadBuf.1, i32 2*/
begin
main_first_marker_exit_i_i_14 = main__backedge_i_i_ReadBuf_1_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %first_marker.exit.i.i*/
/* %14 = getelementptr inbounds i8* %ReadBuf.1, i32 2*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
main_first_marker_exit_i_i_14_reg <= main_first_marker_exit_i_i_14;
if (^reset !== 1'bX && ^(main_first_marker_exit_i_i_14) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_first_marker_exit_i_i_14_reg"); $finish; end
end
end
always @(*) begin
/* main: %first_marker.exit.i.i*/
/* %15 = zext i8 %9 to i32*/
begin
main_first_marker_exit_i_i_15 = main_6_9_reg;
end
end
always @(posedge clk) begin
/* main: %first_marker.exit.i.i*/
/* %15 = zext i8 %9 to i32*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
main_first_marker_exit_i_i_15_reg <= main_first_marker_exit_i_i_15;
if (^reset !== 1'bX && ^(main_first_marker_exit_i_i_15) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_first_marker_exit_i_i_15_reg"); $finish; end
end
end
always @(*) begin
/* main: %first_marker.exit.i.i*/
/* %16 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_first_marker_exit_i_i_16 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %first_marker.exit.i.i*/
/* %17 = add nsw i32 %16, 1*/
begin
main_first_marker_exit_i_i_17 = main_first_marker_exit_i_i_16 + 32'd1;
end
end
always @(*) begin
/* main: %.loopexit3.i.i.i.loopexit*/
/* %scevgep13.i.i.le = getelementptr i8* %.ph.i.i, i32 %tmp12.i.i*/
begin
main__loopexit3_i_i_i_loopexit_scevgep13_i_i_le = main__loopexit_i_preheader_i_i__ph_i_i_reg + 1 * main__loopexit_i_i_i_tmp12_i_i_reg;
end
end
always @(*) begin
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18 = main__loopexit3_i_i_i_18_phi_temp;
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
else if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18 = main__loopexit3_i_i_i_18_phi_temp;
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB11_19) */
begin
main__loopexit3_i_i_i_18 = main__loopexit3_i_i_i_18_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18_reg <= main__loopexit3_i_i_i_18;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_reg"); $finish; end
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18_reg <= main__loopexit3_i_i_i_18;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_reg"); $finish; end
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18_reg <= main__loopexit3_i_i_i_18;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_reg"); $finish; end
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_18_reg <= main__loopexit3_i_i_i_18;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_18) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_reg"); $finish; end
end
end
always @(*) begin
/* main: %.loopexit3.i.i.i*/
/* %storemerge1.i.i.i = getelementptr inbounds i8* %18, i32 1*/
begin
main__loopexit3_i_i_i_storemerge1_i_i_i = main__loopexit3_i_i_i_18 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.loopexit3.i.i.i*/
/* %storemerge1.i.i.i = getelementptr inbounds i8* %18, i32 1*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
main__loopexit3_i_i_i_storemerge1_i_i_i_reg <= main__loopexit3_i_i_i_storemerge1_i_i_i;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_storemerge1_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_storemerge1_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.loopexit3.i.i.i*/
/* %c.0.in2.i.i.i = load i8* %18, align 1*/
begin
main__loopexit3_i_i_i_c_0_in2_i_i_i = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.loopexit3.i.i.i*/
/* %19 = icmp eq i8 %c.0.in2.i.i.i, -1*/
begin
main__loopexit3_i_i_i_19 = main__loopexit3_i_i_i_c_0_in2_i_i_i == -8'd1;
end
end
always @(*) begin
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
main__lr_ph_i_i_i_indvar_i_i = main__lr_ph_i_i_i_indvar_i_i_phi_temp;
end
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB12_22) */
begin
main__lr_ph_i_i_i_indvar_i_i = main__lr_ph_i_i_i_indvar_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
main__lr_ph_i_i_i_indvar_i_i_reg <= main__lr_ph_i_i_i_indvar_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i_i_i_indvar_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_indvar_i_i_reg"); $finish; end
end
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
main__lr_ph_i_i_i_indvar_i_i_reg <= main__lr_ph_i_i_i_indvar_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i_i_i_indvar_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_indvar_i_i_reg"); $finish; end
end
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
main__lr_ph_i_i_i_indvar_i_i_reg <= main__lr_ph_i_i_i_indvar_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i_i_i_indvar_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_indvar_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i.i.i*/
/* %tmp.i.i = add i32 %indvar.i.i, 1*/
begin
main__lr_ph_i_i_i_tmp_i_i = main__lr_ph_i_i_i_indvar_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i.i.i*/
/* %tmp.i.i = add i32 %indvar.i.i, 1*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
main__lr_ph_i_i_i_tmp_i_i_reg <= main__lr_ph_i_i_i_tmp_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i_i_i_tmp_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_tmp_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i.i.i*/
/* %scevgep.i.i = getelementptr i8* %18, i32 %tmp.i.i*/
begin
main__lr_ph_i_i_i_scevgep_i_i = main__loopexit3_i_i_i_18_reg + 1 * main__lr_ph_i_i_i_tmp_i_i;
end
end
always @(*) begin
/* main: %.lr.ph.i.i.i*/
/* %c.0.in.i.i.i = load i8* %scevgep.i.i, align 1*/
begin
main__lr_ph_i_i_i_c_0_in_i_i_i = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i.i.i*/
/* %20 = icmp eq i8 %c.0.in.i.i.i, -1*/
begin
main__lr_ph_i_i_i_20 = main__lr_ph_i_i_i_c_0_in_i_i_i == -8'd1;
end
end
always @(*) begin
/* main: %.loopexit.i.preheader.i.i.loopexit*/
/* %tmp4.i.i = add i32 %indvar.i.i, 2*/
begin
main__loopexit_i_preheader_i_i_loopexit_tmp4_i_i = main__lr_ph_i_i_i_indvar_i_i_reg + 32'd2;
end
end
always @(*) begin
/* main: %.loopexit.i.preheader.i.i.loopexit*/
/* %storemerge.i.i.i = getelementptr i8* %18, i32 %tmp4.i.i*/
begin
main__loopexit_i_preheader_i_i_loopexit_storemerge_i_i_i = main__loopexit3_i_i_i_18_reg + 1 * main__loopexit_i_preheader_i_i_loopexit_tmp4_i_i;
end
end
always @(*) begin
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i = main__loopexit_i_preheader_i_i__ph_i_i_phi_temp;
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i = main__loopexit_i_preheader_i_i__ph_i_i_phi_temp;
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i = main__loopexit_i_preheader_i_i__ph_i_i_phi_temp;
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
else /* if (cur_state == LEGUP_F_main_BB14_26) */
begin
main__loopexit_i_preheader_i_i__ph_i_i = main__loopexit_i_preheader_i_i__ph_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i_reg <= main__loopexit_i_preheader_i_i__ph_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i__ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_reg"); $finish; end
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i_reg <= main__loopexit_i_preheader_i_i__ph_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i__ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_reg"); $finish; end
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i_reg <= main__loopexit_i_preheader_i_i__ph_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i__ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_reg"); $finish; end
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i_reg <= main__loopexit_i_preheader_i_i__ph_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i__ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_reg"); $finish; end
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB14_26)
begin
main__loopexit_i_preheader_i_i__ph_i_i_reg <= main__loopexit_i_preheader_i_i__ph_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i__ph_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.loopexit.i.i.i*/
/* %indvar9.i.i = phi i32 [ 0, %.loopexit.i.preheader.i.i ], [ %tmp12.i.i, %.loopexit.i.i.i ]*/
begin
main__loopexit_i_i_i_indvar9_i_i = main__loopexit_i_i_i_indvar9_i_i_phi_temp;
end
end
always @(*) begin
/* main: %.loopexit.i.i.i*/
/* %scevgep11.i.i = getelementptr i8* %.ph.i.i, i32 %indvar9.i.i*/
begin
main__loopexit_i_i_i_scevgep11_i_i = main__loopexit_i_preheader_i_i__ph_i_i_reg + 1 * main__loopexit_i_i_i_indvar9_i_i;
end
end
always @(*) begin
/* main: %.loopexit.i.i.i*/
/* %tmp12.i.i = add i32 %indvar9.i.i, 1*/
begin
main__loopexit_i_i_i_tmp12_i_i = main__loopexit_i_i_i_indvar9_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i.i*/
/* %tmp12.i.i = add i32 %indvar9.i.i, 1*/
if (cur_state == LEGUP_F_main_BB15_27)
begin
main__loopexit_i_i_i_tmp12_i_i_reg <= main__loopexit_i_i_i_tmp12_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_i_i_tmp12_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_i_tmp12_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.loopexit.i.i.i*/
/* %21 = load i8* %scevgep11.i.i, align 1, !tbaa !1*/
begin
main__loopexit_i_i_i_21 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.loopexit.i.i.i*/
/* %22 = zext i8 %21 to i32*/
begin
main__loopexit_i_i_i_22 = main__loopexit_i_i_i_21;
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i.i*/
/* %22 = zext i8 %21 to i32*/
if (cur_state == LEGUP_F_main_BB15_29)
begin
main__loopexit_i_i_i_22_reg <= main__loopexit_i_i_i_22;
if (^reset !== 1'bX && ^(main__loopexit_i_i_i_22) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_i_22_reg"); $finish; end
end
end
always @(*) begin
/* main: %next_marker.exit.i.i.loopexit*/
/* %scevgep13.i.i = getelementptr i8* %.ph.i.i, i32 %tmp12.i.i*/
begin
main_next_marker_exit_i_i_loopexit_scevgep13_i_i = main__loopexit_i_preheader_i_i__ph_i_i_reg + 1 * main__loopexit_i_i_i_tmp12_i_i_reg;
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
else /* if (cur_state == LEGUP_F_main_BB17_31) */
begin
main_next_marker_exit_i_i_ReadBuf_2 = main_next_marker_exit_i_i_ReadBuf_2_phi_temp;
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_ReadBuf_2_reg <= main_next_marker_exit_i_i_ReadBuf_2;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_reg"); $finish; end
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
else /* if (cur_state == LEGUP_F_main_BB17_31) */
begin
main_next_marker_exit_i_i_unread_marker_0_i_i = main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_reg <= main_next_marker_exit_i_i_unread_marker_0_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_unread_marker_0_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %24 = add nsw i32 %i_marker.1, 1*/
begin
main_next_marker_exit_i_i_24 = main__backedge_i_i_i_marker_1_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %24 = add nsw i32 %i_marker.1, 1*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_24_reg <= main_next_marker_exit_i_i_24;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_24_reg"); $finish; end
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %25 = getelementptr inbounds [10 x i32]* @out_unread_marker, i32 0, i32 %i_marker.1*/
begin
main_next_marker_exit_i_i_25 = `TAG_g_out_unread_marker_a + 4 * main__backedge_i_i_i_marker_1_reg;
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %25 = getelementptr inbounds [10 x i32]* @out_unread_marker, i32 0, i32 %i_marker.1*/
if (cur_state == LEGUP_F_main_BB17_31)
begin
main_next_marker_exit_i_i_25_reg <= main_next_marker_exit_i_i_25;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_25) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_25_reg"); $finish; end
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
begin
main_next_marker_exit_i_i_26 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %next_marker.exit.i.i*/
/* %27 = icmp eq i32 %unread_marker.0.i.i, %26*/
begin
main_next_marker_exit_i_i_27 = main_next_marker_exit_i_i_unread_marker_0_i_i_reg == main_next_marker_exit_i_i_26;
end
end
always @(*) begin
/* main: %28*/
/* %29 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_28_29 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %28*/
/* %30 = add nsw i32 %29, 1*/
begin
main_28_30 = main_28_29 + 32'd1;
end
end
always @(*) begin
/* main: %32*/
/* %33 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
begin
main_32_33 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %33 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_33_reg <= main_32_33;
if (^reset !== 1'bX && ^(main_32_33) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_33_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %34 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
begin
main_32_34 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %35 = zext i8 %34 to i16*/
begin
main_32_35 = main_32_34;
end
end
always @(*) begin
/* main: %32*/
/* %36 = shl nuw i16 %35, 8*/
begin
main_32_36 = main_32_35 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %36 = shl nuw i16 %35, 8*/
if (cur_state == LEGUP_F_main_BB20_41)
begin
main_32_36_reg <= main_32_36;
if (^reset !== 1'bX && ^(main_32_36) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_36_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %37 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
begin
main_32_37 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %37 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_37_reg <= main_32_37;
if (^reset !== 1'bX && ^(main_32_37) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_37_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
begin
main_32_38 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %39 = zext i8 %38 to i16*/
begin
main_32_39 = main_32_38;
end
end
always @(*) begin
/* main: %32*/
/* %40 = or i16 %36, %39*/
begin
main_32_40 = main_32_36_reg | main_32_39;
end
end
always @(*) begin
/* main: %32*/
/* %41 = sext i16 %40 to i32*/
begin
main_32_41 = $signed(main_32_40);
end
end
always @(posedge clk) begin
/* main: %32*/
/* %41 = sext i16 %40 to i32*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
main_32_41_reg <= main_32_41;
if (^reset !== 1'bX && ^(main_32_41) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_41_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %42 = getelementptr inbounds i8* %ReadBuf.2, i32 3*/
begin
main_32_42 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd3;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %42 = getelementptr inbounds i8* %ReadBuf.2, i32 3*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_42_reg <= main_32_42;
if (^reset !== 1'bX && ^(main_32_42) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_42_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
begin
main_32_43 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
main_32_43_reg <= main_32_43;
if (^reset !== 1'bX && ^(main_32_43) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_43_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %44 = getelementptr inbounds i8* %ReadBuf.2, i32 4*/
begin
main_32_44 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd4;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %44 = getelementptr inbounds i8* %ReadBuf.2, i32 4*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_44_reg <= main_32_44;
if (^reset !== 1'bX && ^(main_32_44) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_44_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %45 = load i8* %42, align 1, !tbaa !1*/
begin
main_32_45 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %46 = zext i8 %45 to i16*/
begin
main_32_46 = main_32_45;
end
end
always @(*) begin
/* main: %32*/
/* %47 = shl nuw i16 %46, 8*/
begin
main_32_47 = main_32_46 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %47 = shl nuw i16 %46, 8*/
if (cur_state == LEGUP_F_main_BB20_44)
begin
main_32_47_reg <= main_32_47;
if (^reset !== 1'bX && ^(main_32_47) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_47_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %48 = getelementptr inbounds i8* %ReadBuf.2, i32 5*/
begin
main_32_48 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd5;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %48 = getelementptr inbounds i8* %ReadBuf.2, i32 5*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_48_reg <= main_32_48;
if (^reset !== 1'bX && ^(main_32_48) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_48_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %49 = load i8* %44, align 1, !tbaa !1*/
begin
main_32_49 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %50 = zext i8 %49 to i16*/
begin
main_32_50 = main_32_49;
end
end
always @(*) begin
/* main: %32*/
/* %51 = or i16 %47, %50*/
begin
main_32_51 = main_32_47_reg | main_32_50;
end
end
always @(*) begin
/* main: %32*/
/* %52 = getelementptr inbounds i8* %ReadBuf.2, i32 6*/
begin
main_32_52 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd6;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %52 = getelementptr inbounds i8* %ReadBuf.2, i32 6*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_52_reg <= main_32_52;
if (^reset !== 1'bX && ^(main_32_52) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_52_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %53 = load i8* %48, align 1, !tbaa !1*/
begin
main_32_53 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %54 = zext i8 %53 to i16*/
begin
main_32_54 = main_32_53;
end
end
always @(*) begin
/* main: %32*/
/* %55 = shl nuw i16 %54, 8*/
begin
main_32_55 = main_32_54 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %55 = shl nuw i16 %54, 8*/
if (cur_state == LEGUP_F_main_BB20_48)
begin
main_32_55_reg <= main_32_55;
if (^reset !== 1'bX && ^(main_32_55) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_55_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %56 = getelementptr inbounds i8* %ReadBuf.2, i32 7*/
begin
main_32_56 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd7;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %56 = getelementptr inbounds i8* %ReadBuf.2, i32 7*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_56_reg <= main_32_56;
if (^reset !== 1'bX && ^(main_32_56) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_56_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %57 = load i8* %52, align 1, !tbaa !1*/
begin
main_32_57 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %32*/
/* %58 = zext i8 %57 to i16*/
begin
main_32_58 = main_32_57;
end
end
always @(*) begin
/* main: %32*/
/* %59 = or i16 %55, %58*/
begin
main_32_59 = main_32_55_reg | main_32_58;
end
end
always @(*) begin
/* main: %32*/
/* %60 = getelementptr inbounds i8* %ReadBuf.2, i32 8*/
begin
main_32_60 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd8;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %60 = getelementptr inbounds i8* %ReadBuf.2, i32 8*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
main_32_60_reg <= main_32_60;
if (^reset !== 1'bX && ^(main_32_60) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_60_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
begin
main_32_61 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
main_32_61_reg <= main_32_61;
if (^reset !== 1'bX && ^(main_32_61) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_61_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %63 = sext i8 %43 to i32*/
begin
main_32_63 = $signed(main_32_43);
end
end
always @(posedge clk) begin
/* main: %32*/
/* %63 = sext i8 %43 to i32*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
main_32_63_reg <= main_32_63;
if (^reset !== 1'bX && ^(main_32_63) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_63_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %65 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
begin
main_32_65 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %32*/
/* %66 = sext i16 %65 to i32*/
begin
main_32_66 = $signed(main_32_65);
end
end
always @(*) begin
/* main: %32*/
/* %68 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
begin
main_32_68 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %32*/
/* %69 = sext i16 %68 to i32*/
begin
main_32_69 = $signed(main_32_68);
end
end
always @(*) begin
/* main: %32*/
/* %71 = sext i8 %61 to i32*/
begin
main_32_71 = $signed(main_32_61);
end
end
always @(posedge clk) begin
/* main: %32*/
/* %71 = sext i8 %61 to i32*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
main_32_71_reg <= main_32_71;
if (^reset !== 1'bX && ^(main_32_71) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_71_reg"); $finish; end
end
end
always @(*) begin
/* main: %32*/
/* %73 = icmp eq i16 %40, 17*/
begin
main_32_73 = main_32_40 == 16'd17;
end
end
always @(posedge clk) begin
/* main: %32*/
/* %73 = icmp eq i16 %40, 17*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
main_32_73_reg <= main_32_73;
if (^reset !== 1'bX && ^(main_32_73) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_32_73_reg"); $finish; end
end
end
always @(*) begin
/* main: %74*/
/* %75 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_74_75 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %74*/
/* %76 = add nsw i32 %75, 1*/
begin
main_74_76 = main_74_75 + 32'd1;
end
end
always @(*) begin
/* main: %77*/
/* %78 = icmp eq i8 %43, 8*/
begin
main_77_78 = main_32_43_reg == 8'd8;
end
end
always @(*) begin
/* main: %79*/
/* %80 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_79_80 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %79*/
/* %81 = add nsw i32 %80, 1*/
begin
main_79_81 = main_79_80 + 32'd1;
end
end
always @(*) begin
/* main: %82*/
/* %83 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
begin
main_82_83 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %82*/
/* %84 = icmp eq i16 %83, 59*/
begin
main_82_84 = main_82_83 == 16'd59;
end
end
always @(*) begin
/* main: %85*/
/* %86 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_85_86 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %85*/
/* %87 = add nsw i32 %86, 1*/
begin
main_85_87 = main_85_86 + 32'd1;
end
end
always @(*) begin
/* main: %88*/
/* %89 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
begin
main_88_89 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %88*/
/* %90 = icmp eq i16 %89, 90*/
begin
main_88_90 = main_88_89 == 16'd90;
end
end
always @(*) begin
/* main: %91*/
/* %92 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_91_92 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %91*/
/* %93 = add nsw i32 %92, 1*/
begin
main_91_93 = main_91_92 + 32'd1;
end
end
always @(*) begin
/* main: %94*/
/* %95 = icmp eq i8 %61, 3*/
begin
main_94_95 = main_32_61_reg == 8'd3;
end
end
always @(*) begin
/* main: %.preheader.i.i.i.thread*/
/* %96 = load i32* @main_result, align 4, !tbaa !0*/
begin
main__preheader_i_i_i_thread_96 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %.preheader.i.i.i.thread*/
/* %97 = add nsw i32 %96, 1*/
begin
main__preheader_i_i_i_thread_97 = main__preheader_i_i_i_thread_96 + 32'd1;
end
end
always @(*) begin
/* main: %.preheader.i.i.i*/
/* %98 = icmp sgt i8 %61, 0*/
begin
main__preheader_i_i_i_98 = $signed(main_32_61_reg) > $signed(8'd0);
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_ReadBuf_3 = main__lr_ph_i1_i_i_ReadBuf_3_phi_temp;
end
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB31_82) */
begin
main__lr_ph_i1_i_i_ReadBuf_3 = main__lr_ph_i1_i_i_ReadBuf_3_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_ReadBuf_3_reg <= main__lr_ph_i1_i_i_ReadBuf_3;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_ReadBuf_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_reg"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_ReadBuf_3_reg <= main__lr_ph_i1_i_i_ReadBuf_3;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_ReadBuf_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_reg"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_ReadBuf_3_reg <= main__lr_ph_i1_i_i_ReadBuf_3;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_ReadBuf_3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %ci.02.i.i.i = phi i32 [ %tmp12.i.i.i, %159 ], [ 0, %.preheader.i.i.i.thread ], [ 0, %.preheader.i.i.i ]*/
begin
main__lr_ph_i1_i_i_ci_02_i_i_i = main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_index, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep_i_i_i = `TAG_g_p_jinfo_comps_info_index_a + 1 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_index, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep3.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_id, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep3_i_i_i = `TAG_g_p_jinfo_comps_info_id_a + 1 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep3.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_id, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep3_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep3_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep3_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep3_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep4.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep4_i_i_i = `TAG_g_p_jinfo_comps_info_h_samp_factor_a + 1 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep4.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep4_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep4_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep4_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep4_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep5.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_v_samp_factor, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep5_i_i_i = `TAG_g_p_jinfo_comps_info_v_samp_factor_a + 1 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep5.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_v_samp_factor, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep5_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep5_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep5_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep5_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep6.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_quant_tbl_no, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep6_i_i_i = `TAG_g_p_jinfo_comps_info_quant_tbl_no_a + 1 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep6.i.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_quant_tbl_no, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep6_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep6_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep6_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep6_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %tmp.i.i.i = trunc i32 %ci.02.i.i.i to i8*/
begin
main__lr_ph_i1_i_i_tmp_i_i_i = main__lr_ph_i1_i_i_ci_02_i_i_i[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep7.i.i.i = getelementptr [3 x i32]* @out_index_get_sof, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep7_i_i_i = `TAG_g_out_index_get_sof_a + 4 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep7.i.i.i = getelementptr [3 x i32]* @out_index_get_sof, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep7_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep7_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep7_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep7_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep8.i.i.i = getelementptr [3 x i32]* @out_comp_id_get_sos, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep8_i_i_i = `TAG_g_out_comp_id_get_sos_a + 4 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep8.i.i.i = getelementptr [3 x i32]* @out_comp_id_get_sos, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep8_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep8_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep8_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep8_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep9.i.i.i = getelementptr [3 x i32]* @out_v_samp_factor_get_sof, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep9_i_i_i = `TAG_g_out_v_samp_factor_get_sof_a + 4 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep9.i.i.i = getelementptr [3 x i32]* @out_v_samp_factor_get_sof, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep9_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep9_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep9_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep9_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep11.i.i.i = getelementptr [3 x i32]* @out_ac_tbl_no_get_sos, i32 0, i32 %ci.02.i.i.i*/
begin
main__lr_ph_i1_i_i_scevgep11_i_i_i = `TAG_g_out_ac_tbl_no_get_sos_a + 4 * main__lr_ph_i1_i_i_ci_02_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %scevgep11.i.i.i = getelementptr [3 x i32]* @out_ac_tbl_no_get_sos, i32 0, i32 %ci.02.i.i.i*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_scevgep11_i_i_i_reg <= main__lr_ph_i1_i_i_scevgep11_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_scevgep11_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_scevgep11_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %tmp12.i.i.i = add i32 %ci.02.i.i.i, 1*/
begin
main__lr_ph_i1_i_i_tmp12_i_i_i = main__lr_ph_i1_i_i_ci_02_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %tmp12.i.i.i = add i32 %ci.02.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_tmp12_i_i_i_reg <= main__lr_ph_i1_i_i_tmp12_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_tmp12_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_tmp12_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %99 = getelementptr inbounds i8* %ReadBuf.3, i32 1*/
begin
main__lr_ph_i1_i_i_99 = main__lr_ph_i1_i_i_ReadBuf_3 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %99 = getelementptr inbounds i8* %ReadBuf.3, i32 1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_99_reg <= main__lr_ph_i1_i_i_99;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_99) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_99_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %100 = load i8* %ReadBuf.3, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_100 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %101 = getelementptr inbounds i8* %ReadBuf.3, i32 2*/
begin
main__lr_ph_i1_i_i_101 = main__lr_ph_i1_i_i_ReadBuf_3 + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %101 = getelementptr inbounds i8* %ReadBuf.3, i32 2*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_101_reg <= main__lr_ph_i1_i_i_101;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_101) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_101_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %102 = load i8* %99, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_102 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %103 = lshr i8 %102, 4*/
begin
main__lr_ph_i1_i_i_103 = main__lr_ph_i1_i_i_102 >>> 8'd4 % 8'd8;
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %104 = and i8 %102, 15*/
begin
main__lr_ph_i1_i_i_104 = main__lr_ph_i1_i_i_102 & 8'd15;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %104 = and i8 %102, 15*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
main__lr_ph_i1_i_i_104_reg <= main__lr_ph_i1_i_i_104;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_104) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_104_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %105 = getelementptr inbounds i8* %ReadBuf.3, i32 3*/
begin
main__lr_ph_i1_i_i_105 = main__lr_ph_i1_i_i_ReadBuf_3 + 1 * 32'd3;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %105 = getelementptr inbounds i8* %ReadBuf.3, i32 3*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_105_reg <= main__lr_ph_i1_i_i_105;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_105) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_105_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %106 = load i8* %101, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_106 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %107 = sext i8 %tmp.i.i.i to i32*/
begin
main__lr_ph_i1_i_i_107 = $signed(main__lr_ph_i1_i_i_tmp_i_i_i);
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %107 = sext i8 %tmp.i.i.i to i32*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
main__lr_ph_i1_i_i_107_reg <= main__lr_ph_i1_i_i_107;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_107) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_107_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %109 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_109 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %110 = sext i8 %109 to i32*/
begin
main__lr_ph_i1_i_i_110 = $signed(main__lr_ph_i1_i_i_109);
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %112 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_112 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %113 = sext i8 %112 to i32*/
begin
main__lr_ph_i1_i_i_113 = $signed(main__lr_ph_i1_i_i_112);
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %115 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_115 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %116 = sext i8 %115 to i32*/
begin
main__lr_ph_i1_i_i_116 = $signed(main__lr_ph_i1_i_i_115);
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %118 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_118 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %119 = sext i8 %118 to i32*/
begin
main__lr_ph_i1_i_i_119 = $signed(main__lr_ph_i1_i_i_118);
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %121 = load i8* %scevgep.i.i.i, align 1, !tbaa !1*/
begin
main__lr_ph_i1_i_i_121 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %122 = sext i8 %121 to i32*/
begin
main__lr_ph_i1_i_i_122 = $signed(main__lr_ph_i1_i_i_121);
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %122 = sext i8 %121 to i32*/
if (cur_state == LEGUP_F_main_BB31_107)
begin
main__lr_ph_i1_i_i_122_reg <= main__lr_ph_i1_i_i_122;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_122) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_122_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %123 = load i32* %scevgep7.i.i.i, align 4, !tbaa !0*/
begin
main__lr_ph_i1_i_i_123 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %.lr.ph.i1.i.i*/
/* %124 = icmp eq i32 %122, %123*/
begin
main__lr_ph_i1_i_i_124 = main__lr_ph_i1_i_i_122_reg == main__lr_ph_i1_i_i_123;
end
end
always @(*) begin
/* main: %125*/
/* %126 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_125_126 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %125*/
/* %127 = add nsw i32 %126, 1*/
begin
main_125_127 = main_125_126 + 32'd1;
end
end
always @(*) begin
/* main: %128*/
/* %129 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
begin
main_128_129 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %128*/
/* %130 = sext i8 %129 to i32*/
begin
main_128_130 = $signed(main_128_129);
end
end
always @(posedge clk) begin
/* main: %128*/
/* %130 = sext i8 %129 to i32*/
if (cur_state == LEGUP_F_main_BB33_114)
begin
main_128_130_reg <= main_128_130;
if (^reset !== 1'bX && ^(main_128_130) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_128_130_reg"); $finish; end
end
end
always @(*) begin
/* main: %128*/
/* %131 = load i32* %scevgep8.i.i.i, align 4, !tbaa !0*/
begin
main_128_131 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %128*/
/* %132 = icmp eq i32 %130, %131*/
begin
main_128_132 = main_128_130_reg == main_128_131;
end
end
always @(*) begin
/* main: %133*/
/* %134 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_133_134 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %133*/
/* %135 = add nsw i32 %134, 1*/
begin
main_133_135 = main_133_134 + 32'd1;
end
end
always @(*) begin
/* main: %136*/
/* %137 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
begin
main_136_137 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %136*/
/* %138 = sext i8 %137 to i32*/
begin
main_136_138 = $signed(main_136_137);
end
end
always @(posedge clk) begin
/* main: %136*/
/* %138 = sext i8 %137 to i32*/
if (cur_state == LEGUP_F_main_BB35_121)
begin
main_136_138_reg <= main_136_138;
if (^reset !== 1'bX && ^(main_136_138) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_136_138_reg"); $finish; end
end
end
always @(*) begin
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
begin
main_136_139 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB35_122)
begin
main_136_139_reg <= main_136_139;
if (^reset !== 1'bX && ^(main_136_139) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_136_139_reg"); $finish; end
end
end
always @(*) begin
/* main: %136*/
/* %140 = icmp eq i32 %138, %139*/
begin
main_136_140 = main_136_138_reg == main_136_139;
end
end
always @(*) begin
/* main: %141*/
/* %142 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_141_142 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %141*/
/* %143 = add nsw i32 %142, 1*/
begin
main_141_143 = main_141_142 + 32'd1;
end
end
always @(*) begin
/* main: %144*/
/* %145 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
begin
main_144_145 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %144*/
/* %146 = sext i8 %145 to i32*/
begin
main_144_146 = $signed(main_144_145);
end
end
always @(*) begin
/* main: %144*/
/* %147 = icmp eq i32 %146, %139*/
begin
main_144_147 = main_144_146 == main_136_139_reg;
end
end
always @(*) begin
/* main: %148*/
/* %149 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_148_149 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %148*/
/* %150 = add nsw i32 %149, 1*/
begin
main_148_150 = main_148_149 + 32'd1;
end
end
always @(*) begin
/* main: %151*/
/* %152 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
begin
main_151_152 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %151*/
/* %153 = sext i8 %152 to i32*/
begin
main_151_153 = $signed(main_151_152);
end
end
always @(posedge clk) begin
/* main: %151*/
/* %153 = sext i8 %152 to i32*/
if (cur_state == LEGUP_F_main_BB39_134)
begin
main_151_153_reg <= main_151_153;
if (^reset !== 1'bX && ^(main_151_153) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_151_153_reg"); $finish; end
end
end
always @(*) begin
/* main: %151*/
/* %154 = load i32* %scevgep11.i.i.i, align 4, !tbaa !0*/
begin
main_151_154 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %151*/
/* %155 = icmp eq i32 %153, %154*/
begin
main_151_155 = main_151_153_reg == main_151_154;
end
end
always @(*) begin
/* main: %156*/
/* %157 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_156_157 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %156*/
/* %158 = add nsw i32 %157, 1*/
begin
main_156_158 = main_156_157 + 32'd1;
end
end
always @(*) begin
/* main: %159*/
/* %160 = icmp slt i32 %tmp12.i.i.i, %71*/
begin
main_159_160 = $signed(main__lr_ph_i1_i_i_tmp12_i_i_i_reg) < $signed(main_32_71_reg);
end
end
always @(*) begin
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4 = main___crit_edge_i_i_i_ReadBuf_4_phi_temp;
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
else if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4 = main___crit_edge_i_i_i_ReadBuf_4_phi_temp;
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
else /* if (cur_state == LEGUP_F_main_BB42_140) */
begin
main___crit_edge_i_i_i_ReadBuf_4 = main___crit_edge_i_i_i_ReadBuf_4_phi_temp;
end
end
always @(posedge clk) begin
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4_reg <= main___crit_edge_i_i_i_ReadBuf_4;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_reg"); $finish; end
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4_reg <= main___crit_edge_i_i_i_ReadBuf_4;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_reg"); $finish; end
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4_reg <= main___crit_edge_i_i_i_ReadBuf_4;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_reg"); $finish; end
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
main___crit_edge_i_i_i_ReadBuf_4_reg <= main___crit_edge_i_i_i_ReadBuf_4;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_reg"); $finish; end
end
end
always @(*) begin
/* main: %._crit_edge.i.i.i*/
/* %161 = load i8* getelementptr inbounds ([3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 0), align 1, !tbaa !1*/
begin
main___crit_edge_i_i_i_161 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %._crit_edge.i.i.i*/
/* %162 = icmp eq i8 %161, 2*/
begin
main___crit_edge_i_i_i_162 = main___crit_edge_i_i_i_161 == 8'd2;
end
end
always @(*) begin
/* main: %167*/
/* %168 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
begin
main_167_168 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %168 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
main_167_168_reg <= main_167_168;
if (^reset !== 1'bX && ^(main_167_168) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_168_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %169 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
begin
main_167_169 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %167*/
/* %170 = zext i8 %169 to i16*/
begin
main_167_170 = main_167_169;
end
end
always @(*) begin
/* main: %167*/
/* %171 = shl nuw i16 %170, 8*/
begin
main_167_171 = main_167_170 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %171 = shl nuw i16 %170, 8*/
if (cur_state == LEGUP_F_main_BB45_147)
begin
main_167_171_reg <= main_167_171;
if (^reset !== 1'bX && ^(main_167_171) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_171_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %172 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
begin
main_167_172 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %172 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
main_167_172_reg <= main_167_172;
if (^reset !== 1'bX && ^(main_167_172) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_172_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %173 = load i8* %168, align 1, !tbaa !1*/
begin
main_167_173 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %167*/
/* %174 = zext i8 %173 to i16*/
begin
main_167_174 = main_167_173;
end
end
always @(*) begin
/* main: %167*/
/* %175 = or i16 %171, %174*/
begin
main_167_175 = main_167_171_reg | main_167_174;
end
end
always @(*) begin
/* main: %167*/
/* %176 = sext i16 %175 to i32*/
begin
main_167_176 = $signed(main_167_175);
end
end
always @(*) begin
/* main: %167*/
/* %177 = getelementptr inbounds i8* %ReadBuf.2, i32 3*/
begin
main_167_177 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd3;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %177 = getelementptr inbounds i8* %ReadBuf.2, i32 3*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
main_167_177_reg <= main_167_177;
if (^reset !== 1'bX && ^(main_167_177) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_177_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
begin
main_167_178 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_149)
begin
main_167_178_reg <= main_167_178;
if (^reset !== 1'bX && ^(main_167_178) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_178_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %179 = zext i8 %178 to i32*/
begin
main_167_179 = main_167_178;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %179 = zext i8 %178 to i32*/
if (cur_state == LEGUP_F_main_BB45_149)
begin
main_167_179_reg <= main_167_179;
if (^reset !== 1'bX && ^(main_167_179) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_179_reg"); $finish; end
end
end
always @(*) begin
/* main: %167*/
/* %182 = icmp eq i16 %175, 12*/
begin
main_167_182 = main_167_175 == 16'd12;
end
end
always @(posedge clk) begin
/* main: %167*/
/* %182 = icmp eq i16 %175, 12*/
if (cur_state == LEGUP_F_main_BB45_148)
begin
main_167_182_reg <= main_167_182;
if (^reset !== 1'bX && ^(main_167_182) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_167_182_reg"); $finish; end
end
end
always @(*) begin
/* main: %183*/
/* %184 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_183_184 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %183*/
/* %185 = add nsw i32 %184, 1*/
begin
main_183_185 = main_183_184 + 32'd1;
end
end
always @(*) begin
/* main: %186*/
/* %187 = icmp eq i8 %178, 3*/
begin
main_186_187 = main_167_178_reg == 8'd3;
end
end
always @(*) begin
/* main: %188*/
/* %189 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_188_189 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %188*/
/* %190 = add nsw i32 %189, 1*/
begin
main_188_190 = main_188_189 + 32'd1;
end
end
always @(*) begin
/* main: %.preheader5.i.i.i.preheader*/
/* %191 = sext i8 %p_jinfo_num_components.1.ph13 to i32*/
begin
main__preheader5_i_i_i_preheader_191 = $signed(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg);
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i.preheader*/
/* %191 = sext i8 %p_jinfo_num_components.1.ph13 to i32*/
if (cur_state == LEGUP_F_main_BB49_157)
begin
main__preheader5_i_i_i_preheader_191_reg <= main__preheader5_i_i_i_preheader_191;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_preheader_191) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_preheader_191_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0 = main__preheader5_i_i_i_i_get_sos_0_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
else if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0 = main__preheader5_i_i_i_i_get_sos_0_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
else if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0 = main__preheader5_i_i_i_i_get_sos_0_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
else /* if (cur_state == LEGUP_F_main_BB50_158) */
begin
main__preheader5_i_i_i_i_get_sos_0 = main__preheader5_i_i_i_i_get_sos_0_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0_reg <= main__preheader5_i_i_i_i_get_sos_0;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_i_get_sos_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0_reg <= main__preheader5_i_i_i_i_get_sos_0;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_i_get_sos_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0_reg <= main__preheader5_i_i_i_i_get_sos_0;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_i_get_sos_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0_reg <= main__preheader5_i_i_i_i_get_sos_0;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_i_get_sos_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_i_get_sos_0_reg <= main__preheader5_i_i_i_i_get_sos_0;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_i_get_sos_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5 = main__preheader5_i_i_i_ReadBuf_5_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
else if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5 = main__preheader5_i_i_i_ReadBuf_5_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
else if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5 = main__preheader5_i_i_i_ReadBuf_5_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
else if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5 = main__preheader5_i_i_i_ReadBuf_5_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
else /* if (cur_state == LEGUP_F_main_BB50_158) */
begin
main__preheader5_i_i_i_ReadBuf_5 = main__preheader5_i_i_i_ReadBuf_5_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_ReadBuf_5_reg <= main__preheader5_i_i_i_ReadBuf_5;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_ReadBuf_5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_192 = main__preheader5_i_i_i_192_phi_temp;
end
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
else /* if (cur_state == LEGUP_F_main_BB50_158) */
begin
main__preheader5_i_i_i_192 = main__preheader5_i_i_i_192_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_192_reg <= main__preheader5_i_i_i_192;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_192_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_192_reg <= main__preheader5_i_i_i_192;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_192_reg"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB50_158)
begin
main__preheader5_i_i_i_192_reg <= main__preheader5_i_i_i_192;
if (^reset !== 1'bX && ^(main__preheader5_i_i_i_192) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_192_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader5.i.i.i*/
/* %193 = icmp slt i32 %192, %179*/
begin
main__preheader5_i_i_i_193 = $signed(main__preheader5_i_i_i_192) < $signed(main_167_179_reg);
end
end
always @(*) begin
/* main: %194*/
/* %195 = getelementptr inbounds i8* %ReadBuf.5, i32 1*/
begin
main_194_195 = main__preheader5_i_i_i_ReadBuf_5_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %194*/
/* %195 = getelementptr inbounds i8* %ReadBuf.5, i32 1*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
main_194_195_reg <= main_194_195;
if (^reset !== 1'bX && ^(main_194_195) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_194_195_reg"); $finish; end
end
end
always @(*) begin
/* main: %194*/
/* %196 = load i8* %ReadBuf.5, align 1, !tbaa !1*/
begin
main_194_196 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %194*/
/* %197 = zext i8 %196 to i32*/
begin
main_194_197 = main_194_196;
end
end
always @(posedge clk) begin
/* main: %194*/
/* %197 = zext i8 %196 to i32*/
if (cur_state == LEGUP_F_main_BB51_161)
begin
main_194_197_reg <= main_194_197;
if (^reset !== 1'bX && ^(main_194_197) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_194_197_reg"); $finish; end
end
end
always @(*) begin
/* main: %194*/
/* %198 = getelementptr inbounds i8* %ReadBuf.5, i32 2*/
begin
main_194_198 = main__preheader5_i_i_i_ReadBuf_5_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %194*/
/* %198 = getelementptr inbounds i8* %ReadBuf.5, i32 2*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
main_194_198_reg <= main_194_198;
if (^reset !== 1'bX && ^(main_194_198) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_194_198_reg"); $finish; end
end
end
always @(*) begin
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
begin
main_194_199 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_162)
begin
main_194_199_reg <= main_194_199;
if (^reset !== 1'bX && ^(main_194_199) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_194_199_reg"); $finish; end
end
end
always @(*) begin
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201 = main_200_201_phi_temp;
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
else if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201 = main_200_201_phi_temp;
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
else if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201 = main_200_201_phi_temp;
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
else if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201 = main_200_201_phi_temp;
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
else /* if (cur_state == LEGUP_F_main_BB52_163) */
begin
main_200_201 = main_200_201_phi_temp;
end
end
always @(posedge clk) begin
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB52_163)
begin
main_200_201_reg <= main_200_201;
if (^reset !== 1'bX && ^(main_200_201) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_reg"); $finish; end
end
end
always @(*) begin
/* main: %200*/
/* %202 = icmp slt i32 %201, %191*/
begin
main_200_202 = $signed(main_200_201) < $signed(main__preheader5_i_i_i_preheader_191_reg);
end
end
always @(*) begin
/* main: %203*/
/* %scevgep9.i4.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_id, i32 0, i32 %201*/
begin
main_203_scevgep9_i4_i_i = `TAG_g_p_jinfo_comps_info_id_a + 1 * main_200_201_reg;
end
end
always @(*) begin
/* main: %203*/
/* %204 = load i8* %scevgep9.i4.i.i, align 1, !tbaa !1*/
begin
main_203_204 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %203*/
/* %205 = sext i8 %204 to i32*/
begin
main_203_205 = $signed(main_203_204);
end
end
always @(*) begin
/* main: %203*/
/* %206 = icmp eq i32 %197, %205*/
begin
main_203_206 = main_194_197_reg == main_203_205;
end
end
always @(*) begin
/* main: %207*/
/* %208 = add nsw i32 %201, 1*/
begin
main_207_208 = main_200_201_reg + 32'd1;
end
end
always @(*) begin
/* main: %211*/
/* %scevgep8.i5.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_dc_tbl_no, i32 0, i32 %201*/
begin
main_211_scevgep8_i5_i_i = `TAG_g_p_jinfo_comps_info_dc_tbl_no_a + 1 * main_200_201_reg;
end
end
always @(posedge clk) begin
/* main: %211*/
/* %scevgep8.i5.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_dc_tbl_no, i32 0, i32 %201*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
main_211_scevgep8_i5_i_i_reg <= main_211_scevgep8_i5_i_i;
if (^reset !== 1'bX && ^(main_211_scevgep8_i5_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_211_scevgep8_i5_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %211*/
/* %scevgep7.i6.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_ac_tbl_no, i32 0, i32 %201*/
begin
main_211_scevgep7_i6_i_i = `TAG_g_p_jinfo_comps_info_ac_tbl_no_a + 1 * main_200_201_reg;
end
end
always @(posedge clk) begin
/* main: %211*/
/* %scevgep7.i6.i.i = getelementptr [3 x i8]* @p_jinfo_comps_info_ac_tbl_no, i32 0, i32 %201*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
main_211_scevgep7_i6_i_i_reg <= main_211_scevgep7_i6_i_i;
if (^reset !== 1'bX && ^(main_211_scevgep7_i6_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_211_scevgep7_i6_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %211*/
/* %212 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_211_212 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %211*/
/* %213 = add nsw i32 %212, 1*/
begin
main_211_213 = main_211_212 + 32'd1;
end
end
always @(*) begin
/* main: %211*/
/* %214 = lshr i8 %199, 4*/
begin
main_211_214 = main_194_199_reg >>> 8'd4 % 8'd8;
end
end
always @(posedge clk) begin
/* main: %211*/
/* %214 = lshr i8 %199, 4*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
main_211_214_reg <= main_211_214;
if (^reset !== 1'bX && ^(main_211_214) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_211_214_reg"); $finish; end
end
end
always @(*) begin
/* main: %211*/
/* %215 = and i8 %199, 15*/
begin
main_211_215 = main_194_199_reg & 8'd15;
end
end
always @(posedge clk) begin
/* main: %211*/
/* %215 = and i8 %199, 15*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
main_211_215_reg <= main_211_215;
if (^reset !== 1'bX && ^(main_211_215) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_211_215_reg"); $finish; end
end
end
always @(*) begin
/* main: %211*/
/* %217 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
begin
main_211_217 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %211*/
/* %218 = sext i8 %217 to i32*/
begin
main_211_218 = $signed(main_211_217);
end
end
always @(*) begin
/* main: %211*/
/* %220 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
begin
main_211_220 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %211*/
/* %221 = sext i8 %220 to i32*/
begin
main_211_221 = $signed(main_211_220);
end
end
always @(*) begin
/* main: %211*/
/* %223 = getelementptr inbounds [3 x i32]* @out_comp_id_get_sos, i32 0, i32 %i_get_sos.0*/
begin
main_211_223 = `TAG_g_out_comp_id_get_sos_a + 4 * main__preheader5_i_i_i_i_get_sos_0_reg;
end
end
always @(posedge clk) begin
/* main: %211*/
/* %223 = getelementptr inbounds [3 x i32]* @out_comp_id_get_sos, i32 0, i32 %i_get_sos.0*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
main_211_223_reg <= main_211_223;
if (^reset !== 1'bX && ^(main_211_223) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_211_223_reg"); $finish; end
end
end
always @(*) begin
/* main: %211*/
/* %224 = load i32* %223, align 4, !tbaa !0*/
begin
main_211_224 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %211*/
/* %225 = icmp eq i32 %197, %224*/
begin
main_211_225 = main_194_197_reg == main_211_224;
end
end
always @(*) begin
/* main: %226*/
/* %227 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_226_227 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %226*/
/* %228 = add nsw i32 %227, 1*/
begin
main_226_228 = main_226_227 + 32'd1;
end
end
always @(*) begin
/* main: %229*/
/* %230 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
begin
main_229_230 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %229*/
/* %231 = sext i8 %230 to i32*/
begin
main_229_231 = $signed(main_229_230);
end
end
always @(posedge clk) begin
/* main: %229*/
/* %231 = sext i8 %230 to i32*/
if (cur_state == LEGUP_F_main_BB58_188)
begin
main_229_231_reg <= main_229_231;
if (^reset !== 1'bX && ^(main_229_231) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_229_231_reg"); $finish; end
end
end
always @(*) begin
/* main: %229*/
/* %232 = getelementptr inbounds [3 x i32]* @out_ac_tbl_no_get_sos, i32 0, i32 %i_get_sos.0*/
begin
main_229_232 = `TAG_g_out_ac_tbl_no_get_sos_a + 4 * main__preheader5_i_i_i_i_get_sos_0_reg;
end
end
always @(posedge clk) begin
/* main: %229*/
/* %232 = getelementptr inbounds [3 x i32]* @out_ac_tbl_no_get_sos, i32 0, i32 %i_get_sos.0*/
if (cur_state == LEGUP_F_main_BB58_186)
begin
main_229_232_reg <= main_229_232;
if (^reset !== 1'bX && ^(main_229_232) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_229_232_reg"); $finish; end
end
end
always @(*) begin
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
begin
main_229_233 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB58_189)
begin
main_229_233_reg <= main_229_233;
if (^reset !== 1'bX && ^(main_229_233) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_229_233_reg"); $finish; end
end
end
always @(*) begin
/* main: %229*/
/* %234 = icmp eq i32 %231, %233*/
begin
main_229_234 = main_229_231_reg == main_229_233;
end
end
always @(*) begin
/* main: %235*/
/* %236 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_235_236 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %235*/
/* %237 = add nsw i32 %236, 1*/
begin
main_235_237 = main_235_236 + 32'd1;
end
end
always @(*) begin
/* main: %238*/
/* %239 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
begin
main_238_239 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %238*/
/* %240 = sext i8 %239 to i32*/
begin
main_238_240 = $signed(main_238_239);
end
end
always @(*) begin
/* main: %238*/
/* %241 = icmp eq i32 %240, %233*/
begin
main_238_241 = main_238_240 == main_229_233_reg;
end
end
always @(*) begin
/* main: %242*/
/* %243 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_242_243 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %242*/
/* %244 = add nsw i32 %243, 1*/
begin
main_242_244 = main_242_243 + 32'd1;
end
end
always @(*) begin
/* main: %245*/
/* %246 = add nsw i32 %i_get_sos.0, 1*/
begin
main_245_246 = main__preheader5_i_i_i_i_get_sos_0_reg + 32'd1;
end
end
always @(*) begin
/* main: %245*/
/* %247 = add nsw i32 %192, 1*/
begin
main_245_247 = main__preheader5_i_i_i_192_reg + 32'd1;
end
end
always @(*) begin
/* main: %get_sos.exit.i.i*/
/* %scevgep.i2.i.i = getelementptr i8* %ReadBuf.5, i32 3*/
begin
main_get_sos_exit_i_i_scevgep_i2_i_i = main__preheader5_i_i_i_ReadBuf_5_reg + 1 * 32'd3;
end
end
always @(*) begin
/* main: %248*/
/* %249 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
begin
main_248_249 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %248*/
/* %249 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
main_248_249_reg <= main_248_249;
if (^reset !== 1'bX && ^(main_248_249) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_248_249_reg"); $finish; end
end
end
always @(*) begin
/* main: %248*/
/* %250 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
begin
main_248_250 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %248*/
/* %251 = zext i8 %250 to i16*/
begin
main_248_251 = main_248_250;
end
end
always @(*) begin
/* main: %248*/
/* %252 = shl nuw i16 %251, 8*/
begin
main_248_252 = main_248_251 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %248*/
/* %252 = shl nuw i16 %251, 8*/
if (cur_state == LEGUP_F_main_BB64_203)
begin
main_248_252_reg <= main_248_252;
if (^reset !== 1'bX && ^(main_248_252) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_248_252_reg"); $finish; end
end
end
always @(*) begin
/* main: %248*/
/* %253 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
begin
main_248_253 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %248*/
/* %253 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
main_248_253_reg <= main_248_253;
if (^reset !== 1'bX && ^(main_248_253) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_248_253_reg"); $finish; end
end
end
always @(*) begin
/* main: %248*/
/* %254 = load i8* %249, align 1, !tbaa !1*/
begin
main_248_254 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %248*/
/* %255 = zext i8 %254 to i16*/
begin
main_248_255 = main_248_254;
end
end
always @(*) begin
/* main: %248*/
/* %256 = or i16 %252, %255*/
begin
main_248_256 = main_248_252_reg | main_248_255;
end
end
always @(*) begin
/* main: %248*/
/* %257 = sext i16 %256 to i32*/
begin
main_248_257 = $signed(main_248_256);
end
end
always @(*) begin
/* main: %248*/
/* %258 = add nsw i32 %257, -2*/
begin
main_248_258 = main_248_257 + -32'd2;
end
end
always @(posedge clk) begin
/* main: %248*/
/* %258 = add nsw i32 %257, -2*/
if (cur_state == LEGUP_F_main_BB64_204)
begin
main_248_258_reg <= main_248_258;
if (^reset !== 1'bX && ^(main_248_258) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_248_258_reg"); $finish; end
end
end
always @(*) begin
/* main: %248*/
/* %260 = load i32* %4, align 4, !tbaa !0*/
begin
main_248_260 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %248*/
/* %261 = icmp eq i32 %258, %260*/
begin
main_248_261 = main_248_258_reg == main_248_260;
end
end
always @(*) begin
/* main: %262*/
/* %263 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_262_263 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %262*/
/* %264 = add nsw i32 %263, 1*/
begin
main_262_264 = main_262_263 + 32'd1;
end
end
always @(*) begin
/* main: %.preheader.i7.i.i*/
/* %265 = icmp sgt i32 %258, 16*/
begin
main__preheader_i7_i_i_265 = $signed(main_248_258_reg) > $signed(32'd16);
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2 = main__lr_ph5_i_i_i_i_get_dht_2_phi_temp;
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
else if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2 = main__lr_ph5_i_i_i_i_get_dht_2_phi_temp;
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB67_212) */
begin
main__lr_ph5_i_i_i_i_get_dht_2 = main__lr_ph5_i_i_i_i_get_dht_2_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2_reg <= main__lr_ph5_i_i_i_i_get_dht_2;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_i_get_dht_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_reg"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2_reg <= main__lr_ph5_i_i_i_i_get_dht_2;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_i_get_dht_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_reg"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2_reg <= main__lr_ph5_i_i_i_i_get_dht_2;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_i_get_dht_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_reg"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_i_get_dht_2_reg <= main__lr_ph5_i_i_i_i_get_dht_2;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_i_get_dht_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %ReadBuf.6 = phi i8* [ %ReadBuf.7, %._crit_edge.i12.i.i ], [ %253, %.preheader.i7.i.i ]*/
begin
main__lr_ph5_i_i_i_ReadBuf_6 = main__lr_ph5_i_i_i_ReadBuf_6_phi_temp;
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_length_04_i_i_i = main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp;
end
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB67_212) */
begin
main__lr_ph5_i_i_i_length_04_i_i_i = main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_length_04_i_i_i_reg <= main__lr_ph5_i_i_i_length_04_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_length_04_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_length_04_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_length_04_i_i_i_reg <= main__lr_ph5_i_i_i_length_04_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_length_04_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_length_04_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_length_04_i_i_i_reg <= main__lr_ph5_i_i_i_length_04_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_length_04_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_length_04_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %266 = getelementptr inbounds i8* %ReadBuf.6, i32 1*/
begin
main__lr_ph5_i_i_i_266 = main__lr_ph5_i_i_i_ReadBuf_6 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %266 = getelementptr inbounds i8* %ReadBuf.6, i32 1*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_266_reg <= main__lr_ph5_i_i_i_266;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_266) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_266_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %267 = load i8* %ReadBuf.6, align 1, !tbaa !1*/
begin
main__lr_ph5_i_i_i_267 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %268 = zext i8 %267 to i32*/
begin
main__lr_ph5_i_i_i_268 = main__lr_ph5_i_i_i_267;
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %268 = zext i8 %267 to i32*/
if (cur_state == LEGUP_F_main_BB67_214)
begin
main__lr_ph5_i_i_i_268_reg <= main__lr_ph5_i_i_i_268;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_268) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_268_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %270 = getelementptr inbounds [4 x i32]* @out_index_get_dht, i32 0, i32 %i_get_dht.2*/
begin
main__lr_ph5_i_i_i_270 = `TAG_g_out_index_get_dht_a + 4 * main__lr_ph5_i_i_i_i_get_dht_2;
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %270 = getelementptr inbounds [4 x i32]* @out_index_get_dht, i32 0, i32 %i_get_dht.2*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
main__lr_ph5_i_i_i_270_reg <= main__lr_ph5_i_i_i_270;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_270) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_270_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %271 = load i32* %270, align 4, !tbaa !0*/
begin
main__lr_ph5_i_i_i_271 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %.lr.ph5.i.i.i*/
/* %272 = icmp eq i32 %268, %271*/
begin
main__lr_ph5_i_i_i_272 = main__lr_ph5_i_i_i_268_reg == main__lr_ph5_i_i_i_271;
end
end
always @(*) begin
/* main: %273*/
/* %274 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_273_274 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %273*/
/* %275 = add nsw i32 %274, 1*/
begin
main_273_275 = main_273_274 + 32'd1;
end
end
always @(*) begin
/* main: %276*/
/* %277 = and i32 %268, 16*/
begin
main_276_277 = main__lr_ph5_i_i_i_268_reg & 32'd16;
end
end
always @(*) begin
/* main: %276*/
/* %278 = icmp eq i32 %277, 0*/
begin
main_276_278 = main_276_277 == 32'd0;
end
end
always @(*) begin
/* main: %279*/
/* %280 = add nsw i32 %268, -16*/
begin
main_279_280 = main__lr_ph5_i_i_i_268_reg + -32'd16;
end
end
always @(*) begin
/* main: %279*/
/* %281 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 %280, i32 0*/
begin
main_279_281 = `TAG_g_p_jinfo_ac_xhuff_tbl_bits_a + 144 * main_279_280;
end
end
always @(*) begin
/* main: %279*/
/* %282 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_ac_xhuff_tbl_huffval, i32 0, i32 %280, i32 0*/
begin
main_279_282 = `TAG_g_p_jinfo_ac_xhuff_tbl_huffval_a + 1028 * main_279_280;
end
end
always @(*) begin
/* main: %283*/
/* %284 = getelementptr inbounds [2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 %268, i32 0*/
begin
main_283_284 = `TAG_g_p_jinfo_dc_xhuff_tbl_bits_a + 144 * main__lr_ph5_i_i_i_268_reg;
end
end
always @(*) begin
/* main: %283*/
/* %285 = getelementptr inbounds [2 x [257 x i32]]* @p_jinfo_dc_xhuff_tbl_huffval, i32 0, i32 %268, i32 0*/
begin
main_283_285 = `TAG_g_p_jinfo_dc_xhuff_tbl_huffval_a + 1028 * main__lr_ph5_i_i_i_268_reg;
end
end
always @(*) begin
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_huffval_0_i_i_i = main_286_p_xhtbl_huffval_0_i_i_i_phi_temp;
end
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
else /* if (cur_state == LEGUP_F_main_BB72_224) */
begin
main_286_p_xhtbl_huffval_0_i_i_i = main_286_p_xhtbl_huffval_0_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_huffval_0_i_i_i_reg <= main_286_p_xhtbl_huffval_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_huffval_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_huffval_0_i_i_i_reg"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_huffval_0_i_i_i_reg <= main_286_p_xhtbl_huffval_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_huffval_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_huffval_0_i_i_i_reg"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_huffval_0_i_i_i_reg <= main_286_p_xhtbl_huffval_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_huffval_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_huffval_0_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_bits_0_i_i_i = main_286_p_xhtbl_bits_0_i_i_i_phi_temp;
end
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
else /* if (cur_state == LEGUP_F_main_BB72_224) */
begin
main_286_p_xhtbl_bits_0_i_i_i = main_286_p_xhtbl_bits_0_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_bits_0_i_i_i_reg <= main_286_p_xhtbl_bits_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_bits_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_bits_0_i_i_i_reg"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_bits_0_i_i_i_reg <= main_286_p_xhtbl_bits_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_bits_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_bits_0_i_i_i_reg"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB72_224)
begin
main_286_p_xhtbl_bits_0_i_i_i_reg <= main_286_p_xhtbl_bits_0_i_i_i;
if (^reset !== 1'bX && ^(main_286_p_xhtbl_bits_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_bits_0_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %288 = phi i8* [ %266, %286 ], [ %289, %287 ]*/
begin
main_287_288 = main_287_288_phi_temp;
end
end
always @(*) begin
/* main: %287*/
/* %indvar.i.i.i = phi i32 [ 0, %286 ], [ %tmp.i8.i.i, %287 ]*/
begin
main_287_indvar_i_i_i = main_287_indvar_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_count_01_i_i_i = main_287_count_01_i_i_i_phi_temp;
end
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
else /* if (cur_state == LEGUP_F_main_BB73_225) */
begin
main_287_count_01_i_i_i = main_287_count_01_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_count_01_i_i_i_reg <= main_287_count_01_i_i_i;
if (^reset !== 1'bX && ^(main_287_count_01_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_count_01_i_i_i_reg"); $finish; end
end
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_count_01_i_i_i_reg <= main_287_count_01_i_i_i;
if (^reset !== 1'bX && ^(main_287_count_01_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_count_01_i_i_i_reg"); $finish; end
end
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_count_01_i_i_i_reg <= main_287_count_01_i_i_i;
if (^reset !== 1'bX && ^(main_287_count_01_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_count_01_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %tmp.i8.i.i = add i32 %indvar.i.i.i, 1*/
begin
main_287_tmp_i8_i_i = main_287_indvar_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %tmp.i8.i.i = add i32 %indvar.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_tmp_i8_i_i_reg <= main_287_tmp_i8_i_i;
if (^reset !== 1'bX && ^(main_287_tmp_i8_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_tmp_i8_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %scevgep.i9.i.i = getelementptr i32* %p_xhtbl_bits.0.i.i.i, i32 %tmp.i8.i.i*/
begin
main_287_scevgep_i9_i_i = main_286_p_xhtbl_bits_0_i_i_i_reg + 4 * main_287_tmp_i8_i_i;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %scevgep.i9.i.i = getelementptr i32* %p_xhtbl_bits.0.i.i.i, i32 %tmp.i8.i.i*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_scevgep_i9_i_i_reg <= main_287_scevgep_i9_i_i;
if (^reset !== 1'bX && ^(main_287_scevgep_i9_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_scevgep_i9_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %289 = getelementptr inbounds i8* %288, i32 1*/
begin
main_287_289 = main_287_288 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %289 = getelementptr inbounds i8* %288, i32 1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_289_reg <= main_287_289;
if (^reset !== 1'bX && ^(main_287_289) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_289_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %290 = load i8* %288, align 1, !tbaa !1*/
begin
main_287_290 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %287*/
/* %291 = zext i8 %290 to i32*/
begin
main_287_291 = main_287_290;
end
end
always @(*) begin
/* main: %287*/
/* %292 = add nsw i32 %291, %count.01.i.i.i*/
begin
main_287_292 = main_287_291 + main_287_count_01_i_i_i_reg;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %292 = add nsw i32 %291, %count.01.i.i.i*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
main_287_292_reg <= main_287_292;
if (^reset !== 1'bX && ^(main_287_292) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_292_reg"); $finish; end
end
end
always @(*) begin
/* main: %287*/
/* %exitcond.i.i.i = icmp eq i32 %tmp.i8.i.i, 16*/
begin
main_287_exitcond_i_i_i = main_287_tmp_i8_i_i == 32'd16;
end
end
always @(posedge clk) begin
/* main: %287*/
/* %exitcond.i.i.i = icmp eq i32 %tmp.i8.i.i, 16*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
main_287_exitcond_i_i_i_reg <= main_287_exitcond_i_i_i;
if (^reset !== 1'bX && ^(main_287_exitcond_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_exitcond_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %293*/
/* %295 = getelementptr inbounds [4 x i32]* @out_count_get_dht, i32 0, i32 %i_get_dht.2*/
begin
main_293_295 = `TAG_g_out_count_get_dht_a + 4 * main__lr_ph5_i_i_i_i_get_dht_2_reg;
end
end
always @(posedge clk) begin
/* main: %293*/
/* %295 = getelementptr inbounds [4 x i32]* @out_count_get_dht, i32 0, i32 %i_get_dht.2*/
if (cur_state == LEGUP_F_main_BB74_228)
begin
main_293_295_reg <= main_293_295;
if (^reset !== 1'bX && ^(main_293_295) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_293_295_reg"); $finish; end
end
end
always @(*) begin
/* main: %293*/
/* %296 = load i32* %295, align 4, !tbaa !0*/
begin
main_293_296 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %293*/
/* %297 = icmp eq i32 %292, %296*/
begin
main_293_297 = main_287_292_reg == main_293_296;
end
end
always @(*) begin
/* main: %298*/
/* %299 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_298_299 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %298*/
/* %300 = add nsw i32 %299, 1*/
begin
main_298_300 = main_298_299 + 32'd1;
end
end
always @(*) begin
/* main: %301*/
/* %302 = add nsw i32 %i_get_dht.2, 1*/
begin
main_301_302 = main__lr_ph5_i_i_i_i_get_dht_2_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %301*/
/* %302 = add nsw i32 %i_get_dht.2, 1*/
if (cur_state == LEGUP_F_main_BB76_235)
begin
main_301_302_reg <= main_301_302;
if (^reset !== 1'bX && ^(main_301_302) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_301_302_reg"); $finish; end
end
end
always @(*) begin
/* main: %301*/
/* %303 = icmp sgt i32 %292, 0*/
begin
main_301_303 = $signed(main_287_292_reg) > $signed(32'd0);
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %304 = phi i8* [ %305, %.lr.ph.i10.i.i ], [ %289, %301 ]*/
begin
main__lr_ph_i10_i_i_304 = main__lr_ph_i10_i_i_304_phi_temp;
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %i.13.i.i.i = phi i32 [ %308, %.lr.ph.i10.i.i ], [ 0, %301 ]*/
begin
main__lr_ph_i10_i_i_i_13_i_i_i = main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %scevgep8.i11.i.i = getelementptr i32* %p_xhtbl_huffval.0.i.i.i, i32 %i.13.i.i.i*/
begin
main__lr_ph_i10_i_i_scevgep8_i11_i_i = main_286_p_xhtbl_huffval_0_i_i_i_reg + 4 * main__lr_ph_i10_i_i_i_13_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %scevgep8.i11.i.i = getelementptr i32* %p_xhtbl_huffval.0.i.i.i, i32 %i.13.i.i.i*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
main__lr_ph_i10_i_i_scevgep8_i11_i_i_reg <= main__lr_ph_i10_i_i_scevgep8_i11_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_scevgep8_i11_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_scevgep8_i11_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %305 = getelementptr inbounds i8* %304, i32 1*/
begin
main__lr_ph_i10_i_i_305 = main__lr_ph_i10_i_i_304 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %305 = getelementptr inbounds i8* %304, i32 1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
main__lr_ph_i10_i_i_305_reg <= main__lr_ph_i10_i_i_305;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_305) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_305_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %306 = load i8* %304, align 1, !tbaa !1*/
begin
main__lr_ph_i10_i_i_306 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %307 = zext i8 %306 to i32*/
begin
main__lr_ph_i10_i_i_307 = main__lr_ph_i10_i_i_306;
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %308 = add nsw i32 %i.13.i.i.i, 1*/
begin
main__lr_ph_i10_i_i_308 = main__lr_ph_i10_i_i_i_13_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %308 = add nsw i32 %i.13.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
main__lr_ph_i10_i_i_308_reg <= main__lr_ph_i10_i_i_308;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_308) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_308_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i10.i.i*/
/* %exitcond7.i.i.i = icmp eq i32 %308, %292*/
begin
main__lr_ph_i10_i_i_exitcond7_i_i_i = main__lr_ph_i10_i_i_308 == main_287_292_reg;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %exitcond7.i.i.i = icmp eq i32 %308, %292*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
main__lr_ph_i10_i_i_exitcond7_i_i_i_reg <= main__lr_ph_i10_i_i_exitcond7_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_exitcond7_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_exitcond7_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %._crit_edge.i12.i.i*/
/* %ReadBuf.7 = phi i8* [ %289, %301 ], [ %305, %.lr.ph.i10.i.i ]*/
begin
main___crit_edge_i12_i_i_ReadBuf_7 = main___crit_edge_i12_i_i_ReadBuf_7_phi_temp;
end
end
always @(*) begin
/* main: %._crit_edge.i12.i.i*/
/* %309 = add i32 %length.04.i.i.i, -17*/
begin
main___crit_edge_i12_i_i_309 = main__lr_ph5_i_i_i_length_04_i_i_i_reg + -32'd17;
end
end
always @(*) begin
/* main: %._crit_edge.i12.i.i*/
/* %310 = sub i32 %309, %292*/
begin
main___crit_edge_i12_i_i_310 = main___crit_edge_i12_i_i_309 - main_287_292_reg;
end
end
always @(*) begin
/* main: %._crit_edge.i12.i.i*/
/* %311 = icmp sgt i32 %310, 16*/
begin
main___crit_edge_i12_i_i_311 = $signed(main___crit_edge_i12_i_i_310) > $signed(32'd16);
end
end
always @(*) begin
/* main: %312*/
/* %313 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
begin
main_312_313 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %312*/
/* %313 = getelementptr inbounds i8* %ReadBuf.2, i32 1*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
main_312_313_reg <= main_312_313;
if (^reset !== 1'bX && ^(main_312_313) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_312_313_reg"); $finish; end
end
end
always @(*) begin
/* main: %312*/
/* %314 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
begin
main_312_314 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %312*/
/* %315 = zext i8 %314 to i16*/
begin
main_312_315 = main_312_314;
end
end
always @(*) begin
/* main: %312*/
/* %316 = shl nuw i16 %315, 8*/
begin
main_312_316 = main_312_315 <<< 16'd8 % 16'd16;
end
end
always @(posedge clk) begin
/* main: %312*/
/* %316 = shl nuw i16 %315, 8*/
if (cur_state == LEGUP_F_main_BB79_242)
begin
main_312_316_reg <= main_312_316;
if (^reset !== 1'bX && ^(main_312_316) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_312_316_reg"); $finish; end
end
end
always @(*) begin
/* main: %312*/
/* %317 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
begin
main_312_317 = main_next_marker_exit_i_i_ReadBuf_2_reg + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %312*/
/* %317 = getelementptr inbounds i8* %ReadBuf.2, i32 2*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
main_312_317_reg <= main_312_317;
if (^reset !== 1'bX && ^(main_312_317) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_312_317_reg"); $finish; end
end
end
always @(*) begin
/* main: %312*/
/* %318 = load i8* %313, align 1, !tbaa !1*/
begin
main_312_318 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %312*/
/* %319 = zext i8 %318 to i16*/
begin
main_312_319 = main_312_318;
end
end
always @(*) begin
/* main: %312*/
/* %320 = or i16 %316, %319*/
begin
main_312_320 = main_312_316_reg | main_312_319;
end
end
always @(*) begin
/* main: %312*/
/* %321 = sext i16 %320 to i32*/
begin
main_312_321 = $signed(main_312_320);
end
end
always @(*) begin
/* main: %312*/
/* %322 = add nsw i32 %321, -2*/
begin
main_312_322 = main_312_321 + -32'd2;
end
end
always @(posedge clk) begin
/* main: %312*/
/* %322 = add nsw i32 %321, -2*/
if (cur_state == LEGUP_F_main_BB79_243)
begin
main_312_322_reg <= main_312_322;
if (^reset !== 1'bX && ^(main_312_322) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_312_322_reg"); $finish; end
end
end
always @(*) begin
/* main: %312*/
/* %324 = load i32* %5, align 4, !tbaa !0*/
begin
main_312_324 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %312*/
/* %325 = icmp eq i32 %322, %324*/
begin
main_312_325 = main_312_322_reg == main_312_324;
end
end
always @(*) begin
/* main: %326*/
/* %327 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_326_327 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %326*/
/* %328 = add nsw i32 %327, 1*/
begin
main_326_328 = main_326_327 + 32'd1;
end
end
always @(*) begin
/* main: %.preheader.i13.i.i*/
/* %329 = icmp sgt i32 %322, 0*/
begin
main__preheader_i13_i_i_329 = $signed(main_312_322_reg) > $signed(32'd0);
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2 = main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp;
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2 = main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp;
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB82_251) */
begin
main__lr_ph_i15_i_i_i_get_dqt_2 = main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_reg <= main__lr_ph_i15_i_i_i_get_dqt_2;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_i_get_dqt_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_reg"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_reg <= main__lr_ph_i15_i_i_i_get_dqt_2;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_i_get_dqt_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_reg"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_reg <= main__lr_ph_i15_i_i_i_get_dqt_2;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_i_get_dqt_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_reg"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_reg <= main__lr_ph_i15_i_i_i_get_dqt_2;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_i_get_dqt_2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %330 = phi i8* [ %ReadBuf.8, %.us-lcssa.us.i.i.i ], [ %317, %.preheader.i13.i.i ]*/
begin
main__lr_ph_i15_i_i_330 = main__lr_ph_i15_i_i_330_phi_temp;
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_length_02_i_i_i = main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp;
end
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB82_251) */
begin
main__lr_ph_i15_i_i_length_02_i_i_i = main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_length_02_i_i_i_reg <= main__lr_ph_i15_i_i_length_02_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_length_02_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_length_02_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_length_02_i_i_i_reg <= main__lr_ph_i15_i_i_length_02_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_length_02_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_length_02_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_length_02_i_i_i_reg <= main__lr_ph_i15_i_i_length_02_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_length_02_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_length_02_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %331 = getelementptr inbounds i8* %330, i32 1*/
begin
main__lr_ph_i15_i_i_331 = main__lr_ph_i15_i_i_330 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %331 = getelementptr inbounds i8* %330, i32 1*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_331_reg <= main__lr_ph_i15_i_i_331;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_331) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_331_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %332 = load i8* %330, align 1, !tbaa !1*/
begin
main__lr_ph_i15_i_i_332 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %333 = zext i8 %332 to i32*/
begin
main__lr_ph_i15_i_i_333 = main__lr_ph_i15_i_i_332;
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %334 = lshr i32 %333, 4*/
begin
main__lr_ph_i15_i_i_334 = main__lr_ph_i15_i_i_333 >>> 32'd4 % 32;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %334 = lshr i32 %333, 4*/
if (cur_state == LEGUP_F_main_BB82_253)
begin
main__lr_ph_i15_i_i_334_reg <= main__lr_ph_i15_i_i_334;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_334) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_334_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %335 = and i32 %333, 15*/
begin
main__lr_ph_i15_i_i_335 = main__lr_ph_i15_i_i_333 & 32'd15;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %335 = and i32 %333, 15*/
if (cur_state == LEGUP_F_main_BB82_253)
begin
main__lr_ph_i15_i_i_335_reg <= main__lr_ph_i15_i_i_335;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_335) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_335_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %338 = getelementptr inbounds [2 x i32]* @out_prec_get_dht, i32 0, i32 %i_get_dqt.2*/
begin
main__lr_ph_i15_i_i_338 = `TAG_g_out_prec_get_dht_a + 4 * main__lr_ph_i15_i_i_i_get_dqt_2;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %338 = getelementptr inbounds [2 x i32]* @out_prec_get_dht, i32 0, i32 %i_get_dqt.2*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
main__lr_ph_i15_i_i_338_reg <= main__lr_ph_i15_i_i_338;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_338) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_338_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %339 = load i32* %338, align 4, !tbaa !0*/
begin
main__lr_ph_i15_i_i_339 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %.lr.ph.i15.i.i*/
/* %340 = icmp eq i32 %334, %339*/
begin
main__lr_ph_i15_i_i_340 = main__lr_ph_i15_i_i_334_reg == main__lr_ph_i15_i_i_339;
end
end
always @(*) begin
/* main: %341*/
/* %342 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_341_342 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %341*/
/* %343 = add nsw i32 %342, 1*/
begin
main_341_343 = main_341_342 + 32'd1;
end
end
always @(*) begin
/* main: %344*/
/* %345 = getelementptr inbounds [2 x i32]* @out_num_get_dht, i32 0, i32 %i_get_dqt.2*/
begin
main_344_345 = `TAG_g_out_num_get_dht_a + 4 * main__lr_ph_i15_i_i_i_get_dqt_2_reg;
end
end
always @(*) begin
/* main: %344*/
/* %346 = load i32* %345, align 4, !tbaa !0*/
begin
main_344_346 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %344*/
/* %347 = icmp eq i32 %335, %346*/
begin
main_344_347 = main__lr_ph_i15_i_i_335_reg == main_344_346;
end
end
always @(*) begin
/* main: %348*/
/* %349 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_348_349 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %348*/
/* %350 = add nsw i32 %349, 1*/
begin
main_348_350 = main_348_349 + 32'd1;
end
end
always @(*) begin
/* main: %351*/
/* %352 = add nsw i32 %i_get_dqt.2, 1*/
begin
main_351_352 = main__lr_ph_i15_i_i_i_get_dqt_2_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %351*/
/* %352 = add nsw i32 %i_get_dqt.2, 1*/
if (cur_state == LEGUP_F_main_BB86_266)
begin
main_351_352_reg <= main_351_352;
if (^reset !== 1'bX && ^(main_351_352) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_351_352_reg"); $finish; end
end
end
always @(*) begin
/* main: %351*/
/* %353 = icmp eq i32 %334, 0*/
begin
main_351_353 = main__lr_ph_i15_i_i_334_reg == 32'd0;
end
end
always @(posedge clk) begin
/* main: %351*/
/* %353 = icmp eq i32 %334, 0*/
if (cur_state == LEGUP_F_main_BB86_266)
begin
main_351_353_reg <= main_351_353;
if (^reset !== 1'bX && ^(main_351_353) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_351_353_reg"); $finish; end
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %354 = phi i8* [ %355, %.split.us.i.i.i ], [ %331, %351 ]*/
begin
main__split_us_i_i_i_354 = main__split_us_i_i_i_354_phi_temp;
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %i.01.us.i.i.i = phi i32 [ %360, %.split.us.i.i.i ], [ 0, %351 ]*/
begin
main__split_us_i_i_i_i_01_us_i_i_i = main__split_us_i_i_i_i_01_us_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %scevgep.i16.i.i = getelementptr [64 x i32]* @izigzag_index, i32 0, i32 %i.01.us.i.i.i*/
begin
main__split_us_i_i_i_scevgep_i16_i_i = `TAG_g_izigzag_index_a + 4 * main__split_us_i_i_i_i_01_us_i_i_i;
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %scevgep.i16.i.i = getelementptr [64 x i32]* @izigzag_index, i32 0, i32 %i.01.us.i.i.i*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
main__split_us_i_i_i_scevgep_i16_i_i_reg <= main__split_us_i_i_i_scevgep_i16_i_i;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_scevgep_i16_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_scevgep_i16_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %355 = getelementptr inbounds i8* %354, i32 1*/
begin
main__split_us_i_i_i_355 = main__split_us_i_i_i_354 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %355 = getelementptr inbounds i8* %354, i32 1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
main__split_us_i_i_i_355_reg <= main__split_us_i_i_i_355;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_355) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_355_reg"); $finish; end
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %356 = load i8* %354, align 1, !tbaa !1*/
begin
main__split_us_i_i_i_356 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %357 = zext i8 %356 to i32*/
begin
main__split_us_i_i_i_357 = main__split_us_i_i_i_356;
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %357 = zext i8 %356 to i32*/
if (cur_state == LEGUP_F_main_BB87_269)
begin
main__split_us_i_i_i_357_reg <= main__split_us_i_i_i_357;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_357) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_357_reg"); $finish; end
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %358 = load i32* %scevgep.i16.i.i, align 4, !tbaa !0*/
begin
main__split_us_i_i_i_358 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %.sum.us.i.i.i = add i32 %358, 64*/
begin
main__split_us_i_i_i__sum_us_i_i_i = main__split_us_i_i_i_358 + 32'd64;
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %359 = getelementptr inbounds [4 x [64 x i32]]* @p_jinfo_quant_tbl_quantval, i32 0, i32 %335, i32 %.sum.us.i.i.i*/
begin
main__split_us_i_i_i_359 = `TAG_g_p_jinfo_quant_tbl_quantval_a + 256 * main__lr_ph_i15_i_i_335_reg + 4 * main__split_us_i_i_i__sum_us_i_i_i;
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %360 = add nsw i32 %i.01.us.i.i.i, 1*/
begin
main__split_us_i_i_i_360 = main__split_us_i_i_i_i_01_us_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %360 = add nsw i32 %i.01.us.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
main__split_us_i_i_i_360_reg <= main__split_us_i_i_i_360;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_360) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_360_reg"); $finish; end
end
end
always @(*) begin
/* main: %.split.us.i.i.i*/
/* %exitcond.i17.i.i = icmp eq i32 %360, 64*/
begin
main__split_us_i_i_i_exitcond_i17_i_i = main__split_us_i_i_i_360 == 32'd64;
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %exitcond.i17.i.i = icmp eq i32 %360, 64*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
main__split_us_i_i_i_exitcond_i17_i_i_reg <= main__split_us_i_i_i_exitcond_i17_i_i;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_exitcond_i17_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_exitcond_i17_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %361 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %331, %351 ]*/
begin
main___split_crit_edge_i_i_i_361 = main___split_crit_edge_i_i_i_361_phi_temp;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %i.01.i.i.i = phi i32 [ %372, %..split_crit_edge.i.i.i ], [ 0, %351 ]*/
begin
main___split_crit_edge_i_i_i_i_01_i_i_i = main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %scevgep4.i18.i.i = getelementptr [64 x i32]* @izigzag_index, i32 0, i32 %i.01.i.i.i*/
begin
main___split_crit_edge_i_i_i_scevgep4_i18_i_i = `TAG_g_izigzag_index_a + 4 * main___split_crit_edge_i_i_i_i_01_i_i_i;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %scevgep4.i18.i.i = getelementptr [64 x i32]* @izigzag_index, i32 0, i32 %i.01.i.i.i*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
main___split_crit_edge_i_i_i_scevgep4_i18_i_i_reg <= main___split_crit_edge_i_i_i_scevgep4_i18_i_i;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_scevgep4_i18_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_scevgep4_i18_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %362 = getelementptr inbounds i8* %361, i32 1*/
begin
main___split_crit_edge_i_i_i_362 = main___split_crit_edge_i_i_i_361 + 1 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %362 = getelementptr inbounds i8* %361, i32 1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
main___split_crit_edge_i_i_i_362_reg <= main___split_crit_edge_i_i_i_362;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_362) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_362_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %363 = load i8* %361, align 1, !tbaa !1*/
begin
main___split_crit_edge_i_i_i_363 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %364 = zext i8 %363 to i32*/
begin
main___split_crit_edge_i_i_i_364 = main___split_crit_edge_i_i_i_363;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %365 = shl nuw nsw i32 %364, 8*/
begin
main___split_crit_edge_i_i_i_365 = main___split_crit_edge_i_i_i_364 <<< 32'd8 % 32;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %365 = shl nuw nsw i32 %364, 8*/
if (cur_state == LEGUP_F_main_BB88_273)
begin
main___split_crit_edge_i_i_i_365_reg <= main___split_crit_edge_i_i_i_365;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_365) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_365_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %366 = getelementptr inbounds i8* %361, i32 2*/
begin
main___split_crit_edge_i_i_i_366 = main___split_crit_edge_i_i_i_361 + 1 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %366 = getelementptr inbounds i8* %361, i32 2*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
main___split_crit_edge_i_i_i_366_reg <= main___split_crit_edge_i_i_i_366;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_366) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_366_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %367 = load i8* %362, align 1, !tbaa !1*/
begin
main___split_crit_edge_i_i_i_367 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %368 = zext i8 %367 to i32*/
begin
main___split_crit_edge_i_i_i_368 = main___split_crit_edge_i_i_i_367;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %369 = or i32 %368, %365*/
begin
main___split_crit_edge_i_i_i_369 = main___split_crit_edge_i_i_i_368 | main___split_crit_edge_i_i_i_365_reg;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %369 = or i32 %368, %365*/
if (cur_state == LEGUP_F_main_BB88_274)
begin
main___split_crit_edge_i_i_i_369_reg <= main___split_crit_edge_i_i_i_369;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_369) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_369_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %370 = load i32* %scevgep4.i18.i.i, align 4, !tbaa !0*/
begin
main___split_crit_edge_i_i_i_370 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %.sum.i.i.i = add i32 %370, 64*/
begin
main___split_crit_edge_i_i_i__sum_i_i_i = main___split_crit_edge_i_i_i_370 + 32'd64;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %371 = getelementptr inbounds [4 x [64 x i32]]* @p_jinfo_quant_tbl_quantval, i32 0, i32 %335, i32 %.sum.i.i.i*/
begin
main___split_crit_edge_i_i_i_371 = `TAG_g_p_jinfo_quant_tbl_quantval_a + 256 * main__lr_ph_i15_i_i_335_reg + 4 * main___split_crit_edge_i_i_i__sum_i_i_i;
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %372 = add nsw i32 %i.01.i.i.i, 1*/
begin
main___split_crit_edge_i_i_i_372 = main___split_crit_edge_i_i_i_i_01_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %372 = add nsw i32 %i.01.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
main___split_crit_edge_i_i_i_372_reg <= main___split_crit_edge_i_i_i_372;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_372) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_372_reg"); $finish; end
end
end
always @(*) begin
/* main: %..split_crit_edge.i.i.i*/
/* %exitcond3.i.i.i = icmp eq i32 %372, 64*/
begin
main___split_crit_edge_i_i_i_exitcond3_i_i_i = main___split_crit_edge_i_i_i_372 == 32'd64;
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %exitcond3.i.i.i = icmp eq i32 %372, 64*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg <= main___split_crit_edge_i_i_i_exitcond3_i_i_i;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_exitcond3_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.us-lcssa.us.i.i.i*/
/* %ReadBuf.8 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %355, %.split.us.i.i.i ]*/
begin
main__us_lcssa_us_i_i_i_ReadBuf_8 = main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp;
end
end
always @(*) begin
/* main: %.us-lcssa.us.i.i.i*/
/* %..v.i.i.i = select i1 %353, i32 -65, i32 -129*/
begin
main__us_lcssa_us_i_i_i___v_i_i_i = (main_351_353_reg ? -32'd65 : -32'd129);
end
end
always @(*) begin
/* main: %.us-lcssa.us.i.i.i*/
/* %..i.i.i = add i32 %..v.i.i.i, %length.02.i.i.i*/
begin
main__us_lcssa_us_i_i_i___i_i_i = main__us_lcssa_us_i_i_i___v_i_i_i + main__lr_ph_i15_i_i_length_02_i_i_i_reg;
end
end
always @(*) begin
/* main: %.us-lcssa.us.i.i.i*/
/* %373 = icmp sgt i32 %..i.i.i, 0*/
begin
main__us_lcssa_us_i_i_i_373 = $signed(main__us_lcssa_us_i_i_i___i_i_i) > $signed(32'd0);
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0 = main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp;
end
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
else /* if (cur_state == LEGUP_F_main_BB90_277) */
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0 = main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg <= main_read_markers_exit_i_p_jinfo_jpeg_data_0;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_p_jinfo_jpeg_data_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg <= main_read_markers_exit_i_p_jinfo_jpeg_data_0;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_p_jinfo_jpeg_data_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg <= main_read_markers_exit_i_p_jinfo_jpeg_data_0;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_p_jinfo_jpeg_data_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
begin
main_read_markers_exit_i_374 = memory_controller_out[15:0];
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_279)
begin
main_read_markers_exit_i_374_reg <= main_read_markers_exit_i_374;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_374) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_374_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %375 = sext i16 %374 to i32*/
begin
main_read_markers_exit_i_375 = $signed(main_read_markers_exit_i_374);
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %376 = add nsw i32 %375, -1*/
begin
main_read_markers_exit_i_376 = main_read_markers_exit_i_375 + -32'd1;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %376 = add nsw i32 %375, -1*/
if (cur_state == LEGUP_F_main_BB90_279)
begin
main_read_markers_exit_i_376_reg <= main_read_markers_exit_i_376;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_376) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_376_reg"); $finish; end
end
end
always @(*) begin
main_read_markers_exit_i_377 = main_signed_divide_32_0;
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %377 = sdiv i32 %376, 8*/
if (cur_state == LEGUP_F_main_BB90_319)
begin
main_read_markers_exit_i_377_reg <= main_read_markers_exit_i_377;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_377_reg"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %377 = sdiv i32 %376, 8*/
if (cur_state == LEGUP_F_main_BB90_319)
begin
main_read_markers_exit_i_377_reg <= main_read_markers_exit_i_377;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_377) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_377_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %378 = add nsw i32 %377, 1*/
begin
main_read_markers_exit_i_378 = main_read_markers_exit_i_377_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %378 = add nsw i32 %377, 1*/
if (cur_state == LEGUP_F_main_BB90_327)
begin
main_read_markers_exit_i_378_reg <= main_read_markers_exit_i_378;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_378) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_378_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
begin
main_read_markers_exit_i_379 = memory_controller_out[15:0];
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_280)
begin
main_read_markers_exit_i_379_reg <= main_read_markers_exit_i_379;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_379) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_379_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %380 = sext i16 %379 to i32*/
begin
main_read_markers_exit_i_380 = $signed(main_read_markers_exit_i_379);
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %381 = add nsw i32 %380, -1*/
begin
main_read_markers_exit_i_381 = main_read_markers_exit_i_380 + -32'd1;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %381 = add nsw i32 %380, -1*/
if (cur_state == LEGUP_F_main_BB90_280)
begin
main_read_markers_exit_i_381_reg <= main_read_markers_exit_i_381;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_381) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_381_reg"); $finish; end
end
end
always @(*) begin
main_read_markers_exit_i_382 = main_signed_divide_32_0;
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %382 = sdiv i32 %381, 8*/
if (cur_state == LEGUP_F_main_BB90_320)
begin
main_read_markers_exit_i_382_reg <= main_read_markers_exit_i_382;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_382) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_382_reg"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %382 = sdiv i32 %381, 8*/
if (cur_state == LEGUP_F_main_BB90_320)
begin
main_read_markers_exit_i_382_reg <= main_read_markers_exit_i_382;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_382) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_382_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %383 = add nsw i32 %382, 1*/
begin
main_read_markers_exit_i_383 = main_read_markers_exit_i_382_reg + 32'd1;
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %384 = mul nsw i32 %383, %378*/
begin
main_read_markers_exit_i_384 = main_signed_multiply_32_0;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %384 = mul nsw i32 %383, %378*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
main_read_markers_exit_i_384_reg <= main_read_markers_exit_i_384;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_384) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_384_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
begin
main_read_markers_exit_i_385 = huff_make_dhuff_tb_return_val;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
main_read_markers_exit_i_385_reg <= main_read_markers_exit_i_385;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_385) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_385_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
begin
main_read_markers_exit_i_386 = huff_make_dhuff_tb_return_val;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
main_read_markers_exit_i_386_reg <= main_read_markers_exit_i_386;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_386) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_386_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
begin
main_read_markers_exit_i_387 = huff_make_dhuff_tb_return_val;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
main_read_markers_exit_i_387_reg <= main_read_markers_exit_i_387;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_387) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_387_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
begin
main_read_markers_exit_i_388 = huff_make_dhuff_tb_return_val;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
main_read_markers_exit_i_388_reg <= main_read_markers_exit_i_388;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_388) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_388_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 0, i32 0*/
if (reset) begin main_read_markers_exit_i_scevgep148_i_i = 0; end
begin
main_read_markers_exit_i_scevgep148_i_i = `TAG_main_0_HuffBuff_i_i_a;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 0, i32 0*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_scevgep148_i_i_reg <= main_read_markers_exit_i_scevgep148_i_i;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_scevgep148_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.1.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 1, i32 0*/
if (reset) begin main_read_markers_exit_i_scevgep148_1_i_i = 0; end
begin
main_read_markers_exit_i_scevgep148_1_i_i = `TAG_main_0_HuffBuff_i_i_a + 256 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.1.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 1, i32 0*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_scevgep148_1_i_i_reg <= main_read_markers_exit_i_scevgep148_1_i_i;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_1_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_scevgep148_1_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.2.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 2, i32 0*/
if (reset) begin main_read_markers_exit_i_scevgep148_2_i_i = 0; end
begin
main_read_markers_exit_i_scevgep148_2_i_i = `TAG_main_0_HuffBuff_i_i_a + 256 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %scevgep148.2.i.i = getelementptr [3 x [64 x i32]]* %HuffBuff.i.i, i32 0, i32 2, i32 0*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
main_read_markers_exit_i_scevgep148_2_i_i_reg <= main_read_markers_exit_i_scevgep148_2_i_i;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_scevgep148_2_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %389*/
/* %391 = icmp sgt i32 %384, 0*/
begin
main_389_391 = $signed(main_read_markers_exit_i_384_reg) > $signed(32'd0);
end
end
always @(*) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 0, i32 0*/
if (reset) begin main__preheader21_i_i_preheader_scevgep51_i_i = 0; end
begin
main__preheader21_i_i_preheader_scevgep51_i_i = `TAG_main_0_IDCTBuff_i_i_a;
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 0, i32 0*/
if (cur_state == LEGUP_F_main_BB92_356)
begin
main__preheader21_i_i_preheader_scevgep51_i_i_reg <= main__preheader21_i_i_preheader_scevgep51_i_i;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_preheader_scevgep51_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.1.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 0*/
if (reset) begin main__preheader21_i_i_preheader_scevgep51_1_i_i = 0; end
begin
main__preheader21_i_i_preheader_scevgep51_1_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.1.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 0*/
if (cur_state == LEGUP_F_main_BB92_356)
begin
main__preheader21_i_i_preheader_scevgep51_1_i_i_reg <= main__preheader21_i_i_preheader_scevgep51_1_i_i;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_1_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_preheader_scevgep51_1_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.2.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 0*/
if (reset) begin main__preheader21_i_i_preheader_scevgep51_2_i_i = 0; end
begin
main__preheader21_i_i_preheader_scevgep51_2_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i.preheader*/
/* %scevgep51.2.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 0*/
if (cur_state == LEGUP_F_main_BB92_356)
begin
main__preheader21_i_i_preheader_scevgep51_2_i_i_reg <= main__preheader21_i_i_preheader_scevgep51_2_i_i;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_preheader_scevgep51_2_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader21.i.i*/
/* %CurrentMCU.026.i.i = phi i32 [ %tmp143.i.i, %447 ], [ 0, %.preheader21.i.i.preheader ]*/
begin
main__preheader21_i_i_CurrentMCU_026_i_i = main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp;
end
end
always @(*) begin
/* main: %.preheader21.i.i*/
/* %tmp143.i.i = add i32 %CurrentMCU.026.i.i, 1*/
begin
main__preheader21_i_i_tmp143_i_i = main__preheader21_i_i_CurrentMCU_026_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* %tmp143.i.i = add i32 %CurrentMCU.026.i.i, 1*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
main__preheader21_i_i_tmp143_i_i_reg <= main__preheader21_i_i_tmp143_i_i;
if (^reset !== 1'bX && ^(main__preheader21_i_i_tmp143_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_tmp143_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_i_01_i_i1_i = main_392_i_01_i_i1_i_phi_temp;
end
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB94_366) */
begin
main_392_i_01_i_i1_i = main_392_i_01_i_i1_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_i_01_i_i1_i_reg <= main_392_i_01_i_i1_i;
if (^reset !== 1'bX && ^(main_392_i_01_i_i1_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_i_01_i_i1_i_reg"); $finish; end
end
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_i_01_i_i1_i_reg <= main_392_i_01_i_i1_i;
if (^reset !== 1'bX && ^(main_392_i_01_i_i1_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_i_01_i_i1_i_reg"); $finish; end
end
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_i_01_i_i1_i_reg <= main_392_i_01_i_i1_i;
if (^reset !== 1'bX && ^(main_392_i_01_i_i1_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_i_01_i_i1_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %scevgep3.i.i2.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 %i.01.i.i1.i*/
begin
main_392_scevgep3_i_i2_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd2 + 4 * main_392_i_01_i_i1_i;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %scevgep3.i.i2.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 %i.01.i.i1.i*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_scevgep3_i_i2_i_reg <= main_392_scevgep3_i_i2_i;
if (^reset !== 1'bX && ^(main_392_scevgep3_i_i2_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_scevgep3_i_i2_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %scevgep2.i.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 %i.01.i.i1.i*/
begin
main_392_scevgep2_i_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd1 + 4 * main_392_i_01_i_i1_i;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %scevgep2.i.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 %i.01.i.i1.i*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_scevgep2_i_i_i_reg <= main_392_scevgep2_i_i_i;
if (^reset !== 1'bX && ^(main_392_scevgep2_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_scevgep2_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %scevgep.i.i3.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 0, i32 %i.01.i.i1.i*/
begin
main_392_scevgep_i_i3_i = `TAG_main_0_IDCTBuff_i_i_a + 4 * main_392_i_01_i_i1_i;
end
end
always @(*) begin
/* main: %392*/
/* %scevgep6.i.i4.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 %i.01.i.i1.i*/
begin
main_392_scevgep6_i_i4_i = `TAG_g_rgb_buf_a + 256 * 32'd2 + 4 * main_392_i_01_i_i1_i;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %scevgep6.i.i4.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 %i.01.i.i1.i*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_scevgep6_i_i4_i_reg <= main_392_scevgep6_i_i4_i;
if (^reset !== 1'bX && ^(main_392_scevgep6_i_i4_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_scevgep6_i_i4_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %scevgep5.i.i5.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 %i.01.i.i1.i*/
begin
main_392_scevgep5_i_i5_i = `TAG_g_rgb_buf_a + 256 * 32'd1 + 4 * main_392_i_01_i_i1_i;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %scevgep5.i.i5.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 %i.01.i.i1.i*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_scevgep5_i_i5_i_reg <= main_392_scevgep5_i_i5_i;
if (^reset !== 1'bX && ^(main_392_scevgep5_i_i5_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_scevgep5_i_i5_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %scevgep4.i.i6.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 %i.01.i.i1.i*/
begin
main_392_scevgep4_i_i6_i = `TAG_g_rgb_buf_a + 4 * main_392_i_01_i_i1_i;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %scevgep4.i.i6.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 %i.01.i.i1.i*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
main_392_scevgep4_i_i6_i_reg <= main_392_scevgep4_i_i6_i;
if (^reset !== 1'bX && ^(main_392_scevgep4_i_i6_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_scevgep4_i_i6_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %393 = load i32* %scevgep.i.i3.i, align 4, !tbaa !0*/
begin
main_392_393 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %392*/
/* %394 = load i32* %scevgep2.i.i.i, align 4, !tbaa !0*/
begin
main_392_394 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %392*/
/* %395 = add nsw i32 %394, -128*/
begin
main_392_395 = main_392_394 + -32'd128;
end
end
always @(*) begin
/* main: %392*/
/* %396 = load i32* %scevgep3.i.i2.i, align 4, !tbaa !0*/
begin
main_392_396 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %392*/
/* %397 = add nsw i32 %396, -128*/
begin
main_392_397 = main_392_396 + -32'd128;
end
end
always @(*) begin
/* main: %392*/
/* %398 = shl nsw i32 %393, 8*/
begin
main_392_398 = main_392_393 <<< 32'd8 % 32;
end
end
always @(*) begin
/* main: %392*/
/* %399 = mul nsw i32 %397, 359*/
begin
main_392_399 = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %392*/
/* %400 = or i32 %398, 128*/
begin
main_392_400 = main_392_398 | 32'd128;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %400 = or i32 %398, 128*/
if (cur_state == LEGUP_F_main_BB94_368)
begin
main_392_400_reg <= main_392_400;
if (^reset !== 1'bX && ^(main_392_400) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_400_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %401 = add i32 %399, %400*/
begin
main_392_401 = main_392_399 + main_392_400_reg;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %401 = add i32 %399, %400*/
if (cur_state == LEGUP_F_main_BB94_370)
begin
main_392_401_reg <= main_392_401;
if (^reset !== 1'bX && ^(main_392_401) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_401_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %402 = ashr i32 %401, 8*/
begin
main_392_402 = $signed(main_392_401_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %402 = ashr i32 %401, 8*/
if (cur_state == LEGUP_F_main_BB94_371)
begin
main_392_402_reg <= main_392_402;
if (^reset !== 1'bX && ^(main_392_402) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_402_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %403 = mul i32 %395, -88*/
begin
main_392_403 = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %392*/
/* %404 = mul i32 %397, -182*/
begin
main_392_404 = main_signed_multiply_32_2;
end
end
always @(*) begin
/* main: %392*/
/* %405 = add i32 %403, %400*/
begin
main_392_405 = main_392_403 + main_392_400_reg;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %405 = add i32 %403, %400*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_392_405_reg <= main_392_405;
if (^reset !== 1'bX && ^(main_392_405) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_405_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %406 = add i32 %405, %404*/
begin
main_392_406 = main_392_405_reg + main_392_404;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %406 = add i32 %405, %404*/
if (cur_state == LEGUP_F_main_BB94_370)
begin
main_392_406_reg <= main_392_406;
if (^reset !== 1'bX && ^(main_392_406) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_406_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %407 = ashr i32 %406, 8*/
begin
main_392_407 = $signed(main_392_406_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %407 = ashr i32 %406, 8*/
if (cur_state == LEGUP_F_main_BB94_371)
begin
main_392_407_reg <= main_392_407;
if (^reset !== 1'bX && ^(main_392_407) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_407_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %408 = mul nsw i32 %395, 454*/
begin
main_392_408 = main_signed_multiply_32_2;
end
end
always @(*) begin
/* main: %392*/
/* %409 = add i32 %408, %400*/
begin
main_392_409 = main_392_408 + main_392_400_reg;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %409 = add i32 %408, %400*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_392_409_reg <= main_392_409;
if (^reset !== 1'bX && ^(main_392_409) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_409_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %410 = ashr i32 %409, 8*/
begin
main_392_410 = $signed(main_392_409_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %392*/
/* %410 = ashr i32 %409, 8*/
if (cur_state == LEGUP_F_main_BB94_370)
begin
main_392_410_reg <= main_392_410;
if (^reset !== 1'bX && ^(main_392_410) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_410_reg"); $finish; end
end
end
always @(*) begin
/* main: %392*/
/* %411 = icmp slt i32 %402, 0*/
begin
main_392_411 = $signed(main_392_402) < $signed(32'd0);
end
end
always @(*) begin
/* main: %412*/
/* %413 = icmp sgt i32 %402, 255*/
begin
main_412_413 = $signed(main_392_402_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB97_374)
begin
main_415_r_0_i_i_i = main_415_r_0_i_i_i_phi_temp;
end
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
else /* if (cur_state == LEGUP_F_main_BB97_374) */
begin
main_415_r_0_i_i_i = main_415_r_0_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB97_374)
begin
main_415_r_0_i_i_i_reg <= main_415_r_0_i_i_i;
if (^reset !== 1'bX && ^(main_415_r_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_reg"); $finish; end
end
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB97_374)
begin
main_415_r_0_i_i_i_reg <= main_415_r_0_i_i_i;
if (^reset !== 1'bX && ^(main_415_r_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_reg"); $finish; end
end
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB97_374)
begin
main_415_r_0_i_i_i_reg <= main_415_r_0_i_i_i;
if (^reset !== 1'bX && ^(main_415_r_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %415*/
/* %416 = icmp slt i32 %407, 0*/
begin
main_415_416 = $signed(main_392_407_reg) < $signed(32'd0);
end
end
always @(*) begin
/* main: %417*/
/* %418 = icmp sgt i32 %407, 255*/
begin
main_417_418 = $signed(main_392_407_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB100_377)
begin
main_420_g_0_i_i_i = main_420_g_0_i_i_i_phi_temp;
end
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
else /* if (cur_state == LEGUP_F_main_BB100_377) */
begin
main_420_g_0_i_i_i = main_420_g_0_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB100_377)
begin
main_420_g_0_i_i_i_reg <= main_420_g_0_i_i_i;
if (^reset !== 1'bX && ^(main_420_g_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_reg"); $finish; end
end
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB100_377)
begin
main_420_g_0_i_i_i_reg <= main_420_g_0_i_i_i;
if (^reset !== 1'bX && ^(main_420_g_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_reg"); $finish; end
end
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB100_377)
begin
main_420_g_0_i_i_i_reg <= main_420_g_0_i_i_i;
if (^reset !== 1'bX && ^(main_420_g_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %420*/
/* %421 = icmp slt i32 %410, 0*/
begin
main_420_421 = $signed(main_392_410_reg) < $signed(32'd0);
end
end
always @(*) begin
/* main: %422*/
/* %423 = icmp sgt i32 %410, 255*/
begin
main_422_423 = $signed(main_392_410_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_b_0_i_i_i = main_425_b_0_i_i_i_phi_temp;
end
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
else /* if (cur_state == LEGUP_F_main_BB103_380) */
begin
main_425_b_0_i_i_i = main_425_b_0_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_b_0_i_i_i_reg <= main_425_b_0_i_i_i;
if (^reset !== 1'bX && ^(main_425_b_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_reg"); $finish; end
end
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_b_0_i_i_i_reg <= main_425_b_0_i_i_i;
if (^reset !== 1'bX && ^(main_425_b_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_reg"); $finish; end
end
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_b_0_i_i_i_reg <= main_425_b_0_i_i_i;
if (^reset !== 1'bX && ^(main_425_b_0_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %425*/
/* %426 = add nsw i32 %i.01.i.i1.i, 1*/
begin
main_425_426 = main_392_i_01_i_i1_i_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %425*/
/* %426 = add nsw i32 %i.01.i.i1.i, 1*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_426_reg <= main_425_426;
if (^reset !== 1'bX && ^(main_425_426) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_426_reg"); $finish; end
end
end
always @(*) begin
/* main: %425*/
/* %exitcond53.i.i = icmp eq i32 %426, 64*/
begin
main_425_exitcond53_i_i = main_425_426 == 32'd64;
end
end
always @(posedge clk) begin
/* main: %425*/
/* %exitcond53.i.i = icmp eq i32 %426, 64*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
main_425_exitcond53_i_i_reg <= main_425_exitcond53_i_i;
if (^reset !== 1'bX && ^(main_425_exitcond53_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_exitcond53_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %427 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
begin
main_YuvToRgb_exit_loopexit_i_i_427 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %428 = sext i16 %427 to i32*/
begin
main_YuvToRgb_exit_loopexit_i_i_428 = $signed(main_YuvToRgb_exit_loopexit_i_i_427);
end
end
always @(posedge clk) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %428 = sext i16 %427 to i32*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
main_YuvToRgb_exit_loopexit_i_i_428_reg <= main_YuvToRgb_exit_loopexit_i_i_428;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i_428) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_YuvToRgb_exit_loopexit_i_i_428_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %429 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
begin
main_YuvToRgb_exit_loopexit_i_i_429 = memory_controller_out[15:0];
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %430 = sext i16 %429 to i32*/
begin
main_YuvToRgb_exit_loopexit_i_i_430 = $signed(main_YuvToRgb_exit_loopexit_i_i_429);
end
end
always @(posedge clk) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %430 = sext i16 %429 to i32*/
if (cur_state == LEGUP_F_main_BB104_386)
begin
main_YuvToRgb_exit_loopexit_i_i_430_reg <= main_YuvToRgb_exit_loopexit_i_i_430;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i_430) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_YuvToRgb_exit_loopexit_i_i_430_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %tmp120.i.i = shl nsw i32 %428, 3*/
begin
main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i = main_YuvToRgb_exit_loopexit_i_i_428 <<< 32'd3 % 32;
end
end
always @(posedge clk) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %tmp120.i.i = shl nsw i32 %428, 3*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i_reg <= main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
begin
main_YuvToRgb_exit_loopexit_i_i__pre_i_i = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_387)
begin
main_YuvToRgb_exit_loopexit_i_i__pre_i_i_reg <= main_YuvToRgb_exit_loopexit_i_i__pre_i_i;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i__pre_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_YuvToRgb_exit_loopexit_i_i__pre_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
begin
main_YuvToRgb_exit_loopexit_i_i_431 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_388)
begin
main_YuvToRgb_exit_loopexit_i_i_431_reg <= main_YuvToRgb_exit_loopexit_i_i_431;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i_431) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_YuvToRgb_exit_loopexit_i_i_431_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %433 = phi i32 [ %.pre.i.i, %YuvToRgb.exit.loopexit.i.i ], [ %446, %WriteBlock.exit.i.i ]*/
begin
main_432_433 = main_432_433_phi_temp;
end
end
always @(*) begin
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i = main_432_i_324_i_i_phi_temp;
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
else if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i = main_432_i_324_i_i_phi_temp;
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB105_389) */
begin
main_432_i_324_i_i = main_432_i_324_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i_reg <= main_432_i_324_i_i;
if (^reset !== 1'bX && ^(main_432_i_324_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_reg"); $finish; end
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i_reg <= main_432_i_324_i_i;
if (^reset !== 1'bX && ^(main_432_i_324_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_reg"); $finish; end
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i_reg <= main_432_i_324_i_i;
if (^reset !== 1'bX && ^(main_432_i_324_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_reg"); $finish; end
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_i_324_i_i_reg <= main_432_i_324_i_i;
if (^reset !== 1'bX && ^(main_432_i_324_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %scevgep139.i.i = getelementptr [3 x i32]* @OutData_comp_vpos, i32 0, i32 %i.324.i.i*/
begin
main_432_scevgep139_i_i = `TAG_g_OutData_comp_vpos_a + 4 * main_432_i_324_i_i;
end
end
always @(*) begin
/* main: %432*/
/* %tmp141.i.i = add i32 %i.324.i.i, 1*/
begin
main_432_tmp141_i_i = main_432_i_324_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %432*/
/* %tmp141.i.i = add i32 %i.324.i.i, 1*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_tmp141_i_i_reg <= main_432_tmp141_i_i;
if (^reset !== 1'bX && ^(main_432_tmp141_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_tmp141_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %scevgep142.i.i = getelementptr [3 x i32]* @OutData_comp_hpos, i32 0, i32 %tmp141.i.i*/
begin
main_432_scevgep142_i_i = `TAG_g_OutData_comp_hpos_a + 4 * main_432_tmp141_i_i;
end
end
always @(posedge clk) begin
/* main: %432*/
/* %scevgep142.i.i = getelementptr [3 x i32]* @OutData_comp_hpos, i32 0, i32 %tmp141.i.i*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_scevgep142_i_i_reg <= main_432_scevgep142_i_i;
if (^reset !== 1'bX && ^(main_432_scevgep142_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_scevgep142_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
begin
main_432_434 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB105_391)
begin
main_432_434_reg <= main_432_434;
if (^reset !== 1'bX && ^(main_432_434) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_434_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %435 = shl nsw i32 %434, 3*/
begin
main_432_435 = main_432_434 <<< 32'd3 % 32;
end
end
always @(posedge clk) begin
/* main: %432*/
/* %435 = shl nsw i32 %434, 3*/
if (cur_state == LEGUP_F_main_BB105_391)
begin
main_432_435_reg <= main_432_435;
if (^reset !== 1'bX && ^(main_432_435) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_435_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %436 = shl nsw i32 %433, 3*/
begin
main_432_436 = main_432_433 <<< 32'd3 % 32;
end
end
always @(posedge clk) begin
/* main: %432*/
/* %436 = shl nsw i32 %433, 3*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_436_reg <= main_432_436;
if (^reset !== 1'bX && ^(main_432_436) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_436_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %437 = icmp slt i32 %435, %430*/
begin
main_432_437 = $signed(main_432_435) < $signed(main_YuvToRgb_exit_loopexit_i_i_430_reg);
end
end
always @(*) begin
/* main: %432*/
/* %438 = icmp slt i32 %436, %428*/
begin
main_432_438 = $signed(main_432_436) < $signed(main_YuvToRgb_exit_loopexit_i_i_428_reg);
end
end
always @(posedge clk) begin
/* main: %432*/
/* %438 = icmp slt i32 %436, %428*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
main_432_438_reg <= main_432_438;
if (^reset !== 1'bX && ^(main_432_438) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_438_reg"); $finish; end
end
end
always @(*) begin
/* main: %432*/
/* %or.cond.i.i.i.i = and i1 %437, %438*/
begin
main_432_or_cond_i_i_i_i = main_432_437 & main_432_438_reg;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp61.i.i = add i32 %436, 8*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp61_i_i = main_432_436_reg + 32'd8;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp62149.i.i = or i32 %436, 1*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp62149_i_i = main_432_436_reg | 32'd1;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp63.i.i = icmp sgt i32 %tmp61.i.i, %tmp62149.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp63_i_i = $signed(main__lr_ph8_split_us_i_i_i_i_tmp61_i_i) > $signed(main__lr_ph8_split_us_i_i_i_i_tmp62149_i_i);
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %smax.i.i = select i1 %tmp63.i.i, i32 %tmp61.i.i, i32 %tmp62149.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_smax_i_i = (main__lr_ph8_split_us_i_i_i_i_tmp63_i_i ? main__lr_ph8_split_us_i_i_i_i_tmp61_i_i : main__lr_ph8_split_us_i_i_i_i_tmp62149_i_i);
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %smax.i.i = select i1 %tmp63.i.i, i32 %tmp61.i.i, i32 %tmp62149.i.i*/
if (cur_state == LEGUP_F_main_BB106_392)
begin
main__lr_ph8_split_us_i_i_i_i_smax_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_smax_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_smax_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_smax_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp64.i.i = sub i32 %436, %smax.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp64_i_i = main_432_436_reg - main__lr_ph8_split_us_i_i_i_i_smax_i_i_reg;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp67.i.i = sub i32 %436, %428*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp67_i_i = main_432_436_reg - main_YuvToRgb_exit_loopexit_i_i_428_reg;
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp67.i.i = sub i32 %436, %428*/
if (cur_state == LEGUP_F_main_BB106_392)
begin
main__lr_ph8_split_us_i_i_i_i_tmp67_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_tmp67_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_tmp67_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_tmp67_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp68.i.i = icmp ugt i32 %tmp64.i.i, %tmp67.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp68_i_i = main__lr_ph8_split_us_i_i_i_i_tmp64_i_i > main__lr_ph8_split_us_i_i_i_i_tmp67_i_i_reg;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %umax.i.i = select i1 %tmp68.i.i, i32 %tmp64.i.i, i32 %tmp67.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_umax_i_i = (main__lr_ph8_split_us_i_i_i_i_tmp68_i_i ? main__lr_ph8_split_us_i_i_i_i_tmp64_i_i : main__lr_ph8_split_us_i_i_i_i_tmp67_i_i_reg);
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %umax.i.i = select i1 %tmp68.i.i, i32 %tmp64.i.i, i32 %tmp67.i.i*/
if (cur_state == LEGUP_F_main_BB106_393)
begin
main__lr_ph8_split_us_i_i_i_i_umax_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_umax_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_umax_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_umax_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp69.i.i = sub i32 0, %umax.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp69_i_i = 32'd0 - main__lr_ph8_split_us_i_i_i_i_umax_i_i_reg;
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp69.i.i = sub i32 0, %umax.i.i*/
if (cur_state == LEGUP_F_main_BB106_394)
begin
main__lr_ph8_split_us_i_i_i_i_tmp69_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_tmp69_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_tmp69_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_tmp69_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp82.i.i = add i32 %435, 8*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp82_i_i = main_432_435_reg + 32'd8;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp83150.i.i = or i32 %435, 1*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp83150_i_i = main_432_435_reg | 32'd1;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp84.i.i = icmp sgt i32 %tmp82.i.i, %tmp83150.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp84_i_i = $signed(main__lr_ph8_split_us_i_i_i_i_tmp82_i_i) > $signed(main__lr_ph8_split_us_i_i_i_i_tmp83150_i_i);
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %smax85.i.i = select i1 %tmp84.i.i, i32 %tmp82.i.i, i32 %tmp83150.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_smax85_i_i = (main__lr_ph8_split_us_i_i_i_i_tmp84_i_i ? main__lr_ph8_split_us_i_i_i_i_tmp82_i_i : main__lr_ph8_split_us_i_i_i_i_tmp83150_i_i);
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %smax85.i.i = select i1 %tmp84.i.i, i32 %tmp82.i.i, i32 %tmp83150.i.i*/
if (cur_state == LEGUP_F_main_BB106_392)
begin
main__lr_ph8_split_us_i_i_i_i_smax85_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_smax85_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_smax85_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_smax85_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp86.i.i = sub i32 %435, %smax85.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp86_i_i = main_432_435_reg - main__lr_ph8_split_us_i_i_i_i_smax85_i_i_reg;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp89.i.i = sub i32 %435, %430*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp89_i_i = main_432_435_reg - main_YuvToRgb_exit_loopexit_i_i_430_reg;
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp89.i.i = sub i32 %435, %430*/
if (cur_state == LEGUP_F_main_BB106_392)
begin
main__lr_ph8_split_us_i_i_i_i_tmp89_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_tmp89_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_tmp89_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_tmp89_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp90.i.i = icmp ugt i32 %tmp86.i.i, %tmp89.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp90_i_i = main__lr_ph8_split_us_i_i_i_i_tmp86_i_i > main__lr_ph8_split_us_i_i_i_i_tmp89_i_i_reg;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %umax91.i.i = select i1 %tmp90.i.i, i32 %tmp86.i.i, i32 %tmp89.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_umax91_i_i = (main__lr_ph8_split_us_i_i_i_i_tmp90_i_i ? main__lr_ph8_split_us_i_i_i_i_tmp86_i_i : main__lr_ph8_split_us_i_i_i_i_tmp89_i_i_reg);
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %umax91.i.i = select i1 %tmp90.i.i, i32 %tmp86.i.i, i32 %tmp89.i.i*/
if (cur_state == LEGUP_F_main_BB106_393)
begin
main__lr_ph8_split_us_i_i_i_i_umax91_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_umax91_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_umax91_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_umax91_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp92.i.i = sub i32 0, %umax91.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp92_i_i = 32'd0 - main__lr_ph8_split_us_i_i_i_i_umax91_i_i_reg;
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp92.i.i = sub i32 0, %umax91.i.i*/
if (cur_state == LEGUP_F_main_BB106_394)
begin
main__lr_ph8_split_us_i_i_i_i_tmp92_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_tmp92_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_tmp92_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_tmp92_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp121.i.i = mul i32 %tmp120.i.i, %434*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp121_i_i = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp122.i.i = add i32 %436, %tmp121.i.i*/
begin
main__lr_ph8_split_us_i_i_i_i_tmp122_i_i = main_432_436_reg + main__lr_ph8_split_us_i_i_i_i_tmp121_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp122.i.i = add i32 %436, %tmp121.i.i*/
if (cur_state == LEGUP_F_main_BB106_392)
begin
main__lr_ph8_split_us_i_i_i_i_tmp122_i_i_reg <= main__lr_ph8_split_us_i_i_i_i_tmp122_i_i;
if (^reset !== 1'bX && ^(main__lr_ph8_split_us_i_i_i_i_tmp122_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph8_split_us_i_i_i_i_tmp122_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %439*/
/* %indvar.next18.i.i.i.i = add i32 %indvar17.i.i.i.i, 1*/
begin
main_439_indvar_next18_i_i_i_i = main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg + 32'd1;
end
end
always @(*) begin
/* main: %439*/
/* %exitcond93.i.i = icmp eq i32 %indvar.next18.i.i.i.i, %tmp92.i.i*/
begin
main_439_exitcond93_i_i = main_439_indvar_next18_i_i_i_i == main__lr_ph8_split_us_i_i_i_i_tmp92_i_i_reg;
end
end
always @(*) begin
/* main: %440*/
/* %indvar.i.i.i.i = phi i32 [ 0, %.lr.ph.us.i.i.i.i ], [ %indvar.next.i.i.i.i, %440 ]*/
begin
main_440_indvar_i_i_i_i = main_440_indvar_i_i_i_i_phi_temp;
end
end
always @(*) begin
/* main: %440*/
/* %tmp124.i.i = add i32 %tmp123.i.i, %indvar.i.i.i.i*/
begin
main_440_tmp124_i_i = main__lr_ph_us_i_i_i_i_tmp123_i_i_reg + main_440_indvar_i_i_i_i;
end
end
always @(*) begin
/* main: %440*/
/* %scevgep24.i.i.i.i = getelementptr [3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 %i.324.i.i, i32 %tmp124.i.i*/
begin
main_440_scevgep24_i_i_i_i = `TAG_g_OutData_comp_buf_a + 5310 * main_432_i_324_i_i_reg + 1 * main_440_tmp124_i_i;
end
end
always @(posedge clk) begin
/* main: %440*/
/* %scevgep24.i.i.i.i = getelementptr [3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 %i.324.i.i, i32 %tmp124.i.i*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
main_440_scevgep24_i_i_i_i_reg <= main_440_scevgep24_i_i_i_i;
if (^reset !== 1'bX && ^(main_440_scevgep24_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_440_scevgep24_i_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %440*/
/* %tmp137.i.i = add i32 %tmp136.i.i, %indvar.i.i.i.i*/
begin
main_440_tmp137_i_i = main__lr_ph_us_i_i_i_i_tmp136_i_i_reg + main_440_indvar_i_i_i_i;
end
end
always @(*) begin
/* main: %440*/
/* %.14.us.i.i.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 %i.324.i.i, i32 %tmp137.i.i*/
begin
main_440__14_us_i_i_i_i = `TAG_g_rgb_buf_a + 256 * main_432_i_324_i_i_reg + 4 * main_440_tmp137_i_i;
end
end
always @(*) begin
/* main: %440*/
/* %441 = load i32* %.14.us.i.i.i.i, align 4, !tbaa !0*/
begin
main_440_441 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %440*/
/* %442 = trunc i32 %441 to i8*/
begin
main_440_442 = main_440_441[7:0];
end
end
always @(*) begin
/* main: %440*/
/* %indvar.next.i.i.i.i = add i32 %indvar.i.i.i.i, 1*/
begin
main_440_indvar_next_i_i_i_i = main_440_indvar_i_i_i_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %440*/
/* %indvar.next.i.i.i.i = add i32 %indvar.i.i.i.i, 1*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
main_440_indvar_next_i_i_i_i_reg <= main_440_indvar_next_i_i_i_i;
if (^reset !== 1'bX && ^(main_440_indvar_next_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_440_indvar_next_i_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %440*/
/* %exitcond70.i.i = icmp eq i32 %indvar.next.i.i.i.i, %tmp69.i.i*/
begin
main_440_exitcond70_i_i = main_440_indvar_next_i_i_i_i == main__lr_ph8_split_us_i_i_i_i_tmp69_i_i_reg;
end
end
always @(posedge clk) begin
/* main: %440*/
/* %exitcond70.i.i = icmp eq i32 %indvar.next.i.i.i.i, %tmp69.i.i*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
main_440_exitcond70_i_i_reg <= main_440_exitcond70_i_i;
if (^reset !== 1'bX && ^(main_440_exitcond70_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_440_exitcond70_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i = main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp;
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB109_399) */
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i = main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg <= main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg <= main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg"); $finish; end
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg <= main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp118.i.i = mul i32 %428, %indvar17.i.i.i.i*/
begin
main__lr_ph_us_i_i_i_i_tmp118_i_i = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp123.i.i = add i32 %tmp122.i.i, %tmp118.i.i*/
begin
main__lr_ph_us_i_i_i_i_tmp123_i_i = main__lr_ph8_split_us_i_i_i_i_tmp122_i_i_reg + main__lr_ph_us_i_i_i_i_tmp118_i_i;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp123.i.i = add i32 %tmp122.i.i, %tmp118.i.i*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_tmp123_i_i_reg <= main__lr_ph_us_i_i_i_i_tmp123_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_us_i_i_i_i_tmp123_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_tmp123_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp136.i.i = mul i32 %indvar17.i.i.i.i, %tmp69.i.i*/
begin
main__lr_ph_us_i_i_i_i_tmp136_i_i = main_signed_multiply_32_0;
end
end
always @(posedge clk) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp136.i.i = mul i32 %indvar17.i.i.i.i, %tmp69.i.i*/
if (cur_state == LEGUP_F_main_BB109_399)
begin
main__lr_ph_us_i_i_i_i_tmp136_i_i_reg <= main__lr_ph_us_i_i_i_i_tmp136_i_i;
if (^reset !== 1'bX && ^(main__lr_ph_us_i_i_i_i_tmp136_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_tmp136_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %WriteOneBlock.exit.i.i.i*/
/* %443 = load i32* %scevgep142.i.i, align 4, !tbaa !0*/
begin
main_WriteOneBlock_exit_i_i_i_443 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %WriteOneBlock.exit.i.i.i*/
/* %444 = icmp slt i32 %443, %431*/
begin
main_WriteOneBlock_exit_i_i_i_444 = $signed(main_WriteOneBlock_exit_i_i_i_443) < $signed(main_YuvToRgb_exit_loopexit_i_i_431_reg);
end
end
always @(*) begin
/* main: %WriteBlock.exit.i.i*/
/* %446 = phi i32 [ %443, %WriteOneBlock.exit.i.i.i ], [ 0, %445 ]*/
begin
main_WriteBlock_exit_i_i_446 = main_WriteBlock_exit_i_i_446_phi_temp;
end
end
always @(*) begin
/* main: %WriteBlock.exit.i.i*/
/* %exitcond116.i.i = icmp eq i32 %tmp141.i.i, 3*/
begin
main_WriteBlock_exit_i_i_exitcond116_i_i = main_432_tmp141_i_i_reg == 32'd3;
end
end
always @(*) begin
/* main: %447*/
/* %448 = icmp slt i32 %tmp143.i.i, %384*/
begin
main_447_448 = $signed(main__preheader21_i_i_tmp143_i_i_reg) < $signed(main_read_markers_exit_i_384_reg);
end
end
always @(*) begin
/* main: %449*/
/* %451 = icmp sgt i32 %384, 0*/
begin
main_449_451 = $signed(main_read_markers_exit_i_384_reg) > $signed(32'd0);
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %452 = getelementptr inbounds [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 4, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_452 = 0; end
begin
main__preheader_lr_ph_i_i_452 = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd4;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %452 = getelementptr inbounds [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 4, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_452_reg <= main__preheader_lr_ph_i_i_452;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_452) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_452_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %453 = getelementptr inbounds [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 5, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_453 = 0; end
begin
main__preheader_lr_ph_i_i_453 = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd5;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %453 = getelementptr inbounds [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 5, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_453_reg <= main__preheader_lr_ph_i_i_453;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_453) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_453_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.i8.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 0, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_scevgep_i8_i = 0; end
begin
main__preheader_lr_ph_i_i_scevgep_i8_i = `TAG_main_0_IDCTBuff_i_i_a;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.i8.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 0, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_scevgep_i8_i_reg <= main__preheader_lr_ph_i_i_scevgep_i8_i;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_i8_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_scevgep_i8_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.1.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_scevgep_1_i_i = 0; end
begin
main__preheader_lr_ph_i_i_scevgep_1_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.1.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 1, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_scevgep_1_i_i_reg <= main__preheader_lr_ph_i_i_scevgep_1_i_i;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_1_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_scevgep_1_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.2.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_scevgep_2_i_i = 0; end
begin
main__preheader_lr_ph_i_i_scevgep_2_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd2;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.2.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 2, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_scevgep_2_i_i_reg <= main__preheader_lr_ph_i_i_scevgep_2_i_i;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_scevgep_2_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.3.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 3, i32 0*/
if (reset) begin main__preheader_lr_ph_i_i_scevgep_3_i_i = 0; end
begin
main__preheader_lr_ph_i_i_scevgep_3_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd3;
end
end
always @(posedge clk) begin
/* main: %.preheader.lr.ph.i.i*/
/* %scevgep.3.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 3, i32 0*/
if (cur_state == LEGUP_F_main_BB115_407)
begin
main__preheader_lr_ph_i_i_scevgep_3_i_i_reg <= main__preheader_lr_ph_i_i_scevgep_3_i_i;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_3_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_lr_ph_i_i_scevgep_3_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
main__preheader_i_i_indvar_i7_i = main__preheader_i_i_indvar_i7_i_phi_temp;
end
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB116_408) */
begin
main__preheader_i_i_indvar_i7_i = main__preheader_i_i_indvar_i7_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
main__preheader_i_i_indvar_i7_i_reg <= main__preheader_i_i_indvar_i7_i;
if (^reset !== 1'bX && ^(main__preheader_i_i_indvar_i7_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_indvar_i7_i_reg"); $finish; end
end
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
main__preheader_i_i_indvar_i7_i_reg <= main__preheader_i_i_indvar_i7_i;
if (^reset !== 1'bX && ^(main__preheader_i_i_indvar_i7_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_indvar_i7_i_reg"); $finish; end
end
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
main__preheader_i_i_indvar_i7_i_reg <= main__preheader_i_i_indvar_i7_i;
if (^reset !== 1'bX && ^(main__preheader_i_i_indvar_i7_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_indvar_i7_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.i.i*/
/* %tmp48.i.i = shl i32 %indvar.i7.i, 2*/
begin
main__preheader_i_i_tmp48_i_i = main__preheader_i_i_indvar_i7_i <<< 32'd2 % 32;
end
end
always @(*) begin
/* main: %.preheader.i.i*/
/* %tmp49.i.i = add i32 %tmp48.i.i, 4*/
begin
main__preheader_i_i_tmp49_i_i = main__preheader_i_i_tmp48_i_i + 32'd4;
end
end
always @(posedge clk) begin
/* main: %.preheader.i.i*/
/* %tmp49.i.i = add i32 %tmp48.i.i, 4*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
main__preheader_i_i_tmp49_i_i_reg <= main__preheader_i_i_tmp49_i_i;
if (^reset !== 1'bX && ^(main__preheader_i_i_tmp49_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_tmp49_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
else if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB117_426) */
begin
main__preheader16_i_i_i_517_i_i = main__preheader16_i_i_i_517_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426)
begin
main__preheader16_i_i_i_517_i_i_reg <= main__preheader16_i_i_i_517_i_i;
if (^reset !== 1'bX && ^(main__preheader16_i_i_i_517_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_i_01_i2_i_i = main_454_i_01_i2_i_i_phi_temp;
end
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
else /* if (cur_state == LEGUP_F_main_BB118_427) */
begin
main_454_i_01_i2_i_i = main_454_i_01_i2_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_i_01_i2_i_i_reg <= main_454_i_01_i2_i_i;
if (^reset !== 1'bX && ^(main_454_i_01_i2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_i_01_i2_i_i_reg"); $finish; end
end
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_i_01_i2_i_i_reg <= main_454_i_01_i2_i_i;
if (^reset !== 1'bX && ^(main_454_i_01_i2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_i_01_i2_i_i_reg"); $finish; end
end
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_i_01_i2_i_i_reg <= main_454_i_01_i2_i_i;
if (^reset !== 1'bX && ^(main_454_i_01_i2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_i_01_i2_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %scevgep4.i6.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 0, i32 %i.01.i2.i.i*/
begin
main_454_scevgep4_i6_i_i = `TAG_g_rgb_buf_a + 768 * main__preheader16_i_i_i_517_i_i_reg + 4 * main_454_i_01_i2_i_i;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %scevgep4.i6.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 0, i32 %i.01.i2.i.i*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_scevgep4_i6_i_i_reg <= main_454_scevgep4_i6_i_i;
if (^reset !== 1'bX && ^(main_454_scevgep4_i6_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_scevgep4_i6_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %scevgep5.i7.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 1, i32 %i.01.i2.i.i*/
begin
main_454_scevgep5_i7_i_i = `TAG_g_rgb_buf_a + 768 * main__preheader16_i_i_i_517_i_i_reg + 256 * 32'd1 + 4 * main_454_i_01_i2_i_i;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %scevgep5.i7.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 1, i32 %i.01.i2.i.i*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_scevgep5_i7_i_i_reg <= main_454_scevgep5_i7_i_i;
if (^reset !== 1'bX && ^(main_454_scevgep5_i7_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_scevgep5_i7_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %scevgep6.i8.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 2, i32 %i.01.i2.i.i*/
begin
main_454_scevgep6_i8_i_i = `TAG_g_rgb_buf_a + 768 * main__preheader16_i_i_i_517_i_i_reg + 256 * 32'd2 + 4 * main_454_i_01_i2_i_i;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %scevgep6.i8.i.i = getelementptr [4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 %i.517.i.i, i32 2, i32 %i.01.i2.i.i*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_scevgep6_i8_i_i_reg <= main_454_scevgep6_i8_i_i;
if (^reset !== 1'bX && ^(main_454_scevgep6_i8_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_scevgep6_i8_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %scevgep.i3.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 %i.517.i.i, i32 %i.01.i2.i.i*/
begin
main_454_scevgep_i3_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * main__preheader16_i_i_i_517_i_i_reg + 4 * main_454_i_01_i2_i_i;
end
end
always @(*) begin
/* main: %454*/
/* %scevgep3.i5.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 5, i32 %i.01.i2.i.i*/
begin
main_454_scevgep3_i5_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd5 + 4 * main_454_i_01_i2_i_i;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %scevgep3.i5.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 5, i32 %i.01.i2.i.i*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_scevgep3_i5_i_i_reg <= main_454_scevgep3_i5_i_i;
if (^reset !== 1'bX && ^(main_454_scevgep3_i5_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_scevgep3_i5_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %scevgep2.i4.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 4, i32 %i.01.i2.i.i*/
begin
main_454_scevgep2_i4_i_i = `TAG_main_0_IDCTBuff_i_i_a + 256 * 32'd4 + 4 * main_454_i_01_i2_i_i;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %scevgep2.i4.i.i = getelementptr [6 x [64 x i32]]* %IDCTBuff.i.i, i32 0, i32 4, i32 %i.01.i2.i.i*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
main_454_scevgep2_i4_i_i_reg <= main_454_scevgep2_i4_i_i;
if (^reset !== 1'bX && ^(main_454_scevgep2_i4_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_scevgep2_i4_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %455 = load i32* %scevgep.i3.i.i, align 4, !tbaa !0*/
begin
main_454_455 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %454*/
/* %456 = load i32* %scevgep2.i4.i.i, align 4, !tbaa !0*/
begin
main_454_456 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %454*/
/* %457 = add nsw i32 %456, -128*/
begin
main_454_457 = main_454_456 + -32'd128;
end
end
always @(*) begin
/* main: %454*/
/* %458 = load i32* %scevgep3.i5.i.i, align 4, !tbaa !0*/
begin
main_454_458 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %454*/
/* %459 = add nsw i32 %458, -128*/
begin
main_454_459 = main_454_458 + -32'd128;
end
end
always @(*) begin
/* main: %454*/
/* %460 = shl nsw i32 %455, 8*/
begin
main_454_460 = main_454_455 <<< 32'd8 % 32;
end
end
always @(*) begin
/* main: %454*/
/* %461 = mul nsw i32 %459, 359*/
begin
main_454_461 = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %454*/
/* %462 = or i32 %460, 128*/
begin
main_454_462 = main_454_460 | 32'd128;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %462 = or i32 %460, 128*/
if (cur_state == LEGUP_F_main_BB118_429)
begin
main_454_462_reg <= main_454_462;
if (^reset !== 1'bX && ^(main_454_462) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_462_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %463 = add i32 %461, %462*/
begin
main_454_463 = main_454_461 + main_454_462_reg;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %463 = add i32 %461, %462*/
if (cur_state == LEGUP_F_main_BB118_431)
begin
main_454_463_reg <= main_454_463;
if (^reset !== 1'bX && ^(main_454_463) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_463_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %464 = ashr i32 %463, 8*/
begin
main_454_464 = $signed(main_454_463_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %464 = ashr i32 %463, 8*/
if (cur_state == LEGUP_F_main_BB118_432)
begin
main_454_464_reg <= main_454_464;
if (^reset !== 1'bX && ^(main_454_464) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_464_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %465 = mul i32 %457, -88*/
begin
main_454_465 = main_signed_multiply_32_1;
end
end
always @(*) begin
/* main: %454*/
/* %466 = mul i32 %459, -182*/
begin
main_454_466 = main_signed_multiply_32_2;
end
end
always @(*) begin
/* main: %454*/
/* %467 = add i32 %465, %462*/
begin
main_454_467 = main_454_465 + main_454_462_reg;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %467 = add i32 %465, %462*/
if (cur_state == LEGUP_F_main_BB118_430)
begin
main_454_467_reg <= main_454_467;
if (^reset !== 1'bX && ^(main_454_467) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_467_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %468 = add i32 %467, %466*/
begin
main_454_468 = main_454_467_reg + main_454_466;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %468 = add i32 %467, %466*/
if (cur_state == LEGUP_F_main_BB118_431)
begin
main_454_468_reg <= main_454_468;
if (^reset !== 1'bX && ^(main_454_468) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_468_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %469 = ashr i32 %468, 8*/
begin
main_454_469 = $signed(main_454_468_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %469 = ashr i32 %468, 8*/
if (cur_state == LEGUP_F_main_BB118_432)
begin
main_454_469_reg <= main_454_469;
if (^reset !== 1'bX && ^(main_454_469) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_469_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %470 = mul nsw i32 %457, 454*/
begin
main_454_470 = main_signed_multiply_32_2;
end
end
always @(*) begin
/* main: %454*/
/* %471 = add i32 %470, %462*/
begin
main_454_471 = main_454_470 + main_454_462_reg;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %471 = add i32 %470, %462*/
if (cur_state == LEGUP_F_main_BB118_430)
begin
main_454_471_reg <= main_454_471;
if (^reset !== 1'bX && ^(main_454_471) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_471_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %472 = ashr i32 %471, 8*/
begin
main_454_472 = $signed(main_454_471_reg) >>> 32'd8;
end
end
always @(posedge clk) begin
/* main: %454*/
/* %472 = ashr i32 %471, 8*/
if (cur_state == LEGUP_F_main_BB118_431)
begin
main_454_472_reg <= main_454_472;
if (^reset !== 1'bX && ^(main_454_472) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_472_reg"); $finish; end
end
end
always @(*) begin
/* main: %454*/
/* %473 = icmp slt i32 %464, 0*/
begin
main_454_473 = $signed(main_454_464) < $signed(32'd0);
end
end
always @(*) begin
/* main: %474*/
/* %475 = icmp sgt i32 %464, 255*/
begin
main_474_475 = $signed(main_454_464_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB121_435)
begin
main_477_r_0_i9_i_i = main_477_r_0_i9_i_i_phi_temp;
end
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
else /* if (cur_state == LEGUP_F_main_BB121_435) */
begin
main_477_r_0_i9_i_i = main_477_r_0_i9_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB121_435)
begin
main_477_r_0_i9_i_i_reg <= main_477_r_0_i9_i_i;
if (^reset !== 1'bX && ^(main_477_r_0_i9_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_reg"); $finish; end
end
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB121_435)
begin
main_477_r_0_i9_i_i_reg <= main_477_r_0_i9_i_i;
if (^reset !== 1'bX && ^(main_477_r_0_i9_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_reg"); $finish; end
end
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB121_435)
begin
main_477_r_0_i9_i_i_reg <= main_477_r_0_i9_i_i;
if (^reset !== 1'bX && ^(main_477_r_0_i9_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %477*/
/* %478 = icmp slt i32 %469, 0*/
begin
main_477_478 = $signed(main_454_469_reg) < $signed(32'd0);
end
end
always @(*) begin
/* main: %479*/
/* %480 = icmp sgt i32 %469, 255*/
begin
main_479_480 = $signed(main_454_469_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB124_438)
begin
main_482_g_0_i10_i_i = main_482_g_0_i10_i_i_phi_temp;
end
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
else /* if (cur_state == LEGUP_F_main_BB124_438) */
begin
main_482_g_0_i10_i_i = main_482_g_0_i10_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB124_438)
begin
main_482_g_0_i10_i_i_reg <= main_482_g_0_i10_i_i;
if (^reset !== 1'bX && ^(main_482_g_0_i10_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_reg"); $finish; end
end
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB124_438)
begin
main_482_g_0_i10_i_i_reg <= main_482_g_0_i10_i_i;
if (^reset !== 1'bX && ^(main_482_g_0_i10_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_reg"); $finish; end
end
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB124_438)
begin
main_482_g_0_i10_i_i_reg <= main_482_g_0_i10_i_i;
if (^reset !== 1'bX && ^(main_482_g_0_i10_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %482*/
/* %483 = icmp slt i32 %472, 0*/
begin
main_482_483 = $signed(main_454_472_reg) < $signed(32'd0);
end
end
always @(*) begin
/* main: %484*/
/* %485 = icmp sgt i32 %472, 255*/
begin
main_484_485 = $signed(main_454_472_reg) > $signed(32'd255);
end
end
always @(*) begin
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_b_0_i11_i_i = main_487_b_0_i11_i_i_phi_temp;
end
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
else /* if (cur_state == LEGUP_F_main_BB127_441) */
begin
main_487_b_0_i11_i_i = main_487_b_0_i11_i_i_phi_temp;
end
end
always @(posedge clk) begin
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_b_0_i11_i_i_reg <= main_487_b_0_i11_i_i;
if (^reset !== 1'bX && ^(main_487_b_0_i11_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_reg"); $finish; end
end
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_b_0_i11_i_i_reg <= main_487_b_0_i11_i_i;
if (^reset !== 1'bX && ^(main_487_b_0_i11_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_reg"); $finish; end
end
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_b_0_i11_i_i_reg <= main_487_b_0_i11_i_i;
if (^reset !== 1'bX && ^(main_487_b_0_i11_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %487*/
/* %488 = add nsw i32 %i.01.i2.i.i, 1*/
begin
main_487_488 = main_454_i_01_i2_i_i_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %487*/
/* %488 = add nsw i32 %i.01.i2.i.i, 1*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_488_reg <= main_487_488;
if (^reset !== 1'bX && ^(main_487_488) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_488_reg"); $finish; end
end
end
always @(*) begin
/* main: %487*/
/* %exitcond.i.i = icmp eq i32 %488, 64*/
begin
main_487_exitcond_i_i = main_487_488 == 32'd64;
end
end
always @(posedge clk) begin
/* main: %487*/
/* %exitcond.i.i = icmp eq i32 %488, 64*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
main_487_exitcond_i_i_reg <= main_487_exitcond_i_i;
if (^reset !== 1'bX && ^(main_487_exitcond_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_exitcond_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %YuvToRgb.exit13.i.i*/
/* %489 = add nsw i32 %i.517.i.i, 1*/
begin
main_YuvToRgb_exit13_i_i_489 = main__preheader16_i_i_i_517_i_i_reg + 32'd1;
end
end
always @(*) begin
/* main: %YuvToRgb.exit13.i.i*/
/* %exitcond35.i.i = icmp eq i32 %489, 4*/
begin
main_YuvToRgb_exit13_i_i_exitcond35_i_i = main_YuvToRgb_exit13_i_i_489 == 32'd4;
end
end
always @(*) begin
/* main: %.loopexit.i.i*/
/* %490 = icmp slt i32 %tmp49.i.i, %384*/
begin
main__loopexit_i_i_490 = $signed(main__preheader_i_i_tmp49_i_i_reg) < $signed(main_read_markers_exit_i_384_reg);
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* %490 = icmp slt i32 %tmp49.i.i, %384*/
if (cur_state == LEGUP_function_call_447)
begin
main__loopexit_i_i_490_reg <= main__loopexit_i_i_490;
if (^reset !== 1'bX && ^(main__loopexit_i_i_490) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_490_reg"); $finish; end
end
end
always @(*) begin
/* main: %.loopexit.i.i*/
/* %indvar.next.i.i = add i32 %indvar.i7.i, 1*/
begin
main__loopexit_i_i_indvar_next_i_i = main__preheader_i_i_indvar_i7_i_reg + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* %indvar.next.i.i = add i32 %indvar.i7.i, 1*/
if (cur_state == LEGUP_function_call_447)
begin
main__loopexit_i_i_indvar_next_i_i_reg <= main__loopexit_i_i_indvar_next_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_i_indvar_next_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_indvar_next_i_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %decode_start.exit.i*/
/* %main_result.promoted3.i = load i32* @main_result, align 4*/
begin
main_decode_start_exit_i_main_result_promoted3_i = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_492 = main_491_492_phi_temp;
end
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
else /* if (cur_state == LEGUP_F_main_BB131_457) */
begin
main_491_492 = main_491_492_phi_temp;
end
end
always @(posedge clk) begin
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_492_reg <= main_491_492;
if (^reset !== 1'bX && ^(main_491_492) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_492_reg"); $finish; end
end
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_492_reg <= main_491_492;
if (^reset !== 1'bX && ^(main_491_492) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_492_reg"); $finish; end
end
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_492_reg <= main_491_492;
if (^reset !== 1'bX && ^(main_491_492) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_492_reg"); $finish; end
end
end
always @(*) begin
/* main: %491*/
/* %j.01.i = phi i32 [ 0, %decode_start.exit.i ], [ %498, %491 ]*/
begin
main_491_j_01_i = main_491_j_01_i_phi_temp;
end
end
always @(*) begin
/* main: %491*/
/* %scevgep7.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 0, i32 %j.01.i*/
begin
main_491_scevgep7_i = `TAG_g_hana_bmp_a + 1 * main_491_j_01_i;
end
end
always @(posedge clk) begin
/* main: %491*/
/* %scevgep7.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 0, i32 %j.01.i*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_scevgep7_i_reg <= main_491_scevgep7_i;
if (^reset !== 1'bX && ^(main_491_scevgep7_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_scevgep7_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %491*/
/* %scevgep.i = getelementptr [3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 %j.01.i*/
begin
main_491_scevgep_i = `TAG_g_OutData_comp_buf_a + 1 * main_491_j_01_i;
end
end
always @(*) begin
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
begin
main_491_493 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_459)
begin
main_491_493_reg <= main_491_493;
if (^reset !== 1'bX && ^(main_491_493) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_493_reg"); $finish; end
end
end
always @(*) begin
/* main: %491*/
/* %494 = load i8* %scevgep7.i, align 1, !tbaa !1*/
begin
main_491_494 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %491*/
/* %495 = icmp eq i8 %493, %494*/
begin
main_491_495 = main_491_493_reg == main_491_494;
end
end
always @(*) begin
/* main: %491*/
/* %496 = zext i1 %495 to i32*/
begin
main_491_496 = main_491_495;
end
end
always @(*) begin
/* main: %491*/
/* %497 = add nsw i32 %492, %496*/
begin
main_491_497 = main_491_492_reg + main_491_496;
end
end
always @(*) begin
/* main: %491*/
/* %498 = add nsw i32 %j.01.i, 1*/
begin
main_491_498 = main_491_j_01_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %491*/
/* %498 = add nsw i32 %j.01.i, 1*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_498_reg <= main_491_498;
if (^reset !== 1'bX && ^(main_491_498) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_498_reg"); $finish; end
end
end
always @(*) begin
/* main: %491*/
/* %exitcond.i = icmp eq i32 %498, 5310*/
begin
main_491_exitcond_i = main_491_498 == 32'd5310;
end
end
always @(posedge clk) begin
/* main: %491*/
/* %exitcond.i = icmp eq i32 %498, 5310*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
main_491_exitcond_i_reg <= main_491_exitcond_i;
if (^reset !== 1'bX && ^(main_491_exitcond_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_exitcond_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_499 = main__preheader_1_i_499_phi_temp;
end
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
else /* if (cur_state == LEGUP_F_main_BB132_461) */
begin
main__preheader_1_i_499 = main__preheader_1_i_499_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_499_reg <= main__preheader_1_i_499;
if (^reset !== 1'bX && ^(main__preheader_1_i_499) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_499_reg"); $finish; end
end
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_499_reg <= main__preheader_1_i_499;
if (^reset !== 1'bX && ^(main__preheader_1_i_499) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_499_reg"); $finish; end
end
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_499_reg <= main__preheader_1_i_499;
if (^reset !== 1'bX && ^(main__preheader_1_i_499) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_499_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %j.01.1.i = phi i32 [ %505, %.preheader.1.i ], [ 0, %491 ]*/
begin
main__preheader_1_i_j_01_1_i = main__preheader_1_i_j_01_1_i_phi_temp;
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %scevgep7.1.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 1, i32 %j.01.1.i*/
begin
main__preheader_1_i_scevgep7_1_i = `TAG_g_hana_bmp_a + 5310 * 32'd1 + 1 * main__preheader_1_i_j_01_1_i;
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %scevgep7.1.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 1, i32 %j.01.1.i*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_scevgep7_1_i_reg <= main__preheader_1_i_scevgep7_1_i;
if (^reset !== 1'bX && ^(main__preheader_1_i_scevgep7_1_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_scevgep7_1_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %scevgep.1.i = getelementptr [3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 %j.01.1.i*/
begin
main__preheader_1_i_scevgep_1_i = `TAG_g_OutData_comp_buf_a + 5310 * 32'd1 + 1 * main__preheader_1_i_j_01_1_i;
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
begin
main__preheader_1_i_500 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_463)
begin
main__preheader_1_i_500_reg <= main__preheader_1_i_500;
if (^reset !== 1'bX && ^(main__preheader_1_i_500) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_500_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %501 = load i8* %scevgep7.1.i, align 1, !tbaa !1*/
begin
main__preheader_1_i_501 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %502 = icmp eq i8 %500, %501*/
begin
main__preheader_1_i_502 = main__preheader_1_i_500_reg == main__preheader_1_i_501;
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %503 = zext i1 %502 to i32*/
begin
main__preheader_1_i_503 = main__preheader_1_i_502;
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %504 = add nsw i32 %499, %503*/
begin
main__preheader_1_i_504 = main__preheader_1_i_499_reg + main__preheader_1_i_503;
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %505 = add nsw i32 %j.01.1.i, 1*/
begin
main__preheader_1_i_505 = main__preheader_1_i_j_01_1_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %505 = add nsw i32 %j.01.1.i, 1*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_505_reg <= main__preheader_1_i_505;
if (^reset !== 1'bX && ^(main__preheader_1_i_505) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_505_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.1.i*/
/* %exitcond.1.i = icmp eq i32 %505, 5310*/
begin
main__preheader_1_i_exitcond_1_i = main__preheader_1_i_505 == 32'd5310;
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %exitcond.1.i = icmp eq i32 %505, 5310*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
main__preheader_1_i_exitcond_1_i_reg <= main__preheader_1_i_exitcond_1_i;
if (^reset !== 1'bX && ^(main__preheader_1_i_exitcond_1_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_exitcond_1_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %506 = icmp eq i16 %379, 90*/
begin
main_jpeg2bmp_main_exit_506 = main_read_markers_exit_i_379_reg == 16'd90;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %507 = zext i1 %506 to i32*/
begin
main_jpeg2bmp_main_exit_507 = main_jpeg2bmp_main_exit_506;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %storemerge = add nsw i32 %518, %507*/
begin
main_jpeg2bmp_main_exit_storemerge = main__preheader_2_i_518_reg + main_jpeg2bmp_main_exit_507;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %508 = icmp eq i16 %374, 59*/
begin
main_jpeg2bmp_main_exit_508 = main_read_markers_exit_i_374_reg == 16'd59;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %509 = zext i1 %508 to i32*/
begin
main_jpeg2bmp_main_exit_509 = main_jpeg2bmp_main_exit_508;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %.storemerge = add nsw i32 %storemerge, %509*/
begin
main_jpeg2bmp_main_exit__storemerge = main_jpeg2bmp_main_exit_storemerge + main_jpeg2bmp_main_exit_509;
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %511 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_jpeg2bmp_main_exit_511 = memory_controller_out[31:0];
end
end
always @(*) begin
/* main: %jpeg2bmp_main.exit*/
/* %512 = icmp eq i32 %511, 21745*/
begin
main_jpeg2bmp_main_exit_512 = main_jpeg2bmp_main_exit_511 == 32'd21745;
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_513 = main__preheader_2_i_513_phi_temp;
end
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
else /* if (cur_state == LEGUP_F_main_BB134_469) */
begin
main__preheader_2_i_513 = main__preheader_2_i_513_phi_temp;
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_513_reg <= main__preheader_2_i_513;
if (^reset !== 1'bX && ^(main__preheader_2_i_513) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_513_reg"); $finish; end
end
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_513_reg <= main__preheader_2_i_513;
if (^reset !== 1'bX && ^(main__preheader_2_i_513) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_513_reg"); $finish; end
end
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_513_reg <= main__preheader_2_i_513;
if (^reset !== 1'bX && ^(main__preheader_2_i_513) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_513_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %j.01.2.i = phi i32 [ %519, %.preheader.2.i ], [ 0, %.preheader.1.i ]*/
begin
main__preheader_2_i_j_01_2_i = main__preheader_2_i_j_01_2_i_phi_temp;
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %scevgep7.2.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 2, i32 %j.01.2.i*/
begin
main__preheader_2_i_scevgep7_2_i = `TAG_g_hana_bmp_a + 5310 * 32'd2 + 1 * main__preheader_2_i_j_01_2_i;
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %scevgep7.2.i = getelementptr [3 x [5310 x i8]]* @hana_bmp, i32 0, i32 2, i32 %j.01.2.i*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_scevgep7_2_i_reg <= main__preheader_2_i_scevgep7_2_i;
if (^reset !== 1'bX && ^(main__preheader_2_i_scevgep7_2_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_scevgep7_2_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %scevgep.2.i = getelementptr [3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 %j.01.2.i*/
begin
main__preheader_2_i_scevgep_2_i = `TAG_g_OutData_comp_buf_a + 5310 * 32'd2 + 1 * main__preheader_2_i_j_01_2_i;
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
begin
main__preheader_2_i_514 = memory_controller_out[7:0];
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_471)
begin
main__preheader_2_i_514_reg <= main__preheader_2_i_514;
if (^reset !== 1'bX && ^(main__preheader_2_i_514) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_514_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %515 = load i8* %scevgep7.2.i, align 1, !tbaa !1*/
begin
main__preheader_2_i_515 = memory_controller_out[7:0];
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %516 = icmp eq i8 %514, %515*/
begin
main__preheader_2_i_516 = main__preheader_2_i_514_reg == main__preheader_2_i_515;
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %517 = zext i1 %516 to i32*/
begin
main__preheader_2_i_517 = main__preheader_2_i_516;
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %518 = add nsw i32 %513, %517*/
begin
main__preheader_2_i_518 = main__preheader_2_i_513_reg + main__preheader_2_i_517;
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %518 = add nsw i32 %513, %517*/
if (cur_state == LEGUP_F_main_BB134_472)
begin
main__preheader_2_i_518_reg <= main__preheader_2_i_518;
if (^reset !== 1'bX && ^(main__preheader_2_i_518) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_518_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %519 = add nsw i32 %j.01.2.i, 1*/
begin
main__preheader_2_i_519 = main__preheader_2_i_j_01_2_i + 32'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %519 = add nsw i32 %j.01.2.i, 1*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_519_reg <= main__preheader_2_i_519;
if (^reset !== 1'bX && ^(main__preheader_2_i_519) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_519_reg"); $finish; end
end
end
always @(*) begin
/* main: %.preheader.2.i*/
/* %exitcond.2.i = icmp eq i32 %519, 5310*/
begin
main__preheader_2_i_exitcond_2_i = main__preheader_2_i_519 == 32'd5310;
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %exitcond.2.i = icmp eq i32 %519, 5310*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
main__preheader_2_i_exitcond_2_i_reg <= main__preheader_2_i_exitcond_2_i;
if (^reset !== 1'bX && ^(main__preheader_2_i_exitcond_2_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_exitcond_2_i_reg"); $finish; end
end
end
always @(*) begin
/* main: %524*/
/* %525 = load i32* @main_result, align 4, !tbaa !0*/
begin
main_524_525 = memory_controller_out[31:0];
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
huff_make_dhuff_tb_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
huff_make_dhuff_tb_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
huff_make_dhuff_tb_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
huff_make_dhuff_tb_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
huff_make_dhuff_tb_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
huff_make_dhuff_tb_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
huff_make_dhuff_tb_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
huff_make_dhuff_tb_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_start"); $finish; end
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
huff_make_dhuff_tb_arg_p_xhtbl_bits <= `TAG_g_p_jinfo_dc_xhuff_tbl_bits_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_xhuff_tbl_bits_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_xhtbl_bits"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
huff_make_dhuff_tb_arg_p_xhtbl_bits <= `TAG_g_p_jinfo_dc_xhuff_tbl_bits_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_xhuff_tbl_bits_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_xhtbl_bits"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
huff_make_dhuff_tb_arg_p_xhtbl_bits <= `TAG_g_p_jinfo_ac_xhuff_tbl_bits_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_xhuff_tbl_bits_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_xhtbl_bits"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
huff_make_dhuff_tb_arg_p_xhtbl_bits <= `TAG_g_p_jinfo_ac_xhuff_tbl_bits_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_xhuff_tbl_bits_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_xhtbl_bits"); $finish; end
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
huff_make_dhuff_tb_arg_p_dhtbl_maxcode <= `TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_maxcode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
huff_make_dhuff_tb_arg_p_dhtbl_maxcode <= `TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_maxcode_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_maxcode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
huff_make_dhuff_tb_arg_p_dhtbl_maxcode <= `TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_maxcode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
huff_make_dhuff_tb_arg_p_dhtbl_maxcode <= `TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_maxcode_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_maxcode"); $finish; end
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
huff_make_dhuff_tb_arg_p_dhtbl_mincode <= `TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_mincode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
huff_make_dhuff_tb_arg_p_dhtbl_mincode <= `TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_mincode_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_mincode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
huff_make_dhuff_tb_arg_p_dhtbl_mincode <= `TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_mincode"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
huff_make_dhuff_tb_arg_p_dhtbl_mincode <= `TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_mincode_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_mincode"); $finish; end
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
huff_make_dhuff_tb_arg_p_dhtbl_valptr <= `TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_valptr"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
huff_make_dhuff_tb_arg_p_dhtbl_valptr <= `TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_dc_dhuff_tbl_valptr_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_valptr"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
huff_make_dhuff_tb_arg_p_dhtbl_valptr <= `TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_valptr"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
huff_make_dhuff_tb_arg_p_dhtbl_valptr <= `TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a + 144 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_p_jinfo_ac_dhuff_tbl_valptr_a + 144 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to huff_make_dhuff_tb_arg_p_dhtbl_valptr"); $finish; end
end
end
always @(*) begin
huff_make_dhuff_tb_memory_controller_waitrequest = 1'd0;
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
huff_make_dhuff_tb_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
huff_make_dhuff_tb_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
huff_make_dhuff_tb_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
huff_make_dhuff_tb_memory_controller_waitrequest = memory_controller_waitrequest;
end
end
always @(*) begin
huff_make_dhuff_tb_memory_controller_out = 1'd0;
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
huff_make_dhuff_tb_memory_controller_out = memory_controller_out;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
huff_make_dhuff_tb_memory_controller_out = memory_controller_out;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
huff_make_dhuff_tb_memory_controller_out = memory_controller_out;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
huff_make_dhuff_tb_memory_controller_out = memory_controller_out;
end
end
always @(*) begin
legup_function_call = 1'd0;
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_329)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_333)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_337)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB90_341)
begin
legup_function_call = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_360)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_363)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_411)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_414)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_417)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_420)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_423)
begin
legup_function_call = 1'd1;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
legup_function_call = 1'd1;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
legup_function_call = 1'd1;
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_360)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_363)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_411)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_414)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_417)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_420)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_423)
begin
decode_block_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
decode_block_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_start"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
decode_block_arg_comp_no <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_360)
begin
decode_block_arg_comp_no <= 32'd1;
if (^reset !== 1'bX && ^(32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_363)
begin
decode_block_arg_comp_no <= 32'd2;
if (^reset !== 1'bX && ^(32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
decode_block_arg_comp_no <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_411)
begin
decode_block_arg_comp_no <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_414)
begin
decode_block_arg_comp_no <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_417)
begin
decode_block_arg_comp_no <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_420)
begin
decode_block_arg_comp_no <= 32'd1;
if (^reset !== 1'bX && ^(32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_423)
begin
decode_block_arg_comp_no <= 32'd2;
if (^reset !== 1'bX && ^(32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_comp_no"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
decode_block_arg_out_buf <= main__preheader21_i_i_preheader_scevgep51_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_360)
begin
decode_block_arg_out_buf <= main__preheader21_i_i_preheader_scevgep51_1_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_1_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_363)
begin
decode_block_arg_out_buf <= main__preheader21_i_i_preheader_scevgep51_2_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader21_i_i_preheader_scevgep51_2_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_scevgep_i8_i_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_i8_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_411)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_scevgep_1_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_1_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_414)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_scevgep_2_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_2_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_417)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_scevgep_3_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_scevgep_3_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_420)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_452_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_452_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_423)
begin
decode_block_arg_out_buf <= main__preheader_lr_ph_i_i_453_reg;
if (^reset !== 1'bX && ^(main__preheader_lr_ph_i_i_453_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_out_buf"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_357)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_360)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_1_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_1_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB93_363)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_2_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_2_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_408)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_411)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_414)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_417)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_420)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_1_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_1_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_F_main_BB116_423)
begin
decode_block_arg_HuffBuff <= main_read_markers_exit_i_scevgep148_2_i_i_reg;
if (^reset !== 1'bX && ^(main_read_markers_exit_i_scevgep148_2_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to decode_block_arg_HuffBuff"); $finish; end
end
end
always @(*) begin
decode_block_memory_controller_waitrequest = 1'd0;
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
decode_block_memory_controller_waitrequest = memory_controller_waitrequest;
end
end
always @(*) begin
decode_block_memory_controller_out = 1'd0;
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
decode_block_memory_controller_out = memory_controller_out;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
decode_block_memory_controller_out = memory_controller_out;
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
Write4Blocks_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
Write4Blocks_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_start <= 1'd1;
if (^reset !== 1'bX && ^(1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
Write4Blocks_start <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_start"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_store1 <= `TAG_g_rgb_buf_a;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store1"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_store1 <= `TAG_g_rgb_buf_a + 256 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 256 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store1"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_store1 <= `TAG_g_rgb_buf_a + 256 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 256 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store1"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_store2 <= `TAG_g_rgb_buf_a + 768 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store2"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_store2 <= `TAG_g_rgb_buf_a + 768 * 32'd1 + 256 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd1 + 256 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store2"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_store2 <= `TAG_g_rgb_buf_a + 768 * 32'd1 + 256 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd1 + 256 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store2"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_store3 <= `TAG_g_rgb_buf_a + 768 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store3"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_store3 <= `TAG_g_rgb_buf_a + 768 * 32'd2 + 256 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd2 + 256 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store3"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_store3 <= `TAG_g_rgb_buf_a + 768 * 32'd2 + 256 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd2 + 256 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store3"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_store4 <= `TAG_g_rgb_buf_a + 768 * 32'd3;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd3) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store4"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_store4 <= `TAG_g_rgb_buf_a + 768 * 32'd3 + 256 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd3 + 256 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store4"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_store4 <= `TAG_g_rgb_buf_a + 768 * 32'd3 + 256 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_rgb_buf_a + 768 * 32'd3 + 256 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_store4"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_p_out_vpos <= `TAG_g_OutData_comp_vpos_a;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_vpos_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_vpos"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_p_out_vpos <= `TAG_g_OutData_comp_vpos_a + 4 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_vpos_a + 4 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_vpos"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_p_out_vpos <= `TAG_g_OutData_comp_vpos_a + 4 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_vpos_a + 4 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_vpos"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_p_out_hpos <= `TAG_g_OutData_comp_hpos_a;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_hpos_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_hpos"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_p_out_hpos <= `TAG_g_OutData_comp_hpos_a + 4 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_hpos_a + 4 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_hpos"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_p_out_hpos <= `TAG_g_OutData_comp_hpos_a + 4 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_hpos_a + 4 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_hpos"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_445)
begin
Write4Blocks_arg_p_out_buf <= `TAG_g_OutData_comp_buf_a;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_buf_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_buf"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_448)
begin
Write4Blocks_arg_p_out_buf <= `TAG_g_OutData_comp_buf_a + 5310 * 32'd1;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_buf_a + 5310 * 32'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_buf"); $finish; end
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_F_main_BB129_451)
begin
Write4Blocks_arg_p_out_buf <= `TAG_g_OutData_comp_buf_a + 5310 * 32'd2;
if (^reset !== 1'bX && ^(`TAG_g_OutData_comp_buf_a + 5310 * 32'd2) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to Write4Blocks_arg_p_out_buf"); $finish; end
end
end
always @(*) begin
Write4Blocks_memory_controller_waitrequest = 1'd0;
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
Write4Blocks_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
Write4Blocks_memory_controller_waitrequest = memory_controller_waitrequest;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
Write4Blocks_memory_controller_waitrequest = memory_controller_waitrequest;
end
end
always @(*) begin
Write4Blocks_memory_controller_out = 1'd0;
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
Write4Blocks_memory_controller_out = memory_controller_out;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
Write4Blocks_memory_controller_out = memory_controller_out;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
Write4Blocks_memory_controller_out = memory_controller_out;
end
end
always @(*) begin
/* main: %392*/
/* %403 = mul i32 %395, -88*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_signed_multiply_32_1_op0 = main_392_395;
end
/* main: %392*/
/* %399 = mul nsw i32 %397, 359*/
else if (cur_state == LEGUP_F_main_BB94_370)
begin
main_signed_multiply_32_1_op0 = main_392_397;
end
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp121.i.i = mul i32 %tmp120.i.i, %434*/
else if (cur_state == LEGUP_F_main_BB106_392)
begin
main_signed_multiply_32_1_op0 = main_YuvToRgb_exit_loopexit_i_i_tmp120_i_i_reg;
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp118.i.i = mul i32 %428, %indvar17.i.i.i.i*/
else if (cur_state == LEGUP_F_main_BB109_399)
begin
main_signed_multiply_32_1_op0 = main_YuvToRgb_exit_loopexit_i_i_428_reg;
end
/* main: %454*/
/* %465 = mul i32 %457, -88*/
else if (cur_state == LEGUP_F_main_BB118_430)
begin
main_signed_multiply_32_1_op0 = main_454_457;
end
/* main: %454*/
/* %461 = mul nsw i32 %459, 359*/
else /* if (cur_state == LEGUP_F_main_BB118_431) */
begin
main_signed_multiply_32_1_op0 = main_454_459;
end
end
always @(*) begin
/* main: %392*/
/* %403 = mul i32 %395, -88*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_signed_multiply_32_1_op1 = -32'd88;
end
/* main: %392*/
/* %399 = mul nsw i32 %397, 359*/
else if (cur_state == LEGUP_F_main_BB94_370)
begin
main_signed_multiply_32_1_op1 = 32'd359;
end
/* main: %.lr.ph8.split.us.i.i.i.i*/
/* %tmp121.i.i = mul i32 %tmp120.i.i, %434*/
else if (cur_state == LEGUP_F_main_BB106_392)
begin
main_signed_multiply_32_1_op1 = main_432_434_reg;
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp118.i.i = mul i32 %428, %indvar17.i.i.i.i*/
else if (cur_state == LEGUP_F_main_BB109_399)
begin
main_signed_multiply_32_1_op1 = main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
end
/* main: %454*/
/* %465 = mul i32 %457, -88*/
else if (cur_state == LEGUP_F_main_BB118_430)
begin
main_signed_multiply_32_1_op1 = -32'd88;
end
/* main: %454*/
/* %461 = mul nsw i32 %459, 359*/
else /* if (cur_state == LEGUP_F_main_BB118_431) */
begin
main_signed_multiply_32_1_op1 = 32'd359;
end
end
always @(*) begin
main_signed_multiply_32_1 = main_signed_multiply_32_1_op0 * main_signed_multiply_32_1_op1;
end
always @(*) begin
/* main: %392*/
/* %408 = mul nsw i32 %395, 454*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_signed_multiply_32_2_op0 = main_392_395;
end
/* main: %392*/
/* %404 = mul i32 %397, -182*/
else if (cur_state == LEGUP_F_main_BB94_370)
begin
main_signed_multiply_32_2_op0 = main_392_397;
end
/* main: %454*/
/* %470 = mul nsw i32 %457, 454*/
else if (cur_state == LEGUP_F_main_BB118_430)
begin
main_signed_multiply_32_2_op0 = main_454_457;
end
/* main: %454*/
/* %466 = mul i32 %459, -182*/
else /* if (cur_state == LEGUP_F_main_BB118_431) */
begin
main_signed_multiply_32_2_op0 = main_454_459;
end
end
always @(*) begin
/* main: %392*/
/* %408 = mul nsw i32 %395, 454*/
if (cur_state == LEGUP_F_main_BB94_369)
begin
main_signed_multiply_32_2_op1 = 32'd454;
end
/* main: %392*/
/* %404 = mul i32 %397, -182*/
else if (cur_state == LEGUP_F_main_BB94_370)
begin
main_signed_multiply_32_2_op1 = -32'd182;
end
/* main: %454*/
/* %470 = mul nsw i32 %457, 454*/
else if (cur_state == LEGUP_F_main_BB118_430)
begin
main_signed_multiply_32_2_op1 = 32'd454;
end
/* main: %454*/
/* %466 = mul i32 %459, -182*/
else /* if (cur_state == LEGUP_F_main_BB118_431) */
begin
main_signed_multiply_32_2_op1 = -32'd182;
end
end
always @(*) begin
main_signed_multiply_32_2 = main_signed_multiply_32_2_op0 * main_signed_multiply_32_2_op1;
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %384 = mul nsw i32 %383, %378*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
main_signed_multiply_32_0_op0 = main_read_markers_exit_i_383;
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp136.i.i = mul i32 %indvar17.i.i.i.i, %tmp69.i.i*/
else /* if (cur_state == LEGUP_F_main_BB109_399) */
begin
main_signed_multiply_32_0_op0 = main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i;
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %384 = mul nsw i32 %383, %378*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
main_signed_multiply_32_0_op1 = main_read_markers_exit_i_378_reg;
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %tmp136.i.i = mul i32 %indvar17.i.i.i.i, %tmp69.i.i*/
else /* if (cur_state == LEGUP_F_main_BB109_399) */
begin
main_signed_multiply_32_0_op1 = main__lr_ph8_split_us_i_i_i_i_tmp69_i_i_reg;
end
end
always @(*) begin
main_signed_multiply_32_0 = main_signed_multiply_32_0_op0 * main_signed_multiply_32_0_op1;
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %377 = sdiv i32 %376, 8*/
if (cur_state == LEGUP_F_main_BB90_287)
begin
main_signed_divide_32_0_op0 = main_read_markers_exit_i_376_reg;
end
/* main: %read_markers.exit.i*/
/* %382 = sdiv i32 %381, 8*/
else /* if (cur_state == LEGUP_F_main_BB90_288) */
begin
main_signed_divide_32_0_op0 = main_read_markers_exit_i_381_reg;
end
end
always @(*) begin
/* main: %read_markers.exit.i*/
/* %377 = sdiv i32 %376, 8*/
if (cur_state == LEGUP_F_main_BB90_287)
begin
main_signed_divide_32_0_op1 = 32'd8;
end
/* main: %read_markers.exit.i*/
/* %382 = sdiv i32 %381, 8*/
else /* if (cur_state == LEGUP_F_main_BB90_288) */
begin
main_signed_divide_32_0_op1 = 32'd8;
end
end
always @(*) begin
main_signed_divide_32_0 = lpm_divide_main_read_markers_exit_i_377_out;
end
always @(*) begin
lpm_divide_main_read_markers_exit_i_377_en = memory_controller_waitrequest == 1'd0 & legup_function_call == 1'd0;
end
always @(posedge clk) begin
/* main: %1*/
/* %i.05.i = phi i32 [ 0, %0 ], [ %3, %1 ]*/
if (cur_state == LEGUP_F_main_BB0_1 & memory_controller_waitrequest == 1'd0)
begin
main_1_i_05_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_i_05_i_phi_temp"); $finish; end
end
/* main: %1*/
/* %i.05.i = phi i32 [ 0, %0 ], [ %3, %1 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd0)
begin
main_1_i_05_i_phi_temp <= main_1_3_reg;
if (^reset !== 1'bX && ^(main_1_3_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_1_i_05_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %i_marker.0 = phi i32 [ 0, %1 ], [ %24, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_i_marker_0_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_marker_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %i_marker.0 = phi i32 [ 0, %1 ], [ %24, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_i_marker_0_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_marker_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %i_get_dht.0 = phi i32 [ 0, %1 ], [ %i_get_dht.1.ph, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_i_get_dht_0_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_get_dht_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %i_get_dht.0 = phi i32 [ 0, %1 ], [ %i_get_dht.1.ph, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_i_get_dht_0_phi_temp <= main__backedge_i_i_outer_i_get_dht_1_ph_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_get_dht_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %i_get_dqt.0 = phi i32 [ 0, %1 ], [ %i_get_dqt.1.ph6, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_i_get_dqt_0_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_get_dqt_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %i_get_dqt.0 = phi i32 [ 0, %1 ], [ %i_get_dqt.1.ph6, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_i_get_dqt_0_phi_temp <= main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_i_get_dqt_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %ReadBuf.0 = phi i8* [ getelementptr inbounds ([5310 x i8]* @JpegFileBuf, i32 0, i32 0), %1 ], [ %ReadBuf.2, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_ReadBuf_0_phi_temp <= `TAG_g_JpegFileBuf_a;
if (^reset !== 1'bX && ^(`TAG_g_JpegFileBuf_a) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_ReadBuf_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %ReadBuf.0 = phi i8* [ getelementptr inbounds ([5310 x i8]* @JpegFileBuf, i32 0, i32 0), %1 ], [ %ReadBuf.2, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_ReadBuf_0_phi_temp <= main_next_marker_exit_i_i_ReadBuf_2_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_ReadBuf_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %p_jinfo_num_components.0 = phi i8 [ 0, %1 ], [ %p_jinfo_num_components.1.ph13, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_p_jinfo_num_components_0_phi_temp <= 8'd0;
if (^reset !== 1'bX && ^(8'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_p_jinfo_num_components_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %p_jinfo_num_components.0 = phi i8 [ 0, %1 ], [ %p_jinfo_num_components.1.ph13, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_p_jinfo_num_components_0_phi_temp <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_p_jinfo_num_components_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %p_jinfo_smp_fact.b.0 = phi i1 [ false, %1 ], [ %p_jinfo_smp_fact.b.1.ph14, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %p_jinfo_smp_fact.b.0 = phi i1 [ false, %1 ], [ %p_jinfo_smp_fact.b.1.ph14, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_p_jinfo_smp_fact_b_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB1_4 & memory_controller_waitrequest == 1'd0 & main_1_exitcond11_i_reg == 1'd1)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp <= -1'd1;
if (^reset !== 1'bX && ^(-1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp"); $finish; end
end
/* main: %.outer.i.i*/
/* %sow_SOI.0.ph.i.i = phi i1 [ true, %1 ], [ false, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd216)
begin
main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__outer_i_i_sow_SOI_0_ph_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %i_marker.1.ph = phi i32 [ %i_marker.0, %.outer.i.i ], [ %24, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_i_marker_1_ph_phi_temp <= main__outer_i_i_i_marker_0;
if (^reset !== 1'bX && ^(main__outer_i_i_i_marker_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_marker_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_marker.1.ph = phi i32 [ %i_marker.0, %.outer.i.i ], [ %24, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_i_marker_1_ph_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_marker_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp <= main__outer_i_i_i_get_dht_0;
if (^reset !== 1'bX && ^(main__outer_i_i_i_get_dht_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dht.1.ph = phi i32 [ %i_get_dht.0, %.outer.i.i ], [ %302, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp <= main_301_302_reg;
if (^reset !== 1'bX && ^(main_301_302_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dht_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %i_get_dqt.1.ph = phi i32 [ %i_get_dqt.0, %.outer.i.i ], [ %i_get_dqt.1.ph6, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp <= main__outer_i_i_i_get_dqt_0;
if (^reset !== 1'bX && ^(main__outer_i_i_i_get_dqt_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %i_get_dqt.1.ph = phi i32 [ %i_get_dqt.0, %.outer.i.i ], [ %i_get_dqt.1.ph6, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp <= main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_i_get_dqt_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %ReadBuf.1.ph = phi i8* [ %ReadBuf.0, %.outer.i.i ], [ %ReadBuf.7, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp <= main__outer_i_i_ReadBuf_0;
if (^reset !== 1'bX && ^(main__outer_i_i_ReadBuf_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %ReadBuf.1.ph = phi i8* [ %ReadBuf.0, %.outer.i.i ], [ %ReadBuf.7, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp <= main___crit_edge_i12_i_i_ReadBuf_7;
if (^reset !== 1'bX && ^(main___crit_edge_i12_i_i_ReadBuf_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_ReadBuf_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_num_components.1.ph = phi i8 [ %p_jinfo_num_components.0, %.outer.i.i ], [ %p_jinfo_num_components.1.ph13, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp <= main__outer_i_i_p_jinfo_num_components_0;
if (^reset !== 1'bX && ^(main__outer_i_i_p_jinfo_num_components_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_num_components.1.ph = phi i8 [ %p_jinfo_num_components.0, %.outer.i.i ], [ %p_jinfo_num_components.1.ph13, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_p_jinfo_num_components_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_smp_fact.b.1.ph = phi i1 [ %p_jinfo_smp_fact.b.0, %.outer.i.i ], [ %p_jinfo_smp_fact.b.1.ph14, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB2_5 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp <= main__outer_i_i_p_jinfo_smp_fact_b_0;
if (^reset !== 1'bX && ^(main__outer_i_i_p_jinfo_smp_fact_b_0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer*/
/* %p_jinfo_smp_fact.b.1.ph = phi i1 [ %p_jinfo_smp_fact.b.0, %.outer.i.i ], [ %p_jinfo_smp_fact.b.1.ph14, %._crit_edge.i12.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd0)
begin
main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %i_marker.1.ph5 = phi i32 [ %i_marker.1.ph, %.backedge.i.i.outer ], [ %24, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp <= main__backedge_i_i_outer_i_marker_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_marker_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_marker.1.ph5 = phi i32 [ %i_marker.1.ph, %.backedge.i.i.outer ], [ %24, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_marker_1_ph5_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp <= main__backedge_i_i_outer_i_get_dqt_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dqt_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %i_get_dqt.1.ph6 = phi i32 [ %i_get_dqt.1.ph, %.backedge.i.i.outer ], [ %352, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp <= main_351_352_reg;
if (^reset !== 1'bX && ^(main_351_352_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_i_get_dqt_1_ph6_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %ReadBuf.1.ph7 = phi i8* [ %ReadBuf.1.ph, %.backedge.i.i.outer ], [ %ReadBuf.8, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp <= main__backedge_i_i_outer_ReadBuf_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_ReadBuf_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %ReadBuf.1.ph7 = phi i8* [ %ReadBuf.1.ph, %.backedge.i.i.outer ], [ %ReadBuf.8, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp <= main__us_lcssa_us_i_i_i_ReadBuf_8;
if (^reset !== 1'bX && ^(main__us_lcssa_us_i_i_i_ReadBuf_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_ReadBuf_1_ph7_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_num_components.1.ph8 = phi i8 [ %p_jinfo_num_components.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_num_components.1.ph13, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp <= main__backedge_i_i_outer_p_jinfo_num_components_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_p_jinfo_num_components_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_num_components.1.ph8 = phi i8 [ %p_jinfo_num_components.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_num_components.1.ph13, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp <= main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_smp_fact.b.1.ph9 = phi i1 [ %p_jinfo_smp_fact.b.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_smp_fact.b.1.ph14, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB3_6 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp <= main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_p_jinfo_smp_fact_b_1_ph) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer4*/
/* %p_jinfo_smp_fact.b.1.ph9 = phi i1 [ %p_jinfo_smp_fact.b.1.ph, %.backedge.i.i.outer ], [ %p_jinfo_smp_fact.b.1.ph14, %.us-lcssa.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd0)
begin
main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp <= main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %i_marker.1.ph11 = phi i32 [ %i_marker.1.ph5, %.backedge.i.i.outer4 ], [ %24, %163 ], [ %24, %165 ]*/
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp <= main__backedge_i_i_outer4_i_marker_1_ph5;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_marker_1_ph5) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %i_marker.1.ph11 = phi i32 [ %i_marker.1.ph5, %.backedge.i.i.outer4 ], [ %24, %163 ], [ %24, %165 ]*/
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %i_marker.1.ph11 = phi i32 [ %i_marker.1.ph5, %.backedge.i.i.outer4 ], [ %24, %163 ], [ %24, %165 ]*/
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_i_marker_1_ph11_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %ReadBuf.1.ph12 = phi i8* [ %ReadBuf.1.ph7, %.backedge.i.i.outer4 ], [ %ReadBuf.4, %163 ], [ %ReadBuf.4, %165 ]*/
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp <= main__backedge_i_i_outer4_ReadBuf_1_ph7;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_ReadBuf_1_ph7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %ReadBuf.1.ph12 = phi i8* [ %ReadBuf.1.ph7, %.backedge.i.i.outer4 ], [ %ReadBuf.4, %163 ], [ %ReadBuf.4, %165 ]*/
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp <= main___crit_edge_i_i_i_ReadBuf_4_reg;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %ReadBuf.1.ph12 = phi i8* [ %ReadBuf.1.ph7, %.backedge.i.i.outer4 ], [ %ReadBuf.4, %163 ], [ %ReadBuf.4, %165 ]*/
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp <= main___crit_edge_i_i_i_ReadBuf_4_reg;
if (^reset !== 1'bX && ^(main___crit_edge_i_i_i_ReadBuf_4_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_ReadBuf_1_ph12_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp <= main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_p_jinfo_num_components_1_ph8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp <= main_32_61_reg;
if (^reset !== 1'bX && ^(main_32_61_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_num_components.1.ph13 = phi i8 [ %p_jinfo_num_components.1.ph8, %.backedge.i.i.outer4 ], [ %61, %163 ], [ %61, %165 ]*/
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp <= main_32_61_reg;
if (^reset !== 1'bX && ^(main_32_61_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_num_components_1_ph13_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB4_7 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp <= main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_p_jinfo_smp_fact_b_1_ph9) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB43_143 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp <= -1'd1;
if (^reset !== 1'bX && ^(-1'd1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp"); $finish; end
end
/* main: %.backedge.i.i.outer10*/
/* %p_jinfo_smp_fact.b.1.ph14 = phi i1 [ %p_jinfo_smp_fact.b.1.ph9, %.backedge.i.i.outer4 ], [ true, %163 ], [ false, %165 ]*/
if (cur_state == LEGUP_F_main_BB44_144 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_outer10_p_jinfo_smp_fact_b_1_ph14_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB5_8 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_i_marker_1_phi_temp <= main__backedge_i_i_outer10_i_marker_1_ph11;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_i_marker_1_ph11) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd216 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd192 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd218 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd196 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd219 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd217)
begin
main__backedge_i_i_i_marker_1_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd0)
begin
main__backedge_i_i_i_marker_1_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %i_marker.1 = phi i32 [ %i_marker.1.ph11, %.backedge.i.i.outer10 ], [ %24, %31 ], [ %24, %.preheader.i7.i.i ], [ %24, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd0)
begin
main__backedge_i_i_i_marker_1_phi_temp <= main_next_marker_exit_i_i_24_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_24_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_i_marker_1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB5_8 & memory_controller_waitrequest == 1'd0)
begin
main__backedge_i_i_ReadBuf_1_phi_temp <= main__backedge_i_i_outer10_ReadBuf_1_ph12;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer10_ReadBuf_1_ph12) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd216 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd192 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd218 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd196 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd219 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg != 32'd217)
begin
main__backedge_i_i_ReadBuf_1_phi_temp <= main_next_marker_exit_i_i_ReadBuf_2_reg;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_ReadBuf_2_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd0)
begin
main__backedge_i_i_ReadBuf_1_phi_temp <= main_248_253_reg;
if (^reset !== 1'bX && ^(main_248_253_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_phi_temp"); $finish; end
end
/* main: %.backedge.i.i*/
/* %ReadBuf.1 = phi i8* [ %ReadBuf.1.ph12, %.backedge.i.i.outer10 ], [ %ReadBuf.2, %31 ], [ %253, %.preheader.i7.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd0)
begin
main__backedge_i_i_ReadBuf_1_phi_temp <= main_312_317_reg;
if (^reset !== 1'bX && ^(main_312_317_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__backedge_i_i_ReadBuf_1_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB6_9 & memory_controller_waitrequest == 1'd0 & main__outer_i_i_sow_SOI_0_ph_i_i_reg == 1'd0)
begin
main__loopexit3_i_i_i_18_phi_temp <= main__backedge_i_i_ReadBuf_1;
if (^reset !== 1'bX && ^(main__backedge_i_i_ReadBuf_1) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_phi_temp"); $finish; end
end
/* main: %.loopexit3.i.i.i*/
/* %18 = phi i8* [ %scevgep13.i.i.le, %.loopexit3.i.i.i.loopexit ], [ %ReadBuf.1, %.backedge.i.i ]*/
if (cur_state == LEGUP_F_main_BB10_18 & memory_controller_waitrequest == 1'd0)
begin
main__loopexit3_i_i_i_18_phi_temp <= main__loopexit3_i_i_i_loopexit_scevgep13_i_i_le;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_loopexit_scevgep13_i_i_le) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit3_i_i_i_18_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB9_17 & memory_controller_waitrequest == 1'd0)
begin
main_next_marker_exit_i_i_ReadBuf_2_phi_temp <= main_first_marker_exit_i_i_14_reg;
if (^reset !== 1'bX && ^(main_first_marker_exit_i_i_14_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_phi_temp"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %ReadBuf.2 = phi i8* [ %14, %first_marker.exit.i.i ], [ %scevgep13.i.i, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB16_30 & memory_controller_waitrequest == 1'd0)
begin
main_next_marker_exit_i_i_ReadBuf_2_phi_temp <= main_next_marker_exit_i_i_loopexit_scevgep13_i_i;
if (^reset !== 1'bX && ^(main_next_marker_exit_i_i_loopexit_scevgep13_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_ReadBuf_2_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB9_17 & memory_controller_waitrequest == 1'd0)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp <= main_first_marker_exit_i_i_15_reg;
if (^reset !== 1'bX && ^(main_first_marker_exit_i_i_15_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp"); $finish; end
end
/* main: %next_marker.exit.i.i*/
/* %unread_marker.0.i.i = phi i32 [ %15, %first_marker.exit.i.i ], [ %22, %next_marker.exit.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB16_30 & memory_controller_waitrequest == 1'd0)
begin
main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp <= main__loopexit_i_i_i_22_reg;
if (^reset !== 1'bX && ^(main__loopexit_i_i_i_22_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_next_marker_exit_i_i_unread_marker_0_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB11_21 & memory_controller_waitrequest == 1'd0 & main__loopexit3_i_i_i_19 == 1'd1)
begin
main__loopexit_i_preheader_i_i__ph_i_i_phi_temp <= main__loopexit3_i_i_i_storemerge1_i_i_i_reg;
if (^reset !== 1'bX && ^(main__loopexit3_i_i_i_storemerge1_i_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_phi_temp"); $finish; end
end
/* main: %.loopexit.i.preheader.i.i*/
/* %.ph.i.i = phi i8* [ %storemerge1.i.i.i, %.loopexit3.i.i.i ], [ %storemerge.i.i.i, %.loopexit.i.preheader.i.i.loopexit ]*/
if (cur_state == LEGUP_F_main_BB13_25 & memory_controller_waitrequest == 1'd0)
begin
main__loopexit_i_preheader_i_i__ph_i_i_phi_temp <= main__loopexit_i_preheader_i_i_loopexit_storemerge_i_i_i;
if (^reset !== 1'bX && ^(main__loopexit_i_preheader_i_i_loopexit_storemerge_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_preheader_i_i__ph_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB11_21 & memory_controller_waitrequest == 1'd0 & main__loopexit3_i_i_i_19 == 1'd0)
begin
main__lr_ph_i_i_i_indvar_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_indvar_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.i.i.i*/
/* %indvar.i.i = phi i32 [ %tmp.i.i, %.lr.ph.i.i.i ], [ 0, %.loopexit3.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB12_24 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i_i_i_20 == 1'd0)
begin
main__lr_ph_i_i_i_indvar_i_i_phi_temp <= main__lr_ph_i_i_i_tmp_i_i_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i_i_i_tmp_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i_i_i_indvar_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.loopexit.i.i.i*/
/* %indvar9.i.i = phi i32 [ 0, %.loopexit.i.preheader.i.i ], [ %tmp12.i.i, %.loopexit.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB14_26 & memory_controller_waitrequest == 1'd0)
begin
main__loopexit_i_i_i_indvar9_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_i_indvar9_i_i_phi_temp"); $finish; end
end
/* main: %.loopexit.i.i.i*/
/* %indvar9.i.i = phi i32 [ 0, %.loopexit.i.preheader.i.i ], [ %tmp12.i.i, %.loopexit.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB15_29 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_i_22 == 32'd255)
begin
main__loopexit_i_i_i_indvar9_i_i_phi_temp <= main__loopexit_i_i_i_tmp12_i_i_reg;
if (^reset !== 1'bX && ^(main__loopexit_i_i_i_tmp12_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__loopexit_i_i_i_indvar9_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB19_38 & memory_controller_waitrequest == 1'd0 & main_next_marker_exit_i_i_unread_marker_0_i_i_reg == 32'd217)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp <= 0;
if (^reset !== 1'bX && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp"); $finish; end
end
/* main: %read_markers.exit.i*/
/* %p_jinfo_jpeg_data.0 = phi i8* [ %scevgep.i2.i.i, %get_sos.exit.i.i ], [ null, %31 ]*/
if (cur_state == LEGUP_F_main_BB63_200 & memory_controller_waitrequest == 1'd0)
begin
main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp <= main_get_sos_exit_i_i_scevgep_i2_i_i;
if (^reset !== 1'bX && ^(main_get_sos_exit_i_i_scevgep_i2_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_read_markers_exit_i_p_jinfo_jpeg_data_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB29_80 & memory_controller_waitrequest == 1'd0)
begin
main__lr_ph_i1_i_i_ReadBuf_3_phi_temp <= main_32_60_reg;
if (^reset !== 1'bX && ^(main_32_60_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_phi_temp"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd0 & main__preheader_i_i_i_98 == 1'd1)
begin
main__lr_ph_i1_i_i_ReadBuf_3_phi_temp <= main_32_60_reg;
if (^reset !== 1'bX && ^(main_32_60_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_phi_temp"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ReadBuf.3 = phi i8* [ %105, %159 ], [ %60, %.preheader.i.i.i.thread ], [ %60, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd0 & main_159_160 == 1'd1)
begin
main__lr_ph_i1_i_i_ReadBuf_3_phi_temp <= main__lr_ph_i1_i_i_105_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_105_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ReadBuf_3_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i1.i.i*/
/* %ci.02.i.i.i = phi i32 [ %tmp12.i.i.i, %159 ], [ 0, %.preheader.i.i.i.thread ], [ 0, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB29_80 & memory_controller_waitrequest == 1'd0)
begin
main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ci.02.i.i.i = phi i32 [ %tmp12.i.i.i, %159 ], [ 0, %.preheader.i.i.i.thread ], [ 0, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd0 & main__preheader_i_i_i_98 == 1'd1)
begin
main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.i1.i.i*/
/* %ci.02.i.i.i = phi i32 [ %tmp12.i.i.i, %159 ], [ 0, %.preheader.i.i.i.thread ], [ 0, %.preheader.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd0 & main_159_160 == 1'd1)
begin
main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp <= main__lr_ph_i1_i_i_tmp12_i_i_i_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_tmp12_i_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i1_i_i_ci_02_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB30_81 & memory_controller_waitrequest == 1'd0 & main__preheader_i_i_i_98 == 1'd0)
begin
main___crit_edge_i_i_i_ReadBuf_4_phi_temp <= main_32_60_reg;
if (^reset !== 1'bX && ^(main_32_60_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_phi_temp"); $finish; end
end
/* main: %._crit_edge.i.i.i*/
/* %ReadBuf.4 = phi i8* [ %60, %.preheader.i.i.i ], [ %105, %159 ]*/
if (cur_state == LEGUP_F_main_BB41_139 & memory_controller_waitrequest == 1'd0 & main_159_160 == 1'd0)
begin
main___crit_edge_i_i_i_ReadBuf_4_phi_temp <= main__lr_ph_i1_i_i_105_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i1_i_i_105_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i_i_i_ReadBuf_4_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB49_157 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_i_get_sos_0_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_phi_temp"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %i_get_sos.0 = phi i32 [ %246, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB62_199 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_i_get_sos_0_phi_temp <= main_245_246;
if (^reset !== 1'bX && ^(main_245_246) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_i_get_sos_0_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB49_157 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_ReadBuf_5_phi_temp <= main_167_177_reg;
if (^reset !== 1'bX && ^(main_167_177_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_phi_temp"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %ReadBuf.5 = phi i8* [ %198, %245 ], [ %177, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB62_199 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_ReadBuf_5_phi_temp <= main_194_198_reg;
if (^reset !== 1'bX && ^(main_194_198_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_ReadBuf_5_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB49_157 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_192_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_192_phi_temp"); $finish; end
end
/* main: %.preheader5.i.i.i*/
/* %192 = phi i32 [ %247, %245 ], [ 0, %.preheader5.i.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB62_199 & memory_controller_waitrequest == 1'd0)
begin
main__preheader5_i_i_i_192_phi_temp <= main_245_247;
if (^reset !== 1'bX && ^(main_245_247) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader5_i_i_i_192_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB51_162 & memory_controller_waitrequest == 1'd0)
begin
main_200_201_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_phi_temp"); $finish; end
end
/* main: %200*/
/* %201 = phi i32 [ 0, %194 ], [ %208, %207 ]*/
if (cur_state == LEGUP_F_main_BB54_167 & memory_controller_waitrequest == 1'd0)
begin
main_200_201_phi_temp <= main_207_208;
if (^reset !== 1'bX && ^(main_207_208) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_200_201_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd1)
begin
main__lr_ph5_i_i_i_i_get_dht_2_phi_temp <= main__backedge_i_i_outer_i_get_dht_1_ph_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer_i_get_dht_1_ph_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_phi_temp"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %i_get_dht.2 = phi i32 [ %302, %._crit_edge.i12.i.i ], [ %i_get_dht.1.ph, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd1)
begin
main__lr_ph5_i_i_i_i_get_dht_2_phi_temp <= main_301_302_reg;
if (^reset !== 1'bX && ^(main_301_302_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_i_get_dht_2_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %ReadBuf.6 = phi i8* [ %ReadBuf.7, %._crit_edge.i12.i.i ], [ %253, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd1)
begin
main__lr_ph5_i_i_i_ReadBuf_6_phi_temp <= main_248_253_reg;
if (^reset !== 1'bX && ^(main_248_253_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_ReadBuf_6_phi_temp"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %ReadBuf.6 = phi i8* [ %ReadBuf.7, %._crit_edge.i12.i.i ], [ %253, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd1)
begin
main__lr_ph5_i_i_i_ReadBuf_6_phi_temp <= main___crit_edge_i12_i_i_ReadBuf_7;
if (^reset !== 1'bX && ^(main___crit_edge_i12_i_i_ReadBuf_7) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_ReadBuf_6_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB66_211 & memory_controller_waitrequest == 1'd0 & main__preheader_i7_i_i_265 == 1'd1)
begin
main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp <= main_248_258_reg;
if (^reset !== 1'bX && ^(main_248_258_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph5.i.i.i*/
/* %length.04.i.i.i = phi i32 [ %310, %._crit_edge.i12.i.i ], [ %258, %.preheader.i7.i.i ]*/
if (cur_state == LEGUP_F_main_BB78_239 & memory_controller_waitrequest == 1'd0 & main___crit_edge_i12_i_i_311 == 1'd1)
begin
main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp <= main___crit_edge_i12_i_i_310;
if (^reset !== 1'bX && ^(main___crit_edge_i12_i_i_310) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph5_i_i_i_length_04_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB70_222 & memory_controller_waitrequest == 1'd0)
begin
main_286_p_xhtbl_huffval_0_i_i_i_phi_temp <= main_279_282;
if (^reset !== 1'bX && ^(main_279_282) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_huffval_0_i_i_i_phi_temp"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_huffval.0.i.i.i = phi i32* [ %282, %279 ], [ %285, %283 ]*/
if (cur_state == LEGUP_F_main_BB71_223 & memory_controller_waitrequest == 1'd0)
begin
main_286_p_xhtbl_huffval_0_i_i_i_phi_temp <= main_283_285;
if (^reset !== 1'bX && ^(main_283_285) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_huffval_0_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB70_222 & memory_controller_waitrequest == 1'd0)
begin
main_286_p_xhtbl_bits_0_i_i_i_phi_temp <= main_279_281;
if (^reset !== 1'bX && ^(main_279_281) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_bits_0_i_i_i_phi_temp"); $finish; end
end
/* main: %286*/
/* %p_xhtbl_bits.0.i.i.i = phi i32* [ %281, %279 ], [ %284, %283 ]*/
if (cur_state == LEGUP_F_main_BB71_223 & memory_controller_waitrequest == 1'd0)
begin
main_286_p_xhtbl_bits_0_i_i_i_phi_temp <= main_283_284;
if (^reset !== 1'bX && ^(main_283_284) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_286_p_xhtbl_bits_0_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %287*/
/* %288 = phi i8* [ %266, %286 ], [ %289, %287 ]*/
if (cur_state == LEGUP_F_main_BB72_224 & memory_controller_waitrequest == 1'd0)
begin
main_287_288_phi_temp <= main__lr_ph5_i_i_i_266_reg;
if (^reset !== 1'bX && ^(main__lr_ph5_i_i_i_266_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_288_phi_temp"); $finish; end
end
/* main: %287*/
/* %288 = phi i8* [ %266, %286 ], [ %289, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd0 & main_287_exitcond_i_i_i_reg == 1'd0)
begin
main_287_288_phi_temp <= main_287_289_reg;
if (^reset !== 1'bX && ^(main_287_289_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_288_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %287*/
/* %indvar.i.i.i = phi i32 [ 0, %286 ], [ %tmp.i8.i.i, %287 ]*/
if (cur_state == LEGUP_F_main_BB72_224 & memory_controller_waitrequest == 1'd0)
begin
main_287_indvar_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_indvar_i_i_i_phi_temp"); $finish; end
end
/* main: %287*/
/* %indvar.i.i.i = phi i32 [ 0, %286 ], [ %tmp.i8.i.i, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd0 & main_287_exitcond_i_i_i_reg == 1'd0)
begin
main_287_indvar_i_i_i_phi_temp <= main_287_tmp_i8_i_i_reg;
if (^reset !== 1'bX && ^(main_287_tmp_i8_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_indvar_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB72_224 & memory_controller_waitrequest == 1'd0)
begin
main_287_count_01_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_count_01_i_i_i_phi_temp"); $finish; end
end
/* main: %287*/
/* %count.01.i.i.i = phi i32 [ 0, %286 ], [ %292, %287 ]*/
if (cur_state == LEGUP_F_main_BB73_227 & memory_controller_waitrequest == 1'd0 & main_287_exitcond_i_i_i_reg == 1'd0)
begin
main_287_count_01_i_i_i_phi_temp <= main_287_292;
if (^reset !== 1'bX && ^(main_287_292) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_287_count_01_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %304 = phi i8* [ %305, %.lr.ph.i10.i.i ], [ %289, %301 ]*/
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd0 & main_301_303 == 1'd1)
begin
main__lr_ph_i10_i_i_304_phi_temp <= main_287_289_reg;
if (^reset !== 1'bX && ^(main_287_289_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_304_phi_temp"); $finish; end
end
/* main: %.lr.ph.i10.i.i*/
/* %304 = phi i8* [ %305, %.lr.ph.i10.i.i ], [ %289, %301 ]*/
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i10_i_i_exitcond7_i_i_i_reg == 1'd0)
begin
main__lr_ph_i10_i_i_304_phi_temp <= main__lr_ph_i10_i_i_305_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_305_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_304_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i10.i.i*/
/* %i.13.i.i.i = phi i32 [ %308, %.lr.ph.i10.i.i ], [ 0, %301 ]*/
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd0 & main_301_303 == 1'd1)
begin
main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.i10.i.i*/
/* %i.13.i.i.i = phi i32 [ %308, %.lr.ph.i10.i.i ], [ 0, %301 ]*/
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i10_i_i_exitcond7_i_i_i_reg == 1'd0)
begin
main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp <= main__lr_ph_i10_i_i_308_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_308_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i10_i_i_i_13_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %._crit_edge.i12.i.i*/
/* %ReadBuf.7 = phi i8* [ %289, %301 ], [ %305, %.lr.ph.i10.i.i ]*/
if (cur_state == LEGUP_F_main_BB76_235 & memory_controller_waitrequest == 1'd0 & main_301_303 == 1'd0)
begin
main___crit_edge_i12_i_i_ReadBuf_7_phi_temp <= main_287_289_reg;
if (^reset !== 1'bX && ^(main_287_289_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i12_i_i_ReadBuf_7_phi_temp"); $finish; end
end
/* main: %._crit_edge.i12.i.i*/
/* %ReadBuf.7 = phi i8* [ %289, %301 ], [ %305, %.lr.ph.i10.i.i ]*/
if (cur_state == LEGUP_F_main_BB77_238 & memory_controller_waitrequest == 1'd0 & main__lr_ph_i10_i_i_exitcond7_i_i_i_reg == 1'd1)
begin
main___crit_edge_i12_i_i_ReadBuf_7_phi_temp <= main__lr_ph_i10_i_i_305_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i10_i_i_305_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___crit_edge_i12_i_i_ReadBuf_7_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd1)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp <= main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg;
if (^reset !== 1'bX && ^(main__backedge_i_i_outer4_i_get_dqt_1_ph6_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %i_get_dqt.2 = phi i32 [ %352, %.us-lcssa.us.i.i.i ], [ %i_get_dqt.1.ph6, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd1)
begin
main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp <= main_351_352_reg;
if (^reset !== 1'bX && ^(main_351_352_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_i_get_dqt_2_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %330 = phi i8* [ %ReadBuf.8, %.us-lcssa.us.i.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd1)
begin
main__lr_ph_i15_i_i_330_phi_temp <= main_312_317_reg;
if (^reset !== 1'bX && ^(main_312_317_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_330_phi_temp"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %330 = phi i8* [ %ReadBuf.8, %.us-lcssa.us.i.i.i ], [ %317, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd1)
begin
main__lr_ph_i15_i_i_330_phi_temp <= main__us_lcssa_us_i_i_i_ReadBuf_8;
if (^reset !== 1'bX && ^(main__us_lcssa_us_i_i_i_ReadBuf_8) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_330_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB81_250 & memory_controller_waitrequest == 1'd0 & main__preheader_i13_i_i_329 == 1'd1)
begin
main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp <= main_312_322_reg;
if (^reset !== 1'bX && ^(main_312_322_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.i15.i.i*/
/* %length.02.i.i.i = phi i32 [ %..i.i.i, %.us-lcssa.us.i.i.i ], [ %322, %.preheader.i13.i.i ]*/
if (cur_state == LEGUP_F_main_BB89_276 & memory_controller_waitrequest == 1'd0 & main__us_lcssa_us_i_i_i_373 == 1'd1)
begin
main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp <= main__us_lcssa_us_i_i_i___i_i_i;
if (^reset !== 1'bX && ^(main__us_lcssa_us_i_i_i___i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_i15_i_i_length_02_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %354 = phi i8* [ %355, %.split.us.i.i.i ], [ %331, %351 ]*/
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd1)
begin
main__split_us_i_i_i_354_phi_temp <= main__lr_ph_i15_i_i_331_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_331_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_354_phi_temp"); $finish; end
end
/* main: %.split.us.i.i.i*/
/* %354 = phi i8* [ %355, %.split.us.i.i.i ], [ %331, %351 ]*/
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd0 & main__split_us_i_i_i_exitcond_i17_i_i_reg == 1'd0)
begin
main__split_us_i_i_i_354_phi_temp <= main__split_us_i_i_i_355_reg;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_355_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_354_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.split.us.i.i.i*/
/* %i.01.us.i.i.i = phi i32 [ %360, %.split.us.i.i.i ], [ 0, %351 ]*/
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd1)
begin
main__split_us_i_i_i_i_01_us_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_i_01_us_i_i_i_phi_temp"); $finish; end
end
/* main: %.split.us.i.i.i*/
/* %i.01.us.i.i.i = phi i32 [ %360, %.split.us.i.i.i ], [ 0, %351 ]*/
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd0 & main__split_us_i_i_i_exitcond_i17_i_i_reg == 1'd0)
begin
main__split_us_i_i_i_i_01_us_i_i_i_phi_temp <= main__split_us_i_i_i_360_reg;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_360_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__split_us_i_i_i_i_01_us_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %361 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %331, %351 ]*/
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd0)
begin
main___split_crit_edge_i_i_i_361_phi_temp <= main__lr_ph_i15_i_i_331_reg;
if (^reset !== 1'bX && ^(main__lr_ph_i15_i_i_331_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_361_phi_temp"); $finish; end
end
/* main: %..split_crit_edge.i.i.i*/
/* %361 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %331, %351 ]*/
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd0 & main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg == 1'd0)
begin
main___split_crit_edge_i_i_i_361_phi_temp <= main___split_crit_edge_i_i_i_366_reg;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_366_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_361_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %..split_crit_edge.i.i.i*/
/* %i.01.i.i.i = phi i32 [ %372, %..split_crit_edge.i.i.i ], [ 0, %351 ]*/
if (cur_state == LEGUP_F_main_BB86_266 & memory_controller_waitrequest == 1'd0 & main_351_353 == 1'd0)
begin
main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp"); $finish; end
end
/* main: %..split_crit_edge.i.i.i*/
/* %i.01.i.i.i = phi i32 [ %372, %..split_crit_edge.i.i.i ], [ 0, %351 ]*/
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd0 & main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg == 1'd0)
begin
main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp <= main___split_crit_edge_i_i_i_372_reg;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_372_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main___split_crit_edge_i_i_i_i_01_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.us-lcssa.us.i.i.i*/
/* %ReadBuf.8 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %355, %.split.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB87_270 & memory_controller_waitrequest == 1'd0 & main__split_us_i_i_i_exitcond_i17_i_i_reg == 1'd1)
begin
main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp <= main__split_us_i_i_i_355_reg;
if (^reset !== 1'bX && ^(main__split_us_i_i_i_355_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp"); $finish; end
end
/* main: %.us-lcssa.us.i.i.i*/
/* %ReadBuf.8 = phi i8* [ %366, %..split_crit_edge.i.i.i ], [ %355, %.split.us.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB88_275 & memory_controller_waitrequest == 1'd0 & main___split_crit_edge_i_i_i_exitcond3_i_i_i_reg == 1'd1)
begin
main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp <= main___split_crit_edge_i_i_i_366_reg;
if (^reset !== 1'bX && ^(main___split_crit_edge_i_i_i_366_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__us_lcssa_us_i_i_i_ReadBuf_8_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader21.i.i*/
/* %CurrentMCU.026.i.i = phi i32 [ %tmp143.i.i, %447 ], [ 0, %.preheader21.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB92_356 & memory_controller_waitrequest == 1'd0)
begin
main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp"); $finish; end
end
/* main: %.preheader21.i.i*/
/* %CurrentMCU.026.i.i = phi i32 [ %tmp143.i.i, %447 ], [ 0, %.preheader21.i.i.preheader ]*/
if (cur_state == LEGUP_F_main_BB113_405 & memory_controller_waitrequest == 1'd0 & main_447_448 == 1'd1)
begin
main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp <= main__preheader21_i_i_tmp143_i_i_reg;
if (^reset !== 1'bX && ^(main__preheader21_i_i_tmp143_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader21_i_i_CurrentMCU_026_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_function_call_365 & memory_controller_waitrequest == 1'd0)
begin
main_392_i_01_i_i1_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_i_01_i_i1_i_phi_temp"); $finish; end
end
/* main: %392*/
/* %i.01.i.i1.i = phi i32 [ %426, %425 ], [ 0, %.preheader21.i.i ]*/
if (cur_state == LEGUP_F_main_BB103_382 & memory_controller_waitrequest == 1'd0 & main_425_exitcond53_i_i_reg == 1'd0)
begin
main_392_i_01_i_i1_i_phi_temp <= main_425_426_reg;
if (^reset !== 1'bX && ^(main_425_426_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_392_i_01_i_i1_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB94_371 & memory_controller_waitrequest == 1'd0 & main_392_411 == 1'd1)
begin
main_415_r_0_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_phi_temp"); $finish; end
end
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB95_372 & memory_controller_waitrequest == 1'd0 & main_412_413 == 1'd0)
begin
main_415_r_0_i_i_i_phi_temp <= main_392_402_reg;
if (^reset !== 1'bX && ^(main_392_402_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_phi_temp"); $finish; end
end
/* main: %415*/
/* %r.0.i.i.i = phi i32 [ 255, %414 ], [ %402, %412 ], [ 0, %392 ]*/
if (cur_state == LEGUP_F_main_BB96_373 & memory_controller_waitrequest == 1'd0)
begin
main_415_r_0_i_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_415_r_0_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB97_374 & memory_controller_waitrequest == 1'd0 & main_415_416 == 1'd1)
begin
main_420_g_0_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_phi_temp"); $finish; end
end
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB98_375 & memory_controller_waitrequest == 1'd0 & main_417_418 == 1'd0)
begin
main_420_g_0_i_i_i_phi_temp <= main_392_407_reg;
if (^reset !== 1'bX && ^(main_392_407_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_phi_temp"); $finish; end
end
/* main: %420*/
/* %g.0.i.i.i = phi i32 [ 255, %419 ], [ %407, %417 ], [ 0, %415 ]*/
if (cur_state == LEGUP_F_main_BB99_376 & memory_controller_waitrequest == 1'd0)
begin
main_420_g_0_i_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_420_g_0_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB100_377 & memory_controller_waitrequest == 1'd0 & main_420_421 == 1'd1)
begin
main_425_b_0_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_phi_temp"); $finish; end
end
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB101_378 & memory_controller_waitrequest == 1'd0 & main_422_423 == 1'd0)
begin
main_425_b_0_i_i_i_phi_temp <= main_392_410_reg;
if (^reset !== 1'bX && ^(main_392_410_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_phi_temp"); $finish; end
end
/* main: %425*/
/* %b.0.i.i.i = phi i32 [ 255, %424 ], [ %410, %422 ], [ 0, %420 ]*/
if (cur_state == LEGUP_F_main_BB102_379 & memory_controller_waitrequest == 1'd0)
begin
main_425_b_0_i_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_425_b_0_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %432*/
/* %433 = phi i32 [ %.pre.i.i, %YuvToRgb.exit.loopexit.i.i ], [ %446, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB104_388 & memory_controller_waitrequest == 1'd0)
begin
main_432_433_phi_temp <= main_YuvToRgb_exit_loopexit_i_i__pre_i_i_reg;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit_loopexit_i_i__pre_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_433_phi_temp"); $finish; end
end
/* main: %432*/
/* %433 = phi i32 [ %.pre.i.i, %YuvToRgb.exit.loopexit.i.i ], [ %446, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB112_404 & memory_controller_waitrequest == 1'd0 & main_WriteBlock_exit_i_i_exitcond116_i_i == 1'd0)
begin
main_432_433_phi_temp <= main_WriteBlock_exit_i_i_446;
if (^reset !== 1'bX && ^(main_WriteBlock_exit_i_i_446) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_433_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB104_388 & memory_controller_waitrequest == 1'd0)
begin
main_432_i_324_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_phi_temp"); $finish; end
end
/* main: %432*/
/* %i.324.i.i = phi i32 [ 0, %YuvToRgb.exit.loopexit.i.i ], [ %tmp141.i.i, %WriteBlock.exit.i.i ]*/
if (cur_state == LEGUP_F_main_BB112_404 & memory_controller_waitrequest == 1'd0 & main_WriteBlock_exit_i_i_exitcond116_i_i == 1'd0)
begin
main_432_i_324_i_i_phi_temp <= main_432_tmp141_i_i_reg;
if (^reset !== 1'bX && ^(main_432_tmp141_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_432_i_324_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB106_394 & memory_controller_waitrequest == 1'd0)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp"); $finish; end
end
/* main: %.lr.ph.us.i.i.i.i*/
/* %indvar17.i.i.i.i = phi i32 [ %indvar.next18.i.i.i.i, %439 ], [ 0, %.lr.ph8.split.us.i.i.i.i ]*/
if (cur_state == LEGUP_F_main_BB107_395 & memory_controller_waitrequest == 1'd0 & main_439_exitcond93_i_i == 1'd0)
begin
main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp <= main_439_indvar_next18_i_i_i_i;
if (^reset !== 1'bX && ^(main_439_indvar_next18_i_i_i_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__lr_ph_us_i_i_i_i_indvar17_i_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %440*/
/* %indvar.i.i.i.i = phi i32 [ 0, %.lr.ph.us.i.i.i.i ], [ %indvar.next.i.i.i.i, %440 ]*/
if (cur_state == LEGUP_F_main_BB108_398 & memory_controller_waitrequest == 1'd0 & main_440_exitcond70_i_i_reg == 1'd0)
begin
main_440_indvar_i_i_i_i_phi_temp <= main_440_indvar_next_i_i_i_i_reg;
if (^reset !== 1'bX && ^(main_440_indvar_next_i_i_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_440_indvar_i_i_i_i_phi_temp"); $finish; end
end
/* main: %440*/
/* %indvar.i.i.i.i = phi i32 [ 0, %.lr.ph.us.i.i.i.i ], [ %indvar.next.i.i.i.i, %440 ]*/
if (cur_state == LEGUP_F_main_BB109_399 & memory_controller_waitrequest == 1'd0)
begin
main_440_indvar_i_i_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_440_indvar_i_i_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %WriteBlock.exit.i.i*/
/* %446 = phi i32 [ %443, %WriteOneBlock.exit.i.i.i ], [ 0, %445 ]*/
if (cur_state == LEGUP_F_main_BB110_402 & memory_controller_waitrequest == 1'd0 & main_WriteOneBlock_exit_i_i_i_444 == 1'd1)
begin
main_WriteBlock_exit_i_i_446_phi_temp <= main_WriteOneBlock_exit_i_i_i_443;
if (^reset !== 1'bX && ^(main_WriteOneBlock_exit_i_i_i_443) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_WriteBlock_exit_i_i_446_phi_temp"); $finish; end
end
/* main: %WriteBlock.exit.i.i*/
/* %446 = phi i32 [ %443, %WriteOneBlock.exit.i.i.i ], [ 0, %445 ]*/
if (cur_state == LEGUP_F_main_BB111_403 & memory_controller_waitrequest == 1'd0)
begin
main_WriteBlock_exit_i_i_446_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_WriteBlock_exit_i_i_446_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_F_main_BB115_407 & memory_controller_waitrequest == 1'd0)
begin
main__preheader_i_i_indvar_i7_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_indvar_i7_i_phi_temp"); $finish; end
end
/* main: %.preheader.i.i*/
/* %indvar.i7.i = phi i32 [ 0, %.preheader.lr.ph.i.i ], [ %indvar.next.i.i, %.loopexit.i.i ]*/
if (cur_state == LEGUP_function_call_453 & memory_controller_waitrequest == 1'd0 & main__loopexit_i_i_490_reg == 1'd1)
begin
main__preheader_i_i_indvar_i7_i_phi_temp <= main__loopexit_i_i_indvar_next_i_i_reg;
if (^reset !== 1'bX && ^(main__loopexit_i_i_indvar_next_i_i_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_i_i_indvar_i7_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_function_call_425 & memory_controller_waitrequest == 1'd0)
begin
main__preheader16_i_i_i_517_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_phi_temp"); $finish; end
end
/* main: %.preheader16.i.i*/
/* %i.517.i.i = phi i32 [ 0, %.preheader.i.i ], [ %489, %YuvToRgb.exit13.i.i ]*/
if (cur_state == LEGUP_F_main_BB128_444 & memory_controller_waitrequest == 1'd0 & main_YuvToRgb_exit13_i_i_exitcond35_i_i == 1'd0)
begin
main__preheader16_i_i_i_517_i_i_phi_temp <= main_YuvToRgb_exit13_i_i_489;
if (^reset !== 1'bX && ^(main_YuvToRgb_exit13_i_i_489) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader16_i_i_i_517_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB117_426 & memory_controller_waitrequest == 1'd0)
begin
main_454_i_01_i2_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_i_01_i2_i_i_phi_temp"); $finish; end
end
/* main: %454*/
/* %i.01.i2.i.i = phi i32 [ %488, %487 ], [ 0, %.preheader16.i.i ]*/
if (cur_state == LEGUP_F_main_BB127_443 & memory_controller_waitrequest == 1'd0 & main_487_exitcond_i_i_reg == 1'd0)
begin
main_454_i_01_i2_i_i_phi_temp <= main_487_488_reg;
if (^reset !== 1'bX && ^(main_487_488_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_454_i_01_i2_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB118_432 & memory_controller_waitrequest == 1'd0 & main_454_473 == 1'd1)
begin
main_477_r_0_i9_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_phi_temp"); $finish; end
end
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB119_433 & memory_controller_waitrequest == 1'd0 & main_474_475 == 1'd0)
begin
main_477_r_0_i9_i_i_phi_temp <= main_454_464_reg;
if (^reset !== 1'bX && ^(main_454_464_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_phi_temp"); $finish; end
end
/* main: %477*/
/* %r.0.i9.i.i = phi i32 [ 255, %476 ], [ %464, %474 ], [ 0, %454 ]*/
if (cur_state == LEGUP_F_main_BB120_434 & memory_controller_waitrequest == 1'd0)
begin
main_477_r_0_i9_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_477_r_0_i9_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB121_435 & memory_controller_waitrequest == 1'd0 & main_477_478 == 1'd1)
begin
main_482_g_0_i10_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_phi_temp"); $finish; end
end
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB122_436 & memory_controller_waitrequest == 1'd0 & main_479_480 == 1'd0)
begin
main_482_g_0_i10_i_i_phi_temp <= main_454_469_reg;
if (^reset !== 1'bX && ^(main_454_469_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_phi_temp"); $finish; end
end
/* main: %482*/
/* %g.0.i10.i.i = phi i32 [ 255, %481 ], [ %469, %479 ], [ 0, %477 ]*/
if (cur_state == LEGUP_F_main_BB123_437 & memory_controller_waitrequest == 1'd0)
begin
main_482_g_0_i10_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_482_g_0_i10_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB124_438 & memory_controller_waitrequest == 1'd0 & main_482_483 == 1'd1)
begin
main_487_b_0_i11_i_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_phi_temp"); $finish; end
end
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB125_439 & memory_controller_waitrequest == 1'd0 & main_484_485 == 1'd0)
begin
main_487_b_0_i11_i_i_phi_temp <= main_454_472_reg;
if (^reset !== 1'bX && ^(main_454_472_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_phi_temp"); $finish; end
end
/* main: %487*/
/* %b.0.i11.i.i = phi i32 [ 255, %486 ], [ %472, %484 ], [ 0, %482 ]*/
if (cur_state == LEGUP_F_main_BB126_440 & memory_controller_waitrequest == 1'd0)
begin
main_487_b_0_i11_i_i_phi_temp <= 32'd255;
if (^reset !== 1'bX && ^(32'd255) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_487_b_0_i11_i_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB130_456 & memory_controller_waitrequest == 1'd0)
begin
main_491_492_phi_temp <= main_decode_start_exit_i_main_result_promoted3_i;
if (^reset !== 1'bX && ^(main_decode_start_exit_i_main_result_promoted3_i) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_492_phi_temp"); $finish; end
end
/* main: %491*/
/* %492 = phi i32 [ %main_result.promoted3.i, %decode_start.exit.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd0)
begin
main_491_492_phi_temp <= main_491_497;
if (^reset !== 1'bX && ^(main_491_497) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_492_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %491*/
/* %j.01.i = phi i32 [ 0, %decode_start.exit.i ], [ %498, %491 ]*/
if (cur_state == LEGUP_F_main_BB130_456 & memory_controller_waitrequest == 1'd0)
begin
main_491_j_01_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_j_01_i_phi_temp"); $finish; end
end
/* main: %491*/
/* %j.01.i = phi i32 [ 0, %decode_start.exit.i ], [ %498, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd0)
begin
main_491_j_01_i_phi_temp <= main_491_498_reg;
if (^reset !== 1'bX && ^(main_491_498_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main_491_j_01_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd1)
begin
main__preheader_1_i_499_phi_temp <= main_491_497;
if (^reset !== 1'bX && ^(main_491_497) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_499_phi_temp"); $finish; end
end
/* main: %.preheader.1.i*/
/* %499 = phi i32 [ %504, %.preheader.1.i ], [ %497, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd0)
begin
main__preheader_1_i_499_phi_temp <= main__preheader_1_i_504;
if (^reset !== 1'bX && ^(main__preheader_1_i_504) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_499_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader.1.i*/
/* %j.01.1.i = phi i32 [ %505, %.preheader.1.i ], [ 0, %491 ]*/
if (cur_state == LEGUP_F_main_BB131_460 & memory_controller_waitrequest == 1'd0 & main_491_exitcond_i_reg == 1'd1)
begin
main__preheader_1_i_j_01_1_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_j_01_1_i_phi_temp"); $finish; end
end
/* main: %.preheader.1.i*/
/* %j.01.1.i = phi i32 [ %505, %.preheader.1.i ], [ 0, %491 ]*/
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd0)
begin
main__preheader_1_i_j_01_1_i_phi_temp <= main__preheader_1_i_505_reg;
if (^reset !== 1'bX && ^(main__preheader_1_i_505_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_1_i_j_01_1_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd1)
begin
main__preheader_2_i_513_phi_temp <= main__preheader_1_i_504;
if (^reset !== 1'bX && ^(main__preheader_1_i_504) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_513_phi_temp"); $finish; end
end
/* main: %.preheader.2.i*/
/* %513 = phi i32 [ %518, %.preheader.2.i ], [ %504, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_472 & memory_controller_waitrequest == 1'd0 & main__preheader_2_i_exitcond_2_i_reg == 1'd0)
begin
main__preheader_2_i_513_phi_temp <= main__preheader_2_i_518;
if (^reset !== 1'bX && ^(main__preheader_2_i_518) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_513_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
/* main: %.preheader.2.i*/
/* %j.01.2.i = phi i32 [ %519, %.preheader.2.i ], [ 0, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB132_464 & memory_controller_waitrequest == 1'd0 & main__preheader_1_i_exitcond_1_i_reg == 1'd1)
begin
main__preheader_2_i_j_01_2_i_phi_temp <= 32'd0;
if (^reset !== 1'bX && ^(32'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_j_01_2_i_phi_temp"); $finish; end
end
/* main: %.preheader.2.i*/
/* %j.01.2.i = phi i32 [ %519, %.preheader.2.i ], [ 0, %.preheader.1.i ]*/
if (cur_state == LEGUP_F_main_BB134_472 & memory_controller_waitrequest == 1'd0 & main__preheader_2_i_exitcond_2_i_reg == 1'd0)
begin
main__preheader_2_i_j_01_2_i_phi_temp <= main__preheader_2_i_519_reg;
if (^reset !== 1'bX && ^(main__preheader_2_i_519_reg) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to main__preheader_2_i_j_01_2_i_phi_temp"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
finish <= 1'd0;
if (^reset !== 1'bX && ^(1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
/* main: %524*/
/* ret i32 %525*/
if (cur_state == LEGUP_F_main_BB137_477)
begin
finish <= memory_controller_waitrequest == 1'd0;
if (^reset !== 1'bX && ^(memory_controller_waitrequest == 1'd0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to finish"); $finish; end
end
end
always @(posedge clk) begin
if (cur_state == LEGUP_0)
begin
return_val <= 0;
if (^reset !== 1'bX && ^(0) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
/* main: %524*/
/* ret i32 %525*/
if (cur_state == LEGUP_F_main_BB137_477)
begin
return_val <= main_524_525;
if (^reset !== 1'bX && ^(main_524_525) === 1'bX) begin $display ("ERROR: Right hand side is 'X'. Assigned to return_val"); $finish; end
end
end
always @(*) begin
memory_controller_address = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_address = 0;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
memory_controller_address = huff_make_dhuff_tb_memory_controller_address;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
memory_controller_address = huff_make_dhuff_tb_memory_controller_address;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
memory_controller_address = huff_make_dhuff_tb_memory_controller_address;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
memory_controller_address = huff_make_dhuff_tb_memory_controller_address;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
memory_controller_address = decode_block_memory_controller_address;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
memory_controller_address = Write4Blocks_memory_controller_address;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
memory_controller_address = Write4Blocks_memory_controller_address;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
memory_controller_address = Write4Blocks_memory_controller_address;
end
/* main: %0*/
/* store i32 0, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB0_1)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %1*/
/* %2 = load i8* %scevgep13.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
memory_controller_address = main_1_scevgep13_i;
end
/* main: %1*/
/* store i8 %2, i8* %c.06.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_4)
begin
memory_controller_address = main_1_c_06_i_reg;
end
/* main: %6*/
/* %8 = load i8* %ReadBuf.1, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_10)
begin
memory_controller_address = main__backedge_i_i_ReadBuf_1_reg;
end
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_11)
begin
memory_controller_address = main_6_7_reg;
end
/* main: %first_marker.exit.i.i*/
/* %16 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %first_marker.exit.i.i*/
/* store i32 %17, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_17)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.loopexit3.i.i.i*/
/* %c.0.in2.i.i.i = load i8* %18, align 1*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
memory_controller_address = main__loopexit3_i_i_i_18;
end
/* main: %.lr.ph.i.i.i*/
/* %c.0.in.i.i.i = load i8* %scevgep.i.i, align 1*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
memory_controller_address = main__lr_ph_i_i_i_scevgep_i_i;
end
/* main: %.loopexit.i.i.i*/
/* %21 = load i8* %scevgep11.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB15_27)
begin
memory_controller_address = main__loopexit_i_i_i_scevgep11_i_i;
end
/* main: %next_marker.exit.i.i*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB17_32)
begin
memory_controller_address = main_next_marker_exit_i_i_25_reg;
end
/* main: %28*/
/* %29 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_35)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %28*/
/* store i32 %30, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_37)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %32*/
/* %34 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
memory_controller_address = main_next_marker_exit_i_i_ReadBuf_2_reg;
end
/* main: %32*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_40)
begin
memory_controller_address = main_32_33_reg;
end
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_41)
begin
memory_controller_address = main_32_37_reg;
end
/* main: %32*/
/* %45 = load i8* %42, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
memory_controller_address = main_32_42_reg;
end
/* main: %32*/
/* %49 = load i8* %44, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
memory_controller_address = main_32_44_reg;
end
/* main: %32*/
/* store i16 %51, i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_45)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* main: %32*/
/* %53 = load i8* %48, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_46)
begin
memory_controller_address = main_32_48_reg;
end
/* main: %32*/
/* %57 = load i8* %52, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_47)
begin
memory_controller_address = main_32_52_reg;
end
/* main: %32*/
/* store i16 %59, i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_49)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_50)
begin
memory_controller_address = main_32_56_reg;
end
/* main: %32*/
/* %65 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* main: %32*/
/* %68 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_55)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* main: %74*/
/* %75 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_58)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %74*/
/* store i32 %76, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_60)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %79*/
/* %80 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_62)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %79*/
/* store i32 %81, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_64)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %82*/
/* %83 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB24_65)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* main: %85*/
/* %86 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_68)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %85*/
/* store i32 %87, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_70)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %88*/
/* %89 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB26_71)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* main: %91*/
/* %92 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_74)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %91*/
/* store i32 %93, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_76)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.preheader.i.i.i.thread*/
/* %96 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_78)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.preheader.i.i.i.thread*/
/* store i32 %97, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_80)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %tmp.i.i.i, i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep_i_i_i;
end
/* main: %.lr.ph.i1.i.i*/
/* %100 = load i8* %ReadBuf.3, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_83)
begin
memory_controller_address = main__lr_ph_i1_i_i_ReadBuf_3_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %100, i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_85)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep3_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %102 = load i8* %99, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_86)
begin
memory_controller_address = main__lr_ph_i1_i_i_99_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %103, i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep4_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %104, i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_89)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep5_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %106 = load i8* %101, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_90)
begin
memory_controller_address = main__lr_ph_i1_i_i_101_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %106, i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep6_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %109 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_93)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep3_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %112 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_96)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep4_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %115 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_99)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep5_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %118 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_102)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep6_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %121 = load i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_105)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep_i_i_i_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* %123 = load i32* %scevgep7.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB31_106)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep7_i_i_i_reg;
end
/* main: %125*/
/* %126 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_109)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %125*/
/* store i32 %127, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_111)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %128*/
/* %129 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB33_112)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep3_i_i_i_reg;
end
/* main: %128*/
/* %131 = load i32* %scevgep8.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB33_113)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep8_i_i_i_reg;
end
/* main: %133*/
/* %134 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_116)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %133*/
/* store i32 %135, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_118)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %136*/
/* %137 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB35_119)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep4_i_i_i_reg;
end
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB35_120)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep9_i_i_i_reg;
end
/* main: %141*/
/* %142 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_123)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %141*/
/* store i32 %143, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_125)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %144*/
/* %145 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB37_126)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep5_i_i_i_reg;
end
/* main: %148*/
/* %149 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_129)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %148*/
/* store i32 %150, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_131)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %151*/
/* %152 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB39_132)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep6_i_i_i_reg;
end
/* main: %151*/
/* %154 = load i32* %scevgep11.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB39_133)
begin
memory_controller_address = main__lr_ph_i1_i_i_scevgep11_i_i_i_reg;
end
/* main: %156*/
/* %157 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_136)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %156*/
/* store i32 %158, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_138)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %._crit_edge.i.i.i*/
/* %161 = load i8* getelementptr inbounds ([3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 0), align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
memory_controller_address = `TAG_g_p_jinfo_comps_info_h_samp_factor_a;
end
/* main: %167*/
/* %169 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
memory_controller_address = main_next_marker_exit_i_i_ReadBuf_2_reg;
end
/* main: %167*/
/* %173 = load i8* %168, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_146)
begin
memory_controller_address = main_167_168_reg;
end
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_147)
begin
memory_controller_address = main_167_172_reg;
end
/* main: %183*/
/* %184 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_150)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %183*/
/* store i32 %185, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_152)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %188*/
/* %189 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_154)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %188*/
/* store i32 %190, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_156)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %194*/
/* %196 = load i8* %ReadBuf.5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
memory_controller_address = main__preheader5_i_i_i_ReadBuf_5_reg;
end
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_160)
begin
memory_controller_address = main_194_195_reg;
end
/* main: %203*/
/* %204 = load i8* %scevgep9.i4.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB53_164)
begin
memory_controller_address = main_203_scevgep9_i4_i_i;
end
/* main: %211*/
/* %212 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %211*/
/* store i32 %213, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_171)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %211*/
/* store i8 %214, i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_172)
begin
memory_controller_address = main_211_scevgep8_i5_i_i_reg;
end
/* main: %211*/
/* store i8 %215, i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
memory_controller_address = main_211_scevgep7_i6_i_i_reg;
end
/* main: %211*/
/* %217 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_174)
begin
memory_controller_address = main_211_scevgep8_i5_i_i_reg;
end
/* main: %211*/
/* %220 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_177)
begin
memory_controller_address = main_211_scevgep7_i6_i_i_reg;
end
/* main: %211*/
/* %224 = load i32* %223, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_180)
begin
memory_controller_address = main_211_223_reg;
end
/* main: %226*/
/* %227 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_183)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %226*/
/* store i32 %228, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_185)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %229*/
/* %230 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB58_186)
begin
memory_controller_address = main_211_scevgep8_i5_i_i_reg;
end
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB58_187)
begin
memory_controller_address = main_229_232_reg;
end
/* main: %235*/
/* %236 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_190)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %235*/
/* store i32 %237, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_192)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %238*/
/* %239 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB60_193)
begin
memory_controller_address = main_211_scevgep7_i6_i_i_reg;
end
/* main: %242*/
/* %243 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_196)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %242*/
/* store i32 %244, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_198)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %248*/
/* %250 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
memory_controller_address = main_next_marker_exit_i_i_ReadBuf_2_reg;
end
/* main: %248*/
/* %254 = load i8* %249, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_202)
begin
memory_controller_address = main_248_249_reg;
end
/* main: %248*/
/* %260 = load i32* %4, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB64_205)
begin
memory_controller_address = main__backedge_i_i_outer_4_reg;
end
/* main: %262*/
/* %263 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_208)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %262*/
/* store i32 %264, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_210)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.lr.ph5.i.i.i*/
/* %267 = load i8* %ReadBuf.6, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
memory_controller_address = main__lr_ph5_i_i_i_ReadBuf_6;
end
/* main: %.lr.ph5.i.i.i*/
/* %271 = load i32* %270, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB67_215)
begin
memory_controller_address = main__lr_ph5_i_i_i_270_reg;
end
/* main: %273*/
/* %274 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_218)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %273*/
/* store i32 %275, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_220)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %287*/
/* %290 = load i8* %288, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
memory_controller_address = main_287_288;
end
/* main: %287*/
/* store i32 %291, i32* %scevgep.i9.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
memory_controller_address = main_287_scevgep_i9_i_i_reg;
end
/* main: %293*/
/* %296 = load i32* %295, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB74_229)
begin
memory_controller_address = main_293_295_reg;
end
/* main: %298*/
/* %299 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_232)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %298*/
/* store i32 %300, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_234)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.lr.ph.i10.i.i*/
/* %306 = load i8* %304, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
memory_controller_address = main__lr_ph_i10_i_i_304;
end
/* main: %.lr.ph.i10.i.i*/
/* store i32 %307, i32* %scevgep8.i11.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB77_238)
begin
memory_controller_address = main__lr_ph_i10_i_i_scevgep8_i11_i_i_reg;
end
/* main: %312*/
/* %314 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
memory_controller_address = main_next_marker_exit_i_i_ReadBuf_2_reg;
end
/* main: %312*/
/* %318 = load i8* %313, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_241)
begin
memory_controller_address = main_312_313_reg;
end
/* main: %312*/
/* %324 = load i32* %5, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB79_244)
begin
memory_controller_address = main__backedge_i_i_outer4_5_reg;
end
/* main: %326*/
/* %327 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_247)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %326*/
/* store i32 %328, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_249)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.lr.ph.i15.i.i*/
/* %332 = load i8* %330, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
memory_controller_address = main__lr_ph_i15_i_i_330;
end
/* main: %.lr.ph.i15.i.i*/
/* %339 = load i32* %338, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB82_254)
begin
memory_controller_address = main__lr_ph_i15_i_i_338_reg;
end
/* main: %341*/
/* %342 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_257)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %341*/
/* store i32 %343, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_259)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %344*/
/* %346 = load i32* %345, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB84_260)
begin
memory_controller_address = main_344_345;
end
/* main: %348*/
/* %349 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_263)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %348*/
/* store i32 %350, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_265)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.split.us.i.i.i*/
/* %356 = load i8* %354, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
memory_controller_address = main__split_us_i_i_i_354;
end
/* main: %.split.us.i.i.i*/
/* %358 = load i32* %scevgep.i16.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_268)
begin
memory_controller_address = main__split_us_i_i_i_scevgep_i16_i_i_reg;
end
/* main: %.split.us.i.i.i*/
/* store i32 %357, i32* %359, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_270)
begin
memory_controller_address = main__split_us_i_i_i_359;
end
/* main: %..split_crit_edge.i.i.i*/
/* %363 = load i8* %361, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
memory_controller_address = main___split_crit_edge_i_i_i_361;
end
/* main: %..split_crit_edge.i.i.i*/
/* %367 = load i8* %362, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_272)
begin
memory_controller_address = main___split_crit_edge_i_i_i_362_reg;
end
/* main: %..split_crit_edge.i.i.i*/
/* %370 = load i32* %scevgep4.i18.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_273)
begin
memory_controller_address = main___split_crit_edge_i_i_i_scevgep4_i18_i_i_reg;
end
/* main: %..split_crit_edge.i.i.i*/
/* store i32 %369, i32* %371, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_275)
begin
memory_controller_address = main___split_crit_edge_i_i_i_371;
end
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_278)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* main: %read_markers.exit.i*/
/* store i32 %383, i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
memory_controller_address = `TAG_g_p_jinfo_MCUWidth_a;
end
/* main: %read_markers.exit.i*/
/* store i32 %385, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_332)
begin
memory_controller_address = `TAG_g_p_jinfo_dc_dhuff_tbl_ml_a;
end
/* main: %read_markers.exit.i*/
/* store i32 %386, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_336)
begin
memory_controller_address = `TAG_g_p_jinfo_dc_dhuff_tbl_ml_a + 4 * 32'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %387, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_340)
begin
memory_controller_address = `TAG_g_p_jinfo_ac_dhuff_tbl_ml_a;
end
/* main: %read_markers.exit.i*/
/* store i32 %388, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_344)
begin
memory_controller_address = `TAG_g_p_jinfo_ac_dhuff_tbl_ml_a + 4 * 32'd1;
end
/* main: %read_markers.exit.i*/
/* store i8* %p_jinfo_jpeg_data.0, i8** @CurHuffReadBuf, align 4, !tbaa !4*/
if (cur_state == LEGUP_F_main_BB90_345)
begin
memory_controller_address = `TAG_g_CurHuffReadBuf_a;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_346)
begin
memory_controller_address = main_read_markers_exit_i_scevgep148_i_i_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.1.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_347)
begin
memory_controller_address = main_read_markers_exit_i_scevgep148_1_i_i_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.2.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_348)
begin
memory_controller_address = main_read_markers_exit_i_scevgep148_2_i_i_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_349)
begin
memory_controller_address = `TAG_g_OutData_comp_vpos_a;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_350)
begin
memory_controller_address = `TAG_g_OutData_comp_hpos_a;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_351)
begin
memory_controller_address = `TAG_g_OutData_comp_vpos_a + 4 * 32'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_352)
begin
memory_controller_address = `TAG_g_OutData_comp_hpos_a + 4 * 32'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_353)
begin
memory_controller_address = `TAG_g_OutData_comp_vpos_a + 4 * 32'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_354)
begin
memory_controller_address = `TAG_g_OutData_comp_hpos_a + 4 * 32'd2;
end
/* main: %392*/
/* %393 = load i32* %scevgep.i.i3.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
memory_controller_address = main_392_scevgep_i_i3_i;
end
/* main: %392*/
/* %394 = load i32* %scevgep2.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_367)
begin
memory_controller_address = main_392_scevgep2_i_i_i_reg;
end
/* main: %392*/
/* %396 = load i32* %scevgep3.i.i2.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_368)
begin
memory_controller_address = main_392_scevgep3_i_i2_i_reg;
end
/* main: %425*/
/* store i32 %r.0.i.i.i, i32* %scevgep4.i.i6.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
memory_controller_address = main_392_scevgep4_i_i6_i_reg;
end
/* main: %425*/
/* store i32 %g.0.i.i.i, i32* %scevgep5.i.i5.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_381)
begin
memory_controller_address = main_392_scevgep5_i_i5_i_reg;
end
/* main: %425*/
/* store i32 %b.0.i.i.i, i32* %scevgep6.i.i4.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_382)
begin
memory_controller_address = main_392_scevgep6_i_i4_i_reg;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %427 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_383)
begin
memory_controller_address = `TAG_g_p_jinfo_image_width_a;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %429 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_384)
begin
memory_controller_address = `TAG_g_p_jinfo_image_height_a;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
memory_controller_address = `TAG_g_OutData_comp_hpos_a;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_386)
begin
memory_controller_address = `TAG_g_p_jinfo_MCUWidth_a;
end
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
memory_controller_address = main_432_scevgep139_i_i;
end
/* main: %440*/
/* %441 = load i32* %.14.us.i.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
memory_controller_address = main_440__14_us_i_i_i_i;
end
/* main: %440*/
/* store i8 %442, i8* %scevgep24.i.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB108_398)
begin
memory_controller_address = main_440_scevgep24_i_i_i_i_reg;
end
/* main: %WriteOneBlock.exit.i.i.i*/
/* %443 = load i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB110_400)
begin
memory_controller_address = main_432_scevgep142_i_i_reg;
end
/* main: %445*/
/* store i32 0, i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB111_403)
begin
memory_controller_address = main_432_scevgep142_i_i_reg;
end
/* main: %454*/
/* %455 = load i32* %scevgep.i3.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
memory_controller_address = main_454_scevgep_i3_i_i;
end
/* main: %454*/
/* %456 = load i32* %scevgep2.i4.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_428)
begin
memory_controller_address = main_454_scevgep2_i4_i_i_reg;
end
/* main: %454*/
/* %458 = load i32* %scevgep3.i5.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_429)
begin
memory_controller_address = main_454_scevgep3_i5_i_i_reg;
end
/* main: %487*/
/* store i32 %r.0.i9.i.i, i32* %scevgep4.i6.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
memory_controller_address = main_454_scevgep4_i6_i_i_reg;
end
/* main: %487*/
/* store i32 %g.0.i10.i.i, i32* %scevgep5.i7.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_442)
begin
memory_controller_address = main_454_scevgep5_i7_i_i_reg;
end
/* main: %487*/
/* store i32 %b.0.i11.i.i, i32* %scevgep6.i8.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_443)
begin
memory_controller_address = main_454_scevgep6_i8_i_i_reg;
end
/* main: %decode_start.exit.i*/
/* %main_result.promoted3.i = load i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB130_454)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
memory_controller_address = main_491_scevgep_i;
end
/* main: %491*/
/* %494 = load i8* %scevgep7.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_458)
begin
memory_controller_address = main_491_scevgep7_i_reg;
end
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
memory_controller_address = main__preheader_1_i_scevgep_1_i;
end
/* main: %.preheader.1.i*/
/* %501 = load i8* %scevgep7.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_462)
begin
memory_controller_address = main__preheader_1_i_scevgep7_1_i_reg;
end
/* main: %jpeg2bmp_main.exit*/
/* store i32 %.storemerge, i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %jpeg2bmp_main.exit*/
/* %511 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB133_466)
begin
memory_controller_address = `TAG_g_main_result_a;
end
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
memory_controller_address = main__preheader_2_i_scevgep_2_i;
end
/* main: %.preheader.2.i*/
/* %515 = load i8* %scevgep7.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_470)
begin
memory_controller_address = main__preheader_2_i_scevgep7_2_i_reg;
end
/* main: %524*/
/* %525 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB137_475)
begin
memory_controller_address = `TAG_g_main_result_a;
end
end
always @(*) begin
memory_controller_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_enable = 1'd0;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
memory_controller_enable = huff_make_dhuff_tb_memory_controller_enable;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
memory_controller_enable = huff_make_dhuff_tb_memory_controller_enable;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
memory_controller_enable = huff_make_dhuff_tb_memory_controller_enable;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
memory_controller_enable = huff_make_dhuff_tb_memory_controller_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
memory_controller_enable = decode_block_memory_controller_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
memory_controller_enable = Write4Blocks_memory_controller_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
memory_controller_enable = Write4Blocks_memory_controller_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
memory_controller_enable = Write4Blocks_memory_controller_enable;
end
/* main: %0*/
/* store i32 0, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB0_1)
begin
memory_controller_enable = 1'd1;
end
/* main: %1*/
/* %2 = load i8* %scevgep13.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
memory_controller_enable = 1'd1;
end
/* main: %1*/
/* store i8 %2, i8* %c.06.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_4)
begin
memory_controller_enable = 1'd1;
end
/* main: %6*/
/* %8 = load i8* %ReadBuf.1, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_10)
begin
memory_controller_enable = 1'd1;
end
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_11)
begin
memory_controller_enable = 1'd1;
end
/* main: %first_marker.exit.i.i*/
/* %16 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
memory_controller_enable = 1'd1;
end
/* main: %first_marker.exit.i.i*/
/* store i32 %17, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_17)
begin
memory_controller_enable = 1'd1;
end
/* main: %.loopexit3.i.i.i*/
/* %c.0.in2.i.i.i = load i8* %18, align 1*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i.i.i*/
/* %c.0.in.i.i.i = load i8* %scevgep.i.i, align 1*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
memory_controller_enable = 1'd1;
end
/* main: %.loopexit.i.i.i*/
/* %21 = load i8* %scevgep11.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB15_27)
begin
memory_controller_enable = 1'd1;
end
/* main: %next_marker.exit.i.i*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB17_32)
begin
memory_controller_enable = 1'd1;
end
/* main: %28*/
/* %29 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_35)
begin
memory_controller_enable = 1'd1;
end
/* main: %28*/
/* store i32 %30, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_37)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %34 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_40)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_41)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %45 = load i8* %42, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %49 = load i8* %44, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* store i16 %51, i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_45)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %53 = load i8* %48, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_46)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %57 = load i8* %52, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_47)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* store i16 %59, i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_49)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_50)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %65 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
memory_controller_enable = 1'd1;
end
/* main: %32*/
/* %68 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_55)
begin
memory_controller_enable = 1'd1;
end
/* main: %74*/
/* %75 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_58)
begin
memory_controller_enable = 1'd1;
end
/* main: %74*/
/* store i32 %76, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_60)
begin
memory_controller_enable = 1'd1;
end
/* main: %79*/
/* %80 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_62)
begin
memory_controller_enable = 1'd1;
end
/* main: %79*/
/* store i32 %81, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_64)
begin
memory_controller_enable = 1'd1;
end
/* main: %82*/
/* %83 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB24_65)
begin
memory_controller_enable = 1'd1;
end
/* main: %85*/
/* %86 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_68)
begin
memory_controller_enable = 1'd1;
end
/* main: %85*/
/* store i32 %87, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_70)
begin
memory_controller_enable = 1'd1;
end
/* main: %88*/
/* %89 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB26_71)
begin
memory_controller_enable = 1'd1;
end
/* main: %91*/
/* %92 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_74)
begin
memory_controller_enable = 1'd1;
end
/* main: %91*/
/* store i32 %93, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_76)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.i.i.i.thread*/
/* %96 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_78)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.i.i.i.thread*/
/* store i32 %97, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_80)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %tmp.i.i.i, i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %100 = load i8* %ReadBuf.3, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_83)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %100, i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_85)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %102 = load i8* %99, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_86)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %103, i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %104, i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_89)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %106 = load i8* %101, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_90)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %106, i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %109 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_93)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %112 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_96)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %115 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_99)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %118 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_102)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %121 = load i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_105)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %123 = load i32* %scevgep7.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB31_106)
begin
memory_controller_enable = 1'd1;
end
/* main: %125*/
/* %126 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_109)
begin
memory_controller_enable = 1'd1;
end
/* main: %125*/
/* store i32 %127, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_111)
begin
memory_controller_enable = 1'd1;
end
/* main: %128*/
/* %129 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB33_112)
begin
memory_controller_enable = 1'd1;
end
/* main: %128*/
/* %131 = load i32* %scevgep8.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB33_113)
begin
memory_controller_enable = 1'd1;
end
/* main: %133*/
/* %134 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_116)
begin
memory_controller_enable = 1'd1;
end
/* main: %133*/
/* store i32 %135, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_118)
begin
memory_controller_enable = 1'd1;
end
/* main: %136*/
/* %137 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB35_119)
begin
memory_controller_enable = 1'd1;
end
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB35_120)
begin
memory_controller_enable = 1'd1;
end
/* main: %141*/
/* %142 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_123)
begin
memory_controller_enable = 1'd1;
end
/* main: %141*/
/* store i32 %143, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_125)
begin
memory_controller_enable = 1'd1;
end
/* main: %144*/
/* %145 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB37_126)
begin
memory_controller_enable = 1'd1;
end
/* main: %148*/
/* %149 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_129)
begin
memory_controller_enable = 1'd1;
end
/* main: %148*/
/* store i32 %150, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_131)
begin
memory_controller_enable = 1'd1;
end
/* main: %151*/
/* %152 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB39_132)
begin
memory_controller_enable = 1'd1;
end
/* main: %151*/
/* %154 = load i32* %scevgep11.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB39_133)
begin
memory_controller_enable = 1'd1;
end
/* main: %156*/
/* %157 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_136)
begin
memory_controller_enable = 1'd1;
end
/* main: %156*/
/* store i32 %158, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_138)
begin
memory_controller_enable = 1'd1;
end
/* main: %._crit_edge.i.i.i*/
/* %161 = load i8* getelementptr inbounds ([3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 0), align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
memory_controller_enable = 1'd1;
end
/* main: %167*/
/* %169 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
memory_controller_enable = 1'd1;
end
/* main: %167*/
/* %173 = load i8* %168, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_146)
begin
memory_controller_enable = 1'd1;
end
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_147)
begin
memory_controller_enable = 1'd1;
end
/* main: %183*/
/* %184 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_150)
begin
memory_controller_enable = 1'd1;
end
/* main: %183*/
/* store i32 %185, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_152)
begin
memory_controller_enable = 1'd1;
end
/* main: %188*/
/* %189 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_154)
begin
memory_controller_enable = 1'd1;
end
/* main: %188*/
/* store i32 %190, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_156)
begin
memory_controller_enable = 1'd1;
end
/* main: %194*/
/* %196 = load i8* %ReadBuf.5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
memory_controller_enable = 1'd1;
end
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_160)
begin
memory_controller_enable = 1'd1;
end
/* main: %203*/
/* %204 = load i8* %scevgep9.i4.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB53_164)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* %212 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* store i32 %213, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_171)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* store i8 %214, i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_172)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* store i8 %215, i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* %217 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_174)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* %220 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_177)
begin
memory_controller_enable = 1'd1;
end
/* main: %211*/
/* %224 = load i32* %223, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_180)
begin
memory_controller_enable = 1'd1;
end
/* main: %226*/
/* %227 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_183)
begin
memory_controller_enable = 1'd1;
end
/* main: %226*/
/* store i32 %228, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_185)
begin
memory_controller_enable = 1'd1;
end
/* main: %229*/
/* %230 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB58_186)
begin
memory_controller_enable = 1'd1;
end
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB58_187)
begin
memory_controller_enable = 1'd1;
end
/* main: %235*/
/* %236 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_190)
begin
memory_controller_enable = 1'd1;
end
/* main: %235*/
/* store i32 %237, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_192)
begin
memory_controller_enable = 1'd1;
end
/* main: %238*/
/* %239 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB60_193)
begin
memory_controller_enable = 1'd1;
end
/* main: %242*/
/* %243 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_196)
begin
memory_controller_enable = 1'd1;
end
/* main: %242*/
/* store i32 %244, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_198)
begin
memory_controller_enable = 1'd1;
end
/* main: %248*/
/* %250 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
memory_controller_enable = 1'd1;
end
/* main: %248*/
/* %254 = load i8* %249, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_202)
begin
memory_controller_enable = 1'd1;
end
/* main: %248*/
/* %260 = load i32* %4, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB64_205)
begin
memory_controller_enable = 1'd1;
end
/* main: %262*/
/* %263 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_208)
begin
memory_controller_enable = 1'd1;
end
/* main: %262*/
/* store i32 %264, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_210)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph5.i.i.i*/
/* %267 = load i8* %ReadBuf.6, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph5.i.i.i*/
/* %271 = load i32* %270, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB67_215)
begin
memory_controller_enable = 1'd1;
end
/* main: %273*/
/* %274 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_218)
begin
memory_controller_enable = 1'd1;
end
/* main: %273*/
/* store i32 %275, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_220)
begin
memory_controller_enable = 1'd1;
end
/* main: %287*/
/* %290 = load i8* %288, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
memory_controller_enable = 1'd1;
end
/* main: %287*/
/* store i32 %291, i32* %scevgep.i9.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
memory_controller_enable = 1'd1;
end
/* main: %293*/
/* %296 = load i32* %295, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB74_229)
begin
memory_controller_enable = 1'd1;
end
/* main: %298*/
/* %299 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_232)
begin
memory_controller_enable = 1'd1;
end
/* main: %298*/
/* store i32 %300, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_234)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i10.i.i*/
/* %306 = load i8* %304, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i10.i.i*/
/* store i32 %307, i32* %scevgep8.i11.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB77_238)
begin
memory_controller_enable = 1'd1;
end
/* main: %312*/
/* %314 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
memory_controller_enable = 1'd1;
end
/* main: %312*/
/* %318 = load i8* %313, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_241)
begin
memory_controller_enable = 1'd1;
end
/* main: %312*/
/* %324 = load i32* %5, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB79_244)
begin
memory_controller_enable = 1'd1;
end
/* main: %326*/
/* %327 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_247)
begin
memory_controller_enable = 1'd1;
end
/* main: %326*/
/* store i32 %328, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_249)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i15.i.i*/
/* %332 = load i8* %330, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
memory_controller_enable = 1'd1;
end
/* main: %.lr.ph.i15.i.i*/
/* %339 = load i32* %338, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB82_254)
begin
memory_controller_enable = 1'd1;
end
/* main: %341*/
/* %342 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_257)
begin
memory_controller_enable = 1'd1;
end
/* main: %341*/
/* store i32 %343, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_259)
begin
memory_controller_enable = 1'd1;
end
/* main: %344*/
/* %346 = load i32* %345, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB84_260)
begin
memory_controller_enable = 1'd1;
end
/* main: %348*/
/* %349 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_263)
begin
memory_controller_enable = 1'd1;
end
/* main: %348*/
/* store i32 %350, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_265)
begin
memory_controller_enable = 1'd1;
end
/* main: %.split.us.i.i.i*/
/* %356 = load i8* %354, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
memory_controller_enable = 1'd1;
end
/* main: %.split.us.i.i.i*/
/* %358 = load i32* %scevgep.i16.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_268)
begin
memory_controller_enable = 1'd1;
end
/* main: %.split.us.i.i.i*/
/* store i32 %357, i32* %359, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_270)
begin
memory_controller_enable = 1'd1;
end
/* main: %..split_crit_edge.i.i.i*/
/* %363 = load i8* %361, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
memory_controller_enable = 1'd1;
end
/* main: %..split_crit_edge.i.i.i*/
/* %367 = load i8* %362, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_272)
begin
memory_controller_enable = 1'd1;
end
/* main: %..split_crit_edge.i.i.i*/
/* %370 = load i32* %scevgep4.i18.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_273)
begin
memory_controller_enable = 1'd1;
end
/* main: %..split_crit_edge.i.i.i*/
/* store i32 %369, i32* %371, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_275)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_278)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %383, i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %385, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_332)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %386, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_336)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %387, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_340)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %388, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_344)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i8* %p_jinfo_jpeg_data.0, i8** @CurHuffReadBuf, align 4, !tbaa !4*/
if (cur_state == LEGUP_F_main_BB90_345)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_346)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.1.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_347)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.2.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_348)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_349)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_350)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_351)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_352)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_353)
begin
memory_controller_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_354)
begin
memory_controller_enable = 1'd1;
end
/* main: %392*/
/* %393 = load i32* %scevgep.i.i3.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
memory_controller_enable = 1'd1;
end
/* main: %392*/
/* %394 = load i32* %scevgep2.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_367)
begin
memory_controller_enable = 1'd1;
end
/* main: %392*/
/* %396 = load i32* %scevgep3.i.i2.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_368)
begin
memory_controller_enable = 1'd1;
end
/* main: %425*/
/* store i32 %r.0.i.i.i, i32* %scevgep4.i.i6.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
memory_controller_enable = 1'd1;
end
/* main: %425*/
/* store i32 %g.0.i.i.i, i32* %scevgep5.i.i5.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_381)
begin
memory_controller_enable = 1'd1;
end
/* main: %425*/
/* store i32 %b.0.i.i.i, i32* %scevgep6.i.i4.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_382)
begin
memory_controller_enable = 1'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %427 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_383)
begin
memory_controller_enable = 1'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %429 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_384)
begin
memory_controller_enable = 1'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
memory_controller_enable = 1'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_386)
begin
memory_controller_enable = 1'd1;
end
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
memory_controller_enable = 1'd1;
end
/* main: %440*/
/* %441 = load i32* %.14.us.i.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
memory_controller_enable = 1'd1;
end
/* main: %440*/
/* store i8 %442, i8* %scevgep24.i.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB108_398)
begin
memory_controller_enable = 1'd1;
end
/* main: %WriteOneBlock.exit.i.i.i*/
/* %443 = load i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB110_400)
begin
memory_controller_enable = 1'd1;
end
/* main: %445*/
/* store i32 0, i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB111_403)
begin
memory_controller_enable = 1'd1;
end
/* main: %454*/
/* %455 = load i32* %scevgep.i3.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
memory_controller_enable = 1'd1;
end
/* main: %454*/
/* %456 = load i32* %scevgep2.i4.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_428)
begin
memory_controller_enable = 1'd1;
end
/* main: %454*/
/* %458 = load i32* %scevgep3.i5.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_429)
begin
memory_controller_enable = 1'd1;
end
/* main: %487*/
/* store i32 %r.0.i9.i.i, i32* %scevgep4.i6.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
memory_controller_enable = 1'd1;
end
/* main: %487*/
/* store i32 %g.0.i10.i.i, i32* %scevgep5.i7.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_442)
begin
memory_controller_enable = 1'd1;
end
/* main: %487*/
/* store i32 %b.0.i11.i.i, i32* %scevgep6.i8.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_443)
begin
memory_controller_enable = 1'd1;
end
/* main: %decode_start.exit.i*/
/* %main_result.promoted3.i = load i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB130_454)
begin
memory_controller_enable = 1'd1;
end
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
memory_controller_enable = 1'd1;
end
/* main: %491*/
/* %494 = load i8* %scevgep7.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_458)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.1.i*/
/* %501 = load i8* %scevgep7.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_462)
begin
memory_controller_enable = 1'd1;
end
/* main: %jpeg2bmp_main.exit*/
/* store i32 %.storemerge, i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
memory_controller_enable = 1'd1;
end
/* main: %jpeg2bmp_main.exit*/
/* %511 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB133_466)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
memory_controller_enable = 1'd1;
end
/* main: %.preheader.2.i*/
/* %515 = load i8* %scevgep7.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_470)
begin
memory_controller_enable = 1'd1;
end
/* main: %524*/
/* %525 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB137_475)
begin
memory_controller_enable = 1'd1;
end
end
always @(*) begin
memory_controller_write_enable = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
memory_controller_write_enable = huff_make_dhuff_tb_memory_controller_write_enable;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
memory_controller_write_enable = huff_make_dhuff_tb_memory_controller_write_enable;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
memory_controller_write_enable = huff_make_dhuff_tb_memory_controller_write_enable;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
memory_controller_write_enable = huff_make_dhuff_tb_memory_controller_write_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
memory_controller_write_enable = decode_block_memory_controller_write_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
memory_controller_write_enable = Write4Blocks_memory_controller_write_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
memory_controller_write_enable = Write4Blocks_memory_controller_write_enable;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
memory_controller_write_enable = Write4Blocks_memory_controller_write_enable;
end
/* main: %0*/
/* store i32 0, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB0_1)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %1*/
/* %2 = load i8* %scevgep13.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %1*/
/* store i8 %2, i8* %c.06.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_4)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %6*/
/* %8 = load i8* %ReadBuf.1, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_10)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_11)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %first_marker.exit.i.i*/
/* %16 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %first_marker.exit.i.i*/
/* store i32 %17, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_17)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.loopexit3.i.i.i*/
/* %c.0.in2.i.i.i = load i8* %18, align 1*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i.i.i*/
/* %c.0.in.i.i.i = load i8* %scevgep.i.i, align 1*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.loopexit.i.i.i*/
/* %21 = load i8* %scevgep11.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB15_27)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %next_marker.exit.i.i*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB17_32)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %28*/
/* %29 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_35)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %28*/
/* store i32 %30, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_37)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %32*/
/* %34 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_40)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_41)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %45 = load i8* %42, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %49 = load i8* %44, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* store i16 %51, i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_45)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %32*/
/* %53 = load i8* %48, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_46)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %57 = load i8* %52, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_47)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* store i16 %59, i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_49)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_50)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %65 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %32*/
/* %68 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_55)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %74*/
/* %75 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_58)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %74*/
/* store i32 %76, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_60)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %79*/
/* %80 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_62)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %79*/
/* store i32 %81, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_64)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %82*/
/* %83 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB24_65)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %85*/
/* %86 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_68)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %85*/
/* store i32 %87, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_70)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %88*/
/* %89 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB26_71)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %91*/
/* %92 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_74)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %91*/
/* store i32 %93, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_76)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.preheader.i.i.i.thread*/
/* %96 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_78)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.preheader.i.i.i.thread*/
/* store i32 %97, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_80)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %tmp.i.i.i, i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %100 = load i8* %ReadBuf.3, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_83)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %100, i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_85)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %102 = load i8* %99, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_86)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %103, i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %104, i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_89)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %106 = load i8* %101, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_90)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %106, i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i1.i.i*/
/* %109 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_93)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %112 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_96)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %115 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_99)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %118 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_102)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %121 = load i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_105)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %123 = load i32* %scevgep7.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB31_106)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %125*/
/* %126 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_109)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %125*/
/* store i32 %127, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_111)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %128*/
/* %129 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB33_112)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %128*/
/* %131 = load i32* %scevgep8.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB33_113)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %133*/
/* %134 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_116)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %133*/
/* store i32 %135, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_118)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %136*/
/* %137 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB35_119)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB35_120)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %141*/
/* %142 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_123)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %141*/
/* store i32 %143, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_125)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %144*/
/* %145 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB37_126)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %148*/
/* %149 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_129)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %148*/
/* store i32 %150, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_131)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %151*/
/* %152 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB39_132)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %151*/
/* %154 = load i32* %scevgep11.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB39_133)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %156*/
/* %157 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_136)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %156*/
/* store i32 %158, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_138)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %._crit_edge.i.i.i*/
/* %161 = load i8* getelementptr inbounds ([3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 0), align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %167*/
/* %169 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %167*/
/* %173 = load i8* %168, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_146)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_147)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %183*/
/* %184 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_150)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %183*/
/* store i32 %185, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_152)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %188*/
/* %189 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_154)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %188*/
/* store i32 %190, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_156)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %194*/
/* %196 = load i8* %ReadBuf.5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_160)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %203*/
/* %204 = load i8* %scevgep9.i4.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB53_164)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %211*/
/* %212 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %211*/
/* store i32 %213, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_171)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %211*/
/* store i8 %214, i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_172)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %211*/
/* store i8 %215, i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %211*/
/* %217 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_174)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %211*/
/* %220 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_177)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %211*/
/* %224 = load i32* %223, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_180)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %226*/
/* %227 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_183)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %226*/
/* store i32 %228, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_185)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %229*/
/* %230 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB58_186)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB58_187)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %235*/
/* %236 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_190)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %235*/
/* store i32 %237, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_192)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %238*/
/* %239 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB60_193)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %242*/
/* %243 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_196)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %242*/
/* store i32 %244, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_198)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %248*/
/* %250 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %248*/
/* %254 = load i8* %249, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_202)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %248*/
/* %260 = load i32* %4, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB64_205)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %262*/
/* %263 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_208)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %262*/
/* store i32 %264, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_210)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph5.i.i.i*/
/* %267 = load i8* %ReadBuf.6, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph5.i.i.i*/
/* %271 = load i32* %270, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB67_215)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %273*/
/* %274 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_218)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %273*/
/* store i32 %275, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_220)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %287*/
/* %290 = load i8* %288, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %287*/
/* store i32 %291, i32* %scevgep.i9.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %293*/
/* %296 = load i32* %295, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB74_229)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %298*/
/* %299 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_232)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %298*/
/* store i32 %300, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_234)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i10.i.i*/
/* %306 = load i8* %304, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i10.i.i*/
/* store i32 %307, i32* %scevgep8.i11.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB77_238)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %312*/
/* %314 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %312*/
/* %318 = load i8* %313, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_241)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %312*/
/* %324 = load i32* %5, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB79_244)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %326*/
/* %327 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_247)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %326*/
/* store i32 %328, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_249)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.lr.ph.i15.i.i*/
/* %332 = load i8* %330, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.lr.ph.i15.i.i*/
/* %339 = load i32* %338, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB82_254)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %341*/
/* %342 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_257)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %341*/
/* store i32 %343, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_259)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %344*/
/* %346 = load i32* %345, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB84_260)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %348*/
/* %349 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_263)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %348*/
/* store i32 %350, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_265)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %.split.us.i.i.i*/
/* %356 = load i8* %354, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.split.us.i.i.i*/
/* %358 = load i32* %scevgep.i16.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_268)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.split.us.i.i.i*/
/* store i32 %357, i32* %359, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_270)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %..split_crit_edge.i.i.i*/
/* %363 = load i8* %361, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %..split_crit_edge.i.i.i*/
/* %367 = load i8* %362, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_272)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %..split_crit_edge.i.i.i*/
/* %370 = load i32* %scevgep4.i18.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_273)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %..split_crit_edge.i.i.i*/
/* store i32 %369, i32* %371, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_275)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_278)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 %383, i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %385, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_332)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %386, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_336)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %387, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_340)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %388, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_344)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i8* %p_jinfo_jpeg_data.0, i8** @CurHuffReadBuf, align 4, !tbaa !4*/
if (cur_state == LEGUP_F_main_BB90_345)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_346)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.1.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_347)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.2.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_348)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_349)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_350)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_351)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_352)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_353)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_354)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %392*/
/* %393 = load i32* %scevgep.i.i3.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %392*/
/* %394 = load i32* %scevgep2.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_367)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %392*/
/* %396 = load i32* %scevgep3.i.i2.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_368)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %425*/
/* store i32 %r.0.i.i.i, i32* %scevgep4.i.i6.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %425*/
/* store i32 %g.0.i.i.i, i32* %scevgep5.i.i5.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_381)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %425*/
/* store i32 %b.0.i.i.i, i32* %scevgep6.i.i4.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_382)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %427 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_383)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %429 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_384)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_386)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %440*/
/* %441 = load i32* %.14.us.i.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %440*/
/* store i8 %442, i8* %scevgep24.i.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB108_398)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %WriteOneBlock.exit.i.i.i*/
/* %443 = load i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB110_400)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %445*/
/* store i32 0, i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB111_403)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %454*/
/* %455 = load i32* %scevgep.i3.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %454*/
/* %456 = load i32* %scevgep2.i4.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_428)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %454*/
/* %458 = load i32* %scevgep3.i5.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_429)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %487*/
/* store i32 %r.0.i9.i.i, i32* %scevgep4.i6.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %487*/
/* store i32 %g.0.i10.i.i, i32* %scevgep5.i7.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_442)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %487*/
/* store i32 %b.0.i11.i.i, i32* %scevgep6.i8.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_443)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %decode_start.exit.i*/
/* %main_result.promoted3.i = load i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB130_454)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %491*/
/* %494 = load i8* %scevgep7.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_458)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.preheader.1.i*/
/* %501 = load i8* %scevgep7.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_462)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %jpeg2bmp_main.exit*/
/* store i32 %.storemerge, i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
memory_controller_write_enable = 1'd1;
end
/* main: %jpeg2bmp_main.exit*/
/* %511 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB133_466)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %.preheader.2.i*/
/* %515 = load i8* %scevgep7.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_470)
begin
memory_controller_write_enable = 1'd0;
end
/* main: %524*/
/* %525 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB137_475)
begin
memory_controller_write_enable = 1'd0;
end
end
always @(*) begin
memory_controller_in = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_in = 64'd0;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
memory_controller_in = huff_make_dhuff_tb_memory_controller_in;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
memory_controller_in = huff_make_dhuff_tb_memory_controller_in;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
memory_controller_in = huff_make_dhuff_tb_memory_controller_in;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
memory_controller_in = huff_make_dhuff_tb_memory_controller_in;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
memory_controller_in = decode_block_memory_controller_in;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
memory_controller_in = Write4Blocks_memory_controller_in;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
memory_controller_in = Write4Blocks_memory_controller_in;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
memory_controller_in = Write4Blocks_memory_controller_in;
end
/* main: %0*/
/* store i32 0, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB0_1)
begin
memory_controller_in = 32'd0;
end
/* main: %1*/
/* store i8 %2, i8* %c.06.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_4)
begin
memory_controller_in = main_1_2;
end
/* main: %first_marker.exit.i.i*/
/* store i32 %17, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_17)
begin
memory_controller_in = main_first_marker_exit_i_i_17;
end
/* main: %28*/
/* store i32 %30, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_37)
begin
memory_controller_in = main_28_30;
end
/* main: %32*/
/* store i16 %51, i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_45)
begin
memory_controller_in = main_32_51;
end
/* main: %32*/
/* store i16 %59, i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_49)
begin
memory_controller_in = main_32_59;
end
/* main: %74*/
/* store i32 %76, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_60)
begin
memory_controller_in = main_74_76;
end
/* main: %79*/
/* store i32 %81, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_64)
begin
memory_controller_in = main_79_81;
end
/* main: %85*/
/* store i32 %87, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_70)
begin
memory_controller_in = main_85_87;
end
/* main: %91*/
/* store i32 %93, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_76)
begin
memory_controller_in = main_91_93;
end
/* main: %.preheader.i.i.i.thread*/
/* store i32 %97, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_80)
begin
memory_controller_in = main__preheader_i_i_i_thread_97;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %tmp.i.i.i, i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
memory_controller_in = main__lr_ph_i1_i_i_tmp_i_i_i;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %100, i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_85)
begin
memory_controller_in = main__lr_ph_i1_i_i_100;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %103, i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
memory_controller_in = main__lr_ph_i1_i_i_103;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %104, i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_89)
begin
memory_controller_in = main__lr_ph_i1_i_i_104_reg;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %106, i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
memory_controller_in = main__lr_ph_i1_i_i_106;
end
/* main: %125*/
/* store i32 %127, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_111)
begin
memory_controller_in = main_125_127;
end
/* main: %133*/
/* store i32 %135, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_118)
begin
memory_controller_in = main_133_135;
end
/* main: %141*/
/* store i32 %143, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_125)
begin
memory_controller_in = main_141_143;
end
/* main: %148*/
/* store i32 %150, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_131)
begin
memory_controller_in = main_148_150;
end
/* main: %156*/
/* store i32 %158, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_138)
begin
memory_controller_in = main_156_158;
end
/* main: %183*/
/* store i32 %185, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_152)
begin
memory_controller_in = main_183_185;
end
/* main: %188*/
/* store i32 %190, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_156)
begin
memory_controller_in = main_188_190;
end
/* main: %211*/
/* store i32 %213, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_171)
begin
memory_controller_in = main_211_213;
end
/* main: %211*/
/* store i8 %214, i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_172)
begin
memory_controller_in = main_211_214_reg;
end
/* main: %211*/
/* store i8 %215, i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
memory_controller_in = main_211_215_reg;
end
/* main: %226*/
/* store i32 %228, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_185)
begin
memory_controller_in = main_226_228;
end
/* main: %235*/
/* store i32 %237, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_192)
begin
memory_controller_in = main_235_237;
end
/* main: %242*/
/* store i32 %244, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_198)
begin
memory_controller_in = main_242_244;
end
/* main: %262*/
/* store i32 %264, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_210)
begin
memory_controller_in = main_262_264;
end
/* main: %273*/
/* store i32 %275, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_220)
begin
memory_controller_in = main_273_275;
end
/* main: %287*/
/* store i32 %291, i32* %scevgep.i9.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
memory_controller_in = main_287_291;
end
/* main: %298*/
/* store i32 %300, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_234)
begin
memory_controller_in = main_298_300;
end
/* main: %.lr.ph.i10.i.i*/
/* store i32 %307, i32* %scevgep8.i11.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB77_238)
begin
memory_controller_in = main__lr_ph_i10_i_i_307;
end
/* main: %326*/
/* store i32 %328, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_249)
begin
memory_controller_in = main_326_328;
end
/* main: %341*/
/* store i32 %343, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_259)
begin
memory_controller_in = main_341_343;
end
/* main: %348*/
/* store i32 %350, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_265)
begin
memory_controller_in = main_348_350;
end
/* main: %.split.us.i.i.i*/
/* store i32 %357, i32* %359, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_270)
begin
memory_controller_in = main__split_us_i_i_i_357_reg;
end
/* main: %..split_crit_edge.i.i.i*/
/* store i32 %369, i32* %371, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_275)
begin
memory_controller_in = main___split_crit_edge_i_i_i_369_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 %383, i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
memory_controller_in = main_read_markers_exit_i_383;
end
/* main: %read_markers.exit.i*/
/* store i32 %385, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_332)
begin
memory_controller_in = main_read_markers_exit_i_385_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 %386, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_336)
begin
memory_controller_in = main_read_markers_exit_i_386_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 %387, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_340)
begin
memory_controller_in = main_read_markers_exit_i_387_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 %388, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_344)
begin
memory_controller_in = main_read_markers_exit_i_388_reg;
end
/* main: %read_markers.exit.i*/
/* store i8* %p_jinfo_jpeg_data.0, i8** @CurHuffReadBuf, align 4, !tbaa !4*/
if (cur_state == LEGUP_F_main_BB90_345)
begin
memory_controller_in = main_read_markers_exit_i_p_jinfo_jpeg_data_0_reg;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_346)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.1.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_347)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.2.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_348)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_349)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_350)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_351)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_352)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_353)
begin
memory_controller_in = 32'd0;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_354)
begin
memory_controller_in = 32'd0;
end
/* main: %425*/
/* store i32 %r.0.i.i.i, i32* %scevgep4.i.i6.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
memory_controller_in = main_415_r_0_i_i_i_reg;
end
/* main: %425*/
/* store i32 %g.0.i.i.i, i32* %scevgep5.i.i5.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_381)
begin
memory_controller_in = main_420_g_0_i_i_i_reg;
end
/* main: %425*/
/* store i32 %b.0.i.i.i, i32* %scevgep6.i.i4.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_382)
begin
memory_controller_in = main_425_b_0_i_i_i_reg;
end
/* main: %440*/
/* store i8 %442, i8* %scevgep24.i.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB108_398)
begin
memory_controller_in = main_440_442;
end
/* main: %445*/
/* store i32 0, i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB111_403)
begin
memory_controller_in = 32'd0;
end
/* main: %487*/
/* store i32 %r.0.i9.i.i, i32* %scevgep4.i6.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
memory_controller_in = main_477_r_0_i9_i_i_reg;
end
/* main: %487*/
/* store i32 %g.0.i10.i.i, i32* %scevgep5.i7.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_442)
begin
memory_controller_in = main_482_g_0_i10_i_i_reg;
end
/* main: %487*/
/* store i32 %b.0.i11.i.i, i32* %scevgep6.i8.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_443)
begin
memory_controller_in = main_487_b_0_i11_i_i_reg;
end
/* main: %jpeg2bmp_main.exit*/
/* store i32 %.storemerge, i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
memory_controller_in = main_jpeg2bmp_main_exit__storemerge;
end
end
always @(*) begin
memory_controller_size = 1'd0;
if (cur_state == LEGUP_0)
begin
memory_controller_size = 2'd0;
end
/* main: %read_markers.exit.i*/
/* %385 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_330)
begin
memory_controller_size = huff_make_dhuff_tb_memory_controller_size;
end
/* main: %read_markers.exit.i*/
/* %386 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_dc_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_334)
begin
memory_controller_size = huff_make_dhuff_tb_memory_controller_size;
end
/* main: %read_markers.exit.i*/
/* %387 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_338)
begin
memory_controller_size = huff_make_dhuff_tb_memory_controller_size;
end
/* main: %read_markers.exit.i*/
/* %388 = tail call fastcc i32 @huff_make_dhuff_tb(i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_xhuff_tbl_bits, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_maxcode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_mincode, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([2 x [36 x i32]]* @p_jinfo_ac_dhuff_tbl_valptr, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_342)
begin
memory_controller_size = huff_make_dhuff_tb_memory_controller_size;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep51.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_358)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %scevgep51.1.i.i, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_361)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader21.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %scevgep51.2.i.i, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_364)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.i8.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_409)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.1.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_412)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.2.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_415)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 0, i32* %scevgep.3.i.i, i32* %scevgep148.i.i) nounwind*/
if (cur_state == LEGUP_function_call_418)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 1, i32* %452, i32* %scevgep148.1.i.i) nounwind*/
if (cur_state == LEGUP_function_call_421)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.preheader.i.i*/
/* call fastcc void @decode_block(i32 2, i32* %453, i32* %scevgep148.2.i.i) nounwind*/
if (cur_state == LEGUP_function_call_424)
begin
memory_controller_size = decode_block_memory_controller_size;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 0, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 0, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_446)
begin
memory_controller_size = Write4Blocks_memory_controller_size;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 1, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 1, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 1, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_449)
begin
memory_controller_size = Write4Blocks_memory_controller_size;
end
/* main: %.loopexit.i.i*/
/* call fastcc void @Write4Blocks(i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 0, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 1, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 2, i32 2, i32 0), i32* getelementptr inbounds ([4 x [3 x [64 x i32]]]* @rgb_buf, i32 0, i32 3, i32 2, i32 0), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), i8* getelementptr inbounds ([3 x [5310 x i8]]* @OutData_comp_buf, i32 0, i32 2, i32 0)) nounwind*/
if (cur_state == LEGUP_function_call_452)
begin
memory_controller_size = Write4Blocks_memory_controller_size;
end
/* main: %0*/
/* store i32 0, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB0_1)
begin
memory_controller_size = 2'd2;
end
/* main: %1*/
/* %2 = load i8* %scevgep13.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_2)
begin
memory_controller_size = 2'd0;
end
/* main: %1*/
/* store i8 %2, i8* %c.06.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB1_4)
begin
memory_controller_size = 2'd0;
end
/* main: %6*/
/* %8 = load i8* %ReadBuf.1, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_10)
begin
memory_controller_size = 2'd0;
end
/* main: %6*/
/* %9 = load i8* %7, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB7_11)
begin
memory_controller_size = 2'd0;
end
/* main: %first_marker.exit.i.i*/
/* %16 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_15)
begin
memory_controller_size = 2'd2;
end
/* main: %first_marker.exit.i.i*/
/* store i32 %17, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB9_17)
begin
memory_controller_size = 2'd2;
end
/* main: %.loopexit3.i.i.i*/
/* %c.0.in2.i.i.i = load i8* %18, align 1*/
if (cur_state == LEGUP_F_main_BB11_19)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i.i.i*/
/* %c.0.in.i.i.i = load i8* %scevgep.i.i, align 1*/
if (cur_state == LEGUP_F_main_BB12_22)
begin
memory_controller_size = 2'd0;
end
/* main: %.loopexit.i.i.i*/
/* %21 = load i8* %scevgep11.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB15_27)
begin
memory_controller_size = 2'd0;
end
/* main: %next_marker.exit.i.i*/
/* %26 = load i32* %25, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB17_32)
begin
memory_controller_size = 2'd2;
end
/* main: %28*/
/* %29 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_35)
begin
memory_controller_size = 2'd2;
end
/* main: %28*/
/* store i32 %30, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB18_37)
begin
memory_controller_size = 2'd2;
end
/* main: %32*/
/* %34 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_39)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %38 = load i8* %33, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_40)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %43 = load i8* %37, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_41)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %45 = load i8* %42, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_42)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %49 = load i8* %44, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_43)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* store i16 %51, i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_45)
begin
memory_controller_size = 2'd1;
end
/* main: %32*/
/* %53 = load i8* %48, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_46)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %57 = load i8* %52, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_47)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* store i16 %59, i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_49)
begin
memory_controller_size = 2'd1;
end
/* main: %32*/
/* %61 = load i8* %56, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB20_50)
begin
memory_controller_size = 2'd0;
end
/* main: %32*/
/* %65 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_52)
begin
memory_controller_size = 2'd1;
end
/* main: %32*/
/* %68 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB20_55)
begin
memory_controller_size = 2'd1;
end
/* main: %74*/
/* %75 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_58)
begin
memory_controller_size = 2'd2;
end
/* main: %74*/
/* store i32 %76, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB21_60)
begin
memory_controller_size = 2'd2;
end
/* main: %79*/
/* %80 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_62)
begin
memory_controller_size = 2'd2;
end
/* main: %79*/
/* store i32 %81, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB23_64)
begin
memory_controller_size = 2'd2;
end
/* main: %82*/
/* %83 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB24_65)
begin
memory_controller_size = 2'd1;
end
/* main: %85*/
/* %86 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_68)
begin
memory_controller_size = 2'd2;
end
/* main: %85*/
/* store i32 %87, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB25_70)
begin
memory_controller_size = 2'd2;
end
/* main: %88*/
/* %89 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB26_71)
begin
memory_controller_size = 2'd1;
end
/* main: %91*/
/* %92 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_74)
begin
memory_controller_size = 2'd2;
end
/* main: %91*/
/* store i32 %93, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB27_76)
begin
memory_controller_size = 2'd2;
end
/* main: %.preheader.i.i.i.thread*/
/* %96 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_78)
begin
memory_controller_size = 2'd2;
end
/* main: %.preheader.i.i.i.thread*/
/* store i32 %97, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB29_80)
begin
memory_controller_size = 2'd2;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %tmp.i.i.i, i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_82)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %100 = load i8* %ReadBuf.3, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_83)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %100, i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_85)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %102 = load i8* %99, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_86)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %103, i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_88)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %104, i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_89)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %106 = load i8* %101, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_90)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* store i8 %106, i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_92)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %109 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_93)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %112 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_96)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %115 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_99)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %118 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_102)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %121 = load i8* %scevgep.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB31_105)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i1.i.i*/
/* %123 = load i32* %scevgep7.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB31_106)
begin
memory_controller_size = 2'd2;
end
/* main: %125*/
/* %126 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_109)
begin
memory_controller_size = 2'd2;
end
/* main: %125*/
/* store i32 %127, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB32_111)
begin
memory_controller_size = 2'd2;
end
/* main: %128*/
/* %129 = load i8* %scevgep3.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB33_112)
begin
memory_controller_size = 2'd0;
end
/* main: %128*/
/* %131 = load i32* %scevgep8.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB33_113)
begin
memory_controller_size = 2'd2;
end
/* main: %133*/
/* %134 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_116)
begin
memory_controller_size = 2'd2;
end
/* main: %133*/
/* store i32 %135, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB34_118)
begin
memory_controller_size = 2'd2;
end
/* main: %136*/
/* %137 = load i8* %scevgep4.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB35_119)
begin
memory_controller_size = 2'd0;
end
/* main: %136*/
/* %139 = load i32* %scevgep9.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB35_120)
begin
memory_controller_size = 2'd2;
end
/* main: %141*/
/* %142 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_123)
begin
memory_controller_size = 2'd2;
end
/* main: %141*/
/* store i32 %143, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB36_125)
begin
memory_controller_size = 2'd2;
end
/* main: %144*/
/* %145 = load i8* %scevgep5.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB37_126)
begin
memory_controller_size = 2'd0;
end
/* main: %148*/
/* %149 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_129)
begin
memory_controller_size = 2'd2;
end
/* main: %148*/
/* store i32 %150, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB38_131)
begin
memory_controller_size = 2'd2;
end
/* main: %151*/
/* %152 = load i8* %scevgep6.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB39_132)
begin
memory_controller_size = 2'd0;
end
/* main: %151*/
/* %154 = load i32* %scevgep11.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB39_133)
begin
memory_controller_size = 2'd2;
end
/* main: %156*/
/* %157 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_136)
begin
memory_controller_size = 2'd2;
end
/* main: %156*/
/* store i32 %158, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB40_138)
begin
memory_controller_size = 2'd2;
end
/* main: %._crit_edge.i.i.i*/
/* %161 = load i8* getelementptr inbounds ([3 x i8]* @p_jinfo_comps_info_h_samp_factor, i32 0, i32 0), align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB42_140)
begin
memory_controller_size = 2'd0;
end
/* main: %167*/
/* %169 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_145)
begin
memory_controller_size = 2'd0;
end
/* main: %167*/
/* %173 = load i8* %168, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_146)
begin
memory_controller_size = 2'd0;
end
/* main: %167*/
/* %178 = load i8* %172, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB45_147)
begin
memory_controller_size = 2'd0;
end
/* main: %183*/
/* %184 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_150)
begin
memory_controller_size = 2'd2;
end
/* main: %183*/
/* store i32 %185, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB46_152)
begin
memory_controller_size = 2'd2;
end
/* main: %188*/
/* %189 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_154)
begin
memory_controller_size = 2'd2;
end
/* main: %188*/
/* store i32 %190, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB48_156)
begin
memory_controller_size = 2'd2;
end
/* main: %194*/
/* %196 = load i8* %ReadBuf.5, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_159)
begin
memory_controller_size = 2'd0;
end
/* main: %194*/
/* %199 = load i8* %195, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB51_160)
begin
memory_controller_size = 2'd0;
end
/* main: %203*/
/* %204 = load i8* %scevgep9.i4.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB53_164)
begin
memory_controller_size = 2'd0;
end
/* main: %211*/
/* %212 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_169)
begin
memory_controller_size = 2'd2;
end
/* main: %211*/
/* store i32 %213, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_171)
begin
memory_controller_size = 2'd2;
end
/* main: %211*/
/* store i8 %214, i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_172)
begin
memory_controller_size = 2'd0;
end
/* main: %211*/
/* store i8 %215, i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_173)
begin
memory_controller_size = 2'd0;
end
/* main: %211*/
/* %217 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_174)
begin
memory_controller_size = 2'd0;
end
/* main: %211*/
/* %220 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB56_177)
begin
memory_controller_size = 2'd0;
end
/* main: %211*/
/* %224 = load i32* %223, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB56_180)
begin
memory_controller_size = 2'd2;
end
/* main: %226*/
/* %227 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_183)
begin
memory_controller_size = 2'd2;
end
/* main: %226*/
/* store i32 %228, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB57_185)
begin
memory_controller_size = 2'd2;
end
/* main: %229*/
/* %230 = load i8* %scevgep8.i5.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB58_186)
begin
memory_controller_size = 2'd0;
end
/* main: %229*/
/* %233 = load i32* %232, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB58_187)
begin
memory_controller_size = 2'd2;
end
/* main: %235*/
/* %236 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_190)
begin
memory_controller_size = 2'd2;
end
/* main: %235*/
/* store i32 %237, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB59_192)
begin
memory_controller_size = 2'd2;
end
/* main: %238*/
/* %239 = load i8* %scevgep7.i6.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB60_193)
begin
memory_controller_size = 2'd0;
end
/* main: %242*/
/* %243 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_196)
begin
memory_controller_size = 2'd2;
end
/* main: %242*/
/* store i32 %244, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB61_198)
begin
memory_controller_size = 2'd2;
end
/* main: %248*/
/* %250 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_201)
begin
memory_controller_size = 2'd0;
end
/* main: %248*/
/* %254 = load i8* %249, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB64_202)
begin
memory_controller_size = 2'd0;
end
/* main: %248*/
/* %260 = load i32* %4, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB64_205)
begin
memory_controller_size = 2'd2;
end
/* main: %262*/
/* %263 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_208)
begin
memory_controller_size = 2'd2;
end
/* main: %262*/
/* store i32 %264, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB65_210)
begin
memory_controller_size = 2'd2;
end
/* main: %.lr.ph5.i.i.i*/
/* %267 = load i8* %ReadBuf.6, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB67_212)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph5.i.i.i*/
/* %271 = load i32* %270, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB67_215)
begin
memory_controller_size = 2'd2;
end
/* main: %273*/
/* %274 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_218)
begin
memory_controller_size = 2'd2;
end
/* main: %273*/
/* store i32 %275, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB68_220)
begin
memory_controller_size = 2'd2;
end
/* main: %287*/
/* %290 = load i8* %288, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB73_225)
begin
memory_controller_size = 2'd0;
end
/* main: %287*/
/* store i32 %291, i32* %scevgep.i9.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB73_227)
begin
memory_controller_size = 2'd2;
end
/* main: %293*/
/* %296 = load i32* %295, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB74_229)
begin
memory_controller_size = 2'd2;
end
/* main: %298*/
/* %299 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_232)
begin
memory_controller_size = 2'd2;
end
/* main: %298*/
/* store i32 %300, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB75_234)
begin
memory_controller_size = 2'd2;
end
/* main: %.lr.ph.i10.i.i*/
/* %306 = load i8* %304, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB77_236)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i10.i.i*/
/* store i32 %307, i32* %scevgep8.i11.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB77_238)
begin
memory_controller_size = 2'd2;
end
/* main: %312*/
/* %314 = load i8* %ReadBuf.2, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_240)
begin
memory_controller_size = 2'd0;
end
/* main: %312*/
/* %318 = load i8* %313, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB79_241)
begin
memory_controller_size = 2'd0;
end
/* main: %312*/
/* %324 = load i32* %5, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB79_244)
begin
memory_controller_size = 2'd2;
end
/* main: %326*/
/* %327 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_247)
begin
memory_controller_size = 2'd2;
end
/* main: %326*/
/* store i32 %328, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB80_249)
begin
memory_controller_size = 2'd2;
end
/* main: %.lr.ph.i15.i.i*/
/* %332 = load i8* %330, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB82_251)
begin
memory_controller_size = 2'd0;
end
/* main: %.lr.ph.i15.i.i*/
/* %339 = load i32* %338, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB82_254)
begin
memory_controller_size = 2'd2;
end
/* main: %341*/
/* %342 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_257)
begin
memory_controller_size = 2'd2;
end
/* main: %341*/
/* store i32 %343, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB83_259)
begin
memory_controller_size = 2'd2;
end
/* main: %344*/
/* %346 = load i32* %345, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB84_260)
begin
memory_controller_size = 2'd2;
end
/* main: %348*/
/* %349 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_263)
begin
memory_controller_size = 2'd2;
end
/* main: %348*/
/* store i32 %350, i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB85_265)
begin
memory_controller_size = 2'd2;
end
/* main: %.split.us.i.i.i*/
/* %356 = load i8* %354, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB87_267)
begin
memory_controller_size = 2'd0;
end
/* main: %.split.us.i.i.i*/
/* %358 = load i32* %scevgep.i16.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_268)
begin
memory_controller_size = 2'd2;
end
/* main: %.split.us.i.i.i*/
/* store i32 %357, i32* %359, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB87_270)
begin
memory_controller_size = 2'd2;
end
/* main: %..split_crit_edge.i.i.i*/
/* %363 = load i8* %361, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_271)
begin
memory_controller_size = 2'd0;
end
/* main: %..split_crit_edge.i.i.i*/
/* %367 = load i8* %362, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB88_272)
begin
memory_controller_size = 2'd0;
end
/* main: %..split_crit_edge.i.i.i*/
/* %370 = load i32* %scevgep4.i18.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_273)
begin
memory_controller_size = 2'd2;
end
/* main: %..split_crit_edge.i.i.i*/
/* store i32 %369, i32* %371, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB88_275)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* %374 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_277)
begin
memory_controller_size = 2'd1;
end
/* main: %read_markers.exit.i*/
/* %379 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB90_278)
begin
memory_controller_size = 2'd1;
end
/* main: %read_markers.exit.i*/
/* store i32 %383, i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_328)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 %385, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_332)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 %386, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_dc_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_336)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 %387, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_340)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 %388, i32* getelementptr inbounds ([2 x i32]* @p_jinfo_ac_dhuff_tbl_ml, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_344)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i8* %p_jinfo_jpeg_data.0, i8** @CurHuffReadBuf, align 4, !tbaa !4*/
if (cur_state == LEGUP_F_main_BB90_345)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_346)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.1.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_347)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* %scevgep148.2.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_348)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_349)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_350)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_351)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 1), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_352)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_vpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_353)
begin
memory_controller_size = 2'd2;
end
/* main: %read_markers.exit.i*/
/* store i32 0, i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 2), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB90_354)
begin
memory_controller_size = 2'd2;
end
/* main: %392*/
/* %393 = load i32* %scevgep.i.i3.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_366)
begin
memory_controller_size = 2'd2;
end
/* main: %392*/
/* %394 = load i32* %scevgep2.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_367)
begin
memory_controller_size = 2'd2;
end
/* main: %392*/
/* %396 = load i32* %scevgep3.i.i2.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB94_368)
begin
memory_controller_size = 2'd2;
end
/* main: %425*/
/* store i32 %r.0.i.i.i, i32* %scevgep4.i.i6.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_380)
begin
memory_controller_size = 2'd2;
end
/* main: %425*/
/* store i32 %g.0.i.i.i, i32* %scevgep5.i.i5.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_381)
begin
memory_controller_size = 2'd2;
end
/* main: %425*/
/* store i32 %b.0.i.i.i, i32* %scevgep6.i.i4.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB103_382)
begin
memory_controller_size = 2'd2;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %427 = load i16* @p_jinfo_image_width, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_383)
begin
memory_controller_size = 2'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %429 = load i16* @p_jinfo_image_height, align 2, !tbaa !3*/
if (cur_state == LEGUP_F_main_BB104_384)
begin
memory_controller_size = 2'd1;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %.pre.i.i = load i32* getelementptr inbounds ([3 x i32]* @OutData_comp_hpos, i32 0, i32 0), align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_385)
begin
memory_controller_size = 2'd2;
end
/* main: %YuvToRgb.exit.loopexit.i.i*/
/* %431 = load i32* @p_jinfo_MCUWidth, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB104_386)
begin
memory_controller_size = 2'd2;
end
/* main: %432*/
/* %434 = load i32* %scevgep139.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB105_389)
begin
memory_controller_size = 2'd2;
end
/* main: %440*/
/* %441 = load i32* %.14.us.i.i.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB108_396)
begin
memory_controller_size = 2'd2;
end
/* main: %440*/
/* store i8 %442, i8* %scevgep24.i.i.i.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB108_398)
begin
memory_controller_size = 2'd0;
end
/* main: %WriteOneBlock.exit.i.i.i*/
/* %443 = load i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB110_400)
begin
memory_controller_size = 2'd2;
end
/* main: %445*/
/* store i32 0, i32* %scevgep142.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB111_403)
begin
memory_controller_size = 2'd2;
end
/* main: %454*/
/* %455 = load i32* %scevgep.i3.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_427)
begin
memory_controller_size = 2'd2;
end
/* main: %454*/
/* %456 = load i32* %scevgep2.i4.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_428)
begin
memory_controller_size = 2'd2;
end
/* main: %454*/
/* %458 = load i32* %scevgep3.i5.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB118_429)
begin
memory_controller_size = 2'd2;
end
/* main: %487*/
/* store i32 %r.0.i9.i.i, i32* %scevgep4.i6.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_441)
begin
memory_controller_size = 2'd2;
end
/* main: %487*/
/* store i32 %g.0.i10.i.i, i32* %scevgep5.i7.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_442)
begin
memory_controller_size = 2'd2;
end
/* main: %487*/
/* store i32 %b.0.i11.i.i, i32* %scevgep6.i8.i.i, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB127_443)
begin
memory_controller_size = 2'd2;
end
/* main: %decode_start.exit.i*/
/* %main_result.promoted3.i = load i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB130_454)
begin
memory_controller_size = 2'd2;
end
/* main: %491*/
/* %493 = load i8* %scevgep.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_457)
begin
memory_controller_size = 2'd0;
end
/* main: %491*/
/* %494 = load i8* %scevgep7.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB131_458)
begin
memory_controller_size = 2'd0;
end
/* main: %.preheader.1.i*/
/* %500 = load i8* %scevgep.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_461)
begin
memory_controller_size = 2'd0;
end
/* main: %.preheader.1.i*/
/* %501 = load i8* %scevgep7.1.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB132_462)
begin
memory_controller_size = 2'd0;
end
/* main: %jpeg2bmp_main.exit*/
/* store i32 %.storemerge, i32* @main_result, align 4*/
if (cur_state == LEGUP_F_main_BB133_465)
begin
memory_controller_size = 2'd2;
end
/* main: %jpeg2bmp_main.exit*/
/* %511 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB133_466)
begin
memory_controller_size = 2'd2;
end
/* main: %.preheader.2.i*/
/* %514 = load i8* %scevgep.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_469)
begin
memory_controller_size = 2'd0;
end
/* main: %.preheader.2.i*/
/* %515 = load i8* %scevgep7.2.i, align 1, !tbaa !1*/
if (cur_state == LEGUP_F_main_BB134_470)
begin
memory_controller_size = 2'd0;
end
/* main: %524*/
/* %525 = load i32* @main_result, align 4, !tbaa !0*/
if (cur_state == LEGUP_F_main_BB137_475)
begin
memory_controller_size = 2'd2;
end
end
endmodule
`timescale 1 ns / 1 ns
module ram_two_ports
(
clk,
address_a,
wren_a,
data_a,
q_a,
address_b,
wren_b,
data_b,
q_b,
byteena_a,
byteena_b
);
parameter width_a = 1'd0;
parameter widthad_a = 1'd0;
parameter numwords_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED";
parameter width_be_a = 1'd0;
parameter width_be_b = 1'd0;
input clk;
input [(widthad_a-1):0] address_a;
input wren_a;
input [(width_a-1):0] data_a;
output [(width_a-1):0] q_a;
input [(widthad_b-1):0] address_b;
input wren_b;
input [(width_b-1):0] data_b;
output [(width_b-1):0] q_b;
input [width_be_a-1:0] byteena_a;
input [width_be_b-1:0] byteena_b;
reg clk_wire;
altsyncram altsyncram_component (
.byteena_a (byteena_a),
.byteena_b (byteena_b),
.wren_a (wren_a),
.wren_b (wren_b),
.clock0 (clk_wire),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.aclr0 (1'd0),
.aclr1 (1'd0),
.addressstall_a (1'd0),
.addressstall_b (1'd0),
.clock1 (1'd1),
.clocken0 (1'd1),
.clocken1 (1'd1),
.clocken2 (1'd1),
.clocken3 (1'd1),
.eccstatus (),
.rden_a (1'd1),
.rden_b (1'd1)
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = init_file,
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = numwords_a,
altsyncram_component.numwords_b = numwords_b,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.widthad_a = widthad_a,
altsyncram_component.widthad_b = widthad_b,
altsyncram_component.width_a = width_a,
altsyncram_component.width_b = width_b,
altsyncram_component.width_byteena_a = width_be_a,
altsyncram_component.width_byteena_b = width_be_b;
always @(*) begin
clk_wire = clk;
end
endmodule
`timescale 1 ns / 1 ns
module main_tb
(
);
reg clk;
reg reset;
reg start;
wire [31:0] return_val;
wire finish;
top top_inst (
.clk (clk),
.reset (reset),
.start (start),
.finish (finish),
.return_val (return_val)
);
initial
clk <= #0 0;
always @(clk)
clk <= #1 ~clk;
initial begin
//$monitor("At t=%t clk=%b %b %b %b %d", $time, clk, reset, start, finish, return_val);
@(negedge clk);
reset <= 1;
@(negedge clk);
reset <= 0;
start <= 1;
end
always@(finish) begin
if (finish == 1) begin
$display("At t=%t clk=%b finish=%b return_val=%d", $time, clk, finish, return_val);
$finish;
end
end
endmodule
|
`define HEADER_VENDOR_ID 16'h0000
`define HEADER_DEVICE_ID 16'h0000
`define HEADER_REVISION_ID 8'h00
`define FPGA
`define XILINX
`define WBW_ADDR_LENGTH 7
`define WBR_ADDR_LENGTH 7
`define PCIW_ADDR_LENGTH 7
`define PCIR_ADDR_LENGTH 7
`define PCI_FIFO_RAM_ADDR_LENGTH 8
`define WB_FIFO_RAM_ADDR_LENGTH 8
`define ETH_WISHBONE_B3
`define ETH_TX_FIFO_CNT_WIDTH 4
`define ETH_TX_FIFO_DEPTH 8
`define ETH_RX_FIFO_CNT_WIDTH 4
`define ETH_RX_FIFO_DEPTH 8
`define ETH_BURST_CNT_WIDTH 3
`define ETH_BURST_LENGTH 4
|
`include "device.v"
`include "eth_top.v"
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_clockgen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_clockgen.v,v $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:55 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= #Tp 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= #Tp CounterPreset[7:0];
end
else
Counter[7:0] <= #Tp Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= #Tp 1'b0;
else
begin
if(CountEq0)
Mdc <= #Tp ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_crc.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_crc.v,v $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
parameter Tp = 1;
input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initialize;
output [31:0] Crc;
output CrcError;
reg [31:0] Crc;
wire [31:0] CrcNext;
assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
assign CrcNext[20] = Crc[16];
assign CrcNext[21] = Crc[17];
assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
assign CrcNext[30] = Crc[26];
assign CrcNext[31] = Crc[27];
always @ (posedge Clk or posedge Reset)
begin
if (Reset)
Crc <= #1 32'hffffffff;
else
if(Initialize)
Crc <= #Tp 32'hffffffff;
else
Crc <= #Tp CrcNext;
end
assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_fifo.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_fifo.v,v $
// Revision 1.3 2002/04/22 13:45:52 mohor
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
// ETH_FIFO_XILINX in eth_defines.v).
//
// Revision 1.2 2002/03/25 13:33:04 mohor
// When clear and read/write are active at the same time, cnt and pointers are
// set to 1.
//
// Revision 1.1 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
//
//`include "eth_defines.v"
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_defines.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_defines.v,v $
// Revision 1.29 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.28 2002/11/15 14:27:15 mohor
// Since r_Rst bit is not used any more, default value is changed to 0xa000.
//
// Revision 1.27 2002/11/01 18:19:34 mohor
// Defines fixed to use generic RAM by default.
//
// Revision 1.26 2002/10/24 18:53:03 mohor
// fpga define added.
//
// Revision 1.3 2002/10/11 16:57:54 igorm
// eth_defines.v tagged with rel_5 used.
//
// Revision 1.25 2002/10/10 16:47:44 mohor
// Defines changed to have ETH_ prolog.
// ETH_WISHBONE_B# define added.
//
// Revision 1.24 2002/10/10 16:33:11 mohor
// Bist added.
//
// Revision 1.23 2002/09/23 18:22:48 mohor
// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
// core.
//
// Revision 1.22 2002/09/04 18:36:49 mohor
// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).
//
// Revision 1.21 2002/08/16 22:09:47 mohor
// Defines for register width added. mii_rst signal in MIIMODER register
// changed.
//
// Revision 1.20 2002/08/14 19:31:48 mohor
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
// need to multiply or devide any more.
//
// Revision 1.19 2002/07/23 15:28:31 mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.18 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.17 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.16 2002/03/19 12:53:29 mohor
// Some defines that are used in testbench only were moved to tb_eth_defines.v
// file.
//
// Revision 1.15 2002/02/26 16:11:32 mohor
// Number of interrupts changed
//
// Revision 1.14 2002/02/16 14:03:44 mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.13 2002/02/16 13:06:33 mohor
// EXTERNAL_DMA used instead of WISHBONE_DMA.
//
// Revision 1.12 2002/02/15 10:58:31 mohor
// Changed that were lost with last update put back to the file.
//
// Revision 1.11 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.10 2002/02/12 17:01:19 mohor
// HASH0 and HASH1 registers added.
// Revision 1.9 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.8 2002/02/05 16:44:38 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
// Revision 1.7 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.6 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.5 2001/12/05 10:21:37 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.4 2001/11/13 14:23:56 mohor
// Generic memory model is used. Defines are changed for the same reason.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
// Ethernet implemented in Xilinx Chips
//`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
//`define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
// Core is going to be implemented in Virtex FPGA and contains Virtex
// specific elements.
// Ethernet implemented in ASIC with Virtual Silicon RAMs
// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
`define ETH_MODER_ADR 8'h0 // 0x0
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
`define ETH_INT_MASK_ADR 8'h2 // 0x8
`define ETH_IPGT_ADR 8'h3 // 0xC
`define ETH_IPGR1_ADR 8'h4 // 0x10
`define ETH_IPGR2_ADR 8'h5 // 0x14
`define ETH_PACKETLEN_ADR 8'h6 // 0x18
`define ETH_COLLCONF_ADR 8'h7 // 0x1C
`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
`define ETH_CTRLMODER_ADR 8'h9 // 0x24
`define ETH_MIIMODER_ADR 8'hA // 0x28
`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
`define ETH_MIIADDRESS_ADR 8'hC // 0x30
`define ETH_MIITX_DATA_ADR 8'hD // 0x34
`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
`define ETH_MIISTATUS_ADR 8'hF // 0x3C
`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
`define ETH_HASH0_ADR 8'h12 // 0x48
`define ETH_HASH1_ADR 8'h13 // 0x4C
`define ETH_TX_CTRL_ADR 8'h14 // 0x50
`define ETH_RX_CTRL_ADR 8'h15 // 0x54
`define ETH_MODER_DEF 17'h0A000
`define ETH_INT_MASK_DEF 7'h0
`define ETH_IPGT_DEF 7'h12
`define ETH_IPGR1_DEF 7'h0C
`define ETH_IPGR2_DEF 7'h12
`define ETH_PACKETLEN_DEF 32'h00400600
`define ETH_COLLCONF0_DEF 6'h3f
`define ETH_COLLCONF1_DEF 4'hF
`define ETH_TX_BD_NUM_DEF 8'h40
`define ETH_CTRLMODER_DEF 3'h0
`define ETH_MIIMODER_DEF 10'h064
`define ETH_MIIADDRESS0_DEF 5'h00
`define ETH_MIIADDRESS1_DEF 5'h00
`define ETH_MIITX_DATA_DEF 16'h0000
`define ETH_MIIRX_DATA_DEF 16'h0000
`define ETH_MIISTATUS_DEF 32'h00000000
`define ETH_MAC_ADDR0_DEF 32'h00000000
`define ETH_MAC_ADDR1_DEF 16'h0000
`define ETH_HASH0_DEF 32'h00000000
`define ETH_HASH1_DEF 32'h00000000
`define ETH_RX_CTRL_DEF 16'h0
`define ETH_MODER_WIDTH 17
`define ETH_INT_SOURCE_WIDTH 7
`define ETH_INT_MASK_WIDTH 7
`define ETH_IPGT_WIDTH 7
`define ETH_IPGR1_WIDTH 7
`define ETH_IPGR2_WIDTH 7
`define ETH_PACKETLEN_WIDTH 32
`define ETH_TX_BD_NUM_WIDTH 8
`define ETH_CTRLMODER_WIDTH 3
`define ETH_MIIMODER_WIDTH 9
`define ETH_MIITX_DATA_WIDTH 16
`define ETH_MIIRX_DATA_WIDTH 16
`define ETH_MIISTATUS_WIDTH 3
`define ETH_MAC_ADDR0_WIDTH 32
`define ETH_MAC_ADDR1_WIDTH 16
`define ETH_HASH0_WIDTH 32
`define ETH_HASH1_WIDTH 32
`define ETH_TX_CTRL_WIDTH 17
`define ETH_RX_CTRL_WIDTH 16
// Outputs are registered (uncomment when needed)
`define ETH_REGISTERED_OUTPUTS
// Settings for TX FIFO
//`define ETH_TX_FIFO_CNT_WIDTH 5
//`define ETH_TX_FIFO_DEPTH 16
`define ETH_TX_FIFO_DATA_WIDTH 32
// Settings for RX FIFO
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 16
`define ETH_RX_FIFO_DATA_WIDTH 32
// Burst length
//`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH
//`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH
// WISHBONE interface is Revision B3 compliant (uncomment when needed)
//`define ETH_WISHBONE_B3
//`include "timescale.v"
// `timescale 1ns / 1ns
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
parameter Tp = 1;
input clk;
input reset;
input write;
input read;
input clear;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output almost_full;
output full;
output almost_empty;
output empty;
output [CNT_WIDTH-1:0] cnt;
`ifdef ETH_FIFO_XILINX
`else
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
`endif
reg [CNT_WIDTH-1:0] cnt;
reg [CNT_WIDTH-2:0] read_pointer;
reg [CNT_WIDTH-2:0] write_pointer;
wire [CNT_WIDTH-2:0] write_address;
wire [CNT_WIDTH-2:0] read_address;
always @ (posedge clk or posedge reset)
begin
if(reset)
cnt <=#Tp 0;
else
if(clear)
cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};
else
if(read ^ write)
if(read)
cnt <=#Tp cnt - 1'b1;
else
cnt <=#Tp cnt + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
read_pointer <=#Tp 0;
else
if(clear)
read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};
else
if(read & ~empty)
read_pointer <=#Tp read_pointer + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
write_pointer <=#Tp 0;
else
if(clear)
write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};
else
if(write & ~full)
write_pointer <=#Tp write_pointer + 1'b1;
end
assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full = cnt == DEPTH;
assign almost_full = &cnt[CNT_WIDTH-2:0];
`ifdef ETH_FIFO_XILINX
xilinx_dist_ram_16x32 fifo
( .data_out(data_out),
.we(write & ~full),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.wclk(clk)
);
`else
assign read_address = ( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer);
assign write_address = (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer);
always @ (posedge clk)
begin
if(write & (clear |~full))
fifo[write_address] <=#Tp data_in;
end
assign data_out = fifo[read_address];
`endif
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_receivecontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_receivecontrol.v,v $
// Revision 1.5 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.4 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
);
parameter Tp = 1;
input MTxClk;
input MRxClk;
input TxReset;
input RxReset;
input [7:0] RxData;
input RxValid;
input RxStartFrm;
input RxEndFrm;
input RxFlow;
input ReceiveEnd;
input [47:0]MAC;
input DlyCrcEn;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmOut;
input ReceivedLengthOK;
input ReceivedPacketGood;
input TxUsedDataOutDetected;
input RxStatusWriteLatched_sync2;
input r_PassAll;
output Pause;
output ReceivedPauseFrm;
output AddressOK;
output SetPauseTimer;
reg Pause;
reg AddressOK; // Multicast or unicast address detected
reg TypeLengthOK; // Type/Length field contains 0x8808
reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
reg OpCodeOK; // PAUSE opcode detected (0x0001)
reg [2:0] DlyCrcCnt;
reg [4:0] ByteCnt;
reg [15:0] AssembledTimerValue;
reg [15:0] LatchedTimerValue;
reg ReceivedPauseFrm;
reg ReceivedPauseFrmWAddr;
reg PauseTimerEq0_sync1;
reg PauseTimerEq0_sync2;
reg [15:0] PauseTimer;
reg Divider2;
reg [5:0] SlotTimer;
wire [47:0] ReservedMulticast; // 0x0180C2000001
wire [15:0] TypeLength; // 0x8808
wire ResetByteCnt; //
wire IncrementByteCnt; //
wire ByteCntEq0; // ByteCnt = 0
wire ByteCntEq1; // ByteCnt = 1
wire ByteCntEq2; // ByteCnt = 2
wire ByteCntEq3; // ByteCnt = 3
wire ByteCntEq4; // ByteCnt = 4
wire ByteCntEq5; // ByteCnt = 5
wire ByteCntEq12; // ByteCnt = 12
wire ByteCntEq13; // ByteCnt = 13
wire ByteCntEq14; // ByteCnt = 14
wire ByteCntEq15; // ByteCnt = 15
wire ByteCntEq16; // ByteCnt = 16
wire ByteCntEq17; // ByteCnt = 17
wire ByteCntEq18; // ByteCnt = 18
wire DecrementPauseTimer; //
wire PauseTimerEq0; //
wire ResetSlotTimer; //
wire IncrementSlotTimer; //
wire SlotFinished; //
// Reserved multicast address and Type/Length for PAUSE control
assign ReservedMulticast = 48'h0180C2000001;
assign TypeLength = 16'h8808;
// Address Detection (Multicast or unicast)
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
AddressOK <= #Tp 1'b0;
else
if(DetectionWindow & ByteCntEq0)
AddressOK <= #Tp RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
else
if(DetectionWindow & ByteCntEq1)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
else
if(DetectionWindow & ByteCntEq2)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
else
if(DetectionWindow & ByteCntEq3)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
else
if(DetectionWindow & ByteCntEq4)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK;
else
if(DetectionWindow & ByteCntEq5)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK;
else
if(ReceiveEnd)
AddressOK <= #Tp 1'b0;
end
// TypeLengthOK (Type/Length Control frame detected)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
TypeLengthOK <= #Tp 1'b0;
else
if(DetectionWindow & ByteCntEq12)
TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
else
if(DetectionWindow & ByteCntEq13)
TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
else
if(ReceiveEnd)
TypeLengthOK <= #Tp 1'b0;
end
// Latch Control Frame Opcode
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
OpCodeOK <= #Tp 1'b0;
else
if(ByteCntEq16)
OpCodeOK <= #Tp 1'b0;
else
begin
if(DetectionWindow & ByteCntEq14)
OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
if(DetectionWindow & ByteCntEq15)
OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
end
end
// ReceivedPauseFrmWAddr (+Address Check)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
ReceivedPauseFrmWAddr <= #Tp 1'b0;
else
if(ReceiveEnd)
ReceivedPauseFrmWAddr <= #Tp 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
ReceivedPauseFrmWAddr <= #Tp 1'b1;
end
// Assembling 16-bit timer value from two 8-bit data
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
AssembledTimerValue[15:0] <= #Tp 16'h0;
else
if(RxStartFrm)
AssembledTimerValue[15:0] <= #Tp 16'h0;
else
begin
if(DetectionWindow & ByteCntEq16)
AssembledTimerValue[15:8] <= #Tp RxData[7:0];
if(DetectionWindow & ByteCntEq17)
AssembledTimerValue[7:0] <= #Tp RxData[7:0];
end
end
// Detection window (while PAUSE detection is possible)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
DetectionWindow <= #Tp 1'b1;
else
if(ByteCntEq18)
DetectionWindow <= #Tp 1'b0;
else
if(ReceiveEnd)
DetectionWindow <= #Tp 1'b1;
end
// Latching Timer Value
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
LatchedTimerValue[15:0] <= #Tp 16'h0;
else
if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
else
if(ReceiveEnd)
LatchedTimerValue[15:0] <= #Tp 16'h0;
end
// Delayed CEC counter
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
DlyCrcCnt <= #Tp 3'h0;
else
if(RxValid & RxEndFrm)
DlyCrcCnt <= #Tp 3'h0;
else
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
// Byte counter
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ByteCnt[4:0] <= #Tp 5'h0;
else
if(ResetByteCnt)
ByteCnt[4:0] <= #Tp 5'h0;
else
if(IncrementByteCnt)
ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;
end
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
// PauseTimer[15:0]
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
PauseTimer[15:0] <= #Tp 16'h0;
else
if(SetPauseTimer)
PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];
else
if(DecrementPauseTimer)
PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;
end
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
// Synchronization of the pause timer
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
PauseTimerEq0_sync1 <= #Tp 1'b1;
PauseTimerEq0_sync2 <= #Tp 1'b1;
end
else
begin
PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;
PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;
end
end
// Pause signal generation
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
Pause <= #Tp 1'b0;
else
if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;
end
// Divider2 is used for incrementing the Slot timer every other clock
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
Divider2 <= #Tp 1'b0;
else
if(|PauseTimer[15:0] & RxFlow)
Divider2 <= #Tp ~Divider2;
else
Divider2 <= #Tp 1'b0;
end
assign ResetSlotTimer = RxReset;
assign IncrementSlotTimer = Pause & RxFlow & Divider2;
// SlotTimer
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
SlotTimer[5:0] <= #Tp 6'h0;
else
if(ResetSlotTimer)
SlotTimer[5:0] <= #Tp 6'h0;
else
if(IncrementSlotTimer)
SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;
end
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
// Pause Frame received
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ReceivedPauseFrm <=#Tp 1'b0;
else
if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
ReceivedPauseFrm <=#Tp 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
ReceivedPauseFrm <=#Tp 1'b1;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_maccontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_maccontrol.v,v $
// Revision 1.7 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.6 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.5 2002/11/21 00:14:39 mohor
// TxDone and TxAbort changed so they're not propagated to the wishbone
// module when control frame is transmitted.
//
// Revision 1.4 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input MRxClk; // Receive clock (from PHY)
input TxReset; // Transmit reset
input RxReset; // Receive reset
input TPauseRq; // Transmit control frame (from host)
input [7:0] TxDataIn; // Transmit packet data byte (from host)
input TxStartFrmIn; // Transmit packet start frame input (from host)
input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
input TxEndFrmIn; // Transmit packet end frame input (from host)
input TxDoneIn; // Transmit packet done (from TxEthMAC)
input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
input PadIn; // Padding (input from registers)
input CrcEnIn; // Crc append (input from registers)
input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
input RxValid; // Received a valid packet
input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
input ReceivedPacketGood; // Received packet is good
input ReceivedLengthOK; // Length of the received packet is OK
input TxFlow; // Tx flow control (from registers)
input RxFlow; // Rx flow control (from registers)
input DlyCrcEn; // Delayed CRC enabled (from registers)
input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
input [47:0] MAC; // MAC address (from registers)
input RxStatusWriteLatched_sync2;
input r_PassAll;
output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
output TxDoneOut; // Transmit packet done (to host)
output TxAbortOut; // Transmit packet aborted (to host)
output TxUsedDataOut; // Transmit packet used data (to host)
output PadOut; // Padding (output to TxEthMAC)
output CrcEnOut; // Crc append (output to TxEthMAC)
output WillSendControlFrame;
output TxCtrlEndFrm;
output ReceivedPauseFrm;
output ControlFrmAddressOK;
output SetPauseTimer;
reg TxUsedDataOutDetected;
reg TxAbortInLatched;
reg TxDoneInLatched;
reg MuxedDone;
reg MuxedAbort;
wire Pause;
wire TxCtrlStartFrm;
wire [7:0] ControlData;
wire CtrlMux;
wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
wire BlockTxDone;
// Signal TxUsedDataOut was detected (a transfer is already in progress)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxDoneIn | TxAbortIn)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxUsedDataOut)
TxUsedDataOutDetected <= #Tp 1'b1;
end
// Latching variables
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
TxAbortInLatched <= #Tp 1'b0;
TxDoneInLatched <= #Tp 1'b0;
end
else
begin
TxAbortInLatched <= #Tp TxAbortIn;
TxDoneInLatched <= #Tp TxDoneIn;
end
end
// Generating muxed abort signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedAbort <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedAbort <= #Tp 1'b0;
else
if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
MuxedAbort <= #Tp 1'b1;
end
// Generating muxed done signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedDone <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedDone <= #Tp 1'b0;
else
if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
MuxedDone <= #Tp 1'b1;
end
// TxDoneOut
assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
// TxAbortOut
assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
// TxUsedDataOut
assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
// TxStartFrmOut
assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
// TxEndFrmOut
assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
// TxDataOut[7:0]
assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
// PadOut
assign PadOut = PadIn | SendingCtrlFrm;
// CrcEnOut
assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
// Connecting receivecontrol module
eth_receivecontrol receivecontrol1
(
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
.r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
);
eth_transmitcontrol transmitcontrol1
(
.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
.TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
.MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
.CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
);
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_macstatus.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_macstatus.v,v $
// Revision 1.15 2003/01/30 13:28:19 tadejm
// Defer indication changed.
//
// Revision 1.14 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.13 2002/11/13 22:30:58 tadejm
// Late collision is reported only when not in the full duplex.
// Sample is taken (for status) as soon as MRxDV is not valid (regardless
// of the received byte cnt).
//
// Revision 1.12 2002/09/12 14:50:16 mohor
// CarrierSenseLost bug fixed when operating in full duplex mode.
//
// Revision 1.11 2002/09/04 18:38:03 mohor
// CarrierSenseLost status is not set when working in loopback mode.
//
// Revision 1.10 2002/07/25 18:17:46 mohor
// InvalidSymbol generation changed.
//
// Revision 1.9 2002/04/22 13:51:44 mohor
// Short frame and ReceivedLengthOK were not detected correctly.
//
// Revision 1.8 2002/02/18 10:40:17 mohor
// Small fixes.
//
// Revision 1.7 2002/02/15 17:07:39 mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.6 2002/02/11 09:18:21 mohor
// Tx status is written back to the BD.
//
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
module eth_macstatus(
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, TxStartFrm,
StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
r_FullD
);
parameter Tp = 1;
input MRxClk;
input Reset;
input RxCrcError;
input MRxErr;
input MRxDV;
input RxStateSFD;
input [1:0] RxStateData;
input RxStatePreamble;
input RxStateIdle;
input Transmitting;
input [15:0] RxByteCnt;
input RxByteCntEq0;
input RxByteCntGreat2;
input RxByteCntMaxFrame;
input [3:0] MRxD;
input Collision;
input [5:0] CollValid;
input r_RecSmall;
input [15:0] r_MinFL;
input [15:0] r_MaxFL;
input r_HugEn;
input StartTxDone;
input StartTxAbort;
input [3:0] RetryCnt;
input MTxClk;
input MaxCollisionOccured;
input LateCollision;
input DeferIndication;
input TxStartFrm;
input StatePreamble;
input [1:0] StateData;
input CarrierSense;
input TxUsedData;
input Loopback;
input r_FullD;
output ReceivedLengthOK;
output ReceiveEnd;
output ReceivedPacketGood;
output InvalidSymbol;
output LatchedCrcError;
output RxLateCollision;
output ShortFrame;
output DribbleNibble;
output ReceivedPacketTooBig;
output LoadRxStatus;
output [3:0] RetryCntLatched;
output RetryLimit;
output LateCollLatched;
output DeferLatched;
output CarrierSenseLost;
output LatchedMRxErr;
reg ReceiveEnd;
reg LatchedCrcError;
reg LatchedMRxErr;
reg LoadRxStatus;
reg InvalidSymbol;
reg [3:0] RetryCntLatched;
reg RetryLimit;
reg LateCollLatched;
reg DeferLatched;
reg CarrierSenseLost;
wire TakeSample;
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateSFD)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateData[0])
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
end
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedMRxErr <=#Tp 1'b0;
else
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
LatchedMRxErr <=#Tp 1'b1;
else
LatchedMRxErr <=#Tp 1'b0;
end
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
// Time to take a sample
//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
assign TakeSample = (|RxStateData) & (~MRxDV) |
RxStateData[0] & MRxDV & RxByteCntMaxFrame;
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LoadRxStatus <=#Tp 1'b0;
else
LoadRxStatus <=#Tp TakeSample;
end
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceiveEnd <=#Tp 1'b0;
else
ReceiveEnd <=#Tp LoadRxStatus;
end
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
InvalidSymbol <=#Tp 1'b0;
else
if(LoadRxStatus & ~SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b0;
else
if(SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b1;
end
// Late Collision
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxLateCollision <=#Tp 1'b0;
else
if(LoadRxStatus)
RxLateCollision <=#Tp 1'b0;
else
if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
RxLateCollision <=#Tp 1'b1;
end
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxColWindow <=#Tp 1'b1;
else
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
RxColWindow <=#Tp 1'b0;
else
if(RxStateIdle)
RxColWindow <=#Tp 1'b1;
end
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShortFrame <=#Tp 1'b0;
else
if(LoadRxStatus)
ShortFrame <=#Tp 1'b0;
else
if(TakeSample)
ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
end
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DribbleNibble <=#Tp 1'b0;
else
if(RxStateSFD)
DribbleNibble <=#Tp 1'b0;
else
if(~MRxDV & RxStateData[1])
DribbleNibble <=#Tp 1'b1;
end
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(LoadRxStatus)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(TakeSample)
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCntLatched <=#Tp 4'h0;
else
if(StartTxDone | StartTxAbort)
RetryCntLatched <=#Tp RetryCnt;
end
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryLimit <=#Tp 4'h0;
else
if(StartTxDone | StartTxAbort)
RetryLimit <=#Tp MaxCollisionOccured;
end
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LateCollLatched <=#Tp 1'b0;
else
if(StartTxDone | StartTxAbort)
LateCollLatched <=#Tp LateCollision;
end
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DeferLatched <=#Tp 1'b0;
else
if(DeferIndication & TxUsedData)
DeferLatched <=#Tp 1'b1;
else
if(TxStartFrm)
DeferLatched <=#Tp 1'b0;
end
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
CarrierSenseLost <=#Tp 1'b0;
else
if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
CarrierSenseLost <=#Tp 1'b1;
else
if(TxStartFrm)
CarrierSenseLost <=#Tp 1'b0;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_miim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_miim.v,v $
// Revision 1.4 2002/08/14 18:32:10 mohor
// - Busy signal was not set on time when scan status operation was performed
// and clock was divided with more than 2.
// - Nvalid remains valid two more clocks (was previously cleared too soon).
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_miim
(
Clk,
Reset,
Divider,
NoPre,
CtrlData,
Rgad,
Fiad,
WCtrlData,
RStat,
ScanStat,
Mdi,
Mdo,
MdoEn,
Mdc,
Busy,
Prsd,
LinkFail,
Nvalid,
WCtrlDataStart,
RStatStart,
UpdateMIIRX_DATAReg
);
input Clk; // Host Clock
input Reset; // General Reset
input [7:0] Divider; // Divider for the host clock
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
input Mdi; // MII Management Data In
output Mdc; // MII Management Data Clock
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
parameter Tp = 1;
reg Nvalid;
reg EndBusy_d; // Pre-end Busy signal
reg EndBusy; // End Busy signal (stops the operation in progress)
reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle
reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles
reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles
reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)
reg WCtrlDataStart_q;
reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle
reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles
reg RStat_q1; // Read Status operation delayed 1 Clk cycle
reg RStat_q2; // Read Status operation delayed 2 Clk cycles
reg RStat_q3; // Read Status operation delayed 3 Clk cycles
reg RStatStart; // Start Read Status Command (positive edge detected)
reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle
reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles
reg ScanStat_q1; // Scan Status operation delayed 1 cycle
reg ScanStat_q2; // Scan Status operation delayed 2 cycles
reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn
wire WriteDataOp; // Write Data Operation (positive edge detected)
wire ReadStatusOp; // Read Status Operation (positive edge detected)
wire ScanStatusOp; // Scan Status Operation (positive edge detected)
wire StartOp; // Start Operation (start of any of the preceding operations)
wire EndOp; // End of Operation
reg InProgress; // Operation in progress
reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
reg [6:0] BitCounter; // Bit Counter
wire MdcFrame; // Frame window for limiting the Mdc
wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire LatchByte1_d2;
wire LatchByte0_d2;
reg LatchByte1_d;
reg LatchByte0_d;
reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
EndBusy_d <= #Tp 1'b0;
EndBusy <= #Tp 1'b0;
end
else
begin
EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
EndBusy <= #Tp EndBusy_d;
end
end
// Update MII RX_DATA register
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
UpdateMIIRX_DATAReg <= #Tp 0;
else
if(EndBusy & ~WCtrlDataStart_q)
UpdateMIIRX_DATAReg <= #Tp 1;
else
UpdateMIIRX_DATAReg <= #Tp 0;
end
// Generation of the delayed signals used for positive edge triggering.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlData_q1 <= #Tp 1'b0;
WCtrlData_q2 <= #Tp 1'b0;
WCtrlData_q3 <= #Tp 1'b0;
RStat_q1 <= #Tp 1'b0;
RStat_q2 <= #Tp 1'b0;
RStat_q3 <= #Tp 1'b0;
ScanStat_q1 <= #Tp 1'b0;
ScanStat_q2 <= #Tp 1'b0;
SyncStatMdcEn <= #Tp 1'b0;
end
else
begin
WCtrlData_q1 <= #Tp WCtrlData;
WCtrlData_q2 <= #Tp WCtrlData_q1;
WCtrlData_q3 <= #Tp WCtrlData_q2;
RStat_q1 <= #Tp RStat;
RStat_q2 <= #Tp RStat_q1;
RStat_q3 <= #Tp RStat_q2;
ScanStat_q1 <= #Tp ScanStat;
ScanStat_q2 <= #Tp ScanStat_q1;
if(MdcEn)
SyncStatMdcEn <= #Tp ScanStat_q2;
end
end
// Generation of the Start Commands (Write Control Data or Read Status)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart <= #Tp 1'b0;
WCtrlDataStart_q <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(EndBusy)
begin
WCtrlDataStart <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(WCtrlData_q2 & ~WCtrlData_q3)
WCtrlDataStart <= #Tp 1'b1;
if(RStat_q2 & ~RStat_q3)
RStatStart <= #Tp 1'b1;
WCtrlDataStart_q <= #Tp WCtrlDataStart;
end
end
end
// Generation of the Nvalid signal (indicates when the status is invalid)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Nvalid <= #Tp 1'b0;
else
begin
if(~InProgress_q2 & InProgress_q3)
begin
Nvalid <= #Tp 1'b0;
end
else
begin
if(ScanStat_q2 & ~SyncStatMdcEn)
Nvalid <= #Tp 1'b1;
end
end
end
// Signals used for the generation of the Operation signals (positive edge)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart_q1 <= #Tp 1'b0;
WCtrlDataStart_q2 <= #Tp 1'b0;
RStatStart_q1 <= #Tp 1'b0;
RStatStart_q2 <= #Tp 1'b0;
InProgress_q1 <= #Tp 1'b0;
InProgress_q2 <= #Tp 1'b0;
InProgress_q3 <= #Tp 1'b0;
LatchByte0_d <= #Tp 1'b0;
LatchByte1_d <= #Tp 1'b0;
LatchByte <= #Tp 2'b00;
end
else
begin
if(MdcEn)
begin
WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
RStatStart_q1 <= #Tp RStatStart;
RStatStart_q2 <= #Tp RStatStart_q1;
LatchByte[0] <= #Tp LatchByte0_d;
LatchByte[1] <= #Tp LatchByte1_d;
LatchByte0_d <= #Tp LatchByte0_d2;
LatchByte1_d <= #Tp LatchByte1_d2;
InProgress_q1 <= #Tp InProgress;
InProgress_q2 <= #Tp InProgress_q1;
InProgress_q3 <= #Tp InProgress_q2;
end
end
end
// Generation of the Operation signals
assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
// Busy
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
else
begin
if(MdcEn)
begin
if(StartOp)
begin
if(~InProgress)
WriteOp <= #Tp WriteDataOp;
InProgress <= #Tp 1'b1;
end
else
begin
if(EndOp)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
end
end
end
end
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
BitCounter[6:0] <= #Tp 7'h0;
else
begin
if(MdcEn)
begin
if(InProgress)
begin
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= #Tp 7'h21;
else
BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
end
else
BitCounter[6:0] <= #Tp 7'h0;
end
end
end
// Operation ends when the Bit Counter reaches 63
assign EndOp = BitCounter==63;
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
// Latch Byte selects which part of Read Status Data is updated from the shift register
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
// Connecting the Clock Generator Module
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
);
// Connecting the Shift Register Module
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
);
// Connecting the Output Control Module
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
.Mdo(Mdo), .MdoEn(MdoEn)
);
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_outputcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_outputcontrol.v,v $
// Revision 1.4 2002/07/09 20:11:59 mohor
// Comment removed.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
parameter Tp = 1;
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
wire SerialEn;
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= #Tp 1'b0;
MdoEn_d <= #Tp 1'b0;
MdoEn <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
MdoEn_d <= #Tp MdoEn_2d;
MdoEn <= #Tp MdoEn_d;
end
end
end
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= #Tp 1'b0;
Mdo_d <= #Tp 1'b0;
Mdo <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
Mdo_d <= #Tp ShiftedBit | Mdo_2d;
Mdo <= #Tp Mdo_d;
end
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_random.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_random.v,v $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
parameter Tp = 1;
input MTxClk;
input Reset;
input StateJam;
input StateJam_q;
input [3:0] RetryCnt;
input [15:0] NibCnt;
input [9:0] ByteCnt;
output RandomEq0;
output RandomEqByteCnt;
wire Feedback;
reg [9:0] x;
wire [9:0] Random;
reg [9:0] RandomLatched;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
x[9:0] <= #Tp 0;
else
x[9:0] <= #Tp {x[8:0], Feedback};
end
assign Feedback = ~(x[2] ^ x[9]);
assign Random [0] = x[0];
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RandomLatched <= #Tp 10'h000;
else
begin
if(StateJam & StateJam_q)
RandomLatched <= #Tp Random;
end
end
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0;
assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_register.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_register.v,v $
// Revision 1.6 2002/08/16 22:10:12 mohor
// Synchronous reset added.
//
// Revision 1.5 2002/08/16 12:33:27 mohor
// Parameter ResetValue changed to capital letters.
//
// Revision 1.4 2002/02/26 16:18:08 mohor
// Reset values are passed to registers through parameters
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
//
//
//
//
//
//
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] DataIn;
input Write;
input Clk;
input Reset;
input SyncReset;
output [WIDTH-1:0] DataOut;
reg [WIDTH-1:0] DataOut;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
DataOut<=#1 RESET_VALUE;
else
if(SyncReset)
DataOut<=#1 RESET_VALUE;
else
if(Write) // write
DataOut<=#1 DataIn;
end
endmodule // Register
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_registers.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_registers.v,v $
// Revision 1.24 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.23 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.22 2002/11/14 18:37:20 mohor
// r_Rst signal does not reset any module any more and is removed from the design.
//
// Revision 1.21 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.20 2002/09/04 18:40:25 mohor
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
// the control frames connected.
//
// Revision 1.19 2002/08/19 16:01:40 mohor
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
//
// Revision 1.18 2002/08/16 22:28:23 mohor
// Syntax error fixed.
//
// Revision 1.17 2002/08/16 22:23:03 mohor
// Syntax error fixed.
//
// Revision 1.16 2002/08/16 22:14:22 mohor
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
// changed from bit position 10 to 9.
//
// Revision 1.15 2002/08/14 18:26:37 mohor
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
//
// Revision 1.14 2002/04/22 14:03:44 mohor
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
// or not.
//
// Revision 1.13 2002/02/26 16:18:09 mohor
// Reset values are passed to registers through parameters
//
// Revision 1.12 2002/02/17 13:23:42 mohor
// Define missmatch fixed.
//
// Revision 1.11 2002/02/16 14:03:44 mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.10 2002/02/15 11:08:25 mohor
// File format fixed a bit.
//
// Revision 1.9 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.8 2002/02/12 17:01:19 mohor
// HASH0 and HASH1 registers added.
// Revision 1.7 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.6 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.5 2001/12/05 10:22:19 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.4 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
//
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
LinkFail, r_MAC, WCtrlDataStart, RStatStart,
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
StartTxDone, TxClk, RxClk, SetPauseTimer
);
parameter Tp = 1;
input [31:0] DataIn;
input [7:0] Address;
input Rw;
input Cs;
input Clk;
input Reset;
input WCtrlDataStart;
input RStatStart;
input UpdateMIIRX_DATAReg;
input [15:0] Prsd;
output [31:0] DataOut;
reg [31:0] DataOut;
output r_RecSmall;
output r_Pad;
output r_HugEn;
output r_CrcEn;
output r_DlyCrcEn;
output r_FullD;
output r_ExDfrEn;
output r_NoBckof;
output r_LoopBck;
output r_IFG;
output r_Pro;
output r_Iam;
output r_Bro;
output r_NoPre;
output r_TxEn;
output r_RxEn;
output [31:0] r_HASH0;
output [31:0] r_HASH1;
input TxB_IRQ;
input TxE_IRQ;
input RxB_IRQ;
input RxE_IRQ;
input Busy_IRQ;
output [6:0] r_IPGT;
output [6:0] r_IPGR1;
output [6:0] r_IPGR2;
output [15:0] r_MinFL;
output [15:0] r_MaxFL;
output [3:0] r_MaxRet;
output [5:0] r_CollValid;
output r_TxFlow;
output r_RxFlow;
output r_PassAll;
output r_MiiNoPre;
output [7:0] r_ClkDiv;
output r_WCtrlData;
output r_RStat;
output r_ScanStat;
output [4:0] r_RGAD;
output [4:0] r_FIAD;
output [15:0]r_CtrlData;
input NValid_stat;
input Busy_stat;
input LinkFail;
output [47:0]r_MAC;
output [7:0] r_TxBDNum;
output TX_BD_NUM_Wr;
output int_o;
output [15:0]r_TxPauseTV;
output r_TxPauseRq;
input RstTxPauseRq;
input TxCtrlEndFrm;
input StartTxDone;
input TxClk;
input RxClk;
input SetPauseTimer;
reg irq_txb;
reg irq_txe;
reg irq_rxb;
reg irq_rxe;
reg irq_busy;
reg irq_txc;
reg irq_rxc;
reg SetTxCIrq_txclk;
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
reg SetTxCIrq;
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
reg SetRxCIrq_rxclk;
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
reg SetRxCIrq;
reg ResetRxCIrq_sync1;
reg ResetRxCIrq_sync2;
reg ResetRxCIrq_sync3;
wire Write = Cs & Rw;
wire Read = Cs & ~Rw;
wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR ) & Write;
wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR ) & Write;
wire IPGT_Wr = (Address == `ETH_IPGT_ADR ) & Write;
wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR ) & Write;
wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR ) & Write;
wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR ) & Write;
wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR ) & Write;
wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR ) & Write;
wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR ) & Write;
wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR ) & Write;
wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR ) & Write;
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
wire TXCTRL_Wr = (Address == `ETH_TX_CTRL_ADR ) & Write;
wire RXCTRL_Wr = (Address == `ETH_RX_CTRL_ADR ) & Write;
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write & (DataIn<='h80);
wire [31:0] MODEROut;
wire [31:0] INT_SOURCEOut;
wire [31:0] INT_MASKOut;
wire [31:0] IPGTOut;
wire [31:0] IPGR1Out;
wire [31:0] IPGR2Out;
wire [31:0] PACKETLENOut;
wire [31:0] COLLCONFOut;
wire [31:0] CTRLMODEROut;
wire [31:0] MIIMODEROut;
wire [31:0] MIICOMMANDOut;
wire [31:0] MIIADDRESSOut;
wire [31:0] MIITX_DATAOut;
wire [31:0] MIIRX_DATAOut;
wire [31:0] MIISTATUSOut;
wire [31:0] MAC_ADDR0Out;
wire [31:0] MAC_ADDR1Out;
wire [31:0] TX_BD_NUMOut;
wire [31:0] HASH0Out;
wire [31:0] HASH1Out;
wire [31:0] TXCTRLOut;
wire [31:0] RXCTRLOut;
// MODER Register
eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF) MODER
(
.DataIn (DataIn[`ETH_MODER_WIDTH-1:0]),
.DataOut (MODEROut[`ETH_MODER_WIDTH-1:0]),
.Write (MODER_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
// INT_MASK Register
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF) INT_MASK
(
.DataIn (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
.Write (INT_MASK_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH] = 0;
// IPGT Register
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF) IPGT
(
.DataIn (DataIn[`ETH_IPGT_WIDTH-1:0]),
.DataOut (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
.Write (IPGT_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
// IPGR1 Register
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF) IPGR1
(
.DataIn (DataIn[`ETH_IPGR1_WIDTH-1:0]),
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
.Write (IPGR1_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
// IPGR2 Register
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF) IPGR2
(
.DataIn (DataIn[`ETH_IPGR2_WIDTH-1:0]),
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
.Write (IPGR2_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
// PACKETLEN Register
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
(
.DataIn (DataIn),
.DataOut (PACKETLENOut),
.Write (PACKETLEN_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// COLLCONF Register
eth_register #(6, `ETH_COLLCONF0_DEF) COLLCONF0
(
.DataIn (DataIn[5:0]),
.DataOut (COLLCONFOut[5:0]),
.Write (COLLCONF_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign COLLCONFOut[15:6] = 0;
eth_register #(4, `ETH_COLLCONF1_DEF) COLLCONF1
(
.DataIn (DataIn[19:16]),
.DataOut (COLLCONFOut[19:16]),
.Write (COLLCONF_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign COLLCONFOut[31:20] = 0;
// TX_BD_NUM Register
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
(
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
.Write (TX_BD_NUM_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
// CTRLMODER Register
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF) CTRLMODER2
(
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
.Write (CTRLMODER_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
// MIIMODER Register
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF) MIIMODER
(
.DataIn (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
.Write (MIIMODER_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
// MIICOMMAND Register
eth_register #(1, 0) MIICOMMAND0
(
.DataIn (DataIn[0]),
.DataOut (MIICOMMANDOut[0]),
.Write (MIICOMMAND_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(1, 0) MIICOMMAND1
(
.DataIn (DataIn[1]),
.DataOut (MIICOMMANDOut[1]),
.Write (MIICOMMAND_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (RStatStart)
);
eth_register #(1, 0) MIICOMMAND2
(
.DataIn (DataIn[2]),
.DataOut (MIICOMMANDOut[2]),
.Write (MIICOMMAND_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (WCtrlDataStart)
);
assign MIICOMMANDOut[31:3] = 29'h0;
// MIIADDRESSRegister
eth_register #(5, `ETH_MIIADDRESS0_DEF) MIIADDRESS0
(
.DataIn (DataIn[4:0]),
.DataOut (MIIADDRESSOut[4:0]),
.Write (MIIADDRESS_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIADDRESSOut[7:5] = 0;
eth_register #(5, `ETH_MIIADDRESS1_DEF) MIIADDRESS1
(
.DataIn (DataIn[12:8]),
.DataOut (MIIADDRESSOut[12:8]),
.Write (MIIADDRESS_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIADDRESSOut[31:13] = 0;
// MIITX_DATA Register
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
(
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
.Write (MIITX_DATA_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
// MIIRX_DATA Register
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
(
.DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
.Write (MIIRX_DATA_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
// MAC_ADDR0 Register
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF) MAC_ADDR0
(
.DataIn (DataIn),
.DataOut (MAC_ADDR0Out),
.Write (MAC_ADDR0_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// MAC_ADDR1 Register
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF) MAC_ADDR1
(
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
.Write (MAC_ADDR1_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
// RXHASH0 Register
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF) RXHASH0
(
.DataIn (DataIn),
.DataOut (HASH0Out),
.Write (HASH0_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// RXHASH1 Register
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF) RXHASH1
(
.DataIn (DataIn),
.DataOut (HASH1Out),
.Write (HASH1_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// TXCTRL Register
eth_register #((`ETH_TX_CTRL_WIDTH-1), {(`ETH_TX_CTRL_WIDTH-1){1'b0}}) TXCTRL0
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH-2:0]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH-2:0]),
.Write (TXCTRL_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(1, 1'b0) TXCTRL1 // Request bit is synchronously reset
(
.DataIn (DataIn[16]),
.DataOut (TXCTRLOut[16]),
.Write (TXCTRL_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (RstTxPauseRq)
);
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH] = 0;
// RXCTRL Register
eth_register #(`ETH_RX_CTRL_WIDTH, `ETH_RX_CTRL_DEF) RXCTRL
(
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH-1:0]),
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH-1:0]),
.Write (RXCTRL_Wr),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH] = 0;
// Reading data from registers
always @ (Address or Read or MODEROut or INT_SOURCEOut or
INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
HASH0Out or HASH1Out or TXCTRLOut or RXCTRLOut
)
begin
if(Read) // read
begin
case(Address)
`ETH_MODER_ADR : DataOut<=MODEROut;
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
`ETH_IPGT_ADR : DataOut<=IPGTOut;
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
`ETH_HASH0_ADR : DataOut<=HASH0Out;
`ETH_HASH1_ADR : DataOut<=HASH1Out;
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
`ETH_RX_CTRL_ADR : DataOut<=RXCTRLOut;
default: DataOut<=32'h0;
endcase
end
else
DataOut<=32'h0;
end
assign r_RecSmall = MODEROut[16];
assign r_Pad = MODEROut[15];
assign r_HugEn = MODEROut[14];
assign r_CrcEn = MODEROut[13];
assign r_DlyCrcEn = MODEROut[12];
// assign r_Rst = MODEROut[11]; This signal is not used any more
assign r_FullD = MODEROut[10];
assign r_ExDfrEn = MODEROut[9];
assign r_NoBckof = MODEROut[8];
assign r_LoopBck = MODEROut[7];
assign r_IFG = MODEROut[6];
assign r_Pro = MODEROut[5];
assign r_Iam = MODEROut[4];
assign r_Bro = MODEROut[3];
assign r_NoPre = MODEROut[2];
assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD.
assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD.
assign r_IPGT[6:0] = IPGTOut[6:0];
assign r_IPGR1[6:0] = IPGR1Out[6:0];
assign r_IPGR2[6:0] = IPGR2Out[6:0];
assign r_MinFL[15:0] = PACKETLENOut[31:16];
assign r_MaxFL[15:0] = PACKETLENOut[15:0];
assign r_MaxRet[3:0] = COLLCONFOut[19:16];
assign r_CollValid[5:0] = COLLCONFOut[5:0];
assign r_TxFlow = CTRLMODEROut[2];
assign r_RxFlow = CTRLMODEROut[1];
assign r_PassAll = CTRLMODEROut[0];
assign r_MiiNoPre = MIIMODEROut[8];
assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
assign r_WCtrlData = MIICOMMANDOut[2];
assign r_RStat = MIICOMMANDOut[1];
assign r_ScanStat = MIICOMMANDOut[0];
assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
assign MIISTATUSOut[2] = NValid_stat ;
assign MIISTATUSOut[1] = Busy_stat ;
assign MIISTATUSOut[0] = LinkFail ;
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
assign r_HASH1[31:0] = HASH1Out;
assign r_HASH0[31:0] = HASH0Out;
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
assign r_TxPauseTV[15:0] = TXCTRLOut[15:0];
assign r_TxPauseRq = TXCTRLOut[16];
// Synchronizing TxC Interrupt
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
SetTxCIrq_txclk <=#Tp 1'b0;
else
if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
SetTxCIrq_txclk <=#Tp 1'b1;
else
if(ResetTxCIrq_sync2)
SetTxCIrq_txclk <=#Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync1 <=#Tp 1'b0;
else
SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync2 <=#Tp 1'b0;
else
SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync3 <=#Tp 1'b0;
else
SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq <=#Tp 1'b0;
else
SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
end
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
ResetTxCIrq_sync1 <=#Tp 1'b0;
else
ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
end
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
ResetTxCIrq_sync2 <=#Tp 1'b0;
else
ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
end
// Synchronizing RxC Interrupt
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
SetRxCIrq_rxclk <=#Tp 1'b0;
else
if(SetPauseTimer & r_RxFlow)
SetRxCIrq_rxclk <=#Tp 1'b1;
else
if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
SetRxCIrq_rxclk <=#Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync1 <=#Tp 1'b0;
else
SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync2 <=#Tp 1'b0;
else
SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync3 <=#Tp 1'b0;
else
SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq <=#Tp 1'b0;
else
SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync1 <=#Tp 1'b0;
else
ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync2 <=#Tp 1'b0;
else
ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync3 <=#Tp 1'b0;
else
ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
end
// Interrupt generation
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txb <= 1'b0;
else
if(TxB_IRQ)
irq_txb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[0])
irq_txb <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txe <= 1'b0;
else
if(TxE_IRQ)
irq_txe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[1])
irq_txe <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxb <= 1'b0;
else
if(RxB_IRQ)
irq_rxb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[2])
irq_rxb <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxe <= 1'b0;
else
if(RxE_IRQ)
irq_rxe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[3])
irq_rxe <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_busy <= 1'b0;
else
if(Busy_IRQ)
irq_busy <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[4])
irq_busy <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txc <= 1'b0;
else
if(SetTxCIrq)
irq_txc <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[5])
irq_txc <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxc <= 1'b0;
else
if(SetRxCIrq)
irq_rxc <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[6])
irq_rxc <= #Tp 1'b0;
end
// Generating interrupt signal
assign int_o = irq_txb & INT_MASKOut[0] |
irq_txe & INT_MASKOut[1] |
irq_rxb & INT_MASKOut[2] |
irq_rxe & INT_MASKOut[3] |
irq_busy & INT_MASKOut[4] |
irq_txc & INT_MASKOut[5] |
irq_rxc & INT_MASKOut[6] ;
// For reading interrupt status
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxaddrcheck.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/cores/ethmac/ ////
//// ////
//// Author(s): ////
//// - Bill Dittenhofer ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxaddrcheck.v,v $
// Revision 1.9 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.8 2002/11/19 17:34:52 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.7 2002/09/04 18:41:06 mohor
// Bug when last byte of destination address was not checked fixed.
//
// Revision 1.6 2002/03/20 15:14:11 mohor
// When in promiscous mode some frames were not received correctly. Fixed.
//
// Revision 1.5 2002/03/02 21:06:32 mohor
// Log info was missing.
//
//
// Revision 1.1 2002/02/08 12:51:54 ditt
// Initial release of the ethernet addresscheck module.
//
//
//
//
//
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort, AddressMiss, PassAll,
ControlFrmAddressOK
);
parameter Tp = 1;
input MRxClk;
input Reset;
input [7:0] RxData;
input Broadcast;
input r_Bro;
input r_Pro;
input ByteCntEq2;
input ByteCntEq3;
input ByteCntEq4;
input ByteCntEq5;
input ByteCntEq6;
input ByteCntEq7;
input [31:0] HASH0;
input [31:0] HASH1;
input [5:0] CrcHash;
input CrcHashGood;
input Multicast;
input [47:0] MAC;
input [1:0] StateData;
input RxEndFrm;
input PassAll;
input ControlFrmAddressOK;
output RxAbort;
output AddressMiss;
wire BroadcastOK;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire RxAddressInvalid;
wire RxCheckEn;
wire HashBit;
wire [31:0] IntHash;
reg [7:0] ByteHash;
reg MulticastOK;
reg UnicastOK;
reg RxAbort;
reg AddressMiss;
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
assign BroadcastOK = Broadcast & ~r_Bro;
assign RxCheckEn = | StateData;
// Address Error Reported at end of address cycle
// RxAbort clears after one cycle
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbort <= #Tp 1'b0;
else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
RxAbort <= #Tp 1'b1;
else
RxAbort <= #Tp 1'b0;
end
// This ff holds the "Address Miss" information that is written to the RX BD status.
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
AddressMiss <= #Tp 1'b0;
else if(ByteCntEq7 & RxCheckEn)
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
MulticastOK <= #Tp 1'b0;
else if(RxEndFrm | RxAbort)
MulticastOK <= #Tp 1'b0;
else if(CrcHashGood & Multicast)
MulticastOK <= #Tp HashBit;
end
// Address Detection (unicast)
// start with ByteCntEq2 due to delay of addres from RxData
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
UnicastOK <= #Tp 1'b0;
else
if(RxCheckEn & ByteCntEq2)
UnicastOK <= #Tp RxData[7:0] == MAC[47:40];
else
if(RxCheckEn & ByteCntEq3)
UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq4)
UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq5)
UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq6)
UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq7)
UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0]) & UnicastOK;
else
if(RxEndFrm | RxAbort)
UnicastOK <= #Tp 1'b0;
end
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
always@(CrcHash or IntHash)
begin
case(CrcHash[4:3])
2'b00: ByteHash = IntHash[7:0];
2'b01: ByteHash = IntHash[15:8];
2'b10: ByteHash = IntHash[23:16];
2'b11: ByteHash = IntHash[31:24];
endcase
end
assign HashBit = ByteHash[CrcHash[2:0]];
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxcounters.v,v $
// Revision 1.5 2002/02/15 11:13:29 mohor
// Format of the file changed a bit.
//
// Revision 1.4 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
//
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCnt
);
parameter Tp = 1;
input MRxClk;
input Reset;
input MRxDV;
input StateSFD;
input [1:0] StateData;
input MRxDEqD;
input StateIdle;
input StateDrop;
input DlyCrcEn;
input StatePreamble;
input Transmitting;
input HugEn;
input [15:0] MaxFL;
input r_IFG;
output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
output [3:0] DlyCrcCnt; // Delayed CRC counter
output ByteCntEq0; // Byte counter = 0
output ByteCntEq1; // Byte counter = 1
output ByteCntEq2; // Byte counter = 2
output ByteCntEq3; // Byte counter = 3
output ByteCntEq4; // Byte counter = 4
output ByteCntEq5; // Byte counter = 5
output ByteCntEq6; // Byte counter = 6
output ByteCntEq7; // Byte counter = 7
output ByteCntGreat2; // Byte counter > 2
output ByteCntSmall7; // Byte counter < 7
output ByteCntMaxFrame; // Byte counter = MaxFL
output [15:0] ByteCnt; // Byte counter
wire ResetByteCounter;
wire IncrementByteCounter;
wire ResetIFGCounter;
wire IncrementIFGCounter;
wire ByteCntMax;
reg [15:0] ByteCnt;
reg [3:0] DlyCrcCnt;
reg [4:0] IFGCounter;
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
(StatePreamble | StateSFD | StateIdle & ~Transmitting |
StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 11'h0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= #Tp 11'h0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign ByteCntEq0 = ByteCnt == 16'h0;
assign ByteCntEq1 = ByteCnt == 16'h1;
assign ByteCntEq2 = ByteCnt == 16'h2;
assign ByteCntEq3 = ByteCnt == 16'h3;
assign ByteCntEq4 = ByteCnt == 16'h4;
assign ByteCntEq5 = ByteCnt == 16'h5;
assign ByteCntEq6 = ByteCnt == 16'h6;
assign ByteCntEq7 = ByteCnt == 16'h7;
assign ByteCntGreat2 = ByteCnt > 16'h2;
assign ByteCntSmall7 = ByteCnt < 16'h7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
IFGCounter[4:0] <= #Tp 5'h0;
else
begin
if(ResetIFGCounter)
IFGCounter[4:0] <= #Tp 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
end
end
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt[3:0] <= #Tp 4'h0;
else
begin
if(DlyCrcCnt[3:0] == 4'h9)
DlyCrcCnt[3:0] <= #Tp 4'h0;
else
if(DlyCrcEn & StateSFD)
DlyCrcCnt[3:0] <= #Tp 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxstatem.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxstatem.v,v $
// Revision 1.6 2002/11/13 22:28:26 tadejm
// StartIdle state changed (not important the size of the packet).
// StartData1 activates only while ByteCnt is smaller than the MaxFrame.
//
// Revision 1.5 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.4 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.2 2001/07/03 12:55:41 mohor
// Minor changes because of the synthesys warnings.
//
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
StateDrop
);
parameter Tp = 1;
input MRxClk;
input Reset;
input MRxDV;
input ByteCntEq0;
input ByteCntGreat2;
input MRxDEq5;
input Transmitting;
input MRxDEqD;
input IFGCounterEq24;
input ByteCntMaxFrame;
output [1:0] StateData;
output StateIdle;
output StateDrop;
output StatePreamble;
output StateSFD;
reg StateData0;
reg StateData1;
reg StateIdle;
reg StateDrop;
reg StatePreamble;
reg StateSFD;
wire StartIdle;
wire StartDrop;
wire StartData0;
wire StartData1;
wire StartPreamble;
wire StartSFD;
// Defining the next state
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
| StateData0 & ByteCntMaxFrame
);
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= #Tp 1'b0;
StateDrop <= #Tp 1'b1;
StatePreamble <= #Tp 1'b0;
StateSFD <= #Tp 1'b0;
StateData0 <= #Tp 1'b0;
StateData1 <= #Tp 1'b0;
end
else
begin
if(StartPreamble | StartSFD | StartDrop)
StateIdle <= #Tp 1'b0;
else
if(StartIdle)
StateIdle <= #Tp 1'b1;
if(StartIdle)
StateDrop <= #Tp 1'b0;
else
if(StartDrop)
StateDrop <= #Tp 1'b1;
if(StartSFD | StartIdle | StartDrop)
StatePreamble <= #Tp 1'b0;
else
if(StartPreamble)
StatePreamble <= #Tp 1'b1;
if(StartPreamble | StartIdle | StartData0 | StartDrop)
StateSFD <= #Tp 1'b0;
else
if(StartSFD)
StateSFD <= #Tp 1'b1;
if(StartIdle | StartData1 | StartDrop)
StateData0 <= #Tp 1'b0;
else
if(StartData0)
StateData0 <= #Tp 1'b1;
if(StartIdle | StartData0 | StartDrop)
StateData1 <= #Tp 1'b0;
else
if(StartData1)
StateData1 <= #Tp 1'b1;
end
end
assign StateData[1:0] = {StateData1, StateData0};
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxethmac.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxethmac.v,v $
// Revision 1.10 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.9 2002/11/19 17:35:35 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.8 2002/02/16 07:15:27 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.7 2002/02/15 13:44:28 mohor
// RxAbort is an output. No need to have is declared as wire.
//
// Revision 1.6 2002/02/15 11:17:48 mohor
// File format changed.
//
// Revision 1.5 2002/02/14 20:48:43 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
);
parameter Tp = 1;
input MRxClk;
input MRxDV;
input [3:0] MRxD;
input Transmitting;
input HugEn;
input DlyCrcEn;
input [15:0] MaxFL;
input r_IFG;
input Reset;
input [47:0] MAC; // Station Address
input r_Bro; // broadcast disable
input r_Pro; // promiscuous enable
input [31:0] r_HASH0; // lower 4 bytes Hash Table
input [31:0] r_HASH1; // upper 4 bytes Hash Table
input PassAll;
input ControlFrmAddressOK;
output [7:0] RxData;
output RxValid;
output RxStartFrm;
output RxEndFrm;
output [15:0] ByteCnt;
output ByteCntEq0;
output ByteCntGreat2;
output ByteCntMaxFrame;
output CrcError;
output StateIdle;
output StatePreamble;
output StateSFD;
output [1:0] StateData;
output RxAbort;
output AddressMiss;
reg [7:0] RxData;
reg RxValid;
reg RxStartFrm;
reg RxEndFrm;
reg Broadcast;
reg Multicast;
reg [8:0] CrcHash;
reg CrcHashGood;
reg DelayData;
reg [3:0] LatchedNibble;
reg [7:0] LatchedByte;
reg [7:0] RxData_d;
reg RxValid_d;
reg RxStartFrm_d;
reg RxEndFrm_d;
wire MRxDEqD;
wire MRxDEq5;
wire StateDrop;
wire ByteCntEq1;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire ByteCntEq6;
wire ByteCntEq7;
wire ByteCntSmall7;
wire [31:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire GenerateRxValid;
wire GenerateRxStartFrm;
wire GenerateRxEndFrm;
wire DribbleRxEndFrm;
wire [3:0] DlyCrcCnt;
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
// Rx State Machine module
eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
.StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
.StateSFD(StateSFD), .StateDrop(StateDrop)
);
// Rx Counters module
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
.ByteCnt(ByteCnt)
);
// Rx Address Check
eth_rxaddrcheck rxaddrcheck1
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0), .HASH1(r_HASH1),
.CrcHash(CrcHash[5:0]), .CrcHashGood(CrcHashGood), .StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
);
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
// Connecting module Crc
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Latching CRC for use in the hash table
always @ (posedge MRxClk)
begin
CrcHashGood <= #Tp StateData[0] & ByteCntEq6;
end
always @ (posedge MRxClk)
begin
if(Reset | StateIdle)
CrcHash[8:0] <= #Tp 9'h0;
else
if(StateData[0] & ByteCntEq6)
CrcHash[8:0] <= #Tp Crc[31:23];
end
// Output byte stream
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxData_d[7:0] <= #Tp 8'h0;
DelayData <= #Tp 1'b0;
LatchedNibble[3:0] <= #Tp 4'h0;
LatchedByte[7:0] <= #Tp 8'h0;
RxData[7:0] <= #Tp 8'h0;
end
else
begin
LatchedNibble[3:0] <= #Tp MRxD[3:0]; // Latched nibble
LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedNibble[3:0]}; // Latched byte
DelayData <= #Tp StateData[0];
if(GenerateRxValid)
RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
else
if(~DelayData)
RxData_d[7:0] <= #Tp 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
RxData[7:0] <= #Tp RxData_d[7:0]; // Output data byte
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Broadcast <= #Tp 1'b0;
else
begin
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
Broadcast <= #Tp 1'b0;
else
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
Broadcast <= #Tp 1'b1;
else
if(RxAbort | RxEndFrm)
Broadcast <= #Tp 1'b0;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Multicast <= #Tp 1'b0;
else
begin
if(Reset)
Multicast <= #Tp 1'b0;
else
if(StateData[0] & ByteCntEq1 & LatchedByte == 8'h01)
Multicast <= #Tp 1'b1;
else if(RxAbort | RxEndFrm)
Multicast <= #Tp 1'b0;
end
end
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid_d <= #Tp 1'b0;
RxValid <= #Tp 1'b0;
end
else
begin
RxValid_d <= #Tp GenerateRxValid;
RxValid <= #Tp RxValid_d;
end
end
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStartFrm_d <= #Tp 1'b0;
RxStartFrm <= #Tp 1'b0;
end
else
begin
RxStartFrm_d <= #Tp GenerateRxStartFrm;
RxStartFrm <= #Tp RxStartFrm_d;
end
end
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxEndFrm_d <= #Tp 1'b0;
RxEndFrm <= #Tp 1'b0;
end
else
begin
RxEndFrm_d <= #Tp GenerateRxEndFrm;
RxEndFrm <= #Tp RxEndFrm_d | DribbleRxEndFrm;
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_shiftreg.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_shiftreg.v,v $
// Revision 1.5 2002/08/14 18:16:59 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.4 2002/03/02 21:06:01 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
LatchByte, ShiftedBit, Prsd, LinkFail);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
input Mdi; // MII input data
input [4:0] Fiad; // PHY address
input [4:0] Rgad; // Register address (within the selected PHY)
input [15:0]CtrlData; // Control data (data to be written to the PHY)
input WriteOp; // The current operation is a PHY register write operation
input [3:0] ByteSelect; // Byte select
input [1:0] LatchByte; // Byte select for latching (read operation)
output ShiftedBit; // Bit shifted out of the shift register
output[15:0]Prsd; // Read Status Data (data read from the PHY)
output LinkFail; // Link Integrity Signal
reg [7:0] ShiftReg; // Shift register for shifting the data in and out
reg [15:0]Prsd;
reg LinkFail;
// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
ShiftReg[7:0] <= #Tp 8'h0;
Prsd[15:0] <= #Tp 16'h0;
LinkFail <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
if(|ByteSelect)
begin
case (ByteSelect[3:0])
4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
default : ShiftReg[7:0] <= #Tp 8'h0;
endcase
end
else
begin
ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(LatchByte[0])
begin
Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(Rgad == 5'h01)
LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
end
else
begin
if(LatchByte[1])
Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
end
end
end
end
end
assign ShiftedBit = ShiftReg[7];
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_spram_256x32.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_spram_256x32.v,v $
// Revision 1.4 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.3 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.2 2002/09/23 18:24:31 mohor
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
//
// Revision 1.1 2002/07/23 16:36:09 mohor
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
//
//
//
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
`endif
);
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock, rising edge
input rst; // Reset, active high
input ce; // Chip enable input, active high
input we; // Write enable input, active high
input oe; // Output enable input, active high
input [7:0] addr; // address bus inputs
input [31:0] di; // input data bus
output [31:0] do; // output data bus
`ifdef ETH_BIST
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
`endif
`ifdef ETH_XILINX_RAMB4
RAMB4_S16 ram0
(
.DO (do[15:0]),
.ADDR (addr),
.DI (di[15:0]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);
RAMB4_S16 ram1
(
.DO (do[31:16]),
.ADDR (addr),
.DI (di[31:16]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);
`else // !ETH_XILINX_RAMB4
`ifdef ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_BIST
vs_hdsp_256x32_bist ram0_bist
`else
vs_hdsp_256x32 ram0
`endif
(
.CK (clk),
.CEN (!ce),
.WEN (!we),
.OEN (!oe),
.ADR (addr),
.DI (di),
.DOUT (do)
`ifdef ETH_BIST
,
// debug chain signals
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
`endif
);
`else // !ETH_VIRTUAL_SILICON_RAM
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [31:0] mem [255:0]; // RAM content
wire [31:0] q; // RAM output
reg [7:0] raddr; // RAM read address
//
// Data output drivers
//
assign do = (oe & ce) ? q : {32{1'bz}};
//
// RAM read and write
//
// read operation
always@(posedge clk)
if (ce) // && !we)
raddr <= #1 addr; // read address needs to be registered to read clock
assign #1 q = rst ? {32{1'b0}} : mem[raddr];
// write operation
always@(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
task print_ram;
input [7:0] start;
input [7:0] finish;
integer rnum;
begin
for (rnum=start;rnum<=finish;rnum=rnum+1)
$display("Addr %h = %h",rnum,mem[rnum]);
end
endtask
`endif // !ETH_VIRTUAL_SILICON_RAM
`endif // !ETH_XILINX_RAMB4
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txcounters.v,v $
// Revision 1.5 2002/04/22 14:54:14 mohor
// FCS should not be included in NibbleMinFl.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.4 2001/06/27 21:27:45 mohor
// Few typos fixed.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
);
parameter Tp = 1;
input MTxClk; // Tx clock
input Reset; // Reset
input StatePreamble; // Preamble state
input StateIPG; // IPG state
input [1:0] StateData; // Data state
input StatePAD; // PAD state
input StateFCS; // FCS state
input StateJam; // Jam state
input StateBackOff; // Backoff state
input StateDefer; // Defer state
input StateIdle; // Idle state
input StateSFD; // SFD state
input StartDefer; // Defer state will be activated in next clock
input StartIPG; // IPG state will be activated in next clock
input StartFCS; // FCS state will be activated in next clock
input StartJam; // Jam state will be activated in next clock
input StartBackoff; // Backoff state will be activated in next clock
input TxStartFrm; // Tx start frame
input [15:0] MinFL; // Minimum frame length (in bytes)
input [15:0] MaxFL; // Miximum frame length (in bytes)
input HugEn; // Pakets bigger then MaxFL enabled
input ExDfrEn; // Excessive deferral enabled
input PacketFinished_q;
input DlyCrcEn; // Delayed CRC enabled
output [15:0] ByteCnt; // Byte counter
output [15:0] NibCnt; // Nibble counter
output ExcessiveDefer; // Excessive Deferral occuring
output NibCntEq7; // Nibble counter is equal to 7
output NibCntEq15; // Nibble counter is equal to 15
output MaxFrame; // Maximum frame occured
output NibbleMinFl; // Nibble counter is greater than the minimum frame length
output [2:0] DlyCrcCnt; // Delayed CRC Count
wire ExcessiveDeferCnt;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ByteCntMax;
reg [15:0] NibCnt;
reg [15:0] ByteCnt;
reg [2:0] DlyCrcCnt;
assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) & ~|DlyCrcCnt[2:0] | StatePAD
| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
// Nibble Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= #Tp 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= #Tp 16'h0;
else
if(IncrementNibCnt)
NibCnt <= #Tp NibCnt + 1'b1;
end
end
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
assign IncrementByteCnt = StateData[1] & ~ByteCntMax & ~|DlyCrcCnt[2:0]
| StateBackOff & (&NibCnt[6:0])
| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
// Transmit Byte Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 16'h0;
else
begin
if(ResetByteCnt)
ByteCnt[15:0] <= #Tp 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
assign ByteCntMax = &ByteCnt[15:0];
// Delayed CRC counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt <= #Tp 3'h0;
else
begin
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
DlyCrcCnt <= #Tp 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txethmac.v ////
/// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txethmac.v,v $
// Revision 1.8 2003/01/30 13:33:24 mohor
// When padding was enabled and crc disabled, frame was not ended correctly.
//
// Revision 1.7 2002/02/26 16:24:01 mohor
// RetryCntLatched was unused and removed from design
//
// Revision 1.6 2002/02/22 12:56:35 mohor
// Retry is not activated when a Tx Underrun occured
//
// Revision 1.5 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:08 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:58 mohor
// TxEthMAC initial release.
//
//
//
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
LateCollision, DeferIndication, StatePreamble, StateData
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input Reset; // Reset
input TxStartFrm; // Transmit packet start frame
input TxEndFrm; // Transmit packet end frame
input TxUnderRun; // Transmit packet under-run
input [7:0] TxData; // Transmit packet data byte
input CarrierSense; // Carrier sense (synchronized)
input Collision; // Collision (synchronized)
input Pad; // Pad enable (from register)
input CrcEn; // Crc enable (from register)
input FullD; // Full duplex (from register)
input HugEn; // Huge packets enable (from register)
input DlyCrcEn; // Delayed Crc enabled (from register)
input [15:0] MinFL; // Minimum frame length (from register)
input [15:0] MaxFL; // Maximum frame length (from register)
input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
input [5:0] CollValid; // Valid collision window (from register)
input [3:0] MaxRet; // Maximum retry number (from register)
input NoBckof; // No backoff (from register)
input ExDfrEn; // Excessive defferal enable (from register)
output [3:0] MTxD; // Transmit nibble (to PHY)
output MTxEn; // Transmit enable (to PHY)
output MTxErr; // Transmit error (to PHY)
output TxDone; // Transmit packet done (to RISC)
output TxRetry; // Transmit packet retry (to RISC)
output TxAbort; // Transmit packet abort (to RISC)
output TxUsedData; // Transmit packet used data (to RISC)
output WillTransmit; // Will transmit (to RxEthMAC)
output ResetCollision; // Reset Collision (for synchronizing collision)
output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
output StartTxDone;
output StartTxAbort;
output MaxCollisionOccured;
output LateCollision;
output DeferIndication;
output StatePreamble;
output [1:0] StateData;
reg [3:0] MTxD;
reg MTxEn;
reg MTxErr;
reg TxDone;
reg TxRetry;
reg TxAbort;
reg TxUsedData;
reg WillTransmit;
reg ColWindow;
reg StopExcessiveDeferOccured;
reg [3:0] RetryCnt;
reg [3:0] MTxD_d;
reg StatusLatch;
reg PacketFinished_q;
reg PacketFinished;
wire ExcessiveDeferOccured;
wire StartIPG;
wire StartPreamble;
wire [1:0] StartData;
wire StartFCS;
wire StartJam;
wire StartDefer;
wire StartBackoff;
wire StateDefer;
wire StateIPG;
wire StateIdle;
wire StatePAD;
wire StateFCS;
wire StateJam;
wire StateBackOff;
wire StateSFD;
wire StartTxRetry;
wire UnderRun;
wire TooBig;
wire [31:0] Crc;
wire CrcError;
wire [2:0] DlyCrcCnt;
wire [15:0] NibCnt;
wire NibCntEq7;
wire NibCntEq15;
wire NibbleMinFl;
wire ExcessiveDefer;
wire [15:0] ByteCnt;
wire MaxFrame;
wire RetryMax;
wire RandomEq0;
wire RandomEqByteCnt;
wire PacketFinished_d;
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
assign StateSFD = StatePreamble & NibCntEq15;
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
// StopExcessiveDeferOccured
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
if(ExcessiveDeferOccured)
StopExcessiveDeferOccured <= #Tp 1'b1;
end
end
// Collision Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ColWindow <= #Tp 1'b1;
else
begin
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
ColWindow <= #Tp 1'b0;
else
if(StateIdle | StateIPG)
ColWindow <= #Tp 1'b1;
end
end
// Start Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StatusLatch <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StatusLatch <= #Tp 1'b0;
else
if(ExcessiveDeferOccured | StateIdle)
StatusLatch <= #Tp 1'b1;
end
end
// Transmit packet used data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUsedData <= #Tp 1'b0;
else
TxUsedData <= #Tp |StartData;
end
// Transmit packet done
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDone <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxDone <= #Tp 1'b0;
else
if(StartTxDone)
TxDone <= #Tp 1'b1;
end
end
// Transmit packet retry
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxRetry <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxRetry <= #Tp 1'b0;
else
if(StartTxRetry)
TxRetry <= #Tp 1'b1;
end
end
// Transmit packet abort
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxAbort <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
TxAbort <= #Tp 1'b0;
else
if(StartTxAbort)
TxAbort <= #Tp 1'b1;
end
end
// Retry counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCnt[3:0] <= #Tp 4'h0;
else
begin
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
RetryCnt[3:0] <= #Tp 4'h0;
else
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
end
end
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
// Transmit nibble
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
Crc or NibCnt or NibCntEq15)
begin
if(StateData[0])
MTxD_d[3:0] = TxData[3:0]; // Lower nibble
else
if(StateData[1])
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
else
if(StateFCS)
MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
else
if(StateJam)
MTxD_d[3:0] = 4'h9; // Jam pattern
else
if(StatePreamble)
if(NibCntEq15)
MTxD_d[3:0] = 4'hd; // SFD
else
MTxD_d[3:0] = 4'h5; // Preamble
else
MTxD_d[3:0] = 4'h0;
end
// Transmit Enable
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxEn <= #Tp 1'b0;
else
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
// Transmit nibble
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxD[3:0] <= #Tp 4'h0;
else
MTxD[3:0] <= #Tp MTxD_d[3:0];
end
// Transmit error
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxErr <= #Tp 1'b0;
else
MTxErr <= #Tp TooBig | UnderRun;
end
// WillTransmit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
WillTransmit <= #Tp 1'b0;
else
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
// Packet finished
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
PacketFinished <= #Tp 1'b0;
PacketFinished_q <= #Tp 1'b0;
end
else
begin
PacketFinished <= #Tp PacketFinished_d;
PacketFinished_q <= #Tp PacketFinished;
end
end
// Connecting module Counters
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
.DlyCrcCnt(DlyCrcCnt)
);
// Connecting module StateM
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
);
wire Enable_Crc;
wire [3:0] Data_Crc;
wire Initialize_Crc;
assign Enable_Crc = ~StateFCS;
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
// Connecting module Crc
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Connecting module Random
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txstatem.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txstatem.v,v $
// Revision 1.6 2003/01/30 13:29:08 tadejm
// Defer indication changed.
//
// Revision 1.5 2002/10/30 12:54:50 mohor
// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
);
parameter Tp = 1;
input MTxClk;
input Reset;
input ExcessiveDefer;
input CarrierSense;
input [6:0] NibCnt;
input [6:0] IPGT;
input [6:0] IPGR1;
input [6:0] IPGR2;
input FullD;
input TxStartFrm;
input TxEndFrm;
input TxUnderRun;
input Collision;
input UnderRun;
input StartTxDone;
input TooBig;
input NibCntEq7;
input NibCntEq15;
input MaxFrame;
input Pad;
input CrcEn;
input NibbleMinFl;
input RandomEq0;
input ColWindow;
input RetryMax;
input NoBckof;
input RandomEqByteCnt;
output StateIdle; // Idle state
output StateIPG; // IPG state
output StatePreamble; // Preamble state
output [1:0] StateData; // Data state
output StatePAD; // PAD state
output StateFCS; // FCS state
output StateJam; // Jam state
output StateJam_q; // Delayed Jam state
output StateBackOff; // Backoff state
output StateDefer; // Defer state
output StartFCS; // FCS state will be activated in next clock
output StartJam; // Jam state will be activated in next clock
output StartBackoff; // Backoff state will be activated in next clock
output StartDefer; // Defer state will be activated in next clock
output DeferIndication;
output StartPreamble; // Preamble state will be activated in next clock
output [1:0] StartData; // Data state will be activated in next clock
output StartIPG; // IPG state will be activated in next clock
wire StartIdle; // Idle state will be activated in next clock
wire StartPAD; // PAD state will be activated in next clock
reg StateIdle;
reg StateIPG;
reg StatePreamble;
reg [1:0] StateData;
reg StatePAD;
reg StateFCS;
reg StateJam;
reg StateJam_q;
reg StateBackOff;
reg StateDefer;
reg Rule1;
// Defining the next state
assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
| ~Collision & StatePAD & NibbleMinFl & CrcEn;
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
| StateIdle & CarrierSense
| StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
| StateBackOff & (TxUnderRun | RandomEqByteCnt)
| StartTxDone | TooBig;
assign DeferIndication = StateIdle & CarrierSense;
// Tx State Machine
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
StateIPG <= #Tp 1'b0;
StateIdle <= #Tp 1'b0;
StatePreamble <= #Tp 1'b0;
StateData[1:0] <= #Tp 2'b0;
StatePAD <= #Tp 1'b0;
StateFCS <= #Tp 1'b0;
StateJam <= #Tp 1'b0;
StateJam_q <= #Tp 1'b0;
StateBackOff <= #Tp 1'b0;
StateDefer <= #Tp 1'b1;
end
else
begin
StateData[1:0] <= #Tp StartData[1:0];
StateJam_q <= #Tp StateJam;
if(StartDefer | StartIdle)
StateIPG <= #Tp 1'b0;
else
if(StartIPG)
StateIPG <= #Tp 1'b1;
if(StartDefer | StartPreamble)
StateIdle <= #Tp 1'b0;
else
if(StartIdle)
StateIdle <= #Tp 1'b1;
if(StartData[0] | StartJam)
StatePreamble <= #Tp 1'b0;
else
if(StartPreamble)
StatePreamble <= #Tp 1'b1;
if(StartFCS | StartJam)
StatePAD <= #Tp 1'b0;
else
if(StartPAD)
StatePAD <= #Tp 1'b1;
if(StartJam | StartDefer)
StateFCS <= #Tp 1'b0;
else
if(StartFCS)
StateFCS <= #Tp 1'b1;
if(StartBackoff | StartDefer)
StateJam <= #Tp 1'b0;
else
if(StartJam)
StateJam <= #Tp 1'b1;
if(StartDefer)
StateBackOff <= #Tp 1'b0;
else
if(StartBackoff)
StateBackOff <= #Tp 1'b1;
if(StartIPG)
StateDefer <= #Tp 1'b0;
else
if(StartDefer)
StateDefer <= #Tp 1'b1;
end
end
// This sections defines which interpack gap rule to use
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Rule1 <= #Tp 1'b0;
else
begin
if(StateIdle | StateBackOff)
Rule1 <= #Tp 1'b0;
else
if(StatePreamble | FullD)
Rule1 <= #Tp 1'b1;
end
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_wishbone.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_wishbone.v,v $
// Revision 1.52 2003/01/30 14:51:31 mohor
// Reset has priority in some flipflops.
//
// Revision 1.51 2003/01/30 13:36:22 mohor
// A new bug (entered with previous update) fixed. When abort occured sometimes
// data transmission was blocked.
//
// Revision 1.50 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.49 2003/01/21 12:09:40 mohor
// When receiving normal data frame and RxFlow control was switched on, RXB
// interrupt was not set.
//
// Revision 1.48 2003/01/20 12:05:26 mohor
// When in full duplex, transmit was sometimes blocked. Fixed.
//
// Revision 1.47 2002/11/22 13:26:21 mohor
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
// anywhere. Removed.
//
// Revision 1.46 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.45 2002/11/19 17:33:34 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.44 2002/11/13 22:21:40 tadejm
// RxError is not generated when small frame reception is enabled and small
// frames are received.
//
// Revision 1.43 2002/10/18 20:53:34 mohor
// case changed to casex.
//
// Revision 1.42 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.41 2002/10/18 15:42:09 tadejm
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
//
// Revision 1.40 2002/10/14 16:07:02 mohor
// TxStatus is written after last access to the TX fifo is finished (in case of abort
// or retry). TxDone is fixed.
//
// Revision 1.39 2002/10/11 15:35:20 mohor
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
// TxDone and TxRetry are generated after the current WISHBONE access is
// finished.
//
// Revision 1.38 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.37 2002/09/11 14:18:46 mohor
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
//
// Revision 1.36 2002/09/10 13:48:46 mohor
// Reception is possible after RxPointer is read and not after BD is read. For
// that reason RxBDReady is changed to RxReady.
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
// comes, interrupt is generated.
//
// Revision 1.35 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.34 2002/09/08 16:31:49 mohor
// Async reset for WB_ACK_O removed (when core was in reset, it was
// impossible to access BDs).
// RxPointers and TxPointers names changed to be more descriptive.
// TxUnderRun synchronized.
//
// Revision 1.33 2002/09/04 18:47:57 mohor
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
// was not used OK.
//
// Revision 1.32 2002/08/14 19:31:48 mohor
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
// need to multiply or devide any more.
//
// Revision 1.31 2002/07/25 18:29:01 mohor
// WriteRxDataToMemory signal changed so end of frame (when last word is
// written to fifo) is changed.
//
// Revision 1.30 2002/07/23 15:28:31 mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.29 2002/07/20 00:41:32 mohor
// ShiftEnded synchronization changed.
//
// Revision 1.28 2002/07/18 16:11:46 mohor
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
//
// Revision 1.27 2002/07/11 02:53:20 mohor
// RxPointer bug fixed.
//
// Revision 1.26 2002/07/10 13:12:38 mohor
// Previous bug wasn't succesfully removed. Now fixed.
//
// Revision 1.25 2002/07/09 23:53:24 mohor
// Master state machine had a bug when switching from master write to
// master read.
//
// Revision 1.24 2002/07/09 20:44:41 mohor
// m_wb_cyc_o signal released after every single transfer.
//
// Revision 1.23 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.22 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.21 2002/03/29 16:18:11 lampret
// Small typo fixed.
//
// Revision 1.20 2002/03/25 16:19:12 mohor
// Any address can be used for Tx and Rx BD pointers. Address does not need
// to be aligned.
//
// Revision 1.19 2002/03/19 12:51:50 mohor
// Comments in Slovene language removed.
//
// Revision 1.18 2002/03/19 12:46:52 mohor
// casex changed with case, fifo reset changed.
//
// Revision 1.17 2002/03/09 16:08:45 mohor
// rx_fifo was not always cleared ok. Fixed.
//
// Revision 1.16 2002/03/09 13:51:20 mohor
// Status was not latched correctly sometimes. Fixed.
//
// Revision 1.15 2002/03/08 06:56:46 mohor
// Big Endian problem when sending frames fixed.
//
// Revision 1.14 2002/03/02 19:12:40 mohor
// Byte ordering changed (Big Endian used). casex changed with case because
// Xilinx Foundation had problems. Tested in HW. It WORKS.
//
// Revision 1.13 2002/02/26 16:59:55 mohor
// Small fixes for external/internal DMA missmatches.
//
// Revision 1.12 2002/02/26 16:22:07 mohor
// Interrupts changed
//
// Revision 1.11 2002/02/15 17:07:39 mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.10 2002/02/15 12:17:39 mohor
// RxStartFrm cleared when abort or retry comes.
//
// Revision 1.9 2002/02/15 11:59:10 mohor
// Changes that were lost when updating from 1.5 to 1.8 fixed.
//
// Revision 1.8 2002/02/14 20:54:33 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.7 2002/02/12 17:03:47 mohor
// RxOverRun added to statuses.
//
// Revision 1.6 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.3 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
// Revision 1.2 2002/02/01 12:46:51 mohor
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
// added.
//
// Revision 1.1 2002/01/23 10:47:59 mohor
// Initial version. Equals to eth_wishbonedma.v at this moment.
//
//
//
module eth_wishbone
(
// WISHBONE common
WB_CLK_I, WB_DAT_I, WB_DAT_O,
// WISHBONE slave
WB_ADR_I, WB_WE_I, WB_ACK_O,
BDCs,
Reset,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
PerPacketPad,
//RX
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
// Register
r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
ReceivedPauseFrm,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
// Bist
`ifdef ETH_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
`endif
);
parameter Tp = 1;
// WISHBONE common
input WB_CLK_I; // WISHBONE clock
input [31:0] WB_DAT_I; // WISHBONE data input
output [31:0] WB_DAT_O; // WISHBONE data output
// WISHBONE slave
input [9:2] WB_ADR_I; // WISHBONE address input
input WB_WE_I; // WISHBONE write enable input
input BDCs; // Buffer descriptors are selected
output WB_ACK_O; // WISHBONE acknowledge output
// WISHBONE master
output [31:0] m_wb_adr_o; //
output [3:0] m_wb_sel_o; //
output m_wb_we_o; //
output [31:0] m_wb_dat_o; //
output m_wb_cyc_o; //
output m_wb_stb_o; //
input [31:0] m_wb_dat_i; //
input m_wb_ack_i; //
input m_wb_err_i; //
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
reg [2:0] m_wb_cti_o; // Cycle Type Identifier
`endif
input Reset; // Reset signal
// Rx Status signals
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
input LatchedCrcError; // CRC error
input RxLateCollision; // Late collision occured while receiving frame
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
input DribbleNibble; // Extra nibble received
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
input ReceivedPacketGood;// Received packet's length and CRC are good
input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
input r_RxFlow;
input r_PassAll;
input ReceivedPauseFrm;
// Tx Status signals
input [3:0] RetryCntLatched; // Latched Retry Counter
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
input LateCollLatched; // Late collision occured
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
input TxRetry; // Transmit packet retry
input TxAbort; // Transmit packet abort
input TxDone; // Transmission ended
output TxStartFrm; // Transmit packet start frame
output TxEndFrm; // Transmit packet end frame
output [7:0] TxData; // Transmit packet data byte
output TxUnderRun; // Transmit packet under-run
output PerPacketCrcEn; // Per packet crc enable
output PerPacketPad; // Per packet pading
// Rx
input MRxClk; // Receive clock (from PHY)
input [7:0] RxData; // Received data byte (from PHY)
input RxValid; //
input RxStartFrm; //
input RxEndFrm; //
input RxAbort; // This signal is set when address doesn't match.
output RxStatusWriteLatched_sync2;
//Register
input r_TxEn; // Transmit enable
input r_RxEn; // Receive enable
input [7:0] r_TxBDNum; // Receive buffer descriptor number
input TX_BD_NUM_Wr; // RxBDNumber written
// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxE_IRQ;
output Busy_IRQ;
// Bist
`ifdef ETH_BIST
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
`endif
reg TxB_IRQ;
reg TxE_IRQ;
reg RxB_IRQ;
reg RxE_IRQ;
reg TxStartFrm;
reg TxEndFrm;
reg [7:0] TxData;
reg TxUnderRun;
reg TxUnderRun_wb;
reg TxBDRead;
wire TxStatusWrite;
reg [1:0] TxValidBytesLatched;
reg [15:0] TxLength;
reg [15:0] LatchedTxLength;
reg [14:11] TxStatus;
reg [14:13] RxStatus;
reg TxStartFrm_wb;
reg TxRetry_wb;
reg TxAbort_wb;
reg TxDone_wb;
reg TxDone_wb_q;
reg TxAbort_wb_q;
reg TxRetry_wb_q;
reg TxRetryPacket;
reg TxRetryPacket_NotCleared;
reg TxDonePacket;
reg TxDonePacket_NotCleared;
reg TxAbortPacket;
reg TxAbortPacket_NotCleared;
reg RxBDReady;
reg RxReady;
reg TxBDReady;
reg RxBDRead;
reg [31:0] TxDataLatched;
reg [1:0] TxByteCnt;
reg LastWord;
reg ReadTxDataFromFifo_tck;
reg BlockingTxStatusWrite;
reg BlockingTxBDRead;
reg Flop;
reg [7:0] TxBDAddress;
reg [7:0] RxBDAddress;
reg TxRetrySync1;
reg TxAbortSync1;
reg TxDoneSync1;
reg TxAbort_q;
reg TxRetry_q;
reg TxUsedData_q;
reg [31:0] RxDataLatched2;
reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
reg [1:0] RxValidBytes;
reg [1:0] RxByteCnt;
reg LastByteIn;
reg ShiftWillEnd;
reg WriteRxDataToFifo;
reg [15:0] LatchedRxLength;
reg RxAbortLatched;
reg ShiftEnded;
reg RxOverrun;
reg BDWrite; // BD Write Enable for access from WISHBONE side
reg BDRead; // BD Read access from WISHBONE side
wire [31:0] RxBDDataIn; // Rx BD data in
wire [31:0] TxBDDataIn; // Tx BD data in
reg TxEndFrm_wb;
wire TxRetryPulse;
wire TxDonePulse;
wire TxAbortPulse;
wire StartRxBDRead;
wire StartTxBDRead;
wire TxIRQEn;
wire WrapTxStatusBit;
wire RxIRQEn;
wire WrapRxStatusBit;
wire [1:0] TxValidBytes;
wire [7:0] TempTxBDAddress;
wire [7:0] TempRxBDAddress;
wire RxStatusWrite;
reg WB_ACK_O;
wire [8:0] RxStatusIn;
reg [8:0] RxStatusInLatched;
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
wire ram_ce;
wire ram_we;
wire ram_oe;
reg [7:0] ram_addr;
reg [31:0] ram_di;
wire [31:0] ram_do;
wire StartTxPointerRead;
reg TxPointerRead;
reg TxEn_needed;
reg RxEn_needed;
wire StartRxPointerRead;
reg RxPointerRead;
`ifdef ETH_WISHBONE_B3
assign m_wb_bte_o = 2'b00; // Linear burst
`endif
always @ (posedge WB_CLK_I)
begin
WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
assign WB_DAT_O = ram_do;
// Generic synchronous single-port RAM interface
eth_spram_256x32 bd_ram (
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
`ifdef ETH_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
`endif
);
assign ram_ce = 1'b1;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEn_needed <=#Tp 1'b0;
else
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
TxEn_needed <=#Tp 1'b1;
else
if(TxPointerRead & TxEn & TxEn_q)
TxEn_needed <=#Tp 1'b0;
end
// Enabling access to the RAM for three devices.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn <=#Tp 1'b1;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp 8'h0;
ram_di <=#Tp 32'h0;
BDRead <=#Tp 1'b0;
BDWrite <=#Tp 1'b0;
end
else
begin
// Switching between three stages depends on enable signals
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
5'b100_10, 5'b100_11 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
TxEn <=#Tp 1'b0;
ram_addr <=#Tp RxBDAddress + RxPointerRead;
ram_di <=#Tp RxBDDataIn;
end
5'b100_01 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
ram_addr <=#Tp TxBDAddress + TxPointerRead;
ram_di <=#Tp TxBDDataIn;
end
5'b010_00, 5'b010_10 :
begin
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs & WB_WE_I;
BDRead <=#Tp BDCs & ~WB_WE_I;
end
5'b010_01, 5'b010_11 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
ram_addr <=#Tp TxBDAddress + TxPointerRead;
ram_di <=#Tp TxBDDataIn;
end
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
begin
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs & WB_WE_I;
BDRead <=#Tp BDCs & ~WB_WE_I;
end
5'b100_00 :
begin
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
end
5'b000_00 :
begin
WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs & WB_WE_I;
BDRead <=#Tp BDCs & ~WB_WE_I;
end
endcase
end
end
// Delayed stage signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn_q <=#Tp 1'b0;
RxEn_q <=#Tp 1'b0;
TxEn_q <=#Tp 1'b0;
end
else
begin
WbEn_q <=#Tp WbEn;
RxEn_q <=#Tp RxEn;
TxEn_q <=#Tp TxEn;
end
end
// Changes for tx occur every second clock. Flop is used for this manner.
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Flop <=#Tp 1'b0;
else
if(TxDone | TxAbort | TxRetry_q)
Flop <=#Tp 1'b0;
else
if(TxUsedData)
Flop <=#Tp ~Flop;
end
wire ResetTxBDReady;
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
// Latching READY status of the Tx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDReady <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxBDRead)
TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
else // Only packets larger then 4 bytes are transmitted.
if(ResetTxBDReady)
TxBDReady <=#Tp 1'b0;
end
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDRead <=#Tp 1'b1;
else
if(StartTxBDRead)
TxBDRead <=#Tp 1'b1;
else
if(TxBDReady)
TxBDRead <=#Tp 1'b0;
end
// Reading Tx BD pointer
assign StartTxPointerRead = TxBDRead & TxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerRead <=#Tp 1'b0;
else
if(StartTxPointerRead)
TxPointerRead <=#Tp 1'b1;
else
if(TxEn_q)
TxPointerRead <=#Tp 1'b0;
end
// Writing status back to the Tx buffer descriptor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
// Status writing must occur only once. Meanwhile it is blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite <=#Tp 1'b0;
else
if(~TxDone_wb & ~TxAbort_wb)
BlockingTxStatusWrite <=#Tp 1'b0;
else
if(TxStatusWrite)
BlockingTxStatusWrite <=#Tp 1'b1;
end
reg BlockingTxStatusWrite_sync1;
reg BlockingTxStatusWrite_sync2;
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
end
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
end
// TxBDRead state is activated only once.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxBDRead <=#Tp 1'b0;
else
if(StartTxBDRead)
BlockingTxBDRead <=#Tp 1'b1;
else
if(~StartTxBDRead & ~TxBDReady)
BlockingTxBDRead <=#Tp 1'b0;
end
// Latching status from the tx buffer descriptor
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStatus <=#Tp 4'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxStatus <=#Tp ram_do[14:11];
end
reg ReadTxDataFromMemory;
wire WriteRxDataToMemory;
reg MasterWbTX;
reg MasterWbRX;
reg [31:0] m_wb_adr_o;
reg m_wb_cyc_o;
reg m_wb_stb_o;
reg [3:0] m_wb_sel_o;
reg m_wb_we_o;
wire TxLengthEq0;
wire TxLengthLt4;
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0] TxPointerLSB;
reg [1:0] TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0] RxPointerLSB_rst;
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxLength <=#Tp ram_do[31:16];
else
if(MasterWbTX & m_wb_ack_i)
begin
if(TxLengthLt4)
TxLength <=#Tp 16'h0;
else
if(TxPointerLSB_rst==2'h0)
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h1)
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h2)
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h3)
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request
end
end
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchedTxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
LatchedTxLength <=#Tp ram_do[31:16];
end
assign TxLengthEq0 = TxLength == 0;
assign TxLengthLt4 = TxLength < 4;
reg cyc_cleared;
reg IncrTxPointer;
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
// because TxPointerMSB is only used for word-aligned accesses.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerMSB <=#Tp 30'h0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerMSB <=#Tp ram_do[31:2];
else
if(IncrTxPointer & ~BlockingIncrementTxPointer)
TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned
end
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
// set by this two bits.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB[1:0] <=#Tp 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB[1:0] <=#Tp ram_do[1:0];
end
// Latching 2 MSB bits of the buffer descriptor.
// After the read access, TxLength needs to be decremented for the number of the valid
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are
// valid so this two bits are reset to zero.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB_rst[1:0] <=#Tp 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
else
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
TxPointerLSB_rst[1:0] <=#Tp 0;
end
reg [3:0] RxByteSel;
wire MasterAccessFinished;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingIncrementTxPointer <=#Tp 0;
else
if(MasterAccessFinished)
BlockingIncrementTxPointer <=#Tp 0;
else
if(IncrTxPointer)
BlockingIncrementTxPointer <=#Tp 1'b1;
end
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
reg BlockReadTxDataFromMemory;
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromMemory <=#Tp 1'b0;
else
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
ReadTxDataFromMemory <=#Tp 1'b0;
else
if(SetReadTxDataFromMemory)
ReadTxDataFromMemory <=#Tp 1'b1;
end
reg tx_burst_en;
reg rx_burst_en;
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockReadTxDataFromMemory <=#Tp 1'b0;
else
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
BlockReadTxDataFromMemory <=#Tp 1'b1;
else
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
BlockReadTxDataFromMemory <=#Tp 1'b0;
end
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp 32'h0;
m_wb_cyc_o <=#Tp 1'b0;
m_wb_stb_o <=#Tp 1'b0;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'h0;
cyc_cleared<=#Tp 1'b0;
tx_burst_cnt<=#Tp 0;
rx_burst_cnt<=#Tp 0;
IncrTxPointer<=#Tp 1'b0;
tx_burst_en<=#Tp 1'b1;
rx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
else
begin
// Switching between two stages depends on enable signals
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst}) // synopsys parallel_case
8'b00_10_00_10, // Idle and MRB needed
8'b10_1x_10_1x, // MRB continues
8'b10_10_01_10, // Clear (previously MR) and MRB needed
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
begin
MasterWbTX <=#Tp 1'b1; // tx burst
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b1;
tx_burst_cnt <=#Tp tx_burst_cnt+1;
if(tx_burst_cnt==0)
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
else
m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
tx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b010;
`endif
end
end
8'b00_x1_00_x1, // Idle and MWB needed
8'b01_x1_10_x1, // MWB continues
8'b01_01_01_01, // Clear (previously MW) and MWB needed
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
begin
MasterWbTX <=#Tp 1'b0; // rx burst
MasterWbRX <=#Tp 1'b1;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
IncrTxPointer<=#Tp 1'b0;
cyc_cleared<=#Tp 1'b0;
rx_burst_cnt <=#Tp rx_burst_cnt+1;
if(rx_burst_cnt==0)
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
else
m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
rx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b010;
`endif
end
end
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
IncrTxPointer<=#Tp 1'b0;
end
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
begin
MasterWbTX <=#Tp 1'b1;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
IncrTxPointer<=#Tp 1'b1;
end
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer)
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer)
begin
MasterWbTX <=#Tp 1'b1;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b1;
end
8'b01_01_01_00, // MW and MW needed (data write to rx buffer)
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b0;
end
8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access)
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
begin
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
m_wb_stb_o <=#Tp 1'b0;
cyc_cleared<=#Tp 1'b1;
IncrTxPointer<=#Tp 1'b0;
tx_burst_cnt<=#Tp 0;
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
rx_burst_cnt<=#Tp 0;
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access)
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b0;
m_wb_stb_o <=#Tp 1'b0;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b0;
rx_burst_cnt<=#Tp 0;
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
begin
tx_burst_cnt<=#Tp 0;
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
end
default: // Don't touch
begin
MasterWbTX <=#Tp MasterWbTX;
MasterWbRX <=#Tp MasterWbRX;
m_wb_cyc_o <=#Tp m_wb_cyc_o;
m_wb_stb_o <=#Tp m_wb_stb_o;
m_wb_sel_o <=#Tp m_wb_sel_o;
IncrTxPointer<=#Tp IncrTxPointer;
end
endcase
end
end
wire TxFifoClear;
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
.clk(WB_CLK_I), .reset(Reset),
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
.clear(TxFifoClear), .full(TxBufferFull),
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
.empty(TxBufferEmpty), .cnt(txfifo_cnt)
);
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_wb <=#Tp 1'b0;
else
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
TxStartFrm_wb <=#Tp 1'b1;
else
if(TxStartFrm_syncb2)
TxStartFrm_wb <=#Tp 1'b0;
end
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
StartOccured <=#Tp 1'b0;
else
if(TxStartFrm_wb)
StartOccured <=#Tp 1'b1;
else
if(ResetTxBDReady)
StartOccured <=#Tp 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync1 <=#Tp 1'b0;
else
TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync2 <=#Tp 1'b0;
else
TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb1 <=#Tp 1'b0;
else
TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb2 <=#Tp 1'b0;
else
TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm <=#Tp 1'b0;
else
if(TxStartFrm_sync2)
TxStartFrm <=#Tp 1'b1;
else
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
TxStartFrm <=#Tp 1'b0;
end
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
// TxEndFrm_wb: indicator of the end of frame
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEndFrm_wb <=#Tp 1'b0;
else
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
TxEndFrm_wb <=#Tp 1'b1;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxEndFrm_wb <=#Tp 1'b0;
end
// Marks which bytes are valid within the word.
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
reg LatchValidBytes;
reg LatchValidBytes_q;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes <=#Tp 1'b0;
else
if(TxLengthLt4 & TxBDReady)
LatchValidBytes <=#Tp 1'b1;
else
LatchValidBytes <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes_q <=#Tp 1'b0;
else
LatchValidBytes_q <=#Tp LatchValidBytes;
end
// Latching valid bytes
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxValidBytesLatched <=#Tp 2'h0;
else
if(LatchValidBytes & ~LatchValidBytes_q)
TxValidBytesLatched <=#Tp TxValidBytes;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxValidBytesLatched <=#Tp 2'h0;
end
assign TxIRQEn = TxStatus[14];
assign WrapTxStatusBit = TxStatus[13];
assign PerPacketPad = TxStatus[12];
assign PerPacketCrcEn = TxStatus[11];
assign RxIRQEn = RxStatus[14];
assign WrapRxStatusBit = RxStatus[13];
// Temporary Tx and Rx buffer descriptor address
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1) | // Using first Rx BD
{8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
// Latching Tx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDAddress <=#Tp 8'h0;
else
if(TxStatusWrite)
TxBDAddress <=#Tp TempTxBDAddress;
end
// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
else
if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also
RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
else
if(RxStatusWrite)
RxBDAddress <=#Tp TempRxBDAddress;
end
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
// Signals used for various purposes
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
// Generating delayed signals
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
TxAbort_q <=#Tp 1'b0;
TxRetry_q <=#Tp 1'b0;
TxUsedData_q <=#Tp 1'b0;
end
else
begin
TxAbort_q <=#Tp TxAbort;
TxRetry_q <=#Tp TxRetry;
TxUsedData_q <=#Tp TxUsedData;
end
end
// Generating delayed signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
TxDone_wb_q <=#Tp 1'b0;
TxAbort_wb_q <=#Tp 1'b0;
TxRetry_wb_q <=#Tp 1'b0;
end
else
begin
TxDone_wb_q <=#Tp TxDone_wb;
TxAbort_wb_q <=#Tp TxAbort_wb;
TxRetry_wb_q <=#Tp TxRetry_wb;
end
end
reg TxAbortPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket <=#Tp 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket <=#Tp 1'b1;
else
TxAbortPacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket_NotCleared <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
TxAbortPacket_NotCleared <=#Tp 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacketBlocked <=#Tp 1'b0;
else
if(!TxAbort_wb & TxAbort_wb_q)
TxAbortPacketBlocked <=#Tp 1'b0;
else
if(TxAbortPacket)
TxAbortPacketBlocked <=#Tp 1'b1;
end
reg TxRetryPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket <=#Tp 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
TxRetryPacket <=#Tp 1'b1;
else
TxRetryPacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket_NotCleared <=#Tp 1'b0;
else
if(StartTxBDRead)
TxRetryPacket_NotCleared <=#Tp 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
TxRetryPacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacketBlocked <=#Tp 1'b0;
else
if(!TxRetry_wb & TxRetry_wb_q)
TxRetryPacketBlocked <=#Tp 1'b0;
else
if(TxRetryPacket)
TxRetryPacketBlocked <=#Tp 1'b1;
end
reg TxDonePacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket <=#Tp 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
TxDonePacket <=#Tp 1'b1;
else
TxDonePacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket_NotCleared <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
TxDonePacket_NotCleared <=#Tp 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
TxDonePacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacketBlocked <=#Tp 1'b0;
else
if(!TxDone_wb & TxDone_wb_q)
TxDonePacketBlocked <=#Tp 1'b0;
else
if(TxDonePacket)
TxDonePacketBlocked <=#Tp 1'b1;
end
// Indication of the last word
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LastWord <=#Tp 1'b0;
else
if((TxEndFrm | TxAbort | TxRetry) & Flop)
LastWord <=#Tp 1'b0;
else
if(TxUsedData & Flop & TxByteCnt == 2'h3)
LastWord <=#Tp TxEndFrm_wb;
end
// Tx end frame generation
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxEndFrm <=#Tp 1'b0;
else
if(Flop & TxEndFrm | TxAbort | TxRetry_q)
TxEndFrm <=#Tp 1'b0;
else
if(Flop & LastWord)
begin
case (TxValidBytesLatched) // synopsys parallel_case
1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
0 : TxEndFrm <=#Tp TxByteCnt == 2'h3;
default : TxEndFrm <=#Tp 1'b0;
endcase
end
end
// Tx data selection (latching)
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxData <=#Tp 0;
else
if(TxStartFrm_sync2 & ~TxStartFrm)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
endcase
else
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
else
if(TxUsedData & Flop)
begin
case(TxByteCnt) // synopsys parallel_case
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
1 : TxData <=#Tp TxDataLatched[23:16];
2 : TxData <=#Tp TxDataLatched[15:8];
3 : TxData <=#Tp TxDataLatched[7:0];
endcase
end
end
// Latching tx data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDataLatched[31:0] <=#Tp 32'h0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
end
// Tx under run
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxAbortPulse)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
TxUnderRun_wb <=#Tp 1'b1;
end
reg TxUnderRun_sync1;
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun_sync1 <=#Tp 1'b0;
else
if(TxUnderRun_wb)
TxUnderRun_sync1 <=#Tp 1'b1;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun_sync1 <=#Tp 1'b0;
end
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun <=#Tp 1'b0;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun <=#Tp 1'b0;
else
if(TxUnderRun_sync1)
TxUnderRun <=#Tp 1'b1;
end
// Tx Byte counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxByteCnt <=#Tp 2'h0;
else
if(TxAbort_q | TxRetry_q)
TxByteCnt <=#Tp 2'h0;
else
if(TxStartFrm & ~TxUsedData)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxByteCnt <=#Tp 2'h1;
2'h1 : TxByteCnt <=#Tp 2'h2;
2'h2 : TxByteCnt <=#Tp 2'h3;
2'h3 : TxByteCnt <=#Tp 2'h0;
endcase
else
if(TxUsedData & Flop)
TxByteCnt <=#Tp TxByteCnt + 1'b1;
end
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
reg ReadTxDataFromFifo_sync1;
reg ReadTxDataFromFifo_sync2;
reg ReadTxDataFromFifo_sync3;
reg ReadTxDataFromFifo_syncb1;
reg ReadTxDataFromFifo_syncb2;
reg ReadTxDataFromFifo_syncb3;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_tck <=#Tp 1'b0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
ReadTxDataFromFifo_tck <=#Tp 1'b1;
else
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
ReadTxDataFromFifo_tck <=#Tp 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
end
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetrySync1 <=#Tp 1'b0;
else
TxRetrySync1 <=#Tp TxRetry;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetry_wb <=#Tp 1'b0;
else
TxRetry_wb <=#Tp TxRetrySync1;
end
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDoneSync1 <=#Tp 1'b0;
else
TxDoneSync1 <=#Tp TxDone;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDone_wb <=#Tp 1'b0;
else
TxDone_wb <=#Tp TxDoneSync1;
end
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortSync1 <=#Tp 1'b0;
else
TxAbortSync1 <=#Tp TxAbort;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbort_wb <=#Tp 1'b0;
else
TxAbort_wb <=#Tp TxAbortSync1;
end
reg RxAbortSync1;
reg RxAbortSync2;
reg RxAbortSync3;
reg RxAbortSync4;
reg RxAbortSyncb1;
reg RxAbortSyncb2;
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
// Reading the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDRead <=#Tp 1'b1;
else
if(StartRxBDRead & ~RxReady)
RxBDRead <=#Tp 1'b1;
else
if(RxBDReady)
RxBDRead <=#Tp 1'b0;
end
// Reading of the next receive buffer descriptor starts after reception status is
// written to the previous one.
// Latching READY status of the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDReady <=#Tp 1'b0;
else
if(RxPointerRead)
RxBDReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxBDRead)
RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
end
// Latching Rx buffer descriptor status
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatus <=#Tp 2'h0;
else
if(RxEn & RxEn_q & RxBDRead)
RxStatus <=#Tp ram_do[14:13];
end
// RxReady generation
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxReady <=#Tp 1'b0;
else
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
RxReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxReady <=#Tp 1'b1;
end
// Reading Rx BD pointer
assign StartRxPointerRead = RxBDRead & RxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerRead <=#Tp 1'b0;
else
if(StartRxPointerRead)
RxPointerRead <=#Tp 1'b1;
else
if(RxEn & RxEn_q)
RxPointerRead <=#Tp 1'b0;
end
//Latching Rx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerMSB <=#Tp 30'h0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerMSB <=#Tp ram_do[31:2];
else
if(MasterWbRX & m_wb_ack_i)
RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
end
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerLSB_rst[1:0] <=#Tp 0;
else
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
RxPointerLSB_rst[1:0] <=#Tp 0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
end
always @ (RxPointerLSB_rst)
begin
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
2'h0 : RxByteSel[3:0] = 4'hf;
2'h1 : RxByteSel[3:0] = 4'h7;
2'h2 : RxByteSel[3:0] = 4'h3;
2'h3 : RxByteSel[3:0] = 4'h1;
endcase
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxEn_needed <=#Tp 1'b0;
else
if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
RxEn_needed <=#Tp 1'b1;
else
if(RxPointerRead & RxEn & RxEn_q)
RxEn_needed <=#Tp 1'b0;
end
// Reception status is written back to the buffer descriptor after the end of frame is detected.
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
reg RxEnableWindow;
// Indicating that last byte is being reveived
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LastByteIn <=#Tp 1'b0;
else
if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
LastByteIn <=#Tp 1'b0;
else
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
LastByteIn <=#Tp 1'b1;
end
reg ShiftEnded_rck;
reg ShiftEndedSync1;
reg ShiftEndedSync2;
reg ShiftEndedSync3;
reg ShiftEndedSync_c1;
reg ShiftEndedSync_c2;
wire StartShiftWillEnd;
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
// Indicating that data reception will end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftWillEnd <=#Tp 1'b0;
else
if(ShiftEnded_rck | RxAbort)
ShiftWillEnd <=#Tp 1'b0;
else
if(StartShiftWillEnd)
ShiftWillEnd <=#Tp 1'b1;
end
// Receive byte counter
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxByteCnt <=#Tp 2'h0;
else
if(ShiftEnded_rck | RxAbort)
RxByteCnt <=#Tp 2'h0;
else
if(RxValid & RxStartFrm & RxReady)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxByteCnt <=#Tp 2'h1;
2'h1 : RxByteCnt <=#Tp 2'h2;
2'h2 : RxByteCnt <=#Tp 2'h3;
2'h3 : RxByteCnt <=#Tp 2'h0;
endcase
else
if(RxValid & RxEnableWindow & RxReady | LastByteIn)
RxByteCnt <=#Tp RxByteCnt + 1'b1;
end
// Indicates how many bytes are valid within the last word
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxValidBytes <=#Tp 2'h1;
else
if(RxValid & RxStartFrm)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxValidBytes <=#Tp 2'h1;
2'h1 : RxValidBytes <=#Tp 2'h2;
2'h2 : RxValidBytes <=#Tp 2'h3;
2'h3 : RxValidBytes <=#Tp 2'h0;
endcase
else
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
RxValidBytes <=#Tp RxValidBytes + 1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched1 <=#Tp 24'h0;
else
if(RxValid & RxReady & ~LastByteIn)
if(RxStartFrm)
begin
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
endcase
end
else if (RxEnableWindow)
begin
case(RxByteCnt) // synopsys parallel_case
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
endcase
end
end
wire SetWriteRxDataToFifo;
// Assembling data that will be written to the rx_fifo
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched2 <=#Tp 32'h0;
else
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
else
if(SetWriteRxDataToFifo & ShiftWillEnd)
case(RxValidBytes) // synopsys parallel_case
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
endcase
end
reg WriteRxDataToFifoSync1;
reg WriteRxDataToFifoSync2;
reg WriteRxDataToFifoSync3;
// Indicating start of the reception process
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
(RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) |
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
WriteRxDataToFifo <=#Tp 1'b0;
else
if(SetWriteRxDataToFifo & ~RxAbort)
WriteRxDataToFifo <=#Tp 1'b1;
else
if(WriteRxDataToFifoSync2 | RxAbort)
WriteRxDataToFifo <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync1 <=#Tp 1'b0;
else
if(WriteRxDataToFifo)
WriteRxDataToFifoSync1 <=#Tp 1'b1;
else
WriteRxDataToFifoSync1 <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync2 <=#Tp 1'b0;
else
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync3 <=#Tp 1'b0;
else
WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
end
wire WriteRxDataToFifo_wb;
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
reg LatchedRxStartFrm;
reg SyncRxStartFrm;
reg SyncRxStartFrm_q;
reg SyncRxStartFrm_q2;
wire RxFifoReset;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxStartFrm <=#Tp 0;
else
if(RxStartFrm & ~SyncRxStartFrm_q)
LatchedRxStartFrm <=#Tp 1;
else
if(SyncRxStartFrm_q)
LatchedRxStartFrm <=#Tp 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm <=#Tp 0;
else
if(LatchedRxStartFrm)
SyncRxStartFrm <=#Tp 1;
else
SyncRxStartFrm <=#Tp 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q <=#Tp 0;
else
SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q2 <=#Tp 0;
else
SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
end
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
.clk(WB_CLK_I), .reset(Reset),
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
.clear(RxFifoReset), .full(RxBufferFull),
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
.empty(RxBufferEmpty), .cnt(rxfifo_cnt)
);
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
assign WriteRxDataToMemory = ~RxBufferEmpty;
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEnded_rck <=#Tp 1'b0;
else
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
ShiftEnded_rck <=#Tp 1'b1;
else
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
ShiftEnded_rck <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync1 <=#Tp 1'b0;
else
ShiftEndedSync1 <=#Tp ShiftEnded_rck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync2 <=#Tp 1'b0;
else
ShiftEndedSync2 <=#Tp ShiftEndedSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync3 <=#Tp 1'b0;
else
if(ShiftEndedSync1 & ~ShiftEndedSync2)
ShiftEndedSync3 <=#Tp 1'b1;
else
if(ShiftEnded)
ShiftEndedSync3 <=#Tp 1'b0;
end
// Generation of the end-of-frame signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEnded <=#Tp 1'b0;
else
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
ShiftEnded <=#Tp 1'b1;
else
if(RxStatusWrite)
ShiftEnded <=#Tp 1'b0;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c1 <=#Tp 1'b0;
else
ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c2 <=#Tp 1'b0;
else
ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
end
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxEnableWindow <=#Tp 1'b0;
else
if(RxStartFrm)
RxEnableWindow <=#Tp 1'b1;
else
if(RxEndFrm | RxAbort)
RxEnableWindow <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync1 <=#Tp 1'b0;
else
RxAbortSync1 <=#Tp RxAbortLatched;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync2 <=#Tp 1'b0;
else
RxAbortSync2 <=#Tp RxAbortSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync3 <=#Tp 1'b0;
else
RxAbortSync3 <=#Tp RxAbortSync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync4 <=#Tp 1'b0;
else
RxAbortSync4 <=#Tp RxAbortSync3;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb1 <=#Tp 1'b0;
else
RxAbortSyncb1 <=#Tp RxAbortSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb2 <=#Tp 1'b0;
else
RxAbortSyncb2 <=#Tp RxAbortSyncb1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortLatched <=#Tp 1'b0;
else
if(RxAbortSyncb2)
RxAbortLatched <=#Tp 1'b0;
else
if(RxAbort)
RxAbortLatched <=#Tp 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxLength[15:0] <=#Tp 16'h0;
else
if(LoadRxStatus)
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
end
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxStatusInLatched <=#Tp 'h0;
else
if(LoadRxStatus)
RxStatusInLatched <=#Tp RxStatusIn;
end
// Rx overrun
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxOverrun <=#Tp 1'b0;
else
if(RxStatusWrite)
RxOverrun <=#Tp 1'b0;
else
if(RxBufferFull & WriteRxDataToFifo_wb)
RxOverrun <=#Tp 1'b1;
end
wire TxError;
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
wire RxError;
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
// are aborted when signal r_RecSmall is set to 0 in MODER register.
// AddressMiss is identifying that a frame was received because of the promiscous
// mode and is not an error
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
reg RxStatusWriteLatched;
reg RxStatusWriteLatched_sync1;
reg RxStatusWriteLatched_sync2;
reg RxStatusWriteLatched_syncb1;
reg RxStatusWriteLatched_syncb2;
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWriteLatched_syncb2)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWrite)
RxStatusWriteLatched <=#Tp 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_sync1 <=#Tp 1'b0;
RxStatusWriteLatched_sync2 <=#Tp 1'b0;
end
else
begin
RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
end
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
end
else
begin
RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
end
end
// Tx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxB_IRQ <=#Tp 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxB_IRQ <=#Tp ~TxError;
else
TxB_IRQ <=#Tp 1'b0;
end
// Tx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxE_IRQ <=#Tp 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxE_IRQ <=#Tp TxError;
else
TxE_IRQ <=#Tp 1'b0;
end
// Rx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxB_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxB_IRQ <=#Tp (~RxError);
else
RxB_IRQ <=#Tp 1'b0;
end
// Rx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxE_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxE_IRQ <=#Tp RxError;
else
RxE_IRQ <=#Tp 1'b0;
end
// Busy Interrupt
reg Busy_IRQ_rck;
reg Busy_IRQ_sync1;
reg Busy_IRQ_sync2;
reg Busy_IRQ_sync3;
reg Busy_IRQ_syncb1;
reg Busy_IRQ_syncb2;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Busy_IRQ_rck <=#Tp 1'b0;
else
if(RxValid & RxStartFrm & ~RxReady)
Busy_IRQ_rck <=#Tp 1'b1;
else
if(Busy_IRQ_syncb2)
Busy_IRQ_rck <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I)
begin
Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
end
always @ (posedge MRxClk)
begin
Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
end
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_transmitcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_transmitcontrol.v,v $
// Revision 1.6 2002/11/21 00:16:14 mohor
// When TxUsedData and CtrlMux occur at the same time, byte counter needs
// to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
//
// Revision 1.5 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
ControlData, WillSendControlFrame, BlockTxDone
);
parameter Tp = 1;
input MTxClk;
input TxReset;
input TxUsedDataIn;
input TxUsedDataOut;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmIn;
input TPauseRq;
input TxUsedDataOutDetected;
input TxFlow;
input DlyCrcEn;
input [15:0] TxPauseTV;
input [47:0] MAC;
output TxCtrlStartFrm;
output TxCtrlEndFrm;
output SendingCtrlFrm;
output CtrlMux;
output [7:0] ControlData;
output WillSendControlFrame;
output BlockTxDone;
reg SendingCtrlFrm;
reg CtrlMux;
reg WillSendControlFrame;
reg [3:0] DlyCrcCnt;
reg [5:0] ByteCnt;
reg ControlEnd_q;
reg [7:0] MuxedCtrlData;
reg TxCtrlStartFrm;
reg TxCtrlStartFrm_q;
reg TxCtrlEndFrm;
reg [7:0] ControlData;
reg TxUsedDataIn_q;
reg BlockTxDone;
wire IncrementDlyCrcCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ControlEnd;
wire IncrementByteCntBy2;
wire EnableCnt;
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
WillSendControlFrame <= #Tp 1'b0;
else
if(TxCtrlEndFrm & CtrlMux)
WillSendControlFrame <= #Tp 1'b0;
else
if(TPauseRq & TxFlow)
WillSendControlFrame <= #Tp 1'b1;
end
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(TxUsedDataIn_q & CtrlMux)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
TxCtrlStartFrm <= #Tp 1'b1;
end
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlEndFrm <= #Tp 1'b0;
else
if(ControlEnd | ControlEnd_q)
TxCtrlEndFrm <= #Tp 1'b1;
else
TxCtrlEndFrm <= #Tp 1'b0;
end
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
CtrlMux <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut)
CtrlMux <= #Tp 1'b1;
else
if(TxDoneIn)
CtrlMux <= #Tp 1'b0;
end
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
SendingCtrlFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & TxCtrlStartFrm)
SendingCtrlFrm <= #Tp 1'b1;
else
if(TxDoneIn)
SendingCtrlFrm <= #Tp 1'b0;
end
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataIn_q <= #Tp 1'b0;
else
TxUsedDataIn_q <= #Tp TxUsedDataIn;
end
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
BlockTxDone <= #Tp 1'b0;
else
if(TxCtrlStartFrm)
BlockTxDone <= #Tp 1'b1;
else
if(TxStartFrmIn)
BlockTxDone <= #Tp 1'b0;
end
always @ (posedge MTxClk)
begin
ControlEnd_q <= #Tp ControlEnd;
TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
end
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
DlyCrcCnt <= #Tp 4'h0;
else
if(ResetByteCnt)
DlyCrcCnt <= #Tp 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ByteCnt <= #Tp 6'h0;
else
if(ResetByteCnt)
ByteCnt <= #Tp 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
assign ControlEnd = ByteCnt[5:0] == 6'h22;
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
case(ByteCnt)
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
else
MuxedCtrlData[7:0] = 8'h0;
6'h2: MuxedCtrlData[7:0] = 8'h80;
6'h4: MuxedCtrlData[7:0] = 8'hC2;
6'h6: MuxedCtrlData[7:0] = 8'h00;
6'h8: MuxedCtrlData[7:0] = 8'h00;
6'hA: MuxedCtrlData[7:0] = 8'h01;
6'hC: MuxedCtrlData[7:0] = MAC[47:40];
6'hE: MuxedCtrlData[7:0] = MAC[39:32];
6'h10: MuxedCtrlData[7:0] = MAC[31:24];
6'h12: MuxedCtrlData[7:0] = MAC[23:16];
6'h14: MuxedCtrlData[7:0] = MAC[15:8];
6'h16: MuxedCtrlData[7:0] = MAC[7:0];
6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
6'h1A: MuxedCtrlData[7:0] = 8'h08;
6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
6'h1E: MuxedCtrlData[7:0] = 8'h01;
6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
default: MuxedCtrlData[7:0] = 8'h0;
endcase
end
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ControlData[7:0] <= #Tp 8'h0;
else
if(~ByteCnt[0])
ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_top.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_top.v,v $
// Revision 1.46 2003/01/30 13:30:22 tadejm
// Defer indication changed.
//
// Revision 1.45 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.44 2003/01/21 12:09:40 mohor
// When receiving normal data frame and RxFlow control was switched on, RXB
// interrupt was not set.
//
// Revision 1.43 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.42 2002/11/21 00:09:19 mohor
// TPauseRq synchronized to tx_clk.
//
// Revision 1.41 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.40 2002/11/19 17:34:25 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.39 2002/11/18 17:31:55 mohor
// wb_rst_i is used for MIIM reset.
//
// Revision 1.38 2002/11/14 18:37:20 mohor
// r_Rst signal does not reset any module any more and is removed from the design.
//
// Revision 1.37 2002/11/13 22:25:36 tadejm
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
//
// Revision 1.36 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.35 2002/10/11 13:36:58 mohor
// Typo error fixed. (When using Bist)
//
// Revision 1.34 2002/10/10 16:49:50 mohor
// Signals for WISHBONE B3 compliant interface added.
//
// Revision 1.33 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.32 2002/09/20 17:12:58 mohor
// CsMiss added. When address between 0x800 and 0xfff is accessed within
// Ethernet Core, error acknowledge is generated.
//
// Revision 1.31 2002/09/12 14:50:17 mohor
// CarrierSenseLost bug fixed when operating in full duplex mode.
//
// Revision 1.30 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.29 2002/09/09 13:03:13 mohor
// Error acknowledge is generated when accessing BDs and RST bit in the
// MODER register (r_Rst) is set.
//
// Revision 1.28 2002/09/04 18:44:10 mohor
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
// connected.
//
// Revision 1.27 2002/07/25 18:15:37 mohor
// RxAbort changed. Packets received with MRxErr (from PHY) are also
// aborted.
//
// Revision 1.26 2002/07/17 18:51:50 mohor
// EXTERNAL_DMA removed. External DMA not supported.
//
// Revision 1.25 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.24 2002/04/22 14:15:42 mohor
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
// selected in eth_defines.v
//
// Revision 1.23 2002/03/25 13:33:53 mohor
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
// name was incorrect.
//
// Revision 1.22 2002/02/26 16:59:54 mohor
// Small fixes for external/internal DMA missmatches.
//
// Revision 1.21 2002/02/26 16:21:00 mohor
// Interrupts changed in the top file
//
// Revision 1.20 2002/02/18 10:40:17 mohor
// Small fixes.
//
// Revision 1.19 2002/02/16 14:03:44 mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.18 2002/02/16 13:06:33 mohor
// EXTERNAL_DMA used instead of WISHBONE_DMA.
//
// Revision 1.17 2002/02/16 07:15:27 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.16 2002/02/15 13:49:39 mohor
// RxAbort is connected differently.
//
// Revision 1.15 2002/02/15 11:38:26 mohor
// Changes that were lost when updating from 1.11 to 1.14 fixed.
//
// Revision 1.14 2002/02/14 20:19:11 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.13 2002/02/12 17:03:03 mohor
// HASH0 and HASH1 registers added. Registers address width was
// changed to 8 bits.
//
// Revision 1.12 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.11 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.10 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.9 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.8 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.7 2001/12/05 10:45:59 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.6 2001/10/19 11:24:29 mohor
// Number of addresses (wb_adr_i) minimized.
//
// Revision 1.5 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.4 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.3 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.2 2001/08/15 14:03:59 mohor
// Signal names changed on the top level for easier pad insertion (ASIC).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
module eth_top
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
//RX
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
// MIIM
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
int_o
// Bist
`ifdef ETH_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
`endif
);
parameter Tp = 1;
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output [31:0] wb_dat_o; // WISHBONE data output
output wb_err_o; // WISHBONE error output
// WISHBONE slave
input [11:2] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output wb_ack_o; // WISHBONE acknowledge output
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
`endif
// Tx
input mtx_clk_pad_i; // Transmit clock (from PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
// Rx
input mrx_clk_pad_i; // Receive clock (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
// Common Tx and Rx
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
// MII Management interface
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoe_o; // MII data output enable (to I/O cell)
output int_o; // Interrupt output
// Bist
`ifdef ETH_BIST
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
`endif
wire [7:0] r_ClkDiv;
wire r_MiiNoPre;
wire [15:0] r_CtrlData;
wire [4:0] r_FIAD;
wire [4:0] r_RGAD;
wire r_WCtrlData;
wire r_RStat;
wire r_ScanStat;
wire NValid_stat;
wire Busy_stat;
wire LinkFail;
wire [15:0] Prsd; // Read Status Data (data read from the PHY)
wire WCtrlDataStart;
wire RStatStart;
wire UpdateMIIRX_DATAReg;
wire TxStartFrm;
wire TxEndFrm;
wire TxUsedData;
wire [7:0] TxData;
wire TxRetry;
wire TxAbort;
wire TxUnderRun;
wire TxDone;
wire [5:0] CollValid;
reg WillSendControlFrame_sync1;
reg WillSendControlFrame_sync2;
reg WillSendControlFrame_sync3;
reg RstTxPauseRq;
reg TxPauseRq_sync1;
reg TxPauseRq_sync2;
reg TxPauseRq_sync3;
reg TPauseRq;
// Connecting Miim module
eth_miim miim1
(
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
.MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
wire RegCs; // Connected to registers
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
wire r_RecSmall; // Receive small frames
wire r_LoopBck; // Loopback
wire r_TxEn; // Tx Enable
wire r_RxEn; // Rx Enable
wire MRxDV_Lb; // Muxed MII receive data valid
wire MRxErr_Lb; // Muxed MII Receive Error
wire [3:0] MRxD_Lb; // Muxed MII Receive Data
wire Transmitting; // Indication that TxEthMAC is transmitting
wire r_HugEn; // Huge packet enable
wire r_DlyCrcEn; // Delayed CRC enabled
wire [15:0] r_MaxFL; // Maximum frame length
wire [15:0] r_MinFL; // Minimum frame length
wire ShortFrame;
wire DribbleNibble; // Extra nibble received
wire ReceivedPacketTooBig; // Received packet is too big
wire [47:0] r_MAC; // MAC address
wire LoadRxStatus; // Rx status was loaded
wire [31:0] r_HASH0; // HASH table, lower 4 bytes
wire [31:0] r_HASH1; // HASH table, upper 4 bytes
wire [7:0] r_TxBDNum; // Receive buffer descriptor number
wire [6:0] r_IPGT; //
wire [6:0] r_IPGR1; //
wire [6:0] r_IPGR2; //
wire [5:0] r_CollValid; //
wire [15:0] r_TxPauseTV; // Transmit PAUSE value
wire r_TxPauseRq; // Transmit PAUSE request
wire [3:0] r_MaxRet; //
wire r_NoBckof; //
wire r_ExDfrEn; //
wire TX_BD_NUM_Wr; // Write enable that writes RX_BD_NUM to the registers.
wire r_TxFlow; // Tx flow control enable
wire r_IFG; // Minimum interframe gap for incoming packets
wire TxB_IRQ; // Interrupt Tx Buffer
wire TxE_IRQ; // Interrupt Tx Error
wire RxB_IRQ; // Interrupt Rx Buffer
wire RxE_IRQ; // Interrupt Rx Error
wire Busy_IRQ; // Interrupt Busy (lack of buffers)
wire DWord;
wire BDAck;
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
wire BDCs; // Buffer descriptor CS
wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
// but data is not valid.
wire temp_wb_ack_o;
wire [31:0] temp_wb_dat_o;
wire temp_wb_err_o;
`ifdef ETH_REGISTERED_OUTPUTS
reg temp_wb_ack_o_reg;
reg [31:0] temp_wb_dat_o_reg;
reg temp_wb_err_o_reg;
`endif
assign DWord = &wb_sel_i;
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11]; // 0x800 - 0xfFF
assign temp_wb_ack_o = RegCs | BDAck;
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
`ifdef ETH_REGISTERED_OUTPUTS
assign wb_ack_o = temp_wb_ack_o_reg;
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
assign wb_err_o = temp_wb_err_o_reg;
`else
assign wb_ack_o = temp_wb_ack_o;
assign wb_dat_o[31:0] = temp_wb_dat_o;
assign wb_err_o = temp_wb_err_o;
`endif
`ifdef ETH_REGISTERED_OUTPUTS
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
temp_wb_ack_o_reg <=#Tp 1'b0;
temp_wb_dat_o_reg <=#Tp 32'h0;
temp_wb_err_o_reg <=#Tp 1'b0;
end
else
begin
temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
end
end
`endif
// Connecting Ethernet registers
eth_registers ethreg1
(
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
.r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.r_IPGT(r_IPGT),
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
.r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
.r_TxBDNum(r_TxBDNum), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), .int_o(int_o),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
.SetPauseTimer(SetPauseTimer)
);
wire [7:0] RxData;
wire RxValid;
wire RxStartFrm;
wire RxEndFrm;
wire RxAbort;
wire WillTransmit; // Will transmit (to RxEthMAC)
wire ResetCollision; // Reset Collision (for synchronizing collision)
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
wire WillSendControlFrame;
wire ReceiveEnd;
wire ReceivedPacketGood;
wire ReceivedLengthOK;
wire InvalidSymbol;
wire LatchedCrcError;
wire RxLateCollision;
wire [3:0] RetryCntLatched;
wire [3:0] RetryCnt;
wire StartTxAbort;
wire MaxCollisionOccured;
wire RetryLimit;
wire StatePreamble;
wire [1:0] StateData;
// Connecting MACControl
eth_maccontrol maccontrol1
(
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
.RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
.TxFlow(r_TxFlow),
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
.CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
.RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
.ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
.SetPauseTimer(SetPauseTimer),
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
);
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
wire Collision; // Synchronized Collision
reg CarrierSense_Tx1;
reg CarrierSense_Tx2;
reg Collision_Tx1;
reg Collision_Tx2;
reg RxEnSync; // Synchronized Receive Enable
reg CarrierSense_Rx1;
reg RxCarrierSense; // Synchronized CarrierSense (to Rx clock)
reg WillTransmit_q;
reg WillTransmit_q2;
// Muxed MII receive data valid
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
// Muxed MII Receive Error
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
// Muxed MII Receive Data
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
// Connecting TxEthMAC
eth_txethmac txethmac1
(
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
.MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
.ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
.DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
);
wire [15:0] RxByteCnt;
wire RxByteCntEq0;
wire RxByteCntGreat2;
wire RxByteCntMaxFrame;
wire RxCrcError;
wire RxStateIdle;
wire RxStatePreamble;
wire RxStateSFD;
wire [1:0] RxStateData;
wire AddressMiss;
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
.StateSFD(RxStateSFD), .StateData(RxStateData),
.MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
.AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
);
// MII Carrier Sense Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
CarrierSense_Tx1 <= #Tp 1'b0;
CarrierSense_Tx2 <= #Tp 1'b0;
end
else
begin
CarrierSense_Tx1 <= #Tp mcrs_pad_i;
CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
end
end
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
// MII Collision Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
Collision_Tx1 <= #Tp 1'b0;
Collision_Tx2 <= #Tp 1'b0;
end
else
begin
Collision_Tx1 <= #Tp mcoll_pad_i;
if(ResetCollision)
Collision_Tx2 <= #Tp 1'b0;
else
if(Collision_Tx1)
Collision_Tx2 <= #Tp 1'b1;
end
end
// Synchronized Collision
assign Collision = ~r_FullD & Collision_Tx2;
// Carrier sense is synchronized to receive clock.
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
CarrierSense_Rx1 <= #Tp 1'h0;
RxCarrierSense <= #Tp 1'h0;
end
else
begin
CarrierSense_Rx1 <= #Tp mcrs_pad_i;
RxCarrierSense <= #Tp CarrierSense_Rx1;
end
end
// Delayed WillTransmit
always @ (posedge mrx_clk_pad_i)
begin
WillTransmit_q <= #Tp WillTransmit;
WillTransmit_q2 <= #Tp WillTransmit_q;
end
assign Transmitting = ~r_FullD & WillTransmit_q2;
// Synchronized Receive Enable
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxEnSync <= #Tp 1'b0;
else
if(~RxCarrierSense | RxCarrierSense & Transmitting)
RxEnSync <= #Tp r_RxEn;
end
// Synchronizing WillSendControlFrame to WB_CLK;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync1 <= 1'b0;
else
WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync2 <= 1'b0;
else
WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync3 <= 1'b0;
else
WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RstTxPauseRq <= 1'b0;
else
RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
end
// TX Pause request Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
TxPauseRq_sync1 <= #Tp 1'b0;
TxPauseRq_sync2 <= #Tp 1'b0;
TxPauseRq_sync3 <= #Tp 1'b0;
end
else
begin
TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
end
end
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
TPauseRq <= #Tp 1'b0;
else
TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
end
wire LatchedMRxErr;
reg RxAbort_latch;
reg RxAbort_sync1;
reg RxAbort_sync2;
reg RxAbort_wb;
reg RxAbortRst_sync1;
reg RxAbortRst;
// Synchronizing RxAbort to the WISHBONE clock
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxAbort_latch <= #Tp 1'b0;
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
RxAbort_latch <= #Tp 1'b1;
else if(RxAbortRst)
RxAbort_latch <= #Tp 1'b0;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbort_sync1 <= #Tp 1'b0;
RxAbort_wb <= #Tp 1'b0;
RxAbort_wb <= #Tp 1'b0;
end
else
begin
RxAbort_sync1 <= #Tp RxAbort_latch;
RxAbort_wb <= #Tp RxAbort_sync1;
end
end
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbortRst_sync1 <= #Tp 1'b0;
RxAbortRst <= #Tp 1'b0;
end
else
begin
RxAbortRst_sync1 <= #Tp RxAbort_wb;
RxAbortRst <= #Tp RxAbortRst_sync1;
end
end
// Connecting Wishbone module
eth_wishbone wishbone
(
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
.WB_DAT_O(BD_WB_DAT_O),
// WISHBONE slave
.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
.BDCs(BDCs), .WB_ACK_O(BDAck),
.Reset(wb_rst_i),
// WISHBONE master
.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
`ifdef ETH_WISHBONE_B3
.m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
`endif
//TX
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
.TxUsedData(TxUsedData), .TxData(TxData),
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
.TxDone(TxDone),
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
// Register
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
.TX_BD_NUM_Wr(TX_BD_NUM_Wr), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
//RX
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
.ReceivedPauseFrm(ReceivedPauseFrm)
`ifdef ETH_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
`endif
);
// Connecting MacStatus module
eth_macstatus macstatus1
(
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
.InvalidSymbol(InvalidSymbol),
.MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
.LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
);
endmodule
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
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