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module gsm_impl
#(
parameter DWIDTH = 256,
parameter MWIDTH = 4,
parameter GSIZE = 4,
parameter LOG_MWIDTH = 2,
parameter LOG_GSIZE = 2,
parameter AWIDTH = 7,
parameter LOC_PKT_LEN = 24, // the bit location of packet length field in the 16-byte data cell
parameter LOC_DEST_IP = 31, // the bit location of the destination ip field in the data cell
parameter LOC_SOURCE_ID = 16
)
(
input wire clk_33M,
input wire extern_rst_n,
input wire [MWIDTH*GSIZE-1:0] ingress_valid,
input wire [MWIDTH*GSIZE-1:0] ingress_header,
input wire [MWIDTH*GSIZE-1:0] ingress_data_bit,
input wire [MWIDTH*GSIZE-1:0] egress_stall,
output wire [MWIDTH*GSIZE-1:0] egress_valid,
output reg [MWIDTH*GSIZE-1:0] egress_data_bit
);
genvar i;
reg [DWIDTH-1:0]ingress_data[MWIDTH*GSIZE-1:0];
wire [DWIDTH-1:0] egress_data[MWIDTH*GSIZE-1:0];
wire clk_80M, clr_80M, clk_320M, clr_320M, rst_n;
generate
for(i=0;i<MWIDTH*GSIZE;i=i+1)begin:INGRESS_DATA_GEN
always@(posedge clk_80M)
if(clr_80M)
ingress_data[i] <= 0;
else
ingress_data[i] <= {ingress_data[i], ingress_data_bit[i]};
always@(posedge clk_80M)
if(clr_80M)
egress_data_bit[i] <= 0;
else
egress_data_bit[i] <= |egress_data[i];
end
endgenerate
gsm_sys
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.GSIZE(GSIZE), // group size, number of gsm_unit in each group
.LOG_MWIDTH(LOG_MWIDTH),
.LOG_GSIZE(LOG_GSIZE),
.DWIDTH(DWIDTH), // data width = 16 bytes
.AWIDTH(AWIDTH) // 2 BRAM = total 512 cells, each port is allocated 128 cells
) gsm_sys_inst
(
//** global
.clk_33M(clk_33M),
.extern_rst_n(extern_rst_n),
.clk_320M(clk_320M),
.clk_80M(clk_80M),
.clr_320M(clr_320M),
.clr_80M(clr_80M),
.rst_n(rst_n),
//** 16 ingress ports
// group 0
.i_ingress_valid_0_0(ingress_valid[0]),
.i_ingress_header_0_0(ingress_header[0]),
.i_ingress_data_0_0(ingress_data[0]),
.i_ingress_valid_0_1(ingress_valid[1]),
.i_ingress_header_0_1(ingress_header[1]),
.i_ingress_data_0_1(ingress_data[1]),
.i_ingress_valid_0_2(ingress_valid[2]),
.i_ingress_header_0_2(ingress_header[2]),
.i_ingress_data_0_2(ingress_data[2]),
.i_ingress_valid_0_3(ingress_valid[3]),
.i_ingress_header_0_3(ingress_header[3]),
.i_ingress_data_0_3(ingress_data[3]),
// group 1
.i_ingress_valid_1_0(ingress_valid[4]),
.i_ingress_header_1_0(ingress_header[4]),
.i_ingress_data_1_0(ingress_data[4]),
.i_ingress_valid_1_1(ingress_valid[5]),
.i_ingress_header_1_1(ingress_header[5]),
.i_ingress_data_1_1(ingress_data[5]),
.i_ingress_valid_1_2(ingress_valid[6]),
.i_ingress_header_1_2(ingress_header[6]),
.i_ingress_data_1_2(ingress_data[6]),
.i_ingress_valid_1_3(ingress_valid[7]),
.i_ingress_header_1_3(ingress_header[7]),
.i_ingress_data_1_3(ingress_data[7]),
// group 2
.i_ingress_valid_2_0(ingress_valid[8]),
.i_ingress_header_2_0(ingress_header[8]),
.i_ingress_data_2_0(ingress_data[8]),
.i_ingress_valid_2_1(ingress_valid[9]),
.i_ingress_header_2_1(ingress_header[9]),
.i_ingress_data_2_1(ingress_data[9]),
.i_ingress_valid_2_2(ingress_valid[10]),
.i_ingress_header_2_2(ingress_header[10]),
.i_ingress_data_2_2(ingress_data[10]),
.i_ingress_valid_2_3(ingress_valid[11]),
.i_ingress_header_2_3(ingress_header[11]),
.i_ingress_data_2_3(ingress_data[11]),
// group 3
.i_ingress_valid_3_0(ingress_valid[12]),
.i_ingress_header_3_0(ingress_header[12]),
.i_ingress_data_3_0(ingress_data[12]),
.i_ingress_valid_3_1(ingress_valid[13]),
.i_ingress_header_3_1(ingress_header[13]),
.i_ingress_data_3_1(ingress_data[13]),
.i_ingress_valid_3_2(ingress_valid[14]),
.i_ingress_header_3_2(ingress_header[14]),
.i_ingress_data_3_2(ingress_data[14]),
.i_ingress_valid_3_3(ingress_valid[15]),
.i_ingress_header_3_3(ingress_header[15]),
.i_ingress_data_3_3(ingress_data[15]),
//** 16 egress ports
// group 0
.i_egress_stall_0_0(egress_stall[0]),
.o_egress_valid_0_0(egress_valid[0]),
.o_egress_data_0_0(egress_data[0]),
.i_egress_stall_0_1(egress_stall[1]),
.o_egress_valid_0_1(egress_valid[1]),
.o_egress_data_0_1(egress_data[1]),
.i_egress_stall_0_2(egress_stall[2]),
.o_egress_valid_0_2(egress_valid[2]),
.o_egress_data_0_2(egress_data[2]),
.i_egress_stall_0_3(egress_stall[3]),
.o_egress_valid_0_3(egress_valid[3]),
.o_egress_data_0_3(egress_data[3]),
// group 1
.i_egress_stall_1_0(egress_stall[4]),
.o_egress_valid_1_0(egress_valid[4]),
.o_egress_data_1_0(egress_data[4]),
.i_egress_stall_1_1(egress_stall[5]),
.o_egress_valid_1_1(egress_valid[5]),
.o_egress_data_1_1(egress_data[5]),
.i_egress_stall_1_2(egress_stall[6]),
.o_egress_valid_1_2(egress_valid[6]),
.o_egress_data_1_2(egress_data[6]),
.i_egress_stall_1_3(egress_stall[7]),
.o_egress_valid_1_3(egress_valid[7]),
.o_egress_data_1_3(egress_data[7]),
// group 2
.i_egress_stall_2_0(egress_stall[8]),
.o_egress_valid_2_0(egress_valid[8]),
.o_egress_data_2_0(egress_data[8]),
.i_egress_stall_2_1(egress_stall[9]),
.o_egress_valid_2_1(egress_valid[9]),
.o_egress_data_2_1(egress_data[9]),
.i_egress_stall_2_2(egress_stall[10]),
.o_egress_valid_2_2(egress_valid[10]),
.o_egress_data_2_2(egress_data[10]),
.i_egress_stall_2_3(egress_stall[11]),
.o_egress_valid_2_3(egress_valid[11]),
.o_egress_data_2_3(egress_data[11]),
// group 3
.i_egress_stall_3_0(egress_stall[12]),
.o_egress_valid_3_0(egress_valid[12]),
.o_egress_data_3_0(egress_data[12]),
.i_egress_stall_3_1(egress_stall[13]),
.o_egress_valid_3_1(egress_valid[13]),
.o_egress_data_3_1(egress_data[13]),
.i_egress_stall_3_2(egress_stall[14]),
.o_egress_valid_3_2(egress_valid[14]),
.o_egress_data_3_2(egress_data[14]),
.i_egress_stall_3_3(egress_stall[15]),
.o_egress_valid_3_3(egress_valid[15]),
.o_egress_data_3_3(egress_data[15])
);
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_ram.v
// Description : a time-multiplexing SRAM module, which serves as the building block
// of the grouped-share-memory system.
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-16 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_ram
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter LOG_MWIDTH = 2,
parameter DWIDTH = 128, // data width = 16 bytes
parameter AWIDTH = 9 // 2 BRAM = total 512 cells
)
(
// global
input wire clk,
input wire rst_n,
input wire clr,
// input port
input wire i_wr_en,
input wire [AWIDTH-1:0] i_wr_addr,
input wire [DWIDTH-1:0] i_wr_data,
input wire [MWIDTH-1:0] i_multicast,
// output port
input wire [MWIDTH-1:0] i_egress_stall,
output wire [MWIDTH-1:0] o_egress_sel,
output wire [DWIDTH-1:0] o_egress_data,
// buffer free
output wire o_buf_free,
output wire [AWIDTH-1:0] o_buf_free_addr
);
localparam BRAM_RD_DELAY = 2;
//******************************
// signal declaration
//******************************
genvar i;
reg [MWIDTH-1:0] fsm_opq_sel;
wire [MWIDTH-1:0] opq_empty, opq_full, opq_valid, opq_rd_en;
wire [AWIDTH-1:0] opq_dout[MWIDTH-1:0];
wire [MWIDTH+DWIDTH-1:0] gsm_rd_data;
reg [MWIDTH-1:0] gsm_rd_sel;
reg [MWIDTH-1:0] gsm_rd_sel_delay[BRAM_RD_DELAY-1:0];
reg [BRAM_RD_DELAY-1:0] gsm_rd_valid_delay;
reg [AWIDTH-1:0] gsm_rd_addr;
//******************************
// logics starts here
//******************************
// finite state machine
always@(posedge clk )begin
if(clr)
fsm_opq_sel <= 1;
else
fsm_opq_sel <= {fsm_opq_sel,fsm_opq_sel[MWIDTH-1]};
end
// output pointer queues
assign opq_rd_en = fsm_opq_sel & (~i_egress_stall);// | ~opq_valid;
generate
for(i=0; i<MWIDTH; i=i+1) begin: OPQ_GEN
fifo_16 opq(
.clk(clk),
.rst(clr),
.din(i_wr_addr),
.wr_en(i_wr_en & i_multicast[i]),
.rd_en(opq_rd_en[i]),
.dout(opq_dout[i]),
.full(opq_full[i]),
.empty(opq_empty[i]),
.valid(opq_valid[i])
);
end
endgenerate
// central memory read address
generate
if(MWIDTH == 4)begin
always@(posedge clk )begin
if(clr)
gsm_rd_addr <= 0;
else
case (opq_valid) //(fsm_opq_sel)
4'b0001:gsm_rd_addr <= opq_dout[0];
4'b0010:gsm_rd_addr <= opq_dout[1];
4'b0100:gsm_rd_addr <= opq_dout[2];
4'b1000:gsm_rd_addr <= opq_dout[3];
default:gsm_rd_addr <= 0;
endcase
end
end
endgenerate
// gsm read enable, read select signal and delayed signal
always@(posedge clk )begin
if(clr)
gsm_rd_sel <= 0;
else
gsm_rd_sel <= opq_valid;//(fsm_opq_sel & (~i_egress_stall) & opq_valid);
end
// centralized share memory for data
infer_sdpram
#(
.DWIDTH(MWIDTH+DWIDTH), // data width of the SRAM, 36 bit when configured to be SDP BRAM, otherwise 18 bit wide
.AWIDTH(AWIDTH) // address width of the SRAM
) central_mem
(
// global
.clk_a(clk),
.clk_b(clk),
// port a interface
.en_a(i_wr_en),
.write_a(i_wr_en),
.wr_data_a({i_multicast,i_wr_data}),
.addr_a(i_wr_addr),
// port b interface
.en_b(1'b1),
.addr_b(gsm_rd_addr),
.rd_data_b(gsm_rd_data)
);
/*
gsm_sram central_mem(
.clka(clk),
.wea(i_wr_en),
.addra(i_wr_addr),
.dina({i_multicast,i_wr_data}),
.clkb(clk),
.addrb(gsm_rd_addr),
.doutb(gsm_rd_data)
);
*/
always@(posedge clk )begin
if(clr)
gsm_rd_sel_delay[0] <= 0;
else
gsm_rd_sel_delay[0] <= gsm_rd_sel;
end
generate
for(i=1;i<BRAM_RD_DELAY; i=i+1) begin: GSM_RD_SEL_DELAY
always@(posedge clk )begin
if(clr)
gsm_rd_sel_delay[i] <= 0;
else
gsm_rd_sel_delay[i] <= gsm_rd_sel_delay[i-1];
end
end
endgenerate
always@(posedge clk )begin
if(clr)
gsm_rd_valid_delay <= 0;
else
gsm_rd_valid_delay <= {gsm_rd_valid_delay,|gsm_rd_sel};
end
//**************************************************************
// hardware malloc core logic
// implemented using a single BRAM, with a 1-bit write port
// a 4-bit write port and 4-bit read port. it works as follows:
// 1. in each clk cycle, the 1-bit write port will be enabled
// if there is a valid data sent to the output link. the
// address will be the same of the data being sent
// 2. the 4-bit read port is set to "WRITE_FITST" mode, so that
// after each write, the 4-bit vector of that data can be
// compared with its multicast vector, if the multicast task
// for that data is done, a reset signal will be asserted
// 3. when there is a reset signal, the 4-bit write port will
// be used to reset a specific 4-bit vector in the BRAM
//**************************************************************
reg [AWIDTH-1:0] m_addr;
reg [LOG_MWIDTH-1:0] m_sel_enc;
reg m_wr;
wire m_reset;
reg [AWIDTH-1:0] m_rst_addr[BRAM_RD_DELAY-1:0];
wire [MWIDTH-1:0] m_vec;
reg [MWIDTH-1:0] gsm_vec;
reg [BRAM_RD_DELAY-1:0] m_valid_delay;
always@(posedge clk )begin
if(clr)
m_sel_enc <= 0;
else
case (gsm_rd_sel)
4'b0001:m_sel_enc <= 2'b00;
4'b0010:m_sel_enc <= 2'b01;
4'b0100:m_sel_enc <= 2'b10;
4'b1000:m_sel_enc <= 2'b11;
default:m_sel_enc <= 0;
endcase
end
always@(posedge clk )begin
if(clr)begin
m_addr <= 0;
m_wr <= 0;
gsm_vec <= 0;
end
else begin
m_addr <= gsm_rd_addr;
m_wr <= |gsm_rd_sel;
gsm_vec <= gsm_rd_data[DWIDTH+3:DWIDTH];
end
end
always@(posedge clk )begin
if(clr)
m_valid_delay <= 0;
else
m_valid_delay <= {m_valid_delay,m_wr};
end
always@(posedge clk )begin
if(clr)
m_rst_addr[0] <= 0;
else
m_rst_addr[0] <= m_addr;
end
generate
for(i=1;i<BRAM_RD_DELAY; i=i+1) begin: MULTICAST_COUNTER_ADDR_DELAY
always@(posedge clk )begin
if(clr)
m_rst_addr[i] <= 0;
else
m_rst_addr[i] <= m_rst_addr[i-1];
end
end
endgenerate
malloc_core m_counter(
.clka(clk),
.wea(m_reset),
.addra({1'b0,m_rst_addr[BRAM_RD_DELAY-1]}),
.dina(4'b0000), // reset the counter to all 0s
.douta(),
.clkb(clk),
.rstb(clr),
.web(m_wr), //
.addrb({1'b0,m_addr,m_sel_enc}),
.dinb(1'b1),
.doutb(m_vec)
);
assign m_reset = m_valid_delay[BRAM_RD_DELAY-1] & (m_vec == gsm_vec);
// output port signals
assign o_buf_free = m_reset;
assign o_buf_free_addr = m_rst_addr[BRAM_RD_DELAY-1];
assign o_egress_data = gsm_rd_data[DWIDTH-1:0];
assign o_egress_sel = gsm_rd_sel_delay[BRAM_RD_DELAY-1];
endmodule
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// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_sys.v
// Description : a 16x16 Grouped Shared Memory switch system
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-29 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_sys
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter GSIZE = 4, // group size, number of gsm_unit in each group
parameter LOG_MWIDTH = 2,
parameter LOG_GSIZE = 2,
parameter DWIDTH = 128, // data width = 16 bytes
parameter AWIDTH = 7 // 2 BRAM = total 512 cells, each port is allocated 128 cells
)
(
//** global
input wire clk_33M,
input wire extern_rst_n,
output wire clk_320M,
output wire clk_80M,
output wire clr_320M,
output wire clr_80M,
output wire rst_n,
//** 16 ingress ports
// group 0
input wire i_ingress_valid_0_0,
input wire i_ingress_header_0_0,
input wire [DWIDTH-1:0] i_ingress_data_0_0,
input wire i_ingress_valid_0_1,
input wire i_ingress_header_0_1,
input wire [DWIDTH-1:0] i_ingress_data_0_1,
input wire i_ingress_valid_0_2,
input wire i_ingress_header_0_2,
input wire [DWIDTH-1:0] i_ingress_data_0_2,
input wire i_ingress_valid_0_3,
input wire i_ingress_header_0_3,
input wire [DWIDTH-1:0] i_ingress_data_0_3,
// group 1
input wire i_ingress_valid_1_0,
input wire i_ingress_header_1_0,
input wire [DWIDTH-1:0] i_ingress_data_1_0,
input wire i_ingress_valid_1_1,
input wire i_ingress_header_1_1,
input wire [DWIDTH-1:0] i_ingress_data_1_1,
input wire i_ingress_valid_1_2,
input wire i_ingress_header_1_2,
input wire [DWIDTH-1:0] i_ingress_data_1_2,
input wire i_ingress_valid_1_3,
input wire i_ingress_header_1_3,
input wire [DWIDTH-1:0] i_ingress_data_1_3,
// group 2
input wire i_ingress_valid_2_0,
input wire i_ingress_header_2_0,
input wire [DWIDTH-1:0] i_ingress_data_2_0,
input wire i_ingress_valid_2_1,
input wire i_ingress_header_2_1,
input wire [DWIDTH-1:0] i_ingress_data_2_1,
input wire i_ingress_valid_2_2,
input wire i_ingress_header_2_2,
input wire [DWIDTH-1:0] i_ingress_data_2_2,
input wire i_ingress_valid_2_3,
input wire i_ingress_header_2_3,
input wire [DWIDTH-1:0] i_ingress_data_2_3,
// group 3
input wire i_ingress_valid_3_0,
input wire i_ingress_header_3_0,
input wire [DWIDTH-1:0] i_ingress_data_3_0,
input wire i_ingress_valid_3_1,
input wire i_ingress_header_3_1,
input wire [DWIDTH-1:0] i_ingress_data_3_1,
input wire i_ingress_valid_3_2,
input wire i_ingress_header_3_2,
input wire [DWIDTH-1:0] i_ingress_data_3_2,
input wire i_ingress_valid_3_3,
input wire i_ingress_header_3_3,
input wire [DWIDTH-1:0] i_ingress_data_3_3,
//** 16 egress ports
// group 0
input wire i_egress_stall_0_0,
output reg o_egress_valid_0_0,
output reg [DWIDTH-1:0] o_egress_data_0_0,
input wire i_egress_stall_0_1,
output reg o_egress_valid_0_1,
output reg [DWIDTH-1:0] o_egress_data_0_1,
input wire i_egress_stall_0_2,
output reg o_egress_valid_0_2,
output reg [DWIDTH-1:0] o_egress_data_0_2,
input wire i_egress_stall_0_3,
output reg o_egress_valid_0_3,
output reg [DWIDTH-1:0] o_egress_data_0_3,
// group 1
input wire i_egress_stall_1_0,
output reg o_egress_valid_1_0,
output reg [DWIDTH-1:0] o_egress_data_1_0,
input wire i_egress_stall_1_1,
output reg o_egress_valid_1_1,
output reg [DWIDTH-1:0] o_egress_data_1_1,
input wire i_egress_stall_1_2,
output reg o_egress_valid_1_2,
output reg [DWIDTH-1:0] o_egress_data_1_2,
input wire i_egress_stall_1_3,
output reg o_egress_valid_1_3,
output reg [DWIDTH-1:0] o_egress_data_1_3,
// group 2
input wire i_egress_stall_2_0,
output reg o_egress_valid_2_0,
output reg [DWIDTH-1:0] o_egress_data_2_0,
input wire i_egress_stall_2_1,
output reg o_egress_valid_2_1,
output reg [DWIDTH-1:0] o_egress_data_2_1,
input wire i_egress_stall_2_2,
output reg o_egress_valid_2_2,
output reg [DWIDTH-1:0] o_egress_data_2_2,
input wire i_egress_stall_2_3,
output reg o_egress_valid_2_3,
output reg [DWIDTH-1:0] o_egress_data_2_3,
// group 3
input wire i_egress_stall_3_0,
output reg o_egress_valid_3_0,
output reg [DWIDTH-1:0] o_egress_data_3_0,
input wire i_egress_stall_3_1,
output reg o_egress_valid_3_1,
output reg [DWIDTH-1:0] o_egress_data_3_1,
input wire i_egress_stall_3_2,
output reg o_egress_valid_3_2,
output reg [DWIDTH-1:0] o_egress_data_3_2,
input wire i_egress_stall_3_3,
output reg o_egress_valid_3_3,
output reg [DWIDTH-1:0] o_egress_data_3_3
);
//*************************************************************
// wires and registers
//*************************************************************
genvar i;
//wire clk_320M;
//wire clr_320M;
//wire clk_80M;
//wire clr_80M;
//wire rst_n;
wire [GSIZE-1:0] ingress_valid0, ingress_header0;
wire [GSIZE-1:0] ingress_valid1, ingress_header1;
wire [GSIZE-1:0] ingress_valid2, ingress_header2;
wire [GSIZE-1:0] ingress_valid3, ingress_header3;
wire [DWIDTH-1:0] ingress_data0[GSIZE-1:0];
wire [DWIDTH-1:0] ingress_data1[GSIZE-1:0];
wire [DWIDTH-1:0] ingress_data2[GSIZE-1:0];
wire [DWIDTH-1:0] ingress_data3[GSIZE-1:0];
wire [GSIZE-1:0] egress_rd_0_0, egress_rd_0_1, egress_rd_0_2, egress_rd_0_3;
wire [GSIZE-1:0] egress_valid_0_0, egress_valid_0_1, egress_valid_0_2, egress_valid_0_3;
wire [GSIZE-1:0] egress_grant_0_0, egress_grant_0_1, egress_grant_0_2, egress_grant_0_3;
wire [GSIZE-1:0] egress_rd_1_0, egress_rd_1_1, egress_rd_1_2, egress_rd_1_3;
wire [GSIZE-1:0] egress_valid_1_0, egress_valid_1_1, egress_valid_1_2, egress_valid_1_3;
wire [GSIZE-1:0] egress_grant_1_0, egress_grant_1_1, egress_grant_1_2, egress_grant_1_3;
wire [GSIZE-1:0] egress_rd_2_0, egress_rd_2_1, egress_rd_2_2, egress_rd_2_3;
wire [GSIZE-1:0] egress_valid_2_0, egress_valid_2_1, egress_valid_2_2, egress_valid_2_3;
wire [GSIZE-1:0] egress_grant_2_0, egress_grant_2_1, egress_grant_2_2, egress_grant_2_3;
wire [GSIZE-1:0] egress_rd_3_0, egress_rd_3_1, egress_rd_3_2, egress_rd_3_3;
wire [GSIZE-1:0] egress_valid_3_0, egress_valid_3_1, egress_valid_3_2, egress_valid_3_3;
wire [GSIZE-1:0] egress_grant_3_0, egress_grant_3_1, egress_grant_3_2, egress_grant_3_3;
wire [DWIDTH-1:0] egress_data_0_0[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_0_1[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_0_2[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_0_3[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_1_0[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_1_1[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_1_2[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_1_3[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_2_0[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_2_1[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_2_2[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_2_3[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_3_0[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_3_1[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_3_2[GSIZE-1:0];
wire [DWIDTH-1:0] egress_data_3_3[GSIZE-1:0];
reg [1:0] clk_stable_320M;
//*************************************************************
// logic starts here...
//*************************************************************
ClockGenerator clk_gen
(
.EXTERNAL_RESET_L(extern_rst_n),
.CLOCKS_STABLE_H(clk_stable_80M),
.CLK_33MHz(clk_33M),
.CLK_80MHz(clk_80M),
.CLK_320MHz(clk_320M)
);
always@(posedge clk_320M)begin
clk_stable_320M <= {clk_stable_320M[0],clk_stable_80M};
end
//BUFG RESET_320M_Buffer ( .I(~clk_stable_320M[1]), .O(clr_320M) );
//BUFG RESET_80M_Buffer ( .I(~clk_stable_80M), .O(clr_80M) );
assign clr_320M = ~clk_stable_320M[1];
assign clr_80M = ~clk_stable_80M;
assign rst_n = 1'b1;
// ingress group 0
assign ingress_valid0[0] = i_ingress_valid_0_0;
assign ingress_header0[0] = i_ingress_header_0_0;
assign ingress_data0[0] = i_ingress_data_0_0;
assign ingress_valid0[1] = i_ingress_valid_1_0;
assign ingress_header0[1] = i_ingress_header_1_0;
assign ingress_data0[1] = i_ingress_data_1_0;
assign ingress_valid0[2] = i_ingress_valid_2_0;
assign ingress_header0[2] = i_ingress_header_2_0;
assign ingress_data0[2] = i_ingress_data_2_0;
assign ingress_valid0[3] = i_ingress_valid_3_0;
assign ingress_header0[3] = i_ingress_header_3_0;
assign ingress_data0[3] = i_ingress_data_3_0;
// ingress group 1
assign ingress_valid1[0] = i_ingress_valid_0_1;
assign ingress_header1[0] = i_ingress_header_0_1;
assign ingress_data1[0] = i_ingress_data_0_1;
assign ingress_valid1[1] = i_ingress_valid_1_1;
assign ingress_header1[1] = i_ingress_header_1_1;
assign ingress_data1[1] = i_ingress_data_1_1;
assign ingress_valid1[2] = i_ingress_valid_2_1;
assign ingress_header1[2] = i_ingress_header_2_1;
assign ingress_data1[2] = i_ingress_data_2_1;
assign ingress_valid1[3] = i_ingress_valid_3_1;
assign ingress_header1[3] = i_ingress_header_3_1;
assign ingress_data1[3] = i_ingress_data_3_1;
// ingress group 2
assign ingress_valid2[0] = i_ingress_valid_0_2;
assign ingress_header2[0] = i_ingress_header_0_2;
assign ingress_data2[0] = i_ingress_data_0_2;
assign ingress_valid2[1] = i_ingress_valid_1_2;
assign ingress_header2[1] = i_ingress_header_1_2;
assign ingress_data2[1] = i_ingress_data_1_2;
assign ingress_valid2[2] = i_ingress_valid_2_2;
assign ingress_header2[2] = i_ingress_header_2_2;
assign ingress_data2[2] = i_ingress_data_2_2;
assign ingress_valid2[3] = i_ingress_valid_3_2;
assign ingress_header2[3] = i_ingress_header_3_2;
assign ingress_data2[3] = i_ingress_data_3_2;
// ingress group 3
assign ingress_valid3[0] = i_ingress_valid_0_3;
assign ingress_header3[0] = i_ingress_header_0_3;
assign ingress_data3[0] = i_ingress_data_0_3;
assign ingress_valid3[1] = i_ingress_valid_1_3;
assign ingress_header3[1] = i_ingress_header_1_3;
assign ingress_data3[1] = i_ingress_data_1_3;
assign ingress_valid3[2] = i_ingress_valid_2_3;
assign ingress_header3[2] = i_ingress_header_2_3;
assign ingress_data3[2] = i_ingress_data_2_3;
assign ingress_valid3[3] = i_ingress_valid_3_3;
assign ingress_header3[3] = i_ingress_header_3_3;
assign ingress_data3[3] = i_ingress_data_3_3;
generate
for(i=0;i<GSIZE;i=i+1) begin: GSM_TILE_GEN
gsm_tile
#(
.MWIDTH(MWIDTH),
.GSIZE(GSIZE),
.LOG_MWIDTH(LOG_MWIDTH),
.DWIDTH(DWIDTH),
.AWIDTH(AWIDTH)
)gsm_tile_inst
(
//** global
.clk_320M(clk_320M),
.clr_320M(clr_320M),
.clk_80M(clk_80M),
.clr_80M(clr_80M),
.rst_n(rst_n),
//** 4 ingress ports
.i_ingress_valid0(ingress_valid0[i]),
.i_ingress_header0(ingress_header0[i]),
.i_ingress_data0(ingress_data0[i]),
.i_ingress_valid1(ingress_valid1[i]),
.i_ingress_header1(ingress_header1[i]),
.i_ingress_data1(ingress_data1[i]),
.i_ingress_valid2(ingress_valid2[i]),
.i_ingress_header2(ingress_header2[i]),
.i_ingress_data2(ingress_data2[i]),
.i_ingress_valid3(ingress_valid3[i]),
.i_ingress_header3(ingress_header3[i]),
.i_ingress_data3(ingress_data3[i]),
//** 16 egress ports
// group 1
.i_egress_rd_0_0(egress_grant_0_0[i]),
.o_egress_valid_0_0(egress_valid_0_0[i]),
.o_egress_data_0_0(egress_data_0_0[i]),
.i_egress_rd_0_1(egress_grant_0_1[i]),
.o_egress_valid_0_1(egress_valid_0_1[i]),
.o_egress_data_0_1(egress_data_0_1[i]),
.i_egress_rd_0_2(egress_grant_0_2[i]),
.o_egress_valid_0_2(egress_valid_0_2[i]),
.o_egress_data_0_2(egress_data_0_2[i]),
.i_egress_rd_0_3(egress_grant_0_3[i]),
.o_egress_valid_0_3(egress_valid_0_3[i]),
.o_egress_data_0_3(egress_data_0_3[i]),
// group 2
.i_egress_rd_1_0(egress_grant_1_0[i]),
.o_egress_valid_1_0(egress_valid_1_0[i]),
.o_egress_data_1_0(egress_data_1_0[i]),
.i_egress_rd_1_1(egress_grant_1_1[i]),
.o_egress_valid_1_1(egress_valid_1_1[i]),
.o_egress_data_1_1(egress_data_1_1[i]),
.i_egress_rd_1_2(egress_grant_1_2[i]),
.o_egress_valid_1_2(egress_valid_1_2[i]),
.o_egress_data_1_2(egress_data_1_2[i]),
.i_egress_rd_1_3(egress_grant_1_3[i]),
.o_egress_valid_1_3(egress_valid_1_3[i]),
.o_egress_data_1_3(egress_data_1_3[i]),
// group 3
.i_egress_rd_2_0(egress_grant_2_0[i]),
.o_egress_valid_2_0(egress_valid_2_0[i]),
.o_egress_data_2_0(egress_data_2_0[i]),
.i_egress_rd_2_1(egress_grant_2_1[i]),
.o_egress_valid_2_1(egress_valid_2_1[i]),
.o_egress_data_2_1(egress_data_2_1[i]),
.i_egress_rd_2_2(egress_grant_2_2[i]),
.o_egress_valid_2_2(egress_valid_2_2[i]),
.o_egress_data_2_2(egress_data_2_2[i]),
.i_egress_rd_2_3(egress_grant_2_3[i]),
.o_egress_valid_2_3(egress_valid_2_3[i]),
.o_egress_data_2_3(egress_data_2_3[i]),
// group 3
.i_egress_rd_3_0(egress_grant_3_0[i]),
.o_egress_valid_3_0(egress_valid_3_0[i]),
.o_egress_data_3_0(egress_data_3_0[i]),
.i_egress_rd_3_1(egress_grant_3_1[i]),
.o_egress_valid_3_1(egress_valid_3_1[i]),
.o_egress_data_3_1(egress_data_3_1[i]),
.i_egress_rd_3_2(egress_grant_3_2[i]),
.o_egress_valid_3_2(egress_valid_3_2[i]),
.o_egress_data_3_2(egress_data_3_2[i]),
.i_egress_rd_3_3(egress_grant_3_3[i]),
.o_egress_valid_3_3(egress_valid_3_3[i]),
.o_egress_data_3_3(egress_data_3_3[i])
);
end // end for
endgenerate
// 16 4:1 multiplexers for the 16*4 egress ports
rr_sch_16
#(
.GSIZE(GSIZE), // number of requests to be scheduled
.MWIDTH(MWIDTH),
.LOG_GSIZE(LOG_GSIZE)
)rr_sch_16_inst
(
.clk(clk_80M),
.rst_n(rst_n),
.clr(clr_80M),
// group0
.req_0_0(egress_valid_0_0),
.stall_0_0(i_egress_stall_0_0),
.grant_0_0(egress_grant_0_0),
.req_0_1(egress_valid_0_1),
.stall_0_1(i_egress_stall_0_1),
.grant_0_1(egress_grant_0_1),
.req_0_2(egress_valid_0_2),
.stall_0_2(i_egress_stall_0_2),
.grant_0_2(egress_grant_0_2),
.req_0_3(egress_valid_0_3),
.stall_0_3(i_egress_stall_0_3),
.grant_0_3(egress_grant_0_3),
// group1
.req_1_0(egress_valid_1_0),
.stall_1_0(i_egress_stall_1_0),
.grant_1_0(egress_grant_1_0),
.req_1_1(egress_valid_1_1),
.stall_1_1(i_egress_stall_1_1),
.grant_1_1(egress_grant_1_1),
.req_1_2(egress_valid_1_2),
.stall_1_2(i_egress_stall_1_2),
.grant_1_2(egress_grant_1_2),
.req_1_3(egress_valid_1_3),
.stall_1_3(i_egress_stall_1_3),
.grant_1_3(egress_grant_1_3),
// group2
.req_2_0(egress_valid_2_0),
.stall_2_0(i_egress_stall_2_0),
.grant_2_0(egress_grant_2_0),
.req_2_1(egress_valid_2_1),
.stall_2_1(i_egress_stall_2_1),
.grant_2_1(egress_grant_2_1),
.req_2_2(egress_valid_2_2),
.stall_2_2(i_egress_stall_2_2),
.grant_2_2(egress_grant_2_2),
.req_2_3(egress_valid_2_3),
.stall_2_3(i_egress_stall_2_3),
.grant_2_3(egress_grant_2_3),
// group3
.req_3_0(egress_valid_3_0),
.stall_3_0(i_egress_stall_3_0),
.grant_3_0(egress_grant_3_0),
.req_3_1(egress_valid_3_1),
.stall_3_1(i_egress_stall_3_1),
.grant_3_1(egress_grant_3_1),
.req_3_2(egress_valid_3_2),
.stall_3_2(i_egress_stall_3_2),
.grant_3_2(egress_grant_3_2),
.req_3_3(egress_valid_3_3),
.stall_3_3(i_egress_stall_3_3),
.grant_3_3(egress_grant_3_3)
);
// egress port signals
// group 0
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_0_0 <= 0;
o_egress_data_0_0 <= 0;
end
else if(~i_egress_stall_0_0) begin
o_egress_valid_0_0 <= |egress_grant_0_0;
case(egress_grant_0_0)
4'b0001:o_egress_data_0_0 <= egress_data_0_0[0];
4'b0010:o_egress_data_0_0 <= egress_data_0_0[1];
4'b0100:o_egress_data_0_0 <= egress_data_0_0[2];
4'b1000:o_egress_data_0_0 <= egress_data_0_0[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_0_1 <= 0;
o_egress_data_0_1 <= 0;
end
else if(~i_egress_stall_0_1) begin
o_egress_valid_0_1 <= |egress_grant_0_1;
case(egress_grant_0_1)
4'b0001:o_egress_data_0_1 <= egress_data_0_1[0];
4'b0010:o_egress_data_0_1 <= egress_data_0_1[1];
4'b0100:o_egress_data_0_1 <= egress_data_0_1[2];
4'b1000:o_egress_data_0_1 <= egress_data_0_1[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_0_2 <= 0;
o_egress_data_0_2 <= 0;
end
else if(~i_egress_stall_0_2) begin
o_egress_valid_0_2 <= |egress_grant_0_2;
case(egress_grant_0_2)
4'b0001:o_egress_data_0_2 <= egress_data_0_2[0];
4'b0010:o_egress_data_0_2 <= egress_data_0_2[1];
4'b0100:o_egress_data_0_2 <= egress_data_0_2[2];
4'b1000:o_egress_data_0_2 <= egress_data_0_2[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_0_3 <= 0;
o_egress_data_0_3 <= 0;
end
else if(~i_egress_stall_0_3) begin
o_egress_valid_0_3 <= |egress_grant_0_3;
case(egress_grant_0_3)
4'b0001:o_egress_data_0_3 <= egress_data_0_3[0];
4'b0010:o_egress_data_0_3 <= egress_data_0_3[1];
4'b0100:o_egress_data_0_3 <= egress_data_0_3[2];
4'b1000:o_egress_data_0_3 <= egress_data_0_3[3];
endcase
end
end
// group 1
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_1_0 <= 0;
o_egress_data_1_0 <= 0;
end
else if(~i_egress_stall_1_0) begin
o_egress_valid_1_0 <= |egress_grant_1_0;
case(egress_grant_1_0)
4'b0001:o_egress_data_1_0 <= egress_data_1_0[0];
4'b0010:o_egress_data_1_0 <= egress_data_1_0[1];
4'b0100:o_egress_data_1_0 <= egress_data_1_0[2];
4'b1000:o_egress_data_1_0 <= egress_data_1_0[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_1_1 <= 0;
o_egress_data_1_1 <= 0;
end
else if(~i_egress_stall_1_1) begin
o_egress_valid_1_1 <= |egress_grant_1_1;
case(egress_grant_1_1)
4'b0001:o_egress_data_1_1 <= egress_data_1_1[0];
4'b0010:o_egress_data_1_1 <= egress_data_1_1[1];
4'b0100:o_egress_data_1_1 <= egress_data_1_1[2];
4'b1000:o_egress_data_1_1 <= egress_data_1_1[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_1_2 <= 0;
o_egress_data_1_2 <= 0;
end
else if(~i_egress_stall_1_2) begin
o_egress_valid_1_2 <= |egress_grant_1_2;
case(egress_grant_1_2)
4'b0001:o_egress_data_1_2 <= egress_data_1_2[0];
4'b0010:o_egress_data_1_2 <= egress_data_1_2[1];
4'b0100:o_egress_data_1_2 <= egress_data_1_2[2];
4'b1000:o_egress_data_1_2 <= egress_data_1_2[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_1_3 <= 0;
o_egress_data_1_3 <= 0;
end
else if(~i_egress_stall_1_3) begin
o_egress_valid_1_3 <= |egress_grant_1_3;
case(egress_grant_1_3)
4'b0001:o_egress_data_1_3 <= egress_data_1_3[0];
4'b0010:o_egress_data_1_3 <= egress_data_1_3[1];
4'b0100:o_egress_data_1_3 <= egress_data_1_3[2];
4'b1000:o_egress_data_1_3 <= egress_data_1_3[3];
endcase
end
end
// group 2
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_2_0 <= 0;
o_egress_data_2_0 <= 0;
end
else if(~i_egress_stall_2_0) begin
o_egress_valid_2_0 <= |egress_grant_2_0;
case(egress_grant_2_0)
4'b0001:o_egress_data_2_0 <= egress_data_2_0[0];
4'b0010:o_egress_data_2_0 <= egress_data_2_0[1];
4'b0100:o_egress_data_2_0 <= egress_data_2_0[2];
4'b1000:o_egress_data_2_0 <= egress_data_2_0[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_2_1 <= 0;
o_egress_data_2_1 <= 0;
end
else if(~i_egress_stall_2_1) begin
o_egress_valid_2_1 <= |egress_grant_2_1;
case(egress_grant_2_1)
4'b0001:o_egress_data_2_1 <= egress_data_2_1[0];
4'b0010:o_egress_data_2_1 <= egress_data_2_1[1];
4'b0100:o_egress_data_2_1 <= egress_data_2_1[2];
4'b1000:o_egress_data_2_1 <= egress_data_2_1[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_2_2 <= 0;
o_egress_data_2_2 <= 0;
end
else if(~i_egress_stall_2_2) begin
o_egress_valid_2_2 <= |egress_grant_2_2;
case(egress_grant_2_2)
4'b0001:o_egress_data_2_2 <= egress_data_2_2[0];
4'b0010:o_egress_data_2_2 <= egress_data_2_2[1];
4'b0100:o_egress_data_2_2 <= egress_data_2_2[2];
4'b1000:o_egress_data_2_2 <= egress_data_2_2[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_2_3 <= 0;
o_egress_data_2_3 <= 0;
end
else if(~i_egress_stall_2_3) begin
o_egress_valid_2_3 <= |egress_grant_2_3;
case(egress_grant_2_3)
4'b0001:o_egress_data_2_3 <= egress_data_2_3[0];
4'b0010:o_egress_data_2_3 <= egress_data_2_3[1];
4'b0100:o_egress_data_2_3 <= egress_data_2_3[2];
4'b1000:o_egress_data_2_3 <= egress_data_2_3[3];
endcase
end
end
// group 3
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_3_0 <= 0;
o_egress_data_3_0 <= 0;
end
else if(~i_egress_stall_3_0) begin
o_egress_valid_3_0 <= |egress_grant_3_0;
case(egress_grant_3_0)
4'b0001:o_egress_data_3_0 <= egress_data_3_0[0];
4'b0010:o_egress_data_3_0 <= egress_data_3_0[1];
4'b0100:o_egress_data_3_0 <= egress_data_3_0[2];
4'b1000:o_egress_data_3_0 <= egress_data_3_0[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_3_1 <= 0;
o_egress_data_3_1 <= 0;
end
else if(~i_egress_stall_3_1) begin
o_egress_valid_3_1 <= |egress_grant_3_1;
case(egress_grant_3_1)
4'b0001:o_egress_data_3_1 <= egress_data_3_1[0];
4'b0010:o_egress_data_3_1 <= egress_data_3_1[1];
4'b0100:o_egress_data_3_1 <= egress_data_3_1[2];
4'b1000:o_egress_data_3_1 <= egress_data_3_1[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_3_2 <= 0;
o_egress_data_3_2 <= 0;
end
else if(~i_egress_stall_3_2) begin
o_egress_valid_3_2 <= |egress_grant_3_2;
case(egress_grant_3_2)
4'b0001:o_egress_data_3_2 <= egress_data_3_2[0];
4'b0010:o_egress_data_3_2 <= egress_data_3_2[1];
4'b0100:o_egress_data_3_2 <= egress_data_3_2[2];
4'b1000:o_egress_data_3_2 <= egress_data_3_2[3];
endcase
end
end
always@(posedge clk_80M )begin
if(clr_80M)begin
o_egress_valid_3_3 <= 0;
o_egress_data_3_3 <= 0;
end
else if(~i_egress_stall_3_3) begin
o_egress_valid_3_3 <= |egress_grant_3_3;
case(egress_grant_3_3)
4'b0001:o_egress_data_3_3 <= egress_data_3_3[0];
4'b0010:o_egress_data_3_3 <= egress_data_3_3[1];
4'b0100:o_egress_data_3_3 <= egress_data_3_3[2];
4'b1000:o_egress_data_3_3 <= egress_data_3_3[3];
endcase
end
end
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_tile.v
// Description : Grouped Shared Memory first level switch --- gsm-tile.
// each tile is responsible for data switching of 4 ingress
// and 4 egress links
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-27 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_tile
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter GSIZE = 4, // group size, number of gsm_unit in each group
parameter LOG_MWIDTH = 2,
parameter DWIDTH = 128, // data width = 16 bytes
parameter AWIDTH = 7 // 2 BRAM = total 512 cells, each port is allocated 128 cells
)
(
//** global
input wire clk_320M,
input wire clr_320M,
input wire clk_80M,
input wire clr_80M,
input wire rst_n,
//** 4 ingress ports
input wire i_ingress_valid0,
input wire i_ingress_header0,
input wire [DWIDTH-1:0] i_ingress_data0,
input wire i_ingress_valid1,
input wire i_ingress_header1,
input wire [DWIDTH-1:0] i_ingress_data1,
input wire i_ingress_valid2,
input wire i_ingress_header2,
input wire [DWIDTH-1:0] i_ingress_data2,
input wire i_ingress_valid3,
input wire i_ingress_header3,
input wire [DWIDTH-1:0] i_ingress_data3,
//** 16 egress ports
// group 0
input wire i_egress_rd_0_0,
output wire o_egress_valid_0_0,
output wire [DWIDTH-1:0] o_egress_data_0_0,
input wire i_egress_rd_0_1,
output wire o_egress_valid_0_1,
output wire [DWIDTH-1:0] o_egress_data_0_1,
input wire i_egress_rd_0_2,
output wire o_egress_valid_0_2,
output wire [DWIDTH-1:0] o_egress_data_0_2,
input wire i_egress_rd_0_3,
output wire o_egress_valid_0_3,
output wire [DWIDTH-1:0] o_egress_data_0_3,
// group 1
input wire i_egress_rd_1_0,
output wire o_egress_valid_1_0,
output wire [DWIDTH-1:0] o_egress_data_1_0,
input wire i_egress_rd_1_1,
output wire o_egress_valid_1_1,
output wire [DWIDTH-1:0] o_egress_data_1_1,
input wire i_egress_rd_1_2,
output wire o_egress_valid_1_2,
output wire [DWIDTH-1:0] o_egress_data_1_2,
input wire i_egress_rd_1_3,
output wire o_egress_valid_1_3,
output wire [DWIDTH-1:0] o_egress_data_1_3,
// group 2
input wire i_egress_rd_2_0,
output wire o_egress_valid_2_0,
output wire [DWIDTH-1:0] o_egress_data_2_0,
input wire i_egress_rd_2_1,
output wire o_egress_valid_2_1,
output wire [DWIDTH-1:0] o_egress_data_2_1,
input wire i_egress_rd_2_2,
output wire o_egress_valid_2_2,
output wire [DWIDTH-1:0] o_egress_data_2_2,
input wire i_egress_rd_2_3,
output wire o_egress_valid_2_3,
output wire [DWIDTH-1:0] o_egress_data_2_3,
// group 3
input wire i_egress_rd_3_0,
output wire o_egress_valid_3_0,
output wire [DWIDTH-1:0] o_egress_data_3_0,
input wire i_egress_rd_3_1,
output wire o_egress_valid_3_1,
output wire [DWIDTH-1:0] o_egress_data_3_1,
input wire i_egress_rd_3_2,
output wire o_egress_valid_3_2,
output wire [DWIDTH-1:0] o_egress_data_3_2,
input wire i_egress_rd_3_3,
output wire o_egress_valid_3_3,
output wire [DWIDTH-1:0] o_egress_data_3_3
);
localparam MAX_PKT_LEN = 7; // maximum packet length in unit of 16-byte data cell
localparam LOC_PKT_LEN = 24; // the bit location of packet length field in the 16-byte data cell
localparam LOC_DEST_IP = 32; // the bit location of the destination ip field in the data cell
// ---------------------------------------------------------------------
// wire, registers and genvar
// ---------------------------------------------------------------------
genvar i;
integer j;
reg [MWIDTH-1:0] common_sel;
//reg [DWIDTH-1:0] common_data;
reg [DWIDTH-1:0] common_data_reg[GSIZE-1:0];
//reg [MWIDTH-1:0] common_sel_reg[GSIZE-1:0];
reg [DWIDTH-1:0] ingress_data [MWIDTH-1:0];
wire [DWIDTH-1:0] asyn_rd_data [MWIDTH-1:0];
reg [DWIDTH-1:0] asyn_rd_data_reg [MWIDTH-1:0];
wire [MWIDTH-1:0] asyn_empty;
wire [MAX_PKT_LEN-1:0] ingress_pkt_length0, ingress_pkt_length1, ingress_pkt_length2, ingress_pkt_length3;
wire [31:0] ingress_dest_ip0, ingress_dest_ip1, ingress_dest_ip2, ingress_dest_ip3;
// 0
wire [MWIDTH-1:0] gsm_multicast0 [GSIZE-1:0];
wire [AWIDTH-1:0] gsm_cell_addr0 [GSIZE-1:0];
wire [GSIZE-1:0] gsm_wr_en0 ;
wire [GSIZE-1:0] hmp_rd0, hmp_valid0, bf_free_flag0;
wire [AWIDTH-1:0] hmp_addr0 [GSIZE-1:0];
wire [GSIZE-1:0] egress_rd0;
wire [GSIZE-1:0] egress_valid0;
wire [DWIDTH-1:0] egress_data0[GSIZE-1:0];
// 1
wire [MWIDTH-1:0] gsm_multicast1 [GSIZE-1:0];
wire [AWIDTH-1:0] gsm_cell_addr1 [GSIZE-1:0];
wire [GSIZE-1:0] gsm_wr_en1 ;
wire [GSIZE-1:0] hmp_rd1, hmp_valid1, bf_free_flag1;
wire [AWIDTH-1:0] hmp_addr1 [GSIZE-1:0];
wire [GSIZE-1:0] egress_rd1;
wire [GSIZE-1:0] egress_valid1;
wire [DWIDTH-1:0] egress_data1[GSIZE-1:0];
// 2
wire [MWIDTH-1:0] gsm_multicast2 [GSIZE-1:0];
wire [AWIDTH-1:0] gsm_cell_addr2 [GSIZE-1:0];
wire [GSIZE-1:0] gsm_wr_en2 ;
wire [GSIZE-1:0] hmp_rd2, hmp_valid2, bf_free_flag2;
wire [AWIDTH-1:0] hmp_addr2 [GSIZE-1:0];
wire [GSIZE-1:0] egress_rd2;
wire [GSIZE-1:0] egress_valid2;
wire [DWIDTH-1:0] egress_data2[GSIZE-1:0];
// 3
wire [MWIDTH-1:0] gsm_multicast3 [GSIZE-1:0];
wire [AWIDTH-1:0] gsm_cell_addr3 [GSIZE-1:0];
wire [GSIZE-1:0] gsm_wr_en3 ;
wire [GSIZE-1:0] hmp_rd3, hmp_valid3, bf_free_flag3;
wire [AWIDTH-1:0] hmp_addr3 [GSIZE-1:0];
wire [GSIZE-1:0] egress_rd3;
wire [GSIZE-1:0] egress_valid3;
wire [DWIDTH-1:0] egress_data3[GSIZE-1:0];
// ---------------------------------------------------------------------
// logic starts here...
// ---------------------------------------------------------------------
// the mux logic implements a 4-to-1 multiplexer running at 320M clock domain
// that cycle through each of the 4 data ports, so that they all get served in
// every cycle of the 80M clock domain, the selected data is then broadcast
// to every unit in this GSM group
// the hardware malloc module has a 2 stage pipeline,
// therefore, the data bus also need to be registered
// once more to match the pipeline processing
always@(posedge clk_80M )begin
if(clr_80M)
for(j=0;j<MWIDTH;j=j+1)
ingress_data[j] <= 0;
else begin
ingress_data[0] <= i_ingress_data0;
ingress_data[1] <= i_ingress_data1;
ingress_data[2] <= i_ingress_data2;
ingress_data[3] <= i_ingress_data3;
end
end
generate
for(i=0;i<MWIDTH;i=i+1) begin: DATA_PORT_MUX
asyn_fifo
#(
.DBITWIDTH(DWIDTH), // address + multicast vector + write enable
.ABITWIDTH(2) // 4 entries should be enough to accommodate the pipeline
)
ingress_data
(
// global
.clk_a(clk_80M),
.clk_b(clk_320M),
.rst_n(rst_n),
.clr_a(clr_80M),
.clr_b(clr_320M),
// FIFO write interface
.write(1'b1),
.write_data(ingress_data[i]),
// FIFO read interface
.read(~asyn_empty[i]),
.read_data(asyn_rd_data[i]),
// FIFO status signals
.empty(asyn_empty[i]),
.almost_full(),
.full()
);
always@(posedge clk_320M )begin
if(clr_320M)
asyn_rd_data_reg[i] <= 0;
else
asyn_rd_data_reg[i] <= asyn_rd_data[i];
end
end
endgenerate
// a 4-to-1 multiplexer
always@(posedge clk_320M )begin
if(clr_320M)
common_sel <= 1;
else
common_sel <= {common_sel,common_sel[MWIDTH-1]};
end
always@(posedge clk_320M )begin
if(clr_320M)begin
common_data_reg[0] <= 0;
end
else begin
case (common_sel)
4'b0001:common_data_reg[0] <= asyn_rd_data_reg[0];
4'b0010:common_data_reg[0] <= asyn_rd_data_reg[1];
4'b0100:common_data_reg[0] <= asyn_rd_data_reg[2];
4'b1000:common_data_reg[0] <= asyn_rd_data_reg[3];
endcase
end
end
generate
for(i=1;i<GSIZE;i=i+1) begin: COMMON_DATA_PIPELINE
always@(posedge clk_320M )begin
if(clr_320M)begin
common_data_reg[i] <= 0;
end
else begin
common_data_reg[i] <= common_data_reg[i-1];
end
end
end
endgenerate
// the following generated code construct the GSM group structure.
// each group contains GSIZE (4) gsm units, each unit talks to 4
// hardware malloc logic that manages one of the 4 ingress ports
// the control data embedded in each of 4 ingress port is broadcast
// to 4 hardware malloc module. and the hardware malloc module
// decides whether the ingress data is to be dropped or buffed
// into the gsm switch unit.
assign ingress_pkt_length0 = i_ingress_data0[MAX_PKT_LEN+LOC_PKT_LEN-1:LOC_PKT_LEN];
assign ingress_pkt_length1 = i_ingress_data1[MAX_PKT_LEN+LOC_PKT_LEN-1:LOC_PKT_LEN];
assign ingress_pkt_length2 = i_ingress_data2[MAX_PKT_LEN+LOC_PKT_LEN-1:LOC_PKT_LEN];
assign ingress_pkt_length3 = i_ingress_data3[MAX_PKT_LEN+LOC_PKT_LEN-1:LOC_PKT_LEN];
assign ingress_dest_ip0 = i_ingress_data0[32+LOC_DEST_IP-1:LOC_DEST_IP];
assign ingress_dest_ip1 = i_ingress_data1[32+LOC_DEST_IP-1:LOC_DEST_IP];
assign ingress_dest_ip2 = i_ingress_data2[32+LOC_DEST_IP-1:LOC_DEST_IP];
assign ingress_dest_ip3 = i_ingress_data3[32+LOC_DEST_IP-1:LOC_DEST_IP];
generate
for(i=0;i<GSIZE;i=i+1)begin : GSM_UNIT_GEN
hw_malloc
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.LOG_MWIDTH(LOG_MWIDTH),
.MAX_PKT_LEN(7), // maximum packet lenght in terms of number of 16-byte cells
.AWIDTH(AWIDTH), // 2 BRAM = total 512 cells, each port is allocated 128 cells
.HM_OFFSET(i*MWIDTH) // offset for the multicast vectore
) hw_malloc_inst0
(
// global
.clk(clk_80M),
.rst_n(rst_n),
.clr(clr_80M),
// ingress port
.i_ingress_pkt_length(ingress_pkt_length0),
.i_ingress_dest_ip(ingress_dest_ip0),
.i_ingress_valid(i_ingress_valid0),
.i_ingress_header(i_ingress_header0),
// output to GSM
.o_gsm_multicast(gsm_multicast0[i]),
.o_gsm_cell_addr(gsm_cell_addr0[i]),
.o_gsm_wr_en(gsm_wr_en0[i]),
// input from GSM
.o_hmp_rd(hmp_rd0[i]),
.i_hmp_valid(hmp_valid0[i]),
.i_hmp_addr(hmp_addr0[i]),
.i_bf_free_flag(bf_free_flag0[i])
);
hw_malloc
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.LOG_MWIDTH(LOG_MWIDTH),
.MAX_PKT_LEN(7), // maximum packet lenght in terms of number of 16-byte cells
.AWIDTH(AWIDTH), // 2 BRAM = total 512 cells, each port is allocated 128 cells
.HM_OFFSET(i*MWIDTH) // offset for the multicast vectore
) hw_malloc_inst1
(
// global
.clk(clk_80M),
.rst_n(rst_n),
.clr(clr_80M),
// ingress port
.i_ingress_pkt_length(ingress_pkt_length1),
.i_ingress_dest_ip(ingress_dest_ip1),
.i_ingress_valid(i_ingress_valid1),
.i_ingress_header(i_ingress_header1),
// output to GSM
.o_gsm_multicast(gsm_multicast1[i]),
.o_gsm_cell_addr(gsm_cell_addr1[i]),
.o_gsm_wr_en(gsm_wr_en1[i]),
// input from GSM
.o_hmp_rd(hmp_rd1[i]),
.i_hmp_valid(hmp_valid1[i]),
.i_hmp_addr(hmp_addr1[i]),
.i_bf_free_flag(bf_free_flag1[i])
);
hw_malloc
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.LOG_MWIDTH(LOG_MWIDTH),
.MAX_PKT_LEN(7), // maximum packet lenght in terms of number of 16-byte cells
.AWIDTH(AWIDTH), // 2 BRAM = total 512 cells, each port is allocated 128 cells
.HM_OFFSET(i*MWIDTH) // offset for the multicast vectore
) hw_malloc_inst2
(
// global
.clk(clk_80M),
.rst_n(rst_n),
.clr(clr_80M),
// ingress port
.i_ingress_pkt_length(ingress_pkt_length2),
.i_ingress_dest_ip(ingress_dest_ip2),
.i_ingress_valid(i_ingress_valid2),
.i_ingress_header(i_ingress_header2),
// output to GSM
.o_gsm_multicast(gsm_multicast2[i]),
.o_gsm_cell_addr(gsm_cell_addr2[i]),
.o_gsm_wr_en(gsm_wr_en2[i]),
// input from GSM
.o_hmp_rd(hmp_rd2[i]),
.i_hmp_valid(hmp_valid2[i]),
.i_hmp_addr(hmp_addr2[i]),
.i_bf_free_flag(bf_free_flag2[i])
);
hw_malloc
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.LOG_MWIDTH(LOG_MWIDTH),
.MAX_PKT_LEN(7), // maximum packet lenght in terms of number of 16-byte cells
.AWIDTH(AWIDTH), // 2 BRAM = total 512 cells, each port is allocated 128 cells
.HM_OFFSET(i*MWIDTH) // offset for the multicast vectore
) hw_malloc_inst3
(
// global
.clk(clk_80M),
.rst_n(rst_n),
.clr(clr_80M),
// ingress port
.i_ingress_pkt_length(ingress_pkt_length3),
.i_ingress_dest_ip(ingress_dest_ip3),
.i_ingress_valid(i_ingress_valid3),
.i_ingress_header(i_ingress_header3),
// output to GSM
.o_gsm_multicast(gsm_multicast3[i]),
.o_gsm_cell_addr(gsm_cell_addr3[i]),
.o_gsm_wr_en(gsm_wr_en3[i]),
// input from GSM
.o_hmp_rd(hmp_rd3[i]),
.i_hmp_valid(hmp_valid3[i]),
.i_hmp_addr(hmp_addr3[i]),
.i_bf_free_flag(bf_free_flag3[i])
);
gsm_unit_ex
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.LOG_MWIDTH(LOG_MWIDTH),
.DWIDTH(DWIDTH), // data width = 16 bytes
.AWIDTH(AWIDTH), // 2 BRAM = total 512 cells, each port is allocated 128 cells
.PIPE_STAGE(i)
)gsm_unit_inst
(
// global
.clk_320M(clk_320M),
.clr_320M(clr_320M),
.clk_80M(clk_80M),
.clr_80M(clr_80M),
.rst_n(rst_n),
// ingress malloc ports
.i_wr_en0(gsm_wr_en0[i]),
.i_wr_addr0(gsm_cell_addr0[i]),
.i_multicast0(gsm_multicast0[i]),
.i_wr_en1(gsm_wr_en1[i]),
.i_wr_addr1(gsm_cell_addr1[i]),
.i_multicast1(gsm_multicast1[i]),
.i_wr_en2(gsm_wr_en2[i]),
.i_wr_addr2(gsm_cell_addr2[i]),
.i_multicast2(gsm_multicast2[i]),
.i_wr_en3(gsm_wr_en3[i]),
.i_wr_addr3(gsm_cell_addr3[i]),
.i_multicast3(gsm_multicast3[i]),
// egress ports
.i_egress_rd0(egress_rd0[i]),
.o_egress_valid0(egress_valid0[i]),
.o_egress_data0(egress_data0[i]),
.i_egress_rd1(egress_rd1[i]),
.o_egress_valid1(egress_valid1[i]),
.o_egress_data1(egress_data1[i]),
.i_egress_rd2(egress_rd2[i]),
.o_egress_valid2(egress_valid2[i]),
.o_egress_data2(egress_data2[i]),
.i_egress_rd3(egress_rd3[i]),
.o_egress_valid3(egress_valid3[i]),
.o_egress_data3(egress_data3[i]),
// buffer free interface
.i_hmp_rd0(hmp_rd0[i]), // read a pointer from the Hardware Malloc Pipe
.o_hmp_valid0(hmp_valid0[i]), // Hardware Malloc Pipe is not empty and has available pointer
.o_hmp_addr0(hmp_addr0[i]), // the pointer to the available buffer space
.o_bf_free_flag0(bf_free_flag0[i]), // signal that a pointer has just been freed
.i_hmp_rd1(hmp_rd1[i]),
.o_hmp_valid1(hmp_valid1[i]),
.o_hmp_addr1(hmp_addr1[i]),
.o_bf_free_flag1(bf_free_flag1[i]),
.i_hmp_rd2(hmp_rd2[i]),
.o_hmp_valid2(hmp_valid2[i]),
.o_hmp_addr2(hmp_addr2[i]),
.o_bf_free_flag2(bf_free_flag2[i]),
.i_hmp_rd3(hmp_rd3[i]),
.o_hmp_valid3(hmp_valid3[i]),
.o_hmp_addr3(hmp_addr3[i]),
.o_bf_free_flag3(bf_free_flag3[i]),
// common data bus (at 320Mhz clock domain)
//.i_common_sel(common_sel),
.i_common_wr_data(common_data_reg[i])
);
end // end for
endgenerate
// egress port signals
// egress_rd
assign egress_rd0[0] = i_egress_rd_0_0;
assign egress_rd0[1] = i_egress_rd_1_0;
assign egress_rd0[2] = i_egress_rd_2_0;
assign egress_rd0[3] = i_egress_rd_3_0;
assign egress_rd1[0] = i_egress_rd_0_1;
assign egress_rd1[1] = i_egress_rd_1_1;
assign egress_rd1[2] = i_egress_rd_2_1;
assign egress_rd1[3] = i_egress_rd_3_1;
assign egress_rd2[0] = i_egress_rd_0_2;
assign egress_rd2[1] = i_egress_rd_1_2;
assign egress_rd2[2] = i_egress_rd_2_2;
assign egress_rd2[3] = i_egress_rd_3_2;
assign egress_rd3[0] = i_egress_rd_0_3;
assign egress_rd3[1] = i_egress_rd_1_3;
assign egress_rd3[2] = i_egress_rd_2_3;
assign egress_rd3[3] = i_egress_rd_3_3;
// egress_valid
assign o_egress_valid_0_0 = egress_valid0[0];
assign o_egress_valid_1_0 = egress_valid0[1];
assign o_egress_valid_2_0 = egress_valid0[2];
assign o_egress_valid_3_0 = egress_valid0[3];
assign o_egress_valid_0_1 = egress_valid1[0];
assign o_egress_valid_1_1 = egress_valid1[1];
assign o_egress_valid_2_1 = egress_valid1[2];
assign o_egress_valid_3_1 = egress_valid1[3];
assign o_egress_valid_0_2 = egress_valid2[0];
assign o_egress_valid_1_2 = egress_valid2[1];
assign o_egress_valid_2_2 = egress_valid2[2];
assign o_egress_valid_3_2 = egress_valid2[3];
assign o_egress_valid_0_3 = egress_valid3[0];
assign o_egress_valid_1_3 = egress_valid3[1];
assign o_egress_valid_2_3 = egress_valid3[2];
assign o_egress_valid_3_3 = egress_valid3[3];
// egress_data
assign o_egress_data_0_0 = egress_data0[0];
assign o_egress_data_1_0 = egress_data0[1];
assign o_egress_data_2_0 = egress_data0[2];
assign o_egress_data_3_0 = egress_data0[3];
assign o_egress_data_0_1 = egress_data1[0];
assign o_egress_data_1_1 = egress_data1[1];
assign o_egress_data_2_1 = egress_data1[2];
assign o_egress_data_3_1 = egress_data1[3];
assign o_egress_data_0_2 = egress_data2[0];
assign o_egress_data_1_2 = egress_data2[1];
assign o_egress_data_2_2 = egress_data2[2];
assign o_egress_data_3_2 = egress_data2[3];
assign o_egress_data_0_3 = egress_data3[0];
assign o_egress_data_1_3 = egress_data3[1];
assign o_egress_data_2_3 = egress_data3[2];
assign o_egress_data_3_3 = egress_data3[3];
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_unit.v
// Description : grouped-share-memory switch memory unit
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-20 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_unit
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter LOG_MWIDTH = 2,
parameter DWIDTH = 128, // data width = 16 bytes
parameter AWIDTH = 7 // 2 BRAM = total 512 cells, each port is allocated 128 cells
)
(
// global
input wire clk_320M,
input wire clr_320M,
input wire clk_80M,
input wire clr_80M,
input wire rst_n,
// ingress malloc ports
input wire i_wr_en0,
input wire [AWIDTH-1:0] i_wr_addr0,
input wire [MWIDTH-1:0] i_multicast0,
input wire i_wr_en1,
input wire [AWIDTH-1:0] i_wr_addr1,
input wire [MWIDTH-1:0] i_multicast1,
input wire i_wr_en2,
input wire [AWIDTH-1:0] i_wr_addr2,
input wire [MWIDTH-1:0] i_multicast2,
input wire i_wr_en3,
input wire [AWIDTH-1:0] i_wr_addr3,
input wire [MWIDTH-1:0] i_multicast3,
// egress ports
input wire i_egress_rd0,
output wire o_egress_valid0,
output wire [DWIDTH-1:0] o_egress_data0,
input wire i_egress_rd1,
output wire o_egress_valid1,
output wire [DWIDTH-1:0] o_egress_data1,
input wire i_egress_rd2,
output wire o_egress_valid2,
output wire [DWIDTH-1:0] o_egress_data2,
input wire i_egress_rd3,
output wire o_egress_valid3,
output wire [DWIDTH-1:0] o_egress_data3,
// buffer free interface
output wire o_buf_free0,
output wire [AWIDTH-1:0] o_buf_free_addr0,
output wire o_buf_free1,
output wire [AWIDTH-1:0] o_buf_free_addr1,
output wire o_buf_free2,
output wire [AWIDTH-1:0] o_buf_free_addr2,
output wire o_buf_free3,
output wire [AWIDTH-1:0] o_buf_free_addr3,
// common data bus (at 320Mhz clock domain)
input wire [MWIDTH-1:0] i_common_sel,
input wire [DWIDTH-1:0] i_common_wr_data
);
// ---------------------------------------------------------------------
// wire, registers and integer
// ---------------------------------------------------------------------
genvar i;
wire [AWIDTH+MWIDTH:0] ingress_data[MWIDTH-1:0];
wire [AWIDTH+MWIDTH:0] asyn_rd_data[MWIDTH-1:0];
wire [MWIDTH-1:0] asyn_empty;
reg [AWIDTH+MWIDTH+LOG_MWIDTH:0] gsm_ctl_data;
wire gsm_wr_en;
wire [AWIDTH+LOG_MWIDTH-1:0] gsm_wr_addr;
wire [MWIDTH-1:0] gsm_multicast;
wire [MWIDTH-1:0] egress_wr_sel;
wire [DWIDTH-1:0] egress_wr_data;
wire [DWIDTH-1:0] egress_rd_data[MWIDTH-1:0];
wire [MWIDTH-1:0] egress_empty, egress_almost_full;
wire [MWIDTH-1:0] egress_rd;
wire [MWIDTH-1:0] buf_free_sel, buf_free_empty, buf_free_full;
wire [AWIDTH+LOG_MWIDTH-1:0] buf_free_addr;
wire [AWIDTH-1:0] buf_out_addr[MWIDTH-1:0];
// ---------------------------------------------------------------------
// logic starts here...
// ---------------------------------------------------------------------
assign ingress_data[0] = {i_wr_addr0,i_multicast0,i_wr_en0};
assign ingress_data[1] = {i_wr_addr1,i_multicast1,i_wr_en1};
assign ingress_data[2] = {i_wr_addr2,i_multicast2,i_wr_en2};
assign ingress_data[3] = {i_wr_addr3,i_multicast3,i_wr_en3};
generate
for(i=0;i<MWIDTH;i=i+1) begin: CLOCK_DOMAIN_CROSSING
asyn_fifo
#(
.DBITWIDTH(AWIDTH+MWIDTH), // address + multicast vector + write enable
.ABITWIDTH(2) // 4 entries should be enough to accommodate the pipeline
)
ingress_ctrl
(
// global
.clk_a(clk_80M),
.clk_b(clk_320M),
.rst_n(rst_n),
.clr_a(clr_80M),
.clr_b(clr_320M),
// FIFO write interface
.write(1'b1),
.write_data(ingress_data[i]),
// FIFO read interface
.read(~asyn_empty[i]),
.read_data(asyn_rd_data[i]),
// FIFO status signals
.empty(asyn_empty[i]),
.almost_full(),
.full()
);
end
endgenerate
// a 4-to-1 multiplexer
always@(posedge clk_320M or negedge rst_n)begin
if(!rst_n)begin
gsm_ctl_data <= 0;
end
else if(clr_320M)begin
gsm_ctl_data <= 0;
end
else
case (i_common_sel)
4'b0001: gsm_ctl_data <= {2'b00,asyn_rd_data[0]};
4'b0010: gsm_ctl_data <= {2'b01,asyn_rd_data[1]};
4'b0100: gsm_ctl_data <= {2'b10,asyn_rd_data[2]};
4'b1000: gsm_ctl_data <= {2'b11,asyn_rd_data[3]};
endcase
end
assign gsm_wr_en = gsm_ctl_data[0];
assign gsm_multicast = gsm_ctl_data[MWIDTH:1];
assign gsm_wr_addr = gsm_ctl_data[AWIDTH+MWIDTH+LOG_MWIDTH:MWIDTH+1];
// centralized memory
gsm_ram
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.LOG_MWIDTH(LOG_MWIDTH),
.DWIDTH(DWIDTH), // data width = 16 bytes
.AWIDTH(AWIDTH+LOG_MWIDTH) // 2 BRAM = total 512 cells
)
central_ram
(
// global
.clk(clk_320M),
.rst_n(rst_n),
.clr(clr_320M),
// input port
.i_wr_en(gsm_wr_en),
.i_wr_addr(gsm_wr_addr),
.i_wr_data(i_common_wr_data),
.i_multicast(gsm_multicast),
// output port
.i_egress_stall(egress_almost_full),
.o_egress_sel(egress_wr_sel),
.o_egress_data(egress_wr_data),
// buffer free
.o_buf_free(buf_free),
.o_buf_free_addr(buf_free_addr)
);
// egress ports
assign egress_rd = {i_egress_rd3,i_egress_rd2,i_egress_rd1,i_egress_rd0};
generate
for(i=0;i<MWIDTH;i=i+1) begin: EGRESS_PORTS
asyn_fifo
#(
.DBITWIDTH(DWIDTH),
.ABITWIDTH(4), // 16 entries
.AF_THRESHOLD(4) // set the almost full threshold to be 4
)
egress_port
(
// global
.clk_a(clk_320M),
.clk_b(clk_80M),
.rst_n(rst_n),
.clr_a(clr_320M),
.clr_b(clr_80M),
// FIFO write interface
.write(egress_wr_sel[i]),
.write_data(egress_wr_data),
// FIFO read interface
.read(egress_rd[i]),
.read_data(egress_rd_data[i]),
// FIFO status signals
.empty(egress_empty[i]),
.almost_full(egress_almost_full[i]),
.full()
);
end
endgenerate
assign o_egress_valid0 = ~egress_empty[0];
assign o_egress_valid1 = ~egress_empty[1];
assign o_egress_valid2 = ~egress_empty[2];
assign o_egress_valid3 = ~egress_empty[3];
assign o_egress_data0 = egress_rd_data[0];
assign o_egress_data1 = egress_rd_data[1];
assign o_egress_data2 = egress_rd_data[2];
assign o_egress_data3 = egress_rd_data[3];
// buffer free interface logic
generate
for(i=0;i<MWIDTH;i=i+1) begin: BUFFER_FREE
asyn_fifo
#(
.DBITWIDTH(DWIDTH),
.ABITWIDTH(4) // 16 entries
)
buf_free
(
// global
.clk_a(clk_320M),
.clk_b(clk_80M),
.rst_n(rst_n),
.clr_a(clr_320M),
.clr_b(clr_80M),
// FIFO write interface
.write(buf_free_sel[i] & ~ buf_free_full[i]),
.write_data(buf_free_addr),
// FIFO read interface
.read(~buf_free_empty[i]),
.read_data(buf_out_addr[i]),
// FIFO status signals
.empty(buf_free_empty[i]),
.almost_full(),
.full(buf_free_full)
);
end
endgenerate
assign o_buf_free0 = ~buf_free_empty[0];
assign o_buf_free1 = ~buf_free_empty[1];
assign o_buf_free2 = ~buf_free_empty[2];
assign o_buf_free3 = ~buf_free_empty[3];
assign o_buf_free_addr0 = buf_out_addr[0];
assign o_buf_free_addr1 = buf_out_addr[1];
assign o_buf_free_addr2 = buf_out_addr[2];
assign o_buf_free_addr3 = buf_out_addr[3];
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_unit.v
// Description : grouped-share-memory switch memory unit
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-20 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_unit_ex
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter LOG_MWIDTH = 2,
parameter DWIDTH = 128, // data width = 16 bytes
parameter AWIDTH = 7, // 2 BRAM = total 512 cells, each port is allocated 128 cells
parameter PIPE_STAGE = 0
)
(
// global
input wire clk_320M,
input wire clr_320M,
input wire clk_80M,
input wire clr_80M,
input wire rst_n,
// ingress malloc ports
input wire i_wr_en0,
input wire [AWIDTH-1:0] i_wr_addr0,
input wire [MWIDTH-1:0] i_multicast0,
input wire i_wr_en1,
input wire [AWIDTH-1:0] i_wr_addr1,
input wire [MWIDTH-1:0] i_multicast1,
input wire i_wr_en2,
input wire [AWIDTH-1:0] i_wr_addr2,
input wire [MWIDTH-1:0] i_multicast2,
input wire i_wr_en3,
input wire [AWIDTH-1:0] i_wr_addr3,
input wire [MWIDTH-1:0] i_multicast3,
// egress ports
input wire i_egress_rd0,
output wire o_egress_valid0,
output wire [DWIDTH-1:0] o_egress_data0,
input wire i_egress_rd1,
output wire o_egress_valid1,
output wire [DWIDTH-1:0] o_egress_data1,
input wire i_egress_rd2,
output wire o_egress_valid2,
output wire [DWIDTH-1:0] o_egress_data2,
input wire i_egress_rd3,
output wire o_egress_valid3,
output wire [DWIDTH-1:0] o_egress_data3,
// buffer free interface
input wire i_hmp_rd0, // read a pointer from the Hardware Malloc Pipe
output wire o_hmp_valid0, // Hardware Malloc Pipe is not empty and has available pointer
output wire [AWIDTH-1:0] o_hmp_addr0, // the pointer to the available buffer space
output wire o_bf_free_flag0, // signal that a pointer has just been freed
input wire i_hmp_rd1,
output wire o_hmp_valid1,
output wire [AWIDTH-1:0] o_hmp_addr1,
output wire o_bf_free_flag1,
input wire i_hmp_rd2,
output wire o_hmp_valid2,
output wire [AWIDTH-1:0] o_hmp_addr2,
output wire o_bf_free_flag2,
input wire i_hmp_rd3,
output wire o_hmp_valid3,
output wire [AWIDTH-1:0] o_hmp_addr3,
output wire o_bf_free_flag3,
// common data bus (at 320Mhz clock domain)
//input wire [MWIDTH-1:0] i_common_sel,
input wire [DWIDTH-1:0] i_common_wr_data
);
localparam BRAM_RD_DELAY = 2;
// ---------------------------------------------------------------------
// wire, registers and genvar
// ---------------------------------------------------------------------
genvar i;
reg [MWIDTH-1:0] gsu_common_sel;
wire [AWIDTH+MWIDTH:0] ingress_data[MWIDTH-1:0];
wire [AWIDTH+MWIDTH:0] asyn_rd_data[MWIDTH-1:0];
reg [AWIDTH+MWIDTH:0] asyn_rd_data_reg[MWIDTH-1:0];
wire [MWIDTH-1:0] asyn_empty;
reg [AWIDTH+MWIDTH+LOG_MWIDTH:0] gsm_ctl_data_reg[PIPE_STAGE:0];
wire [AWIDTH+MWIDTH+LOG_MWIDTH:0] gsm_ctl_data;
wire gsm_wr_en;
wire [AWIDTH+LOG_MWIDTH-1:0] gsm_wr_addr;
wire [MWIDTH-1:0] gsm_multicast;
reg [DWIDTH-1:0] gsm_wr_data;
wire [MWIDTH-1:0] egress_wr_sel;
wire [DWIDTH-1:0] egress_wr_data;
wire [DWIDTH-1:0] egress_rd_data[MWIDTH-1:0];
wire [MWIDTH-1:0] egress_empty, egress_almost_full;
wire [MWIDTH-1:0] egress_rd;
wire [MWIDTH-1:0] buf_free_sel, buf_free_empty, buf_free_full;
wire [AWIDTH+LOG_MWIDTH-1:0] buf_free_addr;
wire [AWIDTH-1:0] buf_out_addr[MWIDTH-1:0];
// ---------------------------------------------------------------------
// logic starts here...
// ---------------------------------------------------------------------
assign ingress_data[0] = {i_wr_addr0,i_multicast0,i_wr_en0};
assign ingress_data[1] = {i_wr_addr1,i_multicast1,i_wr_en1};
assign ingress_data[2] = {i_wr_addr2,i_multicast2,i_wr_en2};
assign ingress_data[3] = {i_wr_addr3,i_multicast3,i_wr_en3};
generate
for(i=0;i<MWIDTH;i=i+1) begin: CLOCK_DOMAIN_CROSSING
asyn_fifo
#(
.DBITWIDTH(AWIDTH+MWIDTH+1), // address + multicast vector + write enable
.ABITWIDTH(2) // 4 entries should be enough to cross clock domain
)
ingress_ctrl
(
// global
.clk_a(clk_80M),
.clk_b(clk_320M),
.rst_n(rst_n),
.clr_a(clr_80M),
.clr_b(clr_320M),
// FIFO write interface
.write(1'b1),
.write_data(ingress_data[i]),
// FIFO read interface
.read(~asyn_empty[i]),
.read_data(asyn_rd_data[i]),
// FIFO status signals
.empty(asyn_empty[i]),
.almost_full(),
.full()
);
always@(posedge clk_320M )begin
if(clr_320M)
asyn_rd_data_reg[i] <= 0;
else
asyn_rd_data_reg[i] <= asyn_rd_data[i];
end
end
endgenerate
// a 4-to-1 multiplexer
always@(posedge clk_320M )begin
if(clr_320M)
gsu_common_sel <= 1;
else
gsu_common_sel <= {gsu_common_sel,gsu_common_sel[MWIDTH-1]};
end
always@(posedge clk_320M )begin
if(clr_320M)begin
gsm_ctl_data_reg[0] <= 0;
end
else begin
case (gsu_common_sel)
4'b0001:gsm_ctl_data_reg[0] <= {2'b00,asyn_rd_data_reg[0]};
4'b0010:gsm_ctl_data_reg[0] <= {2'b01,asyn_rd_data_reg[1]};
4'b0100:gsm_ctl_data_reg[0] <= {2'b10,asyn_rd_data_reg[2]};
4'b1000:gsm_ctl_data_reg[0] <= {2'b11,asyn_rd_data_reg[3]};
default:gsm_ctl_data_reg[0] <= 0;
endcase
end
end
generate
for(i=1;i<=PIPE_STAGE;i=i+1) begin: GSM_CTL_DATA_PIPE
always@(posedge clk_320M )begin
if(clr_320M)begin
gsm_ctl_data_reg[i] <= 0;
end
else
gsm_ctl_data_reg[i] <= gsm_ctl_data_reg[i-1];
end
end
endgenerate
assign gsm_ctl_data = gsm_ctl_data_reg[PIPE_STAGE];
assign gsm_wr_en = gsm_ctl_data[0];
assign gsm_multicast = gsm_ctl_data[MWIDTH:1];
assign gsm_wr_addr = gsm_ctl_data[AWIDTH+MWIDTH+LOG_MWIDTH:MWIDTH+1];
// centralized memory
gsm_ram
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.LOG_MWIDTH(LOG_MWIDTH),
.DWIDTH(DWIDTH), // data width = 16 bytes
.AWIDTH(AWIDTH+LOG_MWIDTH) // 2 BRAM = total 512 cells
)
central_ram
(
// global
.clk(clk_320M),
.rst_n(rst_n),
.clr(clr_320M),
// input port
.i_wr_en(gsm_wr_en),
.i_wr_addr(gsm_wr_addr),
.i_wr_data(i_common_wr_data),
.i_multicast(gsm_multicast),
// output port
.i_egress_stall(egress_almost_full),
.o_egress_sel(egress_wr_sel),
.o_egress_data(egress_wr_data),
// buffer free
.o_buf_free(buf_free),
.o_buf_free_addr(buf_free_addr)
);
// egress ports
assign egress_rd = {i_egress_rd3,i_egress_rd2,i_egress_rd1,i_egress_rd0};
generate
for(i=0;i<MWIDTH;i=i+1) begin: EGRESS_PORTS
asyn_fifo
#(
.DBITWIDTH(DWIDTH),
.ABITWIDTH(4), // 16 entries
.AF_THRESHOLD(4) // set the almost full threshold to be 4
)
egress_port
(
// global
.clk_a(clk_320M),
.clk_b(clk_80M),
.rst_n(rst_n),
.clr_a(clr_320M),
.clr_b(clr_80M),
// FIFO write interface
.write(egress_wr_sel[i]),
.write_data(egress_wr_data),
// FIFO read interface
.read(egress_rd[i]),
.read_data(egress_rd_data[i]),
// FIFO status signals
.empty(egress_empty[i]),
.almost_full(egress_almost_full[i]),
.full()
);
end
endgenerate
assign o_egress_valid0 = ~egress_empty[0];
assign o_egress_valid1 = ~egress_empty[1];
assign o_egress_valid2 = ~egress_empty[2];
assign o_egress_valid3 = ~egress_empty[3];
assign o_egress_data0 = egress_rd_data[0];
assign o_egress_data1 = egress_rd_data[1];
assign o_egress_data2 = egress_rd_data[2];
assign o_egress_data3 = egress_rd_data[3];
// buffer free interface logic
reg [AWIDTH-1:0] bf_rd_ptr[MWIDTH-1:0];
reg [AWIDTH-1:0] bf_wr_ptr[MWIDTH-1:0];
reg [AWIDTH:0] bf_dcnt[MWIDTH-1:0];
reg [MWIDTH-1:0] bf_read, bf_write;
reg [AWIDTH+LOG_MWIDTH-1:0] bf_wr_addr, bf_rd_addr;
reg [AWIDTH-1:0] bf_wr_data;
wire [AWIDTH-1:0] bf_rd_data;
wire [10:0] bf_rd_tmp;
wire [MWIDTH-1:0] bf_empty, bf_full;
reg [MWIDTH-1:0] bf_rd_sel;
reg [MWIDTH-1:0] bf_rd_delay[BRAM_RD_DELAY:0];
reg [MWIDTH-1:0] bf_write_delay[BRAM_RD_DELAY:0];
wire [MWIDTH-1:0] bf_write_cross;
wire [MWIDTH-1:0] hmp_write, hmp_read, hmp_empty, hmp_stall;
wire [AWIDTH-1:0] hmp_rd_data[MWIDTH-1:0];
wire [MWIDTH-1:0] bf_free_flag;
reg bf_rd_en;
// generate the read pointer, write pointer and data counter
// calculation logic
generate
for(i=0;i<MWIDTH;i=i+1) begin: BUFFER_FREE_FIFOS
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_ptr[i] <= 0;
else if (bf_read[i])
bf_rd_ptr[i] <= bf_rd_ptr[i] + 1;
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_dcnt[i] <= 0;
else if (bf_write[i] & ~bf_read[i])
bf_dcnt[i] <= bf_dcnt[i] + 1;
else if(~bf_write[i] & bf_read[i])
bf_dcnt[i] <= bf_dcnt[i] - 1;
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_wr_ptr[i] <= 0;
else if (bf_write[i])
bf_wr_ptr[i] <= bf_wr_ptr[i] + 1;
end
assign bf_empty[i] = ~(|bf_dcnt[i]);
//assign bf_full[i] = bf_dcnt[MWIDTH];
end // end for
endgenerate
// bf write
always@(posedge clk_320M )begin
if(clr_320M)
bf_write <= 0;
else begin
case (buf_free_addr[AWIDTH+LOG_MWIDTH-1:AWIDTH+LOG_MWIDTH-2])
2'b00: bf_write <= {3'b0,buf_free};
2'b01: bf_write <= {2'b0,buf_free,1'b0};
2'b10: bf_write <= {1'b0,buf_free,2'b0};
2'b11: bf_write <= {buf_free,3'b0};
endcase
end
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_wr_addr <= 0;
else begin
case (buf_free_addr[AWIDTH+LOG_MWIDTH-1:AWIDTH+LOG_MWIDTH-2])
2'b00: bf_wr_addr <= {2'b00,bf_wr_ptr[0]};
2'b01: bf_wr_addr <= {2'b01,bf_wr_ptr[1]};
2'b10: bf_wr_addr <= {2'b10,bf_wr_ptr[2]};
2'b11: bf_wr_addr <= {2'b11,bf_wr_ptr[3]};
endcase
end
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_wr_data <= 0;
else
bf_wr_data <= buf_free_addr[AWIDTH-1:0];
end
// bf read
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_addr <= 0;
else begin
case (bf_rd_sel)
4'b0001:bf_rd_addr <= {2'b00,bf_rd_ptr[0]};
4'b0010:bf_rd_addr <= {2'b01,bf_rd_ptr[1]};
4'b0100:bf_rd_addr <= {2'b10,bf_rd_ptr[2]};
4'b1000:bf_rd_addr <= {2'b11,bf_rd_ptr[3]};
default:bf_rd_addr <= 0;
endcase
end
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_sel <= 1;
else
bf_rd_sel <= {bf_rd_sel,bf_rd_sel[MWIDTH-1]};
end
always@(*)begin
bf_read = bf_rd_sel & ~hmp_stall & ~bf_empty;
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_en <= 1;
else
bf_rd_en <= |bf_read;
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_delay[0] <= 0;
else
bf_rd_delay[0] <= bf_read;
end
generate
for(i=1;i<=BRAM_RD_DELAY;i=i+1)begin:BRAM_READ_DELAY
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_delay[i] <= 0;
else
bf_rd_delay[i] <= bf_rd_delay[i-1];
end
end// end for
endgenerate
// bf write delay signal is delayed so that the back end
// logic will not underflow the buffer-freed address pipe
always@(posedge clk_320M )begin
if(clr_320M)
bf_write_delay[0] <= 0;
else
bf_write_delay[0] <= bf_write;
end
generate
for(i=1;i<=BRAM_RD_DELAY;i=i+1)begin:BRAM_READ_DELAY_2
always@(posedge clk_320M )begin
if(clr_320M)
bf_write_delay[i] <= 0;
else
bf_write_delay[i] <= bf_write_delay[i-1];
end
end// end for
endgenerate
infer_sdpram
#(
.DWIDTH(7),
.AWIDTH(9) // address width of the SRAM
) bf_fifos
(
// global
.clk_a(clk_320M),
.clk_b(clk_320M),
// write port a interface
.en_a(|bf_write),
.write_a(|bf_write),
.wr_data_a(bf_wr_data),
.addr_a(bf_wr_addr),
// read port b interface
.en_b(bf_rd_en),
.addr_b(bf_rd_addr),
.rd_data_b(bf_rd_data)
);
//===================================================================
assign hmp_write = bf_rd_delay[BRAM_RD_DELAY];
assign hmp_read = {i_hmp_rd3, i_hmp_rd2, i_hmp_rd1, i_hmp_rd0};
assign bf_write_cross = bf_write_delay[BRAM_RD_DELAY];
generate
for(i=0;i<MWIDTH;i=i+1) begin: HMP_GEN
asyn_fifo
#(
.DBITWIDTH(AWIDTH),
.ABITWIDTH(4) // 16 entries
)
hw_malloc_pipe
(
// global
.clk_a(clk_320M),
.clk_b(clk_80M),
.rst_n(rst_n),
.clr_a(clr_320M),
.clr_b(clr_80M),
// FIFO write interface
.write(hmp_write[i]),
.write_data(bf_rd_data),
// FIFO read interface
.read(hmp_read[i]&~hmp_empty[i]),
.read_data(hmp_rd_data[i]),
// FIFO status signals
.empty(hmp_empty[i]),
.almost_full(hmp_stall[i]),
.full()
);
clk_domain_cross buf_free_flag
(
.sigin(bf_write_cross[i]),
.clkin(clk_320M),
.clr_in(clr_320M),
.clr_out(clr_80M),
.clkout(clk_80M),
.sigout(bf_free_flag[i]),
.full()
);
end
endgenerate
assign o_hmp_valid0 = ~hmp_empty[0];
assign o_hmp_valid1 = ~hmp_empty[1];
assign o_hmp_valid2 = ~hmp_empty[2];
assign o_hmp_valid3 = ~hmp_empty[3];
assign o_hmp_addr0 = hmp_rd_data[0];
assign o_hmp_addr1 = hmp_rd_data[1];
assign o_hmp_addr2 = hmp_rd_data[2];
assign o_hmp_addr3 = hmp_rd_data[3];
assign o_bf_free_flag0 = bf_free_flag[0];
assign o_bf_free_flag1 = bf_free_flag[1];
assign o_bf_free_flag2 = bf_free_flag[2];
assign o_bf_free_flag3 = bf_free_flag[3];
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : hw_malloc.v
// Description : hardware malloc module, managing the memory space for packet cells
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-23 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module hw_malloc
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter LOG_MWIDTH = 2,
parameter MAX_PKT_LEN = 7, // maximum packet lenght in terms of number of 16-byte cells
parameter AWIDTH = 7, // 2 BRAM = total 512 cells, each port is allocated 128 cells
parameter HM_OFFSET = 0 // offset for the multicast vectore
)
(
// global
input wire clk,
input wire rst_n,
input wire clr,
// ingress port
input wire [MAX_PKT_LEN-1:0] i_ingress_pkt_length,
input wire [31:0] i_ingress_dest_ip,
input wire i_ingress_valid,
input wire i_ingress_header,
// output to GSM
output wire [MWIDTH-1:0] o_gsm_multicast,
output wire [AWIDTH-1:0] o_gsm_cell_addr,
output wire o_gsm_wr_en,
// input from GSM
output wire o_hmp_rd,
input wire i_hmp_valid,
input wire [AWIDTH-1:0] i_hmp_addr,
input wire i_bf_free_flag
);
// ---------------------------------------------------------------------
// defines and local parameters
// ---------------------------------------------------------------------
localparam INIT_CELL_CNT = 2**AWIDTH;
// ---------------------------------------------------------------------
// wire, registers and integer
// ---------------------------------------------------------------------
reg [AWIDTH:0] avail_cell_cnt;
reg [MWIDTH-1:0] multicast_vec;
reg [AWIDTH:0] init_addr_gen;
wire malloc;
wire has_room;
reg pkt_drop;
reg [AWIDTH-1:0] alloc_addr;
reg alloc_valid;
wire [AWIDTH-1:0] alloc_addr_sel;
// ---------------------------------------------------------------------
// logic starts here...
// ---------------------------------------------------------------------
// alaivable cell address counter, used to decide if an incoming packet
// can be accomodated into the buffer or needs to be dropped
always@(posedge clk )begin
if(clr)
avail_cell_cnt <= INIT_CELL_CNT;
else if(malloc & ~i_bf_free_flag)
avail_cell_cnt <= avail_cell_cnt - 1;
else if(~malloc & i_bf_free_flag)
avail_cell_cnt <= avail_cell_cnt + 1;
end
// init cell address generator: on reset, the allocated cell address will restart
// from 0
always@(posedge clk )begin
if(clr)
init_addr_gen <= 0;
else if(malloc & ~init_addr_gen[AWIDTH])
init_addr_gen <= init_addr_gen + 1;
end
// if current packet is a good packet, we will alloc a cell address for it
always@(posedge clk )begin
if(clr)
pkt_drop <= 0;
else if(i_ingress_header)
pkt_drop <= ~has_room;
end
//assign has_room = ( (i_ingress_pkt_length <= avail_cell_cnt) & (~init_addr_gen[AWIDTH] | i_hmp_valid) )?1'b1:1'b0; // the second condition is to prevent underflow the address asyn_fifo
assign has_room = ( i_ingress_pkt_length <= avail_cell_cnt )?1'b1:1'b0;
assign malloc = i_ingress_valid && (i_ingress_header? (has_room & (|i_ingress_dest_ip[HM_OFFSET+MWIDTH-1:HM_OFFSET])) : (~pkt_drop & (|multicast_vec)));
always@(posedge clk )begin
if(clr)begin
alloc_valid <= 0;
alloc_addr <= 0;
end
else begin
alloc_valid <= malloc;
alloc_addr <= alloc_addr_sel;
end
end
assign o_hmp_rd = malloc & init_addr_gen[AWIDTH];
assign alloc_addr_sel = init_addr_gen[AWIDTH] ? i_hmp_addr : init_addr_gen;
// use one-hot coding for the multicast vector to indicate which output port
// this cell is going to be sent
always@(posedge clk )begin
if(clr)
multicast_vec <= 0;
else if(i_ingress_header)
multicast_vec <= i_ingress_dest_ip[HM_OFFSET+MWIDTH-1:HM_OFFSET];
end
// output signals
assign o_gsm_wr_en = alloc_valid;
assign o_gsm_cell_addr = alloc_addr;
assign o_gsm_multicast = multicast_vec;
endmodule
|
`timescale 1ns/1ps
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : dpram.v
// Description : a generic description of dual port sram, support xilinx device
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-02-10 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module dpSram_32
#(
parameter SRAM_MODE = 1, // 0: generic sram; 1: Xilinx Simple Duel Port mode BRAM 2: Xilinx True Duel Port mode BRAM
parameter DBITWIDTH = 18, // data width of the SRAM, 36 bit when configured to be SDP BRAM, otherwise 18 bit wide
parameter ABITWIDTH = 10 // address width of the SRAM
)
(
// global
input wire clk_a,
input wire clk_b,
input wire clr_a,
input wire clr_b,
// port a interface
input wire en_a,
input wire write_a,
input wire [DBITWIDTH-1:0] wr_data_a,
input wire [ABITWIDTH-1:0] addr_a,
output wire [DBITWIDTH-1:0] rd_data_a,
// port b interface
input wire en_b,
input wire write_b,
input wire [DBITWIDTH-1:0] wr_data_b,
input wire [ABITWIDTH-1:0] addr_b,
output wire [DBITWIDTH-1:0] rd_data_b
);
localparam DO_REG = 1; // register the output data (0 or 1)
generate
// Xilinx Simple Duel Port BRAM
if(SRAM_MODE == 0)begin
wire [31:0] do;
wire [3:0] dop;
wire [3:0] we;
assign rd_data_b = {dop,do};
assign rd_data_a = {dop,do};
assign we = {4{write_a}};
RAMB18SDP #(
.DO_REG(DO_REG) // optional output register (0 or 1)
)
RAMB18SDP_inst
(
.DO(do), // 16-bit A port data/LSB data output
.DOP(dop), // 2-bit B port parity/MSB parity output
.RDCLK(clk_b), // 1-bit read port clock
.RDEN(en_b), // 1-bit read port enable
.REGCE(1'b1), // 1-bit register clock enable output set/reset input, only valid when 'DO_REG=1'
.SSR(1'b0), // 1-bit synchronous output set/reset input
.WRCLK(clk_a), // 1-bit write port clock
.WREN(en_a), // 1-bit write port enable
.WRADDR(addr_a), // 9-bit write port address input
.RDADDR(addr_b), // 9-bit read port address input
.DI(wr_data_a[31:0]),// 32-bit data input
.DIP(wr_data_a[35:32]), // 4-bit parity data input
.WE(we) // 4-bit byte write enable input
);
end
// Xilinx True Duel Port BRAM
else if(SRAM_MODE==1) begin
wire [15:0] doa,dob;
wire [1:0] dopa,dopb;
wire [1:0] wea;
wire [3:0] web;
assign rd_data_a = {dopa,doa};
assign rd_data_b = {dopb,dob};
assign wea = {2{write_a}};
assign web = {4{write_b}};
// RAMB18: 16K+2K Parity Paramatizable True Duel Port BlockRAM
RAMB18E1 #(
.DOA_REG(DO_REG),
.DOB_REG(DO_REG),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18)
)
RAMB18_inst(
.DOADO(doa),
.DOBDO(dob),
.DOPADOP(dopa),
.DOPBDOP(dopb),
.ADDRARDADDR({addr_a,4'b0}),
.ADDRBWRADDR({addr_b,4'b0}),
.CLKARDCLK(clk_a),
.CLKBWRCLK(clk_b),
.DIADI(wr_data_a[15:0]),
.DIBDI(wr_data_b[15:0]),
.DIPADIP(wr_data_a[17:16]),
.DIPBDIP(wr_data_b[17:16]),
.ENARDEN(en_a),
.ENBWREN(en_b), // port enable
.REGCEAREGCE(1'b1),
.REGCEB(1'b1), // output register clock enable signal
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(clr_a),
.RSTREGB(clr_b),
.WEA(wea), // byte write enable
.WEBWE(web)
);
end
// Generic simple duel port sram, 2 write & read ports
else if(SRAM_MODE == 2)begin
reg [DBITWIDTH-1:0] generic_ram [(2**ABITWIDTH)-1:0];
reg [DBITWIDTH-1:0] dout_a, dout_b, din_a, din_b;
reg wr_reg_a, wr_reg_b, en_reg_a, en_reg_b;
reg [ABITWIDTH-1:0] addr_reg_a, addr_reg_b;
always @(posedge clk_a)begin
wr_reg_a <= write_a;
addr_reg_a <= addr_a;
addr_reg_b <= addr_b;
din_a <= wr_data_a;
en_reg_a <= en_a;
en_reg_b <= en_b;
end
always @(posedge clk_a)
if (en_reg_a) begin
if (wr_reg_a)
generic_ram[addr_reg_a] <= din_a;
end
always @(posedge clk_b)
if (en_reg_b)
dout_b <= generic_ram[addr_reg_b];
assign rd_data_a = din_a;
assign rd_data_b = dout_b;
end
// generic simple duel port sram, 1 write port, 1 read port
else begin
reg [DBITWIDTH-1:0] generic_ram [(2**ABITWIDTH)-1:0];
reg [DBITWIDTH-1:0] dout_a, dout_b, din_a, din_b;
reg wr_reg_a, wr_reg_b, en_reg_a, en_reg_b;
reg [ABITWIDTH-1:0] addr_reg_a, addr_reg_b;
always @(posedge clk_a)begin
wr_reg_a <= write_a;
wr_reg_b <= write_b;
addr_reg_a <= addr_a;
addr_reg_b <= addr_b;
din_a <= wr_data_a;
din_b <= wr_data_b;
en_reg_a <= en_a;
en_reg_b <= en_b;
end
always @(posedge clk_a)
if (en_reg_a) begin
if (wr_reg_a)
generic_ram[addr_reg_a] <= din_a;
dout_a <= generic_ram[addr_reg_a];
end
always @(posedge clk_b)
if (en_reg_b) begin
if (wr_reg_a)
generic_ram[addr_reg_b] <= din_b;
dout_b <= generic_ram[addr_reg_b];
end
assign rd_data_a = dout_a;
assign rd_data_b = dout_b;
end
endgenerate
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : infer_sdpram.v
// Description : a generic description of dual port sram, support xilinx device
// : 2 clock, 1 write port and 1 read port
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-02-10 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module infer_sdpram
#(
parameter DWIDTH = 18, // data width of the SRAM, 36 bit when configured to be SDP BRAM, otherwise 18 bit wide
parameter AWIDTH = 10 // address width of the SRAM
)
(
// global
input wire clk_a,
input wire clk_b,
// port a interface
input wire en_a,
input wire write_a,
input wire [DWIDTH-1:0] wr_data_a,
input wire [AWIDTH-1:0] addr_a,
// port b interface
input wire en_b,
input wire [AWIDTH-1:0] addr_b,
output wire [DWIDTH-1:0] rd_data_b
);
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
reg [DWIDTH-1:0] generic_ram [(2**AWIDTH)-1:0];
reg [DWIDTH-1:0] dout_a, dout_b, din_a, din_b;
reg wr_reg_a, wr_reg_b, en_reg_a, en_reg_b;
reg [AWIDTH-1:0] addr_reg_a, addr_reg_b;
always @(posedge clk_a)begin
wr_reg_a <= write_a;
addr_reg_a <= addr_a;
din_a <= wr_data_a;
en_reg_a <= en_a;
end
always @(posedge clk_b)begin
addr_reg_b <= addr_b;
en_reg_b <= en_b;
end
always @(posedge clk_a)
if (en_reg_a) begin
if (wr_reg_a)
generic_ram[addr_reg_a] <= din_a;
end
always @(posedge clk_b)
if (en_reg_b) begin
// if (wr_reg_b)
//generic_ram[addr_reg_b] <= din_b;
dout_b <= generic_ram[addr_reg_b];
end
//assign rd_data_a = dout_a;
assign rd_data_b = dout_b;
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : rr_sch.v
// Description : round robin scheduler
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-29 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module rr_sch
#(
parameter NUM_PORT = 4, // number of requests to be scheduled
parameter LOG_NUM_PORT = 2
)
(
input wire clk,
input wire rst_n,
input wire clr,
input wire [NUM_PORT-1:0] req,
input wire stall,
output wire [NUM_PORT-1:0] grant
);
genvar iRR;
integer i;
reg [NUM_PORT-1:0] rr_prior_non_empty_vec;
reg [NUM_PORT-1:0] rr_prior[0:NUM_PORT-1];
reg [NUM_PORT-1:0] rr_prior_non_empty[0:NUM_PORT-1];
reg [NUM_PORT-1:0] rr_prior_mask[0:NUM_PORT-1];
reg [LOG_NUM_PORT-1:0] rr_index[0:NUM_PORT-1];
reg [LOG_NUM_PORT-1:0] sch_index ;
reg [NUM_PORT-1:0] rr_nxt_non_empty_vec;
always@(*)begin
rr_prior_non_empty_vec = 0;
for(i=0;i<NUM_PORT;i=i+1)
rr_prior_non_empty_vec = rr_prior_non_empty_vec | rr_prior_non_empty[i];
end
generate
for(iRR=0;iRR<NUM_PORT; iRR=iRR+1) begin : ROUND_ROBIN
// the Round Robin priority of each port is updated whenever the token is
// passed from one port to another
always@(posedge clk )begin
if(clr)
rr_index[iRR] <= NUM_PORT - iRR;
else if(~stall)
rr_index[iRR] <= sch_index - iRR + NUM_PORT;
end
always@(*)begin
rr_prior[iRR] = 1 << rr_index[iRR];
rr_prior_mask[iRR] = {NUM_PORT{1'b1}} << (rr_index[iRR] + 1);
rr_prior_non_empty[iRR] = req[iRR] ? rr_prior[iRR] : 0;
end
always@(*)begin
rr_nxt_non_empty_vec[iRR] = req[iRR] ? ( ~|(rr_prior_non_empty_vec & rr_prior_mask[iRR]) ) : 0;
end
end // end for
endgenerate
generate
if(NUM_PORT == 4) begin
always @ (*)
case (rr_nxt_non_empty_vec)
4'b0001: sch_index = 0;
4'b0010: sch_index = 1;
4'b0100: sch_index = 2;
4'b1000: sch_index = 3;
default: sch_index = 0;
endcase
end
endgenerate
assign grant = rr_nxt_non_empty_vec;
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : rr_sch_16.v
// Description : round robin scheduler for 16 groups
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-29 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module rr_sch_16
#(
parameter GSIZE = 4,
parameter MWIDTH = 4, // number of requests to be scheduled
parameter LOG_GSIZE = 2
)
(
input wire clk,
input wire rst_n,
input wire clr,
// group 0
input wire [GSIZE-1:0] req_0_0,
input wire stall_0_0,
output wire [GSIZE-1:0] grant_0_0,
input wire [GSIZE-1:0] req_0_1,
input wire stall_0_1,
output wire [GSIZE-1:0] grant_0_1,
input wire [GSIZE-1:0] req_0_2,
input wire stall_0_2,
output wire [GSIZE-1:0] grant_0_2,
input wire [GSIZE-1:0] req_0_3,
input wire stall_0_3,
output wire [GSIZE-1:0] grant_0_3,
// group 1
input wire [GSIZE-1:0] req_1_0,
input wire stall_1_0,
output wire [GSIZE-1:0] grant_1_0,
input wire [GSIZE-1:0] req_1_1,
input wire stall_1_1,
output wire [GSIZE-1:0] grant_1_1,
input wire [GSIZE-1:0] req_1_2,
input wire stall_1_2,
output wire [GSIZE-1:0] grant_1_2,
input wire [GSIZE-1:0] req_1_3,
input wire stall_1_3,
output wire [GSIZE-1:0] grant_1_3,
// group 0
input wire [GSIZE-1:0] req_2_0,
input wire stall_2_0,
output wire [GSIZE-1:0] grant_2_0,
input wire [GSIZE-1:0] req_2_1,
input wire stall_2_1,
output wire [GSIZE-1:0] grant_2_1,
input wire [GSIZE-1:0] req_2_2,
input wire stall_2_2,
output wire [GSIZE-1:0] grant_2_2,
input wire [GSIZE-1:0] req_2_3,
input wire stall_2_3,
output wire [GSIZE-1:0] grant_2_3,
// group 0
input wire [GSIZE-1:0] req_3_0,
input wire stall_3_0,
output wire [GSIZE-1:0] grant_3_0,
input wire [GSIZE-1:0] req_3_1,
input wire stall_3_1,
output wire [GSIZE-1:0] grant_3_1,
input wire [GSIZE-1:0] req_3_2,
input wire stall_3_2,
output wire [GSIZE-1:0] grant_3_2,
input wire [GSIZE-1:0] req_3_3,
input wire stall_3_3,
output wire [GSIZE-1:0] grant_3_3
);
genvar i;
wire [GSIZE-1:0] req[MWIDTH*GSIZE-1:0];
wire stall[MWIDTH*GSIZE-1:0];
wire [GSIZE-1:0] grant[MWIDTH*GSIZE-1:0];
// req
// group 0
assign req[0] = req_0_0;
assign req[1] = req_0_1;
assign req[2] = req_0_2;
assign req[3] = req_0_3;
// group 1
assign req[4] = req_1_0;
assign req[5] = req_1_1;
assign req[6] = req_1_2;
assign req[7] = req_1_3;
// group 2
assign req[8] = req_2_0;
assign req[9] = req_2_1;
assign req[10] = req_2_2;
assign req[11] = req_2_3;
// group 3
assign req[12] = req_3_0;
assign req[13] = req_3_1;
assign req[14] = req_3_2;
assign req[15] = req_3_3;
// stall
// group0
assign stall[0] = stall_0_0;
assign stall[1] = stall_0_1;
assign stall[2] = stall_0_2;
assign stall[3] = stall_0_3;
// group 1
assign stall[4] = stall_1_0;
assign stall[5] = stall_1_1;
assign stall[6] = stall_1_2;
assign stall[7] = stall_1_3;
// group 2
assign stall[8] = stall_2_0;
assign stall[9] = stall_2_1;
assign stall[10] = stall_2_2;
assign stall[11] = stall_2_3;
// group 3
assign stall[12] = stall_3_0;
assign stall[13] = stall_3_1;
assign stall[14] = stall_3_2;
assign stall[15] = stall_3_3;
// grant
// group0
assign grant_0_0 = grant[0];
assign grant_0_1 = grant[1];
assign grant_0_2 = grant[2];
assign grant_0_3 = grant[3];
// group1
assign grant_1_0 = grant[4];
assign grant_1_1 = grant[5];
assign grant_1_2 = grant[6];
assign grant_1_3 = grant[7];
// group2
assign grant_2_0 = grant[8];
assign grant_2_1 = grant[9];
assign grant_2_2 = grant[10];
assign grant_2_3 = grant[11];
// group3
assign grant_3_0 = grant[12];
assign grant_3_1 = grant[13];
assign grant_3_2 = grant[14];
assign grant_3_3 = grant[15];
generate
for(i=0;i<GSIZE*MWIDTH;i=i+1)begin
rr_sch
#(
.NUM_PORT(GSIZE), // number of requests to be scheduled
.LOG_NUM_PORT(LOG_GSIZE)
)rr_sch_inst
(
.clk(clk),
.rst_n(rst_n),
.clr(clr),
.req(req[i]),
.stall(stall[i]),
.grant(grant[i])
);
end // end for
endgenerate
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_test.v
// Description : test bench for gsm system
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-07-02 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_test;
`define DAT_PKT_PAD 16'hE00F
`define FLAG_HEAD_PKT 16'hABCD
`define FLAG_DAT_PKT 16'h0800
localparam DWIDTH = 256;
localparam MWIDTH = 4;
localparam GSIZE = 4;
localparam LOG_MWIDTH = 2;
localparam LOG_GSIZE = 2;
localparam AWIDTH = 7;
localparam LOC_PKT_LEN = 24; // the bit location of packet length field in the 16-byte data cell
localparam LOC_DEST_IP = 31; // the bit location of the destination ip field in the data cell
localparam LOC_SOURCE_ID = 16;
//-------------------------------------------------
// clk and reset signal generation
//-------------------------------------------------
wire clk_320M, clk_80M, clr_320M, clr_80M;
wire rst_n;
reg clk_33M, extern_rst_n;
initial begin
clk_33M <= 0;
extern_rst_n <= 0;
extern_rst_n <= #(300) 1'b1;
end
always @(clk_33M)begin
clk_33M <= #(25) ~clk_33M;
end
//-------------------------------------------------
// ingress port data generation
//-------------------------------------------------
reg [15:0] pkt_header;
reg ingress_valid, ingress_header;
integer i;
genvar igp;
reg [7:0] sourceID[GSIZE*MWIDTH-1:0];
reg [7:0] pkt_length;
reg [31:0] destIP[GSIZE*MWIDTH-1:0];
reg [DWIDTH-1:0] ingress_data[GSIZE*MWIDTH-1:0];
reg [GSIZE*MWIDTH-1:0] egress_stall;
reg [7:0] pkt_cnt;
initial begin
for(i=0;i<GSIZE*MWIDTH;i=i+1)begin
sourceID[i] = i;
destIP[i] = (1 << i) | (1<<(i+1));
end
egress_stall = 0;
end
always@(*)begin
if(ingress_header)begin
pkt_header = {pkt_cnt,8'hEF};
end
else begin
pkt_header = {pkt_cnt,8'hCD};
end
end
always@(posedge clk_80M)begin
if(clr_80M)begin
ingress_valid <= 0;
pkt_length <= 2;
ingress_header <= 0;
end
else begin
ingress_valid <= 1'b1;
pkt_length <= 2;
ingress_header <= ~ingress_header;
end
end
always@(posedge clk_80M)begin
if(clr_80M)
pkt_cnt <= 0;
else if(ingress_header)
pkt_cnt <= pkt_cnt + 1;
end
generate
for(igp = 0; igp < GSIZE * MWIDTH; igp=igp+1)begin : INGRESS_DATA_GEN
always@(*)begin
ingress_data[igp] = {64'hDDDD,destIP[igp],pkt_length,sourceID[igp],pkt_header};
end
end
endgenerate
gsm_sys
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.GSIZE(GSIZE), // group size, number of gsm_unit in each group
.LOG_MWIDTH(LOG_MWIDTH),
.LOG_GSIZE(LOG_GSIZE),
.DWIDTH(DWIDTH), // data width = 16 bytes
.AWIDTH(AWIDTH) // 2 BRAM = total 512 cells, each port is allocated 128 cells
) gsm_sys_inst
(
//** global
.clk_33M(clk_33M),
.extern_rst_n(extern_rst_n),
.clk_320M(clk_320M),
.clk_80M(clk_80M),
.clr_320M(clr_320M),
.clr_80M(clr_80M),
.rst_n(rst_n),
//** 16 ingress ports
// group 0
.i_ingress_valid_0_0(ingress_valid),
.i_ingress_header_0_0(ingress_header),
.i_ingress_data_0_0(ingress_data[0]),
.i_ingress_valid_0_1(ingress_valid),
.i_ingress_header_0_1(ingress_header),
.i_ingress_data_0_1(ingress_data[1]),
.i_ingress_valid_0_2(ingress_valid),
.i_ingress_header_0_2(ingress_header),
.i_ingress_data_0_2(ingress_data[2]),
.i_ingress_valid_0_3(ingress_valid),
.i_ingress_header_0_3(ingress_header),
.i_ingress_data_0_3(ingress_data[3]),
// group 1
.i_ingress_valid_1_0(ingress_valid),
.i_ingress_header_1_0(ingress_header),
.i_ingress_data_1_0(ingress_data[4]),
.i_ingress_valid_1_1(ingress_valid),
.i_ingress_header_1_1(ingress_header),
.i_ingress_data_1_1(ingress_data[5]),
.i_ingress_valid_1_2(ingress_valid),
.i_ingress_header_1_2(ingress_header),
.i_ingress_data_1_2(ingress_data[6]),
.i_ingress_valid_1_3(ingress_valid),
.i_ingress_header_1_3(ingress_header),
.i_ingress_data_1_3(ingress_data[7]),
// group 2
.i_ingress_valid_2_0(ingress_valid),
.i_ingress_header_2_0(ingress_header),
.i_ingress_data_2_0(ingress_data[8]),
.i_ingress_valid_2_1(ingress_valid),
.i_ingress_header_2_1(ingress_header),
.i_ingress_data_2_1(ingress_data[9]),
.i_ingress_valid_2_2(ingress_valid),
.i_ingress_header_2_2(ingress_header),
.i_ingress_data_2_2(ingress_data[10]),
.i_ingress_valid_2_3(ingress_valid),
.i_ingress_header_2_3(ingress_header),
.i_ingress_data_2_3(ingress_data[11]),
// group 3
.i_ingress_valid_3_0(ingress_valid),
.i_ingress_header_3_0(ingress_header),
.i_ingress_data_3_0(ingress_data[12]),
.i_ingress_valid_3_1(ingress_valid),
.i_ingress_header_3_1(ingress_header),
.i_ingress_data_3_1(ingress_data[13]),
.i_ingress_valid_3_2(ingress_valid),
.i_ingress_header_3_2(ingress_header),
.i_ingress_data_3_2(ingress_data[14]),
.i_ingress_valid_3_3(ingress_valid),
.i_ingress_header_3_3(ingress_header),
.i_ingress_data_3_3(ingress_data[15]),
//** 16 egress ports
// group 0
.i_egress_stall_0_0(egress_stall[0]),
.o_egress_valid_0_0(),
.o_egress_data_0_0(),
.i_egress_stall_0_1(egress_stall[1]),
.o_egress_valid_0_1(),
.o_egress_data_0_1(),
.i_egress_stall_0_2(egress_stall[2]),
.o_egress_valid_0_2(),
.o_egress_data_0_2(),
.i_egress_stall_0_3(egress_stall[3]),
.o_egress_valid_0_3(),
.o_egress_data_0_3(),
// group 1
.i_egress_stall_1_0(egress_stall[4]),
.o_egress_valid_1_0(),
.o_egress_data_1_0(),
.i_egress_stall_1_1(egress_stall[5]),
.o_egress_valid_1_1(),
.o_egress_data_1_1(),
.i_egress_stall_1_2(egress_stall[6]),
.o_egress_valid_1_2(),
.o_egress_data_1_2(),
.i_egress_stall_1_3(egress_stall[7]),
.o_egress_valid_1_3(),
.o_egress_data_1_3(),
// group 2
.i_egress_stall_2_0(egress_stall[8]),
.o_egress_valid_2_0(),
.o_egress_data_2_0(),
.i_egress_stall_2_1(egress_stall[9]),
.o_egress_valid_2_1(),
.o_egress_data_2_1(),
.i_egress_stall_2_2(egress_stall[10]),
.o_egress_valid_2_2(),
.o_egress_data_2_2(),
.i_egress_stall_2_3(egress_stall[11]),
.o_egress_valid_2_3(),
.o_egress_data_2_3(),
// group 3
.i_egress_stall_3_0(egress_stall[12]),
.o_egress_valid_3_0(),
.o_egress_data_3_0(),
.i_egress_stall_3_1(egress_stall[13]),
.o_egress_valid_3_1(),
.o_egress_data_3_1(),
.i_egress_stall_3_2(egress_stall[14]),
.o_egress_valid_3_2(),
.o_egress_data_3_2(),
.i_egress_stall_3_3(egress_stall[15]),
.o_egress_valid_3_3(),
.o_egress_data_3_3()
);
endmodule
|
// $Id: c_constants.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// global constant definitions
//==============================================================================
//------------------------------------------------------------------------------
// reset handling
//------------------------------------------------------------------------------
// asynchronous reset
`define RESET_TYPE_ASYNC 0
// synchronous reset
`define RESET_TYPE_SYNC 1
`define RESET_TYPE_LAST `RESET_TYPE_SYNC
//------------------------------------------------------------------------------
// arbiter types
//------------------------------------------------------------------------------
// round-robin arbiter
`define ARBITER_TYPE_ROUND_ROBIN 0
// matrix arbiter
`define ARBITER_TYPE_MATRIX 1
// DesignWare first-come, first-serve arbiter
`define ARBITER_TYPE_DW_FCFS 2
`define ARBITER_TYPE_LAST `ARBITER_TYPE_DW_FCFS
//------------------------------------------------------------------------------
// error checker capture more
//------------------------------------------------------------------------------
// disable error reporting
`define ERROR_CAPTURE_MODE_NONE 0
// don't hold errors
`define ERROR_CAPTURE_MODE_NO_HOLD 1
// capture first error only (subsequent errors are blocked)
`define ERROR_CAPTURE_MODE_HOLD_FIRST 2
// capture all errors
`define ERROR_CAPTURE_MODE_HOLD_ALL 3
`define ERROR_CAPTURE_MODE_LAST `ERROR_CAPTURE_MODE_HOLD_ALL
//------------------------------------------------------------------------------
// crossbar implementation variants
//------------------------------------------------------------------------------
// tristate-based
`define CROSSBAR_TYPE_TRISTATE 0
// mux-based
`define CROSSBAR_TYPE_MUX 1
// distributed multiplexers
`define CROSSBAR_TYPE_DIST_MUX 2
`define CROSSBAR_TYPE_LAST `CROSSBAR_TYPE_DIST_MUX
//------------------------------------------------------------------------------
// register file implemetation variants
//------------------------------------------------------------------------------
// 2D array implemented using flipflops
`define REGFILE_TYPE_FF_2D 0
// 1D array of flipflops, read using a combinational mux
`define REGFILE_TYPE_FF_1D_MUX 1
// 1D array of flipflops, read using a tristate mux
`define REGFILE_TYPE_FF_1D_TRISTATE 2
// Synopsys DesignWare implementation using flipflips
`define REGFILE_TYPE_FF_DW 3
// 2D array implemented using flipflops
`define REGFILE_TYPE_LAT_2D 4
// 1D array of flipflops, read using a combinational mux
`define REGFILE_TYPE_LAT_1D_MUX 5
// 1D array of flipflops, read using a tristate mux
`define REGFILE_TYPE_LAT_1D_TRISTATE 6
// Synopsys DesignWare implementation using flipflips
`define REGFILE_TYPE_LAT_DW 7
`define REGFILE_TYPE_LAST `REGFILE_TYPE_LAT_DW
//------------------------------------------------------------------------------
// directions of rotation
//------------------------------------------------------------------------------
`define ROTATE_DIR_LEFT 0
`define ROTATE_DIR_RIGHT 1
//------------------------------------------------------------------------------
// wavefront allocator implementation variants
//------------------------------------------------------------------------------
// variant which uses multiplexers to permute inputs and outputs based on
// priority
`define WF_ALLOC_TYPE_MUX 0
// variant which replicates the entire allocation logic for the different
// priorities and selects the result from the appropriate one
`define WF_ALLOC_TYPE_REP 1
// variant implementing a Diagonal Propagation Arbiter as described in Hurt et
// al, "Design and Implementation of High-Speed Symmetric Crossbar Schedulers"
`define WF_ALLOC_TYPE_DPA 2
// variant which rotates inputs and outputs based on priority
`define WF_ALLOC_TYPE_ROT 3
// variant which uses wraparound (forming a false combinational loop) as
// described in Dally et al, "Principles and Practices of Interconnection
// Networks"
`define WF_ALLOC_TYPE_LOOP 4
`define WF_ALLOC_TYPE_LAST `WF_ALLOC_TYPE_LOOP
//------------------------------------------------------------------------------
// binary operators
//------------------------------------------------------------------------------
`define BINARY_OP_AND 0
`define BINARY_OP_NAND 1
`define BINARY_OP_OR 2
`define BINARY_OP_NOR 3
`define BINARY_OP_XOR 4
`define BINARY_OP_XNOR 5
`define BINARY_OP_LAST `BINARY_OP_XNOR
|
// $Id: c_functions.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// global function definitions
//==============================================================================
// compute ceiling of binary logarithm
function integer clogb(input integer argument);
integer i;
begin
clogb = 0;
for(i = argument - 1; i > 0; i = i >> 1)
clogb = clogb + 1;
end
endfunction
// compute ceiling of base-th root of argument
function integer croot(input integer argument, input integer base);
integer i;
integer j;
begin
croot = 0;
i = 0;
while(i < argument)
begin
croot = croot + 1;
i = 1;
for(j = 0; j < base; j = j + 1)
i = i * croot;
end
end
endfunction
// population count (count ones)
function integer pop_count(input integer argument);
integer i;
begin
pop_count = 0;
for(i = argument; i > 0; i = i >> 1)
pop_count = pop_count + (i & 1);
end
endfunction
|
`timescale 1ns/1ps
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: alt_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_fifo (
clock,
data,
rdreq,
sclr,
wrreq,
full,
q);
input clock;
input [8:0] data;
input rdreq;
input sclr;
input wrreq;
output full;
output [8:0] q;
wire sub_wire0;
wire [8:0] sub_wire1;
wire full = sub_wire0;
wire [8:0] q = sub_wire1[8:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.sclr (sclr),
.wrreq (wrreq),
.full (sub_wire0),
.q (sub_wire1),
.aclr (),
.almost_empty (),
.almost_full (),
.empty (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = 512,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 9,
scfifo_component.lpm_widthu = 9,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "9"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "9"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 9 0 data 0 0 9 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: alt_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module alt_fifo (
clock,
data,
rdreq,
sclr,
wrreq,
full,
q);
input clock;
input [8:0] data;
input rdreq;
input sclr;
input wrreq;
output full;
output [8:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "9"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "9"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 9 0 data 0 0 9 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
alt_fifo alt_fifo_inst (
.clock ( clock_sig ),
.data ( data_sig ),
.rdreq ( rdreq_sig ),
.sclr ( sclr_sig ),
.wrreq ( wrreq_sig ),
.full ( full_sig ),
.q ( q_sig )
);
|
//Replacement for Xilinx corgen fifo_16
module fifo_16 #(
parameter AWIDTH = 9 // 2 BRAM = total 512 cells
)(
input clk,
input rst,
input [AWIDTH-1:0] din,
input wr_en,
input rd_en,
output [AWIDTH-1:0] dout,
//output full,
//output empty,
output valid);
alt_fifo alt_fifo_inst (
.clock ( clk ),
.data ( din ),
.rdreq ( rd_en ),
.sclr ( rst ),
.wrreq ( wr_en ),
.full(valid),
.q ( dout )
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: alt_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_pll (
areset,
fbin,
inclk0,
c0,
c1,
fbout,
locked);
input areset;
input fbin;
input inclk0;
output c0;
output c1;
output fbout;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri1 fbin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] sub_wire0;
wire sub_wire2;
wire sub_wire3;
wire [0:0] sub_wire7 = 1'h0;
wire [0:0] sub_wire4 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire fbout = sub_wire2;
wire locked = sub_wire3;
wire c0 = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.areset (areset),
.fbin (fbin),
.inclk (sub_wire6),
.clk (sub_wire0),
.fbout (sub_wire2),
.locked (sub_wire3),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbmimicbidir (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 33,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 80,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 33,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 320,
altpll_component.clk1_phase_shift = "0",
altpll_component.inclk0_input_frequency = 30303,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=alt_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "EXTERNAL_FEEDBACK",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_USED",
altpll_component.port_fbout = "PORT_USED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "320.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "1"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "80.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "320.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "320"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "EXTERNAL_FEEDBACK"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: fbin 0 0 0 0 INPUT VCC "fbin"
// Retrieval info: USED_PORT: fbout 0 0 0 0 OUTPUT VCC "fbout"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @fbin 0 0 0 0 fbin 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: fbout 0 0 0 0 @fbout 0 0 0 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: alt_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module alt_pll (
areset,
fbin,
inclk0,
c0,
c1,
fbout,
locked);
input areset;
input fbin;
input inclk0;
output c0;
output c1;
output fbout;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri1 fbin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "320.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "1"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "80.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "320.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "320"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "EXTERNAL_FEEDBACK"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: fbin 0 0 0 0 INPUT VCC "fbin"
// Retrieval info: USED_PORT: fbout 0 0 0 0 OUTPUT VCC "fbout"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @fbin 0 0 0 0 fbin 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: fbout 0 0 0 0 @fbout 0 0 0 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
alt_pll alt_pll_inst (
.areset ( areset_sig ),
.fbin ( fbin_sig ),
.inclk0 ( inclk0_sig ),
.c0 ( c0_sig ),
.c1 ( c1_sig ),
.fbout ( fbout_sig ),
.locked ( locked_sig )
);
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : asyn_fifo.v
// Description : asynchronous fifo for clock domain crossing
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-02-15 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module asyn_fifo
#(
parameter DBITWIDTH = 32, // bit width of data
parameter ABITWIDTH = 4, // bit width of address
// parameter DOUT_REG = 1, // optional output register
parameter AF_THRESHOLD = 4, // almost full threshold
parameter AF_WIDTH = 0 // additional almost full address width
)
(
// global
input wire clk_a,
input wire clk_b,
input wire rst_n,
input wire clr_a,
input wire clr_b,
// FIFO write interface
input wire write,
input wire [DBITWIDTH-1:0] write_data,
// FIFO read interface
input wire read,
output wire [DBITWIDTH-1:0] read_data,
// FIFO status signals
output wire empty,
output wire almost_full,
output wire full
);
reg [ABITWIDTH:0] dcnt_a,dcnt_b;
reg [ABITWIDTH+AF_WIDTH:0] dcnt_a_almost;
reg [ABITWIDTH-1:0] wrPtr, rdPtr;
wire write_sync, read_sync;
assign empty = ~|dcnt_b;
assign full = dcnt_a[ABITWIDTH];
assign almost_full = |dcnt_a_almost[ABITWIDTH+AF_WIDTH:ABITWIDTH];
clk_domain_cross sync_wr(
.sigin(write),
.clkin(clk_a),
.clr_in(clr_a),
.clr_out(clr_b),
.clkout(clk_b),
.sigout(write_sync),
.full()
);
clk_domain_cross sync_rd(
.sigin(read),
.clkin(clk_b),
.clr_in(clr_b),
.clr_out(clr_a),
.clkout(clk_a),
.sigout(read_sync),
.full()
);
// clock domain a
always@(posedge clk_a )begin
if(clr_a)
dcnt_a <= 0;
else if(write & ~read_sync)
dcnt_a <= dcnt_a + 1;
else if(~write & read_sync)
dcnt_a <= dcnt_a - 1;
end
always@(posedge clk_a )begin
if(clr_a)
dcnt_a_almost <= AF_THRESHOLD;
else if(write & ~read_sync)
dcnt_a_almost <= dcnt_a_almost + 1;
else if(~write & read_sync)
dcnt_a_almost <= dcnt_a_almost - 1;
end
always@(posedge clk_a )begin
if(clr_a)
wrPtr <= 0;
else if(write )
wrPtr <= wrPtr + 1;
end
// clock domain b
always@(posedge clk_b )begin
if(clr_b)
dcnt_b <= 0;
else if(write_sync & ~read)
dcnt_b <= dcnt_b + 1;
else if(~write_sync & read)
dcnt_b <= dcnt_b - 1;
end
always@(posedge clk_b )begin
if(clr_b)
rdPtr <= 0;
else if(read)
rdPtr <= rdPtr + 1;
end
// storage
infer_distributed_ram
#(
.ABITWIDTH(ABITWIDTH),
.DBITWIDTH(DBITWIDTH)
)
mem
(
.clk(clk_a),
.write(write),
.wrAddr(wrPtr),
.rdAddr(rdPtr),
.din(write_data),
.dout(read_data)
);
endmodule
module infer_distributed_ram
#(
parameter ABITWIDTH = 3,
parameter DBITWIDTH = 32
)
(
input wire clk,
input wire write,
input wire [ABITWIDTH-1:0] wrAddr,
input wire [ABITWIDTH-1:0] rdAddr,
input wire [DBITWIDTH-1:0] din,
output wire [DBITWIDTH-1:0] dout
);
localparam MEM_SIZE = (2**ABITWIDTH);
////synthesis attribute ram_style of mem is distributed
reg [DBITWIDTH-1:0] mem[2**ABITWIDTH-1:0]; ////pragma attribute mem ram_block FALSE
always @ (posedge clk)
begin
if (write) begin
mem[wrAddr] <= din;
end
end
assign dout = mem[rdAddr]; //unregistered read
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : clk_domain_cross.v
// Description : circuit synchronizer for signal goes across
// two different clock domains
// Author : NUDT
// -------------------------------------------------------------------------------
// Version :
// -- 2011-02-15 Modify by Zefu Dai, fix the reset signals to make it consistance
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module clk_domain_cross
(
sigin,
clkin,
clr_in,
clr_out,
clkout,
sigout,
full
);
input sigin;
input clkin;
input clr_in;
input clkout;
input clr_out;
output sigout;
output full;
wire [2:0] wptr,sync_wptr;
wire [2:0] rptr,sync_rptr;
wire full;
write_counter_2 write_counter(
.wptr (wptr ),
.full (full ),
.wq2_rptr (sync_rptr),
.winc (sigin ),
.wclk (clkin ),
.wrst_n (clr_in )
);
sync_reg_2 sync_write_ptr(
.out_ptr (sync_wptr),
.in_ptr (wptr ),
.clk (clkout ),
.rst_n (clr_out )
);
sync_reg_2 sync_read_ptr(
.out_ptr (sync_rptr),
.in_ptr (rptr ),
.clk (clkin ),
.rst_n (clr_in )
);
trans_counter_2 trans_counter(
.sigout (sigout ),
.rptr (rptr ),
.rq2_wptr (sync_wptr),
.rclk (clkout ),
.rrst_n (clr_out )
);
endmodule
module write_counter_2(
wptr,
full,
wq2_rptr,
winc,
wclk,
wrst_n
);
output [2:0] wptr;
output full;
input [2:0] wq2_rptr;
input winc, wclk, wrst_n;
reg [2:0] wbin;
wire [2:0] wgraynext, wbinnext;
wire wdec;
reg [2:0] wptr;
reg winc_reg;
wire [2:0] wbinnext_next;
// GRAYSTYLE2 pointer
always @(posedge wclk)
begin
if (wrst_n)
begin
{wbin, wptr} <= 0;
winc_reg<=0;
end
else
begin
{wbin, wptr} <= {wbinnext, wgraynext};
winc_reg <= winc;
end
end
assign wbinnext = wbin + winc_reg;
assign wdec = (wptr!=wq2_rptr);
assign wgraynext = (wbinnext>>1) ^ wbinnext;
assign wbinnext_next=(wbinnext+1);
assign full = (((wbinnext_next>>1)^wbinnext_next)==wq2_rptr);
endmodule
module trans_counter_2(
sigout,
rptr,
rq2_wptr,
rclk,
rrst_n
);
//output reg rempty,
//output [ADDRSIZE-1:0] raddr,
output sigout;
output [2:0] rptr;
input [2:0] rq2_wptr;
input rclk, rrst_n;
reg [2:0] rbin;
wire [2:0] rgraynext, rbinnext;
reg [2:0] rptr;
always @(posedge rclk)
begin
if (rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
end
assign rbinnext = rbin + sigout;//(rinc & ~rempty);
assign rgraynext = (rbin>>1) ^ rbin;//(rbinnext>>1) ^ rbinnext;
assign sigout=(rgraynext != rq2_wptr);
endmodule
module sync_reg_2(
out_ptr,
in_ptr,
clk,
rst_n
);
output [2:0] out_ptr;
input [2:0] in_ptr;
input clk, rst_n;
reg [2:0] out1_ptr;
reg [2:0] out_ptr;
always @(posedge clk)
begin
if (rst_n) {out_ptr,out1_ptr} <= 0;
else {out_ptr,out1_ptr} <= {out1_ptr,in_ptr};
end
endmodule
|
module ClockGenerator
(
input wire EXTERNAL_RESET_L,
output reg CLOCKS_STABLE_H,
input wire CLK_33MHz,
output wire CLK_80MHz,
output wire CLK_320MHz
);
localparam DLL_RESET_COUNTER_LEN = 4;
wire CLK_80MHz_GENERATOR_LOCKED_H, CLK_320MHz_GENERATOR_LOCKED_H;
reg [DLL_RESET_COUNTER_LEN-1:0] DLLResetCounter;
reg CLOCK_GENERATOR_RESET_H;
// This is a registered signal in order to avoid input setup time problems with all the flip flops that use it as a reset
reg CLK_80MHz_GENERATOR_LOCKED_H_REG, CLK_320MHz_GENERATOR_LOCKED_H_REG, EXT_RESET_CLK_80MHz_L;
always @(posedge CLK_80MHz) begin
EXT_RESET_CLK_80MHz_L <= EXTERNAL_RESET_L;
CLK_80MHz_GENERATOR_LOCKED_H_REG <= CLK_80MHz_GENERATOR_LOCKED_H;
// CLK_320MHz_GENERATOR_LOCKED_H_REG <= CLK_320MHz_GENERATOR_LOCKED_H;
CLOCKS_STABLE_H <= EXT_RESET_CLK_80MHz_L & DLLResetCounter[DLL_RESET_COUNTER_LEN-1] & CLK_80MHz_GENERATOR_LOCKED_H_REG;// & CLK_320MHz_GENERATOR_LOCKED_H_REG;
end
// This is a registered signal in order to avoid input setup time problems with all the flip flops that use it as a reset
reg EXT_RESET_CLK_33MHz_L;
// Make sure that the clocks stable signal is low right after FPGA configuration, and set the initial DLLResetCounter to 0
// right after configuration in order to simulate a reset button push.
initial begin
EXT_RESET_CLK_80MHz_L <= 1'b1;
DLLResetCounter <= 0;
CLOCKS_STABLE_H <= 1'b0;
CLOCK_GENERATOR_RESET_H <= 1'b0;
CLK_80MHz_GENERATOR_LOCKED_H_REG <= 1'b0;
// CLK_320MHz_GENERATOR_LOCKED_H_REG <= 1'b0;
end
always @(posedge(CLK_33MHz)) begin
EXT_RESET_CLK_33MHz_L <= EXTERNAL_RESET_L;
if (EXT_RESET_CLK_33MHz_L == 0) begin
DLLResetCounter <= 0;
CLOCK_GENERATOR_RESET_H <= 0;
end
else if (DLLResetCounter[DLL_RESET_COUNTER_LEN-1] == 1'b0) begin
DLLResetCounter <= DLLResetCounter + 1;
CLOCK_GENERATOR_RESET_H <= 1;
end
else
CLOCK_GENERATOR_RESET_H <= 0;
end
// 80MHz clock generation, based on page 91 of the Virtex 5 User Guide, and datasheet
// Fin = 33MHz, Fpfdmin = 19MHz, Fpfdmax = 450MHz, Fvcomin = 400MHz, Fvcomax = 900MHz
// Dmin = Fin/Fpfdmax = 1 (just satisfying the phase detector max frequency)
// Dmax = Fin/Fpfdmin = 1 (if you divide input clock by more than one, 33 MHz will be below 19MHz)
// Mmin = Fvcomin/Fin = 13 (round up to avoid hitting Fvcomin)
// Mmax = Dmin*Fvcomax/Fin = 27 (round down to avoid hitting Fvcomax)
// Mideal = Dmin*Fvcomax/Fin = 27
// In my spreadsheet I found an optimum of Din = 1, M = 17, D0 = 4 gives 140.25MHz
wire CLK_80MHz_FB, CLK_80MHz_Raw, CLK_80MHz_270_Raw;
wire CLK_320MHz_Raw;
/* defparam CLK_80MHz_Generator.CLKIN1_PERIOD = 25.0;
defparam CLK_80MHz_Generator.DIVCLK_DIVIDE = 1;
// 80 MHz
defparam CLK_80MHz_Generator.CLKFBOUT_MULT_F = 16.0;
defparam CLK_80MHz_Generator.CLKOUT0_DIVIDE_F = 16.0;
// 320 MHz
defparam CLK_80MHz_Generator.CLKOUT1_DIVIDE = 4;
MMCM_BASE CLK_80MHz_Generator (
.CLKFBOUT(CLK_80MHz_FB), // 1-bit MMCM Feedback clock output
.CLKFBOUTB(), // 1-bit Inverted MMCM feedback clock output
.CLKOUT0(CLK_80MHz_Raw), // 1-bit MMCM clock output 0
.CLKOUT0B(), // 1-bit Inverted MMCM clock output 0
.CLKOUT1(CLK_320MHz_Raw), // 1-bit MMCM clock output 1
.CLKOUT1B(), // 1-bit Inverted MMCM clock output 1
.CLKOUT2(), // 1-bit MMCM clock output 2
.CLKOUT2B(), // 1-bit Inverted MMCM clock output 2
.CLKOUT3(), // 1-bit MMCM clock output 3
.CLKOUT3B(), // 1-bit Inverted MMCM clock output 3
.CLKOUT4(), // 1-bit MMCM clock output 4
.CLKOUT5(), // 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integer
.CLKOUT6(), // 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integer
.LOCKED(CLK_80MHz_GENERATOR_LOCKED_H), // 1-bit MMC locked signal
.CLKFBIN(CLK_80MHz_FB), // 1-bit Feedback clock pin to the MMCM
.CLKIN1(CLK_33MHz), // 1-bit Reference clock pin 1 to the MMCM
.PWRDWN(1'b0), // 1-bit Power down
.RST(CLOCK_GENERATOR_RESET_H) // 1-bit MMCM global reset pin
);*/
pll_clocks CLK_80MHz_Generator (
.areset ( CLOCK_GENERATOR_RESET_H ),
.inclk0 ( CLK_33MHz ),
.c0 ( CLK_80MHz_Raw ),
.c1 ( CLK_320MHz_Raw ),
.locked ( CLK_80MHz_GENERATOR_LOCKED_H )
);
assign CLK_80MHz_FB = CLK_80MHz_Raw;
/*alt_pll CLK_80MHz_Generator (
.areset ( CLOCK_GENERATOR_RESET_H ),
.fbin ( CLK_80MHz_FB ),
.inclk0 ( CLK_33MHz ),
.c0 ( CLK_80MHz_Raw ),
.c1 ( CLK_320MHz_Raw ),
.fbout ( CLK_80MHz_FB ),
.locked ( CLK_80MHz_GENERATOR_LOCKED_H )
);*/
/* PLL_BASE CLK_80MHz_Generator (
.RST(CLOCK_GENERATOR_RESET_H), // Just use the first SRAM clock reset
.CLKIN(CLK_33MHz),
.CLKFBIN(CLK_80MHz_FB),
.CLKOUT0(CLK_80MHz_Raw),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(CLK_80MHz_FB),
.LOCKED(CLK_80MHz_GENERATOR_LOCKED_H)
);*/
//BUFG CLK_80MHz_Buffer ( .I(CLK_80MHz_Raw), .O(CLK_80MHz) );
//BUFG CLK_320MHz_Buffer ( .I(CLK_320MHz_Raw), .O(CLK_320MHz) );
assign CLK_80MHz = CLK_80MHz_Raw;
assign CLK_320MHz = CLK_320MHz_Raw;
// DDR2 200MHz clock, similar to above
// From the spreadsheet Din = 1, M = 25, D0 = 4 gives 206.25MHz
// From the spreadsheet Din = 1, M = 24, D0 = 4 gives 198.0MHz
/* defparam CLK_320MHz_Generator.CLKIN_PERIOD = 25;
defparam CLK_320MHz_Generator.DIVCLK_DIVIDE = 1;
// 333.33 MHz
defparam CLK_320MHz_Generator.CLKFBOUT_MULT = 16;
defparam CLK_320MHz_Generator.CLKOUT0_DIVIDE = 2;
defparam CLK_80MHz_Generator.CLKIN1_PERIOD = 25.0;
defparam CLK_80MHz_Generator.DIVCLK_DIVIDE = 1;
PLL_BASE CLK_320MHz_Generator (
.RST(CLOCK_GENERATOR_RESET_H), // Just use the first SRAM clock reset
.CLKIN(CLK_33MHz),
.CLKFBIN(CLK_320MHz_FB),
.CLKOUT0(CLK_320MHz_Raw),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(CLK_320MHz_FB),
.LOCKED(CLK_320MHz_GENERATOR_LOCKED_H)
);*/
endmodule
|
// $Id: c_add_nto1.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic n-input adder
//==============================================================================
module c_add_nto1
(data_in, data_out);
`include "c_functions.v"
// width of each input
parameter width = 1;
// number of inputs
parameter num_ports = 2;
// result width
localparam out_width = clogb(num_ports * (1 << width - 1) + 1);
// vector of inputs
input [0:width*num_ports-1] data_in;
// output data
output [0:out_width-1] data_out;
reg [0:out_width-1] data_out;
integer i;
always @(data_in)
begin
data_out = {out_width{1'b0}};
for(i = 0; i < num_ports; i = i + 1)
begin
data_out = data_out + data_in[i*width +: width];
end
end
endmodule
|
// $Id: c_align.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// align a vector inside another one
//==============================================================================
module c_align
(data_in, dest_in, data_out);
// width of input data
parameter in_width = 32;
// width of destination vector
parameter out_width = 32;
// offset at which to place input data within destination vector
// (portions of the input data that end up to the left or right of the
// destination vector will be trimmed)
parameter offset = 0;
// input vector
input [0:in_width-1] data_in;
// destination vector
input [0:out_width-1] dest_in;
// result
output [0:out_width-1] data_out;
wire [0:out_width-1] data_out;
genvar i;
generate
for(i = 0; i < out_width; i = i + 1)
begin:bits
if((i < offset) || (i >= (offset + in_width)))
assign data_out[i] = dest_in[i];
else
assign data_out[i] = data_in[i - offset];
end
endgenerate
endmodule
|
// $Id: c_arbiter.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic arbiter
//==============================================================================
module c_arbiter
(clk, reset, active, req, gnt, update);
`include "c_functions.v"
`include "c_constants.v"
// number of input ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 1;
// number fo bits required to select a port
localparam port_idx_width = clogb(num_ports);
// select type of arbiter to use
parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// request vector
input [0:num_priorities*num_ports-1] req;
// grant vector
output [0:num_priorities*num_ports-1] gnt;
wire [0:num_priorities*num_ports-1] gnt;
// update port priorities
input update;
generate
case(arbiter_type)
`ARBITER_TYPE_ROUND_ROBIN:
begin
c_rr_arbiter
#(.num_ports(num_ports),
.num_priorities(num_priorities),
.reset_type(reset_type))
rr_arb
(.clk(clk),
.reset(reset),
.active(active),
.req(req),
.gnt(gnt),
.update(update));
end
`ARBITER_TYPE_MATRIX:
begin
c_matrix_arbiter
#(.num_ports(num_ports),
.num_priorities(num_priorities),
.reset_type(reset_type))
matrix_arb
(.clk(clk),
.reset(reset),
.active(active),
.req(req),
.gnt(gnt),
.update(update));
end
`ARBITER_TYPE_DW_FCFS:
begin
// synopsys translate_off
if(num_priorities > 1)
begin
initial
begin
$display({"ERROR: DesignWare FCFS arbiter does not ",
"support multiple priorities."});
$stop;
end
end
// synopsys translate_on
if(num_ports == 1)
assign gnt = req;
else if(num_ports > 1)
begin
wire enable;
assign enable = active & update;
wire rst_n;
if(reset_type == `RESET_TYPE_ASYNC)
assign rst_n = ~reset;
else
assign rst_n = 1'b1;
wire init_n;
if(reset_type == `RESET_TYPE_SYNC)
assign init_n = ~reset;
else
assign init_n = 1'b1;
wire parked;
wire locked;
wire [0:port_idx_width-1] grant_index;
DW_arb_fcfs
#(.n(num_ports),
.park_mode(0),
.output_mode(0))
dw_fcfs_arb
(.clk(clk),
.rst_n(rst_n),
.init_n(init_n),
.enable(enable),
.request(req),
.lock({num_ports{1'b0}}),
.mask({num_ports{1'b0}}),
.parked(parked),
.locked(locked),
.grant(gnt),
.grant_index(grant_index));
end
end
endcase
endgenerate
endmodule
|
// $Id: c_binary_op.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// n-input generic binary operator
//==============================================================================
module c_binary_op
(data_in, data_out);
// number of inputs
parameter num_ports = 2;
// width of each input
parameter width = 1;
// select operator
parameter op = `BINARY_OP_XOR;
// vector of inputs
input [0:width*num_ports-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < width; i = i + 1)
begin:bit_positions
wire [0:num_ports-1] data;
genvar j;
for(j = 0; j < num_ports; j = j + 1)
begin:input_ports
assign data[j] = data_in[j*width+i];
end
case(op)
`BINARY_OP_AND:
assign data_out[i] = &data;
`BINARY_OP_NAND:
assign data_out[i] = ~&data;
`BINARY_OP_OR:
assign data_out[i] = |data;
`BINARY_OP_NOR:
assign data_out[i] = ~|data;
`BINARY_OP_XOR:
assign data_out[i] = ^data;
`BINARY_OP_XNOR:
assign data_out[i] = ~^data;
endcase
end
endgenerate
endmodule
|
// $Id: c_clkgate.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// a generic clock gating module
//==============================================================================
module c_clkgate
(clk, active, clk_gated);
input clk;
input active;
output clk_gated;
wire clk_gated;
reg active_q;
always @(clk, active)
begin
if(clk == 0)
active_q <= active;
end
assign clk_gated = clk & active_q;
endmodule
|
// $Id: c_crossbar.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// configurable crossbar module
//==============================================================================
module c_crossbar
(ctrl_ip_op, data_in_ip, data_out_op);
`include "c_constants.v"
// number of input/output ports
parameter num_in_ports = 5;
parameter num_out_ports = 5;
// width per port
parameter width = 32;
// select implementation variant
parameter crossbar_type = `CROSSBAR_TYPE_MUX;
// control signals (request matrix)
input [0:num_in_ports*num_out_ports-1] ctrl_ip_op;
// vector of input data
input [0:num_in_ports*width-1] data_in_ip;
// vector of output data
output [0:num_out_ports*width-1] data_out_op;
wire [0:num_out_ports*width-1] data_out_op;
wire [0:num_out_ports*num_in_ports-1] ctrl_op_ip;
c_interleave
#(.width(num_in_ports*num_out_ports),
.num_blocks(num_in_ports))
ctrl_intl
(.data_in(ctrl_ip_op),
.data_out(ctrl_op_ip));
generate
genvar op;
for(op = 0; op < num_out_ports; op = op + 1)
begin:ops
wire [0:width-1] data_out;
genvar ip;
case(crossbar_type)
`CROSSBAR_TYPE_TRISTATE:
begin
for(ip = 0; ip < num_in_ports; ip = ip + 1)
begin:tristate_ips
wire [0:width-1] in;
assign in = data_in_ip[ip*width:(ip+1)*width-1];
wire ctrl;
assign ctrl = ctrl_op_ip[op*num_in_ports+ip];
assign data_out = ctrl ? in : {width{1'bz}};
end
end
`CROSSBAR_TYPE_MUX:
begin
wire [0:num_in_ports-1] ctrl_ip;
assign ctrl_ip
= ctrl_op_ip[op*num_in_ports:(op+1)*num_in_ports-1];
c_select_1ofn
#(.width(width),
.num_ports(num_in_ports))
out_mux
(.select(ctrl_ip),
.data_in(data_in_ip),
.data_out(data_out));
end
`CROSSBAR_TYPE_DIST_MUX:
begin
wire [0:num_in_ports*width-1] data;
assign data[0:width-1] = data_in_ip[0:width-1];
for(ip = 1; ip < num_in_ports; ip = ip + 1)
begin:dist_mux_ips
wire [0:width-1] in;
assign in = data_in_ip[ip*width:(ip+1)*width-1];
wire [0:width-1] thru;
assign thru = data[(ip-1)*width:ip*width-1];
wire ctrl;
assign ctrl = ctrl_op_ip[op*num_in_ports+ip];
wire [0:width-1] out;
assign out = ctrl ? in : thru;
assign data[ip*width:(ip+1)*width-1] = out;
end
assign data_out
= data[(num_in_ports-1)*width:num_in_ports*width-1];
end
endcase
assign data_out_op[op*width:(op+1)*width-1] = data_out;
end
endgenerate
endmodule
|
// $Id: c_decode.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// decoder from binary to one-hot
//==============================================================================
module c_decode
(data_in, data_out);
`include "c_functions.v"
// number of output ports (i.e., width of decoded word)
parameter num_ports = 8;
localparam width = clogb(num_ports);
// encoded input data
input [0:width-1] data_in;
// decoded output data
output [0:num_ports-1] data_out;
wire [0:num_ports-1] data_out;
generate
genvar position;
for(position = 0; position < num_ports; position = position + 1)
begin:positions
assign data_out[position] = (data_in == position);
end
endgenerate
endmodule
|
// $Id: c_decr.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic modulo decrementer (i.e., decrementer with wraparound)
//==============================================================================
module c_decr
(data_in, data_out);
`include "c_functions.v"
parameter width = 3;
parameter [0:width-1] min_value = 0;
parameter [0:width-1] max_value = (1 << width) - 1;
localparam num_values = max_value - min_value + 1;
localparam cwidth = clogb(num_values);
// operand inputs
input [0:width-1] data_in;
// sum output
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire carry;
assign carry = ~|data_in[(width-cwidth):width-1];
wire wrap;
assign wrap = (data_in[(width-cwidth):width-1] ==
min_value[(width-cwidth):width-1]);
generate
if((1 << cwidth) == num_values)
begin
// if the range is a power of two, we can take advantage of natural
// wraparound for the LSBs
assign data_out[(width-cwidth):width-1]
= data_in[(width-cwidth):width-1] - 1'b1;
end
else
begin
// if the range is not a power of two, we need to implement
// explicit wraparound
assign data_out[(width-cwidth):width-1]
= wrap ?
max_value[(width-cwidth):width-1] :
(data_in[(width-cwidth):width-1] - 1'b1);
end
if(width > cwidth)
begin
if(min_value[0:(width-cwidth)-1] == max_value[0:(width-cwidth)-1])
begin
// if the MSBs are identical for the first and last value, we
// never need to change them
assign data_out[0:(width-cwidth)-1]
= data_in[0:(width-cwidth)-1];
end
else
begin
// if the first and last value have differing MSBs, we need to
// adjust them whenever either the LSBs overflow or wraparound
// occurs
assign data_out[0:(width-cwidth)-1]
= data_in[0:(width-cwidth)-1] - carry + wrap;
end
end
endgenerate
endmodule
|
// $Id: c_dff.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// configurable register
//==============================================================================
module c_dff
(clk, reset, active, d, q);
`include "c_constants.v"
// width of register
parameter width = 32;
// offset (left index) of register
parameter offset = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
parameter [offset:(offset+width)-1] reset_value = {width{1'b0}};
input clk;
input reset;
input active;
// data input
input [offset:(offset+width)-1] d;
// data output
output [offset:(offset+width)-1] q;
reg [offset:(offset+width)-1] q;
generate
case(reset_type)
`RESET_TYPE_ASYNC:
always @(posedge clk, posedge reset)
if(reset)
q <= reset_value;
else if(active)
q <= d;
`RESET_TYPE_SYNC:
always @(posedge clk)
if(reset)
q <= reset_value;
else if(active)
q <= d;
endcase
endgenerate
endmodule
|
// $Id: c_encode.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// encoder from one-hot to binary
//==============================================================================
module c_encode
(data_in, data_out);
`include "c_functions.v"
// number of input ports (i.e., decoded width)
parameter num_ports = 8;
localparam width = clogb(num_ports);
// one-hot input data
input [0:num_ports-1] data_in;
// binary encoded output data
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar level;
for(level = 0; level < width; level = level + 1)
begin:levels
wire [0:num_ports-1] bits;
genvar position;
for(position = 0; position < num_ports; position = position + 1)
begin:positions
if(position & (1 << level))
assign bits[position] = data_in[position];
else
assign bits[position] = 1'b0;
end
assign data_out[(width-1)-level] = |bits;
end
endgenerate
endmodule
|
// $Id: c_err_rpt.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// error reporting module
//==============================================================================
module c_err_rpt
(clk, reset, active, errors_in, errors_out);
`include "c_constants.v"
// number of error inputs
parameter num_errors = 1;
// select mode of operation
parameter capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// raw error inputs
input [0:num_errors-1] errors_in;
// registered and potentially held error outputs
output [0:num_errors-1] errors_out;
wire [0:num_errors-1] errors_out;
generate
if(capture_mode != `ERROR_CAPTURE_MODE_NONE)
begin
wire [0:num_errors-1] errors_s, errors_q;
case(capture_mode)
`ERROR_CAPTURE_MODE_NO_HOLD:
begin
assign errors_s = errors_in;
end
`ERROR_CAPTURE_MODE_HOLD_FIRST:
begin
assign errors_s = ~|errors_q ? errors_in : errors_q;
end
`ERROR_CAPTURE_MODE_HOLD_ALL:
begin
assign errors_s = errors_q | errors_in;
end
endcase
c_dff
#(.width(num_errors),
.reset_type(reset_type))
errorsq
(.clk(clk),
.reset(reset),
.active(active),
.d(errors_s),
.q(errors_q));
assign errors_out = errors_q;
end
else
assign errors_out = {num_errors{1'b0}};
endgenerate
endmodule
|
// $Id: c_fbgen.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic feedback polynomial generator
//==============================================================================
module c_fbgen
(feedback);
`include "c_constants.v"
// width of register (must be greater than one)
parameter width = 32;
// select one of possibly multiple provided polynomials
parameter index = 0;
// generated feedback polynomial
output [0:width-1] feedback;
wire [0:width-1] feedback;
generate
if(width == 1)
begin
assign feedback = 1'h1;
end
else if(width == 2)
begin
assign feedback = 2'h3;
end
else if(width == 3)
begin
if((index % 2) == 0) assign feedback = 3'h5;
else if((index % 2) == 1) assign feedback = 3'h6;
end
else if(width == 4)
begin
if((index % 2) == 0) assign feedback = 4'h9;
else if((index % 2) == 1) assign feedback = 4'hC;
end
else if(width == 5)
begin
if((index % 6) == 0) assign feedback = 5'h12;
else if((index % 6) == 1) assign feedback = 5'h14;
else if((index % 6) == 2) assign feedback = 5'h17;
else if((index % 6) == 3) assign feedback = 5'h1B;
else if((index % 6) == 4) assign feedback = 5'h1D;
else if((index % 6) == 5) assign feedback = 5'h1E;
end
else if(width == 6)
begin
if((index % 6) == 0) assign feedback = 6'h21;
else if((index % 6) == 1) assign feedback = 6'h2D;
else if((index % 6) == 2) assign feedback = 6'h30;
else if((index % 6) == 3) assign feedback = 6'h33;
else if((index % 6) == 4) assign feedback = 6'h36;
else if((index % 6) == 5) assign feedback = 6'h39;
end
else if(width == 7)
begin
if((index % 18) == 0) assign feedback = 7'h41;
else if((index % 18) == 1) assign feedback = 7'h44;
else if((index % 18) == 2) assign feedback = 7'h47;
else if((index % 18) == 3) assign feedback = 7'h48;
else if((index % 18) == 4) assign feedback = 7'h4E;
else if((index % 18) == 5) assign feedback = 7'h53;
else if((index % 18) == 6) assign feedback = 7'h55;
else if((index % 18) == 7) assign feedback = 7'h5C;
else if((index % 18) == 8) assign feedback = 7'h5F;
else if((index % 18) == 9) assign feedback = 7'h60;
else if((index % 18) == 10) assign feedback = 7'h65;
else if((index % 18) == 11) assign feedback = 7'h69;
else if((index % 18) == 12) assign feedback = 7'h6A;
else if((index % 18) == 13) assign feedback = 7'h72;
else if((index % 18) == 14) assign feedback = 7'h77;
else if((index % 18) == 15) assign feedback = 7'h78;
else if((index % 18) == 16) assign feedback = 7'h7B;
else if((index % 18) == 17) assign feedback = 7'h7E;
end
else if(width == 8)
begin
if((index % 16) == 0) assign feedback = 8'h8E;
else if((index % 16) == 1) assign feedback = 8'h95;
else if((index % 16) == 2) assign feedback = 8'h96;
else if((index % 16) == 3) assign feedback = 8'hA6;
else if((index % 16) == 4) assign feedback = 8'hAF;
else if((index % 16) == 5) assign feedback = 8'hB1;
else if((index % 16) == 6) assign feedback = 8'hB2;
else if((index % 16) == 7) assign feedback = 8'hB4;
else if((index % 16) == 8) assign feedback = 8'hB8;
else if((index % 16) == 9) assign feedback = 8'hC3;
else if((index % 16) == 10) assign feedback = 8'hC6;
else if((index % 16) == 11) assign feedback = 8'hD4;
else if((index % 16) == 12) assign feedback = 8'hE1;
else if((index % 16) == 13) assign feedback = 8'hE7;
else if((index % 16) == 14) assign feedback = 8'hF3;
else if((index % 16) == 15) assign feedback = 8'hFA;
end
else if(width == 9)
begin
if((index % 48) == 0) assign feedback = 9'h108;
else if((index % 48) == 1) assign feedback = 9'h10D;
else if((index % 48) == 2) assign feedback = 9'h110;
else if((index % 48) == 3) assign feedback = 9'h116;
else if((index % 48) == 4) assign feedback = 9'h119;
else if((index % 48) == 5) assign feedback = 9'h12C;
else if((index % 48) == 6) assign feedback = 9'h12F;
else if((index % 48) == 7) assign feedback = 9'h134;
else if((index % 48) == 8) assign feedback = 9'h137;
else if((index % 48) == 9) assign feedback = 9'h13B;
else if((index % 48) == 10) assign feedback = 9'h13E;
else if((index % 48) == 11) assign feedback = 9'h143;
else if((index % 48) == 12) assign feedback = 9'h14A;
else if((index % 48) == 13) assign feedback = 9'h151;
else if((index % 48) == 14) assign feedback = 9'h152;
else if((index % 48) == 15) assign feedback = 9'h157;
else if((index % 48) == 16) assign feedback = 9'h15B;
else if((index % 48) == 17) assign feedback = 9'h15E;
else if((index % 48) == 18) assign feedback = 9'h167;
else if((index % 48) == 19) assign feedback = 9'h168;
else if((index % 48) == 20) assign feedback = 9'h16D;
else if((index % 48) == 21) assign feedback = 9'h17A;
else if((index % 48) == 22) assign feedback = 9'h17C;
else if((index % 48) == 23) assign feedback = 9'h189;
else if((index % 48) == 24) assign feedback = 9'h18A;
else if((index % 48) == 25) assign feedback = 9'h18F;
else if((index % 48) == 26) assign feedback = 9'h191;
else if((index % 48) == 27) assign feedback = 9'h198;
else if((index % 48) == 28) assign feedback = 9'h19D;
else if((index % 48) == 29) assign feedback = 9'h1A7;
else if((index % 48) == 30) assign feedback = 9'h1AD;
else if((index % 48) == 31) assign feedback = 9'h1B0;
else if((index % 48) == 32) assign feedback = 9'h1B5;
else if((index % 48) == 33) assign feedback = 9'h1B6;
else if((index % 48) == 34) assign feedback = 9'h1B9;
else if((index % 48) == 35) assign feedback = 9'h1BF;
else if((index % 48) == 36) assign feedback = 9'h1C2;
else if((index % 48) == 37) assign feedback = 9'h1C7;
else if((index % 48) == 38) assign feedback = 9'h1DA;
else if((index % 48) == 39) assign feedback = 9'h1DC;
else if((index % 48) == 40) assign feedback = 9'h1E3;
else if((index % 48) == 41) assign feedback = 9'h1E5;
else if((index % 48) == 42) assign feedback = 9'h1E6;
else if((index % 48) == 43) assign feedback = 9'h1EA;
else if((index % 48) == 44) assign feedback = 9'h1EC;
else if((index % 48) == 45) assign feedback = 9'h1F1;
else if((index % 48) == 46) assign feedback = 9'h1F4;
else if((index % 48) == 47) assign feedback = 9'h1FD;
end
else if(width == 10)
begin
if((index % 60) == 0) assign feedback = 10'h204;
else if((index % 60) == 1) assign feedback = 10'h20D;
else if((index % 60) == 2) assign feedback = 10'h213;
else if((index % 60) == 3) assign feedback = 10'h216;
else if((index % 60) == 4) assign feedback = 10'h232;
else if((index % 60) == 5) assign feedback = 10'h237;
else if((index % 60) == 6) assign feedback = 10'h240;
else if((index % 60) == 7) assign feedback = 10'h245;
else if((index % 60) == 8) assign feedback = 10'h262;
else if((index % 60) == 9) assign feedback = 10'h26B;
else if((index % 60) == 10) assign feedback = 10'h273;
else if((index % 60) == 11) assign feedback = 10'h279;
else if((index % 60) == 12) assign feedback = 10'h27F;
else if((index % 60) == 13) assign feedback = 10'h286;
else if((index % 60) == 14) assign feedback = 10'h28C;
else if((index % 60) == 15) assign feedback = 10'h291;
else if((index % 60) == 16) assign feedback = 10'h298;
else if((index % 60) == 17) assign feedback = 10'h29E;
else if((index % 60) == 18) assign feedback = 10'h2A1;
else if((index % 60) == 19) assign feedback = 10'h2AB;
else if((index % 60) == 20) assign feedback = 10'h2B5;
else if((index % 60) == 21) assign feedback = 10'h2C2;
else if((index % 60) == 22) assign feedback = 10'h2C7;
else if((index % 60) == 23) assign feedback = 10'h2CB;
else if((index % 60) == 24) assign feedback = 10'h2D0;
else if((index % 60) == 25) assign feedback = 10'h2E3;
else if((index % 60) == 26) assign feedback = 10'h2F2;
else if((index % 60) == 27) assign feedback = 10'h2FB;
else if((index % 60) == 28) assign feedback = 10'h2FD;
else if((index % 60) == 29) assign feedback = 10'h309;
else if((index % 60) == 30) assign feedback = 10'h30A;
else if((index % 60) == 31) assign feedback = 10'h312;
else if((index % 60) == 32) assign feedback = 10'h31B;
else if((index % 60) == 33) assign feedback = 10'h321;
else if((index % 60) == 34) assign feedback = 10'h327;
else if((index % 60) == 35) assign feedback = 10'h32D;
else if((index % 60) == 36) assign feedback = 10'h33C;
else if((index % 60) == 37) assign feedback = 10'h33F;
else if((index % 60) == 38) assign feedback = 10'h344;
else if((index % 60) == 39) assign feedback = 10'h35A;
else if((index % 60) == 40) assign feedback = 10'h360;
else if((index % 60) == 41) assign feedback = 10'h369;
else if((index % 60) == 42) assign feedback = 10'h36F;
else if((index % 60) == 43) assign feedback = 10'h37E;
else if((index % 60) == 44) assign feedback = 10'h38B;
else if((index % 60) == 45) assign feedback = 10'h38E;
else if((index % 60) == 46) assign feedback = 10'h390;
else if((index % 60) == 47) assign feedback = 10'h39C;
else if((index % 60) == 48) assign feedback = 10'h3A3;
else if((index % 60) == 49) assign feedback = 10'h3A6;
else if((index % 60) == 50) assign feedback = 10'h3AA;
else if((index % 60) == 51) assign feedback = 10'h3AC;
else if((index % 60) == 52) assign feedback = 10'h3B1;
else if((index % 60) == 53) assign feedback = 10'h3BE;
else if((index % 60) == 54) assign feedback = 10'h3C6;
else if((index % 60) == 55) assign feedback = 10'h3C9;
else if((index % 60) == 56) assign feedback = 10'h3D8;
else if((index % 60) == 57) assign feedback = 10'h3ED;
else if((index % 60) == 58) assign feedback = 10'h3F9;
else if((index % 60) == 59) assign feedback = 10'h3FC;
end
else if(width == 11)
begin
if((index % 100) == 0) assign feedback = 11'h402;
else if((index % 100) == 1) assign feedback = 11'h40B;
else if((index % 100) == 2) assign feedback = 11'h415;
else if((index % 100) == 3) assign feedback = 11'h416;
else if((index % 100) == 4) assign feedback = 11'h423;
else if((index % 100) == 5) assign feedback = 11'h431;
else if((index % 100) == 6) assign feedback = 11'h432;
else if((index % 100) == 7) assign feedback = 11'h438;
else if((index % 100) == 8) assign feedback = 11'h43D;
else if((index % 100) == 9) assign feedback = 11'h446;
else if((index % 100) == 10) assign feedback = 11'h44A;
else if((index % 100) == 11) assign feedback = 11'h44F;
else if((index % 100) == 12) assign feedback = 11'h454;
else if((index % 100) == 13) assign feedback = 11'h458;
else if((index % 100) == 14) assign feedback = 11'h467;
else if((index % 100) == 15) assign feedback = 11'h468;
else if((index % 100) == 16) assign feedback = 11'h470;
else if((index % 100) == 17) assign feedback = 11'h473;
else if((index % 100) == 18) assign feedback = 11'h475;
else if((index % 100) == 19) assign feedback = 11'h47A;
else if((index % 100) == 20) assign feedback = 11'h486;
else if((index % 100) == 21) assign feedback = 11'h489;
else if((index % 100) == 22) assign feedback = 11'h492;
else if((index % 100) == 23) assign feedback = 11'h494;
else if((index % 100) == 24) assign feedback = 11'h49D;
else if((index % 100) == 25) assign feedback = 11'h49E;
else if((index % 100) == 26) assign feedback = 11'h4A2;
else if((index % 100) == 27) assign feedback = 11'h4A4;
else if((index % 100) == 28) assign feedback = 11'h4A8;
else if((index % 100) == 29) assign feedback = 11'h4AD;
else if((index % 100) == 30) assign feedback = 11'h4B9;
else if((index % 100) == 31) assign feedback = 11'h4BA;
else if((index % 100) == 32) assign feedback = 11'h4BF;
else if((index % 100) == 33) assign feedback = 11'h4C1;
else if((index % 100) == 34) assign feedback = 11'h4C7;
else if((index % 100) == 35) assign feedback = 11'h4D5;
else if((index % 100) == 36) assign feedback = 11'h4D6;
else if((index % 100) == 37) assign feedback = 11'h4DC;
else if((index % 100) == 38) assign feedback = 11'h4E3;
else if((index % 100) == 39) assign feedback = 11'h4EC;
else if((index % 100) == 40) assign feedback = 11'h4F2;
else if((index % 100) == 41) assign feedback = 11'h4FB;
else if((index % 100) == 42) assign feedback = 11'h500;
else if((index % 100) == 43) assign feedback = 11'h503;
else if((index % 100) == 44) assign feedback = 11'h509;
else if((index % 100) == 45) assign feedback = 11'h50A;
else if((index % 100) == 46) assign feedback = 11'h514;
else if((index % 100) == 47) assign feedback = 11'h524;
else if((index % 100) == 48) assign feedback = 11'h530;
else if((index % 100) == 49) assign feedback = 11'h536;
else if((index % 100) == 50) assign feedback = 11'h53C;
else if((index % 100) == 51) assign feedback = 11'h53F;
else if((index % 100) == 52) assign feedback = 11'h542;
else if((index % 100) == 53) assign feedback = 11'h548;
else if((index % 100) == 54) assign feedback = 11'h54E;
else if((index % 100) == 55) assign feedback = 11'h553;
else if((index % 100) == 56) assign feedback = 11'h555;
else if((index % 100) == 57) assign feedback = 11'h559;
else if((index % 100) == 58) assign feedback = 11'h55A;
else if((index % 100) == 59) assign feedback = 11'h56A;
else if((index % 100) == 60) assign feedback = 11'h56F;
else if((index % 100) == 61) assign feedback = 11'h574;
else if((index % 100) == 62) assign feedback = 11'h577;
else if((index % 100) == 63) assign feedback = 11'h578;
else if((index % 100) == 64) assign feedback = 11'h57D;
else if((index % 100) == 65) assign feedback = 11'h581;
else if((index % 100) == 66) assign feedback = 11'h584;
else if((index % 100) == 67) assign feedback = 11'h588;
else if((index % 100) == 68) assign feedback = 11'h599;
else if((index % 100) == 69) assign feedback = 11'h59F;
else if((index % 100) == 70) assign feedback = 11'h5A0;
else if((index % 100) == 71) assign feedback = 11'h5A5;
else if((index % 100) == 72) assign feedback = 11'h5AC;
else if((index % 100) == 73) assign feedback = 11'h5AF;
else if((index % 100) == 74) assign feedback = 11'h5B2;
else if((index % 100) == 75) assign feedback = 11'h5B7;
else if((index % 100) == 76) assign feedback = 11'h5BE;
else if((index % 100) == 77) assign feedback = 11'h5C3;
else if((index % 100) == 78) assign feedback = 11'h5C5;
else if((index % 100) == 79) assign feedback = 11'h5C9;
else if((index % 100) == 80) assign feedback = 11'h5CA;
else if((index % 100) == 81) assign feedback = 11'h5D7;
else if((index % 100) == 82) assign feedback = 11'h5DB;
else if((index % 100) == 83) assign feedback = 11'h5DE;
else if((index % 100) == 84) assign feedback = 11'h5E4;
else if((index % 100) == 85) assign feedback = 11'h5ED;
else if((index % 100) == 86) assign feedback = 11'h5EE;
else if((index % 100) == 87) assign feedback = 11'h5F3;
else if((index % 100) == 88) assign feedback = 11'h5F6;
else if((index % 100) == 89) assign feedback = 11'h605;
else if((index % 100) == 90) assign feedback = 11'h606;
else if((index % 100) == 91) assign feedback = 11'h60C;
else if((index % 100) == 92) assign feedback = 11'h60F;
else if((index % 100) == 93) assign feedback = 11'h62B;
else if((index % 100) == 94) assign feedback = 11'h630;
else if((index % 100) == 95) assign feedback = 11'h635;
else if((index % 100) == 96) assign feedback = 11'h639;
else if((index % 100) == 97) assign feedback = 11'h642;
else if((index % 100) == 98) assign feedback = 11'h644;
else if((index % 100) == 99) assign feedback = 11'h64B;
end
else if(width == 12)
begin
if((index % 100) == 0) assign feedback = 12'h829;
else if((index % 100) == 1) assign feedback = 12'h834;
else if((index % 100) == 2) assign feedback = 12'h83D;
else if((index % 100) == 3) assign feedback = 12'h83E;
else if((index % 100) == 4) assign feedback = 12'h84C;
else if((index % 100) == 5) assign feedback = 12'h868;
else if((index % 100) == 6) assign feedback = 12'h875;
else if((index % 100) == 7) assign feedback = 12'h883;
else if((index % 100) == 8) assign feedback = 12'h88F;
else if((index % 100) == 9) assign feedback = 12'h891;
else if((index % 100) == 10) assign feedback = 12'h89D;
else if((index % 100) == 11) assign feedback = 12'h8A7;
else if((index % 100) == 12) assign feedback = 12'h8AB;
else if((index % 100) == 13) assign feedback = 12'h8B0;
else if((index % 100) == 14) assign feedback = 12'h8B5;
else if((index % 100) == 15) assign feedback = 12'h8C2;
else if((index % 100) == 16) assign feedback = 12'h8D9;
else if((index % 100) == 17) assign feedback = 12'h8EC;
else if((index % 100) == 18) assign feedback = 12'h8EF;
else if((index % 100) == 19) assign feedback = 12'h906;
else if((index % 100) == 20) assign feedback = 12'h91B;
else if((index % 100) == 21) assign feedback = 12'h91E;
else if((index % 100) == 22) assign feedback = 12'h933;
else if((index % 100) == 23) assign feedback = 12'h939;
else if((index % 100) == 24) assign feedback = 12'h93F;
else if((index % 100) == 25) assign feedback = 12'h95C;
else if((index % 100) == 26) assign feedback = 12'h960;
else if((index % 100) == 27) assign feedback = 12'h965;
else if((index % 100) == 28) assign feedback = 12'h987;
else if((index % 100) == 29) assign feedback = 12'h98E;
else if((index % 100) == 30) assign feedback = 12'h990;
else if((index % 100) == 31) assign feedback = 12'h99C;
else if((index % 100) == 32) assign feedback = 12'h99F;
else if((index % 100) == 33) assign feedback = 12'h9A6;
else if((index % 100) == 34) assign feedback = 12'h9B8;
else if((index % 100) == 35) assign feedback = 12'h9CC;
else if((index % 100) == 36) assign feedback = 12'h9D1;
else if((index % 100) == 37) assign feedback = 12'h9D4;
else if((index % 100) == 38) assign feedback = 12'hA03;
else if((index % 100) == 39) assign feedback = 12'hA18;
else if((index % 100) == 40) assign feedback = 12'hA1B;
else if((index % 100) == 41) assign feedback = 12'hA27;
else if((index % 100) == 42) assign feedback = 12'hA2E;
else if((index % 100) == 43) assign feedback = 12'hA33;
else if((index % 100) == 44) assign feedback = 12'hA3A;
else if((index % 100) == 45) assign feedback = 12'hA53;
else if((index % 100) == 46) assign feedback = 12'hA56;
else if((index % 100) == 47) assign feedback = 12'hA69;
else if((index % 100) == 48) assign feedback = 12'hA87;
else if((index % 100) == 49) assign feedback = 12'hA8E;
else if((index % 100) == 50) assign feedback = 12'hAA6;
else if((index % 100) == 51) assign feedback = 12'hAC9;
else if((index % 100) == 52) assign feedback = 12'hAE2;
else if((index % 100) == 53) assign feedback = 12'hAEB;
else if((index % 100) == 54) assign feedback = 12'hAEE;
else if((index % 100) == 55) assign feedback = 12'hAF5;
else if((index % 100) == 56) assign feedback = 12'hB04;
else if((index % 100) == 57) assign feedback = 12'hB23;
else if((index % 100) == 58) assign feedback = 12'hB2A;
else if((index % 100) == 59) assign feedback = 12'hB2C;
else if((index % 100) == 60) assign feedback = 12'hB52;
else if((index % 100) == 61) assign feedback = 12'hB5E;
else if((index % 100) == 62) assign feedback = 12'hB8A;
else if((index % 100) == 63) assign feedback = 12'hB8C;
else if((index % 100) == 64) assign feedback = 12'hBA1;
else if((index % 100) == 65) assign feedback = 12'hBA2;
else if((index % 100) == 66) assign feedback = 12'hBBA;
else if((index % 100) == 67) assign feedback = 12'hBC4;
else if((index % 100) == 68) assign feedback = 12'hBD6;
else if((index % 100) == 69) assign feedback = 12'hBD9;
else if((index % 100) == 70) assign feedback = 12'hBDF;
else if((index % 100) == 71) assign feedback = 12'hBE0;
else if((index % 100) == 72) assign feedback = 12'hC2B;
else if((index % 100) == 73) assign feedback = 12'hC2E;
else if((index % 100) == 74) assign feedback = 12'hC48;
else if((index % 100) == 75) assign feedback = 12'hC4B;
else if((index % 100) == 76) assign feedback = 12'hC5C;
else if((index % 100) == 77) assign feedback = 12'hC77;
else if((index % 100) == 78) assign feedback = 12'hC8D;
else if((index % 100) == 79) assign feedback = 12'hC9A;
else if((index % 100) == 80) assign feedback = 12'hCA0;
else if((index % 100) == 81) assign feedback = 12'hCB2;
else if((index % 100) == 82) assign feedback = 12'hCBD;
else if((index % 100) == 83) assign feedback = 12'hCC5;
else if((index % 100) == 84) assign feedback = 12'hCD8;
else if((index % 100) == 85) assign feedback = 12'hCDE;
else if((index % 100) == 86) assign feedback = 12'hCE4;
else if((index % 100) == 87) assign feedback = 12'hCE7;
else if((index % 100) == 88) assign feedback = 12'hCF3;
else if((index % 100) == 89) assign feedback = 12'hD0D;
else if((index % 100) == 90) assign feedback = 12'hD15;
else if((index % 100) == 91) assign feedback = 12'hD19;
else if((index % 100) == 92) assign feedback = 12'hD34;
else if((index % 100) == 93) assign feedback = 12'hD45;
else if((index % 100) == 94) assign feedback = 12'hD68;
else if((index % 100) == 95) assign feedback = 12'hD70;
else if((index % 100) == 96) assign feedback = 12'hD7A;
else if((index % 100) == 97) assign feedback = 12'hD85;
else if((index % 100) == 98) assign feedback = 12'hD89;
else if((index % 100) == 99) assign feedback = 12'hD8F;
end
else if(width == 13)
begin
if((index % 100) == 0) assign feedback = 13'h100D;
else if((index % 100) == 1) assign feedback = 13'h1013;
else if((index % 100) == 2) assign feedback = 13'h101A;
else if((index % 100) == 3) assign feedback = 13'h1029;
else if((index % 100) == 4) assign feedback = 13'h1032;
else if((index % 100) == 5) assign feedback = 13'h1037;
else if((index % 100) == 6) assign feedback = 13'h1045;
else if((index % 100) == 7) assign feedback = 13'h1046;
else if((index % 100) == 8) assign feedback = 13'h104F;
else if((index % 100) == 9) assign feedback = 13'h1052;
else if((index % 100) == 10) assign feedback = 13'h1057;
else if((index % 100) == 11) assign feedback = 13'h105D;
else if((index % 100) == 12) assign feedback = 13'h105E;
else if((index % 100) == 13) assign feedback = 13'h1061;
else if((index % 100) == 14) assign feedback = 13'h1064;
else if((index % 100) == 15) assign feedback = 13'h1070;
else if((index % 100) == 16) assign feedback = 13'h1079;
else if((index % 100) == 17) assign feedback = 13'h1086;
else if((index % 100) == 18) assign feedback = 13'h108A;
else if((index % 100) == 19) assign feedback = 13'h1094;
else if((index % 100) == 20) assign feedback = 13'h1097;
else if((index % 100) == 21) assign feedback = 13'h109D;
else if((index % 100) == 22) assign feedback = 13'h10A1;
else if((index % 100) == 23) assign feedback = 13'h10B3;
else if((index % 100) == 24) assign feedback = 13'h10B5;
else if((index % 100) == 25) assign feedback = 13'h10BC;
else if((index % 100) == 26) assign feedback = 13'h10C4;
else if((index % 100) == 27) assign feedback = 13'h10CB;
else if((index % 100) == 28) assign feedback = 13'h10CE;
else if((index % 100) == 29) assign feedback = 13'h10DF;
else if((index % 100) == 30) assign feedback = 13'h10E0;
else if((index % 100) == 31) assign feedback = 13'h10E3;
else if((index % 100) == 32) assign feedback = 13'h10E6;
else if((index % 100) == 33) assign feedback = 13'h10EF;
else if((index % 100) == 34) assign feedback = 13'h10F1;
else if((index % 100) == 35) assign feedback = 13'h10F8;
else if((index % 100) == 36) assign feedback = 13'h10FD;
else if((index % 100) == 37) assign feedback = 13'h110C;
else if((index % 100) == 38) assign feedback = 13'h1112;
else if((index % 100) == 39) assign feedback = 13'h111B;
else if((index % 100) == 40) assign feedback = 13'h111E;
else if((index % 100) == 41) assign feedback = 13'h1121;
else if((index % 100) == 42) assign feedback = 13'h112D;
else if((index % 100) == 43) assign feedback = 13'h112E;
else if((index % 100) == 44) assign feedback = 13'h113C;
else if((index % 100) == 45) assign feedback = 13'h113F;
else if((index % 100) == 46) assign feedback = 13'h1144;
else if((index % 100) == 47) assign feedback = 13'h114B;
else if((index % 100) == 48) assign feedback = 13'h114D;
else if((index % 100) == 49) assign feedback = 13'h1159;
else if((index % 100) == 50) assign feedback = 13'h115F;
else if((index % 100) == 51) assign feedback = 13'h1166;
else if((index % 100) == 52) assign feedback = 13'h1177;
else if((index % 100) == 53) assign feedback = 13'h117B;
else if((index % 100) == 54) assign feedback = 13'h117D;
else if((index % 100) == 55) assign feedback = 13'h1182;
else if((index % 100) == 56) assign feedback = 13'h1193;
else if((index % 100) == 57) assign feedback = 13'h1195;
else if((index % 100) == 58) assign feedback = 13'h11A3;
else if((index % 100) == 59) assign feedback = 13'h11AA;
else if((index % 100) == 60) assign feedback = 13'h11AC;
else if((index % 100) == 61) assign feedback = 13'h11B7;
else if((index % 100) == 62) assign feedback = 13'h11B8;
else if((index % 100) == 63) assign feedback = 13'h11BE;
else if((index % 100) == 64) assign feedback = 13'h11C3;
else if((index % 100) == 65) assign feedback = 13'h11C6;
else if((index % 100) == 66) assign feedback = 13'h11CA;
else if((index % 100) == 67) assign feedback = 13'h11D1;
else if((index % 100) == 68) assign feedback = 13'h11D4;
else if((index % 100) == 69) assign feedback = 13'h11D8;
else if((index % 100) == 70) assign feedback = 13'h11DB;
else if((index % 100) == 71) assign feedback = 13'h11DD;
else if((index % 100) == 72) assign feedback = 13'h11F0;
else if((index % 100) == 73) assign feedback = 13'h11F6;
else if((index % 100) == 74) assign feedback = 13'h11FC;
else if((index % 100) == 75) assign feedback = 13'h1205;
else if((index % 100) == 76) assign feedback = 13'h1209;
else if((index % 100) == 77) assign feedback = 13'h120F;
else if((index % 100) == 78) assign feedback = 13'h1212;
else if((index % 100) == 79) assign feedback = 13'h1214;
else if((index % 100) == 80) assign feedback = 13'h121E;
else if((index % 100) == 81) assign feedback = 13'h1228;
else if((index % 100) == 82) assign feedback = 13'h122B;
else if((index % 100) == 83) assign feedback = 13'h1230;
else if((index % 100) == 84) assign feedback = 13'h1236;
else if((index % 100) == 85) assign feedback = 13'h123F;
else if((index % 100) == 86) assign feedback = 13'h1241;
else if((index % 100) == 87) assign feedback = 13'h124D;
else if((index % 100) == 88) assign feedback = 13'h124E;
else if((index % 100) == 89) assign feedback = 13'h125A;
else if((index % 100) == 90) assign feedback = 13'h125F;
else if((index % 100) == 91) assign feedback = 13'h1260;
else if((index % 100) == 92) assign feedback = 13'h1263;
else if((index % 100) == 93) assign feedback = 13'h1265;
else if((index % 100) == 94) assign feedback = 13'h1271;
else if((index % 100) == 95) assign feedback = 13'h1284;
else if((index % 100) == 96) assign feedback = 13'h128B;
else if((index % 100) == 97) assign feedback = 13'h128E;
else if((index % 100) == 98) assign feedback = 13'h1290;
else if((index % 100) == 99) assign feedback = 13'h1296;
end
else if(width == 14)
begin
if((index % 100) == 0) assign feedback = 14'h2015;
else if((index % 100) == 1) assign feedback = 14'h201C;
else if((index % 100) == 2) assign feedback = 14'h2029;
else if((index % 100) == 3) assign feedback = 14'h202F;
else if((index % 100) == 4) assign feedback = 14'h203D;
else if((index % 100) == 5) assign feedback = 14'h2054;
else if((index % 100) == 6) assign feedback = 14'h2057;
else if((index % 100) == 7) assign feedback = 14'h205D;
else if((index % 100) == 8) assign feedback = 14'h205E;
else if((index % 100) == 9) assign feedback = 14'h2067;
else if((index % 100) == 10) assign feedback = 14'h2075;
else if((index % 100) == 11) assign feedback = 14'h2079;
else if((index % 100) == 12) assign feedback = 14'h2086;
else if((index % 100) == 13) assign feedback = 14'h2089;
else if((index % 100) == 14) assign feedback = 14'h209D;
else if((index % 100) == 15) assign feedback = 14'h20A1;
else if((index % 100) == 16) assign feedback = 14'h20CD;
else if((index % 100) == 17) assign feedback = 14'h20CE;
else if((index % 100) == 18) assign feedback = 14'h20D3;
else if((index % 100) == 19) assign feedback = 14'h20D6;
else if((index % 100) == 20) assign feedback = 14'h20DA;
else if((index % 100) == 21) assign feedback = 14'h20EA;
else if((index % 100) == 22) assign feedback = 14'h20EC;
else if((index % 100) == 23) assign feedback = 14'h20F8;
else if((index % 100) == 24) assign feedback = 14'h2106;
else if((index % 100) == 25) assign feedback = 14'h212B;
else if((index % 100) == 26) assign feedback = 14'h2130;
else if((index % 100) == 27) assign feedback = 14'h213F;
else if((index % 100) == 28) assign feedback = 14'h2142;
else if((index % 100) == 29) assign feedback = 14'h214E;
else if((index % 100) == 30) assign feedback = 14'h2163;
else if((index % 100) == 31) assign feedback = 14'h2165;
else if((index % 100) == 32) assign feedback = 14'h2166;
else if((index % 100) == 33) assign feedback = 14'h2171;
else if((index % 100) == 34) assign feedback = 14'h2174;
else if((index % 100) == 35) assign feedback = 14'h2177;
else if((index % 100) == 36) assign feedback = 14'h2184;
else if((index % 100) == 37) assign feedback = 14'h2190;
else if((index % 100) == 38) assign feedback = 14'h219F;
else if((index % 100) == 39) assign feedback = 14'h21BE;
else if((index % 100) == 40) assign feedback = 14'h21C3;
else if((index % 100) == 41) assign feedback = 14'h21CA;
else if((index % 100) == 42) assign feedback = 14'h21D7;
else if((index % 100) == 43) assign feedback = 14'h21E4;
else if((index % 100) == 44) assign feedback = 14'h21F5;
else if((index % 100) == 45) assign feedback = 14'h21F6;
else if((index % 100) == 46) assign feedback = 14'h2205;
else if((index % 100) == 47) assign feedback = 14'h2221;
else if((index % 100) == 48) assign feedback = 14'h2239;
else if((index % 100) == 49) assign feedback = 14'h2269;
else if((index % 100) == 50) assign feedback = 14'h226A;
else if((index % 100) == 51) assign feedback = 14'h226F;
else if((index % 100) == 52) assign feedback = 14'h2271;
else if((index % 100) == 53) assign feedback = 14'h227D;
else if((index % 100) == 54) assign feedback = 14'h2295;
else if((index % 100) == 55) assign feedback = 14'h229C;
else if((index % 100) == 56) assign feedback = 14'h22AC;
else if((index % 100) == 57) assign feedback = 14'h22B7;
else if((index % 100) == 58) assign feedback = 14'h22CC;
else if((index % 100) == 59) assign feedback = 14'h22CF;
else if((index % 100) == 60) assign feedback = 14'h22D2;
else if((index % 100) == 61) assign feedback = 14'h22DB;
else if((index % 100) == 62) assign feedback = 14'h22E2;
else if((index % 100) == 63) assign feedback = 14'h22EB;
else if((index % 100) == 64) assign feedback = 14'h22F3;
else if((index % 100) == 65) assign feedback = 14'h22F9;
else if((index % 100) == 66) assign feedback = 14'h22FF;
else if((index % 100) == 67) assign feedback = 14'h2307;
else if((index % 100) == 68) assign feedback = 14'h230E;
else if((index % 100) == 69) assign feedback = 14'h2313;
else if((index % 100) == 70) assign feedback = 14'h231A;
else if((index % 100) == 71) assign feedback = 14'h2323;
else if((index % 100) == 72) assign feedback = 14'h232C;
else if((index % 100) == 73) assign feedback = 14'h2331;
else if((index % 100) == 74) assign feedback = 14'h2338;
else if((index % 100) == 75) assign feedback = 14'h233D;
else if((index % 100) == 76) assign feedback = 14'h2352;
else if((index % 100) == 77) assign feedback = 14'h2362;
else if((index % 100) == 78) assign feedback = 14'h2367;
else if((index % 100) == 79) assign feedback = 14'h236D;
else if((index % 100) == 80) assign feedback = 14'h2398;
else if((index % 100) == 81) assign feedback = 14'h23A7;
else if((index % 100) == 82) assign feedback = 14'h23BF;
else if((index % 100) == 83) assign feedback = 14'h23D3;
else if((index % 100) == 84) assign feedback = 14'h23E0;
else if((index % 100) == 85) assign feedback = 14'h23F2;
else if((index % 100) == 86) assign feedback = 14'h23F4;
else if((index % 100) == 87) assign feedback = 14'h23F7;
else if((index % 100) == 88) assign feedback = 14'h2409;
else if((index % 100) == 89) assign feedback = 14'h240C;
else if((index % 100) == 90) assign feedback = 14'h241D;
else if((index % 100) == 91) assign feedback = 14'h2421;
else if((index % 100) == 92) assign feedback = 14'h242D;
else if((index % 100) == 93) assign feedback = 14'h2430;
else if((index % 100) == 94) assign feedback = 14'h2433;
else if((index % 100) == 95) assign feedback = 14'h243F;
else if((index % 100) == 96) assign feedback = 14'h2441;
else if((index % 100) == 97) assign feedback = 14'h2471;
else if((index % 100) == 98) assign feedback = 14'h248E;
else if((index % 100) == 99) assign feedback = 14'h2496;
end
else if(width == 15)
begin
if((index % 100) == 0) assign feedback = 15'h4001;
else if((index % 100) == 1) assign feedback = 15'h4008;
else if((index % 100) == 2) assign feedback = 15'h400B;
else if((index % 100) == 3) assign feedback = 15'h4016;
else if((index % 100) == 4) assign feedback = 15'h401A;
else if((index % 100) == 5) assign feedback = 15'h402F;
else if((index % 100) == 6) assign feedback = 15'h403B;
else if((index % 100) == 7) assign feedback = 15'h4040;
else if((index % 100) == 8) assign feedback = 15'h4043;
else if((index % 100) == 9) assign feedback = 15'h4049;
else if((index % 100) == 10) assign feedback = 15'h4052;
else if((index % 100) == 11) assign feedback = 15'h4061;
else if((index % 100) == 12) assign feedback = 15'h4067;
else if((index % 100) == 13) assign feedback = 15'h406E;
else if((index % 100) == 14) assign feedback = 15'h4073;
else if((index % 100) == 15) assign feedback = 15'h407A;
else if((index % 100) == 16) assign feedback = 15'h4080;
else if((index % 100) == 17) assign feedback = 15'h408A;
else if((index % 100) == 18) assign feedback = 15'h4092;
else if((index % 100) == 19) assign feedback = 15'h40AB;
else if((index % 100) == 20) assign feedback = 15'h40AE;
else if((index % 100) == 21) assign feedback = 15'h40B0;
else if((index % 100) == 22) assign feedback = 15'h40B6;
else if((index % 100) == 23) assign feedback = 15'h40C2;
else if((index % 100) == 24) assign feedback = 15'h40D0;
else if((index % 100) == 25) assign feedback = 15'h40D3;
else if((index % 100) == 26) assign feedback = 15'h40DC;
else if((index % 100) == 27) assign feedback = 15'h40E5;
else if((index % 100) == 28) assign feedback = 15'h40E6;
else if((index % 100) == 29) assign feedback = 15'h40EF;
else if((index % 100) == 30) assign feedback = 15'h40FE;
else if((index % 100) == 31) assign feedback = 15'h4109;
else if((index % 100) == 32) assign feedback = 15'h411D;
else if((index % 100) == 33) assign feedback = 15'h4122;
else if((index % 100) == 34) assign feedback = 15'h413F;
else if((index % 100) == 35) assign feedback = 15'h4144;
else if((index % 100) == 36) assign feedback = 15'h4147;
else if((index % 100) == 37) assign feedback = 15'h414D;
else if((index % 100) == 38) assign feedback = 15'h4165;
else if((index % 100) == 39) assign feedback = 15'h416C;
else if((index % 100) == 40) assign feedback = 15'h418B;
else if((index % 100) == 41) assign feedback = 15'h418D;
else if((index % 100) == 42) assign feedback = 15'h4195;
else if((index % 100) == 43) assign feedback = 15'h4199;
else if((index % 100) == 44) assign feedback = 15'h41A3;
else if((index % 100) == 45) assign feedback = 15'h41A6;
else if((index % 100) == 46) assign feedback = 15'h41AF;
else if((index % 100) == 47) assign feedback = 15'h41B1;
else if((index % 100) == 48) assign feedback = 15'h41B4;
else if((index % 100) == 49) assign feedback = 15'h41B8;
else if((index % 100) == 50) assign feedback = 15'h41C5;
else if((index % 100) == 51) assign feedback = 15'h41CC;
else if((index % 100) == 52) assign feedback = 15'h41D7;
else if((index % 100) == 53) assign feedback = 15'h41DE;
else if((index % 100) == 54) assign feedback = 15'h41E2;
else if((index % 100) == 55) assign feedback = 15'h41E8;
else if((index % 100) == 56) assign feedback = 15'h420C;
else if((index % 100) == 57) assign feedback = 15'h4211;
else if((index % 100) == 58) assign feedback = 15'h4217;
else if((index % 100) == 59) assign feedback = 15'h4218;
else if((index % 100) == 60) assign feedback = 15'h421B;
else if((index % 100) == 61) assign feedback = 15'h4233;
else if((index % 100) == 62) assign feedback = 15'h4236;
else if((index % 100) == 63) assign feedback = 15'h423C;
else if((index % 100) == 64) assign feedback = 15'h4241;
else if((index % 100) == 65) assign feedback = 15'h424B;
else if((index % 100) == 66) assign feedback = 15'h4250;
else if((index % 100) == 67) assign feedback = 15'h425A;
else if((index % 100) == 68) assign feedback = 15'h426F;
else if((index % 100) == 69) assign feedback = 15'h427B;
else if((index % 100) == 70) assign feedback = 15'h427E;
else if((index % 100) == 71) assign feedback = 15'h428E;
else if((index % 100) == 72) assign feedback = 15'h4290;
else if((index % 100) == 73) assign feedback = 15'h4293;
else if((index % 100) == 74) assign feedback = 15'h4299;
else if((index % 100) == 75) assign feedback = 15'h42A3;
else if((index % 100) == 76) assign feedback = 15'h42A5;
else if((index % 100) == 77) assign feedback = 15'h42AF;
else if((index % 100) == 78) assign feedback = 15'h42B8;
else if((index % 100) == 79) assign feedback = 15'h42BD;
else if((index % 100) == 80) assign feedback = 15'h42C0;
else if((index % 100) == 81) assign feedback = 15'h42C6;
else if((index % 100) == 82) assign feedback = 15'h42D1;
else if((index % 100) == 83) assign feedback = 15'h42D8;
else if((index % 100) == 84) assign feedback = 15'h42E2;
else if((index % 100) == 85) assign feedback = 15'h42E4;
else if((index % 100) == 86) assign feedback = 15'h42ED;
else if((index % 100) == 87) assign feedback = 15'h42F6;
else if((index % 100) == 88) assign feedback = 15'h42F9;
else if((index % 100) == 89) assign feedback = 15'h4304;
else if((index % 100) == 90) assign feedback = 15'h4308;
else if((index % 100) == 91) assign feedback = 15'h430E;
else if((index % 100) == 92) assign feedback = 15'h4315;
else if((index % 100) == 93) assign feedback = 15'h432A;
else if((index % 100) == 94) assign feedback = 15'h432C;
else if((index % 100) == 95) assign feedback = 15'h4332;
else if((index % 100) == 96) assign feedback = 15'h433E;
else if((index % 100) == 97) assign feedback = 15'h4340;
else if((index % 100) == 98) assign feedback = 15'h4354;
else if((index % 100) == 99) assign feedback = 15'h4357;
end
else if(width == 16)
begin
if((index % 100) == 0) assign feedback = 16'h8016;
else if((index % 100) == 1) assign feedback = 16'h801C;
else if((index % 100) == 2) assign feedback = 16'h801F;
else if((index % 100) == 3) assign feedback = 16'h8029;
else if((index % 100) == 4) assign feedback = 16'h805E;
else if((index % 100) == 5) assign feedback = 16'h806B;
else if((index % 100) == 6) assign feedback = 16'h8097;
else if((index % 100) == 7) assign feedback = 16'h809E;
else if((index % 100) == 8) assign feedback = 16'h80A7;
else if((index % 100) == 9) assign feedback = 16'h80AE;
else if((index % 100) == 10) assign feedback = 16'h80CB;
else if((index % 100) == 11) assign feedback = 16'h80D0;
else if((index % 100) == 12) assign feedback = 16'h80D6;
else if((index % 100) == 13) assign feedback = 16'h80DF;
else if((index % 100) == 14) assign feedback = 16'h80E3;
else if((index % 100) == 15) assign feedback = 16'h810A;
else if((index % 100) == 16) assign feedback = 16'h810C;
else if((index % 100) == 17) assign feedback = 16'h8112;
else if((index % 100) == 18) assign feedback = 16'h8117;
else if((index % 100) == 19) assign feedback = 16'h812E;
else if((index % 100) == 20) assign feedback = 16'h8136;
else if((index % 100) == 21) assign feedback = 16'h8142;
else if((index % 100) == 22) assign feedback = 16'h8148;
else if((index % 100) == 23) assign feedback = 16'h8150;
else if((index % 100) == 24) assign feedback = 16'h8172;
else if((index % 100) == 25) assign feedback = 16'h818E;
else if((index % 100) == 26) assign feedback = 16'h81A5;
else if((index % 100) == 27) assign feedback = 16'h81B4;
else if((index % 100) == 28) assign feedback = 16'h81B8;
else if((index % 100) == 29) assign feedback = 16'h81C3;
else if((index % 100) == 30) assign feedback = 16'h81C6;
else if((index % 100) == 31) assign feedback = 16'h81CF;
else if((index % 100) == 32) assign feedback = 16'h81D1;
else if((index % 100) == 33) assign feedback = 16'h81EE;
else if((index % 100) == 34) assign feedback = 16'h81FC;
else if((index % 100) == 35) assign feedback = 16'h8214;
else if((index % 100) == 36) assign feedback = 16'h822B;
else if((index % 100) == 37) assign feedback = 16'h8233;
else if((index % 100) == 38) assign feedback = 16'h8241;
else if((index % 100) == 39) assign feedback = 16'h8244;
else if((index % 100) == 40) assign feedback = 16'h8248;
else if((index % 100) == 41) assign feedback = 16'h825F;
else if((index % 100) == 42) assign feedback = 16'h8260;
else if((index % 100) == 43) assign feedback = 16'h8299;
else if((index % 100) == 44) assign feedback = 16'h82A3;
else if((index % 100) == 45) assign feedback = 16'h82B4;
else if((index % 100) == 46) assign feedback = 16'h82C3;
else if((index % 100) == 47) assign feedback = 16'h82E1;
else if((index % 100) == 48) assign feedback = 16'h82EE;
else if((index % 100) == 49) assign feedback = 16'h82F5;
else if((index % 100) == 50) assign feedback = 16'h8320;
else if((index % 100) == 51) assign feedback = 16'h8325;
else if((index % 100) == 52) assign feedback = 16'h8329;
else if((index % 100) == 53) assign feedback = 16'h8345;
else if((index % 100) == 54) assign feedback = 16'h8361;
else if((index % 100) == 55) assign feedback = 16'h83B5;
else if((index % 100) == 56) assign feedback = 16'h83B6;
else if((index % 100) == 57) assign feedback = 16'h83BC;
else if((index % 100) == 58) assign feedback = 16'h83C1;
else if((index % 100) == 59) assign feedback = 16'h83F8;
else if((index % 100) == 60) assign feedback = 16'h8406;
else if((index % 100) == 61) assign feedback = 16'h8430;
else if((index % 100) == 62) assign feedback = 16'h845F;
else if((index % 100) == 63) assign feedback = 16'h846A;
else if((index % 100) == 64) assign feedback = 16'h846F;
else if((index % 100) == 65) assign feedback = 16'h8471;
else if((index % 100) == 66) assign feedback = 16'h8478;
else if((index % 100) == 67) assign feedback = 16'h847D;
else if((index % 100) == 68) assign feedback = 16'h849C;
else if((index % 100) == 69) assign feedback = 16'h84BE;
else if((index % 100) == 70) assign feedback = 16'h84C5;
else if((index % 100) == 71) assign feedback = 16'h84D2;
else if((index % 100) == 72) assign feedback = 16'h84D7;
else if((index % 100) == 73) assign feedback = 16'h84E1;
else if((index % 100) == 74) assign feedback = 16'h84E2;
else if((index % 100) == 75) assign feedback = 16'h84F3;
else if((index % 100) == 76) assign feedback = 16'h84F9;
else if((index % 100) == 77) assign feedback = 16'h853E;
else if((index % 100) == 78) assign feedback = 16'h8540;
else if((index % 100) == 79) assign feedback = 16'h855D;
else if((index % 100) == 80) assign feedback = 16'h8562;
else if((index % 100) == 81) assign feedback = 16'h8580;
else if((index % 100) == 82) assign feedback = 16'h8589;
else if((index % 100) == 83) assign feedback = 16'h858A;
else if((index % 100) == 84) assign feedback = 16'h85A8;
else if((index % 100) == 85) assign feedback = 16'h85AE;
else if((index % 100) == 86) assign feedback = 16'h85E6;
else if((index % 100) == 87) assign feedback = 16'h85E9;
else if((index % 100) == 88) assign feedback = 16'h85F2;
else if((index % 100) == 89) assign feedback = 16'h8607;
else if((index % 100) == 90) assign feedback = 16'h860E;
else if((index % 100) == 91) assign feedback = 16'h8610;
else if((index % 100) == 92) assign feedback = 16'h8634;
else if((index % 100) == 93) assign feedback = 16'h8638;
else if((index % 100) == 94) assign feedback = 16'h863D;
else if((index % 100) == 95) assign feedback = 16'h8646;
else if((index % 100) == 96) assign feedback = 16'h864A;
else if((index % 100) == 97) assign feedback = 16'h8651;
else if((index % 100) == 98) assign feedback = 16'h8657;
else if((index % 100) == 99) assign feedback = 16'h8679;
end
else if(width == 17)
begin
if((index % 100) == 0) assign feedback = 17'h10004;
else if((index % 100) == 1) assign feedback = 17'h10007;
else if((index % 100) == 2) assign feedback = 17'h10010;
else if((index % 100) == 3) assign feedback = 17'h10016;
else if((index % 100) == 4) assign feedback = 17'h10019;
else if((index % 100) == 5) assign feedback = 17'h1001F;
else if((index % 100) == 6) assign feedback = 17'h10020;
else if((index % 100) == 7) assign feedback = 17'h1002A;
else if((index % 100) == 8) assign feedback = 17'h10034;
else if((index % 100) == 9) assign feedback = 17'h1003D;
else if((index % 100) == 10) assign feedback = 17'h10046;
else if((index % 100) == 11) assign feedback = 17'h1004C;
else if((index % 100) == 12) assign feedback = 17'h10051;
else if((index % 100) == 13) assign feedback = 17'h10057;
else if((index % 100) == 14) assign feedback = 17'h1005D;
else if((index % 100) == 15) assign feedback = 17'h10062;
else if((index % 100) == 16) assign feedback = 17'h1007A;
else if((index % 100) == 17) assign feedback = 17'h10085;
else if((index % 100) == 18) assign feedback = 17'h10086;
else if((index % 100) == 19) assign feedback = 17'h1008C;
else if((index % 100) == 20) assign feedback = 17'h10092;
else if((index % 100) == 21) assign feedback = 17'h1009E;
else if((index % 100) == 22) assign feedback = 17'h100AB;
else if((index % 100) == 23) assign feedback = 17'h100B0;
else if((index % 100) == 24) assign feedback = 17'h100B3;
else if((index % 100) == 25) assign feedback = 17'h100B6;
else if((index % 100) == 26) assign feedback = 17'h100BF;
else if((index % 100) == 27) assign feedback = 17'h100C1;
else if((index % 100) == 28) assign feedback = 17'h100E0;
else if((index % 100) == 29) assign feedback = 17'h100E3;
else if((index % 100) == 30) assign feedback = 17'h100E5;
else if((index % 100) == 31) assign feedback = 17'h100EC;
else if((index % 100) == 32) assign feedback = 17'h100F8;
else if((index % 100) == 33) assign feedback = 17'h10106;
else if((index % 100) == 34) assign feedback = 17'h10111;
else if((index % 100) == 35) assign feedback = 17'h10114;
else if((index % 100) == 36) assign feedback = 17'h10118;
else if((index % 100) == 37) assign feedback = 17'h1011B;
else if((index % 100) == 38) assign feedback = 17'h10122;
else if((index % 100) == 39) assign feedback = 17'h10135;
else if((index % 100) == 40) assign feedback = 17'h1013C;
else if((index % 100) == 41) assign feedback = 17'h1013F;
else if((index % 100) == 42) assign feedback = 17'h10141;
else if((index % 100) == 43) assign feedback = 17'h10148;
else if((index % 100) == 44) assign feedback = 17'h1015A;
else if((index % 100) == 45) assign feedback = 17'h10163;
else if((index % 100) == 46) assign feedback = 17'h1016F;
else if((index % 100) == 47) assign feedback = 17'h10171;
else if((index % 100) == 48) assign feedback = 17'h10174;
else if((index % 100) == 49) assign feedback = 17'h1017E;
else if((index % 100) == 50) assign feedback = 17'h10184;
else if((index % 100) == 51) assign feedback = 17'h10188;
else if((index % 100) == 52) assign feedback = 17'h1018B;
else if((index % 100) == 53) assign feedback = 17'h1018D;
else if((index % 100) == 54) assign feedback = 17'h10193;
else if((index % 100) == 55) assign feedback = 17'h10199;
else if((index % 100) == 56) assign feedback = 17'h1019A;
else if((index % 100) == 57) assign feedback = 17'h101A9;
else if((index % 100) == 58) assign feedback = 17'h101BB;
else if((index % 100) == 59) assign feedback = 17'h101D8;
else if((index % 100) == 60) assign feedback = 17'h101DB;
else if((index % 100) == 61) assign feedback = 17'h101E1;
else if((index % 100) == 62) assign feedback = 17'h101E8;
else if((index % 100) == 63) assign feedback = 17'h101ED;
else if((index % 100) == 64) assign feedback = 17'h101F5;
else if((index % 100) == 65) assign feedback = 17'h10203;
else if((index % 100) == 66) assign feedback = 17'h1020A;
else if((index % 100) == 67) assign feedback = 17'h1020C;
else if((index % 100) == 68) assign feedback = 17'h1020F;
else if((index % 100) == 69) assign feedback = 17'h10217;
else if((index % 100) == 70) assign feedback = 17'h1021E;
else if((index % 100) == 71) assign feedback = 17'h10221;
else if((index % 100) == 72) assign feedback = 17'h1022B;
else if((index % 100) == 73) assign feedback = 17'h1022E;
else if((index % 100) == 74) assign feedback = 17'h10230;
else if((index % 100) == 75) assign feedback = 17'h10233;
else if((index % 100) == 76) assign feedback = 17'h1023A;
else if((index % 100) == 77) assign feedback = 17'h10242;
else if((index % 100) == 78) assign feedback = 17'h10247;
else if((index % 100) == 79) assign feedback = 17'h1024E;
else if((index % 100) == 80) assign feedback = 17'h10255;
else if((index % 100) == 81) assign feedback = 17'h1025C;
else if((index % 100) == 82) assign feedback = 17'h10260;
else if((index % 100) == 83) assign feedback = 17'h10266;
else if((index % 100) == 84) assign feedback = 17'h1027B;
else if((index % 100) == 85) assign feedback = 17'h1027D;
else if((index % 100) == 86) assign feedback = 17'h1028D;
else if((index % 100) == 87) assign feedback = 17'h1028E;
else if((index % 100) == 88) assign feedback = 17'h10293;
else if((index % 100) == 89) assign feedback = 17'h1029A;
else if((index % 100) == 90) assign feedback = 17'h1029F;
else if((index % 100) == 91) assign feedback = 17'h102B1;
else if((index % 100) == 92) assign feedback = 17'h102B2;
else if((index % 100) == 93) assign feedback = 17'h102B7;
else if((index % 100) == 94) assign feedback = 17'h102C9;
else if((index % 100) == 95) assign feedback = 17'h102D2;
else if((index % 100) == 96) assign feedback = 17'h102DD;
else if((index % 100) == 97) assign feedback = 17'h102F6;
else if((index % 100) == 98) assign feedback = 17'h10302;
else if((index % 100) == 99) assign feedback = 17'h1030E;
end
else if(width == 18)
begin
if((index % 100) == 0) assign feedback = 18'h20013;
else if((index % 100) == 1) assign feedback = 18'h2001F;
else if((index % 100) == 2) assign feedback = 18'h20026;
else if((index % 100) == 3) assign feedback = 18'h2003D;
else if((index % 100) == 4) assign feedback = 18'h20040;
else if((index % 100) == 5) assign feedback = 18'h2006D;
else if((index % 100) == 6) assign feedback = 18'h20073;
else if((index % 100) == 7) assign feedback = 18'h20076;
else if((index % 100) == 8) assign feedback = 18'h20083;
else if((index % 100) == 9) assign feedback = 18'h200A7;
else if((index % 100) == 10) assign feedback = 18'h200C8;
else if((index % 100) == 11) assign feedback = 18'h200F1;
else if((index % 100) == 12) assign feedback = 18'h200F4;
else if((index % 100) == 13) assign feedback = 18'h200F7;
else if((index % 100) == 14) assign feedback = 18'h20105;
else if((index % 100) == 15) assign feedback = 18'h20109;
else if((index % 100) == 16) assign feedback = 18'h20130;
else if((index % 100) == 17) assign feedback = 18'h2013A;
else if((index % 100) == 18) assign feedback = 18'h20155;
else if((index % 100) == 19) assign feedback = 18'h20178;
else if((index % 100) == 20) assign feedback = 18'h2018B;
else if((index % 100) == 21) assign feedback = 18'h20195;
else if((index % 100) == 22) assign feedback = 18'h20196;
else if((index % 100) == 23) assign feedback = 18'h201BB;
else if((index % 100) == 24) assign feedback = 18'h201C3;
else if((index % 100) == 25) assign feedback = 18'h201CA;
else if((index % 100) == 26) assign feedback = 18'h201CC;
else if((index % 100) == 27) assign feedback = 18'h201D4;
else if((index % 100) == 28) assign feedback = 18'h201D8;
else if((index % 100) == 29) assign feedback = 18'h201E2;
else if((index % 100) == 30) assign feedback = 18'h201EB;
else if((index % 100) == 31) assign feedback = 18'h201F0;
else if((index % 100) == 32) assign feedback = 18'h2020C;
else if((index % 100) == 33) assign feedback = 18'h20218;
else if((index % 100) == 34) assign feedback = 18'h2021E;
else if((index % 100) == 35) assign feedback = 18'h2022D;
else if((index % 100) == 36) assign feedback = 18'h2023C;
else if((index % 100) == 37) assign feedback = 18'h20244;
else if((index % 100) == 38) assign feedback = 18'h20250;
else if((index % 100) == 39) assign feedback = 18'h20290;
else if((index % 100) == 40) assign feedback = 18'h202C9;
else if((index % 100) == 41) assign feedback = 18'h202CF;
else if((index % 100) == 42) assign feedback = 18'h202E2;
else if((index % 100) == 43) assign feedback = 18'h202ED;
else if((index % 100) == 44) assign feedback = 18'h202F0;
else if((index % 100) == 45) assign feedback = 18'h202FF;
else if((index % 100) == 46) assign feedback = 18'h20304;
else if((index % 100) == 47) assign feedback = 18'h2030E;
else if((index % 100) == 48) assign feedback = 18'h20315;
else if((index % 100) == 49) assign feedback = 18'h2033E;
else if((index % 100) == 50) assign feedback = 18'h20346;
else if((index % 100) == 51) assign feedback = 18'h20394;
else if((index % 100) == 52) assign feedback = 18'h20398;
else if((index % 100) == 53) assign feedback = 18'h203A8;
else if((index % 100) == 54) assign feedback = 18'h203DF;
else if((index % 100) == 55) assign feedback = 18'h203E6;
else if((index % 100) == 56) assign feedback = 18'h203F8;
else if((index % 100) == 57) assign feedback = 18'h20400;
else if((index % 100) == 58) assign feedback = 18'h2041D;
else if((index % 100) == 59) assign feedback = 18'h20439;
else if((index % 100) == 60) assign feedback = 18'h20442;
else if((index % 100) == 61) assign feedback = 18'h20465;
else if((index % 100) == 62) assign feedback = 18'h2046F;
else if((index % 100) == 63) assign feedback = 18'h20477;
else if((index % 100) == 64) assign feedback = 18'h2047E;
else if((index % 100) == 65) assign feedback = 18'h20482;
else if((index % 100) == 66) assign feedback = 18'h20493;
else if((index % 100) == 67) assign feedback = 18'h20496;
else if((index % 100) == 68) assign feedback = 18'h204B2;
else if((index % 100) == 69) assign feedback = 18'h204BD;
else if((index % 100) == 70) assign feedback = 18'h204C9;
else if((index % 100) == 71) assign feedback = 18'h204D1;
else if((index % 100) == 72) assign feedback = 18'h204D2;
else if((index % 100) == 73) assign feedback = 18'h204E4;
else if((index % 100) == 74) assign feedback = 18'h204E7;
else if((index % 100) == 75) assign feedback = 18'h2050E;
else if((index % 100) == 76) assign feedback = 18'h20545;
else if((index % 100) == 77) assign feedback = 18'h2054A;
else if((index % 100) == 78) assign feedback = 18'h20562;
else if((index % 100) == 79) assign feedback = 18'h20567;
else if((index % 100) == 80) assign feedback = 18'h2056B;
else if((index % 100) == 81) assign feedback = 18'h20570;
else if((index % 100) == 82) assign feedback = 18'h2057A;
else if((index % 100) == 83) assign feedback = 18'h2058C;
else if((index % 100) == 84) assign feedback = 18'h20594;
else if((index % 100) == 85) assign feedback = 18'h2059D;
else if((index % 100) == 86) assign feedback = 18'h205A8;
else if((index % 100) == 87) assign feedback = 18'h205B3;
else if((index % 100) == 88) assign feedback = 18'h205C1;
else if((index % 100) == 89) assign feedback = 18'h205E3;
else if((index % 100) == 90) assign feedback = 18'h205EC;
else if((index % 100) == 91) assign feedback = 18'h205F8;
else if((index % 100) == 92) assign feedback = 18'h20625;
else if((index % 100) == 93) assign feedback = 18'h20638;
else if((index % 100) == 94) assign feedback = 18'h2063D;
else if((index % 100) == 95) assign feedback = 18'h20676;
else if((index % 100) == 96) assign feedback = 18'h2067F;
else if((index % 100) == 97) assign feedback = 18'h206C2;
else if((index % 100) == 98) assign feedback = 18'h206CB;
else if((index % 100) == 99) assign feedback = 18'h206CD;
end
else if(width == 19)
begin
if((index % 100) == 0) assign feedback = 19'h40013;
else if((index % 100) == 1) assign feedback = 19'h4001F;
else if((index % 100) == 2) assign feedback = 19'h40023;
else if((index % 100) == 3) assign feedback = 19'h40029;
else if((index % 100) == 4) assign feedback = 19'h4002C;
else if((index % 100) == 5) assign feedback = 19'h40031;
else if((index % 100) == 6) assign feedback = 19'h40037;
else if((index % 100) == 7) assign feedback = 19'h4003E;
else if((index % 100) == 8) assign feedback = 19'h40049;
else if((index % 100) == 9) assign feedback = 19'h40057;
else if((index % 100) == 10) assign feedback = 19'h40070;
else if((index % 100) == 11) assign feedback = 19'h400A1;
else if((index % 100) == 12) assign feedback = 19'h400B0;
else if((index % 100) == 13) assign feedback = 19'h400B5;
else if((index % 100) == 14) assign feedback = 19'h400BA;
else if((index % 100) == 15) assign feedback = 19'h400C2;
else if((index % 100) == 16) assign feedback = 19'h400CE;
else if((index % 100) == 17) assign feedback = 19'h400D0;
else if((index % 100) == 18) assign feedback = 19'h400D6;
else if((index % 100) == 19) assign feedback = 19'h400D9;
else if((index % 100) == 20) assign feedback = 19'h400DF;
else if((index % 100) == 21) assign feedback = 19'h400E3;
else if((index % 100) == 22) assign feedback = 19'h400E6;
else if((index % 100) == 23) assign feedback = 19'h400EF;
else if((index % 100) == 24) assign feedback = 19'h40105;
else if((index % 100) == 25) assign feedback = 19'h40109;
else if((index % 100) == 26) assign feedback = 19'h4010C;
else if((index % 100) == 27) assign feedback = 19'h40112;
else if((index % 100) == 28) assign feedback = 19'h40118;
else if((index % 100) == 29) assign feedback = 19'h40127;
else if((index % 100) == 30) assign feedback = 19'h40128;
else if((index % 100) == 31) assign feedback = 19'h40135;
else if((index % 100) == 32) assign feedback = 19'h40136;
else if((index % 100) == 33) assign feedback = 19'h40141;
else if((index % 100) == 34) assign feedback = 19'h40142;
else if((index % 100) == 35) assign feedback = 19'h4014B;
else if((index % 100) == 36) assign feedback = 19'h40150;
else if((index % 100) == 37) assign feedback = 19'h40190;
else if((index % 100) == 38) assign feedback = 19'h401A3;
else if((index % 100) == 39) assign feedback = 19'h401B4;
else if((index % 100) == 40) assign feedback = 19'h401B7;
else if((index % 100) == 41) assign feedback = 19'h401CF;
else if((index % 100) == 42) assign feedback = 19'h401D2;
else if((index % 100) == 43) assign feedback = 19'h401D4;
else if((index % 100) == 44) assign feedback = 19'h401E4;
else if((index % 100) == 45) assign feedback = 19'h401EB;
else if((index % 100) == 46) assign feedback = 19'h401ED;
else if((index % 100) == 47) assign feedback = 19'h401EE;
else if((index % 100) == 48) assign feedback = 19'h401F9;
else if((index % 100) == 49) assign feedback = 19'h4021B;
else if((index % 100) == 50) assign feedback = 19'h40228;
else if((index % 100) == 51) assign feedback = 19'h4023A;
else if((index % 100) == 52) assign feedback = 19'h4023F;
else if((index % 100) == 53) assign feedback = 19'h40244;
else if((index % 100) == 54) assign feedback = 19'h40248;
else if((index % 100) == 55) assign feedback = 19'h4025A;
else if((index % 100) == 56) assign feedback = 19'h4025C;
else if((index % 100) == 57) assign feedback = 19'h40269;
else if((index % 100) == 58) assign feedback = 19'h4026C;
else if((index % 100) == 59) assign feedback = 19'h4028E;
else if((index % 100) == 60) assign feedback = 19'h40295;
else if((index % 100) == 61) assign feedback = 19'h4029C;
else if((index % 100) == 62) assign feedback = 19'h402A0;
else if((index % 100) == 63) assign feedback = 19'h402A9;
else if((index % 100) == 64) assign feedback = 19'h402AF;
else if((index % 100) == 65) assign feedback = 19'h402B8;
else if((index % 100) == 66) assign feedback = 19'h402BB;
else if((index % 100) == 67) assign feedback = 19'h402D4;
else if((index % 100) == 68) assign feedback = 19'h402DD;
else if((index % 100) == 69) assign feedback = 19'h402E8;
else if((index % 100) == 70) assign feedback = 19'h402EB;
else if((index % 100) == 71) assign feedback = 19'h402EE;
else if((index % 100) == 72) assign feedback = 19'h402F5;
else if((index % 100) == 73) assign feedback = 19'h402FA;
else if((index % 100) == 74) assign feedback = 19'h402FC;
else if((index % 100) == 75) assign feedback = 19'h40304;
else if((index % 100) == 76) assign feedback = 19'h40308;
else if((index % 100) == 77) assign feedback = 19'h40319;
else if((index % 100) == 78) assign feedback = 19'h40320;
else if((index % 100) == 79) assign feedback = 19'h40325;
else if((index % 100) == 80) assign feedback = 19'h40326;
else if((index % 100) == 81) assign feedback = 19'h4032F;
else if((index % 100) == 82) assign feedback = 19'h40332;
else if((index % 100) == 83) assign feedback = 19'h40343;
else if((index % 100) == 84) assign feedback = 19'h40345;
else if((index % 100) == 85) assign feedback = 19'h4035E;
else if((index % 100) == 86) assign feedback = 19'h40361;
else if((index % 100) == 87) assign feedback = 19'h40368;
else if((index % 100) == 88) assign feedback = 19'h40373;
else if((index % 100) == 89) assign feedback = 19'h40376;
else if((index % 100) == 90) assign feedback = 19'h4038A;
else if((index % 100) == 91) assign feedback = 19'h4039D;
else if((index % 100) == 92) assign feedback = 19'h403A2;
else if((index % 100) == 93) assign feedback = 19'h403A4;
else if((index % 100) == 94) assign feedback = 19'h403AB;
else if((index % 100) == 95) assign feedback = 19'h403C2;
else if((index % 100) == 96) assign feedback = 19'h403C8;
else if((index % 100) == 97) assign feedback = 19'h403CE;
else if((index % 100) == 98) assign feedback = 19'h403F7;
else if((index % 100) == 99) assign feedback = 19'h403FE;
end
else if(width == 20)
begin
if((index % 100) == 0) assign feedback = 20'h80004;
else if((index % 100) == 1) assign feedback = 20'h80029;
else if((index % 100) == 2) assign feedback = 20'h80032;
else if((index % 100) == 3) assign feedback = 20'h80034;
else if((index % 100) == 4) assign feedback = 20'h8003D;
else if((index % 100) == 5) assign feedback = 20'h80079;
else if((index % 100) == 6) assign feedback = 20'h800B3;
else if((index % 100) == 7) assign feedback = 20'h800B6;
else if((index % 100) == 8) assign feedback = 20'h800BF;
else if((index % 100) == 9) assign feedback = 20'h800C7;
else if((index % 100) == 10) assign feedback = 20'h800DF;
else if((index % 100) == 11) assign feedback = 20'h80111;
else if((index % 100) == 12) assign feedback = 20'h80114;
else if((index % 100) == 13) assign feedback = 20'h80118;
else if((index % 100) == 14) assign feedback = 20'h8015C;
else if((index % 100) == 15) assign feedback = 20'h80199;
else if((index % 100) == 16) assign feedback = 20'h801A9;
else if((index % 100) == 17) assign feedback = 20'h801AC;
else if((index % 100) == 18) assign feedback = 20'h801B7;
else if((index % 100) == 19) assign feedback = 20'h801E1;
else if((index % 100) == 20) assign feedback = 20'h801FA;
else if((index % 100) == 21) assign feedback = 20'h801FF;
else if((index % 100) == 22) assign feedback = 20'h80211;
else if((index % 100) == 23) assign feedback = 20'h80242;
else if((index % 100) == 24) assign feedback = 20'h8024B;
else if((index % 100) == 25) assign feedback = 20'h80260;
else if((index % 100) == 26) assign feedback = 20'h80263;
else if((index % 100) == 27) assign feedback = 20'h80266;
else if((index % 100) == 28) assign feedback = 20'h80274;
else if((index % 100) == 29) assign feedback = 20'h80284;
else if((index % 100) == 30) assign feedback = 20'h80295;
else if((index % 100) == 31) assign feedback = 20'h802CF;
else if((index % 100) == 32) assign feedback = 20'h802F6;
else if((index % 100) == 33) assign feedback = 20'h802F9;
else if((index % 100) == 34) assign feedback = 20'h80302;
else if((index % 100) == 35) assign feedback = 20'h80315;
else if((index % 100) == 36) assign feedback = 20'h8031C;
else if((index % 100) == 37) assign feedback = 20'h8032A;
else if((index % 100) == 38) assign feedback = 20'h80338;
else if((index % 100) == 39) assign feedback = 20'h8033D;
else if((index % 100) == 40) assign feedback = 20'h8035B;
else if((index % 100) == 41) assign feedback = 20'h8036E;
else if((index % 100) == 42) assign feedback = 20'h80379;
else if((index % 100) == 43) assign feedback = 20'h8038A;
else if((index % 100) == 44) assign feedback = 20'h8039B;
else if((index % 100) == 45) assign feedback = 20'h803A4;
else if((index % 100) == 46) assign feedback = 20'h803BC;
else if((index % 100) == 47) assign feedback = 20'h803EF;
else if((index % 100) == 48) assign feedback = 20'h803FB;
else if((index % 100) == 49) assign feedback = 20'h8040C;
else if((index % 100) == 50) assign feedback = 20'h80414;
else if((index % 100) == 51) assign feedback = 20'h8041B;
else if((index % 100) == 52) assign feedback = 20'h80421;
else if((index % 100) == 53) assign feedback = 20'h80448;
else if((index % 100) == 54) assign feedback = 20'h8044D;
else if((index % 100) == 55) assign feedback = 20'h80456;
else if((index % 100) == 56) assign feedback = 20'h8045F;
else if((index % 100) == 57) assign feedback = 20'h8048D;
else if((index % 100) == 58) assign feedback = 20'h80499;
else if((index % 100) == 59) assign feedback = 20'h8049C;
else if((index % 100) == 60) assign feedback = 20'h804A6;
else if((index % 100) == 61) assign feedback = 20'h804BD;
else if((index % 100) == 62) assign feedback = 20'h804C6;
else if((index % 100) == 63) assign feedback = 20'h804CC;
else if((index % 100) == 64) assign feedback = 20'h804D7;
else if((index % 100) == 65) assign feedback = 20'h804E7;
else if((index % 100) == 66) assign feedback = 20'h804EE;
else if((index % 100) == 67) assign feedback = 20'h804F0;
else if((index % 100) == 68) assign feedback = 20'h80504;
else if((index % 100) == 69) assign feedback = 20'h80513;
else if((index % 100) == 70) assign feedback = 20'h8051A;
else if((index % 100) == 71) assign feedback = 20'h80526;
else if((index % 100) == 72) assign feedback = 20'h80529;
else if((index % 100) == 73) assign feedback = 20'h80534;
else if((index % 100) == 74) assign feedback = 20'h80543;
else if((index % 100) == 75) assign feedback = 20'h8054A;
else if((index % 100) == 76) assign feedback = 20'h80558;
else if((index % 100) == 77) assign feedback = 20'h80568;
else if((index % 100) == 78) assign feedback = 20'h8057A;
else if((index % 100) == 79) assign feedback = 20'h805BC;
else if((index % 100) == 80) assign feedback = 20'h805C1;
else if((index % 100) == 81) assign feedback = 20'h805EA;
else if((index % 100) == 82) assign feedback = 20'h805EC;
else if((index % 100) == 83) assign feedback = 20'h80608;
else if((index % 100) == 84) assign feedback = 20'h80637;
else if((index % 100) == 85) assign feedback = 20'h8065B;
else if((index % 100) == 86) assign feedback = 20'h8069D;
else if((index % 100) == 87) assign feedback = 20'h8069E;
else if((index % 100) == 88) assign feedback = 20'h806D0;
else if((index % 100) == 89) assign feedback = 20'h80705;
else if((index % 100) == 90) assign feedback = 20'h80718;
else if((index % 100) == 91) assign feedback = 20'h80733;
else if((index % 100) == 92) assign feedback = 20'h80735;
else if((index % 100) == 93) assign feedback = 20'h80741;
else if((index % 100) == 94) assign feedback = 20'h80753;
else if((index % 100) == 95) assign feedback = 20'h80769;
else if((index % 100) == 96) assign feedback = 20'h8076F;
else if((index % 100) == 97) assign feedback = 20'h80799;
else if((index % 100) == 98) assign feedback = 20'h807A5;
else if((index % 100) == 99) assign feedback = 20'h807B8;
end
else if(width == 21)
begin
if((index % 100) == 0) assign feedback = 21'h100002;
else if((index % 100) == 1) assign feedback = 21'h100013;
else if((index % 100) == 2) assign feedback = 21'h10001F;
else if((index % 100) == 3) assign feedback = 21'h100032;
else if((index % 100) == 4) assign feedback = 21'h100037;
else if((index % 100) == 5) assign feedback = 21'h10003D;
else if((index % 100) == 6) assign feedback = 21'h10003E;
else if((index % 100) == 7) assign feedback = 21'h100049;
else if((index % 100) == 8) assign feedback = 21'h10005B;
else if((index % 100) == 9) assign feedback = 21'h100083;
else if((index % 100) == 10) assign feedback = 21'h10008F;
else if((index % 100) == 11) assign feedback = 21'h10009D;
else if((index % 100) == 12) assign feedback = 21'h1000A4;
else if((index % 100) == 13) assign feedback = 21'h1000A7;
else if((index % 100) == 14) assign feedback = 21'h1000B6;
else if((index % 100) == 15) assign feedback = 21'h1000B9;
else if((index % 100) == 16) assign feedback = 21'h1000C2;
else if((index % 100) == 17) assign feedback = 21'h1000CB;
else if((index % 100) == 18) assign feedback = 21'h1000CE;
else if((index % 100) == 19) assign feedback = 21'h1000D3;
else if((index % 100) == 20) assign feedback = 21'h1000D5;
else if((index % 100) == 21) assign feedback = 21'h1000DA;
else if((index % 100) == 22) assign feedback = 21'h1000DC;
else if((index % 100) == 23) assign feedback = 21'h1000F1;
else if((index % 100) == 24) assign feedback = 21'h1000F7;
else if((index % 100) == 25) assign feedback = 21'h10010C;
else if((index % 100) == 26) assign feedback = 21'h100112;
else if((index % 100) == 27) assign feedback = 21'h10011B;
else if((index % 100) == 28) assign feedback = 21'h10011E;
else if((index % 100) == 29) assign feedback = 21'h10012D;
else if((index % 100) == 30) assign feedback = 21'h100139;
else if((index % 100) == 31) assign feedback = 21'h100156;
else if((index % 100) == 32) assign feedback = 21'h100169;
else if((index % 100) == 33) assign feedback = 21'h100184;
else if((index % 100) == 34) assign feedback = 21'h10018D;
else if((index % 100) == 35) assign feedback = 21'h1001A9;
else if((index % 100) == 36) assign feedback = 21'h1001B1;
else if((index % 100) == 37) assign feedback = 21'h1001BB;
else if((index % 100) == 38) assign feedback = 21'h1001CF;
else if((index % 100) == 39) assign feedback = 21'h1001D1;
else if((index % 100) == 40) assign feedback = 21'h1001D7;
else if((index % 100) == 41) assign feedback = 21'h1001DD;
else if((index % 100) == 42) assign feedback = 21'h1001E2;
else if((index % 100) == 43) assign feedback = 21'h1001EE;
else if((index % 100) == 44) assign feedback = 21'h10020A;
else if((index % 100) == 45) assign feedback = 21'h10020C;
else if((index % 100) == 46) assign feedback = 21'h100211;
else if((index % 100) == 47) assign feedback = 21'h100224;
else if((index % 100) == 48) assign feedback = 21'h10022E;
else if((index % 100) == 49) assign feedback = 21'h10023A;
else if((index % 100) == 50) assign feedback = 21'h100248;
else if((index % 100) == 51) assign feedback = 21'h10024B;
else if((index % 100) == 52) assign feedback = 21'h100253;
else if((index % 100) == 53) assign feedback = 21'h100272;
else if((index % 100) == 54) assign feedback = 21'h100274;
else if((index % 100) == 55) assign feedback = 21'h100277;
else if((index % 100) == 56) assign feedback = 21'h10027E;
else if((index % 100) == 57) assign feedback = 21'h100287;
else if((index % 100) == 58) assign feedback = 21'h100295;
else if((index % 100) == 59) assign feedback = 21'h1002AA;
else if((index % 100) == 60) assign feedback = 21'h1002DB;
else if((index % 100) == 61) assign feedback = 21'h1002EB;
else if((index % 100) == 62) assign feedback = 21'h1002F0;
else if((index % 100) == 63) assign feedback = 21'h1002F5;
else if((index % 100) == 64) assign feedback = 21'h1002F6;
else if((index % 100) == 65) assign feedback = 21'h100308;
else if((index % 100) == 66) assign feedback = 21'h10031F;
else if((index % 100) == 67) assign feedback = 21'h100329;
else if((index % 100) == 68) assign feedback = 21'h100345;
else if((index % 100) == 69) assign feedback = 21'h10035D;
else if((index % 100) == 70) assign feedback = 21'h100361;
else if((index % 100) == 71) assign feedback = 21'h10036B;
else if((index % 100) == 72) assign feedback = 21'h100370;
else if((index % 100) == 73) assign feedback = 21'h10037F;
else if((index % 100) == 74) assign feedback = 21'h1003A1;
else if((index % 100) == 75) assign feedback = 21'h1003AE;
else if((index % 100) == 76) assign feedback = 21'h1003B5;
else if((index % 100) == 77) assign feedback = 21'h1003BA;
else if((index % 100) == 78) assign feedback = 21'h1003CB;
else if((index % 100) == 79) assign feedback = 21'h1003D5;
else if((index % 100) == 80) assign feedback = 21'h1003D9;
else if((index % 100) == 81) assign feedback = 21'h1003E0;
else if((index % 100) == 82) assign feedback = 21'h1003E6;
else if((index % 100) == 83) assign feedback = 21'h1003E9;
else if((index % 100) == 84) assign feedback = 21'h100406;
else if((index % 100) == 85) assign feedback = 21'h100409;
else if((index % 100) == 86) assign feedback = 21'h10040A;
else if((index % 100) == 87) assign feedback = 21'h100427;
else if((index % 100) == 88) assign feedback = 21'h100430;
else if((index % 100) == 89) assign feedback = 21'h100441;
else if((index % 100) == 90) assign feedback = 21'h100448;
else if((index % 100) == 91) assign feedback = 21'h10044B;
else if((index % 100) == 92) assign feedback = 21'h100455;
else if((index % 100) == 93) assign feedback = 21'h10045C;
else if((index % 100) == 94) assign feedback = 21'h10046F;
else if((index % 100) == 95) assign feedback = 21'h100478;
else if((index % 100) == 96) assign feedback = 21'h10047D;
else if((index % 100) == 97) assign feedback = 21'h10049A;
else if((index % 100) == 98) assign feedback = 21'h1004AC;
else if((index % 100) == 99) assign feedback = 21'h1004B2;
end
else if(width == 22)
begin
if((index % 100) == 0) assign feedback = 22'h200001;
else if((index % 100) == 1) assign feedback = 22'h20001C;
else if((index % 100) == 2) assign feedback = 22'h20005E;
else if((index % 100) == 3) assign feedback = 22'h200061;
else if((index % 100) == 4) assign feedback = 22'h200094;
else if((index % 100) == 5) assign feedback = 22'h2000B0;
else if((index % 100) == 6) assign feedback = 22'h2000B9;
else if((index % 100) == 7) assign feedback = 22'h2000C7;
else if((index % 100) == 8) assign feedback = 22'h2000D9;
else if((index % 100) == 9) assign feedback = 22'h2000F8;
else if((index % 100) == 10) assign feedback = 22'h200111;
else if((index % 100) == 11) assign feedback = 22'h200133;
else if((index % 100) == 12) assign feedback = 22'h200156;
else if((index % 100) == 13) assign feedback = 22'h20015A;
else if((index % 100) == 14) assign feedback = 22'h200182;
else if((index % 100) == 15) assign feedback = 22'h200188;
else if((index % 100) == 16) assign feedback = 22'h2001A5;
else if((index % 100) == 17) assign feedback = 22'h2001B4;
else if((index % 100) == 18) assign feedback = 22'h2001C0;
else if((index % 100) == 19) assign feedback = 22'h2001DB;
else if((index % 100) == 20) assign feedback = 22'h2001E7;
else if((index % 100) == 21) assign feedback = 22'h2001EB;
else if((index % 100) == 22) assign feedback = 22'h2001ED;
else if((index % 100) == 23) assign feedback = 22'h200209;
else if((index % 100) == 24) assign feedback = 22'h200239;
else if((index % 100) == 25) assign feedback = 22'h200244;
else if((index % 100) == 26) assign feedback = 22'h200272;
else if((index % 100) == 27) assign feedback = 22'h200287;
else if((index % 100) == 28) assign feedback = 22'h20028D;
else if((index % 100) == 29) assign feedback = 22'h20029F;
else if((index % 100) == 30) assign feedback = 22'h2002A3;
else if((index % 100) == 31) assign feedback = 22'h2002BD;
else if((index % 100) == 32) assign feedback = 22'h2002C3;
else if((index % 100) == 33) assign feedback = 22'h2002C6;
else if((index % 100) == 34) assign feedback = 22'h2002CC;
else if((index % 100) == 35) assign feedback = 22'h2002DD;
else if((index % 100) == 36) assign feedback = 22'h20030B;
else if((index % 100) == 37) assign feedback = 22'h20030D;
else if((index % 100) == 38) assign feedback = 22'h200332;
else if((index % 100) == 39) assign feedback = 22'h200345;
else if((index % 100) == 40) assign feedback = 22'h200358;
else if((index % 100) == 41) assign feedback = 22'h200361;
else if((index % 100) == 42) assign feedback = 22'h20036D;
else if((index % 100) == 43) assign feedback = 22'h200398;
else if((index % 100) == 44) assign feedback = 22'h2003B5;
else if((index % 100) == 45) assign feedback = 22'h2003BF;
else if((index % 100) == 46) assign feedback = 22'h2003C2;
else if((index % 100) == 47) assign feedback = 22'h2003E3;
else if((index % 100) == 48) assign feedback = 22'h2003EC;
else if((index % 100) == 49) assign feedback = 22'h2003FD;
else if((index % 100) == 50) assign feedback = 22'h200403;
else if((index % 100) == 51) assign feedback = 22'h200414;
else if((index % 100) == 52) assign feedback = 22'h200427;
else if((index % 100) == 53) assign feedback = 22'h200433;
else if((index % 100) == 54) assign feedback = 22'h20044B;
else if((index % 100) == 55) assign feedback = 22'h200459;
else if((index % 100) == 56) assign feedback = 22'h200460;
else if((index % 100) == 57) assign feedback = 22'h200463;
else if((index % 100) == 58) assign feedback = 22'h200481;
else if((index % 100) == 59) assign feedback = 22'h20049F;
else if((index % 100) == 60) assign feedback = 22'h2004BE;
else if((index % 100) == 61) assign feedback = 22'h2004C6;
else if((index % 100) == 62) assign feedback = 22'h2004D7;
else if((index % 100) == 63) assign feedback = 22'h2004DD;
else if((index % 100) == 64) assign feedback = 22'h2004E1;
else if((index % 100) == 65) assign feedback = 22'h2004E2;
else if((index % 100) == 66) assign feedback = 22'h2004ED;
else if((index % 100) == 67) assign feedback = 22'h2004FA;
else if((index % 100) == 68) assign feedback = 22'h200515;
else if((index % 100) == 69) assign feedback = 22'h20051C;
else if((index % 100) == 70) assign feedback = 22'h20053E;
else if((index % 100) == 71) assign feedback = 22'h20054A;
else if((index % 100) == 72) assign feedback = 22'h20054F;
else if((index % 100) == 73) assign feedback = 22'h20056E;
else if((index % 100) == 74) assign feedback = 22'h200575;
else if((index % 100) == 75) assign feedback = 22'h200576;
else if((index % 100) == 76) assign feedback = 22'h20057C;
else if((index % 100) == 77) assign feedback = 22'h200589;
else if((index % 100) == 78) assign feedback = 22'h2005A4;
else if((index % 100) == 79) assign feedback = 22'h2005AD;
else if((index % 100) == 80) assign feedback = 22'h2005B3;
else if((index % 100) == 81) assign feedback = 22'h2005B6;
else if((index % 100) == 82) assign feedback = 22'h2005BA;
else if((index % 100) == 83) assign feedback = 22'h2005BF;
else if((index % 100) == 84) assign feedback = 22'h2005EC;
else if((index % 100) == 85) assign feedback = 22'h2005EF;
else if((index % 100) == 86) assign feedback = 22'h200616;
else if((index % 100) == 87) assign feedback = 22'h200623;
else if((index % 100) == 88) assign feedback = 22'h200634;
else if((index % 100) == 89) assign feedback = 22'h20064A;
else if((index % 100) == 90) assign feedback = 22'h20064C;
else if((index % 100) == 91) assign feedback = 22'h20064F;
else if((index % 100) == 92) assign feedback = 22'h200651;
else if((index % 100) == 93) assign feedback = 22'h200667;
else if((index % 100) == 94) assign feedback = 22'h20066B;
else if((index % 100) == 95) assign feedback = 22'h200685;
else if((index % 100) == 96) assign feedback = 22'h200697;
else if((index % 100) == 97) assign feedback = 22'h20069B;
else if((index % 100) == 98) assign feedback = 22'h20069E;
else if((index % 100) == 99) assign feedback = 22'h2006A8;
end
else if(width == 23)
begin
if((index % 100) == 0) assign feedback = 23'h400010;
else if((index % 100) == 1) assign feedback = 23'h400015;
else if((index % 100) == 2) assign feedback = 23'h400016;
else if((index % 100) == 3) assign feedback = 23'h400019;
else if((index % 100) == 4) assign feedback = 23'h40001F;
else if((index % 100) == 5) assign feedback = 23'h400026;
else if((index % 100) == 6) assign feedback = 23'h400032;
else if((index % 100) == 7) assign feedback = 23'h40003B;
else if((index % 100) == 8) assign feedback = 23'h400043;
else if((index % 100) == 9) assign feedback = 23'h400045;
else if((index % 100) == 10) assign feedback = 23'h40004C;
else if((index % 100) == 11) assign feedback = 23'h400051;
else if((index % 100) == 12) assign feedback = 23'h40005E;
else if((index % 100) == 13) assign feedback = 23'h400062;
else if((index % 100) == 14) assign feedback = 23'h400079;
else if((index % 100) == 15) assign feedback = 23'h40007C;
else if((index % 100) == 16) assign feedback = 23'h400097;
else if((index % 100) == 17) assign feedback = 23'h40009D;
else if((index % 100) == 18) assign feedback = 23'h4000AD;
else if((index % 100) == 19) assign feedback = 23'h4000B0;
else if((index % 100) == 20) assign feedback = 23'h4000B3;
else if((index % 100) == 21) assign feedback = 23'h4000C1;
else if((index % 100) == 22) assign feedback = 23'h4000C4;
else if((index % 100) == 23) assign feedback = 23'h4000FB;
else if((index % 100) == 24) assign feedback = 23'h400100;
else if((index % 100) == 25) assign feedback = 23'h40010F;
else if((index % 100) == 26) assign feedback = 23'h400112;
else if((index % 100) == 27) assign feedback = 23'h400124;
else if((index % 100) == 28) assign feedback = 23'h400127;
else if((index % 100) == 29) assign feedback = 23'h40012B;
else if((index % 100) == 30) assign feedback = 23'h40012D;
else if((index % 100) == 31) assign feedback = 23'h400136;
else if((index % 100) == 32) assign feedback = 23'h40013C;
else if((index % 100) == 33) assign feedback = 23'h400147;
else if((index % 100) == 34) assign feedback = 23'h400148;
else if((index % 100) == 35) assign feedback = 23'h40015C;
else if((index % 100) == 36) assign feedback = 23'h40016F;
else if((index % 100) == 37) assign feedback = 23'h400177;
else if((index % 100) == 38) assign feedback = 23'h400181;
else if((index % 100) == 39) assign feedback = 23'h400193;
else if((index % 100) == 40) assign feedback = 23'h400196;
else if((index % 100) == 41) assign feedback = 23'h4001A0;
else if((index % 100) == 42) assign feedback = 23'h4001B2;
else if((index % 100) == 43) assign feedback = 23'h4001D1;
else if((index % 100) == 44) assign feedback = 23'h4001D2;
else if((index % 100) == 45) assign feedback = 23'h4001D8;
else if((index % 100) == 46) assign feedback = 23'h4001DE;
else if((index % 100) == 47) assign feedback = 23'h4001F6;
else if((index % 100) == 48) assign feedback = 23'h400206;
else if((index % 100) == 49) assign feedback = 23'h400214;
else if((index % 100) == 50) assign feedback = 23'h400228;
else if((index % 100) == 51) assign feedback = 23'h400247;
else if((index % 100) == 52) assign feedback = 23'h400260;
else if((index % 100) == 53) assign feedback = 23'h40026F;
else if((index % 100) == 54) assign feedback = 23'h400293;
else if((index % 100) == 55) assign feedback = 23'h400295;
else if((index % 100) == 56) assign feedback = 23'h4002A0;
else if((index % 100) == 57) assign feedback = 23'h4002B7;
else if((index % 100) == 58) assign feedback = 23'h4002D2;
else if((index % 100) == 59) assign feedback = 23'h4002D4;
else if((index % 100) == 60) assign feedback = 23'h4002E2;
else if((index % 100) == 61) assign feedback = 23'h4002F0;
else if((index % 100) == 62) assign feedback = 23'h400308;
else if((index % 100) == 63) assign feedback = 23'h40030E;
else if((index % 100) == 64) assign feedback = 23'h40032F;
else if((index % 100) == 65) assign feedback = 23'h400331;
else if((index % 100) == 66) assign feedback = 23'h400340;
else if((index % 100) == 67) assign feedback = 23'h40035D;
else if((index % 100) == 68) assign feedback = 23'h400362;
else if((index % 100) == 69) assign feedback = 23'h40036D;
else if((index % 100) == 70) assign feedback = 23'h40036E;
else if((index % 100) == 71) assign feedback = 23'h400376;
else if((index % 100) == 72) assign feedback = 23'h400379;
else if((index % 100) == 73) assign feedback = 23'h400389;
else if((index % 100) == 74) assign feedback = 23'h40038A;
else if((index % 100) == 75) assign feedback = 23'h400391;
else if((index % 100) == 76) assign feedback = 23'h40039B;
else if((index % 100) == 77) assign feedback = 23'h4003BF;
else if((index % 100) == 78) assign feedback = 23'h4003D0;
else if((index % 100) == 79) assign feedback = 23'h4003DA;
else if((index % 100) == 80) assign feedback = 23'h4003EF;
else if((index % 100) == 81) assign feedback = 23'h4003F2;
else if((index % 100) == 82) assign feedback = 23'h4003FB;
else if((index % 100) == 83) assign feedback = 23'h4003FD;
else if((index % 100) == 84) assign feedback = 23'h40041D;
else if((index % 100) == 85) assign feedback = 23'h40041E;
else if((index % 100) == 86) assign feedback = 23'h40042D;
else if((index % 100) == 87) assign feedback = 23'h40043F;
else if((index % 100) == 88) assign feedback = 23'h400444;
else if((index % 100) == 89) assign feedback = 23'h40044D;
else if((index % 100) == 90) assign feedback = 23'h400455;
else if((index % 100) == 91) assign feedback = 23'h400456;
else if((index % 100) == 92) assign feedback = 23'h400460;
else if((index % 100) == 93) assign feedback = 23'h400463;
else if((index % 100) == 94) assign feedback = 23'h40046A;
else if((index % 100) == 95) assign feedback = 23'h400484;
else if((index % 100) == 96) assign feedback = 23'h400490;
else if((index % 100) == 97) assign feedback = 23'h40049C;
else if((index % 100) == 98) assign feedback = 23'h4004AA;
else if((index % 100) == 99) assign feedback = 23'h4004B2;
end
else if(width == 24)
begin
if((index % 100) == 0) assign feedback = 24'h80000D;
else if((index % 100) == 1) assign feedback = 24'h800043;
else if((index % 100) == 2) assign feedback = 24'h800058;
else if((index % 100) == 3) assign feedback = 24'h80006D;
else if((index % 100) == 4) assign feedback = 24'h80007A;
else if((index % 100) == 5) assign feedback = 24'h800092;
else if((index % 100) == 6) assign feedback = 24'h8000BF;
else if((index % 100) == 7) assign feedback = 24'h8000DA;
else if((index % 100) == 8) assign feedback = 24'h8000E5;
else if((index % 100) == 9) assign feedback = 24'h800112;
else if((index % 100) == 10) assign feedback = 24'h800128;
else if((index % 100) == 11) assign feedback = 24'h80012B;
else if((index % 100) == 12) assign feedback = 24'h800136;
else if((index % 100) == 13) assign feedback = 24'h8001B1;
else if((index % 100) == 14) assign feedback = 24'h8001B4;
else if((index % 100) == 15) assign feedback = 24'h8001D7;
else if((index % 100) == 16) assign feedback = 24'h8001E1;
else if((index % 100) == 17) assign feedback = 24'h8001E7;
else if((index % 100) == 18) assign feedback = 24'h8001F9;
else if((index % 100) == 19) assign feedback = 24'h80020C;
else if((index % 100) == 20) assign feedback = 24'h800221;
else if((index % 100) == 21) assign feedback = 24'h800224;
else if((index % 100) == 22) assign feedback = 24'h8002BD;
else if((index % 100) == 23) assign feedback = 24'h800329;
else if((index % 100) == 24) assign feedback = 24'h800345;
else if((index % 100) == 25) assign feedback = 24'h80035E;
else if((index % 100) == 26) assign feedback = 24'h8003A7;
else if((index % 100) == 27) assign feedback = 24'h8003A8;
else if((index % 100) == 28) assign feedback = 24'h8003C7;
else if((index % 100) == 29) assign feedback = 24'h800412;
else if((index % 100) == 30) assign feedback = 24'h80041B;
else if((index % 100) == 31) assign feedback = 24'h800422;
else if((index % 100) == 32) assign feedback = 24'h80042B;
else if((index % 100) == 33) assign feedback = 24'h80044E;
else if((index % 100) == 34) assign feedback = 24'h800453;
else if((index % 100) == 35) assign feedback = 24'h80047E;
else if((index % 100) == 36) assign feedback = 24'h800481;
else if((index % 100) == 37) assign feedback = 24'h8004DE;
else if((index % 100) == 38) assign feedback = 24'h8004ED;
else if((index % 100) == 39) assign feedback = 24'h8004F6;
else if((index % 100) == 40) assign feedback = 24'h800507;
else if((index % 100) == 41) assign feedback = 24'h800520;
else if((index % 100) == 42) assign feedback = 24'h800523;
else if((index % 100) == 43) assign feedback = 24'h80053D;
else if((index % 100) == 44) assign feedback = 24'h80055D;
else if((index % 100) == 45) assign feedback = 24'h800579;
else if((index % 100) == 46) assign feedback = 24'h800580;
else if((index % 100) == 47) assign feedback = 24'h80058F;
else if((index % 100) == 48) assign feedback = 24'h800594;
else if((index % 100) == 49) assign feedback = 24'h80059B;
else if((index % 100) == 50) assign feedback = 24'h8005A2;
else if((index % 100) == 51) assign feedback = 24'h8005A4;
else if((index % 100) == 52) assign feedback = 24'h8005A8;
else if((index % 100) == 53) assign feedback = 24'h8005BA;
else if((index % 100) == 54) assign feedback = 24'h8005D6;
else if((index % 100) == 55) assign feedback = 24'h8005EA;
else if((index % 100) == 56) assign feedback = 24'h800602;
else if((index % 100) == 57) assign feedback = 24'h800613;
else if((index % 100) == 58) assign feedback = 24'h80066E;
else if((index % 100) == 59) assign feedback = 24'h80067F;
else if((index % 100) == 60) assign feedback = 24'h80069B;
else if((index % 100) == 61) assign feedback = 24'h8006B5;
else if((index % 100) == 62) assign feedback = 24'h8006E6;
else if((index % 100) == 63) assign feedback = 24'h8006E9;
else if((index % 100) == 64) assign feedback = 24'h8006EF;
else if((index % 100) == 65) assign feedback = 24'h8006F4;
else if((index % 100) == 66) assign feedback = 24'h80070A;
else if((index % 100) == 67) assign feedback = 24'h800730;
else if((index % 100) == 68) assign feedback = 24'h800759;
else if((index % 100) == 69) assign feedback = 24'h80075F;
else if((index % 100) == 70) assign feedback = 24'h800795;
else if((index % 100) == 71) assign feedback = 24'h8007BE;
else if((index % 100) == 72) assign feedback = 24'h8007DE;
else if((index % 100) == 73) assign feedback = 24'h8007E4;
else if((index % 100) == 74) assign feedback = 24'h800806;
else if((index % 100) == 75) assign feedback = 24'h800817;
else if((index % 100) == 76) assign feedback = 24'h800853;
else if((index % 100) == 77) assign feedback = 24'h800863;
else if((index % 100) == 78) assign feedback = 24'h8008A6;
else if((index % 100) == 79) assign feedback = 24'h8008D1;
else if((index % 100) == 80) assign feedback = 24'h8008D7;
else if((index % 100) == 81) assign feedback = 24'h8008E7;
else if((index % 100) == 82) assign feedback = 24'h8008F3;
else if((index % 100) == 83) assign feedback = 24'h8008FC;
else if((index % 100) == 84) assign feedback = 24'h80090B;
else if((index % 100) == 85) assign feedback = 24'h800916;
else if((index % 100) == 86) assign feedback = 24'h80093B;
else if((index % 100) == 87) assign feedback = 24'h800973;
else if((index % 100) == 88) assign feedback = 24'h8009F8;
else if((index % 100) == 89) assign feedback = 24'h8009FE;
else if((index % 100) == 90) assign feedback = 24'h800A23;
else if((index % 100) == 91) assign feedback = 24'h800A3E;
else if((index % 100) == 92) assign feedback = 24'h800AA1;
else if((index % 100) == 93) assign feedback = 24'h800AA7;
else if((index % 100) == 94) assign feedback = 24'h800AAB;
else if((index % 100) == 95) assign feedback = 24'h800AC4;
else if((index % 100) == 96) assign feedback = 24'h800AD5;
else if((index % 100) == 97) assign feedback = 24'h800B35;
else if((index % 100) == 98) assign feedback = 24'h800B4D;
else if((index % 100) == 99) assign feedback = 24'h800B87;
end
else if(width == 25)
begin
if((index % 100) == 0) assign feedback = 25'h1000004;
else if((index % 100) == 1) assign feedback = 25'h1000007;
else if((index % 100) == 2) assign feedback = 25'h1000016;
else if((index % 100) == 3) assign feedback = 25'h1000040;
else if((index % 100) == 4) assign feedback = 25'h1000049;
else if((index % 100) == 5) assign feedback = 25'h1000062;
else if((index % 100) == 6) assign feedback = 25'h100007F;
else if((index % 100) == 7) assign feedback = 25'h1000086;
else if((index % 100) == 8) assign feedback = 25'h100009E;
else if((index % 100) == 9) assign feedback = 25'h10000A2;
else if((index % 100) == 10) assign feedback = 25'h10000B9;
else if((index % 100) == 11) assign feedback = 25'h10000CB;
else if((index % 100) == 12) assign feedback = 25'h10000D0;
else if((index % 100) == 13) assign feedback = 25'h10000D6;
else if((index % 100) == 14) assign feedback = 25'h10000DC;
else if((index % 100) == 15) assign feedback = 25'h10000E9;
else if((index % 100) == 16) assign feedback = 25'h10000EF;
else if((index % 100) == 17) assign feedback = 25'h10000F4;
else if((index % 100) == 18) assign feedback = 25'h100010A;
else if((index % 100) == 19) assign feedback = 25'h1000111;
else if((index % 100) == 20) assign feedback = 25'h1000118;
else if((index % 100) == 21) assign feedback = 25'h1000144;
else if((index % 100) == 22) assign feedback = 25'h1000160;
else if((index % 100) == 23) assign feedback = 25'h1000165;
else if((index % 100) == 24) assign feedback = 25'h100016F;
else if((index % 100) == 25) assign feedback = 25'h1000172;
else if((index % 100) == 26) assign feedback = 25'h100017D;
else if((index % 100) == 27) assign feedback = 25'h1000182;
else if((index % 100) == 28) assign feedback = 25'h100018B;
else if((index % 100) == 29) assign feedback = 25'h1000190;
else if((index % 100) == 30) assign feedback = 25'h100019C;
else if((index % 100) == 31) assign feedback = 25'h10001A5;
else if((index % 100) == 32) assign feedback = 25'h10001A6;
else if((index % 100) == 33) assign feedback = 25'h10001AF;
else if((index % 100) == 34) assign feedback = 25'h10001B7;
else if((index % 100) == 35) assign feedback = 25'h10001E2;
else if((index % 100) == 36) assign feedback = 25'h10001F5;
else if((index % 100) == 37) assign feedback = 25'h10001FC;
else if((index % 100) == 38) assign feedback = 25'h1000205;
else if((index % 100) == 39) assign feedback = 25'h1000206;
else if((index % 100) == 40) assign feedback = 25'h1000239;
else if((index % 100) == 41) assign feedback = 25'h100025F;
else if((index % 100) == 42) assign feedback = 25'h100026A;
else if((index % 100) == 43) assign feedback = 25'h1000272;
else if((index % 100) == 44) assign feedback = 25'h100027B;
else if((index % 100) == 45) assign feedback = 25'h100027E;
else if((index % 100) == 46) assign feedback = 25'h1000287;
else if((index % 100) == 47) assign feedback = 25'h1000290;
else if((index % 100) == 48) assign feedback = 25'h1000296;
else if((index % 100) == 49) assign feedback = 25'h100029F;
else if((index % 100) == 50) assign feedback = 25'h10002A3;
else if((index % 100) == 51) assign feedback = 25'h10002B4;
else if((index % 100) == 52) assign feedback = 25'h10002B8;
else if((index % 100) == 53) assign feedback = 25'h10002D8;
else if((index % 100) == 54) assign feedback = 25'h10002E7;
else if((index % 100) == 55) assign feedback = 25'h10002EB;
else if((index % 100) == 56) assign feedback = 25'h10002F3;
else if((index % 100) == 57) assign feedback = 25'h1000310;
else if((index % 100) == 58) assign feedback = 25'h1000319;
else if((index % 100) == 59) assign feedback = 25'h1000320;
else if((index % 100) == 60) assign feedback = 25'h100032F;
else if((index % 100) == 61) assign feedback = 25'h1000334;
else if((index % 100) == 62) assign feedback = 25'h100033D;
else if((index % 100) == 63) assign feedback = 25'h1000349;
else if((index % 100) == 64) assign feedback = 25'h100035B;
else if((index % 100) == 65) assign feedback = 25'h1000361;
else if((index % 100) == 66) assign feedback = 25'h1000376;
else if((index % 100) == 67) assign feedback = 25'h100037C;
else if((index % 100) == 68) assign feedback = 25'h1000386;
else if((index % 100) == 69) assign feedback = 25'h1000392;
else if((index % 100) == 70) assign feedback = 25'h1000398;
else if((index % 100) == 71) assign feedback = 25'h100039B;
else if((index % 100) == 72) assign feedback = 25'h100039D;
else if((index % 100) == 73) assign feedback = 25'h10003C8;
else if((index % 100) == 74) assign feedback = 25'h10003CE;
else if((index % 100) == 75) assign feedback = 25'h10003DA;
else if((index % 100) == 76) assign feedback = 25'h10003DC;
else if((index % 100) == 77) assign feedback = 25'h10003E5;
else if((index % 100) == 78) assign feedback = 25'h10003EA;
else if((index % 100) == 79) assign feedback = 25'h10003F1;
else if((index % 100) == 80) assign feedback = 25'h10003FD;
else if((index % 100) == 81) assign feedback = 25'h100042B;
else if((index % 100) == 82) assign feedback = 25'h100042E;
else if((index % 100) == 83) assign feedback = 25'h100043A;
else if((index % 100) == 84) assign feedback = 25'h1000444;
else if((index % 100) == 85) assign feedback = 25'h100044E;
else if((index % 100) == 86) assign feedback = 25'h1000469;
else if((index % 100) == 87) assign feedback = 25'h100046A;
else if((index % 100) == 88) assign feedback = 25'h1000478;
else if((index % 100) == 89) assign feedback = 25'h100047B;
else if((index % 100) == 90) assign feedback = 25'h100048D;
else if((index % 100) == 91) assign feedback = 25'h100048E;
else if((index % 100) == 92) assign feedback = 25'h1000493;
else if((index % 100) == 93) assign feedback = 25'h1000495;
else if((index % 100) == 94) assign feedback = 25'h10004A0;
else if((index % 100) == 95) assign feedback = 25'h10004B1;
else if((index % 100) == 96) assign feedback = 25'h10004B7;
else if((index % 100) == 97) assign feedback = 25'h10004C9;
else if((index % 100) == 98) assign feedback = 25'h10004EB;
else if((index % 100) == 99) assign feedback = 25'h10004F3;
end
else if(width == 26)
begin
if((index % 100) == 0) assign feedback = 26'h2000023;
else if((index % 100) == 1) assign feedback = 26'h2000026;
else if((index % 100) == 2) assign feedback = 26'h2000058;
else if((index % 100) == 3) assign feedback = 26'h2000070;
else if((index % 100) == 4) assign feedback = 26'h200007A;
else if((index % 100) == 5) assign feedback = 26'h200008C;
else if((index % 100) == 6) assign feedback = 26'h200009D;
else if((index % 100) == 7) assign feedback = 26'h20000B6;
else if((index % 100) == 8) assign feedback = 26'h20000BF;
else if((index % 100) == 9) assign feedback = 26'h20000C1;
else if((index % 100) == 10) assign feedback = 26'h20000C4;
else if((index % 100) == 11) assign feedback = 26'h20000DF;
else if((index % 100) == 12) assign feedback = 26'h20000F1;
else if((index % 100) == 13) assign feedback = 26'h2000109;
else if((index % 100) == 14) assign feedback = 26'h200011D;
else if((index % 100) == 15) assign feedback = 26'h2000122;
else if((index % 100) == 16) assign feedback = 26'h2000139;
else if((index % 100) == 17) assign feedback = 26'h2000142;
else if((index % 100) == 18) assign feedback = 26'h200014E;
else if((index % 100) == 19) assign feedback = 26'h2000155;
else if((index % 100) == 20) assign feedback = 26'h200015C;
else if((index % 100) == 21) assign feedback = 26'h2000178;
else if((index % 100) == 22) assign feedback = 26'h200017D;
else if((index % 100) == 23) assign feedback = 26'h20001A0;
else if((index % 100) == 24) assign feedback = 26'h20001A5;
else if((index % 100) == 25) assign feedback = 26'h20001DB;
else if((index % 100) == 26) assign feedback = 26'h20001E4;
else if((index % 100) == 27) assign feedback = 26'h20001FC;
else if((index % 100) == 28) assign feedback = 26'h2000214;
else if((index % 100) == 29) assign feedback = 26'h200021D;
else if((index % 100) == 30) assign feedback = 26'h2000244;
else if((index % 100) == 31) assign feedback = 26'h200024B;
else if((index % 100) == 32) assign feedback = 26'h200024D;
else if((index % 100) == 33) assign feedback = 26'h2000250;
else if((index % 100) == 34) assign feedback = 26'h2000274;
else if((index % 100) == 35) assign feedback = 26'h200028E;
else if((index % 100) == 36) assign feedback = 26'h20002BE;
else if((index % 100) == 37) assign feedback = 26'h20002C5;
else if((index % 100) == 38) assign feedback = 26'h20002DB;
else if((index % 100) == 39) assign feedback = 26'h20002E2;
else if((index % 100) == 40) assign feedback = 26'h2000323;
else if((index % 100) == 41) assign feedback = 26'h2000331;
else if((index % 100) == 42) assign feedback = 26'h200033D;
else if((index % 100) == 43) assign feedback = 26'h2000346;
else if((index % 100) == 44) assign feedback = 26'h200034A;
else if((index % 100) == 45) assign feedback = 26'h2000376;
else if((index % 100) == 46) assign feedback = 26'h200037F;
else if((index % 100) == 47) assign feedback = 26'h2000383;
else if((index % 100) == 48) assign feedback = 26'h2000385;
else if((index % 100) == 49) assign feedback = 26'h200038C;
else if((index % 100) == 50) assign feedback = 26'h2000398;
else if((index % 100) == 51) assign feedback = 26'h200039B;
else if((index % 100) == 52) assign feedback = 26'h200039E;
else if((index % 100) == 53) assign feedback = 26'h20003A7;
else if((index % 100) == 54) assign feedback = 26'h20003D6;
else if((index % 100) == 55) assign feedback = 26'h2000414;
else if((index % 100) == 56) assign feedback = 26'h200041B;
else if((index % 100) == 57) assign feedback = 26'h2000421;
else if((index % 100) == 58) assign feedback = 26'h200042D;
else if((index % 100) == 59) assign feedback = 26'h200045F;
else if((index % 100) == 60) assign feedback = 26'h2000460;
else if((index % 100) == 61) assign feedback = 26'h2000472;
else if((index % 100) == 62) assign feedback = 26'h2000477;
else if((index % 100) == 63) assign feedback = 26'h2000484;
else if((index % 100) == 64) assign feedback = 26'h2000487;
else if((index % 100) == 65) assign feedback = 26'h2000495;
else if((index % 100) == 66) assign feedback = 26'h20004CC;
else if((index % 100) == 67) assign feedback = 26'h20004D8;
else if((index % 100) == 68) assign feedback = 26'h20004DE;
else if((index % 100) == 69) assign feedback = 26'h200051A;
else if((index % 100) == 70) assign feedback = 26'h200053E;
else if((index % 100) == 71) assign feedback = 26'h200055B;
else if((index % 100) == 72) assign feedback = 26'h200057A;
else if((index % 100) == 73) assign feedback = 26'h2000580;
else if((index % 100) == 74) assign feedback = 26'h2000589;
else if((index % 100) == 75) assign feedback = 26'h2000592;
else if((index % 100) == 76) assign feedback = 26'h20005A7;
else if((index % 100) == 77) assign feedback = 26'h20005BC;
else if((index % 100) == 78) assign feedback = 26'h20005BF;
else if((index % 100) == 79) assign feedback = 26'h20005C2;
else if((index % 100) == 80) assign feedback = 26'h20005D5;
else if((index % 100) == 81) assign feedback = 26'h20005DA;
else if((index % 100) == 82) assign feedback = 26'h20005E3;
else if((index % 100) == 83) assign feedback = 26'h20005F1;
else if((index % 100) == 84) assign feedback = 26'h2000607;
else if((index % 100) == 85) assign feedback = 26'h2000608;
else if((index % 100) == 86) assign feedback = 26'h200062C;
else if((index % 100) == 87) assign feedback = 26'h2000637;
else if((index % 100) == 88) assign feedback = 26'h2000645;
else if((index % 100) == 89) assign feedback = 26'h200065B;
else if((index % 100) == 90) assign feedback = 26'h2000679;
else if((index % 100) == 91) assign feedback = 26'h200068F;
else if((index % 100) == 92) assign feedback = 26'h20006B9;
else if((index % 100) == 93) assign feedback = 26'h20006CD;
else if((index % 100) == 94) assign feedback = 26'h20006D5;
else if((index % 100) == 95) assign feedback = 26'h20006E3;
else if((index % 100) == 96) assign feedback = 26'h20006F4;
else if((index % 100) == 97) assign feedback = 26'h2000700;
else if((index % 100) == 98) assign feedback = 26'h2000709;
else if((index % 100) == 99) assign feedback = 26'h200072D;
end
else if(width == 27)
begin
if((index % 100) == 0) assign feedback = 27'h4000013;
else if((index % 100) == 1) assign feedback = 27'h4000068;
else if((index % 100) == 2) assign feedback = 27'h4000073;
else if((index % 100) == 3) assign feedback = 27'h4000075;
else if((index % 100) == 4) assign feedback = 27'h4000094;
else if((index % 100) == 5) assign feedback = 27'h4000098;
else if((index % 100) == 6) assign feedback = 27'h40000AE;
else if((index % 100) == 7) assign feedback = 27'h40000B6;
else if((index % 100) == 8) assign feedback = 27'h40000BC;
else if((index % 100) == 9) assign feedback = 27'h40000C1;
else if((index % 100) == 10) assign feedback = 27'h40000F1;
else if((index % 100) == 11) assign feedback = 27'h4000112;
else if((index % 100) == 12) assign feedback = 27'h4000114;
else if((index % 100) == 13) assign feedback = 27'h400011B;
else if((index % 100) == 14) assign feedback = 27'h4000128;
else if((index % 100) == 15) assign feedback = 27'h4000144;
else if((index % 100) == 16) assign feedback = 27'h4000182;
else if((index % 100) == 17) assign feedback = 27'h40001AA;
else if((index % 100) == 18) assign feedback = 27'h40001B4;
else if((index % 100) == 19) assign feedback = 27'h40001BD;
else if((index % 100) == 20) assign feedback = 27'h40001D1;
else if((index % 100) == 21) assign feedback = 27'h40001D4;
else if((index % 100) == 22) assign feedback = 27'h40001E7;
else if((index % 100) == 23) assign feedback = 27'h4000203;
else if((index % 100) == 24) assign feedback = 27'h4000218;
else if((index % 100) == 25) assign feedback = 27'h4000227;
else if((index % 100) == 26) assign feedback = 27'h400022D;
else if((index % 100) == 27) assign feedback = 27'h400022E;
else if((index % 100) == 28) assign feedback = 27'h4000242;
else if((index % 100) == 29) assign feedback = 27'h400024D;
else if((index % 100) == 30) assign feedback = 27'h400025A;
else if((index % 100) == 31) assign feedback = 27'h4000277;
else if((index % 100) == 32) assign feedback = 27'h4000290;
else if((index % 100) == 33) assign feedback = 27'h40002A5;
else if((index % 100) == 34) assign feedback = 27'h40002AA;
else if((index % 100) == 35) assign feedback = 27'h40002B7;
else if((index % 100) == 36) assign feedback = 27'h40002C0;
else if((index % 100) == 37) assign feedback = 27'h40002D2;
else if((index % 100) == 38) assign feedback = 27'h40002D8;
else if((index % 100) == 39) assign feedback = 27'h40002F0;
else if((index % 100) == 40) assign feedback = 27'h40002F5;
else if((index % 100) == 41) assign feedback = 27'h40002FC;
else if((index % 100) == 42) assign feedback = 27'h400031A;
else if((index % 100) == 43) assign feedback = 27'h400031C;
else if((index % 100) == 44) assign feedback = 27'h400032C;
else if((index % 100) == 45) assign feedback = 27'h4000340;
else if((index % 100) == 46) assign feedback = 27'h400034C;
else if((index % 100) == 47) assign feedback = 27'h4000354;
else if((index % 100) == 48) assign feedback = 27'h400035D;
else if((index % 100) == 49) assign feedback = 27'h400039E;
else if((index % 100) == 50) assign feedback = 27'h40003A7;
else if((index % 100) == 51) assign feedback = 27'h40003AB;
else if((index % 100) == 52) assign feedback = 27'h40003B3;
else if((index % 100) == 53) assign feedback = 27'h40003B5;
else if((index % 100) == 54) assign feedback = 27'h40003B9;
else if((index % 100) == 55) assign feedback = 27'h40003DF;
else if((index % 100) == 56) assign feedback = 27'h40003E3;
else if((index % 100) == 57) assign feedback = 27'h40003F4;
else if((index % 100) == 58) assign feedback = 27'h400040F;
else if((index % 100) == 59) assign feedback = 27'h400042B;
else if((index % 100) == 60) assign feedback = 27'h4000436;
else if((index % 100) == 61) assign feedback = 27'h4000453;
else if((index % 100) == 62) assign feedback = 27'h4000471;
else if((index % 100) == 63) assign feedback = 27'h4000474;
else if((index % 100) == 64) assign feedback = 27'h400048D;
else if((index % 100) == 65) assign feedback = 27'h4000499;
else if((index % 100) == 66) assign feedback = 27'h40004A6;
else if((index % 100) == 67) assign feedback = 27'h40004B2;
else if((index % 100) == 68) assign feedback = 27'h40004BD;
else if((index % 100) == 69) assign feedback = 27'h40004D1;
else if((index % 100) == 70) assign feedback = 27'h40004DB;
else if((index % 100) == 71) assign feedback = 27'h40004E7;
else if((index % 100) == 72) assign feedback = 27'h40004ED;
else if((index % 100) == 73) assign feedback = 27'h40004F5;
else if((index % 100) == 74) assign feedback = 27'h4000507;
else if((index % 100) == 75) assign feedback = 27'h400050E;
else if((index % 100) == 76) assign feedback = 27'h400052A;
else if((index % 100) == 77) assign feedback = 27'h4000534;
else if((index % 100) == 78) assign feedback = 27'h4000545;
else if((index % 100) == 79) assign feedback = 27'h400054C;
else if((index % 100) == 80) assign feedback = 27'h4000551;
else if((index % 100) == 81) assign feedback = 27'h4000562;
else if((index % 100) == 82) assign feedback = 27'h400056E;
else if((index % 100) == 83) assign feedback = 27'h4000597;
else if((index % 100) == 84) assign feedback = 27'h400059E;
else if((index % 100) == 85) assign feedback = 27'h40005A4;
else if((index % 100) == 86) assign feedback = 27'h40005BF;
else if((index % 100) == 87) assign feedback = 27'h40005D3;
else if((index % 100) == 88) assign feedback = 27'h40005D6;
else if((index % 100) == 89) assign feedback = 27'h40005E9;
else if((index % 100) == 90) assign feedback = 27'h40005EC;
else if((index % 100) == 91) assign feedback = 27'h40005FB;
else if((index % 100) == 92) assign feedback = 27'h4000607;
else if((index % 100) == 93) assign feedback = 27'h400062F;
else if((index % 100) == 94) assign feedback = 27'h4000649;
else if((index % 100) == 95) assign feedback = 27'h4000652;
else if((index % 100) == 96) assign feedback = 27'h4000670;
else if((index % 100) == 97) assign feedback = 27'h400067C;
else if((index % 100) == 98) assign feedback = 27'h4000680;
else if((index % 100) == 99) assign feedback = 27'h40006AE;
end
else if(width == 28)
begin
if((index % 100) == 0) assign feedback = 28'h8000004;
else if((index % 100) == 1) assign feedback = 28'h8000029;
else if((index % 100) == 2) assign feedback = 28'h800003B;
else if((index % 100) == 3) assign feedback = 28'h8000070;
else if((index % 100) == 4) assign feedback = 28'h80000B3;
else if((index % 100) == 5) assign feedback = 28'h80000B9;
else if((index % 100) == 6) assign feedback = 28'h80000EF;
else if((index % 100) == 7) assign feedback = 28'h8000100;
else if((index % 100) == 8) assign feedback = 28'h8000111;
else if((index % 100) == 9) assign feedback = 28'h8000159;
else if((index % 100) == 10) assign feedback = 28'h800016C;
else if((index % 100) == 11) assign feedback = 28'h8000190;
else if((index % 100) == 12) assign feedback = 28'h800019C;
else if((index % 100) == 13) assign feedback = 28'h80001AC;
else if((index % 100) == 14) assign feedback = 28'h80001B8;
else if((index % 100) == 15) assign feedback = 28'h80001D8;
else if((index % 100) == 16) assign feedback = 28'h8000205;
else if((index % 100) == 17) assign feedback = 28'h8000214;
else if((index % 100) == 18) assign feedback = 28'h8000217;
else if((index % 100) == 19) assign feedback = 28'h8000256;
else if((index % 100) == 20) assign feedback = 28'h800025A;
else if((index % 100) == 21) assign feedback = 28'h800027E;
else if((index % 100) == 22) assign feedback = 28'h8000296;
else if((index % 100) == 23) assign feedback = 28'h80002E1;
else if((index % 100) == 24) assign feedback = 28'h80002EB;
else if((index % 100) == 25) assign feedback = 28'h80002F5;
else if((index % 100) == 26) assign feedback = 28'h8000308;
else if((index % 100) == 27) assign feedback = 28'h800031F;
else if((index % 100) == 28) assign feedback = 28'h8000334;
else if((index % 100) == 29) assign feedback = 28'h800033E;
else if((index % 100) == 30) assign feedback = 28'h8000358;
else if((index % 100) == 31) assign feedback = 28'h800035B;
else if((index % 100) == 32) assign feedback = 28'h800037F;
else if((index % 100) == 33) assign feedback = 28'h8000380;
else if((index % 100) == 34) assign feedback = 28'h8000386;
else if((index % 100) == 35) assign feedback = 28'h80003C8;
else if((index % 100) == 36) assign feedback = 28'h80003CB;
else if((index % 100) == 37) assign feedback = 28'h80003E6;
else if((index % 100) == 38) assign feedback = 28'h800043A;
else if((index % 100) == 39) assign feedback = 28'h8000444;
else if((index % 100) == 40) assign feedback = 28'h800044B;
else if((index % 100) == 41) assign feedback = 28'h8000456;
else if((index % 100) == 42) assign feedback = 28'h800047D;
else if((index % 100) == 43) assign feedback = 28'h800048D;
else if((index % 100) == 44) assign feedback = 28'h800049A;
else if((index % 100) == 45) assign feedback = 28'h80004B2;
else if((index % 100) == 46) assign feedback = 28'h80004BB;
else if((index % 100) == 47) assign feedback = 28'h80004D2;
else if((index % 100) == 48) assign feedback = 28'h80004D7;
else if((index % 100) == 49) assign feedback = 28'h80004E8;
else if((index % 100) == 50) assign feedback = 28'h800050E;
else if((index % 100) == 51) assign feedback = 28'h8000554;
else if((index % 100) == 52) assign feedback = 28'h8000564;
else if((index % 100) == 53) assign feedback = 28'h800056B;
else if((index % 100) == 54) assign feedback = 28'h8000579;
else if((index % 100) == 55) assign feedback = 28'h800057C;
else if((index % 100) == 56) assign feedback = 28'h8000597;
else if((index % 100) == 57) assign feedback = 28'h80005AD;
else if((index % 100) == 58) assign feedback = 28'h80005C1;
else if((index % 100) == 59) assign feedback = 28'h80005C2;
else if((index % 100) == 60) assign feedback = 28'h80005E6;
else if((index % 100) == 61) assign feedback = 28'h80005F7;
else if((index % 100) == 62) assign feedback = 28'h8000604;
else if((index % 100) == 63) assign feedback = 28'h8000662;
else if((index % 100) == 64) assign feedback = 28'h8000668;
else if((index % 100) == 65) assign feedback = 28'h800068F;
else if((index % 100) == 66) assign feedback = 28'h800069D;
else if((index % 100) == 67) assign feedback = 28'h80006BA;
else if((index % 100) == 68) assign feedback = 28'h80006CE;
else if((index % 100) == 69) assign feedback = 28'h80006FB;
else if((index % 100) == 70) assign feedback = 28'h800070F;
else if((index % 100) == 71) assign feedback = 28'h8000724;
else if((index % 100) == 72) assign feedback = 28'h8000727;
else if((index % 100) == 73) assign feedback = 28'h8000735;
else if((index % 100) == 74) assign feedback = 28'h80007A5;
else if((index % 100) == 75) assign feedback = 28'h80007A9;
else if((index % 100) == 76) assign feedback = 28'h80007AF;
else if((index % 100) == 77) assign feedback = 28'h80007DB;
else if((index % 100) == 78) assign feedback = 28'h80007F3;
else if((index % 100) == 79) assign feedback = 28'h80007F6;
else if((index % 100) == 80) assign feedback = 28'h80007FF;
else if((index % 100) == 81) assign feedback = 28'h8000803;
else if((index % 100) == 82) assign feedback = 28'h800082D;
else if((index % 100) == 83) assign feedback = 28'h8000835;
else if((index % 100) == 84) assign feedback = 28'h8000836;
else if((index % 100) == 85) assign feedback = 28'h8000853;
else if((index % 100) == 86) assign feedback = 28'h8000893;
else if((index % 100) == 87) assign feedback = 28'h80008E2;
else if((index % 100) == 88) assign feedback = 28'h8000907;
else if((index % 100) == 89) assign feedback = 28'h800090E;
else if((index % 100) == 90) assign feedback = 28'h800092C;
else if((index % 100) == 91) assign feedback = 28'h8000932;
else if((index % 100) == 92) assign feedback = 28'h8000949;
else if((index % 100) == 93) assign feedback = 28'h8000961;
else if((index % 100) == 94) assign feedback = 28'h8000964;
else if((index % 100) == 95) assign feedback = 28'h8000979;
else if((index % 100) == 96) assign feedback = 28'h8000991;
else if((index % 100) == 97) assign feedback = 28'h80009AE;
else if((index % 100) == 98) assign feedback = 28'h80009DC;
else if((index % 100) == 99) assign feedback = 28'h80009E3;
end
else if(width == 29)
begin
if((index % 100) == 0) assign feedback = 29'h10000002;
else if((index % 100) == 1) assign feedback = 29'h1000000B;
else if((index % 100) == 2) assign feedback = 29'h1000000E;
else if((index % 100) == 3) assign feedback = 29'h10000046;
else if((index % 100) == 4) assign feedback = 29'h10000061;
else if((index % 100) == 5) assign feedback = 29'h1000007C;
else if((index % 100) == 6) assign feedback = 29'h1000008C;
else if((index % 100) == 7) assign feedback = 29'h1000009D;
else if((index % 100) == 8) assign feedback = 29'h1000009E;
else if((index % 100) == 9) assign feedback = 29'h100000B9;
else if((index % 100) == 10) assign feedback = 29'h100000C4;
else if((index % 100) == 11) assign feedback = 29'h100000C8;
else if((index % 100) == 12) assign feedback = 29'h100000D5;
else if((index % 100) == 13) assign feedback = 29'h100000DF;
else if((index % 100) == 14) assign feedback = 29'h10000103;
else if((index % 100) == 15) assign feedback = 29'h1000010A;
else if((index % 100) == 16) assign feedback = 29'h10000130;
else if((index % 100) == 17) assign feedback = 29'h10000139;
else if((index % 100) == 18) assign feedback = 29'h10000147;
else if((index % 100) == 19) assign feedback = 29'h10000182;
else if((index % 100) == 20) assign feedback = 29'h100001A5;
else if((index % 100) == 21) assign feedback = 29'h100001A9;
else if((index % 100) == 22) assign feedback = 29'h100001B2;
else if((index % 100) == 23) assign feedback = 29'h100001BB;
else if((index % 100) == 24) assign feedback = 29'h100001BE;
else if((index % 100) == 25) assign feedback = 29'h100001CA;
else if((index % 100) == 26) assign feedback = 29'h100001DE;
else if((index % 100) == 27) assign feedback = 29'h100001FA;
else if((index % 100) == 28) assign feedback = 29'h10000206;
else if((index % 100) == 29) assign feedback = 29'h10000211;
else if((index % 100) == 30) assign feedback = 29'h10000218;
else if((index % 100) == 31) assign feedback = 29'h10000221;
else if((index % 100) == 32) assign feedback = 29'h1000022E;
else if((index % 100) == 33) assign feedback = 29'h10000235;
else if((index % 100) == 34) assign feedback = 29'h10000239;
else if((index % 100) == 35) assign feedback = 29'h1000023C;
else if((index % 100) == 36) assign feedback = 29'h1000024B;
else if((index % 100) == 37) assign feedback = 29'h1000024D;
else if((index % 100) == 38) assign feedback = 29'h10000256;
else if((index % 100) == 39) assign feedback = 29'h10000260;
else if((index % 100) == 40) assign feedback = 29'h1000026F;
else if((index % 100) == 41) assign feedback = 29'h1000027B;
else if((index % 100) == 42) assign feedback = 29'h1000029A;
else if((index % 100) == 43) assign feedback = 29'h1000029F;
else if((index % 100) == 44) assign feedback = 29'h100002A0;
else if((index % 100) == 45) assign feedback = 29'h100002A5;
else if((index % 100) == 46) assign feedback = 29'h100002A9;
else if((index % 100) == 47) assign feedback = 29'h100002B8;
else if((index % 100) == 48) assign feedback = 29'h100002C5;
else if((index % 100) == 49) assign feedback = 29'h100002D7;
else if((index % 100) == 50) assign feedback = 29'h100002DD;
else if((index % 100) == 51) assign feedback = 29'h100002E2;
else if((index % 100) == 52) assign feedback = 29'h100002EB;
else if((index % 100) == 53) assign feedback = 29'h100002F3;
else if((index % 100) == 54) assign feedback = 29'h10000308;
else if((index % 100) == 55) assign feedback = 29'h10000310;
else if((index % 100) == 56) assign feedback = 29'h1000031A;
else if((index % 100) == 57) assign feedback = 29'h10000331;
else if((index % 100) == 58) assign feedback = 29'h10000337;
else if((index % 100) == 59) assign feedback = 29'h10000340;
else if((index % 100) == 60) assign feedback = 29'h10000349;
else if((index % 100) == 61) assign feedback = 29'h10000352;
else if((index % 100) == 62) assign feedback = 29'h10000370;
else if((index % 100) == 63) assign feedback = 29'h10000375;
else if((index % 100) == 64) assign feedback = 29'h10000385;
else if((index % 100) == 65) assign feedback = 29'h10000389;
else if((index % 100) == 66) assign feedback = 29'h1000038A;
else if((index % 100) == 67) assign feedback = 29'h1000038C;
else if((index % 100) == 68) assign feedback = 29'h10000398;
else if((index % 100) == 69) assign feedback = 29'h100003A8;
else if((index % 100) == 70) assign feedback = 29'h100003C1;
else if((index % 100) == 71) assign feedback = 29'h100003C2;
else if((index % 100) == 72) assign feedback = 29'h100003D3;
else if((index % 100) == 73) assign feedback = 29'h100003D6;
else if((index % 100) == 74) assign feedback = 29'h100003E6;
else if((index % 100) == 75) assign feedback = 29'h100003FD;
else if((index % 100) == 76) assign feedback = 29'h1000041E;
else if((index % 100) == 77) assign feedback = 29'h10000422;
else if((index % 100) == 78) assign feedback = 29'h1000042D;
else if((index % 100) == 79) assign feedback = 29'h10000447;
else if((index % 100) == 80) assign feedback = 29'h10000455;
else if((index % 100) == 81) assign feedback = 29'h10000460;
else if((index % 100) == 82) assign feedback = 29'h1000046C;
else if((index % 100) == 83) assign feedback = 29'h10000471;
else if((index % 100) == 84) assign feedback = 29'h100004A9;
else if((index % 100) == 85) assign feedback = 29'h100004B1;
else if((index % 100) == 86) assign feedback = 29'h100004B2;
else if((index % 100) == 87) assign feedback = 29'h100004B4;
else if((index % 100) == 88) assign feedback = 29'h100004BB;
else if((index % 100) == 89) assign feedback = 29'h100004C6;
else if((index % 100) == 90) assign feedback = 29'h100004F3;
else if((index % 100) == 91) assign feedback = 29'h10000502;
else if((index % 100) == 92) assign feedback = 29'h10000508;
else if((index % 100) == 93) assign feedback = 29'h1000051F;
else if((index % 100) == 94) assign feedback = 29'h10000557;
else if((index % 100) == 95) assign feedback = 29'h1000055B;
else if((index % 100) == 96) assign feedback = 29'h1000055E;
else if((index % 100) == 97) assign feedback = 29'h10000564;
else if((index % 100) == 98) assign feedback = 29'h10000576;
else if((index % 100) == 99) assign feedback = 29'h10000583;
end
else if(width == 30)
begin
if((index % 100) == 0) assign feedback = 30'h20000029;
else if((index % 100) == 1) assign feedback = 30'h20000057;
else if((index % 100) == 2) assign feedback = 30'h2000005E;
else if((index % 100) == 3) assign feedback = 30'h20000089;
else if((index % 100) == 4) assign feedback = 30'h200000A4;
else if((index % 100) == 5) assign feedback = 30'h200000EC;
else if((index % 100) == 6) assign feedback = 30'h2000011E;
else if((index % 100) == 7) assign feedback = 30'h20000148;
else if((index % 100) == 8) assign feedback = 30'h2000014E;
else if((index % 100) == 9) assign feedback = 30'h20000160;
else if((index % 100) == 10) assign feedback = 30'h20000172;
else if((index % 100) == 11) assign feedback = 30'h2000017B;
else if((index % 100) == 12) assign feedback = 30'h2000018B;
else if((index % 100) == 13) assign feedback = 30'h200001E7;
else if((index % 100) == 14) assign feedback = 30'h200001EB;
else if((index % 100) == 15) assign feedback = 30'h20000241;
else if((index % 100) == 16) assign feedback = 30'h20000244;
else if((index % 100) == 17) assign feedback = 30'h2000027B;
else if((index % 100) == 18) assign feedback = 30'h2000027D;
else if((index % 100) == 19) assign feedback = 30'h200002AC;
else if((index % 100) == 20) assign feedback = 30'h2000031A;
else if((index % 100) == 21) assign feedback = 30'h20000332;
else if((index % 100) == 22) assign feedback = 30'h20000354;
else if((index % 100) == 23) assign feedback = 30'h20000357;
else if((index % 100) == 24) assign feedback = 30'h2000039E;
else if((index % 100) == 25) assign feedback = 30'h200003AB;
else if((index % 100) == 26) assign feedback = 30'h200003B9;
else if((index % 100) == 27) assign feedback = 30'h2000041D;
else if((index % 100) == 28) assign feedback = 30'h20000427;
else if((index % 100) == 29) assign feedback = 30'h20000439;
else if((index % 100) == 30) assign feedback = 30'h2000044E;
else if((index % 100) == 31) assign feedback = 30'h2000046C;
else if((index % 100) == 32) assign feedback = 30'h200004A5;
else if((index % 100) == 33) assign feedback = 30'h200004BE;
else if((index % 100) == 34) assign feedback = 30'h200004C5;
else if((index % 100) == 35) assign feedback = 30'h200004C9;
else if((index % 100) == 36) assign feedback = 30'h200004E1;
else if((index % 100) == 37) assign feedback = 30'h200004E4;
else if((index % 100) == 38) assign feedback = 30'h200004EE;
else if((index % 100) == 39) assign feedback = 30'h2000054C;
else if((index % 100) == 40) assign feedback = 30'h20000567;
else if((index % 100) == 41) assign feedback = 30'h20000597;
else if((index % 100) == 42) assign feedback = 30'h200005BA;
else if((index % 100) == 43) assign feedback = 30'h20000602;
else if((index % 100) == 44) assign feedback = 30'h20000619;
else if((index % 100) == 45) assign feedback = 30'h2000061C;
else if((index % 100) == 46) assign feedback = 30'h2000064A;
else if((index % 100) == 47) assign feedback = 30'h2000065B;
else if((index % 100) == 48) assign feedback = 30'h2000065D;
else if((index % 100) == 49) assign feedback = 30'h20000679;
else if((index % 100) == 50) assign feedback = 30'h200006CB;
else if((index % 100) == 51) assign feedback = 30'h200006D3;
else if((index % 100) == 52) assign feedback = 30'h20000705;
else if((index % 100) == 53) assign feedback = 30'h20000735;
else if((index % 100) == 54) assign feedback = 30'h20000759;
else if((index % 100) == 55) assign feedback = 30'h200007D2;
else if((index % 100) == 56) assign feedback = 30'h200007DD;
else if((index % 100) == 57) assign feedback = 30'h200007EB;
else if((index % 100) == 58) assign feedback = 30'h2000080F;
else if((index % 100) == 59) assign feedback = 30'h20000841;
else if((index % 100) == 60) assign feedback = 30'h20000847;
else if((index % 100) == 61) assign feedback = 30'h2000084E;
else if((index % 100) == 62) assign feedback = 30'h2000088D;
else if((index % 100) == 63) assign feedback = 30'h200008B4;
else if((index % 100) == 64) assign feedback = 30'h200008C3;
else if((index % 100) == 65) assign feedback = 30'h200008DD;
else if((index % 100) == 66) assign feedback = 30'h200008EB;
else if((index % 100) == 67) assign feedback = 30'h20000910;
else if((index % 100) == 68) assign feedback = 30'h2000093D;
else if((index % 100) == 69) assign feedback = 30'h20000951;
else if((index % 100) == 70) assign feedback = 30'h2000096E;
else if((index % 100) == 71) assign feedback = 30'h20000998;
else if((index % 100) == 72) assign feedback = 30'h2000099B;
else if((index % 100) == 73) assign feedback = 30'h200009AD;
else if((index % 100) == 74) assign feedback = 30'h200009C2;
else if((index % 100) == 75) assign feedback = 30'h200009C8;
else if((index % 100) == 76) assign feedback = 30'h200009D5;
else if((index % 100) == 77) assign feedback = 30'h20000A45;
else if((index % 100) == 78) assign feedback = 30'h20000A46;
else if((index % 100) == 79) assign feedback = 30'h20000A9D;
else if((index % 100) == 80) assign feedback = 30'h20000AE0;
else if((index % 100) == 81) assign feedback = 30'h20000AE9;
else if((index % 100) == 82) assign feedback = 30'h20000B03;
else if((index % 100) == 83) assign feedback = 30'h20000B09;
else if((index % 100) == 84) assign feedback = 30'h20000B18;
else if((index % 100) == 85) assign feedback = 30'h20000B53;
else if((index % 100) == 86) assign feedback = 30'h20000B72;
else if((index % 100) == 87) assign feedback = 30'h20000B7D;
else if((index % 100) == 88) assign feedback = 30'h20000B8E;
else if((index % 100) == 89) assign feedback = 30'h20000BA3;
else if((index % 100) == 90) assign feedback = 30'h20000BB8;
else if((index % 100) == 91) assign feedback = 30'h20000BBE;
else if((index % 100) == 92) assign feedback = 30'h20000BCA;
else if((index % 100) == 93) assign feedback = 30'h20000BD1;
else if((index % 100) == 94) assign feedback = 30'h20000C04;
else if((index % 100) == 95) assign feedback = 30'h20000C10;
else if((index % 100) == 96) assign feedback = 30'h20000C23;
else if((index % 100) == 97) assign feedback = 30'h20000C34;
else if((index % 100) == 98) assign feedback = 30'h20000C86;
else if((index % 100) == 99) assign feedback = 30'h20000C92;
end
else if(width == 31)
begin
if((index % 100) == 0) assign feedback = 31'h40000004;
else if((index % 100) == 1) assign feedback = 31'h40000007;
else if((index % 100) == 2) assign feedback = 31'h40000016;
else if((index % 100) == 3) assign feedback = 31'h4000001A;
else if((index % 100) == 4) assign feedback = 31'h40000020;
else if((index % 100) == 5) assign feedback = 31'h40000023;
else if((index % 100) == 6) assign feedback = 31'h4000002A;
else if((index % 100) == 7) assign feedback = 31'h40000040;
else if((index % 100) == 8) assign feedback = 31'h40000045;
else if((index % 100) == 9) assign feedback = 31'h40000054;
else if((index % 100) == 10) assign feedback = 31'h4000005D;
else if((index % 100) == 11) assign feedback = 31'h4000007F;
else if((index % 100) == 12) assign feedback = 31'h4000008F;
else if((index % 100) == 13) assign feedback = 31'h40000097;
else if((index % 100) == 14) assign feedback = 31'h400000A2;
else if((index % 100) == 15) assign feedback = 31'h400000AE;
else if((index % 100) == 16) assign feedback = 31'h400000B0;
else if((index % 100) == 17) assign feedback = 31'h400000B5;
else if((index % 100) == 18) assign feedback = 31'h400000D0;
else if((index % 100) == 19) assign feedback = 31'h400000D6;
else if((index % 100) == 20) assign feedback = 31'h400000E3;
else if((index % 100) == 21) assign feedback = 31'h40000105;
else if((index % 100) == 22) assign feedback = 31'h40000111;
else if((index % 100) == 23) assign feedback = 31'h40000118;
else if((index % 100) == 24) assign feedback = 31'h4000013C;
else if((index % 100) == 25) assign feedback = 31'h40000159;
else if((index % 100) == 26) assign feedback = 31'h40000169;
else if((index % 100) == 27) assign feedback = 31'h4000016F;
else if((index % 100) == 28) assign feedback = 31'h4000017B;
else if((index % 100) == 29) assign feedback = 31'h40000188;
else if((index % 100) == 30) assign feedback = 31'h4000018E;
else if((index % 100) == 31) assign feedback = 31'h40000193;
else if((index % 100) == 32) assign feedback = 31'h400001BD;
else if((index % 100) == 33) assign feedback = 31'h400001C9;
else if((index % 100) == 34) assign feedback = 31'h400001ED;
else if((index % 100) == 35) assign feedback = 31'h40000217;
else if((index % 100) == 36) assign feedback = 31'h40000230;
else if((index % 100) == 37) assign feedback = 31'h40000233;
else if((index % 100) == 38) assign feedback = 31'h40000255;
else if((index % 100) == 39) assign feedback = 31'h40000265;
else if((index % 100) == 40) assign feedback = 31'h4000026A;
else if((index % 100) == 41) assign feedback = 31'h40000272;
else if((index % 100) == 42) assign feedback = 31'h40000278;
else if((index % 100) == 43) assign feedback = 31'h4000028D;
else if((index % 100) == 44) assign feedback = 31'h4000029C;
else if((index % 100) == 45) assign feedback = 31'h4000029F;
else if((index % 100) == 46) assign feedback = 31'h400002B8;
else if((index % 100) == 47) assign feedback = 31'h400002C3;
else if((index % 100) == 48) assign feedback = 31'h400002C6;
else if((index % 100) == 49) assign feedback = 31'h400002E8;
else if((index % 100) == 50) assign feedback = 31'h400002F3;
else if((index % 100) == 51) assign feedback = 31'h400002FA;
else if((index % 100) == 52) assign feedback = 31'h40000301;
else if((index % 100) == 53) assign feedback = 31'h40000326;
else if((index % 100) == 54) assign feedback = 31'h4000033B;
else if((index % 100) == 55) assign feedback = 31'h4000034A;
else if((index % 100) == 56) assign feedback = 31'h4000034C;
else if((index % 100) == 57) assign feedback = 31'h4000037F;
else if((index % 100) == 58) assign feedback = 31'h4000038F;
else if((index % 100) == 59) assign feedback = 31'h40000394;
else if((index % 100) == 60) assign feedback = 31'h4000039D;
else if((index % 100) == 61) assign feedback = 31'h400003A4;
else if((index % 100) == 62) assign feedback = 31'h400003B6;
else if((index % 100) == 63) assign feedback = 31'h400003BF;
else if((index % 100) == 64) assign feedback = 31'h400003C1;
else if((index % 100) == 65) assign feedback = 31'h400003CB;
else if((index % 100) == 66) assign feedback = 31'h400003DA;
else if((index % 100) == 67) assign feedback = 31'h400003DC;
else if((index % 100) == 68) assign feedback = 31'h400003EA;
else if((index % 100) == 69) assign feedback = 31'h400003FE;
else if((index % 100) == 70) assign feedback = 31'h40000403;
else if((index % 100) == 71) assign feedback = 31'h4000040C;
else if((index % 100) == 72) assign feedback = 31'h40000459;
else if((index % 100) == 73) assign feedback = 31'h4000045C;
else if((index % 100) == 74) assign feedback = 31'h4000045F;
else if((index % 100) == 75) assign feedback = 31'h4000046A;
else if((index % 100) == 76) assign feedback = 31'h40000474;
else if((index % 100) == 77) assign feedback = 31'h4000047B;
else if((index % 100) == 78) assign feedback = 31'h40000481;
else if((index % 100) == 79) assign feedback = 31'h4000048D;
else if((index % 100) == 80) assign feedback = 31'h40000493;
else if((index % 100) == 81) assign feedback = 31'h400004B8;
else if((index % 100) == 82) assign feedback = 31'h400004DE;
else if((index % 100) == 83) assign feedback = 31'h400004ED;
else if((index % 100) == 84) assign feedback = 31'h40000501;
else if((index % 100) == 85) assign feedback = 31'h40000513;
else if((index % 100) == 86) assign feedback = 31'h40000525;
else if((index % 100) == 87) assign feedback = 31'h4000052F;
else if((index % 100) == 88) assign feedback = 31'h40000534;
else if((index % 100) == 89) assign feedback = 31'h40000538;
else if((index % 100) == 90) assign feedback = 31'h4000053E;
else if((index % 100) == 91) assign feedback = 31'h40000540;
else if((index % 100) == 92) assign feedback = 31'h40000549;
else if((index % 100) == 93) assign feedback = 31'h4000054F;
else if((index % 100) == 94) assign feedback = 31'h4000055D;
else if((index % 100) == 95) assign feedback = 31'h40000567;
else if((index % 100) == 96) assign feedback = 31'h4000056B;
else if((index % 100) == 97) assign feedback = 31'h40000576;
else if((index % 100) == 98) assign feedback = 31'h40000585;
else if((index % 100) == 99) assign feedback = 31'h400005B6;
end
else if(width == 32)
begin
if((index % 100) == 0) assign feedback = 32'h80000057;
else if((index % 100) == 1) assign feedback = 32'h80000062;
else if((index % 100) == 2) assign feedback = 32'h8000007A;
else if((index % 100) == 3) assign feedback = 32'h80000092;
else if((index % 100) == 4) assign feedback = 32'h800000B9;
else if((index % 100) == 5) assign feedback = 32'h800000BA;
else if((index % 100) == 6) assign feedback = 32'h80000106;
else if((index % 100) == 7) assign feedback = 32'h80000114;
else if((index % 100) == 8) assign feedback = 32'h8000012D;
else if((index % 100) == 9) assign feedback = 32'h8000014E;
else if((index % 100) == 10) assign feedback = 32'h8000016C;
else if((index % 100) == 11) assign feedback = 32'h8000019F;
else if((index % 100) == 12) assign feedback = 32'h800001A6;
else if((index % 100) == 13) assign feedback = 32'h800001F3;
else if((index % 100) == 14) assign feedback = 32'h8000020F;
else if((index % 100) == 15) assign feedback = 32'h800002CC;
else if((index % 100) == 16) assign feedback = 32'h80000349;
else if((index % 100) == 17) assign feedback = 32'h80000370;
else if((index % 100) == 18) assign feedback = 32'h80000375;
else if((index % 100) == 19) assign feedback = 32'h80000392;
else if((index % 100) == 20) assign feedback = 32'h80000398;
else if((index % 100) == 21) assign feedback = 32'h800003BF;
else if((index % 100) == 22) assign feedback = 32'h800003D6;
else if((index % 100) == 23) assign feedback = 32'h800003DF;
else if((index % 100) == 24) assign feedback = 32'h800003E9;
else if((index % 100) == 25) assign feedback = 32'h80000412;
else if((index % 100) == 26) assign feedback = 32'h80000414;
else if((index % 100) == 27) assign feedback = 32'h80000417;
else if((index % 100) == 28) assign feedback = 32'h80000465;
else if((index % 100) == 29) assign feedback = 32'h8000046A;
else if((index % 100) == 30) assign feedback = 32'h80000478;
else if((index % 100) == 31) assign feedback = 32'h800004D4;
else if((index % 100) == 32) assign feedback = 32'h800004F3;
else if((index % 100) == 33) assign feedback = 32'h8000050B;
else if((index % 100) == 34) assign feedback = 32'h80000526;
else if((index % 100) == 35) assign feedback = 32'h8000054C;
else if((index % 100) == 36) assign feedback = 32'h800005B6;
else if((index % 100) == 37) assign feedback = 32'h800005C1;
else if((index % 100) == 38) assign feedback = 32'h800005EC;
else if((index % 100) == 39) assign feedback = 32'h800005F1;
else if((index % 100) == 40) assign feedback = 32'h8000060D;
else if((index % 100) == 41) assign feedback = 32'h8000060E;
else if((index % 100) == 42) assign feedback = 32'h80000629;
else if((index % 100) == 43) assign feedback = 32'h80000638;
else if((index % 100) == 44) assign feedback = 32'h80000662;
else if((index % 100) == 45) assign feedback = 32'h8000066D;
else if((index % 100) == 46) assign feedback = 32'h80000676;
else if((index % 100) == 47) assign feedback = 32'h800006AE;
else if((index % 100) == 48) assign feedback = 32'h800006B0;
else if((index % 100) == 49) assign feedback = 32'h800006BC;
else if((index % 100) == 50) assign feedback = 32'h800006D6;
else if((index % 100) == 51) assign feedback = 32'h8000073C;
else if((index % 100) == 52) assign feedback = 32'h80000748;
else if((index % 100) == 53) assign feedback = 32'h80000766;
else if((index % 100) == 54) assign feedback = 32'h8000079C;
else if((index % 100) == 55) assign feedback = 32'h800007B7;
else if((index % 100) == 56) assign feedback = 32'h800007C3;
else if((index % 100) == 57) assign feedback = 32'h800007D4;
else if((index % 100) == 58) assign feedback = 32'h800007D8;
else if((index % 100) == 59) assign feedback = 32'h80000806;
else if((index % 100) == 60) assign feedback = 32'h8000083F;
else if((index % 100) == 61) assign feedback = 32'h80000850;
else if((index % 100) == 62) assign feedback = 32'h8000088D;
else if((index % 100) == 63) assign feedback = 32'h800008E1;
else if((index % 100) == 64) assign feedback = 32'h80000923;
else if((index % 100) == 65) assign feedback = 32'h80000931;
else if((index % 100) == 66) assign feedback = 32'h80000934;
else if((index % 100) == 67) assign feedback = 32'h8000093B;
else if((index % 100) == 68) assign feedback = 32'h80000958;
else if((index % 100) == 69) assign feedback = 32'h80000967;
else if((index % 100) == 70) assign feedback = 32'h800009D5;
else if((index % 100) == 71) assign feedback = 32'h80000A25;
else if((index % 100) == 72) assign feedback = 32'h80000A26;
else if((index % 100) == 73) assign feedback = 32'h80000A54;
else if((index % 100) == 74) assign feedback = 32'h80000A92;
else if((index % 100) == 75) assign feedback = 32'h80000AC4;
else if((index % 100) == 76) assign feedback = 32'h80000ACD;
else if((index % 100) == 77) assign feedback = 32'h80000B28;
else if((index % 100) == 78) assign feedback = 32'h80000B71;
else if((index % 100) == 79) assign feedback = 32'h80000B7B;
else if((index % 100) == 80) assign feedback = 32'h80000B84;
else if((index % 100) == 81) assign feedback = 32'h80000BA9;
else if((index % 100) == 82) assign feedback = 32'h80000BBE;
else if((index % 100) == 83) assign feedback = 32'h80000BC6;
else if((index % 100) == 84) assign feedback = 32'h80000C34;
else if((index % 100) == 85) assign feedback = 32'h80000C3E;
else if((index % 100) == 86) assign feedback = 32'h80000C43;
else if((index % 100) == 87) assign feedback = 32'h80000C7F;
else if((index % 100) == 88) assign feedback = 32'h80000CA2;
else if((index % 100) == 89) assign feedback = 32'h80000CEC;
else if((index % 100) == 90) assign feedback = 32'h80000D0F;
else if((index % 100) == 91) assign feedback = 32'h80000D22;
else if((index % 100) == 92) assign feedback = 32'h80000D28;
else if((index % 100) == 93) assign feedback = 32'h80000D4E;
else if((index % 100) == 94) assign feedback = 32'h80000DD7;
else if((index % 100) == 95) assign feedback = 32'h80000E24;
else if((index % 100) == 96) assign feedback = 32'h80000E35;
else if((index % 100) == 97) assign feedback = 32'h80000E66;
else if((index % 100) == 98) assign feedback = 32'h80000E74;
else if((index % 100) == 99) assign feedback = 32'h80000EA6;
end
else if(width == 33)
begin
if((index % 100) == 0) assign feedback = 33'h100000029;
else if((index % 100) == 1) assign feedback = 33'h100000034;
else if((index % 100) == 2) assign feedback = 33'h100000043;
else if((index % 100) == 3) assign feedback = 33'h10000004C;
else if((index % 100) == 4) assign feedback = 33'h100000051;
else if((index % 100) == 5) assign feedback = 33'h10000006E;
else if((index % 100) == 6) assign feedback = 33'h100000076;
else if((index % 100) == 7) assign feedback = 33'h10000007A;
else if((index % 100) == 8) assign feedback = 33'h100000083;
else if((index % 100) == 9) assign feedback = 33'h100000091;
else if((index % 100) == 10) assign feedback = 33'h100000098;
else if((index % 100) == 11) assign feedback = 33'h1000000A7;
else if((index % 100) == 12) assign feedback = 33'h1000000B6;
else if((index % 100) == 13) assign feedback = 33'h1000000BC;
else if((index % 100) == 14) assign feedback = 33'h1000000C1;
else if((index % 100) == 15) assign feedback = 33'h1000000E3;
else if((index % 100) == 16) assign feedback = 33'h1000000E6;
else if((index % 100) == 17) assign feedback = 33'h1000000F1;
else if((index % 100) == 18) assign feedback = 33'h1000000F8;
else if((index % 100) == 19) assign feedback = 33'h1000000FE;
else if((index % 100) == 20) assign feedback = 33'h100000105;
else if((index % 100) == 21) assign feedback = 33'h10000010F;
else if((index % 100) == 22) assign feedback = 33'h10000013F;
else if((index % 100) == 23) assign feedback = 33'h10000014D;
else if((index % 100) == 24) assign feedback = 33'h10000014E;
else if((index % 100) == 25) assign feedback = 33'h100000153;
else if((index % 100) == 26) assign feedback = 33'h10000015C;
else if((index % 100) == 27) assign feedback = 33'h100000184;
else if((index % 100) == 28) assign feedback = 33'h100000199;
else if((index % 100) == 29) assign feedback = 33'h10000019F;
else if((index % 100) == 30) assign feedback = 33'h1000001A3;
else if((index % 100) == 31) assign feedback = 33'h1000001A9;
else if((index % 100) == 32) assign feedback = 33'h1000001AF;
else if((index % 100) == 33) assign feedback = 33'h1000001BD;
else if((index % 100) == 34) assign feedback = 33'h1000001CC;
else if((index % 100) == 35) assign feedback = 33'h1000001EE;
else if((index % 100) == 36) assign feedback = 33'h1000001F5;
else if((index % 100) == 37) assign feedback = 33'h100000203;
else if((index % 100) == 38) assign feedback = 33'h10000021E;
else if((index % 100) == 39) assign feedback = 33'h100000235;
else if((index % 100) == 40) assign feedback = 33'h100000244;
else if((index % 100) == 41) assign feedback = 33'h10000026C;
else if((index % 100) == 42) assign feedback = 33'h100000274;
else if((index % 100) == 43) assign feedback = 33'h10000027D;
else if((index % 100) == 44) assign feedback = 33'h10000029A;
else if((index % 100) == 45) assign feedback = 33'h1000002A5;
else if((index % 100) == 46) assign feedback = 33'h1000002DB;
else if((index % 100) == 47) assign feedback = 33'h1000002EB;
else if((index % 100) == 48) assign feedback = 33'h10000031C;
else if((index % 100) == 49) assign feedback = 33'h100000349;
else if((index % 100) == 50) assign feedback = 33'h100000357;
else if((index % 100) == 51) assign feedback = 33'h10000036B;
else if((index % 100) == 52) assign feedback = 33'h10000036D;
else if((index % 100) == 53) assign feedback = 33'h100000383;
else if((index % 100) == 54) assign feedback = 33'h1000003AE;
else if((index % 100) == 55) assign feedback = 33'h1000003EA;
else if((index % 100) == 56) assign feedback = 33'h1000003EF;
else if((index % 100) == 57) assign feedback = 33'h100000403;
else if((index % 100) == 58) assign feedback = 33'h100000412;
else if((index % 100) == 59) assign feedback = 33'h100000439;
else if((index % 100) == 60) assign feedback = 33'h100000447;
else if((index % 100) == 61) assign feedback = 33'h10000045A;
else if((index % 100) == 62) assign feedback = 33'h100000478;
else if((index % 100) == 63) assign feedback = 33'h100000484;
else if((index % 100) == 64) assign feedback = 33'h1000004B2;
else if((index % 100) == 65) assign feedback = 33'h1000004DB;
else if((index % 100) == 66) assign feedback = 33'h1000004FF;
else if((index % 100) == 67) assign feedback = 33'h100000526;
else if((index % 100) == 68) assign feedback = 33'h10000052F;
else if((index % 100) == 69) assign feedback = 33'h100000558;
else if((index % 100) == 70) assign feedback = 33'h100000575;
else if((index % 100) == 71) assign feedback = 33'h100000580;
else if((index % 100) == 72) assign feedback = 33'h100000585;
else if((index % 100) == 73) assign feedback = 33'h1000005A1;
else if((index % 100) == 74) assign feedback = 33'h1000005BA;
else if((index % 100) == 75) assign feedback = 33'h1000005DC;
else if((index % 100) == 76) assign feedback = 33'h1000005DF;
else if((index % 100) == 77) assign feedback = 33'h1000005F1;
else if((index % 100) == 78) assign feedback = 33'h100000602;
else if((index % 100) == 79) assign feedback = 33'h100000608;
else if((index % 100) == 80) assign feedback = 33'h100000610;
else if((index % 100) == 81) assign feedback = 33'h100000664;
else if((index % 100) == 82) assign feedback = 33'h10000066B;
else if((index % 100) == 83) assign feedback = 33'h100000689;
else if((index % 100) == 84) assign feedback = 33'h1000006B3;
else if((index % 100) == 85) assign feedback = 33'h1000006E5;
else if((index % 100) == 86) assign feedback = 33'h1000006E6;
else if((index % 100) == 87) assign feedback = 33'h1000006FB;
else if((index % 100) == 88) assign feedback = 33'h100000711;
else if((index % 100) == 89) assign feedback = 33'h100000714;
else if((index % 100) == 90) assign feedback = 33'h100000735;
else if((index % 100) == 91) assign feedback = 33'h10000073A;
else if((index % 100) == 92) assign feedback = 33'h100000747;
else if((index % 100) == 93) assign feedback = 33'h10000074B;
else if((index % 100) == 94) assign feedback = 33'h100000763;
else if((index % 100) == 95) assign feedback = 33'h100000766;
else if((index % 100) == 96) assign feedback = 33'h100000769;
else if((index % 100) == 97) assign feedback = 33'h100000784;
else if((index % 100) == 98) assign feedback = 33'h100000788;
else if((index % 100) == 99) assign feedback = 33'h1000007A3;
end
else if(width == 34)
begin
if((index % 100) == 0) assign feedback = 34'h200000073;
else if((index % 100) == 1) assign feedback = 34'h20000008C;
else if((index % 100) == 2) assign feedback = 34'h20000008F;
else if((index % 100) == 3) assign feedback = 34'h2000000BA;
else if((index % 100) == 4) assign feedback = 34'h2000000C7;
else if((index % 100) == 5) assign feedback = 34'h2000000D9;
else if((index % 100) == 6) assign feedback = 34'h2000000E9;
else if((index % 100) == 7) assign feedback = 34'h2000000F2;
else if((index % 100) == 8) assign feedback = 34'h200000111;
else if((index % 100) == 9) assign feedback = 34'h200000128;
else if((index % 100) == 10) assign feedback = 34'h20000015F;
else if((index % 100) == 11) assign feedback = 34'h200000172;
else if((index % 100) == 12) assign feedback = 34'h20000018E;
else if((index % 100) == 13) assign feedback = 34'h2000001A3;
else if((index % 100) == 14) assign feedback = 34'h2000001C6;
else if((index % 100) == 15) assign feedback = 34'h2000001CA;
else if((index % 100) == 16) assign feedback = 34'h2000001D4;
else if((index % 100) == 17) assign feedback = 34'h2000001ED;
else if((index % 100) == 18) assign feedback = 34'h200000214;
else if((index % 100) == 19) assign feedback = 34'h200000230;
else if((index % 100) == 20) assign feedback = 34'h20000023F;
else if((index % 100) == 21) assign feedback = 34'h200000253;
else if((index % 100) == 22) assign feedback = 34'h20000025A;
else if((index % 100) == 23) assign feedback = 34'h200000284;
else if((index % 100) == 24) assign feedback = 34'h20000028B;
else if((index % 100) == 25) assign feedback = 34'h200000290;
else if((index % 100) == 26) assign feedback = 34'h2000002C5;
else if((index % 100) == 27) assign feedback = 34'h2000002D8;
else if((index % 100) == 28) assign feedback = 34'h200000313;
else if((index % 100) == 29) assign feedback = 34'h200000326;
else if((index % 100) == 30) assign feedback = 34'h20000032F;
else if((index % 100) == 31) assign feedback = 34'h200000332;
else if((index % 100) == 32) assign feedback = 34'h200000334;
else if((index % 100) == 33) assign feedback = 34'h20000039D;
else if((index % 100) == 34) assign feedback = 34'h2000003B5;
else if((index % 100) == 35) assign feedback = 34'h2000003D0;
else if((index % 100) == 36) assign feedback = 34'h2000003DC;
else if((index % 100) == 37) assign feedback = 34'h200000435;
else if((index % 100) == 38) assign feedback = 34'h200000442;
else if((index % 100) == 39) assign feedback = 34'h200000447;
else if((index % 100) == 40) assign feedback = 34'h20000049F;
else if((index % 100) == 41) assign feedback = 34'h2000004A5;
else if((index % 100) == 42) assign feedback = 34'h2000004CC;
else if((index % 100) == 43) assign feedback = 34'h200000551;
else if((index % 100) == 44) assign feedback = 34'h20000056B;
else if((index % 100) == 45) assign feedback = 34'h20000056E;
else if((index % 100) == 46) assign feedback = 34'h200000575;
else if((index % 100) == 47) assign feedback = 34'h200000580;
else if((index % 100) == 48) assign feedback = 34'h2000005F4;
else if((index % 100) == 49) assign feedback = 34'h2000005F7;
else if((index % 100) == 50) assign feedback = 34'h2000005FB;
else if((index % 100) == 51) assign feedback = 34'h2000005FE;
else if((index % 100) == 52) assign feedback = 34'h200000626;
else if((index % 100) == 53) assign feedback = 34'h20000062F;
else if((index % 100) == 54) assign feedback = 34'h200000631;
else if((index % 100) == 55) assign feedback = 34'h200000645;
else if((index % 100) == 56) assign feedback = 34'h200000668;
else if((index % 100) == 57) assign feedback = 34'h2000006B9;
else if((index % 100) == 58) assign feedback = 34'h2000006D3;
else if((index % 100) == 59) assign feedback = 34'h2000006EA;
else if((index % 100) == 60) assign feedback = 34'h200000718;
else if((index % 100) == 61) assign feedback = 34'h200000727;
else if((index % 100) == 62) assign feedback = 34'h200000739;
else if((index % 100) == 63) assign feedback = 34'h200000750;
else if((index % 100) == 64) assign feedback = 34'h20000076A;
else if((index % 100) == 65) assign feedback = 34'h20000076F;
else if((index % 100) == 66) assign feedback = 34'h200000788;
else if((index % 100) == 67) assign feedback = 34'h200000793;
else if((index % 100) == 68) assign feedback = 34'h2000007A6;
else if((index % 100) == 69) assign feedback = 34'h2000007C9;
else if((index % 100) == 70) assign feedback = 34'h2000007CA;
else if((index % 100) == 71) assign feedback = 34'h2000007ED;
else if((index % 100) == 72) assign feedback = 34'h200000859;
else if((index % 100) == 73) assign feedback = 34'h20000089A;
else if((index % 100) == 74) assign feedback = 34'h2000008A6;
else if((index % 100) == 75) assign feedback = 34'h2000008D1;
else if((index % 100) == 76) assign feedback = 34'h2000008F0;
else if((index % 100) == 77) assign feedback = 34'h200000904;
else if((index % 100) == 78) assign feedback = 34'h200000925;
else if((index % 100) == 79) assign feedback = 34'h200000929;
else if((index % 100) == 80) assign feedback = 34'h200000932;
else if((index % 100) == 81) assign feedback = 34'h20000093B;
else if((index % 100) == 82) assign feedback = 34'h200000985;
else if((index % 100) == 83) assign feedback = 34'h200000986;
else if((index % 100) == 84) assign feedback = 34'h200000994;
else if((index % 100) == 85) assign feedback = 34'h20000099E;
else if((index % 100) == 86) assign feedback = 34'h2000009DC;
else if((index % 100) == 87) assign feedback = 34'h200000A01;
else if((index % 100) == 88) assign feedback = 34'h200000A04;
else if((index % 100) == 89) assign feedback = 34'h200000A10;
else if((index % 100) == 90) assign feedback = 34'h200000A26;
else if((index % 100) == 91) assign feedback = 34'h200000A29;
else if((index % 100) == 92) assign feedback = 34'h200000A6D;
else if((index % 100) == 93) assign feedback = 34'h200000A73;
else if((index % 100) == 94) assign feedback = 34'h200000A7A;
else if((index % 100) == 95) assign feedback = 34'h200000A89;
else if((index % 100) == 96) assign feedback = 34'h200000A94;
else if((index % 100) == 97) assign feedback = 34'h200000AA7;
else if((index % 100) == 98) assign feedback = 34'h200000ABC;
else if((index % 100) == 99) assign feedback = 34'h200000ABF;
end
else if(width == 35)
begin
if((index % 93) == 0) assign feedback = 35'h400000002;
else if((index % 93) == 1) assign feedback = 35'h40000002F;
else if((index % 93) == 2) assign feedback = 35'h40000004F;
else if((index % 93) == 3) assign feedback = 35'h400000057;
else if((index % 93) == 4) assign feedback = 35'h40000009E;
else if((index % 93) == 5) assign feedback = 35'h4000000B6;
else if((index % 93) == 6) assign feedback = 35'h4000000C1;
else if((index % 93) == 7) assign feedback = 35'h4000000CE;
else if((index % 93) == 8) assign feedback = 35'h4000000DC;
else if((index % 93) == 9) assign feedback = 35'h4000000F1;
else if((index % 93) == 10) assign feedback = 35'h4000000F2;
else if((index % 93) == 11) assign feedback = 35'h400000103;
else if((index % 93) == 12) assign feedback = 35'h400000122;
else if((index % 93) == 13) assign feedback = 35'h400000127;
else if((index % 93) == 14) assign feedback = 35'h400000135;
else if((index % 93) == 15) assign feedback = 35'h40000013C;
else if((index % 93) == 16) assign feedback = 35'h400000159;
else if((index % 93) == 17) assign feedback = 35'h400000166;
else if((index % 93) == 18) assign feedback = 35'h400000190;
else if((index % 93) == 19) assign feedback = 35'h4000001E4;
else if((index % 93) == 20) assign feedback = 35'h40000020A;
else if((index % 93) == 21) assign feedback = 35'h40000020C;
else if((index % 93) == 22) assign feedback = 35'h400000218;
else if((index % 93) == 23) assign feedback = 35'h400000239;
else if((index % 93) == 24) assign feedback = 35'h400000244;
else if((index % 93) == 25) assign feedback = 35'h40000028D;
else if((index % 93) == 26) assign feedback = 35'h40000029A;
else if((index % 93) == 27) assign feedback = 35'h4000002B7;
else if((index % 93) == 28) assign feedback = 35'h4000002B8;
else if((index % 93) == 29) assign feedback = 35'h4000002CC;
else if((index % 93) == 30) assign feedback = 35'h4000002D2;
else if((index % 93) == 31) assign feedback = 35'h4000002E4;
else if((index % 93) == 32) assign feedback = 35'h4000002F0;
else if((index % 93) == 33) assign feedback = 35'h4000002F6;
else if((index % 93) == 34) assign feedback = 35'h4000002F9;
else if((index % 93) == 35) assign feedback = 35'h400000301;
else if((index % 93) == 36) assign feedback = 35'h400000308;
else if((index % 93) == 37) assign feedback = 35'h40000032C;
else if((index % 93) == 38) assign feedback = 35'h400000338;
else if((index % 93) == 39) assign feedback = 35'h40000034F;
else if((index % 93) == 40) assign feedback = 35'h40000035B;
else if((index % 93) == 41) assign feedback = 35'h40000037F;
else if((index % 93) == 42) assign feedback = 35'h400000380;
else if((index % 93) == 43) assign feedback = 35'h4000003AE;
else if((index % 93) == 44) assign feedback = 35'h4000003BA;
else if((index % 93) == 45) assign feedback = 35'h4000003D9;
else if((index % 93) == 46) assign feedback = 35'h400000417;
else if((index % 93) == 47) assign feedback = 35'h40000041B;
else if((index % 93) == 48) assign feedback = 35'h40000042D;
else if((index % 93) == 49) assign feedback = 35'h400000430;
else if((index % 93) == 50) assign feedback = 35'h400000453;
else if((index % 93) == 51) assign feedback = 35'h400000463;
else if((index % 93) == 52) assign feedback = 35'h400000471;
else if((index % 93) == 53) assign feedback = 35'h400000478;
else if((index % 93) == 54) assign feedback = 35'h40000048D;
else if((index % 93) == 55) assign feedback = 35'h400000490;
else if((index % 93) == 56) assign feedback = 35'h400000496;
else if((index % 93) == 57) assign feedback = 35'h40000049C;
else if((index % 93) == 58) assign feedback = 35'h4000004B2;
else if((index % 93) == 59) assign feedback = 35'h4000004FA;
else if((index % 93) == 60) assign feedback = 35'h40000051A;
else if((index % 93) == 61) assign feedback = 35'h40000052C;
else if((index % 93) == 62) assign feedback = 35'h40000055E;
else if((index % 93) == 63) assign feedback = 35'h400000561;
else if((index % 93) == 64) assign feedback = 35'h400000594;
else if((index % 93) == 65) assign feedback = 35'h4000005AB;
else if((index % 93) == 66) assign feedback = 35'h4000005AE;
else if((index % 93) == 67) assign feedback = 35'h4000005E5;
else if((index % 93) == 68) assign feedback = 35'h4000005E6;
else if((index % 93) == 69) assign feedback = 35'h4000005F8;
else if((index % 93) == 70) assign feedback = 35'h40000061F;
else if((index % 93) == 71) assign feedback = 35'h400000623;
else if((index % 93) == 72) assign feedback = 35'h400000631;
else if((index % 93) == 73) assign feedback = 35'h40000063E;
else if((index % 93) == 74) assign feedback = 35'h400000652;
else if((index % 93) == 75) assign feedback = 35'h400000668;
else if((index % 93) == 76) assign feedback = 35'h40000066B;
else if((index % 93) == 77) assign feedback = 35'h400000670;
else if((index % 93) == 78) assign feedback = 35'h4000006CE;
else if((index % 93) == 79) assign feedback = 35'h4000006E3;
else if((index % 93) == 80) assign feedback = 35'h400000700;
else if((index % 93) == 81) assign feedback = 35'h400000709;
else if((index % 93) == 82) assign feedback = 35'h400000717;
else if((index % 93) == 83) assign feedback = 35'h40000071B;
else if((index % 93) == 84) assign feedback = 35'h40000071E;
else if((index % 93) == 85) assign feedback = 35'h400000728;
else if((index % 93) == 86) assign feedback = 35'h400000777;
else if((index % 93) == 87) assign feedback = 35'h4000007B4;
else if((index % 93) == 88) assign feedback = 35'h4000007CF;
else if((index % 93) == 89) assign feedback = 35'h4000007D1;
else if((index % 93) == 90) assign feedback = 35'h4000007D2;
else if((index % 93) == 91) assign feedback = 35'h4000007DD;
else if((index % 93) == 92) assign feedback = 35'h4000007EB;
end
else if(width == 36)
begin
if((index % 100) == 0) assign feedback = 36'h80000003B;
else if((index % 100) == 1) assign feedback = 36'h80000003D;
else if((index % 100) == 2) assign feedback = 36'h80000007C;
else if((index % 100) == 3) assign feedback = 36'h8000000B5;
else if((index % 100) == 4) assign feedback = 36'h8000000C1;
else if((index % 100) == 5) assign feedback = 36'h8000000F7;
else if((index % 100) == 6) assign feedback = 36'h80000010C;
else if((index % 100) == 7) assign feedback = 36'h80000011D;
else if((index % 100) == 8) assign feedback = 36'h800000133;
else if((index % 100) == 9) assign feedback = 36'h800000141;
else if((index % 100) == 10) assign feedback = 36'h800000156;
else if((index % 100) == 11) assign feedback = 36'h800000169;
else if((index % 100) == 12) assign feedback = 36'h800000171;
else if((index % 100) == 13) assign feedback = 36'h800000190;
else if((index % 100) == 14) assign feedback = 36'h8000001B8;
else if((index % 100) == 15) assign feedback = 36'h8000001E2;
else if((index % 100) == 16) assign feedback = 36'h8000001FA;
else if((index % 100) == 17) assign feedback = 36'h8000001FC;
else if((index % 100) == 18) assign feedback = 36'h800000221;
else if((index % 100) == 19) assign feedback = 36'h800000256;
else if((index % 100) == 20) assign feedback = 36'h80000028B;
else if((index % 100) == 21) assign feedback = 36'h800000299;
else if((index % 100) == 22) assign feedback = 36'h8000002DD;
else if((index % 100) == 23) assign feedback = 36'h80000030D;
else if((index % 100) == 24) assign feedback = 36'h800000345;
else if((index % 100) == 25) assign feedback = 36'h8000003A2;
else if((index % 100) == 26) assign feedback = 36'h8000003CE;
else if((index % 100) == 27) assign feedback = 36'h800000400;
else if((index % 100) == 28) assign feedback = 36'h800000448;
else if((index % 100) == 29) assign feedback = 36'h8000004CC;
else if((index % 100) == 30) assign feedback = 36'h800000510;
else if((index % 100) == 31) assign feedback = 36'h800000589;
else if((index % 100) == 32) assign feedback = 36'h8000005DF;
else if((index % 100) == 33) assign feedback = 36'h80000063D;
else if((index % 100) == 34) assign feedback = 36'h800000667;
else if((index % 100) == 35) assign feedback = 36'h800000676;
else if((index % 100) == 36) assign feedback = 36'h800000697;
else if((index % 100) == 37) assign feedback = 36'h800000772;
else if((index % 100) == 38) assign feedback = 36'h800000778;
else if((index % 100) == 39) assign feedback = 36'h800000787;
else if((index % 100) == 40) assign feedback = 36'h8000007C6;
else if((index % 100) == 41) assign feedback = 36'h800000830;
else if((index % 100) == 42) assign feedback = 36'h800000848;
else if((index % 100) == 43) assign feedback = 36'h800000855;
else if((index % 100) == 44) assign feedback = 36'h80000087B;
else if((index % 100) == 45) assign feedback = 36'h80000087E;
else if((index % 100) == 46) assign feedback = 36'h80000088B;
else if((index % 100) == 47) assign feedback = 36'h8000008B1;
else if((index % 100) == 48) assign feedback = 36'h8000008BD;
else if((index % 100) == 49) assign feedback = 36'h800000919;
else if((index % 100) == 50) assign feedback = 36'h800000929;
else if((index % 100) == 51) assign feedback = 36'h8000009A7;
else if((index % 100) == 52) assign feedback = 36'h8000009DC;
else if((index % 100) == 53) assign feedback = 36'h800000A01;
else if((index % 100) == 54) assign feedback = 36'h800000A31;
else if((index % 100) == 55) assign feedback = 36'h800000A32;
else if((index % 100) == 56) assign feedback = 36'h800000A62;
else if((index % 100) == 57) assign feedback = 36'h800000B17;
else if((index % 100) == 58) assign feedback = 36'h800000B2E;
else if((index % 100) == 59) assign feedback = 36'h800000B6C;
else if((index % 100) == 60) assign feedback = 36'h800000B7E;
else if((index % 100) == 61) assign feedback = 36'h800000B82;
else if((index % 100) == 62) assign feedback = 36'h800000B95;
else if((index % 100) == 63) assign feedback = 36'h800000B9A;
else if((index % 100) == 64) assign feedback = 36'h800000B9C;
else if((index % 100) == 65) assign feedback = 36'h800000BA6;
else if((index % 100) == 66) assign feedback = 36'h800000BD1;
else if((index % 100) == 67) assign feedback = 36'h800000BEB;
else if((index % 100) == 68) assign feedback = 36'h800000C0B;
else if((index % 100) == 69) assign feedback = 36'h800000C23;
else if((index % 100) == 70) assign feedback = 36'h800000C51;
else if((index % 100) == 71) assign feedback = 36'h800000C61;
else if((index % 100) == 72) assign feedback = 36'h800000C7C;
else if((index % 100) == 73) assign feedback = 36'h800000CCD;
else if((index % 100) == 74) assign feedback = 36'h800000CDC;
else if((index % 100) == 75) assign feedback = 36'h800000D65;
else if((index % 100) == 76) assign feedback = 36'h800000D74;
else if((index % 100) == 77) assign feedback = 36'h800000D7E;
else if((index % 100) == 78) assign feedback = 36'h800000D99;
else if((index % 100) == 79) assign feedback = 36'h800000DC9;
else if((index % 100) == 80) assign feedback = 36'h800000DD8;
else if((index % 100) == 81) assign feedback = 36'h800000E11;
else if((index % 100) == 82) assign feedback = 36'h800000E17;
else if((index % 100) == 83) assign feedback = 36'h800000F79;
else if((index % 100) == 84) assign feedback = 36'h800000F89;
else if((index % 100) == 85) assign feedback = 36'h800000F9E;
else if((index % 100) == 86) assign feedback = 36'h800000FD9;
else if((index % 100) == 87) assign feedback = 36'h800000FE0;
else if((index % 100) == 88) assign feedback = 36'h800000FE6;
else if((index % 100) == 89) assign feedback = 36'h800000FF7;
else if((index % 100) == 90) assign feedback = 36'h800001081;
else if((index % 100) == 91) assign feedback = 36'h8000010C0;
else if((index % 100) == 92) assign feedback = 36'h8000010D8;
else if((index % 100) == 93) assign feedback = 36'h80000111F;
else if((index % 100) == 94) assign feedback = 36'h800001120;
else if((index % 100) == 95) assign feedback = 36'h800001176;
else if((index % 100) == 96) assign feedback = 36'h8000011D5;
else if((index % 100) == 97) assign feedback = 36'h8000011E3;
else if((index % 100) == 98) assign feedback = 36'h80000122F;
else if((index % 100) == 99) assign feedback = 36'h80000123E;
end
else if(width == 37)
begin
if((index % 100) == 0) assign feedback = 37'h100000001F;
else if((index % 100) == 1) assign feedback = 37'h1000000029;
else if((index % 100) == 2) assign feedback = 37'h1000000038;
else if((index % 100) == 3) assign feedback = 37'h100000005B;
else if((index % 100) == 4) assign feedback = 37'h1000000064;
else if((index % 100) == 5) assign feedback = 37'h1000000068;
else if((index % 100) == 6) assign feedback = 37'h100000007A;
else if((index % 100) == 7) assign feedback = 37'h100000009E;
else if((index % 100) == 8) assign feedback = 37'h10000000AE;
else if((index % 100) == 9) assign feedback = 37'h10000000C4;
else if((index % 100) == 10) assign feedback = 37'h10000000E3;
else if((index % 100) == 11) assign feedback = 37'h10000000E6;
else if((index % 100) == 12) assign feedback = 37'h10000000E9;
else if((index % 100) == 13) assign feedback = 37'h10000000F8;
else if((index % 100) == 14) assign feedback = 37'h1000000103;
else if((index % 100) == 15) assign feedback = 37'h100000010C;
else if((index % 100) == 16) assign feedback = 37'h100000017D;
else if((index % 100) == 17) assign feedback = 37'h100000019C;
else if((index % 100) == 18) assign feedback = 37'h10000001A6;
else if((index % 100) == 19) assign feedback = 37'h10000001AA;
else if((index % 100) == 20) assign feedback = 37'h10000001AF;
else if((index % 100) == 21) assign feedback = 37'h10000001B1;
else if((index % 100) == 22) assign feedback = 37'h10000001B7;
else if((index % 100) == 23) assign feedback = 37'h10000001CF;
else if((index % 100) == 24) assign feedback = 37'h10000001DD;
else if((index % 100) == 25) assign feedback = 37'h10000001F9;
else if((index % 100) == 26) assign feedback = 37'h1000000214;
else if((index % 100) == 27) assign feedback = 37'h1000000233;
else if((index % 100) == 28) assign feedback = 37'h1000000260;
else if((index % 100) == 29) assign feedback = 37'h1000000271;
else if((index % 100) == 30) assign feedback = 37'h100000028B;
else if((index % 100) == 31) assign feedback = 37'h100000028E;
else if((index % 100) == 32) assign feedback = 37'h10000002B4;
else if((index % 100) == 33) assign feedback = 37'h10000002BB;
else if((index % 100) == 34) assign feedback = 37'h10000002DE;
else if((index % 100) == 35) assign feedback = 37'h10000002E1;
else if((index % 100) == 36) assign feedback = 37'h10000002E7;
else if((index % 100) == 37) assign feedback = 37'h10000002F0;
else if((index % 100) == 38) assign feedback = 37'h10000002F5;
else if((index % 100) == 39) assign feedback = 37'h1000000316;
else if((index % 100) == 40) assign feedback = 37'h1000000329;
else if((index % 100) == 41) assign feedback = 37'h1000000332;
else if((index % 100) == 42) assign feedback = 37'h1000000345;
else if((index % 100) == 43) assign feedback = 37'h100000035B;
else if((index % 100) == 44) assign feedback = 37'h100000037A;
else if((index % 100) == 45) assign feedback = 37'h1000000386;
else if((index % 100) == 46) assign feedback = 37'h100000038A;
else if((index % 100) == 47) assign feedback = 37'h10000003AB;
else if((index % 100) == 48) assign feedback = 37'h10000003B9;
else if((index % 100) == 49) assign feedback = 37'h10000003BC;
else if((index % 100) == 50) assign feedback = 37'h10000003D0;
else if((index % 100) == 51) assign feedback = 37'h10000003DA;
else if((index % 100) == 52) assign feedback = 37'h10000003EF;
else if((index % 100) == 53) assign feedback = 37'h1000000421;
else if((index % 100) == 54) assign feedback = 37'h1000000433;
else if((index % 100) == 55) assign feedback = 37'h1000000442;
else if((index % 100) == 56) assign feedback = 37'h100000044B;
else if((index % 100) == 57) assign feedback = 37'h1000000463;
else if((index % 100) == 58) assign feedback = 37'h1000000471;
else if((index % 100) == 59) assign feedback = 37'h1000000472;
else if((index % 100) == 60) assign feedback = 37'h100000049C;
else if((index % 100) == 61) assign feedback = 37'h10000004AC;
else if((index % 100) == 62) assign feedback = 37'h10000004B1;
else if((index % 100) == 63) assign feedback = 37'h10000004BE;
else if((index % 100) == 64) assign feedback = 37'h10000004C9;
else if((index % 100) == 65) assign feedback = 37'h10000004D7;
else if((index % 100) == 66) assign feedback = 37'h10000004E1;
else if((index % 100) == 67) assign feedback = 37'h10000004E4;
else if((index % 100) == 68) assign feedback = 37'h10000004F6;
else if((index % 100) == 69) assign feedback = 37'h10000004F9;
else if((index % 100) == 70) assign feedback = 37'h1000000523;
else if((index % 100) == 71) assign feedback = 37'h1000000526;
else if((index % 100) == 72) assign feedback = 37'h100000054F;
else if((index % 100) == 73) assign feedback = 37'h1000000562;
else if((index % 100) == 74) assign feedback = 37'h1000000575;
else if((index % 100) == 75) assign feedback = 37'h1000000592;
else if((index % 100) == 76) assign feedback = 37'h10000005BC;
else if((index % 100) == 77) assign feedback = 37'h10000005C1;
else if((index % 100) == 78) assign feedback = 37'h10000005C8;
else if((index % 100) == 79) assign feedback = 37'h10000005DA;
else if((index % 100) == 80) assign feedback = 37'h10000005E0;
else if((index % 100) == 81) assign feedback = 37'h10000005F4;
else if((index % 100) == 82) assign feedback = 37'h100000060D;
else if((index % 100) == 83) assign feedback = 37'h1000000623;
else if((index % 100) == 84) assign feedback = 37'h1000000632;
else if((index % 100) == 85) assign feedback = 37'h1000000634;
else if((index % 100) == 86) assign feedback = 37'h100000066B;
else if((index % 100) == 87) assign feedback = 37'h100000066E;
else if((index % 100) == 88) assign feedback = 37'h1000000679;
else if((index % 100) == 89) assign feedback = 37'h1000000680;
else if((index % 100) == 90) assign feedback = 37'h100000069B;
else if((index % 100) == 91) assign feedback = 37'h10000006A1;
else if((index % 100) == 92) assign feedback = 37'h10000006AB;
else if((index % 100) == 93) assign feedback = 37'h10000006D6;
else if((index % 100) == 94) assign feedback = 37'h10000006DF;
else if((index % 100) == 95) assign feedback = 37'h10000006F1;
else if((index % 100) == 96) assign feedback = 37'h10000006F2;
else if((index % 100) == 97) assign feedback = 37'h1000000718;
else if((index % 100) == 98) assign feedback = 37'h1000000722;
else if((index % 100) == 99) assign feedback = 37'h100000074E;
end
else if(width == 38)
begin
if((index % 100) == 0) assign feedback = 38'h2000000031;
else if((index % 100) == 1) assign feedback = 38'h2000000051;
else if((index % 100) == 2) assign feedback = 38'h200000006B;
else if((index % 100) == 3) assign feedback = 38'h20000000A1;
else if((index % 100) == 4) assign feedback = 38'h20000000B9;
else if((index % 100) == 5) assign feedback = 38'h20000000D5;
else if((index % 100) == 6) assign feedback = 38'h20000000F8;
else if((index % 100) == 7) assign feedback = 38'h20000000FB;
else if((index % 100) == 8) assign feedback = 38'h2000000106;
else if((index % 100) == 9) assign feedback = 38'h2000000163;
else if((index % 100) == 10) assign feedback = 38'h2000000184;
else if((index % 100) == 11) assign feedback = 38'h2000000199;
else if((index % 100) == 12) assign feedback = 38'h20000001B2;
else if((index % 100) == 13) assign feedback = 38'h20000001B4;
else if((index % 100) == 14) assign feedback = 38'h200000020F;
else if((index % 100) == 15) assign feedback = 38'h2000000239;
else if((index % 100) == 16) assign feedback = 38'h200000026F;
else if((index % 100) == 17) assign feedback = 38'h200000027D;
else if((index % 100) == 18) assign feedback = 38'h20000002AC;
else if((index % 100) == 19) assign feedback = 38'h20000002B2;
else if((index % 100) == 20) assign feedback = 38'h20000002B8;
else if((index % 100) == 21) assign feedback = 38'h200000032F;
else if((index % 100) == 22) assign feedback = 38'h2000000334;
else if((index % 100) == 23) assign feedback = 38'h200000037C;
else if((index % 100) == 24) assign feedback = 38'h200000037F;
else if((index % 100) == 25) assign feedback = 38'h2000000389;
else if((index % 100) == 26) assign feedback = 38'h2000000398;
else if((index % 100) == 27) assign feedback = 38'h20000003A8;
else if((index % 100) == 28) assign feedback = 38'h20000003C1;
else if((index % 100) == 29) assign feedback = 38'h20000003CB;
else if((index % 100) == 30) assign feedback = 38'h20000003CD;
else if((index % 100) == 31) assign feedback = 38'h20000003DA;
else if((index % 100) == 32) assign feedback = 38'h2000000412;
else if((index % 100) == 33) assign feedback = 38'h200000041B;
else if((index % 100) == 34) assign feedback = 38'h2000000428;
else if((index % 100) == 35) assign feedback = 38'h200000043F;
else if((index % 100) == 36) assign feedback = 38'h200000046A;
else if((index % 100) == 37) assign feedback = 38'h2000000472;
else if((index % 100) == 38) assign feedback = 38'h2000000477;
else if((index % 100) == 39) assign feedback = 38'h2000000490;
else if((index % 100) == 40) assign feedback = 38'h20000004AA;
else if((index % 100) == 41) assign feedback = 38'h20000004BD;
else if((index % 100) == 42) assign feedback = 38'h20000004C5;
else if((index % 100) == 43) assign feedback = 38'h20000004DE;
else if((index % 100) == 44) assign feedback = 38'h200000051A;
else if((index % 100) == 45) assign feedback = 38'h2000000552;
else if((index % 100) == 46) assign feedback = 38'h200000055B;
else if((index % 100) == 47) assign feedback = 38'h2000000564;
else if((index % 100) == 48) assign feedback = 38'h2000000568;
else if((index % 100) == 49) assign feedback = 38'h2000000573;
else if((index % 100) == 50) assign feedback = 38'h20000005D3;
else if((index % 100) == 51) assign feedback = 38'h20000005DC;
else if((index % 100) == 52) assign feedback = 38'h20000005E6;
else if((index % 100) == 53) assign feedback = 38'h20000005EF;
else if((index % 100) == 54) assign feedback = 38'h20000005FD;
else if((index % 100) == 55) assign feedback = 38'h2000000640;
else if((index % 100) == 56) assign feedback = 38'h2000000646;
else if((index % 100) == 57) assign feedback = 38'h200000064F;
else if((index % 100) == 58) assign feedback = 38'h2000000657;
else if((index % 100) == 59) assign feedback = 38'h2000000694;
else if((index % 100) == 60) assign feedback = 38'h2000000709;
else if((index % 100) == 61) assign feedback = 38'h2000000711;
else if((index % 100) == 62) assign feedback = 38'h200000072D;
else if((index % 100) == 63) assign feedback = 38'h2000000742;
else if((index % 100) == 64) assign feedback = 38'h2000000756;
else if((index % 100) == 65) assign feedback = 38'h200000076F;
else if((index % 100) == 66) assign feedback = 38'h200000078B;
else if((index % 100) == 67) assign feedback = 38'h2000000795;
else if((index % 100) == 68) assign feedback = 38'h20000007AC;
else if((index % 100) == 69) assign feedback = 38'h20000007B8;
else if((index % 100) == 70) assign feedback = 38'h20000007BE;
else if((index % 100) == 71) assign feedback = 38'h20000007E2;
else if((index % 100) == 72) assign feedback = 38'h20000007EE;
else if((index % 100) == 73) assign feedback = 38'h20000007FC;
else if((index % 100) == 74) assign feedback = 38'h2000000818;
else if((index % 100) == 75) assign feedback = 38'h200000081B;
else if((index % 100) == 76) assign feedback = 38'h200000081D;
else if((index % 100) == 77) assign feedback = 38'h200000083F;
else if((index % 100) == 78) assign feedback = 38'h200000085C;
else if((index % 100) == 79) assign feedback = 38'h20000008AF;
else if((index % 100) == 80) assign feedback = 38'h20000008B4;
else if((index % 100) == 81) assign feedback = 38'h2000000902;
else if((index % 100) == 82) assign feedback = 38'h200000090D;
else if((index % 100) == 83) assign feedback = 38'h200000091C;
else if((index % 100) == 84) assign feedback = 38'h2000000926;
else if((index % 100) == 85) assign feedback = 38'h2000000980;
else if((index % 100) == 86) assign feedback = 38'h2000000989;
else if((index % 100) == 87) assign feedback = 38'h20000009A1;
else if((index % 100) == 88) assign feedback = 38'h20000009AD;
else if((index % 100) == 89) assign feedback = 38'h20000009BA;
else if((index % 100) == 90) assign feedback = 38'h20000009C8;
else if((index % 100) == 91) assign feedback = 38'h2000000A37;
else if((index % 100) == 92) assign feedback = 38'h2000000A54;
else if((index % 100) == 93) assign feedback = 38'h2000000A6D;
else if((index % 100) == 94) assign feedback = 38'h2000000A6E;
else if((index % 100) == 95) assign feedback = 38'h2000000AA4;
else if((index % 100) == 96) assign feedback = 38'h2000000AC4;
else if((index % 100) == 97) assign feedback = 38'h2000000AC8;
else if((index % 100) == 98) assign feedback = 38'h2000000ACD;
else if((index % 100) == 99) assign feedback = 38'h2000000AE9;
end
else if(width == 39)
begin
if((index % 61) == 0) assign feedback = 39'h4000000008;
else if((index % 61) == 1) assign feedback = 39'h4000000049;
else if((index % 61) == 2) assign feedback = 39'h400000006E;
else if((index % 61) == 3) assign feedback = 39'h4000000080;
else if((index % 61) == 4) assign feedback = 39'h40000000A4;
else if((index % 61) == 5) assign feedback = 39'h40000000E3;
else if((index % 61) == 6) assign feedback = 39'h40000000F1;
else if((index % 61) == 7) assign feedback = 39'h4000000105;
else if((index % 61) == 8) assign feedback = 39'h4000000106;
else if((index % 61) == 9) assign feedback = 39'h4000000117;
else if((index % 61) == 10) assign feedback = 39'h4000000121;
else if((index % 61) == 11) assign feedback = 39'h400000012D;
else if((index % 61) == 12) assign feedback = 39'h4000000130;
else if((index % 61) == 13) assign feedback = 39'h400000013A;
else if((index % 61) == 14) assign feedback = 39'h400000013F;
else if((index % 61) == 15) assign feedback = 39'h400000014E;
else if((index % 61) == 16) assign feedback = 39'h4000000155;
else if((index % 61) == 17) assign feedback = 39'h4000000160;
else if((index % 61) == 18) assign feedback = 39'h4000000172;
else if((index % 61) == 19) assign feedback = 39'h4000000199;
else if((index % 61) == 20) assign feedback = 39'h40000001BB;
else if((index % 61) == 21) assign feedback = 39'h40000001CC;
else if((index % 61) == 22) assign feedback = 39'h40000001F9;
else if((index % 61) == 23) assign feedback = 39'h4000000227;
else if((index % 61) == 24) assign feedback = 39'h4000000277;
else if((index % 61) == 25) assign feedback = 39'h40000002A3;
else if((index % 61) == 26) assign feedback = 39'h40000002AC;
else if((index % 61) == 27) assign feedback = 39'h40000002C9;
else if((index % 61) == 28) assign feedback = 39'h40000002D8;
else if((index % 61) == 29) assign feedback = 39'h40000002DD;
else if((index % 61) == 30) assign feedback = 39'h40000002F6;
else if((index % 61) == 31) assign feedback = 39'h4000000313;
else if((index % 61) == 32) assign feedback = 39'h400000031A;
else if((index % 61) == 33) assign feedback = 39'h400000031C;
else if((index % 61) == 34) assign feedback = 39'h4000000323;
else if((index % 61) == 35) assign feedback = 39'h4000000338;
else if((index % 61) == 36) assign feedback = 39'h4000000357;
else if((index % 61) == 37) assign feedback = 39'h4000000361;
else if((index % 61) == 38) assign feedback = 39'h4000000368;
else if((index % 61) == 39) assign feedback = 39'h4000000383;
else if((index % 61) == 40) assign feedback = 39'h4000000391;
else if((index % 61) == 41) assign feedback = 39'h400000039D;
else if((index % 61) == 42) assign feedback = 39'h40000003B5;
else if((index % 61) == 43) assign feedback = 39'h40000003CE;
else if((index % 61) == 44) assign feedback = 39'h40000003D0;
else if((index % 61) == 45) assign feedback = 39'h40000003EF;
else if((index % 61) == 46) assign feedback = 39'h40000003F2;
else if((index % 61) == 47) assign feedback = 39'h400000042E;
else if((index % 61) == 48) assign feedback = 39'h4000000441;
else if((index % 61) == 49) assign feedback = 39'h4000000459;
else if((index % 61) == 50) assign feedback = 39'h400000046A;
else if((index % 61) == 51) assign feedback = 39'h400000048B;
else if((index % 61) == 52) assign feedback = 39'h40000004A5;
else if((index % 61) == 53) assign feedback = 39'h40000004D2;
else if((index % 61) == 54) assign feedback = 39'h40000004E4;
else if((index % 61) == 55) assign feedback = 39'h40000004E8;
else if((index % 61) == 56) assign feedback = 39'h40000004F6;
else if((index % 61) == 57) assign feedback = 39'h4000000502;
else if((index % 61) == 58) assign feedback = 39'h400000050D;
else if((index % 61) == 59) assign feedback = 39'h400000051C;
else if((index % 61) == 60) assign feedback = 39'h4000000523;
end
endgenerate
endmodule
|
// $Id: c_fbmult.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic feedback multiplier for multi-input LFSRs
//==============================================================================
module c_fbmult
(feedback, complete, data_in, data_out);
`include "c_constants.v"
// width of register (must be greater than one)
parameter width = 32;
// how many iterations to perform at once
parameter iterations = 1;
// feedback polynomial(s)
input [0:width-1] feedback;
// include all-zeros state in state sequence
input complete;
// data input
input [0:width-1] data_in;
// data output
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire [0:width-1] feedback_seeds;
wire [0:width*width-1] iter_matrix_noshift_transposed;
generate
if(width == 1)
begin
assign feedback_seeds = complete ^ data_in;
assign iter_matrix_noshift_transposed = feedback;
end
else
begin
assign feedback_seeds[0:(width-1)-1] = data_in[0:(width-1)-1];
assign feedback_seeds[width-1]
= (~|data_in[0:(width-1)-1] & complete) ^ data_in[width-1];
assign iter_matrix_noshift_transposed
= {{((width-1)*width){1'b0}}, feedback};
end
endgenerate
wire [0:width*width-1] iter_matrix_noshift;
c_interleave
#(.width(width*width),
.num_blocks(width))
iter_matrix_noshift_intl
(.data_in(iter_matrix_noshift_transposed),
.data_out(iter_matrix_noshift));
wire [0:width*width-1] initial_matrix;
wire [0:(iterations+1)*width*width-1] matrices;
assign matrices[0:width*width-1] = initial_matrix;
wire [0:width*width-1] feedback_matrix;
assign feedback_matrix
= matrices[iterations*width*width:(iterations+1)*width*width-1];
wire [0:width*width-1] iter_matrix;
wire [0:width*width-1] feedback_matrix_noshift;
generate
genvar row;
for(row = 0; row < width; row = row + 1)
begin:rows
genvar col;
for(col = 0; col < width; col = col + 1)
begin:cols
wire invert;
assign invert = (row == (col + 1));
assign iter_matrix[row*width+col]
= iter_matrix_noshift[row*width+col] ^ invert;
assign feedback_matrix_noshift[row*width+col]
= feedback_matrix[row*width+col] ^ invert;
wire sethi;
assign sethi = (row == col);
assign initial_matrix[row*width+col] = sethi;
end
end
genvar iter;
for(iter = 0; iter < iterations; iter = iter+1)
begin:iters
wire [0:width*width-1] in_matrix;
assign in_matrix = matrices[iter*width*width:(iter+1)*width*width-1];
wire [0:width*width-1] out_matrix;
c_mat_mult
#(.dim1_width(width),
.dim2_width(width),
.dim3_width(width))
out_matrix_mmult
(.input_a(iter_matrix),
.input_b(in_matrix),
.result(out_matrix));
assign matrices[(iter+1)*width*width:(iter+2)*width*width-1]
= out_matrix;
end
endgenerate
wire [0:width-1] feedback_sum;
c_mat_mult
#(.dim1_width(width),
.dim2_width(width),
.dim3_width(1))
feedback_sum_mmult
(.input_a(feedback_matrix_noshift),
.input_b(feedback_seeds),
.result(feedback_sum));
assign data_out = feedback_sum;
endmodule
|
// $Id: c_fifo.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic FIFO buffer built from registers
//==============================================================================
module c_fifo
(clk, reset, push_active, pop_active, push, pop, push_data, pop_data,
almost_empty, empty, almost_full, full, errors);
`include "c_functions.v"
`include "c_constants.v"
// number of entries in FIFO
parameter depth = 4;
// width of each entry
parameter width = 8;
// select implementation variant for register file
parameter regfile_type = `REGFILE_TYPE_FF_2D;
// if enabled, feed through inputs to outputs when FIFO is empty
parameter enable_bypass = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
// width required for read/write address
localparam addr_width = clogb(depth);
input clk;
input reset;
input push_active;
input pop_active;
// write (add) an element
input push;
// read (remove) an element
input pop;
// data to write to FIFO
input [0:width-1] push_data;
// data being read from FIFO
output [0:width-1] pop_data;
wire [0:width-1] pop_data;
// buffer nearly empty (1 used slot remaining) indication
output almost_empty;
wire almost_empty;
// buffer empty indication
output empty;
wire empty;
// buffer almost full (1 unused slot remaining) indication
output almost_full;
wire almost_full;
// buffer full indication
output full;
wire full;
// internal error condition detected
output [0:1] errors;
wire [0:1] errors;
wire error_underflow;
wire error_overflow;
generate
if(depth == 0)
begin
if(enable_bypass)
assign pop_data = push_data;
assign almost_empty = 1'b0;
assign empty = 1'b1;
assign almost_full = 1'b0;
assign full = 1'b1;
assign error_underflow = pop;
assign error_overflow = push;
assign errors[0] = error_underflow;
assign errors[1] = error_overflow;
end
else if(depth == 1)
begin
wire [0:width-1] data_s, data_q;
assign data_s = push ? push_data : data_q;
c_dff
#(.width(width),
.reset_type(reset_type))
dataq
(.clk(clk),
.reset(1'b0),
.active(push_active),
.d(data_s),
.q(data_q));
if(enable_bypass)
assign pop_data = empty ? push_data : data_q;
else
assign pop_data = data_q;
wire empty_active;
assign empty_active = push_active | pop_active;
wire empty_s, empty_q;
assign empty_s = (empty_q | (pop & ~push)) & ~(push & ~pop);
c_dff
#(.width(1),
.reset_value(1'b1),
.reset_type(reset_type))
emptyq
(.clk(clk),
.reset(reset),
.active(empty_active),
.d(empty_s),
.q(empty_q));
assign almost_empty = ~empty_q;
assign empty = empty_q;
assign almost_full = empty_q;
assign full = ~empty_q;
wire error_underflow;
assign error_underflow = empty_q & pop & ~push;
wire error_overflow;
assign error_overflow = ~empty_q & push & ~pop;
assign errors[0] = error_underflow;
assign errors[1] = error_overflow;
end
else if(depth > 1)
begin
wire [0:addr_width-1] push_addr;
wire [0:addr_width-1] pop_addr;
c_fifo_ctrl
#(.depth(depth),
.reset_type(reset_type))
ctrl
(.clk(clk),
.reset(reset),
.push_active(push_active),
.pop_active(pop_active),
.push(push),
.pop(pop),
.push_addr(push_addr),
.pop_addr(pop_addr),
.almost_empty(almost_empty),
.empty(empty),
.almost_full(almost_full),
.full(full),
.errors(errors));
assign error_underflow = errors[0];
assign error_overflow = errors[1];
wire [0:width-1] rf_data;
c_regfile
#(.depth(depth),
.width(width),
.regfile_type(regfile_type))
rf
(.clk(clk),
.write_active(push_active),
.write_enable(push),
.write_address(push_addr),
.write_data(push_data),
.read_active(pop_active),
.read_address(pop_addr),
.read_data(rf_data));
if(enable_bypass)
assign pop_data = empty ? push_data : rf_data;
else
assign pop_data = rf_data;
end
endgenerate
endmodule
|
// $Id: c_fifo_ctrl.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// simple FIFO controller
//==============================================================================
module c_fifo_ctrl
(clk, reset, push_active, pop_active, push, pop, push_addr, pop_addr,
almost_empty, empty, almost_full, full, errors);
`include "c_functions.v"
`include "c_constants.v"
// number of entries in FIFO
parameter depth = 8;
// add additional address bits
parameter extra_addr_width = 0;
// address width
localparam addr_width = clogb(depth) + extra_addr_width;
// starting address (i.e., address of leftmost entry)
parameter offset = 0;
// minimum (leftmost) address
localparam [0:addr_width-1] min_value = offset;
// maximum (rightmost) address
localparam [0:addr_width-1] max_value = offset + depth - 1;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input push_active;
input pop_active;
// write (add) an element
input push;
// read (remove) an element
input pop;
// address to write current input element to
output [0:addr_width-1] push_addr;
wire [0:addr_width-1] push_addr;
// address to read current output element from
output [0:addr_width-1] pop_addr;
wire [0:addr_width-1] pop_addr;
// buffer nearly empty (1 used slot remaining) indication
output almost_empty;
wire almost_empty;
// buffer empty indication
output empty;
wire empty;
// buffer almost full (1 unused slot remaining) indication
output almost_full;
wire almost_full;
// buffer full indication
output full;
wire full;
// internal error condition detected
output [0:1] errors;
wire [0:1] errors;
wire active;
assign active = push_active | pop_active;
generate
if(depth == 1)
begin
assign push_addr = min_value;
assign pop_addr = min_value;
wire empty_s, empty_q;
assign empty_s = empty_q ? (~push | pop) : (~push & pop);
c_dff
#(.width(1),
.reset_value(1'b1),
.reset_type(reset_type))
emptyq
(.clk(clk),
.reset(reset),
.active(active),
.d(empty_s),
.q(empty_q));
assign almost_empty = ~empty_q;
assign empty = empty_q;
assign almost_full = empty_q;
assign full = ~empty_q;
end
else if(depth > 1)
begin
wire [0:addr_width-1] push_addr_q;
wire [0:addr_width-1] push_addr_next;
c_incr
#(.width(addr_width),
.min_value(min_value),
.max_value(max_value))
push_addr_incr
(.data_in(push_addr_q),
.data_out(push_addr_next));
wire [0:addr_width-1] push_addr_prev;
c_decr
#(.width(addr_width),
.min_value(min_value),
.max_value(max_value))
push_addr_decr
(.data_in(push_addr_q),
.data_out(push_addr_prev));
wire [0:addr_width-1] push_addr_s;
assign push_addr_s = push ? push_addr_next : push_addr_q;
c_dff
#(.width(addr_width),
.reset_value(min_value),
.reset_type(reset_type))
push_addrq
(.clk(clk),
.reset(reset),
.active(push_active),
.d(push_addr_s),
.q(push_addr_q));
assign push_addr = push_addr_q;
wire [0:addr_width-1] pop_addr_q;
wire [0:addr_width-1] pop_addr_next;
c_incr
#(.width(addr_width),
.min_value(min_value),
.max_value(max_value))
pop_addr_incr
(.data_in(pop_addr_q),
.data_out(pop_addr_next));
wire [0:addr_width-1] pop_addr_prev;
c_decr
#(.width(addr_width),
.min_value(min_value),
.max_value(max_value))
pop_addr_decr
(.data_in(pop_addr_q),
.data_out(pop_addr_prev));
wire [0:addr_width-1] pop_addr_s;
assign pop_addr_s = pop ? pop_addr_next : pop_addr_q;
c_dff
#(.width(addr_width),
.reset_value(min_value),
.reset_type(reset_type))
pop_addrq
(.clk(clk),
.reset(reset),
.active(pop_active),
.d(pop_addr_s),
.q(pop_addr_q));
assign pop_addr = pop_addr_q;
wire equal;
assign equal = (push_addr_q == pop_addr_q);
wire next_almost_empty;
assign next_almost_empty = (push_addr_prev == pop_addr_next);
wire almost_empty_s, almost_empty_q;
assign almost_empty_s = (almost_empty & ~(push ^ pop)) |
(next_almost_empty & (~push & pop)) |
(equal & (push & ~pop));
c_dff
#(.width(1),
.reset_type(reset_type))
almost_emptyq
(.clk(clk),
.reset(reset),
.active(active),
.d(almost_empty_s),
.q(almost_empty_q));
assign almost_empty = almost_empty_q;
wire next_empty;
assign next_empty = (push_addr_q == pop_addr_next);
wire empty_s, empty_q;
assign empty_s = (empty & ~(push & ~pop)) |
(next_empty & (~push & pop));
c_dff
#(.width(1),
.reset_value(1'b1),
.reset_type(reset_type))
emptyq
(.clk(clk),
.reset(reset),
.active(active),
.d(empty_s),
.q(empty_q));
assign empty = empty_q;
if(depth == 2)
assign almost_full = almost_empty;
else if(depth > 2)
begin
wire next_almost_full;
assign next_almost_full = (push_addr_next == pop_addr_prev);
wire almost_full_s, almost_full_q;
assign almost_full_s = (almost_full & ~(push ^ pop)) |
(next_almost_full & (push & ~pop)) |
(equal & (~push & pop));
c_dff
#(.width(1),
.reset_type(reset_type))
almost_fullq
(.clk(clk),
.reset(reset),
.active(active),
.d(almost_full_s),
.q(almost_full_q));
assign almost_full = almost_full_q;
end
wire next_full;
assign next_full = (push_addr_next == pop_addr_q);
wire full_s, full_q;
assign full_s = (full & ~(~push & pop)) |
(next_full & (push & ~pop));
c_dff
#(.width(1),
.reset_type(reset_type))
fullq
(.clk(clk),
.reset(reset),
.active(active),
.d(full_s),
.q(full_q));
assign full = full_q;
end
// synopsys translate_off
else
begin
initial
begin
$display({"ERROR: FIFO controller module %m requires a depth ",
"of at least one entry."});
$stop;
end
end
// synopsys translate_on
endgenerate
wire error_underflow;
assign error_underflow = empty & ~push & pop;
wire error_overflow;
assign error_overflow = full & push & ~pop;
// synopsys translate_off
always @(posedge clk)
begin
if(error_underflow)
$display("ERROR: FIFO underflow in module %m.");
if(error_overflow)
$display("ERROR: FIFO overflow in module %m.");
end
// synopsys translate_on
assign errors[0] = error_underflow;
assign errors[1] = error_overflow;
endmodule
|
// $Id: c_fifo_tracker.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// module for tracking state of a FIFO
//==============================================================================
module c_fifo_tracker
(clk, reset, active, push, pop, almost_empty, empty, almost_full, full,
free, errors);
`include "c_functions.v"
`include "c_constants.v"
// total number of credits available
parameter depth = 8;
parameter reset_type = `RESET_TYPE_ASYNC;
// width required to represent full range of credit count (0..depth)
localparam free_width = clogb(depth+1);
input clk;
input reset;
input active;
// add an entry
input push;
// remove an entry
input pop;
// all but one entries free
output almost_empty;
wire almost_empty;
// all entries free
output empty;
wire empty;
// all but one entries occupied
output almost_full;
wire almost_full;
// all entries occupied
output full;
wire full;
// number of free entries
output [0:free_width-1] free;
wire [0:free_width-1] free;
// internal error condition encountered
output [0:1] errors;
wire [0:1] errors;
wire [0:free_width-1] free_s, free_q;
c_dff
#(.width(free_width),
.reset_value(depth),
.reset_type(reset_type))
freeq
(.clk(clk),
.reset(reset),
.active(active),
.d(free_s),
.q(free_q));
assign free = free_q;
wire error_underflow;
assign error_underflow = empty & ~push & pop;
wire error_overflow;
assign error_overflow = full & push & ~pop;
generate
if(depth == 1)
begin
assign free_s = free_q ? (~push | pop) : (~push & pop);
assign almost_empty = ~free_q;
assign empty = free_q;
assign almost_full = free_q;
assign full = ~free_q;
end
else if(depth > 1)
begin
wire decr_push;
assign decr_push = ~pop;
wire [0:free_width-1] free_push;
assign free_push = free_q - decr_push;
wire incr_nopush;
assign incr_nopush = pop;
wire [0:free_width-1] free_nopush;
assign free_nopush = free_q + incr_nopush;
assign free_s = push ? free_push : free_nopush;
wire free_max;
assign free_max = (free_q == depth);
wire next_almost_empty;
assign next_almost_empty = (free_q == (depth - 2));
wire almost_empty_s, almost_empty_q;
assign almost_empty_s = (almost_empty & ~(push ^ pop)) |
(next_almost_empty & (~push & pop)) |
(free_max & (push & ~pop));
c_dff
#(.width(1),
.reset_type(reset_type))
almost_emptyq
(.clk(clk),
.reset(reset),
.active(active),
.d(almost_empty_s),
.q(almost_empty_q));
assign almost_empty = almost_empty_q;
wire next_empty;
assign next_empty = (free_q == (depth - 1));
wire empty_s, empty_q;
assign empty_s = (empty & ~(push & ~pop)) |
(next_empty & (~push & pop));
c_dff
#(.width(1),
.reset_value(1'b1),
.reset_type(reset_type))
emptyq
(.clk(clk),
.reset(reset),
.active(active),
.d(empty_s),
.q(empty_q));
assign empty = empty_q;
wire free_zero;
assign free_zero = ~|free_q;
if(depth == 2)
assign almost_full = almost_empty;
else if(depth > 2)
begin
wire next_almost_full;
assign next_almost_full = (free_q == 2);
wire almost_full_s, almost_full_q;
assign almost_full_s = (almost_full & ~(push ^ pop)) |
(next_almost_full & (push & ~pop)) |
(free_zero & (~push & pop));
c_dff
#(.width(1),
.reset_type(reset_type))
almost_fullq
(.clk(clk),
.reset(reset),
.active(active),
.d(almost_full_s),
.q(almost_full_q));
assign almost_full = almost_full_q;
end
wire next_full;
assign next_full = (free_q == 1);
wire full_s, full_q;
assign full_s = (full & ~(~push & pop)) |
(next_full & (push & ~pop));
c_dff
#(.width(1),
.reset_type(reset_type))
fullq
(.clk(clk),
.reset(reset),
.active(active),
.d(full_s),
.q(full_q));
assign full = full_q;
end
// synopsys translate_off
else
begin
initial
begin
$display({"ERROR: FIFO tracker module %m requires a depth of at ",
"least one entry."});
$stop;
end
end
// synopsys translate_on
endgenerate
assign errors = {error_underflow, error_overflow};
endmodule
|
// $Id: c_gather.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// module for extracting a set of bits from an input word (result is
// concatenation of these bits)
//==============================================================================
module c_gather
(data_in, data_out);
// width of input word
parameter in_width = 32;
function integer pop_count(input [0:in_width-1] argument);
integer i;
begin
pop_count = 0;
for(i = 0; i < in_width; i = i + 1)
pop_count = pop_count + argument[i];
end
endfunction
// mask specifying which bits to extract
parameter [0:in_width-1] mask = {in_width{1'b1}};
// width of result
localparam out_width = pop_count(mask);
// input word
input [0:in_width-1] data_in;
// result
output [0:out_width-1] data_out;
reg [0:out_width-1] data_out;
integer idx1, idx2;
always @(data_in)
begin
idx2 = 0;
for(idx1 = 0; idx1 < in_width; idx1 = idx1 + 1)
if(mask[idx1] == 1'b1)
begin
data_out[idx2] = data_in[idx1];
idx2 = idx2 + 1;
end
end
endmodule
|
// $Id: c_incr.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic modulo incrementer (i.e., incrementer with wraparound)
//==============================================================================
module c_incr
(data_in, data_out);
`include "c_functions.v"
parameter width = 3;
parameter [0:width-1] min_value = 0;
parameter [0:width-1] max_value = (1 << width) - 1;
localparam num_values = max_value - min_value + 1;
localparam cwidth = clogb(num_values);
// operand inputs
input [0:width-1] data_in;
// sum output
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire carry;
assign carry = &data_in[(width-cwidth):width-1];
wire wrap;
assign wrap = (data_in[(width-cwidth):width-1] ==
max_value[(width-cwidth):width-1]);
generate
if((1 << cwidth) == num_values)
begin
// if the range is a power of two, we can take advantage of natural
// wraparound for the LSBs
assign data_out[(width-cwidth):width-1]
= data_in[(width-cwidth):width-1] + 1'b1;
end
else
begin
// if the range is not a power of two, we need to implement
// explicit wraparound
assign data_out[(width-cwidth):width-1]
= wrap ?
min_value[(width-cwidth):width-1] :
(data_in[(width-cwidth):width-1] + 1'b1);
end
if(width > cwidth)
begin
if(min_value[0:(width-cwidth)-1] == max_value[0:(width-cwidth)-1])
begin
// if the MSBs are identical for the first and last value, we
// never need to change them
assign data_out[0:(width-cwidth)-1]
= data_in[0:(width-cwidth)-1];
end
else
begin
// if the first and last value have differing MSBs, we need to
// adjust them whenever either the LSBs overflow or wraparound
// occurs
assign data_out[0:(width-cwidth)-1]
= data_in[0:(width-cwidth)-1] + carry - wrap;
end
end
endgenerate
endmodule
|
// $Id: c_interleave.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// interleave a given number of blocks of bits
// (a0 a1 a1 b0 b1 b2 c0 c1 c2) -> (a0 b0 c0 a1 b1 c1 a2 b2 c2)
//==============================================================================
module c_interleave
(data_in, data_out);
// input data width
parameter width = 8;
// number of blocks in input data
parameter num_blocks = 2;
// width of each block
localparam step = width / num_blocks;
// vector of input data
input [0:width-1] data_in;
// vector of output data
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < step; i = i + 1)
begin:blocks
genvar j;
for(j = 0; j < num_blocks; j = j + 1)
begin:bits
assign data_out[i*num_blocks+j] = data_in[i+j*step];
end
end
endgenerate
endmodule
|
// $Id: c_lfsr.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic multi-input linear feedback shift register register
//==============================================================================
module c_lfsr
(clk, reset, active, load, run, feedback, complete, d, q);
`include "c_constants.v"
// width of register (must be greater than one)
parameter width = 32;
// offset (left index) of register
parameter offset = 0;
// initial state
parameter [offset:(offset+width)-1] reset_value = {width{1'b1}};
// how many iterations to perform at once
parameter iterations = 1;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// load data input into signature register
input load;
// activate signature updates
input run;
// feedback polynomial(s)
input [0:width-1] feedback;
// include all-zeros state in state sequence
input complete;
// data input
input [offset:(offset+width)-1] d;
// data output
output [offset:(offset+width)-1] q;
wire [offset:(offset+width)-1] q;
wire [offset:(offset+width)-1] state_q;
wire [0:width-1] feedback_sum;
c_fbmult
#(.width(width),
.iterations(iterations))
fbmult
(.feedback(feedback),
.complete(complete),
.data_in(state_q),
.data_out(feedback_sum));
wire [offset:(offset+width)-1] feedback_value;
assign feedback_value = {width{~load}} & feedback_sum;
wire [offset:(offset+width)-1] toggle_value;
assign toggle_value = feedback_value ^ d;
wire [offset:(offset+width)-1] base_value;
generate
if(width == 1)
begin
assign base_value = 1'b0;
end
else
begin
assign base_value
= {1'b0, {(width-1){~load}} & state_q[offset:(offset+width-1)-1]};
end
endgenerate
wire [offset:(offset+width)-1] state_s;
assign state_s = (load | run) ? (base_value ^ toggle_value) : state_q;
c_dff
#(.width(width),
.offset(offset),
.reset_type(reset_type),
.reset_value(reset_value))
stateq
(.clk(clk),
.reset(reset),
.active(active),
.d(state_s),
.q(state_q));
assign q = state_q;
endmodule
|
// $Id: c_lod.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// leading one detector
//==============================================================================
module c_lod
(data_in, data_out);
// number of input ports
parameter width = 32;
// number of priority levels
parameter num_priorities = 1;
// vector of requests
input [0:num_priorities*width-1] data_in;
// vector of grants
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire [0:num_priorities-1] enable_prio;
assign enable_prio[0] = 1'b1;
wire [0:num_priorities*width-1] data_out_by_prio;
genvar prio;
generate
for(prio = 0; prio < num_priorities; prio = prio + 1)
begin:prios
wire [0:width-1] prio_data_in;
assign prio_data_in = data_in[prio*width:(prio+1)*width-1];
if(prio < (num_priorities - 1))
assign enable_prio[prio+1] = enable_prio[prio] & ~|prio_data_in;
wire [0:width-1] prio_data_out;
if(width == 1)
assign prio_data_out = prio_data_in;
else
begin
// To find the first non-zero bit from the left, we must
// reverse the input and output vectors.
wire [0:width-1] prio_data_in_rev;
c_reverse
#(.width(width))
prio_data_in_rev_revr
(.data_in(prio_data_in),
.data_out(prio_data_in_rev));
wire [0:width-1] prio_data_out_rev;
assign prio_data_out_rev = prio_data_in_rev & -prio_data_in_rev;
c_reverse
#(.width(width))
prio_data_out_revr
(.data_in(prio_data_out_rev),
.data_out(prio_data_out));
end
assign data_out_by_prio[prio*width:(prio+1)*width-1] = prio_data_out;
end
endgenerate
c_select_mofn
#(.num_ports(num_priorities),
.width(width))
data_out_sel
(.select(enable_prio),
.data_in(data_out_by_prio),
.data_out(data_out));
endmodule
|
// $Id: c_matrix_arbiter.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// matrix arbiter
//==============================================================================
module c_matrix_arbiter
(clk, reset, active, req, gnt, update);
`include "c_constants.v"
// number of inputs ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 1;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// request vector
input [0:num_priorities*num_ports-1] req;
// grant vector
output [0:num_priorities*num_ports-1] gnt;
wire [0:num_priorities*num_ports-1] gnt;
// update port priorities
input update;
generate
if(num_ports == 1)
begin
c_lod
#(.width(num_priorities))
gnt_lod
(.data_in(req),
.data_out(gnt));
end
else if(num_ports > 1)
begin
wire [0:num_priorities-1] enable_prio;
assign enable_prio[0] = 1'b1;
genvar prio;
for(prio = 0; prio < (num_priorities - 1); prio = prio + 1)
begin:prios
assign enable_prio[prio+1]
= enable_prio[prio] &
~|req[prio*num_ports:(prio+1)*num_ports-1];
end
wire [0:num_ports-1] gnt_any;
c_select_mofn
#(.num_ports(num_priorities),
.width(num_ports))
gnt_all_sel
(.select(enable_prio),
.data_in(gnt),
.data_out(gnt_any));
// port priority matrix
wire [0:num_ports*num_ports-1] state;
genvar row;
for(row = 0; row < num_ports; row = row + 1)
begin:rows
genvar prio;
for(prio = 0; prio < num_priorities; prio = prio + 1)
begin:prios
// grant requests if we have precedence over all other
// requestors
assign gnt[prio*num_ports+row]
= req[prio*num_ports+row] &
(&(state[row*num_ports:(row+1)*num_ports-1] |
~req[prio*num_ports:(prio+1)*num_ports-1])) &
enable_prio[prio];
end
genvar col;
for(col = 0; col < num_ports; col = col + 1)
begin:cols
// lower triangle has inverted values of transposed upper
// triangle
if(col < row)
assign state[row*num_ports+col]
= ~state[col*num_ports+row];
// diagonal has all ones
else if(col == row)
assign state[row*num_ports+col] = 1'b1;
// upper triangle has actual registers
else if(col > row)
begin
wire state_s, state_q;
assign state_s
= update ?
((state_q | gnt_any[col]) & ~gnt_any[row]) :
state_q;
c_dff
#(.width(1),
.reset_type(reset_type),
.reset_value(1'b1))
stateq
(.clk(clk),
.reset(reset),
.active(active),
.d(state_s),
.q(state_q));
assign state[row*num_ports+col] = state_q;
end
end
end
end
endgenerate
endmodule
|
// $Id: c_mat_mult.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// matrix multiplication
//==============================================================================
module c_mat_mult
(input_a, input_b, result);
`include "c_constants.v"
// matrix dimensions
parameter dim1_width = 1;
parameter dim2_width = 1;
parameter dim3_width = 1;
// multiplication operator
parameter prod_op = `BINARY_OP_AND;
// addition operator
parameter sum_op = `BINARY_OP_XOR;
// first input matrix
input [0:dim1_width*dim2_width-1] input_a;
// second input matrix
input [0:dim2_width*dim3_width-1] input_b;
output [0:dim1_width*dim3_width-1] result;
wire [0:dim1_width*dim3_width-1] result;
generate
genvar row;
for(row = 0; row < dim1_width; row = row + 1)
begin:rows
genvar col;
for(col = 0; col < dim3_width; col = col + 1)
begin:cols
wire [0:dim2_width-1] products;
genvar idx;
for(idx = 0; idx < dim2_width; idx = idx + 1)
begin:idxs
c_binary_op
#(.num_ports(2),
.width(1),
.op(prod_op))
prod
(.data_in({input_a[row*dim2_width+idx],
input_b[idx*dim3_width+col]}),
.data_out(products[idx]));
end
c_binary_op
#(.num_ports(dim2_width),
.width(1),
.op(sum_op))
sum
(.data_in(products),
.data_out(result[row*dim3_width+col]));
end
end
endgenerate
endmodule
|
// $Id: c_multi_hot_det.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic multi-hot detect logic
//==============================================================================
module c_multi_hot_det
(data, multi_hot);
`include "c_constants.v"
`include "c_functions.v"
// width of input vector
parameter width = 8;
// number of reduction levels required
localparam num_levels = clogb(width);
// smallest power-of-two width that is greater than or equal to width
localparam ext_width = (1 << num_levels);
// input data
input [0:width-1] data;
// one-hot indicator
output multi_hot;
wire multi_hot;
genvar level;
generate
if(width == 1)
begin
// a single wire is never multi-hot!
assign multi_hot = 1'b0;
end
else if(width > 1)
begin
// connections between levels
wire [0:(2*ext_width-1)-1] connections;
// for first stage input, zero-extend data to power-of-two width
assign connections[0:width-1] = data;
if(ext_width > width)
assign connections[width:ext_width-1] = {(ext_width-width){1'b0}};
// bit for each level indicating whether multiple bits are set
wire [0:num_levels-1] level_multi_hot;
for(level = 0; level < num_levels; level = level + 1)
begin:levels
wire [0:(ext_width/(1 << level))-1] data;
assign data
= connections[((2*ext_width)-(2*ext_width/(1 << level))):
((2*ext_width)-(ext_width/(1 << level)))-1];
wire [0:(ext_width/(2 << level))-1] both_set;
wire [0:(ext_width/(2 << level))-1] any_set;
genvar pair;
for(pair = 0; pair < (ext_width/(2 << level)); pair = pair + 1)
begin:pairs
assign both_set[pair] = &data[pair*2:pair*2+1];
assign any_set[pair] = |data[pair*2:pair*2+1];
end
assign level_multi_hot[level] = |both_set;
assign connections[((2*ext_width)-(ext_width/(1 << level))):
((2*ext_width)-(ext_width/(2 << level)))-1]
= any_set;
end
assign multi_hot = |level_multi_hot;
end
endgenerate
endmodule
|
// $Id: c_one_hot_filter.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic one-hot filter logic
//==============================================================================
module c_one_hot_filter
(data_in, data_out);
// width of input vector
parameter width = 8;
// input data
input [0:width-1] data_in;
// output data
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
if(width == 1)
assign data_out = data_in;
else
begin
genvar pos;
for(pos = 0; pos < width; pos = pos + 1)
begin:poss
wire [0:(width-1)-1] others;
if(pos > 0)
assign others[0:pos-1] = data_in[0:pos-1];
if(pos < (width - 1))
assign others[pos:(width-1)-1] = data_in[(pos+1):width-1];
assign data_out[pos] = data_in[pos] & ~|others;
end
end
endgenerate
endmodule
|
// $Id: c_prio_enc.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// priority encoder (port 0 has highest priority)
//==============================================================================
module c_prio_enc
(data_in, data_out);
`include "c_functions.v"
// number of input ports (i.e., decoded width)
parameter num_ports = 8;
localparam width = clogb(num_ports);
// one-hot input data
input [0:num_ports-1] data_in;
// binary encoded output data
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire [0:(width+1)*num_ports-1] masks;
assign masks[0:num_ports-1] = {num_ports{1'b1}};
generate
genvar level;
for(level = 0; level < width; level = level + 1)
begin:levels
wire sel;
wire [0:num_ports-1] mask_in;
assign mask_in = masks[level*num_ports:(level+1)*num_ports-1];
wire [0:num_ports-1] bits;
wire value;
wire [0:num_ports-1] mask_out;
genvar position;
for(position = 0; position < num_ports; position = position + 1)
begin:positions
if(position & (1 << level))
begin
assign bits[position]
= data_in[position] & mask_in[position];
assign mask_out[position]
= mask_in[position] & value;
end
else
begin
assign bits[position] = 1'b0;
assign mask_out[position]
= mask_in[position] & ~value;
end
end
assign value = |bits;
assign data_out[(width-1)-level] = value;
assign mask_out[(level+1)*num_ports:(level+2)*num_ports-1]
= mask_out;
end
endgenerate
endmodule
|
// $Id: c_prio_sel.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// priority select logic
//==============================================================================
module c_prio_sel
(priorities, enable, select);
`include "c_functions.v"
// number of input ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 16;
// width of priority fields
localparam prio_width = clogb(num_priorities);
// priority values
input [0:num_ports*prio_width-1] priorities;
// port enable signals
input [0:num_ports-1] enable;
// vector representing maximum priority ports
output [0:num_ports-1] select;
wire [0:num_ports-1] select;
// for each priority bit, list all ports that have this bit set
wire [0:prio_width*num_ports-1] prio_ports;
c_interleave
#(.width(num_ports*prio_width),
.num_blocks(num_ports))
prio_ports_intl
(.data_in(priorities),
.data_out(prio_ports));
wire [0:(prio_width+1)*num_ports-1] mask;
assign mask[0:num_ports-1] = enable;
generate
genvar i;
for(i = 0; i < prio_width; i = i + 1)
begin:is
wire [0:num_ports-1] mask_in;
assign mask_in = mask[i*num_ports:(i+1)*num_ports-1];
wire [0:num_ports-1] prio;
assign prio = prio_ports[i*num_ports:(i+1)*num_ports-1];
wire [0:num_ports-1] mask_out;
assign mask_out = mask_in & (prio | {num_ports{~|(mask_in & prio)}});
assign mask[(i+1)*num_ports:(i+2)*num_ports-1] = mask_out;
end
endgenerate
assign select = mask[prio_width*num_ports:(prio_width+1)*num_ports-1];
endmodule
|
// $Id: c_regfile.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic register file
//==============================================================================
module c_regfile
(clk, write_active, write_enable, write_address, write_data, read_active,
read_address, read_data);
`include "c_functions.v"
`include "c_constants.v"
// number of entries
parameter depth = 8;
// width of each entry
parameter width = 64;
// number of read ports
parameter num_read_ports = 1;
// select implementation variant
parameter regfile_type = `REGFILE_TYPE_FF_2D;
// width required to swelect an entry
localparam addr_width = clogb(depth);
input clk;
input write_active;
// if high, write to entry selected by write_address
input write_enable;
// entry to be written to
input [0:addr_width-1] write_address;
// data to be written
input [0:width-1] write_data;
input [0:num_read_ports-1] read_active;
// entries to read out
input [0:num_read_ports*addr_width-1] read_address;
// contents of entries selected by read_address
output [0:num_read_ports*width-1] read_data;
wire [0:num_read_ports*width-1] read_data;
wire [0:num_read_ports*width-1] cell_data;
genvar read_port;
generate
case(regfile_type)
`REGFILE_TYPE_FF_2D, `REGFILE_TYPE_LAT_2D:
begin
reg [0:width-1] storage_2d [0:depth-1];
case(regfile_type)
`REGFILE_TYPE_FF_2D:
always @(posedge clk)
if(write_active)
if(write_enable)
storage_2d[write_address] <= write_data;
`REGFILE_TYPE_LAT_2D:
always @(clk, write_active, write_enable, write_address,
write_data)
if(~clk)
if(write_active)
if(write_enable)
storage_2d[write_address] <= write_data;
endcase
for(read_port = 0; read_port < num_read_ports;
read_port = read_port + 1)
begin:read_ports_2d
wire [0:addr_width-1] port_read_address;
assign port_read_address
= read_address[read_port*addr_width:
(read_port+1)*addr_width-1];
wire [0:width-1] port_cell_data;
assign port_cell_data = storage_2d[port_read_address];
assign cell_data[read_port*width:(read_port+1)*width-1]
= port_cell_data;
end
end
`REGFILE_TYPE_FF_1D_MUX, `REGFILE_TYPE_LAT_1D_MUX,
`REGFILE_TYPE_FF_1D_TRISTATE, `REGFILE_TYPE_LAT_1D_TRISTATE:
begin
wire [0:depth*width-1] storage_1d;
genvar level;
for(level = 0; level < depth; level = level + 1)
begin:levels
wire write;
assign write = write_enable && (write_address == level);
reg [0:width-1] storage;
case(regfile_type)
`REGFILE_TYPE_FF_1D_MUX, `REGFILE_TYPE_FF_1D_TRISTATE:
always @(posedge clk)
if(write_active)
if(write)
storage <= write_data;
`REGFILE_TYPE_LAT_1D_MUX, `REGFILE_TYPE_LAT_1D_TRISTATE:
always @(clk, write_active, write, write_data)
if(~clk)
if(write_active)
if(write)
storage <= write_data;
endcase
assign storage_1d[level*width:(level+1)*width-1] = storage;
end
for(read_port = 0; read_port < num_read_ports;
read_port = read_port + 1)
begin:read_ports_1d
wire [0:addr_width-1] port_read_address;
assign port_read_address
= read_address[read_port*addr_width:
(read_port+1)*addr_width-1];
wire [0:width-1] port_cell_data;
case(regfile_type)
`REGFILE_TYPE_FF_1D_TRISTATE, `REGFILE_TYPE_LAT_1D_TRISTATE:
begin
wire [0:depth-1] port_read_sel;
c_decode
#(.num_ports(depth))
port_read_sel_dec
(.data_in(port_read_address),
.data_out(port_read_sel));
c_select_1ofn
#(.num_ports(depth),
.width(width))
port_cell_data_sel
(.select(port_read_sel),
.data_in(storage_1d),
.data_out(port_cell_data));
end
`REGFILE_TYPE_FF_1D_MUX, `REGFILE_TYPE_LAT_1D_MUX:
begin
assign port_cell_data
= storage_1d[port_read_address*width +: width];
end
endcase
assign cell_data[read_port*width:(read_port+1)*width-1]
= port_cell_data;
end
end
`REGFILE_TYPE_FF_DW, `REGFILE_TYPE_LAT_DW:
begin
wire write_enable_b;
assign write_enable_b = ~write_enable;
case(num_read_ports)
1:
begin
case(regfile_type)
`REGFILE_TYPE_FF_DW:
begin
DW_ram_r_w_s_dff
#(.data_width(width),
.depth(depth),
.rst_mode(1))
DW_rf_dff
(.clk(clk),
.rst_n(1'b1),
.cs_n(write_enable_b),
.wr_n(write_enable_b),
.rd_addr(read_address),
.wr_addr(write_address),
.data_in(write_data),
.data_out(cell_data));
end
`REGFILE_TYPE_LAT_DW:
begin
DW_ram_r_w_s_lat
#(.data_width(width),
.depth(depth))
DW_rf_lat
(.clk(clk),
.cs_n(write_enable_b),
.wr_n(write_enable_b),
.rd_addr(read_address),
.wr_addr(write_address),
.data_in(write_data),
.data_out(cell_data));
end
endcase
end
2:
begin
wire [0:addr_width-1] read_address_1;
assign read_address_1
= read_address[0:addr_width-1];
wire [0:addr_width-1] read_address_2;
assign read_address_2
= read_address[addr_width:2*addr_width-1];
wire [0:width-1] cell_data_1;
wire [0:width-1] cell_data_2;
case(regfile_type)
`REGFILE_TYPE_FF_DW:
begin
DW_ram_r_w_s_dff
#(.data_width(width),
.depth(depth),
.rst_mode(1))
DW_rf_dff
(.clk(clk),
.rst_n(1'b1),
.cs_n(write_enable_b),
.wr_n(write_enable_b),
.rd1_addr(read_address_1),
.rd2_addr(read_address_2),
.wr_addr(write_address),
.data_in(write_data),
.data_rd1_out(cell_data_1),
.data_rd2_out(cell_data_2));
end
`REGFILE_TYPE_LAT_DW:
begin
DW_ram_r_w_s_lat
#(.data_width(width),
.depth(depth))
DW_rf_lat
(.clk(clk),
.cs_n(write_enable_b),
.wr_n(write_enable_b),
.rd1_addr(read_address_1),
.rd2_addr(read_address_2),
.wr_addr(write_address),
.data_in(write_data),
.data_rd1_out(cell_data_1),
.data_rd2_out(cell_data_2));
end
endcase
assign cell_data = {cell_data_1, cell_data_2};
end
default:
begin
// synopsys translate_off
initial
begin
$display({"ERROR: Register file %m does not support ",
"DesignWare register file models with %d ",
"read ports."}, num_read_ports);
$stop;
end
// synopsys translate_on
end
endcase
end
endcase
for(read_port = 0; read_port < num_read_ports; read_port = read_port + 1)
begin:read_ports
wire [0:width-1] port_cell_data;
assign port_cell_data
= cell_data[read_port*width:(read_port+1)*width-1];
wire [0:width-1] port_read_data;
case(regfile_type)
`REGFILE_TYPE_FF_2D, `REGFILE_TYPE_FF_1D_TRISTATE,
`REGFILE_TYPE_FF_1D_MUX, `REGFILE_TYPE_FF_DW:
begin
assign port_read_data = port_cell_data;
end
`REGFILE_TYPE_LAT_2D, `REGFILE_TYPE_LAT_1D_TRISTATE,
`REGFILE_TYPE_LAT_1D_MUX, `REGFILE_TYPE_LAT_DW:
begin
wire port_read_active;
assign port_read_active = read_active[read_port];
reg [0:width-1] port_buffered_data;
always @(clk, read_active, port_cell_data)
if(clk)
if(port_read_active)
port_buffered_data <= port_cell_data;
assign port_read_data = port_buffered_data;
end
endcase
assign read_data[read_port*width:(read_port+1)*width-1]
= port_read_data;
end
//----------------------------------------------------------------------
// check parameter validity
//----------------------------------------------------------------------
// synopsys translate_off
if(depth < 2)
begin
initial
begin
$display({"ERROR: The register file module requires a depth ",
"of two or more entries."});
$stop;
end
end
// synopsys translate_on
endgenerate
endmodule
|
// $Id: c_reverse.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// module for reversing a set of bits
//==============================================================================
module c_reverse
(data_in, data_out);
// width of input word
parameter width = 32;
// input word
input [0:width-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < width; i = i + 1)
begin:connect
// reverse inputs data
assign data_out[i] = data_in[(width-1)-i];
end
endgenerate
endmodule
|
// $Id: c_rotate.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// rotate bit vector by given amount
//==============================================================================
module c_rotator
(amount, data_in, data_out);
`include "c_functions.v"
`include "c_constants.v"
// width of input data
parameter width = 8;
// direction in which to rotate
parameter rotate_dir = `ROTATE_DIR_LEFT;
// width of rotation amount
localparam amount_width = clogb(width);
// input data
input [0:width-1] data_in;
// result
input [0:amount_width-1] amount;
// amount by which to rotate
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire [0:(2*width-1)-1] data_dup;
wire [0:(2*width-1)-1] data_rot;
generate
case (rotate_dir)
`ROTATE_DIR_LEFT:
begin
assign data_dup = {data_in, data_in[0:(width-1)-1]};
assign data_rot = data_dup << amount;
assign data_out = data_rot[0:width-1];
end
`ROTATE_DIR_RIGHT:
begin
assign data_dup = {data_in[1:width-1], data_in};
assign data_rot = data_dup >> amount;
assign data_out = data_rot[width-1:(2*width-1)-1];
end
endcase
endgenerate
endmodule
|
// $Id: c_rr_arbiter.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// round-robin arbiter
//==============================================================================
module c_rr_arbiter
(clk, reset, active, req, gnt, update);
`include "c_constants.v"
// number of input ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 1;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// vector of requests
input [0:num_priorities*num_ports-1] req;
// vector of grants
output [0:num_priorities*num_ports-1] gnt;
wire [0:num_priorities*num_ports-1] gnt;
// update port priorities
input update;
generate
if(num_ports == 1)
begin
c_lod
#(.width(num_priorities))
gnt_lod
(.data_in(req),
.data_out(gnt));
end
else if(num_ports > 1)
begin
wire [0:num_ports-1] state;
wire [0:num_priorities-1] enable_prio;
assign enable_prio[0] = 1'b1;
wire [0:num_priorities*num_ports-1] next_state_by_prio;
genvar prio;
for(prio = 0; prio < num_priorities; prio = prio + 1)
begin:prios
wire [0:num_ports-1] req_unqual;
assign req_unqual = req[prio*num_ports:(prio+1)*num_ports-1];
if(prio < (num_priorities - 1))
assign enable_prio[prio+1] = enable_prio[prio] & ~|req_unqual;
wire [0:num_ports-1] req_unqual_rev;
c_reverse
#(.width(num_ports))
req_unqual_rev_revr
(.data_in(req_unqual),
.data_out(req_unqual_rev));
wire [0:num_ports-1] req_unqual_rev_compl;
assign req_unqual_rev_compl = -req_unqual_rev;
wire [0:num_ports-1] gnt_unqual_rev;
assign gnt_unqual_rev = req_unqual_rev & req_unqual_rev_compl;
wire [0:num_ports-1] gnt_unqual;
c_reverse
#(.width(num_ports))
gnt_unqual_revr
(.data_in(gnt_unqual_rev),
.data_out(gnt_unqual));
wire [0:num_ports-1] next_state_unqual_rev;
assign next_state_unqual_rev
= req_unqual_rev ^ req_unqual_rev_compl;
wire [0:num_ports-1] next_state_unqual;
c_reverse
#(.width(num_ports))
next_state_unqual_revr
(.data_in(next_state_unqual_rev),
.data_out(next_state_unqual));
wire [0:num_ports-1] req_qual;
assign req_qual = req_unqual & state;
wire [0:num_ports-1] req_qual_rev;
c_reverse
#(.width(num_ports))
req_qual_rev_revr
(.data_in(req_qual),
.data_out(req_qual_rev));
wire [0:num_ports-1] req_qual_rev_compl;
assign req_qual_rev_compl = -req_qual_rev;
wire [0:num_ports-1] gnt_qual_rev;
assign gnt_qual_rev = req_qual_rev & req_qual_rev_compl;
wire [0:num_ports-1] gnt_qual;
c_reverse
#(.width(num_ports))
gnt_qual_revr
(.data_in(gnt_qual_rev),
.data_out(gnt_qual));
wire [0:num_ports-1] next_state_qual_rev;
assign next_state_qual_rev = req_qual_rev ^ req_qual_rev_compl;
wire [0:num_ports-1] next_state_qual;
c_reverse
#(.width(num_ports))
next_state_qual_revr
(.data_in(next_state_qual_rev),
.data_out(next_state_qual));
assign gnt[prio*num_ports:(prio+1)*num_ports-1]
= ((|req_qual) ? gnt_qual : gnt_unqual) &
{num_ports{enable_prio[prio]}};
assign next_state_by_prio[prio*num_ports:(prio+1)*num_ports-1]
= (|req_qual) ? next_state_qual : next_state_unqual;
end
wire [0:num_ports-1] next_state;
c_select_mofn
#(.num_ports(num_priorities),
.width(num_ports))
next_state_sel
(.select(enable_prio),
.data_in(next_state_by_prio),
.data_out(next_state));
wire [0:num_ports-1] state_s, state_q;
assign state_s = update ? next_state : state_q;
assign state_q[0] = 1'b0;
c_dff
#(.width(num_ports-1),
.reset_type(reset_type))
stateq
(.clk(clk),
.reset(reset),
.active(active),
.d(state_s[1:num_ports-1]),
.q(state_q[1:num_ports-1]));
assign state = state_q;
end
endgenerate
endmodule
|
// $Id: c_scatter.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// spread out bit vector into larger vector
//==============================================================================
module c_scatter
(data_in, dest_in, data_out);
// width of output data
parameter out_width = 32;
// population count function (count ones)
function integer pop_count(input [0:out_width-1] argument);
integer i;
begin
pop_count = 0;
for(i = 0; i < out_width; i = i + 1)
pop_count = pop_count + argument[i];
end
endfunction
// mask indicating at which positions to put the input vector's bits
parameter [0:out_width-1] mask = {out_width{1'b1}};
// width of input vector
localparam in_width = pop_count(mask);
// input vector
input [0:in_width-1] data_in;
// destination vector
input [0:out_width-1] dest_in;
// result
output [0:out_width-1] data_out;
reg [0:out_width-1] data_out;
integer idx1, idx2;
always @(data_in)
begin
idx2 = 0;
for(idx1 = 0; idx1 < out_width; idx1 = idx1 + 1)
if(mask[idx1] == 1'b1)
begin
data_out[idx1] = data_in[idx2];
idx2 = idx2 + 1;
end
else
data_out[idx1] = dest_in[idx1];
end
endmodule
|
// $Id: c_select_1ofn.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic select mux (i.e., mux with one-hot control signal)
//==============================================================================
module c_select_1ofn
(select, data_in, data_out);
`include "c_constants.v"
// number of input ports
parameter num_ports = 4;
// width of each port
parameter width = 32;
// control signal to select active port
input [0:num_ports-1] select;
// vector of inputs
input [0:num_ports*width-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
// NOTE: This module was intended to represent something like a pass-gate
// or other multiplexer that requires that no more than one bit in the
// 'select' input is high at any given time. As Design Compiler appears
// to not like prolific use of tri-state logic, it is currently
// functionally identical to 'c_select_mofn' (which ORs all selected
// inputs); however, 'c_select_1ofn' should be preferred wherever the
// 'select' input is known to be one-hot.
/*
genvar p;
for(p = 0; p < num_ports; p = p + 1)
begin:ports
wire sel;
assign sel = select[p];
wire [0:width-1] data;
assign data = data_in[p*width:(p+1)*width-1];
assign data_out = sel ? data : {width{1'bz}};
end
*/
genvar i;
for(i = 0; i < width; i = i + 1)
begin:width_loop
wire [0:num_ports-1] port_bits;
genvar j;
for(j = 0; j < num_ports; j = j + 1)
begin:ports_loop
c_binary_op
#(.num_ports(2),
.width(1),
.op(`BINARY_OP_AND))
prod
(.data_in({data_in[i+j*width], select[j]}),
.data_out(port_bits[j]));
end
c_binary_op
#(.num_ports(num_ports),
.width(1),
.op(`BINARY_OP_OR))
sum
(.data_in(port_bits),
.data_out(data_out[i]));
end
endgenerate
endmodule
|
// $Id: c_select_mofn.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic multi-hot select gate
//==============================================================================
module c_select_mofn
(select, data_in, data_out);
`include "c_constants.v"
// number of input ports
parameter num_ports = 4;
// width of each port
parameter width = 32;
// multiplication operator
parameter prod_op = `BINARY_OP_AND;
// addition operator
parameter sum_op = `BINARY_OP_OR;
// control signal to select active port
input [0:num_ports-1] select;
// vector of inputs
input [0:num_ports*width-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < width; i = i + 1)
begin:width_loop
wire [0:num_ports-1] port_bits;
genvar j;
for(j = 0; j < num_ports; j = j + 1)
begin:ports_loop
c_binary_op
#(.num_ports(2),
.width(1),
.op(prod_op))
prod
(.data_in({data_in[i+j*width], select[j]}),
.data_out(port_bits[j]));
end
c_binary_op
#(.num_ports(num_ports),
.width(1),
.op(sum_op))
sum
(.data_in(port_bits),
.data_out(data_out[i]));
end
endgenerate
endmodule
|
// $Id: c_shift_reg.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// shift register
//==============================================================================
module c_shift_reg
(clk, reset, active, data_in, data_out);
`include "c_constants.v"
// width of register
parameter width = 32;
// depth of register (number of levels)
parameter depth = 2;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// data input
input [0:width-1] data_in;
// data output
output [0:width-1] data_out;
wire [0:width-1] data_out;
genvar level;
wire [0:(depth+1)*width-1] data;
assign data[0:width-1] = data_in;
generate
for(level = 0; level < depth; level = level + 1)
begin:levels
wire [0:width-1] data_s, data_q;
assign data_s = data[level*width:(level+1)*width-1];
c_dff
#(.width(width),
.reset_type(reset_type))
dataq
(.clk(clk),
.reset(reset),
.active(active),
.d(data_s),
.q(data_q));
assign data[(level+1)*width:(level+2)*width-1] = data_q;
end
endgenerate
assign data_out = data[depth*width:(depth+1)*width-1];
endmodule
|
// $Id: c_tree_arbiter.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic tree arbiter
//==============================================================================
module c_tree_arbiter
(clk, reset, active, req, gnt, update);
`include "c_constants.v"
// number of input ports
parameter num_ports = 16;
// number of blocks in first stage of arbitration
parameter num_blocks = 4;
// number of inputs to each first-stage arbiter
localparam ports_per_block = num_ports / num_blocks;
// select arbiter variant to use
parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// request vector
input [0:num_ports-1] req;
// grant vector
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
// update port priorities
input update;
// effective second-stage request vector
wire [0:num_blocks-1] stg2_req;
// second-stage grant vector
wire [0:num_blocks-1] stg2_gnt;
generate
// first stage of arbitration: one arbiter per group
genvar i;
for(i = 0; i < num_blocks; i = i + 1)
begin:blocks
wire [0:ports_per_block-1] stg1_req;
assign stg1_req = req[i*ports_per_block:(i+1)*ports_per_block-1];
assign stg2_req[i] = |stg1_req;
wire [0:ports_per_block-1] stg1_gnt;
c_arbiter
#(.num_ports(ports_per_block),
.reset_type(reset_type),
.arbiter_type(arbiter_type))
stg1_arb
(.clk(clk),
.reset(reset),
.active(active),
.req(stg1_req),
.gnt(stg1_gnt),
.update(update));
assign gnt[i*ports_per_block:(i+1)*ports_per_block-1]
= {ports_per_block{stg2_gnt[i]}} & stg1_gnt;
end
endgenerate
// second stage of arbitration: arbitrate between all groups
c_arbiter
#(.num_ports(num_blocks),
.reset_type(reset_type),
.arbiter_type(arbiter_type))
stg2_arb
(.clk(clk),
.reset(reset),
.active(active),
.req(stg2_req),
.gnt(stg2_gnt),
.update(update));
endmodule
|
// $Id: c_wf_alloc.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic wavefront allocator
//==============================================================================
module c_wf_alloc
(clk, reset, active, req, gnt, update);
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
// number of priority levels
parameter num_priorities = 1;
// select implementation variant
parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
// update port priorities
input update;
generate
// synopsys translate_off
if(num_priorities > 1)
begin
initial
begin
$display({"ERROR: Wavefront allocator does not yet support ",
"multiple priorities."});
$stop;
end
end
// synopsys translate_on
case(wf_alloc_type)
`WF_ALLOC_TYPE_MUX:
begin
c_wf_alloc_mux
#(.num_ports(num_ports),
.reset_type(reset_type))
core_mux
(.clk(clk),
.reset(reset),
.active(active),
.req(req),
.gnt(gnt),
.update(update));
end
`WF_ALLOC_TYPE_REP:
begin
c_wf_alloc_rep
#(.num_ports(num_ports),
.reset_type(reset_type))
core_rep
(.clk(clk),
.reset(reset),
.active(active),
.req(req),
.gnt(gnt),
.update(update));
end
`WF_ALLOC_TYPE_DPA:
begin
c_wf_alloc_dpa
#(.num_ports(num_ports),
.reset_type(reset_type))
core_dpa
(.clk(clk),
.reset(reset),
.active(active),
.req(req),
.gnt(gnt),
.update(update));
end
`WF_ALLOC_TYPE_ROT:
begin
c_wf_alloc_rot
#(.num_ports(num_ports),
.reset_type(reset_type))
core_rot
(.clk(clk),
.reset(reset),
.active(active),
.req(req),
.gnt(gnt),
.update(update));
end
`WF_ALLOC_TYPE_LOOP:
begin
c_wf_alloc_loop
#(.num_ports(num_ports),
.reset_type(reset_type))
core_loop
(.clk(clk),
.reset(reset),
.active(active),
.req(req),
.gnt(gnt),
.update(update));
end
endcase
endgenerate
endmodule
|
// $Id: c_wf_alloc_dpa.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// wavefron allocator variant implementing a Diagonal Propagation Arbiter as
// described in Hurt et al, "Design and Implementation of High-Speed Symmetric
// Crossbar Schedulers"
//==============================================================================
module c_wf_alloc_dpa
(clk, reset, active, req, gnt, update);
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
parameter reset_type = `RESET_TYPE_ASYNC;
// reset value for priority pointer
localparam [0:(2*num_ports-1)-1] prio_init
= {{num_ports{1'b1}}, {(num_ports-1){1'b0}}};
input clk;
input reset;
input active;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
// update port priorities
input update;
wire [0:(2*num_ports-1)-1] prio_q;
wire reset_prio;
assign reset_prio = ~|prio_q[0:(num_ports-1)-1];
wire [0:(2*num_ports-1)-1] prio_next;
assign prio_next
= reset_prio ? prio_init : {1'b0, prio_q[0:(2*num_ports-1)-2]};
wire [0:(2*num_ports-1)-1] prio_s;
assign prio_s = update ? prio_next : prio_q;
c_dff
#(.width(2*num_ports-1),
.reset_type(reset_type),
.reset_value(prio_init))
prioq
(.clk(clk),
.reset(reset),
.active(active),
.d(prio_s),
.q(prio_q));
wire [0:num_ports*(2*num_ports-2)-1] x;
generate
genvar col;
for(col = 0; col < num_ports; col = col + 1)
begin:cols
wire [0:(2*num_ports-1)-1] x_in, y_in;
wire [0:(2*num_ports-1)-1] x_out, y_out;
wire [0:(2*num_ports-1)-1] req_in;
wire [0:(2*num_ports-1)-1] gnt_out;
assign x_in = {1'b1, x[col*(2*num_ports-2):
(col+1)*(2*num_ports-2)-1]};
assign y_in = {1'b1, y_out[0:(2*num_ports-2)-1]};
assign x_out = (x_in & ~(y_in & req_in)) | ~prio_q;
assign y_out = (y_in & ~(x_in & req_in)) | ~prio_q;
assign gnt_out = req_in & x_in & y_in & prio_q;
assign x[((col+1)%num_ports)*(2*num_ports-2):
((col+1)%num_ports+1)*(2*num_ports-2)-1]
= x_out[0:(2*num_ports-2)-1];
genvar row;
for(row = 0; row < num_ports-1; row = row + 1)
begin:rows
assign req_in[row]
= req[((num_ports-col+row)%num_ports)*num_ports + col];
assign req_in[row+num_ports]
= req[((num_ports-col+row)%num_ports)*num_ports + col];
assign gnt[((num_ports-col+row)%num_ports)*num_ports+col]
= gnt_out[row] | gnt_out[row+num_ports];
end
assign req_in[num_ports-1]
= req[((2*num_ports-1-col)%num_ports)*num_ports+col];
assign gnt[((2*num_ports-1-col)%num_ports)*num_ports+col]
= gnt_out[num_ports-1];
end
endgenerate
endmodule
|
// $Id: c_wf_alloc_loop.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// wavefron allocator variant which uses wraparound (forming a false
// combinational loop) as described in Dally et al, "Principles and Practices of
// Interconnection Networks"
//==============================================================================
module c_wf_alloc_loop
(clk, reset, active, req, gnt, update);
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
parameter reset_type = `RESET_TYPE_ASYNC;
// reset value for priority pointer
localparam [0:num_ports-1] prio_init = {1'b1, {(num_ports-1){1'b0}}};
input clk;
input reset;
input active;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
// update port priorities
input update;
// Need to make sure priority is one-hot, otherwise conflicting grants can be
// generated!
wire [0:num_ports-1] prio_s, prio_q;
assign prio_s
= update ? {prio_q[num_ports-1], prio_q[0:num_ports-2]} : prio_q;
c_dff
#(.width(num_ports),
.reset_type(reset_type),
.reset_value(prio_init))
prioq
(.clk(clk),
.reset(reset),
.active(active),
.d(prio_s),
.q(prio_q));
wire [0:num_ports*num_ports-1] x_pri;
wire [0:num_ports*num_ports-1] y_pri;
generate
genvar row;
for(row = 0; row < num_ports; row = row + 1)
begin:rows
genvar col;
for(col = 0; col < num_ports; col = col + 1)
begin:cols
wire req_in;
assign req_in = req[row*num_ports+col];
wire x_pri_in;
assign x_pri_in
= x_pri[row*num_ports + ((col+num_ports-1)%num_ports)] |
prio_q[(row+col)%num_ports];
wire y_pri_in;
assign y_pri_in
= y_pri[((row+num_ports-1)%num_ports)*num_ports + col] |
prio_q[(row+col)%num_ports];
wire gnt_out;
assign gnt_out = req_in & x_pri_in & y_pri_in;
assign gnt[row*num_ports+col] = gnt_out;
wire x_pri_out;
assign x_pri_out = x_pri_in & ~gnt_out;
assign x_pri[row*num_ports+col] = x_pri_out;
wire y_pri_out;
assign y_pri_out = y_pri_in & ~gnt_out;
assign y_pri[row*num_ports+col] = y_pri_out;
end
end
endgenerate
endmodule
|
// $Id: c_wf_alloc_mux.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// wavefront allocator variant which uses multiplexers to permute inputs and
// outputs based on priority
//==============================================================================
module c_wf_alloc_mux
(clk, reset, active, req, gnt, update);
`include "c_functions.v"
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
// update port priorities
input update;
wire [0:port_idx_width-1] prio_q;
wire [0:port_idx_width-1] prio_next;
c_incr
#(.width(port_idx_width),
.min_value(0),
.max_value(num_ports-1))
prio_next_incr
(.data_in(prio_q),
.data_out(prio_next));
wire [0:port_idx_width-1] prio_s;
assign prio_s = update ? prio_next : prio_q;
c_dff
#(.width(port_idx_width),
.reset_type(reset_type))
prioq
(.clk(clk),
.reset(reset),
.active(active),
.d(prio_s),
.q(prio_q));
wire [0:num_ports*num_ports-1] y;
generate
genvar row;
for(row = 0; row < num_ports; row = row + 1)
begin:rows
wire [0:num_ports-1] x_in, y_in;
wire [0:num_ports] x_out, y_out;
assign x_in = x_out[0:num_ports-1];
assign y_in = y[((row+num_ports)%num_ports)*num_ports:
((row+num_ports)%num_ports+1)*num_ports-1];
wire [0:num_ports-1] req_in;
assign x_out = {1'b1, (~y_in | ~req_in) & x_in};
assign y_out = {1'b1, (~x_in | ~req_in) & y_in};
wire [0:num_ports-1] gnt_out;
assign gnt_out = req_in & x_in & y_in;
assign y[((row+num_ports+1)%num_ports)*num_ports:
((row+num_ports+1)%num_ports+1)*num_ports-1]
= y_out[0:num_ports-1];
wire [0:num_ports-1] gnt_row;
assign gnt[row*num_ports:(row+1)*num_ports-1] = gnt_row;
wire [0:num_ports-1] req_row;
assign req_row = req[row*num_ports:(row+1)*num_ports-1];
wire [0:2*num_ports-1] req_dup;
assign req_dup = {2{req_row}};
wire [0:2*num_ports-1] gnt_dup;
genvar col;
for(col = 0; col < num_ports; col = col + 1)
begin:cols
wire [0:num_ports-1] req_rot;
assign req_rot
= req_dup[(col+num_ports-row)%num_ports:
(col+num_ports-row)%num_ports+num_ports-1];
assign req_in[col] = req_rot[prio_q];
// need to reverse the grant vector
assign gnt_dup[num_ports-col-1] = gnt_out[col];
assign gnt_dup[2*num_ports-col-1] = gnt_out[col];
wire [0:num_ports-1] gnt_rot;
assign gnt_rot
= gnt_dup[(2*num_ports-row-col-1)%num_ports:
(2*num_ports-row-col-1)%num_ports+
num_ports-1];
assign gnt_row[col] = gnt_rot[prio_q];
end
end
endgenerate
endmodule
|
// $Id: c_wf_alloc_rep.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// wavefront allocator variant which replicates the entire allocation logic for
// the different priorities and selects the result from the appropriate one
//==============================================================================
module c_wf_alloc_rep
(clk, reset, active, req, gnt, update);
`include "c_functions.v"
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
parameter reset_type = `RESET_TYPE_ASYNC;
// width of priority selector
localparam prio_width = clogb(num_ports);
input clk;
input reset;
input active;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
// update port priorities
input update;
wire [0:prio_width-1] prio_q;
wire [0:prio_width-1] prio_next;
c_incr
#(.width(prio_width),
.min_value(0),
.max_value(num_ports-1))
prio_next_incr
(.data_in(prio_q),
.data_out(prio_next));
wire [0:prio_width-1] prio_s;
assign prio_s = update ? prio_next : prio_q;
c_dff
#(.width(prio_width),
.reset_type(reset_type))
prioq
(.clk(clk),
.reset(reset),
.active(active),
.d(prio_s),
.q(prio_q));
wire [0:num_ports*num_ports*num_ports-1] gnt_by_prio;
generate
genvar prio;
for(prio = 0; prio < num_ports; prio = prio + 1)
begin:prios
wire [0:num_ports*num_ports-1] req_int;
wire [0:num_ports*num_ports-1] gnt_int;
wire [0:num_ports*num_ports-1] y;
genvar row;
for(row = 0; row < num_ports; row = row + 1)
begin:rows
wire [0:num_ports-1] x_in, y_in;
wire [0:num_ports] x_out, y_out;
wire [0:num_ports-1] req_in;
wire [0:num_ports-1] gnt_out;
assign x_in = x_out[0:num_ports-1];
assign y_in
= y[((row+num_ports)%num_ports)*num_ports:
((row+num_ports)%num_ports+1)*num_ports-1];
assign req_in = req_int[row*num_ports:
(row+1)*num_ports-1];
assign x_out = {1'b1, (~y_in | ~req_in) & x_in};
assign y_out = {1'b1, (~x_in | ~req_in) & y_in};
assign gnt_out = req_in & x_in & y_in;
assign y[((row+num_ports+1)%num_ports)*num_ports:
((row+num_ports+1)%num_ports+1)*num_ports-1]
= y_out[0:num_ports-1];
assign gnt_int[row*num_ports:(row+1)*num_ports-1]
= gnt_out;
genvar col;
for(col = 0; col < num_ports; col = col + 1)
begin:cols
assign req_int[row*num_ports+col]
= req[((prio+row)%num_ports)*num_ports +
(num_ports-row+col)%num_ports];
assign gnt_by_prio[((prio+row)%num_ports)*
num_ports +
(num_ports-row+col)%num_ports +
prio*num_ports*num_ports]
= gnt_int[row*num_ports+col];
end
end
end
endgenerate
assign gnt = gnt_by_prio[prio_q*num_ports*num_ports +: num_ports*num_ports];
endmodule
|
// $Id: c_wf_alloc_rot.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// wavefront allocator variant which rotates inputs and outputs based on
// priority
//==============================================================================
module c_wf_alloc_rot
(clk, reset, active, req, gnt, update);
`include "c_functions.v"
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
parameter reset_type = `RESET_TYPE_ASYNC;
localparam prio_width = clogb(num_ports);
input clk;
input reset;
input active;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
// update port priorities
input update;
wire [0:num_ports*num_ports-1] y;
wire [0:prio_width-1] prio_q;
wire [0:prio_width-1] prio_next;
c_incr
#(.width(prio_width),
.min_value(0),
.max_value(num_ports-1))
prio_next_incr
(.data_in(prio_q),
.data_out(prio_next));
wire [0:prio_width-1] prio_s;
assign prio_s = update ? prio_next : prio_q;
c_dff
#(.width(prio_width),
.reset_type(reset_type))
prioq
(.clk(clk),
.reset(reset),
.active(active),
.d(prio_s),
.q(prio_q));
generate
genvar row;
for(row = 0; row < num_ports; row = row + 1)
begin:rows
wire [0:num_ports-1] req_row;
assign req_row = req[row*num_ports:(row+1)*num_ports-1];
wire [0:prio_width-1] current_row;
assign current_row = row;
wire [0:num_ports-1] req_tmp;
c_rotate
#(.width(num_ports),
.rotate_dir(`ROTATE_DIR_RIGHT))
req_tmp_rot
(.amount(current_row),
.data_in(req_row),
.data_out(req_tmp));
wire [0:num_ports-1] req_in;
c_rotate
#(.width(num_ports),
.rotate_dir(`ROTATE_DIR_LEFT))
req_in_rot
(.amount(prio_q),
.data_in(req_tmp),
.data_out(req_in));
wire [0:num_ports-1] x_in, y_in;
wire [0:num_ports] x_out, y_out;
assign x_in = x_out[0:num_ports-1];
assign y_in = y[((row+num_ports)%num_ports)*num_ports:
((row+num_ports)%num_ports+1)*num_ports-1];
assign x_out = {1'b1, (~y_in | ~req_in) & x_in};
assign y_out = {1'b1, (~x_in | ~req_in) & y_in};
wire [0:num_ports-1] gnt_out;
assign gnt_out = req_in & x_in & y_in;
assign y[((row+num_ports+1)%num_ports)*num_ports:
((row+num_ports+1)%num_ports+1)*num_ports-1]
= y_out[0:num_ports-1];
wire [0:num_ports-1] gnt_tmp;
c_rotate
#(.width(num_ports),
.rotate_dir(`ROTATE_DIR_RIGHT))
gnt_tmp_rot
(.amount(prio_q),
.data_in(gnt_out),
.data_out(gnt_tmp));
wire [0:num_ports-1] gnt_row;
c_rotate
#(.width(num_ports),
.rotate_dir(`ROTATE_DIR_LEFT))
gnt_row_rot
(.amount(current_row),
.data_in(gnt_tmp),
.data_out(gnt_row));
assign gnt[row*num_ports:(row+1)*num_ports-1] = gnt_row;
end
endgenerate
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file fifo_16.v when simulating
// the core, fifo_16. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module fifo_16(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
valid
);
input clk;
input rst;
input [8 : 0] din;
input wr_en;
input rd_en;
output [8 : 0] dout;
output full;
output empty;
output valid;
// synthesis translate_off
FIFO_GENERATOR_V8_1 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(9),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(9),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(1),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(5),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(4),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(2),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(510),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(1),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.VALID(valid),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file gsm_sram.v when simulating
// the core, gsm_sram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module gsm_sram(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [131 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [131 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(9),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(1),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(6),
.C_READ_DEPTH_A(512),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(132),
.C_READ_WIDTH_B(132),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(512),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(132),
.C_WRITE_WIDTH_B(132),
.C_XDEVICEFAMILY("virtex6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file malloc_core.v when simulating
// the core, malloc_core. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module malloc_core(
clka,
wea,
addra,
dina,
douta,
clkb,
rstb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [3 : 0] dina;
output [3 : 0] douta;
input clkb;
input rstb;
input [0 : 0] web;
input [11 : 0] addrb;
input [0 : 0] dinb;
output [3 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(1),
.C_HAS_MUX_OUTPUT_REGS_B(1),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(1),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(2),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(4),
.C_READ_WIDTH_B(4),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(4),
.C_WRITE_WIDTH_B(1),
.C_XDEVICEFAMILY("virtex6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.RSTB(rstb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
module gsm_impl
#(
parameter DWIDTH = 256,
parameter MWIDTH = 4,
parameter GSIZE = 4,
parameter LOG_MWIDTH = 2,
parameter LOG_GSIZE = 2,
parameter AWIDTH = 7,
parameter LOC_PKT_LEN = 24, // the bit location of packet length field in the 16-byte data cell
parameter LOC_DEST_IP = 31, // the bit location of the destination ip field in the data cell
parameter LOC_SOURCE_ID = 16
)
(
input wire clk_33M,
input wire extern_rst_n,
input wire [MWIDTH*GSIZE-1:0] ingress_valid,
input wire [MWIDTH*GSIZE-1:0] ingress_header,
input wire [MWIDTH*GSIZE-1:0] ingress_data_bit,
input wire [MWIDTH*GSIZE-1:0] egress_stall,
output wire [MWIDTH*GSIZE-1:0] egress_valid,
output reg [MWIDTH*GSIZE-1:0] egress_data_bit
);
genvar i;
reg [DWIDTH-1:0]ingress_data[MWIDTH*GSIZE-1:0];
wire [DWIDTH-1:0] egress_data[MWIDTH*GSIZE-1:0];
wire clk_80M, clr_80M, clk_320M, clr_320M, rst_n;
generate
for(i=0;i<MWIDTH*GSIZE;i=i+1)begin:INGRESS_DATA_GEN
always@(posedge clk_80M)
if(clr_80M)
ingress_data[i] <= 0;
else
ingress_data[i] <= {ingress_data[i], ingress_data_bit[i]};
always@(posedge clk_80M)
if(clr_80M)
egress_data_bit[i] <= 0;
else
egress_data_bit[i] <= |egress_data[i];
end
endgenerate
gsm_sys
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.GSIZE(GSIZE), // group size, number of gsm_unit in each group
// .LOG_MWIDTH(LOG_MWIDTH),
// .LOG_GSIZE(LOG_GSIZE),
.DWIDTH(DWIDTH), // data width = 16 bytes
.AWIDTH(AWIDTH) // 2 BRAM = total 512 cells, each port is allocated 128 cells
) gsm_sys_inst
(
//** global
.clk_33M(clk_33M),
.extern_rst_n(extern_rst_n),
.clk_320M(clk_320M),
.clk_80M(clk_80M),
.clr_320M(clr_320M),
.clr_80M(clr_80M),
.rst_n(rst_n),
//** 16 ingress ports
// group 0
.i_ingress_valid_0_0(ingress_valid[0]),
.i_ingress_header_0_0(ingress_header[0]),
.i_ingress_data_0_0(ingress_data[0]),
.i_ingress_valid_0_1(ingress_valid[1]),
.i_ingress_header_0_1(ingress_header[1]),
.i_ingress_data_0_1(ingress_data[1]),
.i_ingress_valid_0_2(ingress_valid[2]),
.i_ingress_header_0_2(ingress_header[2]),
.i_ingress_data_0_2(ingress_data[2]),
.i_ingress_valid_0_3(ingress_valid[3]),
.i_ingress_header_0_3(ingress_header[3]),
.i_ingress_data_0_3(ingress_data[3]),
// group 1
.i_ingress_valid_1_0(ingress_valid[4]),
.i_ingress_header_1_0(ingress_header[4]),
.i_ingress_data_1_0(ingress_data[4]),
.i_ingress_valid_1_1(ingress_valid[5]),
.i_ingress_header_1_1(ingress_header[5]),
.i_ingress_data_1_1(ingress_data[5]),
.i_ingress_valid_1_2(ingress_valid[6]),
.i_ingress_header_1_2(ingress_header[6]),
.i_ingress_data_1_2(ingress_data[6]),
.i_ingress_valid_1_3(ingress_valid[7]),
.i_ingress_header_1_3(ingress_header[7]),
.i_ingress_data_1_3(ingress_data[7]),
// group 2
.i_ingress_valid_2_0(ingress_valid[8]),
.i_ingress_header_2_0(ingress_header[8]),
.i_ingress_data_2_0(ingress_data[8]),
.i_ingress_valid_2_1(ingress_valid[9]),
.i_ingress_header_2_1(ingress_header[9]),
.i_ingress_data_2_1(ingress_data[9]),
.i_ingress_valid_2_2(ingress_valid[10]),
.i_ingress_header_2_2(ingress_header[10]),
.i_ingress_data_2_2(ingress_data[10]),
.i_ingress_valid_2_3(ingress_valid[11]),
.i_ingress_header_2_3(ingress_header[11]),
.i_ingress_data_2_3(ingress_data[11]),
// group 3
.i_ingress_valid_3_0(ingress_valid[12]),
.i_ingress_header_3_0(ingress_header[12]),
.i_ingress_data_3_0(ingress_data[12]),
.i_ingress_valid_3_1(ingress_valid[13]),
.i_ingress_header_3_1(ingress_header[13]),
.i_ingress_data_3_1(ingress_data[13]),
.i_ingress_valid_3_2(ingress_valid[14]),
.i_ingress_header_3_2(ingress_header[14]),
.i_ingress_data_3_2(ingress_data[14]),
.i_ingress_valid_3_3(ingress_valid[15]),
.i_ingress_header_3_3(ingress_header[15]),
.i_ingress_data_3_3(ingress_data[15]),
//** 16 egress ports
// group 0
.i_egress_stall_0_0(egress_stall[0]),
.o_egress_valid_0_0(egress_valid[0]),
.o_egress_data_0_0(egress_data[0]),
.i_egress_stall_0_1(egress_stall[1]),
.o_egress_valid_0_1(egress_valid[1]),
.o_egress_data_0_1(egress_data[1]),
.i_egress_stall_0_2(egress_stall[2]),
.o_egress_valid_0_2(egress_valid[2]),
.o_egress_data_0_2(egress_data[2]),
.i_egress_stall_0_3(egress_stall[3]),
.o_egress_valid_0_3(egress_valid[3]),
.o_egress_data_0_3(egress_data[3]),
// group 1
.i_egress_stall_1_0(egress_stall[4]),
.o_egress_valid_1_0(egress_valid[4]),
.o_egress_data_1_0(egress_data[4]),
.i_egress_stall_1_1(egress_stall[5]),
.o_egress_valid_1_1(egress_valid[5]),
.o_egress_data_1_1(egress_data[5]),
.i_egress_stall_1_2(egress_stall[6]),
.o_egress_valid_1_2(egress_valid[6]),
.o_egress_data_1_2(egress_data[6]),
.i_egress_stall_1_3(egress_stall[7]),
.o_egress_valid_1_3(egress_valid[7]),
.o_egress_data_1_3(egress_data[7]),
// group 2
.i_egress_stall_2_0(egress_stall[8]),
.o_egress_valid_2_0(egress_valid[8]),
.o_egress_data_2_0(egress_data[8]),
.i_egress_stall_2_1(egress_stall[9]),
.o_egress_valid_2_1(egress_valid[9]),
.o_egress_data_2_1(egress_data[9]),
.i_egress_stall_2_2(egress_stall[10]),
.o_egress_valid_2_2(egress_valid[10]),
.o_egress_data_2_2(egress_data[10]),
.i_egress_stall_2_3(egress_stall[11]),
.o_egress_valid_2_3(egress_valid[11]),
.o_egress_data_2_3(egress_data[11]),
// group 3
.i_egress_stall_3_0(egress_stall[12]),
.o_egress_valid_3_0(egress_valid[12]),
.o_egress_data_3_0(egress_data[12]),
.i_egress_stall_3_1(egress_stall[13]),
.o_egress_valid_3_1(egress_valid[13]),
.o_egress_data_3_1(egress_data[13]),
.i_egress_stall_3_2(egress_stall[14]),
.o_egress_valid_3_2(egress_valid[14]),
.o_egress_data_3_2(egress_data[14]),
.i_egress_stall_3_3(egress_stall[15]),
.o_egress_valid_3_3(egress_valid[15]),
.o_egress_data_3_3(egress_data[15])
);
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_ram.v
// Description : a time-multiplexing SRAM module, which serves as the building block
// of the grouped-share-memory system.
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-16 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_ram
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter DWIDTH = 128, // data width = 16 bytes
parameter AWIDTH = 9 // 2 BRAM = total 512 cells
)
(
// global
input wire clk,
input wire rst_n,
input wire clr,
// input port
input wire i_wr_en,
input wire [AWIDTH-1:0] i_wr_addr,
input wire [DWIDTH-1:0] i_wr_data,
input wire [MWIDTH-1:0] i_multicast,
// output port
input wire [MWIDTH-1:0] i_egress_stall,
output wire [MWIDTH-1:0] o_egress_sel,
output wire [DWIDTH-1:0] o_egress_data,
// buffer free
output wire o_buf_free,
output wire [AWIDTH-1:0] o_buf_free_addr
//output wire [MWIDTH-1:0] temp
);
`include "c_functions.v"
localparam LOG_MWIDTH = clogb(MWIDTH);
localparam BRAM_RD_DELAY = 2;
//******************************
// signal declaration
//******************************
genvar i;
reg [MWIDTH-1:0] fsm_opq_sel;
//wire [MWIDTH-1:0] opq_empty, opq_full;
wire [MWIDTH-1:0] opq_valid, opq_rd_en;
wire [MWIDTH*AWIDTH-1:0] opq_dout;
wire [MWIDTH+DWIDTH-1:0] gsm_rd_data;
reg [MWIDTH-1:0] gsm_rd_sel;
reg [MWIDTH-1:0] gsm_rd_sel_delay[BRAM_RD_DELAY-1:0];
reg [BRAM_RD_DELAY-1:0] gsm_rd_valid_delay;
reg [AWIDTH-1:0] gsm_rd_addr;
//******************************
// logics starts here
//******************************
// finite state machine
always@(posedge clk )begin
if(clr)
fsm_opq_sel <= 1;
else
fsm_opq_sel <= {fsm_opq_sel,fsm_opq_sel[MWIDTH-1]};
end
// output pointer queues
assign opq_rd_en = fsm_opq_sel & (~i_egress_stall);// | ~opq_valid;
generate
for(i=0; i<MWIDTH; i=i+1) begin: OPQ_GEN
fifo_16 #(.AWIDTH(AWIDTH))
opq(
.clk(clk),
.rst(clr),
.din(i_wr_addr),
.wr_en(i_wr_en & i_multicast[i]),
.rd_en(opq_rd_en[i]),
.dout(opq_dout[(i+1)*AWIDTH-1:i*AWIDTH]),
//.full(opq_full[i]),
//.empty(opq_empty[i]),
.valid(opq_valid[i])
);
end
endgenerate
wire [AWIDTH-1:0] gsm_rd_addr_mux;
c_select_1ofn
#(
.num_ports(MWIDTH),
.width(AWIDTH)
)
rd_addr_mux_inst
(
.select(opq_valid),
.data_in(opq_dout),
.data_out(gsm_rd_addr_mux)
);
// central memory read address
always@(posedge clk )begin
if(clr)
gsm_rd_addr <= 0;
else
gsm_rd_addr <= gsm_rd_addr_mux;
end
// gsm read enable, read select signal and delayed signal
always@(posedge clk )begin
if(clr)
gsm_rd_sel <= 0;
else
gsm_rd_sel <= opq_valid;//(fsm_opq_sel & (~i_egress_stall) & opq_valid);
end
// centralized share memory for data
infer_sdpram
#(
.DWIDTH(MWIDTH+DWIDTH), // data width of the SRAM, 36 bit when configured to be SDP BRAM, otherwise 18 bit wide
.AWIDTH(AWIDTH) // address width of the SRAM
) central_mem
(
// global
.clk_a(clk),
.clk_b(clk),
// port a interface
.en_a(i_wr_en),
.write_a(i_wr_en),
.wr_data_a({i_multicast,i_wr_data}),
.addr_a(i_wr_addr),
// port b interface
.en_b(1'b1),
.addr_b(gsm_rd_addr),
.rd_data_b(gsm_rd_data)
);
//
///*gsm_sram central_mem(
// .clka(clk),
// .wea(i_wr_en),
// .addra(i_wr_addr),
// .dina({i_multicast,i_wr_data}),
// .clkb(clk),
// .addrb(gsm_rd_addr),
// .doutb(gsm_rd_data)
//);*/
always@(posedge clk )begin
if(clr)
gsm_rd_sel_delay[0] <= 0;
else
gsm_rd_sel_delay[0] <= gsm_rd_sel;
end
generate
for(i=1;i<BRAM_RD_DELAY; i=i+1) begin: GSM_RD_SEL_DELAY
always@(posedge clk )begin
if(clr)
gsm_rd_sel_delay[i] <= 0;
else
gsm_rd_sel_delay[i] <= gsm_rd_sel_delay[i-1];
end
end
endgenerate
always@(posedge clk )begin
if(clr)
gsm_rd_valid_delay <= 0;
else
gsm_rd_valid_delay <= {gsm_rd_valid_delay,|gsm_rd_sel};
end
//**************************************************************
// hardware malloc core logic
// implemented using a single BRAM, with a 1-bit write port
// a 4-bit write port and 4-bit read port. it works as follows:
// 1. in each clk cycle, the 1-bit write port will be enabled
// if there is a valid data sent to the output link. the
// address will be the same of the data being sent
// 2. the 4-bit read port is set to "WRITE_FITST" mode, so that
// after each write, the 4-bit vector of that data can be
// compared with its multicast vector, if the multicast task
// for that data is done, a reset signal will be asserted
// 3. when there is a reset signal, the 4-bit write port will
// be used to reset a specific 4-bit vector in the BRAM
//**************************************************************
reg [AWIDTH-1:0] m_addr;
reg [LOG_MWIDTH-1:0] m_sel_enc;
reg m_wr;
wire m_reset;
reg [AWIDTH-1:0] m_rst_addr[BRAM_RD_DELAY-1:0];
wire [MWIDTH-1:0] m_vec;
reg [MWIDTH-1:0] gsm_vec;
reg [BRAM_RD_DELAY-1:0] m_valid_delay;
wire [LOG_MWIDTH-1:0] m_sel_encode;
c_encode
#(
.num_ports(MWIDTH)
)
m_select_encode
(
.data_in(gsm_rd_sel),
.data_out(m_sel_encode)
);
always@(posedge clk )begin
if(clr)
m_sel_enc <= 0;
else
m_sel_enc <= m_sel_encode;
end
always@(posedge clk )begin
if(clr)begin
m_addr <= 0;
m_wr <= 0;
gsm_vec <= 0;
end
else begin
m_addr <= gsm_rd_addr;
m_wr <= |gsm_rd_sel;
gsm_vec <= gsm_rd_data[DWIDTH+MWIDTH-1:DWIDTH];
end
end
always@(posedge clk )begin
if(clr)
m_valid_delay <= 0;
else
m_valid_delay <= {m_valid_delay,m_wr};
end
always@(posedge clk )begin
if(clr)
m_rst_addr[0] <= 0;
else
m_rst_addr[0] <= m_addr;
end
generate
for(i=1;i<BRAM_RD_DELAY; i=i+1) begin: MULTICAST_COUNTER_ADDR_DELAY
always@(posedge clk )begin
if(clr)
m_rst_addr[i] <= 0;
else
m_rst_addr[i] <= m_rst_addr[i-1];
end
end
endgenerate
///*
//malloc_core m_counter(
// .clka(clk),
// .wea(m_reset),
// .addra({1'b0,m_rst_addr[BRAM_RD_DELAY-1]}),
// .dina(4'b0000), // reset the counter to all 0s
// .douta(),
// .clkb(clk),
// .rstb(clr),
// .web(m_wr), //
// .addrb({1'b0,m_addr,m_sel_enc}),
// .dinb(1'b1),
// .doutb(m_vec)
//);
//*/
malloc_core_infer#(
.DWIDTH_A(MWIDTH),
.DWIDTH_B(1),
.AWIDTH_A(AWIDTH),
.AWIDTH_B(AWIDTH+LOG_MWIDTH)
)
m_counter(
.clka(clk),
.wea(m_reset),
.addra(m_rst_addr[BRAM_RD_DELAY-1]),
.dina({MWIDTH{1'b0}}), // reset the counter to all 0s
//.douta(temp),
.clkb(clk),
.rstb(clr),
.web(m_wr), //
.addrb({m_addr,m_sel_enc}),
.dinb(1'b1),
.doutb(m_vec)
);
assign m_reset = m_valid_delay[BRAM_RD_DELAY-1] & (m_vec == gsm_vec);
// output port signals
assign o_buf_free = m_reset;
assign o_buf_free_addr = m_rst_addr[BRAM_RD_DELAY-1];
assign o_egress_data = gsm_rd_data[DWIDTH-1:0];
assign o_egress_sel = gsm_rd_sel_delay[BRAM_RD_DELAY-1];
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_sys.v
// Description : a 16x16 Grouped Shared Memory switch system
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-29 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module shift_data_in
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter GSIZE = 8, // group size, number of gsm_unit in each group
parameter DWIDTH = 128 // data width = 16 bytes
)
(clk, clr, sig_i, sig_o);
input clk, sig_i, clr;
output reg [MWIDTH*GSIZE*DWIDTH-1:0] sig_o;
always @(posedge clk or posedge clr)
begin
if (clr)
begin
sig_o <= 0;
end
else
begin
sig_o <= {sig_o[MWIDTH*GSIZE*DWIDTH-2:0], sig_i};
end
end
endmodule
module shift_data_out
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter GSIZE = 8, // group size, number of gsm_unit in each group
parameter DWIDTH = 128 // data width = 16 bytes
)
(clk, clr, sig_i, sig_o);
input clk, clr;
input [MWIDTH*GSIZE*DWIDTH-1:0] sig_i;
output sig_o;
reg [MWIDTH*GSIZE*DWIDTH-1:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
begin
tmp <= sig_i;
end
else
begin
tmp <= {tmp[MWIDTH*GSIZE*DWIDTH-2:0], sig_i[MWIDTH*GSIZE*DWIDTH-1]};
//tmp <= sig_i;
end
end
assign sig_o = tmp[MWIDTH*GSIZE*DWIDTH-1];
endmodule
module gsm_sys
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter GSIZE = 8, // group size, number of gsm_unit in each group
parameter DWIDTH = 128, // data width = 16 bytes
parameter AWIDTH = 7 // 2 BRAM = total 512 cells, each port is allocated 128 cells
)
(
//** global
input wire clk_33M,
input wire shift_clk,
input wire extern_rst_n,
output wire clr_320M,
output wire clr_80M,
output wire rst_n,
//** 16 ingress ports
input wire [MWIDTH*GSIZE-1:0] i_ingress_valid,
input wire [MWIDTH*GSIZE-1:0] i_ingress_header,
input wire i_ingress_data,
//** 16 egress ports
input wire [MWIDTH*GSIZE-1:0] i_egress_stall,
output reg [MWIDTH*GSIZE-1:0] o_egress_valid,
output wire o_egress_data
);
`include "c_functions.v"
localparam LOG_MWIDTH = clogb(MWIDTH);
localparam LOG_GSIZE = clogb(GSIZE);
//*************************************************************
// wires and registers
//*************************************************************
genvar i,j;
wire clk_320M;
wire clk_80M;
wire [GSIZE*GSIZE*MWIDTH-1:0] egress_rd;
wire [GSIZE*GSIZE*MWIDTH-1:0] egress_valid;
reg [GSIZE*GSIZE*MWIDTH-1:0] egress_grant;
wire [GSIZE*GSIZE*MWIDTH*DWIDTH-1:0] egress_data;
wire clk_stable_80M;
wire [MWIDTH*GSIZE*DWIDTH-1:0] i_ingress_data_wires;
reg [MWIDTH*GSIZE*DWIDTH-1:0] o_egress_data_wires;
reg [1:0] clk_stable_320M;
//*************************************************************
// use shift registers to reduces the size of the I/O data to 1
//*************************************************************
shift_data_in
# (
.MWIDTH(MWIDTH),
.GSIZE(GSIZE),
.DWIDTH(DWIDTH)
)
shift_in (
.clk(shift_clk),
.clr(extern_rst_n),
.sig_i(i_ingress_data),
.sig_o(i_ingress_data_wires)
);
shift_data_out
# (
.MWIDTH(MWIDTH),
.GSIZE(GSIZE),
.DWIDTH(DWIDTH)
)
shift_out (
.clk(shift_clk),
.clr(extern_rst_n),
.sig_i(o_egress_data_wires),
.sig_o(o_egress_data)
);
//*************************************************************
// logic starts here...
//*************************************************************
ClockGenerator clk_gen
(
.EXTERNAL_RESET_L(extern_rst_n),
.CLOCKS_STABLE_H(clk_stable_80M),
.CLK_33MHz(clk_33M),
.CLK_80MHz(clk_80M),
.CLK_320MHz(clk_320M)
);
always@(posedge clk_320M)begin
clk_stable_320M <= {clk_stable_320M[0],clk_stable_80M};
end
//BUFG RESET_320M_Buffer ( .I(~clk_stable_320M[1]), .O(clr_320M) );
//BUFG RESET_80M_Buffer ( .I(~clk_stable_80M), .O(clr_80M) );
assign clr_320M = ~clk_stable_320M[1];
assign clr_80M = ~clk_stable_80M;
assign rst_n = 1'b1;
generate
for(i=0;i<GSIZE;i=i+1) begin: GSM_TILE_GEN
gsm_tile
#(
.MWIDTH(MWIDTH),
.GSIZE(GSIZE),
.DWIDTH(DWIDTH),
.AWIDTH(AWIDTH)
)gsm_tile_inst
(
//** global
.clk_320M(clk_320M),
.clr_320M(clr_320M),
.clk_80M(clk_80M),
.clr_80M(clr_80M),
.rst_n(rst_n),
//** 4 ingress ports
.i_ingress_valid(i_ingress_valid[(i+1)*MWIDTH-1:i*MWIDTH]),
.i_ingress_header(i_ingress_header[(i+1)*MWIDTH-1:i*MWIDTH]),
.i_ingress_data(i_ingress_data_wires[(i+1)*MWIDTH*DWIDTH-1:i*MWIDTH*DWIDTH]),
//** 16 egress ports
// group 1
.i_egress_rd(egress_grant[(i+1)*GSIZE*MWIDTH-1:i*GSIZE*MWIDTH]),
.o_egress_valid(egress_valid[(i+1)*GSIZE*MWIDTH-1:i*GSIZE*MWIDTH]),
.o_egress_data(egress_data[(i+1)*GSIZE*MWIDTH*DWIDTH-1:i*GSIZE*MWIDTH*DWIDTH])
);
end // end for
endgenerate
// 16 4:1 multiplexers for the 16*4 egress ports
reg [GSIZE*GSIZE*MWIDTH-1:0] rr_req, rr_stall;
wire [GSIZE*GSIZE*MWIDTH-1:0] rr_grant;
reg [GSIZE*GSIZE*MWIDTH*DWIDTH-1:0] rr_data;
generate
for(i=0;i<GSIZE*MWIDTH;i=i+1)begin: RR_REQ_GENI
for(j=0;j<GSIZE;j=j+1)begin: RR_REQ_GENJ
always@(*)begin
rr_req[i*GSIZE+j] = egress_valid[j*GSIZE*MWIDTH+i];
//rr_stall[i*GSIZE+j] = i_egress_stall[j*GSIZE*MWIDTH+i];
rr_data[i*GSIZE*DWIDTH+(j+1)*DWIDTH-1:i*GSIZE*DWIDTH+j*DWIDTH]
=
egress_data[j*GSIZE*MWIDTH*DWIDTH+(i+1)*DWIDTH-1:j*GSIZE*MWIDTH*DWIDTH+i*DWIDTH];
end
end
end
endgenerate
generate
for(i=0;i<GSIZE*MWIDTH;i=i+1)begin:rnd_robin2
rr_sch
#(
.NUM_PORT(GSIZE) // number of requests to be scheduled
)rr_sch_inst
(
.clk(clk_80M),
.rst_n(rst_n),
.clr(clr_80M),
.req(rr_req[(i+1)*GSIZE-1:i*GSIZE]),
.stall(i_egress_stall[i]),
.grant(rr_grant[(i+1)*GSIZE-1:i*GSIZE])
);
end // end for rnd_robin2
endgenerate
generate
for(i=0;i<GSIZE*MWIDTH;i=i+1)begin: RR_GRANT_GENI
for(j=0;j<GSIZE;j=j+1)begin: RR_GRANT_GENJ
always@(*)begin
egress_grant[j*GSIZE*MWIDTH+i] = rr_grant[i*GSIZE+j];
end
end
end
endgenerate
wire [DWIDTH-1:0] egress_data_mux[GSIZE*MWIDTH-1:0];
generate
for(i=0;i<GSIZE*MWIDTH;i=i+1)begin: EGRESS_VALID_GEN
always@(posedge clk_80M)begin
if(clr_80M)begin
o_egress_valid[i] <= 0;
o_egress_data_wires[(i+1)*DWIDTH-1:i*DWIDTH] <= 0;
end
else begin
o_egress_valid[i] <= |rr_grant[(i+1)*GSIZE-1:i*GSIZE];
o_egress_data_wires[(i+1)*DWIDTH-1:i*DWIDTH] <=
egress_data_mux[i];
end
end
c_select_1ofn#(
.num_ports(GSIZE),
.width(DWIDTH)
)
egress_dmux
(
.select(rr_grant[(i+1)*GSIZE-1:i*GSIZE]),
.data_in(rr_data[(i+1)*GSIZE*DWIDTH-1:i*GSIZE*DWIDTH]),
.data_out(egress_data_mux[i])
);
end
endgenerate
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_tile.v
// Description : Grouped Shared Memory first level switch --- gsm-tile.
// each tile is responsible for data switching of 4 ingress
// and 4 egress links
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-27 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_tile
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter GSIZE = 4, // group size, number of gsm_unit in each group
parameter DWIDTH = 128, // data width = 16 bytes
parameter AWIDTH = 7 // 2 BRAM = total 512 cells, each port is allocated 128 cells
)
(
//** global
input wire clk_320M,
input wire clr_320M,
input wire clk_80M,
input wire clr_80M,
input wire rst_n,
//** 4 ingress ports
input wire [MWIDTH-1:0] i_ingress_valid,
input wire [MWIDTH-1:0] i_ingress_header,
input wire [MWIDTH*DWIDTH-1:0] i_ingress_data,
//** 16 egress ports
input wire [GSIZE*MWIDTH-1:0] i_egress_rd,
output wire [GSIZE*MWIDTH-1:0] o_egress_valid,
output wire [GSIZE*MWIDTH*DWIDTH-1:0] o_egress_data
);
`include "c_functions.v"
localparam LOG_MWIDTH = clogb(MWIDTH);
localparam MAX_PKT_LEN = 7; // maximum packet length in unit of 16-byte data cell
localparam LOC_PKT_LEN = 24; // the bit location of packet length field in the 16-byte data cell
localparam LOC_DEST_IP = 32; // the bit location of the destination ip field in the data cell
// ---------------------------------------------------------------------
// wire, registers and genvar
// ---------------------------------------------------------------------
genvar i,j;
reg [MWIDTH-1:0] common_sel;
//reg [DWIDTH-1:0] common_data;
reg [DWIDTH-1:0] common_data_reg[GSIZE-1:0];
//reg [MWIDTH-1:0] common_sel_reg[GSIZE-1:0];
reg [DWIDTH-1:0] ingress_data [MWIDTH-1:0];
wire [DWIDTH-1:0] asyn_rd_data [MWIDTH-1:0];
reg [MWIDTH*DWIDTH-1:0] asyn_rd_data_reg;
wire [MWIDTH-1:0] asyn_empty;
reg [MWIDTH*MAX_PKT_LEN-1:0] ingress_pkt_length;
reg [MWIDTH*32-1:0] ingress_dest_ip;
// 0
wire [GSIZE*MWIDTH*MWIDTH-1:0] gsm_multicast;
wire [GSIZE*MWIDTH*AWIDTH-1:0] gsm_cell_addr;
wire [GSIZE*MWIDTH-1:0] gsm_wr_en;
wire [GSIZE*MWIDTH-1:0] hmp_rd,hmp_valid,bf_free_flag;
wire [GSIZE*MWIDTH*AWIDTH-1:0] hmp_addr;
// ---------------------------------------------------------------------
// logic starts here...
// ---------------------------------------------------------------------
// the mux logic implements a 4-to-1 multiplexer running at 320M clock domain
// that cycle through each of the 4 data ports, so that they all get served in
// every cycle of the 80M clock domain, the selected data is then broadcast
// to every unit in this GSM group
// the hardware malloc module has a 2 stage pipeline,
// therefore, the data bus also need to be registered
// once more to match the pipeline processing
//
generate
for(i=0;i<MWIDTH;i=i+1)begin: INGRESS_REG
always@(posedge clk_80M)begin
if(clr_80M)
ingress_data[i] <=0;
else
ingress_data[i] <= i_ingress_data[(i+1)*DWIDTH-1:i*DWIDTH];
end
end
endgenerate
generate
for(i=0;i<MWIDTH;i=i+1) begin: DATA_PORT_MUX
asyn_fifo
#(
.DBITWIDTH(DWIDTH), // address + multicast vector + write enable
.ABITWIDTH(2) // 4 entries should be enough to accommodate the pipeline
)
ingress_data_fifo
(
// global
.clk_a(clk_80M),
.clk_b(clk_320M),
.rst_n(rst_n),
.clr_a(clr_80M),
.clr_b(clr_320M),
// FIFO write interface
.write(1'b1),
.write_data(ingress_data[i]),
// FIFO read interface
.read(~asyn_empty[i]),
.read_data(asyn_rd_data[i]),
// FIFO status signals
.empty(asyn_empty[i]),
.almost_full(),
.full()
);
always@(posedge clk_320M )begin
if(clr_320M)
asyn_rd_data_reg[(i+1)*DWIDTH-1:i*DWIDTH] <= 0;
else
asyn_rd_data_reg[(i+1)*DWIDTH-1:i*DWIDTH] <= asyn_rd_data[i];
end
end
endgenerate
// a 4-to-1 multiplexer
always@(posedge clk_320M )begin
if(clr_320M)
common_sel <= 1;
else
common_sel <= {common_sel,common_sel[MWIDTH-1]};
end
wire [DWIDTH-1:0] common_data_mux;
c_select_1ofn
#(
.num_ports(MWIDTH),
.width(DWIDTH)
)
time_mux
(
.select(common_sel),
.data_in(asyn_rd_data_reg),
.data_out(common_data_mux)
);
always@(posedge clk_320M)begin
if(clr_320M)
common_data_reg[0] <= 0;
else
common_data_reg[0] <= common_data_mux;
end
generate
for(i=1;i<GSIZE;i=i+1) begin: COMMON_DATA_PIPELINE
always@(posedge clk_320M )begin
if(clr_320M)begin
common_data_reg[i] <= 0;
end
else begin
common_data_reg[i] <= common_data_reg[i-1];
end
end
end
endgenerate
// the following generated code construct the GSM group structure.
// each group contains GSIZE (4) gsm units, each unit talks to 4
// hardware malloc logic that manages one of the 4 ingress ports
// the control data embedded in each of 4 ingress port is broadcast
// to 4 hardware malloc module. and the hardware malloc module
// decides whether the ingress data is to be dropped or buffed
// into the gsm switch unit.
generate
for(i=0;i<MWIDTH;i=i+1) begin: INGRESS_PKT_INFO_GEN
always@(*)begin
ingress_pkt_length[(i+1)*MAX_PKT_LEN-1:i*MAX_PKT_LEN] =
i_ingress_data[MAX_PKT_LEN+LOC_PKT_LEN-1+i*DWIDTH:LOC_PKT_LEN+i*DWIDTH];
ingress_dest_ip[(i+1)*32-1:i*32] =
i_ingress_data[32+LOC_DEST_IP-1+i*DWIDTH:LOC_DEST_IP+i*DWIDTH];
end
end
endgenerate
generate
for(i=0;i<GSIZE;i=i+1)begin : GSM_UNIT_GEN
/*
hw_malloc_n
#(
.NUM_PORT(MWIDTH),
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.MAX_PKT_LEN(7), // maximum packet lenght in terms of number of 16-byte cells
.HM_OFFSET(i*MWIDTH), // offset for the multicast vectore
.AWIDTH(AWIDTH) // 2 BRAM = total 512 cells, each port is allocated 128 cells
) hw_malloc_n_inst
(
// global
.clk(clk_80M),
.rst_n(rst_n),
.clr(clr_80M),
// ingress port
.i_ingress_pkt_length(ingress_pkt_length),
.i_ingress_dest_ip(ingress_dest_ip),
.i_ingress_valid(i_ingress_valid),
.i_ingress_header(i_ingress_header),
// output to GSM
.o_gsm_multicast(gsm_multicast[i]),
.o_gsm_cell_addr(gsm_cell_addr[i]),
.o_gsm_wr_en(gsm_wr_en[i]),
// input from GSM
.o_hmp_rd(hmp_rd[i]),
.i_hmp_valid(hmp_valid[i]),
.i_hmp_addr(hmp_addr[i]),
.i_bf_free_flag(bf_free_flag[i])
);
*/
for(j=0;j<MWIDTH;j=j+1) begin: HW_MALLOC_GEN
hw_malloc
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.MAX_PKT_LEN(MAX_PKT_LEN), // maximum packet lenght in terms of number of 16-byte cells
.AWIDTH(AWIDTH), // 2 BRAM = total 512 cells, each port is allocated 128 cells
.HM_OFFSET(i*MWIDTH) // offset for the multicast vectore
) hw_malloc_inst
(
// global
.clk(clk_80M),
.rst_n(rst_n),
.clr(clr_80M),
// ingress port
.i_ingress_pkt_length(ingress_pkt_length[(j+1)*MAX_PKT_LEN-1:j*MAX_PKT_LEN]),
.i_ingress_dest_ip(ingress_dest_ip[(j+1)*32-1:j*32]),
.i_ingress_valid(i_ingress_valid[j]),
.i_ingress_header(i_ingress_header[j]),
// output to GSM
.o_gsm_multicast(gsm_multicast[i*MWIDTH*MWIDTH+(j+1)*MWIDTH-1:i*MWIDTH*MWIDTH+j*MWIDTH]),
.o_gsm_cell_addr(gsm_cell_addr[i*MWIDTH*AWIDTH+(j+1)*AWIDTH-1:i*MWIDTH*AWIDTH+j*AWIDTH]),
.o_gsm_wr_en(gsm_wr_en[i*MWIDTH+j]),
// input from GSM
.o_hmp_rd(hmp_rd[i*MWIDTH+j]),
.i_hmp_valid(hmp_valid[i*MWIDTH+j]),
.i_hmp_addr(hmp_addr[i*MWIDTH*AWIDTH+(j+1)*AWIDTH-1:i*MWIDTH*AWIDTH+j*AWIDTH]),
.i_bf_free_flag(bf_free_flag[i*MWIDTH+j])
);
end
gsm_unit_ex
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.DWIDTH(DWIDTH), // data width = 16 bytes
.AWIDTH(AWIDTH), // 2 BRAM = total 512 cells, each port is allocated 128 cells
.PIPE_STAGE(i)
)gsm_unit_inst
(
// global
.clk_320M(clk_320M),
.clr_320M(clr_320M),
.clk_80M(clk_80M),
.clr_80M(clr_80M),
.rst_n(rst_n),
// ingress malloc ports
.i_wr_en(gsm_wr_en[(i+1)*MWIDTH-1:i*MWIDTH]),
.i_wr_addr(gsm_cell_addr[(i+1)*MWIDTH*AWIDTH-1:i*MWIDTH*AWIDTH]),
.i_multicast(gsm_multicast[(i+1)*MWIDTH*MWIDTH-1:i*MWIDTH*MWIDTH]),
// egress ports
.i_egress_rd(i_egress_rd[(i+1)*MWIDTH-1:i*MWIDTH]),
.o_egress_valid(o_egress_valid[(i+1)*MWIDTH-1:i*MWIDTH]),
.o_egress_data(o_egress_data[(i+1)*MWIDTH*DWIDTH-1:i*MWIDTH*DWIDTH]),
// buffer free interface
.i_hmp_rd(hmp_rd[(i+1)*MWIDTH-1:i*MWIDTH]), // read a pointer from the Hardware Malloc Pipe
.o_hmp_valid(hmp_valid[(i+1)*MWIDTH-1:i*MWIDTH]),// Hardware Malloc Pipe is not empty and has available pointer
.o_hmp_addr(hmp_addr[(i+1)*MWIDTH*AWIDTH-1:i*MWIDTH*AWIDTH]), // the pointer to the available buffer space
.o_bf_free_flag(bf_free_flag[(i+1)*MWIDTH-1:i*MWIDTH]), // signal that a pointer has just been freed
// common data bus (at 320Mhz clock domain)
//.i_common_sel(common_sel),
.i_common_wr_data(common_data_reg[i])
);
end // end for
endgenerate
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_unit.v
// Description : grouped-share-memory switch memory unit
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-20 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_unit
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter LOG_MWIDTH = 2,
parameter DWIDTH = 128, // data width = 16 bytes
parameter AWIDTH = 7 // 2 BRAM = total 512 cells, each port is allocated 128 cells
)
(
// global
input wire clk_320M,
input wire clr_320M,
input wire clk_80M,
input wire clr_80M,
input wire rst_n,
// ingress malloc ports
input wire i_wr_en0,
input wire [AWIDTH-1:0] i_wr_addr0,
input wire [MWIDTH-1:0] i_multicast0,
input wire i_wr_en1,
input wire [AWIDTH-1:0] i_wr_addr1,
input wire [MWIDTH-1:0] i_multicast1,
input wire i_wr_en2,
input wire [AWIDTH-1:0] i_wr_addr2,
input wire [MWIDTH-1:0] i_multicast2,
input wire i_wr_en3,
input wire [AWIDTH-1:0] i_wr_addr3,
input wire [MWIDTH-1:0] i_multicast3,
// egress ports
input wire i_egress_rd0,
output wire o_egress_valid0,
output wire [DWIDTH-1:0] o_egress_data0,
input wire i_egress_rd1,
output wire o_egress_valid1,
output wire [DWIDTH-1:0] o_egress_data1,
input wire i_egress_rd2,
output wire o_egress_valid2,
output wire [DWIDTH-1:0] o_egress_data2,
input wire i_egress_rd3,
output wire o_egress_valid3,
output wire [DWIDTH-1:0] o_egress_data3,
// buffer free interface
output wire o_buf_free0,
output wire [AWIDTH-1:0] o_buf_free_addr0,
output wire o_buf_free1,
output wire [AWIDTH-1:0] o_buf_free_addr1,
output wire o_buf_free2,
output wire [AWIDTH-1:0] o_buf_free_addr2,
output wire o_buf_free3,
output wire [AWIDTH-1:0] o_buf_free_addr3,
// common data bus (at 320Mhz clock domain)
input wire [MWIDTH-1:0] i_common_sel,
input wire [DWIDTH-1:0] i_common_wr_data
);
// ---------------------------------------------------------------------
// wire, registers and integer
// ---------------------------------------------------------------------
genvar i;
wire [AWIDTH+MWIDTH:0] ingress_data[MWIDTH-1:0];
wire [AWIDTH+MWIDTH:0] asyn_rd_data[MWIDTH-1:0];
wire [MWIDTH-1:0] asyn_empty;
reg [AWIDTH+MWIDTH+LOG_MWIDTH:0] gsm_ctl_data;
wire gsm_wr_en;
wire [AWIDTH+LOG_MWIDTH-1:0] gsm_wr_addr;
wire [MWIDTH-1:0] gsm_multicast;
wire [MWIDTH-1:0] egress_wr_sel;
wire [DWIDTH-1:0] egress_wr_data;
wire [DWIDTH-1:0] egress_rd_data[MWIDTH-1:0];
wire [MWIDTH-1:0] egress_empty, egress_almost_full;
wire [MWIDTH-1:0] egress_rd;
wire [MWIDTH-1:0] buf_free_sel, buf_free_empty, buf_free_full;
wire [AWIDTH+LOG_MWIDTH-1:0] buf_free_addr;
wire [AWIDTH-1:0] buf_out_addr[MWIDTH-1:0];
// ---------------------------------------------------------------------
// logic starts here...
// ---------------------------------------------------------------------
assign ingress_data[0] = {i_wr_addr0,i_multicast0,i_wr_en0};
assign ingress_data[1] = {i_wr_addr1,i_multicast1,i_wr_en1};
assign ingress_data[2] = {i_wr_addr2,i_multicast2,i_wr_en2};
assign ingress_data[3] = {i_wr_addr3,i_multicast3,i_wr_en3};
generate
for(i=0;i<MWIDTH;i=i+1) begin: CLOCK_DOMAIN_CROSSING
asyn_fifo
#(
.DBITWIDTH(AWIDTH+MWIDTH), // address + multicast vector + write enable
.ABITWIDTH(2) // 4 entries should be enough to accommodate the pipeline
)
ingress_ctrl
(
// global
.clk_a(clk_80M),
.clk_b(clk_320M),
.rst_n(rst_n),
.clr_a(clr_80M),
.clr_b(clr_320M),
// FIFO write interface
.write(1'b1),
.write_data(ingress_data[i]),
// FIFO read interface
.read(~asyn_empty[i]),
.read_data(asyn_rd_data[i]),
// FIFO status signals
.empty(asyn_empty[i]),
.almost_full(),
.full()
);
end
endgenerate
// a 4-to-1 multiplexer
always@(posedge clk_320M or negedge rst_n)begin
if(!rst_n)begin
gsm_ctl_data <= 0;
end
else if(clr_320M)begin
gsm_ctl_data <= 0;
end
else
case (i_common_sel)
4'b0001: gsm_ctl_data <= {2'b00,asyn_rd_data[0]};
4'b0010: gsm_ctl_data <= {2'b01,asyn_rd_data[1]};
4'b0100: gsm_ctl_data <= {2'b10,asyn_rd_data[2]};
4'b1000: gsm_ctl_data <= {2'b11,asyn_rd_data[3]};
endcase
end
assign gsm_wr_en = gsm_ctl_data[0];
assign gsm_multicast = gsm_ctl_data[MWIDTH:1];
assign gsm_wr_addr = gsm_ctl_data[AWIDTH+MWIDTH+LOG_MWIDTH:MWIDTH+1];
// centralized memory
gsm_ram
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.LOG_MWIDTH(LOG_MWIDTH),
.DWIDTH(DWIDTH), // data width = 16 bytes
.AWIDTH(AWIDTH+LOG_MWIDTH) // 2 BRAM = total 512 cells
)
central_ram
(
// global
.clk(clk_320M),
.rst_n(rst_n),
.clr(clr_320M),
// input port
.i_wr_en(gsm_wr_en),
.i_wr_addr(gsm_wr_addr),
.i_wr_data(i_common_wr_data),
.i_multicast(gsm_multicast),
// output port
.i_egress_stall(egress_almost_full),
.o_egress_sel(egress_wr_sel),
.o_egress_data(egress_wr_data),
// buffer free
.o_buf_free(buf_free),
.o_buf_free_addr(buf_free_addr)
);
// egress ports
assign egress_rd = {i_egress_rd3,i_egress_rd2,i_egress_rd1,i_egress_rd0};
generate
for(i=0;i<MWIDTH;i=i+1) begin: EGRESS_PORTS
asyn_fifo
#(
.DBITWIDTH(DWIDTH),
.ABITWIDTH(4), // 16 entries
.AF_THRESHOLD(4) // set the almost full threshold to be 4
)
egress_port
(
// global
.clk_a(clk_320M),
.clk_b(clk_80M),
.rst_n(rst_n),
.clr_a(clr_320M),
.clr_b(clr_80M),
// FIFO write interface
.write(egress_wr_sel[i]),
.write_data(egress_wr_data),
// FIFO read interface
.read(egress_rd[i]),
.read_data(egress_rd_data[i]),
// FIFO status signals
.empty(egress_empty[i]),
.almost_full(egress_almost_full[i]),
.full()
);
end
endgenerate
assign o_egress_valid0 = ~egress_empty[0];
assign o_egress_valid1 = ~egress_empty[1];
assign o_egress_valid2 = ~egress_empty[2];
assign o_egress_valid3 = ~egress_empty[3];
assign o_egress_data0 = egress_rd_data[0];
assign o_egress_data1 = egress_rd_data[1];
assign o_egress_data2 = egress_rd_data[2];
assign o_egress_data3 = egress_rd_data[3];
// buffer free interface logic
generate
for(i=0;i<MWIDTH;i=i+1) begin: BUFFER_FREE
asyn_fifo
#(
.DBITWIDTH(DWIDTH),
.ABITWIDTH(4) // 16 entries
)
buf_free
(
// global
.clk_a(clk_320M),
.clk_b(clk_80M),
.rst_n(rst_n),
.clr_a(clr_320M),
.clr_b(clr_80M),
// FIFO write interface
.write(buf_free_sel[i] & ~ buf_free_full[i]),
.write_data(buf_free_addr),
// FIFO read interface
.read(~buf_free_empty[i]),
.read_data(buf_out_addr[i]),
// FIFO status signals
.empty(buf_free_empty[i]),
.almost_full(),
.full(buf_free_full)
);
end
endgenerate
assign o_buf_free0 = ~buf_free_empty[0];
assign o_buf_free1 = ~buf_free_empty[1];
assign o_buf_free2 = ~buf_free_empty[2];
assign o_buf_free3 = ~buf_free_empty[3];
assign o_buf_free_addr0 = buf_out_addr[0];
assign o_buf_free_addr1 = buf_out_addr[1];
assign o_buf_free_addr2 = buf_out_addr[2];
assign o_buf_free_addr3 = buf_out_addr[3];
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_unit.v
// Description : grouped-share-memory switch memory unit
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-20 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_unit_ex
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter DWIDTH = 128, // data width = 16 bytes
parameter AWIDTH = 7, // 2 BRAM = total 512 cells, each port is allocated 128 cells
parameter PIPE_STAGE = 0
)
(
// global
input wire clk_320M,
input wire clr_320M,
input wire clk_80M,
input wire clr_80M,
input wire rst_n,
// ingress malloc ports
input wire [MWIDTH-1:0] i_wr_en,
input wire [MWIDTH*AWIDTH-1:0] i_wr_addr,
input wire [MWIDTH*MWIDTH-1:0] i_multicast,
// egress ports
input wire [MWIDTH-1:0] i_egress_rd,
output wire [MWIDTH-1:0] o_egress_valid,
output wire [MWIDTH*DWIDTH-1:0] o_egress_data,
// buffer free interface
input wire [MWIDTH-1:0] i_hmp_rd, // read a pointer from the Hardware Malloc Pipe
output wire [MWIDTH-1:0] o_hmp_valid, // Hardware Malloc Pipe is not empty and has available pointer
output wire [MWIDTH*AWIDTH-1:0] o_hmp_addr, // the pointer to the available buffer space
output wire [MWIDTH-1:0] o_bf_free_flag, // signal that a pointer has just been freed
// common data bus (at 320Mhz clock domain)
//input wire [MWIDTH-1:0] i_common_sel,
input wire [DWIDTH-1:0] i_common_wr_data
);
`include "c_functions.v"
localparam LOG_MWIDTH = clogb(MWIDTH);
localparam BRAM_RD_DELAY = 2;
localparam GSM_CTRL_WIDTH = AWIDTH+MWIDTH+LOG_MWIDTH+1;
// ---------------------------------------------------------------------
// wire, registers and genvar
// ---------------------------------------------------------------------
genvar i;
reg [MWIDTH-1:0] gsu_common_sel;
reg [AWIDTH+MWIDTH:0] ingress_data[MWIDTH-1:0];
wire [AWIDTH+MWIDTH:0] asyn_rd_data[MWIDTH-1:0];
reg [MWIDTH*GSM_CTRL_WIDTH-1:0] asyn_rd_data_reg;
wire [MWIDTH-1:0] asyn_empty;
reg [GSM_CTRL_WIDTH-1:0] gsm_ctl_data_reg[PIPE_STAGE:0];
wire [GSM_CTRL_WIDTH-1:0] gsm_ctl_data;
wire gsm_wr_en;
wire [AWIDTH+LOG_MWIDTH-1:0] gsm_wr_addr;
wire [MWIDTH-1:0] gsm_multicast;
reg [DWIDTH-1:0] gsm_wr_data;
wire [MWIDTH-1:0] egress_wr_sel;
wire [DWIDTH-1:0] egress_wr_data;
wire [DWIDTH-1:0] egress_rd_data[MWIDTH-1:0];
wire [MWIDTH-1:0] egress_empty, egress_almost_full;
wire [MWIDTH-1:0] egress_rd;
wire [MWIDTH-1:0] buf_free_sel, buf_free_empty, buf_free_full;
wire [AWIDTH+LOG_MWIDTH-1:0] buf_free_addr;
wire [AWIDTH-1:0] buf_out_addr[MWIDTH-1:0];
wire buf_free;
// ---------------------------------------------------------------------
// logic starts here...
// ---------------------------------------------------------------------
generate
for(i=0;i<MWIDTH;i=i+1) begin: CLOCK_DOMAIN_CROSSING
always@(*)begin
ingress_data[i] = {i_wr_addr[(i+1)*AWIDTH-1:i*AWIDTH],i_multicast[(i+1)*MWIDTH-1:i*MWIDTH],i_wr_en[i]};
end
asyn_fifo
#(
.DBITWIDTH(AWIDTH+MWIDTH+1), // address + multicast vector + write enable
.ABITWIDTH(2) // 4 entries should be enough to cross clock domain
)
ingress_ctrl
(
// global
.clk_a(clk_80M),
.clk_b(clk_320M),
.rst_n(rst_n),
.clr_a(clr_80M),
.clr_b(clr_320M),
// FIFO write interface
.write(1'b1),
.write_data(ingress_data[i]),
// FIFO read interface
.read(~asyn_empty[i]),
.read_data(asyn_rd_data[i]),
// FIFO status signals
.empty(asyn_empty[i]),
.almost_full(),
.full()
);
always@(posedge clk_320M )begin
if(clr_320M)
asyn_rd_data_reg[(i+1)*GSM_CTRL_WIDTH-1:i*GSM_CTRL_WIDTH] <= 0;
else
asyn_rd_data_reg[(i+1)*GSM_CTRL_WIDTH-1:i*GSM_CTRL_WIDTH] <= {i,asyn_rd_data[i]};
end
end
endgenerate
// a 4-to-1 multiplexer
always@(posedge clk_320M )begin
if(clr_320M)
gsu_common_sel <= 1;
else
gsu_common_sel <= {gsu_common_sel,gsu_common_sel[MWIDTH-1]};
end
wire [GSM_CTRL_WIDTH-1:0] gsm_ctl_data_mux;
c_select_1ofn
#(
.num_ports(MWIDTH),
.width(GSM_CTRL_WIDTH)
)
time_mux
(
.select(gsu_common_sel),
.data_in(asyn_rd_data_reg),
.data_out(gsm_ctl_data_mux)
);
always@(posedge clk_320M )begin
if(clr_320M)begin
gsm_ctl_data_reg[0] <= 0;
end
else begin
gsm_ctl_data_reg[0] <= gsm_ctl_data_mux;
end
end
generate
for(i=1;i<=PIPE_STAGE;i=i+1) begin: GSM_CTL_DATA_PIPE
always@(posedge clk_320M )begin
if(clr_320M)begin
gsm_ctl_data_reg[i] <= 0;
end
else
gsm_ctl_data_reg[i] <= gsm_ctl_data_reg[i-1];
end
end
endgenerate
assign gsm_ctl_data = gsm_ctl_data_reg[PIPE_STAGE];
assign gsm_wr_en = gsm_ctl_data[0];
assign gsm_multicast = gsm_ctl_data[MWIDTH:1];
assign gsm_wr_addr = gsm_ctl_data[AWIDTH+MWIDTH+LOG_MWIDTH:MWIDTH+1];
// centralized memory
gsm_ram
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.DWIDTH(DWIDTH), // data width = 16 bytes
.AWIDTH(AWIDTH+LOG_MWIDTH) // 2 BRAM = total 512 cells
)
central_ram
(
// global
.clk(clk_320M),
.rst_n(rst_n),
.clr(clr_320M),
// input port
.i_wr_en(gsm_wr_en),
.i_wr_addr(gsm_wr_addr),
.i_wr_data(i_common_wr_data),
.i_multicast(gsm_multicast),
// output port
.i_egress_stall(egress_almost_full),
.o_egress_sel(egress_wr_sel),
.o_egress_data(egress_wr_data),
// buffer free
.o_buf_free(buf_free),
.o_buf_free_addr(buf_free_addr)
);
// egress ports
generate
for(i=0;i<MWIDTH;i=i+1) begin: EGRESS_PORTS
asyn_fifo
#(
.DBITWIDTH(DWIDTH),
.ABITWIDTH(4), // 16 entries
.AF_THRESHOLD(4) // set the almost full threshold to be 4
)
egress_port
(
// global
.clk_a(clk_320M),
.clk_b(clk_80M),
.rst_n(rst_n),
.clr_a(clr_320M),
.clr_b(clr_80M),
// FIFO write interface
.write(egress_wr_sel[i]),
.write_data(egress_wr_data),
// FIFO read interface
.read(i_egress_rd[i]),
.read_data(o_egress_data[(i+1)*DWIDTH-1:i*DWIDTH]),
// FIFO status signals
.empty(egress_empty[i]),
.almost_full(egress_almost_full[i]),
.full()
);
end
endgenerate
assign o_egress_valid = ~egress_empty;
// buffer free interface logic
reg [AWIDTH-1:0] bf_rd_ptr[MWIDTH-1:0];
reg [AWIDTH-1:0] bf_wr_ptr[MWIDTH-1:0];
reg [AWIDTH:0] bf_dcnt[MWIDTH-1:0];
reg [MWIDTH-1:0] bf_read, bf_write;
reg [AWIDTH+LOG_MWIDTH-1:0] bf_wr_addr, bf_rd_addr;
reg [AWIDTH-1:0] bf_wr_data;
wire [AWIDTH-1:0] bf_rd_data;
wire [10:0] bf_rd_tmp;
wire [MWIDTH-1:0] bf_empty, bf_full;
reg [MWIDTH-1:0] bf_rd_sel;
reg [MWIDTH-1:0] bf_rd_delay[BRAM_RD_DELAY:0];
reg [MWIDTH-1:0] bf_write_delay[BRAM_RD_DELAY:0];
wire [MWIDTH-1:0] bf_write_cross;
wire [MWIDTH-1:0] hmp_write, hmp_read, hmp_empty, hmp_stall;
wire [AWIDTH-1:0] hmp_rd_data[MWIDTH-1:0];
wire [MWIDTH-1:0] bf_free_flag;
reg bf_rd_en;
// generate the read pointer, write pointer and data counter
// calculation logic
generate
for(i=0;i<MWIDTH;i=i+1) begin: BUFFER_FREE_FIFOS
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_ptr[i] <= 0;
else if (bf_read[i])
bf_rd_ptr[i] <= bf_rd_ptr[i] + 1;
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_dcnt[i] <= 0;
else if (bf_write[i] & ~bf_read[i])
bf_dcnt[i] <= bf_dcnt[i] + 1;
else if(~bf_write[i] & bf_read[i])
bf_dcnt[i] <= bf_dcnt[i] - 1;
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_wr_ptr[i] <= 0;
else if (bf_write[i])
bf_wr_ptr[i] <= bf_wr_ptr[i] + 1;
end
assign bf_empty[i] = ~(|bf_dcnt[i]);
//assign bf_full[i] = bf_dcnt[MWIDTH];
end // end for
endgenerate
// bf write
always@(posedge clk_320M )begin
if(clr_320M)
bf_write <= 0;
else begin
bf_write <= {{MWIDTH{1'b0}},buf_free} << (buf_free_addr[AWIDTH+LOG_MWIDTH-1:AWIDTH]);
end
end
wire [MWIDTH-1:0] bf_wr_sel;
c_decode
#(
.num_ports(MWIDTH)
)
bf_decode_inst
(
.data_in(buf_free_addr[AWIDTH+LOG_MWIDTH-1:AWIDTH]),
.data_out(bf_wr_sel)
);
reg [AWIDTH*MWIDTH-1:0] bf_wr_ptr_array;
generate
for(i=0;i<MWIDTH;i=i+1) begin: BF_WR_PTR_ARRAY_GEN
always@(*)
bf_wr_ptr_array[(i+1)*AWIDTH-1:i*AWIDTH] = bf_wr_ptr[i];
end
endgenerate
wire [AWIDTH-1:0] bf_wr_addr_mux;
c_select_1ofn
#(
.num_ports(MWIDTH),
.width(AWIDTH)
)
bf_wr_addr_mux_inst
(
.select(bf_wr_sel),
.data_in(bf_wr_ptr_array),
.data_out(bf_wr_addr_mux)
);
always@(posedge clk_320M )begin
if(clr_320M)
bf_wr_addr <= 0;
else begin
bf_wr_addr <= {buf_free_addr[AWIDTH+LOG_MWIDTH-1:AWIDTH],bf_wr_addr_mux};
end
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_wr_data <= 0;
else
bf_wr_data <= buf_free_addr[AWIDTH-1:0];
end
// bf read
reg [AWIDTH*MWIDTH-1:0] bf_rd_ptr_array;
generate
for(i=0;i<MWIDTH;i=i+1) begin: BF_RD_PTR_ARRAY_GEN
always@(*)
bf_rd_ptr_array[(i+1)*AWIDTH-1:i*AWIDTH] = bf_rd_ptr[i];
end
endgenerate
wire [AWIDTH-1:0] bf_rd_addr_mux;
c_select_1ofn
#(
.num_ports(MWIDTH),
.width(AWIDTH)
)
bf_rd_addr_mux_inst
(
.select(bf_rd_sel),
.data_in(bf_rd_ptr_array),
.data_out(bf_rd_addr_mux)
);
wire [LOG_MWIDTH-1:0] bf_rd_sel_encode;
c_encode
#(
.num_ports(MWIDTH)
)
bf_rd_encode
(
.data_in(bf_rd_sel),
.data_out(bf_rd_sel_encode)
);
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_addr <= 0;
else begin
bf_rd_addr <= {bf_rd_sel_encode, bf_rd_addr_mux};
end
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_sel <= 1;
else
bf_rd_sel <= {bf_rd_sel,bf_rd_sel[MWIDTH-1]};
end
always@(*)begin
bf_read = bf_rd_sel & ~hmp_stall & ~bf_empty;
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_en <= 1;
else
bf_rd_en <= |bf_read;
end
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_delay[0] <= 0;
else
bf_rd_delay[0] <= bf_read;
end
generate
for(i=1;i<=BRAM_RD_DELAY;i=i+1)begin:BRAM_READ_DELAY
always@(posedge clk_320M )begin
if(clr_320M)
bf_rd_delay[i] <= 0;
else
bf_rd_delay[i] <= bf_rd_delay[i-1];
end
end// end for
endgenerate
// bf write delay signal is delayed so that the back end
// logic will not underflow the buffer-freed address pipe
always@(posedge clk_320M )begin
if(clr_320M)
bf_write_delay[0] <= 0;
else
bf_write_delay[0] <= bf_write;
end
generate
for(i=1;i<=BRAM_RD_DELAY;i=i+1)begin:BRAM_READ_DELAY_2
always@(posedge clk_320M )begin
if(clr_320M)
bf_write_delay[i] <= 0;
else
bf_write_delay[i] <= bf_write_delay[i-1];
end
end// end for
endgenerate
infer_sdpram
#(
.DWIDTH(AWIDTH),
.AWIDTH(AWIDTH+LOG_MWIDTH) // address width of the SRAM
) bf_fifos
(
// global
.clk_a(clk_320M),
.clk_b(clk_320M),
// write port a interface
.en_a(|bf_write),
.write_a(|bf_write),
.wr_data_a(bf_wr_data),
.addr_a(bf_wr_addr),
// read port b interface
.en_b(bf_rd_en),
.addr_b(bf_rd_addr),
.rd_data_b(bf_rd_data)
);
//===================================================================
assign hmp_write = bf_rd_delay[BRAM_RD_DELAY];
assign bf_write_cross = bf_write_delay[BRAM_RD_DELAY];
generate
for(i=0;i<MWIDTH;i=i+1) begin: HMP_GEN
asyn_fifo
#(
.DBITWIDTH(AWIDTH),
.ABITWIDTH(4) // 16 entries
)
hw_malloc_pipe
(
// global
.clk_a(clk_320M),
.clk_b(clk_80M),
.rst_n(rst_n),
.clr_a(clr_320M),
.clr_b(clr_80M),
// FIFO write interface
.write(hmp_write[i]),
.write_data(bf_rd_data),
// FIFO read interface
.read(i_hmp_rd[i]&~hmp_empty[i]),
.read_data(o_hmp_addr[(i+1)*AWIDTH-1:i*AWIDTH]),
// FIFO status signals
.empty(hmp_empty[i]),
.almost_full(hmp_stall[i]),
.full()
);
clk_domain_cross buf_free_flag
(
.sigin(bf_write_cross[i]),
.clkin(clk_320M),
.clr_in(clr_320M),
.clr_out(clr_80M),
.clkout(clk_80M),
.sigout(o_bf_free_flag[i]),
.full()
);
end
endgenerate
assign o_hmp_valid = ~hmp_empty;
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : hw_malloc.v
// Description : hardware malloc module, managing the memory space for packet cells
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-23 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module hw_malloc
#(
parameter MWIDTH = 4, // multicast width = 4 output ports
parameter AWIDTH = 7, // 2 BRAM = total 512 cells, each port is allocated 128 cells
parameter MAX_PKT_LEN = 7, // maximum packet lenght in terms of number of 16-byte cells
parameter HM_OFFSET = 0 // offset for the multicast vectore
)
(
// global
input wire clk,
input wire rst_n,
input wire clr,
// ingress port
input wire [MAX_PKT_LEN-1:0] i_ingress_pkt_length,
input wire [31:0] i_ingress_dest_ip,
input wire i_ingress_valid,
input wire i_ingress_header,
// output to GSM
output wire [MWIDTH-1:0] o_gsm_multicast,
output wire [AWIDTH-1:0] o_gsm_cell_addr,
output wire o_gsm_wr_en,
// input from GSM
output wire o_hmp_rd,
input wire i_hmp_valid,
input wire [AWIDTH-1:0] i_hmp_addr,
input wire i_bf_free_flag
);
// ---------------------------------------------------------------------
// defines and local parameters
// ---------------------------------------------------------------------
`include "c_functions.v"
localparam LOG_MWIDTH = clogb(MWIDTH);
localparam INIT_CELL_CNT = 2**AWIDTH;
// ---------------------------------------------------------------------
// wire, registers and integer
// ---------------------------------------------------------------------
reg [AWIDTH:0] avail_cell_cnt;
reg [MWIDTH-1:0] multicast_vec;
reg [AWIDTH:0] init_addr_gen;
wire malloc;
wire has_room;
reg pkt_drop;
reg [AWIDTH-1:0] alloc_addr;
reg alloc_valid;
wire [AWIDTH-1:0] alloc_addr_sel;
// ---------------------------------------------------------------------
// logic starts here...
// ---------------------------------------------------------------------
// alaivable cell address counter, used to decide if an incoming packet
// can be accomodated into the buffer or needs to be dropped
always@(posedge clk )begin
if(clr)
avail_cell_cnt <= INIT_CELL_CNT;
else if(malloc & ~i_bf_free_flag)
avail_cell_cnt <= avail_cell_cnt - 1;
else if(~malloc & i_bf_free_flag)
avail_cell_cnt <= avail_cell_cnt + 1;
end
// init cell address generator: on reset, the allocated cell address will restart
// from 0
always@(posedge clk )begin
if(clr)
init_addr_gen <= 0;
else if(malloc & ~init_addr_gen[AWIDTH])
init_addr_gen <= init_addr_gen + 1;
end
// if current packet is a good packet, we will alloc a cell address for it
always@(posedge clk )begin
if(clr)
pkt_drop <= 0;
else if(i_ingress_header)
pkt_drop <= ~has_room;
end
//assign has_room = ( (i_ingress_pkt_length <= avail_cell_cnt) & (~init_addr_gen[AWIDTH] | i_hmp_valid) )?1'b1:1'b0; // the second condition is to prevent underflow the address asyn_fifo
assign has_room = ( i_ingress_pkt_length <= avail_cell_cnt )?1'b1:1'b0;
assign malloc = i_ingress_valid && (i_ingress_header? (has_room & (|i_ingress_dest_ip[HM_OFFSET+MWIDTH-1:HM_OFFSET])) : (~pkt_drop & (|multicast_vec)));
always@(posedge clk )begin
if(clr)begin
alloc_valid <= 0;
alloc_addr <= 0;
end
else begin
alloc_valid <= malloc;
alloc_addr <= alloc_addr_sel;
end
end
assign o_hmp_rd = malloc & init_addr_gen[AWIDTH];
assign alloc_addr_sel = init_addr_gen[AWIDTH] ? i_hmp_addr : init_addr_gen;
// use one-hot coding for the multicast vector to indicate which output port
// this cell is going to be sent
always@(posedge clk )begin
if(clr)
multicast_vec <= 0;
else if(i_ingress_header)
multicast_vec <= i_ingress_dest_ip[HM_OFFSET+MWIDTH-1:HM_OFFSET];
end
// output signals
assign o_gsm_wr_en = alloc_valid;
assign o_gsm_cell_addr = alloc_addr;
assign o_gsm_multicast = multicast_vec;
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : hw_malloc_n.v
// Description : multi_port hardware memory allocation module
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2012-07-03 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module hw_malloc_n
#(
parameter NUM_PORT = 4,
parameter MWIDTH = 4,
parameter AWIDTH = 7,
parameter HM_OFFSET = 0,
parameter MAX_PKT_LEN = 7
)
(
// global
input wire clk_80M,
input wire rst_n,
input wire clr_80M,
// ingress port
input wire [NUM_PORT*MAX_PKT_LEN-1:0] i_ingress_pkt_length,
input wire [NUM_PORT*32-1:0] i_ingress_dest_ip,
input wire [NUM_PORT-1:0] i_ingress_valid,
input wire [NUM_PORT-1:0] i_ingress_header,
// output to GSM
output wire [NUM_PORT*MWIDTH-1:0] o_gsm_multicast,
output wire [NUM_PORT*AWIDTH-1:0] o_gsm_cell_addr,
output wire [NUM_PORT-1:0] o_gsm_wr_en,
// input from GSM
output wire [NUM_PORT-1:0] o_hmp_rd,
input wire [NUM_PORT-1:0] i_hmp_valid,
input wire [NUM_PORT*AWIDTH-1:0] i_hmp_addr,
input wire [NUM_PORT-1:0] i_bf_free_flag
);
generate
genvar i;
for(i=0;i<NUM_PORT;i=i+1) begin: HW_MALLOC_GEN
hw_malloc
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.MAX_PKT_LEN(MAX_PKT_LEN), // maximum packet lenght in terms of number of 16-byte cells
.AWIDTH(AWIDTH), // 2 BRAM = total 512 cells, each port is allocated 128 cells
.HM_OFFSET(HM_OFFSET) // offset for the multicast vectore
) hw_malloc_inst0
(
// global
.clk(clk_80M),
.rst_n(rst_n),
.clr(clr_80M),
// ingress port
.i_ingress_pkt_length(i_ingress_pkt_length[(i+1)*MAX_PKT_LEN-1:i*MAX_PKT_LEN]),
.i_ingress_dest_ip(i_ingress_dest_ip[(i+1)*32-1:i*32]),
.i_ingress_valid(i_ingress_valid[i]),
.i_ingress_header(i_ingress_header[i]),
// output to GSM
.o_gsm_multicast(o_gsm_multicast[(i+1)*MWIDTH-1:i*MWIDTH]),
.o_gsm_cell_addr(o_gsm_cell_addr[(i+1)*AWIDTH-1:i*AWIDTH]),
.o_gsm_wr_en(o_gsm_wr_en[i]),
// input from GSM
.o_hmp_rd(o_hmp_rd[i]),
.i_hmp_valid(i_hmp_valid[i]),
.i_hmp_addr(i_hmp_addr[(i+1)*AWIDTH-1:i*AWIDTH]),
.i_bf_free_flag(i_bf_free_flag[i])
);
end
endgenerate
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : infer_ram_wr.v
// Description : infer a write through ram
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2012-07-03 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module infer_ram_wt
#(
parameter DWIDTH = 18, // data width of the SRAM, 36 bit when configured to be SDP BRAM, otherwise 18 bit wide
parameter AWIDTH = 10 // address width of the SRAM
)
(
// global
input wire clk_a,
input wire clk_b,
// port a interface
input wire en_a,
input wire write_a,
input wire [DWIDTH-1:0] din_a,
input wire [AWIDTH-1:0] addr_a,
//output wire [DWIDTH-1:0] dout_a,
// port b interface
input wire en_b,
input wire write_b,
input wire [DWIDTH-1:0] din_b,
input wire [AWIDTH-1:0] addr_b,
output wire [DWIDTH-1:0] dout_b
);
alt_infer_ram_wt
#(
.DWIDTH(DWIDTH),
.AWIDTH(AWIDTH)
)
alt_infer_ram_wt_inst (
.clk_a(clk_a),
.clk_b(clk_b),
.write_a(en_a&write_a),
.din_a(din_a),
.addr_a(addr_a),
//.dout_a(dout_a),
.write_b(en_b&write_b),
.din_b(din_b),
.addr_b(addr_b),
.dout_b(dout_b)
);
endmodule
//Fix for altera ram inference
//Quartus does not like both write enable and general enables
module alt_infer_ram_wt
#(
parameter DWIDTH = 18, // data width of the SRAM, 36 bit when configured to be SDP BRAM, otherwise 18 bit wide
parameter AWIDTH = 10 // address width of the SRAM
)
(
// global
input wire clk_a,
input wire clk_b,
// port a interface
// input wire en_a,
input wire write_a,
input wire [DWIDTH-1:0] din_a,
input wire [AWIDTH-1:0] addr_a,
//output reg [DWIDTH-1:0] dout_a,
// port b interface
// input wire en_b,
input wire write_b,
input wire [DWIDTH-1:0] din_b,
input wire [AWIDTH-1:0] addr_b,
output reg [DWIDTH-1:0] dout_b
);
//(* RAM_STYLE="BLOCK" *)
(* ramstyle = "M9K" *) reg [DWIDTH-1:0] generic_ram [(2**AWIDTH)-1:0];
always @(posedge clk_a)begin
// if (en_a) begin
if (write_a)begin
generic_ram[addr_a] <= din_a;
//dout_a <= din_a;
end
//else
//dout_a <= generic_ram[addr_a];
// end
end
always @(posedge clk_b)begin
// if (en_b) begin
if (write_b)begin
generic_ram[addr_b] <= din_b;
dout_b <= din_b;
end
else
dout_b <= generic_ram[addr_b];
// end
end
endmodule
|
module malloc_core_infer
#(
parameter DWIDTH_A = 4,
parameter DWIDTH_B = 1,
parameter AWIDTH_A = 9,
parameter AWIDTH_B = 11
)
(
input clka,
input wea,
input [AWIDTH_A-1:0] addra,
input [DWIDTH_A-1:0] dina,
//output [DWIDTH_A-1:0] douta,
input clkb,
input rstb,
input web,
input [AWIDTH_B-1:0] addrb,
input [DWIDTH_B-1:0] dinb,
output [DWIDTH_A-1:0] doutb
);
`include "c_functions.v"
localparam PORT_RATIO = (DWIDTH_A/DWIDTH_B);
localparam LOW_ADDR_WIDTH = clogb(PORT_RATIO);
wire [PORT_RATIO-1:0] enb;
c_decode
#(
.num_ports(PORT_RATIO)
)
ram_sel
(
.data_in(addrb[LOW_ADDR_WIDTH-1:0]),
.data_out(enb)
);
genvar i;
generate
for(i=0;i<PORT_RATIO;i=i+1)begin:WRITE_PORT_A
infer_ram_wt
#(
.DWIDTH(DWIDTH_B),
.AWIDTH(AWIDTH_A)
)
bit_vec
(
.clk_a(clka),
.clk_b(clkb),
.en_a(wea),
.write_a(wea),
.din_a(dina[(i+1)*DWIDTH_B-1:i*DWIDTH_B]),
.addr_a(addra),
.dout_a(),
.en_b(enb[i]),
.write_b(web),
.addr_b(addrb[AWIDTH_B-1:LOW_ADDR_WIDTH]),
.din_b(dinb),
.dout_b(doutb[(i+1)*DWIDTH_B-1:i*DWIDTH_B])
);
end
endgenerate
endmodule
|
// $Id: c_constants.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// global constant definitions
//==============================================================================
//------------------------------------------------------------------------------
// reset handling
//------------------------------------------------------------------------------
// asynchronous reset
`define RESET_TYPE_ASYNC 0
// synchronous reset
`define RESET_TYPE_SYNC 1
`define RESET_TYPE_LAST `RESET_TYPE_SYNC
//------------------------------------------------------------------------------
// arbiter types
//------------------------------------------------------------------------------
// round-robin arbiter
`define ARBITER_TYPE_ROUND_ROBIN 0
// matrix arbiter
`define ARBITER_TYPE_MATRIX 1
// DesignWare first-come, first-serve arbiter
`define ARBITER_TYPE_DW_FCFS 2
`define ARBITER_TYPE_LAST `ARBITER_TYPE_DW_FCFS
//------------------------------------------------------------------------------
// error checker capture more
//------------------------------------------------------------------------------
// disable error reporting
`define ERROR_CAPTURE_MODE_NONE 0
// don't hold errors
`define ERROR_CAPTURE_MODE_NO_HOLD 1
// capture first error only (subsequent errors are blocked)
`define ERROR_CAPTURE_MODE_HOLD_FIRST 2
// capture all errors
`define ERROR_CAPTURE_MODE_HOLD_ALL 3
`define ERROR_CAPTURE_MODE_LAST `ERROR_CAPTURE_MODE_HOLD_ALL
//------------------------------------------------------------------------------
// crossbar implementation variants
//------------------------------------------------------------------------------
// tristate-based
`define CROSSBAR_TYPE_TRISTATE 0
// mux-based
`define CROSSBAR_TYPE_MUX 1
// distributed multiplexers
`define CROSSBAR_TYPE_DIST_MUX 2
`define CROSSBAR_TYPE_LAST `CROSSBAR_TYPE_DIST_MUX
//------------------------------------------------------------------------------
// register file implemetation variants
//------------------------------------------------------------------------------
// 2D array implemented using flipflops
`define REGFILE_TYPE_FF_2D 0
// 1D array of flipflops, read using a combinational mux
`define REGFILE_TYPE_FF_1D_MUX 1
// 1D array of flipflops, read using a tristate mux
`define REGFILE_TYPE_FF_1D_TRISTATE 2
// Synopsys DesignWare implementation using flipflips
`define REGFILE_TYPE_FF_DW 3
// 2D array implemented using flipflops
`define REGFILE_TYPE_LAT_2D 4
// 1D array of flipflops, read using a combinational mux
`define REGFILE_TYPE_LAT_1D_MUX 5
// 1D array of flipflops, read using a tristate mux
`define REGFILE_TYPE_LAT_1D_TRISTATE 6
// Synopsys DesignWare implementation using flipflips
`define REGFILE_TYPE_LAT_DW 7
`define REGFILE_TYPE_LAST `REGFILE_TYPE_LAT_DW
//------------------------------------------------------------------------------
// directions of rotation
//------------------------------------------------------------------------------
`define ROTATE_DIR_LEFT 0
`define ROTATE_DIR_RIGHT 1
//------------------------------------------------------------------------------
// wavefront allocator implementation variants
//------------------------------------------------------------------------------
// variant which uses multiplexers to permute inputs and outputs based on
// priority
`define WF_ALLOC_TYPE_MUX 0
// variant which replicates the entire allocation logic for the different
// priorities and selects the result from the appropriate one
`define WF_ALLOC_TYPE_REP 1
// variant implementing a Diagonal Propagation Arbiter as described in Hurt et
// al, "Design and Implementation of High-Speed Symmetric Crossbar Schedulers"
`define WF_ALLOC_TYPE_DPA 2
// variant which rotates inputs and outputs based on priority
`define WF_ALLOC_TYPE_ROT 3
// variant which uses wraparound (forming a false combinational loop) as
// described in Dally et al, "Principles and Practices of Interconnection
// Networks"
`define WF_ALLOC_TYPE_LOOP 4
`define WF_ALLOC_TYPE_LAST `WF_ALLOC_TYPE_LOOP
//------------------------------------------------------------------------------
// binary operators
//------------------------------------------------------------------------------
`define BINARY_OP_AND 0
`define BINARY_OP_NAND 1
`define BINARY_OP_OR 2
`define BINARY_OP_NOR 3
`define BINARY_OP_XOR 4
`define BINARY_OP_XNOR 5
`define BINARY_OP_LAST `BINARY_OP_XNOR
|
// $Id: c_functions.v 4079 2011-10-22 21:59:12Z dub $
/*
Copyright (c) 2007-2011, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// global function definitions
//==============================================================================
// compute ceiling of binary logarithm
function integer clogb(input integer argument);
integer i;
begin
clogb = 0;
for(i = argument - 1; i > 0; i = i >> 1)
clogb = clogb + 1;
end
endfunction
// compute ceiling of base-th root of argument
function integer croot(input integer argument, input integer base);
integer i;
integer j;
begin
croot = 0;
i = 0;
while(i < argument)
begin
croot = croot + 1;
i = 1;
for(j = 0; j < base; j = j + 1)
i = i * croot;
end
end
endfunction
// population count (count ones)
function integer pop_count(input integer argument);
integer i;
begin
pop_count = 0;
for(i = argument; i > 0; i = i >> 1)
pop_count = pop_count + (i & 1);
end
endfunction
|
`timescale 1ns/1ps
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_clocks.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_clocks (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 33,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 80,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 33,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 320,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 30303,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_clocks",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "320.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "320.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_clocks.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "320"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_clocks.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module pll_clocks (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "320.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "320.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_clocks.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "320"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_clocks_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
pll_clocks pll_clocks_inst (
.areset ( areset_sig ),
.inclk0 ( inclk0_sig ),
.c0 ( c0_sig ),
.c1 ( c1_sig ),
.locked ( locked_sig )
);
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : dpram.v
// Description : a generic description of dual port sram, support xilinx device
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-02-10 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module dpSram_32
#(
parameter SRAM_MODE = 1, // 0: generic sram; 1: Xilinx Simple Duel Port mode BRAM 2: Xilinx True Duel Port mode BRAM
parameter DBITWIDTH = 18, // data width of the SRAM, 36 bit when configured to be SDP BRAM, otherwise 18 bit wide
parameter ABITWIDTH = 10 // address width of the SRAM
)
(
// global
input wire clk_a,
input wire clk_b,
input wire clr_a,
input wire clr_b,
// port a interface
input wire en_a,
input wire write_a,
input wire [DBITWIDTH-1:0] wr_data_a,
input wire [ABITWIDTH-1:0] addr_a,
output wire [DBITWIDTH-1:0] rd_data_a,
// port b interface
input wire en_b,
input wire write_b,
input wire [DBITWIDTH-1:0] wr_data_b,
input wire [ABITWIDTH-1:0] addr_b,
output wire [DBITWIDTH-1:0] rd_data_b
);
localparam DO_REG = 1; // register the output data (0 or 1)
generate
// Xilinx Simple Duel Port BRAM
if(SRAM_MODE == 0)begin
wire [31:0] do1;
wire [3:0] dop;
wire [3:0] we;
assign rd_data_b = {dop,do1};
assign rd_data_a = {dop,do1};
assign we = {4{write_a}};
RAMB18SDP #(
.DO_REG(DO_REG) // optional output register (0 or 1)
)
RAMB18SDP_inst
(
.DO(do1), // 16-bit A port data/LSB data output
.DOP(dop), // 2-bit B port parity/MSB parity output
.RDCLK(clk_b), // 1-bit read port clock
.RDEN(en_b), // 1-bit read port enable
.REGCE(1'b1), // 1-bit register clock enable output set/reset input, only valid when 'DO_REG=1'
.SSR(1'b0), // 1-bit synchronous output set/reset input
.WRCLK(clk_a), // 1-bit write port clock
.WREN(en_a), // 1-bit write port enable
.WRADDR(addr_a), // 9-bit write port address input
.RDADDR(addr_b), // 9-bit read port address input
.DI(wr_data_a[31:0]),// 32-bit data input
.DIP(wr_data_a[35:32]), // 4-bit parity data input
.WE(we) // 4-bit byte write enable input
);
end
// Xilinx True Duel Port BRAM
else if(SRAM_MODE==1) begin
wire [15:0] doa,dob;
wire [1:0] dopa,dopb;
wire [1:0] wea;
wire [3:0] web;
assign rd_data_a = {dopa,doa};
assign rd_data_b = {dopb,dob};
assign wea = {2{write_a}};
assign web = {4{write_b}};
// RAMB18: 16K+2K Parity Paramatizable True Duel Port BlockRAM
RAMB18E1 #(
.DOA_REG(DO_REG),
.DOB_REG(DO_REG),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18)
)
RAMB18_inst(
.DOADO(doa),
.DOBDO(dob),
.DOPADOP(dopa),
.DOPBDOP(dopb),
.ADDRARDADDR({addr_a,4'b0}),
.ADDRBWRADDR({addr_b,4'b0}),
.CLKARDCLK(clk_a),
.CLKBWRCLK(clk_b),
.DIADI(wr_data_a[15:0]),
.DIBDI(wr_data_b[15:0]),
.DIPADIP(wr_data_a[17:16]),
.DIPBDIP(wr_data_b[17:16]),
.ENARDEN(en_a),
.ENBWREN(en_b), // port enable
.REGCEAREGCE(1'b1),
.REGCEB(1'b1), // output register clock enable signal
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(clr_a),
.RSTREGB(clr_b),
.WEA(wea), // byte write enable
.WEBWE(web)
);
end
// Generic simple duel port sram, 2 write & read ports
else if(SRAM_MODE == 2)begin
reg [DBITWIDTH-1:0] generic_ram [(2**ABITWIDTH)-1:0];
reg [DBITWIDTH-1:0] dout_a, dout_b, din_a, din_b;
reg wr_reg_a, wr_reg_b, en_reg_a, en_reg_b;
reg [ABITWIDTH-1:0] addr_reg_a, addr_reg_b;
always @(posedge clk_a)begin
wr_reg_a <= write_a;
addr_reg_a <= addr_a;
addr_reg_b <= addr_b;
din_a <= wr_data_a;
en_reg_a <= en_a;
en_reg_b <= en_b;
end
always @(posedge clk_a)
if (en_reg_a) begin
if (wr_reg_a)
generic_ram[addr_reg_a] <= din_a;
end
always @(posedge clk_b)
if (en_reg_b)
dout_b <= generic_ram[addr_reg_b];
assign rd_data_a = din_a;
assign rd_data_b = dout_b;
end
// generic simple duel port sram, 1 write port, 1 read port
else begin
reg [DBITWIDTH-1:0] generic_ram [(2**ABITWIDTH)-1:0];
reg [DBITWIDTH-1:0] dout_a, dout_b, din_a, din_b;
reg wr_reg_a, wr_reg_b, en_reg_a, en_reg_b;
reg [ABITWIDTH-1:0] addr_reg_a, addr_reg_b;
always @(posedge clk_a)begin
wr_reg_a <= write_a;
wr_reg_b <= write_b;
addr_reg_a <= addr_a;
addr_reg_b <= addr_b;
din_a <= wr_data_a;
din_b <= wr_data_b;
en_reg_a <= en_a;
en_reg_b <= en_b;
end
always @(posedge clk_a)
if (en_reg_a) begin
if (wr_reg_a)
generic_ram[addr_reg_a] <= din_a;
dout_a <= generic_ram[addr_reg_a];
end
always @(posedge clk_b)
if (en_reg_b) begin
if (wr_reg_a)
generic_ram[addr_reg_b] <= din_b;
dout_b <= generic_ram[addr_reg_b];
end
assign rd_data_a = dout_a;
assign rd_data_b = dout_b;
end
endgenerate
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : infer_sdpram.v
// Description : a generic description of dual port sram, support xilinx device
// : 2 clock, 1 write port and 1 read port
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-02-10 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module infer_sdpram
#(
parameter DWIDTH = 18, // data width of the SRAM, 36 bit when configured to be SDP BRAM, otherwise 18 bit wide
parameter AWIDTH = 10 // address width of the SRAM
)
(
// global
input wire clk_a,
input wire clk_b,
// port a interface
input wire en_a,
input wire write_a,
input wire [DWIDTH-1:0] wr_data_a,
input wire [AWIDTH-1:0] addr_a,
// port b interface
input wire en_b,
input wire [AWIDTH-1:0] addr_b,
output wire [DWIDTH-1:0] rd_data_b
);
//(* RAM_STYLE="BLOCK" *)
reg [DWIDTH-1:0] generic_ram [(2**AWIDTH)-1:0];
reg [DWIDTH-1:0] dout_a, dout_b, din_a, din_b;
reg wr_reg_a, wr_reg_b, en_reg_a, en_reg_b;
reg [AWIDTH-1:0] addr_reg_a, addr_reg_b;
always @(posedge clk_a)begin
wr_reg_a <= write_a;
addr_reg_a <= addr_a;
din_a <= wr_data_a;
en_reg_a <= en_a;
end
always @(posedge clk_b)begin
addr_reg_b <= addr_b;
en_reg_b <= en_b;
end
always @(posedge clk_a)
if (en_reg_a) begin
if (wr_reg_a)
generic_ram[addr_reg_a] <= din_a;
end
always @(posedge clk_b)
if (en_reg_b) begin
// if (wr_reg_b)
//generic_ram[addr_reg_b] <= din_b;
dout_b <= generic_ram[addr_reg_b];
end
//assign rd_data_a = dout_a;
assign rd_data_b = dout_b;
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : rr_sch.v
// Description : round robin scheduler
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-29 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module rr_sch
#(
parameter NUM_PORT = 4 // number of requests to be scheduled
)
(
input wire clk,
input wire rst_n,
input wire clr,
input wire [NUM_PORT-1:0] req,
input wire stall,
output wire [NUM_PORT-1:0] grant
);
`include "c_functions.v"
localparam LOG_NUM_PORT = 2;
genvar iRR;
integer i;
reg [NUM_PORT-1:0] rr_prior_non_empty_vec;
reg [NUM_PORT-1:0] rr_prior[0:NUM_PORT-1];
reg [NUM_PORT-1:0] rr_prior_non_empty[0:NUM_PORT-1];
reg [NUM_PORT-1:0] rr_prior_mask[0:NUM_PORT-1];
reg [LOG_NUM_PORT-1:0] rr_index[0:NUM_PORT-1];
wire [LOG_NUM_PORT-1:0] sch_index ;
reg [NUM_PORT-1:0] rr_nxt_non_empty_vec;
always@(*)begin
rr_prior_non_empty_vec = 0;
for(i=0;i<NUM_PORT;i=i+1)
rr_prior_non_empty_vec = rr_prior_non_empty_vec | rr_prior_non_empty[i];
end
generate
for(iRR=0;iRR<NUM_PORT; iRR=iRR+1) begin : ROUND_ROBIN
// the Round Robin priority of each port is updated whenever the token is
// passed from one port to another
always@(posedge clk )begin
if(clr)
rr_index[iRR] <= NUM_PORT - iRR;
else if(~stall)
rr_index[iRR] <= sch_index - iRR + NUM_PORT;
end
always@(*)begin
rr_prior[iRR] = 1 << rr_index[iRR];
rr_prior_mask[iRR] = {NUM_PORT{1'b1}} << (rr_index[iRR] + 1);
rr_prior_non_empty[iRR] = req[iRR] ? rr_prior[iRR] : 0;
end
always@(*)begin
rr_nxt_non_empty_vec[iRR] = req[iRR] ? ( ~|(rr_prior_non_empty_vec & rr_prior_mask[iRR]) ) : 0;
end
end // end for
endgenerate
c_encode#(
.num_ports(NUM_PORT)
)
one_hot_index
(
.data_in(rr_nxt_non_empty_vec),
.data_out(sch_index)
);
/*
generate
if(NUM_PORT == 4) begin
always @ (*)
case (rr_nxt_non_empty_vec)
4'b0001: sch_index = 0;
4'b0010: sch_index = 1;
4'b0100: sch_index = 2;
4'b1000: sch_index = 3;
default: sch_index = 0;
endcase
end
endgenerate
*/
assign grant = rr_nxt_non_empty_vec;
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : rr_sch_16.v
// Description : round robin scheduler for 16 groups
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-06-29 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module rr_sch_16
#(
parameter GSIZE = 4,
parameter MWIDTH = 4, // number of requests to be scheduled
parameter LOG_GSIZE = 2
)
(
input wire clk,
input wire rst_n,
input wire clr,
// group 0
input wire [GSIZE-1:0] req_0_0,
input wire stall_0_0,
output wire [GSIZE-1:0] grant_0_0,
input wire [GSIZE-1:0] req_0_1,
input wire stall_0_1,
output wire [GSIZE-1:0] grant_0_1,
input wire [GSIZE-1:0] req_0_2,
input wire stall_0_2,
output wire [GSIZE-1:0] grant_0_2,
input wire [GSIZE-1:0] req_0_3,
input wire stall_0_3,
output wire [GSIZE-1:0] grant_0_3,
// group 1
input wire [GSIZE-1:0] req_1_0,
input wire stall_1_0,
output wire [GSIZE-1:0] grant_1_0,
input wire [GSIZE-1:0] req_1_1,
input wire stall_1_1,
output wire [GSIZE-1:0] grant_1_1,
input wire [GSIZE-1:0] req_1_2,
input wire stall_1_2,
output wire [GSIZE-1:0] grant_1_2,
input wire [GSIZE-1:0] req_1_3,
input wire stall_1_3,
output wire [GSIZE-1:0] grant_1_3,
// group 0
input wire [GSIZE-1:0] req_2_0,
input wire stall_2_0,
output wire [GSIZE-1:0] grant_2_0,
input wire [GSIZE-1:0] req_2_1,
input wire stall_2_1,
output wire [GSIZE-1:0] grant_2_1,
input wire [GSIZE-1:0] req_2_2,
input wire stall_2_2,
output wire [GSIZE-1:0] grant_2_2,
input wire [GSIZE-1:0] req_2_3,
input wire stall_2_3,
output wire [GSIZE-1:0] grant_2_3,
// group 0
input wire [GSIZE-1:0] req_3_0,
input wire stall_3_0,
output wire [GSIZE-1:0] grant_3_0,
input wire [GSIZE-1:0] req_3_1,
input wire stall_3_1,
output wire [GSIZE-1:0] grant_3_1,
input wire [GSIZE-1:0] req_3_2,
input wire stall_3_2,
output wire [GSIZE-1:0] grant_3_2,
input wire [GSIZE-1:0] req_3_3,
input wire stall_3_3,
output wire [GSIZE-1:0] grant_3_3
);
genvar i;
wire [GSIZE-1:0] req[MWIDTH*GSIZE-1:0];
wire stall[MWIDTH*GSIZE-1:0];
wire [GSIZE-1:0] grant[MWIDTH*GSIZE-1:0];
// req
// group 0
assign req[0] = req_0_0;
assign req[1] = req_0_1;
assign req[2] = req_0_2;
assign req[3] = req_0_3;
// group 1
assign req[4] = req_1_0;
assign req[5] = req_1_1;
assign req[6] = req_1_2;
assign req[7] = req_1_3;
// group 2
assign req[8] = req_2_0;
assign req[9] = req_2_1;
assign req[10] = req_2_2;
assign req[11] = req_2_3;
// group 3
assign req[12] = req_3_0;
assign req[13] = req_3_1;
assign req[14] = req_3_2;
assign req[15] = req_3_3;
// stall
// group0
assign stall[0] = stall_0_0;
assign stall[1] = stall_0_1;
assign stall[2] = stall_0_2;
assign stall[3] = stall_0_3;
// group 1
assign stall[4] = stall_1_0;
assign stall[5] = stall_1_1;
assign stall[6] = stall_1_2;
assign stall[7] = stall_1_3;
// group 2
assign stall[8] = stall_2_0;
assign stall[9] = stall_2_1;
assign stall[10] = stall_2_2;
assign stall[11] = stall_2_3;
// group 3
assign stall[12] = stall_3_0;
assign stall[13] = stall_3_1;
assign stall[14] = stall_3_2;
assign stall[15] = stall_3_3;
// grant
// group0
assign grant_0_0 = grant[0];
assign grant_0_1 = grant[1];
assign grant_0_2 = grant[2];
assign grant_0_3 = grant[3];
// group1
assign grant_1_0 = grant[4];
assign grant_1_1 = grant[5];
assign grant_1_2 = grant[6];
assign grant_1_3 = grant[7];
// group2
assign grant_2_0 = grant[8];
assign grant_2_1 = grant[9];
assign grant_2_2 = grant[10];
assign grant_2_3 = grant[11];
// group3
assign grant_3_0 = grant[12];
assign grant_3_1 = grant[13];
assign grant_3_2 = grant[14];
assign grant_3_3 = grant[15];
generate
for(i=0;i<GSIZE*MWIDTH;i=i+1)begin:rnd_robin
rr_sch
#(
.NUM_PORT(GSIZE), // number of requests to be scheduled
.LOG_NUM_PORT(LOG_GSIZE)
)rr_sch_inst
(
.clk(clk),
.rst_n(rst_n),
.clr(clr),
.req(req[i]),
.stall(stall[i]),
.grant(grant[i])
);
end // end for rnd_robin
endgenerate
endmodule
|
// zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
// File Name : gsm_test.v
// Description : test bench for gsm system
// Author : Zefu Dai
// -------------------------------------------------------------------------------
// Version :
// -- 2011-07-02 created by Zefu Dai
// fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
`include "timescale.v"
module gsm_test;
`define DAT_PKT_PAD 16'hE00F
`define FLAG_HEAD_PKT 16'hABCD
`define FLAG_DAT_PKT 16'h0800
localparam DWIDTH = 256;
localparam MWIDTH = 4;
localparam GSIZE = 4;
localparam SWITCH_SIZE = MWIDTH*GSIZE;
localparam LOG_MWIDTH = 2;
localparam LOG_GSIZE = 2;
localparam AWIDTH = 7;
localparam LOC_PKT_LEN = 24; // the bit location of packet length field in the 16-byte data cell
localparam LOC_DEST_IP = 31; // the bit location of the destination ip field in the data cell
localparam LOC_SOURCE_ID = 16;
//-------------------------------------------------
// clk and reset signal generation
//-------------------------------------------------
wire clk_320M, clk_80M, clr_320M, clr_80M;
wire rst_n;
reg clk_33M, extern_rst_n;
initial begin
clk_33M <= 0;
extern_rst_n <= 0;
extern_rst_n <= #(300) 1'b1;
end
always @(clk_33M)begin
clk_33M <= #(25) ~clk_33M;
end
//-------------------------------------------------
// ingress port data generation
//-------------------------------------------------
reg [15:0] pkt_header;
reg ingress_valid, ingress_header;
integer i;
genvar igp;
reg [7:0] sourceID[GSIZE*MWIDTH-1:0];
reg [7:0] pkt_length;
reg [31:0] destIP[GSIZE*MWIDTH-1:0];
reg [GSIZE*MWIDTH*DWIDTH-1:0] ingress_data;
reg [GSIZE*MWIDTH-1:0] egress_stall;
reg [7:0] pkt_cnt;
initial begin
for(i=0;i<GSIZE*MWIDTH;i=i+1)begin
sourceID[i] = i;
destIP[i] = (1 << i) | (1<<(i+1));
end
egress_stall = 0;
end
always@(*)begin
if(ingress_header)begin
pkt_header = {pkt_cnt,8'hEF};
end
else begin
pkt_header = {pkt_cnt,8'hCD};
end
end
always@(posedge clk_80M)begin
if(clr_80M)begin
ingress_valid <= 0;
pkt_length <= 2;
ingress_header <= 0;
end
else begin
ingress_valid <= 1'b1;
pkt_length <= 2;
ingress_header <= ~ingress_header;
end
end
always@(posedge clk_80M)begin
if(clr_80M)
pkt_cnt <= 0;
else if(ingress_header)
pkt_cnt <= pkt_cnt + 1;
end
generate
for(igp = 0; igp < GSIZE * MWIDTH; igp=igp+1)begin : INGRESS_DATA_GEN
always@(*)begin
ingress_data[(igp+1)*DWIDTH-1:igp*DWIDTH] = {64'hDDDD,destIP[igp],pkt_length,sourceID[igp],pkt_header};
end
end
endgenerate
gsm_sys
#(
.MWIDTH(MWIDTH), // multicast width = 4 output ports
.GSIZE(GSIZE), // group size, number of gsm_unit in each group
.DWIDTH(DWIDTH), // data width = 16 bytes
.AWIDTH(AWIDTH) // 2 BRAM = total 512 cells, each port is allocated 128 cells
) gsm_sys_inst
(
//** global
.clk_33M(clk_33M),
.extern_rst_n(extern_rst_n),
.clk_320M(clk_320M),
.clk_80M(clk_80M),
.clr_320M(clr_320M),
.clr_80M(clr_80M),
.rst_n(rst_n),
//** 16 ingress ports
// group 0
.i_ingress_valid({SWITCH_SIZE{ingress_valid}}),
.i_ingress_header({SWITCH_SIZE{ingress_header}}),
.i_ingress_data(ingress_data),
//** 16 egress ports
// group 0
.i_egress_stall(egress_stall),
.o_egress_valid(),
.o_egress_data()
);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
//
// $Date: 2004/02/18 11:40:46 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_byte_ctrl.v,v $
// Revision 1.7 2004/02/18 11:40:46 rherveille
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
//
// Revision 1.6 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.5 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.4 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.3 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_byte_ctrl (
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input nReset; // asynchronous active low reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter [4:0] ST_IDLE = 5'b0_0000;
parameter [4:0] ST_START = 5'b0_0001;
parameter [4:0] ST_READ = 5'b0_0010;
parameter [4:0] ST_WRITE = 5'b0_0100;
parameter [4:0] ST_ACK = 5'b0_1000;
parameter [4:0] ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= #1 8'h0;
else if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= #1 3'h0;
else if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state; // synopsis enum_state
always @(posedge clk or negedge nReset)
if (!nReset)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master controller defines ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $
//
// $Date: 2001/11/05 11:59:25 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_defines.v,v $
// Revision 1.3 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
// I2C registers wishbone addresses
// bitcontroller states
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $
//
// $Date: 2005/02/27 09:26:24 $
// $Revision: 1.11 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_top.v,v $
// Revision 1.11 2005/02/27 09:26:24 rherveille
// Fixed register overwrite issue.
// Removed full_case pragma, replaced it by a default statement.
//
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
// Revision 1.8 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.7 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.6 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.5 2001/11/10 10:52:55 rherveille
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 2'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
`timescale 1ns / 10ps
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
/*-----------------------------------------------------------------------
-- AESL_FPSim_pkg.v:
-- Floating point simulation model for verilog.
--
-----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-- FAdd, FSub, FAddSub, FMul, FDiv, FSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision units.
-- DAdd, DSub, DAddSub, DMul, DDiv, DSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision Add.
-------------------------------------------------------------------------------
*/
module ACMP_fadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Sub.
-------------------------------------------------------------------------------
*/
module ACMP_fsub_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision AddSub.
-------------------------------------------------------------------------------
*/
module ACMP_faddfsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_faddfsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision ADD
-------------------------------------------------------------------------------
*/
module ACMP_dadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Sub
-------------------------------------------------------------------------------
*/
module ACMP_dsub_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision AddSub
-------------------------------------------------------------------------------
*/
module ACMP_dadddsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadddsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_fcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_dcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_fptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_dptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_sitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_sitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_fptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_dptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_uitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_uitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- single to double precision
-------------------------------------------------------------------------------
*/
module ACMP_fpext_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fpext(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- double to single precision
-------------------------------------------------------------------------------
*/
module ACMP_fptrunc_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptrunc(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module do_rotate (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
a_address0,
a_ce0,
a_we0,
a_d0,
a_q0,
a_address1,
a_ce1,
a_we1,
a_d1,
a_q1,
v_address0,
v_ce0,
v_we0,
v_d0,
v_q0,
v_address1,
v_ce1,
v_we1,
v_d1,
v_q1,
s,
tau,
ip,
iq
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output [13:0] a_address0;
output a_ce0;
output a_we0;
output [31:0] a_d0;
input [31:0] a_q0;
output [13:0] a_address1;
output a_ce1;
output a_we1;
output [31:0] a_d1;
input [31:0] a_q1;
output [13:0] v_address0;
output v_ce0;
output v_we0;
output [31:0] v_d0;
input [31:0] v_q0;
output [13:0] v_address1;
output v_ce1;
output v_we1;
output [31:0] v_d1;
input [31:0] v_q1;
input [31:0] s;
input [31:0] tau;
input [6:0] ip;
input [8:0] iq;
reg ap_done;
reg ap_idle;
reg[13:0] a_address0;
reg a_ce0;
reg a_we0;
reg[13:0] a_address1;
reg a_ce1;
reg a_we1;
reg[31:0] a_d1;
reg[13:0] v_address0;
reg v_ce0;
reg v_we0;
reg[13:0] v_address1;
reg v_ce1;
reg v_we1;
reg [3:0] ap_CS_fsm;
reg [31:0] indvar2_reg_168;
reg [31:0] indvar4_reg_179;
reg [31:0] indvar1_reg_190;
reg [7:0] indvar_reg_201;
reg [7:0] j_3_reg_212;
reg [31:0] reg_240;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg ap_reg_ppiten_pp0_it4;
reg ap_reg_ppiten_pp0_it5;
reg ap_reg_ppiten_pp0_it6;
reg ap_reg_ppiten_pp0_it7;
reg ap_reg_ppiten_pp0_it8;
reg ap_reg_ppiten_pp0_it9;
reg ap_reg_ppiten_pp0_it10;
reg ap_reg_ppiten_pp0_it11;
reg [0:0] tmp_4_reg_683;
reg ap_reg_ppiten_pp1_it0;
reg ap_reg_ppiten_pp1_it1;
reg ap_reg_ppiten_pp1_it2;
reg ap_reg_ppiten_pp1_it3;
reg ap_reg_ppiten_pp1_it4;
reg ap_reg_ppiten_pp1_it5;
reg ap_reg_ppiten_pp1_it6;
reg ap_reg_ppiten_pp1_it7;
reg ap_reg_ppiten_pp1_it8;
reg ap_reg_ppiten_pp1_it9;
reg ap_reg_ppiten_pp1_it10;
reg ap_reg_ppiten_pp1_it11;
reg [0:0] tmp_13_reg_707;
reg ap_reg_ppiten_pp2_it0;
reg ap_reg_ppiten_pp2_it1;
reg ap_reg_ppiten_pp2_it2;
reg ap_reg_ppiten_pp2_it3;
reg ap_reg_ppiten_pp2_it4;
reg ap_reg_ppiten_pp2_it5;
reg ap_reg_ppiten_pp2_it6;
reg ap_reg_ppiten_pp2_it7;
reg ap_reg_ppiten_pp2_it8;
reg ap_reg_ppiten_pp2_it9;
reg ap_reg_ppiten_pp2_it10;
reg ap_reg_ppiten_pp2_it11;
reg [0:0] exitcond_reg_736;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it1;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it2;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it3;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it4;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it5;
reg [31:0] ap_reg_ppstg_reg_240_pp0_it6;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it1;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it2;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it3;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it4;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it5;
reg [31:0] ap_reg_ppstg_reg_240_pp1_it6;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it1;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it2;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it3;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it4;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it5;
reg [31:0] ap_reg_ppstg_reg_240_pp2_it6;
reg [31:0] reg_247;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it1;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it2;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it3;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it4;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it5;
reg [31:0] ap_reg_ppstg_reg_247_pp0_it6;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it1;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it2;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it3;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it4;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it5;
reg [31:0] ap_reg_ppstg_reg_247_pp1_it6;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it1;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it2;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it3;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it4;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it5;
reg [31:0] ap_reg_ppstg_reg_247_pp2_it6;
wire [31:0] grp_fu_232_p2;
reg [31:0] reg_254;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it2;
reg ap_reg_ppiten_pp3_it2;
reg ap_reg_ppiten_pp3_it0;
reg ap_reg_ppiten_pp3_it1;
reg ap_reg_ppiten_pp3_it3;
reg ap_reg_ppiten_pp3_it4;
reg ap_reg_ppiten_pp3_it5;
reg ap_reg_ppiten_pp3_it6;
reg ap_reg_ppiten_pp3_it7;
reg ap_reg_ppiten_pp3_it8;
reg ap_reg_ppiten_pp3_it9;
reg ap_reg_ppiten_pp3_it10;
reg ap_reg_ppiten_pp3_it11;
reg [0:0] exitcond1_reg_755;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it2;
wire [31:0] grp_fu_236_p2;
reg [31:0] reg_259;
wire [31:0] grp_fu_224_p2;
reg [31:0] reg_264;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it4;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it4;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it4;
wire [31:0] grp_fu_228_p2;
reg [31:0] reg_269;
reg [31:0] reg_274;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it6;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it6;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it6;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it6;
reg [31:0] reg_279;
reg [31:0] reg_284;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it9;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it9;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it9;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it9;
reg [31:0] reg_290;
reg [31:0] ap_reg_ppstg_reg_290_pp0_it10;
reg [31:0] ap_reg_ppstg_reg_290_pp1_it10;
reg [31:0] ap_reg_ppstg_reg_290_pp2_it10;
reg [31:0] ap_reg_ppstg_reg_290_pp3_it10;
wire [7:0] ip_cast2_fu_296_p1;
reg [7:0] ip_cast2_reg_636;
reg [31:0] tmp_1_cast_reg_641;
wire [31:0] tmp1_fu_314_p1;
reg [31:0] tmp1_reg_646;
wire [15:0] tmp33_cast_fu_322_p1;
reg [15:0] tmp33_cast_reg_651;
wire [31:0] tmp34_cast_fu_332_p1;
reg [31:0] tmp34_cast_reg_657;
wire [15:0] tmp36_cast1_fu_336_p1;
reg [15:0] tmp36_cast1_reg_662;
wire [13:0] tmp36_cast_fu_344_p1;
reg [13:0] tmp36_cast_reg_667;
wire [31:0] tmp37_cast_fu_354_p1;
reg [31:0] tmp37_cast_reg_673;
wire [31:0] j_fu_374_p2;
reg [31:0] j_reg_678;
wire [0:0] tmp_4_fu_380_p2;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it7;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it8;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it10;
reg [0:0] ap_reg_ppstg_tmp_4_reg_683_pp0_it11;
reg [13:0] a_addr_2_reg_687;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it1;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it2;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it3;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it4;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it5;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it6;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it7;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it8;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it9;
reg [13:0] ap_reg_ppstg_a_addr_2_reg_687_pp0_it10;
reg [13:0] a_addr_1_reg_692;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it1;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it2;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it3;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it4;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it5;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it6;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it7;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it8;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it9;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it10;
reg [13:0] ap_reg_ppstg_a_addr_1_reg_692_pp0_it11;
reg [31:0] tmp_5_cast_reg_697;
wire [31:0] tmp6_cast_fu_413_p1;
reg [31:0] tmp6_cast_reg_702;
wire [0:0] tmp_13_fu_422_p2;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it1;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it3;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it5;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it7;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it8;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it10;
reg [0:0] ap_reg_ppstg_tmp_13_reg_707_pp1_it11;
reg [31:0] indvar_next5_reg_711;
reg [13:0] a_addr_2_6_reg_716;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it1;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it2;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it3;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it4;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it5;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it6;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it7;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it8;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it9;
reg [13:0] ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it10;
reg [13:0] a_addr_3_reg_721;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it1;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it2;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it3;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it4;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it5;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it6;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it7;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it8;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it9;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it10;
reg [13:0] ap_reg_ppstg_a_addr_3_reg_721_pp1_it11;
wire [31:0] tmp_cast_fu_478_p1;
reg [31:0] tmp_cast_reg_726;
reg [31:0] tmp10_reg_731;
wire [0:0] exitcond_fu_509_p2;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it1;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it3;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it5;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it7;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it8;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it10;
reg [0:0] ap_reg_ppstg_exitcond_reg_736_pp2_it11;
reg [31:0] indvar_next2_reg_740;
reg [13:0] a_addr_4_reg_745;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it1;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it2;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it3;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it4;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it5;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it6;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it7;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it8;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it9;
reg [13:0] ap_reg_ppstg_a_addr_4_reg_745_pp2_it10;
reg [13:0] a_addr_5_reg_750;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it1;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it2;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it3;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it4;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it5;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it6;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it7;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it8;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it9;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it10;
reg [13:0] ap_reg_ppstg_a_addr_5_reg_750_pp2_it11;
wire [0:0] exitcond1_fu_565_p2;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it1;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it3;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it5;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it7;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it8;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it10;
reg [0:0] ap_reg_ppstg_exitcond1_reg_755_pp3_it11;
reg [7:0] indvar_next_reg_759;
reg [13:0] v_addr_12_reg_764;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it1;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it2;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it3;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it4;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it5;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it6;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it7;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it8;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it9;
reg [13:0] ap_reg_ppstg_v_addr_12_reg_764_pp3_it10;
reg [13:0] v_addr_1_reg_769;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it1;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it2;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it3;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it4;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it5;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it6;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it7;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it8;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it9;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it10;
reg [13:0] ap_reg_ppstg_v_addr_1_reg_769_pp3_it11;
reg [7:0] tmp_41_reg_774;
reg [31:0] v_load_reg_779;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it1;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it2;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it3;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it4;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it5;
reg [31:0] ap_reg_ppstg_v_load_reg_779_pp3_it6;
reg [31:0] v_load_1_reg_786;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it1;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it2;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it3;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it4;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it5;
reg [31:0] ap_reg_ppstg_v_load_1_reg_786_pp3_it6;
reg [31:0] indvar2_phi_fu_172_p4;
reg [31:0] indvar4_phi_fu_183_p4;
reg [31:0] indvar1_phi_fu_194_p4;
reg [7:0] indvar_phi_fu_205_p4;
reg [7:0] j_3_phi_fu_216_p4;
wire [63:0] tmp_3_fu_385_p1;
wire [63:0] tmp_14_fu_390_p1;
wire [63:0] tmp_32_fu_448_p1;
wire [63:0] tmp_42_fu_464_p1;
wire [63:0] tmp_44_fu_540_p1;
wire [63:0] tmp_46_fu_560_p1;
wire [63:0] tmp_47_fu_596_p1;
wire [63:0] tmp_48_fu_606_p1;
reg [31:0] grp_fu_224_p0;
reg [31:0] grp_fu_224_p1;
reg [31:0] grp_fu_228_p0;
reg [31:0] grp_fu_228_p1;
reg [31:0] grp_fu_232_p0;
reg [31:0] grp_fu_232_p1;
reg [31:0] grp_fu_236_p0;
reg [31:0] grp_fu_236_p1;
wire [8:0] ip_cast1_cast_fu_300_p1;
wire [8:0] tmp_1_fu_304_p2;
wire [9:0] tmp33_cast1_fu_318_p1;
wire [9:0] tmp2_fu_326_p2;
wire [8:0] tmp36_cast2_fu_340_p1;
wire [8:0] tmp5_fu_348_p2;
wire [31:0] tmp7_fu_358_p2;
wire [31:0] a_addr5_fu_369_p2;
wire [31:0] a_addr8_fu_364_p2;
wire [9:0] iq_cast_cast_fu_395_p1;
wire [9:0] tmp_5_fu_398_p2;
wire [7:0] tmp6_fu_408_p2;
wire [31:0] j_1_fu_417_p2;
wire [13:0] a_addr9_fu_433_p2;
wire [31:0] a_addr9_cast_fu_438_p1;
wire [31:0] a_addr2_fu_442_p2;
wire [31:0] a_addr6_fu_453_p2;
wire [31:0] a_addr7_fu_459_p2;
wire [9:0] iq_cast1_fu_469_p1;
wire [9:0] tmp_fu_472_p2;
wire [0:0] tmp3_fu_482_p2;
wire [8:0] tmp4_fu_488_p3;
wire [9:0] tmp8_fu_495_p1;
wire [9:0] tmp9_fu_499_p2;
wire [13:0] a_addr3_fu_525_p2;
wire [31:0] a_addr3_cast_fu_530_p1;
wire [31:0] j_2_fu_520_p2;
wire [31:0] a_addr4_fu_534_p2;
wire [15:0] a_addr_fu_545_p2;
wire [31:0] a_addr_cast_fu_550_p1;
wire [31:0] a_addr1_fu_554_p2;
wire [14:0] tmp_32_trn_cast_fu_577_p1;
wire [14:0] v_addr_fu_581_p2;
wire [15:0] v_addr_cast_fu_587_p1;
wire [15:0] v_addr1_fu_591_p2;
wire [15:0] v_addr2_fu_601_p2;
reg [1:0] grp_fu_224_opcode;
wire grp_fu_224_ce;
reg [1:0] grp_fu_228_opcode;
wire grp_fu_228_ce;
wire grp_fu_232_ce;
wire grp_fu_236_ce;
reg [3:0] ap_NS_fsm;
wire [63:0] a_addr_1_reg_6920;
wire [63:0] a_addr_2_6_reg_7160;
wire [63:0] a_addr_2_reg_6870;
wire [63:0] a_addr_3_reg_7210;
wire [63:0] a_addr_4_reg_7450;
wire [63:0] a_addr_5_reg_7500;
wire [63:0] v_addr_12_reg_7640;
wire [63:0] v_addr_1_reg_7690;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 4'b0000;
parameter ap_ST_st1_fsm_1 = 4'b0001;
parameter ap_ST_pp0_stg0_fsm_2 = 4'b0010;
parameter ap_ST_pp0_stg1_fsm_3 = 4'b0011;
parameter ap_ST_st26_fsm_4 = 4'b0100;
parameter ap_ST_pp1_stg0_fsm_5 = 4'b0101;
parameter ap_ST_pp1_stg1_fsm_6 = 4'b0110;
parameter ap_ST_st51_fsm_7 = 4'b0111;
parameter ap_ST_pp2_stg0_fsm_8 = 4'b1000;
parameter ap_ST_pp2_stg1_fsm_9 = 4'b1001;
parameter ap_ST_pp3_stg0_fsm_10 = 4'b1010;
parameter ap_ST_pp3_stg1_fsm_11 = 4'b1011;
parameter ap_ST_st100_fsm_12 = 4'b1100;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv9_1FF = 9'b111111111;
parameter ap_const_lv10_80 = 10'b0010000000;
parameter ap_const_lv9_80 = 9'b010000000;
parameter ap_const_lv32_7 = 32'b00000000000000000000000000000111;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv10_3FF = 10'b1111111111;
parameter ap_const_lv14_7 = 14'b00000000000111;
parameter ap_const_lv10_1 = 10'b0000000001;
parameter ap_const_lv10_81 = 10'b0010000001;
parameter ap_const_lv16_7 = 16'b0000000000000111;
parameter ap_const_lv8_80 = 8'b10000000;
parameter ap_const_lv15_7 = 15'b000000000000111;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_true = 1'b1;
do_rotate_grp_fu_224_ACMP_faddfsub_1 #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
do_rotate_grp_fu_224_ACMP_faddfsub_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_224_p0 ),
.din1( grp_fu_224_p1 ),
.opcode( grp_fu_224_opcode ),
.ce( grp_fu_224_ce ),
.dout( grp_fu_224_p2 )
);
do_rotate_grp_fu_228_ACMP_faddfsub_2 #(
.ID( 2 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
do_rotate_grp_fu_228_ACMP_faddfsub_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_228_p0 ),
.din1( grp_fu_228_p1 ),
.opcode( grp_fu_228_opcode ),
.ce( grp_fu_228_ce ),
.dout( grp_fu_228_p2 )
);
do_rotate_grp_fu_232_ACMP_fmul_3 #(
.ID( 3 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
do_rotate_grp_fu_232_ACMP_fmul_3_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_232_p0 ),
.din1( grp_fu_232_p1 ),
.ce( grp_fu_232_ce ),
.dout( grp_fu_232_p2 )
);
do_rotate_grp_fu_236_ACMP_fmul_4 #(
.ID( 4 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
do_rotate_grp_fu_236_ACMP_fmul_4_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_236_p0 ),
.din1( grp_fu_236_p1 ),
.ce( grp_fu_236_ce ),
.dout( grp_fu_236_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_4_fu_380_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (tmp_4_reg_683 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~(tmp_4_reg_683 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_13_fu_422_p2))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_reg_707))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if (((ap_ST_st26_fsm_4 == ap_CS_fsm) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_13_reg_707)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it10 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it10 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it10 <= ap_reg_ppiten_pp1_it9;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it10 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it11 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it11 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it11 <= ap_reg_ppiten_pp1_it10;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it11 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it2 <= ap_reg_ppiten_pp1_it1;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it3 <= ap_reg_ppiten_pp1_it2;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it4 <= ap_reg_ppiten_pp1_it3;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it5 <= ap_reg_ppiten_pp1_it4;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it6 <= ap_reg_ppiten_pp1_it5;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it7 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it7 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it7 <= ap_reg_ppiten_pp1_it6;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it7 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it8 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it8 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it8 <= ap_reg_ppiten_pp1_it7;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it8 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp1_it9 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it9 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it9 <= ap_reg_ppiten_pp1_it8;
end else if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
ap_reg_ppiten_pp1_it9 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_0;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp2_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_reg_736))) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_1;
end else if (((ap_ST_st51_fsm_7 == ap_CS_fsm) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_reg_736)))) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it10 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it10 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it10 <= ap_reg_ppiten_pp2_it9;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it10 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it11 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it11 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it11 <= ap_reg_ppiten_pp2_it10;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it11 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it2 <= ap_reg_ppiten_pp2_it1;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it3 <= ap_reg_ppiten_pp2_it2;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it4 <= ap_reg_ppiten_pp2_it3;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it5 <= ap_reg_ppiten_pp2_it4;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it6 <= ap_reg_ppiten_pp2_it5;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it7 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it7 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it7 <= ap_reg_ppiten_pp2_it6;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it7 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it8 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it8 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it8 <= ap_reg_ppiten_pp2_it7;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it8 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it9 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp2_it9 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it9 <= ap_reg_ppiten_pp2_it8;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
ap_reg_ppiten_pp2_it9 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp3_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_reg_755)))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it10 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it10 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it10 <= ap_reg_ppiten_pp3_it9;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it10 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it11 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it11 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it11 <= ap_reg_ppiten_pp3_it10;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it11 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it2 <= ap_reg_ppiten_pp3_it1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it3 <= ap_reg_ppiten_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it4 <= ap_reg_ppiten_pp3_it3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it5 <= ap_reg_ppiten_pp3_it4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it6 <= ap_reg_ppiten_pp3_it5;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it7 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it7 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it7 <= ap_reg_ppiten_pp3_it6;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it7 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it8 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it8 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it8 <= ap_reg_ppiten_pp3_it7;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it8 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp3_it9 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp3_it9 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppiten_pp3_it9 <= ap_reg_ppiten_pp3_it8;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
ap_reg_ppiten_pp3_it9 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2))) begin
a_addr_1_reg_692 <= a_addr_1_reg_6920;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2))) begin
a_addr_2_6_reg_716 <= a_addr_2_6_reg_7160;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2))) begin
a_addr_2_reg_687 <= a_addr_2_reg_6870;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2))) begin
a_addr_3_reg_721 <= a_addr_3_reg_7210;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2))) begin
a_addr_4_reg_745 <= a_addr_4_reg_7450;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2))) begin
a_addr_5_reg_750 <= a_addr_5_reg_7500;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it1 <= a_addr_1_reg_692;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it10 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it11 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it10;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it2 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it3 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it4 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it5 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it6 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it7 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it8 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_1_reg_692_pp0_it9 <= ap_reg_ppstg_a_addr_1_reg_692_pp0_it8;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it1 <= a_addr_2_6_reg_716;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it10 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it9;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it2 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it1;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it3 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it2;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it4 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it3;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it5 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it4;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it6 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it5;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it7 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it6;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it8 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it7;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it9 <= ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it8;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it1 <= a_addr_2_reg_687;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it10 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it2 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it3 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it4 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it5 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it6 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it7 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it8 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_2_reg_687_pp0_it9 <= ap_reg_ppstg_a_addr_2_reg_687_pp0_it8;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it1 <= a_addr_3_reg_721;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it10 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it9;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it11 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it10;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it2 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it1;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it3 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it2;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it4 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it3;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it5 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it4;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it6 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it5;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it7 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it6;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it8 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it7;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_3_reg_721_pp1_it9 <= ap_reg_ppstg_a_addr_3_reg_721_pp1_it8;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it1 <= a_addr_4_reg_745;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it10 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it9;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it2 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it1;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it3 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it2;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it4 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it3;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it5 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it4;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it6 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it5;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it7 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it6;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it8 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it7;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_4_reg_745_pp2_it9 <= ap_reg_ppstg_a_addr_4_reg_745_pp2_it8;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it1 <= a_addr_5_reg_750;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it10 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it9;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it11 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it10;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it2 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it1;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it3 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it2;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it4 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it3;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it5 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it4;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it6 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it5;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it7 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it6;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it8 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it7;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_a_addr_5_reg_750_pp2_it9 <= ap_reg_ppstg_a_addr_5_reg_750_pp2_it8;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it1 <= exitcond1_reg_755;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it10 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it9;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it11 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it10;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it2 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it1;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it3 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it2;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it4 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it3;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it5 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it4;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it6 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it5;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it7 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it6;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it8 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it7;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond1_reg_755_pp3_it9 <= ap_reg_ppstg_exitcond1_reg_755_pp3_it8;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it1 <= exitcond_reg_736;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it10 <= ap_reg_ppstg_exitcond_reg_736_pp2_it9;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it11 <= ap_reg_ppstg_exitcond_reg_736_pp2_it10;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it2 <= ap_reg_ppstg_exitcond_reg_736_pp2_it1;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it3 <= ap_reg_ppstg_exitcond_reg_736_pp2_it2;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it4 <= ap_reg_ppstg_exitcond_reg_736_pp2_it3;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it5 <= ap_reg_ppstg_exitcond_reg_736_pp2_it4;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it6 <= ap_reg_ppstg_exitcond_reg_736_pp2_it5;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it7 <= ap_reg_ppstg_exitcond_reg_736_pp2_it6;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it8 <= ap_reg_ppstg_exitcond_reg_736_pp2_it7;
end
if ((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_736_pp2_it9 <= ap_reg_ppstg_exitcond_reg_736_pp2_it8;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it1 <= reg_240;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it2 <= ap_reg_ppstg_reg_240_pp0_it1;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it3 <= ap_reg_ppstg_reg_240_pp0_it2;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it4 <= ap_reg_ppstg_reg_240_pp0_it3;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it5 <= ap_reg_ppstg_reg_240_pp0_it4;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp0_it6 <= ap_reg_ppstg_reg_240_pp0_it5;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it1 <= reg_240;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it2 <= ap_reg_ppstg_reg_240_pp1_it1;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it3 <= ap_reg_ppstg_reg_240_pp1_it2;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it4 <= ap_reg_ppstg_reg_240_pp1_it3;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it5 <= ap_reg_ppstg_reg_240_pp1_it4;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp1_it6 <= ap_reg_ppstg_reg_240_pp1_it5;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it1 <= reg_240;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it2 <= ap_reg_ppstg_reg_240_pp2_it1;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it3 <= ap_reg_ppstg_reg_240_pp2_it2;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it4 <= ap_reg_ppstg_reg_240_pp2_it3;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it5 <= ap_reg_ppstg_reg_240_pp2_it4;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_240_pp2_it6 <= ap_reg_ppstg_reg_240_pp2_it5;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it1 <= reg_247;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it2 <= ap_reg_ppstg_reg_247_pp0_it1;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it3 <= ap_reg_ppstg_reg_247_pp0_it2;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it4 <= ap_reg_ppstg_reg_247_pp0_it3;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it5 <= ap_reg_ppstg_reg_247_pp0_it4;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp0_it6 <= ap_reg_ppstg_reg_247_pp0_it5;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it1 <= reg_247;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it2 <= ap_reg_ppstg_reg_247_pp1_it1;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it3 <= ap_reg_ppstg_reg_247_pp1_it2;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it4 <= ap_reg_ppstg_reg_247_pp1_it3;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it5 <= ap_reg_ppstg_reg_247_pp1_it4;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp1_it6 <= ap_reg_ppstg_reg_247_pp1_it5;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it1 <= reg_247;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it2 <= ap_reg_ppstg_reg_247_pp2_it1;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it3 <= ap_reg_ppstg_reg_247_pp2_it2;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it4 <= ap_reg_ppstg_reg_247_pp2_it3;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it5 <= ap_reg_ppstg_reg_247_pp2_it4;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_247_pp2_it6 <= ap_reg_ppstg_reg_247_pp2_it5;
end
if ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_290_pp0_it10 <= reg_290;
end
if ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_290_pp1_it10 <= reg_290;
end
if ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_290_pp2_it10 <= reg_290;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_reg_290_pp3_it10 <= reg_290;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it1 <= tmp_13_reg_707;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it10 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it9;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it11 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it10;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it2 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it1;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it3 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it2;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it4 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it3;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it5 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it4;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it6 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it5;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it7 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it6;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it8 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it7;
end
if ((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_13_reg_707_pp1_it9 <= ap_reg_ppstg_tmp_13_reg_707_pp1_it8;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it1 <= tmp_4_reg_683;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it10 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it11 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it10;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it2 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it3 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it4 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it5 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it6 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it7 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it8 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_4_reg_683_pp0_it9 <= ap_reg_ppstg_tmp_4_reg_683_pp0_it8;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it1 <= v_addr_12_reg_764;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it10 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it9;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it2 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it1;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it3 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it2;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it4 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it3;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it5 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it4;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it6 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it5;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it7 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it6;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it8 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it7;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_12_reg_764_pp3_it9 <= ap_reg_ppstg_v_addr_12_reg_764_pp3_it8;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it1 <= v_addr_1_reg_769;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it10 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it9;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it11 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it10;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it2 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it1;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it3 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it2;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it4 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it3;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it5 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it4;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it6 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it5;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it7 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it6;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it8 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it7;
end
if ((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)) begin
ap_reg_ppstg_v_addr_1_reg_769_pp3_it9 <= ap_reg_ppstg_v_addr_1_reg_769_pp3_it8;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it1 <= v_load_1_reg_786;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it2 <= ap_reg_ppstg_v_load_1_reg_786_pp3_it1;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it3 <= ap_reg_ppstg_v_load_1_reg_786_pp3_it2;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it4 <= ap_reg_ppstg_v_load_1_reg_786_pp3_it3;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it5 <= ap_reg_ppstg_v_load_1_reg_786_pp3_it4;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_1_reg_786_pp3_it6 <= ap_reg_ppstg_v_load_1_reg_786_pp3_it5;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it1 <= v_load_reg_779;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it2 <= ap_reg_ppstg_v_load_reg_779_pp3_it1;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it3 <= ap_reg_ppstg_v_load_reg_779_pp3_it2;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it4 <= ap_reg_ppstg_v_load_reg_779_pp3_it3;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it5 <= ap_reg_ppstg_v_load_reg_779_pp3_it4;
end
if ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm)) begin
ap_reg_ppstg_v_load_reg_779_pp3_it6 <= ap_reg_ppstg_v_load_reg_779_pp3_it5;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm))) begin
exitcond1_reg_755 <= (indvar_phi_fu_205_p4 == ap_const_lv8_80? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
exitcond_reg_736 <= (indvar1_phi_fu_194_p4 == tmp10_reg_731? 1'b1: 1'b0);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
indvar1_reg_190 <= indvar_next2_reg_740;
end else if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
indvar1_reg_190 <= ap_const_lv32_0;
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar2_reg_168 <= ap_const_lv32_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar2_reg_168 <= j_reg_678;
end
if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
indvar4_reg_179 <= ap_const_lv32_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
indvar4_reg_179 <= indvar_next5_reg_711;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
indvar_next2_reg_740 <= (indvar1_phi_fu_194_p4 + ap_const_lv32_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
indvar_next5_reg_711 <= (indvar4_phi_fu_183_p4 + ap_const_lv32_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm))) begin
indvar_next_reg_759 <= (indvar_phi_fu_205_p4 + ap_const_lv8_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
indvar_reg_201 <= ap_const_lv8_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
indvar_reg_201 <= indvar_next_reg_759;
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ip_cast2_reg_636[0] <= ip_cast2_fu_296_p1[0];
ip_cast2_reg_636[1] <= ip_cast2_fu_296_p1[1];
ip_cast2_reg_636[2] <= ip_cast2_fu_296_p1[2];
ip_cast2_reg_636[3] <= ip_cast2_fu_296_p1[3];
ip_cast2_reg_636[4] <= ip_cast2_fu_296_p1[4];
ip_cast2_reg_636[5] <= ip_cast2_fu_296_p1[5];
ip_cast2_reg_636[6] <= ip_cast2_fu_296_p1[6];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2))) begin
j_3_reg_212 <= ap_const_lv8_1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
j_3_reg_212 <= tmp_41_reg_774;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
j_reg_678 <= (indvar2_phi_fu_172_p4 + ap_const_lv32_1);
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (tmp_4_reg_683 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == tmp_13_reg_707)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_lv1_0 == exitcond_reg_736)))) begin
reg_240 <= a_q0;
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (tmp_4_reg_683 == ap_const_lv1_0)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_const_lv1_0 == tmp_13_reg_707)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_lv1_0 == exitcond_reg_736)))) begin
reg_247 <= a_q1;
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2)))) begin
reg_254 <= grp_fu_232_p2;
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it2) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it2) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2)))) begin
reg_259 <= grp_fu_236_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it4)))) begin
reg_264 <= grp_fu_224_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it4)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it4)))) begin
reg_269 <= grp_fu_228_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it6)))) begin
reg_274 <= grp_fu_232_p2;
end
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it6)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it6)))) begin
reg_279 <= grp_fu_236_p2;
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it9)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it9) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it9)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it9) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it9)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it9) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it9)))) begin
reg_284 <= grp_fu_224_p2;
end
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it9)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it9) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it9)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it9) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it9)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it9) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it9)))) begin
reg_290 <= grp_fu_228_p2;
end
if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
tmp10_reg_731 <= {{22{tmp9_fu_499_p2[9]}}, {tmp9_fu_499_p2}};
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp1_reg_646[0] <= tmp1_fu_314_p1[0];
tmp1_reg_646[1] <= tmp1_fu_314_p1[1];
tmp1_reg_646[2] <= tmp1_fu_314_p1[2];
tmp1_reg_646[3] <= tmp1_fu_314_p1[3];
tmp1_reg_646[4] <= tmp1_fu_314_p1[4];
tmp1_reg_646[5] <= tmp1_fu_314_p1[5];
tmp1_reg_646[6] <= tmp1_fu_314_p1[6];
tmp1_reg_646[7] <= tmp1_fu_314_p1[7];
tmp1_reg_646[8] <= tmp1_fu_314_p1[8];
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp33_cast_reg_651[0] <= tmp33_cast_fu_322_p1[0];
tmp33_cast_reg_651[1] <= tmp33_cast_fu_322_p1[1];
tmp33_cast_reg_651[2] <= tmp33_cast_fu_322_p1[2];
tmp33_cast_reg_651[3] <= tmp33_cast_fu_322_p1[3];
tmp33_cast_reg_651[4] <= tmp33_cast_fu_322_p1[4];
tmp33_cast_reg_651[5] <= tmp33_cast_fu_322_p1[5];
tmp33_cast_reg_651[6] <= tmp33_cast_fu_322_p1[6];
tmp33_cast_reg_651[7] <= tmp33_cast_fu_322_p1[7];
tmp33_cast_reg_651[8] <= tmp33_cast_fu_322_p1[8];
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp34_cast_reg_657[0] <= tmp34_cast_fu_332_p1[0];
tmp34_cast_reg_657[1] <= tmp34_cast_fu_332_p1[1];
tmp34_cast_reg_657[2] <= tmp34_cast_fu_332_p1[2];
tmp34_cast_reg_657[3] <= tmp34_cast_fu_332_p1[3];
tmp34_cast_reg_657[4] <= tmp34_cast_fu_332_p1[4];
tmp34_cast_reg_657[5] <= tmp34_cast_fu_332_p1[5];
tmp34_cast_reg_657[6] <= tmp34_cast_fu_332_p1[6];
tmp34_cast_reg_657[7] <= tmp34_cast_fu_332_p1[7];
tmp34_cast_reg_657[8] <= tmp34_cast_fu_332_p1[8];
tmp34_cast_reg_657[9] <= tmp34_cast_fu_332_p1[9];
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp36_cast1_reg_662[0] <= tmp36_cast1_fu_336_p1[0];
tmp36_cast1_reg_662[1] <= tmp36_cast1_fu_336_p1[1];
tmp36_cast1_reg_662[2] <= tmp36_cast1_fu_336_p1[2];
tmp36_cast1_reg_662[3] <= tmp36_cast1_fu_336_p1[3];
tmp36_cast1_reg_662[4] <= tmp36_cast1_fu_336_p1[4];
tmp36_cast1_reg_662[5] <= tmp36_cast1_fu_336_p1[5];
tmp36_cast1_reg_662[6] <= tmp36_cast1_fu_336_p1[6];
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp36_cast_reg_667[0] <= tmp36_cast_fu_344_p1[0];
tmp36_cast_reg_667[1] <= tmp36_cast_fu_344_p1[1];
tmp36_cast_reg_667[2] <= tmp36_cast_fu_344_p1[2];
tmp36_cast_reg_667[3] <= tmp36_cast_fu_344_p1[3];
tmp36_cast_reg_667[4] <= tmp36_cast_fu_344_p1[4];
tmp36_cast_reg_667[5] <= tmp36_cast_fu_344_p1[5];
tmp36_cast_reg_667[6] <= tmp36_cast_fu_344_p1[6];
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp37_cast_reg_673[0] <= tmp37_cast_fu_354_p1[0];
tmp37_cast_reg_673[1] <= tmp37_cast_fu_354_p1[1];
tmp37_cast_reg_673[2] <= tmp37_cast_fu_354_p1[2];
tmp37_cast_reg_673[3] <= tmp37_cast_fu_354_p1[3];
tmp37_cast_reg_673[4] <= tmp37_cast_fu_354_p1[4];
tmp37_cast_reg_673[5] <= tmp37_cast_fu_354_p1[5];
tmp37_cast_reg_673[6] <= tmp37_cast_fu_354_p1[6];
end
if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
tmp6_cast_reg_702[0] <= tmp6_cast_fu_413_p1[0];
tmp6_cast_reg_702[1] <= tmp6_cast_fu_413_p1[1];
tmp6_cast_reg_702[2] <= tmp6_cast_fu_413_p1[2];
tmp6_cast_reg_702[3] <= tmp6_cast_fu_413_p1[3];
tmp6_cast_reg_702[4] <= tmp6_cast_fu_413_p1[4];
tmp6_cast_reg_702[5] <= tmp6_cast_fu_413_p1[5];
tmp6_cast_reg_702[6] <= tmp6_cast_fu_413_p1[6];
tmp6_cast_reg_702[7] <= tmp6_cast_fu_413_p1[7];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
tmp_13_reg_707 <= ($signed(tmp_5_cast_reg_697) < $signed(j_1_fu_417_p2)? 1'b1: 1'b0);
end
if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
tmp_1_cast_reg_641 <= {{23{tmp_1_fu_304_p2[8]}}, {tmp_1_fu_304_p2}};
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
tmp_41_reg_774 <= (j_3_phi_fu_216_p4 + ap_const_lv8_1);
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
tmp_4_reg_683 <= ($signed(tmp_1_cast_reg_641) < $signed(j_fu_374_p2)? 1'b1: 1'b0);
end
if ((ap_ST_st26_fsm_4 == ap_CS_fsm)) begin
tmp_5_cast_reg_697 <= {{22{tmp_5_fu_398_p2[9]}}, {tmp_5_fu_398_p2}};
end
if ((ap_ST_st51_fsm_7 == ap_CS_fsm)) begin
tmp_cast_reg_726[0] <= tmp_cast_fu_478_p1[0];
tmp_cast_reg_726[1] <= tmp_cast_fu_478_p1[1];
tmp_cast_reg_726[2] <= tmp_cast_fu_478_p1[2];
tmp_cast_reg_726[3] <= tmp_cast_fu_478_p1[3];
tmp_cast_reg_726[4] <= tmp_cast_fu_478_p1[4];
tmp_cast_reg_726[5] <= tmp_cast_fu_478_p1[5];
tmp_cast_reg_726[6] <= tmp_cast_fu_478_p1[6];
tmp_cast_reg_726[7] <= tmp_cast_fu_478_p1[7];
tmp_cast_reg_726[8] <= tmp_cast_fu_478_p1[8];
tmp_cast_reg_726[9] <= tmp_cast_fu_478_p1[9];
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
v_addr_12_reg_764 <= v_addr_12_reg_7640;
end
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
v_addr_1_reg_769 <= v_addr_1_reg_7690;
end
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
v_load_1_reg_786 <= v_q1;
end
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
v_load_reg_779 <= v_q0;
end
end
/// a_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it10 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it10 or tmp_4_fu_380_p2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it10 or ap_reg_ppstg_a_addr_2_reg_687_pp0_it10 or tmp_13_fu_422_p2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it10 or ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it10 or exitcond_fu_509_p2 or ap_reg_ppstg_exitcond_reg_736_pp2_it10 or ap_reg_ppstg_a_addr_4_reg_745_pp2_it10 or tmp_3_fu_385_p1 or tmp_32_fu_448_p1 or tmp_44_fu_540_p1)
begin
if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it10))) begin
a_address0 = ap_reg_ppstg_a_addr_4_reg_745_pp2_it10;
end else if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it10))) begin
a_address0 = ap_reg_ppstg_a_addr_2_6_reg_716_pp1_it10;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it10))) begin
a_address0 = ap_reg_ppstg_a_addr_2_reg_687_pp0_it10;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2))) begin
a_address0 = tmp_44_fu_540_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2))) begin
a_address0 = tmp_32_fu_448_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2))) begin
a_address0 = tmp_3_fu_385_p1;
end else begin
a_address0 = ap_reg_ppstg_a_addr_4_reg_745_pp2_it10;
end
end
/// a_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it11 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it11 or tmp_4_fu_380_p2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it11 or ap_reg_ppstg_a_addr_1_reg_692_pp0_it11 or tmp_13_fu_422_p2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it11 or ap_reg_ppstg_a_addr_3_reg_721_pp1_it11 or exitcond_fu_509_p2 or ap_reg_ppstg_exitcond_reg_736_pp2_it11 or ap_reg_ppstg_a_addr_5_reg_750_pp2_it11 or tmp_14_fu_390_p1 or tmp_42_fu_464_p1 or tmp_46_fu_560_p1)
begin
if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it11))) begin
a_address1 = ap_reg_ppstg_a_addr_5_reg_750_pp2_it11;
end else if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it11))) begin
a_address1 = ap_reg_ppstg_a_addr_3_reg_721_pp1_it11;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it11))) begin
a_address1 = ap_reg_ppstg_a_addr_1_reg_692_pp0_it11;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2))) begin
a_address1 = tmp_46_fu_560_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2))) begin
a_address1 = tmp_42_fu_464_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2))) begin
a_address1 = tmp_14_fu_390_p1;
end else begin
a_address1 = ap_reg_ppstg_a_addr_5_reg_750_pp2_it11;
end
end
/// a_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it10 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it10 or tmp_4_fu_380_p2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it10 or tmp_13_fu_422_p2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it10 or exitcond_fu_509_p2 or ap_reg_ppstg_exitcond_reg_736_pp2_it10)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it10)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it10)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it10)))) begin
a_ce0 = ap_const_logic_1;
end else begin
a_ce0 = ap_const_logic_0;
end
end
/// a_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it11 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it11 or tmp_4_fu_380_p2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it11 or tmp_13_fu_422_p2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it11 or exitcond_fu_509_p2 or ap_reg_ppstg_exitcond_reg_736_pp2_it11)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_4_fu_380_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & (ap_const_lv1_0 == tmp_13_fu_422_p2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond_fu_509_p2)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it11)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it11)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it11)))) begin
a_ce1 = ap_const_logic_1;
end else begin
a_ce1 = ap_const_logic_0;
end
end
/// a_d1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp1_it11 or ap_reg_ppiten_pp2_it11 or ap_reg_ppstg_reg_290_pp0_it10 or ap_reg_ppstg_reg_290_pp1_it10 or ap_reg_ppstg_reg_290_pp2_it10 or ap_reg_ppstg_tmp_4_reg_683_pp0_it11 or ap_reg_ppstg_tmp_13_reg_707_pp1_it11 or ap_reg_ppstg_exitcond_reg_736_pp2_it11)
begin
if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it11))) begin
a_d1 = ap_reg_ppstg_reg_290_pp2_it10;
end else if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it11))) begin
a_d1 = ap_reg_ppstg_reg_290_pp1_it10;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it11))) begin
a_d1 = ap_reg_ppstg_reg_290_pp0_it10;
end else begin
a_d1 = ap_reg_ppstg_reg_290_pp2_it10;
end
end
/// a_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp1_it10 or ap_reg_ppiten_pp2_it10 or ap_reg_ppstg_tmp_4_reg_683_pp0_it10 or ap_reg_ppstg_tmp_13_reg_707_pp1_it10 or ap_reg_ppstg_exitcond_reg_736_pp2_it10)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it10)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it10) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it10)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it10)))) begin
a_we0 = ap_const_logic_1;
end else begin
a_we0 = ap_const_logic_0;
end
end
/// a_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp1_it11 or ap_reg_ppiten_pp2_it11 or ap_reg_ppstg_tmp_4_reg_683_pp0_it11 or ap_reg_ppstg_tmp_13_reg_707_pp1_it11 or ap_reg_ppstg_exitcond_reg_736_pp2_it11)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it11)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it11)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it11)))) begin
a_we1 = ap_const_logic_1;
end else begin
a_we1 = ap_const_logic_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp1_it0 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it10 or ap_reg_ppiten_pp1_it11 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it10 or ap_reg_ppiten_pp2_it11 or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it10 or ap_reg_ppiten_pp3_it11 or tmp_4_fu_380_p2 or tmp_13_fu_422_p2 or exitcond_fu_509_p2 or exitcond1_fu_565_p2)
begin
if (((ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~(ap_const_lv1_0 == exitcond1_fu_565_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
ap_NS_fsm = ap_ST_pp3_stg1_fsm_11;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond1_fu_565_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it10)))) begin
ap_NS_fsm = ap_ST_st100_fsm_12;
end else if (((ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & ~(ap_const_lv1_0 == exitcond_fu_509_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it1)))) begin
ap_NS_fsm = ap_ST_pp2_stg1_fsm_9;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm) & ~(ap_const_lv1_0 == exitcond_fu_509_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it1)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it10)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & ~((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp3_it10))))) begin
ap_NS_fsm = ap_ST_pp3_stg0_fsm_10;
end else if (((ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_const_lv1_0 == tmp_13_fu_422_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
ap_NS_fsm = ap_ST_pp1_stg1_fsm_6;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_13_fu_422_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it10)))) begin
ap_NS_fsm = ap_ST_st51_fsm_7;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_const_lv1_0 == tmp_4_fu_380_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_pp0_stg1_fsm_3;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_4_fu_380_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it10)))) begin
ap_NS_fsm = ap_ST_st26_fsm_4;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st100_fsm_12 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if (((ap_ST_st51_fsm_7 == ap_CS_fsm) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & ~((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it10))))) begin
ap_NS_fsm = ap_ST_pp2_stg0_fsm_8;
end else if (((ap_ST_st26_fsm_4 == ap_CS_fsm) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & ~((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp1_it10))))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_5;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & ~((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it10))))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st100_fsm_12 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st100_fsm_12 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// grp_fu_224_opcode assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7)))) begin
grp_fu_224_opcode = ap_const_lv2_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)))) begin
grp_fu_224_opcode = ap_const_lv2_0;
end else begin
grp_fu_224_opcode = ap_const_lv2_1;
end
end
/// grp_fu_224_p0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_reg_240_pp0_it6 or ap_reg_ppstg_reg_240_pp1_it6 or ap_reg_ppstg_reg_240_pp2_it6 or reg_254 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7 or ap_reg_ppstg_v_load_reg_779_pp3_it6)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7))) begin
grp_fu_224_p0 = ap_reg_ppstg_v_load_reg_779_pp3_it6;
end else if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7))) begin
grp_fu_224_p0 = ap_reg_ppstg_reg_240_pp2_it6;
end else if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7))) begin
grp_fu_224_p0 = ap_reg_ppstg_reg_240_pp1_it6;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7))) begin
grp_fu_224_p0 = ap_reg_ppstg_reg_240_pp0_it6;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)))) begin
grp_fu_224_p0 = reg_254;
end else begin
grp_fu_224_p0 = ap_reg_ppstg_v_load_reg_779_pp3_it6;
end
end
/// grp_fu_224_p1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_reg_247_pp0_it2 or ap_reg_ppstg_reg_247_pp1_it2 or ap_reg_ppstg_reg_247_pp2_it2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or reg_274 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7 or ap_reg_ppstg_v_load_1_reg_786_pp3_it2)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm))) begin
grp_fu_224_p1 = ap_reg_ppstg_v_load_1_reg_786_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
grp_fu_224_p1 = ap_reg_ppstg_reg_247_pp2_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
grp_fu_224_p1 = ap_reg_ppstg_reg_247_pp1_it2;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7)))) begin
grp_fu_224_p1 = reg_274;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
grp_fu_224_p1 = ap_reg_ppstg_reg_247_pp0_it2;
end else begin
grp_fu_224_p1 = ap_reg_ppstg_v_load_1_reg_786_pp3_it2;
end
end
/// grp_fu_228_opcode assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)))) begin
grp_fu_228_opcode = ap_const_lv2_1;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7)))) begin
grp_fu_228_opcode = ap_const_lv2_0;
end else begin
grp_fu_228_opcode = ap_const_lv2_1;
end
end
/// grp_fu_228_p0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_reg_240_pp0_it2 or ap_reg_ppstg_reg_240_pp1_it2 or ap_reg_ppstg_reg_240_pp2_it2 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or reg_279 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7 or ap_reg_ppstg_v_load_reg_779_pp3_it2)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm))) begin
grp_fu_228_p0 = ap_reg_ppstg_v_load_reg_779_pp3_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
grp_fu_228_p0 = ap_reg_ppstg_reg_240_pp2_it2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
grp_fu_228_p0 = ap_reg_ppstg_reg_240_pp1_it2;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7)))) begin
grp_fu_228_p0 = reg_279;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
grp_fu_228_p0 = ap_reg_ppstg_reg_240_pp0_it2;
end else begin
grp_fu_228_p0 = ap_reg_ppstg_v_load_reg_779_pp3_it2;
end
end
/// grp_fu_228_p1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp1_it3 or ap_reg_ppiten_pp1_it7 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it7 or ap_reg_ppstg_reg_247_pp0_it6 or ap_reg_ppstg_reg_247_pp1_it6 or ap_reg_ppstg_reg_247_pp2_it6 or ap_reg_ppstg_tmp_4_reg_683_pp0_it2 or ap_reg_ppstg_tmp_13_reg_707_pp1_it2 or ap_reg_ppstg_exitcond_reg_736_pp2_it2 or ap_reg_ppiten_pp3_it3 or ap_reg_ppiten_pp3_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it2 or reg_259 or ap_reg_ppstg_tmp_4_reg_683_pp0_it7 or ap_reg_ppstg_tmp_13_reg_707_pp1_it7 or ap_reg_ppstg_exitcond_reg_736_pp2_it7 or ap_reg_ppstg_exitcond1_reg_755_pp3_it7 or ap_reg_ppstg_v_load_1_reg_786_pp3_it6)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it7))) begin
grp_fu_228_p1 = ap_reg_ppstg_v_load_1_reg_786_pp3_it6;
end else if (((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it7))) begin
grp_fu_228_p1 = ap_reg_ppstg_reg_247_pp2_it6;
end else if (((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it7))) begin
grp_fu_228_p1 = ap_reg_ppstg_reg_247_pp1_it6;
end else if (((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it7))) begin
grp_fu_228_p1 = ap_reg_ppstg_reg_247_pp0_it6;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it2) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it2) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it2) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it3) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it2) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm)))) begin
grp_fu_228_p1 = reg_259;
end else begin
grp_fu_228_p1 = ap_reg_ppstg_v_load_1_reg_786_pp3_it6;
end
end
/// grp_fu_232_p0 assign process. ///
always @ (ap_CS_fsm or reg_240 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or tmp_4_reg_683 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it5 or tmp_13_reg_707 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it5 or exitcond_reg_736 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it5 or exitcond1_reg_755 or reg_264 or ap_reg_ppstg_tmp_4_reg_683_pp0_it5 or ap_reg_ppstg_tmp_13_reg_707_pp1_it5 or ap_reg_ppstg_exitcond_reg_736_pp2_it5 or ap_reg_ppstg_exitcond1_reg_755_pp3_it5 or v_load_reg_779)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
grp_fu_232_p0 = v_load_reg_779;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it5)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it5)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it5)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it5)))) begin
grp_fu_232_p0 = reg_264;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)))) begin
grp_fu_232_p0 = reg_240;
end else begin
grp_fu_232_p0 = v_load_reg_779;
end
end
/// grp_fu_232_p1 assign process. ///
always @ (ap_CS_fsm or s or tau or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or tmp_4_reg_683 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it5 or tmp_13_reg_707 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it5 or exitcond_reg_736 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it5 or exitcond1_reg_755 or ap_reg_ppstg_tmp_4_reg_683_pp0_it5 or ap_reg_ppstg_tmp_13_reg_707_pp1_it5 or ap_reg_ppstg_exitcond_reg_736_pp2_it5 or ap_reg_ppstg_exitcond1_reg_755_pp3_it5)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it5)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it5)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it5)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it5)))) begin
grp_fu_232_p1 = s;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755)))) begin
grp_fu_232_p1 = tau;
end else begin
grp_fu_232_p1 = s;
end
end
/// grp_fu_236_p0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or tmp_4_reg_683 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it5 or tmp_13_reg_707 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it5 or exitcond_reg_736 or reg_247 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it5 or exitcond1_reg_755 or reg_269 or ap_reg_ppstg_tmp_4_reg_683_pp0_it5 or ap_reg_ppstg_tmp_13_reg_707_pp1_it5 or ap_reg_ppstg_exitcond_reg_736_pp2_it5 or ap_reg_ppstg_exitcond1_reg_755_pp3_it5 or v_load_1_reg_786)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
grp_fu_236_p0 = v_load_1_reg_786;
end else if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it5)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it5)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it5)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it5)))) begin
grp_fu_236_p0 = reg_269;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)))) begin
grp_fu_236_p0 = reg_247;
end else begin
grp_fu_236_p0 = v_load_1_reg_786;
end
end
/// grp_fu_236_p1 assign process. ///
always @ (ap_CS_fsm or s or tau or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or tmp_4_reg_683 or ap_reg_ppiten_pp1_it1 or ap_reg_ppiten_pp1_it5 or tmp_13_reg_707 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it5 or exitcond_reg_736 or ap_reg_ppiten_pp3_it1 or ap_reg_ppiten_pp3_it5 or exitcond1_reg_755 or ap_reg_ppstg_tmp_4_reg_683_pp0_it5 or ap_reg_ppstg_tmp_13_reg_707_pp1_it5 or ap_reg_ppstg_exitcond_reg_736_pp2_it5 or ap_reg_ppstg_exitcond1_reg_755_pp3_it5)
begin
if ((((ap_ST_pp0_stg1_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_4_reg_683_pp0_it5)) | ((ap_ST_pp1_stg1_fsm_6 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_13_reg_707_pp1_it5)) | ((ap_ST_pp2_stg1_fsm_9 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_736_pp2_it5)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it5) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it5)))) begin
grp_fu_236_p1 = s;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm)) | ((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755)))) begin
grp_fu_236_p1 = tau;
end else begin
grp_fu_236_p1 = s;
end
end
/// indvar1_phi_fu_194_p4 assign process. ///
always @ (ap_CS_fsm or indvar1_reg_190 or ap_reg_ppiten_pp2_it1 or exitcond_reg_736 or indvar_next2_reg_740)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_lv1_0 == exitcond_reg_736) & (ap_ST_pp2_stg0_fsm_8 == ap_CS_fsm))) begin
indvar1_phi_fu_194_p4 = indvar_next2_reg_740;
end else begin
indvar1_phi_fu_194_p4 = indvar1_reg_190;
end
end
/// indvar2_phi_fu_172_p4 assign process. ///
always @ (ap_CS_fsm or indvar2_reg_168 or ap_reg_ppiten_pp0_it1 or tmp_4_reg_683 or j_reg_678)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (tmp_4_reg_683 == ap_const_lv1_0) & (ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm))) begin
indvar2_phi_fu_172_p4 = j_reg_678;
end else begin
indvar2_phi_fu_172_p4 = indvar2_reg_168;
end
end
/// indvar4_phi_fu_183_p4 assign process. ///
always @ (ap_CS_fsm or indvar4_reg_179 or ap_reg_ppiten_pp1_it1 or tmp_13_reg_707 or indvar_next5_reg_711)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & (ap_const_lv1_0 == tmp_13_reg_707) & (ap_ST_pp1_stg0_fsm_5 == ap_CS_fsm))) begin
indvar4_phi_fu_183_p4 = indvar_next5_reg_711;
end else begin
indvar4_phi_fu_183_p4 = indvar4_reg_179;
end
end
/// indvar_phi_fu_205_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_201 or ap_reg_ppiten_pp3_it1 or exitcond1_reg_755 or indvar_next_reg_759)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
indvar_phi_fu_205_p4 = indvar_next_reg_759;
end else begin
indvar_phi_fu_205_p4 = indvar_reg_201;
end
end
/// j_3_phi_fu_216_p4 assign process. ///
always @ (ap_CS_fsm or j_3_reg_212 or ap_reg_ppiten_pp3_it1 or exitcond1_reg_755 or tmp_41_reg_774)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_reg_755))) begin
j_3_phi_fu_216_p4 = tmp_41_reg_774;
end else begin
j_3_phi_fu_216_p4 = j_3_reg_212;
end
end
/// v_address0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it10 or exitcond1_fu_565_p2 or ap_reg_ppstg_exitcond1_reg_755_pp3_it10 or ap_reg_ppstg_v_addr_12_reg_764_pp3_it10 or tmp_47_fu_596_p1)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it10))) begin
v_address0 = ap_reg_ppstg_v_addr_12_reg_764_pp3_it10;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
v_address0 = tmp_47_fu_596_p1;
end else begin
v_address0 = ap_reg_ppstg_v_addr_12_reg_764_pp3_it10;
end
end
/// v_address1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it11 or exitcond1_fu_565_p2 or ap_reg_ppstg_exitcond1_reg_755_pp3_it11 or ap_reg_ppstg_v_addr_1_reg_769_pp3_it11 or tmp_48_fu_606_p1)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it11))) begin
v_address1 = ap_reg_ppstg_v_addr_1_reg_769_pp3_it11;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2))) begin
v_address1 = tmp_48_fu_606_p1;
end else begin
v_address1 = ap_reg_ppstg_v_addr_1_reg_769_pp3_it11;
end
end
/// v_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it10 or exitcond1_fu_565_p2 or ap_reg_ppstg_exitcond1_reg_755_pp3_it10)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it10)))) begin
v_ce0 = ap_const_logic_1;
end else begin
v_ce0 = ap_const_logic_0;
end
end
/// v_ce1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it0 or ap_reg_ppiten_pp3_it11 or exitcond1_fu_565_p2 or ap_reg_ppstg_exitcond1_reg_755_pp3_it11)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & (ap_ST_pp3_stg0_fsm_10 == ap_CS_fsm) & (ap_const_lv1_0 == exitcond1_fu_565_p2)) | ((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it11)))) begin
v_ce1 = ap_const_logic_1;
end else begin
v_ce1 = ap_const_logic_0;
end
end
/// v_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it10 or ap_reg_ppstg_exitcond1_reg_755_pp3_it10)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it10) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it10))) begin
v_we0 = ap_const_logic_1;
end else begin
v_we0 = ap_const_logic_0;
end
end
/// v_we1 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp3_it11 or ap_reg_ppstg_exitcond1_reg_755_pp3_it11)
begin
if (((ap_ST_pp3_stg1_fsm_11 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it11) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond1_reg_755_pp3_it11))) begin
v_we1 = ap_const_logic_1;
end else begin
v_we1 = ap_const_logic_0;
end
end
assign a_addr1_fu_554_p2 = (a_addr_cast_fu_550_p1 + j_2_fu_520_p2);
assign a_addr2_fu_442_p2 = (a_addr9_cast_fu_438_p1 + j_1_fu_417_p2);
assign a_addr3_cast_fu_530_p1 = {{18{1'b0}}, {a_addr3_fu_525_p2}};
assign a_addr3_fu_525_p2 = tmp36_cast_reg_667 << ap_const_lv14_7;
assign a_addr4_fu_534_p2 = (a_addr3_cast_fu_530_p1 + j_2_fu_520_p2);
assign a_addr5_fu_369_p2 = (tmp37_cast_reg_673 + tmp7_fu_358_p2);
assign a_addr6_fu_453_p2 = j_1_fu_417_p2 << ap_const_lv32_7;
assign a_addr7_fu_459_p2 = (a_addr6_fu_453_p2 + tmp1_reg_646);
assign a_addr8_fu_364_p2 = (tmp34_cast_reg_657 + tmp7_fu_358_p2);
assign a_addr9_cast_fu_438_p1 = {{18{1'b0}}, {a_addr9_fu_433_p2}};
assign a_addr9_fu_433_p2 = tmp36_cast_reg_667 << ap_const_lv14_7;
assign a_addr_1_reg_6920 = {{32{a_addr8_fu_364_p2[31]}}, {a_addr8_fu_364_p2}};
assign a_addr_2_6_reg_7160 = {{32{a_addr2_fu_442_p2[31]}}, {a_addr2_fu_442_p2}};
assign a_addr_2_reg_6870 = {{32{a_addr5_fu_369_p2[31]}}, {a_addr5_fu_369_p2}};
assign a_addr_3_reg_7210 = {{32{a_addr7_fu_459_p2[31]}}, {a_addr7_fu_459_p2}};
assign a_addr_4_reg_7450 = {{32{a_addr4_fu_534_p2[31]}}, {a_addr4_fu_534_p2}};
assign a_addr_5_reg_7500 = {{32{a_addr1_fu_554_p2[31]}}, {a_addr1_fu_554_p2}};
assign a_addr_cast_fu_550_p1 = {{16{1'b0}}, {a_addr_fu_545_p2}};
assign a_addr_fu_545_p2 = tmp33_cast_reg_651 << ap_const_lv16_7;
assign a_d0 = reg_284;
assign exitcond1_fu_565_p2 = (indvar_phi_fu_205_p4 == ap_const_lv8_80? 1'b1: 1'b0);
assign exitcond_fu_509_p2 = (indvar1_phi_fu_194_p4 == tmp10_reg_731? 1'b1: 1'b0);
assign grp_fu_224_ce = ap_const_logic_1;
assign grp_fu_228_ce = ap_const_logic_1;
assign grp_fu_232_ce = ap_const_logic_1;
assign grp_fu_236_ce = ap_const_logic_1;
assign ip_cast1_cast_fu_300_p1 = {{2{1'b0}}, {ip}};
assign ip_cast2_fu_296_p1 = {{1{1'b0}}, {ip}};
assign iq_cast1_fu_469_p1 = {{1{1'b0}}, {iq}};
assign iq_cast_cast_fu_395_p1 = {{1{1'b0}}, {iq}};
assign j_1_fu_417_p2 = (tmp6_cast_reg_702 + indvar4_phi_fu_183_p4);
assign j_2_fu_520_p2 = (tmp_cast_reg_726 + indvar1_phi_fu_194_p4);
assign j_fu_374_p2 = (indvar2_phi_fu_172_p4 + ap_const_lv32_1);
assign tmp1_fu_314_p1 = {{23{1'b0}}, {iq}};
assign tmp2_fu_326_p2 = (tmp33_cast1_fu_318_p1 + ap_const_lv10_80);
assign tmp33_cast1_fu_318_p1 = {{1{1'b0}}, {iq}};
assign tmp33_cast_fu_322_p1 = {{7{1'b0}}, {iq}};
assign tmp34_cast_fu_332_p1 = {{22{1'b0}}, {tmp2_fu_326_p2}};
assign tmp36_cast1_fu_336_p1 = {{9{1'b0}}, {ip}};
assign tmp36_cast2_fu_340_p1 = {{2{1'b0}}, {ip}};
assign tmp36_cast_fu_344_p1 = {{7{1'b0}}, {ip}};
assign tmp37_cast_fu_354_p1 = {{23{1'b0}}, {tmp5_fu_348_p2}};
assign tmp3_fu_482_p2 = (tmp_fu_472_p2 > ap_const_lv10_81? 1'b1: 1'b0);
assign tmp4_fu_488_p3 = ((tmp3_fu_482_p2)? iq: ap_const_lv9_80);
assign tmp5_fu_348_p2 = (tmp36_cast2_fu_340_p1 | ap_const_lv9_80);
assign tmp6_cast_fu_413_p1 = {{24{1'b0}}, {tmp6_fu_408_p2}};
assign tmp6_fu_408_p2 = (ip_cast2_reg_636 + ap_const_lv8_1);
assign tmp7_fu_358_p2 = indvar2_phi_fu_172_p4 << ap_const_lv32_7;
assign tmp8_fu_495_p1 = {{1{1'b0}}, {tmp4_fu_488_p3}};
assign tmp9_fu_499_p2 = (tmp8_fu_495_p1 - iq_cast1_fu_469_p1);
assign tmp_13_fu_422_p2 = ($signed(tmp_5_cast_reg_697) < $signed(j_1_fu_417_p2)? 1'b1: 1'b0);
assign tmp_14_fu_390_p1 = {{32{a_addr8_fu_364_p2[31]}}, {a_addr8_fu_364_p2}};
assign tmp_1_fu_304_p2 = (ip_cast1_cast_fu_300_p1 + ap_const_lv9_1FF);
assign tmp_32_fu_448_p1 = {{32{a_addr2_fu_442_p2[31]}}, {a_addr2_fu_442_p2}};
assign tmp_32_trn_cast_fu_577_p1 = {{7{1'b0}}, {j_3_phi_fu_216_p4}};
assign tmp_3_fu_385_p1 = {{32{a_addr5_fu_369_p2[31]}}, {a_addr5_fu_369_p2}};
assign tmp_42_fu_464_p1 = {{32{a_addr7_fu_459_p2[31]}}, {a_addr7_fu_459_p2}};
assign tmp_44_fu_540_p1 = {{32{a_addr4_fu_534_p2[31]}}, {a_addr4_fu_534_p2}};
assign tmp_46_fu_560_p1 = {{32{a_addr1_fu_554_p2[31]}}, {a_addr1_fu_554_p2}};
assign tmp_47_fu_596_p1 = {{48{1'b0}}, {v_addr1_fu_591_p2}};
assign tmp_48_fu_606_p1 = {{48{1'b0}}, {v_addr2_fu_601_p2}};
assign tmp_4_fu_380_p2 = ($signed(tmp_1_cast_reg_641) < $signed(j_fu_374_p2)? 1'b1: 1'b0);
assign tmp_5_fu_398_p2 = (iq_cast_cast_fu_395_p1 + ap_const_lv10_3FF);
assign tmp_cast_fu_478_p1 = {{22{1'b0}}, {tmp_fu_472_p2}};
assign tmp_fu_472_p2 = (iq_cast1_fu_469_p1 + ap_const_lv10_1);
assign v_addr1_fu_591_p2 = (v_addr_cast_fu_587_p1 | tmp36_cast1_reg_662);
assign v_addr2_fu_601_p2 = (v_addr_cast_fu_587_p1 + tmp33_cast_reg_651);
assign v_addr_12_reg_7640 = {{48{1'b0}}, {v_addr1_fu_591_p2}};
assign v_addr_1_reg_7690 = {{48{1'b0}}, {v_addr2_fu_601_p2}};
assign v_addr_cast_fu_587_p1 = {{1{1'b0}}, {v_addr_fu_581_p2}};
assign v_addr_fu_581_p2 = tmp_32_trn_cast_fu_577_p1 << ap_const_lv15_7;
assign v_d0 = reg_284;
assign v_d1 = ap_reg_ppstg_reg_290_pp3_it10;
always @ (ap_clk)
begin
ip_cast2_reg_636[7] <= 1'b0;
end
always @ (ap_clk)
begin
tmp1_reg_646[9] <= 1'b0;
tmp1_reg_646[10] <= 1'b0;
tmp1_reg_646[11] <= 1'b0;
tmp1_reg_646[12] <= 1'b0;
tmp1_reg_646[13] <= 1'b0;
tmp1_reg_646[14] <= 1'b0;
tmp1_reg_646[15] <= 1'b0;
tmp1_reg_646[16] <= 1'b0;
tmp1_reg_646[17] <= 1'b0;
tmp1_reg_646[18] <= 1'b0;
tmp1_reg_646[19] <= 1'b0;
tmp1_reg_646[20] <= 1'b0;
tmp1_reg_646[21] <= 1'b0;
tmp1_reg_646[22] <= 1'b0;
tmp1_reg_646[23] <= 1'b0;
tmp1_reg_646[24] <= 1'b0;
tmp1_reg_646[25] <= 1'b0;
tmp1_reg_646[26] <= 1'b0;
tmp1_reg_646[27] <= 1'b0;
tmp1_reg_646[28] <= 1'b0;
tmp1_reg_646[29] <= 1'b0;
tmp1_reg_646[30] <= 1'b0;
tmp1_reg_646[31] <= 1'b0;
end
always @ (ap_clk)
begin
tmp33_cast_reg_651[9] <= 1'b0;
tmp33_cast_reg_651[10] <= 1'b0;
tmp33_cast_reg_651[11] <= 1'b0;
tmp33_cast_reg_651[12] <= 1'b0;
tmp33_cast_reg_651[13] <= 1'b0;
tmp33_cast_reg_651[14] <= 1'b0;
tmp33_cast_reg_651[15] <= 1'b0;
end
always @ (ap_clk)
begin
tmp34_cast_reg_657[10] <= 1'b0;
tmp34_cast_reg_657[11] <= 1'b0;
tmp34_cast_reg_657[12] <= 1'b0;
tmp34_cast_reg_657[13] <= 1'b0;
tmp34_cast_reg_657[14] <= 1'b0;
tmp34_cast_reg_657[15] <= 1'b0;
tmp34_cast_reg_657[16] <= 1'b0;
tmp34_cast_reg_657[17] <= 1'b0;
tmp34_cast_reg_657[18] <= 1'b0;
tmp34_cast_reg_657[19] <= 1'b0;
tmp34_cast_reg_657[20] <= 1'b0;
tmp34_cast_reg_657[21] <= 1'b0;
tmp34_cast_reg_657[22] <= 1'b0;
tmp34_cast_reg_657[23] <= 1'b0;
tmp34_cast_reg_657[24] <= 1'b0;
tmp34_cast_reg_657[25] <= 1'b0;
tmp34_cast_reg_657[26] <= 1'b0;
tmp34_cast_reg_657[27] <= 1'b0;
tmp34_cast_reg_657[28] <= 1'b0;
tmp34_cast_reg_657[29] <= 1'b0;
tmp34_cast_reg_657[30] <= 1'b0;
tmp34_cast_reg_657[31] <= 1'b0;
end
always @ (ap_clk)
begin
tmp36_cast1_reg_662[7] <= 1'b0;
tmp36_cast1_reg_662[8] <= 1'b0;
tmp36_cast1_reg_662[9] <= 1'b0;
tmp36_cast1_reg_662[10] <= 1'b0;
tmp36_cast1_reg_662[11] <= 1'b0;
tmp36_cast1_reg_662[12] <= 1'b0;
tmp36_cast1_reg_662[13] <= 1'b0;
tmp36_cast1_reg_662[14] <= 1'b0;
tmp36_cast1_reg_662[15] <= 1'b0;
end
always @ (ap_clk)
begin
tmp36_cast_reg_667[7] <= 1'b0;
tmp36_cast_reg_667[8] <= 1'b0;
tmp36_cast_reg_667[9] <= 1'b0;
tmp36_cast_reg_667[10] <= 1'b0;
tmp36_cast_reg_667[11] <= 1'b0;
tmp36_cast_reg_667[12] <= 1'b0;
tmp36_cast_reg_667[13] <= 1'b0;
end
always @ (ap_clk)
begin
tmp37_cast_reg_673[7] <= 1'b1;
tmp37_cast_reg_673[8] <= 1'b0;
tmp37_cast_reg_673[9] <= 1'b0;
tmp37_cast_reg_673[10] <= 1'b0;
tmp37_cast_reg_673[11] <= 1'b0;
tmp37_cast_reg_673[12] <= 1'b0;
tmp37_cast_reg_673[13] <= 1'b0;
tmp37_cast_reg_673[14] <= 1'b0;
tmp37_cast_reg_673[15] <= 1'b0;
tmp37_cast_reg_673[16] <= 1'b0;
tmp37_cast_reg_673[17] <= 1'b0;
tmp37_cast_reg_673[18] <= 1'b0;
tmp37_cast_reg_673[19] <= 1'b0;
tmp37_cast_reg_673[20] <= 1'b0;
tmp37_cast_reg_673[21] <= 1'b0;
tmp37_cast_reg_673[22] <= 1'b0;
tmp37_cast_reg_673[23] <= 1'b0;
tmp37_cast_reg_673[24] <= 1'b0;
tmp37_cast_reg_673[25] <= 1'b0;
tmp37_cast_reg_673[26] <= 1'b0;
tmp37_cast_reg_673[27] <= 1'b0;
tmp37_cast_reg_673[28] <= 1'b0;
tmp37_cast_reg_673[29] <= 1'b0;
tmp37_cast_reg_673[30] <= 1'b0;
tmp37_cast_reg_673[31] <= 1'b0;
end
always @ (ap_clk)
begin
tmp6_cast_reg_702[8] <= 1'b0;
tmp6_cast_reg_702[9] <= 1'b0;
tmp6_cast_reg_702[10] <= 1'b0;
tmp6_cast_reg_702[11] <= 1'b0;
tmp6_cast_reg_702[12] <= 1'b0;
tmp6_cast_reg_702[13] <= 1'b0;
tmp6_cast_reg_702[14] <= 1'b0;
tmp6_cast_reg_702[15] <= 1'b0;
tmp6_cast_reg_702[16] <= 1'b0;
tmp6_cast_reg_702[17] <= 1'b0;
tmp6_cast_reg_702[18] <= 1'b0;
tmp6_cast_reg_702[19] <= 1'b0;
tmp6_cast_reg_702[20] <= 1'b0;
tmp6_cast_reg_702[21] <= 1'b0;
tmp6_cast_reg_702[22] <= 1'b0;
tmp6_cast_reg_702[23] <= 1'b0;
tmp6_cast_reg_702[24] <= 1'b0;
tmp6_cast_reg_702[25] <= 1'b0;
tmp6_cast_reg_702[26] <= 1'b0;
tmp6_cast_reg_702[27] <= 1'b0;
tmp6_cast_reg_702[28] <= 1'b0;
tmp6_cast_reg_702[29] <= 1'b0;
tmp6_cast_reg_702[30] <= 1'b0;
tmp6_cast_reg_702[31] <= 1'b0;
end
always @ (ap_clk)
begin
tmp_cast_reg_726[10] <= 1'b0;
tmp_cast_reg_726[11] <= 1'b0;
tmp_cast_reg_726[12] <= 1'b0;
tmp_cast_reg_726[13] <= 1'b0;
tmp_cast_reg_726[14] <= 1'b0;
tmp_cast_reg_726[15] <= 1'b0;
tmp_cast_reg_726[16] <= 1'b0;
tmp_cast_reg_726[17] <= 1'b0;
tmp_cast_reg_726[18] <= 1'b0;
tmp_cast_reg_726[19] <= 1'b0;
tmp_cast_reg_726[20] <= 1'b0;
tmp_cast_reg_726[21] <= 1'b0;
tmp_cast_reg_726[22] <= 1'b0;
tmp_cast_reg_726[23] <= 1'b0;
tmp_cast_reg_726[24] <= 1'b0;
tmp_cast_reg_726[25] <= 1'b0;
tmp_cast_reg_726[26] <= 1'b0;
tmp_cast_reg_726[27] <= 1'b0;
tmp_cast_reg_726[28] <= 1'b0;
tmp_cast_reg_726[29] <= 1'b0;
tmp_cast_reg_726[30] <= 1'b0;
tmp_cast_reg_726[31] <= 1'b0;
end
endmodule //do_rotate
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module do_rotate_grp_fu_224_ACMP_faddfsub_1(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module do_rotate_grp_fu_228_ACMP_faddfsub_2(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 5 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
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