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// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_634_ACMP_fmul_17(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_640_ACMP_fmul_18(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_652_ACMP_fmul_19(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_658_ACMP_fmul_20(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_663_ACMP_fmul_21(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_668_ACMP_fmul_22(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_673_ACMP_fmul_23(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_678_ACMP_fmul_24(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_683_ACMP_fmul_25(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_692_ACMP_fmul_26(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_696_ACMP_fmul_27(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_701_ACMP_fmul_28(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_705_ACMP_fmul_29(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_709_ACMP_fmul_30(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_714_ACMP_fmul_31(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_718_ACMP_fmul_32(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_722_ACMP_fmul_33(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_727_ACMP_fmul_34(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_732_ACMP_fmul_35(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_737_ACMP_fmul_36(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_742_ACMP_fmul_37(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_747_ACMP_fmul_38(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_755_ACMP_fmul_39(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_759_ACMP_fmul_40(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_763_ACMP_fmul_41(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_767_ACMP_fmul_42(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_771_ACMP_fmul_43(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_775_ACMP_fmul_44(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_779_ACMP_fmul_45(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_783_ACMP_fmul_46(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_787_ACMP_fmul_47(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_791_ACMP_fmul_48(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
/*-----------------------------------------------------------------------
-- AESL_FPSim_pkg.v:
-- Floating point simulation model for verilog.
--
-----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-- FAdd, FSub, FAddSub, FMul, FDiv, FSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision units.
-- DAdd, DSub, DAddSub, DMul, DDiv, DSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision Add.
-------------------------------------------------------------------------------
*/
module ACMP_fadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Sub.
-------------------------------------------------------------------------------
*/
module ACMP_fsub_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision AddSub.
-------------------------------------------------------------------------------
*/
module ACMP_faddfsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_faddfsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision ADD
-------------------------------------------------------------------------------
*/
module ACMP_dadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Sub
-------------------------------------------------------------------------------
*/
module ACMP_dsub_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision AddSub
-------------------------------------------------------------------------------
*/
module ACMP_dadddsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadddsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_fcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_dcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_fptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_dptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_sitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_sitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_fptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_dptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_uitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_uitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- single to double precision
-------------------------------------------------------------------------------
*/
module ACMP_fpext_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fpext(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- double to single precision
-------------------------------------------------------------------------------
*/
module ACMP_fptrunc_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptrunc(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
|
// ==============================================================
// RTL generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
/* X_x,
X_y,
X_z,
X_qr,
X_qx,
X_qy,
X_qz,
U_x,
U_y,
U_z,
U_qr,
U_qx,
U_qy,
U_qz, */
df_dx_address0,
df_dx_ce0,
df_dx_we0,
df_dx_d0,
df_dx_q0,
df_dx_address1,
df_dx_ce1,
df_dx_we1,
df_dx_d1,
df_dx_q1,
out_X_oplus_U_x_address0,
out_X_oplus_U_x_ce0,
out_X_oplus_U_x_we0,
out_X_oplus_U_x_d0,
out_X_oplus_U_x_q0,
out_X_oplus_U_x_address1,
out_X_oplus_U_x_ce1,
out_X_oplus_U_x_we1,
out_X_oplus_U_x_d1,
out_X_oplus_U_x_q1,
out_X_oplus_U_y_address0,
out_X_oplus_U_y_ce0,
out_X_oplus_U_y_we0,
out_X_oplus_U_y_d0,
out_X_oplus_U_y_q0,
out_X_oplus_U_y_address1,
out_X_oplus_U_y_ce1,
out_X_oplus_U_y_we1,
out_X_oplus_U_y_d1,
out_X_oplus_U_y_q1,
out_X_oplus_U_z_address0,
out_X_oplus_U_z_ce0,
out_X_oplus_U_z_we0,
out_X_oplus_U_z_d0,
out_X_oplus_U_z_q0,
out_X_oplus_U_z_address1,
out_X_oplus_U_z_ce1,
out_X_oplus_U_z_we1,
out_X_oplus_U_z_d1,
out_X_oplus_U_z_q1,
out_X_oplus_U_qr_address0,
out_X_oplus_U_qr_ce0,
out_X_oplus_U_qr_we0,
out_X_oplus_U_qr_d0,
out_X_oplus_U_qr_q0,
out_X_oplus_U_qr_address1,
out_X_oplus_U_qr_ce1,
out_X_oplus_U_qr_we1,
out_X_oplus_U_qr_d1,
out_X_oplus_U_qr_q1,
out_X_oplus_U_qx_address0,
out_X_oplus_U_qx_ce0,
out_X_oplus_U_qx_we0,
out_X_oplus_U_qx_d0,
out_X_oplus_U_qx_q0,
out_X_oplus_U_qx_address1,
out_X_oplus_U_qx_ce1,
out_X_oplus_U_qx_we1,
out_X_oplus_U_qx_d1,
out_X_oplus_U_qx_q1,
out_X_oplus_U_qy_address0,
out_X_oplus_U_qy_ce0,
out_X_oplus_U_qy_we0,
out_X_oplus_U_qy_d0,
out_X_oplus_U_qy_q0,
out_X_oplus_U_qy_address1,
out_X_oplus_U_qy_ce1,
out_X_oplus_U_qy_we1,
out_X_oplus_U_qy_d1,
out_X_oplus_U_qy_q1,
out_X_oplus_U_qz_address0,
out_X_oplus_U_qz_ce0,
out_X_oplus_U_qz_we0,
out_X_oplus_U_qz_d0,
out_X_oplus_U_qz_q0,
out_X_oplus_U_qz_address1,
out_X_oplus_U_qz_ce1,
out_X_oplus_U_qz_we1,
out_X_oplus_U_qz_d1,
out_X_oplus_U_qz_q1,
shift_clk,
shift_in_bit0
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
/*
input [31:0] X_x;
input [31:0] X_y;
input [31:0] X_z;
input [31:0] X_qr;
input [31:0] X_qx;
input [31:0] X_qy;
input [31:0] X_qz;
input [31:0] U_x;
input [31:0] U_y;
input [31:0] U_z;
input [31:0] U_qr;
input [31:0] U_qx;
input [31:0] U_qy;
input [31:0] U_qz;
*/
output [4:0] df_dx_address0;
output df_dx_ce0;
output df_dx_we0;
output [31:0] df_dx_d0;
input [31:0] df_dx_q0;
output [4:0] df_dx_address1;
output df_dx_ce1;
output df_dx_we1;
output [31:0] df_dx_d1;
input [31:0] df_dx_q1;
output [0:0] out_X_oplus_U_x_address0;
output out_X_oplus_U_x_ce0;
output out_X_oplus_U_x_we0;
output [31:0] out_X_oplus_U_x_d0;
input [31:0] out_X_oplus_U_x_q0;
output [0:0] out_X_oplus_U_x_address1;
output out_X_oplus_U_x_ce1;
output out_X_oplus_U_x_we1;
output [31:0] out_X_oplus_U_x_d1;
input [31:0] out_X_oplus_U_x_q1;
output [0:0] out_X_oplus_U_y_address0;
output out_X_oplus_U_y_ce0;
output out_X_oplus_U_y_we0;
output [31:0] out_X_oplus_U_y_d0;
input [31:0] out_X_oplus_U_y_q0;
output [0:0] out_X_oplus_U_y_address1;
output out_X_oplus_U_y_ce1;
output out_X_oplus_U_y_we1;
output [31:0] out_X_oplus_U_y_d1;
input [31:0] out_X_oplus_U_y_q1;
output [0:0] out_X_oplus_U_z_address0;
output out_X_oplus_U_z_ce0;
output out_X_oplus_U_z_we0;
output [31:0] out_X_oplus_U_z_d0;
input [31:0] out_X_oplus_U_z_q0;
output [0:0] out_X_oplus_U_z_address1;
output out_X_oplus_U_z_ce1;
output out_X_oplus_U_z_we1;
output [31:0] out_X_oplus_U_z_d1;
input [31:0] out_X_oplus_U_z_q1;
output [0:0] out_X_oplus_U_qr_address0;
output out_X_oplus_U_qr_ce0;
output out_X_oplus_U_qr_we0;
output [31:0] out_X_oplus_U_qr_d0;
input [31:0] out_X_oplus_U_qr_q0;
output [0:0] out_X_oplus_U_qr_address1;
output out_X_oplus_U_qr_ce1;
output out_X_oplus_U_qr_we1;
output [31:0] out_X_oplus_U_qr_d1;
input [31:0] out_X_oplus_U_qr_q1;
output [0:0] out_X_oplus_U_qx_address0;
output out_X_oplus_U_qx_ce0;
output out_X_oplus_U_qx_we0;
output [31:0] out_X_oplus_U_qx_d0;
input [31:0] out_X_oplus_U_qx_q0;
output [0:0] out_X_oplus_U_qx_address1;
output out_X_oplus_U_qx_ce1;
output out_X_oplus_U_qx_we1;
output [31:0] out_X_oplus_U_qx_d1;
input [31:0] out_X_oplus_U_qx_q1;
output [0:0] out_X_oplus_U_qy_address0;
output out_X_oplus_U_qy_ce0;
output out_X_oplus_U_qy_we0;
output [31:0] out_X_oplus_U_qy_d0;
input [31:0] out_X_oplus_U_qy_q0;
output [0:0] out_X_oplus_U_qy_address1;
output out_X_oplus_U_qy_ce1;
output out_X_oplus_U_qy_we1;
output [31:0] out_X_oplus_U_qy_d1;
input [31:0] out_X_oplus_U_qy_q1;
output [0:0] out_X_oplus_U_qz_address0;
output out_X_oplus_U_qz_ce0;
output out_X_oplus_U_qz_we0;
output [31:0] out_X_oplus_U_qz_d0;
input [31:0] out_X_oplus_U_qz_q0;
output [0:0] out_X_oplus_U_qz_address1;
output out_X_oplus_U_qz_ce1;
output out_X_oplus_U_qz_we1;
output [31:0] out_X_oplus_U_qz_d1;
input [31:0] out_X_oplus_U_qz_q1;
//Use a shift register to remove 395 output pins
// which will allow this design to fit on a stratixIV device
input shift_clk;
input shift_in_bit0;
reg [447:0] shift_in;
always@(posedge shift_in) begin
shift_in <= {shift_in[446:0],shift_in_bit0};
end
wire [31:0] X_x;
wire [31:0] X_y;
wire [31:0] X_z;
wire [31:0] X_qr;
wire [31:0] X_qx;
wire [31:0] X_qy;
wire [31:0] X_qz;
wire [31:0] U_x;
wire [31:0] U_y;
wire [31:0] U_z;
wire [31:0] U_qr;
wire [31:0] U_qx;
wire [31:0] U_qy;
wire [31:0] U_qz;
assign X_x = shift_in[31:0];
assign X_y = shift_in[63:32];
assign X_z = shift_in[95:64];
assign X_qr = shift_in[127:96];
assign X_qx = shift_in[159:128];
assign X_qy = shift_in[191:160];
assign X_qz = shift_in[223:192];
assign U_x = shift_in[255:224];
assign U_y = shift_in[287:256];
assign U_z = shift_in[319:288];
assign U_qr = shift_in[351:320];
assign U_qx = shift_in[383:352];
assign U_qy = shift_in[415:384];
assign U_qz = shift_in[447:416];
reg ap_done;
reg ap_idle;
reg[4:0] df_dx_address0;
reg df_dx_ce0;
reg df_dx_we0;
reg[31:0] df_dx_d0;
reg[4:0] df_dx_address1;
reg df_dx_ce1;
reg df_dx_we1;
reg[31:0] df_dx_d1;
reg out_X_oplus_U_x_ce0;
reg out_X_oplus_U_x_we0;
reg out_X_oplus_U_y_ce0;
reg out_X_oplus_U_y_we0;
reg out_X_oplus_U_z_ce0;
reg out_X_oplus_U_z_we0;
reg out_X_oplus_U_qr_ce0;
reg out_X_oplus_U_qr_we0;
reg out_X_oplus_U_qx_ce0;
reg out_X_oplus_U_qx_we0;
reg out_X_oplus_U_qy_ce0;
reg out_X_oplus_U_qy_we0;
reg out_X_oplus_U_qz_ce0;
reg out_X_oplus_U_qz_we0;
reg [6:0] ap_CS_fsm;
wire [31:0] grp_fu_634_p2;
reg [31:0] reg_795;
wire [31:0] grp_fu_640_p2;
reg [31:0] reg_829;
wire [31:0] grp_fu_555_p2;
reg [31:0] reg_850;
wire [31:0] grp_fu_560_p2;
reg [31:0] reg_869;
reg [31:0] reg_889;
reg [31:0] reg_903;
reg [31:0] reg_931;
reg [31:0] reg_943;
reg [31:0] reg_954;
wire [31:0] grp_fu_566_p2;
reg [31:0] reg_961;
reg [31:0] reg_976;
wire [31:0] grp_fu_571_p2;
reg [31:0] reg_983;
reg [31:0] reg_990;
reg [31:0] reg_999;
reg [31:0] reg_1006;
reg [31:0] reg_1013;
wire [31:0] grp_fu_652_p2;
reg [31:0] reg_1019;
reg [31:0] reg_1038;
reg [31:0] reg_1047;
wire [31:0] grp_fu_658_p2;
reg [31:0] reg_1057;
wire [31:0] grp_fu_663_p2;
reg [31:0] reg_1072;
wire [31:0] grp_fu_668_p2;
reg [31:0] reg_1085;
wire [31:0] grp_fu_673_p2;
reg [31:0] reg_1098;
wire [31:0] grp_fu_678_p2;
reg [31:0] reg_1110;
wire [31:0] grp_fu_683_p2;
reg [31:0] reg_1123;
reg [31:0] reg_1136;
reg [31:0] reg_1144;
reg [31:0] reg_1152;
wire [31:0] grp_fu_583_p2;
reg [31:0] reg_1157;
reg [31:0] reg_1167;
wire [31:0] grp_fu_588_p2;
reg [31:0] reg_1178;
wire [31:0] grp_fu_592_p2;
reg [31:0] reg_1186;
wire [31:0] grp_fu_596_p2;
reg [31:0] reg_1194;
wire [31:0] grp_fu_692_p2;
reg [31:0] reg_1201;
wire [31:0] grp_fu_600_p2;
reg [31:0] reg_1212;
wire [31:0] grp_fu_696_p2;
reg [31:0] reg_1220;
wire [31:0] grp_fu_701_p2;
reg [31:0] reg_1231;
wire [31:0] grp_fu_705_p2;
reg [31:0] reg_1242;
wire [31:0] grp_fu_709_p2;
reg [31:0] reg_1252;
reg [31:0] reg_1261;
wire [31:0] grp_fu_604_p2;
reg [31:0] reg_1270;
wire [31:0] grp_fu_608_p2;
reg [31:0] reg_1277;
wire [31:0] grp_fu_612_p2;
reg [31:0] reg_1284;
reg [31:0] reg_1291;
wire [31:0] grp_fu_714_p2;
reg [31:0] reg_1299;
wire [31:0] grp_fu_718_p2;
reg [31:0] reg_1307;
wire [31:0] grp_fu_722_p2;
reg [31:0] reg_1315;
wire [31:0] grp_fu_727_p2;
reg [31:0] reg_1325;
wire [31:0] grp_fu_732_p2;
reg [31:0] reg_1335;
wire [31:0] grp_fu_737_p2;
reg [31:0] reg_1345;
wire [31:0] grp_fu_742_p2;
reg [31:0] reg_1355;
wire [31:0] grp_fu_747_p2;
reg [31:0] reg_1365;
reg [31:0] reg_1375;
reg [31:0] reg_1383;
reg [31:0] reg_1394;
reg [31:0] reg_1403;
reg [31:0] reg_1414;
reg [31:0] reg_1425;
reg [31:0] reg_1435;
reg [31:0] reg_1444;
reg [31:0] reg_1454;
reg [31:0] reg_1460;
reg [31:0] reg_1467;
reg [31:0] reg_1473;
reg [31:0] reg_1479;
reg [31:0] reg_1485;
wire [31:0] grp_fu_755_p2;
reg [31:0] reg_1491;
wire [31:0] grp_fu_759_p2;
reg [31:0] reg_1497;
wire [31:0] grp_fu_763_p2;
reg [31:0] reg_1503;
wire [31:0] grp_fu_767_p2;
reg [31:0] reg_1509;
wire [31:0] grp_fu_771_p2;
reg [31:0] reg_1515;
reg [31:0] reg_1521;
reg [31:0] reg_1530;
reg [31:0] reg_1536;
reg [31:0] reg_1542;
reg [31:0] reg_1547;
reg [31:0] reg_1552;
reg [31:0] reg_1557;
reg [31:0] reg_1562;
reg [31:0] reg_1567;
reg [31:0] reg_1572;
wire [31:0] grp_fu_618_p2;
reg [31:0] reg_1577;
wire [31:0] grp_fu_622_p2;
reg [31:0] reg_1583;
wire [31:0] grp_fu_626_p2;
reg [31:0] reg_1589;
wire [31:0] grp_fu_630_p2;
reg [31:0] reg_1595;
reg [31:0] tmp_reg_1756;
reg [31:0] tmp_48_reg_1776;
reg [31:0] X_plus_U_qz_reg_1782;
reg [31:0] tmp_4_reg_1793;
reg [30:0] tmp_53_reg_1799;
wire [31:0] tmp1_i1_fu_1624_p1;
reg [31:0] tmp1_i1_reg_1804;
reg [30:0] tmp_52_reg_1809;
wire [31:0] tmp1_i_fu_1652_p1;
reg [31:0] tmp1_i_reg_1838;
reg [31:0] tmp_27_reg_1869;
reg [31:0] tmp_163_reg_1876;
reg [31:0] tmp_169_reg_1881;
reg [31:0] tmp_42_reg_1886;
reg [31:0] tmp_43_reg_1894;
reg [31:0] tmp_239_reg_1902;
reg [31:0] tmp_253_reg_1907;
reg [31:0] tmp_281_reg_1912;
wire [31:0] grp_fu_775_p2;
reg [31:0] tmp_324_reg_1917;
wire [31:0] grp_fu_779_p2;
reg [31:0] tmp_330_reg_1922;
wire [31:0] grp_fu_783_p2;
reg [31:0] tmp_331_reg_1927;
wire [31:0] grp_fu_787_p2;
reg [31:0] tmp_337_reg_1932;
wire [31:0] grp_fu_791_p2;
reg [31:0] tmp_338_reg_1937;
reg [31:0] grp_fu_555_p0;
reg [31:0] grp_fu_555_p1;
reg [31:0] grp_fu_560_p0;
reg [31:0] grp_fu_560_p1;
reg [31:0] grp_fu_566_p0;
reg [31:0] grp_fu_566_p1;
reg [31:0] grp_fu_571_p0;
reg [31:0] grp_fu_571_p1;
reg [31:0] grp_fu_583_p0;
reg [31:0] grp_fu_583_p1;
reg [31:0] grp_fu_588_p0;
reg [31:0] grp_fu_588_p1;
reg [31:0] grp_fu_592_p0;
reg [31:0] grp_fu_592_p1;
reg [31:0] grp_fu_596_p0;
reg [31:0] grp_fu_596_p1;
reg [31:0] grp_fu_600_p0;
reg [31:0] grp_fu_600_p1;
reg [31:0] grp_fu_604_p0;
reg [31:0] grp_fu_604_p1;
reg [31:0] grp_fu_608_p0;
reg [31:0] grp_fu_608_p1;
reg [31:0] grp_fu_612_p0;
reg [31:0] grp_fu_612_p1;
reg [31:0] grp_fu_618_p0;
reg [31:0] grp_fu_618_p1;
reg [31:0] grp_fu_622_p0;
reg [31:0] grp_fu_622_p1;
reg [31:0] grp_fu_626_p0;
reg [31:0] grp_fu_626_p1;
reg [31:0] grp_fu_630_p0;
reg [31:0] grp_fu_630_p1;
reg [31:0] grp_fu_634_p0;
reg [31:0] grp_fu_634_p1;
reg [31:0] grp_fu_640_p0;
reg [31:0] grp_fu_640_p1;
reg [31:0] grp_fu_652_p0;
reg [31:0] grp_fu_652_p1;
reg [31:0] grp_fu_658_p0;
reg [31:0] grp_fu_658_p1;
reg [31:0] grp_fu_663_p0;
reg [31:0] grp_fu_663_p1;
reg [31:0] grp_fu_668_p0;
reg [31:0] grp_fu_668_p1;
reg [31:0] grp_fu_673_p0;
reg [31:0] grp_fu_673_p1;
reg [31:0] grp_fu_678_p0;
reg [31:0] grp_fu_678_p1;
reg [31:0] grp_fu_683_p0;
reg [31:0] grp_fu_683_p1;
reg [31:0] grp_fu_692_p0;
reg [31:0] grp_fu_692_p1;
reg [31:0] grp_fu_696_p0;
reg [31:0] grp_fu_696_p1;
reg [31:0] grp_fu_701_p0;
reg [31:0] grp_fu_701_p1;
reg [31:0] grp_fu_705_p0;
reg [31:0] grp_fu_705_p1;
reg [31:0] grp_fu_709_p0;
reg [31:0] grp_fu_709_p1;
reg [31:0] grp_fu_714_p0;
reg [31:0] grp_fu_714_p1;
reg [31:0] grp_fu_718_p0;
reg [31:0] grp_fu_718_p1;
reg [31:0] grp_fu_722_p0;
reg [31:0] grp_fu_722_p1;
reg [31:0] grp_fu_727_p0;
reg [31:0] grp_fu_727_p1;
reg [31:0] grp_fu_732_p0;
reg [31:0] grp_fu_732_p1;
reg [31:0] grp_fu_737_p0;
reg [31:0] grp_fu_737_p1;
reg [31:0] grp_fu_742_p0;
reg [31:0] grp_fu_742_p1;
reg [31:0] grp_fu_747_p0;
reg [31:0] grp_fu_747_p1;
reg [31:0] grp_fu_755_p0;
reg [31:0] grp_fu_755_p1;
reg [31:0] grp_fu_759_p0;
reg [31:0] grp_fu_759_p1;
reg [31:0] grp_fu_763_p0;
reg [31:0] grp_fu_763_p1;
reg [31:0] grp_fu_767_p0;
reg [31:0] grp_fu_767_p1;
reg [31:0] grp_fu_771_p0;
reg [31:0] grp_fu_771_p1;
wire [31:0] grp_fu_775_p0;
wire [31:0] grp_fu_775_p1;
wire [31:0] grp_fu_779_p0;
wire [31:0] grp_fu_779_p1;
wire [31:0] grp_fu_783_p0;
wire [31:0] grp_fu_783_p1;
wire [31:0] grp_fu_787_p0;
wire [31:0] grp_fu_787_p1;
wire [31:0] grp_fu_791_p0;
wire [31:0] grp_fu_791_p1;
wire [31:0] i_3_fu_1601_p1;
wire [31:0] i_fu_1618_p1;
wire [31:0] i_fu_1618_p2;
wire [31:0] i_2_fu_1629_p1;
wire [31:0] i_1_fu_1646_p1;
wire [31:0] i_1_fu_1646_p2;
reg [1:0] grp_fu_555_opcode;
wire grp_fu_555_ce;
reg [1:0] grp_fu_560_opcode;
wire grp_fu_560_ce;
reg [1:0] grp_fu_566_opcode;
wire grp_fu_566_ce;
reg [1:0] grp_fu_571_opcode;
wire grp_fu_571_ce;
reg [1:0] grp_fu_583_opcode;
wire grp_fu_583_ce;
reg [1:0] grp_fu_588_opcode;
wire grp_fu_588_ce;
wire grp_fu_592_ce;
wire grp_fu_596_ce;
wire grp_fu_600_ce;
wire grp_fu_604_ce;
wire grp_fu_608_ce;
wire grp_fu_612_ce;
wire grp_fu_618_ce;
wire grp_fu_622_ce;
wire grp_fu_626_ce;
wire grp_fu_630_ce;
wire grp_fu_634_ce;
wire grp_fu_640_ce;
wire grp_fu_652_ce;
wire grp_fu_658_ce;
wire grp_fu_663_ce;
wire grp_fu_668_ce;
wire grp_fu_673_ce;
wire grp_fu_678_ce;
wire grp_fu_683_ce;
wire grp_fu_692_ce;
wire grp_fu_696_ce;
wire grp_fu_701_ce;
wire grp_fu_705_ce;
wire grp_fu_709_ce;
wire grp_fu_714_ce;
wire grp_fu_718_ce;
wire grp_fu_722_ce;
wire grp_fu_727_ce;
wire grp_fu_732_ce;
wire grp_fu_737_ce;
wire grp_fu_742_ce;
wire grp_fu_747_ce;
wire grp_fu_755_ce;
wire grp_fu_759_ce;
wire grp_fu_763_ce;
wire grp_fu_767_ce;
wire grp_fu_771_ce;
wire grp_fu_775_ce;
wire grp_fu_779_ce;
wire grp_fu_783_ce;
wire grp_fu_787_ce;
wire grp_fu_791_ce;
reg [6:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 7'b0000000;
parameter ap_ST_st1_fsm_1 = 7'b0000001;
parameter ap_ST_st2_fsm_2 = 7'b0000010;
parameter ap_ST_st3_fsm_3 = 7'b0000011;
parameter ap_ST_st4_fsm_4 = 7'b0000100;
parameter ap_ST_st5_fsm_5 = 7'b0000101;
parameter ap_ST_st6_fsm_6 = 7'b0000110;
parameter ap_ST_st7_fsm_7 = 7'b0000111;
parameter ap_ST_st8_fsm_8 = 7'b0001000;
parameter ap_ST_st9_fsm_9 = 7'b0001001;
parameter ap_ST_st10_fsm_10 = 7'b0001010;
parameter ap_ST_st11_fsm_11 = 7'b0001011;
parameter ap_ST_st12_fsm_12 = 7'b0001100;
parameter ap_ST_st13_fsm_13 = 7'b0001101;
parameter ap_ST_st14_fsm_14 = 7'b0001110;
parameter ap_ST_st15_fsm_15 = 7'b0001111;
parameter ap_ST_st16_fsm_16 = 7'b0010000;
parameter ap_ST_st17_fsm_17 = 7'b0010001;
parameter ap_ST_st18_fsm_18 = 7'b0010010;
parameter ap_ST_st19_fsm_19 = 7'b0010011;
parameter ap_ST_st20_fsm_20 = 7'b0010100;
parameter ap_ST_st21_fsm_21 = 7'b0010101;
parameter ap_ST_st22_fsm_22 = 7'b0010110;
parameter ap_ST_st23_fsm_23 = 7'b0010111;
parameter ap_ST_st24_fsm_24 = 7'b0011000;
parameter ap_ST_st25_fsm_25 = 7'b0011001;
parameter ap_ST_st26_fsm_26 = 7'b0011010;
parameter ap_ST_st27_fsm_27 = 7'b0011011;
parameter ap_ST_st28_fsm_28 = 7'b0011100;
parameter ap_ST_st29_fsm_29 = 7'b0011101;
parameter ap_ST_st30_fsm_30 = 7'b0011110;
parameter ap_ST_st31_fsm_31 = 7'b0011111;
parameter ap_ST_st32_fsm_32 = 7'b0100000;
parameter ap_ST_st33_fsm_33 = 7'b0100001;
parameter ap_ST_st34_fsm_34 = 7'b0100010;
parameter ap_ST_st35_fsm_35 = 7'b0100011;
parameter ap_ST_st36_fsm_36 = 7'b0100100;
parameter ap_ST_st37_fsm_37 = 7'b0100101;
parameter ap_ST_st38_fsm_38 = 7'b0100110;
parameter ap_ST_st39_fsm_39 = 7'b0100111;
parameter ap_ST_st40_fsm_40 = 7'b0101000;
parameter ap_ST_st41_fsm_41 = 7'b0101001;
parameter ap_ST_st42_fsm_42 = 7'b0101010;
parameter ap_ST_st43_fsm_43 = 7'b0101011;
parameter ap_ST_st44_fsm_44 = 7'b0101100;
parameter ap_ST_st45_fsm_45 = 7'b0101101;
parameter ap_ST_st46_fsm_46 = 7'b0101110;
parameter ap_ST_st47_fsm_47 = 7'b0101111;
parameter ap_ST_st48_fsm_48 = 7'b0110000;
parameter ap_ST_st49_fsm_49 = 7'b0110001;
parameter ap_ST_st50_fsm_50 = 7'b0110010;
parameter ap_ST_st51_fsm_51 = 7'b0110011;
parameter ap_ST_st52_fsm_52 = 7'b0110100;
parameter ap_ST_st53_fsm_53 = 7'b0110101;
parameter ap_ST_st54_fsm_54 = 7'b0110110;
parameter ap_ST_st55_fsm_55 = 7'b0110111;
parameter ap_ST_st56_fsm_56 = 7'b0111000;
parameter ap_ST_st57_fsm_57 = 7'b0111001;
parameter ap_ST_st58_fsm_58 = 7'b0111010;
parameter ap_ST_st59_fsm_59 = 7'b0111011;
parameter ap_ST_st60_fsm_60 = 7'b0111100;
parameter ap_ST_st61_fsm_61 = 7'b0111101;
parameter ap_ST_st62_fsm_62 = 7'b0111110;
parameter ap_ST_st63_fsm_63 = 7'b0111111;
parameter ap_ST_st64_fsm_64 = 7'b1000000;
parameter ap_ST_st65_fsm_65 = 7'b1000001;
parameter ap_ST_st66_fsm_66 = 7'b1000010;
parameter ap_ST_st67_fsm_67 = 7'b1000011;
parameter ap_ST_st68_fsm_68 = 7'b1000100;
parameter ap_ST_st69_fsm_69 = 7'b1000101;
parameter ap_ST_st70_fsm_70 = 7'b1000110;
parameter ap_ST_st71_fsm_71 = 7'b1000111;
parameter ap_ST_st72_fsm_72 = 7'b1001000;
parameter ap_ST_st73_fsm_73 = 7'b1001001;
parameter ap_ST_st74_fsm_74 = 7'b1001010;
parameter ap_ST_st75_fsm_75 = 7'b1001011;
parameter ap_ST_st76_fsm_76 = 7'b1001100;
parameter ap_ST_st77_fsm_77 = 7'b1001101;
parameter ap_ST_st78_fsm_78 = 7'b1001110;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv64_1 = 64'b0000000000000000000000000000000000000000000000000000000000000001;
parameter ap_const_lv64_2 = 64'b0000000000000000000000000000000000000000000000000000000000000010;
parameter ap_const_lv64_3 = 64'b0000000000000000000000000000000000000000000000000000000000000011;
parameter ap_const_lv64_4 = 64'b0000000000000000000000000000000000000000000000000000000000000100;
parameter ap_const_lv64_5 = 64'b0000000000000000000000000000000000000000000000000000000000000101;
parameter ap_const_lv64_6 = 64'b0000000000000000000000000000000000000000000000000000000000000110;
parameter ap_const_lv64_7 = 64'b0000000000000000000000000000000000000000000000000000000000000111;
parameter ap_const_lv64_8 = 64'b0000000000000000000000000000000000000000000000000000000000001000;
parameter ap_const_lv64_9 = 64'b0000000000000000000000000000000000000000000000000000000000001001;
parameter ap_const_lv64_A = 64'b0000000000000000000000000000000000000000000000000000000000001010;
parameter ap_const_lv64_B = 64'b0000000000000000000000000000000000000000000000000000000000001011;
parameter ap_const_lv64_C = 64'b0000000000000000000000000000000000000000000000000000000000001100;
parameter ap_const_lv64_D = 64'b0000000000000000000000000000000000000000000000000000000000001101;
parameter ap_const_lv64_E = 64'b0000000000000000000000000000000000000000000000000000000000001110;
parameter ap_const_lv64_F = 64'b0000000000000000000000000000000000000000000000000000000000001111;
parameter ap_const_lv64_10 = 64'b0000000000000000000000000000000000000000000000000000000000010000;
parameter ap_const_lv64_11 = 64'b0000000000000000000000000000000000000000000000000000000000010001;
parameter ap_const_lv64_12 = 64'b0000000000000000000000000000000000000000000000000000000000010010;
parameter ap_const_lv64_13 = 64'b0000000000000000000000000000000000000000000000000000000000010011;
parameter ap_const_lv64_14 = 64'b0000000000000000000000000000000000000000000000000000000000010100;
parameter ap_const_lv64_15 = 64'b0000000000000000000000000000000000000000000000000000000000010101;
parameter ap_const_lv64_16 = 64'b0000000000000000000000000000000000000000000000000000000000010110;
parameter ap_const_lv64_17 = 64'b0000000000000000000000000000000000000000000000000000000000010111;
parameter ap_const_lv64_18 = 64'b0000000000000000000000000000000000000000000000000000000000011000;
parameter ap_const_lv64_19 = 64'b0000000000000000000000000000000000000000000000000000000000011001;
parameter ap_const_lv64_1A = 64'b0000000000000000000000000000000000000000000000000000000000011010;
parameter ap_const_lv64_1B = 64'b0000000000000000000000000000000000000000000000000000000000011011;
parameter ap_const_lv32_80000000 = 32'b10000000000000000000000000000000;
parameter ap_const_lv32_3FC00000 = 32'b00111111110000000000000000000000;
parameter ap_const_lv32_3F000000 = 32'b00111111000000000000000000000000;
parameter ap_const_lv32_40000000 = 32'b01000000000000000000000000000000;
parameter ap_const_lv32_C0000000 = 32'b11000000000000000000000000000000;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv32_1F = 32'b00000000000000000000000000011111;
parameter ap_const_lv32_5F3759D5 = 32'b01011111001101110101100111010101;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv2_1 = 2'b01;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_true = 1'b1;
jacobiansPoseComposition_grp_fu_555_ACMP_faddfsub_1 #(
.ID( 1 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_555_ACMP_faddfsub_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_555_p0 ),
.din1( grp_fu_555_p1 ),
.opcode( grp_fu_555_opcode ),
.ce( grp_fu_555_ce ),
.dout( grp_fu_555_p2 )
);
jacobiansPoseComposition_grp_fu_560_ACMP_faddfsub_2 #(
.ID( 2 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_560_ACMP_faddfsub_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_560_p0 ),
.din1( grp_fu_560_p1 ),
.opcode( grp_fu_560_opcode ),
.ce( grp_fu_560_ce ),
.dout( grp_fu_560_p2 )
);
jacobiansPoseComposition_grp_fu_566_ACMP_faddfsub_3 #(
.ID( 3 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_566_ACMP_faddfsub_3_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_566_p0 ),
.din1( grp_fu_566_p1 ),
.opcode( grp_fu_566_opcode ),
.ce( grp_fu_566_ce ),
.dout( grp_fu_566_p2 )
);
jacobiansPoseComposition_grp_fu_571_ACMP_faddfsub_4 #(
.ID( 4 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_571_ACMP_faddfsub_4_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_571_p0 ),
.din1( grp_fu_571_p1 ),
.opcode( grp_fu_571_opcode ),
.ce( grp_fu_571_ce ),
.dout( grp_fu_571_p2 )
);
jacobiansPoseComposition_grp_fu_583_ACMP_faddfsub_5 #(
.ID( 5 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_583_ACMP_faddfsub_5_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_583_p0 ),
.din1( grp_fu_583_p1 ),
.opcode( grp_fu_583_opcode ),
.ce( grp_fu_583_ce ),
.dout( grp_fu_583_p2 )
);
jacobiansPoseComposition_grp_fu_588_ACMP_faddfsub_6 #(
.ID( 6 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_588_ACMP_faddfsub_6_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_588_p0 ),
.din1( grp_fu_588_p1 ),
.opcode( grp_fu_588_opcode ),
.ce( grp_fu_588_ce ),
.dout( grp_fu_588_p2 )
);
jacobiansPoseComposition_grp_fu_592_ACMP_fadd_7 #(
.ID( 7 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_592_ACMP_fadd_7_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_592_p0 ),
.din1( grp_fu_592_p1 ),
.ce( grp_fu_592_ce ),
.dout( grp_fu_592_p2 )
);
jacobiansPoseComposition_grp_fu_596_ACMP_fadd_8 #(
.ID( 8 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_596_ACMP_fadd_8_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_596_p0 ),
.din1( grp_fu_596_p1 ),
.ce( grp_fu_596_ce ),
.dout( grp_fu_596_p2 )
);
jacobiansPoseComposition_grp_fu_600_ACMP_fadd_9 #(
.ID( 9 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_600_ACMP_fadd_9_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_600_p0 ),
.din1( grp_fu_600_p1 ),
.ce( grp_fu_600_ce ),
.dout( grp_fu_600_p2 )
);
jacobiansPoseComposition_grp_fu_604_ACMP_fadd_10 #(
.ID( 10 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_604_ACMP_fadd_10_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_604_p0 ),
.din1( grp_fu_604_p1 ),
.ce( grp_fu_604_ce ),
.dout( grp_fu_604_p2 )
);
jacobiansPoseComposition_grp_fu_608_ACMP_fadd_11 #(
.ID( 11 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_608_ACMP_fadd_11_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_608_p0 ),
.din1( grp_fu_608_p1 ),
.ce( grp_fu_608_ce ),
.dout( grp_fu_608_p2 )
);
jacobiansPoseComposition_grp_fu_612_ACMP_fadd_12 #(
.ID( 12 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_612_ACMP_fadd_12_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_612_p0 ),
.din1( grp_fu_612_p1 ),
.ce( grp_fu_612_ce ),
.dout( grp_fu_612_p2 )
);
jacobiansPoseComposition_grp_fu_618_ACMP_fadd_13 #(
.ID( 13 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_618_ACMP_fadd_13_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_618_p0 ),
.din1( grp_fu_618_p1 ),
.ce( grp_fu_618_ce ),
.dout( grp_fu_618_p2 )
);
jacobiansPoseComposition_grp_fu_622_ACMP_fadd_14 #(
.ID( 14 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_622_ACMP_fadd_14_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_622_p0 ),
.din1( grp_fu_622_p1 ),
.ce( grp_fu_622_ce ),
.dout( grp_fu_622_p2 )
);
jacobiansPoseComposition_grp_fu_626_ACMP_fadd_15 #(
.ID( 15 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_626_ACMP_fadd_15_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_626_p0 ),
.din1( grp_fu_626_p1 ),
.ce( grp_fu_626_ce ),
.dout( grp_fu_626_p2 )
);
jacobiansPoseComposition_grp_fu_630_ACMP_fadd_16 #(
.ID( 16 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_630_ACMP_fadd_16_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_630_p0 ),
.din1( grp_fu_630_p1 ),
.ce( grp_fu_630_ce ),
.dout( grp_fu_630_p2 )
);
jacobiansPoseComposition_grp_fu_634_ACMP_fmul_17 #(
.ID( 17 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_634_ACMP_fmul_17_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_634_p0 ),
.din1( grp_fu_634_p1 ),
.ce( grp_fu_634_ce ),
.dout( grp_fu_634_p2 )
);
jacobiansPoseComposition_grp_fu_640_ACMP_fmul_18 #(
.ID( 18 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_640_ACMP_fmul_18_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_640_p0 ),
.din1( grp_fu_640_p1 ),
.ce( grp_fu_640_ce ),
.dout( grp_fu_640_p2 )
);
jacobiansPoseComposition_grp_fu_652_ACMP_fmul_19 #(
.ID( 19 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_652_ACMP_fmul_19_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_652_p0 ),
.din1( grp_fu_652_p1 ),
.ce( grp_fu_652_ce ),
.dout( grp_fu_652_p2 )
);
jacobiansPoseComposition_grp_fu_658_ACMP_fmul_20 #(
.ID( 20 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_658_ACMP_fmul_20_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_658_p0 ),
.din1( grp_fu_658_p1 ),
.ce( grp_fu_658_ce ),
.dout( grp_fu_658_p2 )
);
jacobiansPoseComposition_grp_fu_663_ACMP_fmul_21 #(
.ID( 21 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_663_ACMP_fmul_21_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_663_p0 ),
.din1( grp_fu_663_p1 ),
.ce( grp_fu_663_ce ),
.dout( grp_fu_663_p2 )
);
jacobiansPoseComposition_grp_fu_668_ACMP_fmul_22 #(
.ID( 22 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_668_ACMP_fmul_22_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_668_p0 ),
.din1( grp_fu_668_p1 ),
.ce( grp_fu_668_ce ),
.dout( grp_fu_668_p2 )
);
jacobiansPoseComposition_grp_fu_673_ACMP_fmul_23 #(
.ID( 23 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_673_ACMP_fmul_23_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_673_p0 ),
.din1( grp_fu_673_p1 ),
.ce( grp_fu_673_ce ),
.dout( grp_fu_673_p2 )
);
jacobiansPoseComposition_grp_fu_678_ACMP_fmul_24 #(
.ID( 24 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_678_ACMP_fmul_24_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_678_p0 ),
.din1( grp_fu_678_p1 ),
.ce( grp_fu_678_ce ),
.dout( grp_fu_678_p2 )
);
jacobiansPoseComposition_grp_fu_683_ACMP_fmul_25 #(
.ID( 25 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_683_ACMP_fmul_25_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_683_p0 ),
.din1( grp_fu_683_p1 ),
.ce( grp_fu_683_ce ),
.dout( grp_fu_683_p2 )
);
jacobiansPoseComposition_grp_fu_692_ACMP_fmul_26 #(
.ID( 26 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_692_ACMP_fmul_26_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_692_p0 ),
.din1( grp_fu_692_p1 ),
.ce( grp_fu_692_ce ),
.dout( grp_fu_692_p2 )
);
jacobiansPoseComposition_grp_fu_696_ACMP_fmul_27 #(
.ID( 27 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_696_ACMP_fmul_27_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_696_p0 ),
.din1( grp_fu_696_p1 ),
.ce( grp_fu_696_ce ),
.dout( grp_fu_696_p2 )
);
jacobiansPoseComposition_grp_fu_701_ACMP_fmul_28 #(
.ID( 28 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_701_ACMP_fmul_28_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_701_p0 ),
.din1( grp_fu_701_p1 ),
.ce( grp_fu_701_ce ),
.dout( grp_fu_701_p2 )
);
jacobiansPoseComposition_grp_fu_705_ACMP_fmul_29 #(
.ID( 29 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_705_ACMP_fmul_29_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_705_p0 ),
.din1( grp_fu_705_p1 ),
.ce( grp_fu_705_ce ),
.dout( grp_fu_705_p2 )
);
jacobiansPoseComposition_grp_fu_709_ACMP_fmul_30 #(
.ID( 30 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_709_ACMP_fmul_30_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_709_p0 ),
.din1( grp_fu_709_p1 ),
.ce( grp_fu_709_ce ),
.dout( grp_fu_709_p2 )
);
jacobiansPoseComposition_grp_fu_714_ACMP_fmul_31 #(
.ID( 31 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_714_ACMP_fmul_31_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_714_p0 ),
.din1( grp_fu_714_p1 ),
.ce( grp_fu_714_ce ),
.dout( grp_fu_714_p2 )
);
jacobiansPoseComposition_grp_fu_718_ACMP_fmul_32 #(
.ID( 32 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_718_ACMP_fmul_32_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_718_p0 ),
.din1( grp_fu_718_p1 ),
.ce( grp_fu_718_ce ),
.dout( grp_fu_718_p2 )
);
jacobiansPoseComposition_grp_fu_722_ACMP_fmul_33 #(
.ID( 33 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_722_ACMP_fmul_33_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_722_p0 ),
.din1( grp_fu_722_p1 ),
.ce( grp_fu_722_ce ),
.dout( grp_fu_722_p2 )
);
jacobiansPoseComposition_grp_fu_727_ACMP_fmul_34 #(
.ID( 34 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_727_ACMP_fmul_34_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_727_p0 ),
.din1( grp_fu_727_p1 ),
.ce( grp_fu_727_ce ),
.dout( grp_fu_727_p2 )
);
jacobiansPoseComposition_grp_fu_732_ACMP_fmul_35 #(
.ID( 35 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_732_ACMP_fmul_35_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_732_p0 ),
.din1( grp_fu_732_p1 ),
.ce( grp_fu_732_ce ),
.dout( grp_fu_732_p2 )
);
jacobiansPoseComposition_grp_fu_737_ACMP_fmul_36 #(
.ID( 36 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_737_ACMP_fmul_36_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_737_p0 ),
.din1( grp_fu_737_p1 ),
.ce( grp_fu_737_ce ),
.dout( grp_fu_737_p2 )
);
jacobiansPoseComposition_grp_fu_742_ACMP_fmul_37 #(
.ID( 37 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_742_ACMP_fmul_37_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_742_p0 ),
.din1( grp_fu_742_p1 ),
.ce( grp_fu_742_ce ),
.dout( grp_fu_742_p2 )
);
jacobiansPoseComposition_grp_fu_747_ACMP_fmul_38 #(
.ID( 38 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_747_ACMP_fmul_38_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_747_p0 ),
.din1( grp_fu_747_p1 ),
.ce( grp_fu_747_ce ),
.dout( grp_fu_747_p2 )
);
jacobiansPoseComposition_grp_fu_755_ACMP_fmul_39 #(
.ID( 39 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_755_ACMP_fmul_39_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_755_p0 ),
.din1( grp_fu_755_p1 ),
.ce( grp_fu_755_ce ),
.dout( grp_fu_755_p2 )
);
jacobiansPoseComposition_grp_fu_759_ACMP_fmul_40 #(
.ID( 40 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_759_ACMP_fmul_40_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_759_p0 ),
.din1( grp_fu_759_p1 ),
.ce( grp_fu_759_ce ),
.dout( grp_fu_759_p2 )
);
jacobiansPoseComposition_grp_fu_763_ACMP_fmul_41 #(
.ID( 41 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_763_ACMP_fmul_41_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_763_p0 ),
.din1( grp_fu_763_p1 ),
.ce( grp_fu_763_ce ),
.dout( grp_fu_763_p2 )
);
jacobiansPoseComposition_grp_fu_767_ACMP_fmul_42 #(
.ID( 42 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_767_ACMP_fmul_42_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_767_p0 ),
.din1( grp_fu_767_p1 ),
.ce( grp_fu_767_ce ),
.dout( grp_fu_767_p2 )
);
jacobiansPoseComposition_grp_fu_771_ACMP_fmul_43 #(
.ID( 43 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_771_ACMP_fmul_43_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_771_p0 ),
.din1( grp_fu_771_p1 ),
.ce( grp_fu_771_ce ),
.dout( grp_fu_771_p2 )
);
jacobiansPoseComposition_grp_fu_775_ACMP_fmul_44 #(
.ID( 44 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_775_ACMP_fmul_44_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_775_p0 ),
.din1( grp_fu_775_p1 ),
.ce( grp_fu_775_ce ),
.dout( grp_fu_775_p2 )
);
jacobiansPoseComposition_grp_fu_779_ACMP_fmul_45 #(
.ID( 45 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_779_ACMP_fmul_45_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_779_p0 ),
.din1( grp_fu_779_p1 ),
.ce( grp_fu_779_ce ),
.dout( grp_fu_779_p2 )
);
jacobiansPoseComposition_grp_fu_783_ACMP_fmul_46 #(
.ID( 46 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_783_ACMP_fmul_46_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_783_p0 ),
.din1( grp_fu_783_p1 ),
.ce( grp_fu_783_ce ),
.dout( grp_fu_783_p2 )
);
jacobiansPoseComposition_grp_fu_787_ACMP_fmul_47 #(
.ID( 47 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_787_ACMP_fmul_47_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_787_p0 ),
.din1( grp_fu_787_p1 ),
.ce( grp_fu_787_ce ),
.dout( grp_fu_787_p2 )
);
jacobiansPoseComposition_grp_fu_791_ACMP_fmul_48 #(
.ID( 48 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
jacobiansPoseComposition_grp_fu_791_ACMP_fmul_48_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_791_p0 ),
.din1( grp_fu_791_p1 ),
.ce( grp_fu_791_ce ),
.dout( grp_fu_791_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st14_fsm_14 == ap_CS_fsm)) begin
X_plus_U_qz_reg_1782 <= grp_fu_555_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm))) begin
reg_1006 <= grp_fu_555_p2;
end
if (((ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm))) begin
reg_1013 <= grp_fu_571_p2;
end
if (((ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1019 <= grp_fu_652_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm))) begin
reg_1038 <= grp_fu_566_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1047 <= grp_fu_652_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1057 <= grp_fu_658_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1072 <= grp_fu_663_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1085 <= grp_fu_668_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1098 <= grp_fu_673_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1110 <= grp_fu_678_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1123 <= grp_fu_683_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm))) begin
reg_1136 <= grp_fu_560_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm))) begin
reg_1144 <= grp_fu_566_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm))) begin
reg_1152 <= grp_fu_571_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1157 <= grp_fu_583_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1167 <= grp_fu_663_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1178 <= grp_fu_588_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1186 <= grp_fu_592_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1194 <= grp_fu_596_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1201 <= grp_fu_692_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1212 <= grp_fu_600_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1220 <= grp_fu_696_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_1231 <= grp_fu_701_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1242 <= grp_fu_705_p2;
end
if (((ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1252 <= grp_fu_709_p2;
end
if (((ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1261 <= grp_fu_673_p2;
end
if (((ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1270 <= grp_fu_604_p2;
end
if (((ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1277 <= grp_fu_608_p2;
end
if (((ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_1284 <= grp_fu_612_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm))) begin
reg_1291 <= grp_fu_583_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1299 <= grp_fu_714_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1307 <= grp_fu_718_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1315 <= grp_fu_722_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1325 <= grp_fu_727_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1335 <= grp_fu_732_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1345 <= grp_fu_737_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1355 <= grp_fu_742_p2;
end
if (((ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1365 <= grp_fu_747_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm))) begin
reg_1375 <= grp_fu_658_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1383 <= grp_fu_668_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm))) begin
reg_1394 <= grp_fu_678_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1403 <= grp_fu_683_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1414 <= grp_fu_692_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1425 <= grp_fu_696_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm))) begin
reg_1435 <= grp_fu_701_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1444 <= grp_fu_705_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1454 <= grp_fu_696_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1460 <= grp_fu_701_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm))) begin
reg_1467 <= grp_fu_705_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm))) begin
reg_1473 <= grp_fu_709_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm))) begin
reg_1479 <= grp_fu_714_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1485 <= grp_fu_718_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1491 <= grp_fu_755_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1497 <= grp_fu_759_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1503 <= grp_fu_763_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1509 <= grp_fu_767_p2;
end
if (((ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1515 <= grp_fu_771_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
reg_1521 <= grp_fu_709_p2;
end
if (((ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1530 <= grp_fu_658_p2;
end
if (((ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1536 <= grp_fu_678_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1542 <= grp_fu_588_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1547 <= grp_fu_592_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1552 <= grp_fu_596_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1557 <= grp_fu_600_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1562 <= grp_fu_604_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1567 <= grp_fu_608_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1572 <= grp_fu_612_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1577 <= grp_fu_618_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1583 <= grp_fu_622_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1589 <= grp_fu_626_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_1595 <= grp_fu_630_p2;
end
if (((ap_ST_st4_fsm_4 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_795 <= grp_fu_634_p2;
end
if (((ap_ST_st4_fsm_4 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
reg_829 <= grp_fu_640_p2;
end
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm))) begin
reg_850 <= grp_fu_555_p2;
end
if (((ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
reg_869 <= grp_fu_560_p2;
end
if (((ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm))) begin
reg_889 <= grp_fu_555_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_903 <= grp_fu_634_p2;
end
if (((ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
reg_931 <= grp_fu_555_p2;
end
if (((ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
reg_943 <= grp_fu_640_p2;
end
if (((ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_954 <= grp_fu_560_p2;
end
if (((ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
reg_961 <= grp_fu_566_p2;
end
if (((ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm))) begin
reg_976 <= grp_fu_560_p2;
end
if (((ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st16_fsm_16 == ap_CS_fsm))) begin
reg_983 <= grp_fu_571_p2;
end
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm))) begin
reg_990 <= grp_fu_560_p2;
end
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm))) begin
reg_999 <= grp_fu_566_p2;
end
if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
tmp1_i1_reg_1804 <= i_fu_1618_p2;
end
if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
tmp1_i_reg_1838 <= i_1_fu_1646_p2;
end
if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
tmp_163_reg_1876 <= grp_fu_683_p2;
end
if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
tmp_169_reg_1881 <= grp_fu_692_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_239_reg_1902 <= grp_fu_652_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_253_reg_1907 <= grp_fu_673_p2;
end
if ((ap_ST_st46_fsm_46 == ap_CS_fsm)) begin
tmp_27_reg_1869 <= grp_fu_571_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_281_reg_1912 <= grp_fu_714_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_324_reg_1917 <= grp_fu_775_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_330_reg_1922 <= grp_fu_779_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_331_reg_1927 <= grp_fu_783_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_337_reg_1932 <= grp_fu_787_p2;
end
if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
tmp_338_reg_1937 <= grp_fu_791_p2;
end
if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
tmp_42_reg_1886 <= grp_fu_714_p2;
end
if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
tmp_43_reg_1894 <= grp_fu_718_p2;
end
if ((ap_ST_st12_fsm_12 == ap_CS_fsm)) begin
tmp_48_reg_1776 <= grp_fu_555_p2;
end
if ((ap_ST_st18_fsm_18 == ap_CS_fsm)) begin
tmp_4_reg_1793 <= grp_fu_555_p2;
end
if ((ap_ST_st31_fsm_31 == ap_CS_fsm)) begin
tmp_52_reg_1809 <= {{i_2_fu_1629_p1[ap_const_lv32_1F : ap_const_lv32_1]}};
end
if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
tmp_53_reg_1799 <= {{i_3_fu_1601_p1[ap_const_lv32_1F : ap_const_lv32_1]}};
end
if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
tmp_reg_1756 <= grp_fu_634_p2;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((ap_ST_st78_fsm_78 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_start))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st78_fsm_78;
end else if ((ap_ST_st76_fsm_76 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st77_fsm_77;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st76_fsm_76;
end else if ((ap_ST_st74_fsm_74 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st75_fsm_75;
end else if ((ap_ST_st73_fsm_73 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st74_fsm_74;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st73_fsm_73;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st72_fsm_72;
end else if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st71_fsm_71;
end else if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st70_fsm_70;
end else if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st69_fsm_69;
end else if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st68_fsm_68;
end else if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st67_fsm_67;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st66_fsm_66;
end else if ((ap_ST_st64_fsm_64 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st65_fsm_65;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st64_fsm_64;
end else if ((ap_ST_st62_fsm_62 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st63_fsm_63;
end else if ((ap_ST_st61_fsm_61 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st62_fsm_62;
end else if ((ap_ST_st60_fsm_60 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st61_fsm_61;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st60_fsm_60;
end else if ((ap_ST_st58_fsm_58 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st59_fsm_59;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st58_fsm_58;
end else if ((ap_ST_st56_fsm_56 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st57_fsm_57;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st56_fsm_56;
end else if ((ap_ST_st54_fsm_54 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st55_fsm_55;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st54_fsm_54;
end else if ((ap_ST_st52_fsm_52 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st53_fsm_53;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st52_fsm_52;
end else if ((ap_ST_st50_fsm_50 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st51_fsm_51;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st50_fsm_50;
end else if ((ap_ST_st48_fsm_48 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st49_fsm_49;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st48_fsm_48;
end else if ((ap_ST_st46_fsm_46 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st47_fsm_47;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st46_fsm_46;
end else if ((ap_ST_st44_fsm_44 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st45_fsm_45;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st44_fsm_44;
end else if ((ap_ST_st42_fsm_42 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st43_fsm_43;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st42_fsm_42;
end else if ((ap_ST_st40_fsm_40 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st41_fsm_41;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st40_fsm_40;
end else if ((ap_ST_st38_fsm_38 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st39_fsm_39;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st38_fsm_38;
end else if ((ap_ST_st36_fsm_36 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st37_fsm_37;
end else if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st36_fsm_36;
end else if ((ap_ST_st34_fsm_34 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st35_fsm_35;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st34_fsm_34;
end else if ((ap_ST_st32_fsm_32 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st33_fsm_33;
end else if ((ap_ST_st31_fsm_31 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st32_fsm_32;
end else if ((ap_ST_st30_fsm_30 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st31_fsm_31;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st30_fsm_30;
end else if ((ap_ST_st28_fsm_28 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st29_fsm_29;
end else if ((ap_ST_st27_fsm_27 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st28_fsm_28;
end else if ((ap_ST_st26_fsm_26 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st27_fsm_27;
end else if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st26_fsm_26;
end else if ((ap_ST_st24_fsm_24 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st25_fsm_25;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st24_fsm_24;
end else if ((ap_ST_st22_fsm_22 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st23_fsm_23;
end else if ((ap_ST_st21_fsm_21 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st22_fsm_22;
end else if ((ap_ST_st20_fsm_20 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st21_fsm_21;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st20_fsm_20;
end else if ((ap_ST_st18_fsm_18 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st19_fsm_19;
end else if ((ap_ST_st17_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st18_fsm_18;
end else if ((ap_ST_st16_fsm_16 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st17_fsm_17;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st16_fsm_16;
end else if ((ap_ST_st14_fsm_14 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st15_fsm_15;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st14_fsm_14;
end else if ((ap_ST_st12_fsm_12 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st13_fsm_13;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st12_fsm_12;
end else if ((ap_ST_st10_fsm_10 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st11_fsm_11;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st10_fsm_10;
end else if ((ap_ST_st8_fsm_8 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st9_fsm_9;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st8_fsm_8;
end else if ((ap_ST_st6_fsm_6 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st7_fsm_7;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st6_fsm_6;
end else if ((ap_ST_st4_fsm_4 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st5_fsm_5;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st4_fsm_4;
end else if ((ap_ST_st2_fsm_2 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st3_fsm_3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st2_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_ST_st78_fsm_78 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// df_dx_address0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_1A;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_18;
end else if ((ap_ST_st76_fsm_76 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_16;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_14;
end else if ((ap_ST_st74_fsm_74 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_12;
end else if ((ap_ST_st73_fsm_73 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_10;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_E;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_C;
end else if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_A;
end else if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_8;
end else if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_6;
end else if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_4;
end else if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_2;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
df_dx_address0 = ap_const_lv64_0;
end else begin
df_dx_address0 = ap_const_lv64_1A;
end
end
/// df_dx_address1 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_1B;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_19;
end else if ((ap_ST_st76_fsm_76 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_17;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_15;
end else if ((ap_ST_st74_fsm_74 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_13;
end else if ((ap_ST_st73_fsm_73 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_11;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_F;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_D;
end else if ((ap_ST_st70_fsm_70 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_B;
end else if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_9;
end else if ((ap_ST_st68_fsm_68 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_7;
end else if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_5;
end else if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_3;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
df_dx_address1 = ap_const_lv64_1;
end else begin
df_dx_address1 = ap_const_lv64_1B;
end
end
/// df_dx_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm))) begin
df_dx_ce0 = ap_const_logic_1;
end else begin
df_dx_ce0 = ap_const_logic_0;
end
end
/// df_dx_ce1 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm))) begin
df_dx_ce1 = ap_const_logic_1;
end else begin
df_dx_ce1 = ap_const_logic_0;
end
end
/// df_dx_d0 assign process. ///
always @ (ap_CS_fsm or reg_850 or reg_889 or reg_961 or reg_999 or reg_1157 or reg_1186 or reg_1212 or reg_1277 or reg_1577 or reg_1589)
begin
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
df_dx_d0 = reg_1589;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
df_dx_d0 = reg_1577;
end else if ((ap_ST_st72_fsm_72 == ap_CS_fsm)) begin
df_dx_d0 = reg_961;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
df_dx_d0 = reg_850;
end else if (((ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm))) begin
df_dx_d0 = reg_1277;
end else if (((ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm))) begin
df_dx_d0 = reg_1212;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm))) begin
df_dx_d0 = reg_1186;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm))) begin
df_dx_d0 = reg_1157;
end else if ((ap_ST_st66_fsm_66 == ap_CS_fsm)) begin
df_dx_d0 = reg_999;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
df_dx_d0 = reg_889;
end else begin
df_dx_d0 = reg_1589;
end
end
/// df_dx_d1 assign process. ///
always @ (ap_CS_fsm or reg_869 or reg_983 or reg_1178 or reg_1194 or reg_1270 or reg_1284 or reg_1583 or reg_1595)
begin
if ((ap_ST_st78_fsm_78 == ap_CS_fsm)) begin
df_dx_d1 = reg_1595;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
df_dx_d1 = reg_1583;
end else if (((ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm))) begin
df_dx_d1 = reg_1284;
end else if (((ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm))) begin
df_dx_d1 = reg_1270;
end else if (((ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm))) begin
df_dx_d1 = reg_1194;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm))) begin
df_dx_d1 = reg_1178;
end else if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm))) begin
df_dx_d1 = reg_983;
end else if (((ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm))) begin
df_dx_d1 = reg_869;
end else begin
df_dx_d1 = reg_1595;
end
end
/// df_dx_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm))) begin
df_dx_we0 = ap_const_logic_1;
end else begin
df_dx_we0 = ap_const_logic_0;
end
end
/// df_dx_we1 assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm))) begin
df_dx_we1 = ap_const_logic_1;
end else begin
df_dx_we1 = ap_const_logic_0;
end
end
/// grp_fu_555_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_555_opcode = ap_const_lv2_1;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) | (ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st7_fsm_7 == ap_CS_fsm) | (ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st11_fsm_11 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_555_opcode = ap_const_lv2_0;
end else begin
grp_fu_555_opcode = ap_const_lv2_1;
end
end
/// grp_fu_555_p0 assign process. ///
always @ (ap_CS_fsm or X_x or X_qr or X_qy or X_qz or reg_795 or reg_850 or reg_889 or reg_903 or reg_931 or reg_976 or reg_1038 or reg_1057 or tmp_48_reg_1776 or tmp_4_reg_1793)
begin
if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_850;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_931;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_903;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_1057;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_1038;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_555_p0 = ap_const_lv32_3FC00000;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_555_p0 = X_x;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_555_p0 = ap_const_lv32_80000000;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
grp_fu_555_p0 = tmp_4_reg_1793;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_555_p0 = reg_976;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
grp_fu_555_p0 = tmp_48_reg_1776;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
grp_fu_555_p0 = X_qz;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_555_p0 = reg_889;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
grp_fu_555_p0 = X_qy;
end else if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_555_p0 = reg_795;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
grp_fu_555_p0 = X_qr;
end else begin
grp_fu_555_p0 = ap_const_lv32_3FC00000;
end
end
/// grp_fu_555_p1 assign process. ///
always @ (ap_CS_fsm or X_qr or U_x or U_qr or U_qx or U_qy or U_qz or reg_795 or reg_829 or reg_903 or reg_943 or reg_1057 or reg_1072 or reg_1098)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_555_p1 = reg_943;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_555_p1 = reg_1057;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_555_p1 = reg_1072;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_555_p1 = U_qx;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_555_p1 = reg_1098;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_555_p1 = U_x;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_555_p1 = X_qr;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_555_p1 = reg_795;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
grp_fu_555_p1 = U_qz;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_555_p1 = reg_903;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
grp_fu_555_p1 = U_qy;
end else if (((ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_555_p1 = reg_829;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
grp_fu_555_p1 = U_qr;
end else begin
grp_fu_555_p1 = U_x;
end
end
/// grp_fu_560_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_560_opcode = ap_const_lv2_1;
end else if (((ap_ST_st3_fsm_3 == ap_CS_fsm) | (ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st11_fsm_11 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_560_opcode = ap_const_lv2_0;
end else begin
grp_fu_560_opcode = ap_const_lv2_1;
end
end
/// grp_fu_560_p0 assign process. ///
always @ (ap_CS_fsm or X_y or X_qx or reg_829 or reg_869 or reg_943 or reg_954 or reg_990 or reg_1019 or reg_1085 or reg_1277 or tmp_reg_1756 or tmp_239_reg_1902)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_560_p0 = reg_869;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_560_p0 = tmp_239_reg_1902;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_1085;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_1277;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_1019;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_560_p0 = X_y;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_560_p0 = ap_const_lv32_80000000;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_990;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_943;
end else if (((ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_560_p0 = reg_954;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
grp_fu_560_p0 = tmp_reg_1756;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
grp_fu_560_p0 = reg_829;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
grp_fu_560_p0 = X_qx;
end else begin
grp_fu_560_p0 = ap_const_lv32_80000000;
end
end
/// grp_fu_560_p1 assign process. ///
always @ (ap_CS_fsm or X_qy or U_y or U_qx or U_qy or reg_795 or reg_829 or reg_850 or reg_903 or reg_943 or reg_1057 or reg_1072 or reg_1098 or reg_1252 or reg_1530)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_560_p1 = reg_829;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_1530;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_1072;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_1098;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_560_p1 = U_qy;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_1252;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_850;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_560_p1 = reg_1057;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_560_p1 = U_y;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_560_p1 = X_qy;
end else if (((ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm))) begin
grp_fu_560_p1 = reg_795;
end else if (((ap_ST_st11_fsm_11 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_560_p1 = reg_943;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm))) begin
grp_fu_560_p1 = reg_903;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
grp_fu_560_p1 = U_qx;
end else begin
grp_fu_560_p1 = U_y;
end
end
/// grp_fu_566_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_566_opcode = ap_const_lv2_1;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_566_opcode = ap_const_lv2_0;
end else begin
grp_fu_566_opcode = ap_const_lv2_1;
end
end
/// grp_fu_566_p0 assign process. ///
always @ (ap_CS_fsm or X_z or reg_795 or reg_961 or reg_999 or reg_1110 or reg_1167 or tmp_reg_1756)
begin
if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_566_p0 = reg_1110;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm))) begin
grp_fu_566_p0 = reg_1167;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_566_p0 = X_z;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm))) begin
grp_fu_566_p0 = ap_const_lv32_80000000;
end else if (((ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_566_p0 = reg_999;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_566_p0 = tmp_reg_1756;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_566_p0 = reg_961;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
grp_fu_566_p0 = reg_795;
end else begin
grp_fu_566_p0 = ap_const_lv32_80000000;
end
end
/// grp_fu_566_p1 assign process. ///
always @ (ap_CS_fsm or X_qz or U_z or U_qz or reg_795 or reg_869 or reg_903 or reg_1019 or reg_1047 or reg_1085 or reg_1383 or tmp_163_reg_1876)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_566_p1 = reg_1047;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_566_p1 = reg_1019;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_566_p1 = reg_1383;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_566_p1 = tmp_163_reg_1876;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_566_p1 = U_qz;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_566_p1 = reg_869;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_566_p1 = reg_1085;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_566_p1 = U_z;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_566_p1 = X_qz;
end else if (((ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm))) begin
grp_fu_566_p1 = reg_795;
end else if (((ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st15_fsm_15 == ap_CS_fsm))) begin
grp_fu_566_p1 = reg_903;
end else begin
grp_fu_566_p1 = tmp_163_reg_1876;
end
end
/// grp_fu_571_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm))) begin
grp_fu_571_opcode = ap_const_lv2_1;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_571_opcode = ap_const_lv2_0;
end else begin
grp_fu_571_opcode = ap_const_lv2_1;
end
end
/// grp_fu_571_p0 assign process. ///
always @ (ap_CS_fsm or reg_889 or reg_976 or reg_983 or reg_1013 or reg_1178 or tmp_169_reg_1881 or tmp_253_reg_1907)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_571_p0 = reg_1013;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_571_p0 = tmp_253_reg_1907;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_571_p0 = reg_983;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_571_p0 = tmp_169_reg_1881;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_571_p0 = ap_const_lv32_80000000;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_571_p0 = reg_1178;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_571_p0 = ap_const_lv32_3FC00000;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
grp_fu_571_p0 = reg_976;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
grp_fu_571_p0 = reg_889;
end else begin
grp_fu_571_p0 = ap_const_lv32_3FC00000;
end
end
/// grp_fu_571_p1 assign process. ///
always @ (ap_CS_fsm or reg_795 or reg_931 or reg_1057 or reg_1098 or reg_1110 or reg_1454 or reg_1530 or reg_1536)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_1530;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_571_p1 = reg_1057;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_1536;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_1098;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_1454;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_931;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_571_p1 = reg_1110;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm))) begin
grp_fu_571_p1 = reg_795;
end else begin
grp_fu_571_p1 = reg_1536;
end
end
/// grp_fu_583_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm))) begin
grp_fu_583_opcode = ap_const_lv2_1;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_583_opcode = ap_const_lv2_0;
end else begin
grp_fu_583_opcode = ap_const_lv2_1;
end
end
/// grp_fu_583_p0 assign process. ///
always @ (ap_CS_fsm or reg_1072 or reg_1157 or reg_1291 or reg_1403 or reg_1460)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_583_p0 = reg_1291;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_583_p0 = reg_1403;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_583_p0 = reg_1157;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_583_p0 = reg_1460;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_583_p0 = reg_1072;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm))) begin
grp_fu_583_p0 = ap_const_lv32_80000000;
end else begin
grp_fu_583_p0 = ap_const_lv32_80000000;
end
end
/// grp_fu_583_p1 assign process. ///
always @ (ap_CS_fsm or X_qx or reg_1072 or reg_1110 or reg_1167 or reg_1414 or reg_1467 or X_plus_U_qz_reg_1782)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_583_p1 = reg_1167;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_583_p1 = reg_1072;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_583_p1 = reg_1414;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_583_p1 = reg_1467;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
grp_fu_583_p1 = X_plus_U_qz_reg_1782;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_583_p1 = reg_1110;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_583_p1 = X_qx;
end else begin
grp_fu_583_p1 = X_plus_U_qz_reg_1782;
end
end
/// grp_fu_588_opcode assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_588_opcode = ap_const_lv2_1;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_588_opcode = ap_const_lv2_0;
end else begin
grp_fu_588_opcode = ap_const_lv2_1;
end
end
/// grp_fu_588_p0 assign process. ///
always @ (ap_CS_fsm or reg_1047 or reg_1178 or reg_1186 or reg_1454 or reg_1473 or reg_1542)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_588_p0 = reg_1542;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_588_p0 = reg_1454;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_588_p0 = reg_1178;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_588_p0 = reg_1473;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_588_p0 = reg_1186;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_588_p0 = reg_1047;
end else begin
grp_fu_588_p0 = reg_1542;
end
end
/// grp_fu_588_p1 assign process. ///
always @ (ap_CS_fsm or reg_1057 or reg_1085 or reg_1098 or reg_1123 or reg_1383 or reg_1460 or reg_1479)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1383;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_588_p1 = reg_1085;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1460;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1123;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1479;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1098;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_588_p1 = reg_1057;
end else begin
grp_fu_588_p1 = reg_1479;
end
end
/// grp_fu_592_p0 assign process. ///
always @ (ap_CS_fsm or reg_1085 or reg_1123 or reg_1186 or reg_1444 or reg_1485 or reg_1547)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_592_p0 = reg_1547;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_592_p0 = reg_1444;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_592_p0 = reg_1186;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_592_p0 = reg_1485;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_592_p0 = reg_1123;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_592_p0 = reg_1085;
end else begin
grp_fu_592_p0 = reg_1547;
end
end
/// grp_fu_592_p1 assign process. ///
always @ (ap_CS_fsm or reg_1057 or reg_1098 or reg_1201 or reg_1261 or reg_1315 or reg_1521)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_592_p1 = reg_1261;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_592_p1 = reg_1521;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_592_p1 = reg_1201;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_592_p1 = reg_1315;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_592_p1 = reg_1057;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_592_p1 = reg_1098;
end else begin
grp_fu_592_p1 = reg_1521;
end
end
/// grp_fu_596_p0 assign process. ///
always @ (ap_CS_fsm or reg_1110 or reg_1194 or reg_1325 or reg_1552 or tmp_281_reg_1912)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_596_p0 = reg_1552;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_596_p0 = tmp_281_reg_1912;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_596_p0 = reg_1325;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_596_p0 = reg_1194;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_596_p0 = reg_1110;
end else begin
grp_fu_596_p0 = tmp_281_reg_1912;
end
end
/// grp_fu_596_p1 assign process. ///
always @ (ap_CS_fsm or reg_829 or reg_1110 or reg_1123 or reg_1220 or reg_1335 or reg_1485 or reg_1536)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_1536;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_596_p1 = reg_1110;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_1485;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_1220;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_1335;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_829;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_596_p1 = reg_1123;
end else begin
grp_fu_596_p1 = reg_1536;
end
end
/// grp_fu_600_p0 assign process. ///
always @ (ap_CS_fsm or reg_1072 or reg_1201 or reg_1212 or reg_1315 or reg_1345 or reg_1557)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_600_p0 = reg_1557;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_600_p0 = reg_1315;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_600_p0 = reg_1212;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_600_p0 = reg_1345;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_600_p0 = reg_1201;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_600_p0 = reg_1072;
end else begin
grp_fu_600_p0 = reg_1557;
end
end
/// grp_fu_600_p1 assign process. ///
always @ (ap_CS_fsm or reg_1057 or reg_1085 or reg_1123 or reg_1231 or reg_1325 or reg_1355 or reg_1403)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1403;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_600_p1 = reg_1123;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1325;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1231;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1355;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1085;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_600_p1 = reg_1057;
end else begin
grp_fu_600_p1 = reg_1403;
end
end
/// grp_fu_604_p0 assign process. ///
always @ (ap_CS_fsm or reg_1212 or reg_1270 or reg_1335 or reg_1365 or reg_1562)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_604_p0 = reg_1562;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_604_p0 = reg_1335;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_604_p0 = reg_1270;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_604_p0 = reg_1365;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_604_p0 = reg_1212;
end else begin
grp_fu_604_p0 = reg_1562;
end
end
/// grp_fu_604_p1 assign process. ///
always @ (ap_CS_fsm or reg_1201 or reg_1220 or reg_1345 or reg_1414 or reg_1467 or reg_1491)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_604_p1 = reg_1414;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_604_p1 = reg_1201;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_604_p1 = reg_1345;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_604_p1 = reg_1467;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_604_p1 = reg_1491;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_604_p1 = reg_1220;
end else begin
grp_fu_604_p1 = reg_1491;
end
end
/// grp_fu_608_p0 assign process. ///
always @ (ap_CS_fsm or reg_1231 or reg_1277 or reg_1355 or reg_1497 or reg_1567)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_608_p0 = reg_1567;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_608_p0 = reg_1355;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_608_p0 = reg_1277;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_608_p0 = reg_1497;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_608_p0 = reg_1231;
end else begin
grp_fu_608_p0 = reg_1567;
end
end
/// grp_fu_608_p1 assign process. ///
always @ (ap_CS_fsm or reg_1220 or reg_1242 or reg_1365 or reg_1425 or reg_1473 or reg_1503)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_608_p1 = reg_1425;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_608_p1 = reg_1220;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_608_p1 = reg_1365;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_608_p1 = reg_1473;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_608_p1 = reg_1503;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_608_p1 = reg_1242;
end else begin
grp_fu_608_p1 = reg_1503;
end
end
/// grp_fu_612_p0 assign process. ///
always @ (ap_CS_fsm or reg_1123 or reg_1284 or reg_1491 or reg_1509 or reg_1572)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_612_p0 = reg_1572;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_612_p0 = reg_1491;
end else if (((ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_612_p0 = reg_1284;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_612_p0 = reg_1509;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_612_p0 = reg_1123;
end else begin
grp_fu_612_p0 = reg_1572;
end
end
/// grp_fu_612_p1 assign process. ///
always @ (ap_CS_fsm or reg_1019 or reg_1231 or reg_1460 or reg_1479 or reg_1497 or reg_1515)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_612_p1 = reg_1460;
end else if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm))) begin
grp_fu_612_p1 = reg_1231;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_612_p1 = reg_1497;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_612_p1 = reg_1479;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_612_p1 = reg_1515;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_612_p1 = reg_1019;
end else begin
grp_fu_612_p1 = reg_1515;
end
end
/// grp_fu_618_p0 assign process. ///
always @ (ap_CS_fsm or reg_1503 or reg_1577)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_618_p0 = reg_1577;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_618_p0 = reg_1503;
end else begin
grp_fu_618_p0 = reg_1577;
end
end
/// grp_fu_618_p1 assign process. ///
always @ (ap_CS_fsm or reg_1242 or reg_1509)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_618_p1 = reg_1242;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_618_p1 = reg_1509;
end else begin
grp_fu_618_p1 = reg_1509;
end
end
/// grp_fu_622_p0 assign process. ///
always @ (ap_CS_fsm or reg_1515 or reg_1583)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_622_p0 = reg_1583;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_622_p0 = reg_1515;
end else begin
grp_fu_622_p0 = reg_1583;
end
end
/// grp_fu_622_p1 assign process. ///
always @ (ap_CS_fsm or reg_1252 or tmp_324_reg_1917)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_622_p1 = reg_1252;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_622_p1 = tmp_324_reg_1917;
end else begin
grp_fu_622_p1 = tmp_324_reg_1917;
end
end
/// grp_fu_626_p0 assign process. ///
always @ (ap_CS_fsm or reg_1589 or tmp_330_reg_1922)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_626_p0 = reg_1589;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_626_p0 = tmp_330_reg_1922;
end else begin
grp_fu_626_p0 = tmp_330_reg_1922;
end
end
/// grp_fu_626_p1 assign process. ///
always @ (ap_CS_fsm or reg_1299 or tmp_331_reg_1927)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_626_p1 = reg_1299;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_626_p1 = tmp_331_reg_1927;
end else begin
grp_fu_626_p1 = tmp_331_reg_1927;
end
end
/// grp_fu_630_p0 assign process. ///
always @ (ap_CS_fsm or reg_1595 or tmp_337_reg_1932)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_630_p0 = reg_1595;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_630_p0 = tmp_337_reg_1932;
end else begin
grp_fu_630_p0 = tmp_337_reg_1932;
end
end
/// grp_fu_630_p1 assign process. ///
always @ (ap_CS_fsm or reg_1307 or tmp_338_reg_1937)
begin
if (((ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_630_p1 = reg_1307;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_630_p1 = tmp_338_reg_1937;
end else begin
grp_fu_630_p1 = tmp_338_reg_1937;
end
end
/// grp_fu_634_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qy or X_qz or U_y or reg_795 or reg_850 or reg_889 or reg_903 or reg_931 or reg_954 or reg_976 or reg_1006 or reg_1047 or reg_1152 or reg_1375 or X_plus_U_qz_reg_1782)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_1375;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_1047;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_976;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_954;
end else if (((ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm))) begin
grp_fu_634_p0 = reg_1152;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_634_p0 = U_y;
end else if (((ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_634_p0 = reg_795;
end else if (((ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st23_fsm_23 == ap_CS_fsm))) begin
grp_fu_634_p0 = reg_1006;
end else if (((ap_ST_st31_fsm_31 == ap_CS_fsm) | (ap_ST_st35_fsm_35 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_634_p0 = reg_903;
end else if (((ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_634_p0 = reg_889;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_634_p0 = X_plus_U_qz_reg_1782;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_931;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
grp_fu_634_p0 = X_qz;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
grp_fu_634_p0 = reg_850;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
grp_fu_634_p0 = X_qy;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
grp_fu_634_p0 = X_qr;
end else begin
grp_fu_634_p0 = U_y;
end
end
/// grp_fu_634_p1 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qy or X_qz or U_qr or U_qy or U_qz or reg_795 or reg_850 or reg_889 or reg_903 or reg_931 or reg_1006 or reg_1038 or reg_1242 or X_plus_U_qz_reg_1782 or tmp1_i1_fu_1624_p1 or tmp1_i1_reg_1804 or tmp1_i_fu_1652_p1 or tmp1_i_reg_1838)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_634_p1 = U_qz;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_634_p1 = U_qy;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_1242;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_634_p1 = U_qr;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_903;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_634_p1 = ap_const_lv32_40000000;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_795;
end else if (((ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm))) begin
grp_fu_634_p1 = tmp1_i_reg_1838;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_1038;
end else if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
grp_fu_634_p1 = tmp1_i_fu_1652_p1;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_634_p1 = tmp1_i1_reg_1804;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
grp_fu_634_p1 = tmp1_i1_fu_1624_p1;
end else if (((ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st31_fsm_31 == ap_CS_fsm))) begin
grp_fu_634_p1 = ap_const_lv32_3F000000;
end else if (((ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm))) begin
grp_fu_634_p1 = reg_1006;
end else if (((ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm))) begin
grp_fu_634_p1 = reg_889;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
grp_fu_634_p1 = X_plus_U_qz_reg_1782;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_931;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
grp_fu_634_p1 = X_qz;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
grp_fu_634_p1 = reg_850;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
grp_fu_634_p1 = X_qy;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
grp_fu_634_p1 = X_qr;
end else begin
grp_fu_634_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_640_p0 assign process. ///
always @ (ap_CS_fsm or X_qx or X_qy or X_qz or reg_795 or reg_829 or reg_869 or reg_943 or reg_1047 or reg_1186 or reg_1194 or reg_1375)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_1375;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_1047;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_795;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_1194;
end else if (((ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_640_p0 = reg_943;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_1186;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_640_p0 = reg_829;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm))) begin
grp_fu_640_p0 = X_qy;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
grp_fu_640_p0 = X_qz;
end else if (((ap_ST_st7_fsm_7 == ap_CS_fsm) | (ap_ST_st47_fsm_47 == ap_CS_fsm))) begin
grp_fu_640_p0 = reg_869;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_640_p0 = X_qx;
end else begin
grp_fu_640_p0 = X_qz;
end
end
/// grp_fu_640_p1 assign process. ///
always @ (ap_CS_fsm or X_qx or U_z or U_qx or U_qy or reg_795 or reg_869 or reg_889 or reg_903 or reg_961 or reg_1136 or reg_1252)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_640_p1 = U_qy;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_961;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_1252;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_640_p1 = U_qx;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_903;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_640_p1 = ap_const_lv32_40000000;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_1136;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_889;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_640_p1 = U_z;
end else if (((ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm))) begin
grp_fu_640_p1 = ap_const_lv32_C0000000;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
grp_fu_640_p1 = reg_869;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
grp_fu_640_p1 = X_qx;
end else begin
grp_fu_640_p1 = ap_const_lv32_C0000000;
end
end
/// grp_fu_652_p0 assign process. ///
always @ (ap_CS_fsm or X_qx or X_qy or reg_795 or reg_829 or reg_903 or reg_931 or reg_954 or reg_1019 or reg_1047 or reg_1284 or reg_1375)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_1375;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_795;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_903;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_1284;
end else if (((ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm))) begin
grp_fu_652_p0 = reg_1047;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_954;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_931;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_1019;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_652_p0 = X_qy;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_652_p0 = reg_829;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
grp_fu_652_p0 = X_qx;
end else begin
grp_fu_652_p0 = X_qy;
end
end
/// grp_fu_652_p1 assign process. ///
always @ (ap_CS_fsm or U_x or U_y or U_qr or reg_795 or reg_850 or reg_889 or reg_903 or reg_1136 or reg_1299)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_652_p1 = U_qr;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_652_p1 = reg_1299;
end else if (((ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_652_p1 = reg_850;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_652_p1 = reg_903;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_652_p1 = ap_const_lv32_40000000;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_652_p1 = reg_1136;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_652_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_652_p1 = reg_889;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_652_p1 = U_y;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_652_p1 = U_x;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
grp_fu_652_p1 = ap_const_lv32_C0000000;
end else begin
grp_fu_652_p1 = ap_const_lv32_C0000000;
end
end
/// grp_fu_658_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qz or reg_795 or reg_943 or reg_1047 or reg_1057 or reg_1315 or reg_1375 or X_plus_U_qz_reg_1782)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_658_p0 = reg_1047;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_658_p0 = reg_943;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_658_p0 = reg_795;
end else if (((ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm))) begin
grp_fu_658_p0 = reg_1375;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_658_p0 = reg_1315;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_658_p0 = X_plus_U_qz_reg_1782;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_658_p0 = reg_1057;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_658_p0 = X_qz;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_658_p0 = X_qr;
end else begin
grp_fu_658_p0 = X_plus_U_qz_reg_1782;
end
end
/// grp_fu_658_p1 assign process. ///
always @ (ap_CS_fsm or U_y or U_z or U_qr or U_qx or reg_795 or reg_889 or reg_903 or reg_1123 or reg_1136 or reg_1307)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_658_p1 = U_qx;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_658_p1 = reg_1307;
end else if (((ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_658_p1 = U_qr;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_658_p1 = reg_1123;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_658_p1 = reg_903;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_658_p1 = reg_1136;
end else if (((ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_658_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_658_p1 = reg_889;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_658_p1 = U_z;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_658_p1 = U_y;
end else begin
grp_fu_658_p1 = U_z;
end
end
/// grp_fu_663_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qz or reg_795 or reg_829 or reg_850 or reg_903 or reg_1072 or reg_1167 or reg_1261 or reg_1325 or reg_1394)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_1394;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_1261;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_903;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_795;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_1167;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_1325;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_850;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_663_p0 = reg_1072;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_663_p0 = X_qr;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_663_p0 = reg_829;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_663_p0 = X_qz;
end else begin
grp_fu_663_p0 = X_qz;
end
end
/// grp_fu_663_p1 assign process. ///
always @ (ap_CS_fsm or U_x or U_qy or U_qz or reg_795 or reg_869 or reg_903 or reg_1072 or reg_1144 or reg_1157 or reg_1201 or reg_1242)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_663_p1 = U_qz;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_663_p1 = U_qy;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_1242;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_869;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_1201;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_1072;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_1144;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_663_p1 = reg_1157;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm))) begin
grp_fu_663_p1 = U_x;
end else begin
grp_fu_663_p1 = U_x;
end
end
/// grp_fu_668_p0 assign process. ///
always @ (ap_CS_fsm or X_qx or X_qy or reg_795 or reg_829 or reg_931 or reg_943 or reg_961 or reg_999 or reg_1261 or reg_1315 or reg_1394)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_1394;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_1261;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_829;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_943;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_795;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_999;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_1315;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_931;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_668_p0 = reg_961;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_668_p0 = X_qx;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_668_p0 = X_qy;
end else begin
grp_fu_668_p0 = X_qy;
end
end
/// grp_fu_668_p1 assign process. ///
always @ (ap_CS_fsm or U_x or U_y or U_qy or U_qz or reg_795 or reg_829 or reg_903 or reg_961 or reg_1144 or reg_1157 or reg_1220 or reg_1252)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_668_p1 = U_qy;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_961;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_1252;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_668_p1 = U_qz;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_1220;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_829;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_1144;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_668_p1 = reg_1157;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_668_p1 = U_y;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_668_p1 = U_x;
end else begin
grp_fu_668_p1 = U_x;
end
end
/// grp_fu_673_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qz or reg_795 or reg_829 or reg_903 or reg_1019 or reg_1085 or reg_1261 or reg_1325 or reg_1383 or reg_1394 or X_plus_U_qz_reg_1782)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1394;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1261;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_829;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_903;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_795;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1383;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1325;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_673_p0 = X_plus_U_qz_reg_1782;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1085;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_673_p0 = X_qz;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_673_p0 = X_qr;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_673_p0 = reg_1019;
end else begin
grp_fu_673_p0 = X_plus_U_qz_reg_1782;
end
end
/// grp_fu_673_p1 assign process. ///
always @ (ap_CS_fsm or U_y or U_z or U_qr or reg_795 or reg_850 or reg_903 or reg_961 or reg_1085 or reg_1144 or reg_1157 or reg_1231 or reg_1299)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_850;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_673_p1 = U_qr;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_1299;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_961;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_1231;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_1085;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_1144;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_673_p1 = reg_1157;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_673_p1 = U_z;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_673_p1 = U_y;
end else begin
grp_fu_673_p1 = U_z;
end
end
/// grp_fu_678_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or X_qx or reg_829 or reg_850 or reg_943 or reg_1261 or reg_1315 or reg_1394)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_678_p0 = reg_1394;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_678_p0 = reg_943;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_678_p0 = reg_829;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_678_p0 = reg_1315;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_678_p0 = reg_850;
end else if (((ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm))) begin
grp_fu_678_p0 = reg_1261;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_678_p0 = X_qx;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_678_p0 = X_qr;
end else begin
grp_fu_678_p0 = X_qr;
end
end
/// grp_fu_678_p1 assign process. ///
always @ (ap_CS_fsm or U_x or U_z or U_qr or U_qx or reg_795 or reg_869 or reg_903 or reg_990 or reg_1019 or reg_1123 or reg_1307 or tmp_27_reg_1869)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_678_p1 = U_qr;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_678_p1 = U_qx;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_1307;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_869;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_1123;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_1019;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_678_p1 = tmp_27_reg_1869;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_678_p1 = reg_990;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_678_p1 = U_z;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_678_p1 = U_x;
end else begin
grp_fu_678_p1 = tmp_27_reg_1869;
end
end
/// grp_fu_683_p0 assign process. ///
always @ (ap_CS_fsm or X_qx or reg_829 or reg_869 or reg_1019 or reg_1110 or reg_1167 or reg_1325 or reg_1394 or reg_1425 or reg_1435)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1435;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1425;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1019;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1167;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1394;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1325;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_869;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_683_p0 = reg_1110;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_683_p0 = X_qx;
end else if (((ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm))) begin
grp_fu_683_p0 = reg_829;
end else begin
grp_fu_683_p0 = X_qx;
end
end
/// grp_fu_683_p1 assign process. ///
always @ (ap_CS_fsm or U_x or U_y or U_qr or U_qy or U_qz or reg_795 or reg_903 or reg_990 or reg_1098 or reg_1201 or reg_1242 or tmp_27_reg_1869)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_683_p1 = U_qz;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_683_p1 = U_qy;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_1242;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_683_p1 = U_qr;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_1201;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_1098;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_683_p1 = tmp_27_reg_1869;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_683_p1 = reg_990;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_683_p1 = U_x;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
grp_fu_683_p1 = U_y;
end else begin
grp_fu_683_p1 = tmp_27_reg_1869;
end
end
/// grp_fu_692_p0 assign process. ///
always @ (ap_CS_fsm or X_qz or U_x or reg_829 or reg_1019 or reg_1123 or reg_1315 or reg_1383 or reg_1403 or reg_1425 or reg_1435 or X_plus_U_qz_reg_1782)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1435;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1425;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1019;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1383;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_829;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1403;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1315;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_692_p0 = X_plus_U_qz_reg_1782;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_692_p0 = reg_1123;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_692_p0 = X_qz;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_692_p0 = U_x;
end else begin
grp_fu_692_p0 = U_x;
end
end
/// grp_fu_692_p1 assign process. ///
always @ (ap_CS_fsm or U_qx or U_qy or reg_795 or reg_903 or reg_961 or reg_990 or reg_1057 or reg_1220 or reg_1252 or tmp_27_reg_1869)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_692_p1 = U_qy;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_961;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_1252;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_692_p1 = U_qx;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_1220;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_1057;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_692_p1 = tmp_27_reg_1869;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_692_p1 = reg_795;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm))) begin
grp_fu_692_p1 = reg_990;
end else begin
grp_fu_692_p1 = tmp_27_reg_1869;
end
end
/// grp_fu_696_p0 assign process. ///
always @ (ap_CS_fsm or X_qr or reg_829 or reg_850 or reg_983 or reg_1013 or reg_1019 or reg_1167 or reg_1325 or reg_1425 or reg_1435)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_1435;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_1425;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_1167;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_829;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_1013;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_1325;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_850;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_696_p0 = reg_983;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_696_p0 = X_qr;
end else if (((ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_696_p0 = reg_1019;
end else begin
grp_fu_696_p0 = X_qr;
end
end
/// grp_fu_696_p1 assign process. ///
always @ (ap_CS_fsm or U_z or U_qr or reg_795 or reg_850 or reg_903 or reg_1038 or reg_1110 or reg_1231 or reg_1291 or reg_1299)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_696_p1 = U_qr;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_1299;
end else if (((ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_696_p1 = reg_850;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_1231;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_1110;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_1291;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_696_p1 = reg_1038;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_696_p1 = U_z;
end else begin
grp_fu_696_p1 = U_z;
end
end
/// grp_fu_701_p0 assign process. ///
always @ (ap_CS_fsm or X_qx or U_x or reg_869 or reg_1019 or reg_1201 or reg_1335 or reg_1383 or reg_1414 or reg_1425 or reg_1435)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1435;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1425;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1383;
end else if (((ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm))) begin
grp_fu_701_p0 = reg_1019;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1414;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1335;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_869;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_701_p0 = reg_1201;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_701_p0 = X_qx;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_701_p0 = U_x;
end else begin
grp_fu_701_p0 = U_x;
end
end
/// grp_fu_701_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or U_qx or reg_795 or reg_889 or reg_903 or reg_1038 or reg_1123 or reg_1291 or reg_1307)
begin
if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_701_p1 = U_qx;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_1307;
end else if (((ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm))) begin
grp_fu_701_p1 = U_qr;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_1123;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_903;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_1291;
end else if (((ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm))) begin
grp_fu_701_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_1038;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_701_p1 = reg_889;
end else begin
grp_fu_701_p1 = U_qr;
end
end
/// grp_fu_705_p0 assign process. ///
always @ (ap_CS_fsm or X_qy or X_qz or reg_931 or reg_1019 or reg_1167 or reg_1220 or reg_1345 or reg_1425 or tmp_42_reg_1886 or tmp_43_reg_1894)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_705_p0 = tmp_43_reg_1894;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_705_p0 = tmp_42_reg_1886;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_1167;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_1019;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_1425;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_1345;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_931;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_705_p0 = reg_1220;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_705_p0 = X_qy;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_705_p0 = X_qz;
end else begin
grp_fu_705_p0 = tmp_43_reg_1894;
end
end
/// grp_fu_705_p1 assign process. ///
always @ (ap_CS_fsm or U_y or U_qy or U_qz or reg_795 or reg_869 or reg_903 or reg_1038 or reg_1072 or reg_1201 or reg_1291)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_705_p1 = U_qz;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_705_p1 = U_qy;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_869;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_1201;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_1072;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_1291;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_795;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
grp_fu_705_p1 = reg_1038;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_705_p1 = U_y;
end else begin
grp_fu_705_p1 = U_y;
end
end
/// grp_fu_709_p0 assign process. ///
always @ (ap_CS_fsm or reg_829 or reg_1019 or reg_1231 or reg_1335 or reg_1383 or reg_1435 or tmp_42_reg_1886 or tmp_43_reg_1894)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_709_p0 = tmp_43_reg_1894;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_709_p0 = tmp_42_reg_1886;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_1383;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_1019;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_1435;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_1335;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_1231;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_709_p0 = reg_829;
end else begin
grp_fu_709_p0 = tmp_43_reg_1894;
end
end
/// grp_fu_709_p1 assign process. ///
always @ (ap_CS_fsm or U_z or U_qy or U_qz or reg_795 or reg_829 or reg_903 or reg_961 or reg_1220)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_709_p1 = U_qy;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_709_p1 = reg_961;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_709_p1 = U_qz;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_709_p1 = reg_1220;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_709_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_709_p1 = reg_829;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_709_p1 = reg_795;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
grp_fu_709_p1 = U_z;
end else begin
grp_fu_709_p1 = U_z;
end
end
/// grp_fu_714_p0 assign process. ///
always @ (ap_CS_fsm or reg_1019 or reg_1167 or reg_1242 or reg_1345 or reg_1444 or tmp_42_reg_1886 or tmp_43_reg_1894)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_714_p0 = tmp_43_reg_1894;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_714_p0 = tmp_42_reg_1886;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_714_p0 = reg_1167;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_714_p0 = reg_1019;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_714_p0 = reg_1444;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_714_p0 = reg_1345;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_714_p0 = reg_1242;
end else begin
grp_fu_714_p0 = tmp_43_reg_1894;
end
end
/// grp_fu_714_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or reg_795 or reg_850 or reg_903 or reg_961 or reg_1085 or reg_1231)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_850;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_714_p1 = U_qr;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_961;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_1231;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_1085;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_714_p1 = reg_795;
end else begin
grp_fu_714_p1 = U_qr;
end
end
/// grp_fu_718_p0 assign process. ///
always @ (ap_CS_fsm or reg_1335 or reg_1383 or tmp_48_reg_1776 or tmp_4_reg_1793 or tmp_42_reg_1886 or tmp_43_reg_1894)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_718_p0 = tmp_43_reg_1894;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_718_p0 = tmp_42_reg_1886;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_718_p0 = reg_1383;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_718_p0 = tmp_4_reg_1793;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_718_p0 = reg_1335;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_718_p0 = tmp_48_reg_1776;
end else begin
grp_fu_718_p0 = tmp_43_reg_1894;
end
end
/// grp_fu_718_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or U_qx or reg_795 or reg_869 or reg_903 or reg_1019)
begin
if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
grp_fu_718_p1 = U_qr;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
grp_fu_718_p1 = U_qx;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_718_p1 = reg_869;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
grp_fu_718_p1 = reg_903;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_718_p1 = reg_1019;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_718_p1 = reg_795;
end else begin
grp_fu_718_p1 = U_qr;
end
end
/// grp_fu_722_p0 assign process. ///
always @ (ap_CS_fsm or reg_889 or reg_1345 or reg_1403)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_722_p0 = reg_1403;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_722_p0 = reg_1345;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_722_p0 = reg_889;
end else begin
grp_fu_722_p0 = reg_1403;
end
end
/// grp_fu_722_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or reg_1098)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_722_p1 = U_qr;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_722_p1 = reg_1098;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_722_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_722_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_727_p0 assign process. ///
always @ (ap_CS_fsm or reg_990 or reg_1335 or reg_1414)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_727_p0 = reg_1414;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_727_p0 = reg_1335;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_727_p0 = reg_990;
end else begin
grp_fu_727_p0 = reg_1414;
end
end
/// grp_fu_727_p1 assign process. ///
always @ (ap_CS_fsm or U_qx or reg_1057)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_727_p1 = U_qx;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_727_p1 = reg_1057;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_727_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_727_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_732_p0 assign process. ///
always @ (ap_CS_fsm or reg_1157 or reg_1345 or reg_1403)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_732_p0 = reg_1403;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_732_p0 = reg_1345;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_732_p0 = reg_1157;
end else begin
grp_fu_732_p0 = reg_1403;
end
end
/// grp_fu_732_p1 assign process. ///
always @ (ap_CS_fsm or reg_850 or reg_1110)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_732_p1 = reg_850;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_732_p1 = reg_1110;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_732_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_732_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_737_p0 assign process. ///
always @ (ap_CS_fsm or reg_1178 or reg_1355 or reg_1414)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_737_p0 = reg_1414;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_737_p0 = reg_1355;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_737_p0 = reg_1178;
end else begin
grp_fu_737_p0 = reg_1414;
end
end
/// grp_fu_737_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or reg_795)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_737_p1 = U_qr;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_737_p1 = reg_795;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_737_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_737_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_742_p0 assign process. ///
always @ (ap_CS_fsm or reg_1212 or reg_1365 or reg_1403)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_742_p0 = reg_1403;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_742_p0 = reg_1365;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_742_p0 = reg_1212;
end else begin
grp_fu_742_p0 = reg_1403;
end
end
/// grp_fu_742_p1 assign process. ///
always @ (ap_CS_fsm or reg_869 or reg_1072)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_742_p1 = reg_869;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_742_p1 = reg_1072;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_742_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_742_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_747_p0 assign process. ///
always @ (ap_CS_fsm or reg_1270 or reg_1355 or reg_1414)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_747_p0 = reg_1414;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_747_p0 = reg_1355;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_747_p0 = reg_1270;
end else begin
grp_fu_747_p0 = reg_1414;
end
end
/// grp_fu_747_p1 assign process. ///
always @ (ap_CS_fsm or U_qz or reg_829)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_747_p1 = U_qz;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_747_p1 = reg_829;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
grp_fu_747_p1 = ap_const_lv32_40000000;
end else begin
grp_fu_747_p1 = ap_const_lv32_40000000;
end
end
/// grp_fu_755_p0 assign process. ///
always @ (ap_CS_fsm or reg_1365 or reg_1403)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_755_p0 = reg_1403;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_755_p0 = reg_1365;
end else begin
grp_fu_755_p0 = reg_1403;
end
end
/// grp_fu_755_p1 assign process. ///
always @ (ap_CS_fsm or reg_961 or reg_1085)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_755_p1 = reg_961;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_755_p1 = reg_1085;
end else begin
grp_fu_755_p1 = reg_1085;
end
end
/// grp_fu_759_p0 assign process. ///
always @ (ap_CS_fsm or reg_1355 or reg_1414)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_759_p0 = reg_1414;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_759_p0 = reg_1355;
end else begin
grp_fu_759_p0 = reg_1414;
end
end
/// grp_fu_759_p1 assign process. ///
always @ (ap_CS_fsm or reg_869 or reg_1019)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_759_p1 = reg_869;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_759_p1 = reg_1019;
end else begin
grp_fu_759_p1 = reg_1019;
end
end
/// grp_fu_763_p0 assign process. ///
always @ (ap_CS_fsm or reg_1365 or reg_1444)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_763_p0 = reg_1444;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_763_p0 = reg_1365;
end else begin
grp_fu_763_p0 = reg_1444;
end
end
/// grp_fu_763_p1 assign process. ///
always @ (ap_CS_fsm or U_qr or reg_1098)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_763_p1 = U_qr;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_763_p1 = reg_1098;
end else begin
grp_fu_763_p1 = U_qr;
end
end
/// grp_fu_767_p0 assign process. ///
always @ (ap_CS_fsm or reg_1355 or reg_1521)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_767_p0 = reg_1521;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_767_p0 = reg_1355;
end else begin
grp_fu_767_p0 = reg_1521;
end
end
/// grp_fu_767_p1 assign process. ///
always @ (ap_CS_fsm or U_qx or reg_1057)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_767_p1 = U_qx;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_767_p1 = reg_1057;
end else begin
grp_fu_767_p1 = U_qx;
end
end
/// grp_fu_771_p0 assign process. ///
always @ (ap_CS_fsm or reg_1365 or reg_1444)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_771_p0 = reg_1444;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_771_p0 = reg_1365;
end else begin
grp_fu_771_p0 = reg_1444;
end
end
/// grp_fu_771_p1 assign process. ///
always @ (ap_CS_fsm or reg_850 or reg_1110)
begin
if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
grp_fu_771_p1 = reg_850;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
grp_fu_771_p1 = reg_1110;
end else begin
grp_fu_771_p1 = reg_1110;
end
end
/// out_X_oplus_U_qr_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qr_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qr_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qr_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qr_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qr_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qx_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qx_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qx_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qx_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qx_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qx_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qy_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qy_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qy_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qy_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qy_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qy_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qz_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qz_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qz_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_qz_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
out_X_oplus_U_qz_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_qz_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_x_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_x_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_x_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_x_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_x_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_x_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_y_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_y_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_y_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_y_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_y_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_y_we0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_z_ce0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_z_ce0 = ap_const_logic_1;
end else begin
out_X_oplus_U_z_ce0 = ap_const_logic_0;
end
end
/// out_X_oplus_U_z_we0 assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
out_X_oplus_U_z_we0 = ap_const_logic_1;
end else begin
out_X_oplus_U_z_we0 = ap_const_logic_0;
end
end
assign grp_fu_555_ce = ap_const_logic_1;
assign grp_fu_560_ce = ap_const_logic_1;
assign grp_fu_566_ce = ap_const_logic_1;
assign grp_fu_571_ce = ap_const_logic_1;
assign grp_fu_583_ce = ap_const_logic_1;
assign grp_fu_588_ce = ap_const_logic_1;
assign grp_fu_592_ce = ap_const_logic_1;
assign grp_fu_596_ce = ap_const_logic_1;
assign grp_fu_600_ce = ap_const_logic_1;
assign grp_fu_604_ce = ap_const_logic_1;
assign grp_fu_608_ce = ap_const_logic_1;
assign grp_fu_612_ce = ap_const_logic_1;
assign grp_fu_618_ce = ap_const_logic_1;
assign grp_fu_622_ce = ap_const_logic_1;
assign grp_fu_626_ce = ap_const_logic_1;
assign grp_fu_630_ce = ap_const_logic_1;
assign grp_fu_634_ce = ap_const_logic_1;
assign grp_fu_640_ce = ap_const_logic_1;
assign grp_fu_652_ce = ap_const_logic_1;
assign grp_fu_658_ce = ap_const_logic_1;
assign grp_fu_663_ce = ap_const_logic_1;
assign grp_fu_668_ce = ap_const_logic_1;
assign grp_fu_673_ce = ap_const_logic_1;
assign grp_fu_678_ce = ap_const_logic_1;
assign grp_fu_683_ce = ap_const_logic_1;
assign grp_fu_692_ce = ap_const_logic_1;
assign grp_fu_696_ce = ap_const_logic_1;
assign grp_fu_701_ce = ap_const_logic_1;
assign grp_fu_705_ce = ap_const_logic_1;
assign grp_fu_709_ce = ap_const_logic_1;
assign grp_fu_714_ce = ap_const_logic_1;
assign grp_fu_718_ce = ap_const_logic_1;
assign grp_fu_722_ce = ap_const_logic_1;
assign grp_fu_727_ce = ap_const_logic_1;
assign grp_fu_732_ce = ap_const_logic_1;
assign grp_fu_737_ce = ap_const_logic_1;
assign grp_fu_742_ce = ap_const_logic_1;
assign grp_fu_747_ce = ap_const_logic_1;
assign grp_fu_755_ce = ap_const_logic_1;
assign grp_fu_759_ce = ap_const_logic_1;
assign grp_fu_763_ce = ap_const_logic_1;
assign grp_fu_767_ce = ap_const_logic_1;
assign grp_fu_771_ce = ap_const_logic_1;
assign grp_fu_775_ce = ap_const_logic_1;
assign grp_fu_775_p0 = reg_1521;
assign grp_fu_775_p1 = U_qr;
assign grp_fu_779_ce = ap_const_logic_1;
assign grp_fu_779_p0 = reg_1444;
assign grp_fu_779_p1 = reg_869;
assign grp_fu_783_ce = ap_const_logic_1;
assign grp_fu_783_p0 = reg_1521;
assign grp_fu_783_p1 = U_qz;
assign grp_fu_787_ce = ap_const_logic_1;
assign grp_fu_787_p0 = reg_1444;
assign grp_fu_787_p1 = reg_961;
assign grp_fu_791_ce = ap_const_logic_1;
assign grp_fu_791_p0 = reg_1521;
assign grp_fu_791_p1 = reg_869;
assign i_1_fu_1646_p1 = {{1{tmp_52_reg_1809[30]}}, {tmp_52_reg_1809}};
assign i_1_fu_1646_p2 = (ap_const_lv32_5F3759D5 - i_1_fu_1646_p1);
assign i_2_fu_1629_p1 = reg_903;
assign i_3_fu_1601_p1 = reg_795;
assign i_fu_1618_p1 = {{1{tmp_53_reg_1799[30]}}, {tmp_53_reg_1799}};
assign i_fu_1618_p2 = (ap_const_lv32_5F3759D5 - i_fu_1618_p1);
assign out_X_oplus_U_qr_address0 = ap_const_lv64_0;
assign out_X_oplus_U_qr_address1 = ap_const_lv1_0;
assign out_X_oplus_U_qr_ce1 = ap_const_logic_0;
assign out_X_oplus_U_qr_d0 = reg_850;
assign out_X_oplus_U_qr_d1 = ap_const_lv32_0;
assign out_X_oplus_U_qr_we1 = ap_const_logic_0;
assign out_X_oplus_U_qx_address0 = ap_const_lv64_0;
assign out_X_oplus_U_qx_address1 = ap_const_lv1_0;
assign out_X_oplus_U_qx_ce1 = ap_const_logic_0;
assign out_X_oplus_U_qx_d0 = reg_869;
assign out_X_oplus_U_qx_d1 = ap_const_lv32_0;
assign out_X_oplus_U_qx_we1 = ap_const_logic_0;
assign out_X_oplus_U_qy_address0 = ap_const_lv64_0;
assign out_X_oplus_U_qy_address1 = ap_const_lv1_0;
assign out_X_oplus_U_qy_ce1 = ap_const_logic_0;
assign out_X_oplus_U_qy_d0 = reg_931;
assign out_X_oplus_U_qy_d1 = ap_const_lv32_0;
assign out_X_oplus_U_qy_we1 = ap_const_logic_0;
assign out_X_oplus_U_qz_address0 = ap_const_lv64_0;
assign out_X_oplus_U_qz_address1 = ap_const_lv1_0;
assign out_X_oplus_U_qz_ce1 = ap_const_logic_0;
assign out_X_oplus_U_qz_d0 = X_plus_U_qz_reg_1782;
assign out_X_oplus_U_qz_d1 = ap_const_lv32_0;
assign out_X_oplus_U_qz_we1 = ap_const_logic_0;
assign out_X_oplus_U_x_address0 = ap_const_lv64_0;
assign out_X_oplus_U_x_address1 = ap_const_lv1_0;
assign out_X_oplus_U_x_ce1 = ap_const_logic_0;
assign out_X_oplus_U_x_d0 = reg_1006;
assign out_X_oplus_U_x_d1 = ap_const_lv32_0;
assign out_X_oplus_U_x_we1 = ap_const_logic_0;
assign out_X_oplus_U_y_address0 = ap_const_lv64_0;
assign out_X_oplus_U_y_address1 = ap_const_lv1_0;
assign out_X_oplus_U_y_ce1 = ap_const_logic_0;
assign out_X_oplus_U_y_d0 = reg_1136;
assign out_X_oplus_U_y_d1 = ap_const_lv32_0;
assign out_X_oplus_U_y_we1 = ap_const_logic_0;
assign out_X_oplus_U_z_address0 = ap_const_lv64_0;
assign out_X_oplus_U_z_address1 = ap_const_lv1_0;
assign out_X_oplus_U_z_ce1 = ap_const_logic_0;
assign out_X_oplus_U_z_d0 = reg_1144;
assign out_X_oplus_U_z_d1 = ap_const_lv32_0;
assign out_X_oplus_U_z_we1 = ap_const_logic_0;
assign tmp1_i1_fu_1624_p1 = i_fu_1618_p2;
assign tmp1_i_fu_1652_p1 = i_1_fu_1646_p2;
endmodule //jacobiansPoseComposition
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_555_ACMP_faddfsub_1(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_560_ACMP_faddfsub_2(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_566_ACMP_faddfsub_3(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_571_ACMP_faddfsub_4(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_583_ACMP_faddfsub_5(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_588_ACMP_faddfsub_6(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[2 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_faddfsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_faddfsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_592_ACMP_fadd_7(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_596_ACMP_fadd_8(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_600_ACMP_fadd_9(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_604_ACMP_fadd_10(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_608_ACMP_fadd_11(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_612_ACMP_fadd_12(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_618_ACMP_fadd_13(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_622_ACMP_fadd_14(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_626_ACMP_fadd_15(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_630_ACMP_fadd_16(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_634_ACMP_fmul_17(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_640_ACMP_fmul_18(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_652_ACMP_fmul_19(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_658_ACMP_fmul_20(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_663_ACMP_fmul_21(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_668_ACMP_fmul_22(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_673_ACMP_fmul_23(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_678_ACMP_fmul_24(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_683_ACMP_fmul_25(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_692_ACMP_fmul_26(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_696_ACMP_fmul_27(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_701_ACMP_fmul_28(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_705_ACMP_fmul_29(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_709_ACMP_fmul_30(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_714_ACMP_fmul_31(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_718_ACMP_fmul_32(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_722_ACMP_fmul_33(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_727_ACMP_fmul_34(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_732_ACMP_fmul_35(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_737_ACMP_fmul_36(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_742_ACMP_fmul_37(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_747_ACMP_fmul_38(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_755_ACMP_fmul_39(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_759_ACMP_fmul_40(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_763_ACMP_fmul_41(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_767_ACMP_fmul_42(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_771_ACMP_fmul_43(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_775_ACMP_fmul_44(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_779_ACMP_fmul_45(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_783_ACMP_fmul_46(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_787_ACMP_fmul_47(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoESL - High-Level Synthesis System (C, C++, SystemC)
// Version: 2011.1
// Copyright (C) 2011 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module jacobiansPoseComposition_grp_fu_791_ACMP_fmul_48(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_clockgen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_clockgen.v,v $
// Revision 1.4 2005/02/21 12:48:05 igorm
// Warning fixes.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:55 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= #Tp 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= #Tp CounterPreset[7:0];
end
else
Counter[7:0] <= #Tp Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= #Tp 1'b0;
else
begin
if(CountEq0)
Mdc <= #Tp ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_cop.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_cop.v,v $
// Revision 1.4 2003/06/13 11:55:37 mohor
// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
// moved from tb_eth_defines.v to eth_defines.v.
//
// Revision 1.3 2002/10/10 16:43:59 mohor
// Minor $display change.
//
// Revision 1.2 2002/09/09 12:54:13 mohor
// error acknowledge cycle termination added to display.
//
// Revision 1.1 2002/08/14 17:16:07 mohor
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
// interfaces:
// - Host connects to the master interface
// - Ethernet master (DMA) connects to the second master interface
// - Memory interface connects to the slave interface
// - Ethernet slave interface (access to registers and BDs) connects to second
// slave interface
//
//
//
//
//
`include "eth_defines.v"
`include "timescale.v"
module eth_cop
(
// WISHBONE common
wb_clk_i, wb_rst_i,
// WISHBONE MASTER 1
m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o,
m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
m1_wb_err_o,
// WISHBONE MASTER 2
m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o,
m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
m2_wb_err_o,
// WISHBONE slave 1
s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o,
s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
s1_wb_dat_o,
// WISHBONE slave 2
s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,
s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
s2_wb_dat_o
);
parameter Tp=1;
// WISHBONE common
input wb_clk_i, wb_rst_i;
// WISHBONE MASTER 1
input [31:0] m1_wb_adr_i, m1_wb_dat_i;
input [3:0] m1_wb_sel_i;
input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
output [31:0] m1_wb_dat_o;
output m1_wb_ack_o, m1_wb_err_o;
// WISHBONE MASTER 2
input [31:0] m2_wb_adr_i, m2_wb_dat_i;
input [3:0] m2_wb_sel_i;
input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
output [31:0] m2_wb_dat_o;
output m2_wb_ack_o, m2_wb_err_o;
// WISHBONE slave 1
input [31:0] s1_wb_dat_i;
input s1_wb_ack_i, s1_wb_err_i;
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
output [3:0] s1_wb_sel_o;
output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o;
// WISHBONE slave 2
input [31:0] s2_wb_dat_i;
input s2_wb_ack_i, s2_wb_err_i;
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
output [3:0] s2_wb_sel_o;
output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o;
reg m1_in_progress;
reg m2_in_progress;
reg [31:0] s1_wb_adr_o;
reg [3:0] s1_wb_sel_o;
reg s1_wb_we_o;
reg [31:0] s1_wb_dat_o;
reg s1_wb_cyc_o;
reg s1_wb_stb_o;
reg [31:0] s2_wb_adr_o;
reg [3:0] s2_wb_sel_o;
reg s2_wb_we_o;
reg [31:0] s2_wb_dat_o;
reg s2_wb_cyc_o;
reg s2_wb_stb_o;
reg m1_wb_ack_o;
reg [31:0] m1_wb_dat_o;
reg m2_wb_ack_o;
reg [31:0] m2_wb_dat_o;
reg m1_wb_err_o;
reg m2_wb_err_o;
wire m_wb_access_finished;
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
m1_in_progress <=#Tp 0;
m2_in_progress <=#Tp 0;
s1_wb_adr_o <=#Tp 0;
s1_wb_sel_o <=#Tp 0;
s1_wb_we_o <=#Tp 0;
s1_wb_dat_o <=#Tp 0;
s1_wb_cyc_o <=#Tp 0;
s1_wb_stb_o <=#Tp 0;
s2_wb_adr_o <=#Tp 0;
s2_wb_sel_o <=#Tp 0;
s2_wb_we_o <=#Tp 0;
s2_wb_dat_o <=#Tp 0;
s2_wb_cyc_o <=#Tp 0;
s2_wb_stb_o <=#Tp 0;
end
else
begin
case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case
5'b00_10_0, 5'b00_11_0 :
begin
m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m
if(`M1_ADDRESSED_S1)
begin
s1_wb_adr_o <=#Tp m1_wb_adr_i;
s1_wb_sel_o <=#Tp m1_wb_sel_i;
s1_wb_we_o <=#Tp m1_wb_we_i;
s1_wb_dat_o <=#Tp m1_wb_dat_i;
s1_wb_cyc_o <=#Tp 1'b1;
s1_wb_stb_o <=#Tp 1'b1;
end
else if(`M1_ADDRESSED_S2)
begin
s2_wb_adr_o <=#Tp m1_wb_adr_i;
s2_wb_sel_o <=#Tp m1_wb_sel_i;
s2_wb_we_o <=#Tp m1_wb_we_i;
s2_wb_dat_o <=#Tp m1_wb_dat_i;
s2_wb_cyc_o <=#Tp 1'b1;
s2_wb_stb_o <=#Tp 1'b1;
end
else
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
end
5'b00_01_0 :
begin
m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m
if(`M2_ADDRESSED_S1)
begin
s1_wb_adr_o <=#Tp m2_wb_adr_i;
s1_wb_sel_o <=#Tp m2_wb_sel_i;
s1_wb_we_o <=#Tp m2_wb_we_i;
s1_wb_dat_o <=#Tp m2_wb_dat_i;
s1_wb_cyc_o <=#Tp 1'b1;
s1_wb_stb_o <=#Tp 1'b1;
end
else if(`M2_ADDRESSED_S2)
begin
s2_wb_adr_o <=#Tp m2_wb_adr_i;
s2_wb_sel_o <=#Tp m2_wb_sel_i;
s2_wb_we_o <=#Tp m2_wb_we_i;
s2_wb_dat_o <=#Tp m2_wb_dat_i;
s2_wb_cyc_o <=#Tp 1'b1;
s2_wb_stb_o <=#Tp 1'b1;
end
else
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
end
5'b10_10_1, 5'b10_11_1 :
begin
m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.
if(`M1_ADDRESSED_S1)
begin
s1_wb_cyc_o <=#Tp 1'b0;
s1_wb_stb_o <=#Tp 1'b0;
end
else if(`M1_ADDRESSED_S2)
begin
s2_wb_cyc_o <=#Tp 1'b0;
s2_wb_stb_o <=#Tp 1'b0;
end
end
5'b01_01_1, 5'b01_11_1 :
begin
m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.
if(`M2_ADDRESSED_S1)
begin
s1_wb_cyc_o <=#Tp 1'b0;
s1_wb_stb_o <=#Tp 1'b0;
end
else if(`M2_ADDRESSED_S2)
begin
s2_wb_cyc_o <=#Tp 1'b0;
s2_wb_stb_o <=#Tp 1'b0;
end
end
endcase
end
end
// Generating Ack for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
begin
if(m1_in_progress)
begin
if(`M1_ADDRESSED_S1) begin
m1_wb_ack_o <= s1_wb_ack_i;
m1_wb_dat_o <= s1_wb_dat_i;
end
else if(`M1_ADDRESSED_S2) begin
m1_wb_ack_o <= s2_wb_ack_i;
m1_wb_dat_o <= s2_wb_dat_i;
end
end
else
m1_wb_ack_o <= 0;
end
// Generating Ack for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
begin
if(m2_in_progress)
begin
if(`M2_ADDRESSED_S1) begin
m2_wb_ack_o <= s1_wb_ack_i;
m2_wb_dat_o <= s1_wb_dat_i;
end
else if(`M2_ADDRESSED_S2) begin
m2_wb_ack_o <= s2_wb_ack_i;
m2_wb_dat_o <= s2_wb_dat_i;
end
end
else
m2_wb_ack_o <= 0;
end
// Generating Err for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
m1_wb_cyc_i or m1_wb_stb_i)
begin
if(m1_in_progress) begin
if(`M1_ADDRESSED_S1)
m1_wb_err_o <= s1_wb_err_i;
else if(`M1_ADDRESSED_S2)
m1_wb_err_o <= s2_wb_err_i;
end
else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
m1_wb_err_o <= 1'b1;
else
m1_wb_err_o <= 1'b0;
end
// Generating Err for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
m2_wb_cyc_i or m2_wb_stb_i)
begin
if(m2_in_progress) begin
if(`M2_ADDRESSED_S1)
m2_wb_err_o <= s1_wb_err_i;
else if(`M2_ADDRESSED_S2)
m2_wb_err_o <= s2_wb_err_i;
end
else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
m2_wb_err_o <= 1'b1;
else
m2_wb_err_o <= 1'b0;
end
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
// Activity monitor
integer cnt;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
cnt <=#Tp 0;
else
if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
cnt <=#Tp 0;
else
if(s1_wb_cyc_o | s2_wb_cyc_o)
cnt <=#Tp cnt+1;
end
always @ (posedge wb_clk_i)
begin
if(cnt==1000) begin
$display("(%0t)(%m) ERROR: WB activity ??? ", $time);
if(s1_wb_cyc_o) begin
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
end
else if(s2_wb_cyc_o) begin
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
end
$stop;
end
end
always @ (posedge wb_clk_i)
begin
if(s1_wb_err_i & s1_wb_cyc_o) begin
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
$stop;
end
if(s2_wb_err_i & s2_wb_cyc_o) begin
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
$stop;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_crc.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_crc.v,v $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
parameter Tp = 1;
input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initialize;
output [31:0] Crc;
output CrcError;
reg [31:0] Crc;
wire [31:0] CrcNext;
assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
assign CrcNext[20] = Crc[16];
assign CrcNext[21] = Crc[17];
assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
assign CrcNext[30] = Crc[26];
assign CrcNext[31] = Crc[27];
always @ (posedge Clk or posedge Reset)
begin
if (Reset)
Crc <= #1 32'hffffffff;
else
if(Initialize)
Crc <= #Tp 32'hffffffff;
else
Crc <= #Tp CrcNext;
end
assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_defines.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_defines.v,v $
// Revision 1.34 2005/02/21 12:48:06 igorm
// Warning fixes.
//
// Revision 1.33 2003/11/12 18:24:58 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.32 2003/10/17 07:46:13 markom
// mbist signals updated according to newest convention
//
// Revision 1.31 2003/08/14 16:42:58 simons
// Artisan ram instance added.
//
// Revision 1.30 2003/06/13 11:55:37 mohor
// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
// moved from tb_eth_defines.v to eth_defines.v.
//
// Revision 1.29 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.28 2002/11/15 14:27:15 mohor
// Since r_Rst bit is not used any more, default value is changed to 0xa000.
//
// Revision 1.27 2002/11/01 18:19:34 mohor
// Defines fixed to use generic RAM by default.
//
// Revision 1.26 2002/10/24 18:53:03 mohor
// fpga define added.
//
// Revision 1.3 2002/10/11 16:57:54 igorm
// eth_defines.v tagged with rel_5 used.
//
// Revision 1.25 2002/10/10 16:47:44 mohor
// Defines changed to have ETH_ prolog.
// ETH_WISHBONE_B# define added.
//
// Revision 1.24 2002/10/10 16:33:11 mohor
// Bist added.
//
// Revision 1.23 2002/09/23 18:22:48 mohor
// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
// core.
//
// Revision 1.22 2002/09/04 18:36:49 mohor
// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).
//
// Revision 1.21 2002/08/16 22:09:47 mohor
// Defines for register width added. mii_rst signal in MIIMODER register
// changed.
//
// Revision 1.20 2002/08/14 19:31:48 mohor
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
// need to multiply or devide any more.
//
// Revision 1.19 2002/07/23 15:28:31 mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.18 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.17 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.16 2002/03/19 12:53:29 mohor
// Some defines that are used in testbench only were moved to tb_eth_defines.v
// file.
//
// Revision 1.15 2002/02/26 16:11:32 mohor
// Number of interrupts changed
//
// Revision 1.14 2002/02/16 14:03:44 mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.13 2002/02/16 13:06:33 mohor
// EXTERNAL_DMA used instead of WISHBONE_DMA.
//
// Revision 1.12 2002/02/15 10:58:31 mohor
// Changed that were lost with last update put back to the file.
//
// Revision 1.11 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.10 2002/02/12 17:01:19 mohor
// HASH0 and HASH1 registers added.
// Revision 1.9 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.8 2002/02/05 16:44:38 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
// Revision 1.7 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.6 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.5 2001/12/05 10:21:37 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.4 2001/11/13 14:23:56 mohor
// Generic memory model is used. Defines are changed for the same reason.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
// Ethernet implemented in Xilinx Chips (uncomment following lines)
// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
// Core is going to be implemented in Virtex FPGA and contains Virtex
// specific elements.
// Ethernet implemented in Altera Chips (uncomment following lines)
//`define ETH_ALTERA_ALTSYNCRAM
// Ethernet implemented in ASIC with Virtual Silicon RAMs
// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
// Ethernet implemented in ASIC with Artisan RAMs
// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
// Uncomment when Avalon bus is used
//`define ETH_AVALON_BUS
`define ETH_MODER_ADR 8'h0 // 0x0
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
`define ETH_INT_MASK_ADR 8'h2 // 0x8
`define ETH_IPGT_ADR 8'h3 // 0xC
`define ETH_IPGR1_ADR 8'h4 // 0x10
`define ETH_IPGR2_ADR 8'h5 // 0x14
`define ETH_PACKETLEN_ADR 8'h6 // 0x18
`define ETH_COLLCONF_ADR 8'h7 // 0x1C
`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
`define ETH_CTRLMODER_ADR 8'h9 // 0x24
`define ETH_MIIMODER_ADR 8'hA // 0x28
`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
`define ETH_MIIADDRESS_ADR 8'hC // 0x30
`define ETH_MIITX_DATA_ADR 8'hD // 0x34
`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
`define ETH_MIISTATUS_ADR 8'hF // 0x3C
`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
`define ETH_HASH0_ADR 8'h12 // 0x48
`define ETH_HASH1_ADR 8'h13 // 0x4C
`define ETH_TX_CTRL_ADR 8'h14 // 0x50
`define ETH_RX_CTRL_ADR 8'h15 // 0x54
`define ETH_MODER_DEF_0 8'h00
`define ETH_MODER_DEF_1 8'hA0
`define ETH_MODER_DEF_2 1'h0
`define ETH_INT_MASK_DEF_0 7'h0
`define ETH_IPGT_DEF_0 7'h12
`define ETH_IPGR1_DEF_0 7'h0C
`define ETH_IPGR2_DEF_0 7'h12
`define ETH_PACKETLEN_DEF_0 8'h00
`define ETH_PACKETLEN_DEF_1 8'h06
`define ETH_PACKETLEN_DEF_2 8'h40
`define ETH_PACKETLEN_DEF_3 8'h00
`define ETH_COLLCONF_DEF_0 6'h3f
`define ETH_COLLCONF_DEF_2 4'hF
`define ETH_TX_BD_NUM_DEF_0 8'h40
`define ETH_CTRLMODER_DEF_0 3'h0
`define ETH_MIIMODER_DEF_0 8'h64
`define ETH_MIIMODER_DEF_1 1'h0
`define ETH_MIIADDRESS_DEF_0 5'h00
`define ETH_MIIADDRESS_DEF_1 5'h00
`define ETH_MIITX_DATA_DEF_0 8'h00
`define ETH_MIITX_DATA_DEF_1 8'h00
`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB
`define ETH_MAC_ADDR0_DEF_0 8'h00
`define ETH_MAC_ADDR0_DEF_1 8'h00
`define ETH_MAC_ADDR0_DEF_2 8'h00
`define ETH_MAC_ADDR0_DEF_3 8'h00
`define ETH_MAC_ADDR1_DEF_0 8'h00
`define ETH_MAC_ADDR1_DEF_1 8'h00
`define ETH_HASH0_DEF_0 8'h00
`define ETH_HASH0_DEF_1 8'h00
`define ETH_HASH0_DEF_2 8'h00
`define ETH_HASH0_DEF_3 8'h00
`define ETH_HASH1_DEF_0 8'h00
`define ETH_HASH1_DEF_1 8'h00
`define ETH_HASH1_DEF_2 8'h00
`define ETH_HASH1_DEF_3 8'h00
`define ETH_TX_CTRL_DEF_0 8'h00 //
`define ETH_TX_CTRL_DEF_1 8'h00 //
`define ETH_TX_CTRL_DEF_2 1'h0 //
`define ETH_RX_CTRL_DEF_0 8'h00
`define ETH_RX_CTRL_DEF_1 8'h00
`define ETH_MODER_WIDTH_0 8
`define ETH_MODER_WIDTH_1 8
`define ETH_MODER_WIDTH_2 1
`define ETH_INT_SOURCE_WIDTH_0 7
`define ETH_INT_MASK_WIDTH_0 7
`define ETH_IPGT_WIDTH_0 7
`define ETH_IPGR1_WIDTH_0 7
`define ETH_IPGR2_WIDTH_0 7
`define ETH_PACKETLEN_WIDTH_0 8
`define ETH_PACKETLEN_WIDTH_1 8
`define ETH_PACKETLEN_WIDTH_2 8
`define ETH_PACKETLEN_WIDTH_3 8
`define ETH_COLLCONF_WIDTH_0 6
`define ETH_COLLCONF_WIDTH_2 4
`define ETH_TX_BD_NUM_WIDTH_0 8
`define ETH_CTRLMODER_WIDTH_0 3
`define ETH_MIIMODER_WIDTH_0 8
`define ETH_MIIMODER_WIDTH_1 1
`define ETH_MIICOMMAND_WIDTH_0 3
`define ETH_MIIADDRESS_WIDTH_0 5
`define ETH_MIIADDRESS_WIDTH_1 5
`define ETH_MIITX_DATA_WIDTH_0 8
`define ETH_MIITX_DATA_WIDTH_1 8
`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB
`define ETH_MIISTATUS_WIDTH 3 // not written from WB
`define ETH_MAC_ADDR0_WIDTH_0 8
`define ETH_MAC_ADDR0_WIDTH_1 8
`define ETH_MAC_ADDR0_WIDTH_2 8
`define ETH_MAC_ADDR0_WIDTH_3 8
`define ETH_MAC_ADDR1_WIDTH_0 8
`define ETH_MAC_ADDR1_WIDTH_1 8
`define ETH_HASH0_WIDTH_0 8
`define ETH_HASH0_WIDTH_1 8
`define ETH_HASH0_WIDTH_2 8
`define ETH_HASH0_WIDTH_3 8
`define ETH_HASH1_WIDTH_0 8
`define ETH_HASH1_WIDTH_1 8
`define ETH_HASH1_WIDTH_2 8
`define ETH_HASH1_WIDTH_3 8
`define ETH_TX_CTRL_WIDTH_0 8
`define ETH_TX_CTRL_WIDTH_1 8
`define ETH_TX_CTRL_WIDTH_2 1
`define ETH_RX_CTRL_WIDTH_0 8
`define ETH_RX_CTRL_WIDTH_1 8
// Outputs are registered (uncomment when needed)
`define ETH_REGISTERED_OUTPUTS
// Settings for TX FIFO
`define ETH_TX_FIFO_CNT_WIDTH 5
`define ETH_TX_FIFO_DEPTH 16
`define ETH_TX_FIFO_DATA_WIDTH 32
// Settings for RX FIFO
`define ETH_RX_FIFO_CNT_WIDTH 5
`define ETH_RX_FIFO_DEPTH 16
`define ETH_RX_FIFO_DATA_WIDTH 32
// Burst length
`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH
`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH
// WISHBONE interface is Revision B3 compliant (uncomment when needed)
//`define ETH_WISHBONE_B3
// Following defines are needed when eth_cop.v is used. Otherwise they may be deleted.
`define ETH_BASE 32'hd0000000
`define ETH_WIDTH 32'h800
`define MEMORY_BASE 32'h2000
`define MEMORY_WIDTH 32'h10000
`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
// Previous defines are only needed for eth_cop.v
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_fifo.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_fifo.v,v $
// Revision 1.4 2005/02/21 12:48:07 igorm
// Warning fixes.
//
// Revision 1.3 2002/04/22 13:45:52 mohor
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
// ETH_FIFO_XILINX in eth_defines.v).
//
// Revision 1.2 2002/03/25 13:33:04 mohor
// When clear and read/write are active at the same time, cnt and pointers are
// set to 1.
//
// Revision 1.1 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
//
`include "eth_defines.v"
`include "timescale.v"
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
parameter Tp = 1;
input clk;
input reset;
input write;
input read;
input clear;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output almost_full;
output full;
output almost_empty;
output empty;
output [CNT_WIDTH-1:0] cnt;
`ifdef ETH_FIFO_XILINX
`else
`ifdef ETH_ALTERA_ALTSYNCRAM
`else
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
reg [DATA_WIDTH-1:0] data_out;
`endif
`endif
reg [CNT_WIDTH-1:0] cnt;
reg [CNT_WIDTH-2:0] read_pointer;
reg [CNT_WIDTH-2:0] write_pointer;
always @ (posedge clk or posedge reset)
begin
if(reset)
cnt <=#Tp 0;
else
if(clear)
cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};
else
if(read ^ write)
if(read)
cnt <=#Tp cnt - 1'b1;
else
cnt <=#Tp cnt + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
read_pointer <=#Tp 0;
else
if(clear)
read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};
else
if(read & ~empty)
read_pointer <=#Tp read_pointer + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
write_pointer <=#Tp 0;
else
if(clear)
write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};
else
if(write & ~full)
write_pointer <=#Tp write_pointer + 1'b1;
end
assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full = cnt == DEPTH;
assign almost_full = &cnt[CNT_WIDTH-2:0];
`ifdef ETH_FIFO_XILINX
xilinx_dist_ram_16x32 fifo
( .data_out(data_out),
.we(write & ~full),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.wclk(clk)
);
`else // !ETH_FIFO_XILINX
`ifdef ETH_ALTERA_ALTSYNCRAM
altera_dpram_16x32 altera_dpram_16x32_inst
(
.data (data_in),
.wren (write & ~full),
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
.clock (clk),
.q (data_out)
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
`else // !ETH_ALTERA_ALTSYNCRAM
always @ (posedge clk)
begin
if(write & clear)
fifo[0] <=#Tp data_in;
else
if(write & ~full)
fifo[write_pointer] <=#Tp data_in;
end
always @ (posedge clk)
begin
if(clear)
data_out <=#Tp fifo[0];
else
data_out <=#Tp fifo[read_pointer];
end
`endif // !ETH_ALTERA_ALTSYNCRAM
`endif // !ETH_FIFO_XILINX
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_maccontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_maccontrol.v,v $
// Revision 1.7 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.6 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.5 2002/11/21 00:14:39 mohor
// TxDone and TxAbort changed so they're not propagated to the wishbone
// module when control frame is transmitted.
//
// Revision 1.4 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
`include "timescale.v"
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input MRxClk; // Receive clock (from PHY)
input TxReset; // Transmit reset
input RxReset; // Receive reset
input TPauseRq; // Transmit control frame (from host)
input [7:0] TxDataIn; // Transmit packet data byte (from host)
input TxStartFrmIn; // Transmit packet start frame input (from host)
input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
input TxEndFrmIn; // Transmit packet end frame input (from host)
input TxDoneIn; // Transmit packet done (from TxEthMAC)
input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
input PadIn; // Padding (input from registers)
input CrcEnIn; // Crc append (input from registers)
input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
input RxValid; // Received a valid packet
input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
input ReceivedPacketGood; // Received packet is good
input ReceivedLengthOK; // Length of the received packet is OK
input TxFlow; // Tx flow control (from registers)
input RxFlow; // Rx flow control (from registers)
input DlyCrcEn; // Delayed CRC enabled (from registers)
input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
input [47:0] MAC; // MAC address (from registers)
input RxStatusWriteLatched_sync2;
input r_PassAll;
output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
output TxDoneOut; // Transmit packet done (to host)
output TxAbortOut; // Transmit packet aborted (to host)
output TxUsedDataOut; // Transmit packet used data (to host)
output PadOut; // Padding (output to TxEthMAC)
output CrcEnOut; // Crc append (output to TxEthMAC)
output WillSendControlFrame;
output TxCtrlEndFrm;
output ReceivedPauseFrm;
output ControlFrmAddressOK;
output SetPauseTimer;
reg TxUsedDataOutDetected;
reg TxAbortInLatched;
reg TxDoneInLatched;
reg MuxedDone;
reg MuxedAbort;
wire Pause;
wire TxCtrlStartFrm;
wire [7:0] ControlData;
wire CtrlMux;
wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
wire BlockTxDone;
// Signal TxUsedDataOut was detected (a transfer is already in progress)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxDoneIn | TxAbortIn)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxUsedDataOut)
TxUsedDataOutDetected <= #Tp 1'b1;
end
// Latching variables
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
TxAbortInLatched <= #Tp 1'b0;
TxDoneInLatched <= #Tp 1'b0;
end
else
begin
TxAbortInLatched <= #Tp TxAbortIn;
TxDoneInLatched <= #Tp TxDoneIn;
end
end
// Generating muxed abort signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedAbort <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedAbort <= #Tp 1'b0;
else
if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
MuxedAbort <= #Tp 1'b1;
end
// Generating muxed done signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedDone <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedDone <= #Tp 1'b0;
else
if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
MuxedDone <= #Tp 1'b1;
end
// TxDoneOut
assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
// TxAbortOut
assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
// TxUsedDataOut
assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
// TxStartFrmOut
assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
// TxEndFrmOut
assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
// TxDataOut[7:0]
assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
// PadOut
assign PadOut = PadIn | SendingCtrlFrm;
// CrcEnOut
assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
// Connecting receivecontrol module
eth_receivecontrol receivecontrol1
(
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
.r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
);
eth_transmitcontrol transmitcontrol1
(
.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
.TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
.MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
.CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_macstatus.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_macstatus.v,v $
// Revision 1.17 2005/03/21 20:07:18 igorm
// Some small fixes + some troubles fixed.
//
// Revision 1.16 2005/02/21 10:42:11 igorm
// Defer indication fixed.
//
// Revision 1.15 2003/01/30 13:28:19 tadejm
// Defer indication changed.
//
// Revision 1.14 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.13 2002/11/13 22:30:58 tadejm
// Late collision is reported only when not in the full duplex.
// Sample is taken (for status) as soon as MRxDV is not valid (regardless
// of the received byte cnt).
//
// Revision 1.12 2002/09/12 14:50:16 mohor
// CarrierSenseLost bug fixed when operating in full duplex mode.
//
// Revision 1.11 2002/09/04 18:38:03 mohor
// CarrierSenseLost status is not set when working in loopback mode.
//
// Revision 1.10 2002/07/25 18:17:46 mohor
// InvalidSymbol generation changed.
//
// Revision 1.9 2002/04/22 13:51:44 mohor
// Short frame and ReceivedLengthOK were not detected correctly.
//
// Revision 1.8 2002/02/18 10:40:17 mohor
// Small fixes.
//
// Revision 1.7 2002/02/15 17:07:39 mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.6 2002/02/11 09:18:21 mohor
// Tx status is written back to the BD.
//
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
`include "timescale.v"
module eth_macstatus(
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
r_FullD
);
parameter Tp = 1;
input MRxClk;
input Reset;
input RxCrcError;
input MRxErr;
input MRxDV;
input RxStateSFD;
input [1:0] RxStateData;
input RxStatePreamble;
input RxStateIdle;
input Transmitting;
input [15:0] RxByteCnt;
input RxByteCntEq0;
input RxByteCntGreat2;
input RxByteCntMaxFrame;
input [3:0] MRxD;
input Collision;
input [5:0] CollValid;
input r_RecSmall;
input [15:0] r_MinFL;
input [15:0] r_MaxFL;
input r_HugEn;
input StartTxDone;
input StartTxAbort;
input [3:0] RetryCnt;
input MTxClk;
input MaxCollisionOccured;
input LateCollision;
input DeferIndication;
input TxStartFrm;
input StatePreamble;
input [1:0] StateData;
input CarrierSense;
input TxUsedData;
input Loopback;
input r_FullD;
output ReceivedLengthOK;
output ReceiveEnd;
output ReceivedPacketGood;
output InvalidSymbol;
output LatchedCrcError;
output RxLateCollision;
output ShortFrame;
output DribbleNibble;
output ReceivedPacketTooBig;
output LoadRxStatus;
output [3:0] RetryCntLatched;
output RetryLimit;
output LateCollLatched;
output DeferLatched;
input RstDeferLatched;
output CarrierSenseLost;
output LatchedMRxErr;
reg ReceiveEnd;
reg LatchedCrcError;
reg LatchedMRxErr;
reg LoadRxStatus;
reg InvalidSymbol;
reg [3:0] RetryCntLatched;
reg RetryLimit;
reg LateCollLatched;
reg DeferLatched;
reg CarrierSenseLost;
wire TakeSample;
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateSFD)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateData[0])
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
end
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedMRxErr <=#Tp 1'b0;
else
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
LatchedMRxErr <=#Tp 1'b1;
else
LatchedMRxErr <=#Tp 1'b0;
end
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
// Time to take a sample
//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
assign TakeSample = (|RxStateData) & (~MRxDV) |
RxStateData[0] & MRxDV & RxByteCntMaxFrame;
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LoadRxStatus <=#Tp 1'b0;
else
LoadRxStatus <=#Tp TakeSample;
end
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceiveEnd <=#Tp 1'b0;
else
ReceiveEnd <=#Tp LoadRxStatus;
end
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
InvalidSymbol <=#Tp 1'b0;
else
if(LoadRxStatus & ~SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b0;
else
if(SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b1;
end
// Late Collision
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxLateCollision <=#Tp 1'b0;
else
if(LoadRxStatus)
RxLateCollision <=#Tp 1'b0;
else
if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
RxLateCollision <=#Tp 1'b1;
end
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxColWindow <=#Tp 1'b1;
else
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
RxColWindow <=#Tp 1'b0;
else
if(RxStateIdle)
RxColWindow <=#Tp 1'b1;
end
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShortFrame <=#Tp 1'b0;
else
if(LoadRxStatus)
ShortFrame <=#Tp 1'b0;
else
if(TakeSample)
ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
end
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DribbleNibble <=#Tp 1'b0;
else
if(RxStateSFD)
DribbleNibble <=#Tp 1'b0;
else
if(~MRxDV & RxStateData[1])
DribbleNibble <=#Tp 1'b1;
end
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(LoadRxStatus)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(TakeSample)
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCntLatched <=#Tp 4'h0;
else
if(StartTxDone | StartTxAbort)
RetryCntLatched <=#Tp RetryCnt;
end
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryLimit <=#Tp 1'h0;
else
if(StartTxDone | StartTxAbort)
RetryLimit <=#Tp MaxCollisionOccured;
end
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LateCollLatched <=#Tp 1'b0;
else
if(StartTxDone | StartTxAbort)
LateCollLatched <=#Tp LateCollision;
end
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DeferLatched <=#Tp 1'b0;
else
if(DeferIndication)
DeferLatched <=#Tp 1'b1;
else
if(RstDeferLatched)
DeferLatched <=#Tp 1'b0;
end
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
CarrierSenseLost <=#Tp 1'b0;
else
if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
CarrierSenseLost <=#Tp 1'b1;
else
if(TxStartFrm)
CarrierSenseLost <=#Tp 1'b0;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_miim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_miim.v,v $
// Revision 1.7 2005/03/21 20:07:18 igorm
// Some small fixes + some troubles fixed.
//
// Revision 1.6 2005/02/21 12:48:07 igorm
// Warning fixes.
//
// Revision 1.5 2003/05/16 10:08:27 mohor
// Busy was set 2 cycles too late. Reported by Dennis Scott.
//
// Revision 1.4 2002/08/14 18:32:10 mohor
// - Busy signal was not set on time when scan status operation was performed
// and clock was divided with more than 2.
// - Nvalid remains valid two more clocks (was previously cleared too soon).
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_miim
(
Clk,
Reset,
Divider,
NoPre,
CtrlData,
Rgad,
Fiad,
WCtrlData,
RStat,
ScanStat,
Mdi,
Mdo,
MdoEn,
Mdc,
Busy,
Prsd,
LinkFail,
Nvalid,
WCtrlDataStart,
RStatStart,
UpdateMIIRX_DATAReg
);
input Clk; // Host Clock
input Reset; // General Reset
input [7:0] Divider; // Divider for the host clock
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
input Mdi; // MII Management Data In
output Mdc; // MII Management Data Clock
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
parameter Tp = 1;
reg Nvalid;
reg EndBusy_d; // Pre-end Busy signal
reg EndBusy; // End Busy signal (stops the operation in progress)
reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle
reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles
reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles
reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)
reg WCtrlDataStart_q;
reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle
reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles
reg RStat_q1; // Read Status operation delayed 1 Clk cycle
reg RStat_q2; // Read Status operation delayed 2 Clk cycles
reg RStat_q3; // Read Status operation delayed 3 Clk cycles
reg RStatStart; // Start Read Status Command (positive edge detected)
reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle
reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles
reg ScanStat_q1; // Scan Status operation delayed 1 cycle
reg ScanStat_q2; // Scan Status operation delayed 2 cycles
reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn
wire WriteDataOp; // Write Data Operation (positive edge detected)
wire ReadStatusOp; // Read Status Operation (positive edge detected)
wire ScanStatusOp; // Scan Status Operation (positive edge detected)
wire StartOp; // Start Operation (start of any of the preceding operations)
wire EndOp; // End of Operation
reg InProgress; // Operation in progress
reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
reg [6:0] BitCounter; // Bit Counter
wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
wire LatchByte1_d2;
wire LatchByte0_d2;
reg LatchByte1_d;
reg LatchByte0_d;
reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
EndBusy_d <= #Tp 1'b0;
EndBusy <= #Tp 1'b0;
end
else
begin
EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
EndBusy <= #Tp EndBusy_d;
end
end
// Update MII RX_DATA register
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
UpdateMIIRX_DATAReg <= #Tp 0;
else
if(EndBusy & ~WCtrlDataStart_q)
UpdateMIIRX_DATAReg <= #Tp 1;
else
UpdateMIIRX_DATAReg <= #Tp 0;
end
// Generation of the delayed signals used for positive edge triggering.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlData_q1 <= #Tp 1'b0;
WCtrlData_q2 <= #Tp 1'b0;
WCtrlData_q3 <= #Tp 1'b0;
RStat_q1 <= #Tp 1'b0;
RStat_q2 <= #Tp 1'b0;
RStat_q3 <= #Tp 1'b0;
ScanStat_q1 <= #Tp 1'b0;
ScanStat_q2 <= #Tp 1'b0;
SyncStatMdcEn <= #Tp 1'b0;
end
else
begin
WCtrlData_q1 <= #Tp WCtrlData;
WCtrlData_q2 <= #Tp WCtrlData_q1;
WCtrlData_q3 <= #Tp WCtrlData_q2;
RStat_q1 <= #Tp RStat;
RStat_q2 <= #Tp RStat_q1;
RStat_q3 <= #Tp RStat_q2;
ScanStat_q1 <= #Tp ScanStat;
ScanStat_q2 <= #Tp ScanStat_q1;
if(MdcEn)
SyncStatMdcEn <= #Tp ScanStat_q2;
end
end
// Generation of the Start Commands (Write Control Data or Read Status)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart <= #Tp 1'b0;
WCtrlDataStart_q <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(EndBusy)
begin
WCtrlDataStart <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(WCtrlData_q2 & ~WCtrlData_q3)
WCtrlDataStart <= #Tp 1'b1;
if(RStat_q2 & ~RStat_q3)
RStatStart <= #Tp 1'b1;
WCtrlDataStart_q <= #Tp WCtrlDataStart;
end
end
end
// Generation of the Nvalid signal (indicates when the status is invalid)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Nvalid <= #Tp 1'b0;
else
begin
if(~InProgress_q2 & InProgress_q3)
begin
Nvalid <= #Tp 1'b0;
end
else
begin
if(ScanStat_q2 & ~SyncStatMdcEn)
Nvalid <= #Tp 1'b1;
end
end
end
// Signals used for the generation of the Operation signals (positive edge)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart_q1 <= #Tp 1'b0;
WCtrlDataStart_q2 <= #Tp 1'b0;
RStatStart_q1 <= #Tp 1'b0;
RStatStart_q2 <= #Tp 1'b0;
InProgress_q1 <= #Tp 1'b0;
InProgress_q2 <= #Tp 1'b0;
InProgress_q3 <= #Tp 1'b0;
LatchByte0_d <= #Tp 1'b0;
LatchByte1_d <= #Tp 1'b0;
LatchByte <= #Tp 2'b00;
end
else
begin
if(MdcEn)
begin
WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
RStatStart_q1 <= #Tp RStatStart;
RStatStart_q2 <= #Tp RStatStart_q1;
LatchByte[0] <= #Tp LatchByte0_d;
LatchByte[1] <= #Tp LatchByte1_d;
LatchByte0_d <= #Tp LatchByte0_d2;
LatchByte1_d <= #Tp LatchByte1_d2;
InProgress_q1 <= #Tp InProgress;
InProgress_q2 <= #Tp InProgress_q1;
InProgress_q3 <= #Tp InProgress_q2;
end
end
end
// Generation of the Operation signals
assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
// Busy
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
else
begin
if(MdcEn)
begin
if(StartOp)
begin
if(~InProgress)
WriteOp <= #Tp WriteDataOp;
InProgress <= #Tp 1'b1;
end
else
begin
if(EndOp)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
end
end
end
end
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
BitCounter[6:0] <= #Tp 7'h0;
else
begin
if(MdcEn)
begin
if(InProgress)
begin
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= #Tp 7'h21;
else
BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
end
else
BitCounter[6:0] <= #Tp 7'h0;
end
end
end
// Operation ends when the Bit Counter reaches 63
assign EndOp = BitCounter==63;
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
// Latch Byte selects which part of Read Status Data is updated from the shift register
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
// Connecting the Clock Generator Module
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
);
// Connecting the Shift Register Module
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
);
// Connecting the Output Control Module
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
.Mdo(Mdo), .MdoEn(MdoEn)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_outputcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_outputcontrol.v,v $
// Revision 1.4 2002/07/09 20:11:59 mohor
// Comment removed.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
parameter Tp = 1;
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
wire SerialEn;
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= #Tp 1'b0;
MdoEn_d <= #Tp 1'b0;
MdoEn <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
MdoEn_d <= #Tp MdoEn_2d;
MdoEn <= #Tp MdoEn_d;
end
end
end
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= #Tp 1'b0;
Mdo_d <= #Tp 1'b0;
Mdo <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
Mdo_d <= #Tp ShiftedBit | Mdo_2d;
Mdo <= #Tp Mdo_d;
end
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_random.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_random.v,v $
// Revision 1.4 2003/06/13 11:26:08 mohor
// Binary operator used instead of unary (xnor).
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
`include "timescale.v"
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
parameter Tp = 1;
input MTxClk;
input Reset;
input StateJam;
input StateJam_q;
input [3:0] RetryCnt;
input [15:0] NibCnt;
input [9:0] ByteCnt;
output RandomEq0;
output RandomEqByteCnt;
wire Feedback;
reg [9:0] x;
wire [9:0] Random;
reg [9:0] RandomLatched;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
x[9:0] <= #Tp 0;
else
x[9:0] <= #Tp {x[8:0], Feedback};
end
assign Feedback = ~(x[2] ^ x[9]);
assign Random [0] = x[0];
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RandomLatched <= #Tp 10'h000;
else
begin
if(StateJam & StateJam_q)
RandomLatched <= #Tp Random;
end
end
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0;
assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_receivecontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_receivecontrol.v,v $
// Revision 1.5 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.4 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
`include "timescale.v"
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
);
parameter Tp = 1;
input MTxClk;
input MRxClk;
input TxReset;
input RxReset;
input [7:0] RxData;
input RxValid;
input RxStartFrm;
input RxEndFrm;
input RxFlow;
input ReceiveEnd;
input [47:0]MAC;
input DlyCrcEn;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmOut;
input ReceivedLengthOK;
input ReceivedPacketGood;
input TxUsedDataOutDetected;
input RxStatusWriteLatched_sync2;
input r_PassAll;
output Pause;
output ReceivedPauseFrm;
output AddressOK;
output SetPauseTimer;
reg Pause;
reg AddressOK; // Multicast or unicast address detected
reg TypeLengthOK; // Type/Length field contains 0x8808
reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
reg OpCodeOK; // PAUSE opcode detected (0x0001)
reg [2:0] DlyCrcCnt;
reg [4:0] ByteCnt;
reg [15:0] AssembledTimerValue;
reg [15:0] LatchedTimerValue;
reg ReceivedPauseFrm;
reg ReceivedPauseFrmWAddr;
reg PauseTimerEq0_sync1;
reg PauseTimerEq0_sync2;
reg [15:0] PauseTimer;
reg Divider2;
reg [5:0] SlotTimer;
wire [47:0] ReservedMulticast; // 0x0180C2000001
wire [15:0] TypeLength; // 0x8808
wire ResetByteCnt; //
wire IncrementByteCnt; //
wire ByteCntEq0; // ByteCnt = 0
wire ByteCntEq1; // ByteCnt = 1
wire ByteCntEq2; // ByteCnt = 2
wire ByteCntEq3; // ByteCnt = 3
wire ByteCntEq4; // ByteCnt = 4
wire ByteCntEq5; // ByteCnt = 5
wire ByteCntEq12; // ByteCnt = 12
wire ByteCntEq13; // ByteCnt = 13
wire ByteCntEq14; // ByteCnt = 14
wire ByteCntEq15; // ByteCnt = 15
wire ByteCntEq16; // ByteCnt = 16
wire ByteCntEq17; // ByteCnt = 17
wire ByteCntEq18; // ByteCnt = 18
wire DecrementPauseTimer; //
wire PauseTimerEq0; //
wire ResetSlotTimer; //
wire IncrementSlotTimer; //
wire SlotFinished; //
// Reserved multicast address and Type/Length for PAUSE control
assign ReservedMulticast = 48'h0180C2000001;
assign TypeLength = 16'h8808;
// Address Detection (Multicast or unicast)
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
AddressOK <= #Tp 1'b0;
else
if(DetectionWindow & ByteCntEq0)
AddressOK <= #Tp RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
else
if(DetectionWindow & ByteCntEq1)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
else
if(DetectionWindow & ByteCntEq2)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
else
if(DetectionWindow & ByteCntEq3)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
else
if(DetectionWindow & ByteCntEq4)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK;
else
if(DetectionWindow & ByteCntEq5)
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK;
else
if(ReceiveEnd)
AddressOK <= #Tp 1'b0;
end
// TypeLengthOK (Type/Length Control frame detected)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
TypeLengthOK <= #Tp 1'b0;
else
if(DetectionWindow & ByteCntEq12)
TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
else
if(DetectionWindow & ByteCntEq13)
TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
else
if(ReceiveEnd)
TypeLengthOK <= #Tp 1'b0;
end
// Latch Control Frame Opcode
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
OpCodeOK <= #Tp 1'b0;
else
if(ByteCntEq16)
OpCodeOK <= #Tp 1'b0;
else
begin
if(DetectionWindow & ByteCntEq14)
OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
if(DetectionWindow & ByteCntEq15)
OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
end
end
// ReceivedPauseFrmWAddr (+Address Check)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
ReceivedPauseFrmWAddr <= #Tp 1'b0;
else
if(ReceiveEnd)
ReceivedPauseFrmWAddr <= #Tp 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
ReceivedPauseFrmWAddr <= #Tp 1'b1;
end
// Assembling 16-bit timer value from two 8-bit data
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
AssembledTimerValue[15:0] <= #Tp 16'h0;
else
if(RxStartFrm)
AssembledTimerValue[15:0] <= #Tp 16'h0;
else
begin
if(DetectionWindow & ByteCntEq16)
AssembledTimerValue[15:8] <= #Tp RxData[7:0];
if(DetectionWindow & ByteCntEq17)
AssembledTimerValue[7:0] <= #Tp RxData[7:0];
end
end
// Detection window (while PAUSE detection is possible)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
DetectionWindow <= #Tp 1'b1;
else
if(ByteCntEq18)
DetectionWindow <= #Tp 1'b0;
else
if(ReceiveEnd)
DetectionWindow <= #Tp 1'b1;
end
// Latching Timer Value
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
LatchedTimerValue[15:0] <= #Tp 16'h0;
else
if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
else
if(ReceiveEnd)
LatchedTimerValue[15:0] <= #Tp 16'h0;
end
// Delayed CEC counter
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
DlyCrcCnt <= #Tp 3'h0;
else
if(RxValid & RxEndFrm)
DlyCrcCnt <= #Tp 3'h0;
else
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
// Byte counter
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ByteCnt[4:0] <= #Tp 5'h0;
else
if(ResetByteCnt)
ByteCnt[4:0] <= #Tp 5'h0;
else
if(IncrementByteCnt)
ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;
end
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
// PauseTimer[15:0]
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
PauseTimer[15:0] <= #Tp 16'h0;
else
if(SetPauseTimer)
PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];
else
if(DecrementPauseTimer)
PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;
end
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
// Synchronization of the pause timer
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
PauseTimerEq0_sync1 <= #Tp 1'b1;
PauseTimerEq0_sync2 <= #Tp 1'b1;
end
else
begin
PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;
PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;
end
end
// Pause signal generation
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
Pause <= #Tp 1'b0;
else
if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;
end
// Divider2 is used for incrementing the Slot timer every other clock
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
Divider2 <= #Tp 1'b0;
else
if(|PauseTimer[15:0] & RxFlow)
Divider2 <= #Tp ~Divider2;
else
Divider2 <= #Tp 1'b0;
end
assign ResetSlotTimer = RxReset;
assign IncrementSlotTimer = Pause & RxFlow & Divider2;
// SlotTimer
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
SlotTimer[5:0] <= #Tp 6'h0;
else
if(ResetSlotTimer)
SlotTimer[5:0] <= #Tp 6'h0;
else
if(IncrementSlotTimer)
SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;
end
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
// Pause Frame received
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ReceivedPauseFrm <=#Tp 1'b0;
else
if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
ReceivedPauseFrm <=#Tp 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
ReceivedPauseFrm <=#Tp 1'b1;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_register.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_register.v,v $
// Revision 1.6 2002/08/16 22:10:12 mohor
// Synchronous reset added.
//
// Revision 1.5 2002/08/16 12:33:27 mohor
// Parameter ResetValue changed to capital letters.
//
// Revision 1.4 2002/02/26 16:18:08 mohor
// Reset values are passed to registers through parameters
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
//
//
//
//
//
//
`include "timescale.v"
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] DataIn;
input Write;
input Clk;
input Reset;
input SyncReset;
output [WIDTH-1:0] DataOut;
reg [WIDTH-1:0] DataOut;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
DataOut<=#1 RESET_VALUE;
else
if(SyncReset)
DataOut<=#1 RESET_VALUE;
else
if(Write) // write
DataOut<=#1 DataIn;
end
endmodule // Register
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_registers.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_registers.v,v $
// Revision 1.29 2005/03/21 20:07:18 igorm
// Some small fixes + some troubles fixed.
//
// Revision 1.28 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.27 2004/04/26 11:42:17 igorm
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
//
// Revision 1.26 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.25 2003/04/18 16:26:25 mohor
// RxBDAddress was updated also when value to r_TxBDNum was written with
// greater value than allowed.
//
// Revision 1.24 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.23 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.22 2002/11/14 18:37:20 mohor
// r_Rst signal does not reset any module any more and is removed from the design.
//
// Revision 1.21 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.20 2002/09/04 18:40:25 mohor
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
// the control frames connected.
//
// Revision 1.19 2002/08/19 16:01:40 mohor
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
//
// Revision 1.18 2002/08/16 22:28:23 mohor
// Syntax error fixed.
//
// Revision 1.17 2002/08/16 22:23:03 mohor
// Syntax error fixed.
//
// Revision 1.16 2002/08/16 22:14:22 mohor
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
// changed from bit position 10 to 9.
//
// Revision 1.15 2002/08/14 18:26:37 mohor
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
//
// Revision 1.14 2002/04/22 14:03:44 mohor
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
// or not.
//
// Revision 1.13 2002/02/26 16:18:09 mohor
// Reset values are passed to registers through parameters
//
// Revision 1.12 2002/02/17 13:23:42 mohor
// Define missmatch fixed.
//
// Revision 1.11 2002/02/16 14:03:44 mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.10 2002/02/15 11:08:25 mohor
// File format fixed a bit.
//
// Revision 1.9 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.8 2002/02/12 17:01:19 mohor
// HASH0 and HASH1 registers added.
// Revision 1.7 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.6 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.5 2001/12/05 10:22:19 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.4 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
//
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
LinkFail, r_MAC, WCtrlDataStart, RStatStart,
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
StartTxDone, TxClk, RxClk, SetPauseTimer
);
parameter Tp = 1;
input [31:0] DataIn;
input [7:0] Address;
input Rw;
input [3:0] Cs;
input Clk;
input Reset;
input WCtrlDataStart;
input RStatStart;
input UpdateMIIRX_DATAReg;
input [15:0] Prsd;
output [31:0] DataOut;
reg [31:0] DataOut;
output r_RecSmall;
output r_Pad;
output r_HugEn;
output r_CrcEn;
output r_DlyCrcEn;
output r_FullD;
output r_ExDfrEn;
output r_NoBckof;
output r_LoopBck;
output r_IFG;
output r_Pro;
output r_Iam;
output r_Bro;
output r_NoPre;
output r_TxEn;
output r_RxEn;
output [31:0] r_HASH0;
output [31:0] r_HASH1;
input TxB_IRQ;
input TxE_IRQ;
input RxB_IRQ;
input RxE_IRQ;
input Busy_IRQ;
output [6:0] r_IPGT;
output [6:0] r_IPGR1;
output [6:0] r_IPGR2;
output [15:0] r_MinFL;
output [15:0] r_MaxFL;
output [3:0] r_MaxRet;
output [5:0] r_CollValid;
output r_TxFlow;
output r_RxFlow;
output r_PassAll;
output r_MiiNoPre;
output [7:0] r_ClkDiv;
output r_WCtrlData;
output r_RStat;
output r_ScanStat;
output [4:0] r_RGAD;
output [4:0] r_FIAD;
output [15:0]r_CtrlData;
input NValid_stat;
input Busy_stat;
input LinkFail;
output [47:0]r_MAC;
output [7:0] r_TxBDNum;
output int_o;
output [15:0]r_TxPauseTV;
output r_TxPauseRq;
input RstTxPauseRq;
input TxCtrlEndFrm;
input StartTxDone;
input TxClk;
input RxClk;
input SetPauseTimer;
reg irq_txb;
reg irq_txe;
reg irq_rxb;
reg irq_rxe;
reg irq_busy;
reg irq_txc;
reg irq_rxc;
reg SetTxCIrq_txclk;
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
reg SetTxCIrq;
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
reg SetRxCIrq_rxclk;
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
reg SetRxCIrq;
reg ResetRxCIrq_sync1;
reg ResetRxCIrq_sync2;
reg ResetRxCIrq_sync3;
wire [3:0] Write = Cs & {4{Rw}};
wire Read = (|Cs) & ~Rw;
wire MODER_Sel = (Address == `ETH_MODER_ADR );
wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR );
wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR );
wire IPGT_Sel = (Address == `ETH_IPGT_ADR );
wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR );
wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR );
wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR );
wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR );
wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR );
wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR );
wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR );
wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR );
wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR );
wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR );
wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR );
wire HASH0_Sel = (Address == `ETH_HASH0_ADR );
wire HASH1_Sel = (Address == `ETH_HASH1_ADR );
wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR );
wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR );
wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR );
wire [2:0] MODER_Wr;
wire [0:0] INT_SOURCE_Wr;
wire [0:0] INT_MASK_Wr;
wire [0:0] IPGT_Wr;
wire [0:0] IPGR1_Wr;
wire [0:0] IPGR2_Wr;
wire [3:0] PACKETLEN_Wr;
wire [2:0] COLLCONF_Wr;
wire [0:0] CTRLMODER_Wr;
wire [1:0] MIIMODER_Wr;
wire [0:0] MIICOMMAND_Wr;
wire [1:0] MIIADDRESS_Wr;
wire [1:0] MIITX_DATA_Wr;
wire MIIRX_DATA_Wr;
wire [3:0] MAC_ADDR0_Wr;
wire [1:0] MAC_ADDR1_Wr;
wire [3:0] HASH0_Wr;
wire [3:0] HASH1_Wr;
wire [2:0] TXCTRL_Wr;
wire [0:0] TX_BD_NUM_Wr;
assign MODER_Wr[0] = Write[0] & MODER_Sel;
assign MODER_Wr[1] = Write[1] & MODER_Sel;
assign MODER_Wr[2] = Write[2] & MODER_Sel;
assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel;
assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel;
assign IPGT_Wr[0] = Write[0] & IPGT_Sel;
assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel;
assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel;
assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel;
assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel;
assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel;
assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel;
assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel;
assign COLLCONF_Wr[1] = 1'b0; // Not used
assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel;
assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel;
assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel;
assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel;
assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel;
assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel;
assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel;
assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel;
assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel;
assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel;
assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel;
assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel;
assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel;
assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel;
assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel;
assign HASH0_Wr[0] = Write[0] & HASH0_Sel;
assign HASH0_Wr[1] = Write[1] & HASH0_Sel;
assign HASH0_Wr[2] = Write[2] & HASH0_Sel;
assign HASH0_Wr[3] = Write[3] & HASH0_Sel;
assign HASH1_Wr[0] = Write[0] & HASH1_Sel;
assign HASH1_Wr[1] = Write[1] & HASH1_Sel;
assign HASH1_Wr[2] = Write[2] & HASH1_Sel;
assign HASH1_Wr[3] = Write[3] & HASH1_Sel;
assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel;
assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel;
assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
wire [31:0] MODEROut;
wire [31:0] INT_SOURCEOut;
wire [31:0] INT_MASKOut;
wire [31:0] IPGTOut;
wire [31:0] IPGR1Out;
wire [31:0] IPGR2Out;
wire [31:0] PACKETLENOut;
wire [31:0] COLLCONFOut;
wire [31:0] CTRLMODEROut;
wire [31:0] MIIMODEROut;
wire [31:0] MIICOMMANDOut;
wire [31:0] MIIADDRESSOut;
wire [31:0] MIITX_DATAOut;
wire [31:0] MIIRX_DATAOut;
wire [31:0] MIISTATUSOut;
wire [31:0] MAC_ADDR0Out;
wire [31:0] MAC_ADDR1Out;
wire [31:0] TX_BD_NUMOut;
wire [31:0] HASH0Out;
wire [31:0] HASH1Out;
wire [31:0] TXCTRLOut;
// MODER Register
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
(
.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
.Write (MODER_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1
(
.DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
.Write (MODER_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2
(
.DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
.Write (MODER_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
// INT_MASK Register
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0
(
.DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
.Write (INT_MASK_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
// IPGT Register
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0
(
.DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
.DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
.Write (IPGT_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
// IPGR1 Register
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0
(
.DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
.Write (IPGR1_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
// IPGR2 Register
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0
(
.DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
.Write (IPGR2_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
// PACKETLEN Register
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
.Write (PACKETLEN_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
.Write (PACKETLEN_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
.Write (PACKETLEN_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
.Write (PACKETLEN_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// COLLCONF Register
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0
(
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
.Write (COLLCONF_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2
(
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
.Write (COLLCONF_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
// TX_BD_NUM Register
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
(
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
.Write (TX_BD_NUM_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
// CTRLMODER Register
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0
(
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
.Write (CTRLMODER_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
// MIIMODER Register
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0
(
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
.Write (MIIMODER_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1
(
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
.Write (MIIMODER_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
// MIICOMMAND Register
eth_register #(1, 0) MIICOMMAND0
(
.DataIn (DataIn[0]),
.DataOut (MIICOMMANDOut[0]),
.Write (MIICOMMAND_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(1, 0) MIICOMMAND1
(
.DataIn (DataIn[1]),
.DataOut (MIICOMMANDOut[1]),
.Write (MIICOMMAND_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (RStatStart)
);
eth_register #(1, 0) MIICOMMAND2
(
.DataIn (DataIn[2]),
.DataOut (MIICOMMANDOut[2]),
.Write (MIICOMMAND_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (WCtrlDataStart)
);
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
// MIIADDRESSRegister
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
(
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
.Write (MIIADDRESS_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
(
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
.Write (MIIADDRESS_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
// MIITX_DATA Register
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
(
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
.Write (MIITX_DATA_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
(
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
.Write (MIITX_DATA_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
// MIIRX_DATA Register
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
(
.DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
.Write (MIIRX_DATA_Wr), // not written from WB
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
// MAC_ADDR0 Register
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
.Write (MAC_ADDR0_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
.Write (MAC_ADDR0_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
.Write (MAC_ADDR0_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
.Write (MAC_ADDR0_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// MAC_ADDR1 Register
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0
(
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
.Write (MAC_ADDR1_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1
(
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
.Write (MAC_ADDR1_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
// RXHASH0 Register
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
.Write (HASH0_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
.Write (HASH0_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
.Write (HASH0_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
.Write (HASH0_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// RXHASH1 Register
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
.Write (HASH1_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
.Write (HASH1_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
.Write (HASH1_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
.Write (HASH1_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// TXCTRL Register
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
.Write (TXCTRL_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
.Write (TXCTRL_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
.Write (TXCTRL_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (RstTxPauseRq)
);
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
// Reading data from registers
always @ (Address or Read or MODEROut or INT_SOURCEOut or
INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
HASH0Out or HASH1Out or TXCTRLOut
)
begin
if(Read) // read
begin
case(Address)
`ETH_MODER_ADR : DataOut<=MODEROut;
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
`ETH_IPGT_ADR : DataOut<=IPGTOut;
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
`ETH_HASH0_ADR : DataOut<=HASH0Out;
`ETH_HASH1_ADR : DataOut<=HASH1Out;
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
default: DataOut<=32'h0;
endcase
end
else
DataOut<=32'h0;
end
assign r_RecSmall = MODEROut[16];
assign r_Pad = MODEROut[15];
assign r_HugEn = MODEROut[14];
assign r_CrcEn = MODEROut[13];
assign r_DlyCrcEn = MODEROut[12];
// assign r_Rst = MODEROut[11]; This signal is not used any more
assign r_FullD = MODEROut[10];
assign r_ExDfrEn = MODEROut[9];
assign r_NoBckof = MODEROut[8];
assign r_LoopBck = MODEROut[7];
assign r_IFG = MODEROut[6];
assign r_Pro = MODEROut[5];
assign r_Iam = MODEROut[4];
assign r_Bro = MODEROut[3];
assign r_NoPre = MODEROut[2];
assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD.
assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD.
assign r_IPGT[6:0] = IPGTOut[6:0];
assign r_IPGR1[6:0] = IPGR1Out[6:0];
assign r_IPGR2[6:0] = IPGR2Out[6:0];
assign r_MinFL[15:0] = PACKETLENOut[31:16];
assign r_MaxFL[15:0] = PACKETLENOut[15:0];
assign r_MaxRet[3:0] = COLLCONFOut[19:16];
assign r_CollValid[5:0] = COLLCONFOut[5:0];
assign r_TxFlow = CTRLMODEROut[2];
assign r_RxFlow = CTRLMODEROut[1];
assign r_PassAll = CTRLMODEROut[0];
assign r_MiiNoPre = MIIMODEROut[8];
assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
assign r_WCtrlData = MIICOMMANDOut[2];
assign r_RStat = MIICOMMANDOut[1];
assign r_ScanStat = MIICOMMANDOut[0];
assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
assign MIISTATUSOut[2] = NValid_stat ;
assign MIISTATUSOut[1] = Busy_stat ;
assign MIISTATUSOut[0] = LinkFail ;
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
assign r_HASH1[31:0] = HASH1Out;
assign r_HASH0[31:0] = HASH0Out;
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
assign r_TxPauseTV[15:0] = TXCTRLOut[15:0];
assign r_TxPauseRq = TXCTRLOut[16];
// Synchronizing TxC Interrupt
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
SetTxCIrq_txclk <=#Tp 1'b0;
else
if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
SetTxCIrq_txclk <=#Tp 1'b1;
else
if(ResetTxCIrq_sync2)
SetTxCIrq_txclk <=#Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync1 <=#Tp 1'b0;
else
SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync2 <=#Tp 1'b0;
else
SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync3 <=#Tp 1'b0;
else
SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq <=#Tp 1'b0;
else
SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
end
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
ResetTxCIrq_sync1 <=#Tp 1'b0;
else
ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
end
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
ResetTxCIrq_sync2 <=#Tp 1'b0;
else
ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
end
// Synchronizing RxC Interrupt
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
SetRxCIrq_rxclk <=#Tp 1'b0;
else
if(SetPauseTimer & r_RxFlow)
SetRxCIrq_rxclk <=#Tp 1'b1;
else
if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
SetRxCIrq_rxclk <=#Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync1 <=#Tp 1'b0;
else
SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync2 <=#Tp 1'b0;
else
SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync3 <=#Tp 1'b0;
else
SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq <=#Tp 1'b0;
else
SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync1 <=#Tp 1'b0;
else
ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync2 <=#Tp 1'b0;
else
ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync3 <=#Tp 1'b0;
else
ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
end
// Interrupt generation
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txb <= 1'b0;
else
if(TxB_IRQ)
irq_txb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[0])
irq_txb <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txe <= 1'b0;
else
if(TxE_IRQ)
irq_txe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[1])
irq_txe <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxb <= 1'b0;
else
if(RxB_IRQ)
irq_rxb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[2])
irq_rxb <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxe <= 1'b0;
else
if(RxE_IRQ)
irq_rxe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[3])
irq_rxe <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_busy <= 1'b0;
else
if(Busy_IRQ)
irq_busy <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[4])
irq_busy <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txc <= 1'b0;
else
if(SetTxCIrq)
irq_txc <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[5])
irq_txc <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxc <= 1'b0;
else
if(SetRxCIrq)
irq_rxc <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[6])
irq_rxc <= #Tp 1'b0;
end
// Generating interrupt signal
assign int_o = irq_txb & INT_MASKOut[0] |
irq_txe & INT_MASKOut[1] |
irq_rxb & INT_MASKOut[2] |
irq_rxe & INT_MASKOut[3] |
irq_busy & INT_MASKOut[4] |
irq_txc & INT_MASKOut[5] |
irq_rxc & INT_MASKOut[6] ;
// For reading interrupt status
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxaddrcheck.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/cores/ethmac/ ////
//// ////
//// Author(s): ////
//// - Bill Dittenhofer ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxaddrcheck.v,v $
// Revision 1.9 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.8 2002/11/19 17:34:52 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.7 2002/09/04 18:41:06 mohor
// Bug when last byte of destination address was not checked fixed.
//
// Revision 1.6 2002/03/20 15:14:11 mohor
// When in promiscous mode some frames were not received correctly. Fixed.
//
// Revision 1.5 2002/03/02 21:06:32 mohor
// Log info was missing.
//
//
// Revision 1.1 2002/02/08 12:51:54 ditt
// Initial release of the ethernet addresscheck module.
//
//
//
//
//
`include "timescale.v"
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort, AddressMiss, PassAll,
ControlFrmAddressOK
);
parameter Tp = 1;
input MRxClk;
input Reset;
input [7:0] RxData;
input Broadcast;
input r_Bro;
input r_Pro;
input ByteCntEq2;
input ByteCntEq3;
input ByteCntEq4;
input ByteCntEq5;
input ByteCntEq6;
input ByteCntEq7;
input [31:0] HASH0;
input [31:0] HASH1;
input [5:0] CrcHash;
input CrcHashGood;
input Multicast;
input [47:0] MAC;
input [1:0] StateData;
input RxEndFrm;
input PassAll;
input ControlFrmAddressOK;
output RxAbort;
output AddressMiss;
wire BroadcastOK;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire RxAddressInvalid;
wire RxCheckEn;
wire HashBit;
wire [31:0] IntHash;
reg [7:0] ByteHash;
reg MulticastOK;
reg UnicastOK;
reg RxAbort;
reg AddressMiss;
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
assign BroadcastOK = Broadcast & ~r_Bro;
assign RxCheckEn = | StateData;
// Address Error Reported at end of address cycle
// RxAbort clears after one cycle
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbort <= #Tp 1'b0;
else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
RxAbort <= #Tp 1'b1;
else
RxAbort <= #Tp 1'b0;
end
// This ff holds the "Address Miss" information that is written to the RX BD status.
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
AddressMiss <= #Tp 1'b0;
else if(ByteCntEq7 & RxCheckEn)
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
MulticastOK <= #Tp 1'b0;
else if(RxEndFrm | RxAbort)
MulticastOK <= #Tp 1'b0;
else if(CrcHashGood & Multicast)
MulticastOK <= #Tp HashBit;
end
// Address Detection (unicast)
// start with ByteCntEq2 due to delay of addres from RxData
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
UnicastOK <= #Tp 1'b0;
else
if(RxCheckEn & ByteCntEq2)
UnicastOK <= #Tp RxData[7:0] == MAC[47:40];
else
if(RxCheckEn & ByteCntEq3)
UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq4)
UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq5)
UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq6)
UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq7)
UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0]) & UnicastOK;
else
if(RxEndFrm | RxAbort)
UnicastOK <= #Tp 1'b0;
end
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
always@(CrcHash or IntHash)
begin
case(CrcHash[4:3])
2'b00: ByteHash = IntHash[7:0];
2'b01: ByteHash = IntHash[15:8];
2'b10: ByteHash = IntHash[23:16];
2'b11: ByteHash = IntHash[31:24];
endcase
end
assign HashBit = ByteHash[CrcHash[2:0]];
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxcounters.v,v $
// Revision 1.6 2005/02/21 11:00:57 igorm
// Delayed CRC fixed.
//
// Revision 1.5 2002/02/15 11:13:29 mohor
// Format of the file changed a bit.
//
// Revision 1.4 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
//
`include "timescale.v"
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
);
parameter Tp = 1;
input MRxClk;
input Reset;
input MRxDV;
input StateSFD;
input [1:0] StateData;
input MRxDEqD;
input StateIdle;
input StateDrop;
input DlyCrcEn;
input StatePreamble;
input Transmitting;
input HugEn;
input [15:0] MaxFL;
input r_IFG;
output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
output [3:0] DlyCrcCnt; // Delayed CRC counter
output ByteCntEq0; // Byte counter = 0
output ByteCntEq1; // Byte counter = 1
output ByteCntEq2; // Byte counter = 2
output ByteCntEq3; // Byte counter = 3
output ByteCntEq4; // Byte counter = 4
output ByteCntEq5; // Byte counter = 5
output ByteCntEq6; // Byte counter = 6
output ByteCntEq7; // Byte counter = 7
output ByteCntGreat2; // Byte counter > 2
output ByteCntSmall7; // Byte counter < 7
output ByteCntMaxFrame; // Byte counter = MaxFL
output [15:0] ByteCntOut; // Byte counter
wire ResetByteCounter;
wire IncrementByteCounter;
wire ResetIFGCounter;
wire IncrementIFGCounter;
wire ByteCntMax;
reg [15:0] ByteCnt;
reg [3:0] DlyCrcCnt;
reg [4:0] IFGCounter;
wire [15:0] ByteCntDelayed;
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
(StatePreamble | StateSFD | StateIdle & ~Transmitting |
StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 16'h0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= #Tp 16'h0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign ByteCntDelayed = ByteCnt + 3'h4;
assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
assign ByteCntEq0 = ByteCnt == 16'h0;
assign ByteCntEq1 = ByteCnt == 16'h1;
assign ByteCntEq2 = ByteCnt == 16'h2;
assign ByteCntEq3 = ByteCnt == 16'h3;
assign ByteCntEq4 = ByteCnt == 16'h4;
assign ByteCntEq5 = ByteCnt == 16'h5;
assign ByteCntEq6 = ByteCnt == 16'h6;
assign ByteCntEq7 = ByteCnt == 16'h7;
assign ByteCntGreat2 = ByteCnt > 16'h2;
assign ByteCntSmall7 = ByteCnt < 16'h7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
IFGCounter[4:0] <= #Tp 5'h0;
else
begin
if(ResetIFGCounter)
IFGCounter[4:0] <= #Tp 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
end
end
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt[3:0] <= #Tp 4'h0;
else
begin
if(DlyCrcCnt[3:0] == 4'h9)
DlyCrcCnt[3:0] <= #Tp 4'h0;
else
if(DlyCrcEn & StateSFD)
DlyCrcCnt[3:0] <= #Tp 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxethmac.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxethmac.v,v $
// Revision 1.13 2005/02/21 12:48:07 igorm
// Warning fixes.
//
// Revision 1.12 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.11 2004/03/17 09:32:15 igorm
// Multicast detection fixed. Only the LSB of the first byte is checked.
//
// Revision 1.10 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.9 2002/11/19 17:35:35 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.8 2002/02/16 07:15:27 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.7 2002/02/15 13:44:28 mohor
// RxAbort is an output. No need to have is declared as wire.
//
// Revision 1.6 2002/02/15 11:17:48 mohor
// File format changed.
//
// Revision 1.5 2002/02/14 20:48:43 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
`include "timescale.v"
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
);
parameter Tp = 1;
input MRxClk;
input MRxDV;
input [3:0] MRxD;
input Transmitting;
input HugEn;
input DlyCrcEn;
input [15:0] MaxFL;
input r_IFG;
input Reset;
input [47:0] MAC; // Station Address
input r_Bro; // broadcast disable
input r_Pro; // promiscuous enable
input [31:0] r_HASH0; // lower 4 bytes Hash Table
input [31:0] r_HASH1; // upper 4 bytes Hash Table
input PassAll;
input ControlFrmAddressOK;
output [7:0] RxData;
output RxValid;
output RxStartFrm;
output RxEndFrm;
output [15:0] ByteCnt;
output ByteCntEq0;
output ByteCntGreat2;
output ByteCntMaxFrame;
output CrcError;
output StateIdle;
output StatePreamble;
output StateSFD;
output [1:0] StateData;
output RxAbort;
output AddressMiss;
reg [7:0] RxData;
reg RxValid;
reg RxStartFrm;
reg RxEndFrm;
reg Broadcast;
reg Multicast;
reg [5:0] CrcHash;
reg CrcHashGood;
reg DelayData;
reg [7:0] LatchedByte;
reg [7:0] RxData_d;
reg RxValid_d;
reg RxStartFrm_d;
reg RxEndFrm_d;
wire MRxDEqD;
wire MRxDEq5;
wire StateDrop;
wire ByteCntEq1;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire ByteCntEq6;
wire ByteCntEq7;
wire ByteCntSmall7;
wire [31:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire GenerateRxValid;
wire GenerateRxStartFrm;
wire GenerateRxEndFrm;
wire DribbleRxEndFrm;
wire [3:0] DlyCrcCnt;
wire IFGCounterEq24;
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
// Rx State Machine module
eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
.StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
.StateSFD(StateSFD), .StateDrop(StateDrop)
);
// Rx Counters module
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
.ByteCntOut(ByteCnt)
);
// Rx Address Check
eth_rxaddrcheck rxaddrcheck1
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0), .HASH1(r_HASH1),
.CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
);
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
// Connecting module Crc
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Latching CRC for use in the hash table
always @ (posedge MRxClk)
begin
CrcHashGood <= #Tp StateData[0] & ByteCntEq6;
end
always @ (posedge MRxClk)
begin
if(Reset | StateIdle)
CrcHash[5:0] <= #Tp 6'h0;
else
if(StateData[0] & ByteCntEq6)
CrcHash[5:0] <= #Tp Crc[31:26];
end
// Output byte stream
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxData_d[7:0] <= #Tp 8'h0;
DelayData <= #Tp 1'b0;
LatchedByte[7:0] <= #Tp 8'h0;
RxData[7:0] <= #Tp 8'h0;
end
else
begin
LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
DelayData <= #Tp StateData[0];
if(GenerateRxValid)
RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
else
if(~DelayData)
RxData_d[7:0] <= #Tp 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
RxData[7:0] <= #Tp RxData_d[7:0]; // Output data byte
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Broadcast <= #Tp 1'b0;
else
begin
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
Broadcast <= #Tp 1'b0;
else
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
Broadcast <= #Tp 1'b1;
else
if(RxAbort | RxEndFrm)
Broadcast <= #Tp 1'b0;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Multicast <= #Tp 1'b0;
else
begin
if(StateData[0] & ByteCntEq1 & LatchedByte[0])
Multicast <= #Tp 1'b1;
else if(RxAbort | RxEndFrm)
Multicast <= #Tp 1'b0;
end
end
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid_d <= #Tp 1'b0;
RxValid <= #Tp 1'b0;
end
else
begin
RxValid_d <= #Tp GenerateRxValid;
RxValid <= #Tp RxValid_d;
end
end
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStartFrm_d <= #Tp 1'b0;
RxStartFrm <= #Tp 1'b0;
end
else
begin
RxStartFrm_d <= #Tp GenerateRxStartFrm;
RxStartFrm <= #Tp RxStartFrm_d;
end
end
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxEndFrm_d <= #Tp 1'b0;
RxEndFrm <= #Tp 1'b0;
end
else
begin
RxEndFrm_d <= #Tp GenerateRxEndFrm;
RxEndFrm <= #Tp RxEndFrm_d | DribbleRxEndFrm;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxstatem.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxstatem.v,v $
// Revision 1.6 2002/11/13 22:28:26 tadejm
// StartIdle state changed (not important the size of the packet).
// StartData1 activates only while ByteCnt is smaller than the MaxFrame.
//
// Revision 1.5 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.4 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.2 2001/07/03 12:55:41 mohor
// Minor changes because of the synthesys warnings.
//
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
`include "timescale.v"
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
StateDrop
);
parameter Tp = 1;
input MRxClk;
input Reset;
input MRxDV;
input ByteCntEq0;
input ByteCntGreat2;
input MRxDEq5;
input Transmitting;
input MRxDEqD;
input IFGCounterEq24;
input ByteCntMaxFrame;
output [1:0] StateData;
output StateIdle;
output StateDrop;
output StatePreamble;
output StateSFD;
reg StateData0;
reg StateData1;
reg StateIdle;
reg StateDrop;
reg StatePreamble;
reg StateSFD;
wire StartIdle;
wire StartDrop;
wire StartData0;
wire StartData1;
wire StartPreamble;
wire StartSFD;
// Defining the next state
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
| StateData0 & ByteCntMaxFrame
);
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= #Tp 1'b0;
StateDrop <= #Tp 1'b1;
StatePreamble <= #Tp 1'b0;
StateSFD <= #Tp 1'b0;
StateData0 <= #Tp 1'b0;
StateData1 <= #Tp 1'b0;
end
else
begin
if(StartPreamble | StartSFD | StartDrop)
StateIdle <= #Tp 1'b0;
else
if(StartIdle)
StateIdle <= #Tp 1'b1;
if(StartIdle)
StateDrop <= #Tp 1'b0;
else
if(StartDrop)
StateDrop <= #Tp 1'b1;
if(StartSFD | StartIdle | StartDrop)
StatePreamble <= #Tp 1'b0;
else
if(StartPreamble)
StatePreamble <= #Tp 1'b1;
if(StartPreamble | StartIdle | StartData0 | StartDrop)
StateSFD <= #Tp 1'b0;
else
if(StartSFD)
StateSFD <= #Tp 1'b1;
if(StartIdle | StartData1 | StartDrop)
StateData0 <= #Tp 1'b0;
else
if(StartData0)
StateData0 <= #Tp 1'b1;
if(StartIdle | StartData0 | StartDrop)
StateData1 <= #Tp 1'b0;
else
if(StartData1)
StateData1 <= #Tp 1'b1;
end
end
assign StateData[1:0] = {StateData1, StateData0};
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_shiftreg.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_shiftreg.v,v $
// Revision 1.6 2005/03/08 14:45:09 igorm
// Case statement improved for synthesys.
//
// Revision 1.5 2002/08/14 18:16:59 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.4 2002/03/02 21:06:01 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
LatchByte, ShiftedBit, Prsd, LinkFail);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
input Mdi; // MII input data
input [4:0] Fiad; // PHY address
input [4:0] Rgad; // Register address (within the selected PHY)
input [15:0]CtrlData; // Control data (data to be written to the PHY)
input WriteOp; // The current operation is a PHY register write operation
input [3:0] ByteSelect; // Byte select
input [1:0] LatchByte; // Byte select for latching (read operation)
output ShiftedBit; // Bit shifted out of the shift register
output[15:0]Prsd; // Read Status Data (data read from the PHY)
output LinkFail; // Link Integrity Signal
reg [7:0] ShiftReg; // Shift register for shifting the data in and out
reg [15:0]Prsd;
reg LinkFail;
// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
ShiftReg[7:0] <= #Tp 8'h0;
Prsd[15:0] <= #Tp 16'h0;
LinkFail <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
if(|ByteSelect)
begin
case (ByteSelect[3:0]) // synopsys parallel_case full_case
4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
endcase
end
else
begin
ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(LatchByte[0])
begin
Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(Rgad == 5'h01)
LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
end
else
begin
if(LatchByte[1])
Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
end
end
end
end
end
assign ShiftedBit = ShiftReg[7];
endmodule
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