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2.1M
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module bug();
reg [9:0] i;
reg [7:0] j;
initial begin
i = 10\'h3ff;
j = (i / 4) & 8\'hfe;
$display("\'h%h", j);
end
endmodule
|
// Check that dynamic arrays with compatible packed base types can be passed as
// task arguments. Even it the element types are not identical.
module test;
typedef logic [31:0] T[];
task t1(logic [31:0] d[]);
d[0] = 1;
endtask
task t2(logic [7:0][3:0] d[]);
d[0] = 1;
endtask
task t3([31:0] d[]);
d[0] = 1;
endtask
task t4(T d);
d[0] = 1;
endtask
// For two packed types to be compatible they need to have the same packed
// width, both be 2-state or 4-state and both be either signed or unsigned.
logic [31:0] d1[];
logic [7:0][3:0] d2[];
initial begin
d1 = new[1];
d2 = new[1];
t1(d1);
t1(d2);
t2(d1);
t2(d2);
t3(d1);
t3(d2);
t4(d1);
t4(d2);
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 1999 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
primitive BUFG ( O, I );
output O;
input I;
table
0 : 0 ;
1 : 1 ;
endtable
endprimitive
module main;
wire out;
reg in;
BUFG #5 bg(out, in);
initial begin
in = 0;
#10 if (out !== 0) begin
\t $display("FAILED -- %b != 0", out);
\t $finish;
end
in = 1;
#4 if (out !== 0) begin
\t $display("FAILED -- %b != 0", out);
\t $finish;
end
#2 if (out !== 1) begin
\t $display("FAILED -- %b != 1", out);
\t $finish;
end
$display("PASSED");
end
endmodule
|
module dut(input EN, input DIR, inout A, inout B);
assign A = EN && DIR == 0 ? B : 1\'bz;
assign B = EN && DIR == 1 ? A : 1\'bz;
specify
(A => B) = (2);
(B => A) = (3);
(EN => A) = (4);
(EN => B) = (4);
endspecify
endmodule
module test();
wire EN1;
wire EN2;
wire I1;
wire I2;
tri O;
pulldown(O);
dut dut1(EN1, 1\'b1, I1, O);
dut dut2(EN2, 1\'b0, O, I2);
reg failed = 0;
initial begin
$monitor($time,,EN1,,I1,,EN2,,I2,,O);
force EN1 = 0;
force EN2 = 0;
#4;
#0 if (O !== 0) failed = 1;
force I1 = 1;
force I2 = 1;
#1;
force EN1 = 1;
#3;
#0 if (O !== 0) failed = 1;
#1;
#0 if (O !== 1) failed = 1;
force I1 = 0;
#1;
#0 if (O !== 1) failed = 1;
#1;
#0 if (O !== 0) failed = 1;
force EN1 = 0;
force EN2 = 1;
#3;
#0 if (O !== 0) failed = 1;
#1;
#0 if (O !== 1) failed = 1;
force I2 = 0;
#2;
#0 if (O !== 1) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
module br987_test;
logic clk, trig, data_o;
bug5 dut(clk, trig, data_o);
initial begin
trig = 1;
clk = 0;
#1 clk = ~clk;
#1 clk = ~clk;
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate release statement
//
// D: This code verifies the release statement.
// D: It depends on the force statement being
// D: functional! (Kinda have to - no way to
// D: release if you haven\'t forced the issue.
// D: It is intended to be self checking.
//
// By: Steve Wilson
//
module main ();
reg working;
reg timer;
initial
working = 1;
initial
begin
#5 ;
force working = 0;
end
initial
begin
#10;
release working;\t// This releases the force
#2 ;
working = 1;\t// This allows a new value onto the reg.
end
initial
begin
#20;
if(!working)
$display("FAILED\
");
else
$display("PASSED\
");
end
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main ();
initial
begin
\t$display("%0d (should be -1)", -1);
end
endmodule
|
//
// Copyright (c) 1999 Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
wire [3:0] a,b,c;
assign a=4\'d5, b=4\'d8, c=4\'d12;
initial begin
#1;
if (a===4\'d5 && b===4\'d8 && c==4\'d12)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module bug();
localparam integer a = 1;
integer b = 2;
initial begin
if (a == b)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* This tests a trivial class. This tests that simple user defined
* constructors work.
*/
program main;
// Trivial examples of classes.
class foo_t ;
int value;
function new();
\t value = 42;
endfunction // new
endclass : foo_t // foo_t
class bar_t ;
int value;
function new (int init);
\tvalue = init;
endfunction // new
endclass : bar_t // foo_t
foo_t obj1;
bar_t obj2;
initial begin
obj1 = new;
if (obj1.value !== 42) begin
\t $display("FAILED -- Default constructor left value=%0d.", obj1.value);
\t $finish;
end
obj2 = new(53);
if (obj2.value !== 53) begin
\t $display("FAILED -- new(53) constructure left value=%0d.", obj2.value);
\t $finish;
end
$display("PASSED");
$finish;
end
endprogram // main
|
module addN
#(parameter WID = 4)
(input wire [WID-1:0] A,
input wire [WID-1:0] B,
output wire [WID:0] Q
/* */);
assign Q = A + B;
endmodule // add
|
module top;
reg pass = 1\'b1;
reg in;
wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2;
initial begin
// $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);
if (bf1 !== 1\'bx && bf2 !== 1\'bx) begin
$display("Buffer failed, expected 2\'bxx, got %b%b", bf1, bf2);
pass = 1\'b0;
end
if (nt1 !== 1\'bx && nt2 !== 1\'bx) begin
$display("Inverter (not) failed, expected 2\'bxx, got %b%b", nt1, nt2);
pass = 1\'b0;
end
if (pd1 !== 1\'b0 && pd2 !== 1\'b0) begin
$display("Pull down failed, expected 2\'b00, got %b%b", pd1, pd2);
pass = 1\'b0;
end
if (pu1 !== 1\'b1 && pu2 !== 1\'b1) begin
$display("Pull up failed, expected 2\'b11, got %b%b", pu1, pu2);
pass = 1\'b0;
end
in = 1\'b0;
#1;
if (bf1 !== 1\'b0 && bf2 !== 1\'b0) begin
$display("Buffer failed, expected 2\'b00, got %b%b", bf1, bf2);
pass = 1\'b0;
end
if (nt1 !== 1\'b1 && nt2 !== 1\'b1) begin
$display("Inverter (not) failed, expected 2\'b11, got %b%b", nt1, nt2);
pass = 1\'b0;
end
if (pd1 !== 1\'b0 && pd2 !== 1\'b0) begin
$display("Pull down failed, expected 2\'b00, got %b%b", pd1, pd2);
pass = 1\'b0;
end
if (pu1 !== 1\'b1 && pu2 !== 1\'b1) begin
$display("Pull up failed, expected 2\'b11, got %b%b", pu1, pu2);
pass = 1\'b0;
end
in = 1\'b1;
#1;
if (bf1 !== 1\'b1 && bf2 !== 1\'b1) begin
$display("Buffer failed, expected 2\'b11, got %b%b", bf1, bf2);
pass = 1\'b0;
end
if (nt1 !== 1\'b0 && nt2 !== 1\'b0) begin
$display("Inverter (not) failed, expected 2\'b00, got %b%b", nt1, nt2);
pass = 1\'b0;
end
if (pd1 !== 1\'b0 && pd2 !== 1\'b0) begin
$display("Pull down failed, expected 2\'b00, got %b%b", pd1, pd2);
pass = 1\'b0;
end
if (pu1 !== 1\'b1 && pu2 !== 1\'b1) begin
$display("Pull up failed, expected 2\'b11, got %b%b", pu1, pu2);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
buf (bf1, bf2, in);
not (nt1, nt2, in);
pulldown (pd1, pd2);
pullup (pu1, pu2);
endmodule
|
// Check that the class new initializer can be used for all sorts for variable
// declarations
package P;
class C;
endclass
C c = new;
endpackage
module test;
class C;
task check;
$display("PASSED");
endtask
endclass
class D;
C c = new;
endclass
C c = new;
initial begin
static C c = new;
c.check();
end
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test is intended to be run with ``iverilog -S foo.v\'\',
* and tests the situation addressed by pr#519.
*/
module main;
reg [3:0] a, b, c, t;
(* ivl_combinational *)
always @(a, b) begin
t = a + b;
c = 4\'d1 + ~t;
end
(* ivl_synthesis_off *)
initial begin
a = 1;
for (b = 0 ; b < 4\'hf ; b = b + 1) begin
\t#1 if (c !== -(a + b)) begin
\t $display("FAILED -- a=%b, b=%b, t=%b, c=%b", a, b, t, c);
\t $finish;
\tend
end
$display("PASSED");
end // initial begin
endmodule
|
/* pr1612693.v */
module test ();
reg [9:0] col;
wire [9:0] xsize;
// The setup for this expression caused an assertion at run time
// according to pr1612693.
wire vschg = (col == (xsize>>1));
initial begin
#1 $display("PASSED");
end
endmodule
|
// Check that it is possible to reference a package scoped type identifier in an
// expression.
bit failed = 1\'b0;
`define check(expr, val) \\
if (expr !== val) begin \\
$display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \\
failed = 1\'b1; \\
end
package P;
typedef integer T;
endpackage
module test;
initial begin
`check($bits(P::T), $bits(integer))
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module test_mux
(input wire [1:0] D0, D1,
input wire [1:0] S,
output reg [1:0] Q);
always @(*) begin
case (S)
\t2'b00: Q = D0;
\t2'b01: Q = D1;
\tdefault: Q = 0;
endcase // case (S)
end
endmodule // test_mux
|
/*
* Generate a combinational adder of any width. The width parameter can
* be any integer value >0. The A and B inputs have WID bits, and the Q
* output has WID+1 bits to include the overflow.
*/
module addN
#(parameter WID = 4)
(input wire [WID-1:0] A,
input wire [WID-1:0] B,
output wire [WID:0] Q
/* */);
wire [WID-1:0]\tCout;
/* The least significant slice has no Cin */
add1 U0 (.A(A[0]), .B(B[0]), .Cin(1'b0), .Q(Q[0]), .Cout(Cout[0]));
/* Generate all the remaining slices */
genvar i;
for (i = 1 ; i < WID ; i = i+1) begin : U
add1 Un (.A(A[i]), .B(B[i]), .Cin(Cout[i-1]), .Q(Q[i]), .Cout(Cout[i]));
end
assign Q[WID] = Cout[WID-1];
endmodule // add
/*
* This is a single-bit combinational adder used by the addH module
* above.
*/
module add1(input A, input B, input Cin, output reg Q, output reg Cout);
always @* begin
Q = A ^ B ^ Cin;
Cout = A&B | A&Cin | B&Cin;
end
endmodule // hadd
|
module test ();
parameter p = 0;
reg dummy;
initial dummy = block.f(0);
generate case(1)
p==0:
begin : block
function f;
input i;
begin
$display("p == 0: %0s", p==0?"OK":"FAILED");
\t if (! (p==0)) $finish;
end
endfunction
end
default:
begin : block
function f;
input i;
begin
$display("default: %0s", p!=0?"OK":"FAILED");
\t if (p==0) $finish;
end
endfunction
end
endcase
endgenerate
endmodule
module top ();
test #(0) a();
test #(1) b();
initial #1 $display("PASSED");
endmodule
|
// Check that declaring multiple non-ANSI module ports with an implicit type and
// the same name is an error. Even if the signal was previously declared as a
// net.
module test(x);
wire x;
input x;
input x;
endmodule
|
module main;
reg [7:0] val;
initial begin
val = 120;
if (8\'d5 < val) begin
\t $display("OK");
end else begin
\t $display("FAILED");
\t $finish;
end
if (8\'d5 <= val) begin
\t $display("OK");
end else begin
\t $display("FAILED");
\t $finish;
end
if (8\'d121 > val) begin
\t $display("OK");
end else begin
\t $display("FAILED");
\t $finish;
end
if (8\'d121 >= val) begin
\t $display("OK");
end else begin
\t $display("FAILED");
\t $finish;
end
if (val > 8\'d5) begin
\t $display("OK");
end else begin
\t $display("FAILED");
\t $finish;
end
if (val >= 8\'d5) begin
\t $display("OK");
end else begin
\t $display("FAILED");
\t $finish;
end
if (val < 8\'d121) begin
\t $display("OK");
end else begin
\t $display("FAILED");
\t $finish;
end
if (val <= 8\'d121) begin
\t $display("OK");
end else begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// This test is mostly to make sure valgrind cleans up correctly.
`timescale 1ns/1ns
module top;
wire real rtm;
wire [31:0] res1, res2;
integer a = 10;
assign #1 rtm = $realtime;
assign #1 res1 = $clog2(a);
lwr dut(res2, a);
initial begin
$monitor($realtime,, rtm, res1,, res2,, a);
#5 a = 20;
end
endmodule
module lwr(out, in);
output [31:0] out;
input [31:0] in;
wire [31:0] out, in;
assign out = $clog2(in);
specify
(in => out) = (1, 1);
endspecify
endmodule
|
module top;
// The array code does not currently work because we need &APV<>!
// Both &PV<> and &APV<> (when implemented) need to have bit
// specific value change callbacks to function correctly.
reg [7:0] array [1:0];
reg [7:0] bs, ps;
integer idx;
initial begin
bs = 8\'b0;
ps = 8\'b0;
array[0] = 8\'b0;
$monitor($time," BS = ", bs[1], ", PS = ", ps[2:1], ", AR = ", array[0][1]);
// This should only trigger the $monitor when bit 1 changes.
for (idx = 0; idx < 8 ; idx = idx + 1) begin
#1 bs[idx] = 1\'b1;
end
// This should only trigger the $monitor when bit 1 or 2 changes.
for (idx = 0; idx < 8 ; idx = idx + 1) begin
#1 ps[idx] = 1\'b1;
end
// This should only trigger the $monitor when bit 1 of array[0] changes..
for (idx = 0; idx < 8 ; idx = idx + 1) begin
#1 array[0][idx] = 1\'b1;
end
end
endmodule
|
module main;
function [15:0] sum;
input [15:0] a;
input [15:0] b;
sum = a + b;
endfunction // sum
reg\t\t clk;
reg [15:0]\t d, e, out;
(* ivl_synthesis_on *)
always @(posedge clk)
out <= sum(d, e);
initial begin
clk = 0;
d = 0;
e = 0;
#1 clk = 1;
#1 clk = 0;
if (out !== 16\'d0) begin
\t $display("FAILED -- sum(%0d,%d) --> %0d", d, e, out);
\t $finish;
end
d = 5;
e = 13;
#1 clk = 1;
#1 clk = 0;
if (out !== 16\'d18) begin
\t $display("FAILED -- sum(%0d,%d) --> %0d", d, e, out);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
module top;
reg pass;
reg in;
wire out, outb;
lower_cell dutb(outb, in);
lower_no_cell dut(out, in);
always @(outb) begin
if (outb !== ~in) begin
$display("FAILED outb at time %t, expected %b, got %b", $time, ~in, outb);
pass = 1\'b0;
end
end
always @(out) begin
if (out !== in) begin
$display("FAILED out at time %t, expected %b, got %b", $time, in, out);
pass = 1\'b0;
end
end
initial begin
pass = 1\'b1;
#1 in = 1\'b0;
#1 in = 1\'b1;
#1 in = 1\'b0;
#1 if (pass) $display("Verilog checking was OK.");
$is_cell(dut);
$is_cell(dutb);
end
endmodule
`celldefine
module lower_cell(output out, input in);
not(out, in);
endmodule
`endcelldefine
module lower_no_cell(output out, input in);
buf(out, in);
endmodule
|
module test();
parameter N_CH = 1;
reg pass = 1\'b1;
reg clk;
reg [31:0] data[0: N_CH-1];
generate
genvar i;
for (i=0; i<N_CH; i = i + 1)
begin: sdac
always @ (posedge clk)
data[i] <= 32\'h0;
end
endgenerate
initial
begin
clk = 0;
if (data[0] != 32\'bx) begin
$display("FAILED: initial value, expected 32\'bx, got %b", data[0]);
pass = 1\'b0;
end
#26 // Check after the first clock edge.
if (data[0] != 32\'b0) begin
$display("FAILED: final value, expected 32\'b0, got %b", data[0]);
pass = 1\'b0;
end
if (pass) $display("PASSED");
$finish;
end
always #25 clk = ~clk;
endmodule // test
|
module recursive_task();
task automatic factorial;
input integer n;
output integer f;
integer t;
fork
begin
if (n > 1)
factorial(n - 1, t);
else
t = 1;
#1 f = n * t;
end
begin
@f $display("intermediate value = %0d", f);
end
join
endtask
integer r1;
integer r2;
integer r3;
initial begin
fork
factorial(3, r1);
factorial(4, r2);
factorial(5, r3);
join
$display("factorial 3 = %0d", r1);
$display("factorial 4 = %0d", r2);
$display("factorial 5 = %0d", r3);
end
endmodule
|
// This tests the basic support for default arguments to task/function
// ports. The default port syntax gives SystemVerilog a limited form
// of variable argument lists.
program main;
class foo_t;
int int_val;
logic[3:0] log_val;
string text_val;
task init (int int_init, logic[3:0]log_init = 4\'bzzzz, string text_init = "default text");
\t this.init2(int_init, log_init, text_init);
endtask : init
task init2 (int int_init, logic[3:0]log_init, string text_init);
\t int_val = int_init;
\t log_val = log_init;
\t text_val = text_init;
endtask : init2
endclass : foo_t
foo_t obj1;
initial begin
obj1 = new;
obj1.init(4, 4\'b0101, "new text");
if (obj1.int_val != 4 || obj1.log_val !== 4\'b0101 || obj1.text_val != "new text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val);
\t $finish;
end
obj1 = new;
obj1.init(5, , "new text");
if (obj1.int_val != 5 || obj1.log_val !== 4\'bzzzz || obj1.text_val != "new text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val);
\t $finish;
end
obj1 = new;
obj1.init(6, 4\'b1010);
if (obj1.int_val != 6 || obj1.log_val !== 4\'b1010 || obj1.text_val != "default text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val);
\t $finish;
end
obj1 = new;
obj1.init(7);
if (obj1.int_val != 7 || obj1.text_val != "default text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val);
\t $finish;
end
$display("PASSED");
end
endprogram // main
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test was derived from PR615.v
**/
module main();
parameter INIT_00 = 32\'hffffffff;
reg [4:0] c;
initial begin
c = 0;
$display("%b",INIT_00[c]);
if (INIT_00[c] !== 1\'b1) begin
$display("FAILED");
$finish;
end
c = 1;
$display("%b",INIT_00[c]);
if (INIT_00[c] !== 1\'b1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
module test ();
parameter fuse_a_msb = 4;
parameter fuse_q_msb = (2**(fuse_a_msb+1))-1;
initial begin
if (fuse_q_msb != \'h1f) begin
\t $display("FAILED -- fuse_q_msb = %d", fuse_q_msb);
\t $finish;
end
$display("PASSED");
end
endmodule
|
module top;
parameter parm = 1;
parameter name0_s = 1; // signal
wire [1:0] out;
/***********
* Check signals
***********/
// Check signal/parameter name issues.
wire name0_s;
// Check signal/genvar name issues.
genvar name0_v;
generate
for (name0_v = 0; name0_v < 2; name0_v = name0_v + 1) begin
assign out[name0_v] = name0_v;
end
endgenerate
wire name0_v;
// Check signal/task name issues.
task name1_st;
$display("FAILED in task name1_st");
endtask
wire name1_st;
// Check signal/function name issues.
function name2_sf;
input in;
name2_sf = in;
endfunction
wire name2_sf;
// Check signal/module instance name issues.
test name3_si(out[0]);
wire name3_si;
// Check signal/named block name issues.
initial begin: name4_sb
$display("FAILED in name4_sb");
end
wire name4_sb;
// Check signal/named event name issues.
event name5_se;
wire name5_se;
// Check signal/generate loop name issues.
genvar i;
generate
for (i = 0; i < 2 ; i = i + 1) begin: name6_sgl
assign out[i] = i;
end
endgenerate
wire name6_sgl;
// Check signal/generate if name issues.
generate
if (parm == 1) begin: name7_sgi
assign out[1] = 1;
end
endgenerate
wire name7_sgi;
// Check signal/generate case name issues.
generate
case (parm)
1: begin: name8_sgc
assign out[1] = 1;
end
default: begin: name8_sgc
assign out[1] = 0;
end
endcase
endgenerate
wire name8_sgc;
// Check signal/generate block name issues.
generate
begin: name9_sgb
assign out[0] = 0;
end
endgenerate
wire name9_sgb;
initial $display("FAILED");
endmodule
module test(out);
output out;
reg out = 1\'b0;
endmodule
|
module top;
reg pass;
time change;
reg in;
wire c1, c2a, c2b, c3;
wire v1, v2, v3;
const_1 d_c1(c1, in);
const_2a d_c2a(c2a, in);
const_2b d_c2b(c2b, in);
const_3 d_c3(c3, in);
var_1 d_v1(v1, in);
// var_2 d_v2(v2, in);
var_3 d_v3(v2, in);
initial begin
pass = 1\'b1;
#1000 in = 1\'b0;
#1000 in = 1\'b1;
#1000 in = 1\'b0;
#1000 in = 1\'b1;
#1000 in = 1\'bx;
#1000 in = 1\'b0;
#1000 in = 1\'bx;
#1000 in = 1\'b1;
#1000 in = 1\'b0;
#1000 if (pass) $display("PASSED");
end
always @(in) change = $time;
endmodule
// All delays should be 200.
module const_1 (output out, input in);
assign #(200) out = (in === 1\'bx) ? 1\'bz : ~in;
always @(out) begin
case (out)
1\'b0: if ($time - top.change != 200) begin
$display("Failed const_1 fall");
top.pass = 1\'b0;
end
1\'b1: if ($time - top.change != 200) begin
$display("Failed const_1 rise");
top.pass = 1\'b0;
end
1\'bz: if ($time - top.change != 200) begin
$display("Failed const_1 high-Z");
top.pass = 1\'b0;
end
default: begin
$display("FAILED const_1 default");
top.pass = 1\'b0;
end
endcase
end
endmodule
// Decay should also be 100.
module const_2a (output out, input in);
assign #(200, 100) out = (in === 1\'bx) ? 1\'bz : ~in;
always @(out) begin
case (out)
1\'b0: if ($time - top.change != 100) begin
$display("Failed const_2a fall");
top.pass = 1\'b0;
end
1\'b1: if ($time - top.change != 200) begin
$display("Failed const_2a rise");
top.pass = 1\'b0;
end
1\'bz: if ($time - top.change != 100) begin
$display("Failed const_2a high-Z");
top.pass = 1\'b0;
end
default: begin
$display("FAILED const_2a default");
top.pass = 1\'b0;
end
endcase
end
endmodule
// Decay should also be 100.
module const_2b (output out, input in);
assign #(100, 200) out = (in === 1\'bx) ? 1\'bz : ~in;
always @(out) begin
case (out)
1\'b0: if ($time - top.change != 200) begin
$display("Failed const_2b fall");
top.pass = 1\'b0;
end
1\'b1: if ($time - top.change != 100) begin
$display("Failed const_2b rise");
top.pass = 1\'b0;
end
1\'bz: if ($time - top.change != 100) begin
$display("Failed const_2b high-Z");
top.pass = 1\'b0;
end
default: begin
$display("FAILED const_2b default");
top.pass = 1\'b0;
end
endcase
end
endmodule
// All delays as given.
module const_3 (output out, input in);
assign #(100, 200, 300) out = (in === 1\'bx) ? 1\'bz : ~in;
always @(out) begin
case (out)
1\'b0: if ($time - top.change != 200) begin
$display("Failed const_3 fall");
top.pass = 1\'b0;
end
1\'b1: if ($time - top.change != 100) begin
$display("Failed const_3 rise");
top.pass = 1\'b0;
end
1\'bz: if ($time - top.change != 300) begin
$display("Failed const_3 high-Z");
top.pass = 1\'b0;
end
default: begin
$display("FAILED const_3 default");
top.pass = 1\'b0;
end
endcase
end
endmodule
// All delays should be delay.
module var_1 (output out, input in);
time delay = 200;
assign #(delay) out = (in === 1\'bx) ? 1\'bz : ~in;
always @(out) begin
case (out)
1\'b0: if ($time - top.change != delay) begin
$display("Failed var_1 fall");
top.pass = 1\'b0;
end
1\'b1: if ($time - top.change != delay) begin
$display("Failed var_1 rise");
top.pass = 1\'b0;
end
1\'bz: if ($time - top.change != delay) begin
$display("Failed var_1 high-Z");
top.pass = 1\'b0;
end
default: begin
$display("FAILED var_1 default");
top.pass = 1\'b0;
end
endcase
end
endmodule
/*
* We do not currently support calculating the decay time from the
* variable rise and fall times. The compiler will print a message
* and assert in the code generator.
*
* We need an a and b version to check both ways.
*
// Decay should be the minimum of rise and fall delay.
module var_2 (output out, input in);
time delayr = 100;
time delayf = 200;
assign #(delayr, delayf) out = ~in;
function automatic real min_real(real a, real b);
min_real = a < b ? a : b;
endfunction
always @(out) begin
case (out)
1\'b0: if ($time - top.change != delayf) begin
$display("Failed var_2 fall");
top.pass = 1\'b0;
end
1\'b1: if ($time - top.change != delayr) begin
$display("Failed var_2 rise");
top.pass = 1\'b0;
end
1\'bz: if ($time - top.change != min_real(delayf, delayr)) begin
$display("Failed var_2 high-Z");
top.pass = 1\'b0;
end
default: begin
$display("FAILED var_2 default");
top.pass = 1\'b0;
end
endcase
end
endmodule
*/
// All delays as given.
module var_3 (output out, input in);
time delayr = 100;
time delayf = 200;
time delayd = 300;
assign #(delayr, delayf, delayd) out = (in === 1\'bx) ? 1\'bz : ~in;
always @(out) begin
case (out)
1\'b0: if ($time - top.change != delayf) begin
$display("Failed var_3 fall");
top.pass = 1\'b0;
end
1\'b1: if ($time - top.change != delayr) begin
$display("Failed var_3 rise");
top.pass = 1\'b0;
end
1\'bz: if ($time - top.change != delayd) begin
$display("Failed var_3 high-Z");
top.pass = 1\'b0;
end
default: begin
$display("FAILED var_3 default");
top.pass = 1\'b0;
end
endcase
end
endmodule
|
module main;
typedef struct packed {
logic [1:0] hig;
logic [1:0] low;
} word_as_nibbles;
typedef union packed {
logic [3:0] bits;
word_as_nibbles words;
} bits_t;
bits_t foo;
initial begin
foo.bits = \'b1001;
if (foo.bits != \'b1001) begin
\t $display("FAILED -- foo.bits=%b", foo.bits);
\t $finish;
end
if (foo.words != \'b1001) begin
\t $display("FAILED -- foo.words=%b", foo.words);
\t $finish;
end
//foo.words.low = \'b00;
//foo.words.hig = \'b11;
foo.words = \'b1100;
if (foo.words != \'b1100) begin
\t $display("FAILED -- foo.words=%b", foo.words);
\t $finish;
end
if (foo.bits != \'b1100) begin
\t $display("FAILED -- foo.bits=%b", foo.bits);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Check that it is possible to declare the data type for a enum type module
// port before the direction for non-ANSI style port declarations.
typedef enum integer {
A, B
} T;
module test(x);
T x;
output x;
initial begin
if ($bits(x) == $bits(T)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This tests the primitive synthesis of a simple left shift.
*/
module test (clk,c,a,b);
input clk;
input a, b;
output [1:0] c;
reg [1:0] c;
(* ivl_synthesis_on *)
always @(posedge clk)
c <= (a << 1) | b;
endmodule
module main;
reg a, b, clk;
wire [1:0] c;
test dut (.clk(clk), .c(c), .a(a), .b(b));
integer x;
(* ivl_synthesis_off *)
initial begin
clk = 0;
for (x = 0 ; x < 4 ; x = x+1) begin
\t a = x[1];
\t b = x[0];
\t #1 clk = 1;
\t #1 clk = 0;
\t if (c !== x[1:0]) begin
\t $display("FAILED == x=%0d (ab=%b%b), c=%b", x, a, b, c);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
module main;
typedef enum logic [3:0] { WORD0, WORD1, WORD9=\'b1001, WORDC=\'b1100 } word_t;
typedef union packed {
logic [3:0] bits;
word_t words;
} bits_t;
bits_t foo;
initial begin
foo.bits = \'b1001;
if (foo.bits !== \'b1001) begin
\t $display("FAILED -- foo.bits=%b", foo.bits);
\t $finish;
end
if (foo.words !== WORD9) begin
\t $display("FAILED -- foo.words=%b", foo.words);
\t $finish;
end
foo.words = WORDC;
if (foo.words !== WORDC) begin
\t $display("FAILED -- foo.words=%b", foo.words);
\t $finish;
end
if (foo.bits !== \'b1100) begin
\t $display("FAILED -- foo.bits=%b", foo.bits);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module test();
reg\t\tc;
a #(1) ua( .c(c), .b(h));
initial begin
c = 0;
#1 c = 1;
#1 c = 0;
$display("PASSED");
end
endmodule
module a(
\t\tc,
\t\tb,
\t\t);
parameter e = 2;
input\t c;
output [e-1:0] b;
reg [e-1:0] f;
reg [e-1:0] g;
reg [e-1:0] b;
integer\t d;
always @(posedge c) begin
for(d=0; d<e; d=d+1)
b[d] <= (f[d] & (b[d] | g[d]));
end
endmodule
|
module dff (q, d, cp, sdn, cdn);
output q;
input cp;
input d;
input sdn;
input cdn;
reg q;
always @(posedge cp or negedge sdn or negedge cdn) begin
if (~sdn) q <= 1;
else if (~cdn) q <= 0;
else q <= d;
end
specify
if (sdn && cdn) (posedge cp => (q +: d)) = (1, 1);
(negedge cdn => (q +: 1\'b0)) = (1, 1);
(negedge sdn => (q -: 1\'b1)) = (1, 1);
endspecify
endmodule
module test;
reg d, clk, set, clr;
dff dut(q, d, clk, ~set, ~clr);
initial begin
d=0; clk=0; set=0; clr=0;
$monitor($time,, "d=%b, clk=%b, set=%b, clr=%b, q=%b",
d, clk, set, clr, q);
$sdf_annotate("ivltests/sdf6.sdf");
#10 d = 1;
#10 set = 1;
#10 set = 0;
#10 clr = 1;
#10 clr = 0;
#10 clk = 1;
#10 d = 0;
end
endmodule
|
module foo(input x);
parameter n = 0;
pulldown p1(x);
initial #n $display("x(%0d) : %b", n, x);
endmodule
module tb;
wire y;
wire z;
foo #1 bar1(1\'b0);
foo #2 bar2(1\'b1);
foo #3 bar3(1\'bz);
foo #4 bar4(y);
foo #5 bar5({z});
initial #6 $display("y : ", y);
initial #7 $display("z : ", z);
endmodule
|
// specify3.v
module top;
reg a, b, fast;
wire q;
initial begin
a = 0;
b = 0;
fast = 0;
#10 $monitor($time,,"a=%b, b=%b, fast=%b, q=%b", a, b, fast, q);
#10 a = 1;
#10 a = 0;
#10 b = 1;
#10 b = 0;
#10 a = 1;
#10 fast = 1;
#10 b = 1;
#10 b = 0;
#10 a = 0;
#10 a = 1;
#10 $finish(0);
end
myxor g1 (q, a, b, fast);
endmodule
module myxor (q, a, b, fast);
output q;
input a, b, fast;
xor g1 (q, a, b);
specify
if (fast) (b => q) = 1;
if (fast) (a => q) = 1;
if (~fast) (b => q) = 4;
if (~fast) (a => q) = 4;
endspecify
endmodule
|
module top;
reg [20*8-1:0] str;
real rval;
reg [7:0] array [0:7];
reg [7:0] array2 [8:15];
reg [7:0] check [0:7];
integer idx, istr;
initial begin
for (idx = 0; idx < 8; idx = idx + 1) array[idx] = idx + 1;
for (idx = 8; idx < 16; idx = idx + 1) array2[idx] = 0;
// An invalid string.
$writememb(str, array);
$writememb(istr, array);
// Check a valid string.
str = "work/writemem.txt";
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememb(str, array);
$readmemb(str, check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememb 1, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
// Check a string with a non-printing character.
str[7:0] = \'d2;
$writememb(str, array);
// This should write, but will print a warning about the real.
rval = 0.0;
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememb("work/writemem.txt", array, rval);
$readmemb("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememb 2, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
// This should write, but will print a warning about the real.
rval = 7.0;
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememb("work/writemem.txt", array, 0, rval);
$readmemb("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememb 3, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
// These should not write the array.
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememb("work/writemem.txt", check, -1, 7);
$readmemb("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememb 4, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememb("work/writemem.txt", array2, 7, 15);
$readmemb("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememb 5, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememb("work/writemem.txt", check, 0, 8);
$readmemb("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememb 6, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememb("work/writemem.txt", array2, 8, 16);
$readmemb("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememb 7, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
// Check that we can write part of an array.
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememb("work/writemem.txt", array, 0, 6);
$readmemb("work/writemem.txt", check, 0, 6);
for (idx = 0; idx < 7; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememb 8, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
if (check[7] !== 0) begin
$display("Failed: for index 7 of writememb 8, expected 0, got %0d",
check[7]);
end
// An invalid string.
str = \'bx;
$writememh(str, array);
$writememh(istr, array);
// Check a valid string.
str = "work/writemem.txt";
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememh(str, array);
$readmemh(str, check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememh 1, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
// Check a string with a non-printing character.
str[7:0] = \'d2;
$writememh(str, array);
// This should write, but will print a warning about the real.
rval = 0.0;
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememh("work/writemem.txt", array, rval);
$readmemh("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememh 2, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
// This should write, but will print a warning about the real.
rval = 7.0;
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememh("work/writemem.txt", array, 0, rval);
$readmemh("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememh 3, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
// These should not write the array.
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememh("work/writemem.txt", check, -1, 7);
$readmemh("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememh 4, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememh("work/writemem.txt", array2, 7, 15);
$readmemh("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememh 5, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememh("work/writemem.txt", check, 0, 8);
$readmemh("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememh 6, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememh("work/writemem.txt", array2, 8, 16);
$readmemh("work/writemem.txt", check);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememh 7, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
// Check that we can write part of an array.
for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0;
$writememh("work/writemem.txt", array, 0, 6);
$readmemh("work/writemem.txt", check, 0, 6);
for (idx = 0; idx < 7; idx = idx + 1) begin
if (check[idx] !== idx + 1) begin
$display("Failed: for index %0d of writememh 8, expected %0d, got %0d",
idx, idx+1, check[idx]);
end
end
if (check[7] !== 0) begin
$display("Failed: for index 7 of writememh 8, expected 0, got %0d",
check[7]);
end
end
endmodule
|
`timescale 1ns/1ps
module BUFGCE(
output O,
input I,
input CE
);
bufif1(O, I, CE);
specify
(I => O) = (0.1, 0.2);
(CE => O) = (0.3, 0.4);
endspecify
endmodule
module dut(
output out,
input in,
input en
);
BUFGCE clk_IBUF_BUFG_inst(.O(out), .I(in), .CE(en));
endmodule
module top;
wire out;
reg in, en;
dut dut(out, in, en);
initial begin
$sdf_annotate("ivltests/br_ml20190814.sdf", dut);
end
endmodule
|
/*
* This is a simplified version of the test program for issue 1323691
* from the iverilog bugs database.
*/
`timescale 1ns/1ns
module main;
parameter early_empty=1;
reg\t re;
reg\t rc_isEmpty, rc_willBeEmpty;
wire empty;
assign empty = (early_empty!=0) ?
\t\t\t rc_willBeEmpty && re || rc_isEmpty :
\t\t\t rc_isEmpty;
initial begin
rc_isEmpty <= 1\'bx;
rc_willBeEmpty <= 1\'b1;
re <= 1\'b0;
rc_isEmpty <= 1\'b0;
#1 if (empty !== 1\'b0) begin
\t $display("FAILED -- empty == %b (s.b. 0)", empty);
\t $finish;
end
rc_isEmpty <= 1;
#1 if (empty !== 1\'b1) begin
\t $display("FAILED -- empty == %b (s.b. 1)", empty);
\t $finish;
end
$display("PASSED");
end
endmodule
|
// Check that assignment operators on real arrays are supported.
module test;
real r[1:0];
integer i = 1;
initial begin
// Immediate index
r[0] = 8.0;
r[0] += 1.0;
r[0] -= 2.0;
r[0] *= 3.0;
r[0] /= 7.0;
r[0]++;
r[0]--;
// Variable index
r[i] = 8.0;
r[i] += 1.0;
r[i] -= 2.0;
r[i] *= 3.0;
r[i] /= 7.0;
r[i]++;
r[i]--;
if (r[0] == 3.0 && r[1] == 3.0) begin
$display("PASSED");
end else begin
$display("FAILED. Expected %f, got %f and %f", 3.0, r[0], r[1]);
end
end
endmodule
|
/*
* land2 - a verilog test for logical and operator && in boolean context
*
*
* Copyright (C) 1999 Stephen G. Tell
* Portions inspired by qmark.v by Steven Wilson ([email protected])
* Modified by SDW to self test.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
module land2;
reg Clk;
reg a;
reg b;
reg c;
reg error;
wire q;
wire q_calc;
tand tand_m(q, q_calc, a, b, c);
initial Clk = 0;
always #10 Clk = ~Clk;
always @(posedge Clk)
begin
#1;
if(q != q_calc)
begin
$display("FAILED - expr && using %b%b%b is %b s/b %b",
a, b, c, q,q_calc);
error = 1;
end
end
reg [3:0] bvec;
integer xa;
integer xb;
integer xc;
initial begin
bvec = 4\'bzx10 ;
error = 0;
for(xa = 0; xa <= 3; xa = xa + 1)
\t for(xb = 0; xb <= 3; xb = xb + 1)
\t for(xc = 0; xc <= 3; xc = xc + 1)
\t begin
\t\t @(posedge Clk)
\t\t a = bvec[xa];
\t\t b = bvec[xb];
\t\t c = bvec[xc];
\t end // for (var3 = 0; var3 <= 3; var3 = var3 + 1)
if(error == 0 ) $display("PASSED");
$finish;
end
endmodule
module tand(q, q_calc, a, b, c);
output q;
output q_calc;
input a;
input b;
input c;
wire q = ( (a===b) && (b===c) );
reg q_calc;
always @(a or b or c)
begin
if(a === b)
begin
if( b === c)
q_calc = 1\'b1;
else
q_calc = 1\'b0;
end
else
q_calc = 1\'b0;
end
endmodule // foo
|
module test;
parameter width = 16;
localparam count = 1<<width;
reg [width-1:0] array[count];
integer\t idx;
initial begin
for (idx = 0 ; idx < count ; idx = idx+1)
\tarray[idx] = idx;
if (array[count/2] !== count/2) begin
\t $display("FAILED");
\t $finish;
end
if (array[0] !== 0) begin
\t $display("FAILED");
\t $finish;
end
for (idx = 0 ; idx < count ; idx = idx+1)
\tif (array[idx] !== idx) begin
\t $display("FAILED");
\t $finish;
\tend
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always 3.1.1B always reg_lvalue = boolean_expression ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
if(value1 != 4\'b1)
\t$display("FAILED - 3.1.1B always reg_lvalue = boolean_expression\
");
else
\tbegin
$display("PASSED\
");
\t $finish;
end
always value1 = 1\'b1 && 1\'b1 ;
endmodule
|
// Copyright 2008, Martin Whitaker.
// This file may be freely copied for any purpose.
module multiply();
reg signed [31:0] A;
reg signed [31:0] B;
wire signed [63:0] Y;
assign Y = A * B;
initial begin
A = -1;
B = -1;
#1 $display("(%0d)*(%0d) = %0d", A, B, Y);
if (Y !== 64\'d1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
module automatic_error();
reg global;
task automatic auto_task;
reg local;
begin:block
@(local || global);
end
endtask
endmodule
|
/*
* integer2le - a verilog test for integer less-or-equal conditional <=
*
* Copyright (C) 1999 Stephen G. Tell
* Portions inspired by qmark.v by Steven Wilson ([email protected])
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
module integer2le;
integer a;
integer b;
integer c;
reg error;
initial
begin
error = 0;
a = 1;
if(a <= 2)
begin
\t b = 1;
end
else
begin
\t $display("FAILED 1 <= 2");
\t error = 1;
end
a = 2;
if(a <= 2)
begin
\t b = 1;
end
else
begin
\t $display("FAILED 2 <= 2");
\t error = 1;
end
a = 3;
if(a <= 2)
begin
\t $display("FAILED 3 <= 2");
\t error = 1;
end
c = 0;
a = 10;
for(b = 0; a <= 5; b = b + 1)
begin
\t b = b + a;
\t c = c + 1;
\t if(c > 10)
begin
\t $display("FAILED (infinite loop) a=%d b=%d", a, b);
\t error = 1;
\t $finish;
\t end
end
if(b != 0)
begin
\t $display("FAILED forloop a=%d b=%d", a, b);
\t error = 1;
end
if(a != 10)
begin
\t $display("FAILED forloop a=%d b=%d", a, b);
\t error = 1;
end
b = 0;
c = 0;
for(a = 0; a <= 5; a = a + 1)
begin
\t b = b + a;
\t c = c + 1;
\t if(c > 10)
begin
\t $display("FAILED (infinite loop) a=%d b=%d", a, b);
\t error = 1;
\t $finish;
\t end
end
if(b != 15)
begin
\t $display("FAILED forloop b=%d expected 15", b);
\t error = 1;
end
if(error == 0)
\t $display("PASSED");
$finish;
end // initial begin
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Compound ifdef test with else, exterior define
//
`define DOUBLE
module ifdef1;
reg error ;
`ifdef DOUBLE
`ifdef NOCODE
initial
begin
#20;
error = 1;
#20;
end
`else
initial
begin
#20;
error = 0;
#20;
end
`endif
`endif
initial
begin
#1;
error = 1;
#40;
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
module top;
reg pass;
real rval;
reg [7:0] res;
initial begin
pass = 1\'b1;
res = 6.0;
if (res !== 8\'d6) begin
$display("Failed blocking assignment, expeted 6, got %d", res);
pass = 1\'b0;
end
// The compiler is generating bad code for a NB-assign with a real r-value.
res <= 7.0;
#1 if (res !== 8\'d7) begin
$display("Failed nonblocking assignment, expeted 7, got %d", res);
pass = 1\'b0;
end
rval = 8.0;
res <= rval;
#1 if (res !== 8\'d8) begin
$display("Failed nonblocking assignment, expeted 8, got %d", res);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module test();
reg [7:0] ival = $signed(1.0);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate variable right shift in function
module main;
reg globvar;
reg [7:0] var1,var2,var3;
reg error;
reg [7:0] value;
function [7:0] rshft;
input [7:0] var1,var2;
begin
rshft = var1 >> var2;
end
endfunction
initial
begin
error = 0;
#1 ;
var1 = 8\'h80;
var2 = 8\'h7;
value = rshft(var1,var2);
#1;
if(value !== 8\'h1)
begin
error = 1;
\t$display ("FAILED - 80 >> 7 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h6;
value = rshft(var1,var2);
#1;
if(value !== 8\'h2)
begin
error = 1;
\t$display ("FAILED - 80 >> 6 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h5;
value = rshft(var1,var2);
#1;
if(value !== 8\'h4)
begin
error = 1;
\t$display ("FAILED - 80 >> 5 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h4;
value = rshft(var1,var2);
#1;
if(value !== 8\'h8)
begin
error = 1;
\t$display ("FAILED - 80 >> 4 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h3;
value = rshft(var1,var2);
#1;
if(value !== 8\'h10)
begin
error = 1;
\t$display ("FAILED - 80 >> 3 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h2;
value = rshft(var1,var2);
#1;
if(value !== 8\'h20)
begin
error = 1;
\t$display ("FAILED - 80 >> 2 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h1;
value = rshft(var1,var2);
#1;
if(value !== 8\'h40)
begin
error = 1;
\t$display ("FAILED - 80 >> 1 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h0;
value = rshft(var1,var2);
#1;
if(value !== 8\'h80)
begin
error = 1;
\t$display ("FAILED - 80 >> 0 is %h",value);
end
#1 ;
var1 = 8\'ha5;
var2 = 8\'h7;
value = rshft(var1,var2);
#1;
if(value !== 8\'h01)
begin
error = 1;
\t$display ("FAILED - a5 >> 7 is %h",value);
end
#1 ;
var1 = 8\'ha5;
var2 = 8\'h1;
value = rshft(var1,var2);
#1;
if(value !== 8\'h52)
begin
error = 1;
\t$display ("FAILED - aa >> 1 is %h",value);
end
if(error === 0)
$display("PASSED");
end
endmodule // main
|
// pr1855504
module mul_test();
reg [15:0] prod;
reg [7:0] op2;
reg [15:0] op1;
initial begin
op1 = 16\'h0DA0;
op2 = 8\'h0A;
prod = 16\'h0000;
end
always begin
prod <= op1[7:0] * op2;
#5 $display("op1 = %h, op2 = %h, prod = %h", op1, op2, prod);
#5 $finish(0);
end
endmodule // mul_test
|
module dut(input EN, input I, output O);
assign O = EN ? I : 1\'bz;
specify
(I => O) = (2);
(EN *> O) = (4);
endspecify
endmodule
module test();
reg EN;
reg I;
tri O;
pulldown(O);
dut dut(EN, I, O);
reg failed = 0;
initial begin
$monitor($time,,EN,,I,,O);
EN = 0;
#4;
#0 if (O !== 0) failed = 1;
#1 I = 1;
#1 EN = 1;
#3;
#0 if (O !== 0) failed = 1;
#1;
#0 if (O !== 1) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module bug;
function real sin;
\tinput x;
\treal x;
\tsin = 1.570794*x;
endfunction
real ax, ay;
initial begin
\tax = 2.0;
\tay = sin(ax);
\t$display("sin(%g) is not really %g", ax, ay);
end
endmodule
|
// This module generate M single 2*HW-1 bit vector each T time steps
module stimulus #(parameter HW = 4, T = 10, M = 200) (
output reg [2*HW-1:0] a
);
int i;
int MAX;
initial begin
MAX = 1 << 2*HW;
for (i = 0; i < M; i=i+1) begin
a = $random % MAX ;
#T;
end
end
endmodule
// This module always checks that y complies with an XOR reduction operation on 2*HW-1 bits input as x
module check #(parameter HW = 4) (input [2*HW-1:0] x, input y);
wire yi = ^x;
always @(y, yi) begin
#1;
if (y !== yi) begin
$display("ERROR");
$finish;
end
end
endmodule
module test;
parameter M = 200; // number of test vectors
parameter T = 10; // time step unit
parameter HW = 4; // bit width of input vecotrs
parameter S = M*T + 40;
wire [2*HW-1:0] a;
wire y;
stimulus #(HW, T, M) stim (.a(a));
gxor_reduce #(HW) duv (.a(a), .ar(y));
check check (.x(a), .y(y) );
initial begin
#S;
$display("PASSED");
$finish;
end
endmodule
|
/*
* This test file is based on PR991.
*/
module bug();
wire _d1,_d2,test,test1,test2,test3;
assign _d1 = 1;
assign _d2 = 0;
assign test = (_d1 && _d2) != 0;
assign test1 = (_d1 && _d2) == 0;
assign test2 = (_d1 && _d2) !== 0;
assign test3 = (_d1 && _d2) === 0;
initial begin
#1;
$displayb(_d2); // Should be 0
$displayb(test); // Should be 0 (1 && 0) != 0 --> 0 != 0
$displayb(test1); // Should be 1
$displayb(test2); // Should be 0
$displayb(test3); // Should be 1
end
endmodule
|
module stimulus (output reg A, B);
initial begin
{A, B} = 2\'b00;
#10 {A, B} = 2\'b01;
#10 {A, B} = 2\'b10;
#10 {A, B} = 2\'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
2\'b00: gate_output = 1;
2\'b01: gate_output = 0;
2\'b10: gate_output = 0;
2\'b11: gate_output = 0;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in NOR operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
nor_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#100;
$display("PASSED");
$finish;
end
endmodule
|
// Regression test for bug reported by Niels Moeller on
// 15-Mar-2015 via the iverilog-devel mailing list.
module test();
wire [7:0] my_net;
assign my_net[3:0] = 1;
assign my_net[7:4] = 2;
initial begin
#1 $monitor("At time %0t, field 1 = %h, field 2 = %h",
$time, my_net[3:0], my_net[7:4]);
#1 $finish(0);
end
endmodule
|
module check (input signed [22:0] a, b, c);
wire signed [22:0] int_AB;
assign int_AB = a - b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB != c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg signed [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
end
#1 A = 0;
B = 0;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 0;
#1 A = -1;
#1 B = 1;
#1 A = 1;
end
endmodule
module test;
wire signed [22:0] a, b;
wire signed [22:0] r;
stimulus stim (.A(a), .B(b));
ssub23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#20000;
$display("PASSED");
$finish;
end
endmodule
|
// Catch problem where we assign to function params
module top();
integer r;
function integer fact;
input n;
integer n;
for (fact = 1; n > 0; n = n - 1) begin
fact = fact * n;
end
endfunction // for
initial begin
r = fact(5);
$display("fact(5) = %d", r);
if (r == 120)
$display("PASSED");
else
$display("FAILED");
end
endmodule // top
|
/*
* Copyright (c) 1998 Purdea Andrei ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This demonstrates proper handling of leading zeroes, and the %0b format.
*/
module main();
initial
begin
$display("|%b|", 10\'b11);
$display("|%0b|", 10\'b11);
$display("|%b|", 10\'b0);
$display("|%0b|", 10\'b0);
$finish(0);
end
endmodule
|
module top;
real var1, var2;
reg [7:0] bvar;
reg result;
wire r_a = &var1;
wire r_o = |var1;
wire r_x = ^var1;
wire r_na = ~&var1;
wire r_no = ~|var1;
wire r_xn1 = ~^var1;
wire r_xn2 = ^~var1;
wire r_b_a = var1 & var2;
wire r_b_o = var1 | var2;
wire r_b_x = var1 ^ var2;
wire r_b_na = var1 ~& var2;
wire r_b_no = var1 ~| var2;
wire r_b_xn1 = var1 ~^ var2;
wire r_b_xn2 = var1 ^~ var2;
wire r_eeq = var1 === var2;
wire r_neeq = var1 !== var2;
wire r_ls = var1 << var2;
wire r_als = var1 <<< var2;
wire r_rs = var1 >> var2;
wire r_ars = var1 >>> var2;
wire r_con = {var1};
wire r_rep = {2.0{var1}};
initial begin
var1 = 1.0;
var2 = 2.0;
#1;
/* These should all fail in the compiler. */
result = &var1;
result = |var1;
result = ^var1;
result = ~&var1;
result = ~|var1;
result = ~^var1;
result = ^~var1;
result = var1 & var2;
result = var1 | var2;
result = var1 ^ var2;
result = var1 ~& var2;
result = var1 ~| var2;
result = var1 ~^ var2;
result = var1 ^~ var2;
result = var1 === var2;
result = var1 !== var2;
bvar = var1 << var2;
bvar = var1 <<< var2;
bvar = var1 >> var2;
bvar = var1 >>> var2;
bvar = {var1};
bvar = {2.0{var1}};
$display("Failed");
end
endmodule
|
module top();
wire out1, out2;
child c1(1, 0, out1);
child c2(1, 1, out2);
initial begin
#1;
if (out1 !== 0)
$display("FAILED -- out1 !== 0");
else if (out2 !== 1)
$display("FAILED -- out2 !== 1");
else
$display("PASSED");
end
endmodule // top
module child(in1, in2, out);
input in1, in2;
output out;
assign out = in1 & in2;
endmodule // child
|
module main;
// The declaration assignment within a task it not allowed
// in Verilog, but it is allowed in SystemVerilog.
task foo (input integer x, output integer y);
integer step = 3;
y = x + step;
endtask // foo
integer\t a, b;
initial begin
a = 3;
foo(a, b);
if (b !== 6) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Check that declaring a variable multiple times for a signal that was
// previously declared as a non-ANSI task input port is an error.
module test;
task t;
input x;
reg x;
reg x;
$display("FAILED");
endtask
reg y;
initial t(y);
endmodule
|
// Regression test for GitHub issue #60 part 1 - sized numeric constants
// must have size greater than zero.
module test();
localparam Value = 0'b0;
endmodule
|
// Copyright (c) 2000 Steve Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Try the always @ * construct from Verilog 2000 LRM spec
module test;
//
// Define a procedural assignment based mux.
//
reg [1:0] sel;
reg [1:0] out, a,b,c,d;
reg error;
always @ *
case (sel)
2\'b00: out = a;
2\'b01: out = b;
2\'b10: out = c;
2\'b11: out = d;
endcase
initial
begin
error = 0;
#1 ;
sel = 0;
a = 0;
#1;
if(out !== 2\'b00)
begin
$display("FAILED - Wildcard sensitivy list a != 0(1)");
error =1;
end
#1;
a = 1;
#1;
if(out !== 2\'b01)
begin
$display("FAILED - Wildcard sensitivity list a != 1 (2)");
error =1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
module test ();
wire [5:0] a [0:2];
b b(.a(a[0]));
initial begin
#1 if (a[0] !== 5) begin
\t $display("FAILED -- a[0] == %d", a[0]);
\t $finish;
end
if (a[1] !== 6\'bzzzzzz) begin
\t $display("FAILED -- a[1] == %h", a[1]);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule
module b (output wire [5:0] a);
assign a = 5;
endmodule
|
module top;
reg var;
always if (var);
endmodule
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* SDW: Verify addition in a param declaration
*/
module test;
parameter A0 = 4\'b0011 + 4\'b0001 ;
initial
begin
if(A0 !== 4\'b0100)
$display("FAILED - Addition in a param declaration.");
else
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 2002 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Synth of basic latch form
//
//
module basiclatch ( clk, d, q);
input clk, d;
output q;
reg q;
always @ (clk or d)
if(~clk)
q = d;
endmodule
module tbench ;
reg clk, d;
basiclatch u_reg (clk,d,q);
initial
begin
clk = 0;
d = 0;
#1 ;
if(q !== 0)
begin
$display("FAILED - initial value not 0");
\t $finish;
end
#1 ;
clk = 1;
# 1;
d = 1;
# 1;
if(q !== 0)
begin
$display("FAILED - Didn\'t latch initial 0");
\t $finish;
end
#1
clk = 0;
# 1;
if(q !== 1)
begin
$display("FAILED - Didn\'t pass 1 after latch dropped");
\t $finish;
end
#1
clk = 1;
# 1;
d = 0;
# 1;
if(q !== 1)
begin
$display("FAILED - Didn\'t latch 1 after latch dropped");
\t $finish;
end
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always assign reg_lvalue = boolean_expression ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
if(value1 != 4\'h1)
\t$display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr\
");
else
\tbegin
$display("PASSED\
");
\t $finish;
end
always assign value1 = 1\'b1 && 1\'b1 ;
endmodule
|
// Regression test for bug reported by Niels Moeller on 21-Mar-2015 via
// iverilog-devel mailing list. Extended to cover similar problems. This
// is just testing compiler error recovery.
module test();
integer array[3:0];
integer i1;
always @* begin
for (i1 = 0; i1 < 4; i1 = i1 + 1) begin
array[i1] = undeclared;
end
end
integer i2;
always @* begin
for (i2 = 0; i2 < 4; i2 = i2 + 1) begin
undeclared = array[i2];
end
end
integer i3;
always @* begin
for (i3 = undeclared; i3 < 4; i3 = i3 + 1) begin
array[i3] = i3;
end
end
integer i4;
always @* begin
for (i4 = 0; i4 < undeclared; i4 = i4 + 1) begin
array[i4] = i4;
end
end
integer i5;
always @* begin
for (i5 = 0; i5 < 4; i5 = i5 + undeclared) begin
array[i5] = i5;
end
end
integer i6;
always @* begin
i6 = 0;
while (i6 < undeclared) begin
array[i6] = i6;
i6 = i6 + 1;
end
end
integer i7;
always @* begin
i7 = 0;
while (i7 < 4) begin
array[i7] = undeclared;
i7 = i7 + 1;
end
end
integer i8;
always @* begin
i8 = 0;
repeat (undeclared) begin
array[i8] = i8;
i8 = i8 + 1;
end
end
integer i9;
always @* begin
i9 = 0;
repeat (4) begin
array[i9] = undeclared;
i9 = i9 + 1;
end
end
endmodule
|
// Test implicit casts during procedural continuous (reg) assignments.
module implicit_cast();
real src_r;
bit unsigned [7:0] src_u2;
bit signed [7:0] src_s2;
logic unsigned [7:0] src_u4;
logic signed [7:0] src_s4;
logic unsigned [7:0] src_ux;
logic signed [7:0] src_sx;
real dst_r;
bit unsigned [3:0] dst_u2s;
bit signed [3:0] dst_s2s;
bit unsigned [11:0] dst_u2l;
bit signed [11:0] dst_s2l;
logic unsigned [3:0] dst_u4s;
logic signed [3:0] dst_s4s;
logic unsigned [11:0] dst_u4l;
logic signed [11:0] dst_s4l;
bit failed;
initial begin
failed = 0;
src_r = -7;
src_u2 = 7;
src_s2 = -7;
src_u4 = 7;
src_s4 = -7;
src_ux = 8\'bx0z00111;
src_sx = 8\'bx0z00111;
$display("cast to real");
assign dst_r = src_r; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
assign dst_r = src_u2; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
assign dst_r = src_s2; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
assign dst_r = src_u4; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
assign dst_r = src_s4; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
assign dst_r = src_ux; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
assign dst_r = src_sx; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
$display("cast to small unsigned bit");
assign dst_u2s = src_r; $display("%d", dst_u2s); if (dst_u2s !== 4\'d9) failed = 1;
assign dst_u2s = src_u2; $display("%d", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1;
assign dst_u2s = src_s2; $display("%d", dst_u2s); if (dst_u2s !== 4\'d9) failed = 1;
assign dst_u2s = src_u4; $display("%d", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1;
assign dst_u2s = src_s4; $display("%d", dst_u2s); if (dst_u2s !== 4\'d9) failed = 1;
assign dst_u2s = src_ux; $display("%d", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1;
assign dst_u2s = src_sx; $display("%d", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1;
$display("cast to small signed bit");
assign dst_s2s = src_r; $display("%d", dst_s2s); if (dst_s2s !== -4\'sd7) failed = 1;
assign dst_s2s = src_u2; $display("%d", dst_s2s); if (dst_s2s !== 4\'sd7) failed = 1;
assign dst_s2s = src_s2; $display("%d", dst_s2s); if (dst_s2s !== -4\'sd7) failed = 1;
assign dst_s2s = src_u4; $display("%d", dst_s2s); if (dst_s2s !== 4\'sd7) failed = 1;
assign dst_s2s = src_s4; $display("%d", dst_s2s); if (dst_s2s !== -4\'sd7) failed = 1;
assign dst_s2s = src_ux; $display("%d", dst_s2s); if (dst_s2s !== 4\'sd7) failed = 1;
assign dst_s2s = src_sx; $display("%d", dst_s2s); if (dst_s2s !== 4\'sd7) failed = 1;
$display("cast to large unsigned bit");
assign dst_u2l = src_r; $display("%d", dst_u2l); if (dst_u2l !== 12\'d4089) failed = 1;
assign dst_u2l = src_u2; $display("%d", dst_u2l); if (dst_u2l !== 12\'d7) failed = 1;
assign dst_u2l = src_s2; $display("%d", dst_u2l); if (dst_u2l !== 12\'d4089) failed = 1;
assign dst_u2l = src_u4; $display("%d", dst_u2l); if (dst_u2l !== 12\'d7) failed = 1;
assign dst_u2l = src_s4; $display("%d", dst_u2l); if (dst_u2l !== 12\'d4089) failed = 1;
assign dst_u2l = src_ux; $display("%b", dst_u2l); if (dst_u2l !== 12\'b000000000111) failed = 1;
assign dst_u2l = src_sx; $display("%b", dst_u2l); if (dst_u2l !== 12\'b000000000111) failed = 1;
$display("cast to large signed bit");
assign dst_s2l = src_r; $display("%d", dst_s2l); if (dst_s2l !== -12\'sd7) failed = 1;
assign dst_s2l = src_u2; $display("%d", dst_s2l); if (dst_s2l !== 12\'sd7) failed = 1;
assign dst_s2l = src_s2; $display("%d", dst_s2l); if (dst_s2l !== -12\'sd7) failed = 1;
assign dst_s2l = src_u4; $display("%d", dst_s2l); if (dst_s2l !== 12\'sd7) failed = 1;
assign dst_s2l = src_s4; $display("%d", dst_s2l); if (dst_s2l !== -12\'sd7) failed = 1;
assign dst_s2l = src_ux; $display("%b", dst_s2l); if (dst_s2l !== 12\'b000000000111) failed = 1;
assign dst_s2l = src_sx; $display("%b", dst_s2l); if (dst_s2l !== 12\'b000000000111) failed = 1;
$display("cast to small unsigned logic");
assign dst_u4s = src_r; $display("%d", dst_u4s); if (dst_u4s !== 4\'d9) failed = 1;
assign dst_u4s = src_u2; $display("%d", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1;
assign dst_u4s = src_s2; $display("%d", dst_u4s); if (dst_u4s !== 4\'d9) failed = 1;
assign dst_u4s = src_u4; $display("%d", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1;
assign dst_u4s = src_s4; $display("%d", dst_u4s); if (dst_u4s !== 4\'d9) failed = 1;
assign dst_u4s = src_ux; $display("%d", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1;
assign dst_u4s = src_sx; $display("%d", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1;
$display("cast to small signed logic");
assign dst_s4s = src_r; $display("%d", dst_s4s); if (dst_s4s !== -4\'sd7) failed = 1;
assign dst_s4s = src_u2; $display("%d", dst_s4s); if (dst_s4s !== 4\'sd7) failed = 1;
assign dst_s4s = src_s2; $display("%d", dst_s4s); if (dst_s4s !== -4\'sd7) failed = 1;
assign dst_s4s = src_u4; $display("%d", dst_s4s); if (dst_s4s !== 4\'sd7) failed = 1;
assign dst_s4s = src_s4; $display("%d", dst_s4s); if (dst_s4s !== -4\'sd7) failed = 1;
assign dst_s4s = src_ux; $display("%d", dst_s4s); if (dst_s4s !== 4\'sd7) failed = 1;
assign dst_s4s = src_sx; $display("%d", dst_s4s); if (dst_s4s !== 4\'sd7) failed = 1;
$display("cast to large unsigned logic");
assign dst_u4l = src_r; $display("%d", dst_u4l); if (dst_u4l !== 12\'d4089) failed = 1;
assign dst_u4l = src_u2; $display("%d", dst_u4l); if (dst_u4l !== 12\'d7) failed = 1;
assign dst_u4l = src_s2; $display("%d", dst_u4l); if (dst_u4l !== 12\'d4089) failed = 1;
assign dst_u4l = src_u4; $display("%d", dst_u4l); if (dst_u4l !== 12\'d7) failed = 1;
assign dst_u4l = src_s4; $display("%d", dst_u4l); if (dst_u4l !== 12\'d4089) failed = 1;
assign dst_u4l = src_ux; $display("%b", dst_u4l); if (dst_u4l !== 12\'b0000x0z00111) failed = 1;
assign dst_u4l = src_sx; $display("%b", dst_u4l); if (dst_u4l !== 12\'bxxxxx0z00111) failed = 1;
$display("cast to large signed logic");
assign dst_s4l = src_r; $display("%d", dst_s4l); if (dst_s4l !== -12\'sd7) failed = 1;
assign dst_s4l = src_u2; $display("%d", dst_s4l); if (dst_s4l !== 12\'sd7) failed = 1;
assign dst_s4l = src_s2; $display("%d", dst_s4l); if (dst_s4l !== -12\'sd7) failed = 1;
assign dst_s4l = src_u4; $display("%d", dst_s4l); if (dst_s4l !== 12\'sd7) failed = 1;
assign dst_s4l = src_s4; $display("%d", dst_s4l); if (dst_s4l !== -12\'sd7) failed = 1;
assign dst_s4l = src_ux; $display("%b", dst_s4l); if (dst_s4l !== 12\'b0000x0z00111) failed = 1;
assign dst_s4l = src_sx; $display("%b", dst_s4l); if (dst_s4l !== 12\'bxxxxx0z00111) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test checks that the upwards search for a name stops at a
* module boundary. In this example, the q variable in the instance
* "inst" of the test module should be an implicit wire, even though
* it is placed into the containing main scope that has a wire q in it.
*/
module test(p);
output p;
assign q = 1; // This should generate an error, q not defined
assign p = q;
endmodule // test
module main;
wire q = 0;
wire sig;
test inst(sig);
initial begin
#1 if (q !== 1\'b0) begin
\t $display("FAILED -- main.q == %b", q);
\t $finish;
end
if (sig !== 1\'b1) begin
\t $display("FAILED -- main.test.q == %b", sig);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module top;
reg [7:0] vec = 8\'b10100101;
reg passed = 1;
function [3:0] copy;
input [3:0] in;
copy = in;
endfunction
initial begin
if (copy(vec>>4) != 4\'b1010) begin
passed = 0;
$display("Failed!");
end
if (passed) $display("PASSED");
end
endmodule
|
module top;
bit [2:-1] vec = 4\'b1001;
bit btvar = 0;
byte bvar = 0;
shortint svar = 0;
int ivar = 0;
longint lvar = 0;
initial begin
if ((vec[-1] != 1) && (vec[0] != 0) &&
(vec[1] != 0) && (vec[2] != 1)) begin
$display("Failed to select vector bits correctly");
$finish;
end
$display("Vec: ", vec);
$display("Bit: ", btvar);
$display("Byte: ", bvar);
$display("Short: ", svar);
$display("Int: ", ivar);
$display("Long: ", lvar);
$display("Monitor results:");
$monitor("Time: ", $stime,
"\
Bit: ", btvar,
"\
Byte: ", bvar,
"\
Short: ", svar,
"\
Int: ", ivar,
"\
Long: ", lvar);
#1 btvar = 1;
#1 bvar = 1;
#1 svar = 1;
#1 ivar = 1;
#1 lvar = 1;
end
endmodule
|
/*
* Copyright (c) 1998 Philips Semiconductors ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test();
MUX_REG_8x8 PAGE_REG_B3 (
\t\t\t.CLK\t(CLK),
\t\t\t/*
\t\t\t.IN\t(DATA_RES[31:24]),
\t\t\t.OUT\t(PAGE[31:24]),
\t\t\t.EN_IN\t(EN_B3),
\t\t\t.EN_OUT\t(PAGE_SEL),
\t\t\t*/
\t\t\t.TC\t(),
\t\t\t.TD\t(),
\t\t\t.TQ\t());
endmodule
|
module top;
reg pass;
uwire zero, one;
assign one = 1\'b1;
initial begin
pass = 1\'b1;
#1;
if (zero !== 1\'bz) begin
$display("Failed: undriven uwire gave %b", zero);
pass = 1\'b0;
end
if (one !== 1\'b1) begin
$display("Failed: driven uwire gave %b", one);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`timescale 1us/100ns
module top;
reg pass = 1\'b1;
real ra, rb, rpow;
initial begin
ra = 1.0; rb = 2.0;
rpow = ra ** rb;
if (rpow != 1.0) begin
pass = 1\'b0;
$display("Real: power value not correct, expected 1.0 got %g.", rpow);
end
ra = 2.0;
rpow = ra ** rb;
if (rpow != 4.0) begin
pass = 1\'b0;
$display("Real: power value not correct, expected 4.0 got %g.", rpow);
end
ra = 0.0;
rpow = ra ** rb;
if (rpow != 0.0) begin
pass = 1\'b0;
$display("Real: power value not correct, expected 0.0 got %g.", rpow);
end
ra = 10.0;
rpow = ra ** rb;
if (rpow != 100.0) begin
pass = 1\'b0;
$display("Real: power value not correct, expected 100.0 got %g.", rpow);
end
ra = 0.0; rb = -1.0;
rpow = ra ** rb;
$display("0.0 ** -1.0 = %g", rpow);
ra = -1.0; rb = 2.5;
rpow = ra ** rb;
$display("-1.0 ** 2.5 = %g", rpow);
if (pass) $display("PASSED");
end
endmodule
|
`timescale 1ns/10ps
module top;
reg pass;
reg a;
reg p;
wire y;
supply1 vdd;
supply0 gnd;
tranif1 #(5) nmos_0(gnd, y, a);
tranif0 #(5) pmos_0(y, vdd, a);
initial begin
$monitor($realtime,, y,, a);
pass = 1\'b1;
p = 1\'bx;
a <= 1\'b0;
repeat (2) #10 a = ~a;
#10;
if (pass) $display("PASSED");
$finish;
end
always @(a) begin
#4.99 if (y !== p) begin
$display("Failed at %.2f (early), expected %b, got %b", $realtime, p, y);
pass = 1\'b0;
end
#0.02 if (y !== ~a) begin
$display("Failed at %.2f (late), expected %b, got %b", $realtime, ~a, y);
pass = 1\'b0;
end
p = y;
end
endmodule
|
module test();
wire [7:0] value1;
wire [7:0] value2;
assign value1[3:0] = 4\'d2;
assign value2 = value1 + 8\'d1;
initial begin
#2 $display("%b %b", value1, value2);
if (value2 === 8\'bx)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module test;
event e_Peek;
event e_Poke;
initial begin
\t// $dumpvars;
\t#0;
\t->e_Poke;
\t#51 $finish(0);
end
always @(e_Poke) begin
\t$display("e_Poke received @ %0t", $time);
\t#10;
\t$display("e_Peek asserted @ %0t", $time);
\t->e_Peek;
end
endmodule
|
// Check that the signedness of class properties are handled correctly when
// accessing the property on a class object and passing it to a system function.
module test;
class C;
shortint s = -1;
bit [15:0] u = -1;
endclass
C c;
string s;
initial begin
c = new;
s = $sformatf("%0d %0d", c.s, c.u);
if (s == "-1 65535") begin
$display("PASSED");
end else begin
$display("FAILED s=%s", s);
end
end
endmodule
|
// Check that it is possible to declare the data type for a struct type task
// port before the direction for non-ANSI style port declarations.
module test;
typedef struct packed {
reg [31:0] x;
reg [7:0] y;
} T;
task t;
input x;
T x;
if (x.x == 10 && x.y == 20 && $bits(x) == $bits(T)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial begin
static T val;
val.x = 10;
val.y = 20;
t(val);
end
endmodule
|
// Check that blocking partial writes to a 4-state vector are correctly
// handlded.
module test;
reg failed = 1\'b0;
`define check(val, exp) \\
if (exp !== val) begin \\
$display("FAILED. Got %b, expected %b.", val, exp); \\
failed = 1\'b1; \\
end
reg [3:0] x;
integer i;
initial begin
// Immediate index
// Within bounds
x = \'hx;
x[2:1] = 2\'b10;
`check(x, 4\'bx10x)
// Partially oob at high and low side
x = \'hx;
x[4:-1] = 6\'b101010;
`check(x, 4\'b0101)
// Partially oob at low side
x = \'hx;
x[0:-1] = 2\'b10;
`check(x, 4\'bxxx1)
// Partially oob at high side
x = \'hx;
x[4:3] = 2\'b01;
`check(x, 4\'b1xxx)
// Fully oob at low side
x = \'hx;
x[-1:-2] = 2\'b11;
`check(x, 4\'bxxxx)
// Fully oob at high side
x = \'hx;
x[6:5] = 2\'b11;
`check(x, 4\'bxxxx)
// Variable index
// Within bounds
i = 1;
x = \'hx;
x[i+:2] = 2\'b10;
`check(x, 4\'bx10x)
// Partially oob at high and low side
i = -1;
x = \'hx;
x[i+:6] = 6\'b101010;
`check(x, 4\'b0101)
// Partially oob at low side
i = -1;
x = \'hx;
x[i+:2] = 2\'b10;
`check(x, 4\'bxxx1)
// Partially oob at high side
i = 3;
x = \'hx;
x[i+:2] = 2\'b01;
`check(x, 4\'b1xxx)
// Fully oob at low side
i = -2;
x = \'hx;
x[i+:2] = 2\'b11;
`check(x, 4\'bxxxx)
// Fully oob at high side
i = 5;
x = \'hx;
x[i+:2] = 2\'b11;
`check(x, 4\'bxxxx)
// Undefined index
i = \'hx;
x = \'hx;
x[i+:2] = 2\'b11;
`check(x, 4\'bxxxx)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module top;
// This should be valid. The Icarus compiler keeps these as negatives, but
// the run time doesn\'t support negative values.
enum bit signed [7:0] {rn = -1, yn = -2, gn = -3} nl;
integer val;
initial begin
nl = rn;
$display("First: %d", nl);
nl = nl.next;
$display("Second: %d", nl);
nl = nl.next;
$display("Third: %d", nl);
nl = nl.next;
$display("Wrapped: %d", nl);
nl = nl.prev;
$display("Wrapped: %d", nl);
val = nl;
$display("As integer: %d", val);
end
// This should be a signed value!
initial #1 $display("Compile: ", rn);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary or ^~(value)
//
module main;
reg [3:0] vect;
reg\terror;
wire\tresult;
assign result = ^~(vect);
initial
begin
error = 0;
for(vect=4\'b0001;vect<4\'b0000;vect = vect << 1)
begin
#1;
if(result !== 1\'b0)
begin
$display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
error = 1\'b1;
end
end
#1;
for(vect=4\'b0011;vect<4\'b0000;vect = vect << 1)
begin
#1;
if(result !== 1\'b0)
begin
$display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
error = 1\'b1;
end
end
#1;
vect = 4\'b0000;
#1;
if(result !== 1\'b1)
begin
$display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
error = 1\'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
// Michael Runyan (mrunyan at chiaro.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg [5:0]\taddr;
reg [75:0]\tm_poke[4:0];
reg [75:0]\tm_peek[4:0];
task f_copy_for_buggy_eda_vendor;
\tinteger i;
\treg [75:0] tmp;
begin
\tfor (i = 0; i < 5; i = i + 1) begin
\t tmp = m_poke[i];
\t m_peek[i] = tmp;
\tend
end
endtask
task f_copy;
\tinteger i;
begin
\tfor (i = 0; i < 5; i = i + 1) begin
\t m_peek[i] = m_poke[i];
\tend
end
endtask
task f_dump;
\tinteger i;
begin
\tfor (i = 0; i < 5; i = i + 1) begin
\t $display ("%0d: m_poke <=> m_peek, 0x%x <=> 0x%x%s",
\t\ti, m_poke[i], m_peek[i],
\t\tm_poke[i] !== m_peek[i] ? " - ERROR" : "");
\tend
end
endtask
initial begin
\t#0;
\t$mempoke;
\t#10;
\tf_copy;
\t//f_copy_buggy_eda_vendor;
\t#10;
\t$mempeek;
\t#10;
\tf_dump;
end
endmodule
|
module switch_primitives();
wire a;
wire b0;
wire b1;
wire m0;
wire m1;
wire t0;
wire t1;
reg in;
reg en;
bufif0(b0, a, en);
bufif1(b1, a, en);
pmos(m0, a, en);
nmos(m1, a, en);
tranif0(t0, a, en);
tranif1(a, t1, en);
assign a = in;
initial begin
$monitor("%b %b %b %b %b %b %b %b %v %v %v %v %v %v",
en, a, b0, b1, m0, m1, t0, t1,
b0, b1, m0, m1, t0, t1);
#1 $display("------------------");
#1 en = 1\'b0; in = 1\'b0;
#1 en = 1\'b0; in = 1\'b1;
#1 en = 1\'b0; in = 1\'bx;
#1 en = 1\'b0; in = 1\'bz;
#1 $display("------------------");
#1 en = 1\'b1; in = 1\'b0;
#1 en = 1\'b1; in = 1\'b1;
#1 en = 1\'b1; in = 1\'bx;
#1 en = 1\'b1; in = 1\'bz;
#1 $display("------------------");
#1 en = 1\'bx; in = 1\'b0;
#1 en = 1\'bx; in = 1\'b1;
#1 en = 1\'bx; in = 1\'bx;
#1 en = 1\'bx; in = 1\'bz;
#1 $display("------------------");
#1 en = 1\'bz; in = 1\'b0;
#1 en = 1\'bz; in = 1\'b1;
#1 en = 1\'bz; in = 1\'bx;
#1 en = 1\'bz; in = 1\'bz;
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* The output from this program should be:
* 1001
* 0100
* 0010
* 1001
* 1100
*/
module main;
reg [7:0] foo;
initial begin
foo = 8\'b11001001;
$display("%b", foo[3:0]);
$display("%b", foo[4:1]);
$display("%b", foo[5:2]);
$display("%b", foo[6:3]);
$display("%b", foo[7:4]);
end
endmodule // main
|
/*
* This module instantiates the fa4 entity, which in turn
* instantiates other entities. This demonstrates hierarchical
* constructs in VHDL.
*/
module test;
reg [3:0] a, b;
reg cin;
wire [3:0] s;
wire cout;
initial begin
cin = 0;
a = 4\'h2;
b = 4\'h3;
end
initial begin
#1;
if (s !== 4\'h5) begin
$display("Error in trivial sum");
$finish;
end
$display ("PASSED");
end
fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) );
endmodule // test
|
// pr1960548
module test;
initial
$display("B`x");
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always if ( constant) statement ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
\tbegin
value1 = 0;
# 5 ;
if(value1 != 4\'d4)
$display("FAILED - always 3.1.5A always if ( constant) statement \
");
else
$display("PASSED");
\t $finish;
end
always if( 1\'b1) begin
# 1;
value1 = value1 + 1;
end
endmodule
|
module main;
parameter [15:0] a = 16\'h8421;
reg [3:0] b, c;
reg pass;
always @* begin
b = a[c+:4];
// $display($time, " c: %d, b: %h", c, b);
end
initial begin
pass = 1\'b1;
c = 0;
#1 if (b !== 4\'d1) begin
$display("FAILED: c = 0, expected 1, got %0d", b);
pass = 1\'b0;
end
#9 c = 4;
#1 if (b !== 4\'d2) begin
$display("FAILED: c = 4, expected 2, got %0d", b);
pass = 1\'b0;
end
#9 c = 8;
#1 if (b !== 4\'d4) begin
$display("FAILED: c = 8, expected 4, got %0d", b);
pass = 1\'b0;
end
#9 c = 12;
#1 if (b !== 4\'d8) begin
$display("FAILED: c = 12, expected 8, got %0d", b);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Check the basic parsing.
*/
/*
* Check the various timeunit/precision combinations (this is valid SV syntax).
*/
// A global timeunit and timeprecision are OK
timeunit 100us/1us;
// Both a local time unit and precision are OK.
module check_tup;
timeunit 10us/10us;
endmodule
/*
* Now do the same with repeat declarations (this is valid SV syntax).
*/
// A global timeunit and timeprecision are OK
timeunit 100us/1us;
// Both a local time unit and precision are OK.
module check_tup_d;
timeunit 10us/10us;
timeunit 10us/10us;
timeunit 10us;
timeprecision 10us;
endmodule
/*
* Now check all the valid timeunit and time precision values.
*/
module check_100s;
timeunit 100s / 100s;
endmodule
module check_10s;
timeunit 10s / 10s;
endmodule
module check_1s;
timeunit 1s / 1s;
endmodule
module check_100ms;
timeunit 100ms / 100ms;
endmodule
module check_10ms;
timeunit 10ms / 10ms;
endmodule
module check_1ms;
timeunit 1ms / 1ms;
endmodule
module check_100us;
timeunit 100us / 100us;
endmodule
module check_10us;
timeunit 10us / 10us;
endmodule
module check_1us;
timeunit 1us / 1us;
endmodule
module check_100ns;
timeunit 100ns / 100ns;
endmodule
module check_10ns;
timeunit 10ns / 10ns;
endmodule
module check_1ns;
timeunit 1ns / 1ns;
endmodule
module check_100ps;
timeunit 100ps / 100ps;
endmodule
module check_10ps;
timeunit 10ps / 10ps;
endmodule
module check_1ps;
timeunit 1ps / 1ps;
endmodule
module check_100fs;
timeunit 100fs / 100fs;
endmodule
module check_10fs;
timeunit 10fs / 10fs;
endmodule
module check_1fs;
timeunit 1fs / 1fs;
endmodule
module check1;
initial begin
$printtimescale(check_100s);
$printtimescale(check_10s);
$printtimescale(check_1s);
$printtimescale(check_100ms);
$printtimescale(check_10ms);
$printtimescale(check_1ms);
$printtimescale(check_100us);
$printtimescale(check_10us);
$printtimescale(check_1us);
$printtimescale(check_100ns);
$printtimescale(check_10ns);
$printtimescale(check_1ns);
$printtimescale(check_100ps);
$printtimescale(check_10ps);
$printtimescale(check_1ps);
$printtimescale(check_100fs);
$printtimescale(check_10fs);
$printtimescale(check_1fs);
$display("");
$printtimescale(check_tup);
$printtimescale(check_tup_d);
end
endmodule
|
module example;
task simple_task;
input in;
output out;
begin
out = in;
end
endtask
reg x = 0;
initial begin
simple_task(x,x,x);
$finish;
end
endmodule
|
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