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/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: udp_lfsr.v,v 1.1 2001/10/27 23:38:29 sib4 Exp $
module test_lfsr;
reg cp;
reg\t in;
wire out;
reg\t reset;
lfsr sr(cp, reset, in, out);
reg\t errors;
initial errors = 0;
integer i;
initial
begin
in = 0;
\tcp = 0;
\t#2 reset = 1;
\t#2 reset = 0;
\t#1;
\tfor (i=0; i<512; i=i+1)
\t #5 cp = ~cp;
in = 0;
\tcp = 0;
\t#2 reset = 1;
\t#2 reset = 0;
\t#1;
\tfor (i=0; i<512; i=i+1)
\t #5 cp <= ~cp;
\t#5;
\tif (errors == 0)
\t $display("PASSED");
\t#10 $finish;
end
reg [7:0] here;
reg [7:0] next;
reg [7:0] old;
reg [7:0] new;
always @(reset)
if (reset)
begin
\t here = 1;
\t #1;
\t old = {out, sr.s};
\t if (old === here)
\t begin
\t $display("%b RESET", old);
\t end
\t else
\t begin
\t $display("%b RESET FAILED: expect %b", old, here);
\t errors = 1;
\t end
end
always
begin
\t@(posedge cp) old = {out, sr.s};
\tnext = {here[6:0], ^(here & sr.P) ^ in};
\t@(negedge cp) new = {out, sr.s};
\tif (old != here || new !== next)
\t begin
\t $display("%b->%b FAILED: expect %b->%b", old, new, here, next);
\t errors = 1;
\t end
\telse
\t begin
\t $display("%b->%b", old, new);
\t end
\there = next;
end
endmodule
module lfsr (clk, reset, in, out);
parameter\t P = 8\'b 1101_1001;
input\t clk;
input\t reset;
input\t in;
output\t out;
wire [6:0]\t s;
wire\t\t i = ^{P & {out,s}} ^ in;
jkff ff1 (s[0], clk, i, ~i, reset, 0);
jkff ff2 (s[1], clk, s[0], ~s[0], 0, reset);
jkff ff3 (s[2], clk, s[1], ~s[1], 0, reset);
jkff ff4 (s[3], clk, s[2], ~s[2], 0, reset);
jkff ff8 (out, clk, s[6], ~s[6], 0, reset);
jkff ff7 (s[6], clk, s[5], ~s[5], 0, reset);
jkff ff6 (s[5], clk, s[4], ~s[4], 0, reset);
jkff ff5 (s[4], clk, s[3], ~s[3], 0, reset);
endmodule
primitive jkff(q, cp, j, k, s, r);
output q;
input cp, j, k, s, r;
reg\t q;
table
// (cp) j k s r : q : q ;
? ? ? (?0) 0 : ? : - ;
? ? ? 0 (?0) : ? : - ;
? * ? 0 0 : ? : - ;
? ? * 0 0 : ? : - ;
? ? ? 1 0 : ? : 1 ;
? ? ? 0 1 : ? : 0 ;
? ? ? x 0 : 1 : 1 ;
? ? ? 0 x : 0 : 0 ;
(?0) ? ? 0 0 : ? : - ;
(1x) ? ? 0 0 : ? : - ;
(?1) 0 ? 0 0 : 0 : 0 ;
(?1) ? 0 0 0 : 1 : 1 ;
(0x) 0 ? 0 0 : 0 : 0 ;
(0x) ? 0 0 0 : 1 : 1 ;
(01) 1 ? 0 0 : 0 : 1 ;
(01) ? 1 0 0 : 1 : 0 ;
(01) 1 0 0 0 : x : 1 ;
(01) 0 1 0 0 : x : 0 ;
endtable
endprimitive
|
// pr1784984
module signed_test;
reg [31:0] a;
initial begin
a = (32\'h80000000);
a = a / 2;
$display ("Current Value of a = %h", a);
if (a !== 32\'h40000000) begin
\t $display("FAILED");
\t $finish;
end
a = a * 2;
$display("Current value of a = %h", a);
if (a !== 32\'h80000000) begin
\t $display("FAILED");
\t $finish;
end
a = (32\'h80000000)/2;
$display ("Current Value of a = %h", a);
if (a !== 32\'h40000000) begin
\t $display("FAILED");
\t $finish;
end
a = (32\'h40000000)*2;
$display ("Current Value of a = %h", a);
if (a !== 32\'h80000000) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // signed_test
|
module partsel(inout wire [1:0] part);
assign part = 2\'bz;
endmodule
module test();
wire [3:0] full;
partsel sel(full[2:1]);
initial begin
#1 $peek(full[2:1]);
#0 $display("display : %b %b", sel.part, full);
#1 $force(full[2:1]);
#1 $peek(full[2:1]);
#0 $display("display : %b %b", sel.part, full);
#1 $release(full[2:1]);
#0 $display("display : %b %b", sel.part, full);
#1 $force(full[2:1]);
#1 $peek(full[2:1]);
#0 $display("display : %b %b", sel.part, full);
#1 $poke(full[2:1]);
#1 $peek(full[2:1]);
#0 $display("display : %b %b", sel.part, full);
#1 $release(full[2:1]);
#0 $display("display : %b %b", sel.part, full);
#1 $poke(full[2:1]);
#1 $peek(full[2:1]);
#0 $display("display : %b %b", sel.part, full);
end
endmodule
|
// Test implicit casts during net declaration assignments.
`ifdef __ICARUS__
`define SUPPORT_REAL_NETS_IN_IVTEST
`define SUPPORT_TWO_STATE_NETS_IN_IVTEST
`endif
module implicit_cast();
real src_r;
bit unsigned [7:0] src_u2;
bit signed [7:0] src_s2;
logic unsigned [7:0] src_u4;
logic signed [7:0] src_s4;
logic unsigned [7:0] src_ux;
logic signed [7:0] src_sx;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
wire real dst1_r = src_r;
wire real dst2_r = src_u2;
wire real dst3_r = src_s2;
wire real dst4_r = src_u4;
wire real dst5_r = src_s4;
wire real dst6_r = src_ux;
wire real dst7_r = src_sx;
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
wire bit unsigned [3:0] dst1_u2s = src_r;
wire bit unsigned [3:0] dst2_u2s = src_u2;
wire bit unsigned [3:0] dst3_u2s = src_s2;
wire bit unsigned [3:0] dst4_u2s = src_u4;
wire bit unsigned [3:0] dst5_u2s = src_s4;
wire bit unsigned [3:0] dst6_u2s = src_ux;
wire bit unsigned [3:0] dst7_u2s = src_sx;
wire bit signed [3:0] dst1_s2s = src_r;
wire bit signed [3:0] dst2_s2s = src_u2;
wire bit signed [3:0] dst3_s2s = src_s2;
wire bit signed [3:0] dst4_s2s = src_u4;
wire bit signed [3:0] dst5_s2s = src_s4;
wire bit signed [3:0] dst6_s2s = src_ux;
wire bit signed [3:0] dst7_s2s = src_sx;
wire bit unsigned [11:0] dst1_u2l = src_r;
wire bit unsigned [11:0] dst2_u2l = src_u2;
wire bit unsigned [11:0] dst3_u2l = src_s2;
wire bit unsigned [11:0] dst4_u2l = src_u4;
wire bit unsigned [11:0] dst5_u2l = src_s4;
wire bit unsigned [11:0] dst6_u2l = src_ux;
wire bit unsigned [11:0] dst7_u2l = src_sx;
wire bit signed [11:0] dst1_s2l = src_r;
wire bit signed [11:0] dst2_s2l = src_u2;
wire bit signed [11:0] dst3_s2l = src_s2;
wire bit signed [11:0] dst4_s2l = src_u4;
wire bit signed [11:0] dst5_s2l = src_s4;
wire bit signed [11:0] dst6_s2l = src_ux;
wire bit signed [11:0] dst7_s2l = src_sx;
`endif
wire logic unsigned [3:0] dst1_u4s = src_r;
wire logic unsigned [3:0] dst2_u4s = src_u2;
wire logic unsigned [3:0] dst3_u4s = src_s2;
wire logic unsigned [3:0] dst4_u4s = src_u4;
wire logic unsigned [3:0] dst5_u4s = src_s4;
wire logic unsigned [3:0] dst6_u4s = src_ux;
wire logic unsigned [3:0] dst7_u4s = src_sx;
wire logic signed [3:0] dst1_s4s = src_r;
wire logic signed [3:0] dst2_s4s = src_u2;
wire logic signed [3:0] dst3_s4s = src_s2;
wire logic signed [3:0] dst4_s4s = src_u4;
wire logic signed [3:0] dst5_s4s = src_s4;
wire logic signed [3:0] dst6_s4s = src_ux;
wire logic signed [3:0] dst7_s4s = src_sx;
wire logic unsigned [11:0] dst1_u4l = src_r;
wire logic unsigned [11:0] dst2_u4l = src_u2;
wire logic unsigned [11:0] dst3_u4l = src_s2;
wire logic unsigned [11:0] dst4_u4l = src_u4;
wire logic unsigned [11:0] dst5_u4l = src_s4;
wire logic unsigned [11:0] dst6_u4l = src_ux;
wire logic unsigned [11:0] dst7_u4l = src_sx;
wire logic signed [11:0] dst1_s4l = src_r;
wire logic signed [11:0] dst2_s4l = src_u2;
wire logic signed [11:0] dst3_s4l = src_s2;
wire logic signed [11:0] dst4_s4l = src_u4;
wire logic signed [11:0] dst5_s4l = src_s4;
wire logic signed [11:0] dst6_s4l = src_ux;
wire logic signed [11:0] dst7_s4l = src_sx;
bit failed;
initial begin
failed = 0;
src_r = -7;
src_u2 = 7;
src_s2 = -7;
src_u4 = 7;
src_s4 = -7;
src_ux = 8\'bx0z00111;
src_sx = 8\'bx0z00111;
#1;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
$display("cast to real");
$display("%g", dst1_r); if (dst1_r != -7.0) failed = 1;
$display("%g", dst2_r); if (dst4_r != 7.0) failed = 1;
$display("%g", dst3_r); if (dst5_r != -7.0) failed = 1;
$display("%g", dst4_r); if (dst2_r != 7.0) failed = 1;
$display("%g", dst5_r); if (dst3_r != -7.0) failed = 1;
$display("%g", dst6_r); if (dst6_r != 7.0) failed = 1;
$display("%g", dst7_r); if (dst7_r != 7.0) failed = 1;
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
$display("cast to small unsigned bit");
$display("%d", dst1_u2s); if (dst1_u2s !== 4\'d9) failed = 1;
$display("%d", dst2_u2s); if (dst4_u2s !== 4\'d7) failed = 1;
$display("%d", dst3_u2s); if (dst5_u2s !== 4\'d9) failed = 1;
$display("%d", dst4_u2s); if (dst2_u2s !== 4\'d7) failed = 1;
$display("%d", dst5_u2s); if (dst3_u2s !== 4\'d9) failed = 1;
$display("%d", dst6_u2s); if (dst6_u2s !== 4\'d7) failed = 1;
$display("%d", dst7_u2s); if (dst7_u2s !== 4\'d7) failed = 1;
$display("cast to small signed bit");
$display("%d", dst1_s2s); if (dst1_s2s !== -4\'sd7) failed = 1;
$display("%d", dst2_s2s); if (dst4_s2s !== 4\'sd7) failed = 1;
$display("%d", dst3_s2s); if (dst5_s2s !== -4\'sd7) failed = 1;
$display("%d", dst4_s2s); if (dst2_s2s !== 4\'sd7) failed = 1;
$display("%d", dst5_s2s); if (dst3_s2s !== -4\'sd7) failed = 1;
$display("%d", dst6_s2s); if (dst6_s2s !== 4\'sd7) failed = 1;
$display("%d", dst7_s2s); if (dst7_s2s !== 4\'sd7) failed = 1;
$display("cast to large unsigned bit");
$display("%d", dst1_u2l); if (dst1_u2l !== 12\'d4089) failed = 1;
$display("%d", dst2_u2l); if (dst4_u2l !== 12\'d7) failed = 1;
$display("%d", dst3_u2l); if (dst5_u2l !== 12\'d4089) failed = 1;
$display("%d", dst4_u2l); if (dst2_u2l !== 12\'d7) failed = 1;
$display("%d", dst5_u2l); if (dst3_u2l !== 12\'d4089) failed = 1;
$display("%b", dst6_u2l); if (dst6_u2l !== 12\'b000000000111) failed = 1;
$display("%b", dst7_u2l); if (dst7_u2l !== 12\'b000000000111) failed = 1;
$display("cast to large signed bit");
$display("%d", dst1_s2l); if (dst1_s2l !== -12\'sd7) failed = 1;
$display("%d", dst2_s2l); if (dst4_s2l !== 12\'sd7) failed = 1;
$display("%d", dst3_s2l); if (dst5_s2l !== -12\'sd7) failed = 1;
$display("%d", dst4_s2l); if (dst2_s2l !== 12\'sd7) failed = 1;
$display("%d", dst5_s2l); if (dst3_s2l !== -12\'sd7) failed = 1;
$display("%b", dst6_s2l); if (dst6_s2l !== 12\'b000000000111) failed = 1;
$display("%b", dst7_s2l); if (dst7_s2l !== 12\'b000000000111) failed = 1;
`endif
$display("cast to small unsigned logic");
$display("%d", dst1_u4s); if (dst1_u4s !== 4\'d9) failed = 1;
$display("%d", dst2_u4s); if (dst4_u4s !== 4\'d7) failed = 1;
$display("%d", dst3_u4s); if (dst5_u4s !== 4\'d9) failed = 1;
$display("%d", dst4_u4s); if (dst2_u4s !== 4\'d7) failed = 1;
$display("%d", dst5_u4s); if (dst3_u4s !== 4\'d9) failed = 1;
$display("%d", dst6_u4s); if (dst6_u4s !== 4\'d7) failed = 1;
$display("%d", dst7_u4s); if (dst7_u4s !== 4\'d7) failed = 1;
$display("cast to small signed logic");
$display("%d", dst1_s4s); if (dst1_s4s !== -4\'sd7) failed = 1;
$display("%d", dst2_s4s); if (dst4_s4s !== 4\'sd7) failed = 1;
$display("%d", dst3_s4s); if (dst5_s4s !== -4\'sd7) failed = 1;
$display("%d", dst4_s4s); if (dst2_s4s !== 4\'sd7) failed = 1;
$display("%d", dst5_s4s); if (dst3_s4s !== -4\'sd7) failed = 1;
$display("%d", dst6_s4s); if (dst6_s4s !== 4\'sd7) failed = 1;
$display("%d", dst7_s4s); if (dst7_s4s !== 4\'sd7) failed = 1;
$display("cast to large unsigned logic");
$display("%d", dst1_u4l); if (dst1_u4l !== 12\'d4089) failed = 1;
$display("%d", dst2_u4l); if (dst4_u4l !== 12\'d7) failed = 1;
$display("%d", dst3_u4l); if (dst5_u4l !== 12\'d4089) failed = 1;
$display("%d", dst4_u4l); if (dst2_u4l !== 12\'d7) failed = 1;
$display("%d", dst5_u4l); if (dst3_u4l !== 12\'d4089) failed = 1;
$display("%b", dst6_u4l); if (dst6_u4l !== 12\'b0000x0z00111) failed = 1;
$display("%b", dst7_u4l); if (dst7_u4l !== 12\'bxxxxx0z00111) failed = 1;
$display("cast to large signed logic");
$display("%d", dst1_s4l); if (dst1_s4l !== -12\'sd7) failed = 1;
$display("%d", dst2_s4l); if (dst4_s4l !== 12\'sd7) failed = 1;
$display("%d", dst3_s4l); if (dst5_s4l !== -12\'sd7) failed = 1;
$display("%d", dst4_s4l); if (dst2_s4l !== 12\'sd7) failed = 1;
$display("%d", dst5_s4l); if (dst3_s4l !== -12\'sd7) failed = 1;
$display("%b", dst6_s4l); if (dst6_s4l !== 12\'b0000x0z00111) failed = 1;
$display("%b", dst7_s4l); if (dst7_s4l !== 12\'bxxxxx0z00111) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test ();
generate
if (1) begin
initial begin : a
integer i;
i=0;
\t $display("PASSED");
end
end
endgenerate
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate defparam
module main ();
reg clock;
reg q;
reg reset;
reg error;
always @(posedge clock or posedge reset)
begin : FF
# 2;
if(reset)
q <= 0;
else
q <= ~q;
end
initial
begin
// Set reset to init f/f.
error = 0;
clock = 0;
reset = 1;
#4 ;
if(q != 1\'b0)
begin
$display("FAILED - disable3.6A - Flop didn\'t clear on clock & reset");
error = 1;
end
reset = 1\'b0;
clock = 1\'b1;
# 3;
if(q != 1\'b1)
begin
$display("FAILED - disable3.6A - Flop didn\'t set on clock");
error = 1;
end
clock = 1\'b0;
# 3;
clock = 1\'b1;\t// Now cause the toggle edge
# 1;
disable FF;\t\t// And disable the toggle event
# 2;
if(q != 1\'b1)
begin
$display("FAILED - disable3.6A - Disable didn\'t stop FF toggle");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
module test;
reg [31:0] src;
wire [7:0] tmp;
subbuf U1 (.out(tmp), .in(src));
wire [31:0] dst = {24\'h00_00_00, tmp};
initial begin
src = 32\'h11_22_33_44;
#1 if (dst !== 32\'h00_00_00_bb) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule
module subbuf (output [31:0] out, input[31:0]in);
assign out = ~in;
endmodule // subbuf
|
// Check that declaring a real typed variable for a signal that was previously
// declared as a non-ANSI task port is an error. Even if the types for both
// declarations are the same.
module test;
task t;
output real x;
real x;
$display("FAILED");
endtask
real y;
initial t(y);
endmodule
|
module main;
parameter CACHE_RAM = 128;
parameter ADR_WIDTH = 7;
reg [31:0] buff[0:CACHE_RAM], data_o, data_i;
reg [ADR_WIDTH-1:0] addr;
reg\t clk, rst, wr;
(* ivl_synthesis_on *)
always @(posedge clk)
if (wr) buff[addr] <= data_i;
(* ivl_synthesis_on *)
always @(posedge clk or posedge rst)
begin
\tif (rst)
\t data_o <= 32\'h0;
\telse if (wr)
\t data_o <= data_i;
\telse
\t data_o <= buff[addr];
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
rst = 0;
wr = 1;
for (addr = 0 ; addr < 64 ; addr = addr+1) begin
\t data_i <= addr;
\t #1 clk = 1;
\t #1 clk = 0;
\t if (data_o !== data_i) begin
\t $display("FAILED -- write addr=0x%h, data_o=%h", addr, data_o);
\t $finish;
\t end
end
wr = 0;
data_i = 32\'hx;
for (addr = 0 ; addr < 64 ; addr = addr+1) begin
\t #1 clk = 1;
\t #1 clk = 0;
\t if (data_o !== addr) begin
\t $display("FAILED -- read addr=0x%h, data_o=%h", addr, data_o);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
module test();
localparam [7:0] dly1 = 1;
wire [7:0] dly2 = 2;
reg [7:0] dly3 = 3;
reg i;
wire [6:1] o;
buf #(dly1, dly2) buf1(o[1], i);
buf #(dly2, dly1) buf2(o[2], i);
buf #(dly1, dly3) buf3(o[3], i);
buf #(dly3, dly1) buf4(o[4], i);
buf #(dly2, dly3+1) buf5(o[5], i);
buf #(4, 2) buf6(o[6], i);
function check(input o1, input o2, input o3, input o4, input o5, input o6);
begin
check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3)
&& (o[4] == o4) && (o[5] == o5) && (o[6] == o6);
end
endfunction
reg failed = 0;
initial begin
#1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);
i = 1\'b1;
#0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'bx, 1\'b1, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'bx, 1\'b1, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1;
i = 1\'b0;
#0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'b0, 1\'b1, 1\'b0, 1\'b1, 1\'b1)) failed = 1;
#1; #0 if (!check(1\'b0, 1\'b0, 1\'b1, 1\'b0, 1\'b1, 1\'b0)) failed = 1;
#1; #0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b1, 1\'b0)) failed = 1;
#1; #0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0)) failed = 1;
i = 1\'bx;
#0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'b0, 1\'b0)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
i = 1\'bz;
#0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz)) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* What matters here is the size of the display, which should reflect
* the size of 20, which is written with an _ character. Weird, but
* legal.
*/
module underscore_in_size;
initial
\t$display ( "%d %d %d %d", 2_0\'b0, 2_0\'d0, 2_0\'o0, 2_0\'h0 );
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue = @ (event_expression) boolean_expr
//
module main ;
reg [3:0] value1 ;
reg event_var ;
initial
begin
# 2 ;
value1 = 5\'h 0 ;
# 3 ;
event_var = 1\'b0 ;
# 2 ;
value1 = 5\'h 0 ;
# 3 ;
event_var = 1\'b1 ;
#5 ;
end
initial
begin\t\t\t// Should be xxxx at initial time
if(value1 !== 4\'bxxxx)
\t$display("FAILED - always reg_lvalue = @ (event_expression) boolean_expr\
");
# 6 ;
if(value1 != 4\'h1)\t// Time 5 should see a change of 0 to 1
\t$display("FAILED - always reg_lvalue = @ (event_expression) boolean_expr\
");
# 5 ;
if(value1 != 4\'h1)\t// Time 5 should see a change of 0 to 1
\t$display("FAILED - always reg_lvalue = @ (event_expression) boolean_expr\
");
begin
$display("PASSED\
");
$finish ;
end
end
always value1 = @ (event_var) 1\'b1 && 1\'b1 ;
endmodule
|
// Eleven basic tests in here:
// 1. shortint must be initialised before any initial or always block
// 2. assignments to (unsigned) shortint with random numbers
// 3. assignments to (unsigned) shortint with random values including X and Z
// 4. converting unsigned integers to unsigned shortint
// 5. converting signed integers to unsigned shortint
// 6. converting integers including X and Z states to unsigned shortint
// 7. trying unsigned sums (procedural, function, task and module)
// 8. trying unsigned mults (procedural, function and task)
// 9. trying relational operators
// 10. smaller signed numbers to unsigned shortint (signed extension)
// 11. trying some concatenations from bytes to shortints
module mu_add (input shortint unsigned a, b, output shortint unsigned sc, ss);
assign sc = a + b;
always @(a, b) ss = a + b;
endmodule
module main;
parameter N_REPS = 500; // repetition with random numbers
parameter XZ_REPS = 500; // repetition with \'x \'z values
parameter UMAX = 65536;
parameter MAX8 = 256;
parameter LEN = 16;
// variables used as golden references
reg unsigned [LEN-1:0] ar; // holds numbers
reg unsigned [LEN-1:0] ar_xz; // holds \'x and/or \'z in random positions
reg unsigned [LEN-1:0] ar_expected;
integer unsigned ui;
integer signed si;
reg signed [LEN/2-1:0] slice;
// type assumed tested before
byte unsigned pt1, pt2;
// types to be tested
shortint unsigned bu; // holds numbers
shortint unsigned bu_xz; // \'x and \'z are attempted on this
shortint unsigned bresult; // hold results from sums and mults
shortint unsigned mcaresult; // wired to a module instance
shortint unsigned mabresult; // also wired to a module instance
integer i;
// continuous assigments
// type LHS type RHS
// --------- ---------
// shortint 4-value logic
assign bu = ar;
assign bu_xz = ar_xz;
// module instantiation
mu_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) );
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if (bu !== 16\'b0 || bu_xz !== 16\'b0 || bresult !== 16\'b0 || mcaresult !== 16\'b0 || mabresult !== 16\'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// driving shortint type with unsigned random numbers from a variable
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = {$random} % UMAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to shortint: %b", bu);
$finish;
end
end
# 1;
// attempting to drive variables having \'x \'z values into type unsigned shortint
// \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
ar = {$random} % UMAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0
begin
$display ("FAILED - incorrect assigment to shortint (when \'x \'z): %b", bu);
$finish;
end
end
// converting unsigned integers to unsigned shortint
// truncation expected (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ui = {$random} % UMAX;
#1;
force bu = ui;
#1;
if (bu !== ui[LEN-1:0])
begin
$display ("FAILED - incorrect truncation from unsigned integer to shortint: %b", bu);
$finish;
end
end
release bu;
// converting signed integers to unsigned shortints
// truncation expected (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
si = $random % UMAX/2-1;
#1;
force bu = si;
#1;
if (bu !== si[LEN-1:0])
begin
$display ("FAILED - incorrect truncation from signed integer to shortint: %b mismatchs %b", bu, si[LEN-1:0]);
$finish;
end
end
release bu;
// converting integers having \'x \'z values into type unsigned shortint
// \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM)
// truncation and coercion to zero expected
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
si = $random;
ar_xz = xz_inject (si[LEN-1:0]);
si = {si[31:LEN], ar_xz};
ar_expected = xz_expected (ar_xz);
#1;
force bu_xz = si;
#1;
if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0
begin
$display ("FAILED - incorrect conversion from integer (with \'x \'z) to shortint: %b mismatchs %b", bu_xz, ar_expected);
$finish;
end
end
release bu_xz;
// trying unsigned sums
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = {$random} % UMAX;
ar_xz = {$random} % UMAX;
#1;
bresult = bu + bu_xz;
#1;
if ( bresult !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned shortints: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz));
$finish;
end
// invoking shortint sum function
if ( fu_sum (bu, bu_xz) !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned shortint in function");
$finish;
end
// invoking byte sum task
tu_sum (bu, bu_xz, bresult);
if ( bresult !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned shortint in task: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz));
$finish;
end
// checking shortint sum from module
if ( mcaresult !== u_sum(ar, ar_xz) || mabresult !== u_sum(ar, ar_xz))
begin
$display ("FAILED - incorrect addition of unsigned shortint from module");
$finish;
end
end
// trying unsigned mults
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = ({$random} % UMAX) << LEN/2;
ar_xz = ({$random} % UMAX) << (LEN/2 - 1);
#1;
bresult = bu * bu_xz; // truncated multiplication
#1;
if ( bresult !== uh_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect multiplication of unsigned shortints (truncated)");
$finish;
end
#1;
pt1 = {$random};
pt2 = {$random};
#1;
bresult = pt1 * pt2; // shortint = byte x byte
#1;
if ( bresult !== u_mul(pt1, pt2) )
begin
$display ("FAILED - incorrect multiplication of unsigned shortints for bytes inputs");
$finish;
end
// invoking shortint mult function (byte*byte)
if ( fu_mul (pt1, pt2) !== u_mul(pt1, pt2) )
begin
$display ("FAILED - incorrect product of unsigned bytes for a function returning unsigned shortint");
$finish;
end
// invoking shortint mult task (byte*byte)
tu_mul (pt1, pt2, bresult);
if ( bresult !== u_mul(pt1, pt2) )
begin
$display ("FAILED - incorrect product of unsigned bytes in task returning unsigned shortint");
$finish;
end
end
// trying relational operators
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = {$random} % UMAX;
ar_xz = {$random} % UMAX;
#1;
if ( (bu < bu_xz ) !== (ar < ar_xz) )
begin
$display ("FAILED - incorrect \'less than\' on unsigned shortints");
$finish;
end
if ( (bu <= bu_xz ) !== (ar <= ar_xz) )
begin
$display ("FAILED - incorrect \'less than or equal\' on unsigned shortints");
$finish;
end
if ( (bu > bu_xz ) !== (ar > ar_xz) )
begin
$display ("FAILED - incorrect \'greater than\' on unsigned shortints");
$finish;
end
if ( (bu >= bu_xz ) !== (ar >= ar_xz) )
begin
$display ("FAILED - incorrect \'greater than or equal\' than on unsigned shortints");
$finish;
end
if ( (bu == bu_xz ) !== (ar == ar_xz) )
begin
$display ("FAILED - incorrect \'equal to\' on unsigned shortints");
$finish;
end
if ( (bu != bu_xz ) !== (ar != ar_xz) )
begin
$display ("FAILED - incorrect \'not equal to\' on unsigned shortints");
$finish;
end
end
# 1;
// signed small number to unsigned shorint
for (i = 0; i < (1<<LEN/2); i = i+1)
begin
#1;
slice = $random % \'h7f;
force bu = slice;
ar = slice;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect signed extend to unsigned shortint");
$finish;
end
end
release bu;
// trying concatenations
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
pt1 = {$random} % MAX8;
pt2 = {$random} % MAX8;
#1;
bresult = {pt1, pt2};
#1;
if ( bresult[15:8] !== pt1 || bresult[7:0] !== pt2)
begin
$display ("FAILED - incorrect concatenation of unsigned shortints");
$finish;
end
end
#1;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [LEN-1:0] xz_inject (input unsigned [LEN-1:0] value);
integer i, temp;
begin
temp = {$random} % UMAX;
for (i=0; i<LEN; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random % UMAX;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [LEN-1:0] xz_expected (input unsigned [LEN-1:0] value_xz);
integer i;
begin
for (i=0; i<LEN; i=i+1)
begin
if (value_xz[i] === 1\'bx || value_xz[i] === 1\'bz )
value_xz[i] = 1\'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
// unsigned 4-value sum
function unsigned [LEN-1:0] u_sum (input unsigned [LEN-1:0] a, b);
u_sum = a + b;
endfunction
// unsigned shortint sum as function
function shortint unsigned fu_sum (input shortint unsigned a, b);
fu_sum = a + b;
endfunction
// unsigned shortint sum as task
task tu_sum (input shortint unsigned a, b, output shortint unsigned c);
c = a + b;
endtask
// unsigned 4-value truncated mults
function unsigned [LEN-1:0] uh_mul (input unsigned [LEN-1:0] a, b);
uh_mul = a * b;
endfunction
// unsigned 4-value mults
function unsigned [LEN-1:0] u_mul (input unsigned [LEN/2-1:0] a, b);
u_mul = a * b;
endfunction
// unsigned shortint mult as function
function shortint unsigned fu_mul (input byte unsigned a, b);
fu_mul = a * b;
endfunction
// unsigned shortint mult as task
task tu_mul (input byte unsigned a, b, output shortint unsigned c);
c = a * b;
endtask
endmodule
|
// Check that it is not possible to override parameters in generate blocks
module test;
generate
genvar i;
for (i = 0; i < 2; i = i + 1) begin : loop
parameter A = i;
reg [A:0] r = A+1;
end
endgenerate
defparam loop[0].A = 10;
defparam loop[1].A = 20;
endmodule
|
module top;
initial begin : named_begin
$display("FAILED");
end : wrong_name
endmodule
|
// This program is about testing that the value ranges parse and work for
// integer parameters.
module test(input wire in);
parameter real foo = 0.0 from [-10.0 : 10.0] exclude [1:2);
parameter real bar = 0 from (-inf:0];
initial begin
$display("foo = %f", foo);
$display("PASSED");
$finish;
end
endmodule // test
module main;
reg rrr = 0;
test #(.foo(2), .bar(-5.0)) dut (rrr);
endmodule // main
|
`ifdef __ICARUS__
`define SUPPORT_TWO_STATE_NETS_IN_IVTEST
`endif
module test();
int x2;
int z2;
function int y2(int x);
endfunction
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
wire int w2 = y2(x2);
`else
wire integer w2 = 0;
`endif
integer x4;
integer z4;
function integer y4(integer x);
endfunction
wire integer w4 = y4(x4);
initial begin
#1;
$display(w2);
z2 = y2(x2);
$display(z2);
$display(w4);
z4 = y4(x4);
$display(z4);
if (w2 === 0 && z2 === 0 && w4 === \'bx && z4 === \'bx)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
package test_pkg;
class uvm_phase;
function void print(string str);
$display(str);
endfunction
endclass : uvm_phase
class uvm_component;
virtual function void build_phase(uvm_phase phase);
phase.print("building");
endfunction : build_phase
virtual task run_phase(uvm_phase phase);
phase.print("running");
endtask : run_phase
virtual task run_all();
uvm_phase p0;
p0 = new();
this.build_phase(p0);
this.run_phase(p0);
endtask : run_all
endclass : uvm_component
endpackage : test_pkg
module m;
import test_pkg::*;
uvm_component u0;
initial begin : test
u0 = new();
u0.run_all();
end : test
endmodule : m
|
task a_task (input int id);
$display("This is task %0d.", id);
endtask
// This should print the following:
// This is task 2.
// This is task 1.
module top;
initial begin
a_task(2);
a_task(1);
end
endmodule
|
module test();
// wire r;
a ua ( .r ( !r ));
endmodule
module a ( r );
input r;
endmodule
|
`begin_keywords "1364-2005"
module main;
wire [1:0] di;
reg [1:0] do;
reg\t dir;
wire [1:0] q;
sub dut(.Q({q[0],q[1]}), .Di(di), .Do(do), .dir(dir));
initial begin
dir = 0;
do = 2\'b10;
#1 if (q !== 2\'bzz) begin
\t $display("FAILED -- q=%b, dir=%b", q, dir);
\t $finish;
end
dir = 1;
#1 if (q !== 2\'b01) begin
\t $display("FAILED -- q=%b, dir=%b, do=%b", q, dir, do);
\t $finish;
end
if (di !== 2\'b10) begin
\t $display("FAILED -- di=%b, dir=%b, do=%b", di, dir, do);
\t $finish;
end
$display("PASSED");
end
endmodule // main
module sub(inout [1:0]Q,
\t output[1:0]Di,
\t input [1:0]Do,
\t input dir);
assign\t Di = Q;
assign\t Q = dir? Do : 2\'bzz;
endmodule // sub
`end_keywords
|
module automatic_task();
task automatic fill_array;
input [7:0] value;
reg [7:0] array[3:0];
event step;
fork
begin
#10 array[0] = value; ->step;
#10 array[1] = array[0]; ->step;
#10 array[2] = array[1]; ->step;
#10 array[3] = array[2]; ->step;
end
begin
@step $display(array[0], array[1], array[2], array[3]);
@step $display(array[0], array[1], array[2], array[3]);
@step $display(array[0], array[1], array[2], array[3]);
@step $display(array[0], array[1], array[2], array[3]);
end
join
endtask
initial #1 fill_array(1);
initial #2 fill_array(2);
endmodule
|
module test;
wire a;
reg [20:0] b;
assign a = ((b[20:4]) || (b[3] && b[2:0])) ? 1\'b0 : 1\'b1;
initial begin
b = 0;
#1 if (a !== 1\'b1) begin
\t $display("FAILED -- b=%h, a=%b", b, a);
\t $finish;
end
b = 8;
#1 if (a !== 1\'b1) begin
\t $display("FAILED -- b=%h, a=%b", b, a);
\t $finish;
end
b = 12;
#1 if (a !== 1\'b0) begin
\t $display("FAILED -- b=%h, a=%b", b, a);
\t $finish;
end
b = 16;
#1 if (a !== 1\'b0) begin
\t $display("FAILED -- b=%h, a=%b", b, a);
\t $finish;
end
$display("PASSED");
end
endmodule
|
//
// Author: Pawel Szostek ([email protected])
// Date: 01.08.2011
`timescale 1ns/1ps
module dummy_v( input [7:0] in, output reg [7:0] out);
assign out = {in[7], 7\'b1111111}; //there is no equivalent to vhdl\'s `others\'
endmodule
module stimulus (output reg [7:0] a);
parameter S = 20000;
int unsigned j,i;
initial begin
for(i=0; i<S; i=i+1) begin
#10;
a[7] <= inject();
a[6] <= inject();
a[5] <= inject();
a[4] <= inject();
a[3] <= inject();
a[2] <= inject();
a[1] <= inject();
a[0] <= inject();
end
end
function inject();
reg ret;
reg unsigned [3:0] temp;
temp[3:0] = $random % 16;
begin
if(temp >= 10)
ret = 1\'b1;
else if(temp >= 4)
ret = 1\'b0;
else if(temp >= 2)
ret = 1\'bx;
else
ret = 1\'b0;
inject = ret;
end
endfunction
endmodule
module main;
wire [7:0] i,o;
wire [7:0] veri;
dummy dummy_vhdl(i,o);
dummy_v dummy_verilog(i, veri);
stimulus stim(i);
always @(i) begin
#1;
if(o != veri) begin
$display("ERROR!");
$display("VERILOG: ", veri);
$display("VHDL: ", o);
$stop;
end
end
initial begin
#12000;
#10;
$display("PASSED");
//stop;
end
endmodule
|
// Copyright (c) 2014 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Tests accessing individual characters in a string
module string_index();
initial begin
int i;
string str = "that is a test string";
for(i = 0; i < $size(str); ++i)
begin
if(str[i] == "t")
str[i] = "w";
end
if(str != "whaw is a wesw swring")
begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
module dut(input EN, input I, inout O);
assign O = EN ? I : 1\'bz;
specify
(I => O) = (2);
(EN *> O) = (4);
endspecify
endmodule
module test();
reg EN;
reg I;
tri0 O;
dut dut(EN, I, O);
reg failed = 0;
initial begin
$monitor($time,,EN,,I,,O);
EN = 0;
#4;
#0 if (O !== 0) failed = 1;
#1 I = 1;
#1 EN = 1;
#3;
#0 if (O !== 0) failed = 1;
#1;
#0 if (O !== 1) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module top;
logic passed;
logic [7:0] value;
integer ones;
function automatic integer count_by_one(input integer start);
if (start) count_by_one = (value[start] ? 1 : 0) + count_ones(start-1);
else count_by_one = value[start] ? 1 : 0;
endfunction
function automatic integer count_ones(input integer start);
if (start) count_ones = (value[start] ? 1 : 0) + count_by_one(start-1);
else count_ones = value[start] ? 1 : 0;
endfunction
always_comb ones = count_ones(7);
initial begin
passed = 1\'b1;
value = 8\'b0000_0000;
#1;
if (ones !== 0) begin
$display("Expected 0, got %d", ones);
passed = 1\'b0;
end
value = 8\'b0011_1100;
#1;
if (ones !== 4) begin
$display("Expected 4, got %d", ones);
passed = 1\'b0;
end
value = 8\'b1011_1101;
#1;
if (ones !== 6) begin
$display("Expected 6, got %d", ones);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
module top;
reg pass = 1\'b1;
reg [1:0] rval = 2\'b10;
wire [1:0] wval = (wval > 0) ? 2\'b01 : 2\'b00;
// This works as follows:
// rlval starts are 0.0 which is not greater than 0.0 (false).
// This sets rlval to 2.0 which is greater than 0.0 (true).
// This then sets the value to 1.0 which is still true and stable.
wire real rlval = (rlval > 0.0) ? 1.0 : 2.0;
initial begin
#1;
if (rval != 2\'b10) begin
$display("FAILED initial value expected 2\'b10, got %b.", rval);
pass = 1\'b0;
end
if (wval !== 2\'b0x) begin
$display("FAILED net value expected 2\'b0x, got %b.", wval);
pass = 1\'b0;
end
if (rlval != 1.0) begin
$display("FAILED net real value expected 1.0, got %f.", rlval);
pass = 1\'b0;
end
#1 assign rval = (rval > 0) ? 2\'b01 : 2\'b00;
if (rval != 2\'b01) begin
$display("FAILED forced value expected 2\'b01, got %b.", rval);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module top;
wire [15:0] number =16\'h20;
wire shift_cmp = (number == (1 << 5));
initial begin
#1; // Make sure things are settled.
if (shift_cmp === 1\'b1) $display("PASSED");
else $display("FAILED, got %b expected 1\'b1", shift_cmp);
end
endmodule
|
module top();
reg pass = 1\'b1;
reg [31:0] in = \'bx;
reg signed [31:0] sin = \'bx;
wire [63:0] res;
wire signed [63:0] sres;
lower lwr(res, in);
slower slwr(sres, sin);
initial begin
#1;
if (res !== {32\'b0, 32\'bx}) begin
$display("FAILED: unsigned output (%b)", res);
pass = 1\'b0;
end
if (lwr.lout !== {32\'b0, 32\'bx}) begin
$display("FAILED: unsigned input (%b)", lwr.lout);
pass = 1\'b0;
end
if (sres !== 64\'bx) begin
$display("FAILED: signed output (%b)", sres);
pass = 1\'b0;
end
if (slwr.lout !== 64\'bx) begin
$display("FAILED: signed input (%b)", slwr.lout);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
module lower(lrtn, lin);
output [31:0] lrtn;
input [63:0] lin;
wire [63:0] lout = lin;
assign lrtn = lout[31:0];
endmodule
module slower(lrtn, lin);
output signed [31:0] lrtn;
input signed[63:0] lin;
wire signed [63:0] lout = lin;
assign lrtn = lout[31:0];
endmodule
|
//
// Copyright (c) 2000 Steve Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// for3.16A - Template 1 - for(val1=0; val1 <= expr ; val1 = val1 + 1) some_action
//
module pr1120 ();
wire [31:0] foo;
reg [31:0] bar;
// FAIL
assign foo[31:16] = (bar & 32\'hffffffff) >> 16;
// PASS
//assign foo[31:16] = bar >> 16;
initial
begin
bar = 32\'ha5a5_3f3f;
#100;
$display("foo[31:16] = %x bar = %x",foo[31:16],bar);
//if(foo[31:16]==((bar & 32\'hffffffff) >> 16))
if(foo[31:16] === 16\'ha5a5)
\t$display("PASS (%x)",foo[31:16]);
else
$display("FAIL (%x vs %x)",foo[31:16],((bar & 32\'hffffffff) >> 16));
$finish;
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Detect that b is declared as a scaler and a vector.
*/
module simple (a, b);
input [7:0] a;
output [7:0] b;
reg b;\t// Error here!
always @(a)
begin
b = a;
end
endmodule
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for concurrent assertion statements.
module vhdl_concurrent_assert_test;
vhdl_concurrent_assert dut();
// we do not need anything else here
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate module a(),b();
module foo(a);
output a;
wire a = 1\'b1 ;
endmodule
module main;
wire b;
foo foo1 (.a()),
foo2 (.a(b));
initial
if(!b)
$display("FAILED - 3.12C - Module with output only failed");
else
$display("PASSED");
endmodule // main
|
/*
* This module demonstrates the ability to use a defparam to control
* the instantation of an instance array, and to also control
* parameter values within the instance array.
*/
module main;
localparam wid = 5;
reg [wid-1:0] clk;
if (wid > 0) begin : D
dut xx (.clk(clk));
end
// This defparam sets the desired with of the U instance vector.
defparam main.D.xx.wid = wid;
// These defparams set parameters within U instances.
defparam main.D.xx.sub[0].U.number = 0;
defparam main.D.xx.sub[1].U.number = 1;
defparam main.D.xx.sub[2].U.number = 2;
defparam main.D.xx.sub[3].U.number = 3;
defparam main.D.xx.sub[4].U.number = 4;
initial begin
clk = 0;
#1 clk = 1;
while (clk != 0)
\t #1 clk = clk << 1;
$finish(0);
end
endmodule // main
module dut #(parameter wid = 1) (input [wid-1:0] clk);
genvar i;
for (i = 0 ; i < wid ; i = i+1) begin : sub
target U (.clk(clk[i]));
end
endmodule //
module target(input wire clk);
parameter number = 999;
always @(posedge clk)
$display("%m: number=%0d", number);
endmodule // target
|
// Check the power operator (compile time).
module top;
reg pass;
integer res;
initial begin
pass = 1\'b1;
// Check the constant ** with various arguments (table 5-6 1364-2005).
res = -3**\'bx;
if (res !== \'bx) begin
$display("Failed: constant -3**\'bx, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = -1**\'bx;
if (res !== \'bx) begin
$display("Failed: constant -1**\'bx, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = 0**\'bx;
if (res !== \'bx) begin
$display("Failed: constant 0**\'bx, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = 1**\'bx;
if (res !== \'bx) begin
$display("Failed: constant 1**\'bx, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = 3**\'bx;
if (res !== \'bx) begin
$display("Failed: constant 3**\'bx, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = \'bx**-3;
if (res !== \'bx) begin
$display("Failed: constant \'bx**-3, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = \'bx**-2;
if (res !== \'bx) begin
$display("Failed: constant \'bx**-2, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = \'bx**-1;
if (res !== \'bx) begin
$display("Failed: constant \'bx**-1, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = \'bx**0;
if (res !== \'bx) begin
$display("Failed: constant \'bx**0, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = \'bx**1;
if (res !== \'bx) begin
$display("Failed: constant \'bx**1, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = \'bx**2;
if (res !== \'bx) begin
$display("Failed: constant \'bx**2, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = \'bx**3;
if (res !== \'bx) begin
$display("Failed: constant \'bx**3, expected \'bx, got %0d", res);
pass = 1\'b0;
end
// Check the 1st line (rvalue is positive).
res = -3**3;
if (res !== -27) begin
$display("Failed: constant -3**3, expected -27, got %0d", res);
pass = 1\'b0;
end
res = -3**2;
if (res !== 9) begin
$display("Failed: constant -3**2, expected 9, got %0d", res);
pass = 1\'b0;
end
res = -1**3;
if (res !== -1) begin
$display("Failed: constant -1**3, expected -1, got %0d", res);
pass = 1\'b0;
end
res = -1**2;
if (res !== 1) begin
$display("Failed: constant -1**2, expected 1, got %0d", res);
pass = 1\'b0;
end
res = 0**3;
if (res !== 0) begin
$display("Failed: constant 0**3, expected 0, got %0d", res);
pass = 1\'b0;
end
res = 0**2;
if (res !== 0) begin
$display("Failed: constant 0**2, expected 0, got %0d", res);
pass = 1\'b0;
end
res = 1**3;
if (res !== 1) begin
$display("Failed: constant 1**3, expected 1, got %0d", res);
pass = 1\'b0;
end
res = 1**2;
if (res !== 1) begin
$display("Failed: constant 1**2, expected 1, got %0d", res);
pass = 1\'b0;
end
res = 3**3;
if (res !== 27) begin
$display("Failed: constant 3**3, expected 27, got %0d", res);
pass = 1\'b0;
end
res = 3**2;
if (res !== 9) begin
$display("Failed: constant 3**2, expected 9, got %0d", res);
pass = 1\'b0;
end
// Check the 2nd line (rvalue is zero).
res = -3**0;
if (res !== 1) begin
$display("Failed: constant -3**0, expected 1, got %0d", res);
pass = 1\'b0;
end
res = -2**0;
if (res !== 1) begin
$display("Failed: constant -2**0, expected 1, got %0d", res);
pass = 1\'b0;
end
res = -1**0;
if (res !== 1) begin
$display("Failed: constant -1**0, expected 1, got %0d", res);
pass = 1\'b0;
end
res = 0**0;
if (res !== 1) begin
$display("Failed: constant 0**0, expected 1, got %0d", res);
pass = 1\'b0;
end
res = 1**0;
if (res !== 1) begin
$display("Failed: constant 1**0, expected 1, got %0d", res);
pass = 1\'b0;
end
res = 2**0;
if (res !== 1) begin
$display("Failed: constant 2**0, expected 1, got %0d", res);
pass = 1\'b0;
end
res = 3**0;
if (res !== 1) begin
$display("Failed: constant 3**0, expected 1, got %0d", res);
pass = 1\'b0;
end
// Check the 3rd line (rvalue is negative).
res = -2**-3;
if (res !== 0) begin
$display("Failed: constant -2**-3, expected 0, got %0d", res);
pass = 1\'b0;
end
res = -2**-2;
if (res !== 0) begin
$display("Failed: constant -2**-2, expected 0, got %0d", res);
pass = 1\'b0;
end
res = -1**-3;
if (res !== -1) begin
$display("Failed: constant -1**-3, expected -1, got %0d", res);
pass = 1\'b0;
end
res = -1**-2;
if (res !== 1) begin
$display("Failed: constant -1**-2, expected 1, got %0d", res);
pass = 1\'b0;
end
res = 0**-3;
if (res !== \'bx) begin
$display("Failed: constant 0**-3, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = 0**-2;
if (res !== \'bx) begin
$display("Failed: constant 0**-2, expected \'bx, got %0d", res);
pass = 1\'b0;
end
res = 1**-3;
if (res !== 1) begin
$display("Failed: constant 1**-3, expected 1, got %0d", res);
pass = 1\'b0;
end
res = 1**-2;
if (res !== 1) begin
$display("Failed: constant 1**-2, expected 1, got %0d", res);
pass = 1\'b0;
end
res = 2**-3;
if (res !== 0) begin
$display("Failed: constant 2**-3, expected 0, got %0d", res);
pass = 1\'b0;
end
res = 2**-2;
if (res !== 0) begin
$display("Failed: constant 2**-2, expected 0, got %0d", res);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* part select in continuous assignment.
*/
`timescale 1ns/1ns
module main;
reg [3:0] src;
wire foo = src[3:1] == 3\'b101;
integer idx;
initial
begin
\tfor (idx = 0 ; idx < 16 ; idx = idx+1) begin
\t src = idx;
\t #1 if (foo !== (src[3:1] == 3\'b101)) begin
\t $display("FAILED -- src=%b, foo=%b", src, foo);
\t $finish;
\t end
\tend
\t$display("PASSED");
end // initial begin
endmodule
|
module top;
reg a;
reg q, d;
reg clk;
event foo;
real rl;
int ar [];
int start = 0;
int stop = 1;
int step = 1;
int done = 0;
task a_task;
real trl;
event tevt;
reg tvr;
$display("user task");
endtask
always_ff @(posedge clk) begin: blk_name
event int1, int2;
real intrl;
q = d;
-> foo;
rl = 0.0;
rl <= 1.0;
ar = new [2];
for (int idx = start; idx < stop; idx += step) $display("For: %0d", idx);
for (int idx = 0; done; idx = done + 1) $display("Should never run!");
for (int idx = 0; idx; done = done + 1) $display("Should never run!");
for (int idx = 0; idx; {done, idx} = done + 1) $display("Should never run!");
for (int idx = 0; idx; idx <<= 1) $display("Should never run!");
for (int idx = 0; idx; idx = idx << 1) $display("Should never run!");
$display("array size: %0d", ar.size());
ar.delete();
$display("array size: %0d", ar.size());
a_task;
assign a = 1\'b0;
deassign a;
do $display("do/while");
while (a);
force a = 1\'b1;
release a;
while(a) begin
$display("while");
a = 1\'b0;
end
repeat(2) $display("repeat");
disable out_name;
forever begin
$display("forever");
disable blk_name; // This one should not generate a warning
end
end
initial begin
#1 clk = 1\'b1;
#0 $display("Expect compile warnings!\
PASSED");
end
initial begin: out_name
#2 $display("FAILED");
end
endmodule
|
module top;
wire [3:0] array [1:0];
integer sel;
assign array[0] = 4\'h0;
assign array[1] = 4\'h1;
initial begin
#1;
$display(" %h %h", array[0], array[1]);
// This is only a problem for a wire (net array)!
sel = 0;
$display(" %h %h", array[sel], array[sel+1]);
$display("PASSED");
end
endmodule
|
module top;
reg pass;
reg [8:0] a;
wire [7:0] res_a;
reg [6:0] b;
wire [7:0] res_b;
reg signed [6:0] c;
wire [7:0] res_c;
assign res_a = Copy(a);
assign res_b = Copy(b);
assign res_c = Copy(c);
initial begin
pass = 1\'b1;
a = 9\'h101;
b = -7\'d1;
c = -7\'d1;
#1;
if (res_a !== 8\'h01) begin
$display("Failed to crop a vector, got %b.", res_a);
pass = 1\'b0;
end
if (res_b !== 8\'h7f) begin
$display("Failed to zero extend an unsigned vector, got %b.", res_b);
pass = 1\'b0;
end
if (res_c !== 8\'hff) begin
$display("Failed to sign extend a signed vector, got %b.", res_c);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
function [7:0] Copy;
input [7:0] Value;
begin
Copy = Value;
end
endfunction
endmodule
|
// Copyright (c) 2014 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test real to integer conversion
module vhdl_rtoi_testbench;
vhdl_rtoi dut();
initial begin
#1; // wait for the no_init signal assignment
if (dut.a !== 2) begin
$display("FAILED 1");
$finish;
end
if (dut.b !== 4) begin
$display("FAILED 2");
$finish;
end
if (dut.c !== 5) begin
$display("FAILED 3");
$finish;
end
if (dut.d !== 17) begin
$display("FAILED 4");
$finish;
end
$display("PASSED");
end
endmodule
|
module top;
// This should fail because XX4 is not given a constant.
enum {VAL4, XX4 = $time} en4;
initial $display("FAILED");
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass = 1\'b1;
wire [3:0] part_idx_up, part_idx_down, part_sel;
wire [3:0] ps_array [1:0];
// Check the positive indexed part select.
// assign part_idx_up[-1+:2] = 2\'b01; // We do not currently support this!
assign part_idx_up[1+:2] = 2\'b01;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign part_idx_up[3+:2] = 2\'b01;
assign part_idx_up[5+:2] = 2\'b01; // This should be skipped
assign part_idx_up[7+:3] = 3\'b001; // This should be skipped
`else
assign part_idx_up[3] = 1\'b1;
`endif
// Check the negative indexed part select.
// assign part_idx_down[0-:2] = 2\'b10; // We do not currently support this!
assign part_idx_down[2-:2] = 2\'b10;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign part_idx_down[4-:2] = 2\'b10;
assign part_idx_down[6-:2] = 2\'b10; // This should be skipped
assign part_idx_down[9-:3] = 3\'b100; // This should be skipped
`else
assign part_idx_down[3] = 1\'b0;
`endif
// Check a normal constant part select.
// assign part_sel[1:-1] = 2\'b01; // We do not currently support this!
assign part_sel[2:1] = 2\'b01;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign part_sel[4:3] = 2\'b01;
assign part_sel[6:5] = 2\'b01; // This should be skipped
assign part_sel[9:7] = 3\'b001; // This should be skipped
`else
assign part_sel[3] = 1\'b1;
`endif
// Check a normal constant part select on an array.
// assign ps_array[0][1:-1] = 2\'b01; // We do not currently support this!
assign ps_array[0][2:1] = 2\'b01;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign ps_array[0][4:3] = 2\'b01;
assign ps_array[0][6:5] = 2\'b01; // This should be skipped
assign ps_array[0][9:7] = 3\'b001; // This should be skipped
`else
assign ps_array[0][3] = 1\'b1;
`endif
initial begin
#1;
if (part_idx_up !== 4\'b101z) begin
$display("Failed +: select, expected 4\'b101z, got %b", part_idx_up);
pass = 1\'b0;
end
if (part_idx_down !== 4\'b010z) begin
$display("Failed -: select, expected 4\'b010z, got %b", part_idx_down);
pass = 1\'b0;
end
if (part_sel !== 4\'b101z) begin
$display("Failed const. part select, expected 4\'b101z, got %b", part_sel);
pass = 1\'b0;
end
if (ps_array[0] !== 4\'b101z) begin
$display("Failed array part select, expected 4\'b101z, got %b",
ps_array[0]);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Based on bug report PR#842.
*/
module test;
foo _foo();
initial
begin
// Access the FOO parameter inside the _foo instance ?
$display("%d", _foo.FOO);
\t if (_foo.FOO != 17) begin
\t $display("FAILED -- _foo.FOO=%d", _foo.FOO);
\t $finish;
\t end
\t $display("PASSED");
end
endmodule
module foo;
parameter FOO = 17;
endmodule
|
`begin_keywords "1364-2005"
module top;
reg pass;
reg [3:0] var;
integer fd, code;
initial begin
pass = 1\'b1;
fd = $fopen("ivltests/pr2824189.txt", "r");
code = $fscanf(fd, "%x\
", var);
if (code != 1) begin
$display("Failed initial variable read count expected 1, got %d", code);
pass = 1\'b0;
end
if (var !== 4\'ha) begin
$display("Failed initial variable read value expected a, got %h", var);
pass = 1\'b0;
end
code = $fscanf(fd, "%x\
", var);
if (code != -1) begin
$display("Failed $fscanf() at EOF");
pass = 1\'b0;
end
$fclose(fd);
if (pass) $display("PASSED");
end
endmodule
`end_keywords
|
/*
* Check $ferror() compile time errors.
*/
module top;
integer errno, fd;
reg [639:0] result;
reg [63:0] sresult;
initial begin
fd = 0;
errno = $ferror("string", result); // Invalid first argument.
errno = $ferror(fd); // Missing second argument.
errno = $ferror(fd, "string"); // Invalid second argument.
errno = $ferror(fd, sresult); // Second argument is too small.
errno = $ferror(fd, result, "xx"); // Extra arguments.
end
endmodule
|
// This tests SystemVerilog packages. Make sure that names that
// are the same is different packages can be references properly
// in the various packages.
package p1;
localparam step = 1;
function int next_step(int x);
next_step = x + step;
endfunction // next_step
endpackage // p1
package p2;
localparam step = 2;
function int next_step(int x);
next_step = x + step;
endfunction // next_step
endpackage // p2
program main;
int x;
initial begin
if (p1::step != 1) begin
\t $display("FAILED -- p1::step == %0d", p1::step);
\t $finish;
end
if (p2::step != 2) begin
\t $display("FAILED -- p2::step == %0d", p1::step);
\t $finish;
end
x = p1::next_step(0);
if (x != 1) begin
\t $display("FAILED -- p1::next_step(0) --> %0d", x);
\t $finish;
end
x = p2::next_step(0);
if (x != 2) begin
\t $display("FAILED -- p2::next_step(0) --> %0d", x);
\t $finish;
end
$display("PASSED");
end
endprogram // main
|
module test ( input a, input _b_, output A, output b__);
assign A = a;
assign b__ = _b_;
endmodule
|
//
// Copyright (c) 2002 Stephen Williams
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
reg ena, wea;
reg enb, web;
reg clk;
reg out = 0;
always @(posedge clk) begin
if ((ena == 1) && (wea == 1) &&
\t (enb == 1) && (web == 1))
\tout <= 1;
end
initial begin
clk = 0;
ena = 0;
enb = 0;
wea = 0;
web = 0;
$monitor("clk=%b: ena=%b, enb=%b, wea=%b, web=%b --> out=%b",
\t clk, ena, enb, wea, web, out);
#1 clk = 1;
#1 clk = 0;
ena = 1;
enb = 1;
#1 clk = 1;
#1 clk = 0;
wea = 1;
web = 1;
#1 clk = 1;
#1 clk = 0;
end // initial begin
endmodule // main
|
/*
* This should produce x StL x StL
*
* When using both nmos and pmos you get the correct
* result if only one of the control signals is X, but
* when used individually you get StX not StL. This
* appears to be a vec4 vs vec8 problem. R versions
* give similar results.
*
* If both control inputs are X and the input is 0 the
* value is calculated incorrectly.
*/
module top;
reg nctl, pctl, b;
wire c, d;
initial begin
$display("These should all produce:\
x StL x StL\
-----------");
$monitor("c=%b(%v), d=%b(%v), b=%b, nctl=%b, pctl=%b", c, c, d, d, b, nctl, pctl);
b = 0;
nctl = 0;
pctl = 1\'bx;
#1 nctl = 1\'bx;
#1 b = 1;
end
nmos n1 (c, b, nctl);
pmos p1 (c, b, pctl);
pmos p2 (d, b, pctl);
// bufif1 n1 (c, b, nctl);
// bufif0 p1 (c, b, pctl);
// bufif0 p2 (d, b, pctl);
endmodule
|
`begin_keywords "1364-2005"
module top;
localparam string = "ab";
localparam rg_res = string & 9\'h1ff;
reg passed;
integer fd, res;
reg [8:0] rg;
reg [7:0] mem [31:0];
initial begin
passed = 1\'b1;
fd = $fopen("ThisFileDoesNotExist.txt", "r");
res = $fread(rg, fd); // Try to read from an invalid fd.
if (res != 0) begin
$display("$fread (register fd) count is wrong, expected 0, got %0d", res);
passed = 1\'b0;
end
if (rg !== 9\'bx) begin
$display("$fread (register fd) value is wrong, expected 9\'bx, got %b",
rg);
passed = 1\'b0;
end
fd = $fopen("ivltests/fread.txt", "r");
res = $fread(mem, fd, -1); // Try an invalid start
if (res != 0) begin
$display("$fread (mem. start) count is wrong, expected 0, got %0d", res);
passed = 1\'b0;
end
if (mem[0] !== 8\'bx) begin
$display("$fread (mem. start[0]) value is wrong, expected 8\'bx, got %b",
mem[0]);
passed = 1\'b0;
end
if (mem[15] !== 8\'bx) begin
$display("$fread (mem. start[15]) value is wrong, expected 8\'bx, got %b",
mem[15]);
passed = 1\'b0;
end
if (mem[31] !== 8\'bx) begin
$display("$fread (mem. start[31]) value is wrong, expected 8\'bx, got %b",
mem[31]);
passed = 1\'b0;
end
// Check $fread with a register value.
res = $fread(rg, fd); // Load with the lower nine bits of "ab".
if (res != 2) begin
$display("$fread (register) count is wrong, expected 2, got %0d", res);
passed = 1\'b0;
end
if (rg !== rg_res) begin
$display("$fread (register) value is wrong, expected %b, got %b",
rg_res, rg);
passed = 1\'b0;
end
// Check $fread with a memory.
res = $fread(mem, fd, 0, 2); // Load 0 with "0" and 1 with "1".
if (res != 2) begin
$display("$fread (mem. 1) count is wrong, expected 2, got %0d", res);
passed = 1\'b0;
end
if (mem[0] !== "0") begin
$display("$fread (mem. 1[0]) value is wrong, expected %b, got %b",
"0", mem[0]);
passed = 1\'b0;
end
if (mem[1] !== "1") begin
$display("$fread (mem. 1[1]) value is wrong, expected %b, got %b",
"1", mem[1]);
passed = 1\'b0;
end
res = $fread(mem, fd, 31); // Load 31 with "z".
if (res != 1) begin
$display("$fread (mem. 2) count is wrong, expected 1, got %0d", res);
passed = 1\'b0;
end
if (mem[31] !== "z") begin
$display("$fread (mem. 2[31]) value is wrong, expected %b, got %b",
"z", mem[31]);
passed = 1\'b0;
end
res = $fread(mem, fd, 31, 2); // Load 31 with "y" and warns.
if (res != 1) begin
$display("$fread (mem. 3) count is wrong, expected 1, got %0d", res);
passed = 1\'b0;
end
if (mem[31] !== "y") begin
$display("$fread (mem. 3[31]) value is wrong, expected %b, got %b",
"y", mem[31]);
passed = 1\'b0;
end
res = $fread(mem, fd); // Load with repeated "0" .. "9" pattern.
if (res != 32) begin
$display("$fread (mem. 4) count is wrong, expected 32, got %0d", res);
passed = 1\'b0;
end
// Just check the end values and a value in the middle (15).
if (mem[0] !== "0") begin
$display("$fread (mem. 4[0]) value is wrong, expected %b, got %b",
"0", mem[0]);
passed = 1\'b0;
end
if (mem[15] !== "5") begin
$display("$fread (mem. 4[15]) value is wrong, expected %b, got %b",
"5", mem[15]);
passed = 1\'b0;
end
if (mem[31] !== "1") begin
$display("$fread (mem. 4[31]) value is wrong, expected %b, got %b",
"1", mem[31]);
passed = 1\'b0;
end
// This only gets the trailing new line.
rg = 9\'bx;
res = $fread(rg, fd);
if (res != 1) begin
$display("$fread (EOL) count is wrong, expected 1, got %0d", res);
passed = 1\'b0;
end
if (rg !== 9\'h0xx) begin
$display("$fread (EOL value is wrong, expected 9\'b0xx, got %b", rg);
passed = 1\'b0;
end
// There are no bits left so this array should be the same.
res = $fread(mem, fd);
if (res != 0) begin
$display("$fread (mem. EOL) count is wrong, expected 0, got %0d", res);
passed = 1\'b0;
end
// Just check the end values and a value in the middle (15).
if (mem[0] !== "0") begin
$display("$fread (mem. EOL[0]) value is wrong, expected %b, got %b",
"0", mem[0]);
passed = 1\'b0;
end
if (mem[15] !== "5") begin
$display("$fread (mem. EOL[15]) value is wrong, expected %b, got %b",
"5", mem[15]);
passed = 1\'b0;
end
if (mem[31] !== "1") begin
$display("$fread (mem. EOL[31]) value is wrong, expected %b, got %b",
"1", mem[31]);
passed = 1\'b0;
end
$fclose(fd);
if (passed) $display("PASSED");
else $display("FAILED");
end
endmodule
`end_keywords
|
//
// Copyright (c) 1999 Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
reg clk,reset;
wire [3:0] a,b;
swap s(clk,reset,a,b);
initial begin
clk = 0;
reset = 0;
#1; reset = 1; #1; reset = 0;
#1; clk = 1; #5; clk = 0;
if (a===4\'d6 && b===4\'d5)
$display("PASSED");
else
$display("FAILED");
end
endmodule
module swap(clk,reset,a,b);
input clk,reset;
output [3:0] a,b;
reg [3:0] a,b;
always @(posedge clk or posedge reset)
if (reset) begin
a <= #1 4\'d5;
b <= #1 4\'d6;
end else begin
a <= #1 b;
b <= #1 a;
end
endmodule
|
// This trivial program is NOT valid. "always" blocks are not
// valid in program blocks.
program main ();
initial $display("Hello, World.");
always #1 $finish;
final $display("FAILED");
endprogram : main
|
// This tests end labes (test should pass compilation)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test ();
// error counter
bit err = 0;
initial
begin : dummy_label
if (!err) $display("PASSED");
end : dummy_label
endmodule : test
|
module top;
reg clk = 0;
reg [1:0] in = 2'b00;
wire [1:0] out;
test t1 (clk, out, in);
endmodule
module test(clk, a, b);
input clk;
output a;
input [1:0] b;
reg [1:0] a;
always @(posedge clk) begin
a <= b;
end
endmodule
|
// Ten basic tests in here:
// 1. byte must be initialised before any initial or always block
// 2. assignments to (signed) bytes with random numbers
// 3. assignments to (signed) bytes with random values including X and Z
// 4. converting unsigned integers to signed bytes
// 5. converting signed integers to signed bytes
// 6. converting integers including X and Z states to signed bytes
// 7. trying signed sums (procedural, function, task and module)
// 8. trying signed mults (procedural, function and task)
// 9. trying relational operators
// 10. smaller signed numbers to signed bytes (sign extension)
module ms_add (input byte signed a, b, output byte signed sc, ss);
assign sc = a + b;
always @(a, b) ss = a + b;
endmodule
module main;
parameter N_REPS = 500; // repetition with random numbers
parameter XZ_REPS = 500; // repetition with \'x \'z values
parameter MAX = \'h7f;
parameter LEN = 8;
// variables used as golden references
reg signed [LEN-1:0] ar; // holds numbers
reg signed [LEN-1:0] ar_xz; // holds \'x and/or \'z in random positions
reg signed [LEN-1:0] ar_expected;
integer unsigned ui;
integer signed si;
reg signed [LEN/2-1:0] slice;
// types to be tested
byte signed bu; // holds numbers
byte signed bu_xz; // \'x and \'z are attempted on this
byte signed bresult; // hold results from sums and mults
byte signed mcaresult; // this is permanently wired to a module
byte signed mabresult; // this is permanently wired to a module
integer i;
// continuous assigments
// type LHS type RHS
// --------- ---------
// byte 4-value logic
assign bu = ar;
assign bu_xz = ar_xz;
// module instantiation
ms_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) );
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if (bu !== 8\'b0 || bu_xz != 8\'b0 || bresult !== 8\'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// driving byte type with signed random numbers from a variable
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = $random % MAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to byte: %b", bu);
$finish;
end
end
# 1;
// attempting to drive variables having \'x \'z values into type unsigned bytes
// \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
ar = $random % MAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0
begin
$display ("FAILED - incorrect assigment to byte (when \'x \'z): %b", bu);
$finish;
end
end
// converting unsigned integers to signed bytes
// truncation expected (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ui = {$random} % 2*(MAX+1); // full range as unsigned
#1;
force bu = ui;
#1;
if (bu !== ui[LEN-1:0])
begin
$display ("FAILED - incorrect truncation from unsigned integer to byte: %b", bu);
$finish;
end
end
release bu;
// converting signed integers to signed bytes
// truncation expected (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
si = $random % MAX;
#1;
force bu = si;
#1;
if (bu !== si[LEN-1:0])
begin
$display ("FAILED - incorrect truncation from signed integer to byte: %b mismatchs %b", bu, si[LEN-1:0]);
$finish;
end
end
release bu;
// converting signed integers having \'x \'z values into type signed bytes
// \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM)
// truncation and coercion to zero expected
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
si = $random;
ar_xz = xz_inject (si[LEN-1:0]);
si = {si[31:LEN], ar_xz};
ar_expected = xz_expected (ar_xz);
#1;
force bu_xz = si;
#1;
if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0
begin
$display ("FAILED - incorrect conversion from integer (with \'x \'z) to byte: %b mismatchs %b", bu_xz, ar_expected);
$finish;
end
end
release bu_xz;
// trying signed sums
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = $random % MAX;
ar_xz = $random % MAX;
#1;
bresult = bu + bu_xz;
#1;
if ( bresult !== s_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of signed bytes: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz));
$finish;
end
// invoking byte sum function
if ( fs_sum (bu, bu_xz) !== s_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of signed bytes in function");
$finish;
end
// invoking byte sum task
ts_sum (bu, bu_xz, bresult);
if ( bresult !== s_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of signed bytes in task: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz));
$finish;
end
// checking byte sum from module
if ( mcaresult !== s_sum(ar, ar_xz) || mabresult !== s_sum(ar, ar_xz))
begin
$display ("FAILED - incorrect addition of signed bytes from module");
$finish;
end
end
// trying signed mults, forcing truncation
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = ($random % MAX) << LEN/2;
ar_xz = ($random % MAX) << (LEN/2 - 1);
#1;
bresult = bu * bu_xz;
#1;
if ( bresult !== s_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect product of signed bytes: %0d mismatchs %0d", bresult, s_mul(ar, ar_xz));
$finish;
end
// invoking byte mult function
if ( fs_mul (bu, bu_xz) !== s_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect product of signed bytes in function");
$finish;
end
// invoking byte mult task
ts_mul (bu, bu_xz, bresult);
if ( bresult !== s_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect product of signed bytes in task: %0d mismatchs %0d", bresult, s_mul(ar, ar_xz));
$finish;
end
end
// trying relational operators
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = $random % MAX;
ar_xz = $random % MAX;
#1;
if ( (bu < bu_xz ) !== (ar < ar_xz) )
begin
$display ("FAILED - incorrect \'less than\' on signed bytes");
$finish;
end
if ( (bu <= bu_xz ) !== (ar <= ar_xz) )
begin
$display ("FAILED - incorrect \'less than or equal\' on signed bytes");
$finish;
end
if ( (bu > bu_xz ) !== (ar > ar_xz) )
begin
$display ("FAILED - incorrect \'greater than\' on signed bytes");
$finish;
end
if ( (bu >= bu_xz ) !== (ar >= ar_xz) )
begin
$display ("FAILED - incorrect \'greater than or equal\' than on signed bytes");
$finish;
end
if ( (bu == bu_xz ) !== (ar == ar_xz) )
begin
$display ("FAILED - incorrect \'equal to\' on signed bytes");
$finish;
end
if ( (bu != bu_xz ) !== (ar != ar_xz) )
begin
$display ("FAILED - incorrect \'not equal to\' on signed bytes");
$finish;
end
end
// signed small number to signed byte
for (i = 0; i < (1<<LEN/2); i = i+1)
begin
#1;
slice = $random % \'h7;
force bu = slice;
ar = slice;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect signed extend to signed bytes");
$finish;
end
end
release bu;
# 1;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [LEN-1:0] xz_inject (input signed [LEN-1:0] value);
integer i, temp;
begin
temp = {$random} % 2*(MAX+1); // possible 1 in any position
for (i=0; i<LEN; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random % MAX;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [LEN-1:0] xz_expected (input signed [LEN-1:0] value_xz);
integer i;
begin
for (i=0; i<LEN; i=i+1)
begin
if (value_xz[i] === 1\'bx || value_xz[i] === 1\'bz )
value_xz[i] = 1\'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
// signed 4-value sum
function signed [LEN-1:0] s_sum (input signed [LEN-1:0] a, b);
s_sum = a + b;
endfunction
// signed byte sum as function
function byte signed fs_sum (input byte signed a, b);
fs_sum = a + b;
endfunction
// signed byte sum as task
task ts_sum (input byte signed a, b, output byte signed c);
c = a + b;
endtask
// signed 4-value mults
function signed [LEN-1:0] s_mul (input signed [LEN-1:0] a, b);
s_mul = a * b;
endfunction
// signed byte mults
function byte signed fs_mul (input byte signed a, b);
fs_mul = a * b;
endfunction
// signed byte mult as task
task ts_mul (input byte signed a, b, output byte signed c);
c = a * b;
endtask
endmodule
|
//---------------------------------------------------------------------------
//
//---------------------------------------------------------------------------
module xor_try;
reg [1:0] inp_xor; // The two-bit inputs to the XOR
reg out_xor; // The XOR output
reg clk;
initial begin clk = 1'b1; #10 $sn; #160 $finish(0); end
always #50 clk = ~clk;
// The clock
always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]);
// The actual operation
endmodule
|
`begin_keywords "1364-2005"
/*
* This tests the synthesis of a case statement that has an empty case.
*/
module main;
reg bit, foo, bar;
// Combinational device that sends 1 or 0 to foo, to follow bit.
// This tests the special situation that the case condition only sets
// some of the bits that the case as a whole sets. This is OK if
// the bits that are sometimes not set are covered elsewhere.
always @*
begin
\tfoo = 0;
\tbar = 0;
\tcase (bit)
\t 1\'b0: bar = 1;
\t 1\'b1: foo = 1;
\tendcase // case(bit)
end
(* ivl_synthesis_off *)
initial begin
bit = 0;
# 6 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar);
if (bit !== 0 || foo !== 0 || bar !== 1) begin
\t $display("FAILED");
\t $finish;
end
bit <= 1;
#10 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar);
if (bit !== 1 || foo !== 1 || bar !== 0) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
`end_keywords
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
wire [2:0] arr [0:7];
reg rarr [0:7];
integer i;
initial begin
pass = 1\'b1;
#1;
for (i = 0; i <=7 ; i = i + 1) begin
if (arr[i] !== i) begin
$display("FAILED: index %1d, expected %1d, got %1d", i, i, arr[i]);
pass = 1\'b0;
end
end
if (pass) $display("PASSED");
end
// This should display a warning and just ignore the whole statement.
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign arr[20] = \'b0;
assign arr[-1] = \'b0;
`endif
genvar m;
generate
// This like above should warn when 8 <= m <= 15.
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
for (m=0; m<=15; m=m+1) begin: arr_loop
`else
for (m=0; m<=7; m=m+1) begin: arr_loop
`endif
assign arr[m] = m;
end
endgenerate
endmodule
|
//
// Copyright (c) 2001 Stephan Boettcher <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Validates Non-blocking assignment propagation
// $Id: nblkpush.v,v 1.2 2005/07/07 16:25:20 stevewilliams Exp $
// Update: This test has a race in it that makes it not valid. The
// assumption that a blocking assign will push through the continuous
// assignment before the thread doing the assign is allowed to advance
// is not valid. This test only passes Verilog XL. Every other tool,
// commercial or otherwise, seems to FAIL this test. Therefore, this
// test should not be relied on.
module test;
reg a, b, c, d;
wire ab = a & b;
wire abc = ab | c;
wire abcd = abc & d;
initial
begin
\ta = 0;
\tb = 1;
\tc = 0;
\td = 1;
\t#1;
\ta = 1;
\tif (abcd === 1)
\t begin
\t $display("PASSED");
\t $finish;
\t end
\t$display("FAILED ab=%b, abc=%b, abcd=%b", ab, abc, abcd);
\t#1;
\tif (abcd === 1)
\t $display("abcd value changed late");
\telse
\t $display("abcd value still wrong");
end
endmodule
|
module bug();
reg [0:1][0:15][0:7] array;
reg failed = 0;
integer i;
reg [3:0] index;
initial begin
i = $bits(array);
$display("width 0 = %0d", i);
if (i !== 256) failed = 1;
i = $bits(array[0]);
$display("width 1 = %0d", i);
if (i !== 128) failed = 1;
i = $bits(array[0][0]);
$display("width 2 = %0d", i);
if (i !== 8) failed = 1;
for (i = 0; i < 16; i++) begin
index = i[3:0];
array[0][index] = {4\'d0, index};
array[1][index] = {4\'d1, index};
end
$display("%h", array);
if (array !== 256\'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f)
failed = 1;
for (i = 0; i < 16; i++) begin
index = i[3:0];
$display("%h : %h %h", index, array[0][index], array[1][index]);
if (array[0][index] !== {4\'d0, index}) failed = 1;
if (array[1][index] !== {4\'d1, index}) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
`timescale 1ns/10ps
module top;
reg a, pass;
wire z;
time edge_time;
always @(z) begin
if ((z === 0) && (($time - edge_time) != 4)) begin
$display("Falling took %d, expected 4", $time - edge_time);
pass = 1\'b0;
end
if ((z === 1) && (($time - edge_time) != 3)) begin
$display("Rising took %d, expected 3", $time - edge_time);
pass = 1\'b0;
end
end
initial begin
pass = 1\'b1;
$sdf_annotate("ivltests/sdf_del.sdf", top);
#10;
edge_time = $time;
a = 1\'b0;
#10;
edge_time = $time;
a = 1\'b1;
#10 if (pass) $display("PASSED");
end
my_buf dut(z, a);
endmodule
module my_buf (output z, input a);
buf (z, a);
specify
(a => z) = (0, 0);
endspecify
endmodule
|
`timescale 1ns/10ps
module top;
reg pass;
reg [60*8-1:0] str, cmp;
reg [7:0] bval;
reg [15:0] oval, hval;
integer dval;
time tval;
real rval;
initial begin
pass = 1\'b1;
// Check the %b conversion.
bval = 8\'b01101001;
cmp = "1101001";
$sformat(str, "%0b", bval);
if (str != cmp) begin
$display("FAILED: %%0b, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "0000000001101001";
$sformat(str, "%016b", bval);
if (str != cmp) begin
$display("FAILED: %%016b, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "1101001 ";
$sformat(str, "%-016b", bval);
if (str != cmp) begin
$display("FAILED: %%-016b, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
// Check the %o conversion.
oval = 16\'o01234;
cmp = "1234";
$sformat(str, "%0o", oval);
if (str != cmp) begin
$display("FAILED: %%0o, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "00001234";
$sformat(str, "%08o", oval);
if (str != cmp) begin
$display("FAILED: %%08o, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "1234 ";
$sformat(str, "%-08o", oval);
if (str != cmp) begin
$display("FAILED: %%-08o, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
// Check the %h conversion.
hval = 16\'h0abc;
cmp = "abc";
$sformat(str, "%0h", hval);
if (str != cmp) begin
$display("FAILED: %%0h, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "00000abc";
$sformat(str, "%08h", hval);
if (str != cmp) begin
$display("FAILED: %%08h, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "abc ";
$sformat(str, "%-08h", hval);
if (str != cmp) begin
$display("FAILED: %%-08h, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
// Check the %c conversion.
bval = "c";
cmp = "c";
$sformat(str, "%0c", bval);
if (str != cmp) begin
$display("FAILED: %%0c, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "000c";
$sformat(str, "%04c", bval);
if (str != cmp) begin
$display("FAILED: %%04c, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
// Check the %d conversion.
dval = 123;
cmp = "00000123";
$sformat(str, "%08d", dval);
if (str != cmp) begin
$display("FAILED: %%08d, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "+0000123";
$sformat(str, "%+08d", dval);
if (str != cmp) begin
$display("FAILED: %%+08d, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = " 123";
$sformat(str, "%d", dval);
if (str != cmp) begin
$display("FAILED: %%d, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "123 ";
$sformat(str, "%-08d", dval);
if (str != cmp) begin
$display("FAILED: %%-08d, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "123";
$sformat(str, "%0d", dval);
if (str != cmp) begin
$display("FAILED: %%0d, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
dval = -123;
cmp = "-0000123";
$sformat(str, "%08d", dval);
if (str != cmp) begin
$display("FAILED: %%08d, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
$sformat(str, "%+08d", dval);
if (str != cmp) begin
$display("FAILED: %%+08d, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = " -123";
$sformat(str, "%d", dval);
if (str != cmp) begin
$display("FAILED: %%d, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
// Check the %t conversion.
tval = 100_000;
cmp = "0010000000";
$sformat(str, "%010t", tval);
if (str != cmp) begin
$display("FAILED: %%010t, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = " 10000000"; // Default width is 20.
$sformat(str, "%t", tval);
if (str != cmp) begin
$display("FAILED: %%t, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "10000000 ";
$sformat(str, "%-010t", tval);
if (str != cmp) begin
$display("FAILED: %%-010t, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "10000000";
$sformat(str, "%0t", tval);
if (str != cmp) begin
$display("FAILED: %%0t, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
rval=100_000.25;
cmp = "0010000025";
$sformat(str, "%010t", rval);
if (str != cmp) begin
$display("FAILED: %%010t (real), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = " 10000025"; // Default width is 20.
$sformat(str, "%t", rval);
if (str != cmp) begin
$display("FAILED: %%t (real), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "10000025 ";
$sformat(str, "%-010t", rval);
if (str != cmp) begin
$display("FAILED: %%-010t (real), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "10000025";
$sformat(str, "%0t", rval);
if (str != cmp) begin
$display("FAILED: %%0t (real), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
// Display in ns with 10ps resolution.
$timeformat(-9, 2, " ns", 15);
cmp = "000100000.00 ns";
$sformat(str, "%015t", tval);
if (str != cmp) begin
$display("FAILED: %%015t (w/$tf), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = " 100000.00 ns";
$sformat(str, "%t", tval);
if (str != cmp) begin
$display("FAILED: %%t (w/$tf), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "100000.00 ns ";
$sformat(str, "%-015t", tval);
if (str != cmp) begin
$display("FAILED: %%-015t (w/$tf), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "100000.00 ns";
$sformat(str, "%-0t", tval);
if (str != cmp) begin
$display("FAILED: %%-0t (w/$tf), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "000100000.25 ns";
$sformat(str, "%015t", rval);
if (str != cmp) begin
$display("FAILED: %%015t (w/$tf, rl), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = " 100000.25 ns";
$sformat(str, "%t", rval);
if (str != cmp) begin
$display("FAILED: %%t (w/$tf, rl), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "100000.25 ns ";
$sformat(str, "%-015t", rval);
if (str != cmp) begin
$display("FAILED: %%-015t (w/$tf, rl), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "100000.25 ns";
$sformat(str, "%-0t", rval);
if (str != cmp) begin
$display("FAILED: %%-0t (w/$tf, rl), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
// Check the real conversions (%e, %f, %g). If one works they all
// they all work (uses system conversion).
rval = 1.25;
cmp = "000000001.250000";
$sformat(str, "%016.6f", rval);
if (str != cmp) begin
$display("FAILED: %%016.6f, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "+00000001.250000";
$sformat(str, "%+016.6f", rval);
if (str != cmp) begin
$display("FAILED: %%+016.6f, expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
rval = -1.25;
cmp = "-00000001.250000";
$sformat(str, "%016.6f", rval);
if (str != cmp) begin
$display("FAILED: %%016.6f (negative), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
cmp = "-00000001.250000";
$sformat(str, "%+016.6f", rval);
if (str != cmp) begin
$display("FAILED: %%+016.6f (negative), expected %0s, got %0s", cmp, str);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
package mypackage;
logic [1:0] array1[] = new[4];
logic [1:0] array2[] = new[4](\'{0,1,2,3});
endpackage
module test();
import mypackage::*;
logic [1:0] array3[] = new[4];
logic [1:0] array4[] = new[4](\'{0,1,2,3});
reg failed = 0;
initial begin
foreach (array1[i]) begin
array1[i] = i;
end
foreach (array1[i]) begin
$display(array1[i]);
if (array1[i] !== i) failed = 1;
end
foreach (array2[i]) begin
$display(array2[i]);
if (array2[i] !== i) failed = 1;
end
foreach (array3[i]) begin
array3[i] = i;
end
foreach (array3[i]) begin
$display(array3[i]);
if (array3[i] !== i) failed = 1;
end
foreach (array4[i]) begin
$display(array4[i]);
if (array4[i] !== i) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module dut(i, o);
input [3:0] i;
output [3:0] o;
wire logic [3:0] i;
reg [3:0] o;
always @* o = i;
endmodule
module test();
logic [3:0] i, o;
dut dut(i, o);
reg failed = 0;
initial begin
i = 4\'b01xz;
#0 $display("%b %b", i, o);
if (o !== 4\'b01xz) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
`timescale 1ns/1ns
module top;
wire q;
reg a, b;
initial begin
// $dumpfile("test.lx2"); // Need to also use the -lxt2 flags on exe.
// $dumpvars(0, top);
// Initial value should be X is 1.
#1 a = 1\'b1; // Should be X is 1.
#1 if (q !== 1\'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 a = 1\'b0; // Correct: 1.
#1 if (q !== 1\'b1) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 a = 1\'b1; // Should be X is 1.
#1 if (q !== 1\'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 a = 1\'bx; // Should be X is 1.
#1 if (q !== 1\'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 a = 1\'b1; // Should be X is 1.
#1 if (q !== 1\'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 a = 1\'bx; b = 1\'b1; // Correct: X.
#1 if (q !== 1\'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 b = 1\'b0; // Correct: 1.
#1 if (q !== 1\'b1) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
#1 b = 1\'b1; // Correct: X, but following #1 delay is missing.
#1 if (q !== 1\'bx) begin
$display("FAILED -- %b nand %b --> %b", a, b, q);
$finish;
end
$display("PASSED");
$finish;
end
nand dut (q, a, b);
// nand dut (q, b, a); // This also produces incorrect results.
endmodule
|
program main;
function int sum_array(bit[7:0] array[]);
int idx;
sum_array = 0;
for (idx = 0 ; idx < array.size() ; idx = idx+1)
\tsum_array += array[idx];
endfunction // sum_array
bit [7:0] obj[];
int\t foo;
initial begin
foo = sum_array(\'{});
if (foo !== 0) begin
\t $display("FAILED -- sum of empty array returns %0d", foo);
\t $finish;
end
obj = new[3];
obj[0] = 1;
obj[1] = 2;
obj[2] = 3;
foo = sum_array(obj);
if (foo !== 6) begin
\t $display("FAILED -- sum of \'{1,2,3} is %0d", foo);
\t $finish;
end
$display("PASSED");
end // initial begin
endprogram // main
|
/*
* This program tests that enumeration value first/last/next
* methods work properly. The .next method requires some run-time
* support for enumeration.
*/
module main;
enum { RED, GREEN = 2, BLUE } color1;
initial begin
color1 = RED;
$display("color1.first == %0d", color1.first);
$display("color1.last == %0d", color1.last);
$display("color1.num == %0d", color1.num);
$display("color1.next == %0d", color1.next);
color1 = color1.next;
if (color1 != GREEN || color1 !== 2) begin
\t $display("FAILED -- should be %0d, got %0d", GREEN, color1);
\t $finish;
end
color1 = color1.next;
if (color1 != BLUE || color1 !== 3 || color1 != color1.last) begin
\t $display("FAILED -- should be %0d, got %0d", BLUE, color1);
\t $finish;
end
color1 = color1.prev;
if (color1 != GREEN || color1 !== 2) begin
\t $display("FAILED -- should be %0d, got %0d", GREEN, color1);
\t $finish;
end
color1 = color1.prev;
if (color1 != RED || color1 !== 0 || color1 != color1.first) begin
\t $display("FAILED -- should be %0d, got %0d", RED, color1);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module top;
reg pass = 1\'b1;
parameter one = 1\'b1;
parameter zero = 1\'b0;
parameter udef = 1\'bx;
real rl1 = one ? 4 : 4.5; // 4.0
real rl2 = zero ? 4.0 : 5; // 5.0
real rl3 = udef ? 6 : 6.0; // 6.0
real rl4 = udef ? 7 : 7; // 7.0
initial begin
#1;
if (rl1 != 4.0) begin
$display("FAILED: real expression one, expected 4.0, got %f", rl1);
pass = 1\'b0;
end
if (rl2 != 5.0) begin
$display("FAILED: real expression two, expected 5.0, got %f)", rl2);
pass = 1\'b0;
end
if (rl3 != 6.0) begin
$display("FAILED: real expression three, expected 6.0, got %f", rl3);
pass = 1\'b0;
end
if (rl4 != 7.0) begin
$display("FAILED: real expression four, expected 7.0, got %f", rl4);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`define FOO(val=42, text="42") do_foo(val, text)
module main;
int ref_val;
string ref_text;
task do_foo(int val, string text);
if (val!=ref_val || text!=ref_text) begin
\t $display("FAILED -- val=%d (expect %d), text=%0s, (expect %0s)",
\t\t val, ref_val, text, ref_text);
\t $finish;
end
endtask // do_foo
initial begin
ref_val = 42;
ref_text = "42";
`FOO(,);
ref_val = 42;
ref_text = "41";
`FOO(,"41");
ref_val = 41;
ref_text = "42";
`FOO(41,);
ref_val = 41;
ref_text = "41";
`FOO(41,"41");
$display("PASSED");
end // initial begin
endmodule // main
|
// Icarus doesn\'t properly support variable expressions on the right hand
// side of a procedural CA - see bug 605.
module test();
reg [1:0] addr;
reg [3:0] memory[3:0];
reg [3:0] data;
initial begin
assign data = memory[addr];
addr = 1;
memory[addr] = 2;
#0 $display("%d", data);
if (data === 2)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test();
reg [7:0] test;
wire [7:0] neg_test = -test;
initial begin
for (test = 0 ; test < 255 ; test = test + 1) begin
\t #1 if (neg_test !== (-test)) begin
\t $display("FAILED -- %b !== -%b", neg_test, test);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule
|
module top;
wire real test;
initial begin
if (test != 0.0) $display("FAILED");
else $display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 David Leask ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Modified to be self checking
/*
** The problem:
** Reading in a series of bytes, one per clock, to create a
** large vector which holds the bytes in a parallel form.
*/
module demo_assign_problem;
reg [7:0] mem_buffer [0:3];
wire [31:0] big_word;
reg error;
reg [31:0] myconst;
integer i;
assign big_word[ 31: 24] = mem_buffer[0];
assign big_word[ 23: 16] = mem_buffer[1];
assign big_word[ 15: 8] = mem_buffer[2];
assign big_word[ 7: 0] = mem_buffer[3];
initial
begin
error = 0;
for (i = 0; i < 4; i = i+1)
mem_buffer[i] = 0;
#50;
mem_buffer[0] = 8\'h12;
#50;
myconst = 32\'h12_00_00_00;
if(big_word !== 32\'h12_00_00_00)
begin
$display("FAILED -Memory assign - expect %h, but have %h",
myconst,big_word);
error = 1;
end
#100 ;
mem_buffer[1] = 8\'h34;
#50;
myconst = 32\'h12_34_00_00;
if(big_word !== 32\'h12_34_00_00)
begin
$display("FAILED -Memory assign - expect %h, but have %h",
myconst,big_word);
error = 1;
end
#100 ;
mem_buffer[2] = 8\'h56;
#50;
myconst = 32\'h12_34_56_00;
if(big_word !== 32\'h12_34_56_00)
begin
$display("FAILED -Memory assign - expect %h, but have %h",
myconst,big_word);
error = 1;
end
#100;
mem_buffer[3] = 8\'h78;
#50;
myconst = 32\'h12_34_56_00;
if(big_word !== 32\'h12_34_56_78)
begin
$display("FAILED - Memory assign - expect %h, but have %h",
myconst,big_word);
error = 1;
end
#100;
mem_buffer[0] = 8\'hab;
#50;
myconst = 32\'hab_34_56_00;
if(big_word !== 32\'hab_34_56_78)
begin
$display("FAILED - Memory assign - expect %h, but have %h",
myconst,big_word);
error = 1;
end
#100;
if (error ===0)
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
parameter PARM = 2;
reg [3:0] b;
wire [1:0] a;
assign a = b[3:(3-PARM+1)] + 1;
initial begin
b = 4\'b1011;
#1;
if (a===2\'b11)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
`begin_keywords "1364-2005"
module top;
reg passed, in, expect;
integer lp;
wire rand = ∈
wire ror = |in;
wire rxor = ^in;
wire rnand = ~∈
wire rnor = ~|in;
wire rxnor = ~^in;
initial begin
passed = 1\'b1;
for (lp=0; lp < 3 ; lp = lp + 1) begin
case (lp)
0: {in,expect} = 2\'b00;
1: {in,expect} = 2\'b11;
2: {in,expect} = 2\'bzx;
3: {in,expect} = 2\'bxx;
endcase
#1;
// Check the normal reductions.
if (rand !== expect) begin
$display("FAILED CA reduction & with input %b, expected %b, got %b",
in, expect, rand);
passed = 1\'b0;
end
if (ror !== expect) begin
$display("FAILED CA reduction | with input %b, expected %b, got %b",
in, expect, ror);
passed = 1\'b0;
end
if (rxor !== expect) begin
$display("FAILED CA reduction ^ with input %b, expected %b, got %b",
in, expect, rxor);
passed = 1\'b0;
end
// Check the inverted reductions.
if (rnand !== ~expect) begin
$display("FAILED CA reduction ~& with input %b, expected %b, got %b",
in, ~expect, rnand);
passed = 1\'b0;
end
if (rnor !== ~expect) begin
$display("FAILED CA reduction ~| with input %b, expected %b, got %b",
in, ~expect, rnor);
passed = 1\'b0;
end
if (rxnor !== ~expect) begin
$display("FAILED CA reduction ~^ with input %b, expected %b, got %b",
in, ~expect, rxnor);
passed = 1\'b0;
end
end
if (passed) $display("PASSED");
end
endmodule
`end_keywords
|
module dpram #(
\tparameter aw=8,
\tparameter dw=8
) (input clka, clkb, wena,
\tinput [aw-1:0] addra, addrb,
\tinput [dw-1:0] dina,
\toutput [dw-1:0] doutb
);
// minimalist dual-port RAM model, hope most tools can synthesize it
localparam sz=(32\'b1<<aw)-1;
reg [dw-1:0] mem[sz:0];
reg [aw-1:0] alb=0;
(* ivl_synthesis_on *)
always @(posedge clka) if (wena) mem[addra] <= dina;
always @(posedge clkb) alb <= addrb;
assign doutb = mem[alb];
(* ivl_synthesis_off *)
initial $display("PASSED");
endmodule
|
module main;
reg passed = 1\'b1;
wire out1;
reg local_out;
reg mode;
assign out1 = mode ? 1\'bz : local_out;
pullup(out1);
initial begin
mode = 1\'b1;
local_out = 1\'bx;
// The pull up device sets the level.
#1 if (out1 !== 1\'b1) begin
$display("FAILED test 1, expected 1\'b1, got %b", out1);
passed = 1\'b0;
end
mode = 1\'b0;
local_out = 1\'b0;
// Set by local out.
#1 if (out1 !== local_out) begin
$display("FAILED test 1, expected %b, got %b", local_out, out1);
passed = 1\'b0;
end
local_out = 1\'b1;
// Set by local out.
#1 if (out1 !== local_out) begin
$display("FAILED test 1, expected %b, got %b", local_out, out1);
passed = 1\'b0;
end
local_out = 1\'bx;
// Set by local out.
#1 if (out1 !== local_out) begin
$display("FAILED test 1, expected %b, got %b", local_out, out1);
passed = 1\'b0;
end
local_out = 1\'bz;
// The pull up device sets the level.
#1 if (out1 !== 1\'b1) begin
$display("FAILED test 1, expected 1\'b1, got %b", out1);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
//---------------------------------------------------------------------------
//
//---------------------------------------------------------------------------
module xor_try;
reg [1:0] inp_xor; // The two-bit inputs to the XOR
reg out_xor; // The XOR output
reg clk;
initial begin clk = 1'b1; #10 $sn; #160 $finish(0); end
always #50 clk = ~clk;
// The clock
always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]);
// The actual operation
endmodule
|
module m;
reg [15:8] r;
integer i;
initial
begin
r = 8'b01101001;
for (i = 8; i <= 15; i = i + 1)
$display(r[i]);
end
endmodule
|
module top;
reg in;
wire [7:0] out;
lwr dut(out, in);
initial begin
$display("FAILED");
end
endmodule
module lwr(out, in);
output [7:0] out;
input in;
assign out = {8{in}};
specify
// It is an error to use a parallel connection here since the input
// and output (source/destination) do not have the same width.
(in => out) = 2;
endspecify
endmodule
|
module genvar_scopes();
// This test is designed to check that genvars can be declared
// within a generate block and do not collide with genvars of
// the same name declared in the enclosing scope.
genvar i;
genvar j;
reg [1:0] a[1:0];
wire [1:0] b[1:0];
wire [1:0] c[1:0];
wire [1:0] d[1:0];
for (i = 0; i < 2; i = i + 1) begin
for (j = 0; j < 2; j = j + 1) begin
assign b[i][j] = a[i][j];
end
end
for (i = 0; i < 2; i = i + 1) begin
genvar j;
for (j = 0; j < 2; j = j + 1) begin
assign c[i][j] = a[i][j];
end
end
for (j = 0; j < 2; j = j + 1) begin
genvar k;
for (k = 0; k < 2; k = k + 1) begin
assign d[j][k] = a[j][k];
end
end
initial begin
a[0] = 2\'b01;
a[1] = 2\'b10;
#1;
$display("%b %b", b[0], b[1]);
$display("%b %b", c[0], c[1]);
$display("%b %b", d[0], d[1]);
if ((b[0] === 2\'b01) && (b[1] === 2\'b10)
&& (c[0] === 2\'b01) && (c[1] === 2\'b10)
&& (d[0] === 2\'b01) && (d[1] === 2\'b10))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* Copyright (c) 1999 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
primitive BUFG ( O, I );
output O;
input I;
table
0 : 0 ;
1 : 1 ;
endtable
endprimitive
module main;
wire out;
reg in;
BUFG bg(out, in);
initial begin
in = 0;
#1 if (out != 0) begin
\t $display("FAILED -- %b != 0", out);
\t $finish;
end
in = 1;
#1 if (out != 1) begin
\t $display("FAILED -- %b != 1", out);
\t $finish;
end
$display("PASSED");
end
endmodule
|
module test();
localparam [7:0] dly1 = 4;
wire [7:0] dly2 = 3;
reg [7:0] dly3 = 2;
reg i;
wire [6:1] o;
nmos #(dly1, dly2, dly3) buf1(o[1], i, 1\'b1);
nmos #(dly2, dly3, dly1) buf2(o[2], i, 1\'b1);
nmos #(dly3, dly1, dly2) buf3(o[3], i, 1\'b1);
nmos #(dly2-1, dly2-2, dly2-3) buf4(o[4], i, 1\'b1);
nmos #(dly3+1, dly3+2, dly3+3) buf5(o[5], i, 1\'b1);
nmos #(4, 3, 2) buf6(o[6], i, 1\'b1);
function check(input o1, input o2, input o3, input o4, input o5, input o6);
begin
check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3)
&& (o[4] == o4) && (o[5] == o5) && (o[6] == o6);
end
endfunction
reg failed = 0;
initial begin
#1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);
i = 1\'b1;
#0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'b1, 1\'b1, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1;
i = 1\'b0;
#0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b0, 1\'b1, 1\'b1)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'b0, 1\'b1, 1\'b0, 1\'b1, 1\'b1)) failed = 1;
#1; #0 if (!check(1\'b0, 1\'b0, 1\'b1, 1\'b0, 1\'b1, 1\'b0)) failed = 1;
#1; #0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0)) failed = 1;
i = 1\'bx;
#0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'bx, 1\'b0, 1\'b0)) failed = 1;
#1; #0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'bx, 1\'b0, 1\'b0)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'b0, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
i = 1\'bz;
#0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bz, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bz, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bz, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bz, 1\'bx, 1\'bx, 1\'bz, 1\'bx, 1\'bz)) failed = 1;
#1; #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bx, 1\'bz)) failed = 1;
#1; #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz)) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module automatic_error();
task automatic auto_task;
reg local;
local = 1;
endtask
initial auto_task.local = 0;
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for VHDL std.textio & ieee.std_logic_textio functions implemented using VPI.
`timescale 1ns/1ns
typedef enum integer { false, true } boolean;
typedef enum integer { read_mode , write_mode , append_mode } file_open_kind;
module vhdl_textio_test;
string line;
int file;
string str;
bit [3:0][7:0] str_lim;
real r;
int in;
integer i;
byte by;
time t;
boolean boo;
logic l;
logic [7:0] lv;
bit bi;
bit [7:0] biv;
initial begin
static string filename = "vpi_textio_text.tmp";
// values to be saved
str = "test_string";
str_lim = "TEST";
r = -2.5e3;
in = 120;
i = -12;
by = 8\'h1f;
t = 100ns;
boo = true;
l = 1\'bx;
lv = 8\'b110101xz;
bi = 1\'b0;
biv = 8\'b10111001;
// write test
$ivlh_file_open(file, filename, write_mode);
$ivlh_write(line, str, 0); // standard format
$ivlh_write(line, " ", 0);
$ivlh_write(line, str_lim, 4); // string format
$ivlh_write(line, " ", 0);
$ivlh_write(line, r, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, in, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, i, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, by, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, t, 2); // time format
// this will be intentionally skipped during the read test
$ivlh_write(line, " ", 0);
$ivlh_write(line, l, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, lv, 0);
if(line != "test_string TEST -2500.000000 120 -12 31 100 ns X 110101XZ") begin
$display("FAILED 1");
$finish();
end
$ivlh_writeline(file, line);
// writeline should clear the written string
if(line != "") begin
$display("FAILED 2");
$finish();
end
$ivlh_write(line, boo, 1); // boolean format
$ivlh_write(line, " ", 0);
$ivlh_write(line, l, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, lv, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, bi, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, biv, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, biv, 3); // hex format
if(line != "TRUE X 110101XZ 0 10111001 B9") begin
$display("FAILED 3");
$finish();
end
$ivlh_writeline(file, line);
$fclose(file);
// reset variables
str = "";
r = 0;
in = 0;
i = 0;
by = 0;
t = 0s;
boo = false;
l = 0;
lv = 0;
bi = 0;
biv = 0;
// read test
$ivlh_file_open(file, filename, read_mode );
$ivlh_readline(file, line);
$ivlh_read(line, str, 0); // standard format
$ivlh_read(line, str_lim, 4); // string format
$ivlh_read(line, r, 0);
$ivlh_read(line, in, 0);
$ivlh_read(line, i, 0);
$ivlh_read(line, by, 0);
$ivlh_read(line, t, 2); // time format
$ivlh_readline(file, line);
$ivlh_read(line, boo, 1); // boolean format
$ivlh_read(line, l, 0);
$ivlh_read(line, lv, 0);
$ivlh_read(line, bi, 0);
$ivlh_read(line, biv, 0);
$ivlh_read(line, biv, 3); // hex format
$fclose(file);
// compare read and expected values
if(str != "test_string") begin
$display("FAILED 5");
$finish();
end
if(str_lim != "TEST") begin
$display("FAILED 6");
$finish();
end
if(r != -2.5e3) begin
$display("FAILED 7");
$finish();
end
if(in !== 120) begin
$display("FAILED 8");
$finish();
end
if(i !== -12) begin
$display("FAILED 9");
$finish();
end
if(by !== 8\'h1f) begin
$display("FAILED 10");
$finish();
end
if(t != 100ns) begin
$display("FAILED 11");
$finish();
end
if(boo !== true) begin
$display("FAILED 12");
$finish();
end
if(l !== 1\'bx) begin
$display("FAILED 13");
$finish();
end
if(lv !== 8\'b110101xz) begin
$display("FAILED 14");
$finish();
end
if(bi !== 1\'b0) begin
$display("FAILED 15");
$finish();
end
if(biv !== 8\'b10111001) begin
$display("FAILED 16");
$finish();
end
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate left hand variable index
module main ;
reg [3:0] a,b;
reg c;
reg error;
always @(c or b)
a[b] = c;
initial
begin
#1 ;
a = 4\'b1111;
error = 0;
b = 1\'b0;
c = 1\'b0;
#1 ;
if(a != 4\'b1110)
begin
$display("FAILED - var index - a = %b, [b] = %d, c=%b",a,b,c);
error = 1;
end
#1 ;
b = 1;
#1 ;
if(a != 4\'b1100)
begin
$display("FAILED - var index - a = %b, [b] = %d, c=%b",a,b,c);
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
module main;
// Model a pin with a weak keeper circuit. The way this works:
// If the pin value is 1, then attach a weak1 pullup, but
// if the pin value is 0, attach a weak0 pulldown.
wire pin;
pullup (weak1) (keep1);
pulldown (weak0) (keep0);
tranif1 (pin, keep1, pin);
tranif0 (pin, keep0, pin);
// Logic to drive a value onto a pin.
reg\tvalue, enable;
bufif1 (pin, value, enable);
initial begin
value = 0;
enable = 1;
#1 if (pin !== 0) begin
\t $display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin);
\t $finish;
end
// pin should hold its value after the drive is removed.
enable = 0;
#1 if (pin !== 0) begin
\t $display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin);
\t $finish;
end
value = 1;
enable = 1;
#1 if (pin !== 1) begin
\t $display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin);
\t $finish;
end
// pin should hold its value after the drive is removed.
enable = 0;
#1 if (pin !== 1) begin
\t $display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module top;
parameter WIDTH = dut.WIDTH;
test dut();
endmodule
module test;
parameter WIDTH = 8;
endmodule
|
`begin_keywords "1364-2005"
module top;
reg [31:0] var;
initial begin
$monitor(var);
var = 0;
repeat (60) begin
#1 var = $urandom_range(0,16);
end
end
endmodule
`end_keywords
|
module test();
struct packed {
logic [15:0] value;
} data;
initial begin
data.value[7:0] = 8\'h55;
data.value[15:8] = 8\'haa;
if (data !== 16\'haa55) begin
$display("FAILED -- data=%h", data);
$finish;
end
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - include a two levels deep
//
`include "ivltests/include1.v"
|
//
// Copyright (c) 1999 Thomas Coonan ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// **** Here\'s a simple, sequential multiplier. Very simple, unsigned..
// Not very well tested, play with testbench, use at your own risk, blah blah blah..
//
//
// Unsigned 16-bit multiply (multiply two 16-bit inputs to get a 32-bit output)
//
// Present data and assert start synchronous with clk.
// Assert start for ONLY one cycle.
// Wait N cycles for answer (at most). Answer will remain stable until next start.
// You may use DONE signal as handshake.
//
// Written by tom coonan
//
module mult16 (clk, resetb, start, done, ain, bin, yout);
parameter N = 16;
input\t\t\tclk;
input\t\t\tresetb;
input\t\t\tstart; // Register the ain and bin inputs (they can change afterwards)
//input [N-1:0]\t\tain;
//input [N-1:0]\t\tbin;
//output [2*N-1:0]\tyout;
input [15:0]\t\tain;
input [15:0]\t\tbin;
output [31:0]\tyout;
output\t\t\tdone;
//reg [2*N-1:0]\t\ta;
//reg [N-1:0]\t\tb;
//reg [2*N-1:0]\t\tyout;
reg [31:0]\t\ta;
reg [15:0]\t\tb;
reg [31:0]\t\tyout;
reg\t\tdone;
always @(posedge clk or negedge resetb) begin
if (~resetb) begin
a <= 0;
b <= 0;
yout <= 0;
done <= 1\'b1;
end
else begin
// Load will register the input and clear the counter.
if (start) begin
a <= ain;
b <= bin;
yout <= 0;
done <= 0;
end
else begin
// Go until b is zero
if (~done) begin
if (b != 0) begin
// If \'1\' then add a to sum
if (b[0]) begin
yout <= yout + a;
end
b <= b >> 1;
a <= a << 1;
$display ("a = %h, b = %h, yout = %h", a,b,yout);
end
else begin
done <= 1\'b1;
end
end
end
end
end
endmodule
module mul16;
reg clk, resetb, start;
reg [15:0] a;
reg [15:0] b;
wire [31:0] y;
wire done;
mult16 mult16inst (clk, resetb, start, done, a, b, y);
initial begin
clk = 0;
forever begin
#10 clk = ~clk;
end
end
initial begin
resetb = 0;
#30 resetb = 1;
end
integer num_errors;
parameter MAX_TRIALS = 10;
initial begin
// $dumpfile ("multdiv.vcd");
// $dumpvars (0,a);
// $dumpvars (0,b);
// $dumpvars (0,y);
// $dumpvars (0,resetb);
// $dumpvars (0,done);
num_errors = 0;
#100;
// Do a bunch of random multiplies
repeat (MAX_TRIALS) begin
test_multiply ($random, $random);
end
// Special cases
test_multiply ($random, 1);
test_multiply (1, $random);
test_multiply ($random, 0);
test_multiply (0, $random);
$display ("Done. %0d Errors", num_errors);
#800;
$finish;
end
task test_multiply;
input [15:0] aarg;
input [15:0] barg;
integer expected_answer;
begin
if (~done) begin
$display ("Multiplier is Busy!!");
end
else begin
@(negedge clk);
start = 1;
a = aarg;
b = barg;
@(negedge clk) start = 0;
@(posedge done);
expected_answer = a*b;
$display ("%0d * %0d = %0h, Reality = %0h", a, b, y, expected_answer);
if (y !== expected_answer) begin
$display (" FAILURE!");
num_errors = num_errors + 1;
end
end
end
endtask
endmodule
|
module top;
event my_event;
// The following two line should be an error
// You can not take the edge of a named event.
always @(posedge my_event) $display("Posedge event.");
always @(negedge my_event) $display("Negedge event.");
// This should work correctly.
always @(my_event) $display("Any event edge.");
initial begin
#1 ->my_event;
#1 $display("FAILED");
end
endmodule
|
module top;
wire [2:0] value = 2;
shim shim(
.bit0(value[0]),
.bit1(value[1]),
.bit2(value[2])
);
endmodule
module shim(
inout wire bit0,
inout wire bit1,
inout wire bit2
);
wire [2:0] value = {bit2, bit1, bit0};
initial begin
#1 $display(value);
if (value === 2)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
timeunit 10us / 10us;
module fast_g (out);
output out;
reg\t out;
initial begin
#0 out = 0;
#1 out = 1; // 10us
end
endmodule // fast_g
`timescale 100us / 1us
// These will be ignored since a `timescale was already given.
timeunit 10us/10us;
module slow (out);
output out;
reg\t out;
initial begin
#0 out = 0;
#1 out = 1; // 100us
end
endmodule // slow
module fast (out);
timeunit 10us/1us;
output out;
reg\t out;
initial begin
#0 out = 0;
#1 out = 1; // 10us
end
endmodule // fast
module saf(out);
output out;
reg\t out;
initial begin
#0 out = 0;
#1 out = 1; // 100us
end
endmodule // saf
`timescale 1us / 1us
module main;
reg pass;
wire slow, fast, fast_g, saf;
slow m1 (slow);
fast_g m2 (fast_g);
fast m3 (fast);
saf m4 (saf);
initial begin
pass = 1\'b1;
#9;
\tif (slow !== 1\'b0) begin
\t $display("FAILED: slow at 9us, expected 1\'b0, got %b.", slow);
\t pass = 1\'b0;
\tend
\tif (saf !== 1\'b0) begin
\t $display("FAILED: saf at 9us, expected 1\'b0, got %b.", saf);
\t pass = 1\'b0;
\tend
if (fast !== 1\'b0) begin
\t $display("FAILED: fast at 9us, expected 1\'b0, got %b.", fast);
\t pass = 1\'b0;
\tend
if (fast_g !== 1\'b0) begin
\t $display("FAILED: fast_g at 9us, expected 1\'b0, got %b.", fast_g);
\t pass = 1\'b0;
\tend
#2 // 11us
\tif (slow !== 1\'b0) begin
\t $display("FAILED: slow at 11us, expected 1\'b0, got %b.", slow);
\t pass = 1\'b0;
\tend
\tif (saf !== 1\'b0) begin
\t $display("FAILED: saf at 11us, expected 1\'b0, got %b.", saf);
\t pass = 1\'b0;
\tend
if (fast !== 1\'b1) begin
\t $display("FAILED: fast at 11us, expected 1\'b1, got %b.", fast);
\t pass = 1\'b0;
\tend
if (fast_g !== 1\'b1) begin
\t $display("FAILED: fast_g at 11us, expected 1\'b1, got %b.", fast_g);
\t pass = 1\'b0;
\tend
#88 // 99 us
\tif (slow !== 1\'b0) begin
\t $display("FAILED: slow at 99us, expected 1\'b0, got %b.", slow);
\t pass = 1\'b0;
\tend
\tif (saf !== 1\'b0) begin
\t $display("FAILED: saf at 99us, expected 1\'b0, got %b.", saf);
\t pass = 1\'b0;
\tend
if (fast !== 1\'b1) begin
\t $display("FAILED: fast at 99us, expected 1\'b1, got %b.", fast);
\t pass = 1\'b0;
\tend
if (fast_g !== 1\'b1) begin
\t $display("FAILED: fast_g at 99us, expected 1\'b1, got %b.", fast_g);
\t pass = 1\'b0;
\tend
#2 // 101 us
\tif (slow !== 1\'b1) begin
\t $display("FAILED: slow at 101us, expected 1\'b1, got %b.", slow);
\t pass = 1\'b0;
\tend
\tif (saf !== 1\'b1) begin
\t $display("FAILED: saf at 101us, expected 1\'b1, got %b.", saf);
\t pass = 1\'b0;
\tend
if (fast !== 1\'b1) begin
\t $display("FAILED: fast at 101us, expected 1\'b1, got %b.", fast);
\t pass = 1\'b0;
\tend
if (fast_g !== 1\'b1) begin
\t $display("FAILED: fast_g at 101us, expected 1\'b1, got %b.", fast_g);
\t pass = 1\'b0;
\tend
if (pass) $display("PASSED");
end // initial begin
endmodule // main
|
module bug();
reg [-1:0][-1:14][-1:6] array;
reg failed = 0;
integer i;
reg signed [4:0] index;
initial begin
i = $bits(array);
$display("width 0 = %0d", i);
if (i !== 256) failed = 1;
i = $bits(array[0]);
$display("width 1 = %0d", i);
if (i !== 128) failed = 1;
i = $bits(array[0][0]);
$display("width 2 = %0d", i);
if (i !== 8) failed = 1;
for (i = 0; i < 16; i++) begin
index = i[4:0];
array[-1][-5\'sd1+index] = {4\'d0, index[3:0]};
array[ 0][-5\'sd1+index] = {4\'d1, index[3:0]};
end
$display("%h", array);
if (array !== 256\'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f)
failed = 1;
for (i = 0; i < 16; i++) begin
index = i[3:0];
$display("%h : %h %h", index, array[-1][-5\'sd1+index], array[0][-5\'sd1+index]);
if (array[-1][-5\'sd1+index] !== {4\'d0, index[3:0]}) failed = 1;
if (array[ 0][-5\'sd1+index] !== {4\'d1, index[3:0]}) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that the var keyword is supported for function ports
`define check(val, exp) \\
if (val !== exp) begin \\
$display("FAILED(%0d). \'%s\' expected %b, got %b", `__LINE__, `"val`", val, exp); \\
return 1\'b1; \\
end \\
return 1\'b0;
module test;
function bit f1 (var int x);
`check(x, 10)
endfunction
function bit f2 (input var int x);
`check(x, 20)
endfunction
function bit f3 (var [7:0] x);
`check(x, 30)
endfunction
function bit f4 (input var [7:0] x);
`check(x, 40)
endfunction
initial begin
bit failed;
failed = f1(10);
failed |= f2(20);
failed |= f3(30);
failed |= f4(40);
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module top;
initial begin
$display("Output a slash \\\\.");
$display("Output a double slash \\\\\\\\.");
end
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
*/
`timescale 1ns / 1ns
module main;
initial begin
#3 $display("$time = %t (unformatted)", $time);
$timeformat(-6, 6, "ns", 12);
$display("$time = %t (-6,6)", $time);
$timeformat(-6, 1, "ns", 12);
$display("$time = %t (-6,1)", $time);
end
endmodule // main
|
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