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// Check that structs with invalid member declarations are deteceted, report an
// error and do not cause a crash
module test;
struct packed {
logic x; // OK
logic y, z; // OK
logic bit; // Invalid
logic a b c; // Invalid
logc d; // Invalid
e; // Invalid
} s;
endmodule
|
module main;
reg [2:0] Q;
reg\t clk, clr, up;
(*ivl_synthesis_off *)
initial begin
clk = 0;
up = 0;
clr = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
\t $display("FAILED");
\t $finish;
end
up = 1;
clr = 0;
#1 clk = 1;
#1 clk = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3\'b010) begin
\t $display("FAILED");
\t $finish;
end
up = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3\'b010) begin
\t $display("FAILED");
\t $finish;
end
clr = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
$finish;
end
/*
* This statement models a snythesizable UP counter. The up
* count is enabled by the up signal. The clr is an asynchronous
* clear input.
*
* NOTE: This is bad style. Bad, bad style. It comes from a
* customer\'s customer, so I try to support it, but I\'ll moan
* about it. Much better (and clearer) is:
*
* if (clr)
* Q <= 0;
* else
* Q <= Q+1;
*/
(* ivl_synthesis_on *)
always @(posedge clk, posedge clr) begin
if (up)
\tQ = Q + 1;
if (clr)
\tQ = 0;
end
endmodule // main
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: task_port_size.v,v 1.1 2001/07/24 04:13:49 sib4 Exp $
// PR#205
module main;
function f;
input a;
begin
f = a;
end
endfunction
reg r;
initial
begin
r <= f(32\'b 101);
$display("PASSED");
end
endmodule
|
// Check that unsigned arguments to a sign cast are evaluated as self-determined.
module test;
reg [3:0] op1;
reg [2:0] op2;
reg [7:0] result;
bit failed = 1\'b0;
`define check(val, exp) \\
if (exp !== val) begin \\
$display("FAILED(%0d). Got %b, expected %b.", `__LINE__, val, exp); \\
failed = 1\'b1; \\
end
initial begin
// Addition tests
op1 = 4\'b1111; op2 = 3\'b111;
result = 8\'sd0 + signed\'(op1 + op2);
`check(result, 8\'b00000110);
result = 8\'sd0 + unsigned\'(op1 + op2);
`check(result, 8\'b00000110);
op1 = 4\'b1000; op2 = 3\'b011;
result = 8\'sd0 + signed\'(op1 + op2);
`check(result, 8\'b11111011);
result = 8\'sd0 + unsigned\'(op1 + op2);
`check(result, 8\'b00001011);
// Multiply tests
op1 = 4\'b0101; op2 = 3\'b100;
result = 8\'sd0 + signed\'(op1 * op2);
`check(result, 8\'b00000100);
result = 8\'sd0 + unsigned\'(op1 * op2);
`check(result, 8\'b00000100);
op1 = 4\'b0010; op2 = 3\'b100;
result = 8\'sd0 + signed\'(op1 * op2);
`check(result, 8\'b11111000);
result = 8\'sd0 + unsigned\'(op1 * op2);
`check(result, 8\'b00001000);
// Left ASR tests
op1 = 4\'b1010;
result = 8\'sd0 + signed\'(op1 <<< 1);
`check(result, 8\'b00000100);
result = 8\'sd0 + unsigned\'(op1 <<< 1);
`check(result, 8\'b00000100);
op1 = 4\'b0101;
result = 8\'sd0 + signed\'(op1 <<< 1);
`check(result, 8\'b11111010);
result = 8\'sd0 + unsigned\'(op1 <<< 1);
`check(result, 8\'b00001010);
// Right ASR tests
op1 = 4\'b1010;
result = 8\'sd0 + signed\'(op1 >>> 1);
`check(result, 8\'b00000101);
result = 8\'sd0 + unsigned\'(op1 >>> 1);
`check(result, 8\'b00000101);
op1 = 4\'b1010;
result = 8\'sd0 + signed\'(op1 >>> 0);
`check(result, 8\'b11111010);
result = 8\'sd0 + unsigned\'(op1 >>> 0);
`check(result, 8\'b00001010);
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module dupe;
integer cc;
reg signed [19:0] y;
initial for (cc=0; cc<20; cc=cc+1) begin
\ty = $floor(200000.0*$sin(cc*0.81)+0.5);
\t$display("%7d", y);
end
endmodule
|
module main;
reg [5:0] idx, mask;
wire [5:0] foo = idx & mask;
initial begin
mask = 5\'h1f;
for (idx = 0 ; idx < 5 ; idx = idx+1)
\twait (foo == idx) begin
\t $display("foo=%d, idx=%d", foo, idx);
\t if (foo !== idx) begin
\t $display("FAILED");
\t $finish;
\t end
\tend
$display("PASSED");
end
endmodule // main
|
timeunit 100ps / 10ps;
task delay(output [63:0] t);
begin
$printtimescale(top);
$printtimescale;
#5ns t = $time;
end
endtask
module top();
timeunit 1ns / 1ps;
reg [63:0] t1;
reg [63:0] t2;
initial begin
$printtimescale;
delay(t1);
t2 = $time;
$display("%0d %0d", t1, t2);
if ((t1 === 50) && (t2 === 5))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module test
(output reg [1:0] foo,
input wire [1:0] addr,
input wire\t in0, in1,
input wire\t en0, en1
/* */);
localparam foo_default = 2\'b00;
always @*
begin
\tfoo = foo_default;
\tcase (addr)
\t 0: if (en0) foo[0] = in0;
\t 1: if (en1) foo[1] = in1;
\t 2: foo = {in1, in0};
\t default: foo = 0;
\tendcase
end
endmodule // test
module main;
wire [1:0] foo;
reg [1:0] addr;
reg\t in0, in1;
reg\t en0, en1;
test dut(.foo(foo), .addr(addr), .in0(in0), .in1(in1), .en0(en0), .en1(en1));
initial begin
in0 = 1;
in1 = 1;
en0 = 1;
en1 = 1;
addr = 3;
#1 if (foo !== 2\'b00) begin
\t $display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
\t\t foo, in1, in0, en1, en0, addr);
\t $finish;
end
addr = 0;
#1 if (foo !== 2\'b01) begin
\t $display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
\t $finish;
end
addr = 1;
#1 if (foo !== 2\'b10) begin
\t $display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
\t $finish;
end
addr = 2;
#1 if (foo !== 2\'b11) begin
\t $display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
\t $finish;
end
en0 = 0;
en1 = 0;
addr = 3;
#1 if (foo !== 2\'b00) begin
\t $display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
\t\t foo, in1, in0, en1, en0, addr);
\t $finish;
end
addr = 0;
#1 if (foo !== 2\'b00) begin
\t $display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
\t\t foo, in1, in0, en1, en0, addr);
\t $finish;
end
addr = 1;
#1 if (foo !== 2\'b00) begin
\t $display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
\t $finish;
end
addr = 2;
#1 if (foo !== 2\'b11) begin
\t $display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
\t\t foo, in1, in0, en1, en0, addr);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* Copyright (c) 2003\tMichael Ruff (mruff at chiaro.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test that named events are passed properly to system tasks.
*/
module test();
event evt, evt2;
initial begin
\t//->evt;
\t$test(evt, evt2, test);
end
endmodule
|
// Check that it is possible to call a package scoped function.
package P;
function integer T(integer x, integer y);
return x + y;
endfunction
endpackage
module test;
initial begin
integer x;
x = P::T(1, 2);
if (x === 3) begin
$display("PASSED");
end else begin
$display("FAILED. x = %d, expected 3", x);
end
end
endmodule
|
module sysSimpleTest();
reg CLK;
reg RST_N;
initial begin
#0
RST_N = 1\'b0;
#1;
CLK = 1\'b1;
$display("reset");
#1;
RST_N = 1\'b1;
$display("reset done");
end
always
begin
#5;
CLK = 1\'b0 ;
#5;
CLK = 1\'b1 ;
end
// register y
reg [98 : 0] y;
wire [98 : 0] y$D_IN;
wire y$EN;
// register z
reg [98 : 0] z;
wire [98 : 0] z$D_IN;
wire z$EN;
// remaining internal signals
wire [98 : 0] IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29,
\t\tIF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28,
\t\tIF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30,
\t\tIF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31,
\t\tx__h201,
\t\ty__h141,
\t\tz_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d17;
wire y_SLT_0___d33,
z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22,
z_SLT_0___d32;
// register y
assign y$D_IN = 99\'h0 ;
assign y$EN = 1\'b0 ;
// register z
assign z$EN = 1\'b0 ;
assign z$D_IN = 99\'h0 ;
// remaining internal signals
assign IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29 =
\t (y_SLT_0___d33 && !z_SLT_0___d32 ||
\t !y_SLT_0___d33 && z_SLT_0___d32) ?
\t -IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30 :
\t IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30 ;
assign IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28 =
\t y_SLT_0___d33 ?
\t -IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31 :
\t IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31 ;
assign IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30 =
\t x__h201 / y__h141 ;
assign IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31 =
\t x__h201 % y__h141 ;
assign x__h201 = y_SLT_0___d33 ? -y : y ;
assign y_SLT_0___d33 =
\t (y ^ 99\'h4000000000000000000000000) <
\t 99\'h4000000000000000000000000 ;
assign y__h141 = z_SLT_0___d32 ? -z : z ;
assign z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d17 =
\t z * IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29 ;
assign z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22 =
\t z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d17 +
\t IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28 ==
\t y ;
assign z_SLT_0___d32 =
\t (z ^ 99\'h4000000000000000000000000) <
\t 99\'h4000000000000000000000000 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
// y <= 1;
// z <= 1;
y <= 99\'h7FFFFFF04A62A1453402211B2;
\tz <= 99\'h000000023E84321AAFCCC70C2;
end
else
begin
if (y$EN) y <= y$D_IN;
\tif (z$EN) z <= z$D_IN;
end
end
// synopsys translate_off
initial
begin
y = 99\'h2AAAAAAAAAAAAAAAAAAAAAAAA;
z = 99\'h2AAAAAAAAAAAAAAAAAAAAAAAA;
end
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N)
if (z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22)
\t$display("OK: %0d * %0d + %0d == %0d",
\t\t $signed(z),
\t\t $signed(IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29),
\t\t $signed(IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28),
\t\t $signed(y));
if (RST_N)
if (!z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22)
\t$display("BAD: %0d * %0d + %0d != %0d",
\t\t $signed(z),
\t\t $signed(IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29),
\t\t $signed(IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28),
\t\t $signed(y));
if (RST_N) $finish(32\'d0);
end
// synopsys translate_on
endmodule // sysSimpleTest
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Function scope handling
//
// D: Validate scope handling of variables
//
module main ();
reg [3:0] global_reg;
reg [3:0] result;
function [3:0] my_func ;
input [3:0] a;
reg [3:0] global_reg;
begin
global_reg = a + a;
my_func = a + a;
end
endfunction
initial
begin
global_reg = 2;
result = my_func(global_reg);
if(result != 4)
begin
$display("FAILED - function didn\'t function!\
");
$finish ;
end
if(global_reg != 2)
begin
$display("FAILED - function scope problem!\
");
$finish ;
end
$display("PASSED\
");
$finish ;
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always wait (expression ) reg_lvalue = constant ;
module main ;
reg [3:0] value1,value2,value3;
always wait (value1 == 4\'h3) begin
value2 = 3 ;
#1 ;
end
initial
begin
value1 = 0;
value2 = 0;
value3 = 0;
#2 ;
if(value2 != 0)
begin
$display("FAILED - 3.1.8A always wait (expr) reg_lval = const (1);");
value3 = 1;
end
value1 = 1;
#2 ;
if(value2 != 0)
begin
$display("FAILED - 3.1.8A always wait (expr) reg_lval = const (2);");
value3 = 1;
end
value1 = 2;
#2 ;
if(value2 != 0)
begin
$display("FAILED - 3.1.8A always wait (expr) reg_lval = const (3);");
value3 = 1;
end
value1 = 4\'h3;
#2;
if(value2 != 3)
begin
$display("FAILED - 3.1.8A always wait (expr) reg_lval = const (4);");
value3 = 1;
end
#10;
if(value3 == 0)
$display("PASSED");
$finish ;
end
endmodule
|
`timescale 1us/100ns
module top;
reg pass = 1\'b1;
real ra = 1.0, rb = 2.0;
wire real rpow;
/* Real Power. */
assign #1 rpow = ra ** rb;
initial begin
#0.9;
if (rpow == 1.0) begin
pass = 1\'b0;
$display("Real: power value not delayed.");
end
#0.1;
#0;
if (rpow != 1.0) begin
pass = 1\'b0;
$display("Real: power value not correct, expected 1.0 got %g.", rpow);
end
#1 ra = 2.0;
#2;
if (rpow != 4.0) begin
pass = 1\'b0;
$display("Real: power value not correct, expected 4.0 got %g.", rpow);
end
#1 ra = 0.0;
#2;
if (rpow != 0.0) begin
pass = 1\'b0;
$display("Real: power value not correct, expected 0.0 got %g.", rpow);
end
#1 ra = 10.0;
#2;
if (rpow != 100.0) begin
pass = 1\'b0;
$display("Real: power value not correct, expected 100.0 got %g.", rpow);
end
#1 ra = 0.0; rb = -1.0;
#2;
$display("0.0 ** -1.0 = %g", rpow);
#1 ra = -1.0; rb = 2.5;
#2;
$display("-1.0 ** 2.5 = %g", rpow);
if (pass) $display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate assign { ident0, ident1 } = expression ;
module main ;
wire a;
wire [30:0] b;
wire [14:0] c;
reg [31:0] val;
reg error;
assign {b,a} = val;\t\t\t// full variable
assign {c,a} = val[31:16];\t\t// Top portion bit select
initial
begin
error = 0;
if(a != 1\'bx)
begin
$display("FAILED - assign 3.2B assign ident = expr");
error = 1;
end
if(b != 31\'bx)
begin
$display("FAILED - assign 3.2B assign ident = expr");
error = 1;
end
if(c != 14\'bx)
begin
$display("FAILED - assign 3.2B assign ident = expr");
error = 1;
end
#1 ;
val = 32\'h87654321;
#1 ;
if(a != 1\'b1)
begin
$display("FAILED - 3.2A assign ident = expr");
error = 1;
end
if(b != (32\'h87654321) >> 1)
begin
$display("FAILED - 3.2A assign ident = expr");
error = 1;
end
if(c != (16\'h8765) >> 1)
begin
$display("FAILED - 3.2A assign ident = expr");
error = 1;
end
if(error == 0)
$display("PASSED");
$finish ;
end
endmodule
|
module check (input unsigned [22:0] a, b,
\t\t input unsigned [45:0] c);
wire unsigned [45:0] int_AB;
assign int_AB = a * b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
#1 A = 0;
B = 0;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 0;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = {$random} % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = {$random} % MAX;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input unsigned [22:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [45:0] r;
stimulus stim (.A(a), .B(b));
umul23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
// Check that queues with compatible packed base types can be passed as task
// arguments. Even it the element types are not identical.
module test;
typedef logic [31:0] T[$];
task t1(logic [31:0] q[$]);
q[0] = 1;
endtask
task t2(logic [7:0][3:0] q[$]);
q[0] = 1;
endtask
task t3([31:0] q[$]);
q[0] = 1;
endtask
task t4(T q);
q[0] = 1;
endtask
// For two packed types to be compatible they need to have the same packed
// width, both be 2-state or 4-state and both be either signed or unsigned.
logic [31:0] q1[$];
logic [7:0][3:0] q2[$];
initial begin
q1.push_back(1);
q2.push_back(2);
t1(q1);
t1(q2);
t2(q1);
t2(q2);
t3(q1);
t3(q2);
t4(q1);
t4(q2);
$display("PASSED");
end
endmodule
|
// Copyright 2008, Martin Whitaker.
// This file may be copied freely for any purpose. No attribution required.
module pr2169870();
task automatic count;
integer i;
begin
i = 0;
while (i < 10) begin
#1 $display("%0d", i);
i = i + 1;
end
end
endtask
initial count;
initial count;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate various module formats
module foo(a);
output a;
wire a = 1\'b1 ;
endmodule
module main;
wire b;
foo foo1 (.a());
foo foo2 (.a(b));
initial
if(!b)
$display("FAILED - 3.12B - Module with output only failed");
else
$display("PASSED");
endmodule // main
|
module main;
wire [2:0] value1, value2, value3, value4;
dut #( .select(1) ) dut1(value1);
dut #( .select(2) ) dut2(value2);
dut #( .select(3) ) dut3(value3);
dut #( .select(4) ) dut4(value4);
initial begin
#1 $display("value1=%d, value2=%d, value3=%d, value4=%d",
\t\t value1, value2, value3, value4);
if (value1 !== 1) begin
\t $display("FAILED -- value1=%b", value1);
\t $finish;
end
if (value2 !== 2) begin
\t $display("FAILED -- value2=%b", value2);
\t $finish;
end
if (value3 !== 3) begin
\t $display("FAILED -- value3=%b", value3);
\t $finish;
end
if (value4 !== 7) begin
\t $display("FAILED -- value4=%b", value4);
\t $finish;
end
$display("PASSED");
end
endmodule // main
module dut(output wire [2:0] value);
parameter select = 0;
case (select)
0: begin
\tfunction [2:0] funfun;
\t input integer in;
\t funfun = in;
\tendfunction // funfun
\tassign value = funfun(select);
end
1: begin
\tfunction [2:0] funfun;
\t input integer in;
\t funfun = in;
\tendfunction // funfun
\tassign value = funfun(1);
end
2: assign value = 2;
3: assign value = 3;
default:
assign value = 7;
endcase // case endcase
endmodule // dut
|
// Check that it is an error to declare a non-ANSI module port with implicit
// packed dimensions if it is later redeclared as a enum typed variable. Even if
// the size of the packed dimensions matches that of the size of the enum type.
typedef enum integer {
A, B
} T;
module test(x);
output [31:0] x;
T x;
initial begin
$display("FAILED");
end
endmodule
|
//
// Copyright (c) 2001 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Tests defparam \\$ in module name and if()
module test ();
parameter init = 16\'h1234;
reg [15:0] rcv;
initial
begin
#10;
rcv = init ;
$display("Init value is %h",rcv);
end
endmodule
module \\$I178 ();
defparam \\$I178 .a.init = 16\'h0040;
defparam \\$I178 .b.init = 16\'h0041;
defparam \\$I178 .c.init = 16\'h0042;
test a ();
test b ();
test c ();
reg error;
initial
begin
error = 0;
#20;
if(\\$I178 .a.rcv !== 16\'h0040)
begin
$display("FAILED");
\t error = 1;
end
if(\\$I178 .b.rcv !== 16\'h0041)
begin
$display("FAILED");
\t error = 1;
end
if(\\$I178 .c.rcv !== 16\'h0042)
begin
$display("FAILED");
\t error = 1;
end
if(error === 0)
$display("PASSED");
end
endmodule
|
/*
* This tests some compile-time division of very long constants.
*/
module main;
initial begin
$display(\'h9000_0000_0000_0000_0000 / \'h3000_0000_0000_0000_0000);
if (\'h9000_0000_0000_0000_0000 / \'h3000_0000_0000_0000_0000 !== 3) begin
\t $display("FAILED");
\t $finish;
end
$display(\'h5000_0000_0000_0000_0000 / \'h5000_0000_0000_0000_0000);
if (\'ha000_0000_0000_0000_0000 / \'h5000_0000_0000_0000_0000 !== 2) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module check (input unsigned [22:0] a, b, c);
wire unsigned [22:0] int_AB;
assign int_AB = a + b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB != c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
#1 A = 0;
B = 0;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 0;
end
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [22:0] r;
stimulus stim (.A(a), .B(b));
uadd23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#20000;
$display("PASSED");
$finish;
end
endmodule
|
module stimulus (output reg A);
initial begin
// input is x
#0 A = 1\'bx;
// input is z
#10 A = 1\'bz;
// one input is a zero
#10 A = 1\'b0;
// one input is a one
#10 A = 1\'b1;
end
endmodule
module scoreboard (input Y, A);
function truth_table (input a);
reg gate_operand;
reg gate_output;
begin
gate_operand = a;
case (gate_operand)
// input is x
1\'bx: gate_output = 1\'bx;
// inputs is z
1\'bz: gate_output = 1\'bx;
// normal operation on bit
1\'b0: gate_output = 1;
1\'b1: gate_output = 0;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A) begin
Y_t = truth_table (A);
#1;
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for input %b in NOT operation", A);
$finish;
end
end
endmodule
module test;
stimulus stim (A);
not_func duv (.a_i(A), .c_o(Y) );
scoreboard mon (Y, A);
initial begin
#200;
$display("PASSED");
$finish;
end
endmodule
|
//`timescale 1ns/1ps
module test;
reg c1reg,c2reg;
pulldown (weak0) pd1 (r1a,r1c,r1o);
pulldown (weak0) pd2 (r2a,r2c,r2o);
pulldown pd (r1a);
pullup pu (r2a);
wire c1 = c1reg;
wire c2 = c2reg;
SPDT_RELAY r1 (.COIL1(c1), .COIL2(c2), .ARM(r1a), .NC(r1c), .NO(r1o));
SPDT_RELAY r2 (.COIL1(c1), .COIL2(c2), .ARM(r2a), .NC(r2c), .NO(r2o));
initial
begin
c1reg = 0;
c2reg = 0;
repeat (16)
begin
c1reg = 1;
#10;
c1reg = 0;
#10;
end
$display ("%t: Test passed.",$realtime);
$display ("PASSED");
$finish;
end
endmodule
module SPDT_RELAY (COIL1, COIL2, ARM, NC, NO);
inout COIL1, COIL2, ARM, NC, NO;
wire coil = ((COIL1===1\'b1) && (COIL2===1\'b0)) || ((COIL1===1\'b0) && (COIL2===1\'b1));
wire #1 dly_coil = coil;
wire coil_on = coil & dly_coil;
wire coil_off = !coil & !dly_coil;
//assign NC = (coil_off) ? ARM : 1\'bz;
//assign NO = (coil_on) ? ARM : 1\'bz;
tranif1 t1 (ARM,NC,coil_off);
tranif1 t2 (ARM,NO,coil_on);
endmodule
|
module test;
event e;
initial begin
\trepeat (5) begin
\t #10;
\t ->e;
\tend
end
endmodule
|
// Check that it is not possible to assign a dynamic array with a 2-state
// element type to a dynamic array with 4-state element type. Even if they are
// otherwise identical.
module test;
logic [31:0] d1[];
bit [31:0] d2[];
initial begin
d1 = d2;
$dispaly("FAILED");
end
endmodule
|
// Check that declaring a net multiple times for a signal that was previously
// declared as a non-ANSI module port is an error.
module test(x);
input x;
wire x;
wire x;
endmodule
|
module top;
parameter rep = 4\'bx;
wire [31:0] b = {rep{8\'hab}}; // This should be a compilation error.
initial $display("FAILED");
endmodule
|
// Check that parameter declared in the module body can not be overridden by a
// defparam if the module has a parameter port list.
module a #(parameter A = 1);
// This behaves like a localparam
parameter B = 2;
initial begin
$display("FAILED");
end
endmodule
module test;
a i_a();
defparam i_a.A = 10;
defparam i_a.B = 20; // Error
endmodule
|
module top;
initial begin
// This will fail at run time.
$fdisplay(32\'h8000_000f, "write to invalid FD");
end
endmodule
|
// Check that a vector base type of a queue type gets evaluated in the right
// scope if the base type is defined in a different scope than the array type.
localparam A = 8;
typedef logic [A-1:0] Base;
module test;
localparam A = 4;
typedef Base T[$];
T x;
initial begin
x.push_back(8\'hff);
if (x[0] === 8\'hff) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module top;
parameter real rpar = 2.0;
real rvar;
real rarr [1:0];
real rout, rtmp;
wire real wrarr [1:0];
wire real wrbslv, wrpslv, wruplv, wrdolv;
wire real wrbstr, wrpstr, wruptr, wrdotr;
wire real wrpbs = rpar[0];
wire real wrpps = rpar[0:0];
wire real wrpup = rpar[0+:1];
wire real wrpdo = rpar[0-:1];
wire real wrbs = rvar[0];
wire real wrps = rvar[0:0];
wire real wrup = rvar[0+:1];
wire real wrdo = rvar[0-:1];
wire real wrabs = rarr[0][0];
wire real wraps = rarr[0][0:0];
wire real wraup = rarr[0][0+:1];
wire real wrado = rarr[0][0-:1];
assign wrbslv[0] = rvar;
assign wrpslv[0:0] = rvar;
assign wruplv[0+:1] = rvar;
assign wrdolv[0-:1] = rvar;
assign wrarr[0][0] = rvar;
assign wrarr[0][0:0] = rvar;
assign wrarr[0][0+:1] = rvar;
assign wrarr[0][0-:1] = rvar;
tran(wrbstr[0], wrarr[1]);
tran(wrpstr[0:0], wrarr[1]);
tran(wruptr[0+:1], wrarr[1]);
tran(wrdotr[0-:1], wrarr[1]);
submod1 s1 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]);
submod2 s2 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]);
submod3 s3 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]);
initial begin
rtmp = rpar[0];
rtmp = rpar[0:0];
rtmp = rpar[0+:1];
rtmp = rpar[0-:1];
rtmp = rvar[0];
rtmp = rvar[0:0];
rtmp = rvar[0+:1];
rtmp = rvar[0-:1];
rtmp = rarr[0][0];
rtmp = rarr[0][0:0];
rtmp = rarr[0][0+:1];
rtmp = rarr[0][0-:1];
rout[0] = 2.0;
rout[0:0] = 2.0;
rout[0+:1] = 2.0;
rout[0-:1] = 2.0;
rarr[0][0] = 1.0;
rarr[0][0:0] = 1.0;
rarr[0][0+:1] = 1.0;
rarr[0][0-:1] = 1.0;
end
endmodule
module submod1(arg1, arg2, arg3, arg4);
input arg1, arg2, arg3, arg4;
wire real arg1, arg2, arg3, arg4;
initial $display("In submod1 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
endmodule
module submod2(arg1, arg2, arg3, arg4);
output arg1, arg2, arg3, arg4;
real arg1, arg2, arg3, arg4;
initial $display("In submod2 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
endmodule
module submod3(arg1, arg2, arg3, arg4);
inout arg1, arg2, arg3, arg4;
wire real arg1, arg2, arg3, arg4;
initial $display("In submod3 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
endmodule
|
// Verify that icarus can handle real compare versus int constant
module test ();
real myv;
parameter myp = 1.0;
initial
begin
myv = 1.0;
if(myv <= 1)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module main;
integer x;
initial begin
x = $copy_test(1);
if (x !== 1) begin
\t $display("FAILED -- x == %b (should be 1)", x);
\t $finish;
end
x = $copy_test(8);
if (x !== 8) begin
\t $display("FAILED -- x == %b (should be 8)", x);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module top;
reg q, clk, d;
always_ff begin
q <= d;
@(posedge clk);
end
initial $display("Expected compile failure!");
endmodule
|
// Check that functions returning a class object are supported
module test;
class C;
int i;
task t;
if (i == 10) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
endclass
function C f;
C c;
c = new;
c.i = 10;
return c;
endfunction
initial begin
C c;
c = f();
c.t;
end
endmodule
|
// Regression test for GitHub issue 25
// This should result in a compile-time error when the language generation
// is 1364-2005 or earlier.
task test(input i, output o);
begin
o = i;
end
endtask
module tb;
reg passed = 0;
initial begin
test(1, passed);
if (passed)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module top;
reg result;
initial begin
result = $isunknown(top);
result = $isunknown("a string");
result = $isunknown(4\'b001, 1\'b0);
end
endmodule
|
// $abs should take a real argument and return a real result.
module test();
localparam s = 0;
localparam a = 1.5;
localparam b = 1;
localparam r = $abs((s ? a : b) / 2);
initial begin
$display("%g", r);
if (r == 0.5)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// Check the various variable array selects (large to small).
module top;
reg passed;
wire [1:0] a [4:1];
wire [0:0] s0 = 0;
wire [1:0] s1 = 0;
wire [2:0] s2 = 0;
reg [1:0] ar [4:1];
wire [1:0] c [0:-3];
wire [0:0] s3 = 0;
wire [1:0] s4 = 0;
reg [1:0] cr [0:-3];
wire [1:0] res_a0 = a[s0];
wire [1:0] res_a1 = a[s1];
wire [1:0] res_a2 = a[s2];
wire [1:0] res_c3 = c[s3];
wire [1:0] res_c4 = c[s4];
reg res_a [4:1];
reg res_c [0:-3];
assign a[1] = 2\'d0;
assign a[2] = 2\'b1;
assign a[3] = 2\'d2;
assign a[4] = 2\'d3;
assign c[-3] = 2\'d0;
assign c[-2] = 2\'b1;
assign c[-1] = 2\'d2;
assign c[0] = 2\'d3;
initial begin
#1;
passed = 1\'b1;
ar[1] = 2\'d0;
ar[2] = 2\'b1;
ar[3] = 2\'d2;
ar[4] = 2\'d3;
cr[-3] = 2\'d0;
cr[-2] = 2\'b1;
cr[-1] = 2\'d2;
cr[0] = 2\'d3;
// Check procedural R-value variable bit selects of a net.
$display("a[s0]: %b", a[s0]);
if (a[s0] !== 2\'bxx) begin
$display("Failed a[s0], expected 2\'bxx, got %b", a[s0]);
passed = 1\'b0;
end
$display("a[s1]: %b", a[s1]);
if (a[s1] !== 2\'bxx) begin
$display("Failed a[s1], expected 2\'bxx, got %b", a[s1]);
passed = 1\'b0;
end
$display("a[s2]: %b", a[s2]);
if (a[s2] !== 2\'bxx) begin
$display("Failed a[s2], expected 2\'bxx, got %b", a[s2]);
passed = 1\'b0;
end
$display("c[s3]: %b", c[s3]);
if (c[s3] !== 2\'b11) begin
$display("Failed c[s3], expected 2\'b11, got %b", c[s3]);
passed = 1\'b0;
end
$display("c[s4]: %b", c[s4]);
if (c[s4] !== 2\'b11) begin
$display("Failed c[s4], expected 2\'b11, got %b", c[s4]);
passed = 1\'b0;
end
// Check procedural R-value variable bit selects of a reg.
$display("ar[s0]: %b", ar[s0]);
if (ar[s0] !== 2\'bxx) begin
$display("Failed ar[s0], expected 2\'bxx, got %b", ar[s0]);
passed = 1\'b0;
end
$display("ar[s1]: %b", ar[s1]);
if (ar[s1] !== 2\'bxx) begin
$display("Failed ar[s1], expected 2\'bxx, got %b", ar[s1]);
passed = 1\'b0;
end
$display("ar[s2]: %b", ar[s2]);
if (ar[s2] !== 2\'bxx) begin
$display("Failed ar[s2], expected 2\'bxx, got %b", ar[s2]);
passed = 1\'b0;
end
$display("cr[s3]: %b", cr[s3]);
if (cr[s3] !== 2\'b11) begin
$display("Failed cr[s3], expected 2\'b11, got %b", cr[s3]);
passed = 1\'b0;
end
$display("cr[s4]: %b", cr[s4]);
if (cr[s4] !== 2\'b11) begin
$display("Failed cr[s4], expected 2\'b11, got %b", cr[s4]);
passed = 1\'b0;
end
// Check continuous assignment R-value variable bit selects.
if (res_a0 !== 2\'bxx) begin
$display("Failed res_a0, expected 2\'bxx, got %b", res_a0);
passed = 1\'b0;
end
if (res_a1 !== 2\'bxx) begin
$display("Failed res_a1, expected 2\'bxx, got %b", res_a1);
passed = 1\'b0;
end
if (res_a2 !== 2\'bxx) begin
$display("Failed res_a2, expected 2\'bxx, got %b", res_a2);
passed = 1\'b0;
end
if (res_c3 !== 2\'b11) begin
$display("Failed res_c3, expected 2\'b11, got %b", res_c3);
passed = 1\'b0;
end
if (res_c4 !== 2\'b11) begin
$display("Failed res_c4, expected 2\'b11, got %b", res_c4);
passed = 1\'b0;
end
// Check procedural L-value variable bit selects.
res_a[1] = 1\'bx;
res_a[2] = 1\'bx;
res_a[3] = 1\'bx;
res_a[4] = 1\'bx;
res_a[s0] = 1\'b0;
if (res_a[1] !== 1\'bx) begin
$display("Failed res_a[s0], expected 1\'bx for [1], got %b", res_a[1]);
passed = 1\'b0;
end
if (res_a[2] !== 1\'bx) begin
$display("Failed res_a[s0], expected 1\'bx for [2], got %b", res_a[2]);
passed = 1\'b0;
end
if (res_a[3] !== 1\'bx) begin
$display("Failed res_a[s0], expected 1\'bx for [3], got %b", res_a[3]);
passed = 1\'b0;
end
if (res_a[4] !== 1\'bx) begin
$display("Failed res_a[s0], expected 1\'bx for [4], got %b", res_a[4]);
passed = 1\'b0;
end
res_a[1] = 1\'bx;
res_a[2] = 1\'bx;
res_a[3] = 1\'bx;
res_a[4] = 1\'bx;
res_a[s1] = 1\'b0;
if (res_a[1] !== 1\'bx) begin
$display("Failed res_a[s1], expected 1\'bx for [1], got %b", res_a[1]);
passed = 1\'b0;
end
if (res_a[2] !== 1\'bx) begin
$display("Failed res_a[s1], expected 1\'bx for [2], got %b", res_a[2]);
passed = 1\'b0;
end
if (res_a[3] !== 1\'bx) begin
$display("Failed res_a[s1], expected 1\'bx for [3], got %b", res_a[3]);
passed = 1\'b0;
end
if (res_a[4] !== 1\'bx) begin
$display("Failed res_a[s1], expected 1\'bx for [4], got %b", res_a[4]);
passed = 1\'b0;
end
res_a[1] = 1\'bx;
res_a[2] = 1\'bx;
res_a[3] = 1\'bx;
res_a[4] = 1\'bx;
res_a[s2] = 1\'b0;
if (res_a[1] !== 1\'bx) begin
$display("Failed res_a[s2], expected 1\'bx for [1], got %b", res_a[1]);
passed = 1\'b0;
end
if (res_a[2] !== 1\'bx) begin
$display("Failed res_a[s2], expected 1\'bx for [2], got %b", res_a[2]);
passed = 1\'b0;
end
if (res_a[3] !== 1\'bx) begin
$display("Failed res_a[s2], expected 1\'bx for [3], got %b", res_a[3]);
passed = 1\'b0;
end
if (res_a[4] !== 1\'bx) begin
$display("Failed res_a[s2], expected 1\'bx for [4], got %b", res_a[4]);
passed = 1\'b0;
end
res_c[-3] = 1\'bx;
res_c[-2] = 1\'bx;
res_c[-1] = 1\'bx;
res_c[0] = 1\'bx;
res_c[s3] = 1\'b0;
if (res_c[-3] !== 1\'bx) begin
$display("Failed res_c[s3], expected 1\'bx for [-3], got %b", res_c[-3]);
passed = 1\'b0;
end
if (res_c[-2] !== 1\'bx) begin
$display("Failed res_c[s3], expected 1\'bx for [-2], got %b", res_c[-2]);
passed = 1\'b0;
end
if (res_c[-1] !== 1\'bx) begin
$display("Failed res_c[s3], expected 1\'bx for [-1], got %b", res_c[-1]);
passed = 1\'b0;
end
if (res_c[0] !== 1\'b0) begin
$display("Failed res_c[s3], expected 1\'b0 for [0], got %b", res_c[0]);
passed = 1\'b0;
end
res_c[-3] = 1\'bx;
res_c[-2] = 1\'bx;
res_c[-1] = 1\'bx;
res_c[0] = 1\'bx;
res_c[s4] = 1\'b0;
if (res_c[-3] !== 1\'bx) begin
$display("Failed res_c[s4], expected 1\'bx for [-3], got %b", res_c[-3]);
passed = 1\'b0;
end
if (res_c[-2] !== 1\'bx) begin
$display("Failed res_c[s4], expected 1\'bx for [-2], got %b", res_c[-2]);
passed = 1\'b0;
end
if (res_c[-1] !== 1\'bx) begin
$display("Failed res_c[s4], expected 1\'bx for [-1], got %b", res_c[-1]);
passed = 1\'b0;
end
if (res_c[0] !== 1\'b0) begin
$display("Failed res_c[s4], expected 1\'b0 for [0], got %b", res_c[0]);
passed = 1\'b0;
end
if (passed) $display("Compare tests passed");
end
endmodule
|
module dut1(input real i1, output real o1);
assign o1 = i1;
endmodule
module dut2(input real i2, output real o2);
assign o2 = i2;
endmodule
module test();
real a, b, c;
dut2 dut2(a, b);
dut1 dut1(b, c);
initial begin
$list_vars;
end
endmodule
|
module top;
reg value = 1;
integer val = 100;
initial begin
$display("1. The value is %3d", value*100);
$display("2. The value is %3.0f", value*100.0);
$display("3. The value is %3.0f", 100);
$display("4. The value is %3.0f", val);
$display("5. The value is %3.0f", value*100); // This fails!
$finish(0);
end
endmodule
|
// Check that a SystemVerilog do/while loop works correctly.
module top;
int i;
initial begin
i = 0;
do begin
i += 1;
$display("The value of i is %0d", i);
end while (i < 2);
$display("PASSED");
end
endmodule
|
module top;
reg [47:0] out1, out2, out3, out4, out5;
integer i;
initial begin
for (i=-1 ; i<2; i=i+1) begin
// i is signed so should it be sign extended?
out1 = 48\'d16 + i;
// I would have expected this to be the same as (i+0) below!
out2 = 48\'d16 + (i);
// All the rest of these are sign extended?
out3 = 48\'d16 + (i+0);
out4 = 48\'sd16 + i;
out5 = 48\'d16 + (i-1);
$display("16 + %2d = %10d, %10d, %2d, %2d, -1 = %2d",
i, out1, out2, out3, out4, out5);
end
end
endmodule
|
// Test that cast to enum works in procedural assignments
module test();
typedef enum { a, b, c } enum_type;
enum_type enum_value;
initial begin
enum_value = enum_type\'(1);
if (enum_value == b) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
// test that .* implicit ports work with override
module m(input a, output b, output c, output d, output e);
assign b = a;
assign c = ~a;
assign d = ~a;
assign e = ~a;
endmodule
module top;
reg a;
reg x;
wire b, d;
m foo(.a(x), .e(), .*, .c(d), .d());
m foo2(.a(x), .d(), .*, .c(), .e());
m foo3(.a(x), .*, .d(), .c(), .e());
m foo4(.*, .a(x), .d(), .c(), .e());
m foo5(.a(x), .d(), .c(), .*, .e());
m foo6(.a(x), .d(), .c(), .e(), .*);
initial begin
a = 0;
x = 1;
#1 if (b !== x || d !== ~x) begin
$display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d);
end
#1 a = 1;
#1 if (b !== x || d !== ~x) begin
$display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d);
end
$display("PASSED");
end
endmodule
|
// We want to print a warning if we find a delay that comes from the
// default timescale (1s) and then one from a given timescale.
// Basically we want to have either the case of no timescales or
// timescales for all delays.
module wo_time;
initial #1 $display("The time in %m is: %e", $abstime);
endmodule
`timescale 1ns/1ns
module w_time;
initial #1 $display("The time in %m is: %e", $abstime);
endmodule
|
module top;
reg q, en, d;
always_latch begin
if (en) #0 q <= d;
end
initial $display("Expected compile failure!");
endmodule
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [1:0] out;
initial begin
out = 2\'b0;
if (out !== 2\'b0) begin
\t $display("FAILED to initialize: out == %b", out);
\t $finish;
end
out <= #5 2\'b1;
if (out !== 2\'b0) begin
\t $display("FAILED -- changed immediately: out == %b", out);
\t $finish;
end
#4 if (out !== 2\'b0) begin
\t $display("FAILED -- changed too soon: out == %b", out);
\t $finish;
end
#2 if (out !== 2\'b1) begin
\t $display("FAILED to change after delay: out == %b", out);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// pr1697250
module test();
wire active;
reg [63:0] bus;
assign active = ((|(bus)===0)?0:1);
initial begin
bus = \'haaaa;
#1 if (active !== 1) begin
\t $display("FAILED -- bus=%h, active=%b", bus, active);
\t $finish;
end
bus = 0;
#1 if (active !== 0) begin
\t $display("FAILED == bus=%h, active=%b", bus, active);
\t $finish;
end
$display("PASSED");
end
endmodule
|
/*
* Author: Oswaldo Cadenas <[email protected]>
*
* The test checks the module reg ouput type accepts default
* initialization value. If no default value is given to reg output
* type then this test fails.
*/
module clkgen(output reg clk = 0);
initial begin
#100;
disable checking;
disable gen;
$display ("PASSED");
$finish;
end
initial begin
fork
gen;
checking;
join
end
task gen;
forever #10 clk = ~clk;
endtask
task checking;
forever begin
#1;
if (clk === 1\'bx ) begin
$display ("FAILED!");
\t $finish;
end
end
endtask
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate that an array of modules in supported.
//
module my_and (out,a,b);
input a,b;
output out;
and u0 (out,a,b);
endmodule
module main;
reg globvar;
wire [15:0] out;
reg [15:0] a,b, rslt;
reg error;
// The test gate goes HERE!
my_and foo [0:15] (out,a,b);
always @(a or b)
rslt = a & b;
initial
begin // {
error = 0;
# 1;
for(a = 16\'h1; a != 16\'hffff; a = (a << 1) | 1)
begin // {
for(b = 16\'hffff; b !== 16\'h0; b = b >> 1)
begin // {
#1 ;
if(out !== rslt)
begin // {
$display("FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h",
a,b,rslt,out);
error = 1;
end // }
end // }
end // }
if( error == 0)
$display("PASSED");
end // }
endmodule // main
|
module top;
reg [31:0] in_32, out_32, out_32x;
reg [63:0] out_64;
integer res, fd;
reg passed;
initial begin
passed = 1\'b1;
// Check that a normal 32 bit %z catches missing bytes.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%u", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #1 returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that a normal 64 bit %z catches missing bytes (1/4).
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%u", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%z", out_64);
if (res !== -1) begin
$display("FAILED: $fscanf() #2a returned %d (%b)", res, out_64);
passed = 1\'b0;
end
$fclose(fd);
// Check that a normal 64 bit %z catches missing bytes (1/2).
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%z", out_64);
if (res !== -1) begin
$display("FAILED: $fscanf() #2b returned %d (%b)", res, out_64);
passed = 1\'b0;
end
$fclose(fd);
// Check that a normal 64 bit %z catches missing bytes (3/4).
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z%u", in_32, in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%z", out_64);
if (res !== -1) begin
$display("FAILED: $fscanf() #2c returned %d (%b)", res, out_64);
passed = 1\'b0;
end
$fclose(fd);
// Check that a normal 32 bit %z suppression catches missing bytes.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%u", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%*z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #3 returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that a multiple read %z catches missing bytes (1/2).
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z%u", in_32, in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%z%z", out_32, out_32x);
if (res !== 1) begin
$display("FAILED: $fscanf() #4 returned %d (%b)", res, out_32x);
passed = 1\'b0;
end else begin
if (in_32 !== out_32) begin
$display("FAILED: $fscanf() #4 %b !== %b", in_32, out_32);
passed = 1\'b0;
end
if (out_32x !== 32\'bx) begin
$display("FAILED: $fscanf() #4 %b !== 32\'bx", out_32x);
passed = 1\'b0;
end
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #4 EOF returned %d (%b)", res, out_32);
passed = 1\'b0;
end
$fclose(fd);
// Check that a suppression/read %z catches missing bytes (1/2).
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z%u", in_32, in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
out_32 = 32\'bx;
res = $fscanf(fd, "%*z%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #5 returned %d (%b)", res, out_32);
passed = 1\'b0;
end else if (out_32 !== 32\'bx) begin
$display("FAILED: $fscanf() #5 %b !== 32\'bx", out_32);
passed = 1\'b0;
end
$fclose(fd);
if (passed) $display("PASSED");
end
endmodule
|
module pr2849783();
reg i;
wire a, b, c, d;
assign a = i;
assign b = a;
assign c = 1;
assign d = c;
reg pass;
initial begin
i = 1;
pass = 1;
#1 $display("%b %b", a, b);
if ((a !== 1) || (b !== 1)) pass = 0;
#1 force a = 0;
#1 $display("%b %b", a, b);
if ((a !== 0) || (b !== 0)) pass = 0;
#1 release a;
#1 $display("%b %b", a, b);
if ((a !== 1) || (b !== 1)) pass = 0;
#1 $display("%b %b", c, d);
if ((c !== 1) || (d !== 1)) pass = 0;
#1 force c = 0;
#1 $display("%b %b", c, d);
if ((c !== 0) || (d !== 0)) pass = 0;
#1 release c;
#1 $display("%b %b", c, d);
if ((c !== 1) || (d !== 1)) pass = 0;
if (pass)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW: Module instantiation with non-ordered port assignment
//
// D: Same as sdw_inst1 except using .net(net) port convention.
//
module test_mod (reset,clka,out);
input reset;
input clka;
output out;
reg out;
always @(posedge clka or posedge reset)
if(reset)
out = 0;
else
out = ~out;
endmodule
module main();
reg reset,clk_0,clk_1;
wire out_0,out_1;
test_mod module_1 (.reset(reset),.clka(clk_0),.out(out_0));
test_mod module_2 (.reset(reset),.clka(clk_1),.out(out_1));
initial
begin
clk_0 = 0;
clk_1 = 0;
#1 reset = 1;
# 2;
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\
",$time,reset,clk_0,
clk_1,out_0,out_1);
// Validate that both out_0 and out_1 are reset
if(out_0)
begin
$display("FAILED - out_0 not reset\
");
$finish ;
end
if(out_1)
begin
$display("FAILED - out_1 not reset\
");
$finish ;
end
reset = 0;
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\
",$time,reset,clk_0,
clk_1,out_0,out_1);
# 2;
clk_0 = 1;
# 2; // Wait so we don\'t worry about races.
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\
",$time,reset,clk_0,
clk_1,out_0,out_1);
if(!out_0)
begin
$display("FAILED - out_0 didn\'t set on clk_0\
");
$finish ;
end
if(out_1)
begin
$display("FAILED - out_1 set on wrong clk!\
");
$finish ;
end
clk_1 = 1;
# 2; // Wait so we don\'t worry about races.
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\
",$time,reset,clk_0,
clk_1,out_0,out_1);
if(!out_1)
begin
$display("FAILED - out_1 didn\'t set on clk_1\
");
$finish ;
end
if(!out_0)
begin
$display("FAILED - out_0 changed due to clk_0\
");
$finish ;
end
$display("PASSED\
");
$finish ;
end
endmodule
|
module bug04_integerDiv;
reg passed;
reg signed[31:0] reg0;
reg signed[31:0] reg1;
reg signed[31:0] rquot;
wire signed[31:0] dividend=reg0;
wire signed[31:0] divisor=reg1;
wire signed[31:0] quotient;
assign quotient= dividend/divisor;
initial begin
\tpassed = 1\'b1;
\treg0=32\'h76c3625e;
\treg1=32\'hffffffff;
\t//BUG here: quotient==32\'hxxxxxxxx, should be 32\'h893c9da2
\t#1 if (quotient !== 32\'h893c9da2) begin
\t\t$display("Failed: CA division, expected 32\'h893c9da2, got %h",
\t\t quotient);
\t\tpassed = 1\'b0;
\tend
\trquot = reg0/reg1;
\tif (rquot !== 32\'h893c9da2) begin
\t\t$display("Failed: division, expected 32\'h893c9da2, got %h",
\t\t rquot);
\t\tpassed = 1\'b0;
\tend
\tif (passed) $display("PASSED");
end
endmodule
|
module top;
integer result;
initial begin
result = $countones(top);
result = $countones("a string");
result = $countones(4\'b001, 1\'b0);
end
endmodule
|
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test some multiply values for an 18*18-->36 multiply.
*/
module main;
wire [35:0] p;
reg [17:0] a, b;
reg\t clk, ce, reset;
parameter MAX_TRIALS = 1000;
integer idx;
MULT18X18S dut (p, a, b, clk, ce, reset);
initial begin
clk <= 0;
ce <= 1;
reset <= 1;
a <= 0;
b <= 0;
#5 clk <= 1;
#5 clk <= 0;
if (p !== 36\'h0) begin
\t $display("FAILED -- reset p=%h", p);
\t $finish;
end
reset <= 0;
/* A magical value I know failed at one time. */
a <= 18\'h3ff82;
b <= 18\'h04000;
#5 clk <= 1;
#5 clk <= 0;
if (p !== 36\'hfffe08000) begin
\t $display("FAILED -- %h * %h --> %h", a, b, p);
\t $finish;
end
for (idx = 0 ; idx < MAX_TRIALS ; idx = idx + 1) begin
\t a <= $random;
\t b <= $random;
\t #5 clk <= 1;
\t #5 clk <= 0;
\t if ($signed(p) !== ($signed(a) * $signed(b))) begin
\t $display("FAILED == %h * %h --> %h", a, b, p);
\t $finish;
\t end
end // for (idx = 0 ; idx < `MAX_TRIALS ; idx = idx + 1)
$display("PASSED");
end // initial begin
endmodule // main
module MULT18X18S (output reg [35:0] P,
\t\t input [17:0] A,
\t\t input [17:0] B,
\t\t input C, CE, R);
wire [35:0] a_in = { {18{A[17]}}, A[17:0] };
wire [35:0] b_in = { {18{B[17]}}, B[17:0] };
wire [35:0] p_in;
reg [35:0] p_out;
assign p_in = a_in * b_in;
always @(posedge C)
if (R)
P <= 36\'b0;
else if (CE)
P <= p_in;
endmodule
|
module top();
integer i = 1;
integer j = 0;
always @(i) j = i;
initial begin
#0 $display("%0d %0d", i, j);
if ((i === 1) && (j === 0))
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
`begin_keywords "1364-2005"
module automatic_error();
task automatic auto_task;
integer local;
begin
$monitor("%0d", local);
#1 local = 0;
#1 local = 1;
end
endtask
initial auto_task;
endmodule
`end_keywords
|
/*
* Copyright (c) 2014 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
`default_nettype none
class test_t;
reg [1:0] a;
reg [2:0] b;
function new (int ax, int bx);
begin
\t a = ax;
\t b = bx;
end
endfunction // new
endclass // test_t
module main;
class container_t;
test_t foo [0:3][0:7];
function new();
\t bit [3:0] idx1, idx2;
\t begin
\t for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
\t for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
\t\t foo[idx1][idx2] = new(idx1,idx2);
\t end
\t end
endfunction // new
task run();
\t bit [3:0] idx1, idx2;
\t test_t tmp;
\t foreach (foo[ia,ib]) begin
\t if (ia > 3 || ib > 7) begin
\t $display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib);
\t $finish;
\t end
\t tmp = foo[ia][ib];
\t if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin
\t $display("FAILED -- foo[%0d][%0d] == %b", ia, ib, {tmp.a, tmp.b});
\t $finish;
\t end
\t foo[ia][ib] = null;
\t end
\t for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
\t for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
\t if (foo[idx1][idx2] != null) begin
\t\t $display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2);
\t\t $finish;
\t end
\t end
endtask // run
endclass
container_t dut;
initial begin
dut = new;
dut.run;
$display("PASSED");
end
endmodule // main
|
program main;
function string sum_array(string array[]);
int idx;
sum_array = "";
for (idx = 0 ; idx < array.size() ; idx = idx+1)
\tsum_array = {sum_array, array[idx]};
endfunction // sum_array
string obj[];
string foo;
initial begin
foo = sum_array(\'{});
if (foo != "") begin
\t $display("FAILED -- sum of empty array returns %0s", foo);
\t $finish;
end
obj = new[3];
obj = \'{"1", "2", "3"};
foo = sum_array(obj);
if (foo != "123") begin
\t $display("FAILED -- sum of \'{\\"1\\",\\"2\\",\\"3\\"} is %0s", foo);
\t $finish;
end
obj = new[3] (\'{"A", "B", "C"});
foo = sum_array(obj);
if (foo != "ABC") begin
\t $display("FAILED -- sum of \'{\\"A\\",\\"B\\",\\"C\\"} is %0s", foo);
\t $finish;
end
obj = new[3] ("A");
foo = sum_array(obj);
if (foo != "AAA") begin
\t $display("FAILED -- sum of \\"AAA\\" is %0s", foo);
\t $finish;
end
$display("PASSED");
end // initial begin
endprogram // main
|
`begin_keywords "1364-2005"
`timescale 1ns/1ns
module test;
\treg fail = 0;
\ttask check;
\t\tinput [10*8:1] expect;
\t\treg [10*8:1] s;
\t\tbegin
\t\t\t$swrite(s, "Time %t", $time);
\t\t\t$write("%s", s);
\t\t\tif (s === expect)
\t\t\t\t$display("");
\t\t\telse
\t\t\tbegin
\t\t\t\t$display(" != %s", expect);
\t\t\t\tfail = 1;
\t\t\tend
\t\tend
\tendtask
\tinitial
\tbegin
\t\t$display("Test display formatting of time values");
\t\t$timeformat(-6, 3, " us", 20);
\t\tfork
\t\t\t#0000 check(" 0.000 us");
\t\t\t#0001 check(" 0.001 us");
\t\t\t#0010 check(" 0.010 us");
\t\t\t#0011 check(" 0.011 us");
\t\t\t#0100 check(" 0.100 us");
\t\t\t#0101 check(" 0.101 us");
\t\t\t#1000 check(" 1.000 us");
\t\t\t#1001 check(" 1.001 us");
\t\tjoin
\t\t$display("%s", fail? "FAILED" : "PASSED");
\tend
endmodule
`end_keywords
|
// This test program shows how programs can be instantiated
// within another module.
program test(input [7:0] sh1, input [7:0] sh2);
final begin
if (sh1 !== \'h55) begin
\t $display("FAILED -- shared=%b is not correct", sh1);
\t $finish;
end
if (sh2 !== \'haa) begin
\t $display("FAILED -- sh2 not correct", sh2);
\t $finish;
end
$display("PASSED");
end
endprogram :test
module main;
reg[7:0] shared = \'h55;
wire [7:0] not_shared = ~shared;
test check(shared, not_shared);
endmodule // main
|
module MULT32;
wire VDD = 1 ;
wire VSS = 0 ;
wire X00, X31 ;
reg [1:0] state ;
assign {X31, X00} = state ;
ADDERXY XX1 (VSS, N1110, VSS, N2166, X00, X31);\t/* This one! */
ADDERXY XX127 (N1076, N1044, N2131, N2100, VSS, VSS);
initial
\tbegin
\tstate = 0 ;
\t$monitor( X00, X31, VSS, VSS,,, N2166, N1110 ) ;
\t#10 state = 1 ;
\t#10 state = 0 ;
\t#10 state = 1 ;
\t#10 state = 0 ;
\t#10 $finish(0);
\tend
endmodule
module ADDERXY( cin, cout, b, sum, x, y );
input cin, b, x, y;
output cout, sum;
reg [1:0] total ;
assign sum = total[0] ;
assign cout = total[1] ;
always @ (x or y or b or cin)
\tbegin
\t total = ( x & y ) + b + cin ;
\tend
endmodule // ADDERXY
|
module top;
reg[63:0] a;
initial begin
a = 64\'h7fe8000000000000;
// This used to fail because we printed floating point using
// the default buffer which was only 256 bytes long. To fix
// this the default size was changed to 512 bytes and this is
// increased when needed (%400.300f, etc.).
$display("%6.3f", $bitstoreal(a));
$display("PASSED");
end
endmodule
|
// Test mixed type/width case expressions inside a constant function
module constfunc13();
function [2:0] lookup1(input signed [2:0] value);
begin
case (value)
4\'sb0100 : lookup1 = 1;
3\'sb100 : lookup1 = 2;
2\'sb10 : lookup1 = 3;
default : lookup1 = 4;
endcase
$display("case = %d", lookup1);
end
endfunction
function [2:0] lookup2(input signed [2:0] value);
begin
case (value)
4\'b1100 : lookup2 = 1;
3\'sb100 : lookup2 = 2;
2\'sb10 : lookup2 = 3;
default : lookup2 = 4;
endcase
$display("case = %d", lookup2);
end
endfunction
function [2:0] lookup3(input real value);
begin
case (value)
4\'b0001 : lookup3 = 1;
3\'sb010 : lookup3 = 2;
2\'sb11 : lookup3 = 3;
default : lookup3 = 4;
endcase
$display("case = %d", lookup3);
end
endfunction
function [2:0] lookup4(input signed [2:0] value);
begin
case (value)
4\'b0110 : lookup4 = 1;
3\'sb110 : lookup4 = 2;
-1.0 : lookup4 = 3;
default : lookup4 = 4;
endcase
$display("case = %d", lookup4);
end
endfunction
localparam res11 = lookup1(3\'sb100);
localparam res12 = lookup1(3\'sb110);
localparam res13 = lookup1(3\'sb010);
localparam res21 = lookup2(3\'sb100);
localparam res22 = lookup2(3\'sb010);
localparam res23 = lookup2(3\'sb110);
localparam res31 = lookup3( 1.0);
localparam res32 = lookup3( 2.0);
localparam res33 = lookup3(-1.0);
localparam res34 = lookup3( 1.5);
localparam res41 = lookup4(3\'sb110);
localparam res42 = lookup4(3\'sb111);
localparam res43 = lookup4(3\'sb011);
reg failed = 0;
initial begin
$display("case = %d", res11); if (res11 != 2) failed = 1;
$display("case = %d", res12); if (res12 != 3) failed = 1;
$display("case = %d", res13); if (res13 != 4) failed = 1;
$display("");
$display("case = %d", res21); if (res21 != 2) failed = 1;
$display("case = %d", res22); if (res22 != 3) failed = 1;
$display("case = %d", res23); if (res23 != 4) failed = 1;
$display("");
$display("case = %d", res31); if (res31 != 1) failed = 1;
$display("case = %d", res32); if (res32 != 2) failed = 1;
$display("case = %d", res33); if (res33 != 3) failed = 1;
$display("case = %d", res34); if (res34 != 4) failed = 1;
$display("");
$display("case = %d", res41); if (res41 != 2) failed = 1;
$display("case = %d", res42); if (res42 != 3) failed = 1;
$display("case = %d", res43); if (res43 != 4) failed = 1;
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that the var keyword is supported for module non-ANSI output ports
bit failed = 1\'b0;
`define check(val, exp) \\
if (val !== exp) begin \\
$display("FAILED(%0d). \'%s\' expected %b, got %b", `__LINE__, `"val`", val, exp); \\
failed = 1\'b1; \\
end
module M(x, y, z, w);
parameter VAL_X = 0;
parameter VAL_Y = 0;
parameter VAL_Z = 0;
parameter VAL_W = 0;
output var x;
output var [7:0] y;
output var signed [7:0] z;
output var logic [7:0] w;
assign x = VAL_X;
assign y = VAL_Y;
assign z = VAL_Z;
assign w = VAL_W;
endmodule
module test;
logic x1;
logic x2;
logic [7:0] y1;
logic [7:0] y2;
logic signed [7:0] z1;
logic signed [7:0] z2;
logic [7:0] w1;
logic [7:0] w2;
M #(
.VAL_X (1\'b1),
.VAL_Y (10),
.VAL_Z (-1),
.VAL_W (20)
) i_m1 (
.x (x1),
.y (y1),
.z (z1),
.w (w1)
);
// The type for var should default to logic, check that the value can be X
M #(
.VAL_X (1\'bx),
.VAL_Y (8\'hxx),
.VAL_Z (8\'hxx),
.VAL_W (8\'hxx)
) i_m2 (
.x (x2),
.y (y2),
.z (z2),
.w (w2)
);
initial begin
`check(x1, 1\'b1)
`check(y1, 10)
`check(z1, -1)
`check(w1, 20)
`check(x2, 1\'bx)
`check(y2, 8\'hxx)
`check(z2, 8\'hxx)
`check(w2, 8\'hxx)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
//
// Copyright (c) 2002 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Synth of basic expression assign with add
//
//
module mul (q,a,b );
input a,b;
output [1:0] q;
assign q = {1\'b0,a} * {1\'b0,b};
endmodule
module test ;
reg d;
wire [1:0] q;
mul u_mul (.q(q),.a(d),.b(d));
(* ivl_synthesis_off *)
initial
begin
// $dumpfile("test.vcd");
// $dumpvars(0,test);
d = 0;
# 1;
if (q !== 2\'b0)
begin
$display("FAILED - Q isn\'t 0 ");
\t $finish;
end
#1 ;
d = 1;
# 1;
if (q !== 2\'b01)
begin
$display("FAILED - Q isn\'t 2 ");
\t $finish;
end
$display("PASSED");
end
endmodule
|
/*
* This is a post-synthesis test for the blif_shift.v test. Run this
* simulation in these steps:
*
* $ iverilog -tblif -o foo.blif blif_shift.v
* $ abc
* abc 01> read_blif foo.blif
* abc 02> write_verilog foo.v
* abc 03> quit
* $ iverilog -g2009 -o foo.vvp blif_shift_tb.v foo.v
* $ vvp foo.vvp
*/
module main;
parameter W=3;
reg [W:0] D;
reg [W:0] S;
parameter WO=5;
wire [WO:0] SHL;
wire [WO:0] SHR;
wire [WO:0] ASHL;
wire [WO:0] ASHR;
reg [WO:0] shl;
reg [WO:0] shr;
reg [WO:0] ashl;
reg [WO:0] ashr;
`ifdef DUMMY
shift ss(.D (D), .S (S), .SHL (SHL), .SHR (SHR), .ASHL (ASHL), .ASHR (ASHR));
`else
shift ss(.\\D[3] (D[3]), .\\D[2] (D[2]), .\\D[1] (D[1]), .\\D[0] (D[0]),
.\\S[3] (S[3]), .\\S[2] (S[2]), .\\S[1] (S[1]), .\\S[0] (S[0]),
.\\SHL[5] (SHL[5]), .\\SHL[4] (SHL[4]), .\\SHL[3] (SHL[3]), .\\SHL[2] (SHL[2]), .\\SHL[1] (SHL[1]), .\\SHL[0] (SHL[0]),
.\\SHR[5] (SHR[5]), .\\SHR[4] (SHR[4]), .\\SHR[3] (SHR[3]), .\\SHR[2] (SHR[2]), .\\SHR[1] (SHR[1]), .\\SHR[0] (SHR[0]),
.\\ASHL[5] (ASHL[5]), .\\ASHL[4] (ASHL[4]), .\\ASHL[3] (ASHL[3]), .\\ASHL[2] (ASHL[2]), .\\ASHL[1] (ASHL[1]), .\\ASHL[0] (ASHL[0]),
.\\ASHR[5] (ASHR[5]), .\\ASHR[4] (ASHR[4]), .\\ASHR[3] (ASHR[3]), .\\ASHR[2] (ASHR[2]), .\\ASHR[1] (ASHR[1]), .\\ASHR[0] (ASHR[0]));
`endif
int\t\t ddx;
int\t\t sdx;
initial begin
for (ddx = 0 ; ddx < 1 << (W+1) ; ddx = ddx+1)
for (sdx = 0 ; sdx < WO + 2 ; sdx = sdx+1) begin
\t D = ddx[W:0];
\t S = sdx[W:0];
shl = D << S;
shr = D >> S;
ashl = $signed(D) <<< S;
ashr = $signed(D) >>> S;
// $display("D = %b, S = %b", D, S);
// $display("shl = %b, shr = %b", shl, shr);
// $display("ashl = %b, ashr = %b", ashl, ashr);
#1;
\t if (SHL !== shl) begin
\t $display("FAILED -- D=%b, S=%b, SHL=%b (should be %b)", D, S, SHL, shl);
\t $finish;
end
\t if (SHR !== shr) begin
\t $display("FAILED -- D=%b, S=%b, SHR=%b (should be %b)", D, S, SHR, shr);
\t $finish;
end
\t if (ASHL !== ashl) begin
\t $display("FAILED -- D=%b, S=%b, ASHL=%b (should be %b)", D, S, ASHL, ashl);
\t $finish;
end
\t if (ASHR !== ashr) begin
\t $display("FAILED -- D=%b, S=%b, SHL=%b (should be %b)", D, S, ASHR, ashr);
\t $finish;
end
end
$display("PASSED");
end
endmodule // main
|
module top;
wire out;
// wire in; // Adding this makes it compile.
assign out = ~in;
zero zzz(in);
initial #1 if (out == 1\'b1) $display("PASSED"); else $display("FAILED");
endmodule
module zero(output wire foo);
assign foo = 1\'b0;
endmodule
|
/*
* Based on PR#941.
* This tests that trivial contant expressions passed as input to
* user defined tasks will work. A possible bug would be that the
* addition expression gets useless code generated.
*/
module test;
task foo;
input [16:0] in1;
begin
$display("%d", in1);
$display("PASSED");
end
endtask
initial begin
foo(16\'h00 + \'h00);
end
endmodule
|
module test ();
reg [30:0] a, b;
initial begin
b = 1;
a = (0 << b);
// $display ("a: %d", a);
if (a !== 31\'b0) $display("FAILED");
else $display("PASSED");
end
endmodule
|
(* this_is_module_bar *)
module bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1\'d0;
else out <= ~inp;
endmodule
(* this_is_module_foo *)
module foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance (clk, rst, inp, out);
initial begin
$display("PASSED");
end
endmodule
|
// Check that bounded queues are supported as function return types.
module test;
typedef int Q[$:1];
function automatic Q f();
// The last element should be discarded
return \'{1, 2, 3};
endfunction
initial begin
int q[$];
q = f();
if (q.size() == 2 && q[0] == 1 && q[1] == 2) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
// Test array variables inside a constant function
module constfunc14();
function [7:0] concat1(input [7:0] value);
reg [3:0] tmp[1:2];
begin
{tmp[1], tmp[2]} = {value[3:0], value[7:4]};
{concat1[3:0], concat1[7:4]} = {tmp[2], tmp[1]};
end
endfunction
function [7:0] concat2(input [7:0] value);
reg [3:0] tmp[1:2];
begin
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
{tmp[1], tmp[3]} = {value[3:0], value[7:4]};
{concat2[3:0], concat2[7:4]} = {tmp[3], tmp[1]};
`else
{tmp[1]} = {value[3:0]};
{concat2[3:0], concat2[7:4]} = {4\'bxxxx, tmp[1]};
`endif
end
endfunction
function [7:0] concat3(input [7:0] value);
reg [3:0] tmp[1:2];
begin
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
{tmp[\'bx], tmp[1]} = {value[3:0], value[7:4]};
{concat3[3:0], concat3[7:4]} = {tmp[\'bx], tmp[1]};
`else
{tmp[1]} = {value[7:4]};
{concat3[3:0], concat3[7:4]} = {4\'bxxxx, tmp[1]};
`endif
end
endfunction
localparam res1 = concat1(8\'ha5);
localparam res2 = concat2(8\'ha5);
localparam res3 = concat2(8\'ha5);
reg failed = 0;
initial begin
$display("%h", res1); if (res1 !== 8\'h5a) failed = 1;
$display("%h", res2); if (res2 !== 8\'h5x) failed = 1;
$display("%h", res3); if (res3 !== 8\'h5x) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Regression test for bug #973
module test();
typedef enum bit { A0, A1 } A;
typedef enum logic { B0, B1 } B;
typedef enum reg { C0, C1 } C;
A enum1;
B enum2;
C enum3;
initial begin
if ($bits(enum1) == 1 && $bits(enum2) == 1 && $bits(enum3) == 1)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module top;
reg result;
initial begin
result = $onehot0(top);
result = $onehot0("a string");
result = $onehot0(4\'b001, 1\'b0);
end
endmodule
|
module main;
task take_args;
input integer iarg;
input real rarg;
output integer iout;
output real rout;
begin
\t iout = iarg + 1;
\t rout = rarg + 1.0;
end
endtask // take_args
integer ii, io;
real ri, ro;
initial begin
ii = 4;
ri = 6.0;
io = 0;
ro = 0.0;
take_args(ii,ri,io,ro);
if (io !== 5) begin
\t $display("FAILED -- ii=%d, io=%d", ii, io);
\t $finish;
end
if (ro != 7.0) begin
\t $display("FAILED -- ri=%f, ro=%f", ri, ro);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module test (d, en, g, s, a);
input [31:2] d;
input en;
output g, s, a;
reg g, s, a;
reg [31:21] r14;
reg [2:0] r18;
always @(d or r18 or r14 or en) begin
casex ({d[31:12],r18[2:0],en})
{20\'b1111_1111_0011_????_????, 3\'b???, 1\'b1} : s = 1\'b1;
{20\'b1111_1111_0010_????_????, 3\'b???, 1\'b1} : g = 1\'b1;
{{r14[31:21], 9\'b0_01??_????}, 3\'b???, 1\'b?} : a = 1\'b1;
{{r14[31:21], 9\'b1_????_????}, 3\'b???, 1\'b?} : a = 1\'b1;
endcase
end
// Other tests check functionality so if this compiles it is fine.
initial $display("PASSED");
endmodule
|
module top;
string q_tst [$:2];
string q_tmp [$];
bit passed;
task automatic check_size(integer size,
string fname,
integer lineno);
if (q_tst.size() !== size) begin
$display("%s:%0d: Failed: queue initial size != %0d (%0d)",
fname, lineno, size, q_tst.size);
passed = 1\'b0;
end
endtask
task automatic check_idx_value(integer idx,
string expected,
string fname,
integer lineno);
if (q_tst[idx] != expected) begin
$display("%s:%0d: Failed: element [%0d] != \'%s\' (\'%s\')",
fname, lineno, idx, expected, q_tst[idx]);
passed = 1\'b0;
end
endtask
initial begin
passed = 1\'b1;
check_size(0, `__FILE__, `__LINE__);
q_tst.push_back("World");
q_tst.push_front("Hello");
q_tst.push_back("!");
q_tst.push_back("This will not be added"); // Warning: item not added.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, "Hello", `__FILE__, `__LINE__);
check_idx_value(1, "World", `__FILE__, `__LINE__);
check_idx_value(2, "!", `__FILE__, `__LINE__);
q_tst.push_front("I say,"); // Warning: sback item removed.
q_tst[3] = "Will not be added"; // Warning: item not added.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, "I say,", `__FILE__, `__LINE__);
check_idx_value(1, "Hello", `__FILE__, `__LINE__);
check_idx_value(2, "World", `__FILE__, `__LINE__);
q_tst.insert(3, "Will not be added"); // Warning: item not added.
q_tst.insert(1, "to you"); // Warning: back item removed.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, "I say,", `__FILE__, `__LINE__);
check_idx_value(1, "to you", `__FILE__, `__LINE__);
check_idx_value(2, "Hello", `__FILE__, `__LINE__);
q_tst = \'{"Hello", "World", "!", "Will not be added"}; // Warning: items not added.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, "Hello", `__FILE__, `__LINE__);
check_idx_value(1, "World", `__FILE__, `__LINE__);
check_idx_value(2, "!", `__FILE__, `__LINE__);
q_tmp = \'{"Again,", "Hello", "World", "!"};
q_tst = q_tmp; // Warning not all items copied
q_tmp[0] = "Will not change anything";
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, "Again,", `__FILE__, `__LINE__);
check_idx_value(1, "Hello", `__FILE__, `__LINE__);
check_idx_value(2, "World", `__FILE__, `__LINE__);
if (passed) $display("PASSED");
end
endmodule : top
|
module et1;
reg [31:0] a;
reg [31:0] b;
wire [31:0] x;
reg [31:0] y;
event e1;
initial begin
//\t$dumpvars;
\t$monitor ("T=", $time, ", a=", a, ", b=", b, ", x=",
x, ", y=", y);
\t#200
\t$finish(0);
end
initial begin
\ta = 10;
\tb = 20;
\t#10
\ta = 30;
\t#10
\tb = 40;
\t#10
\ta = 50;
\t-> et1.m1.e2;
\t#10
\tb = 60;
\t-> et1.m1.e2;
\t#10
\ta = 70;
\t-> et1.m1.e2;
\tb = 80;
\t#10
\ta = 90;
end
always @e1 begin
\ty <= b;
end
m m1 (a,x);
endmodule
module m (a,x);
input [31:0] a;
output [31:0] x;
reg [31:0] x;
event e2;
always @e2 begin
\t#1
\tx <= a;
\t#2
\t-> et1.e1;
end
endmodule
|
// Check that part selects are evaluated correctly within assignment patterns.
// The result should be the same as assigning the expression to a variable with
// the same type as the base type of the assignment pattern target.
module test;
int d[];
int tmp;
bit failed = 1\'b0;
`define check(expr) \\
d = \'{expr}; \\
tmp = expr; \\
if (d[0] !== tmp) begin \\
$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", d[0], tmp); \\
failed = 1\'b1; \\
end
logic [23:0] x;
int i = 13;
initial begin
x = 24\'ha5a5a5;
`check(x[0])
`check(x[7:0])
`check(x[3+:8])
`check(x[23-:5])
`check(x[i+:8])
`check(x[i-:5])
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
// A global timeunit and local time precision.
timeunit 10s;
module gtu_ltp1;
timeprecision 10ps;
endmodule
module gtu_ltp2;
timeprecision 1ns;
endmodule
`timescale 1s/1s
module check4;
initial begin
$printtimescale(gtu_ltp1);
$printtimescale(gtu_ltp2);
end
endmodule
|
/*
* Derived from PR#513
*/
`timescale 1 ps / 1 ps
module example;
integer fd;
initial begin
#100
fd = $fopen( "work/example.dump" );
$fdisplay( fd );
#1000
$display( "PASSED" );
end
endmodule
|
//
// Author: Pawel Szostek ([email protected])
// Date: 01.08.2011
`timescale 1ns/1ps
module stimulus (output reg [7:0] a);
parameter S = 20000;
int unsigned j,i;
initial begin
for(i=0; i<S; i=i+1) begin
#10;
a[7] <= inject();
a[6] <= inject();
a[5] <= inject();
a[4] <= inject();
a[3] <= inject();
a[2] <= inject();
a[1] <= inject();
a[0] <= inject();
end
end
function inject();
reg ret;
reg unsigned [3:0] temp;
temp[3:0] = $random % 16;
begin
if(temp >= 10)
ret = 1\'b1;
else if(temp >= 4)
ret = 1\'b0;
else if(temp >= 2)
ret = 1\'bx;
else
ret = 1\'b0;
inject = ret;
end
endfunction
endmodule
module main;
wire [7:0] i, o;
wire [0:7] o_vl;
dummy dummy_vhdl(o, i);
stimulus stim(i);
assign o_vl = i;
always @(i) begin
#1;
if(o !== o_vl) begin
$display("OUTPUT: ", o);
$display("INPUT: ", i);
$display("CORRECT: ", o_vl);
end
end
initial begin
#120000;
$display("PASSED");
$finish;
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test case for handling an array of arrays
module vhdl_array_of_array_test;
vhdl_array_of_array dut();
initial begin
if(dut.sig[0] !== 8\'haa)
begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
module main;
wire dst;
reg\tsrc;
spec_buf dut(dst, src);
initial begin
src = 0;
#10 if (dst !== 0) begin
\t $display("FAILED -- setup failed: src=%b, dst=%b", src, dst);
\t $finish;
end
src = 1;
#5 if (dst !== 0) begin
\t $display("FAILED -- dst changed too fast. src=%b, dst=%b", src, dst);
\t $finish;
end
#5 if (dst !== 1) begin
\t $display("FAILED -- dst failed to change. src=%b, dst=%b", src, dst);
\t $finish;
end
src = 0;
#5 if (dst !== 1) begin
\t $display("FAILED -- dst changed too fast. src=%b, dst=%b", src, dst);
\t $finish;
end
#5 if (dst !== 0) begin
\t $display("FAILED -- dst failed to change. src=%b, dst=%b", src, dst);
\t $finish;
end
$display("PASSED");
end
endmodule // main
module spec_buf(output wire O, input wire I);
buf (O, I);
specify
(I => O) = (7);
endspecify
endmodule // sec_buf
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test the ability to resolve resolve tri-state drivers onto a single
* signal. Use multiple continuous assignments to a wire to create
* multiple drivers, and use the ?: operator to tri-state the driven
* value based on the sel value.
*/
module main;
wire [1:0] out;
reg [1:0] sel = 2\'bzz;
reg [1:0] v0 = 0;
reg [1:0] v1 = 1;
reg [1:0] v2 = 2;
reg [1:0] v3 = 3;
assign out = (sel == 2\'b00)? v0 : 2\'bz;
assign out = (sel == 2\'b01)? v1 : 2\'bz;
assign out = (sel == 2\'b10)? v2 : 2\'bz;
assign out = (sel == 2\'b11)? v3 : 2\'bz;
initial begin
#1 if (out !== 2\'bxx) begin
\t $display("FAILED -- sel==%b, out==%b", sel, out);
\t $finish;
end
sel = 0;
#1 if (out !== 2\'b00) begin
\t $display("FAILED -- sel==%b, out==%b, v0==%b", sel, out, v0);
\t $finish;
end
sel = 1;
#1 if (out !== 2\'b01) begin
\t $display("FAILED -- sel==%b, out==%b", sel, out);
\t $finish;
end
sel = 2;
#1 if (out !== 2\'b10) begin
\t $display("FAILED -- sel==%b, out==%b", sel, out);
\t $finish;
end
sel = 3;
#1 if (out !== 2\'b11) begin
\t $display("FAILED -- sel==%b, out==%b", sel, out);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// Check that it is an error to not declare the data type in for loops, even
// when using var
module test;
initial begin
// The data type is not optional in a for loop, even when using var
for (var [7:0] i = 0; i < 10; i++) begin
end
$display("FAILED");
end
endmodule
|
// Check that all types of constant expression are supported for attributes
module test;
localparam [7:0] x = 1;
// Binary operators
(* attr = x + x *) reg attr0;
(* attr = x - x *) reg attr1;
(* attr = x * x *) reg attr2;
(* attr = x / x *) reg attr3;
(* attr = x % x *) reg attr4;
(* attr = x == x *) reg attr5;
(* attr = x != x *) reg attr6;
(* attr = x === x *) reg attr7;
(* attr = x !== x *) reg attr8;
(* attr = x && x *) reg attr9;
(* attr = x || x *) reg attr10;
(* attr = x ** x *) reg attr11;
(* attr = x < x *) reg attr12;
(* attr = x <= x *) reg attr13;
(* attr = x > x *) reg attr14;
(* attr = x >= x *) reg attr15;
(* attr = x & x *) reg attr16;
(* attr = x | x *) reg attr17;
(* attr = x ^ x *) reg attr18;
(* attr = x ^~ x *) reg attr19;
(* attr = x >> x *) reg attr20;
(* attr = x << x *) reg attr21;
(* attr = x >>> x *) reg attr22;
(* attr = x <<< x *) reg attr23;
// Unary operators
(* attr = +x *) reg attr24;
(* attr = -x *) reg attr25;
(* attr = !x *) reg attr26;
(* attr = ~x *) reg attr27;
(* attr = &x *) reg attr28;
(* attr = ~&x *) reg attr29;
(* attr = |x *) reg attr30;
(* attr = ~|x *) reg attr31;
(* attr = ^x *) reg attr32;
(* attr = ~^x *) reg attr33;
// Ternary operator
(* attr = x ? x : x *) reg attr34;
// Concat
(* attr = {x,x} *) reg attr35;
(* attr = {3{x}} *) reg attr36;
// Part select
(* attr = x[0] *) reg attr37;
(* attr = x[1:0] *) reg attr38;
(* attr = x[0+:1] *) reg attr39;
(* attr = x[1-:1] *) reg attr40;
// Parenthesis
(* attr = (x) *) reg attr41;
// Literals
(* attr = 10 *) reg attr42;
(* attr = 32\'h20 *) reg attr43;
(* attr = "test" *) reg attr44;
// System function
(* attr = $clog2(10) *) reg attr45;
// Function
function fn;
input x;
fn = x*2;
endfunction
(* attr = fn(10) *) reg attr46;
initial begin
$display("PASSED");
end
endmodule
|
module constfunc2();
function integer factorial;
input integer n;
begin
if (n > 1)
factorial = n * factorial(n - 1);
else
factorial = n;
end
endfunction
localparam value1 = factorial(1);
localparam value2 = factorial(2);
localparam value3 = factorial(3);
localparam value4 = factorial(4);
localparam value5 = factorial(5);
localparam value6 = factorial(6);
initial begin
$display("value 1 = %0d", value1);
$display("value 2 = %0d", value2);
$display("value 3 = %0d", value3);
$display("value 4 = %0d", value4);
$display("value 5 = %0d", value5);
$display("value 6 = %0d", value6);
if ((value1 === 1)
&& (value2 === 2)
&& (value3 === 6)
&& (value4 === 24)
&& (value5 === 120)
&& (value6 === 720))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* I expect the following statistics results:
* 0 x 0 x x x
* 1 x 1 x 0 0
* 2 1 2 x 1 0
* 3 1 3 x 2 1
* 2 1 3 3 2 2
* 2 1 3 3 3 2
* 3 1 3 3 4 2
* 1 1 3 3 1 3
* 0 1 3 2 x 3
* 1 2 3 2 0 2
* 0 2 3 1 x 3
* 1 3 3 1 0 2
* 2 2 3 1 1 2
* 3 2 3 1 2 2
*
* x implies there is no defined value for that statistic.
*/
module top;
reg pass;
integer res, status, value, value2;
integer id, job, item;
initial begin
pass = 1\'b1;
id = 1;
// Use id = 1, type = 1 (FIFO) and a size of 5.
$display("----- INIT -----");
$q_initialize(id, 1, 5, status);
if (status !== 0) begin
$display("Failed to initialize queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
// Add an element to the queue.
job = 1;
item = 10;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#1;
// Add a second element to the queue.
job = 1;
item = 20;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#1;
// Add a third element to the queue.
job = 1;
item = 30;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#1;
// Remove an element from the queue.
$display("----- REMOVE -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element from the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#1
print_stats(id);
#1;
// Add a fourth element to the queue.
job = 1;
item = 30;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#1;
// Remove two elements from the queue.
$display("----- REMOVE TWO -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element (1) from the queue, got %d", status);
pass = 1\'b0;
end
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element (2) from the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#1;
// Remove an element from the queue.
$display("----- REMOVE -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element from the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#1;
// Add a fifth element to the queue.
job = 1;
item = 50;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#1;
// Remove an element from the queue.
$display("----- REMOVE -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element from the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#7;
// Add a sixth element to the queue.
job = 1;
item = 60;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#1;
// Add a seventh element to the queue.
job = 1;
item = 70;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
#1;
// Add a eight element to the queue.
job = 1;
item = 80;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1\'b0;
end
print_stats(id);
if (pass) $display("PASSED");
end
task print_stats;
input id;
integer id;
integer len, inter, max, short, long, avg, status;
// Icarus uses a status code of 10 to indicate no statistics available.
begin
len = 32\'bx;
inter = 32\'bx;
max = 32\'bx;
short = 32\'bx;
long = 32\'bx;
avg = 32\'bx;
$display("Queue statistics at time %0d", $time);
// Get the queue length.
$q_exam(id, 1, len, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the length, status %0d", status);
pass = 1\'b0;
end
// Get the mean inter-arrival time.
$q_exam(id, 2, inter, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the inter-arrival, status %0d", status);
pass = 1\'b0;
end
// Get the maximum length.
$q_exam(id, 3, max, status);
if ((status !== 0) && (status !== 10)) begin
\t$display(" Failed to get the maximum length, status %0d", status);
\tpass = 1\'b0;
end
// Get the shortest wait time.
$q_exam(id, 4, short, status);
if ((status !== 0) && (status !== 10)) begin
\t$display(" Failed to get the shortest wait time, status %0d", status);
\tpass = 1\'b0;
end
// Get the longest wait time.
$q_exam(id, 5, long, status);
if ((status !== 0) && (status !== 10)) begin
\t$display(" Failed to get the longest wait time, status %0d", status);
\tpass = 1\'b0;
end
// Get the average wait time.
$q_exam(id, 6, avg, status);
if ((status !== 0) && (status !== 10)) begin
\t$display(" Failed to get the average wait time, status %0d", status);
\tpass = 1\'b0;
end
$display(" %0d, %0d, %0d, %0d, %0d, %0d",
len, inter, max, short, long, avg);
end
endtask
endmodule
|
module top_module(
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[N][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
|
/*
* This tests a trivial class. This tests that simple property
* initializers work.
*/
program main;
// Trivial examples of classes.
class foo_t ;
int int_value = 42;
bit [3:0] bit_value = 5;
string\ttxt_value = "text";
endclass : foo_t // foo_t
foo_t obj1;
foo_t obj2;
initial begin
obj1 = new;
// The shallow copy constructor bypasses (or at least overrides)
// property declaration assignments, so obj2 should hold the
// updated values and not the constructed values.
obj1.int_value = 43;
obj1.bit_value = 10;
obj1.txt_value = "fluf";
obj2 = new obj1;
if (obj2.int_value !== 43) begin
\t $display("FAILED -- obj2.int_value=%0d.", obj2.int_value);
\t $finish;
end
if (obj2.bit_value !== 4\'d10) begin
\t $display("FAILED -- obj2.bit_value=%0b.", obj2.bit_value);
\t $finish;
end
if (obj2.txt_value != "fluf") begin
\t $display("FAILED -- obj2.txt_value=%s", obj2.txt_value);
\t $finish;
end
$display("PASSED");
$finish;
end
endprogram // main
|
module top;
reg pass;
reg [7:0] a, b;
wire [15:0] ruu, rsu, rus, rss;
reg signed [15:0] res;
integer i;
assign ruu = a / b;
assign rsu = $signed(a) / b;
assign rus = a / $signed(b);
assign rss = $signed(a) / $signed(b);
initial begin
pass = 1\'b1;
// Run 1000 random vectors
for (i = 0; i < 1000; i = i + 1) begin
// Random vectors
a = $random;
b = $random;
#1;
// Check unsigned / unsigned.
if (ruu !== a/b) begin
$display("FAILED: u/u (%b/%b) gave %b, expected %b", a, b, ruu, a/b);
pass = 1\'b0;
end
// Check signed / unsigned.
if (rsu !== a/b) begin
$display("FAILED: s/u (%b/%b) gave %b, expected %b", a, b, rsu, a/b);
pass = 1\'b0;
end
// Check unsigned / signed.
if (rus !== a/b) begin
$display("FAILED: u/s (%b/%b) gave %b, expected %b", a, b, rus, a/b);
pass = 1\'b0;
end
// Check signed / signed.
res = $signed(a)/$signed(b);
if (rss !== res) begin
$display("FAILED: s/s (%b/%b) gave %b, expected %b", a, b, rss, res);
pass = 1\'b0;
end
end
if (pass) $display("PASSED");
end
endmodule
|
// The IEEE standard allows the out-of-bounds part-selects to be flagged as
// compile-time errors. If they are not, this test should pass.
module top;
reg [3:0][3:0] array1;
reg [3:0][3:0] array2;
reg [3:0][3:0] array3;
reg [3:0][3:0] array4;
reg [3:0][3:0] array5;
reg [3:0][3:0] array6;
reg failed = 0;
initial begin
array1[-2+:2] = 8\'h00;
array1[ 0+:2] = 8\'h21;
array1[ 2+:2] = 8\'h43;
array1[ 4+:2] = 8\'h55;
array1[-1+:2] = 8\'h10;
array2[ 1+:2] = 8\'h32;
array2[ 3+:2] = 8\'h54;
array3[-1-:2] = 8\'h00;
array3[ 1-:2] = 8\'h21;
array3[ 3-:2] = 8\'h43;
array3[ 5-:2] = 8\'h55;
array4[ 0-:2] = 8\'h10;
array4[ 2-:2] = 8\'h32;
array4[ 4-:2] = 8\'h54;
array5[-1:-2] = 8\'h00;
array5[ 1:0 ] = 8\'h21;
array5[ 3:2 ] = 8\'h43;
array5[ 5:4 ] = 8\'h55;
array6[ 0:-1] = 8\'h10;
array6[ 2:1 ] = 8\'h32;
array6[ 4:3 ] = 8\'h54;
$display("%h", array1);
if (array1 !== 16\'h4321) failed = 1;
$display("%h", array2);
if (array2 !== 16\'h4321) failed = 1;
$display("%h", array3);
if (array3 !== 16\'h4321) failed = 1;
$display("%h", array4);
if (array4 !== 16\'h4321) failed = 1;
$display("%h", array5);
if (array5 !== 16\'h4321) failed = 1;
$display("%h", array6);
if (array6 !== 16\'h4321) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2002 Jane Skinner
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// Icarus 0.6, snapshot 20020728 or snapshot 20010806
// ==================================================
// -- confused by complex disables
//
// -- to run, incant
// iverilog tt.v
// vvp a.out
//
// Veriwell
// ========
// -- OK
//
module top;
integer loop_cntr, simple_fail, loop_fail;
reg fred, abort;
initial begin
#1;
simple_fail = 0;
loop_fail = 0;
fred = 0;
abort = 1;
#4;
fred = 1;
#4
if(simple_fail) $display("\
***** simple block disable FAILED *****");
else $display("\
***** simple block disable PASSED *****");
if(loop_fail) $display("***** complex block & loop disable FAILED *****\
");
else $display("***** complex block & loop disable PASSED *****\
");
$finish(0);
end
// simple block disable
initial begin: block_name
#2;
disable block_name;
simple_fail = 1;
end
// more complex: block disable inside for-loop
initial begin
#2;
begin: configloop
for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin
\twait (fred);
\tif (abort) begin
\t disable configloop;
\tend
\tloop_fail = 1;
end
end // configloop block
if (loop_fail) $display("\
\\ttime: %0t, loop_cntr: %0d",$time,loop_cntr);
end
endmodule
|
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