text
stringlengths 1
2.1M
|
|---|
//
// Copyright (c) 1999 Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// 9/7/99 - SDW - Modified by instantiating Peter\'s module into a
// self-checking structure. Moved bar=result inside
// begin clause in function.
//
// SDW - Validate function contains a register
module main ();
reg [1:0] val1;
reg\t val2;
reg\t error;
function bar;
input [1:0] arg;
reg result;
begin
result = |arg;
bar = result;
end
endfunction
initial
begin
error = 0;
val2 = bar(2\'b01);
if(val2 != 1)
begin
$display("FAILED function 3.11F - register within a function(1)");
error = 1;
end
val1 = 2\'b11 ;
val2 = bar(val1) ;
if(val2 != 1)
begin
$display("FAILED function 3.11F - register within a function(2)");
error = 1;
end
val2 = bar(2\'b00);
if(val2 != 0)
begin
$display("FAILED function 3.11F - register within a function(2)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
/*
* Copyright (c) 2000 Chris Lattner <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test;
reg [31:0] buff[256*2*2-1:0];
reg [31:0] x;
initial
begin
buff[0] = 0;
x = 256;
buff[x+0] = 1234;
if (buff[0] != 0) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
module top;
initial begin
if ("this matches" == "this\\
matches") $display("PASSED");
else $display("FAILED");
end
endmodule
|
// pr1703959
module test();
ma ia (.IO(b), .ZI(c));
mb ib( .b({b}), .c({c}));
// mb ib( .b(b), .c(c));
initial #10 $display("PASSED");
endmodule
module ma(ZI,IO);
inout ZI;
inout IO;
pmos (ZI, IO, 1\'b0);
// pmos (IO, ZI, 1\'b0);
endmodule
module mb ( b, c);
// input b;
output b;
input c;
// inout b;
// inout c;
endmodule // mb
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test tests simple zero-extend of small r-values into large
* l-values.
*
* Correction and extensions by EML; 2007-11-15
*/
module main;
reg [3:0] y;
reg signed xs;
reg\t x;
reg\t fail;
initial begin
fail = 0;
x = 1\'b0;
y = x;
if (y !== 4\'b0000) begin
\t $display("FAILED 1 -- x=%b, y=%b", x, y);
\t fail = 1;
end
x = 1\'b1;
y = x;
if (y !== 4\'b0001) begin
\t $display("FAILED 2 -- x=%b, y=%b", x, y);
\t fail = 1;
end
// x is a 1-bit unsigned reg; it zero-extends when assigned to y
x = 1\'bx;
y = x;
if (y !== 4\'b000x) begin
\t $display("FAILED 3 -- x=%b, y=%b", x, y);
\t fail = 1;
end
// x is a 1-bit unsigned reg; it zero-extends when assigned to y
x = 1\'bz;
y = x;
if (y !== 4\'b000z) begin
\t $display("FAILED 4 -- x=%b, y=%b", x, y);
\t fail = 1;
end
// xs is a 1-bit signed reg; it top-bit-extends when assigned to y
xs = 1\'bx;
y = xs;
if (y !== 4\'bxxxx) begin
\t $display("FAILED 5 -- xs=%b, y=%b", xs, y);
\t fail = 1;
end
// xs is a 1-bit signed reg; it top-bit-extends when assigned to y
xs = 1\'bz;
y = xs;
if (y !== 4\'bzzzz) begin
\t $display("FAILED 6 -- xs=%b, y=%b", xs, y);
\t fail = 1;
end
// \'bx is an unsized unsigned constant; it X-extends to the size of
// the expression it is in
y = \'bx;
if (y !== 4\'bxxxx) begin
\t $display("FAILED 7 -- y=%b", y);
\t fail = 1;
end
// \'bz is an unsized unsigned constant; it Z-extends to the size of
// the expression it is in
y = \'bz;
if (y !== 4\'bzzzz) begin
\t $display("FAILED 8 -- y=%b", y);
\t fail = 1;
end
// this is the only case in which a constant pads to the left with
// X\'s. 4\'bx is 4-bit unsigned, but it is specified with fewer than 4
// bits
y = 4\'bx;
if (y !== 4\'bxxxx) begin
\t $display("FAILED 9 -- y=%b", y);
\t fail = 1;
end
// this is the only case in which a constant pads to the left with
// Z\'s. 4\'bz is 4-bit unsigned, but it is specified with fewer than 4
// bits
y = 4\'bz;
if (y !== 4\'bzzzz) begin
\t $display("FAILED 10 -- y=%b", y);
\t fail = 1;
end
if (!fail) $display("PASSED");
end // initial begin
endmodule // main
|
module sub(input [3:0] value);
wire [3:0] array[1:0];
reg [3:0] monitor;
assign array[0] = $unsigned(value);
always @(array[0]) begin
monitor = array[0];
end
endmodule
module top;
wire [3:0] value;
sub sub1(value);
sub sub2(value);
initial begin
force value = 5;
#0;
if ((sub1.monitor === 5) && (sub2.monitor === 5))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module main;
real x;
real y;
real bar;
initial begin
x = 5.0;
y = 10.0;
bar = x % y;
$display("bar=%f", bar);
if (bar != 5.0) begin
\t $display("FAILED -- x %% y --> %f (s.b. 5.0)", bar);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This sample tests that the supply0 and supply1 nets take on
* the proper initial value. This adds to the supply1 test some
* constant drivers that could tickle constant propagation bugs.
*/
module test;
supply0 gnd;
supply1 vdd;
// These should drop away as meaningless.
assign gnd = 1;
assign vdd = 0;
initial begin #1
if (gnd !== 0) begin
\t $display("FAILED -- gnd == %b", gnd);
\t $finish;
end
if (vdd !== 1) begin
\t $display("FAILED -- vdd == %b", vdd);
\t $finish;
end
$display("PASSED");
end
endmodule
|
// Verify that a zero width constant replication is handled correctly.
module top;
reg pass;
reg [31:0] in_full;
wire [31:0] pa_out_full, ca_out_full;
reg [29:0] in_part;
wire [31:0] pa_out_part, ca_out_part;
initial begin
pass = 1\'b1;
in_full = {16{2\'b10}};
in_part = {15{2\'b01}};
#1;
if (pa_out_full !== 32\'b10101010101010101010101010101010) begin
$display("Failed: pa_out_full, got %b", pa_out_full);
pass = 1\'b1;
end
if (ca_out_full !== 32\'b10101010101010101010101010101010) begin
$display("Failed: ca_out_full, got %b", ca_out_full);
pass = 1\'b1;
end
if (pa_out_part !== 32\'bxx010101010101010101010101010101) begin
$display("Failed: pa_out_part, got %b", pa_out_part);
pass = 1\'b1;
end
if (ca_out_part !== 32\'bzz010101010101010101010101010101) begin
$display("Failed: ca_out_part, got %b", ca_out_part);
pass = 1\'b1;
end
if (pass) $display("PASSED");
end
param #(32) full(pa_out_full, ca_out_full, in_full);
param #(30) part(pa_out_part, ca_out_part, in_part);
endmodule
module param #(parameter width = 32) (
output reg [31:0] pa_out,
output wire [31:0] ca_out,
input [width-1:0] in);
assign ca_out = {{32-width{1\'bz}}, in};
always @* pa_out = {{32-width{1\'bx}}, in};
endmodule
|
module main;
reg signed [5:0] GAIN = 2;
reg signed [23:0] iir = -8;
wire signed [23:0] iir_s1 = iir >>> 2;
wire signed [23:0] iir_s2 = iir >>> GAIN;
initial begin
#1 /* Wait for inputs values to settle. */ ;
if (iir_s1 !== -24\'sd2) begin
\t $display("FAILED -- s1 = %d (%h)", iir_s1, iir_s1);
\t $finish;
end
if (iir_s2 !== -24\'sd2) begin
\t $display("FAILED -- s2 = %d (%h)", iir_s2, iir_s2);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* Copyright (c) 2000 Guy Hutchison ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module xnor_test;
reg onebit1, onebit2;
reg [3:0] small1, small2;
reg [15:0] large1, large2, large3, large4;
reg\t fail;
initial
begin
fail = 0;
// single bit xnor testing
if ((1\'b0 ~^ 1\'b1) === 1\'b1) fail = 1;
if ((1\'b1 ^~ 1\'b0) === 1\'b1) fail = 1;
if ((1\'b0 ^~ 1\'b0) === 1\'b0) fail = 1;
if ((1\'b1 ~^ 1\'b1) === 1\'b0) fail = 1;
// different sized operands (equality)
for (small1=0; small1 < 15; small1=small1+1)
\tbegin
\t large1 = { 12\'b0, small1 };
\t large2 = small1 ~^ large1;
\t if (large2 !== {16{1\'b1}}) fail = 1;
\t large2 = large1 ^~ small1;
\t if (large2 !== {16{1\'b1}}) fail = 1;
\tend
// random test
// assumes +, &, |, and ~ work correctly
for (large1 = 0; large1 < 1000; large1=large1+1)
\tbegin
\t large2 = large1 + 1511; // prime number
\t large3 = large1 ^~ large2;
\t large4 = (large1 & large2) | (~large1 & ~large2);
\t if (large3 !== large4)
\t begin
\t fail = 1;
\t $display ("Pattern failed: %h != %h", large3, large4);
\t end
\tend // for (large1 = 0; large1 < 1000; large1=large1+1)
if (fail)
\t$display ("FAILED");
else $display ("PASSED");
$finish;
end // initial begin
endmodule // xnor_test
|
// Check that non-blocking event control assignments with multiple events in the
// event control expression are supported.
module test;
reg failed = 1\'b0;
`define check(val, exp) \\
if (val !== exp) begin \\
$display("FAILED. Expected %d, got %d.", exp, val); \\
failed = 1\'b1; \\
end
integer x = 0;
event e1, e2, e3;
initial begin
// Any of them should trigger the event
x <= @(e1 or e2 or e3) x + 1;
#1
`check(x, 0);
->e1;
`check(x, 1);
x <= @(e1 or e2 or e3) x + 1;
#1
`check(x, 1);
->e2;
`check(x, 2);
// Alternative syntax, but still the same behavior
x <= @(e1, e2, e3) x + 1;
#1
`check(x, 2);
->e3;
`check(x, 3);
// In combination with repeat
x <= repeat(3) @(e1, e2, e3) x + 1;
#1
`check(x, 3);
->e1;
`check(x, 3);
->e2;
`check(x, 3);
->e3;
`check(x, 4);
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
// Check that it is possible to declare the data type for a vector type task
// port before the direction for non-ANSI style port declarations.
module test;
task t;
reg [7:0] x;
input [7:0] x;
if (x == 10 && $bits(x) == 8) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t(10);
endmodule
|
/*
* This demonstrates a basic dynamic array
*/
module main;
int foo[];
int idx;
initial begin
if (foo.size() != 0) begin
\t $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
\t $finish;
end
foo = new[10];
if (foo.size() != 10) begin
\t $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
\t $finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
\t foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
\t $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
\t $finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
\t $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
\t $finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
\t if (foo[idx%10] != (idx%10)) begin
\t $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]);
\t $finish;
\t end
end
foo.delete();
if (foo.size() != 0) begin
\t $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* This tests a trivial class. This tests that simple user defined
* constructors work, and also tests shallow copoy "new".
*/
program main;
// Trivial examples of classes.
class foo_t ;
int value;
function new();
\t value = 42;
endfunction // new
endclass : foo_t // foo_t
class bar_t ;
int value;
function new (int init);
\tvalue = init;
endfunction // new
endclass : bar_t // foo_t
foo_t obj1;
bar_t obj2;
foo_t obj1b;
initial begin
obj1 = new;
if (obj1.value !== 42) begin
\t $display("FAILED -- Default constructor left value=%0d.", obj1.value);
\t $finish;
end
obj2 = new(53);
if (obj2.value !== 53) begin
\t $display("FAILED -- new(53) constructure left value=%0d.", obj2.value);
\t $finish;
end
// Shallow object copy
obj1b = new obj1;
if (obj1b.value !== 42) begin
\t $display("FAILED -- Shallow copy constructor left value=%0d.", obj1b.value);
\t $finish;
end
obj1.value = 85;
if (obj1b.value !== 42) begin
\t $display("FAILED -- Shallow copied value changed to %0d.", obj1b.value);
\t $finish;
end
$display("PASSED");
$finish;
end
endprogram // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous << in assignment..dependent on always << working
//
module main;
reg globvar;
reg [3:0] var1,var2,var3;
wire [3:0] var3a;
reg error;
assign var3a = var1 << var2;
always @( var1 or var2)
var3 = var1 << var2 ;
initial
begin
error = 0;
for ( var1 = 4\'b0; var1 != 4\'hf; var1 = var1 + 1)
for ( var2 = 4\'b0; var2 != 4\'hf; var2 = var2 + 1)
begin
#1 ;
if(var3 != var3a)
begin
$display("FAILED continous << 1=%h,2=%h,3=%h,3a=%h",
var1,var2,var3,var3a);
error = 1;
end
#1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
/**********************************************************************
* $my_monitor example -- Verilog HDL test bench.
*
* Verilog test bench to test the $my_monitor PLI application.
*
* For the book, "The Verilog PLI Handbook" by Stuart Sutherland
* Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA
* Contact: www.wkap.il
* Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
* Contact: www.sutherland-hdl.com
*********************************************************************/
`timescale 1ns / 1ns
module test;
reg a, b, ci, clk;
wire sum, co;
addbit i1 (a, b, ci, sum, co);
initial
$my_monitor(i1);
initial
begin
#0 a = 0;
#0 b = 0;
#0 ci = 0;
#10 a = 1;
#10 a = 0;
#10 b = 1;
#10 a = 1;
#10 $finish(0);
end
endmodule
/*** A gate level 1 bit adder model ***/
`timescale 1ns / 1ns
module addbit (a, b, ci, sum, co);
input a, b, ci;
output sum, co;
wire a, b, ci, sum, co,
n1, n2, n3;
/*
assign n1 = a ^ b;
assign sum = n1 ^ ci;
assign n2 = a & b;
assign n3 = n1 & ci;
assign co = n2 | n3;
*/
// Gate delays are used to ensure the signal changes occur in a
// defined order.
xor #1 (n1, a, b);
and #2 (n2, a, b);
and #3 (n3, n1, ci);
xor #4 (sum, n1, ci);
or #4 (co, n2, n3);
endmodule
/*********************************************************************/
|
module top;
reg passed = 1\'b1;
reg [199:0] r, a, b;
initial begin
a = \'d5;
b = \'d2; // A simple test.
r = a ** b;
if (r != \'d25) begin
$display("Failed: 5 ** 2 gave %d, expected 25", r);
passed = 1\'b0;
end
b = \'d55; // A 128 bit value.
r = a ** b;
if (r != 200\'d277555756156289135105907917022705078125) begin
$display("Failed: 5 ** 55\
gave %0d", r);
$display(" expected 277555756156289135105907917022705078125");
passed = 1\'b0;
end
b = \'d86; // A 200 bit value.
r = a ** b;
if (r != 200\'d1292469707114105741986576081359316958696581423282623291015625) begin
$display("Failed: 5 ** 55\
gave %0d", r);
$display(" expected 1292469707114105741986576081359316958696581423282623291015625");
passed = 1\'b0;
end
if (r != \'d5**\'d86) begin
$display("Failed: compile-time/run-time value mismatch.");
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
// Check that the signedness of class properties are handled correctly when
// accessing the property in a class method.
module test;
bit failed = 1\'b0;
`define check(x) \\
if (!(x)) begin \\
$display("FAILED: ", `"x`", `__LINE__); \\
failed = 1\'b1; \\
end
int unsigned x = 10;
int y = 10;
int z;
class C;
shortint s = -1;
bit [15:0] u = -1;
task test;
// These all evaluate as signed
`check(s < 0)
`check($signed(u) < 0)
// These all evaluate as unsigned
`check(u > 0)
`check({s} > 0)
`check($unsigned(s) > 0)
`check(s > 16\'h0)
// In arithmetic expressions if one operand is unsigned all operands are
// considered unsigned
z = u + x;
`check(z === 65545)
z = u + y;
`check(z === 65545)
z = s + x;
`check(z === 65545)
z = s + y;
`check(z === 9)
// For ternary operators if one operand is unsigned the result is unsigend
z = x ? u : x;
`check(z === 65535)
z = x ? u : y;
`check(z === 65535)
z = x ? s : x;
`check(z === 65535)
z = x ? s : y;
`check(z === -1)
if (!failed) begin
$display("PASSED");
end
endtask
endclass
C c;
initial begin
c = new;
c.test();
end
endmodule
|
module bar(clk, rst, inp_a, inp_b, out);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output reg [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= inp_a + (* ripple_adder *) inp_b;
endmodule
module foo(clk, rst, inp_a, inp_b, out);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output wire [7:0] out;
bar bar_instance (clk, rst, inp_a, inp_b, out);
initial begin
$display("PASSED");
end
endmodule
|
module main;
localparam AMAX = 7;
localparam SHIFT = 4;
int foo [AMAX:0];
int unsigned foo_u [AMAX:0];
int idx;
initial begin
for (idx = 0 ; idx <= AMAX ; idx = idx+1) begin
\t foo[idx] = idx - SHIFT;
\t foo_u[idx] = idx;
end
for (idx = 0 ; idx <= AMAX ; idx = idx+1) begin
\t if (idx < SHIFT && foo[idx] > 0) begin
\t $display("FAIL -- foo[%0d] = %0d (not signed?)", idx, foo[idx]);
\t $finish;
\t end
\t if (foo[idx] != (idx-SHIFT)) begin
\t $display("FAIL -- foo[%0d] = %0d", idx, foo[idx]);
\t $finish;
\t end
\t if (foo_u[idx] != idx) begin
\t $display("FAIL -- foo_u[%0d] = %0d", idx, foo[idx]);
\t $finish;
\t end
end
$display("PASSED");
$finish;
end // initial begin
endmodule // main
|
module test ();
reg [2:0] in;
wire Oand, Oor;
dut #(.is_and(1)) dand (.O(Oand), .A(in[1]), .B(in[0]));
dut #(.is_and(0)) dor (.O(Oor ), .A(in[1]), .B(in[0]));
initial begin
for (in = 0 ; in < 4 ; in = in+1) begin
\t #1 /* settle time. */ ;
\t if (Oand !== &in[1:0]) begin
\t $display("FAILED -- in=%b, Oand=%b", in, Oand);
\t $finish;
\t end
\t if (Oor !== |in[1:0]) begin
\t $display("FAILED -- in=%b, Oor=%b", in, Oor);
\t $finish;
\t end
end // for (in = 0 ; in < 4 ; in = in+1)
$display("PASSED");
end
endmodule
module dut (output O, input A, input B);
parameter is_and = 1;
generate
if (is_and)
\tand g(O, A, B);
else
\tor g(O, A, B);
endgenerate
endmodule // dut
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test catches the case where the operands of the ?: operator
* have different sizes.
*/
module main;
reg [3:0] r;
reg [3:0] a;
reg [4:0] b;
reg\t f;
initial begin
a = 4\'b1010;
b = 5\'b10101;
f = 1;
r = f? a : b;
if (r !== 4\'b1010) begin
\t $display("FAILED: r === %b", r);
\t $finish;
end
f = 0;
r = f? a : b;
if (r !== 4\'b0101) begin
\t $display("FAILED: r === %b", r);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module tb;
parameter P = \'1;
parameter W = 82;
wire [W-1:0] one = \'1;
wire [W-1:0] zero = \'0;
wire [W-1:0] x = \'x;
wire [W-1:0] z = \'z;
wire [15:0] expr_add = 16\'h0 + \'1;
wire [15:0] expr_xor = 16\'haaaa ^ \'1;
wire [3:0] bitsel = 4\'h2;
wire [3:0] bitsel_lv;
wire [3:0] param = P;
assign bitsel_lv[\'1] = 1\'b1;
initial begin
#5;
if (4\'hf !== \'1) begin
$display("FAILED, 4\'hf !== \'1");
$finish;
end
if (one !== \'1) begin
$display("FAILED, one !== \'1");
$finish;
end
if (one !== {W{1\'b1}}) begin
$display("FAILED, one = %b", one);
$finish;
end
if (zero !== {W{1\'b0}}) begin
$display("FAILED, zero = %b", zero);
$finish;
end
if (x !== {W{1\'bx}}) begin
$display("FAILED, x = %b", x);
$finish;
end
if (z !== {W{1\'bz}}) begin
$display("FAILED, z = %b", z);
$finish;
end
if (expr_add !== 16\'hffff) begin
$display("FAILED, expr_add = %b", expr_add);
$finish;
end
if (expr_xor !== 16\'h5555) begin
$display("FAILED, expr_xor = %b", expr_xor);
$finish;
end
if (bitsel_lv[1] !== 1\'b1) begin
$display("FAILED, bitsel_lv[1] = %b", bitsel_lv[1]);
$finish;
end
if (bitsel[\'1] !== 1\'b1) begin
$display("FAILED, bitsel[\'1] = %b", bitsel[\'1]);
$finish;
end
if (bitsel[\'1:\'0] !== 2\'b10) begin
$display("FAILED, bitsel[\'1:\'0] = %b", bitsel[\'1:\'0]);
$finish;
end
if (param !== 4\'h1) begin
$display("FAILED, param = %b, %b", param, P);
$finish;
end
$display("PASSED");
end
endmodule
|
/*
*/
module main();
reg [8:0] foo;
reg [1:0] bar;
initial begin
foo = 2\'b00 ? 9\'b000111xxx : 9\'b01x01x01x;
$display("00: foo = %b", foo);
foo = 2\'b01 ? 9\'b000111xxx : 9\'b01x01x01x;
$display("01: foo = %b", foo);
foo = 2\'b0x ? 9\'b000111xxx : 9\'b01x01x01x;
$display("0x: foo = %b", foo);
foo = 2\'b11 ? 9\'b000111xxx : 9\'b01x01x01x;
$display("11: foo = %b", foo);
foo = 2\'b1x ? 9\'b000111xxx : 9\'b01x01x01x;
$display("1x: foo = %b", foo);
bar = 2\'b00;
foo = bar? 9\'b000111xxx : 9\'b01x01x01x;
$display("%b: foo = %b", bar, foo);
bar = 2\'b01;
foo = bar? 9\'b000111xxx : 9\'b01x01x01x;
$display("%b: foo = %b", bar, foo);
bar = 2\'b0x;
foo = bar? 9\'b000111xxx : 9\'b01x01x01x;
$display("%b: foo = %b", bar, foo);
bar = 2\'b11;
foo = bar? 9\'b000111xxx : 9\'b01x01x01x;
$display("%b: foo = %b", bar, foo);
bar = 2\'b1x;
foo = bar? 9\'b000111xxx : 9\'b01x01x01x;
$display("%b: foo = %b", bar, foo);
end
endmodule
|
module main;
reg [3:0] cond;
reg [2:0] t;
always @*
case (cond&4\'b1110)
\'h0: t = 7;
\'h2: t = 6;
\'h4: t = 5;
\'h6: t = 4;
\'h8: t = 3;
\'ha: t = 2;
\'hc: t = 1;
\'he: t = 0;
endcase
integer i;
initial begin
for (i = 0 ; i < 8 ; i = i + 1) begin
\t cond = i << 1;
\t #1 if (t !== (7 - i)) begin
\t $display("FAILED -- i=%d, cond=%b, t=%b", i, cond, t);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
// Check that it is an error to declare a non-ANSI module port with implicit
// packed dimensions if it is later redeclared as a packed struct typed
// variable. Even if the size of the packed dimensions matches that of the size
// of the struct.
typedef struct packed {
reg [31:0] x;
reg [7:0] y;
} T;
module test(x);
output [47:0] x;
T x;
initial begin
$display("FAILED");
end
endmodule
|
// Check that it is possible to reference a package scoped function, even if
// there is a type identifier of the same name in the current scope.
bit failed = 1\'b0;
`define check(expr, val) \\
if (expr !== val) begin \\
$display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \\
failed = 1\'b1; \\
end
package P;
function integer T(integer x);
return x + 1;
endfunction
endpackage
module test;
typedef integer T;
initial begin
integer x;
x = P::T(10);
`check(x, 11)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module top;
localparam irparam = -1.0;
localparam iiparam = -1;
localparam [7:0] uparam = -1.0;
localparam signed [7:0] sparam = -1.0;
localparam real rparam = -1;
localparam realtime rtparam = -1;
localparam integer iparam = -1.0;
localparam time tparam = -1.0;
initial begin
$display("Implicit real: ", irparam);
$display("Implicit integer: ", iiparam);
$display("Unsigned: ", uparam);
$display("Signed: ", sparam);
$display("Real: ", rparam);
$display("Real time: ", rtparam);
$display("Integer: ", iparam);
$display("Time: ", tparam);
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test was inspired by PR#539. We check that the calculated bit
* select of a net in a continuous assignment gets bits in the right
* order and position. The trick here is that the bits are numbered
* from MSB to LSB.
*/
module main;
reg [63:0] target0 = 64\'h0040_2000_0000_0000;
reg [64:1] target1 = 64\'h0040_2000_0000_0000;
reg [6:0] idx;
wire mux0 = target0[idx];
wire mux1 = target1[idx+1];
initial begin
$display( "Using constant indices:" );
$display( " %b=v[45]", target0[45] );
if (target0[45] !== 1\'b1) begin
\t $display("FAILED -- target0[45] != 1");
\t $finish;
end
$display( " %b=v[54]", target0[54] );
if (target0[54] !== 1\'b1) begin
\t $display("FAILED -- target0[54] != 1");
\t $finish;
end
$display( " %b=v[18]", target0[18] );
if (target0[18] !== 1\'b0) begin
\t $display("FAILED -- target0[18] != 0");
\t $finish;
end
$display( " %b=v[ 9]", target0[9] );
if (target0[9] !== 1\'b0) begin
\t $display("FAILED -- target0[ 9] != 0");
\t $finish;
end
$display( "Using calcuated indices:" );
for (idx = 0 ; idx < 64 ; idx = idx + 1) begin
\t #1 $display("target0[%2d]=%b, mux0=%b", idx, target0[idx], mux0);
\t $display("target1[%2d]=%b, mux1=%b", idx+1, target1[idx+1], mux1);
\t if (target0[idx] !== mux0) begin
\t $display("FAILED -- target0[idx] != mux0");
\t $finish;
\t end
\t if (target1[idx+1] !== mux1) begin
\t $display("FAILED -- target1[idx+1] != mux1");
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
module test3;
initial #1 $mytest;
endmodule
module test2;
initial #2 $mytest;
test3 t3();
endmodule
module test;
initial #3 $mytest;
test2 t2();
endmodule
|
// Check that it is possible to reference a package scoped type identifier as
// the type in a type cast expression, even if there is a identifier of the same
// name in the local scope.
bit failed = 1\'b0;
`define check(expr, val) \\
if (expr !== val) begin \\
$display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \\
failed = 1\'b1; \\
end
package P;
typedef integer T;
endpackage
module test;
localparam T = 2;
integer x;
initial begin
x = P::T\'(-1024.123);
`check(x, -1024)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module test();
reg clk;
reg sel;
reg [7:0] a;
reg [6:0] b;
reg [5:0] q;
(* ivl_synthesis_on *)
always @(posedge clk) begin
if (sel)
q <= b;
else
q <= a;
end
(* ivl_synthesis_off *)
reg failed;
initial begin
a = \'haa;
b = \'hbb;
clk = 0;
sel = 0;
#1 clk = 1;
#1 clk = 0;
$display("%h", q);
if (q !== 6\'h2a) failed = 1;
sel = 1;
#1 clk = 1;
#1 clk = 0;
$display("%h", q);
if (q !== 6\'h3b) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module bug();
reg clock = 0;
always begin
#1 clock = 1;
#1 clock = 0;
end
integer count = 0;
initial begin:counter
forever begin
repeat (2) @(posedge clock);
count = count + 1;
$display(count);
end
end
initial begin
repeat (5) @(posedge clock);
disable counter;
repeat (4) @(posedge clock);
if (count === 2)
$display("PASSED");
else
$display("FAILED");
$finish;
end
endmodule
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for NOW() system function.
module now_test;
logic gen_report;
now_entity dut(gen_report);
initial begin
gen_report = 0;
#5;
gen_report = 1;
#5;
gen_report = 0;
#5;
gen_report = 1;
#5;
gen_report = 0;
#5;
gen_report = 1;
end
endmodule
|
/*
* This is a simple test for the for...join_any syntax. There is a
* fork statement to start a bunch of threads. We wait for none of
* them and instead watch them progress with the master thread.
*/
module main;
int flag;
initial begin
flag = 0;
fork
\t # 10 flag = 10;
\t # 20 flag = 20;
\t # 30 flag = 30;
join_any
#5 if (flag != 10) begin
\t $display("FAILED -- flag=%d (s.b. 10)", flag);
\t $finish;
end
#10 if (flag != 20) begin
\t $display("FAILED -- flag=%d (s.b. 20)", flag);
\t $finish;
end
#10 if (flag != 30) begin
\t $display("FAILED -- flag=%d (s.b. 30)", flag);
\t $finish;
end
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Simple parameter declaration
//
// D: Declare a parameter value, then assign it to a variable.
// D: Check the value of the variable.
//
module main();
parameter VAL_1\t= 16\'h0001;
parameter VAL_2 = 16\'h5432;
reg [15:0] test_var;
initial // Excitation block
begin
test_var = VAL_1 ;
#5 ;
test_var = VAL_2 ;
#5 ;
end
initial // Validation block
begin
#1 ;
if(test_var != 16\'h0001)
begin
$display("FAILED - param 1st assign didn\'t work\
");
$finish ;
end
#5 ;
if(test_var != 16\'h5432)
begin
$display("FAILED - param 2nd assign didn\'t work\
");
$finish ;
end
$display("PASSED\
");
$finish ;
end
endmodule
|
module negvalue;
reg[7:0]reg1;
initial begin
reg1 <= -13 +21 ;
#1
reg1 <= 0 -13 +21 ;
end
always@(reg1)begin
$display("%d (should be 8)",reg1);
end
endmodule
|
/*
* Copyright (c) 2005 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.will need a Picture Elements Binary Software
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program catches some glitches in the MUXZ that Icarus Verilog
* uses to implement the ?: in structural cases.
*/
module main;
parameter FOO = 0;
initial begin
if ((FOO < -255) || (FOO > 255)) begin
\t $display("FAILED -- foo=%d does not fall in the range?", FOO);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Regression test for GitHub issue 13 : Icarus Verilog creates huge in-memory
// arrays for shifts with large rhs.
module bug();
localparam [4:0] p = 1\'b1 << ~40\'b0;
initial begin
$display("%b", p);
if (p === 5\'b00000)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
//
// Name: testbench1.vhdl
//
// Author: Chris Eilbeck, [email protected]
//
// Purpose: VHDL testbench for a DES encryptor.
//
// IP Status: Free use is hereby granted for all civil use including personal, educational and commercial use.
// The use of this code for military, diplomatic or governmental purposes is specifically forbidden.
//
// Warranty: There is absolutely no warranty given with this code. You accept all responsibility for the use
// of this code and any damage so caused.
//
// Vers Info: v0.1 14/11/1998 - Creation.
//\t\t\t\t 14/11/1999 - Converted to Verilog (ajb)
//
module top;
reg clk;
reg [1:64] pt, key;
wire [1:64] ct;
integer i;
des des(pt, key, ct, clk);
initial
begin
$dumpfile("des.vcd");
$dumpvars(0, top);
key = 64\'h0000000000000000;
pt = 64\'h0000000000000000;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'hffffffffffffffff;
pt = 64\'hffffffffffffffff;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h3000000000000000;
pt = 64\'h1000000000000001;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h1111111111111111;
pt = 64\'h1111111111111111;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h0123456789abcdef;
pt = 64\'h1111111111111111;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h1111111111111111;
pt = 64\'h0123456789abcdef;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h0000000000000000;
pt = 64\'h0000000000000000;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'hfedcba9876543210;
pt = 64\'h0123456789abcdef;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h7ca110454a1a6e57;
pt = 64\'h01a1d6d039776742;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h0131d9619dc1376e;
pt = 64\'h5cd54ca83def57da;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h07a1133e4a0b2686;
pt = 64\'h0248d43806f67172;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h3849674c2602319e;
pt = 64\'h51454b582ddf440a;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h04b915ba43feb5b6;
pt = 64\'h42fd443059577fa2;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h0113b970fd34f2ce;
pt = 64\'h059b5e0851cf143a;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h0170f175468fb5e6;
pt = 64\'h0756d8e0774761d2;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h43297fad38e373fe;
pt = 64\'h762514b829bf486a;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h07a7137045da2a16;
pt = 64\'h3bdd119049372802;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h04689104c2fd3b2f;
pt = 64\'h26955f6835af609a;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h37d06bb516cb7546;
pt = 64\'h164d5e404f275232;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h1f08260d1ac2465e;
pt = 64\'h6b056e18759f5cca;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h584023641aba6176;
pt = 64\'h004bd6ef09176062;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
key = 64\'h025816164629b007;
pt = 64\'h480d39006ee762f2;
for(i=0;i<16;i=i+1) begin #1 clk=0; #1 clk=1; end
/*
int testkeys[]= // key, pt, ct
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8ca64de9, 0xc1b123a7,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x7359b216, 0x3e4edc58,
0x30000000, 0x00000000, 0x10000000, 0x00000001, 0x958e6e62, 0x7a05557b,
0x11111111, 0x11111111, 0x11111111, 0x11111111, 0xf40379ab, 0x9e0ec533,
0x01234567, 0x89abcdef, 0x11111111, 0x11111111, 0x17668dfc, 0x7292532d,
0x11111111, 0x11111111, 0x01234567, 0x89abcdef, 0x8a5ae1f8, 0x1ab8f2dd,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8ca64de9, 0xc1b123a7,
0xfedcba98, 0x76543210, 0x01234567, 0x89abcdef, 0xed39d950, 0xfa74bcc4,
0x7ca11045, 0x4a1a6e57, 0x01a1d6d0, 0x39776742, 0x690f5b0d, 0x9a26939b,
0x0131d961, 0x9dc1376e, 0x5cd54ca8, 0x3def57da, 0x7a389d10, 0x354bd271,
0x07a1133e, 0x4a0b2686, 0x0248d438, 0x06f67172, 0x868ebb51, 0xcab4599a,
0x3849674c, 0x2602319e, 0x51454b58, 0x2ddf440a, 0x7178876e, 0x01f19b2a,
0x04b915ba, 0x43feb5b6, 0x42fd4430, 0x59577fa2, 0xaf37fb42, 0x1f8c4095,
0x0113b970, 0xfd34f2ce, 0x059b5e08, 0x51cf143a, 0x86a560f1, 0x0ec6d85b,
0x0170f175, 0x468fb5e6, 0x0756d8e0, 0x774761d2, 0x0cd3da02, 0x0021dc09,
0x43297fad, 0x38e373fe, 0x762514b8, 0x29bf486a, 0xea676b2c, 0xb7db2b7a,
0x07a71370, 0x45da2a16, 0x3bdd1190, 0x49372802, 0xdfd64a81, 0x5caf1a0f,
0x04689104, 0xc2fd3b2f, 0x26955f68, 0x35af609a, 0x5c513c9c, 0x4886c088,
0x37d06bb5, 0x16cb7546, 0x164d5e40, 0x4f275232, 0x0a2aeeae, 0x3ff4ab77,
0x1f08260d, 0x1ac2465e, 0x6b056e18, 0x759f5cca, 0xef1bf03e, 0x5dfa575a,
0x58402364, 0x1aba6176, 0x004bd6ef, 0x09176062, 0x88bf0db6, 0xd70dee56,
0x02581616, 0x4629b007, 0x480d3900, 0x6ee762f2, 0xa1f99155, 0x41020b56,
0x49793ebc, 0x79b3258f, 0x437540c8, 0x698f3cfa, 0x6fbf1caf, 0xcffd0556,
0x4fb05e15, 0x15ab73a7, 0x072d43a0, 0x77075292, 0x2f22e49b, 0xab7ca1ac,
0x49e95d6d, 0x4ca229bf, 0x02fe5577, 0x8117f12a, 0x5a6b612c, 0xc26cce4a,
0x018310dc, 0x409b26d6, 0x1d9d5c50, 0x18f728c2, 0x5f4c038e, 0xd12b2e41,
0x1c587f1c, 0x13924fef, 0x30553228, 0x6d6f295a, 0x63fac0d0, 0x34d9f793,
0x01010101, 0x01010101, 0x01234567, 0x89abcdef, 0x617b3a0c, 0xe8f07100,
0x1f1f1f1f, 0x0e0e0e0e, 0x01234567, 0x89abcdef, 0xdb958605, 0xf8c8c606,
0xe0fee0fe, 0xf1fef1fe, 0x01234567, 0x89abcdef, 0xedbfd1c6, 0x6c29ccc7,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x355550b2, 0x150e2451,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0xcaaaaf4d, 0xeaf1dbae,
0x01234567, 0x89abcdef, 0x00000000, 0x00000000, 0xd5d44ff7, 0x20683d0d,
0xfedcba98, 0x76543210, 0xffffffff, 0xffffffff, 0x2a2bb008, 0xdf97c2f2,
};
*/
end
endmodule
module des(pt, key, ct, clk);
input\t[1:64] pt;
input\t[1:64] key;
output\t[1:64] ct;
input\tclk;
wire\t[1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x;
wire\t[1:32] l0x,l1x,l2x,l3x,l4x,l5x,l6x,l7x,l8x,l9x,l10x,l11x,l12x,l13x,l14x,l15x,l16x;
wire\t[1:32] r0x,r1x,r2x,r3x,r4x,r5x,r6x,r7x,r8x,r9x,r10x,r11x,r12x,r13x,r14x,r15x,r16x;
keysched keysched(key, k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x);
ip ip(pt, l0x, r0x);
roundfunc round1(clk, l0x, r0x, l1x, r1x, k1x);
roundfunc round2(clk, l1x, r1x, l2x, r2x, k2x);
roundfunc round3(clk, l2x, r2x, l3x, r3x, k3x);
roundfunc round4(clk, l3x, r3x, l4x, r4x, k4x);
roundfunc round5(clk, l4x, r4x, l5x, r5x, k5x);
roundfunc round6(clk, l5x, r5x, l6x, r6x, k6x);
roundfunc round7(clk, l6x, r6x, l7x, r7x, k7x);
roundfunc round8(clk, l7x, r7x, l8x, r8x, k8x);
roundfunc round9(clk, l8x, r8x, l9x, r9x, k9x);
roundfunc round10(clk, l9x, r9x, l10x, r10x, k10x);
roundfunc round11(clk, l10x, r10x, l11x, r11x, k11x);
roundfunc round12(clk, l11x, r11x, l12x, r12x, k12x);
roundfunc round13(clk, l12x, r12x, l13x, r13x, k13x);
roundfunc round14(clk, l13x, r13x, l14x, r14x, k14x);
roundfunc round15(clk, l14x, r14x, l15x, r15x, k15x);
roundfunc round16(clk, l15x, r15x, l16x, r16x, k16x);
fp fp(r16x, l16x, ct);
endmodule
module pc1(key, c0x, d0x);
input\t[1:64] key;
output\t[1:28] c0x, d0x;
wire\t[1:56] XX;
assign XX[1]=key[57]; assign XX[2]=key[49]; assign XX[3]=key[41]; assign XX[4]=key[33]; assign XX[5]=key[25]; assign XX[6]=key[17]; assign XX[7]=key[9];
assign XX[8]=key[1]; assign XX[9]=key[58]; assign XX[10]=key[50]; assign XX[11]=key[42]; assign XX[12]=key[34]; assign XX[13]=key[26]; assign XX[14]=key[18];
assign XX[15]=key[10]; assign XX[16]=key[2]; assign XX[17]=key[59]; assign XX[18]=key[51]; assign XX[19]=key[43]; assign XX[20]=key[35]; assign XX[21]=key[27];
assign XX[22]=key[19]; assign XX[23]=key[11]; assign XX[24]=key[3]; assign XX[25]=key[60]; assign XX[26]=key[52]; assign XX[27]=key[44]; assign XX[28]=key[36];
assign XX[29]=key[63]; assign XX[30]=key[55]; assign XX[31]=key[47]; assign XX[32]=key[39]; assign XX[33]=key[31]; assign XX[34]=key[23]; assign XX[35]=key[15];
assign XX[36]=key[7]; assign XX[37]=key[62]; assign XX[38]=key[54]; assign XX[39]=key[46]; assign XX[40]=key[38]; assign XX[41]=key[30]; assign XX[42]=key[22];
assign XX[43]=key[14]; assign XX[44]=key[6]; assign XX[45]=key[61]; assign XX[46]=key[53]; assign XX[47]=key[45]; assign XX[48]=key[37]; assign XX[49]=key[29];
assign XX[50]=key[21]; assign XX[51]=key[13]; assign XX[52]=key[5]; assign XX[53]=key[28]; assign XX[54]=key[20]; assign XX[55]=key[12]; assign XX[56]=key[4];
assign c0x=XX[1:28]; assign d0x=XX[29:56];
endmodule
module pc2(c,d,k);
input\t[1:28] c,d;
output\t[1:48] k;
wire\t[1:56] YY;
assign YY[1:28]=c; assign YY[29:56]=d;
assign k[1]=YY[14]; assign k[2]=YY[17]; assign k[3]=YY[11]; assign k[4]=YY[24]; assign k[5]=YY[1]; assign k[6]=YY[5];
assign k[7]=YY[3]; assign k[8]=YY[28]; assign k[9]=YY[15]; assign k[10]=YY[6]; assign k[11]=YY[21]; assign k[12]=YY[10];
assign k[13]=YY[23]; assign k[14]=YY[19]; assign k[15]=YY[12]; assign k[16]=YY[4]; assign k[17]=YY[26]; assign k[18]=YY[8];
assign k[19]=YY[16]; assign k[20]=YY[7]; assign k[21]=YY[27]; assign k[22]=YY[20]; assign k[23]=YY[13]; assign k[24]=YY[2];
assign k[25]=YY[41]; assign k[26]=YY[52]; assign k[27]=YY[31]; assign k[28]=YY[37]; assign k[29]=YY[47]; assign k[30]=YY[55];
assign k[31]=YY[30]; assign k[32]=YY[40]; assign k[33]=YY[51]; assign k[34]=YY[45]; assign k[35]=YY[33]; assign k[36]=YY[48];
assign k[37]=YY[44]; assign k[38]=YY[49]; assign k[39]=YY[39]; assign k[40]=YY[56]; assign k[41]=YY[34]; assign k[42]=YY[53];
assign k[43]=YY[46]; assign k[44]=YY[42]; assign k[45]=YY[50]; assign k[46]=YY[36]; assign k[47]=YY[29]; assign k[48]=YY[32];
endmodule
module rol1(o, i);
output\t[1:28] o;
input\t[1:28] i;
assign o={i[2:28],i[1]};
endmodule
module rol2(o, i);
output\t[1:28] o;
input\t[1:28] i;
assign o={i[3:28],i[1:2]};
endmodule
module keysched(key,k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x);
input\t[1:64] key;
output\t[1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x;
wire\t[1:28] c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,c10x,c11x,c12x,c13x,c14x,c15x,c16x;
wire\t[1:28] d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,d10x,d11x,d12x,d13x,d14x,d15x,d16x;
pc1 pc1(key, c0x, d0x);
rol1 rc1(c1x, c0x); rol1 rd1(d1x, d0x);
rol1 rc2(c2x, c1x); rol1 rd2(d2x, d1x);
rol2 rc3(c3x, c2x); rol2 rd3(d3x, d2x);
rol2 rc4(c4x, c3x); rol2 rd4(d4x, d3x);
rol2 rc5(c5x, c4x); rol2 rd5(d5x, d4x);
rol2 rc6(c6x, c5x); rol2 rd6(d6x, d5x);
rol2 rc7(c7x, c6x); rol2 rd7(d7x, d6x);
rol2 rc8(c8x, c7x); rol2 rd8(d8x, d7x);
rol1 rc9(c9x, c8x); rol1 rd9(d9x, d8x);
rol2 rca(c10x, c9x); rol2 rda(d10x, d9x);
rol2 rcb(c11x, c10x); rol2 rdb(d11x, d10x);
rol2 rcc(c12x, c11x); rol2 rdc(d12x, d11x);
rol2 rcd(c13x, c12x); rol2 rdd(d13x, d12x);
rol2 rce(c14x, c13x); rol2 rde(d14x, d13x);
rol2 rcf(c15x, c14x); rol2 rdf(d15x, d14x);
rol1 rcg(c16x, c15x); rol1 rdg(d16x, d15x);
pc2 pc2x1(c1x,d1x,k1x);
pc2 pc2x2(c2x,d2x,k2x);
pc2 pc2x3(c3x,d3x,k3x);
pc2 pc2x4(c4x,d4x,k4x);
pc2 pc2x5(c5x,d5x,k5x);
pc2 pc2x6(c6x,d6x,k6x);
pc2 pc2x7(c7x,d7x,k7x);
pc2 pc2x8(c8x,d8x,k8x);
pc2 pc2x9(c9x,d9x,k9x);
pc2 pc2x10(c10x,d10x,k10x);
pc2 pc2x11(c11x,d11x,k11x);
pc2 pc2x12(c12x,d12x,k12x);
pc2 pc2x13(c13x,d13x,k13x);
pc2 pc2x14(c14x,d14x,k14x);
pc2 pc2x15(c15x,d15x,k15x);
pc2 pc2x16(c16x,d16x,k16x);
endmodule
module s1(clk, b, so);
input\tclk;
input\t[1:6] b;
output\t[1:4] so;
reg\t[1:4] so;
\talways @(posedge clk)
\t\tcasex(b)
\t\t\t\t6\'b000000 :\tso=4\'he;
\t\t\t\t6\'b000010 :\tso=4\'h4;
\t\t\t\t6\'b000100 :\tso=4\'hd;
\t\t\t\t6\'b000110 :\tso=4\'h1;
\t\t\t\t6\'b001000 :\tso=4\'h2;
\t\t\t\t6\'b001010 :\tso=4\'hf;
\t\t\t\t6\'b001100 :\tso=4\'hb;
\t\t\t\t6\'b001110 :\tso=4\'h8;
\t\t\t\t6\'b010000 :\tso=4\'h3;
\t\t\t\t6\'b010010 :\tso=4\'ha;
\t\t\t\t6\'b010100 :\tso=4\'h6;
\t\t\t\t6\'b010110 :\tso=4\'hc;
\t\t\t\t6\'b011000 :\tso=4\'h5;
\t\t\t\t6\'b011010 :\tso=4\'h9;
\t\t\t\t6\'b011100 :\tso=4\'h0;
\t\t\t\t6\'b011110 :\tso=4\'h7;
\t\t\t\t6\'b000001 :\tso=4\'h0;
\t\t\t\t6\'b000011 :\tso=4\'hf;
\t\t\t\t6\'b000101 :\tso=4\'h7;
\t\t\t\t6\'b000111 :\tso=4\'h4;
\t\t\t\t6\'b001001 :\tso=4\'he;
\t\t\t\t6\'b001011 :\tso=4\'h2;
\t\t\t\t6\'b001101 :\tso=4\'hd;
\t\t\t\t6\'b001111 :\tso=4\'h1;
\t\t\t\t6\'b010001 :\tso=4\'ha;
\t\t\t\t6\'b010011 :\tso=4\'h6;
\t\t\t\t6\'b010101 :\tso=4\'hc;
\t\t\t\t6\'b010111 :\tso=4\'hb;
\t\t\t\t6\'b011001 :\tso=4\'h9;
\t\t\t\t6\'b011011 :\tso=4\'h5;
\t\t\t\t6\'b011101 :\tso=4\'h3;
\t\t\t\t6\'b011111 :\tso=4\'h8;
\t\t\t\t6\'b100000 :\tso=4\'h4;
\t\t\t\t6\'b100010 :\tso=4\'h1;
\t\t\t\t6\'b100100 :\tso=4\'he;
\t\t\t\t6\'b100110 :\tso=4\'h8;
\t\t\t\t6\'b101000 :\tso=4\'hd;
\t\t\t\t6\'b101010 :\tso=4\'h6;
\t\t\t\t6\'b101100 :\tso=4\'h2;
\t\t\t\t6\'b101110 :\tso=4\'hb;
\t\t\t\t6\'b110000 :\tso=4\'hf;
\t\t\t\t6\'b110010 :\tso=4\'hc;
\t\t\t\t6\'b110100 :\tso=4\'h9;
\t\t\t\t6\'b110110 :\tso=4\'h7;
\t\t\t\t6\'b111000 :\tso=4\'h3;
\t\t\t\t6\'b111010 :\tso=4\'ha;
\t\t\t\t6\'b111100 :\tso=4\'h5;
\t\t\t\t6\'b111110 :\tso=4\'h0;
\t\t\t\t6\'b100001 :\tso=4\'hf;
\t\t\t\t6\'b100011 :\tso=4\'hc;
\t\t\t\t6\'b100101 :\tso=4\'h8;
\t\t\t\t6\'b100111 :\tso=4\'h2;
\t\t\t\t6\'b101001 :\tso=4\'h4;
\t\t\t\t6\'b101011 :\tso=4\'h9;
\t\t\t\t6\'b101101 :\tso=4\'h1;
\t\t\t\t6\'b101111 :\tso=4\'h7;
\t\t\t\t6\'b110001 :\tso=4\'h5;
\t\t\t\t6\'b110011 :\tso=4\'hb;
\t\t\t\t6\'b110101 :\tso=4\'h3;
\t\t\t\t6\'b110111 :\tso=4\'he;
\t\t\t\t6\'b111001 :\tso=4\'ha;
\t\t\t\t6\'b111011 :\tso=4\'h0;
\t\t\t\t6\'b111101 :\tso=4\'h6;
\t\t\t\tdefault so=4\'hd;
\t\t\tendcase
endmodule
module s2(clk, b, so);
input\tclk;
input\t[1:6] b;
output\t[1:4] so;
reg\t[1:4] so;
\talways @(posedge clk)
\t\tcasex(b)
6\'b000000 : so=4\'hf;
6\'b000010 : so=4\'h1;
6\'b000100 : so=4\'h8;
6\'b000110 : so=4\'he;
6\'b001000 : so=4\'h6;
6\'b001010 : so=4\'hb;
6\'b001100 : so=4\'h3;
6\'b001110 : so=4\'h4;
6\'b010000 : so=4\'h9;
6\'b010010 : so=4\'h7;
6\'b010100 : so=4\'h2;
6\'b010110 : so=4\'hd;
6\'b011000 : so=4\'hc;
6\'b011010 : so=4\'h0;
6\'b011100 : so=4\'h5;
6\'b011110 : so=4\'ha;
6\'b000001 : so=4\'h3;
6\'b000011 : so=4\'hd;
6\'b000101 : so=4\'h4;
6\'b000111 : so=4\'h7;
6\'b001001 : so=4\'hf;
6\'b001011 : so=4\'h2;
6\'b001101 : so=4\'h8;
6\'b001111 : so=4\'he;
6\'b010001 : so=4\'hc;
6\'b010011 : so=4\'h0;
6\'b010101 : so=4\'h1;
6\'b010111 : so=4\'ha;
6\'b011001 : so=4\'h6;
6\'b011011 : so=4\'h9;
6\'b011101 : so=4\'hb;
6\'b011111 : so=4\'h5;
6\'b100000 : so=4\'h0;
6\'b100010 : so=4\'he;
6\'b100100 : so=4\'h7;
6\'b100110 : so=4\'hb;
6\'b101000 : so=4\'ha;
6\'b101010 : so=4\'h4;
6\'b101100 : so=4\'hd;
6\'b101110 : so=4\'h1;
6\'b110000 : so=4\'h5;
6\'b110010 : so=4\'h8;
6\'b110100 : so=4\'hc;
6\'b110110 : so=4\'h6;
6\'b111000 : so=4\'h9;
6\'b111010 : so=4\'h3;
6\'b111100 : so=4\'h2;
6\'b111110 : so=4\'hf;
6\'b100001 : so=4\'hd;
6\'b100011 : so=4\'h8;
6\'b100101 : so=4\'ha;
6\'b100111 : so=4\'h1;
6\'b101001 : so=4\'h3;
6\'b101011 : so=4\'hf;
6\'b101101 : so=4\'h4;
6\'b101111 : so=4\'h2;
6\'b110001 : so=4\'hb;
6\'b110011 : so=4\'h6;
6\'b110101 : so=4\'h7;
6\'b110111 : so=4\'hc;
6\'b111001 : so=4\'h0;
6\'b111011 : so=4\'h5;
6\'b111101 : so=4\'he;
default so=4\'h9;
\t\t\tendcase
endmodule
module s3(clk, b, so);
input\tclk;
input\t[1:6] b;
output\t[1:4] so;
reg\t[1:4] so;
\talways @(posedge clk)
\t\tcasex(b)
6\'b000000 : so=4\'ha;
6\'b000010 : so=4\'h0;
6\'b000100 : so=4\'h9;
6\'b000110 : so=4\'he;
6\'b001000 : so=4\'h6;
6\'b001010 : so=4\'h3;
6\'b001100 : so=4\'hf;
6\'b001110 : so=4\'h5;
6\'b010000 : so=4\'h1;
6\'b010010 : so=4\'hd;
6\'b010100 : so=4\'hc;
6\'b010110 : so=4\'h7;
6\'b011000 : so=4\'hb;
6\'b011010 : so=4\'h4;
6\'b011100 : so=4\'h2;
6\'b011110 : so=4\'h8;
6\'b000001 : so=4\'hd;
6\'b000011 : so=4\'h7;
6\'b000101 : so=4\'h0;
6\'b000111 : so=4\'h9;
6\'b001001 : so=4\'h3;
6\'b001011 : so=4\'h4;
6\'b001101 : so=4\'h6;
6\'b001111 : so=4\'ha;
6\'b010001 : so=4\'h2;
6\'b010011 : so=4\'h8;
6\'b010101 : so=4\'h5;
6\'b010111 : so=4\'he;
6\'b011001 : so=4\'hc;
6\'b011011 : so=4\'hb;
6\'b011101 : so=4\'hf;
6\'b011111 : so=4\'h1;
6\'b100000 : so=4\'hd;
6\'b100010 : so=4\'h6;
6\'b100100 : so=4\'h4;
6\'b100110 : so=4\'h9;
6\'b101000 : so=4\'h8;
6\'b101010 : so=4\'hf;
6\'b101100 : so=4\'h3;
6\'b101110 : so=4\'h0;
6\'b110000 : so=4\'hb;
6\'b110010 : so=4\'h1;
6\'b110100 : so=4\'h2;
6\'b110110 : so=4\'hc;
6\'b111000 : so=4\'h5;
6\'b111010 : so=4\'ha;
6\'b111100 : so=4\'he;
6\'b111110 : so=4\'h7;
6\'b100001 : so=4\'h1;
6\'b100011 : so=4\'ha;
6\'b100101 : so=4\'hd;
6\'b100111 : so=4\'h0;
6\'b101001 : so=4\'h6;
6\'b101011 : so=4\'h9;
6\'b101101 : so=4\'h8;
6\'b101111 : so=4\'h7;
6\'b110001 : so=4\'h4;
6\'b110011 : so=4\'hf;
6\'b110101 : so=4\'he;
6\'b110111 : so=4\'h3;
6\'b111001 : so=4\'hb;
6\'b111011 : so=4\'h5;
6\'b111101 : so=4\'h2;
default so=4\'hc;
\t\t\tendcase
endmodule
module s4(clk, b, so);
input\tclk;
input\t[1:6] b;
output\t[1:4] so;
reg\t[1:4] so;
\talways @(posedge clk)
\t\tcasex(b)
6\'b000000 : so=4\'h7;
6\'b000010 : so=4\'hd;
6\'b000100 : so=4\'he;
6\'b000110 : so=4\'h3;
6\'b001000 : so=4\'h0;
6\'b001010 : so=4\'h6;
6\'b001100 : so=4\'h9;
6\'b001110 : so=4\'ha;
6\'b010000 : so=4\'h1;
6\'b010010 : so=4\'h2;
6\'b010100 : so=4\'h8;
6\'b010110 : so=4\'h5;
6\'b011000 : so=4\'hb;
6\'b011010 : so=4\'hc;
6\'b011100 : so=4\'h4;
6\'b011110 : so=4\'hf;
6\'b000001 : so=4\'hd;
6\'b000011 : so=4\'h8;
6\'b000101 : so=4\'hb;
6\'b000111 : so=4\'h5;
6\'b001001 : so=4\'h6;
6\'b001011 : so=4\'hf;
6\'b001101 : so=4\'h0;
6\'b001111 : so=4\'h3;
6\'b010001 : so=4\'h4;
6\'b010011 : so=4\'h7;
6\'b010101 : so=4\'h2;
6\'b010111 : so=4\'hc;
6\'b011001 : so=4\'h1;
6\'b011011 : so=4\'ha;
6\'b011101 : so=4\'he;
6\'b011111 : so=4\'h9;
6\'b100000 : so=4\'ha;
6\'b100010 : so=4\'h6;
6\'b100100 : so=4\'h9;
6\'b100110 : so=4\'h0;
6\'b101000 : so=4\'hc;
6\'b101010 : so=4\'hb;
6\'b101100 : so=4\'h7;
6\'b101110 : so=4\'hd;
6\'b110000 : so=4\'hf;
6\'b110010 : so=4\'h1;
6\'b110100 : so=4\'h3;
6\'b110110 : so=4\'he;
6\'b111000 : so=4\'h5;
6\'b111010 : so=4\'h2;
6\'b111100 : so=4\'h8;
6\'b111110 : so=4\'h4;
6\'b100001 : so=4\'h3;
6\'b100011 : so=4\'hf;
6\'b100101 : so=4\'h0;
6\'b100111 : so=4\'h6;
6\'b101001 : so=4\'ha;
6\'b101011 : so=4\'h1;
6\'b101101 : so=4\'hd;
6\'b101111 : so=4\'h8;
6\'b110001 : so=4\'h9;
6\'b110011 : so=4\'h4;
6\'b110101 : so=4\'h5;
6\'b110111 : so=4\'hb;
6\'b111001 : so=4\'hc;
6\'b111011 : so=4\'h7;
6\'b111101 : so=4\'h2;
default so=4\'he;
\t\t\tendcase
endmodule
module s5(clk, b, so);
input\tclk;
input\t[1:6] b;
output\t[1:4] so;
reg\t[1:4] so;
\talways @(posedge clk)
\t\tcasex(b)
6\'b000000 : so=4\'h2;
6\'b000010 : so=4\'hc;
6\'b000100 : so=4\'h4;
6\'b000110 : so=4\'h1;
6\'b001000 : so=4\'h7;
6\'b001010 : so=4\'ha;
6\'b001100 : so=4\'hb;
6\'b001110 : so=4\'h6;
6\'b010000 : so=4\'h8;
6\'b010010 : so=4\'h5;
6\'b010100 : so=4\'h3;
6\'b010110 : so=4\'hf;
6\'b011000 : so=4\'hd;
6\'b011010 : so=4\'h0;
6\'b011100 : so=4\'he;
6\'b011110 : so=4\'h9;
6\'b000001 : so=4\'he;
6\'b000011 : so=4\'hb;
6\'b000101 : so=4\'h2;
6\'b000111 : so=4\'hc;
6\'b001001 : so=4\'h4;
6\'b001011 : so=4\'h7;
6\'b001101 : so=4\'hd;
6\'b001111 : so=4\'h1;
6\'b010001 : so=4\'h5;
6\'b010011 : so=4\'h0;
6\'b010101 : so=4\'hf;
6\'b010111 : so=4\'ha;
6\'b011001 : so=4\'h3;
6\'b011011 : so=4\'h9;
6\'b011101 : so=4\'h8;
6\'b011111 : so=4\'h6;
6\'b100000 : so=4\'h4;
6\'b100010 : so=4\'h2;
6\'b100100 : so=4\'h1;
6\'b100110 : so=4\'hb;
6\'b101000 : so=4\'ha;
6\'b101010 : so=4\'hd;
6\'b101100 : so=4\'h7;
6\'b101110 : so=4\'h8;
6\'b110000 : so=4\'hf;
6\'b110010 : so=4\'h9;
6\'b110100 : so=4\'hc;
6\'b110110 : so=4\'h5;
6\'b111000 : so=4\'h6;
6\'b111010 : so=4\'h3;
6\'b111100 : so=4\'h0;
6\'b111110 : so=4\'he;
6\'b100001 : so=4\'hb;
6\'b100011 : so=4\'h8;
6\'b100101 : so=4\'hc;
6\'b100111 : so=4\'h7;
6\'b101001 : so=4\'h1;
6\'b101011 : so=4\'he;
6\'b101101 : so=4\'h2;
6\'b101111 : so=4\'hd;
6\'b110001 : so=4\'h6;
6\'b110011 : so=4\'hf;
6\'b110101 : so=4\'h0;
6\'b110111 : so=4\'h9;
6\'b111001 : so=4\'ha;
6\'b111011 : so=4\'h4;
6\'b111101 : so=4\'h5;
default so=4\'h3;
\t\t\tendcase
endmodule
module s6(clk, b, so);
input\tclk;
input\t[1:6] b;
output\t[1:4] so;
reg\t[1:4] so;
\talways @(posedge clk)
\t\tcasex(b)
6\'b000000 : so=4\'hc;
6\'b000010 : so=4\'h1;
6\'b000100 : so=4\'ha;
6\'b000110 : so=4\'hf;
6\'b001000 : so=4\'h9;
6\'b001010 : so=4\'h2;
6\'b001100 : so=4\'h6;
6\'b001110 : so=4\'h8;
6\'b010000 : so=4\'h0;
6\'b010010 : so=4\'hd;
6\'b010100 : so=4\'h3;
6\'b010110 : so=4\'h4;
6\'b011000 : so=4\'he;
6\'b011010 : so=4\'h7;
6\'b011100 : so=4\'h5;
6\'b011110 : so=4\'hb;
6\'b000001 : so=4\'ha;
6\'b000011 : so=4\'hf;
6\'b000101 : so=4\'h4;
6\'b000111 : so=4\'h2;
6\'b001001 : so=4\'h7;
6\'b001011 : so=4\'hc;
6\'b001101 : so=4\'h9;
6\'b001111 : so=4\'h5;
6\'b010001 : so=4\'h6;
6\'b010011 : so=4\'h1;
6\'b010101 : so=4\'hd;
6\'b010111 : so=4\'he;
6\'b011001 : so=4\'h0;
6\'b011011 : so=4\'hb;
6\'b011101 : so=4\'h3;
6\'b011111 : so=4\'h8;
6\'b100000 : so=4\'h9;
6\'b100010 : so=4\'he;
6\'b100100 : so=4\'hf;
6\'b100110 : so=4\'h5;
6\'b101000 : so=4\'h2;
6\'b101010 : so=4\'h8;
6\'b101100 : so=4\'hc;
6\'b101110 : so=4\'h3;
6\'b110000 : so=4\'h7;
6\'b110010 : so=4\'h0;
6\'b110100 : so=4\'h4;
6\'b110110 : so=4\'ha;
6\'b111000 : so=4\'h1;
6\'b111010 : so=4\'hd;
6\'b111100 : so=4\'hb;
6\'b111110 : so=4\'h6;
6\'b100001 : so=4\'h4;
6\'b100011 : so=4\'h3;
6\'b100101 : so=4\'h2;
6\'b100111 : so=4\'hc;
6\'b101001 : so=4\'h9;
6\'b101011 : so=4\'h5;
6\'b101101 : so=4\'hf;
6\'b101111 : so=4\'ha;
6\'b110001 : so=4\'hb;
6\'b110011 : so=4\'he;
6\'b110101 : so=4\'h1;
6\'b110111 : so=4\'h7;
6\'b111001 : so=4\'h6;
6\'b111011 : so=4\'h0;
6\'b111101 : so=4\'h8;
default so=4\'hd;
\t\t\tendcase
endmodule
module s7(clk, b, so);
input\tclk;
input\t[1:6] b;
output\t[1:4] so;
reg\t[1:4] so;
\talways @(posedge clk)
\t\tcasex(b)
6\'b000000 : so=4\'h4;
6\'b000010 : so=4\'hb;
6\'b000100 : so=4\'h2;
6\'b000110 : so=4\'he;
6\'b001000 : so=4\'hf;
6\'b001010 : so=4\'h0;
6\'b001100 : so=4\'h8;
6\'b001110 : so=4\'hd;
6\'b010000 : so=4\'h3;
6\'b010010 : so=4\'hc;
6\'b010100 : so=4\'h9;
6\'b010110 : so=4\'h7;
6\'b011000 : so=4\'h5;
6\'b011010 : so=4\'ha;
6\'b011100 : so=4\'h6;
6\'b011110 : so=4\'h1;
6\'b000001 : so=4\'hd;
6\'b000011 : so=4\'h0;
6\'b000101 : so=4\'hb;
6\'b000111 : so=4\'h7;
6\'b001001 : so=4\'h4;
6\'b001011 : so=4\'h9;
6\'b001101 : so=4\'h1;
6\'b001111 : so=4\'ha;
6\'b010001 : so=4\'he;
6\'b010011 : so=4\'h3;
6\'b010101 : so=4\'h5;
6\'b010111 : so=4\'hc;
6\'b011001 : so=4\'h2;
6\'b011011 : so=4\'hf;
6\'b011101 : so=4\'h8;
6\'b011111 : so=4\'h6;
6\'b100000 : so=4\'h1;
6\'b100010 : so=4\'h4;
6\'b100100 : so=4\'hb;
6\'b100110 : so=4\'hd;
6\'b101000 : so=4\'hc;
6\'b101010 : so=4\'h3;
6\'b101100 : so=4\'h7;
6\'b101110 : so=4\'he;
6\'b110000 : so=4\'ha;
6\'b110010 : so=4\'hf;
6\'b110100 : so=4\'h6;
6\'b110110 : so=4\'h8;
6\'b111000 : so=4\'h0;
6\'b111010 : so=4\'h5;
6\'b111100 : so=4\'h9;
6\'b111110 : so=4\'h2;
6\'b100001 : so=4\'h6;
6\'b100011 : so=4\'hb;
6\'b100101 : so=4\'hd;
6\'b100111 : so=4\'h8;
6\'b101001 : so=4\'h1;
6\'b101011 : so=4\'h4;
6\'b101101 : so=4\'ha;
6\'b101111 : so=4\'h7;
6\'b110001 : so=4\'h9;
6\'b110011 : so=4\'h5;
6\'b110101 : so=4\'h0;
6\'b110111 : so=4\'hf;
6\'b111001 : so=4\'he;
6\'b111011 : so=4\'h2;
6\'b111101 : so=4\'h3;
default so=4\'hc;
\t\t\tendcase
endmodule
module s8(clk, b, so);
input\tclk;
input\t[1:6] b;
output\t[1:4] so;
reg\t[1:4] so;
\talways @(posedge clk)
\t\tcasex(b)
6\'b000000 : so=4\'hd;
6\'b000010 : so=4\'h2;
6\'b000100 : so=4\'h8;
6\'b000110 : so=4\'h4;
6\'b001000 : so=4\'h6;
6\'b001010 : so=4\'hf;
6\'b001100 : so=4\'hb;
6\'b001110 : so=4\'h1;
6\'b010000 : so=4\'ha;
6\'b010010 : so=4\'h9;
6\'b010100 : so=4\'h3;
6\'b010110 : so=4\'he;
6\'b011000 : so=4\'h5;
6\'b011010 : so=4\'h0;
6\'b011100 : so=4\'hc;
6\'b011110 : so=4\'h7;
6\'b000001 : so=4\'h1;
6\'b000011 : so=4\'hf;
6\'b000101 : so=4\'hd;
6\'b000111 : so=4\'h8;
6\'b001001 : so=4\'ha;
6\'b001011 : so=4\'h3;
6\'b001101 : so=4\'h7;
6\'b001111 : so=4\'h4;
6\'b010001 : so=4\'hc;
6\'b010011 : so=4\'h5;
6\'b010101 : so=4\'h6;
6\'b010111 : so=4\'hb;
6\'b011001 : so=4\'h0;
6\'b011011 : so=4\'he;
6\'b011101 : so=4\'h9;
6\'b011111 : so=4\'h2;
6\'b100000 : so=4\'h7;
6\'b100010 : so=4\'hb;
6\'b100100 : so=4\'h4;
6\'b100110 : so=4\'h1;
6\'b101000 : so=4\'h9;
6\'b101010 : so=4\'hc;
6\'b101100 : so=4\'he;
6\'b101110 : so=4\'h2;
6\'b110000 : so=4\'h0;
6\'b110010 : so=4\'h6;
6\'b110100 : so=4\'ha;
6\'b110110 : so=4\'hd;
6\'b111000 : so=4\'hf;
6\'b111010 : so=4\'h3;
6\'b111100 : so=4\'h5;
6\'b111110 : so=4\'h8;
6\'b100001 : so=4\'h2;
6\'b100011 : so=4\'h1;
6\'b100101 : so=4\'he;
6\'b100111 : so=4\'h7;
6\'b101001 : so=4\'h4;
6\'b101011 : so=4\'ha;
6\'b101101 : so=4\'h8;
6\'b101111 : so=4\'hd;
6\'b110001 : so=4\'hf;
6\'b110011 : so=4\'hc;
6\'b110101 : so=4\'h9;
6\'b110111 : so=4\'h0;
6\'b111001 : so=4\'h3;
6\'b111011 : so=4\'h5;
6\'b111101 : so=4\'h6;
default so=4\'hb;
\t\t\tendcase
endmodule
module ip(pt, l0x, r0x);
input\t[1:64] pt;
output\t[1:32] l0x, r0x;
assign l0x[1]=pt[58]; assign l0x[2]=pt[50]; assign l0x[3]=pt[42]; assign l0x[4]=pt[34];
assign l0x[5]=pt[26]; assign l0x[6]=pt[18]; assign l0x[7]=pt[10]; assign l0x[8]=pt[2];
assign l0x[9]=pt[60]; assign l0x[10]=pt[52]; assign l0x[11]=pt[44]; assign l0x[12]=pt[36];
assign l0x[13]=pt[28]; assign l0x[14]=pt[20]; assign l0x[15]=pt[12]; assign l0x[16]=pt[4];
assign l0x[17]=pt[62]; assign l0x[18]=pt[54]; assign l0x[19]=pt[46]; assign l0x[20]=pt[38];
assign l0x[21]=pt[30]; assign l0x[22]=pt[22]; assign l0x[23]=pt[14]; assign l0x[24]=pt[6];
assign l0x[25]=pt[64]; assign l0x[26]=pt[56]; assign l0x[27]=pt[48]; assign l0x[28]=pt[40];
assign l0x[29]=pt[32]; assign l0x[30]=pt[24]; assign l0x[31]=pt[16]; assign l0x[32]=pt[8];
assign r0x[1]=pt[57]; assign r0x[2]=pt[49]; assign r0x[3]=pt[41]; assign r0x[4]=pt[33];
assign r0x[5]=pt[25]; assign r0x[6]=pt[17]; assign r0x[7]=pt[9]; assign r0x[8]=pt[1];
assign r0x[9]=pt[59]; assign r0x[10]=pt[51]; assign r0x[11]=pt[43]; assign r0x[12]=pt[35];
assign r0x[13]=pt[27]; assign r0x[14]=pt[19]; assign r0x[15]=pt[11]; assign r0x[16]=pt[3];
assign r0x[17]=pt[61]; assign r0x[18]=pt[53]; assign r0x[19]=pt[45]; assign r0x[20]=pt[37];
assign r0x[21]=pt[29]; assign r0x[22]=pt[21]; assign r0x[23]=pt[13]; assign r0x[24]=pt[5];
assign r0x[25]=pt[63]; assign r0x[26]=pt[55]; assign r0x[27]=pt[47]; assign r0x[28]=pt[39];
assign r0x[29]=pt[31]; assign r0x[30]=pt[23]; assign r0x[31]=pt[15]; assign r0x[32]=pt[7];
endmodule
module xp(ri, e);
input [1:32] ri;
output [1:48] e;
assign e[1]=ri[32]; assign e[2]=ri[1]; assign e[3]=ri[2]; assign e[4]=ri[3]; assign e[5]=ri[4]; assign e[6]=ri[5]; assign e[7]=ri[4]; assign e[8]=ri[5];
assign e[9]=ri[6]; assign e[10]=ri[7]; assign e[11]=ri[8]; assign e[12]=ri[9]; assign e[13]=ri[8]; assign e[14]=ri[9]; assign e[15]=ri[10]; assign e[16]=ri[11];
assign e[17]=ri[12]; assign e[18]=ri[13]; assign e[19]=ri[12]; assign e[20]=ri[13]; assign e[21]=ri[14]; assign e[22]=ri[15]; assign e[23]=ri[16]; assign e[24]=ri[17];
assign e[25]=ri[16]; assign e[26]=ri[17]; assign e[27]=ri[18]; assign e[28]=ri[19]; assign e[29]=ri[20]; assign e[30]=ri[21]; assign e[31]=ri[20]; assign e[32]=ri[21];
assign e[33]=ri[22]; assign e[34]=ri[23]; assign e[35]=ri[24]; assign e[36]=ri[25]; assign e[37]=ri[24]; assign e[38]=ri[25]; assign e[39]=ri[26]; assign e[40]=ri[27];
assign e[41]=ri[28]; assign e[42]=ri[29]; assign e[43]=ri[28]; assign e[44]=ri[29]; assign e[45]=ri[30]; assign e[46]=ri[31]; assign e[47]=ri[32]; assign e[48]=ri[1];
endmodule
module desxor1(e,b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x,k);
input\t[1:48] e;
output\t[1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x;
input\t[1:48] k;
wire\t[1:48] XX;
assign XX = k ^ e;
assign b1x = XX[1:6];
assign b2x = XX[7:12];
assign b3x = XX[13:18];
assign b4x = XX[19:24];
assign b5x = XX[25:30];
assign b6x = XX[31:36];
assign b7x = XX[37:42];
assign b8x = XX[43:48];
endmodule
module pp(so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x,ppo);
input\t[1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x;
output\t[1:32] ppo;
wire\t[1:32] XX;
assign XX[1:4]=so1x; assign XX[5:8]=so2x; assign XX[9:12]=so3x; assign XX[13:16]=so4x;
assign XX[17:20]=so5x; assign XX[21:24]=so6x; assign XX[25:28]=so7x; assign XX[29:32]=so8x;
assign ppo[1]=XX[16]; assign ppo[2]=XX[7]; assign ppo[3]=XX[20]; assign ppo[4]=XX[21];
assign ppo[5]=XX[29]; assign ppo[6]=XX[12]; assign ppo[7]=XX[28]; assign ppo[8]=XX[17];
assign ppo[9]=XX[1]; assign ppo[10]=XX[15]; assign ppo[11]=XX[23]; assign ppo[12]=XX[26];
assign ppo[13]=XX[5]; assign ppo[14]=XX[18]; assign ppo[15]=XX[31]; assign ppo[16]=XX[10];
assign ppo[17]=XX[2]; assign ppo[18]=XX[8]; assign ppo[19]=XX[24]; assign ppo[20]=XX[14];
assign ppo[21]=XX[32]; assign ppo[22]=XX[27]; assign ppo[23]=XX[3]; assign ppo[24]=XX[9];
assign ppo[25]=XX[19]; assign ppo[26]=XX[13]; assign ppo[27]=XX[30]; assign ppo[28]=XX[6];
assign ppo[29]=XX[22]; assign ppo[30]=XX[11]; assign ppo[31]=XX[4]; assign ppo[32]=XX[25];
endmodule
module desxor2(d,l,q);
input\t[1:32] d,l;
output\t[1:32] q;
assign q = d ^ l;
endmodule
module roundfunc(clk, li, ri, lo, ro, k);
input\tclk;
input\t[1:32] li, ri;
input\t[1:48] k;
output\t[1:32] lo, ro;
wire\t[1:48] e;
wire\t[1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x;
wire\t[1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x;
wire\t[1:32] ppo;
xp xp(ri, e);
desxor1 desxor1(e, b1x, b2x, b3x, b4x, b5x, b6x, b7x, b8x, k);
s1 s1(clk, b1x, so1x);
s2 s2(clk, b2x, so2x);
s3 s3(clk, b3x, so3x);
s4 s4(clk, b4x, so4x);
s5 s5(clk, b5x, so5x);
s6 s6(clk, b6x, so6x);
s7 s7(clk, b7x, so7x);
s8 s8(clk, b8x, so8x);
pp pp(so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x, ppo);
desxor2 desxor2(ppo, li, ro);
assign lo=ri;
endmodule
module fp(l,r,ct);
input\t[1:32] l,r;
output\t[1:64] ct;
\tassign ct[1]=r[8];\tassign ct[2]=l[8];\tassign ct[3]=r[16];\tassign ct[4]=l[16];\tassign ct[5]=r[24];\tassign ct[6]=l[24];\tassign ct[7]=r[32];\tassign ct[8]=l[32];
\tassign ct[9]=r[7];\tassign ct[10]=l[7];\tassign ct[11]=r[15];\tassign ct[12]=l[15];\tassign ct[13]=r[23];\tassign ct[14]=l[23];\tassign ct[15]=r[31];\tassign ct[16]=l[31];
\tassign ct[17]=r[6];\tassign ct[18]=l[6];\tassign ct[19]=r[14];\tassign ct[20]=l[14];\tassign ct[21]=r[22];\tassign ct[22]=l[22];\tassign ct[23]=r[30];\tassign ct[24]=l[30];
\tassign ct[25]=r[5];\tassign ct[26]=l[5];\tassign ct[27]=r[13];\tassign ct[28]=l[13];\tassign ct[29]=r[21];\tassign ct[30]=l[21];\tassign ct[31]=r[29];\tassign ct[32]=l[29];
\tassign ct[33]=r[4];\tassign ct[34]=l[4];\tassign ct[35]=r[12];\tassign ct[36]=l[12];\tassign ct[37]=r[20];\tassign ct[38]=l[20];\tassign ct[39]=r[28];\tassign ct[40]=l[28];
\tassign ct[41]=r[3];\tassign ct[42]=l[3];\tassign ct[43]=r[11];\tassign ct[44]=l[11];\tassign ct[45]=r[19];\tassign ct[46]=l[19];\tassign ct[47]=r[27];\tassign ct[48]=l[27];
\tassign ct[49]=r[2];\tassign ct[50]=l[2];\tassign ct[51]=r[10];\tassign ct[52]=l[10];\tassign ct[53]=r[18];\tassign ct[54]=l[18];\tassign ct[55]=r[26];\tassign ct[56]=l[26];
\tassign ct[57]=r[1];\tassign ct[58]=l[1];\tassign ct[59]=r[9];\tassign ct[60]=l[9];\tassign ct[61]=r[17];\tassign ct[62]=l[17];\tassign ct[63]=r[25];\tassign ct[64]=l[25];
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casez/endcase w/ known labels - no default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
casez (val1 & val2 )
3\'b000: result = 0;
3\'b001: result = 1 ;
3\'b010: result = 2;
endcase
initial
begin
error = 0;
val1 = 3\'b0;
val2 = 3\'b0;
if(result !=0)
begin
$display("FAILED casez 3.10A - case (expr) lab1: ");
error = 1;
end
val1 = 3\'b001;
val2 = 3\'b011;
if(result !=1)
begin
$display("FAILED casez 3.10A - case (expr) lab2: ");
error = 1;
end
val1 = 3\'b111;\t// Should get no-action - expr = 3\'b011
if(result !=1)
begin
$display("FAILED casez 3.10A - case (expr) lab1: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
// Copyright (c) 2006 Stephen Williams
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
reg [7:0] mem [0:1];
initial begin
mem[0] = 0;
mem[1] = 1;
$memmonitor(mem);
#1 mem[0] = 4;
#1 mem[1] = 5;
#1 $finish(0);
end
endmodule // main
|
// Check that it is possible to specify a default port value for each port in a
// output port declaration list.
module M (
output [31:0] x = 1, y = 2
);
`define check(val, exp) \\
if (val !== exp) begin \\
$display("FAILED(%0d): %s, expected %0h got %0h", `__LINE__, `"val`", exp, val); \\
failed = 1\'b1; \\
end
reg failed = 1\'b0;
initial begin
`check(x, 1)
`check(y, 2)
if (!failed) begin
$display("PASSED");
end
end
endmodule
module test;
M i_m ();
endmodule
|
module test();
wire [3:0] IN;
wire [3:0] OUT;
assign OUT = IN;
initial begin
#1 $peek(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $force(IN[2:1]);
#1 $peek(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $release(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $force(IN[2:1]);
#1 $peek(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $poke(IN[2:1]);
#1 $peek(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $release(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $poke(IN[2:1]);
#1 $peek(IN[2:1]);
#0 $display("display :%b", OUT);
end
endmodule
|
// (c) [email protected] - 2002, Quantum Magnetics Inc, San Diego CA
// This source file is licensed under the GNU public license version 2.0
// All other rights reserved.
// NOTE: This test catches addition of wide (>16 bits) constants
// to wide vectors. -- Steve Williams
module source ( C, h );
output [ 0:0] C;
output [11:0] h;
reg [ 0:0] C;
reg [11:0] h;
reg [21:0] l;
parameter kh = 3;
parameter kl = 21\'d364066;
parameter wl = 21\'h100000;
initial #5
\tbegin
\tC <= 0;
\tl <= 0;
\th <= 0;
\tend
always #10 C = ~C;
always @(posedge C)
begin\tif ( l >= wl )
\tbegin\tl <= l + kl - wl;
\t\th <= h + kh + 1;
\tend else
\tbegin\tl <= l + kl;
\t\th <= h + kh;
\tend
end
endmodule
module bench;
wire [ 0:0] clock;
wire [11:0] h;
source dut ( .C(clock), .h(h) );
initial #85
\tbegin
\tif ( h == 13 ) begin
\t\t$display ( "%7d", h );
\t\t$display ("PASSED");
\tend else begin
\t\t$display ( "%7d = FAIL", h );
\tend
\t$finish;
\tend
endmodule
|
// Tests that it possible to omit the initial `parameter` keyword in a parameter
// port list in SystemVerilog. In Verilog this is not allowed and should result
// in an error.
module a #(integer A = 1);
initial begin
if (A == 10) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
module test;
a #(.A(10.1)) i_a();
endmodule
|
module test;
// This example was adapted from:
// DRAFT STANDARD VERILOG HARDWARE DESCRIPTION LANGUAGE
// IEEE P1364-2005/D3, 1/7/04
// Section 4.4.2 "An example of an expression bit-length problem"
// pg. 59
reg [15:0] a, b, answer; // 16-bit regs
initial
begin
a = 16\'h8000;
b = 16\'h8000;
answer = (a + b + 0) >> 1; //will work correctly
if ( answer != 16\'h8000 )
begin
$display("FAILED -- expected 16\'h8000 received 16\'h%h", answer);
$finish;
end
$display("PASSED");
end
endmodule
|
module top;
parameter le0 = 1\'b0 <-> 1\'b0; // 1\'b1
parameter le1 = 1\'b0 <-> 1\'b1; // 1\'b0
parameter le2 = 1\'b0 <-> 1\'bz; // 1\'bx
parameter le3 = 1\'b0 <-> 1\'bx; // 1\'bx
parameter le4 = 1\'b1 <-> 1\'b0; // 1\'b0
parameter le5 = 1\'b1 <-> 1\'b1; // 1\'b1
parameter le6 = 1\'b1 <-> 1\'bz; // 1\'bx
parameter le7 = 1\'b1 <-> 1\'bx; // 1\'bx
parameter le8 = 1\'bz <-> 1\'b0; // 1\'bx
parameter le9 = 1\'bz <-> 1\'b1; // 1\'bx
parameter lea = 1\'bz <-> 1\'bz; // 1\'bx
parameter leb = 1\'bz <-> 1\'bx; // 1\'bx
parameter lec = 1\'bx <-> 1\'b0; // 1\'bx
parameter led = 1\'bx <-> 1\'b1; // 1\'bx
parameter lee = 1\'bx <-> 1\'bz; // 1\'bx
parameter lef = 1\'bx <-> 1\'bx; // 1\'bx
parameter [1:0] lew = 4\'b0110 <-> 4\'b1001; // 2\'b01
parameter [1:0] lews = $signed(4\'b0110 <-> 4\'b1001); // 2\'b11
parameter ler0 = 0.0 <-> 1\'b0; // 1\'b1
parameter ler1 = 1\'b0 <-> 2.0; // 1\'b0
parameter ler2 = 2.0 <-> 1\'bx; // 1\'bx
parameter ler3 = -5.0 <-> 2.0; // 1\'b1
reg pass;
initial begin
pass = 1\'b1;
if (le0 !== 1\'b1) begin
$display("FAILED: 1\'b0 <-> 1\'b0 returned %b not 1\'b1", le0);
pass = 1\'b0;
end
if (le1 !== 1\'b0) begin
$display("FAILED: 1\'b0 <-> 1\'b1 returned %b not 1\'b0", le1);
pass = 1\'b0;
end
if (le2 !== 1\'bx) begin
$display("FAILED: 1\'b0 <-> 1\'bz returned %b not 1\'bx", le2);
pass = 1\'b0;
end
if (le3 !== 1\'bx) begin
$display("FAILED: 1\'b0 <-> 1\'bx returned %b not 1\'bx", le3);
pass = 1\'b0;
end
if (le4 !== 1\'b0) begin
$display("FAILED: 1\'b1 <-> 1\'b0 returned %b not 1\'b0", le4);
pass = 1\'b0;
end
if (le5 !== 1\'b1) begin
$display("FAILED: 1\'b1 <-> 1\'b1 returned %b not 1\'b1", le5);
pass = 1\'b0;
end
if (le6 !== 1\'bx) begin
$display("FAILED: 1\'b1 <-> 1\'bz returned %b not 1\'bx", le6);
pass = 1\'b0;
end
if (le7 !== 1\'bx) begin
$display("FAILED: 1\'b1 <-> 1\'bx returned %b not 1\'bx", le7);
pass = 1\'b0;
end
if (le8 !== 1\'bx) begin
$display("FAILED: 1\'bz <-> 1\'b0 returned %b not 1\'bx", le8);
pass = 1\'b0;
end
if (le9 !== 1\'bx) begin
$display("FAILED: 1\'bz <-> 1\'b1 returned %b not 1\'bx", le9);
pass = 1\'b0;
end
if (lea !== 1\'bx) begin
$display("FAILED: 1\'bz <-> 1\'bz returned %b not 1\'bx", lea);
pass = 1\'b0;
end
if (leb !== 1\'bx) begin
$display("FAILED: 1\'bz <-> 1\'bx returned %b not 1\'bx", leb);
pass = 1\'b0;
end
if (lec !== 1\'bx) begin
$display("FAILED: 1\'bx <-> 1\'b0 returned %b not 1\'bx", lec);
pass = 1\'b0;
end
if (led !== 1\'bx) begin
$display("FAILED: 1\'bx <-> 1\'b0 returned %b not 1\'bx", led);
pass = 1\'b0;
end
if (lee !== 1\'bx) begin
$display("FAILED: 1\'bx <-> 1\'bz returned %b not 1\'bx", lee);
pass = 1\'b0;
end
if (lef !== 1\'bx) begin
$display("FAILED: 1\'bx <-> 1\'bx returned %b not 1\'bx", lef);
pass = 1\'b0;
end
if (ler0 !== 1\'b1) begin
$display("FAILED: 0.0 <-> 1\'b0 returned %b not 1\'b1", ler0);
pass = 1\'b0;
end
if (ler1 !== 1\'b0) begin
$display("FAILED: 1\'b0 <-> 2.0 returned %b not 1\'b1", ler1);
pass = 1\'b0;
end
if (ler2 !== 1\'bx) begin
$display("FAILED: 2.0 <-> 1\'bx returned %b not 1\'b1", ler2);
pass = 1\'b0;
end
if (ler3 !== 1\'b1) begin
$display("FAILED: -5.0 <-> 2.0 returned %b not 1\'b1", ler3);
pass = 1\'b0;
end
if (lew !== 2\'b01) begin
$display("FAILED: 4\'b0110 <-> 4\'b1001 returned %b not 2\'b01", lew);
pass = 1\'b0;
end
if (lews !== 2\'b11) begin
$display("FAILED: 4\'b0110 <-> 4\'b1001 returned %b not 2\'b11", lews);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Check Verilog types on a module input port. In Verilog this is an error, but
// in SystemVerilog it is supported
module test (
input reg a,
input time b,
input integer c
);
initial begin
$display("PASSED");
end
endmodule
|
// Test case statements inside a constant function
module constfunc12();
function [1:0] onehot_to_binary(input [3:1] x);
case (x)
default : onehot_to_binary = 0;
3\'b001 : onehot_to_binary = 1;
3\'b010 : onehot_to_binary = 2;
3\'b100 : onehot_to_binary = 3;
endcase
endfunction
function [1:0] find_first_one(input [3:1] x);
casez (x)
3\'b1?? : find_first_one = 3;
3\'b01? : find_first_one = 2;
3\'b001 : find_first_one = 1;
default : find_first_one = 0;
endcase
endfunction
function [1:0] find_first_zero(input [3:1] x);
casex (x)
3\'b0zz : find_first_zero = 3;
3\'b10x : find_first_zero = 2;
3\'b110 : find_first_zero = 1;
default : find_first_zero = 0;
endcase
endfunction
function [1:0] match_real_value(input real x);
case (x)
1.0 : match_real_value = 1;
2.0 : match_real_value = 2;
3.0 : match_real_value = 3;
default : match_real_value = 0;
endcase
endfunction
localparam otb0 = onehot_to_binary(3\'b000);
localparam otb1 = onehot_to_binary(3\'b001);
localparam otb2 = onehot_to_binary(3\'b010);
localparam otb3 = onehot_to_binary(3\'b100);
localparam otb4 = onehot_to_binary(3\'b101);
localparam otb5 = onehot_to_binary(3\'b10z);
localparam otb6 = onehot_to_binary(3\'bx01);
localparam ffo0 = find_first_one(3\'b000);
localparam ffo1 = find_first_one(3\'b001);
localparam ffo2 = find_first_one(3\'b01x);
localparam ffo3 = find_first_one(3\'b1xx);
localparam ffo4 = find_first_one(3\'bxx1);
localparam ffo5 = find_first_one(3\'b00z);
localparam ffo6 = find_first_one(3\'b0zz);
localparam ffo7 = find_first_one(3\'bzzz);
localparam ffz0 = find_first_zero(3\'b111);
localparam ffz1 = find_first_zero(3\'b110);
localparam ffz2 = find_first_zero(3\'b10x);
localparam ffz3 = find_first_zero(3\'b0xx);
localparam ffz4 = find_first_zero(3\'bzzz);
localparam ffz5 = find_first_zero(3\'b11x);
localparam ffz6 = find_first_zero(3\'b1xx);
localparam ffz7 = find_first_zero(3\'bxxx);
localparam mrv0 = match_real_value(0.0);
localparam mrv1 = match_real_value(1.0);
localparam mrv2 = match_real_value(2.0);
localparam mrv3 = match_real_value(3.0);
localparam mrv4 = match_real_value(4.0);
reg failed = 0;
initial begin
$display("%d", otb0); if (otb0 !== 2\'d0) failed = 1;
$display("%d", otb1); if (otb1 !== 2\'d1) failed = 1;
$display("%d", otb2); if (otb2 !== 2\'d2) failed = 1;
$display("%d", otb3); if (otb3 !== 2\'d3) failed = 1;
$display("%d", otb4); if (otb4 !== 2\'d0) failed = 1;
$display("%d", otb5); if (otb5 !== 2\'d0) failed = 1;
$display("%d", otb6); if (otb6 !== 2\'d0) failed = 1;
$display("");
$display("%d", ffo0); if (ffo0 !== 2\'d0) failed = 1;
$display("%d", ffo1); if (ffo1 !== 2\'d1) failed = 1;
$display("%d", ffo2); if (ffo2 !== 2\'d2) failed = 1;
$display("%d", ffo3); if (ffo3 !== 2\'d3) failed = 1;
$display("%d", ffo4); if (ffo4 !== 2\'d0) failed = 1;
$display("%d", ffo5); if (ffo5 !== 2\'d1) failed = 1;
$display("%d", ffo6); if (ffo6 !== 2\'d2) failed = 1;
$display("%d", ffo7); if (ffo7 !== 2\'d3) failed = 1;
$display("");
$display("%d", ffz0); if (ffz0 !== 2\'d0) failed = 1;
$display("%d", ffz1); if (ffz1 !== 2\'d1) failed = 1;
$display("%d", ffz2); if (ffz2 !== 2\'d2) failed = 1;
$display("%d", ffz3); if (ffz3 !== 2\'d3) failed = 1;
$display("%d", ffz4); if (ffz4 !== 2\'d3) failed = 1;
$display("%d", ffz5); if (ffz5 !== 2\'d1) failed = 1;
$display("%d", ffz6); if (ffz6 !== 2\'d2) failed = 1;
$display("%d", ffz7); if (ffz7 !== 2\'d3) failed = 1;
$display("");
$display("%d", mrv0); if (mrv0 !== 2\'d0) failed = 1;
$display("%d", mrv1); if (mrv1 !== 2\'d1) failed = 1;
$display("%d", mrv2); if (mrv2 !== 2\'d2) failed = 1;
$display("%d", mrv3); if (mrv3 !== 2\'d3) failed = 1;
$display("%d", mrv4); if (mrv4 !== 2\'d0) failed = 1;
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
`begin_keywords "1364-2005"
module top;
reg pass = 1\'b1;
reg clk = 0;
reg [7:0] result;
reg [3:0] bit;
always #10 clk = ~clk;
initial begin
// Since the bit is not defined this assignment will not happen.
// We will check to verify this fact 1 time step after it should
// happen (50).
result[bit] <= repeat(3) @(posedge clk) 1\'b0;
if ($simtime != 0 || result !== 8\'bx) begin
$display("Failed repeat(3) blocked at %0t, expected 8\'hxx, got %h",
$simtime, result);
pass = 1\'b0;
end
#51;
if (result !== 8\'hxx) begin
$display("Failed repeat(3) at %0t, expected 8\'hxx, got %h",
$simtime, result);
pass = 1\'b0;
end
bit = 0;
result[bit] <= @(posedge clk) 4\'h0;
@(result)
if ($simtime != 70 || result !== 8\'bxxxxxxx0) begin
$display("Failed repeat(3) at %0t, expected 8\'bxxxxxxx0, got %h",
$simtime, result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
$finish;
end
endmodule
`end_keywords
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
//
module main ();
reg [7:0] array [7:0];
reg\t error ;
reg [3:0] count;
initial
begin
\tfor(count = 0; count <= 7; count = count + 1)
\t begin
\t array[count] = 1 << count;
\t end
\t$writememh("work/writememh2.dat", array, 6, 1);
\tfor(count = 0; count <= 7; count = count + 1)
\t begin
\t array[count] = \'bx;
\t end
\terror = 0;
\t$readmemh("work/writememh2.dat", array);
\tfor(count = 0; count <= 5; count = count + 1)
\t begin
\t if(array[count] !== (1<<(6-count)))
begin
\t\t error = 1;
\t\t $display("FAILED - array[count] == %h, s/b %h",
\t\t\t array[count], 1 << count);
end
\t end
\tif(error == 0)
\t $display("PASSED\
");
\t$finish ;
end
endmodule
|
module test;
initial begin
\t$display("Error: \\"FloatTest.bsv\\", line 234, column 24: (R0001)\
Mutually exclusive rules (from the ME sets [RL_action_l234c24] and\
[RL_action_l235c24, RL_action_l236c24, RL_action_l237c24, RL_action_l238c24,\
RL_action_l239c24, RL_action_l240c24, RL_action_l241c24, RL_action_l242c24,\
RL_action_l243c24, RL_action_l244c24, RL_action_l245c24, RL_action_l246c24,\
RL_action_l247c24, RL_action_l248c24, RL_action_l249c24, RL_action_l250c24,\
RL_action_l251c24, RL_action_l252c24, RL_action_l253c24, RL_action_l255c24,\
RL_action_l256c24, RL_action_l257c24, RL_action_l258c24, RL_action_l259c24,\
RL_action_l260c24, RL_action_l261c24, RL_action_l262c24, RL_action_l263c24,\
RL_action_l264c24, RL_action_l265c24, RL_action_l266c24, RL_action_l267c24,\
RL_action_l268c24, RL_action_l269c24, RL_action_l270c24, RL_action_l271c24,\
RL_action_l272c24, RL_action_l273c24, RL_action_l274c24, RL_action_l276c24,\
RL_action_l277c24, RL_action_l278c24, RL_action_l279c24, RL_action_l280c24,\
RL_action_l281c24, RL_action_l282c24, RL_action_l283c24, RL_action_l284c24,\
RL_action_l285c24, RL_action_l286c24, RL_action_l287c24, RL_action_l288c24,\
RL_action_l289c24, RL_action_l290c24, RL_action_l291c24, RL_action_l292c24,\
RL_action_l293c24, RL_action_l294c24, RL_action_l295c24, RL_action_l297c24,\
RL_action_l298c24, RL_action_l299c24, RL_action_l300c24, RL_action_l301c24,\
RL_action_l302c24, RL_action_l303c24, RL_action_l304c24, RL_action_l305c24,\
RL_action_l306c24, RL_action_l307c24, RL_action_l308c24, RL_action_l309c24,\
RL_action_l310c24, RL_action_l311c24, RL_action_l312c24, RL_action_l313c24,\
RL_action_l314c24, RL_action_l315c24, RL_action_l316c24, RL_action_l318c24,\
RL_action_l319c24, RL_action_l320c24, RL_action_l321c24, RL_action_l322c24,\
RL_action_l323c24, RL_action_l324c24, RL_action_l326c24, RL_action_l327c24,\
RL_action_l328c24, RL_action_l329c24, RL_action_l330c24, RL_action_l331c24,\
RL_action_l332c24, RL_action_l333c24, RL_action_l334c24, RL_action_l335c24,\
RL_action_l336c24, RL_action_l337c24, RL_action_l338c24, RL_action_l339c24,\
RL_action_l340c24, RL_action_l341c24, RL_action_l342c24, RL_action_l343c24,\
RL_action_l344c24, RL_action_l345c24, RL_action_l348c18, RL_action_l353c22,\
RL_action_l354c22, RL_action_l355c22, RL_action_l356c22, RL_action_l357c22,\
RL_action_l358c22, RL_action_l359c22, RL_action_l360c22, RL_action_l361c22,\
RL_action_l362c22, RL_action_l363c22, RL_action_l364c22, RL_action_l365c22,\
RL_action_l366c22, RL_action_l367c22, RL_action_l368c22, RL_action_l369c22,\
RL_action_l370c22, RL_action_l371c22, RL_action_l372c22, RL_action_l374c22,\
RL_action_l376c22, RL_action_l377c22, RL_action_l378c22, RL_action_l379c22,\
RL_action_l381c22, RL_action_l383c22, RL_action_l384c22, RL_action_l386c22,\
RL_action_l387c22, RL_action_l390c18, RL_action_l395c23, RL_action_l396c23,\
RL_action_l398c23, RL_action_l399c23, RL_action_l400c23, RL_action_l401c23,\
RL_action_l402c23, RL_action_l403c23, RL_action_l404c23, RL_action_l405c23,\
RL_action_l406c23, RL_action_l407c23, RL_action_l408c23, RL_action_l409c23,\
RL_action_l410c23, RL_action_l411c23, RL_action_l412c23, RL_action_l413c23,\
RL_action_l414c23, RL_action_l415c23, RL_action_l416c23, RL_action_l417c23,\
RL_action_l419c23, RL_action_l420c23, RL_action_l421c23, RL_action_l422c23,\
RL_action_l423c23, RL_action_l424c23, RL_action_l425c23, RL_action_l426c23,\
RL_action_l427c23, RL_action_l428c23, RL_action_l429c23, RL_action_l430c23,\
RL_action_l431c23, RL_action_l432c23, RL_action_l433c23, RL_action_l434c23,\
RL_action_l435c23, RL_action_l436c23, RL_action_l437c23, RL_action_l438c23,\
RL_action_l441c18, RL_action_l446c28, RL_action_l447c28, RL_action_l448c28,\
RL_action_l449c28, RL_action_l450c28, RL_action_l451c28, RL_action_l452c28,\
RL_action_l453c28, RL_action_l455c28, RL_action_l456c28, RL_action_l457c28,\
RL_action_l458c28, RL_action_l459c28, RL_action_l460c28, RL_action_l461c28,\
RL_action_l462c28, RL_action_l463c28, RL_action_l464c28, RL_action_l465c28,\
RL_action_l466c28, RL_action_l467c28, RL_action_l468c28, RL_action_l469c28,\
RL_action_l470c28, RL_action_l471c28, RL_action_l472c28, RL_action_l473c28,\
RL_action_l474c28, RL_action_l475c28, RL_action_l476c28, RL_action_l478c28,\
RL_action_l479c28, RL_action_l481c28, RL_action_l484c18, RL_action_l489c21,\
RL_action_l490c21, RL_action_l491c21, RL_action_l492c21, RL_action_l493c21,\
RL_action_l494c21, RL_action_l495c21, RL_action_l496c21, RL_action_l497c21,\
RL_action_l498c21, RL_action_l499c21, RL_action_l500c21, RL_action_l501c21,\
RL_action_l502c21, RL_action_l503c21, RL_action_l504c21, RL_action_l505c21,\
RL_action_l506c21, RL_action_l507c21, RL_action_l508c21, RL_action_l509c21,\
RL_action_l510c21, RL_action_l512c21, RL_action_l513c21, RL_action_l514c21,\
RL_action_l515c21, RL_action_l516c21, RL_action_l517c21, RL_action_l518c21,\
RL_action_l519c21, RL_action_l520c21, RL_action_l521c21, RL_action_l522c21,\
RL_action_l523c21, RL_action_l524c21, RL_action_l525c21, RL_action_l526c21,\
RL_action_l527c21, RL_action_l528c21, RL_action_l529c21, RL_action_l530c21,\
RL_action_l531c21, RL_action_l533c26, RL_action_l534c26, RL_action_l535c26,\
RL_action_l536c26, RL_action_l537c26, RL_action_l538c26, RL_action_l539c26,\
RL_action_l540c26, RL_action_l542c26, RL_action_l543c26, RL_action_l544c26,\
RL_action_l545c26, RL_action_l546c26, RL_action_l547c26, RL_action_l548c26,\
RL_action_l549c26, RL_action_l550c26, RL_action_l551c26, RL_action_l552c26,\
RL_action_l553c26, RL_action_l554c26, RL_action_l555c26, RL_action_l556c26,\
RL_action_l557c26, RL_action_l558c26, RL_action_l559c26, RL_action_l560c26,\
RL_action_l561c26, RL_action_l562c26, RL_action_l563c26, RL_action_l565c26,\
RL_action_l566c26, RL_action_l568c26, RL_action_l570c21, RL_action_l572c21,\
RL_action_l574c26, RL_action_l576c26, RL_action_l577c26, RL_action_l579c26,\
RL_action_l582c18, RL_action_l587c28, RL_action_l588c28, RL_action_l589c28,\
RL_action_l590c28, RL_action_l591c28, RL_action_l592c28, RL_action_l593c28,\
RL_action_l594c28, RL_action_l595c28, RL_action_l596c28, RL_action_l597c28,\
RL_action_l598c28, RL_action_l599c28, RL_action_l600c28, RL_action_l601c28,\
RL_action_l602c28, RL_action_l603c28, RL_action_l604c28, RL_action_l605c28,\
RL_action_l606c28, RL_action_l607c28, RL_action_l609c28, RL_action_l610c28,\
RL_action_l611c28, RL_action_l613c28, RL_action_l614c28, RL_action_l615c28,\
RL_action_l616c28, RL_action_l617c28, RL_action_l618c28, RL_action_l619c28,\
RL_action_l621c28, RL_action_l622c28, RL_action_l623c28, RL_action_l624c28,\
RL_action_l625c28, RL_action_l626c28, RL_action_l627c28, RL_action_l628c28,\
RL_action_l629c28, RL_action_l630c28, RL_action_l631c28, RL_action_l632c28,\
RL_action_l633c28, RL_action_l634c28, RL_action_l635c28, RL_action_l636c28,\
RL_action_l637c28, RL_action_l638c28, RL_action_l639c28, RL_action_l645c18,\
RL_action_l647c7] ) fired in the same clock cycle.\
PASSED");
end
endmodule
|
/*
* This is the crux of PR487.
*/
module test();
parameter[1:4] async_wrport = 4\'b1100;
reg async_wri;
reg[1:4] async_i;
initial begin
for(async_i=1;async_i<=4;async_i=async_i+1) begin
async_wri=async_wrport[async_i];
$display("async_wrport[%d] --> %b", async_i, async_wri);
end
end
endmodule
|
/*
* Verilog-A math library test code for Icarus Verilog.
* http://www.icarus.com/eda/verilog/
*
* Copyright (C) 2007-2009 Cary R. ([email protected])
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
/*
* As of Dec. 2009 some systems have started returning the sign of
* a NaN, because of this we can for some conditions get -nan. This
* will cause mismatches with the gold file. Alan M. Feldstein
* suggested on the iverilog-devel mailing list that we use fabs
* ($abs()) since C99 speifies that it will remove the sign of the
* NaN. This appears to work, so I wrapped all functions that we
* expect to return NaN with a call to $abs().
*/
// Get the Verilog-A constants.
`include "constants.vams"
module top;
real zero, mzero, inf, minf, nan;
initial begin
// Define a few constants.
zero = 0.0;
mzero = -1.0 * zero;
inf = 1/0.0;
minf = $ln(0);
nan = $abs($sqrt(-1.0));
$display("Using +0 = %f, -0 = %f, nan = %f, inf = %f and -inf = %f.\
",
zero, mzero, nan, inf, minf);
// Check that the comparisons used to detection a NaN work correctly.
if (nan != nan) $display("NaN != comparison works correctly.");
else $display("NaN != comparison failed.");
if (nan == nan) $display("NaN == comparison failed.\
");
else $display("NaN == comparison works correctly.\
");
check_sqrt;
$display("");
check_ln;
$display("");
check_log;
$display("");
check_exp;
$display("");
check_abs;
$display("");
check_ceil;
$display("");
check_floor;
$display("");
check_sin;
$display("");
check_cos;
$display("");
check_tan;
$display("");
check_asin;
$display("");
check_acos;
$display("");
check_atan;
$display("");
check_sinh;
$display("");
check_cosh;
$display("");
check_tanh;
$display("");
check_asinh;
$display("");
check_acosh;
$display("");
check_atanh;
$display("");
check_min;
$display("");
check_max;
$display("");
check_pow;
$display("");
check_atan2;
$display("");
check_hypot;
$display("");
check_constants;
end
// Task to check the square root function.
task check_sqrt;
begin
$display("--- Checking the $sqrt function ---");
$display("The square root of 2.0 is %f.", $sqrt(2.0));
$display("The square root of 1.0 is %f.", $sqrt(1.0));
$display("The square root of 0.0 is %f.", $sqrt(zero));
$display("The square root of -0.0 is %f.", $sqrt(mzero));
$display("The square root of -1.0 is %f.", $abs($sqrt(-1.0)));
$display("The square root of inf is %f.", $sqrt(inf));
$display("The square root of -inf is %f.", $abs($sqrt(minf)));
$display("The square root of nan is %f.", $abs($sqrt(nan)));
end
endtask
// Task to check the natural log function.
task check_ln;
begin
$display("--- Checking the $ln function ---");
$display("The natural log of 10.0 is %f.", $ln(10.0));
$display("The natural log of 1.0 is %f.", $ln(1.0));
$display("The natural log of 0.5 is %f.", $ln(0.5));
$display("The natural log of 0.0 is %f.", $ln(zero));
$display("The natural log of -0.0 is %f.", $ln(mzero));
$display("The natural log of -1.0 is %f.", $abs($ln(-1.0)));
$display("The natural log of inf is %f.", $ln(inf));
$display("The natural log of -inf is %f.", $abs($ln(minf)));
$display("The natural log of nan is %f.", $abs($ln(nan)));
end
endtask
// Task to check the log base 10 function.
// This was originally $log, but that was deprecated in VAMS-2.3.
task check_log;
begin
$display("--- Checking the $log10 function ---");
$display("The log base 10 of 10.0 is %f.", $log10(10.0));
$display("The log base 10 of 1.0 is %f.", $log10(1.0));
$display("The log base 10 of 0.5 is %f.", $log10(0.5));
$display("The log base 10 of 0.0 is %f.", $log10(zero));
$display("The log base 10 of -0.0 is %f.", $log10(mzero));
$display("The log base 10 of -1.0 is %f.", $abs($log10(-1.0)));
$display("The log base 10 of inf is %f.", $log10(inf));
$display("The log base 10 of -inf is %f.", $abs($log10(minf)));
$display("The log base 10 of nan is %f.", $abs($log10(nan)));
end
endtask
// Task to check the exponential function.
task check_exp;
begin
$display("--- Checking the $exp function ---");
$display("The exponential of 1.0 is %f.", $exp(1.0));
$display("The exponential of 0.0 is %f.", $exp(zero));
$display("The exponential of -0.0 is %f.", $exp(mzero));
$display("The exponential of -1.0 is %f.", $exp(-1.0));
$display("The exponential of inf is %f.", $exp(inf));
$display("The exponential of -inf is %f.", $exp(minf));
$display("The exponential of nan is %f.", $abs($exp(nan)));
end
endtask
// Task to check the absolute value function.
task check_abs;
begin
$display("--- Checking the $abs function ---");
$display("The absolute value of 1.0 is %f.", $abs(1.0));
$display("The absolute value of 0.0 is %f.", $abs(zero));
$display("The absolute value of -0.0 is %f.", $abs(mzero));
$display("The absolute value of -1.0 is %f.", $abs(-1.0));
$display("The absolute value of inf is %f.", $abs(inf));
$display("The absolute value of -inf is %f.", $abs(minf));
$display("The absolute value of nan is %f.", $abs(nan));
end
endtask
// Task to check the ceiling function.
task check_ceil;
begin
$display("--- Checking the $ceil function ---");
$display("The ceiling of 2.1 is %f.", $ceil(2.1));
$display("The ceiling of 0.5 is %f.", $ceil(0.5));
// Some C math libraries return -0.0 and some return 0.0.
// Both appear to be correct since the standard does not
// specify exactly what should be done so convert to 0.0.
$display("The ceiling of -0.5 is %f.", $ceil(-0.5)+0.0);
$display("The ceiling of -1.1 is %f.", $ceil(-1.1));
$display("The ceiling of inf is %f.", $ceil(inf));
$display("The ceiling of -inf is %f.", $ceil(minf));
$display("The ceiling of nan is %f.", $abs($ceil(nan)));
end
endtask
// Task to check the floor function.
task check_floor;
begin
$display("--- Checking the $floor function ---");
$display("The floor of 2.1 is %f.", $floor(2.1));
$display("The floor of 0.5 is %f.", $floor(0.5));
$display("The floor of -0.5 is %f.", $floor(-0.5));
$display("The floor of -1.1 is %f.", $floor(-1.1));
$display("The floor of inf is %f.", $floor(inf));
$display("The floor of -inf is %f.", $floor(minf));
$display("The floor of nan is %f.", $abs($floor(nan)));
end
endtask
// Task to check the sin function.
task check_sin;
begin
$display("--- Checking the $sin function ---");
$display("The sin of 4.0 is %f.", $sin(4.0));
$display("The sin of 1.0 is %f.", $sin(1.0));
$display("The sin of 0.0 is %f.", $sin(zero));
$display("The sin of -0.0 is %f.", $sin(mzero));
$display("The sin of -1.0 is %f.", $sin(-1.0));
$display("The sin of -4.0 is %f.", $sin(-4.0));
$display("The sin of inf is %f.", $abs($sin(inf)));
$display("The sin of -inf is %f.", $abs($sin(minf)));
$display("The sin of nan is %f.", $abs($sin(nan)));
end
endtask
// Task to check the cos function.
task check_cos;
begin
$display("--- Checking the $cos function ---");
$display("The cos of 4.0 is %f.", $cos(4.0));
$display("The cos of 1.0 is %f.", $cos(1.0));
$display("The cos of 0.0 is %f.", $cos(zero));
$display("The cos of -0.0 is %f.", $cos(mzero));
$display("The cos of -1.0 is %f.", $cos(-1.0));
$display("The cos of -4.0 is %f.", $cos(-4.0));
$display("The cos of inf is %f.", $abs($cos(inf)));
$display("The cos of -inf is %f.", $abs($cos(minf)));
$display("The cos of nan is %f.", $abs($cos(nan)));
end
endtask
// Task to check the tan function.
task check_tan;
begin
$display("--- Checking the $tan function ---");
$display("The tan of 4.0 is %f.", $tan(4.0));
$display("The tan of 1.0 is %f.", $tan(1.0));
$display("The tan of 0.0 is %f.", $tan(zero));
$display("The tan of -0.0 is %f.", $tan(mzero));
$display("The tan of -1.0 is %f.", $tan(-1.0));
$display("The tan of -4.0 is %f.", $tan(-4.0));
// The underlying C math libraries can give different results for
// this corner case, so we can only use four significant digits
// for these two tests.
$display("The tan of pi/2 is %.4g.", $tan($asin(1.0)));
$display("The tan of -pi/2 is %.4g.", $tan($asin(-1.0)));
$display("The tan of inf is %f.", $abs($tan(inf)));
$display("The tan of -inf is %f.", $abs($tan(minf)));
$display("The tan of nan is %f.", $abs($tan(nan)));
end
endtask
// Task to check the asin function.
task check_asin;
begin
$display("--- Checking the $asin function ---");
$display("The asin of 1.1 is %f.", $abs($asin(1.1)));
$display("The asin of 1.0 is %f.", $asin(1.0));
$display("The asin of 0.5 is %f.", $asin(0.5));
$display("The asin of 0.0 is %f.", $asin(zero));
$display("The asin of -0.0 is %f.", $asin(mzero));
$display("The asin of -0.5 is %f.", $asin(-0.5));
$display("The asin of -1.0 is %f.", $asin(-1.0));
$display("The asin of -1.1 is %f.", $abs($asin(-1.1)));
$display("The asin of inf is %f.", $abs($asin(inf)));
$display("The asin of -inf is %f.", $abs($asin(minf)));
$display("The asin of nan is %f.", $abs($asin(nan)));
end
endtask
// Task to check the acos function.
task check_acos;
begin
$display("--- Checking the $acos function ---");
$display("The acos of 1.1 is %f.", $abs($acos(1.1)));
$display("The acos of 1.0 is %f.", $acos(1.0));
$display("The acos of 0.5 is %f.", $acos(0.5));
$display("The acos of 0.0 is %f.", $acos(zero));
$display("The acos of -0.0 is %f.", $acos(mzero));
$display("The acos of -0.5 is %f.", $acos(-0.5));
$display("The acos of -1.0 is %f.", $acos(-1.0));
$display("The acos of -1.1 is %f.", $abs($acos(-1.1)));
$display("The acos of inf is %f.", $abs($acos(inf)));
$display("The acos of -inf is %f.", $abs($acos(minf)));
$display("The acos of nan is %f.", $abs($acos(nan)));
end
endtask
// Task to check the atan function.
task check_atan;
begin
$display("--- Checking the $atan function ---");
$display("The atan of 2.0 is %f.", $atan(2.0));
$display("The atan of 0.5 is %f.", $atan(0.5));
$display("The atan of 0.0 is %f.", $atan(zero));
$display("The atan of -0.0 is %f.", $atan(mzero));
$display("The atan of -0.5 is %f.", $atan(-0.5));
$display("The atan of -2.0 is %f.", $atan(-2.0));
$display("The atan of inf is %f.", $atan(inf));
$display("The atan of -inf is %f.", $atan(minf));
$display("The atan of nan is %f.", $abs($atan(nan)));
end
endtask
// Task to check the sinh function.
task check_sinh;
begin
$display("--- Checking the $sinh function ---");
$display("The sinh of 2.0 is %f.", $sinh(2.0));
$display("The sinh of 1.0 is %f.", $sinh(1.0));
$display("The sinh of 0.5 is %f.", $sinh(0.5));
$display("The sinh of 0.0 is %f.", $sinh(zero));
$display("The sinh of -0.0 is %f.", $sinh(mzero));
$display("The sinh of -0.5 is %f.", $sinh(-0.5));
$display("The sinh of -1.0 is %f.", $sinh(-1.0));
$display("The sinh of -2.0 is %f.", $sinh(-2.0));
$display("The sinh of inf is %f.", $sinh(inf));
$display("The sinh of -inf is %f.", $sinh(minf));
$display("The sinh of nan is %f.", $abs($sinh(nan)));
end
endtask
// Task to check the cosh function.
task check_cosh;
begin
$display("--- Checking the $cosh function ---");
$display("The cosh of 2.0 is %f.", $cosh(2.0));
$display("The cosh of 1.0 is %f.", $cosh(1.0));
$display("The cosh of 0.5 is %f.", $cosh(0.5));
$display("The cosh of 0.0 is %f.", $cosh(zero));
$display("The cosh of -0.0 is %f.", $cosh(mzero));
$display("The cosh of -0.5 is %f.", $cosh(-0.5));
$display("The cosh of -1.0 is %f.", $cosh(-1.0));
$display("The cosh of -2.0 is %f.", $cosh(-2.0));
$display("The cosh of inf is %f.", $cosh(inf));
$display("The cosh of -inf is %f.", $cosh(minf));
$display("The cosh of nan is %f.", $abs($cosh(nan)));
end
endtask
// Task to check the tanh function.
task check_tanh;
begin
$display("--- Checking the $tanh function ---");
$display("The tanh of 2.0 is %f.", $tanh(2.0));
$display("The tanh of 1.0 is %f.", $tanh(1.0));
$display("The tanh of 0.5 is %f.", $tanh(0.5));
$display("The tanh of 0.0 is %f.", $tanh(zero));
$display("The tanh of -0.0 is %f.", $tanh(mzero));
$display("The tanh of -0.5 is %f.", $tanh(-0.5));
$display("The tanh of -1.0 is %f.", $tanh(-1.0));
$display("The tanh of -2.0 is %f.", $tanh(-2.0));
$display("The tanh of inf is %f.", $tanh(inf));
$display("The tanh of -inf is %f.", $tanh(minf));
$display("The tanh of nan is %f.", $abs($tanh(nan)));
end
endtask
// Task to check the asinh function.
task check_asinh;
begin
$display("--- Checking the $asinh function ---");
$display("The asinh of 2.0 is %f.", $asinh(2.0));
$display("The asinh of 1.0 is %f.", $asinh(1.0));
$display("The asinh of 0.5 is %f.", $asinh(0.5));
$display("The asinh of 0.0 is %f.", $asinh(zero));
$display("The asinh of -0.0 is %f.", $asinh(mzero));
$display("The asinh of -0.5 is %f.", $asinh(-0.5));
$display("The asinh of -1.0 is %f.", $asinh(-1.0));
$display("The asinh of -2.0 is %f.", $asinh(-2.0));
$display("The asinh of inf is %f.", $asinh(inf));
$display("The asinh of -inf is %f.", $asinh(minf));
$display("The asinh of nan is %f.", $abs($asinh(nan)));
end
endtask
// Task to check the acosh function.
task check_acosh;
begin
$display("--- Checking the $acosh function ---");
$display("The acosh of 2.0 is %f.", $acosh(2.0));
$display("The acosh of 1.0 is %f.", $acosh(1.0));
$display("The acosh of 0.5 is %f.", $abs($acosh(0.5)));
$display("The acosh of 0 is %f.", $abs($acosh(zero)));
$display("The acosh of -0 is %f.", $abs($acosh(mzero)));
$display("The acosh of -0.5 is %f.", $abs($acosh(-0.5)));
$display("The acosh of -1.0 is %f.", $abs($acosh(-1.0)));
$display("The acosh of -2.0 is %f.", $abs($acosh(-2.0)));
$display("The acosh of inf is %f.", $acosh(inf));
$display("The acosh of -inf is %f.", $abs($acosh(minf)));
$display("The acosh of nan is %f.", $abs($acosh(nan)));
end
endtask
// Task to check the atanh function.
task check_atanh;
begin
$display("--- Checking the $atanh function ---");
$display("The atanh of 2.0 is %f.", $abs($atanh(2.0)));
$display("The atanh of 1.0 is %f.", $atanh(1.0));
$display("The atanh of 0.5 is %f.", $atanh(0.5));
$display("The atanh of 0.0 is %f.", $atanh(zero));
$display("The atanh of -0.0 is %f.", $atanh(mzero));
$display("The atanh of -0.5 is %f.", $atanh(-0.5));
$display("The atanh of -1.0 is %f.", $atanh(-1.0));
$display("The atanh of -2.0 is %f.", $abs($atanh(-2.0)));
$display("The atanh of inf is %f.", $abs($atanh(inf)));
$display("The atanh of -inf is %f.", $abs($atanh(minf)));
$display("The atanh of nan is %f.", $abs($atanh(nan)));
end
endtask
// Task to check the min function.
task check_min;
begin
$display("--- Checking the $min function ---");
$display("The minimum of 1.0 and 2.0 is %f.", $min(1.0, 2.0));
$display("The minimum of 2.0 and 1.0 is %f.", $min(2.0, 1.0));
$display("The minimum of 1.0 and -1.0 is %f.", $min(1.0, -1.0));
$display("The minimum of -1.0 and -2.0 is %f.", $min(-1.0, -2.0));
$display("The minimum of 2.0 and inf is %f.", $min(2.0, inf));
$display("The minimum of inf and 2.0 is %f.", $min(inf, 2.0));
$display("The minimum of 2.0 and -inf is %f.", $min(2.0, minf));
$display("The minimum of -inf and 2.0 is %f.", $min(minf, 2.0));
$display("The minimum of 2.0 and nan is %f.", $min(2.0, nan));
$display("The minimum of nan and 2.0 is %f.", $min(nan, 2.0));
end
endtask
// Task to check the max function.
task check_max;
begin
$display("--- Checking the $max function ---");
$display("The maximum of 1.0 and 2.0 is %f.", $max(1.0, 2.0));
$display("The maximum of 2.0 and 1.0 is %f.", $max(2.0, 1.0));
$display("The maximum of 1.0 and -1.0 is %f.", $max(1.0, -1.0));
$display("The maximum of -1.0 and -2.0 is %f.", $max(-1.0, -2.0));
$display("The maximum of 2.0 and inf is %f.", $max(2.0, inf));
$display("The maximum of inf and 2.0 is %f.", $max(inf, 2.0));
$display("The maximum of 2.0 and -inf is %f.", $max(2.0, minf));
$display("The maximum of -inf and 2.0 is %f.", $max(minf, 2.0));
$display("The maximum of 2.0 and nan is %f.", $max(2.0, nan));
$display("The maximum of nan and 2.0 is %f.", $max(nan, 2.0));
end
endtask
// Task to check the power function.
task check_pow;
begin
$display("--- Checking the $pow function ---");
$display(" 0.0 to the power of 0.0 is %f.", $pow(zero, zero));
$display(" 1.0 to the power of 0.0 is %f.", $pow(1.0, zero));
$display("-1.0 to the power of 0.0 is %f.", $pow(-1.0, zero));
$display(" 0.0 to the power of 1.0 is %f.", $pow(zero, 1.0));
$display(" 1.0 to the power of 1.0 is %f.", $pow(1.0, 1.0));
$display("-1.0 to the power of 1.0 is %f.", $pow(-1.0, 1.0));
$display(" 8.0 to the power of 1/3 is %f.", $pow(8.0, 1.0/3.0));
$display(" 8.0 to the power of -1/3 is %f.", $pow(8.0, -1.0/3.0));
$display(" 2.0 to the power of 3.0 is %f.", $pow(2.0, 3.0));
$display(" 2.0 to the power of 5000 is %f.", $pow(2.0, 5000));
$display("-2.0 to the power of 5001 is %f.", $pow(-2.0, 5001));
$display(" 2.0 to the power of -5000 is %f.", $pow(2.0, -5000));
$display(" inf to the power of 0.0 is %f.", $pow(inf, zero));
$display("-inf to the power of 0.0 is %f.", $pow(minf, zero));
$display(" inf to the power of 1.0 is %f.", $pow(inf, 1.0));
$display("-inf to the power of 1.0 is %f.", $pow(minf, 1.0));
$display(" inf to the power of 2.0 is %f.", $pow(inf, 2.0));
$display("-inf to the power of 2.0 is %f.", $pow(minf, 2.0));
$display(" 1.0 to the power of inf is %f.", $pow(1.0, inf));
$display("-1.0 to the power of inf is %f.", $pow(-1.0, inf));
$display(" 0.5 to the power of inf is %f.", $pow(0.5, inf));
$display(" 2.0 to the power of inf is %f.", $pow(2.0, inf));
$display(" 1.0 to the power of -inf is %f.", $pow(1.0, minf));
$display("-1.0 to the power of -inf is %f.", $pow(-1.0, minf));
$display(" 0.5 to the power of -inf is %f.", $pow(0.5, minf));
$display(" 2.0 to the power of -inf is %f.", $pow(2.0, minf));
$display("-1.0 to the power of -1/3 is %f.", $abs($pow(-1.0, -1.0/3.0)));
$display(" 1.0 to the power of nan is %f.", $pow(1.0, nan));
$display(" nan to the power of 1.0 is %f.", $abs($pow(nan, 1.0)));
$display(" nan to the power of 0.0 is %f.", $pow(nan, zero));
$display(" nan to the power of nan is %f.", $abs($pow(nan, nan)));
end
endtask
// Task to check the atan of x/y function.
task check_atan2;
begin
$display("--- Checking the $atan2 function ---");
$display("The atan of 0.0/ 0.0 is %f.", $atan2(zero, zero));
$display("The atan of -0.0/ 0.0 is %f.", $atan2(mzero, zero));
$display("The atan of 0.0/-0.0 is %f.", $atan2(zero, mzero));
$display("The atan of -0.0/-0.0 is %f.", $atan2(mzero, mzero));
$display("The atan of 0.0/ 1.0 is %f.", $atan2(zero, 1.0));
$display("The atan of 1.0/ 0.0 is %f.", $atan2(1.0, zero));
$display("The atan of 1.0/ 1.0 is %f.", $atan2(1.0, 1.0));
$display("The atan of 0.0/-1.0 is %f.", $atan2(zero, -1.0));
$display("The atan of -1.0/ 0.0 is %f.", $atan2(-1.0, zero));
$display("The atan of -1.0/-1.0 is %f.", $atan2(-1.0, -1.0));
$display("The atan of inf/ 0.0 is %f.", $atan2(inf, zero));
$display("The atan of 0.0/ inf is %f.", $atan2(zero, inf));
$display("The atan of inf/ inf is %f.", $atan2(inf, inf));
$display("The atan of -inf/ 0.0 is %f.", $atan2(minf, zero));
$display("The atan of 0.0/-inf is %f.", $atan2(zero, minf));
$display("The atan of -inf/-inf is %f.", $atan2(minf, minf));
$display("The atan of nan/ 0.0 is %f.", $abs($atan2(nan, zero)));
$display("The atan of nan/ 1.0 is %f.", $abs($atan2(nan, 1.0)));
$display("The atan of 1.0/ nan is %f.", $abs($atan2(1.0, nan)));
end
endtask
// Task to check the distance from origin function.
task check_hypot;
begin
$display("--- Checking the $hypot function ---");
$display("The distance to ( 0.0, 0.0) is %f.", $hypot(zero, zero));
$display("The distance to ( 2.0, 0.0) is %f.", $hypot(2.0, zero));
$display("The distance to ( -2.0, 0.0) is %f.", $hypot(-2.0, zero));
$display("The distance to ( 0.0, 2.0) is %f.", $hypot(zero, 2.0));
$display("The distance to ( 0.0, -2.0) is %f.", $hypot(zero, -2.0));
$display("The distance to ( inf, 0.0) is %f.", $hypot(inf, zero));
$display("The distance to ( 0.0, inf) is %f.", $hypot(zero, inf));
$display("The distance to ( -inf, 0.0) is %f.", $hypot(minf, zero));
$display("The distance to ( nan, 0.0) is %f.", $abs($hypot(nan, zero)));
$display("The distance to ( 0.0, nan) is %f.", $abs($hypot(zero, nan)));
end
endtask
// Task to check the mathematical constants.
task check_constants;
begin
$display("--- Checking the mathematical constants ---");
$display(" Pi is %.16f.", `M_PI);
$display(" 2*Pi is %.16f.", `M_TWO_PI);
$display(" Pi/2 is %.16f.", `M_PI_2);
$display(" Pi/4 is %.16f.", `M_PI_4);
$display(" 1/Pi is %.16f.", `M_1_PI);
$display(" 2/Pi is %.16f.", `M_2_PI);
$display("2/sqrt(Pi) is %.16f.", `M_2_SQRTPI);
$display(" e is %.16f.", `M_E);
$display(" log2(e) is %.16f.", `M_LOG2E);
$display(" log10(e) is %.16f.", `M_LOG10E);
$display(" loge(2) is %.16f.", `M_LN2);
$display(" loge(10) is %.16f.", `M_LN10);
$display(" sqrt(2) is %.16f.", `M_SQRT2);
$display(" 1/sqrt(2) is %.16f.", `M_SQRT1_2);
end
endtask
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate assign procedural assign ident = expr;
module main ;
reg [31:0] value;
reg control;
reg clock;
reg error;
always @(posedge clock)
value = 3;
always @(control)
if(control)
assign value = 2;
else
deassign value ;
// Setup a clock generator.
always begin
#2;
clock = ~clock;
end
initial
begin
clock = 0;
error = 0;
# 3;
if(value != 3)
begin
$display("FAILED - assign3.2C - procedural assignment(1)");
error = 1;
end
# 2;
control = 1;
# 1;
if(value != 2)
begin
$display("FAILED - assign3.2C - procedural assignment(2)");
error = 1;
end
# 3 ;
control = 0;
# 2;
if(value != 3)
begin
$display("FAILED - assign3.2C - procedural assignment(3)");
error = 1;
end
if(error == 0) $display ("PASSED");
$finish ;
end
endmodule
|
// Check that range mismatches between port direction and data type are detected
// for module ports. An error should be reported and no crash should occur.
module test;
input [1:0] x;
wire [3:0] x;
wire [3:0] y;
assign y = x;
initial begin
$display("FAILED");
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Basic test for functions that work with unbounded vectors as return
// and param types.
module vhdl_unbounded_func_test();
vhdl_unbounded_func dut();
initial begin
#1; // wait for signal assignment
if(dut.test_out1 != \'b1010100110) begin
$display("FAILED 1");
$finish;
end
if(dut.test_out2 != \'b010110) begin
$display("FAILED 2");
$finish;
end
if(dut.neg_test_out1 != ~dut.test_out1) begin
$display("FAILED 3");
$finish;
end
if(dut.neg_test_out2 != ~dut.test_out2) begin
$display("FAILED 4");
$finish;
end
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 2002 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Synth of basic expression assign with add
//
//
module adder (q,a,b );
input a,b;
output [1:0] q;
assign q = a + b;
endmodule
module test ;
reg d;
wire [1:0] q;
adder u_add (.q(q),.a(d),.b(d));
(* ivl_synthesis_off *)
initial
begin
// $dumpfile("test.vcd");
// $dumpvars(0,test);
d = 0;
# 1;
if (q !== 2\'b0)
begin
$display("FAILED - Q isn\'t 0 ");
\t $finish;
end
#1 ;
d = 1;
# 1;
if (q !== 2\'b10)
begin
$display("FAILED - Q isn\'t 2 ");
\t $finish;
end
$display("PASSED");
end
endmodule
|
module DFF
(output reg Q0,
output reg [1:0] Q1,
input wire D0,
input wire [1:0] D1,
input wire CLK,
input wire RST
/* */);
always @(posedge CLK or posedge RST)
if (RST) begin
\tQ0 <= 0;
\tQ1 <= 0;
end else begin
\tQ0 <= D0;
\tQ1 <= D1;
end
endmodule // dut
module main;
wire q0;
wire [1:0] q1;
reg\t d0, clk, rst;
reg [1:0] d1;
DFF dut (.Q0(q0), .Q1(q1), .D0(d0), .D1(d1), .CLK(clk), .RST(rst));
initial begin
clk <= 1;
d0 <= 0;
d1 <= 2;
#1 rst <= 1;
#1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin
\t $display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1);
\t $finish;
end
#1 rst <= 0;
#1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin
\t $display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1);
\t $finish;
end
#1 clk <= 0;
#1 clk <= 1;
#1 if (q0 !== d0 || q1 !== d1) begin
\t $display("FAILED -- Q0=%b Q1=%b, D0=%b D1=%b", q0, q1, d0, d1);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
`begin_keywords "1364-2005"
`timescale 1ns/100ps
module top;
parameter pdly = 1.2;
real rdly = 1.3;
integer idly = 1;
reg in = 1\'b0;
wire gi, gf, gs, gt;
wire #idly int = in;
wire #1.1 first = in;
wire #pdly second = in;
wire #rdly third = in;
buf #idly (gi, in);
buf #1.1 (gf, in);
buf #pdly (gs, in);
buf #rdly (gt, in);
initial begin
$monitor($realtime,, int,, first,, second,, third,, gi,, gf,, gs,, gt);
#0 in = 1\'b1;
#2 in = 1\'b0;
#4;
rdly = -6.1; // Since we are at 6 this will not wrap.
in = 1\'b1;
@(third or gt) $display("Large delay: ", $realtime);
end
initial #1.1 $display("Should be 1.1: ", $realtime); // This should be 1.1
initial #pdly $display("Should be 1.2: ", $realtime); // This should be 1.2
initial begin
#0; // We need this so that rdly has a defined value.
#rdly $display("Should be 1.3: ", $realtime); // This should be 1.3
end
initial begin
#0; // We need this so that rdly has a defined value.
#idly $display("Should be 1.0: ", $realtime); // This should be 1.0
end
endmodule
`timescale 1ns/1ps
module top2;
initial #1.001 $display("Should be 1.001: ", $realtime);
endmodule
`end_keywords
|
module stimulus (output reg A, B);
initial begin
// both inputs are x
#0 {A, B} = 2\'bxx;
// both inputs are z
#10 {A, B} = 2\'bzz;
// one input is a zero
#10 {A, B} = 2\'b0x;
#10 {A, B} = 2\'bx0;
#10 {A, B} = 2\'b0z;
#10 {A, B} = 2\'bz0;
// one input is a one
#10 {A, B} = 2\'b1x;
#10 {A, B} = 2\'bx1;
#10 {A, B} = 2\'b1z;
#10 {A, B} = 2\'bz1;
// one input x, other z
#10 {A, B} = 2\'bxz;
#10 {A, B} = 2\'bzx;
// normal bit operands
#10 {A, B} = 2\'b00;
#10 {A, B} = 2\'b01;
#10 {A, B} = 2\'b10;
#10 {A, B} = 2\'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
// both inputs are x
2\'bxx: gate_output = 1\'bx;
// both inputs are z
2\'bzz: gate_output = 1\'bx;
// output should be x (one input is a one)
2\'b1x: gate_output = 1\'bx;
2\'bx1: gate_output = 1\'bx;
2\'b1z: gate_output = 1\'bx;
2\'bz1: gate_output = 1\'bx;
// output is x (one input is a zero)
2\'b0x: gate_output = 1\'bx;
2\'bx0: gate_output = 1\'bx;
2\'b0z: gate_output = 1\'bx;
2\'bz0: gate_output = 1\'bx;
// inputs x, z
2\'bxz: gate_output = 1\'bx;
2\'bzx: gate_output = 1\'bx;
// normal operation on bit
2\'b00: gate_output = 1;
2\'b01: gate_output = 0;
2\'b10: gate_output = 0;
2\'b11: gate_output = 1;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in XNOR operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
xnor_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#200;
$display("PASSED");
$finish;
end
endmodule
|
// Check compiler can handle zero widths in indexed
// part selects.
module bug();
localparam off1 = 1;
localparam wid1 = 0;
integer off2 = 1;
integer wid2 = 0;
wire [7:0] vector = 8'h55;
wire part1 = |vector[off1 +: wid1];
wire part2 = |vector[off2 +: wid2];
endmodule
|
// Check that declaring multiple non-ANSI module ports with the same name is an
// error. Even if they both have an implicit type.
module test(x);
input x;
input x;
endmodule
|
// This test program shows how programs can be contained by
// modules, and can access variables in the context.
module main;
reg[7:0] shared;
wire [7:0] not_shared = ~shared;
program test1;
initial shared <= \'h55;
endprogram :test1
program test2;
reg [7:0] tmp;
final begin
if (shared !== \'h55) begin
\t $display("FAILED -- shared=%b is not correct", shared);
\t $finish;
end
tmp = ~shared;
if (not_shared !== \'haa || not_shared !== tmp) begin
\t $display("FAILED -- not_shared is not correct", not_shared);
\t $finish;
end
$display("PASSED");
end
endprogram :test2
endmodule // main
|
/*
* Copyright (c) 2000 Intrinsity, Inc.
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test_bufif1 ( );
reg gnd, vdd, x, z;
wire t0, t1, t2, t3, t4, t5, t6, t7,
t8, t9, ta, tb, tc, td, te, tf;
reg failed;
wire StH, StL;
assign (strong1, highz0) StH = 1\'bx;
assign (highz1, strong0) StL = 1\'bx;
bufif1 b0 ( t0, gnd, gnd);
bufif1 b1 ( t1, gnd, vdd);
bufif1 b2 ( t2, gnd, x);
bufif1 b3 ( t3, gnd, z);
bufif1 b4 ( t4, vdd, gnd);
bufif1 b5 ( t5, vdd, vdd);
bufif1 b6 ( t6, vdd, x);
bufif1 b7 ( t7, vdd, z);
bufif1 b8 ( t8, x, gnd);
bufif1 b9 ( t9, x, vdd);
bufif1 ba ( ta, x, x);
bufif1 bb ( tb, x, z);
bufif1 bc ( tc, z, gnd);
bufif1 bd ( td, z, vdd);
bufif1 be ( te, z, x);
bufif1 bf ( tf, z, z);
initial begin
//
// work around initial state assignment bug
failed = 0;
assign gnd = 1\'b1;
assign vdd = 1\'b0;
assign x = 1\'b1;
assign z = 1\'b1;
#10;
assign gnd = 1\'b0;
assign vdd = 1\'b1;
assign x = 1\'bx;
assign z = 1\'bz;
#10;
if (t0 !== z)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:z", gnd, gnd, t0 );
end
if (t1 !== 0)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:0", gnd, vdd, t1 );
end
if (t2 !== StL)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:StL", gnd, x, t2 );
end
if (t3 !== StL)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:StL", gnd, z, t3 );
end
if (t4 !== 1\'bz)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:z", gnd, z, t4 );
end
if (t5 !== 1)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:1", vdd, vdd, t5 );
end
if (t6 !== StH)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:StH", vdd, x, t6 );
end
if (t7 !== StH)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:StH", vdd, z, t7 );
end
if (t8 !== 1\'bz)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:z", x, gnd, t8 );
end
if (t9 !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", x, vdd, t9 );
end
if (ta !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", x, x, ta );
end
if (tb !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", x, z, tb );
end
if (tc !== 1\'bz)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:z", z, gnd, tc );
end
if (td !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", z, vdd, td );
end
if (te !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", z, x, te );
end
if (tf !== 1\'bx)
begin
failed = 1;
$display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", z, z, tf );
end
if (failed == 0)
$display ("PASSED");
end
endmodule
|
module test;
reg [1:0] bus;
reg [1:0] skewed_bus;
integer delay0; initial delay0 = 5;
integer delay1; initial delay1 = 10;
/* attempt to model skew across the bus using transport delays */
always @( bus[0] )
begin
skewed_bus[0] <= #delay0 bus[0];
end
always @( bus[1] )
begin
skewed_bus[1] <= #delay1 bus[1];
end
initial begin
#1 bus = 2\'b00;
#11 if (skewed_bus !== 2\'b00) begin
\t $display("FAILED -- setup failed.");
\t $finish;
end
bus = 2\'b11;
#4 if (skewed_bus !== 2\'b00) begin
\t $display("FAILED -- changed far too soon");
\t $finish;
end
#2 if (skewed_bus !== 2\'b01) begin
\t $display("FAILED -- partial change not right.");
\t $finish;
end
#5 if (skewed_bus !== 2\'b11) begin
\t $display("FAILED -- final change not right");
\t $finish;
end
$display("PASSED");
end
endmodule
|
`define FAIL
module top;
reg[7:0] pattern;
initial begin
// Mask off the MSB and the two lower bits.
pattern = ~0 ^ 2\'b11;
pattern[7] = 0;
`ifndef FAIL
#0;
`endif
if ((8\'b01111110&pattern) == (8\'b11111101&pattern)) $display("PASSED");
else $display("Fail: %b", pattern);
end
endmodule
|
// Copyright (c) 2001 Stephen Williams ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* This module implements what essentially amounts to an array of DFF
* devices with output enable. This test checks the operation of the
* pmos and nmos devices.
*/
module grayGap (ad, clk, read, write);
output [31:0] ad;
input\t clk, read, write;
reg [15:0] regff;
pmos ad_drv [31:0] (ad, {16\'b0, regff}, read);
always @(posedge clk)
if (write) regff = ad[15:0];
endmodule
module main;
wire [31:0] ad;
reg\t clk, read, write;
reg [31:0] ad_val;
reg ad_en;
nmos ad_drv[31:0] (ad, ad_val, ad_en);
grayGap test (ad, clk, read, write);
always #10 clk = ~clk;
initial begin
clk = 1;
read = 1;
write = 0;
$monitor($time, "ad=%b", ad);
// Set up to write a value into the grayGap register.
@(negedge clk)
\tad_val = 32\'haaaa_aaaa;
read = 1;
write = 1;
ad_en = 1;
// The posedge has passed, now set up to read that value
// out. Turn all the drivers off for a moment, to see that the
// line becomes tri-state...
@(negedge clk)
\tad_en = 0;
write = 0;
// Now read the value.
#1 read = 0;
#1 $display("Wrote %h, got %h", ad_val, ad);
if (ad !== 32\'b0000_0000_0000_0000_1010_1010_1010_1010) begin
\t $display("FAILED -- ad is %b", ad);
\t $finish;
end
#2 read = 1;
$display("PASSED");
$finish;
end
endmodule // main
|
module test();
reg signed [3:0] a;
reg [7:0] b;
reg signed [7:0] c;
reg signed [7:0] d;
reg signed [7:0] e;
reg failed = 0;
initial begin
a = -1;
b = 4;
c = 4;
d = 4;
e = 4;
b += a;
c += a;
{d} += a;
e[7:0] += a;
$display("%0d", b);
if (b !== 19) failed = 1;
$display("%0d", c);
if (c !== 3) failed = 1;
$display("%0d", d);
if (d !== 19) failed = 1;
$display("%0d", e);
if (e !== 19) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test the select of a bit from a vector.
*/
module main;
reg [3:0] a = 4\'b0110;
reg [1:0] s = 0;
wire b = a[s];
initial begin
#1 if (b !== 0) begin
\t $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
\t $finish;
end
s = 1;
#1 if (b !== 1) begin
\t $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
\t $finish;
end
s = 2;
#1 if (b !== 1) begin
\t $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
\t $finish;
end
s = 3;
#1 if (b !== 0) begin
\t $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
\t $finish;
end
s = 2\'bxx;
#1 if (b !== 1\'bx) begin
\t $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// Check that when a enum type is declared inside a struct that the enum is
// properly installed in the scope and the enum items are available
module test;
struct packed {
enum integer {
A
} e;
} s;
initial begin
s.e = A;
if (s.e == A) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
`define STOP_HERE
`define my_macro(a0, a1=HERE, a2=HERE) \\
`ifdef STOP_``a1 \\
$display(a0); \\
`elsif STOP_``a2 \\
$display(a0, a1); \\
`else \\
$display(a0, a1, a2); \\
`endif \\
module test();
initial begin
`my_macro("No args");
`my_macro("Args = %s", "hello");
`my_macro("Args = %0d, %s", 123, "hello");
end
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: rop.v,v 1.2 2001/06/20 00:04:09 ka6s Exp $
// $Log: rop.v,v $
// Revision 1.2 2001/06/20 00:04:09 ka6s
// Updated the code to print out "PASSED" when appropriate.
//
// Revision 1.1 2001/06/19 13:52:13 ka6s
// Added 4 tests from Stephan Boettcher
//
//
// Test of === operator
module rop;
reg [2:0] a;
reg\t b;
reg\t error;
initial
begin
error = 0;
\ta = 3\'b 10z;
\tb = & a;
\t$display(" & 3\'b%b === %b", a, b);
\tif (b !== 1\'b0)
\tbegin
\t $display("FAILED");
\t error = 1;
end
\tb = | a;
\t$display(" | 3\'b%b === %b", a, b);
\tif (b !== 1\'b1)
begin
\t error = 1;
\t $display("FAILED");
\t end
\tb = ^ a;
\t$display(" ^ 3\'b%b === %b", a, b);
\tif (b !== 1\'bx)
begin
\t $display("FAILED");
\t error = 1;
end
\tb = ~& a;
\t$display("~& 3\'b%b === %b", a, b);
\tif (b !== 1\'b1)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~| a;
\t$display("~| 3\'b%b === %b", a, b);
\tif (b !== 1\'b0)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~^ a;
\t$display("~^ 3\'b%b === %b", a, b);
\tif (b !== 1\'bx)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\ta = 3\'b 0xz;
\tb = & a;
\t$display(" & 3\'b%b === %b", a, b);
\tif (b !== 1\'b0)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = | a;
\t$display(" | 3\'b%b === %b", a, b);
\tif (b !== 1\'bx)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ^ a;
\t$display(" ^ 3\'b%b === %b", a, b);
\tif (b !== 1\'bx)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~& a;
\t$display("~& 3\'b%b === %b", a, b);
\tif (b !== 1\'b1)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~| a;
\t$display("~| 3\'b%b === %b", a, b);
\tif (b !== 1\'bx)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~^ a;
\t$display("~^ 3\'b%b === %b", a, b);
\tif (b !== 1\'bx)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\ta = 3\'b 1xz;
\tb = & a;
\t$display(" & 3\'b%b === %b", a, b);
\tif (b !== 1\'bx)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = | a;
\t$display(" | 3\'b%b === %b", a, b);
\tif (b !== 1\'b1)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ^ a;
\t$display(" ^ 3\'b%b === %b", a, b);
\tif (b !== 1\'bx)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~& a;
\t$display("~& 3\'b%b === %b", a, b);
\tif (b !== 1\'bx)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~| a;
\t$display("~| 3\'b%b === %b", a, b);
\tif (b !== 1\'b0)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~^ a;
\t$display("~^ 3\'b%b === %b", a, b);
\tif (b !== 1\'bx)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\ta = 3\'b 000;
\tb = & a;
\t$display(" & 3\'b%b === %b", a, b);
\tif (b !== 1\'b0)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = | a;
\t$display(" | 3\'b%b === %b", a, b);
\tif (b !== 1\'b0)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ^ a;
\t$display(" ^ 3\'b%b === %b", a, b);
\tif (b !== 1\'b0)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~& a;
\t$display("~& 3\'b%b === %b", a, b);
\tif (b !== 1\'b1)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~| a;
\t$display("~| 3\'b%b === %b", a, b);
\tif (b !== 1\'b1)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~^ a;
\t$display("~^ 3\'b%b === %b", a, b);
\tif (b !== 1\'b1)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\ta = 3\'b 111;
\tb = & a;
\t$display(" & 3\'b%b === %b", a, b);
\tif (b !== 1\'b1)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = | a;
\t$display(" | 3\'b%b === %b", a, b);
\tif (b !== 1\'b1)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ^ a;
$display(" ^ 3\'b%b === %b", a, b);
\tif (b !== 1\'b1)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~& a;
\t$display("~& 3\'b%b === %b", a, b);
\tif (b !== 1\'b0)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~| a;
\t$display("~| 3\'b%b === %b", a, b);
\tif (b !== 1\'b0)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
\tb = ~^ a;
\t$display("~^ 3\'b%b === %b", a, b);
\tif (b !== 1\'b0)
\t begin
\t $display("FAILED");
\t error = 1;
\t end
if(error === 0)
\t $display("PASSED");
end
endmodule
|
// This tests unalligned write/read access to packed structures
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test;
typedef struct packed {
logic [7:0] high;
logic [7:0] low;
} word_t;
// Declare word* as a VARIABLE
word_t word_se0, word_se1, word_se2, word_se3;
word_t word_sw0, word_sw1, word_sw2, word_sw3;
word_t word_sp0, word_sp1, word_sp2, word_sp3;
word_t word_ep0, word_ep1, word_ep2, word_ep3;
// error counter
bit err = 0;
// access to structure elements
assign word_se1.high = {8+0{1\'b1}};
assign word_se1.low = {8+0{1\'b0}};
assign word_se2.high = {8+1{1\'b1}};
assign word_se2.low = {8+1{1\'b0}};
assign word_se3.high = {8-1{1\'b1}};
assign word_se3.low = {8-1{1\'b0}};
// access to whole structure
assign word_sw1 = {16+0{1\'b1}};
assign word_sw2 = {16+1{1\'b1}};
assign word_sw3 = {16-1{1\'b1}};
// access to parts of structure elements
assign word_ep1.high [3:0] = {4+0{1\'b1}};
assign word_ep1.low [3:0] = {4+0{1\'b0}};
assign word_ep2.high [3:0] = {4+1{1\'b1}};
assign word_ep2.low [3:0] = {4+1{1\'b0}};
assign word_ep3.high [3:0] = {4-1{1\'b1}};
assign word_ep3.low [3:0] = {4-1{1\'b0}};
// access to parts of the whole structure
assign word_sp1 [11:4] = {8+0{1\'b1}};
assign word_sp2 [11:4] = {8+1{1\'b1}};
assign word_sp3 [11:4] = {8-1{1\'b1}};
initial begin
#1;
// access to structure elements
if (word_se0 !== 16\'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_se0 = \'b%b", word_se0 ); err=1; end
if (word_se1 !== 16\'b11111111_00000000) begin $display("FAILED -- word_se1 = \'b%b", word_se1 ); err=1; end
if (word_se1.high !== 8\'b11111111 ) begin $display("FAILED -- word_se1.high = \'b%b", word_se1.high); err=1; end
if (word_se1.low !== 8\'b00000000 ) begin $display("FAILED -- word_se1.low = \'b%b", word_se1.low ); err=1; end
if (word_se2 !== 16\'b11111111_00000000) begin $display("FAILED -- word_se2 = \'b%b", word_se2 ); err=1; end
if (word_se2.high !== 8\'b11111111 ) begin $display("FAILED -- word_se2.high = \'b%b", word_se2.high); err=1; end
if (word_se2.low !== 8\'b00000000 ) begin $display("FAILED -- word_se2.low = \'b%b", word_se2.low ); err=1; end
if (word_se3 !== 16\'b01111111_00000000) begin $display("FAILED -- word_se3 = \'b%b", word_se3 ); err=1; end
if (word_se3.high !== 8\'b01111111 ) begin $display("FAILED -- word_se3.high = \'b%b", word_se3.high); err=1; end
if (word_se3.low !== 8\'b00000000 ) begin $display("FAILED -- word_se3.low = \'b%b", word_se3.low ); err=1; end
// access to whole structure
if (word_sw0 !== 16\'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_sw0 = \'b%b", word_sw0 ); err=1; end
if (word_sw1 !== 16\'b11111111_11111111) begin $display("FAILED -- word_sw1 = \'b%b", word_sw1 ); err=1; end
if (word_sw2 !== 16\'b11111111_11111111) begin $display("FAILED -- word_sw2 = \'b%b", word_sw2 ); err=1; end
if (word_sw3 !== 16\'b01111111_11111111) begin $display("FAILED -- word_sw3 = \'b%b", word_sw3 ); err=1; end
// access to parts of structure elements
if (word_ep0 !== 16\'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_ep0 = \'b%b", word_ep0 ); err=1; end
if (word_ep1 !== 16\'bzzzz1111_zzzz0000) begin $display("FAILED -- word_ep1 = \'b%b", word_ep1 ); err=1; end
if (word_ep1.high !== 8\'bzzzz1111 ) begin $display("FAILED -- word_ep1.high = \'b%b", word_ep1.high); err=1; end
if (word_ep1.low !== 8\'bzzzz0000 ) begin $display("FAILED -- word_ep1.low = \'b%b", word_ep1.low ); err=1; end
if (word_ep2 !== 16\'bzzzz1111_zzzz0000) begin $display("FAILED -- word_ep2 = \'b%b", word_ep2 ); err=1; end
if (word_ep2.high !== 8\'bzzzz1111 ) begin $display("FAILED -- word_ep2.high = \'b%b", word_ep2.high); err=1; end
if (word_ep2.low !== 8\'bzzzz0000 ) begin $display("FAILED -- word_ep2.low = \'b%b", word_ep2.low ); err=1; end
if (word_ep3 !== 16\'bzzzz0111_zzzz0000) begin $display("FAILED -- word_ep3 = \'b%b", word_ep3 ); err=1; end
if (word_ep3.high !== 8\'bzzzz0111 ) begin $display("FAILED -- word_ep3.high = \'b%b", word_ep3.high); err=1; end
if (word_ep3.low !== 8\'bzzzz0000 ) begin $display("FAILED -- word_ep3.low = \'b%b", word_ep3.low ); err=1; end
// access to parts of the whole structure
if (word_sp0 !== 16\'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_sp0 = \'b%b", word_sp0 ); err=1; end
if (word_sp1 !== 16\'bzzzz1111_1111zzzz) begin $display("FAILED -- word_sp1 = \'b%b", word_sp1 ); err=1; end
if (word_sp2 !== 16\'bzzzz1111_1111zzzz) begin $display("FAILED -- word_sp2 = \'b%b", word_sp2 ); err=1; end
if (word_sp3 !== 16\'bzzzz0111_1111zzzz) begin $display("FAILED -- word_sp3 = \'b%b", word_sp3 ); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
// Check that trying to override a parameter that does not exist results in an
// error
module a #(
parameter A = 1
);
initial begin
$display("FAILED");
end
endmodule
module test;
a #(
.A(10)
) i_a();
defparam i_a.Z = 10; // Error
endmodule
|
//
// Copyright (c) 2001 Stephen Williams <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* This program tests the behavior of a simple non-blocking assignment
* with an internal delay. We can check that the value changes at the
* right time and not the wrong time.
*/
module main ;
reg a;
initial begin
a = 0;
if (a !== 0) begin
\t $display("FAILED -- a at 0 is %b", a);
\t $finish;
end
a <= #2 1;
if (a !== 0) begin
\t $display("FAILED -- (0) a should still be 0 but is %b", a);
\t $finish;
end
#1 if (a !== 0) begin
\t $display("FAILED -- (1) a should still be 0 but is %b", a);
\t $finish;
end
#2 if (a !== 1\'b1) begin
\t $display("FAILED -- a should now be 1, but is %b", a);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests that a non-integer delay gets its extra
* precision accounted for if the timescale supports it. In this
* example, set the units to 1ms, but set the precision so that the
* numbers can be given accurate to .1ms. This should cause a delay
* of 2.4 and 2.6 to really be different.
*/
`timescale 1ms / 100us
module main;
reg err;
reg clk;
reg out1, out2;
realtime time1;
realtime time2;
real eps;
always @(posedge clk) #2.4 begin
$display($time,,$realtime, " set out1 == 1");
time1 = $realtime;
out1 = 1;
end
always @(posedge clk) #2.6 begin
$display($time,,$realtime, " set out2 == 1");
time2 = $realtime;
out2 = 1;
end
initial begin
clk = 0;
out1 = 0;
out2 = 0;
time1 = 0;
time2 = 0;
err = 0;
$timeformat(-3,1,"ms",5);
#1 if (out1 !== 0) begin
\t $display("Error -- out1 s/b 0 at time $time but is=%x", out1);
\t err =1 ;
end
clk = 1;
#3 if (out1 !== 1) begin
\t $display("Error -- out1 s/b 1 at time $time but is=%x", out1);
\t err =1 ;
end
eps = time1 - 3.4;
if (eps < 0.0)
\teps = 0.0 - eps;
if (eps > 0.0001) begin
\t $display("Error -- time1 s/b 3.4 but is=%t", time1);
\t err =1 ;
end
#1 eps = time2 - 3.6;
if (eps < 0.0)
\teps = 0.0 - eps;
if (eps > 0.0001) begin
\t $display("Error -- time2 s/b 3.6 but is=%t, ", time2);
\t err =1 ;
end
if(err == 0)
$display("PASSED");
else
$display("FAILED");
end // initial begin
endmodule // main
|
module top;
reg [4:1] res;
reg pass;
initial begin
pass = 1\'b1;
res = 4\'b0000;
fork
#3 res[3] = 1\'b1;
#4 res[4] = 1\'b1;
join_none
fork
#1 res[1] = 1\'b1;
#2 res[2] = 1\'b1;
join_any
if (res != 4\'b0001) begin
$display("Error: Only first process should have run: %b", res);
pass = 1\'b0;
end
wait fork;
if (res != 4\'b1111) begin
$display("Error: All processes should have run: %b", res);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* This test is based on PR#905
*/
module bug();
initial begin
$displayh("", 99);
$displayo("", 99);
$displayb("", 99);
end
endmodule // bug
|
module ts_pad (
inout wire pad,
input wire oe,
input wire op
);
assign pad = oe ? op : 1\'bz;
endmodule
module test();
wire bus0;
wire bus1;
reg oe1 = 1\'b0;
reg oe2 = 1\'b0;
reg oe3 = 1\'b0;
reg oe4 = 1\'b0;
reg oe5 = 1\'b0;
reg oe6 = 1\'b0;
wire op1 = 1\'b0;
wire op2 = 1\'b1;
wire op3 = 1\'b1;
wire op4 = 1\'b0;
wire op5 = 1\'bx;
wire op6 = 1\'bx;
ts_pad pad1(bus0, oe1, op1);
ts_pad pad2(bus1, oe2, op2);
ts_pad pad3(bus0, oe3, op3);
ts_pad pad4(bus1, oe4, op4);
bufif1(bus0, op5, oe5);
bufif1(bus1, op6, oe6);
integer multi;
integer forced;
integer countD;
integer count0;
integer count1;
integer countX;
reg failed = 0;
task check_results;
input integer expected_multi;
input integer expected_forced;
input integer expected_countD;
input integer expected_count0;
input integer expected_count1;
input integer expected_countX;
begin
$write("multi = %0d ", multi);
if (multi !== expected_multi) failed = 1;
if (expected_forced != -1) begin
$write("forced = %0d ", forced);
if (forced !== expected_forced) failed = 1;
end
if (expected_countD != -1) begin
$write("countD = %0d ", countD);
if (countD !== expected_countD) failed = 1;
end
if (expected_count0 != -1) begin
$write("count0 = %0d ", count0);
if (count0 !== expected_count0) failed = 1;
end
if (expected_count1 != -1) begin
$write("count1 = %0d ", count1);
if (count1 !== expected_count1) failed = 1;
end
if (expected_countX != -1) begin
$write("countX = %0d ", countX);
if (countX !== expected_countX) failed = 1;
end
$write("\
");
end
endtask
initial begin
#1;
multi = $countdrivers(bus0, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(bus1, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
$display("");
oe1 = 1\'b1;
#1;
multi = $countdrivers(bus0, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(bus1, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
$display("");
oe2 = 1\'b1;
#1;
multi = $countdrivers(bus0, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(bus1, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
$display("");
oe3 = 1\'b1;
#1;
multi = $countdrivers(bus0, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(bus1, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
$display("");
oe4 = 1\'b1;
#1;
multi = $countdrivers(bus0, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(bus1, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
$display("");
oe5 = 1\'b1;
#1;
multi = $countdrivers(bus0, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(bus1, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
$display("");
oe6 = 1\'b1;
#1;
multi = $countdrivers(bus0, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(bus1, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* This test is based on PR#978.
* Check that user defined functions can have real-valued
* results, and that the result gets properly returned.
*/
module test();
real m;
function real dummy;
input b;
begin
\t dummy=2.5;
end
endfunction
initial
begin
\tm=dummy(0);
\tif (m != 2.5) begin
\t $display("FAILED: return result is %f", m);
\t $finish;
\tend
\t$display("PASSED");
end
endmodule
|
module test;
// force leading zero on outer scope genblk numbers
localparam genblk1 = 0;
localparam genblk2 = 0;
localparam genblk3 = 0;
localparam genblk4 = 0;
localparam genblk5 = 0;
localparam genblk6 = 0;
localparam genblk7 = 0;
localparam genblk8 = 0;
localparam genblk9 = 0;
parameter TRUE = 1;
genvar i;
genvar j;
for (i = 0; i < 2; i = i + 1) begin
reg r1 = 1;
end
for (i = 0; i < 2; i = i + 1) begin
for (j = 0; j < 2; j = j + 1) begin
reg r2 = 1;
end
end
for (i = 0; i < 2; i = i + 1) begin
case (TRUE)
0: begin
reg r3a = 1;
end
1: begin
reg r3b = 1;
end
endcase
end
for (i = 0; i < 2; i = i + 1) begin
if (TRUE)
begin
reg r4a = 1;
end
else
begin
reg r4b = 1;
end
end
for (i = 0; i < 2; i = i + 1) begin
if (!TRUE)
begin
reg r5a = 1;
end
else
begin
if (TRUE)
begin
reg r5b = 1;
end
else
begin
reg r5c = 1;
end
end
end
for (i = 0; i < 2; i = i + 1) begin
if (!TRUE)
begin
reg r6a = 1;
end
else
begin
if (!TRUE)
begin
reg r6b = 1;
end
else
begin
reg r6c = 1;
end
end
end
case (TRUE)
0: begin
reg r7a = 1;
end
1: begin
reg r7b = 1;
end
endcase
case (TRUE)
0: begin
case (TRUE)
0: begin
reg r8a = 1;
end
1: begin
reg r8b = 1;
end
endcase
end
1: begin
case (TRUE)
0: begin
reg r8c = 1;
end
1: begin
reg r8d = 1;
end
endcase
end
endcase
case (TRUE)
0: begin
if (TRUE)
begin
reg r9a = 1;
end
else
begin
reg r9b = 1;
end
end
1: begin
if (TRUE)
begin
reg r9c = 1;
end
else
begin
reg r9d = 1;
end
end
endcase
case (TRUE)
0: begin
if (!TRUE)
begin
reg r10a = 1;
end
else
begin
if (TRUE)
begin
reg r10b = 1;
end
else
begin
reg r10c = 1;
end
end
end
1: begin
if (!TRUE)
begin
reg r10d = 1;
end
else
begin
if (TRUE)
begin
reg r10e = 1;
end
else
begin
reg r10f = 1;
end
end
end
endcase
case (TRUE)
0: begin
if (!TRUE)
begin
reg r11a = 1;
end
else
begin
if (!TRUE)
begin
reg r11b = 1;
end
else
begin
reg r11c = 1;
end
end
end
1: begin
if (!TRUE)
begin
reg r11d = 1;
end
else
begin
if (!TRUE)
begin
reg r11e = 1;
end
else
begin
reg r11f = 1;
end
end
end
endcase
case (TRUE)
0: begin
if (!TRUE)
begin
reg r12a = 1;
end
else if (TRUE)
begin
reg r12b = 1;
end
else
begin
reg r12c = 1;
end
end
1: begin
if (!TRUE)
begin
reg r12d = 1;
end
else if (TRUE)
begin
reg r12e = 1;
end
else
begin
reg r12f = 1;
end
end
endcase
case (TRUE)
0: begin
if (!TRUE)
begin
reg r13a = 1;
end
else if (!TRUE)
begin
reg r13b = 1;
end
else
begin
reg r13c = 1;
end
end
1: begin
if (!TRUE)
begin
reg r13d = 1;
end
else if (!TRUE)
begin
reg r13e = 1;
end
else
begin
reg r13f = 1;
end
end
endcase
if (TRUE)
begin
reg r14a = 1;
end
else
begin
reg r14b = 1;
end
if (!TRUE)
begin
reg r15a = 1;
end
else
begin
if (TRUE)
begin
reg r15b = 1;
end
else
begin
reg r15c = 1;
end
end
if (!TRUE)
begin
reg r16a = 1;
end
else
begin
if (!TRUE)
begin
reg r16b = 1;
end
else
begin
reg r16c = 1;
end
end
if (!TRUE)
begin
reg r17a = 1;
end
else if (TRUE)
begin
reg r17b = 1;
end
else
begin
reg r17c = 1;
end
if (!TRUE)
begin
reg r18a = 1;
end
else if (!TRUE)
begin
reg r18b = 1;
end
else
begin
reg r18c = 1;
end
if (TRUE)
begin
if (TRUE)
begin
reg r19a = 1;
end
else
begin
reg r19b = 1;
end
end
else
begin
reg r19c = 1;
end
if (TRUE)
begin
if (!TRUE)
begin
reg r20a = 1;
end
else
begin
reg r20b = 1;
end
end
else
begin
reg r20c = 1;
end
if (TRUE)
begin
case (TRUE)
0: begin
reg r21a = 1;
end
1: begin
reg r21b = 1;
end
endcase
end
else
begin
case (TRUE)
0: begin
reg r21c = 1;
end
1: begin
reg r21d = 1;
end
endcase
end
if (!TRUE)
begin
case (TRUE)
0: begin
reg r22a = 1;
end
1: begin
reg r22b = 1;
end
endcase
end
else if (TRUE)
begin
case (TRUE)
0: begin
reg r22c = 1;
end
1: begin
reg r22d = 1;
end
endcase
end
else
begin
case (TRUE)
0: begin
reg r22e = 1;
end
1: begin
reg r22f = 1;
end
endcase
end
if (!TRUE)
begin
case (TRUE)
0: begin
reg r23a = 1;
end
1: begin
reg r23b = 1;
end
endcase
end
else if (!TRUE)
begin
case (TRUE)
0: begin
reg r23c = 1;
end
1: begin
reg r23d = 1;
end
endcase
end
else
begin
case (TRUE)
0: begin
reg r23e = 1;
end
1: begin
reg r23f = 1;
end
endcase
end
initial begin
$list_regs;
end
endmodule
|
module pr2974294;
reg [7:0] array[1:0];
wire [7:0] word;
reg fail;
assign word = array[0];
initial begin
fail = 0;
#0 $display("%b", word);
if (word !== 8\'bx) fail = 1;
#1 $display("%b", word);
if (word !== 8\'bx) fail = 1;
array[0] = 8\'d0;
#0 $display("%b", word);
if (word !== 8\'d0) fail = 1;
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module top;
parameter pnani = $sqrt(-1);
parameter pnanr = $sqrt(-1.0);
parameter p0i = $sqrt(0);
parameter p0r = $sqrt(0.0);
parameter p2i = $sqrt(4);
parameter p2r = $sqrt(4.0);
parameter pln = $ln(1);
parameter plog10 = $log10(10);
parameter pexp = $exp(0);
parameter pfloor = $floor(1.5);
parameter pceil = $ceil(1.5);
parameter psin = $sin(0);
parameter pcos = $cos(0);
parameter ptan = $tan(0);
parameter pasin = $asin(0);
parameter pacos = $acos(1);
parameter patan = $atan(0);
parameter psinh = $sinh(0);
parameter pcosh = $cosh(0);
parameter ptanh = $tanh(0);
parameter pasinh = $asinh(0);
parameter pacosh = $acosh(1);
parameter patanh = $atanh(0);
parameter ppow = $pow(-2, 2);
parameter patan2 = $atan2(0, 0);
parameter phypot = $hypot(-1, 0);
reg [$sqrt(16)-1:0] reg4 = \'b0;
reg pass = 1\'b1;
real result, rin;
wire [7:0] out = $sqrt(rin);
wire real rout = $sqrt(rin);
initial begin
/* Test the elab_pexpr implementation. */
if ($bits(reg4) !== 4) begin
$display("Failed register size, expected 4, got %d", $bits(reg4));
pass = 1\'b0;
end
if (!(pnani != pnani)) begin
$display("Failed with param. NaN (int), expected NaN, got %f", pnani);
pass = 1\'b0;
end
if (!(pnanr != pnanr)) begin
$display("Failed with param. NaN (real), expected NaN, got %f", pnanr);
pass = 1\'b0;
end
if (p0i != 0.0) begin
$display("Failed with param. 0, expected 0.0, got %f", p0i);
pass = 1\'b0;
end
if (p0r != 0.0) begin
$display("Failed with param. 0.0, expected 0.0, got %f", p0r);
pass = 1\'b0;
end
if (p2i != 2.0) begin
$display("Failed with param. 4, expected 2.0, got %f", p2i);
pass = 1\'b0;
end
if (p2r != 2.0) begin
$display("Failed with param. 4.0, expected 2.0, got %f", p2r);
pass = 1\'b0;
end
if (pln != 0.0) begin
$display("Failed with param. $ln, expected 0.0, got %f", pln);
pass = 1\'b0;
end
if (plog10 != 1.0) begin
$display("Failed with param. $log10, expected 1.0, got %f", plog10);
pass = 1\'b0;
end
if (pexp != 1.0) begin
$display("Failed with param. $exp, expected 1.0, got %f", pexp);
pass = 1\'b0;
end
if (pfloor != 1.0) begin
$display("Failed with param. $floor, expected 1.0, got %f", pfloor);
pass = 1\'b0;
end
if (pceil != 2.0) begin
$display("Failed with param. $ceil, expected 2.0, got %f", pceil);
pass = 1\'b0;
end
if (psin != 0.0) begin
$display("Failed with param. $sin, expected 0.0, got %f", psin);
pass = 1\'b0;
end
if (pcos != 1.0) begin
$display("Failed with param. $cos, expected 1.0, got %f", pcos);
pass = 1\'b0;
end
if (ptan != 0.0) begin
$display("Failed with param. $tan, expected 0.0, got %f", ptan);
pass = 1\'b0;
end
if (pasin != 0.0) begin
$display("Failed with param. $asin, expected 0.0, got %f", pasin);
pass = 1\'b0;
end
if (pacos != 0.0) begin
$display("Failed with param. $acos, expected 0.0, got %f", pacos);
pass = 1\'b0;
end
if (patan != 0.0) begin
$display("Failed with param. $atan, expected 0.0, got %f", patan);
pass = 1\'b0;
end
if (psinh != 0.0) begin
$display("Failed with param. $sinh, expected 0.0, got %f", psinh);
pass = 1\'b0;
end
if (pcosh != 1.0) begin
$display("Failed with param. $cosh, expected 1.0, got %f", pcosh);
pass = 1\'b0;
end
if (ptanh != 0.0) begin
$display("Failed with param. $tanh, expected 0.0, got %f", ptanh);
pass = 1\'b0;
end
if (pasinh != 0.0) begin
$display("Failed with param. $asinh, expected 0.0, got %f", pasinh);
pass = 1\'b0;
end
if (pacosh != 0.0) begin
$display("Failed with param. $acosh, expected 0.0, got %f", pacosh);
pass = 1\'b0;
end
if (patanh != 0.0) begin
$display("Failed with param. $atanh, expected 0.0, got %f", patanh);
pass = 1\'b0;
end
if (ppow != 4.0) begin
$display("Failed with param. $pow, expected 4.0, got %f", ppow);
pass = 1\'b0;
end
if (patan2 != 0.0) begin
$display("Failed with param. $atan2, expected 4.0, got %f", patan2);
pass = 1\'b0;
end
if (phypot != 1.0) begin
$display("Failed with param. $hypot, expected 1.0, got %f", phypot);
pass = 1\'b0;
end
/* Test the eval_tree implementation. */
result = $sqrt(0);
if (result != 0.0) begin
$display("Failed with 0, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $sqrt(0.0);
if (result != 0.0) begin
$display("Failed with 0.0, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $sqrt(4);
if (result != 2.0) begin
$display("Failed with 4, expected 2.0, got %f", result);
pass = 1\'b0;
end
result = $sqrt(4.0);
if (result != 2.0) begin
$display("Failed with 4.0, expected 2.0, got %f", result);
pass = 1\'b0;
end
result = $ln(1);
if (result != 0.0) begin
$display("Failed with $ln, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $log10(10);
if (result != 1.0) begin
$display("Failed with $log10, expected 1.0, got %f", result);
pass = 1\'b0;
end
result = $exp(0);
if (result != 1.0) begin
$display("Failed with $exp, expected 1.0, got %f", result);
pass = 1\'b0;
end
result = $floor(1.5);
if (result != 1.0) begin
$display("Failed with $floor, expected 1.0, got %f", result);
pass = 1\'b0;
end
result = $ceil(1.5);
if (result != 2.0) begin
$display("Failed with $ceil, expected 2.0, got %f", result);
pass = 1\'b0;
end
result = $sin(0);
if (result != 0.0) begin
$display("Failed with $sin, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $cos(0);
if (result != 1.0) begin
$display("Failed with $cos, expected 1.0, got %f", result);
pass = 1\'b0;
end
result = $tan(0);
if (result != 0.0) begin
$display("Failed with $tan, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $asin(0);
if (result != 0.0) begin
$display("Failed with $asin, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $acos(1);
if (result != 0.0) begin
$display("Failed with $acos, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $atan(0);
if (result != 0.0) begin
$display("Failed with $atan, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $sinh(0);
if (result != 0.0) begin
$display("Failed with $sinh, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $cosh(0);
if (result != 1.0) begin
$display("Failed with $cosh, expected 1.0, got %f", result);
pass = 1\'b0;
end
result = $tanh(0);
if (result != 0.0) begin
$display("Failed with $tanh, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $asinh(0);
if (result != 0.0) begin
$display("Failed with $asinh, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $acosh(1);
if (result != 0.0) begin
$display("Failed with $acosh, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $atanh(0);
if (result != 0.0) begin
$display("Failed with $atanh, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $pow(-2, 2);
if (result != 4.0) begin
$display("Failed with $pow, expected 4.0, got %f", result);
pass = 1\'b0;
end
result = $atan2(0, 0);
if (result != 0.0) begin
$display("Failed with $atan2, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $hypot(-1, 0);
if (result != 1.0) begin
$display("Failed with $hypot, expected 1.0, got %f", result);
pass = 1\'b0;
end
/* Test the CA statements and the vpi implementation. */
rin = -1;
#1 if (out !== 8\'bx) begin
$display("Failed CA (int) with -1.0, expected \'bx, got %d", out);
pass = 1\'b0;
end
if (!(rout != rout)) begin
$display("Failed CA (real) with -1.0, expected NaN, got %f", rout);
pass = 1\'b0;
end
rin = 4.0;
#1 if (out !== 2) begin
$display("Failed CA (int) with 4.0, expected 2, got %d", out);
pass = 1\'b0;
end
if (rout != 2.0) begin
$display("Failed CA (real) with 4.0, expected 2.0, got %f", rout);
pass = 1\'b0;
end
// Run time generated.
rin = -1.0;
result = $sqrt(rin);
if (!(result != result)) begin
$display("Failed run time with -1.0, expected NaN got %f", result);
pass = 1\'b0;
end
rin = 1.0;
result = $ln(rin);
if (result != 0.0) begin
$display("Failed run time $ln, expected 0.0, got %f", result);
pass = 1\'b0;
end
rin = 10.0;
result = $log10(rin);
if (result != 1.0) begin
$display("Failed run time $log10, expected 1.0, got %f", result);
pass = 1\'b0;
end
rin = 0.0;
result = $exp(rin);
if (result != 1.0) begin
$display("Failed run time $exp, expected 1.0, got %f", result);
pass = 1\'b0;
end
rin = 1.5;
result = $floor(rin);
if (result != 1.0) begin
$display("Failed run time $floor, expected 1.0, got %f", result);
pass = 1\'b0;
end
result = $ceil(rin);
if (result != 2.0) begin
$display("Failed run time $ceil, expected 2.0, got %f", result);
pass = 1\'b0;
end
rin = 0.0;
result = $sin(rin);
if (result != 0.0) begin
$display("Failed run time $sin, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $cos(rin);
if (result != 1.0) begin
$display("Failed run time $cos, expected 1.0, got %f", result);
pass = 1\'b0;
end
result = $tan(rin);
if (result != 0.0) begin
$display("Failed run time $tan, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $asin(rin);
if (result != 0.0) begin
$display("Failed run time $asin, expected 0.0, got %f", result);
pass = 1\'b0;
end
rin = 1.0;
result = $acos(rin);
if (result != 0.0) begin
$display("Failed run time $acos, expected 0.0, got %f", result);
pass = 1\'b0;
end
rin = 0.0;
result = $atan(rin);
if (result != 0.0) begin
$display("Failed run time $atan, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $sinh(rin);
if (result != 0.0) begin
$display("Failed run time $sinh, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $cosh(rin);
if (result != 1.0) begin
$display("Failed run time $cosh, expected 1.0, got %f", result);
pass = 1\'b0;
end
result = $tanh(rin);
if (result != 0.0) begin
$display("Failed run time $tanh, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $asinh(rin);
if (result != 0.0) begin
$display("Failed run time $asinh, expected 0.0, got %f", result);
pass = 1\'b0;
end
rin = 1.0;
result = $acosh(rin);
if (result != 0.0) begin
$display("Failed run time $acosh, expected 0.0, got %f", result);
pass = 1\'b0;
end
rin = 0.0;
result = $atanh(rin);
if (result != 0.0) begin
$display("Failed run time $atanh, expected 0.0, got %f", result);
pass = 1\'b0;
end
rin = 2.0;
result = $pow(-2, rin);
if (result != 4.0) begin
$display("Failed run time $pow, expected 4.0, got %f", result);
pass = 1\'b0;
end
rin = 0.0;
result = $atan2(0, rin);
if (result != 0.0) begin
$display("Failed run time $atan2, expected 0.0, got %f", result);
pass = 1\'b0;
end
result = $hypot(-1, rin);
if (result != 1.0) begin
$display("Failed run time $hypot, expected 1.0, got %f", result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* This is a post-wynthesis test for the blif01a.v test. Run this
* simulation in these steps:
*
* $ iverilog -tblif -o foo.blif blif01a.v
* $ abc
* abc 01> read_blif foo.blif
* abc 02> write_verilog foo.v
* abc 03> quit
* $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v
* $ vvp foo.vvp
*/
module main;
parameter WID = 4;
reg [WID-1:0] A, B;
wire [WID:0] Q;
subN usum(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]),
\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]),
\t .\\Q[4] (Q[4]), .\\Q[3] (Q[3]), .\\Q[2] (Q[2]), .\\Q[1] (Q[1]), .\\Q[0] (Q[0]));
int\t\t adx;
int\t\t bdx;
initial begin
for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
\t A <= adx[WID-1:0];
\t B <= bdx[WID-1:0];
\t #1 if (Q !== (adx[WID-1:0]-bdx[WID-1:0])) begin
\t $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q);
\t $finish;
\t end
\t end
end
$display("PASSED");
end
endmodule // main
|
module test();
string str1 = "abcd";
string str2 = "efgh";
typedef bit [31:0] vector;
vector data[1:0];
initial begin
data[0] = vector\'(str1);
data[1] = vector\'(str2);
$display("%s %s", data[0], data[1]);
if (data[0] === "abcd" && data[1] === "efgh")
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
`begin_keywords "1364-2005"
module test();
reg signed [15:0] a;
reg signed [7:0] b;
reg signed [31:0] expect;
wire signed [31:0] actual;
reg signed [127:0] long_x;
real real_x;
assign actual = a ** b;
initial begin
for (a = -32768; a < 32767; a = a + 1) begin:outer_loop
long_x = 1;
for (b = 0; b < 127; b = b + 1) begin:inner_loop
real_x = $itor(a) ** $itor(b);
if (real_x < 0.0) real_x = -real_x;
if (real_x >= 2.0**128.0) disable outer_loop;
expect = long_x;
#0; // wait for net propagation
if (actual !== expect) begin
$display("FAILED : %0d ** %0d = %0d not %0d", a, b, expect, actual);
$finish;
end
long_x = long_x * a;
end
end
$display("PASSED");
end
endmodule
`end_keywords
|
// Check that it is possible to call a package scoped function with empty
// positional arguments.
package P;
function integer T(integer x = 1, integer y = 2);
return x + y;
endfunction
endpackage
module test;
initial begin
integer x;
x = P::T(, 4);
if (x === 5) begin
$display("PASSED");
end else begin
$display("FAILED. x = %d, expected 5", x);
end
end
endmodule
|
//
// Copyright (c) 2001 Ed Schwartz ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Verify PR142 - Added something to print PASSED..
module testit;
reg clk;
reg [2:0] cnt;
always
begin
# 50 clk = ~clk;
end // always begin
task idle;
input [15:0] waitcnt;
begin: idletask
// begin
integer i;
for (i=0; i < waitcnt; i = i + 1)
begin
@ (posedge clk);
end // for (i=0; i < waitcnt; i = i + 1)
end
endtask // idle
initial begin
clk = 0;
cnt = 0;
$display ("One");
cnt = cnt + 1;
idle(3);
cnt = cnt + 1;
$display ("Two");
if(cnt === 2)
$display("PASSED");
else
$display("FAILED");
$finish;
end
endmodule
|
//
// Copyright (c) 2000 Steve Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// for3.16A - Template 1 - for(val1=0; val1 <= expr ; val1 = val1 + 1) some_action
//
module test ;
reg [3:0] val1;
reg [3:0] val2;
initial
begin
val2 = 0;
for(val1 = 0; val1 <= 4\'ha; val1 = val1+1)
begin
val2 = val2 + 1;
end
if(val2 === 4\'hb)
$display("PASSED");
else
begin
$display("FAILED val2 s/b 4\'ha, but is %h",val2);
end
end
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: task_scope.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $
// $Log: task_scope.v,v $
// Revision 1.1 2001/06/19 13:52:13 ka6s
// Added 4 tests from Stephan Boettcher
//
// Test for task scope lookup in VVP
module test;
wire w;
jobs j(w);
task ini;
begin
\t j.set(1\'bz);
end
endtask
initial
begin
\tini;
\t#1;
\tj.set(1\'b1);
\t#1;
\tif (w===1)
\t $display("PASSED");
\telse
\t $display("FAILED");
end
endmodule // test
module jobs (out);
output out;
reg\t out;
task set;
input val;
begin
\t #1 out = val;
end
endtask
endmodule // jobs
|
module test ();
reg pass = 1\'b1;
reg d;
real a = 0.0;
wire real f = a;
always @(d) force f = 0.0;
initial begin
// Verify the initial value.
#1;
if (f != 0.0) begin
$display("Failed initial value, expected 0.0, got %f", f);
pass = 1\'b0;
end
// Verify the value can change.
#1 a = 1.0;
if (f != 1.0) begin
$display("Failed value change, expected 1.0, got %f", f);
pass = 1\'b0;
end
// Verify that the force changed the value and that the CA is blocked.
#1 d = 0;
#1 a = 1.0;
if (f != 0.0) begin
$display("Failed force holding, expected 0.0, got %f", f);
pass = 1\'b0;
end
// Verify that the release propagates the CA value.
#1 release f;
if (f != 1.0) begin
$display("Failed release change, expected 1.0, got %f", f);
pass = 1\'b0;
end
// Verify that the value can be changed after a release.
#1 a = 0.0;
if (f != 0.0) begin
$display("Failed release, expected 0.0, got %f", f);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Copyright (c) 2002\tMichael Ruff (mruff at chiaro.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module lvl2;
reg r;
time t;
event e;
integer i;
task t_my;
\tr = 1'b0;
endtask
function f_my;
\tinput in;
begin
\tf_my = !in;
end
endfunction
initial begin: init
\tt_my;
\tr = f_my(r);
\tr = f_my(i);
\tr = f_my(t);
\t->e;
end
endmodule
module lvl1;
lvl2 lvl2();
endmodule
module top0;
reg r;
time t;
event e;
integer i;
task t_my;
\tr = 1'b0;
endtask
function f_my;
\tinput in;
begin
\tf_my = !in;
end
endfunction
initial begin: init
\tt_my;
\tr = f_my(r);
\tr = f_my(i);
\tr = f_my(t);
\t->e;
end
lvl1 lvl1_0();
lvl1 lvl1_1();
endmodule
module top1;
initial begin: init
\t$test;
end
endmodule
|
// Check that it is possible to declare the data type for an integer type task
// port separately from the direction for non-ANSI style port declarations.
module test;
task t;
input x;
integer x;
if (x == 10 && $bits(x) == $bits(integer)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t(10);
endmodule
|
// Check that declaring a queue typed member in a packed union is an
// error.
module test;
union packed {
int x[$];
} s;
initial begin
$display("FAILED");
end
endmodule
|
// Incomplete case statements in asynchronous logic are dangerous in
// synthesisable code, as in real hardware the inferred latch will be
// sensitive to glitches as the case select value changes. Check that
// the compiler outputs a warning for this.
module mux(
input wire [2:0] sel,
input wire [2:0] i1,
input wire [2:0] i2,
input wire [2:0] i3,
input wire [2:0] i4,
output reg [2:0] o
);
(* ivl_synthesis_on *)
always @* begin
case (sel)
0 : o = 0;
1 : o = i1;
2 : o = i2;
3 : o = i3;
4 : o = i4;
endcase
end
(* ivl_synthesis_off *)
initial $display("PASSED");
endmodule
|
// Check that the var keyword is supported for module non-ANSI input ports
bit failed = 1\'b0;
`define check(val, exp) \\
if (val !== exp) begin \\
$display("FAILED(%0d). \'%s\' expected %b, got %b", `__LINE__, `"val`", val, exp); \\
failed = 1\'b1; \\
end
module M(x, y, z, w);
parameter VAL_X = 0;
parameter VAL_Y = 0;
parameter VAL_Z = 0;
parameter VAL_W = 0;
input var x;
input var [7:0] y;
input var signed [7:0] z;
input var logic [7:0] w;
initial begin
`check(x, VAL_X)
`check(y, VAL_Y)
`check(z, VAL_Z)
`check(w, VAL_W)
end
endmodule
module test;
M #(
.VAL_X (1\'b1),
.VAL_Y (8\'d10),
.VAL_Z (-8\'sd1),
.VAL_W (8\'d20)
) i_m1 (
.x (1\'b1),
.y (8\'d10),
.z (-8\'sd1),
.w (8\'d20)
);
// When unconnected it should default to x, rather z
M #(
.VAL_X (1\'bx),
.VAL_Y (8\'hx),
.VAL_Z (8\'hx),
.VAL_W (8\'hx)
) i_m2 ();
initial begin
#1
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
// Copyright (c) 2014 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for casting a string to a vector type.
module sv_cast_string();
string str;
typedef logic [55:0] strbits;
strbits chars;
initial begin
int i;
str = "0123456";
chars = strbits\'(str);
if(chars != 56\'h30313233343536)
begin
$display("FAILED 1 chars = %x", chars);
$finish();
end
str = "6543210";
chars = strbits\'(str);
if(chars != "6543210")
begin
$display("FAILED 2 chars = %x", chars);
$finish();
end
str = "wrong string";
// Vector to string casting
str = string\'(chars);
if(str != "6543210")
begin
$display("FAILED 3 str = %s", str);
$finish();
end
$display("PASSED");
end
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.