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/* PR1625912 */
/*
* Substatuting in either of the commented out lines caused VVP to fail.
*/
module top;
integer cnt;
real result, win;
initial begin
cnt = -10;
for (result=-10; result<=10; result=result+2) begin
\t #1 if (result != cnt) begin
\t $display("FAILED -- cnt=%0d, result=%f", cnt, result);
\t end
\t cnt = cnt + 2;
end
$display("PASSED");
$finish;
end
endmodule
|
module top;
logic passed;
logic [7:0] y;
logic [7:0] yv;
logic [39:0] a;
logic [3:0][9:0] t;
int idx;
assign t = a;
assign y = t[1][9-:8];
assign yv = t[1][idx-:8];
initial begin
passed = 1\'b1;
idx = 9;
a = {10\'h3ff, 10\'h2a5, 10\'h000};
#1;
if (y != 8\'ha9) begin
$display("FAILED: expected 8\'ha9 for constant select, got %h." , y);
passed = 1\'b0;
end
if (yv != 8\'ha9) begin
$display("FAILED: expected 8\'ha9 for variable select, got %h." , yv);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
/* Copyright (C) 2000 Stephen G. Tell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
/* fdisplay3 - check that $fdisplay rejects bogus first arguments */
module fdisplay3;
initial begin
// This error is now caught at compile time so this message will not
// be printed.
//
// $display("expect compile or runtime error from bad $fdisplay args:");
$fdisplay(fdisplay3, "bogus message");
$finish;
end // initial begin
endmodule
|
///////////////////////////////////////////////////////////////////////////
//
// To test:
// (a) The use & representation of time variables
// (b) The display of time variables
//
// Compile and run the program
// iverilog tt_clean.v
// vvp a.out
//
// VISUALLY INSPECT the displays. (There ain\'t no way to automate this)
//
///////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
`define\tPCI_CLK_PERIOD\t\t15.0\t\t// 66 Mhz
module top;
reg PCI_Clk;
reg fail;
initial PCI_Clk <= 0;
always #(`PCI_CLK_PERIOD/2) PCI_Clk <= ~PCI_Clk;
initial begin
fail = 0;
$display("\
\\t\\t==> CHECK THIS DISPLAY ==>\
");
$display("pci_clk_period:\\t\\t\\t %0d",`PCI_CLK_PERIOD);
$display("pci_clk_period:\\t\\t\\t %0t",`PCI_CLK_PERIOD);
if($time !== 0) fail = 1;
if (fail == 1)
$display("$time=%0d (0)", $time);
delay_pci(3);
if($simtime !== 4500) fail = 1;
if($time !== 45) fail = 1;
if (fail == 1)
$display("$time=%0d (45)", $time);
#15;
if($simtime !== 6000) fail = 1;
if($time !== 60) fail = 1;
#(`PCI_CLK_PERIOD);
if($simtime !== 7500) fail = 1;
if($time !== 75) fail = 1;
#(`PCI_CLK_PERIOD *2);
if($simtime !== 10500) fail = 1;
if($time !== 105) fail = 1;
$timeformat(-9,2,"ns",20);
$display("after setting timeformat:");
$display("pci_clk_period:\\t\\t\\t %0d",`PCI_CLK_PERIOD);
$display("pci_clk_period:\\t\\t\\t %0t",`PCI_CLK_PERIOD);
delay_pci(3);
if($simtime !== 15000) fail = 1;
if($time !== 150) fail = 1;
#15;
if($simtime !== 16500) fail = 1;
if($time !== 165) fail = 1;
#(`PCI_CLK_PERIOD);
if($simtime !== 18000) fail = 1;
if($time !== 180) fail = 1;
#(`PCI_CLK_PERIOD *2);
if($simtime !== 21000) fail = 1;
if($time !== 210) fail = 1;
$display("\\t\\t**********************************************");
if(fail) $display("\\t\\t****** time representation test BAD *******");
else $display("\\t\\t****** time representation test OK *******");
$display("\\t\\t**********************************************\
");
$finish(0);
end
task delay_pci;
input delta;
integer delta;
integer ii;
begin
#(`PCI_CLK_PERIOD * delta);
end
endtask
endmodule
|
module top;
reg pass;
reg result;
reg [3:0] expr;
initial begin
pass = 1\'b1;
result = $onehot(1\'b0);
if (result != 0) begin
$display("FAILED: for 1\'b0 expected 0, got %b", result);
pass = 1\'b0;
end
result = $onehot(1\'b1);
if (result != 1) begin
$display("FAILED: for 1\'b1 expected 1, got %b", result);
pass = 1\'b0;
end
result = $onehot(2\'b01);
if (result != 1) begin
$display("FAILED: for 2\'b01 expected 1, got %b", result);
pass = 1\'b0;
end
result = $onehot(4\'b0x11);
if (result != 0) begin
$display("FAILED: for 4\'b0x11 expected 0, got %b", result);
pass = 1\'b0;
end
expr = 4\'b1100;
result = $onehot(expr);
if (result != 0) begin
$display("FAILED: for 4\'b1100 expected 0, got %b", result);
pass = 1\'b0;
end
result = $onehot(34\'b1100000000000000000000000000000001);
if (result != 0) begin
$display("FAILED: for 34\'1100000000000000000000000000000001 expected 0, got %b", result);
pass = 1\'b0;
end
result = $onehot(34\'b1000000000000000000000000000000000);
if (result != 1) begin
$display("FAILED: for 34\'1000000000000000000000000000000000 expected 1, got %b", result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`timescale 1ns/10ps
module top;
reg topvar;
initial begin
topvar = 0;
lwr.lowervar = 1;
lwr.elwr.evenlowervar = 0;
othertop.othertopvar = 1;
#10 $display("%m var is (%b)", topvar);
end
lower lwr();
endmodule
module lower;
reg lowervar;
initial begin
#11 $display("%m var is (%b)", lowervar);
end
evenlower elwr();
endmodule
module evenlower;
reg evenlowervar;
initial begin
#12 $display("%m var is (%b)", evenlowervar);
$display("Up reference to me (%b)", elwr.evenlowervar);
$display("Up reference to parent (%b)", lwr.lowervar);
$display("Up reference is (%b)", lower.lowervar);
end
endmodule
module othertop;
reg othertopvar;
initial begin
#20 $display("%m var is (%b)", othertopvar);
end
endmodule
|
`timescale 1ns/1ns
`define DAC_MSB 7
`define ADC_MSB 15
`define NSEC 1
`define USEC (`NSEC*1000)
`define MSEC (`USEC*1000)
// TOPLEVEL TO STIMULATE
module toy_toplevel(
\t input wire [`ADC_MSB:0]\tV_load_adc,
\t input wire\t\t\tV_load_valid,
\t output reg\t\t\tpwm,
\t output reg [`DAC_MSB:0]\tV_src
\t ) ;
\tparameter time STARTUP_DELAY = 2 * `MSEC;
\tparameter real ADC_RANGE = 32.0;
\tparameter real ADC_OFFSET = -ADC_RANGE/2.0;
\tparameter real DAC_RANGE = 16.0;
\tparameter real DAC_OFFSET = -DAC_RANGE/2.0;
\tparameter real UPDATE_FREQ_MHZ = 1.0;
\tparameter time CLOCK_INTERVAL = `USEC / UPDATE_FREQ_MHZ;
\treg clk = 0;
\treg ls_only = 0;
\treal V_load = 0.0;
\tfunction real decode_value( input real base, input real range, input integer msb, input integer value );
\tbegin
\t\tdecode_value = base + range * value / $itor(1<< (msb+1));
\tend
\tendfunction
\tfunction integer encode_value( input real base, input real range, input integer msb, input real value );
\tbegin
\t\tencode_value = (value -base) * $itor(1<< (msb+1)) / range;
\tend
\tendfunction
\talways @( posedge(V_load_valid) )
\tbegin
\t\tV_load = decode_value( ADC_OFFSET, ADC_RANGE, `ADC_MSB, V_load_adc );
\tend
\tinitial
\tbegin
\t\tclk = 0;
\t\tls_only = 0;
\t\t#( `USEC * 1 );
\t\t# ( CLOCK_INTERVAL/4 );
\t\t$finish(0); // Stop things for VPI unit test...
\t\tforever
\t\tbegin
\t\t\t# ( CLOCK_INTERVAL/2 );
\t\t\tclk <= ! clk;
\t\tend
\tend
\talways @clk
\tbegin
\t\tls_only= (V_load >2.5);
\t\tpwm <= clk | ls_only;
\tend
\tinitial
\tbegin
\t V_src = encode_value( DAC_OFFSET, DAC_RANGE, `DAC_MSB, 7.2 );
\tend
endmodule
|
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This sample demonstrates the post 20030904 Icarus Verilog feature
* where combinational blocks with time-0 races against the rest of
* the design can be resolved.
*
* The always @(foo) threads should be detected by the compiler as
* combinational, and should be pushed to the front of the time-0
* scheduling queue. This causes the threads to enter the wait early
* so that it can detect the change from x to 1 for its value.
*
* The program HAS a time-0 race according to the IEEE1364 standard,
* but Icarus Verilog as an extension resolves this race intentionally
* as described.
*/
module main;
reg foo, bar;
reg foo_ok = 0, bar_ok = 0;
initial foo = 1;
always @(foo) begin
if (foo !== 1\'b1) begin
\t $display("FAILED --(foo = %b)", foo);
\t $finish;
end
foo_ok = 1;
end
always @(bar) begin
if (bar !== 1\'b1) begin
\t $display("FAILED --(bar = %b)", bar);
\t $finish;
end
bar_ok = 1;
end
initial bar = 1;
initial begin
#1 if (foo_ok !== 1) begin
\t $display("FAILED -- foo lost the race");
\t $finish;
end
if (bar_ok !== 1) begin
\t $display("FAILED -- bar lost the race");
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module top;
reg passed = 1\'b1;
real rvar [1:0];
initial begin
#1;
rvar[0] = -1.0;
if (rvar[0] != -1.0) begin
$display("Failed: real array[0], expected -1.0, got %g", rvar[0]);
passed = 1\'b0;
end
rvar[1] = 2.0;
if (rvar[1] != 2.0) begin
$display("Failed: real array[1], expected 2.0, got %g", rvar[1]);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
module top;
event evt;
reg rval;
// Call user function with event (continuous assign).
wire wval = func(evt);
function func;
input arg;
begin
$display("FAILED func.");
func = 1\'bx;
end
endfunction
task tsk;
input arg;
begin
$display("FAILED task.");
end
endtask
// Call user function with event (procedural) and user task.
initial begin
rval = func(evt);
tsk(evt);
end
endmodule
|
// test that .* implicit ports work
module m(input a, output b, output c);
assign b = a;
assign c = ~a;
endmodule
module top;
reg a;
wire b, d;
m foo(.*, .c(d));
initial begin
a = 0;
#1 if (b !== a || d !== ~a) begin
$display("FAILED -- a=%b, b=%b, d=%b", a, b, d);
end
#1 a = 1;
#1 if (b !== a || d !== ~a) begin
$display("FAILED -- a=%b, b=%b, d=%b", a, b, d);
end
$display("PASSED");
end
endmodule
|
module top;
parameter parg0 = 0.0;
parameter parg1 = 1.0;
parameter parg2 = 2.0;
parameter pargi = 1.0/0.0; // Inf.
parameter pargn = $sqrt(-1.0); // NaN.
real arg0, arg1, arg2, argi, argn;
reg result, pass;
initial begin
pass = 1\'b1;
arg0 = 0.0;
arg1 = 1.0;
arg2 = 2.0;
argi = 1.0/0.0; // Inf.
argn = $sqrt(-1.0); // NaN.
/* Check ! on a constant real value. */
result = !parg0;
if (result !== 1\'b1) begin
$display("Failed: constant !0.0, expected 1\'b1, got %b", result);
pass = 1\'b0;
end
result = !parg1;
if (result !== 1\'b0) begin
$display("Failed: constant !1.0, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = !parg2;
if (result !== 1\'b0) begin
$display("Failed: constant !2.0, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = !pargi;
if (result !== 1\'b0) begin
$display("Failed: constant !Inf, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = !pargn;
if (result !== 1\'b0) begin
$display("Failed: constant !NaN, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
/* Check ! on a real variable. */
result = !arg0;
if (result !== 1\'b1) begin
$display("Failed: !0.0, expected 1\'b1, got %b", result);
pass = 1\'b0;
end
result = !arg1;
if (result !== 1\'b0) begin
$display("Failed: !1.0, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = !arg2;
if (result !== 1\'b0) begin
$display("Failed: !2.0, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = !argi;
if (result !== 1\'b0) begin
$display("Failed: !Inf, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = !argn;
if (result !== 1\'b0) begin
$display("Failed: !NaN, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
/* Check && on a constant real value. */
result = parg0 && parg1;
if (result !== 1\'b0) begin
$display("Failed: constant 0.0 && 1.0, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = parg0 && parg2;
if (result !== 1\'b0) begin
$display("Failed: constant 0.0 && 2.0, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = parg1 && parg2;
if (result !== 1\'b1) begin
$display("Failed: constant 1.0 && 2.0, expected 1\'b1, got %b", result);
pass = 1\'b0;
end
/* Check && on a real variable. */
result = arg0 && arg1;
if (result !== 1\'b0) begin
$display("Failed: 0.0 && 1.0, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = arg0 && arg2;
if (result !== 1\'b0) begin
$display("Failed: 0.0 && 2.0, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = arg1 && arg2;
if (result !== 1\'b1) begin
$display("Failed: 1.0 && 2.0, expected 1\'b1, got %b", result);
pass = 1\'b0;
end
/* Check || on a constant real value. */
result = parg0 || 0;
if (result !== 1\'b0) begin
$display("Failed: constant 0.0 || 0, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = parg0 || parg1;
if (result !== 1\'b1) begin
$display("Failed: constant 0.0 || 1.0, expected 1\'b1, got %b", result);
pass = 1\'b0;
end
result = parg0 || parg2;
if (result !== 1\'b1) begin
$display("Failed: constant 0.0 || 2.0, expected 1\'b1, got %b", result);
pass = 1\'b0;
end
/* Check || on a real variable. */
result = arg0 || 0;
if (result !== 1\'b0) begin
$display("Failed: 0.0 || 0, expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = arg0 || arg1;
if (result !== 1\'b1) begin
$display("Failed: 0.0 || 1.0, expected 1\'b1, got %b", result);
pass = 1\'b0;
end
result = arg0 || arg2;
if (result !== 1\'b1) begin
$display("Failed: 0.0 || 2.0, expected 1\'b1, got %b", result);
pass = 1\'b0;
end
/* Check the ternary with a constant real cond. value. */
result = parg0 ? 1\'b1 : 1\'b0;
if (result !== 1\'b0) begin
$display("Failed: constant 0.0 ? ..., expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = parg1 ? 1\'b1 : 1\'b0;
if (result !== 1\'b1) begin
$display("Failed: constant 1.0 ? ..., expected 1\'b1, got %b", result);
pass = 1\'b0;
end
result = parg2 ? 1\'b1 : 1\'b0;
if (result !== 1\'b1) begin
$display("Failed: constant 2.0 ? ..., expected 1\'b1, got %b", result);
pass = 1\'b0;
end
result = pargi ? 1\'b1 : 1\'b0;
if (result !== 1\'b1) begin
$display("Failed: constant Inf ? ..., expected 1\'b1, got %b", result);
pass = 1\'b0;
end
result = pargn ? 1\'b1 : 1\'b0;
if (result !== 1\'b1) begin
$display("Failed: constant NaN ? ..., expected 1\'b1, got %b", result);
pass = 1\'b0;
end
/* Check the ternary with a real cond. variable. */
result = arg0 ? 1\'b1 : 1\'b0;
if (result !== 1\'b0) begin
$display("Failed: 0.0 ? ..., expected 1\'b0, got %b", result);
pass = 1\'b0;
end
result = arg1 ? 1\'b1 : 1\'b0;
if (result !== 1\'b1) begin
$display("Failed: 1.0 ? ..., expected 1\'b1, got %b", result);
pass = 1\'b0;
end
result = arg2 ? 1\'b1 : 1\'b0;
if (result !== 1\'b1) begin
$display("Failed: 2.0 ? ..., expected 1\'b1, got %b", result);
pass = 1\'b0;
end
result = argi ? 1\'b1 : 1\'b0;
if (result !== 1\'b1) begin
$display("Failed: Inf ? ..., expected 1\'b1, got %b", result);
pass = 1\'b0;
end
result = argn ? 1\'b1 : 1\'b0;
if (result !== 1\'b1) begin
$display("Failed: NaN ? ..., expected 1\'b1, got %b", result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module top;
reg pass = 1\'b1;
reg [1:0] in;
wire out;
function IS_NOT_ZERO;
input [3:0] in;
begin
IS_NOT_ZERO = |in;
end
endfunction
assign out = (IS_NOT_ZERO(in) == 1\'b1);
initial begin
in = 2\'b00;
#1 if (out != 1\'b0) begin
$display("Failed for 2\'b00 case.");
pass = 1\'b0;
end
in = 2\'b01;
#1 if (out != 1\'b1) begin
$display("Failed for 2\'b01 case.");
pass = 1\'b0;
end
in = 2\'b10;
#1 if (out != 1\'b1) begin
$display("Failed for 2\'b01 case.");
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Check that it is an error to declare a non-ANSI module port with implicit
// packed dimensions if it is later redeclared as a packed array typed variable.
// Even if the size of the packed dimensions matches that of the size of the
// packed array.
typedef reg [7:0] T1;
typedef T1 [3:0] T2;
module test(x);
output [31:0] x;
T2 x;
initial begin
$display("FAILED");
end
endmodule
|
// Check a global timeprecision that is too large.
`resetall
timeunit 1ns;
timeprecision 10ns;
module gtp_large;
endmodule
|
module main;
reg [7:0] period;
reg\t drive;
wire trace;
// This is the main point of the test. Non-constant delay expressions
// should work here.
assign #(period) trace = drive;
initial begin
period = 8;
// Initially, set up a period=8 and get the trace to start
// following the drive.
#1 drive <= 1;
#9 if (trace !== drive) begin
\t $display("FAILED -- time=%0t, drive=%b, trace=%b",
\t\t $time, drive, trace);
\t $finish;
end
// The drive should NOT change the trace before the period.
drive <= 0;
#7 if (trace !== 1\'b1) begin
\t $display("FAILED -- time=%0t, drive=%b, trace=%b",
\t\t $time, drive, trace);
\t $finish;
end
#2 if (trace !== drive) begin
\t $display("FAILED -- time=%0t, drive=%b, trace=%b",
\t\t $time, drive, trace);
\t $finish;
end
// Change the period.
period = 6;
// Now check that the new delay is taken.
#1 drive <= 1;
#5 if (trace !== 1\'b0) begin
\t $display("FAILED -- time=%0t, drive=%b, trace=%b",
\t\t $time, drive, trace);
\t $finish;
end
#2 if (trace !== drive) begin
\t $display("FAILED -- time=%0t, drive=%b, trace=%b",
\t\t $time, drive, trace);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
module top;
wire [2:-1] vec;
integer idx;
initial begin
idx = 'bx;
force vec[idx] = 1'b1;
release vec[idx];
end
endmodule
|
module top;
integer ival=-1;
initial begin
$display("The value is %5.2f", ival);
$display("The value is %5.2f", -1);
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
module br985_test;
logic [3:0] sel;
logic value, spi_sdo;
bug3 dut(sel, value, spi_sdo);
initial begin
int i;
sel = 4\'b0000;
#1 if(spi_sdo !== 1\'b1)
begin
$display("FAILED");
$finish();
end
for(i = 1; i < 16; i = i + 1)
begin
sel = i;
#1 if(spi_sdo !== 1\'b0)
begin
$display("FAILED");
$finish();
end
end
$display("PASSED");
end
endmodule
|
module top;
reg passed;
reg [9*8:1] check;
reg [71:0] value;
reg [7:0] nval;
real rval;
initial begin
passed = 1\'b1;
// Look for the hex value using a runtime string.
check = "hex=%h";
if (! $value$plusargs(check, value)) begin
$display("FAILED: Unable to get hex value.");
passed = 1\'b0;
end
if (value !== 72\'h0123456789abcdefxz) begin
$display("FAILED: expected hex value 72\'h0123456789abcdefxz, got %h",
value);
passed = 1\'b0;
end
// Look for a hex (x) value.
if (! $value$plusargs("hex=%x", value)) begin
$display("FAILED: Unable to get hex value.");
passed = 1\'b0;
end
if (value !== 72\'h0123456789abcdefxz) begin
$display("FAILED: expected hex value 72\'h0123456789abcdefxz, got %h",
value);
passed = 1\'b0;
end
// Look for an octal value.
if (! $value$plusargs("oct=%o", value)) begin
$display("FAILED: Unable to get octal value.");
passed = 1\'b0;
end
if (value !== 72\'o01234567xz) begin
$display("FAILED: expected octal value 72\'o01234567xz, got %o",
value);
passed = 1\'b0;
end
// Look for a binary value.
if (! $value$plusargs("bin=%b", value)) begin
$display("FAILED: Unable to get binary value.");
passed = 1\'b0;
end
if (value !== 72\'b0101xz) begin
$display("FAILED: expected binary value 72\'b0101xz, got %b",
value);
passed = 1\'b0;
end
// Look for a negative binary value.
if (! $value$plusargs("neg=%b", value)) begin
$display("FAILED: Unable to get negative binary value.");
passed = 1\'b0;
end
if (value !== 72\'hfffffffffffffffffc) begin
$display("FAILED: expected binary value 72\'hff...fc, got %h",
value);
passed = 1\'b0;
end
// Look for a negative octal value.
if (! $value$plusargs("neg=%o", value)) begin
$display("FAILED: Unable to get negative octal value.");
passed = 1\'b0;
end
if (value !== 72\'hffffffffffffffffc0) begin
$display("FAILED: expected octal value 72\'hff...fc0, got %h",
value);
passed = 1\'b0;
end
// Look for a truncated negative hex value.
if (! $value$plusargs("neg=%h", nval)) begin
$display("FAILED: Unable to get negative hex value.");
passed = 1\'b0;
end
if (nval !== 8\'h00) begin
$display("FAILED: expected hex value 8\'h00, got %h",
nval);
passed = 1\'b0;
end
// Look for a bad binary value.
if (! $value$plusargs("bad_num=%b", value)) begin
$display("FAILED: Unable to get bad binary value.");
passed = 1\'b0;
end
if (value !== \'bx) begin
$display("FAILED: expected bad binary value \'bx, got %d",
value);
passed = 1\'b0;
end
// Look for a bad octal value.
if (! $value$plusargs("bad_num=%o", value)) begin
$display("FAILED: Unable to get bad octal value.");
passed = 1\'b0;
end
if (value !== \'bx) begin
$display("FAILED: expected bad octal value \'bx, got %d",
value);
passed = 1\'b0;
end
// Look for a bad hex value.
if (! $value$plusargs("bad_num=%h", value)) begin
$display("FAILED: Unable to get bad hex value.");
passed = 1\'b0;
end
if (value !== \'bx) begin
$display("FAILED: expected bad hex value \'bx, got %d",
value);
passed = 1\'b0;
end
// Look for a bad hex (x) value.
if (! $value$plusargs("bad_num=%x", value)) begin
$display("FAILED: Unable to get bad hex (x) value.");
passed = 1\'b0;
end
if (value !== \'bx) begin
$display("FAILED: expected bad hex (x) value \'bx, got %d",
value);
passed = 1\'b0;
end
// Look for a decimal value.
if (! $value$plusargs("dec=%d", value)) begin
$display("FAILED: Unable to get decimal value.");
passed = 1\'b0;
end
if (value !== \'d0123456789) begin
$display("FAILED: expected decimal value \'d0123456789, got %d",
value);
passed = 1\'b0;
end
// Look for a negative decimal value.
if (! $value$plusargs("neg=%d", value)) begin
$display("FAILED: Unable to get negative decimal value.");
passed = 1\'b0;
end
if (value !== -100) begin
$display("FAILED: expected decimal value 72\'hff...fc0, got %h",
value);
passed = 1\'b0;
end
// Look for a bad decimal value.
if (! $value$plusargs("bad_num=%d", value)) begin
$display("FAILED: Unable to get bad decimal value.");
passed = 1\'b0;
end
if (value !== \'bx) begin
$display("FAILED: expected bad decimal value \'bx, got %d",
value);
passed = 1\'b0;
end
// Look for a decimal "x" value.
if (! $value$plusargs("dec_x=%d", value)) begin
$display("FAILED: Unable to get decimal \\"x\\" value.");
passed = 1\'b0;
end
if (value !== \'dx) begin
$display("FAILED: expected decimal value \'dx, got %d",
value);
passed = 1\'b0;
end
// Look for a decimal "z" value.
if (! $value$plusargs("dec_z=%d", value)) begin
$display("FAILED: Unable to get decimal \\"z\\" value.");
passed = 1\'b0;
end
if (value !== \'dz) begin
$display("FAILED: expected decimal value \'dz, got %d",
value);
passed = 1\'b0;
end
// Look for a real value.
if (! $value$plusargs("real=%f", rval)) begin
$display("FAILED: Unable to get real value.");
passed = 1\'b0;
end
if (rval != 12.3456789) begin
$display("FAILED: expected real value 12.3456789, got %f",
rval);
passed = 1\'b0;
end
// Look for a negative real value.
if (! $value$plusargs("neg_real=%f", rval)) begin
$display("FAILED: Unable to get a negative real value.");
passed = 1\'b0;
end
if (rval != -23456.0) begin
$display("FAILED: expected negative real value -23456.0, got %f",
rval);
passed = 1\'b0;
end
// Look for an infinite real value.
if (! $value$plusargs("real_inf=%f", rval)) begin
$display("FAILED: Unable to get infinite real value.");
passed = 1\'b0;
end
if (rval != 1.0/0.0) begin
$display("FAILED: expected infinite real value Inf, got %f",
rval);
passed = 1\'b0;
end
// Look for a bad real value.
if (! $value$plusargs("bad_num=%f", rval)) begin
$display("FAILED: Unable to get bad real value.");
passed = 1\'b0;
end
if (rval != 0.0) begin
$display("FAILED: expected bad real value 0.0, got %f",
rval);
passed = 1\'b0;
end
// Look for a warning real value.
if (! $value$plusargs("warn_real=%f", rval)) begin
$display("FAILED: Unable to get warning real value.");
passed = 1\'b0;
end
if (rval != 9.825) begin
$display("FAILED: expected warning real value 9.825, got %f",
rval);
passed = 1\'b0;
end
// Put a decimal value into a real based value.
if (! $value$plusargs("dec=%d", rval)) begin
$display("FAILED: Unable to get decimal (real) value.");
passed = 1\'b0;
end
if (rval != 123456789.0) begin
$display("FAILED: expected decimal as real value 12...89.0, got %f",
rval);
passed = 1\'b0;
end
// Put a negative decimal into a real based value.
if (! $value$plusargs("neg=%d", rval)) begin
$display("FAILED: Unable to get negative decimal (real) value.");
passed = 1\'b0;
end
if (rval != -100.0) begin
$display("FAILED: expected decimal as real value -100, got %f",
rval);
passed = 1\'b0;
end
// Put a real value into a bit based value.
if (! $value$plusargs("real=%f", value)) begin
$display("FAILED: Unable to get real (bit) value.");
passed = 1\'b0;
end
if (value !== 12) begin
$display("FAILED: expected real as bit value 12, got %d",
value);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
module dff (clk, d, q) ;
input d,clk;
output q;
reg q_out;
wire q;
specify
specparam tR_clk_q = 100,
tF_clk_q = 150;
(clk,d => q) = (tR_clk_q,tF_clk_q);
endspecify
always @(posedge clk)
q_out <= d;
buf u_buf (q,q_out);
endmodule
module test;
reg clk, d;
reg err;
time pos_lvl,neg_lvl;
dff u_dff (clk,d,q);
initial
begin
// $dumpfile("test.vcd");
// $dumpvars(0,test);
err = 0;
d = 0;
clk = 0;
#200;
clk = 1;
#200;
clk = 0;
#200;
clk = 1;
#200;
clk = 0;
#200;
clk = 1;
$display("pos_lvl=%t neg_lvl=%t",pos_lvl,neg_lvl);
if((pos_lvl != 700) && (neg_lvl != 350))
$display("FAILED");
else
$display("PASSED");
end
always @(posedge q)
pos_lvl = $time;
always @(negedge q)
neg_lvl = $time;
initial
begin
#250;
d = 1;
#450;
d = 0;
end
endmodule
|
// Check that localparam can not be overridden by defparam
module a;
localparam A = 1;
initial begin
$display("FAILED");
end
endmodule
module test;
a i_a();
defparam i_a.A = 10; // Error
endmodule
|
module main;
reg [1:0] src;
wire [3:0] dst, dst2, dst3;
foo_entity dut (.data_o(dst), .data_o2(dst2), .data_o3(dst3), .data_i(src));
initial begin
src = 2\'b00;
#1 if (dst != 4\'b0001 || dst2 != 4\'bxxxx || dst3 != 4\'bxxx) begin
\t $display("FAILED");
\t $finish;
end
src = 2\'b01;
#1 if (dst != 4\'b0010 || dst2 != 4\'b0101 || dst3 != 4\'b0011) begin
\t $display("FAILED");
\t $finish;
end
src = 2\'b10;
#1 if (dst != 4\'b0100 || dst2 != 4\'b0101 || dst3 != 4\'b1100) begin
\t $display("FAILED");
\t $finish;
end
src = 2\'b11;
#1 if (dst != 4\'b1000 || dst2 != 4\'b0101 || dst3 != 4\'b1100) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
`begin_keywords "1364-2005"
module top;
reg pass;
real rvar;
wire [3:0] var;
assign var = rvar;
initial begin
pass = 1\'b1;
rvar <= 1\'b0;
#1 rvar = 1\'b1;
#1 rvar = 2\'b10;
#1 rvar = 2\'b11;
#1 if (pass) $display("PASSED");
end
real_to_bit u1(rvar);
real_to_real u2(rvar);
real_to_real u3[1:0](rvar);
real_to_vec u4(rvar);
real_to_vec u5[1:0](rvar);
bit_to_real u6(var[0]);
vec_to_real u7(var);
vec_to_real u8[1:0](var);
endmodule
// Check a real value going to a single bit.
module real_to_bit (input wire in);
always @(in) if (in !== $stime%2) begin
$display("Failed real_to_bit %m at %1d, got %b, expected %2b",
$stime, in, $stime%2);
top.pass = 1\'b0;
end
endmodule
// Check a real value going to a real wire.
module real_to_real (input wire real in);
always @(in) if (in != $stime) begin
$display("Failed real_to_real %m at %1d, got %0d, expected %0d",
$stime, in, $stime);
top.pass = 1\'b0;
end
endmodule
// Check a real value going to multiple bit.
module real_to_vec (input wire [3:0] in);
always @(in) if (in !== $stime) begin
$display("Failed real_to_vec %m at %1d, got %0d, expected %0d",
$stime, in, $stime);
top.pass = 1\'b0;
end
endmodule
// Check a single bit going to a real wire.
module bit_to_real (input wire real in);
always @(in) if (in != $stime%2) begin
$display("Failed bit_to_real %m at %1d, got %0d, expected %0d",
$stime, in, $stime%2);
top.pass = 1\'b0;
end
endmodule
// Check a vector going to a real wire.
module vec_to_real (input wire real in);
always @(in) if (in != $stime) begin
$display("Failed vec_to_real %m at %1d, got %0d, expected %0d",
$stime, in, $stime);
top.pass = 1\'b0;
end
endmodule
`end_keywords
|
// Check that using the class new operator on a dynamic array variable results
// in an error.
module test;
int i[];
initial begin
i = new;
$display("FAILED");
end
endmodule
|
module mixed_width_case();
function [2:0] lookup1(input signed [2:0] value);
begin
case (value)
4\'sb0100 : lookup1 = 1;
3\'sb100 : lookup1 = 2;
2\'sb10 : lookup1 = 3;
default : lookup1 = 4;
endcase
$display("case = %d", lookup1);
end
endfunction
function [2:0] lookup2(input signed [2:0] value);
begin
case (value)
4\'b1100 : lookup2 = 1;
3\'sb100 : lookup2 = 2;
2\'sb10 : lookup2 = 3;
default : lookup2 = 4;
endcase
$display("case = %d", lookup2);
end
endfunction
function [2:0] lookup3(input real value);
begin
case (value)
4\'b0001 : lookup3 = 1;
3\'sb010 : lookup3 = 2;
2\'sb11 : lookup3 = 3;
default : lookup3 = 4;
endcase
$display("case = %d", lookup3);
end
endfunction
function [2:0] lookup4(input signed [2:0] value);
begin
case (value)
4\'b0110 : lookup4 = 1;
3\'sb110 : lookup4 = 2;
-1.0 : lookup4 = 3;
default : lookup4 = 4;
endcase
$display("case = %d", lookup4);
end
endfunction
reg [2:0] result;
reg failed = 0;
initial begin
result = lookup1(3\'sb100); if ( result != 2) failed = 1;
result = lookup1(3\'sb110); if ( result != 3) failed = 1;
result = lookup1(3\'sb010); if ( result != 4) failed = 1;
$display("");
result = lookup2(3\'sb100); if ( result != 2) failed = 1;
result = lookup2(3\'sb010); if ( result != 3) failed = 1;
result = lookup2(3\'sb110); if ( result != 4) failed = 1;
$display("");
result = lookup3( 1.0); if ( result != 1) failed = 1;
result = lookup3( 2.0); if ( result != 2) failed = 1;
result = lookup3(-1.0); if ( result != 3) failed = 1;
result = lookup3( 1.5); if ( result != 4) failed = 1;
$display("");
result = lookup4(3\'sb110); if ( result != 2) failed = 1;
result = lookup4(3\'sb111); if ( result != 3) failed = 1;
result = lookup4(3\'sb011); if ( result != 4) failed = 1;
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module top;
reg passed = 1\'b1;
reg [199:0] a, b;
wire [199:0] r;
assign #1 r = a ** b;
initial begin
a = \'d5;
b = \'d2; // A simple test.
#2;
if (r != \'d25) begin
$display("Failed: 5 ** 2 gave %d, expected 25", r);
passed = 1\'b0;
end
b = \'d55; // A 128 bit value.
#2;
if (r != 200\'d277555756156289135105907917022705078125) begin
$display("Failed: 5 ** 55\
gave %0d", r);
$display(" expected 277555756156289135105907917022705078125");
passed = 1\'b0;
end
b = \'d86; // A 200 bit value.
#2;
if (r != 200\'d1292469707114105741986576081359316958696581423282623291015625) begin
$display("Failed: 5 ** 55\
gave %0d", r);
$display(" expected 1292469707114105741986576081359316958696581423282623291015625");
passed = 1\'b0;
end
if (r != \'d5**\'d86) begin
$display("Failed: compile-time/run-time value mismatch.");
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
module test ();
wire [2:0] d [0:2];
reg [2:0] src[0:2];
genvar i;
for (i = 0 ; i < 3 ; i = i+1)
assign d[i] = src[i];
integer idx;
initial begin
for (idx = 0 ; idx < 3 ; idx = idx+1)
\tsrc[idx] = idx;
#1 for (idx = 0 ; idx < 3 ; idx = idx+1)
\tif (d[idx] !== idx) begin
\t $display("FAILED -- d[%0d] = %b", idx, d[idx]);
\t $finish;
\tend
$display("PASSED");
end // initial begin
endmodule
|
module test();
real r;
initial
begin
r=0.25;
$write("%f %b %f\
",r, $realtobits(r), $bitstoreal($realtobits(r)));
r=0.5;
$write("%f %b %f\
",r, $realtobits(r), $bitstoreal($realtobits(r)));
$display("neg reals don\'t work");
r=-0.25;
$write("%f %b %f\
",r, $realtobits(r), $bitstoreal($realtobits(r)));
r=-0.5;
$write("%f %b %f\
",r, $realtobits(r), $bitstoreal($realtobits(r)));
end
endmodule
|
\r
\r
module test();\r
typedef struct packed {\r
logic [31:0] sub_local;\r
} row_entry_t; \r
\r
typedef struct packed {\r
logic [31:0] row_local;\r
row_entry_t sub;\r
row_entry_t [1:0] sub_list;\r
} row_t; \r
\r
row_t main;\r
\r
initial begin\r
main.row_local = 32\'hCAFE;\t\r
main.sub.sub_local = 32\'h00000001;\r
main.sub_list[0].sub_local = 32\'hACE;\r
main.sub_list[1].sub_local = 32\'hECA;\r
$display("main=0x%08X", main);\r
if (main !== 128\'h0000cafe0000000100000eca00000ace) begin\r
\t $display("FAILED -- main != 128\'h0000cafe0000000100000eca00000ace");\r
\t $finish;\r
end\r
$display("main.row_local=0x%08X", main.row_local); \r
$display("main.sub=0x%08X", main.sub); \r
$display("main.sub.sub_local=0x%08X", main.sub.sub_local); \r
if (main.sub.sub_local !== 32\'h00000001) begin\r
\t $display("FAILED -- main.sub.sub_local != 32\'h00000001");\r
\t $finish;\r
end\r
$display("main.sub_list[0].sub_local=0x%08X", main.sub_list[0].sub_local); \r
if (main.sub_list[0].sub_local !== 32\'hACE) begin\r
\t $display("FAILED -- main.sub.sub_local != 32\'h00000ace");\r
\t $finish;\r
end\r
$display("main.sub_list[1].sub_local=0x%08X", main.sub_list[1].sub_local); \r
if (main.sub_list[1].sub_local !== 32\'hECA) begin\r
\t $display("FAILED -- main.sub.sub_local != 32\'h00000eca");\r
\t $finish;\r
end\r
$display("PASSED");\r
$finish();\r
end\r
\r
endmodule\r
|
// Check that parameters without default values outside the parameter port list
// generate an error.
module a;
parameter A;
initial begin
$display("FAILED");
end
endmodule
module test;
a #(.A(10)) i_a();
endmodule
|
// Test implicit casts during parameter declarations.
module implicit_cast();
localparam real src_r = -7;
localparam bit unsigned [7:0] src_u2 = 7;
localparam bit signed [7:0] src_s2 = -7;
localparam logic unsigned [7:0] src_u4 = 7;
localparam logic signed [7:0] src_s4 = -7;
localparam logic unsigned [7:0] src_ux = 8\'bx0z00111;
localparam logic signed [7:0] src_sx = 8\'bx0z00111;
localparam real dst1_r = src_r;
localparam real dst2_r = src_u4;
localparam real dst3_r = src_s4;
localparam real dst4_r = src_u2;
localparam real dst5_r = src_s2;
localparam real dst6_r = src_ux;
localparam real dst7_r = src_sx;
localparam bit unsigned [3:0] dst1_u2s = src_r;
localparam bit unsigned [3:0] dst2_u2s = src_u4;
localparam bit unsigned [3:0] dst3_u2s = src_s4;
localparam bit unsigned [3:0] dst4_u2s = src_u2;
localparam bit unsigned [3:0] dst5_u2s = src_s2;
localparam bit unsigned [3:0] dst6_u2s = src_ux;
localparam bit unsigned [3:0] dst7_u2s = src_sx;
localparam bit signed [3:0] dst1_s2s = src_r;
localparam bit signed [3:0] dst2_s2s = src_u4;
localparam bit signed [3:0] dst3_s2s = src_s4;
localparam bit signed [3:0] dst4_s2s = src_u2;
localparam bit signed [3:0] dst5_s2s = src_s2;
localparam bit signed [3:0] dst6_s2s = src_ux;
localparam bit signed [3:0] dst7_s2s = src_sx;
localparam bit unsigned [11:0] dst1_u2l = src_r;
localparam bit unsigned [11:0] dst2_u2l = src_u4;
localparam bit unsigned [11:0] dst3_u2l = src_s4;
localparam bit unsigned [11:0] dst4_u2l = src_u2;
localparam bit unsigned [11:0] dst5_u2l = src_s2;
localparam bit unsigned [11:0] dst6_u2l = src_ux;
localparam bit unsigned [11:0] dst7_u2l = src_sx;
localparam bit signed [11:0] dst1_s2l = src_r;
localparam bit signed [11:0] dst2_s2l = src_u4;
localparam bit signed [11:0] dst3_s2l = src_s4;
localparam bit signed [11:0] dst4_s2l = src_u2;
localparam bit signed [11:0] dst5_s2l = src_s2;
localparam bit signed [11:0] dst6_s2l = src_ux;
localparam bit signed [11:0] dst7_s2l = src_sx;
localparam logic unsigned [3:0] dst1_u4s = src_r;
localparam logic unsigned [3:0] dst2_u4s = src_u4;
localparam logic unsigned [3:0] dst3_u4s = src_s4;
localparam logic unsigned [3:0] dst4_u4s = src_u2;
localparam logic unsigned [3:0] dst5_u4s = src_s2;
localparam logic unsigned [3:0] dst6_u4s = src_ux;
localparam logic unsigned [3:0] dst7_u4s = src_sx;
localparam logic signed [3:0] dst1_s4s = src_r;
localparam logic signed [3:0] dst2_s4s = src_u4;
localparam logic signed [3:0] dst3_s4s = src_s4;
localparam logic signed [3:0] dst4_s4s = src_u2;
localparam logic signed [3:0] dst5_s4s = src_s2;
localparam logic signed [3:0] dst6_s4s = src_ux;
localparam logic signed [3:0] dst7_s4s = src_sx;
localparam logic unsigned [11:0] dst1_u4l = src_r;
localparam logic unsigned [11:0] dst2_u4l = src_u4;
localparam logic unsigned [11:0] dst3_u4l = src_s4;
localparam logic unsigned [11:0] dst4_u4l = src_u2;
localparam logic unsigned [11:0] dst5_u4l = src_s2;
localparam logic unsigned [11:0] dst6_u4l = src_ux;
localparam logic unsigned [11:0] dst7_u4l = src_sx;
localparam logic signed [11:0] dst1_s4l = src_r;
localparam logic signed [11:0] dst2_s4l = src_u4;
localparam logic signed [11:0] dst3_s4l = src_s4;
localparam logic signed [11:0] dst4_s4l = src_u2;
localparam logic signed [11:0] dst5_s4l = src_s2;
localparam logic signed [11:0] dst6_s4l = src_ux;
localparam logic signed [11:0] dst7_s4l = src_sx;
bit failed;
initial begin
failed = 0;
$display("cast to real");
$display("%g", dst1_r); if (dst1_r != -7.0) failed = 1;
$display("%g", dst2_r); if (dst2_r != 7.0) failed = 1;
$display("%g", dst3_r); if (dst3_r != -7.0) failed = 1;
$display("%g", dst4_r); if (dst4_r != 7.0) failed = 1;
$display("%g", dst5_r); if (dst5_r != -7.0) failed = 1;
$display("%g", dst6_r); if (dst6_r != 7.0) failed = 1;
$display("%g", dst7_r); if (dst7_r != 7.0) failed = 1;
$display("cast to small unsigned bit");
$display("%d", dst1_u2s); if (dst1_u2s !== 4\'d9) failed = 1;
$display("%d", dst2_u2s); if (dst2_u2s !== 4\'d7) failed = 1;
$display("%d", dst3_u2s); if (dst3_u2s !== 4\'d9) failed = 1;
$display("%d", dst4_u2s); if (dst4_u2s !== 4\'d7) failed = 1;
$display("%d", dst5_u2s); if (dst5_u2s !== 4\'d9) failed = 1;
$display("%d", dst6_u2s); if (dst6_u2s !== 4\'d7) failed = 1;
$display("%d", dst7_u2s); if (dst7_u2s !== 4\'d7) failed = 1;
$display("cast to small signed bit");
$display("%d", dst1_s2s); if (dst1_s2s !== -4\'sd7) failed = 1;
$display("%d", dst2_s2s); if (dst2_s2s !== 4\'sd7) failed = 1;
$display("%d", dst3_s2s); if (dst3_s2s !== -4\'sd7) failed = 1;
$display("%d", dst4_s2s); if (dst4_s2s !== 4\'sd7) failed = 1;
$display("%d", dst5_s2s); if (dst5_s2s !== -4\'sd7) failed = 1;
$display("%d", dst6_s2s); if (dst6_s2s !== 4\'sd7) failed = 1;
$display("%d", dst7_s2s); if (dst7_s2s !== 4\'sd7) failed = 1;
$display("cast to large unsigned bit");
$display("%d", dst1_u2l); if (dst1_u2l !== 12\'d4089) failed = 1;
$display("%d", dst2_u2l); if (dst2_u2l !== 12\'d7) failed = 1;
$display("%d", dst3_u2l); if (dst3_u2l !== 12\'d4089) failed = 1;
$display("%d", dst4_u2l); if (dst4_u2l !== 12\'d7) failed = 1;
$display("%d", dst5_u2l); if (dst5_u2l !== 12\'d4089) failed = 1;
$display("%b", dst6_u2l); if (dst6_u2l !== 12\'b000000000111) failed = 1;
$display("%b", dst7_u2l); if (dst7_u2l !== 12\'b000000000111) failed = 1;
$display("cast to large signed bit");
$display("%d", dst1_s2l); if (dst1_s2l !== -12\'sd7) failed = 1;
$display("%d", dst2_s2l); if (dst2_s2l !== 12\'sd7) failed = 1;
$display("%d", dst3_s2l); if (dst3_s2l !== -12\'sd7) failed = 1;
$display("%d", dst4_s2l); if (dst4_s2l !== 12\'sd7) failed = 1;
$display("%d", dst5_s2l); if (dst5_s2l !== -12\'sd7) failed = 1;
$display("%b", dst6_s2l); if (dst6_s2l !== 12\'b000000000111) failed = 1;
$display("%b", dst7_s2l); if (dst7_s2l !== 12\'b000000000111) failed = 1;
$display("cast to small unsigned logic");
$display("%d", dst1_u4s); if (dst1_u4s !== 4\'d9) failed = 1;
$display("%d", dst2_u4s); if (dst2_u4s !== 4\'d7) failed = 1;
$display("%d", dst3_u4s); if (dst3_u4s !== 4\'d9) failed = 1;
$display("%d", dst4_u4s); if (dst4_u4s !== 4\'d7) failed = 1;
$display("%d", dst5_u4s); if (dst5_u4s !== 4\'d9) failed = 1;
$display("%d", dst6_u4s); if (dst6_u4s !== 4\'d7) failed = 1;
$display("%d", dst7_u4s); if (dst7_u4s !== 4\'d7) failed = 1;
$display("cast to small signed logic");
$display("%d", dst1_s4s); if (dst1_s4s !== -4\'sd7) failed = 1;
$display("%d", dst2_s4s); if (dst2_s4s !== 4\'sd7) failed = 1;
$display("%d", dst3_s4s); if (dst3_s4s !== -4\'sd7) failed = 1;
$display("%d", dst4_s4s); if (dst4_s4s !== 4\'sd7) failed = 1;
$display("%d", dst5_s4s); if (dst5_s4s !== -4\'sd7) failed = 1;
$display("%d", dst6_s4s); if (dst6_s4s !== 4\'sd7) failed = 1;
$display("%d", dst7_s4s); if (dst7_s4s !== 4\'sd7) failed = 1;
$display("cast to large unsigned logic");
$display("%d", dst1_u4l); if (dst1_u4l !== 12\'d4089) failed = 1;
$display("%d", dst2_u4l); if (dst2_u4l !== 12\'d7) failed = 1;
$display("%d", dst3_u4l); if (dst3_u4l !== 12\'d4089) failed = 1;
$display("%d", dst4_u4l); if (dst4_u4l !== 12\'d7) failed = 1;
$display("%d", dst5_u4l); if (dst5_u4l !== 12\'d4089) failed = 1;
$display("%b", dst6_u4l); if (dst6_u4l !== 12\'b0000x0z00111) failed = 1;
$display("%b", dst7_u4l); if (dst7_u4l !== 12\'bxxxxx0z00111) failed = 1;
$display("cast to large signed logic");
$display("%d", dst1_s4l); if (dst1_s4l !== -12\'sd7) failed = 1;
$display("%d", dst2_s4l); if (dst2_s4l !== 12\'sd7) failed = 1;
$display("%d", dst3_s4l); if (dst3_s4l !== -12\'sd7) failed = 1;
$display("%d", dst4_s4l); if (dst4_s4l !== 12\'sd7) failed = 1;
$display("%d", dst5_s4l); if (dst5_s4l !== -12\'sd7) failed = 1;
$display("%b", dst6_s4l); if (dst6_s4l !== 12\'b0000x0z00111) failed = 1;
$display("%b", dst7_s4l); if (dst7_s4l !== 12\'bxxxxx0z00111) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module example();
reg [7:0] scale, a, b;
wire [7:0] c;
function [7:0] scaled;
input [7:0] value;
begin
scaled = value * scale;
end
endfunction
assign c = scaled(a) + scaled(b);
initial begin
#1 a = 2;
#1 scale = 2;
#1 b = 3;
#1 $display(c);
if (c === 10)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// This tests that the individual bits of a uwire are checked for
// double-driving individually. The code below uses a packed struct
// to represent individual bits.
module test;
struct packed {
logic [15:0] hig;
logic [15:0] low;
} foo;
assign foo.low = \'haaaa;
assign foo.hig = \'h5555;
initial begin
#1 if (foo !== \'h5555aaaa) begin
\t $display("FAILED -- foo=%h", foo);
\t $finish;
end
$display("PASSED");
end
endmodule // test
|
`begin_keywords "1364-2005"
module automatic_error();
task automatic auto_task;
integer local;
begin
local = 1;
$strobe("%0d", local);
end
endtask
initial auto_task;
endmodule
`end_keywords
|
// Test implicit casts during module output assignments.
`ifdef __ICARUS__
`define SUPPORT_REAL_NETS_IN_IVTEST
`define SUPPORT_TWO_STATE_NETS_IN_IVTEST
`endif
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
module cp_r(output wire real dst,
input wire real src);
assign dst = src;
endmodule
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
module cp_u2(output wire bit unsigned [7:0] dst,
input wire bit unsigned [7:0] src);
assign dst = src;
endmodule
module cp_s2(output wire bit signed [7:0] dst,
input wire bit signed [7:0] src);
assign dst = src;
endmodule
`endif
module cp_u4(output wire logic unsigned [7:0] dst,
input wire logic unsigned [7:0] src);
assign dst = src;
endmodule
module cp_s4(output wire logic signed [7:0] dst,
input wire logic signed [7:0] src);
assign dst = src;
endmodule
module implicit_cast();
real src_r;
bit unsigned [7:0] src_u2;
bit signed [7:0] src_s2;
logic unsigned [7:0] src_u4;
logic signed [7:0] src_s4;
logic unsigned [7:0] src_ux;
logic signed [7:0] src_sx;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
wire real dst1_r;
wire real dst2_r;
wire real dst3_r;
wire real dst4_r;
wire real dst5_r;
wire real dst6_r;
wire real dst7_r;
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
wire bit unsigned [3:0] dst1_u2s;
wire bit unsigned [3:0] dst2_u2s;
wire bit unsigned [3:0] dst3_u2s;
wire bit unsigned [3:0] dst4_u2s;
wire bit unsigned [3:0] dst5_u2s;
wire bit unsigned [3:0] dst6_u2s;
wire bit unsigned [3:0] dst7_u2s;
wire bit signed [3:0] dst1_s2s;
wire bit signed [3:0] dst2_s2s;
wire bit signed [3:0] dst3_s2s;
wire bit signed [3:0] dst4_s2s;
wire bit signed [3:0] dst5_s2s;
wire bit signed [3:0] dst6_s2s;
wire bit signed [3:0] dst7_s2s;
wire bit unsigned [11:0] dst1_u2l;
wire bit unsigned [11:0] dst2_u2l;
wire bit unsigned [11:0] dst3_u2l;
wire bit unsigned [11:0] dst4_u2l;
wire bit unsigned [11:0] dst5_u2l;
wire bit unsigned [11:0] dst6_u2l;
wire bit unsigned [11:0] dst7_u2l;
wire bit signed [11:0] dst1_s2l;
wire bit signed [11:0] dst2_s2l;
wire bit signed [11:0] dst3_s2l;
wire bit signed [11:0] dst4_s2l;
wire bit signed [11:0] dst5_s2l;
wire bit signed [11:0] dst6_s2l;
wire bit signed [11:0] dst7_s2l;
`endif
wire logic unsigned [3:0] dst1_u4s;
wire logic unsigned [3:0] dst2_u4s;
wire logic unsigned [3:0] dst3_u4s;
wire logic unsigned [3:0] dst4_u4s;
wire logic unsigned [3:0] dst5_u4s;
wire logic unsigned [3:0] dst6_u4s;
wire logic unsigned [3:0] dst7_u4s;
wire logic signed [3:0] dst1_s4s;
wire logic signed [3:0] dst2_s4s;
wire logic signed [3:0] dst3_s4s;
wire logic signed [3:0] dst4_s4s;
wire logic signed [3:0] dst5_s4s;
wire logic signed [3:0] dst6_s4s;
wire logic signed [3:0] dst7_s4s;
wire logic unsigned [11:0] dst1_u4l;
wire logic unsigned [11:0] dst2_u4l;
wire logic unsigned [11:0] dst3_u4l;
wire logic unsigned [11:0] dst4_u4l;
wire logic unsigned [11:0] dst5_u4l;
wire logic unsigned [11:0] dst6_u4l;
wire logic unsigned [11:0] dst7_u4l;
wire logic signed [11:0] dst1_s4l;
wire logic signed [11:0] dst2_s4l;
wire logic signed [11:0] dst3_s4l;
wire logic signed [11:0] dst4_s4l;
wire logic signed [11:0] dst5_s4l;
wire logic signed [11:0] dst6_s4l;
wire logic signed [11:0] dst7_s4l;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
cp_r cp1_r(dst1_r, src_r);
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
cp_u2 cp2_r(dst2_r, src_u2);
cp_s2 cp3_r(dst3_r, src_s2);
`endif
cp_u4 cp4_r(dst4_r, src_u4);
cp_s4 cp5_r(dst5_r, src_s4);
cp_u4 cp6_r(dst6_r, src_ux);
cp_s4 cp7_r(dst7_r, src_sx);
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
cp_r cp1_u2s(dst1_u2s, src_r);
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
cp_u2 cp2_u2s(dst2_u2s, src_u2);
cp_s2 cp3_u2s(dst3_u2s, src_s2);
`endif
cp_u4 cp4_u2s(dst4_u2s, src_u4);
cp_s4 cp5_u2s(dst5_u2s, src_s4);
cp_u4 cp6_u2s(dst6_u2s, src_ux);
cp_s4 cp7_u2s(dst7_u2s, src_sx);
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
cp_r cp1_s2s(dst1_s2s, src_r);
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
cp_u2 cp2_s2s(dst2_s2s, src_u2);
cp_s2 cp3_s2s(dst3_s2s, src_s2);
`endif
cp_u4 cp4_s2s(dst4_s2s, src_u4);
cp_s4 cp5_s2s(dst5_s2s, src_s4);
cp_u4 cp6_s2s(dst6_s2s, src_ux);
cp_s4 cp7_s2s(dst7_s2s, src_sx);
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
cp_r cp1_u2l(dst1_u2l, src_r);
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
cp_u2 cp2_u2l(dst2_u2l, src_u2);
cp_s2 cp3_u2l(dst3_u2l, src_s2);
`endif
cp_u4 cp4_u2l(dst4_u2l, src_u4);
cp_s4 cp5_u2l(dst5_u2l, src_s4);
cp_u4 cp6_u2l(dst6_u2l, src_ux);
cp_s4 cp7_u2l(dst7_u2l, src_sx);
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
cp_r cp1_s2l(dst1_s2l, src_r);
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
cp_u2 cp2_s2l(dst2_s2l, src_u2);
cp_s2 cp3_s2l(dst3_s2l, src_s2);
`endif
cp_u4 cp4_s2l(dst4_s2l, src_u4);
cp_s4 cp5_s2l(dst5_s2l, src_s4);
cp_u4 cp6_s2l(dst6_s2l, src_ux);
cp_s4 cp7_s2l(dst7_s2l, src_sx);
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
cp_r cp1_u4s(dst1_u4s, src_r);
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
cp_u2 cp2_u4s(dst2_u4s, src_u2);
cp_s2 cp3_u4s(dst3_u4s, src_s2);
`endif
cp_u4 cp4_u4s(dst4_u4s, src_u4);
cp_s4 cp5_u4s(dst5_u4s, src_s4);
cp_u4 cp6_u4s(dst6_u4s, src_ux);
cp_s4 cp7_u4s(dst7_u4s, src_sx);
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
cp_r cp1_s4s(dst1_s4s, src_r);
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
cp_u2 cp2_s4s(dst2_s4s, src_u2);
cp_s2 cp3_s4s(dst3_s4s, src_s2);
`endif
cp_u4 cp4_s4s(dst4_s4s, src_u4);
cp_s4 cp5_s4s(dst5_s4s, src_s4);
cp_u4 cp6_s4s(dst6_s4s, src_ux);
cp_s4 cp7_s4s(dst7_s4s, src_sx);
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
cp_r cp1_u4l(dst1_u4l, src_r);
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
cp_u2 cp2_u4l(dst2_u4l, src_u2);
cp_s2 cp3_u4l(dst3_u4l, src_s2);
`endif
cp_u4 cp4_u4l(dst4_u4l, src_u4);
cp_s4 cp5_u4l(dst5_u4l, src_s4);
cp_u4 cp6_u4l(dst6_u4l, src_ux);
cp_s4 cp7_u4l(dst7_u4l, src_sx);
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
cp_r cp1_s4l(dst1_s4l, src_r);
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
cp_u2 cp2_s4l(dst2_s4l, src_u2);
cp_s2 cp3_s4l(dst3_s4l, src_s2);
`endif
cp_u4 cp4_s4l(dst4_s4l, src_u4);
cp_s4 cp5_s4l(dst5_s4l, src_s4);
cp_u4 cp6_s4l(dst6_s4l, src_ux);
cp_s4 cp7_s4l(dst7_s4l, src_sx);
bit failed;
initial begin
failed = 0;
src_r = -7;
src_u2 = 7;
src_s2 = -7;
src_u4 = 7;
src_s4 = -7;
src_ux = 8\'bx0z00111;
src_sx = 8\'bx0z00111;
#1;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
$display("cast to real");
$display("%g", dst1_r); if (dst1_r != -7.0) failed = 1;
$display("%g", dst2_r); if (dst2_r != 7.0) failed = 1;
$display("%g", dst3_r); if (dst3_r != -7.0) failed = 1;
$display("%g", dst4_r); if (dst4_r != 7.0) failed = 1;
$display("%g", dst5_r); if (dst5_r != -7.0) failed = 1;
$display("%g", dst6_r); if (dst6_r != 7.0) failed = 1;
$display("%g", dst7_r); if (dst7_r != 7.0) failed = 1;
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
$display("cast to small unsigned bit");
$display("%d", dst1_u2s); if (dst1_u2s !== 4\'d9) failed = 1;
$display("%d", dst2_u2s); if (dst2_u2s !== 4\'d7) failed = 1;
$display("%d", dst3_u2s); if (dst3_u2s !== 4\'d9) failed = 1;
$display("%d", dst4_u2s); if (dst4_u2s !== 4\'d7) failed = 1;
$display("%d", dst5_u2s); if (dst5_u2s !== 4\'d9) failed = 1;
$display("%d", dst6_u2s); if (dst6_u2s !== 4\'d7) failed = 1;
$display("%d", dst7_u2s); if (dst7_u2s !== 4\'d7) failed = 1;
$display("cast to small signed bit");
$display("%d", dst1_s2s); if (dst1_s2s !== -4\'sd7) failed = 1;
$display("%d", dst2_s2s); if (dst2_s2s !== 4\'sd7) failed = 1;
$display("%d", dst3_s2s); if (dst3_s2s !== -4\'sd7) failed = 1;
$display("%d", dst4_s2s); if (dst4_s2s !== 4\'sd7) failed = 1;
$display("%d", dst5_s2s); if (dst5_s2s !== -4\'sd7) failed = 1;
$display("%d", dst6_s2s); if (dst6_s2s !== 4\'sd7) failed = 1;
$display("%d", dst7_s2s); if (dst7_s2s !== 4\'sd7) failed = 1;
$display("cast to large unsigned bit");
$display("%d", dst1_u2l); if (dst1_u2l !== 12\'d4089) failed = 1;
$display("%d", dst2_u2l); if (dst2_u2l !== 12\'d7) failed = 1;
$display("%d", dst3_u2l); if (dst3_u2l !== 12\'d4089) failed = 1;
$display("%d", dst4_u2l); if (dst4_u2l !== 12\'d7) failed = 1;
$display("%d", dst5_u2l); if (dst5_u2l !== 12\'d4089) failed = 1;
$display("%b", dst6_u2l); if (dst6_u2l !== 12\'b000000000111) failed = 1;
$display("%b", dst7_u2l); if (dst7_u2l !== 12\'b000000000111) failed = 1;
$display("cast to large signed bit");
$display("%d", dst1_s2l); if (dst1_s2l !== -12\'sd7) failed = 1;
$display("%d", dst2_s2l); if (dst2_s2l !== 12\'sd7) failed = 1;
$display("%d", dst3_s2l); if (dst3_s2l !== -12\'sd7) failed = 1;
$display("%d", dst4_s2l); if (dst4_s2l !== 12\'sd7) failed = 1;
$display("%d", dst5_s2l); if (dst5_s2l !== -12\'sd7) failed = 1;
$display("%b", dst6_s2l); if (dst6_s2l !== 12\'b000000000111) failed = 1;
$display("%b", dst7_s2l); if (dst7_s2l !== 12\'b000000000111) failed = 1;
`endif
$display("cast to small unsigned logic");
$display("%d", dst1_u4s); if (dst1_u4s !== 4\'d9) failed = 1;
$display("%d", dst2_u4s); if (dst2_u4s !== 4\'d7) failed = 1;
$display("%d", dst3_u4s); if (dst3_u4s !== 4\'d9) failed = 1;
$display("%d", dst4_u4s); if (dst4_u4s !== 4\'d7) failed = 1;
$display("%d", dst5_u4s); if (dst5_u4s !== 4\'d9) failed = 1;
$display("%d", dst6_u4s); if (dst6_u4s !== 4\'d7) failed = 1;
$display("%d", dst7_u4s); if (dst7_u4s !== 4\'d7) failed = 1;
$display("cast to small signed logic");
$display("%d", dst1_s4s); if (dst1_s4s !== -4\'sd7) failed = 1;
$display("%d", dst2_s4s); if (dst2_s4s !== 4\'sd7) failed = 1;
$display("%d", dst3_s4s); if (dst3_s4s !== -4\'sd7) failed = 1;
$display("%d", dst4_s4s); if (dst4_s4s !== 4\'sd7) failed = 1;
$display("%d", dst5_s4s); if (dst5_s4s !== -4\'sd7) failed = 1;
$display("%d", dst6_s4s); if (dst6_s4s !== 4\'sd7) failed = 1;
$display("%d", dst7_s4s); if (dst7_s4s !== 4\'sd7) failed = 1;
$display("cast to large unsigned logic");
$display("%d", dst1_u4l); if (dst1_u4l !== 12\'d4089) failed = 1;
$display("%d", dst2_u4l); if (dst2_u4l !== 12\'d7) failed = 1;
$display("%d", dst3_u4l); if (dst3_u4l !== 12\'d4089) failed = 1;
$display("%d", dst4_u4l); if (dst4_u4l !== 12\'d7) failed = 1;
$display("%d", dst5_u4l); if (dst5_u4l !== 12\'d4089) failed = 1;
$display("%b", dst6_u4l); if (dst6_u4l !== 12\'b0000x0z00111) failed = 1;
$display("%b", dst7_u4l); if (dst7_u4l !== 12\'bxxxxx0z00111) failed = 1;
$display("cast to large signed logic");
$display("%d", dst1_s4l); if (dst1_s4l !== -12\'sd7) failed = 1;
$display("%d", dst2_s4l); if (dst2_s4l !== 12\'sd7) failed = 1;
$display("%d", dst3_s4l); if (dst3_s4l !== -12\'sd7) failed = 1;
$display("%d", dst4_s4l); if (dst4_s4l !== 12\'sd7) failed = 1;
$display("%d", dst5_s4l); if (dst5_s4l !== -12\'sd7) failed = 1;
$display("%b", dst6_s4l); if (dst6_s4l !== 12\'b0000x0z00111) failed = 1;
$display("%b", dst7_s4l); if (dst7_s4l !== 12\'bxxxxx0z00111) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that the signedness of the element type of a queue is correctly handled
// whenn calling one of the pop methods with parenthesis.
module test;
bit failed = 1\'b0;
`define check(x) \\
if (!(x)) begin \\
$display("FAILED(%0d): ", `__LINE__, `"x`"); \\
failed = 1\'b1; \\
end
int unsigned x = 10;
int y = 10;
int z;
longint w;
shortint qs[$];
bit [15:0] qu[$];
initial begin
for (int i = 0; i < 16; i++) begin
qu.push_back(-1);
qs.push_back(-1);
end
// These all evaluate as signed
`check($signed(qu.pop_back()) < 0)
`check(qs.pop_back() < 0)
`check($signed(qu.pop_front()) < 0)
`check(qs.pop_front() < 0)
// These all evaluate as unsigned
`check(qu.pop_back() > 0)
`check({qs.pop_back()} > 0)
`check($unsigned(qs.pop_back()) > 0)
`check(qs.pop_back() > 16\'h0)
`check(qu.pop_front() > 0)
`check({qs.pop_front()} > 0)
`check($unsigned(qs.pop_front()) > 0)
`check(qs.pop_front() > 16\'h0)
// In arithmetic expressions if one operand is unsigned all operands are
// considered unsigned
z = qu.pop_back() + x;
`check(z === 65545)
z = qu.pop_back() + y;
`check(z === 65545)
z = qu.pop_front() + x;
`check(z === 65545)
z = qu.pop_front() + y;
`check(z === 65545)
z = qs.pop_back() + x;
`check(z === 65545)
z = qs.pop_back() + y;
`check(z === 9)
z = qs.pop_front() + x;
`check(z === 65545)
z = qs.pop_front() + y;
`check(z === 9)
// For ternary operators if one operand is unsigned the result is unsigend
z = x ? qu.pop_back() : x;
`check(z === 65535)
z = x ? qu.pop_back() : y;
`check(z === 65535)
z = x ? qu.pop_front() : x;
`check(z === 65535)
z = x ? qu.pop_front() : y;
`check(z === 65535)
z = x ? qs.pop_back() : x;
`check(z === 65535)
z = x ? qs.pop_back() : y;
`check(z === -1)
z = x ? qs.pop_front() : x;
`check(z === 65535)
z = x ? qs.pop_front() : y;
`check(z === -1)
// Size return value is always positive, but check that it gets padded
// properly
w = x ? qu.size() : 64\'h123;
`check(w === 64\'h4)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
// output ports may be uwire, or even a variable, if wire-ness
// or variable-ness are not explicitly stated.
typedef struct packed {
logic [1:0] a;
logic [1:0] b;
} sample_t;
module main;
sample_t dst;
logic [1:0] src_a, src_b;
DUT dut(.out(dst), .a(src_a), .b(src_b));
initial begin
src_a = 1;
src_b = 2;
#1 /* wait for dst */;
if (dst.a !== 1) begin
\t $display("FAILED -- dst.a=%b (dst=%b)", dst.a, dst);
\t $finish;
end
if (dst.b !== 2) begin
\t $display("FAILED -- dst.b=%b (dst=%b)", dst.b, dst);
\t $finish;
end
$display("PASSED");
end
endmodule // main
module DUT(output sample_t out,
\t input logic [1:0] a, b);
always @* begin
out.a = a;
out.b = b;
end
endmodule
|
module test();
typedef enum logic [8:0] { ILLEGAL, IA, IB } inst_t;
inst_t ipb_inst;
typedef struct packed {
inst_t inst;
logic iw;
} ipb_data_t;
ipb_data_t ipb_d;
initial begin
ipb_d.inst = IA;
ipb_inst = ipb_d.inst;
if (ipb_inst === IA)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module top;
reg pass = 1\'b1;
reg a, b;
real c, d;
initial begin
c = 0.0;
d = 1.0;
a = 1\'b0;
b = 1\'b0;
assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));
#1;
if (c != 3.0) begin
$display("FAILED, expected 3.0, got %f", c);
pass = 1\'b0;
end
a = 1\'b1;
b = 1\'b0;
assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));
#1;
if (c != 2.0) begin
$display("FAILED, expected 2.0, got %f", c);
pass = 1\'b0;
end
a = 1\'b0;
b = 1\'b1;
assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));
#1;
if (c != 6.0) begin
$display("FAILED, expected 6.0, got %f", c);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module pr2837451();
// this code provides a regression test that exercises
// vvp_fun_part_sa::recv_vec4_pv
reg [3:0] a;
wire [7:0] b;
wire [3:0] c;
wire [3:0] d;
wire [3:0] e;
assign b[5:2] = a;
assign c = b[4:1];
assign d = b[5:2];
assign e = b[6:3];
initial begin
a = 4\'b0101;
#1;
$display("%b %b %b %b %b", a, b, c, d, e);
if ((b === 8\'bzz0101zz)
&& (c === 4\'b101z)
&& (d === 4\'b0101)
&& (e === 4\'bz010))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// This is an error since the timeunit is less than the precision.
`timescale 1ns/10ns
|
// Check a missing global time precision.
`resetall
timeunit 1ns;
module no_gtp;
endmodule
|
module bug();
reg d;
reg [31:0] x;
reg [31:0] y;
reg [31:0] z;
initial begin
d = 1;
x = 32\'hffffffff << {d, 64\'d0};
y = 32\'hffffffff >> {d, 64\'d0};
z = 32\'hffffffff >>> {d, 64\'d0};
$display("%h", x);
$display("%h", y);
$display("%h", z);
if (x === 32\'d0 && y === 32\'d0 && z === 32\'d0)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* This program tests the synthesis of small memories, including
* aysnchronous read w/ synchronous write.
*/
module main;
reg clk;
reg Q, D;
(* ivl_synthesys_on *)
always @(negedge clk)
Q <= D;
(* ivl_synthesys_off *)
initial begin
clk = 1;
D = 0;
#2 clk = 0;
#2 clk = 1;
#2 if (Q !== 0) begin
\t $display("FAILED -- initial setup D=%b, Q=%b", D, Q);
\t $finish;
end
D = 1;
#2 clk = 0;
#2 if (Q !== 1) begin
\t $display("FAILED -- negedge clk failed D=%b, Q=%b", D, Q);
\t $finish;
end
D = 0;
#2 clk = 1;
#2 if (Q !== 1) begin
\t $display("FAILED -- posedge clk tripped FF. D=%b, Q=%b", D, Q);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
module top;
reg pass;
reg [7:0] a, b;
wire [15:0] ruu, rsu, rus, rss;
reg signed [15:0] res;
integer i;
assign ruu = a % b;
assign rsu = $signed(a) % b;
assign rus = a % $signed(b);
assign rss = $signed(a) % $signed(b);
initial begin
pass = 1\'b1;
// Run 1000 random vectors
for (i = 0; i < 1000; i = i + 1) begin
// Random vectors
a = $random;
b = $random;
#1;
// Check unsigned % unsigned.
if (ruu !== a%b) begin
$display("FAILED: u%%u (%b%%%b) gave %b, expected %b", a, b, ruu, a%b);
pass = 1\'b0;
end
// Check signed % unsigned division.
if (rsu !== a%b) begin
$display("FAILED: s%%u (%b%%%b) gave %b, expected %b", a, b, rsu, a%b);
pass = 1\'b0;
end
// Check unsigned % signed division.
if (rus !== a%b) begin
$display("FAILED: u%%s (%b%%%b) gave %b, expected %b", a, b, rus, a%b);
pass = 1\'b0;
end
// Check signed % signed division.
res = $signed(a)%$signed(b);
if (rss !== res) begin
$display("FAILED: s%%s (%b%%%b) gave %b, expected %b", a, b, rss, res);
pass = 1\'b0;
end
end
if (pass) $display("PASSED");
end
endmodule
|
module test;
reg cp;
reg\td;
wire q;
dff ff(q, cp, d);
always begin #5 cp=0; #5 cp=1; end
always
begin
\t@(negedge cp)
\t d <= ~d;
\t@(posedge cp)
\t if (q !== \'bx && d === q)
\t begin
\t $display("FAILED, d=%b, q=%b", d, q);
\t #1 $finish;
\t end
end
initial
begin
\t#1 d <= 1;
\t#22;
\t$display("PASSED");
\t$finish;
end
initial $monitor($time,,cp,,d,,q);
endmodule
primitive dff(q, cp, d);
output q;
input cp, d;
reg\t q;
table
// (cp) d : q : q ;
? * : ? : - ;
(?0) ? : ? : - ;
(1x) ? : ? : - ;
(x1) 0 : 0 : 0 ;
(x1) 1 : 1 : 1 ;
(0x) 0 : 0 : 0 ;
(0x) 1 : 1 : 1 ;
(01) 0 : ? : 0 ;
(01) 1 : ? : 1 ;
endtable
endprimitive
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests that a non-integer delay, in the absence of any
* timescale values, will round properly. A 2.4 delay rounds to 2, and
* a 2.6 delay rounds to 3.
*/
module main;
reg clk;
reg out1, out2;
time time1;
time time2;
always @(posedge clk) #2.4 begin
$display($time,, "set out1 == 1");
time1 = $time;
out1 = 1;
end
always @(posedge clk) #2.6 begin
$display($time,, "set out2 == 1");
time2 = $time;
out2 = 1;
end
initial begin
clk = 0;
out1 = 0;
out2 = 0;
time1 = 0;
time2 = 0;
#1 if (out1 !== 0) begin
\t $display("FAILED -- out1 is not 0: %b", out1);
\t $finish;
end
clk = 1;
#3 if (out1 !== 1) begin
\t $display("FAILED -- out is not 1 at time 3: %b", out1);
\t $finish;
end
if (time1 != 3) begin
\t $display("FAILED -- time1 = %d", time1);
\t $finish;
end
#1 if (time2 != 4) begin
\t $display("FAILED -- time2 = %d", time2);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module check (input unsigned [22:0] a, b, c);
wire unsigned [22:0] int_AB;
assign int_AB = a + b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
#1 A = 0;
B = 0;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 0;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = {$random} % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = {$random} % MAX;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input unsigned [22:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [22:0] r;
stimulus stim (.A(a), .B(b));
uadd23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
// Check that it is possible to declare the data type for a real type task port
// separately from the direction for non-ANSI style port declarations.
module test;
task t;
input x;
real x;
if (x == 1.23) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t(1.23);
endmodule
|
// Copyright (c) 2003 Michael Ruff (mruff at chiaro.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// Test basic functionality of convertion system VPI functions.
//
module test;
integer\terr, i;
real\tr;
reg [63:0]\tb;
parameter PI = 3.1415926535_8979323846_2643383279;
initial begin
\terr = 0;
\t//
\t// $rtoi()
\t//
\ti = $rtoi(0.1);
\tif (i != 0) begin
\t err = 1;
\t $display("$rtoi(0.1): %0d != 0", i);
\tend
\ti = $rtoi(9.6);
\tif (i != 9) begin
\t err = 1;
\t $display("$rtoi(9.6): %0d != 9", i);
\tend
\t//
\t// $realtobits()
\t//
\tb = $realtobits(PI);
\tif (b != 64\'h400921FB54442D18) begin
\t err = 1;
\t $display("$realtobits(PI): \'h%x != \'h400921FB54442D18", b);
\tend
\tb = $realtobits(1.1);
\tif (b != 64\'h3ff199999999999a) begin
\t err = 1;
\t $display("$realtobits(1.1): \'h%x != \'h400921FB54442D18", b);
\tend
\t//
\t// $bitstoreal()
\t//
\tr = $bitstoreal(64\'h400921FB54442D18);
\tif (r != PI) begin
\t err = 1;
\t $display("$realtobits(PI): %20.17f != %20.17f", r, PI);
\tend
\tr = $bitstoreal(64\'h3FF4CCCCCCCCCCCD);
\tif (r != 1.3) begin
\t err = 1;
\t $display("$realtobits(1.3): %20.17f != 1.3", r);
\tend
\t//
\t// $itor()
\t//
\tr = $itor(1);
\tif (r != 1.0) begin
\t err = 1;
\t $display("$itor(1): %20.1f != 1.0", r);
\tend
\tr = $itor(123456789);
\tif (r != 123456789.0) begin
\t err = 1;
\t $display("$itor(123456789): %20.1f != 123456789.0", r);
\tend
\tif (err)
\t $display("FAILED");
\telse
\t $display("PASSED");
\t$finish;
end
endmodule
|
/*
* Copyright (c) 2001 Peter Bain <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test;
task foo;
begin
$display("PASSED");
end
endtask
task bar;
begin
test.foo;
end
endtask
initial begin
test.bar;
end
endmodule
|
module br932a();
task check_str(input string str);
begin
$display("%s", str);
if (str == "br932a")
$display("PASSED");
else
$display("FAILED");
end
endtask
initial begin
check_str("br932a");
end
endmodule
|
// Check that it is possible to declare the data type for a packed array module
// port separately from the direction for non-ANSI style port declarations.
// declarations.
typedef logic [3:0] T1;
typedef T1 [7:0] T2;
module test(x);
output x;
T2 x;
initial begin
if ($bits(x) == $bits(T2)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module test;
/* The base+b calculation uses %load/vp0 and this will cause invalid
* results when the sum of base+b is larger than what will fit
* in b. The addition is done at b\'s width. It appears that
* %load/vp0 needs to be enhanced, or something else needs to
* be used.
*
* The workaround is to make b large enough to access
* the largest a index not a\'s range. */
parameter base = 8;
reg [31:0] a[15:base];
reg [2:0] b;
initial begin
for (b=0; b<7; b=b+1) begin
a[base+b] = 32\'d2+b;
$display("Value[%0d]: %1d", b, a[base+b]);
end
end
endmodule
|
class my_class;
task run_test();
$display("PASSED");
endtask
endclass
module test();
class extended_class extends my_class;
endclass
extended_class obj;
initial begin
obj = new();
obj.run_test();
end
endmodule
|
module main;
reg a, b;
always @(a or b) begin
if ($ivlh_attribute_event(a))
\t$display("%0t: EVENT on a", $time);
if ($ivlh_attribute_event(b))
\t$display("%0t: EVENT on b", $time);
end
initial begin
#1 a <= 1;
#1 b <= 1;
#1 a <= 0;
#1 b <= 0;
#1 $finish(0);
end
endmodule // main
|
$display("file %s line %0d", `__FILE__, `__LINE__);
|
module example;
function simple_func;
input in;
begin
simple_func = in;
end
endfunction
reg x = 0;
initial begin
x = simple_func(x,x);
$finish;
end
endmodule
|
// Check a local timeprecision that is too large.
`resetall
module ltp_large;
timeunit 1ns;
timeprecision 10ns;
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for $ivlh_{rising,falling}_edge VPI functions
// (mostly used by the VHDL frontend).
module main;
reg a, b;
always @(a or b) begin
if ($ivlh_rising_edge(a))
\t$display("%0t: rising_edge(a)", $time);
if ($ivlh_falling_edge(a))
\t$display("%0t: falling_edge(a)", $time);
if ($ivlh_rising_edge(b))
\t$display("%0t: rising_edge(b)", $time);
if ($ivlh_falling_edge(b))
\t$display("%0t: falling_edge(b)", $time);
end
initial begin
#1 a <= 1;
#1 b <= 1;
#1 a <= 0;
#1 b <= 0;
#1 a <= 0; // nothing should be detected
#1 b <= 0;
#1 a <= 1;
#1 b <= 1;
#1 a <= 1; // nothing should be detected
#1 b <= 1;
#1 a <= 0;
#1 b <= 0;
#1 $finish(0);
end
endmodule // main
|
// This just tests the compiler accepts the syntax. It needs to be improved
// when deferred assumeions are supported.
module test();
integer i = 1;
initial begin
assume final (i == 1);
assume final (i == 0);
assume final (i == 1) else $display("Check 3 : this shouldn\'t be displayed");
assume final (i == 0) else $display("Check 4 : this should be displayed");
assume final (i == 1) $display("Check 5 : this should be displayed");
assume final (i == 0) $display("Check 6 : this shouldn\'t be displayed");
assume final (i == 1) $display("Check 7 : this should be displayed");
else $display("Check 7 : this shouldn\'t be displayed");
assume final (i == 0) $display("Check 8 : this shouldn\'t be displayed");
else $display("Check 8 : this should be displayed");
end
endmodule
|
class test_t;
typedef enum bit [1:0] { U, V } uv_t;
uv_t foo;
task go;
foo = U;
$display("test_t.foo=%b (U==0)", foo);
if (foo !== U) begin
\t $display("FAILED");
\t $finish;
end
foo = V;
$display("test_t.foo=%b (V==1)", foo);
if (foo !== V) begin
\t $display("FAILED");
\t $finish;
end
endtask
endclass // test_t
module main;
typedef enum bit [1:0] { X, Y } xy_t;
xy_t foo;
initial begin
foo = Y;
$display("foo=%b (Y==1)", foo);
if (foo !== Y) begin
\t $display("FAILED");
\t $finish;
end
foo = X;
$display("foo=%b (X==0)", foo);
if (foo !== X) begin
\t $display("FAILED");
\t $finish;
end
end
test_t bar;
initial begin
bar = new;
bar.go();
end
initial begin
#1 $display("PASSED");
$finish;
end
endmodule // main
|
/* From PR#516 */
module top ();
parameter GEORGE = 8\'d5;
parameter HARRY = 10;
initial begin
#1;
$display("decimal GEORGE: %0d, HARRY: %0d",GEORGE, HARRY);
$display("binary GEORGE: \'b%0b, HARRY: \'b%0b",GEORGE, HARRY);
$finish(0);
end
endmodule
|
module test();
logic [1:0] array = new[4];
endmodule
|
module test();
task t(input integer a, integer b);
$display(a,,b);
endtask
initial t(0, 1);
endmodule
|
module main;
function integer my_ceil;
input number;
real number;
if (number > $rtoi(number))
my_ceil = $rtoi(number) + 1;
else
my_ceil = number;
endfunction
real tck;
parameter CL_TIME = 13125;
wire [31:0] result1 = my_ceil( CL_TIME/tck );
integer result2;
initial begin
tck = 2.0;
result2 = my_ceil( CL_TIME/tck );
if (result2 !== 6563) begin
\t $display("FAILED -- result2=%d", result2);
\t $finish;
end
#1 if (result1 !== 6563) begin
\t $display("FAILED -- result1=%d", result1);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// Check that it is not possible to assign a queue with an int element type to a
// queue with a real element type.
module test;
real q1[$];
int q2[$];
initial begin
q1 = q2;
$display("FAILED");
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for array query functions applied to localparams.
module lparam_query;
localparam const_param = 16\'b0001110111001111;
initial begin
if($left(const_param) !== 15) begin
$display("FAILED 1");
$finish();
end
if($right(const_param) !== 0) begin
$display("FAILED 2");
$finish();
end
if($high(const_param) !== 15) begin
$display("FAILED 3");
$finish();
end
if($low(const_param) !== 0) begin
$display("FAILED 4");
$finish();
end
if($increment(const_param) !== 1) begin
$display("FAILED 5");
$finish();
end
if($size(const_param) !== 16) begin
$display("FAILED 6");
$finish();
end
$display("PASSED");
end
endmodule
|
// This is a regression test for the bug fixed in patch tracker #1268.
module test();
reg [19:0] a[15:0];
reg [3:0] idx[3:1];
initial begin
idx[1] = 2;
idx[2] = 3;
idx[3] = 4;
a[idx[1]][idx[2]*4 +: 4] <= #(idx[3]) 4\'ha;
#4;
$display("%h", a[2]);
if (a[2] !== 20\'hxxxxx) begin
$display("FAILED");
$finish;
end
#1;
$display("%h", a[2]);
if (a[2] !== 20\'hxaxxx) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
module main;
int foo, bar = 10;
int wire_res;
int var_res;
assign wire_res = foo*bar;
initial begin
foo = 9;
var_res = foo * bar;
$display("%0d * %0d = %0d %0d", foo, bar, foo * bar, var_res);
if ((foo * bar) !== 90) begin
\t $display("FAILED");
\t $finish;
end
if (var_res !== 90) begin
\t $display("FAILED");
\t $finish;
end
#0; // allow CA to propagate
$display("%0d * %0d = %0d", foo, bar, wire_res);
if (wire_res !== 90) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module inner ();
initial
a.dump;
endmodule
module outer ();
inner i ();
generate
begin : a
task dump;
begin
$display ("PASSED");
end
endtask
end
endgenerate
endmodule
|
module test();
`define MACRO \\
$display("file %s line %0d", \\
`__FILE__, `__LINE__);
initial begin
$display("file %s line %0d", `__FILE__, `__LINE__);
`line 1 "real_source.v" 0
$display("file %s line %0d", `__FILE__, `__LINE__);
`include "line_directive_inc.v"
$display("file %s line %0d", `__FILE__, `__LINE__);
`MACRO
$display("file %s line %0d", `__FILE__, `__LINE__);
end
endmodule
|
module top;
parameter C1 = 1.0e-6;
reg pass;
real rval;
real exp_result;
initial begin
pass = 1\'b1;
exp_result = -1000000.0;
// Check with a constant and a parameter.
rval = -1 / C1;
if (rval != exp_result) begin
$display ("FAILED: -1/%f gave %f, expected %f", C1, rval, exp_result);
pass = 1\'b0;
end
// Check with both constants.
rval = -1 / 1.0e-6;
if (rval != exp_result) begin
$display ("FAILED: -1/1.0e-6 gave %f, expected %f", rval, exp_result);
pass = 1\'b0;
end
// Check with a positive value.
exp_result = 1000000.0;
rval = 1 / C1;
if (rval != exp_result) begin
$display ("FAILED: 1/%f gave %f, not expected %f", C1, rval, exp_result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for subtype definitions.
module vhdl_subtypes_test;
int a, b, c;
time d;
int e;
vhdl_subtypes dut(a, b, c, d, e);
initial
begin
#1;
if(a !== 1) begin
$display("FAILED");
$finish();
end
if(b !== 2) begin
$display("FAILED");
$finish();
end
if(c !== 3) begin
$display("FAILED");
$finish();
end
if(d !== 4) begin
$display("FAILED");
$finish();
end
if(e !== 5) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
`timescale 1ns/1ps
module top;
`timescale 1us/1ns
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program checks that the code generator properly handles
* ocncatenation expressions as parameters to system tasks.
*/
module main;
reg [3:0] a, b;
initial begin
a = 0;
b = 0;
for (a = 0 ; a < 4\'d15 ; a = a + 1)
\tfor (b = 0 ; b < 4\'d15 ; b = b + 1)
\t $display("{a, b} == %b", {a, b});
end
endmodule // main
|
module kk_timing (A, B, C, D, E, F);
input A, B, D, E, F;
output C;
wire A, B, D, E, F;
reg C;
wire [1:0] BL;
wire [1:0] BL_X;
assign BL[0] = E;
assign BL_X[0] = F;
wire BL_0 = BL[0] ;
wire BL_X_0 = BL_X[0];
specify
$setuphold(posedge A &&& B, BL[0], 0, 0, C,,,D, BL_X[0]); // line 14 compile fail iverilog_20060618
$setuphold(posedge A &&& B, BL_0 , 0, 0, C,,,D, BL_X[0]); // line 15 compile fail iverilog_20060618
$setuphold(posedge A &&& B, BL[0], 0, 0, C,,,D, BL_X_0 ); // line 16 compile pass iverilog_20060618
$setuphold(posedge A &&& B, BL_0 , 0, 0, C,,,D, BL_X_0 ); // line 17 compile pass iverilog_20060618
endspecify
endmodule
|
module stimulus (output reg A, B);
initial begin
// both inputs are x
#0 {A, B} = 2\'bxx;
// both inputs are z
#10 {A, B} = 2\'bzz;
// one input is a zero
#10 {A, B} = 2\'b0x;
#10 {A, B} = 2\'bx0;
#10 {A, B} = 2\'b0z;
#10 {A, B} = 2\'bz0;
// one input is a one
#10 {A, B} = 2\'b1x;
#10 {A, B} = 2\'bx1;
#10 {A, B} = 2\'b1z;
#10 {A, B} = 2\'bz1;
// one input x, other z
#10 {A, B} = 2\'bxz;
#10 {A, B} = 2\'bzx;
// normal bit operands
#10 {A, B} = 2\'b00;
#10 {A, B} = 2\'b01;
#10 {A, B} = 2\'b10;
#10 {A, B} = 2\'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
// both inputs are x
2\'bxx: gate_output = 1\'bx;
// both inputs are z
2\'bzz: gate_output = 1\'bx;
// output should be zero (one input is a one)
2\'b1x: gate_output = 0;
2\'bx1: gate_output = 0;
2\'b1z: gate_output = 0;
2\'bz1: gate_output = 0;
// output is x (one input is a zero)
2\'b0x: gate_output = 1\'bx;
2\'bx0: gate_output = 1\'bx;
2\'b0z: gate_output = 1\'bx;
2\'bz0: gate_output = 1\'bx;
// inputs x, z
2\'bxz: gate_output = 1\'bx;
2\'bzx: gate_output = 1\'bx;
// normal operation on bit
2\'b00: gate_output = 1;
2\'b01: gate_output = 0;
2\'b10: gate_output = 0;
2\'b11: gate_output = 0;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in NOR operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
nor_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#200;
$display("PASSED");
$finish;
end
endmodule
|
package pkg1;
typedef enum logic [1:0] {
R0 = 2\'b00,
R1 = 2\'b01,
R2 = 2\'b10,
R3 = 2\'b11
} reg_t;
endpackage
module dut(input pkg1::reg_t r1, output pkg1::reg_t r3);
import pkg1::*;
reg_t r2;
always_comb
r2 = r1;
always_comb
r3 = r2;
endmodule
module test();
import pkg1::*;
reg_t v1;
reg_t v2;
dut dut(v1, v2);
reg failed = 0;
initial begin
v1 = R0;
#1 $display("%h %h", v1, v2);
if (v2 !== R0) failed = 1;
v1 = R1;
#1 $display("%h %h", v1, v2);
if (v2 !== R1) failed = 1;
v1 = R2;
#1 $display("%h %h", v1, v2);
if (v2 !== R2) failed = 1;
v1 = R3;
#1 $display("%h %h", v1, v2);
if (v2 !== R3) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Released under GPL2.0
// (c) 2002 Tom Verbeure
module main;
\tinteger myInt;
\treg [39:0] myReg40;
\treg [0:39] myReg40r;
\treg [0:38] myReg39r;
\treg [13:0] myReg14;
\treg [7:0] myReg8;
\treg [31:0] myReg32;
\tinitial begin
\t\t$display("============================ myReg14 = -10");
\t\tmyReg14 = -10;
\t\t$display(">|16374|");
\t\t$display("*|%d|", myReg14);
\t\t$display("*|%0d|", myReg14);
\t\t$display("*|",myReg14,"|");
\t\t$display("============================ myReg14 = 65");
\t\tmyReg14 = 65;
\t\t$display(">| 65|");
\t\t$display("*|%d|", myReg14);
\t\t$display("*|",myReg14,"|");
\t\t$display(">|65|");
\t\t$display("*|%0d|", myReg14);
\t\t$display(">|0041|");
\t\t$display("*|%h|", myReg14);
\t\t$display(">|41|");
\t\t$display("*|%0h|", myReg14);
\t\t$display(">|00101|");
\t\t$display("*|%o|", myReg14);
\t\t$display(">|101|");
\t\t$display("*|%0o|", myReg14);
\t\t$display(">|00000001000001|");
\t\t$display("*|%b|", myReg14);
\t\t$display(">|1000001|");
\t\t$display("*|%0b|", myReg14);
\t\t$display(">| A|");
\t\t$display("*|%s|", myReg14);
\t\t$display(">|A|");
\t\t$display("*|%0s|", myReg14);
\t\t$display("============================ myInt = -10");
\t\tmyInt = -10;
\t\t$display(">| -10|");
\t\t$display("*|%d|", myInt);
\t\t$display("*|",myInt,"|");
\t\t$display(">|-10|");
\t\t$display("*|%0d|", myInt);
\t\t$display(">|fffffff6|");
\t\t$display("*|%h|", myInt);
\t\t$display("*|%0h|", myInt);
\t\t$display(">|37777777766|");
\t\t$display("*|%o|", myInt);
\t\t$display("*|%0o|", myInt);
\t\t$display(">|11111111111111111111111111110110|");
\t\t$display("*|%b|", myInt);
\t\t$display("*|%0b|", myInt);
\t\t$display("============================ myReg32 = -10");
\t\tmyReg32 = -10;
\t\t$display(">|4294967286|");
\t\t$display("*|%d|", myReg32);
\t\t$display("*|%0d|", myReg32);
\t\t$display("*|",myReg32,"|");
\t\t$display(">|fffffff6|");
\t\t$display("*|%h|", myReg32);
\t\t$display("*|%0h|", myReg32);
\t\t$display(">|37777777766|");
\t\t$display("*|%o|", myReg32);
\t\t$display("*|%0o|", myReg32);
\t\t$display("============================ myInt = 65");
\t\tmyInt = 65;
\t\t$display(">| 65|");
\t\t$display("*|%d|", myInt);
\t\t$display("*|",myInt,"|");
\t\t$display(">|65|");
\t\t$display("*|%0d|", myInt);
\t\t$display(">|00000041|");
\t\t$display("*|%h|", myInt);
\t\t$display(">|41|");
\t\t$display("*|%0h|", myInt);
\t\t$display(">|00000000101|");
\t\t$display("*|%o|", myInt);
\t\t$display(">|101|");
\t\t$display("*|%0o|", myInt);
\t\t$display(">|00000000000000000000000001000001|");
\t\t$display("*|%b|", myInt);
\t\t$display(">|1000001|");
\t\t$display("*|%0b|", myInt);
\t\t$display("*| A|");
\t\t$display(">|%s|", myInt);
\t\t$display("*|A|");
\t\t$display(">|%0s|", myInt);
\t\t$display("============================ Print \\" A\\"");
\t\t$display("*| A|");
\t\t$display(">|%s|", " A");
\t\t$display(">|%0s|", " A");
\t\t$display("============================ Print $time");
\t\t$display("*| 0|");
\t\t$display(">|%t|", $time);
\t\t$display("*|0|");
\t\t$display(">|%0t|", $time);
\tend
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary nor ~|(value)
//
module main;
reg [3:0] vect;
reg\terror;
wire\tresult;
assign result = ~|(vect);
initial
begin
error = 0;
for(vect=4\'b0001;vect<4\'b1111;vect = vect + 1)
begin
#1;
if(result !== 1\'b0)
begin
$display("FAILED - Unary nor ~|(%b)=%b",vect,result);
error = 1\'b1;
end
end
#1;
vect = 4\'b0000;
#1;
if(result !== 1\'b1)
begin
$display("FAILED - Unary nor |~(%b)=%b",vect,result);
error = 1\'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
module bug();
reg [1:0][15:0][7:0] array;
reg failed = 0;
integer i;
reg [3:0] index;
initial begin
i = $bits(array);
$display("width 0 = %0d", i);
if (i !== 256) failed = 1;
i = $bits(array[0]);
$display("width 1 = %0d", i);
if (i !== 128) failed = 1;
i = $bits(array[0][0]);
$display("width 2 = %0d", i);
if (i !== 8) failed = 1;
for (i = 0; i < 16; i++) begin
index = i[3:0];
array[0][index] = {4\'d0, index};
array[1][index] = {4\'d1, index};
end
$display("%h", array);
if (array !== 256\'h1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100)
failed = 1;
for (i = 0; i < 16; i++) begin
index = i[3:0];
$display("%h : %h %h", index, array[0][index], array[1][index]);
if (array[0][index] !== {4\'d0, index}) failed = 1;
if (array[1][index] !== {4\'d1, index}) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module add32(sum, cOut, clock, a, b, cIn);
input clock;
input a, b, cIn;
output sum, cOut;
reg [31:0] a, b;
reg cIn;
wire [31:0] sum;
wire cOut;
always @(posedge clock)
//{cOut, sum} = a + b + cIn;
assign sum = a + b + cIn;
endmodule
//////////////////////////
module main;
reg CLOCK;
reg [31:0] A, B;
reg C_IN;
reg [31:0] SUM;
wire C_OUT;
add32 myAdder(SUM, C_OUT, CLOCK, A, B, C_OUT);
always #1 CLOCK = ~ CLOCK;
initial
begin
$monitor($time,, " CLOCK=%d, A=%x, B=%x, C_IN=%d -- SUM=%x, C_OUT=%d",
CLOCK, A, B, C_IN, SUM, C_OUT);
end
initial
begin
CLOCK = 0;
A = 32\'h00000001;
B = 32\'h00000002;
C_IN = 1\'b0;
#20 $finish;
end
endmodule
|
// Extended version of original test case, covering part-driven operands
// for all logical operations.
module pr2974051;
wire [7:0] a;
wire [7:0] b;
reg\t c;
assign a[5:2] = 4\'b0101;
assign b[5:2] = 4\'b1010;
wire [7:0] d = c ? b : a;
wire [7:0] e = a & b;
wire [7:0] f = a | b;
wire [7:0] g = a ^ b;
wire [7:0] h = a;
wire [7:0] i = ~a;
reg fail;
initial begin
fail = 0;
c = 0;
#1 $display("%b", d);
if (d !== 8\'bzz0101zz) fail = 1;
c = 1;
#1 $display("%b", d);
if (d !== 8\'bzz1010zz) fail = 1;
#1 $display("%b", e);
if (e !== 8\'bxx0000xx) fail = 1;
#1 $display("%b", f);
if (f !== 8\'bxx1111xx) fail = 1;
#1 $display("%b", g);
if (g !== 8\'bxx1111xx) fail = 1;
#1 $display("%b", h);
if (h !== 8\'bzz0101zz) fail = 1;
#1 $display("%b", i);
if (i !== 8\'bxx1010xx) fail = 1;
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that using a real type as the base type for an enum results in an
// error.
module test;
typedef real T;
enum T {
A
} e;
initial begin
$display("FAILED");
end
endmodule
|
// Note: when __ICARUS_UNSIZED__ is not defined, this test assumes integers
// are 32 bits wide.
module main();
reg [34:0] my_reg;
reg\t error;
reg [34:0] ref_val;
reg [34:0] ref_val2;
reg [7:0] count;
initial
begin
\t error = 0;
\t // Create reference value that is bigger than 32 bits...
\t ref_val = 0;
\t ref_val[0] = 1;
\t ref_val[34] = 1;
\t $display("*:%d", ref_val);
\t ref_val2 = 35\'h7ffffffff;
\t $display("*:%d", ref_val2);
\t // Trivial test to see that small unsized integers still work.
\t my_reg = 100;
\t if (my_reg != \'h64)
\t begin
\t error = 1;
\t $display("Error: expected 100");
\t end
\t my_reg = 17179869185;
\t $display("1:%d", my_reg);
`ifdef __ICARUS_UNSIZED__
\t // Ordinary compilers will truncate unsized integer
\t // constants to 32bits. Icarus Verilog is more generous.
\t if (my_reg !== 35\'h4_00000001) begin
\t error = 1;
\t $display("Error: expected 17179869185");
\t end
`else
\t // Unsized integers bigger than 32 bits are truncated...
\t // Value below has bit 34 and bit 0 set to \'1\'
\t if (my_reg != 1)
\t begin
\t error = 1;
\t $display("Error: expected 1");
\t end
`endif
\t // Another unsized integer, but this time \'d specifier...
\t my_reg = \'d17179869184;
\t $display("2:%d", my_reg);
`ifdef __ICARUS_UNSIZED__
\t // Ordinary compilers will truncate unsized integer
\t // constants to 32bits. Icarus Verilog is more generous.
\t if (my_reg !== 35\'h4_00000000) begin
\t error = 1;
\t $display("Error: expected 17179869184");
\t end
`else
\t if (my_reg != 0)
\t begin
\t error = 1;
\t $display("Error: expected 1");
\t end
`endif
\t // This should finally work!
\t my_reg = 35\'sd17179869185;
\t $display("3:%d", my_reg);
\t if (my_reg != ref_val)
\t begin
\t error = 1;
\t $display("Error: expected 17179869185");
\t end
\t // This should work too.
\t my_reg = 35\'d 17179869185;
\t $display("4:%d", my_reg);
\t if (my_reg != ref_val)
\t begin
\t error = 1;
\t $display("Error: expected 17179869185");
\t end
\t // Overflow...
\t my_reg = 35\'d 34359738369;
\t $display("5:%d", my_reg);
\t if (my_reg != 1)
\t begin
\t error = 1;
\t $display("Error: expected 1");
\t end
\t // Just no overflow
\t my_reg = 35\'d 34359738367;
\t $display("6:%d", my_reg);
\t if (my_reg != ref_val2)
\t begin
\t error = 1;
\t $display("Error: expected 34359738367");
\t end
`ifdef __ICARUS_UNSIZED__
\t // Since Icarus Verilog doesn\'t truncate constant values,
\t // the whole idea of truncating then sign-extending the result
\t // to go into the wide reg does not apply. So skip this
\t // test.
`else
\t // Unsized integers bigger than 32 bits are truncated...
\t // Here all the bits are set. Since there is no \'d prefix,
\t // it will be sign extended later on.
\t my_reg = 17179869183;
\t $display("7:%d", my_reg);
\t if (my_reg != ref_val2)
\t begin
\t error = 1;
\t $display("Error: expected 34359738367");
\t end
`endif
\t // Unsized integers bigger than 32 bits are truncated...
\t // Here all the bits are set. Since there *IS* a \'d prefix
\t // it will NOT be sign extended later on.
\t my_reg = \'d17179869183;
\t $display("8:%d", my_reg);
`ifdef __ICARUS_UNSIZED__
\t if (my_reg != \'d17179869183)
\t begin
\t error = 1;
\t $display("Error: expected \'d17179869183");
\t end
`else
\t if (my_reg != \'d4294967295)
\t begin
\t error = 1;
\t $display("Error: expected 4294967295");
\t end
`endif
\t if (error==1)
\t begin
\t $display("FAILED");
\t end
\t else
\t begin
\t $display("PASSED");
\t end
\t $finish;
end
endmodule
|
/*
* This demonstrates a basic dynamic array
*/
module main;
byte foo[];
int idx;
initial begin
if (foo.size() != 0) begin
\t $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
\t $finish;
end
foo = new[10];
if (foo.size() != 10) begin
\t $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
\t $finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
\t foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
\t $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
\t $finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
\t $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
\t $finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
\t if (foo[idx%10] != (idx%10)) begin
\t $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]);
\t $finish;
\t end
end
foo.delete();
if (foo.size() != 0) begin
\t $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
`define TESTFILE "ivltests/pr3012758.inc"
module top;
`include `TESTFILE
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Comma separated parameter def used as a width subscript
//
//
// D: This validates that parameters can be used as literals
// D: in the width subscript.
//
module main();
parameter VAL_1 = 5,
VAL_2 = 0;
reg [VAL_1: VAL_2] temp_var;
initial // Excitation block
begin
temp_var = 6\'h11;
#5 ;
end
initial // Validation block
begin
#1 ;
if(temp_var != 6\'h11)
begin
$display("FAILED - parameter assignment didn\'t work\
");
$finish ;
end
$display("PASSED\
");
$finish ;
end
endmodule
|
// Check that declaring a non-ANSI task port with an explicit type for a signal
// that was previously declared real variable is an error.
module test;
task t;
real x;
output integer x;
$display("FAILED");
endtask
real y;
initial t(y);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always force reg_lvalue = boolean_expr ;
// D: This is an infinite loop - thus compile only
// SJW - rework from akways3.1.3E to make it runnable.
module main ;
reg [3:0] value1 ;
initial
begin
#15;
if(value1 !== 4\'b1)
$display("FAILED - 3.1.3E always force reg_lvalue = boolean_expr;");
else
$display("PASSED");
$finish;
end
always #10 force value1 = 1\'b1 & 1\'b1 ;
endmodule
|
/*
* See PR#810 in the test suite.
*/
`timescale 1 ns / 1 ps
module RR64X1_4LA1 ();
parameter I_AADR_01_DOA_01_T2 = 1.167000;
parameter I_AADR_10_DOA_01_T2 = 1.176000;
parameter taaa_d1 = ( I_AADR_01_DOA_01_T2 > I_AADR_10_DOA_01_T2 )
? I_AADR_01_DOA_01_T2 : I_AADR_10_DOA_01_T2;
parameter I_AADR_01_DOA_10_T2 = 1.276000;
parameter I_AADR_10_DOA_10_T2 = 1.267000;
parameter taaa_d0 = ( I_AADR_01_DOA_10_T2 > I_AADR_10_DOA_10_T2 )
? I_AADR_01_DOA_10_T2 : I_AADR_10_DOA_10_T2;
parameter taaa = ( taaa_d1 > taaa_d0 ) ? taaa_d1 : taaa_d0;
initial begin
if (taaa_d1 != I_AADR_10_DOA_01_T2) begin
\t $display("FAILED -- taaa_d1=%f", taaa_d1);
\t $finish;
end
if (taaa_d0 != I_AADR_01_DOA_10_T2) begin
\t $display("FAILED -- taaa_d0=%f", taaa_d0);
\t $finish;
end
if (taaa != taaa_d0) begin
\t $display("FAILED -- taaa=%f", taaa);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule
|
// This tests the basic support for default arguments to task/function
// ports. The default port syntax gives SystemVerilog a limited form
// of variable argument lists.
program main;
class foo_t;
int int_val;
logic [3:0] log_val;
task init (int int_init, logic[3:0] log_init = 4\'bzzzz);
\t int_val = int_init;
\t log_val = log_init;
endtask
endclass : foo_t
foo_t obj1;
initial begin
obj1 = new;
obj1.init(5, 4\'b1111);
if (obj1.int_val != 5 || obj1.log_val !== 4\'b1111) begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b", obj1.int_val, obj1.log_val);
\t $finish;
end
obj1 = new;
obj1.init(7);
if (obj1.int_val != 7 || obj1.log_val !== 4\'bzzzz) begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%0s", obj1.int_val, obj1.log_val);
\t $finish;
end
$display("PASSED");
end
endprogram // main
|
module top;
parameter parm = 1;
parameter name_v = 1; // genvar
localparam name_lpv = 0; // genvar
parameter name_t = 1; // task
parameter name_f = 1; // function
parameter name_i = 1; // module instance
parameter name_b = 1; // named block
parameter name_gl = 1; // generate block loop
parameter name_gi = 1; // generate block if
parameter name_gc = 1; // generate block case
parameter name_gb = 1; // generate block
parameter name_e = 1; // named event
parameter name_s = 1; // signal
wire [1:0] out;
/***********
* Check genvars
***********/
// Check genvar/parameter name issues.
genvar name_v;
generate
for (name_v = 0; name_v < 2; name_v = name_v + 1) begin
assign out[name_v] = name_v;
end
endgenerate
// Check genvar/localparam name issues.
genvar name_lpv;
generate
for (name_lpv = 0; name_lpv < 2; name_lpv = name_lpv + 1) begin
assign out[name_lpv] = name_lpv;
end
endgenerate
// Check genvar/genvar name issues.
// This is in a different file since this fails during parsing.
/***********
* Check tasks.
***********/
// Check task/parameter name issues.
task name_t;
$display("FAILED in task name_t");
endtask
// Check task/task name issues.
// This is in a different file since this fails during parsing.
// Check task/genvar name issues.
genvar name_tv;
generate
for (name_tv = 0; name_tv < 2; name_tv = name_tv + 1) begin
assign out[name_tv] = name_tv;
end
endgenerate
task name_tv;
$display("FAILED in task name_tv");
endtask
/***********
* Check functions.
***********/
// Check function/parameter name issues.
function name_f;
input in;
name_f = in;
endfunction
// Check function/task name issues.
task name_ft;
$display("FAILED in task name_ft");
endtask
function name_ft;
input in;
name_tf = in;
endfunction
// Check function/function name issues.
// This is in a different file since this fails during parsing.
// Check function/genvar name issues.
genvar name_fv;
generate
for (name_fv = 0; name_fv < 2; name_fv = name_fv + 1) begin
assign out[name_fv] = name_fv;
end
endgenerate
function name_fv;
input in;
name_fv = in;
endfunction
/***********
* Check module instances.
***********/
// Check modul instance/parameter name issues.
test name_i(out[0]);
// Check module instance/task name issues.
task name_it;
$display("FAILED in task name_it");
endtask
test name_it(out[0]);
// Check module instance/function name issues.
function name_if;
input in;
name_if = in;
endfunction
test name_if(out[0]);
// Check module instance/genvar name issues.
genvar name_iv;
generate
for (name_iv = 0; name_iv < 2; name_iv = name_iv + 1) begin
assign out[name_iv] = name_iv;
end
endgenerate
test name_iv(out[1]);
// Check module instance/module instance name issues.
test name_ii(out[0]);
test name_ii(out[1]);
/***********
* Check named blocks.
***********/
// Check named block/parameter name issues.
initial begin: name_b
$display("FAILED in name_b");
end
// Check named block/task name issues.
task name_bt;
$display("FAILED in task name_bt");
endtask
initial begin: name_bt
$display("FAILED in name_bt");
end
// Check named block/function name issues.
function name_bf;
input in;
name_bf = in;
endfunction
initial begin: name_bf
$display("FAILED in name_bf");
end
// Check named block/genvar name issues.
genvar name_bv;
generate
for (name_bv = 0; name_bv < 2; name_bv = name_bv + 1) begin
assign out[name_bv] = name_bv;
end
endgenerate
initial begin: name_bv
$display("FAILED in name_bv");
end
// Check named block/module instance name issues.
test name_bi(out[0]);
initial begin: name_bi
$display("FAILED in name_bi");
end
// Check named block/named block name issues.
initial begin: name_bb
$display("FAILED in name_bb(a)");
end
initial begin: name_bb
$display("FAILED in name_bb(b)");
end
/***********
* Check named events
***********/
// Check named event/parameter name issues.
event name_e;
// Check named event/task name issues.
task name_et;
$display("FAILED in task name_et");
endtask
event name_et;
// Check named event/function name issues.
function name_ef;
input in;
name_ef = in;
endfunction
event name_ef;
// Check named event/genvar name issues.
genvar name_ev;
generate
for (name_ev = 0; name_ev < 2; name_ev = name_ev + 1) begin
assign out[name_ev] = name_ev;
end
endgenerate
event name_ev;
// Check named event/module instance name issues.
test name_ei(out[0]);
event name_ei;
// Check named event/named block name issues.
initial begin: name_eb
$display("FAILED in name_eb");
end
event name_eb;
// Check named event/named event name issues.
// This is in a different file since this fails during parsing.
/***********
* Check generate loop blocks
***********/
genvar i;
// Check generate loop/parameter name issues.
generate
for (i = 0; i < 2; i = i + 1) begin: name_gl
assign out[i] = i;
end
endgenerate
// Check generate loop/task name issues.
task name_glt;
$display("FAILED in task name_glt");
endtask
generate
for (i = 0; i < 2; i = i + 1) begin: name_glt
assign out[i] = i;
end
endgenerate
// Check generate loop/function name issues.
function name_glf;
input in;
name_glf = in;
endfunction
generate
for (i = 0; i < 2; i = i + 1) begin: name_glf
assign out[i] = i;
end
endgenerate
// Check generate loop/genvar name issues.
genvar name_glv;
generate
for (name_glv = 0; name_glv < 2; name_glv = name_glv + 1) begin
assign out[name_glv] = name_glv;
end
endgenerate
generate
for (i = 0; i < 2; i = i + 1) begin: name_glv
assign out[i] = i;
end
endgenerate
// Check generate loop/module instance name issues.
test name_gli(out[0]);
generate
for (i = 0; i < 2; i = i + 1) begin: name_gli
assign out[i] = i;
end
endgenerate
// Check generate loop/named block name issues.
initial begin: name_glb
$display("FAILED in name_glb");
end
generate
for (i = 0; i < 2; i = i + 1) begin: name_glb
assign out[i] = i;
end
endgenerate
// Check generate loop/named event name issues.
event name_gle;
generate
for (i = 0; i < 2; i = i + 1) begin: name_gle
assign out[i] = i;
end
endgenerate
// Check generate loop/generate loop name issues.
generate
for (i = 0; i < 2; i = i + 1) begin: name_glgl
assign out[i] = i;
end
endgenerate
generate
for (i = 0; i < 2; i = i + 1) begin: name_glgl
assign out[i] = i;
end
endgenerate
/***********
* Check generate if blocks
***********/
// Check generate if/parameter name issues.
generate
if (parm == 1) begin: name_gi
assign out[1] = 1;
end
endgenerate
// Check generate if/task name issues.
task name_git;
$display("FAILED in task name_git");
endtask
generate
if (parm == 1) begin: name_git
assign out[1] = 1;
end
endgenerate
// Check generate if/function name issues.
function name_gif;
input in;
name_gif = in;
endfunction
generate
if (parm == 1) begin: name_gif
assign out[1] = 1;
end
endgenerate
// Check generate if/genvar name issues.
genvar name_giv;
generate
for (name_giv = 0; name_giv < 2; name_giv = name_giv + 1) begin
assign out[name_giv] = name_giv;
end
endgenerate
generate
if (parm == 1) begin: name_giv
assign out[1] = 1;
end
endgenerate
// Check generate if/module instance name issues.
test name_gii(out);
generate
if (parm == 1) begin: name_gii
assign out[1] = 1;
end
endgenerate
// Check generate if/named block name issues.
initial begin: name_gib
$display("FAILED in name_gib");
end
generate
if (parm == 1) begin: name_gib
assign out[1] = 1;
end
endgenerate
// Check generate if/named event name issues.
event name_gie;
generate
if (parm == 1) begin: name_gie
assign out[1] = 1;
end
endgenerate
// Check generate if/generate if name issues.
generate
if (parm == 1) begin: name_gigi
assign out[1] = 1;
end
endgenerate
generate
if (parm == 1) begin: name_gigi
assign out[1] = 0;
end
endgenerate
/***********
* Check generate case blocks
***********/
// Check generate case/parameter name issues.
generate
case (parm)
1: begin: name_gc
assign out[1] = 1;
end
default: begin: name_gc
assign out[1] = 0;
end
endcase
endgenerate
// Check generate case/task name issues.
task name_gct;
$display("FAILED in task name_gct");
endtask
generate
case (parm)
1: begin: name_gct
assign out[1] = 1;
end
default: begin: name_gct
assign out[1] = 0;
end
endcase
endgenerate
// Check generate case/function name issues.
function name_gcf;
input in;
name_gcf = in;
endfunction
generate
case (parm)
1: begin: name_gcf
assign out[1] = 1;
end
default: begin: name_gcf
assign out[1] = 0;
end
endcase
endgenerate
// Check generate case/genvar name issues.
genvar name_gcv;
generate
for (name_gcv = 0; name_gcv < 2; name_gcv = name_gcv + 1) begin
assign out[name_gcv] = name_gcv;
end
endgenerate
generate
case (parm)
1: begin: name_gcv
assign out[1] = 1;
end
default: begin: name_gcv
assign out[1] = 0;
end
endcase
endgenerate
// Check generate case/module instance name issues.
test name_gci(out[0]);
generate
case (parm)
1: begin: name_gci
assign out[1] = 1;
end
default: begin: name_gci
assign out[1] = 0;
end
endcase
endgenerate
// Check generate case/named block name issues.
initial begin: name_gcb
$display("FAILED in name_gcb");
end
generate
case (parm)
1: begin: name_gcb
assign out[1] = 1;
end
default: begin: name_gcb
assign out[1] = 0;
end
endcase
endgenerate
// Check generate case/named event name issues.
event name_gce;
generate
case (parm)
1: begin: name_gce
assign out[1] = 1;
end
default: begin: name_gce
assign out[1] = 0;
end
endcase
endgenerate
// Check generate case/generate case name issues.
generate
case (parm)
1: begin: name_gcgc
assign out[1] = 1;
end
default: begin: name_gcgc
assign out[1] = 0;
end
endcase
endgenerate
generate
case (parm)
1: begin: name_gcgc
assign out[1] = 1;
end
default: begin: name_gcgc
assign out[1] = 0;
end
endcase
endgenerate
/***********
* Check generate blocks (from 1364-2001)
***********/
// Check generate block/parameter name issues.
generate
begin: name_gb
assign out[0] = 0;
end
endgenerate
// Check generate block/task name issues.
task name_gbt;
$display("FAILED in task name_gbt");
endtask
generate
begin: name_gbt
assign out[0] = 0;
end
endgenerate
// Check generate block/function name issues.
function name_gbf;
input in;
name_gbf = in;
endfunction
generate
begin: name_gbf
assign out[0] = 0;
end
endgenerate
// Check generate block/genvar name issues.
genvar name_gbv;
generate
for (name_gbv = 0; name_gbv < 2; name_gbv = name_gbv + 1) begin
assign out[name_gbv] = name_gbv;
end
endgenerate
generate
begin: name_gbv
assign out[0] = 0;
end
endgenerate
// Check generate block/module instance name issues.
test name_gbi(out[0]);
generate
begin: name_gbi
assign out[0] = 0;
end
endgenerate
// Check generate block/named block name issues.
initial begin: name_gbb
$display("FAILED in name_gbb");
end
generate
begin: name_gbb
assign out[0] = 0;
end
endgenerate
// Check generate case/named event name issues.
event name_gbe;
generate
begin: name_gbe
assign out[0] = 0;
end
endgenerate
// Check generate case/generate case name issues.
generate
begin: name_gbgb
assign out[0] = 0;
end
endgenerate
generate
begin: name_gbgb
assign out[0] = 0;
end
endgenerate
initial $display("FAILED");
endmodule
module test(out);
output out;
reg out = 1\'b0;
endmodule
|
// Check that declaring a net of string type results in an error
module test;
wire string x;
initial begin
$display("FAILED");
end
endmodule
|
module stimulus (output reg A, B);
initial begin
// both inputs are x
#0 {A, B} = 2\'bxx;
// both inputs are z
#10 {A, B} = 2\'bzz;
// one input is a zero
#10 {A, B} = 2\'b0x;
#10 {A, B} = 2\'bx0;
#10 {A, B} = 2\'b0z;
#10 {A, B} = 2\'bz0;
// one input is a one
#10 {A, B} = 2\'b1x;
#10 {A, B} = 2\'bx1;
#10 {A, B} = 2\'b1z;
#10 {A, B} = 2\'bz1;
// one input x, other z
#10 {A, B} = 2\'bxz;
#10 {A, B} = 2\'bzx;
// normal bit operands
#10 {A, B} = 2\'b00;
#10 {A, B} = 2\'b01;
#10 {A, B} = 2\'b10;
#10 {A, B} = 2\'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
// both inputs are x
2\'bxx: gate_output = 1\'bx;
// both inputs are z
2\'bzz: gate_output = 1\'bx;
// output should be one (one input is a one)
2\'b1x: gate_output = 1;
2\'bx1: gate_output = 1;
2\'b1z: gate_output = 1;
2\'bz1: gate_output = 1;
// output is x (one input is a zero)
2\'b0x: gate_output = 1\'bx;
2\'bx0: gate_output = 1\'bx;
2\'b0z: gate_output = 1\'bx;
2\'bz0: gate_output = 1\'bx;
// inputs x, z
2\'bxz: gate_output = 1\'bx;
2\'bzx: gate_output = 1\'bx;
// normal operation on bit
2\'b00: gate_output = 0;
2\'b01: gate_output = 1;
2\'b10: gate_output = 1;
2\'b11: gate_output = 1;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in OR operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
or_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#200;
$display("PASSED");
$finish;
end
endmodule
|
/*
* This is the most basic test of string variables.
*/
module main;
string foo;
string bar;
initial begin
foo = "foo";
bar = "bar";
if (foo != "foo") begin
\t $display("FAILED -- foo=%0s (1)", foo);
\t $finish;
end
if (bar != "bar") begin
\t $display("FAILED -- bar=%0s (2)", bar);
\t $finish;
end
if (foo == bar) begin
\t $display("FAILED -- %0s == %0s (3)", foo, bar);
\t $finish;
end
if (! (foo != bar)) begin
\t $display("FAILED -- ! (%0s != %0s) (4)", foo, bar);
\t $finish;
end
if (bar > foo) begin
\t $display("FAILED -- %s > %s (5)", bar, foo);
\t $finish;
end
if (bar >= foo) begin
\t $display("FAILED -- %s >= %s (6)", bar, foo);
\t $finish;
end
if (foo < bar) begin
\t $display("FAILED -- %s < %s (7)", foo, bar);
\t $finish;
end
if (foo <= bar) begin
\t $display("FAILED -- %s <= %s (8)", foo, bar);
\t $finish;
end
bar = foo;
if (foo != bar) begin
\t $display("FAILED -- %0s != %0s (9)", foo, bar);
\t $finish;
end
if (foo > bar) begin
\t $display("FAILED -- %0s > %0s (10)", foo, bar);
\t $finish;
end
if (foo < bar) begin
\t $display("FAILED -- %0s < %0s (11)", foo, bar);
\t $finish;
end
if (! (foo == bar)) begin
\t $display("FAILED -- ! (%0s == %0s) (12)", foo, bar);
\t $finish;
end
if (! (foo <= bar)) begin
\t $display("FAILED -- ! (%0s <= %0s) (13)", foo, bar);
\t $finish;
end
if (! (foo >= bar)) begin
\t $display("FAILED -- ! (%0s >= %0s) (14)", foo, bar);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
// Check behaviour with out-of-range and undefined array indices
// on LHS of procedural continuous (reg) assignment.
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg [1:0] array1[2:1];
reg [1:0] array2[1:0];
reg [1:0] var1;
`ifndef VLOG95
real array3[2:1];
real array4[1:0];
real var2;
`endif
reg failed;
initial begin
failed = 0;
array1[1] = 2\'d0;
array1[2] = 2\'d0;
array2[0] = 2\'d0;
array2[1] = 2\'d0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array1[0] = 2\'d1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d0)) failed = 1;
deassign array1[0];
`endif
/* This is not supported at present
assign array1[1] = 2\'d1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2\'d1) || (array1[2] !== 2\'d0)) failed = 1;
deassign array1[1];
assign array1[2] = var1;
var1 = 2\'d1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d1)) failed = 1;
var1 = 2\'d2;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d2)) failed = 1;
deassign array1[2];
*/
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array1[3] = var1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d0)) failed = 1;
deassign array1[3];
assign array2[\'bx] = 2\'d1;
#1 $display("array = %h %h", array2[1], array2[0]);
if ((array2[0] !== 2\'d0) || (array2[1] !== 2\'d0)) failed = 1;
deassign array2[\'bx];
`endif
`ifndef VLOG95
array3[1] = 0.0;
array3[2] = 0.0;
array4[0] = 0.0;
array4[1] = 0.0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array3[0] = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[0];
`endif
/* This is not supported at present
assign array3[1] = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 1.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[1];
assign array3[2] = var2;
var2 = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 1.0)) failed = 1;
var2 = 2.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 2.0)) failed = 1;
deassign array3[2];
*/
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array3[3] = var2;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[3];
assign array4[\'bx] = 1.0;
#1 $display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
deassign array4[\'bx];
`endif
`endif
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module top;
reg pass;
reg result;
reg [3:0] expr;
initial begin
pass = 1\'b1;
result = $isunknown(1\'b0);
if (result != 0) begin
$display("FAILED: for 1\'b0 expected 0, got %b", result);
pass = 1\'b0;
end
result = $isunknown(1\'b1);
if (result != 0) begin
$display("FAILED: for 1\'b1 expected 0, got %b", result);
pass = 1\'b0;
end
result = $isunknown(2\'b01);
if (result != 0) begin
$display("FAILED: for 2\'b01 expected 0, got %b", result);
pass = 1\'b0;
end
result = $isunknown(4\'b0x11);
if (result != 1) begin
$display("FAILED: for 4\'b0x11 expected 1, got %b", result);
pass = 1\'b0;
end
expr = 4\'b110x;
result = $isunknown(expr);
if (result != 1) begin
$display("FAILED: for 4\'b110x expected 1, got %b", result);
pass = 1\'b0;
end
result = $isunknown(34\'bx100000000000000000000000000000001);
if (result != 1) begin
$display("FAILED: for 34\'x100000000000000000000000000000001 expected 1, got %b", result);
pass = 1\'b0;
end
result = $isunknown(34\'b100000000000000000000000000000000x);
if (result != 1) begin
$display("FAILED: for 34\'100000000000000000000000000000000x expected 1, got %b", result);
pass = 1\'b0;
end
result = $isunknown(34\'b1000000000000000000000000000000000);
if (result != 0) begin
$display("FAILED: for 34\'1000000000000000000000000000000000 expected 0, got %b", result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
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