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module top;
// Does this have to be signed?
wire signed [7:0] out;
// Either of these will not expand correctly.
// assign out = 'sh1f;
assign out = 5'sh1f;
initial #1 $displayb(out);
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: dangling_port.v,v 1.1 2001/07/08 03:22:08 sib4 Exp $
// $Log: dangling_port.v,v $
// Revision 1.1 2001/07/08 03:22:08 sib4
// Test for PR#209
//
//
// Test for PR#209, VVP wrong nodangle of dangling port.
module main;
reg retval;
reg a, b;
function f;
input dangle;
begin
\t f = retval;
end
endfunction
initial
begin
\t#1 retval <= 1;
\t#1 a <= f(0);
\t#1 b <= f(1);
\t#1 $display("PASSED");
\t$finish;
end
endmodule
|
module main;
typedef union packed {
logic [3:0] bits;
struct packed { logic [1:0] hig; logic [1:0] low; } words;
} bits_t;
bits_t foo;
initial begin
foo.bits = \'b1001;
if (foo.bits !== \'b1001) begin
\t $display("FAILED -- foo.bits=%b", foo.bits);
\t $finish;
end
if (foo.words !== \'b1001) begin
\t $display("FAILED -- foo.words=%b", foo.words);
\t $finish;
end
//foo.words.low = \'b00;
//foo.words.hig = \'b11;
foo.words = \'b1100;
if (foo.words !== \'b1100) begin
\t $display("FAILED -- foo.words=%b", foo.words);
\t $finish;
end
if (foo.bits !== \'b1100) begin
\t $display("FAILED -- foo.bits=%b", foo.bits);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* Do some run time checks with $ferror(). We can not count on the return
* code or the strings to be the same on different machines so we can only
* look for the existence of an error and call that good enough. We humans
* can look at the full output to see if it is correct.
*/
module top;
parameter work_file = "work/pr2800985.txt";
reg pass;
integer errno, bfd, vfd, mcd, res;
reg [639:0] result, str;
/*
* Tasks to check and clear the error state.
*/
task check_error;
begin
// Check that there was an error.
if (errno == 0) begin
$display(" FAILED: expected an error!");
pass = 1\'b0;
end
clear_error;
end
endtask
task clear_error;
begin
// Clear the error state.
res = $ftell(vfd);
errno = $ferror(vfd, result);
if (errno != 0) begin
$display("Failed to clear error state (%0s)", result);
$finish;
end
end
endtask
initial begin
pass = 1\'b1;
vfd = $fopen(work_file, "w+");
if (vfd == 0) begin
errno = $ferror(vfd, result);
$display("Failed to open required file %s (%0s).", work_file, result);
$finish;
end
/*
* $ferror() only takes a fd, so a valid MCD is not valid..
*/
$display("Check a valid MCD.");
errno = $ferror(1, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Basic $fopen() checking.
*/
$display("Opening a file that does not exist.");
bfd = $fopen("FileDoesNotExist", "r");
$display(" $fopen returned: %h", bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* These do not work when the user has root privileges, so we need to
* just skip them.
*
$display("Opening a file that we should not be able to write to.");
bfd = $fopen("/FileDoesNotExist", "w");
$display(" $fopen returned: %h", bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
$display("Opening a file that we should not be able to write to (MCD).");
mcd = $fopen("/FileDoesNotExist");
$display(" $fopen returned: %h", mcd);
errno = $ferror(mcd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
*/
$display("Opening a directory we should not be able to write.");
bfd = $fopen("/", "w");
$display(" $fopen returned: %h", bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $fclose().
*/
$display("Checking $fclose with fd 0 and -1.");
bfd = 0;
$fclose(bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
$fclose(bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $fdisplay(), assume the b/h/o version work the same.
*/
$display("Checking $fdisplay with fd 0 and -1.");
bfd = 0;
$fdisplay(bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
$fdisplay(bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $fwrite(), assume the b/h/o version work the same.
*/
$display("Checking $fwrite with fd 0 and -1.");
bfd = 0;
$fwrite(bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
$fwrite(bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $fstrobe(), assume the b/h/o version work the same.
*/
$display("Checking $fstrobe with fd 0 and -1.");
bfd = 0;
$fstrobe(bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
$fstrobe(bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $fgetc().
*/
$display("Checking $fgetc with fd 0 and -1.");
bfd = 0;
res = $fgetc(bfd);
$display(" $fgetc returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
res = $fgetc(bfd);
$display(" $fgetc returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $ungetc().
*/
$display("Checking $ungetc with fd 0 and -1 and char = EOF.");
bfd = 0;
res = $ungetc(0, bfd);
$display(" $ungetc returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
res = $ungetc(0, bfd);
$display(" $ungetc returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
// This returns EOF (-1), but does not set errno.
res = $ungetc(-1, vfd);
$display(" $ungetc returned: %0d", res);
errno = $ferror(vfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
if (res != -1 || errno != 0) begin
$display(" Failed expected result (-1, 0), got (%0d, %0d).", res, errno);
// It\'s OK if this returns a value in errno.
if (res != -1) pass = 1\'b0;
clear_error;
end
/*
* Check $fgets().
*/
$display("Checking $fgets with fd 0 and -1.");
bfd = 0;
res = $fgets(str, bfd);
$display(" $fgets returned: %0d, \'%0s\'", res, str);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
res = $fgets(str, bfd);
$display(" $fgets returned: %0d, \'%0s\'", res, str);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $fscanf().
*/
$display("Checking $fscanf with fd 0 and -1.");
bfd = 0;
res = $fscanf(bfd, "%s", str);
$display(" $fscanf returned: %0d, \'%0s\'", res, str);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
res = $fscanf(bfd, "%s", str);
$display(" $fscanf returned: %0d, \'%0s\'", res, str);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $fread().
*/
$display("Checking $fread with fd 0 and -1.");
bfd = 0;
res = $fread(str, bfd);
$display(" $fread returned: %0d, \'%0s\'", res, str);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
res = $fread(str, bfd);
$display(" $fread returned: %0d, \'%0s\'", res, str);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $ftell().
*/
$display("Checking $ftell with fd 0 and -1.");
bfd = 0;
res = $ftell(bfd);
$display(" $ftell returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
res = $ftell(bfd);
$display(" $ftell returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $fseek().
*/
$display("Checking $fseek.");
bfd = 0;
res = $fseek(bfd, 0, 0);
$display(" $fseek returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
res = $fseek(bfd, 0, 0);
$display(" $fseek returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
// A valid fd, but an invalid operation.
res = $fseek(vfd, 0, 4);
$display(" $fseek returned: %0d", res);
errno = $ferror(vfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $rewind().
*/
$display("Checking $rewind with fd 0 and -1.");
bfd = 0;
res = $rewind(bfd);
$display(" $rewind returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
res = $rewind(bfd);
$display(" $rewind returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $fflush().
*/
$display("Checking $fflush with fd 0 and -1.");
bfd = 0;
$fflush(bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
$fflush(bfd);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $feof().
*/
$display("Checking $feof with fd 0 and -1.");
bfd = 0;
res = $feof(bfd);
$display(" $feof returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
res = $feof(bfd);
$display(" $feof returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
/*
* Check $fputc() (Icarus specific).
*/
`ifdef __ICARUS__
$display("Checking $fputc with fd 0 and -1.");
bfd = 0;
res = $fputc(0, bfd);
$display(" $fputc returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
bfd = -1;
res = $fputc(0, bfd);
$display(" $fputc returned: %0d", res);
errno = $ferror(bfd, result);
$display(" $ferror returned: %0d, \'%0s\'", errno, result);
check_error;
`endif
/*
* Check that $fstrobe does not access a file after it is closed.
*/
$display("Checking $fstrobe after $fclose.");
res = $rewind(vfd);
if (res != 0) begin
$display("Failed to rewind file");
$finish;
end
$fwrite(vfd, "test-");
$fstrobe(vfd, "FAILED");
$fclose(vfd);
vfd = $fopen(work_file, "r");
if (vfd == 0) begin
errno = $ferror(vfd, result);
$display("Failed to open required file %s (%0s).", work_file, result);
$finish;
end
res = $fgets(str, vfd);
if (res == 0) begin
errno = $ferror(vfd, result);
$display("Failed to read back result (%0s)", result);
str = "failed";
end
if (str !== "test-") begin
$display("$fstrobe was not skipped, expected \'test-\', got \'%0s\'", str);
pass = 1\'b0;
end
$fclose(vfd);
if (pass) $display("PASSED");
end
endmodule
|
module test();
reg [0:(8*6)-1] identstr= "PASSED";
reg [7:0] identdata= 8\'b0;
integer i;
initial
begin
//\t$dumpfile("indexed_part.vcd");
//\t$dumpvars;
end
initial
begin
\tfor (i=0; i<6; i=i+1)
\t begin
\t #10 identdata = identstr[i*8 +:8];
\t $write("%c", identdata);
\t end
\t$write("\
");
\t$finish;
end
endmodule // test
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
wire no, po;
reg\td, c;
nmos n (no, d, c);
pmos p (po, d, c);
initial begin
c = 0;
d = 0;
#1 if (no !== 1\'bz) begin
\t $display("FAILED -- n (%b, %b, %b)", no, d, c);
\t $finish;
end
if (po !== 1\'b0) begin
\t $display("FAILED -- p (%b, %b, %b)", po, d, c);
\t $finish;
end
d = 1;
#1 if (no !== 1\'bz) begin
\t $display("FAILED -- n (%b, %b, %b)", no, d, c);
\t $finish;
end
if (po !== 1\'b1) begin
\t $display("FAILED -- p (%b, %b, %b)", po, d, c);
\t $finish;
end
c = 1;
#1 if (no !== 1\'b1) begin
\t $display("FAILED -- n (%b, %b, %b)", no, d, c);
\t $finish;
end
if (po !== 1\'bz) begin
\t $display("FAILED -- p (%b, %b, %b)", po, d, c);
\t $finish;
end
d = 0;
#1 if (no !== 1\'b0) begin
\t $display("FAILED -- n (%b, %b, %b)", no, d, c);
\t $finish;
end
if (po !== 1\'bz) begin
\t $display("FAILED -- p (%b, %b, %b)", po, d, c);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/* PR#445 */
module foo ();
initial
if (!(1\'b0))
$display("PASSED");
else
$display("FAILED");
endmodule
|
module top_module();
integer N;
(* attr = N *)
initial $display(N);
endmodule
|
/*
* This example is a distillation of the essence of PR#993.
* Or at least the essence that led to a bug report.
*/
module main;
parameter [31:0] fifo_address = 32\'hc0_00_00_00;
reg [31:0]\t bar;
reg\t\t flag;
wire [31:0] foo = flag? fifo_address : bar;
initial begin
bar = ~fifo_address;
flag = 1;
#1 if (foo !== fifo_address) begin
\t $display("FAILED");
\t $finish;
end
flag = 0;
#1 if (foo !== bar) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
/***************************************************************
** Author: Oswaldo Cadenas ([email protected])
** Date: September 26 2011
**
** Test: Intended to test a system composed of some parametric system
** that has an adder, a register and an incrementer
** Each module has parameter: N for data length
**
** A system is given parameter P and should return P-1, this is run for M test vectors
**************************************************************************************/
module test;
parameter integer T = 25; // for the clock period
parameter integer P = 1000; // a constant passed to the system under test
parameter integer M = 200; // number of test vectors
int i;
bit clk = 0, reset = 0;
byte unsigned x;
wire [10:0] y;
initial forever #(T) clk = !clk;
initial begin
@(negedge clk);
reset = 1\'b1;
repeat(6) @(negedge clk);
reset = 1\'b0;
end
initial begin
@(posedge reset);
@(negedge reset);
for (i = 0; i < M; i=i+1) begin
x = {$random} % 255;
@(negedge clk);
if (y !== P-1) begin
$display ("ERROR");
$finish;
end
end
#100;
$display ("PASSED");
$finish;
end
const_system #(P) duv (.clk(clk), .reset(reset), .x(x), .y(y) );
endmodule
|
/*
* Copyright (c) Peter Monta ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
wire [4:0] a;
reg [4:0] b;
initial
b = {5{a[4]}};
// b = {5{1\'b0}}; // this works
initial
$display("PASSED");
endmodule
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program checks that a function execution that includes part
* selects properly evaluates expressions. This is inspired by PR#95.
*/
module main;
wire [3:0] a = 4\'h1;
wire [3:0] b = 4\'h3;
reg [1:0] got1, got2;
reg [7:0] line;
initial
begin
line = 8\'h30;
#1; // Need some delay for the assignments to run.
\tgot1 = { (b[3:0] == line[7:4]), (a[3:0] == line[3:0]) };
\tgot2 = test(a, b, line);
\t$display("a=%b, b=%b, line=%b, got1=%b, got2=%b",
\t\t a, b, line, got1, got2);
\tif (got1 !== 2\'b10) begin
\t $display("FAILED -- got1 is wrong: %b !== 2\'b10", got1);
\t $finish;
\tend
\tif (got1 !== got2) begin
\t $display("FAILED -- got2 is incorrect: %b !== %b", got1, got2);
\t $finish;
\tend
\t$display("PASSED");
$finish;
end
function [1:0] test;
input [3:0] a, b;
input [7:0] line;
test = { (b == line[7:4]), (a[3:0] == line[3:0]) };
endfunction // test
endmodule // main
|
// Check that declaring a dynamic array typed member in a packed struct is an
// error.
module test;
struct packed {
int x[];
} s;
initial begin
$display("FAILED");
end
endmodule
|
// Test the various string.Xtoa() methods
module testbench;
string str;
int \t val;
real valr;
task test_string_value(string str, string reference);
if (str != reference) begin
\t $display("FAILED -- str=%0s, should be %s", str, reference);
\t $finish;
end
endtask // test_string_value
initial begin
val = 11;
valr = 11.1;
str.itoa(val);
test_string_value(str, "11");
str.hextoa(val);
test_string_value(str, "b");
str.octtoa(val);
test_string_value(str, "13");
str.bintoa(val);
test_string_value(str, "1011");
str.realtoa(valr);
test_string_value(str, "11.1");
val = -11;
valr = -11.1;
str.itoa(val);
test_string_value(str, "-11");
str.hextoa(val);
test_string_value(str, "-b");
str.octtoa(val);
test_string_value(str, "-13");
str.bintoa(val);
test_string_value(str, "-1011");
str.realtoa(valr);
test_string_value(str, "-11.1");
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 2001 Stephan Gehring (stephan.gehring@@ieee.org)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Has a constant 'hzz that blows up icarus
module Bug;
reg [7:0] x;
initial begin
x = 'h4000 + 'hzz; // iverilog doesn't like 'hzz
end
endmodule
|
//
// Copyright (c) 2001 Steve Williams <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* The $depost system task takes the inputs a depositible object and a
* value to deposit. The $deposit works like a blocking assignment, so
* the target takes the value right away.
*
* This example tests the $deposit on a wire object. What that means is
* that the wire takes on the deposited value, but that value doesn\'t
* stick if its normal input changes.
*/
module main ;
reg in;
wire test = in;
initial begin
in = 1\'b0;
#1 if (test !== 1\'b0) begin
\t $display("FAILED -- test starts out as %b", test);
\t //$finish;
end
$deposit(test, 1\'b1);
#1 if (test !== 1\'b1) begin
\t $display("FAILED -- test after deposit is %b", test);
\t $finish;
end
in = 1\'bz;
#1 if (test !== 1\'bz) begin
\t $display("FAILED -- test after input is %b", test);
\t $finish;
end
$display("PASSED");
end
endmodule
|
module top;
reg [31:0] mem[0:0];
initial begin
$readmemh( "ivltests/pr2709097.hex", mem );
//\t$display("mem[0] = %d", mem[0]);
\tif (mem[0] !== 10) $display("FAILED");
\telse $display("PASSED");
end
endmodule
|
module main;
reg [1:0] D0, D1;
reg\t sel;
wire [1:0] Q;
test_mux DUT(.\\S[1] (1\'b0), .\\S[0] (sel),
\t\t.\\D0[1] (D0[1]), .\\D0[0] (D0[0]),
\t\t.\\D1[1] (D1[1]), .\\D1[0] (D1[0]),
\t\t.\\Q[1] (Q[1]), .\\Q[0] (Q[0]));
initial begin
D0 = \'b01;
D1 = \'b10;
sel = 0;
#1 ;
if (Q !== D0) begin
\t $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q);
\t $finish;
end
sel = 1;
#1 ;
if (Q !== D1) begin
\t $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module test();
tri1 a;
tri0 b;
assign (pull1,pull0) a = 1\'b0;
assign (pull1,pull0) b = 1\'b1;
reg failed;
initial begin
failed = 0; #1;
$display("a = %b, expect x", a); if (a !== 1\'bx) failed = 1;
$display("b = %b, expect x", b); if (b !== 1\'bx) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Copyright (c) 2015 CERN
// @author Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// boolean values test.
module vhdl_boolean_test;
vhdl_boolean dut();
initial begin
if(dut.true_val != \\true ) begin
$display("FAILED true 1");
$finish();
end
if(!dut.true_val) begin
$display("FAILED true 2");
$finish();
end
if(dut.false_val != \\false ) begin
$display("FAILED false 1");
$finish();
end
if(dut.false_val) begin
$display("FAILED false 2");
$finish();
end
if(!dut.and1) begin
$display("FAILED and1");
$finish();
end
if(dut.and2) begin
$display("FAILED and2");
$finish();
end
if(dut.and3) begin
$display("FAILED and3");
$finish();
end
if(!dut.or1) begin
$display("FAILED or1");
$finish();
end
if(!dut.or2) begin
$display("FAILED or2");
$finish();
end
if(dut.or3) begin
$display("FAILED or3");
$finish();
end
if(!dut.not1) begin
$display("FAILED not1");
$finish();
end
if(dut.not2) begin
$display("FAILED not2");
$finish();
end
$display("PASSED");
end
endmodule
|
// Check that non-blocking partial writes to a 4-state vector array element are
// correctly handlded.
module test;
reg failed = 1\'b0;
`define check(val, exp) \\
if (exp !== val) begin \\
$display("FAILED. Got %b, expected %b.", val, exp); \\
failed = 1\'b1; \\
end
reg [3:0] x[1:0];
integer i;
initial begin
// Immediate index
// Within bounds
x[0] = \'hx;
x[0][2:1] <= 2\'b10;
#1
`check(x[0], 4\'bx10x)
// Partially oob at high and low side
x[0] = \'hx;
x[0][4:-1] <= 6\'b101010;
#1
`check(x[0], 4\'b0101)
// Partially oob at low side
x[0] = \'hx;
x[0][0:-1] <= 2\'b10;
#1
`check(x[0], 4\'bxxx1)
// Partially oob at high side
x[0] = \'hx;
x[0][4:3] <= 2\'b01;
#1
`check(x[0], 4\'b1xxx)
// Fully oob at low side
x[0] = \'hx;
x[0][-1:-2] <= 2\'b11;
#1
`check(x[0], 4\'bxxxx)
// Fully oob at high side
x[0] = \'hx;
x[0][6:5] <= 2\'b11;
#1
`check(x[0], 4\'bxxxx)
// Variable index
// Within bounds
i = 1;
x[0] = \'hx;
x[0][i+:2] <= 2\'b10;
#1
`check(x[0], 4\'bx10x)
// Partially oob at high and low side
i = -1;
x[0] = \'hx;
x[0][i+:6] <= 6\'b101010;
#1
`check(x[0], 4\'b0101)
// Partially oob at low side
i = -1;
x[0] = \'hx;
x[0][i+:2] <= 2\'b10;
#1
`check(x[0], 4\'bxxx1)
// Partially oob at high side
i = 3;
x[0] = \'hx;
x[0][i+:2] <= 2\'b01;
#1
`check(x[0], 4\'b1xxx)
// Fully oob at low side
i = -2;
x[0] = \'hx;
x[0][i+:2] <= 2\'b11;
#1
`check(x[0], 4\'bxxxx)
// Fully oob at high side
i = 5;
x[0] = \'hx;
x[0][i+:2] <= 2\'b11;
#1
`check(x[0], 4\'bxxxx)
// Undefined index
i = 5;
x[0] = \'hx;
x[0][i+:2] <= 2\'b11;
#1
`check(x[0], 4\'bxxxx)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
parameter num1 = 201, str1 = "unit2";
parameter num2 = 202, str2 = "unit2";
parameter num3 = 203, str3 = "unit2";
module m3();
parameter num2 = 232, str2 = "m3";
initial begin
#2; // allow m1 to go first
m2.m1inst.obj.display;
$display("%d from %s", num1, str1);
$display("%d from %s", num2, str2);
$display("%d from %s", num3, str3);
$display("%d from %s", m4.num4, m4.str4);
end
/* This should not change the result, but Icarus ignores the order in
which variables are declared and used.
parameter num = 113, str3 = "m3";
*/
endmodule
module m4();
parameter num1 = 241, str1 = "m4";
parameter num2 = 242, str2 = "m4";
parameter num3 = 243, str3 = "m4";
parameter num4 = 244, str4 = "m4";
m3 m3inst();
endmodule
|
module test
(output reg a,
output reg\t b,
input wire [1:0] sel,
input wire\t d
/* */);
always @* begin
b = d;
case (sel)
\t0:
\t begin
\t a = 0;
\t b = 1;
\t end
\t1:
\t begin
\t a = 1;
\t //b = 0; // Pick up input from d instead.
\t end
\tdefault:
\t begin
\t a = d;
\t end
endcase // case (sel)
end // always @ *
endmodule // test
module main;
reg [1:0] sel;
reg\t d;
wire a, b;
test dut (.a(a), .b(b), .sel(sel), .d(d));
initial begin
d = 0;
sel = 0;
#1 if (a!==0 || b!==1) begin
\t $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
\t $finish;
end
sel = 1;
#1 if (a!==1 || b!==0) begin
\t $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
\t $finish;
end
sel = 2;
#1 if (a!==0 || b!==0) begin
\t $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
\t $finish;
end
d = 1;
#1 if (a!==1 || b!==1) begin
\t $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
\t $finish;
end
$display("PASSED");
end
endmodule
|
class testclass;
task start();
top.dut.signal = 1;
endtask
endclass
module dut();
logic signal = 0;
initial begin
$display(signal);
@(signal);
$display(signal);
if (signal === 1)
$display("PASSED");
else
$display("FAILED");
$finish;
end
endmodule
module top();
testclass tc;
initial begin
#1 tc.start();
end
dut dut();
endmodule
|
// Check that the var keyword is supported for task ports
bit failed = 1\'b0;
`define check(val, exp) \\
if (val !== exp) begin \\
$display("FAILED(%0d). \'%s\' expected %b, got %b", `__LINE__, `"val`", val, exp); \\
failed = 1\'b1; \\
end
module test;
task t1 (var int x);
`check(x, 10)
endtask
task t2 (input var int x, output var int y);
`check(x, 20)
y = x;
endtask
task t3 (var [7:0] x);
`check(x, 30)
endtask
task t4 (input var [7:0] x, output var [7:0] y);
`check(x, 40)
y = x;
endtask
initial begin
int o1;
logic [7:0] o2;
t1(10);
t2(20, o1);
t3(30);
t4(40, o2);
`check(o1, 20)
`check(o2, 40)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module top;
reg real vo;
initial begin
vo = 3.3;
#1000 vo = 4.5776;
#1000 vo = -4;
end
rcvr U1(vo);
endmodule
module rcvr(vo);
input vo;
wire real vo;
always @(vo)
$display("Real value is %f at %g", vo, $time);
endmodule
|
// based on PR#1022
module foo;
wire [-1:0] fred;
assign fred = 1;
initial begin
#1 if (fred[0] !== 1) begin
\t $display("FAILED -- fred[0] = %b", fred[0]);
\t $finish;
end
if (fred[-1] !== 0) begin
\t $display("FAILED -- fred[-1] = %b", fred[-1]);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule
|
module top;
reg pass = 1\'b1;
integer count;
reg [2:0] icount;
reg clk = 0;
real in = 0.0;
real result = -1.0;
always #10 clk = ~clk;
always #20 in = in + 1.0;
initial begin
count = 3;
result <= repeat(count) @(posedge clk) in;
if ($simtime != 0 || result != -1.0) begin
$display("Failed repeat(3) blocked at %0t, expected -1.0, got %f",
$simtime, result);
pass = 1\'b0;
end
@(result);
if ($simtime != 50 || result != 0.0) begin
$display("Failed repeat(3) at %0t, expected 0.0, got %f",
$simtime, result);
pass = 1\'b0;
end
#15;
count = 0;
result <= repeat(count) @(posedge clk) in;
#0; // This may not work since there is no delay.
if ($simtime != 65 || result != 3.0) begin
$display("Failed repeat(0) at %0t, expected 3.0, got %f",
$simtime, result);
pass = 1\'b0;
end
#20;
count = -1;
result <= repeat(count) @(posedge clk) in;
#0; // This may not work since there is no delay.
if ($simtime != 85 || result != 4.0) begin
$display("Failed repeat(-1) at %0t, expected 4.0, got %f",
$simtime, result);
pass = 1\'b0;
end
#20;
result <= @(posedge clk) 0.0;
result <= @(posedge clk) in; // This one sets the final value.
@(result);
if ($simtime != 110 || result != 5.0) begin
$display("Failed @ at %0t, expected 5.0, got %f",
$simtime, result);
pass = 1\'b0;
end
icount = 3\'d2;
result <= @(posedge clk) 1.0;
result <= repeat(icount) @(posedge clk) 2.0;
result <= repeat(3) @(posedge clk) 3.0;
@(result);
if ($simtime != 130 || result != 1.0) begin
$display("Failed first @ at %0t, expected 1.0, got %f",
$simtime, result);
pass = 1\'b0;
end
@(result);
if ($simtime != 150 || result != 2.0) begin
$display("Failed second @ at %0t, expected 2.0, got %f",
$simtime, result);
pass = 1\'b0;
end
@(result);
if ($simtime != 170 || result != 3.0) begin
$display("Failed third @ at %0t, expected 3.0, got %f",
$simtime, result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
$finish;
end
endmodule
|
module main;
reg bool [31:0] idx;
initial begin
idx = 0;
if (idx < 17) $display("PASSED");
else $display("FAILED");
end
endmodule
|
// Check that the signedness of methods on the built-in enum type is handled
// correctly when calling the method with parenthesis.
module test;
bit failed = 1\'b0;
`define check(x) \\
if (!(x)) begin \\
$display("FAILED(%0d): ", `__LINE__, `"x`"); \\
failed = 1\'b1; \\
end
int unsigned x = 10;
int y = 10;
int z;
enum shortint {
A = -1,
B = -2,
C = -3
} es;
enum bit [15:0] {
X = 65535,
Y = 65534,
Z = 65533
} eu;
initial begin
es = B;
eu = Y;
// These all evaluate as signed
`check($signed(eu.first()) < 0)
`check(es.first() < 0)
`check($signed(eu.last()) < 0)
`check(es.last() < 0)
`check($signed(eu.prev()) < 0)
`check(es.prev() < 0)
`check($signed(eu.next()) < 0)
`check(es.next() < 0)
// These all evaluate as unsigned
`check(eu.first() > 0)
`check({es.first()} > 0)
`check($unsigned(es.first()) > 0)
`check(es.first() > 16\'h0)
`check(eu.last() > 0)
`check({es.last()} > 0)
`check($unsigned(es.last()) > 0)
`check(es.last() > 16\'h0)
`check(eu.prev() > 0)
`check({es.prev()} > 0)
`check($unsigned(es.prev()) > 0)
`check(es.prev() > 16\'h0)
`check(eu.next() > 0)
`check({es.next()} > 0)
`check($unsigned(es.next()) > 0)
`check(es.next() > 16\'h0)
// In arithmetic expressions if one operand is unsigned all operands are
// considered unsigned
z = eu.first() + x;
`check(z === 65545)
z = eu.first() + y;
`check(z === 65545)
z = eu.last() + x;
`check(z === 65543)
z = eu.last() + y;
`check(z === 65543)
z = eu.prev() + x;
`check(z === 65545)
z = eu.prev() + y;
`check(z === 65545)
z = eu.next() + x;
`check(z === 65543)
z = eu.next() + y;
`check(z === 65543)
z = es.first() + x;
`check(z === 65545)
z = es.first() + y;
`check(z === 9)
z = es.last() + x;
`check(z === 65543)
z = es.last() + y;
`check(z === 7)
z = es.prev() + x;
`check(z === 65545)
z = es.prev() + y;
`check(z === 9)
z = es.next() + x;
`check(z === 65543)
z = es.next() + y;
`check(z === 7)
// For ternary operators if one operand is unsigned the result is unsigend
z = x ? eu.first() : x;
`check(z === 65535)
z = x ? eu.first() : y;
`check(z === 65535)
z = x ? eu.last() : x;
`check(z === 65533)
z = x ? eu.last() : y;
`check(z === 65533)
z = x ? eu.prev() : x;
`check(z === 65535)
z = x ? eu.prev() : y;
`check(z === 65535)
z = x ? eu.next() : x;
`check(z === 65533)
z = x ? eu.next() : y;
`check(z === 65533)
z = x ? es.first() : x;
`check(z === 65535)
z = x ? es.first() : y;
`check(z === -1)
z = x ? es.last() : x;
`check(z === 65533)
z = x ? es.last() : y;
`check(z === -3)
z = x ? es.prev() : x;
`check(z === 65535)
z = x ? es.prev() : y;
`check(z === -1)
z = x ? es.next() : x;
`check(z === 65533)
z = x ? es.next() : y;
`check(z === -3)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
/*
* Copyright (c) 2014 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
`default_nettype none
module main;
string words [$];
int nums[$];
initial begin
words.push_back("Hello, World!");
nums.push_back(42);
words = {};
if (words.size != 0) begin
\t $display("FAILED -- words.size=%0d after clear", words.size);
\t $finish;
end
nums = {};
if (nums.size != 0) begin
\t $display("FAILED -- nums.size=%0d after clear", nums.size);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module pr0;
reg r;
initial r = ( 1\'b1 ? 1\'b0 : 1\'b0) ? 1\'b0 : 1\'b0;
initial begin
#1 if (r !== 1\'b0) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule
|
module top;
reg pass = 1\'b1;
genvar lp;
for (lp=1; lp <= 128; lp = lp + 1) begin: loop
test #(lp) dut();
end
initial #1000 if (pass) $display("PASSED");
endmodule
module test;
parameter wid = 62;
localparam X = {4\'b1000, {wid{1\'b0}}};
localparam Y = {1\'b1, {wid{1\'b0}}};
reg [wid:0] y = Y;
reg [wid+3:0] x = X;
reg [3:0] res;
initial begin
#wid; // Wait for the x and y values to get assigned.
res = X/Y;
if (res !== 4\'b1000) begin
$display("Failed const. division for %3d, expected 4\'b1000, got %b",
wid, res);
top.pass = 1\'b0;
end
res = X/y;
if (res !== 4\'b1000) begin
$display("Failed const. numerator for %3d, expected 4\'b1000, got %b",
wid, res);
top.pass = 1\'b0;
end
res = x/Y;
if (res !== 4\'b1000) begin
$display("Failed const. denominator for %3d, expected 4\'b1000, got %b",
wid, res);
top.pass = 1\'b0;
end
res = x/y;
if (res !== 4\'b1000) begin
$display("Failed variable division for %3d, expected 4\'b1000, got %b",
wid, res);
top.pass = 1\'b0;
end
end
endmodule
|
module tb();
typedef enum logic [1:0] {
IDLE = 0,
RESET = 1,
START = 2,
WAITFOR = 3
} stateType;
stateType state;
string workingString = "WORKING";
initial begin
$display("DIRECT ASSIGNED STRING is ", workingString);
#10;
state = IDLE;
end
string state_txt;
always @* begin
case(state)
IDLE : state_txt = "IDLE";
RESET : state_txt = "RST";
START : state_txt = "STRT";
WAITFOR : state_txt = "WAIT";
endcase
$display("Controller\'s new state is %s",state_txt);
end
endmodule
|
module main;
reg [31:0] bytes;
initial begin
bytes = "\\101\\102\\103\
";
$write("bytes=%h\
", bytes);
$finish(0);
end
endmodule // main
|
`define EOF -1
module bar;
integer line, rc, file, a, b, c;
reg [8*256:1] str;
initial begin
file = $fopen ("ivltests/pr1687193.dat", "r");
if (file == 0)
\t$finish;
for (line = 1; line <= 5; line = line + 1) begin
\t rc = $fgets (str, file);
\t if (rc == `EOF)
\t $finish;
\t rc = $sscanf (str, "%h %h %h\
", a, b, c);
\t $display ("\\tLine %d matches %d args: %h %h %h", line, rc, a, b, c);
end
$fclose (file);
$finish(0);
end
endmodule
|
package my_package1;
parameter p1 = 1;
localparam p2 = 2;
typedef logic [1:0] word;
word v;
event e;
function word f(word g);
f = g + 1;
endfunction
task h(word i);
v = v + i;
$display(v);
endtask
endpackage
package my_package2;
parameter p1 = 1;
localparam p2 = 2;
typedef logic [1:0] word;
word v;
event e;
function word f(word g);
f = g + 1;
endfunction
task h(word i);
v = v + i;
$display(v);
endtask
endpackage
module test();
import my_package1::*;
import my_package2::*;
word my_v;
initial begin
@(e) v = p1 + p2;
h(f(1));
end
endmodule
|
`timescale 1 ns / 1 ps
module test;
initial begin
\t#12.3456;
\t$display("$time = %0t", $time);
\t$test(test);
\t#34.5678;
\t$display("$time = %0t", $time);
\t$test(test);
end
endmodule
`timescale 1 ps / 1 ps
module test2;
initial begin
\t#56.7890;
\t$display("$time = %0t", $time);
\t$test(test2);
\t#78.9012;
\t$display("$time = %0t", $time);
\t$test(test2);
end
endmodule
|
module test ();
reg pass = 1\'b1;
reg d;
real f = 0.0;
always @(d) assign f = 0;
initial begin
// Verify the initial value.
#1;
if (f != 0.0) begin
$display("Failed initial value, expected 0.0, got %f", f);
pass = 1\'b0;
end
// Verify the value can change.
#1 f = 1.0;
if (f != 1.0) begin
$display("Failed value change, expected 1.0, got %f", f);
pass = 1\'b0;
end
// Verify that the assign changed the value and that a normal assign
// is blocked.
#1 d = 0;
#1 f = 1.0;
if (f != 0.0) begin
$display("Failed assign holding, expected 0.0, got %f", f);
pass = 1\'b0;
end
// Verify that the release holds the previous value.
#1 deassign f;
if (f != 0.0) begin
$display("Failed release holding, expected 0.0, got %f", f);
pass = 1\'b0;
end
// Verify that the value can be changed after a release.
#1 f = 1.0;
if (f != 1.0) begin
$display("Failed release, expected 1.0, got %f", f);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module test();
parameter N_N = 3;
reg signed [2*N_N-1:0] val_neg;
reg signed [2*N_N-1:0] val_pos;
initial
begin
\tval_neg = {{N_N+1{1\'b1}},{N_N-1{1\'b0}}};
\tval_pos = {{N_N+1{1\'b0}},{N_N-1{1\'b1}}};
\t#1 $display("Var %d vs signed(concat) %d",
\t\t val_neg,
\t\t $signed({{N_N+1{1\'b1}},{N_N-1{1\'b0}}}));
\t$finish(0);
end // initial begin
endmodule // test
|
// This tests system functions available for packed structures
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test;
typedef struct packed {
logic [7:0] high;
logic [7:0] low;
} word_t;
// Declare word0 as a VARIABLE
word_t word0;
// error counter
bit err = 0;
initial begin
if ($bits(word0 ) !== 16) begin $display("FAILED -- $bits(word0 ) = %d", $bits(word0 )); err=1; end
if ($bits(word0.high) !== 8) begin $display("FAILED -- $bits(word0.high) = %d", $bits(word0.high)); err=1; end
if ($bits(word0.low ) !== 8) begin $display("FAILED -- $bits(word0.low ) = %d", $bits(word0.low )); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* $Id: sqrt-virtex.v,v 1.5 2007/03/22 16:08:18 steve Exp $"
*/
/*
* This module is a synthesizable square-root function. It is also a
* detailed example of how to target Xilinx Virtex parts using
* Icarus Verilog. In fact, for no particular reason other than to
* be excessively specific, I will step through the process of
* generating a design for a Spartan-II XC2S15-VQ100, and also how to
* generate a generic library part for larger Virtex designs.
*
* In addition to Icarus Verilog, you will need implementation
* software from Xilinx. As of this writing, this example was tested
* with Foundation 4.2i, but it should work the same with ISE and
* WebPACK software.
*
* This example source contains all the Verilog needed to do
* everything described below. We use conditional compilation to
* select the bits of Verilog that are needed to perform each specific
* task.
*
* SIMULATE THE DESIGN
*
* This source file includes a simulation test bench. To compile the
* program to include this test bench, use the command line:
*
* iverilog -DSIMULATE=1 -oa.out sqrt-virtex.v
*
* This generates the file "a.out" that can then be executed with the
* command:
*
* vvp a.out
*
* This causes the simulation to run a long set of example sqrt
* calculations. Each result is checked by the test bench to assure
* that the result is valid. When it is done, the program prints
* "PASSED" and finishes the simulation.
*
* When you take a close look at the "main" module below, you will see
* that it uses Verilog constructs that are not synthesizable. This
* is fine, as we will never try to synthesize it.
*
* LIBRARY PARTS
*
* One can use the sqrt32 module to generate an EDIF file suitable for
* use as a library part. This part can be imported to the Xilinx
* schematic editor, then placed like any other pre-existing
* macro. One can also pass the generated EDIF as a precompiled macro
* that other designers may use as they see fit.
*
* To make an EDIF file from the sqrt32 module, execute the command:
*
* iverilog -osqrt32.edf -tfpga -parch=virtex sqrt-virtex.v
*
* The -parch=virtex tells the code generator to generate code for the
* virtex architecture family (we don\'t yet care what specific part)
* and the -osqrt32.edf places the output into the file
* sqrt32.edf.
*
* Without any preprocessor directives, the only module is the sqrt32
* module, so sqrt32 is compiled as the root. The ports of the module
* are automatically made into ports of the sqrt32.edf netlist, and
* the contents of the sqrt32 module are connected appropriately.
*
* COMPLETE CHIP DESIGNS
*
* To make a complete chip design, there are other bits that need to
* be accounted for. Signals must be assigned to pins, and some
* special devices may need to be created. We also want to write into
* the EDIF file complete part information so that the implementation
* tools know how to route the complete design. The command to compile
* for our target part is:
*
* iverilog -ochip.edf -tfpga \\
* -parch=virtex -ppart=XC2S15-VQ100 \\
* -DMAKE_CHIP=1 sqrt-virtex.v
*
* This command uses the "chip" module as the root. This module in
* turn has ports that are destined to be the pins of the completed
* part. The -ppart= option gives complete part information, that is
* in turn written into the EDIF file. This saves us the drudgery of
* repeating that part number for later commands.
*
* The next steps involve Xilinx software, and to talk to Xilinx
* software, the netlist must be in the form of an "ngd" file, a
* binary netlist format. The command:
*
* ngdbuild chip.edf chip.ngd
*
* does the trick. The input to ngdbuild is the chip.edf file created
* by Icarus Verilog, and the output is the chip.ngd file that the
* implementation tools may read. From this point, it is best to refer
* to Xilinx documentation for the software you are using, but the
* quick summary is:
*
* map -o map.ncd chip.ngd
* par -w map.ncd chip.ncd
*
* The result of this sequence of commands is the chip.ncd file that
* is ready to be viewed by FPGA Edit, or converted to a bit stream,
* or whatever.
*
* POST MAP SIMULATION
*
* Warm fuzzies are good, and retesting your design after the part
* is mapped by the Xilinx backend tools is a cheap source of fuzzies.
* The command to make a Verilog file out of the mapped design is:
*
* ngd2ver chip.ngd chip_root.v
*
* This command creates from the chip.ngd the file "chip_root.v" that
* contains Verilog code that simulates the mapped design. This output
* Verilog has the single root module "chip_root", which came from the
* name of the root module when we were making the EDIF file in the
* first place. The module has ports named just line the ports of the
* chip_root module below.
*
* The generated Verilog uses the library in the directory
* $(XILINX)/verilog/src/simprims. This directory comes with the ISE
* WebPACK installation that you are using. Icarus Verilog is able to
* simulate using that library.
*
* To compile a post-map simulation of the chip_root.v, use the
* command:
*
* iverilog -DSIMULATE -DPOST_MAP -ob.out \\
* -y $(XILINX)/verilog/src/simprims \\
* sqrt-virtex.v chip_root.v \\
* $(XILINX)/verilog/src/glbl.v
*
* This command line generates b.out from the source files
* sqrt-virtex.v and chip_root.v (the latter from ngd2ver)
* and the "-y <path>" flag specifies the library directory that will
* be needed. The glbl.v source file is also included to provide the
* GSR and related signals.
*
* The POST_MAP compiler directive causes the GSR manipulations
* included in the test bench to be compiled in, to simulate the chip
* startup. Other than that, the test bench runs the post-map design
* the same way the pre-synthesis design works.
*
* Run this design with the command:
*
* vvp b.out
*
* And there you go.
*/
`ifndef POST_MAP
/*
* This module approximates the square root of an unsigned 32bit
* number. The algorithm works by doing a bit-wise binary search.
* Starting from the most significant bit, the accumulated value
* tries to put a 1 in the bit position. If that makes the square
* too big for the input, the bit is left zero, otherwise it is set
* in the result. This continues for each bit, decreasing in
* significance, until all the bits are calculated or all the
* remaining bits are zero.
*
* Since the result is an integer, this function really calculates
* value of the expression:
*
* x = floor(sqrt(y))
*
* where sqrt(y) is the exact square root of y and floor(N) is the
* largest integer <= N.
*
* For 32 bit numbers, this will never run more than 16 iterations,
* which amounts to 16 clocks.
*/
module sqrt32(clk, rdy, reset, x, .y(acc));
input clk;
output rdy;
input reset;
input [31:0] x;
output [15:0] acc;
// acc holds the accumulated result, and acc2 is the accumulated
// square of the accumulated result.
reg [15:0] acc;
reg [31:0] acc2;
// Keep track of which bit I\'m working on.
reg [4:0] bitl;
wire [15:0] bit = 1 << bitl;
wire [31:0] bit2 = 1 << (bitl << 1);
// The output is ready when the bitl counter underflows.
wire rdy = bitl[4];
// guess holds the potential next values for acc, and guess2 holds
// the square of that guess. The guess2 calculation is a little bit
// subtle. The idea is that:
//
// guess2 = (acc + bit) * (acc + bit)
// = (acc * acc) + 2*acc*bit + bit*bit
// = acc2 + 2*acc*bit + bit2
// = acc2 + 2 * (acc<<bitl) + bit
//
// This works out using shifts because bit and bit2 are known to
// have only a single bit in them.
wire [15:0] guess = acc | bit;
wire [31:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
(* ivl_synthesis_on *)
always @(posedge clk or posedge reset)
if (reset) begin
\t acc = 0;
\t acc2 = 0;
\t bitl = 15;
end else begin
\t if (guess2 <= x) begin
\t acc <= guess;
\t acc2 <= guess2;
\t end
\t bitl <= bitl - 5\'d1;
end
endmodule // sqrt32
`endif // `ifndef POST_MAP
`ifdef SIMULATE
/*
* This module is a test bench for the sqrt32 module. It runs some
* test input values through the sqrt32 module, and checks that the
* output is valid. If an invalid output is generated, print and
* error message and stop immediately. If all the tested values pass,
* then print PASSED after the test is complete.
*/
module main;
reg [31:0] x;
reg\t clk, reset;
wire [15:0] y;
wire rdy;
`ifdef POST_MAP
chip_root dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
`else
sqrt32 dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
`endif
(* ivl_synthesis_off *)
always #5 clk = !clk;
task reset_dut;
begin
\t reset = 1;
\t @(posedge clk) ;
\t #1 reset = 0;
\t @(negedge clk) ;
end
endtask // reset_dut
task crank_dut;
begin
\t while (rdy == 0) begin
\t @(posedge clk) /* wait */;
\t end
end
endtask // crank_dut
`ifdef POST_MAP
reg GSR;
assign glbl.GSR = GSR;
`endif
integer idx;
(* ivl_synthesis_off *)
initial begin
reset = 0;
clk = 0;
/* If doing a post-map simulation, when we need to wiggle
The GSR bit to simulate chip power-up. */
`ifdef POST_MAP
GSR = 1;
#100 GSR = 0;
`endif
#100 x = 1;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
x = 3;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
x = 4;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
for (idx = 0 ; idx < 200 ; idx = idx + 1) begin
\t x = $random;
\t reset_dut;
\t crank_dut;
\t $display("x=%d, y=%d", x, y);
\t if (x < (y * y)) begin
\t $display("ERROR: y is too big");
\t $finish;
\t end
\t if (x > ((y + 1)*(y + 1))) begin
\t $display("ERROR: y is too small");
\t $finish;
\t end
end
$display("PASSED");
$finish;
end
endmodule // main
`endif
`ifdef MAKE_CHIP
/*
* This module represents the chip packaging that we intend to
* generate. We bind pins here, and route the clock to the global
* clock buffer.
*/
module chip_root(clk, rdy, reset, x, y);
input clk;
output rdy;
input reset;
input [31:0] x;
output [15:0] y;
wire\t clk_int;
(* cellref="BUFG:O,I" *)
buf gbuf (clk_int, clk);
sqrt32 dut(.clk(clk_int), .reset(reset), .rdy(rdy), .x(x), .y(y));
/* Assign the clk to GCLK0, which is on pin P39. */
$attribute(clk, "PAD", "P39");
// We don\'t care where the remaining pins go, so set the pin number
// to 0. This tells the implementation tools that we want a PAD,
// but we don\'t care which. Also note the use of a comma (,)
// separated list to assign pins to the bits of a vector.
$attribute(rdy, "PAD", "0");
$attribute(reset, "PAD", "0");
$attribute(x, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
$attribute(y, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
endmodule // chip_root
`endif
|
module top;
specify
specparam Tdelay = 1.0;
endspecify
initial if (Tdelay != 1.0) $display("FAILED:, got %f", Tdelay);
else $display("PASSED");
endmodule
|
module top;
reg pass;
real rarr [1:0];
real rat;
integer i;
wire real rmon = rarr[0];
wire real rmonv = rarr[i];
always @(rarr[0]) begin
rat = rarr[0];
end
initial begin
pass = 1\'b1;
i = 0;
rarr[0] = 1.125;
#1;
if (rmon != 1.125) begin
$display("Failed CA at 0, expected 1.125, got %6.3f", rmon);
pass = 1\'b0;
end
if (rmonv != 1.125) begin
$display("Failed CA (var) at 0, expected 1.125, got %6.3f", rmonv);
pass = 1\'b0;
end
if (rat != 1.125) begin
$display("Failed @ at 0, expected 1.125, got %6.3f", rat);
pass = 1\'b0;
end
rarr[0] = 2.25;
#1;
if (rmon != 2.25) begin
$display("Failed CA at 1, expected 2.250, got %6.3f", rmon);
pass = 1\'b0;
end
if (rmonv != 2.25) begin
$display("Failed CA (var) at 1, expected 2.250, got %6.3f", rmonv);
pass = 1\'b0;
end
if (rat != 2.25) begin
$display("Failed @ at 1, expected 2.250, got %6.3f", rat);
pass = 1\'b0;
end
i = 1;
#1
if (rmonv != 0.0) begin
$display("Failed CA (var) at 2, expected 0.000, got %6.3f", rmonv);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module test();
reg a, b;
wire a1, a2, a3, a4, a5, a6, a7;
assign (supply1, supply0) a1 = a;
tran t1(a1, a2);
tran t2(a2, a3);
tran t3(a3, a4);
tran t4(a4, a5);
tran t5(a5, a6);
tran t6(a6, a7);
wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15;
wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25;
wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35;
wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45;
wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55;
assign (supply1, supply0) a11 = a, b11 = b;
assign (supply1, strong0) a12 = a, b12 = b;
assign (supply1, pull0) a13 = a, b13 = b;
assign (supply1, weak0) a14 = a, b14 = b;
assign (supply1, highz0) a15 = a, b15 = b;
assign (strong1, supply0) a21 = a, b21 = b;
assign (strong1, strong0) a22 = a, b22 = b;
assign (strong1, pull0) a23 = a, b23 = b;
assign (strong1, weak0) a24 = a, b24 = b;
assign (strong1, highz0) a25 = a, b25 = b;
assign ( pull1, supply0) a31 = a, b31 = b;
assign ( pull1, strong0) a32 = a, b32 = b;
assign ( pull1, pull0) a33 = a, b33 = b;
assign ( pull1, weak0) a34 = a, b34 = b;
assign ( pull1, highz0) a35 = a, b35 = b;
assign ( weak1, supply0) a41 = a, b41 = b;
assign ( weak1, strong0) a42 = a, b42 = b;
assign ( weak1, pull0) a43 = a, b43 = b;
assign ( weak1, weak0) a44 = a, b44 = b;
assign ( weak1, highz0) a45 = a, b45 = b;
assign ( highz1, supply0) a51 = a, b51 = b;
assign ( highz1, strong0) a52 = a, b52 = b;
assign ( highz1, pull0) a53 = a, b53 = b;
assign ( highz1, weak0) a54 = a, b54 = b;
tran t11(a11, b11);
tran t12(a12, b12);
tran t13(a13, b13);
tran t14(a14, b14);
tran t15(a15, b15);
tran t21(a21, b21);
tran t22(a22, b22);
tran t23(a23, b23);
tran t24(a24, b24);
tran t25(a25, b25);
tran t31(a31, b31);
tran t32(a32, b32);
tran t33(a33, b33);
tran t34(a34, b34);
tran t35(a35, b35);
tran t41(a41, b41);
tran t42(a42, b42);
tran t43(a43, b43);
tran t44(a44, b44);
tran t45(a45, b45);
tran t51(a51, b51);
tran t52(a52, b52);
tran t53(a53, b53);
tran t54(a54, b54);
tran t55(a55, b55);
task display_strengths;
input ta, tb;
begin
a = ta;
b = tb;
#1;
$display("a = %b b = %b", a, b);
$display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7);
$display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15);
$display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25);
$display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35);
$display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45);
$display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55);
end
endtask
initial begin
display_strengths(1\'bz, 1\'bz);
display_strengths(1\'bx, 1\'bz);
display_strengths(1\'b0, 1\'bz);
display_strengths(1\'b1, 1\'bz);
display_strengths(1\'bz, 1\'bx);
display_strengths(1\'bx, 1\'bx);
display_strengths(1\'b0, 1\'bx);
display_strengths(1\'b1, 1\'bx);
display_strengths(1\'bz, 1\'b0);
display_strengths(1\'bx, 1\'b0);
display_strengths(1\'b0, 1\'b0);
display_strengths(1\'b1, 1\'b0);
display_strengths(1\'bz, 1\'b1);
display_strengths(1\'bx, 1\'b1);
display_strengths(1\'b0, 1\'b1);
display_strengths(1\'b1, 1\'b1);
end
endmodule
|
module top;
reg [1:0] lv, rv;
reg res, pass;
initial begin
pass = 1\'b1;
lv = 2\'b00;
rv = 2\'b00;
res = lv ==? rv;
if (res !== 1\'b1) begin
$display("Failed: %b ==? %b returned 1\'b%b not 1\'b1", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b00;
rv = 2\'b01;
res = lv ==? rv;
if (res !== 1\'b0) begin
$display("Failed: %b ==? %b returned 1\'b%b not 1\'b0", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b10;
rv = 2\'b00;
res = lv ==? rv;
if (res !== 1\'b0) begin
$display("Failed: %b ==? %b returned 1\'b%b not 1\'b0", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b1x;
rv = 2\'b00;
res = lv ==? rv;
if (res !== 1\'b0) begin
$display("Failed: %b ==? %b returned 1\'b%b not 1\'b0", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b0x;
rv = 2\'b00;
res = lv ==? rv;
if (res !== 1\'bx) begin
$display("Failed: %b ==? %b returned 1\'b%b not 1\'bx", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b00;
rv = 2\'b0x;
res = lv ==? rv;
if (res !== 1\'b1) begin
$display("Failed: %b ==? %b returned 1\'b%b not 1\'b1", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b01;
rv = 2\'b0x;
res = lv ==? rv;
if (res !== 1\'b1) begin
$display("Failed: %b ==? %b returned 1\'b%b not 1\'b1", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b0z;
rv = 2\'b0x;
res = lv ==? rv;
if (res !== 1\'b1) begin
$display("Failed: %b ==? %b returned 1\'b%b not 1\'b1", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b0x;
rv = 2\'b0x;
res = lv ==? rv;
if (res !== 1\'b1) begin
$display("Failed: %b ==? %b returned 1\'b%b not 1\'b1", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b00;
rv = 2\'b00;
res = lv !=? rv;
if (res !== 1\'b0) begin
$display("Failed: %b !=? %b returned 1\'b%b not 1\'b0", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b00;
rv = 2\'b01;
res = lv !=? rv;
if (res !== 1\'b1) begin
$display("Failed: %b !=? %b returned 1\'b%b not 1\'b1", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b10;
rv = 2\'b00;
res = lv !=? rv;
if (res !== 1\'b1) begin
$display("Failed: %b !=? %b returned 1\'b%b not 1\'b1", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b1x;
rv = 2\'b00;
res = lv !=? rv;
if (res !== 1\'b1) begin
$display("Failed: %b !=? %b returned 1\'b%b not 1\'b1", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b0x;
rv = 2\'b00;
res = lv !=? rv;
if (res !== 1\'bx) begin
$display("Failed: %b !=? %b returned 1\'b%b not 1\'bx", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b00;
rv = 2\'b0x;
res = lv !=? rv;
if (res !== 1\'b0) begin
$display("Failed: %b !=? %b returned 1\'b%b not 1\'b0", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b01;
rv = 2\'b0x;
res = lv !=? rv;
if (res !== 1\'b0) begin
$display("Failed: %b !=? %b returned 1\'b%b not 1\'b0", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b0z;
rv = 2\'b0x;
res = lv !=? rv;
if (res !== 1\'b0) begin
$display("Failed: %b !=? %b returned 1\'b%b not 1\'b0", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b0x;
rv = 2\'b0x;
res = lv !=? rv;
if (res !== 1\'b0) begin
$display("Failed: %b !=? %b returned 1\'b%b not 1\'b0", lv, rv, res);
pass = 1\'b0;
end
// Check in a few other contexts.
lv = 2\'b01;
rv = 2\'b0x;
res = (lv ==? rv) ? 1\'b1 : 1\'b0;
if (res !== 1\'b1) begin
$display("Failed: %b ==? %b (ternary) returned 1\'b%b not 1\'b1", lv, rv, res);
pass = 1\'b0;
end
if (lv !=? rv) begin
$display("Failed: %b ==? %b (if) returned 1\'b%b not 1\'b1", lv, rv, res);
pass = 1\'b0;
end
lv = 2\'b00;
while (lv ==? rv) lv += 2\'b01;
if (lv !== 2\'b10) begin
$display("Failed: %b ==? %b (while) expected lv to be 2\'b10", lv, rv);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Check that declaring multiple task non-ANSI ports with the same name is an
// error. Even if they both have an implicit type.
module test;
task t;
input x;
input x;
$display("FAILED");
endtask
reg y;
initial t(y, y);
endmodule
|
// Check that declarations for dynamic arrays of unpacked arrays are supported.
module test;
// Dynamic array of unpacked arrays
int q[10][];
endmodule
|
module main;
reg [7:0] mem;
reg [2:0] addr;
reg\t out;
reg\t clk;
(* ivl_synthesis_on *)
always @(posedge clk) out <= mem[addr];
integer idx;
(* ivl_synthesis_off *)
initial begin
mem = 8\'hca;
addr = 0;
clk = 0;
for (idx = 0 ; idx < 8 ; idx = idx+1) begin
\t addr = idx[2:0];
\t #1 clk = 1;
\t #1 clk = 0;
\t if (out !== mem[idx]) begin
\t $display("FAILED -- mem[%d] = %b", idx, out);
\t $finish;
\t end
end
$display("PASSED");
end // initial begin
endmodule // main
|
module test;
string x[], y[], z[];
string src[0:7];
int\t i;
initial begin
src[0] = "a";
src[1] = "b";
src[2] = "c";
src[3] = "d";
src[4] = "e";
src[5] = "f";
src[6] = "g";
src[7] = "h";
x = new [4];
for (i = 0; i < 4; i = i + 1) x[i] = src[i];
y = x;
z = new [4](x);
for (i = 0; i < 4; i = i + 1) y[i] = src[3 - i];
for (i = 0; i < 4; i = i + 1) z[i] = src[7 - i];
// Expected output:
// a b c d
// d c b a
// h g f e
$display(x[0],,x[1],,x[2],,x[3]);
$display(y[0],,y[1],,y[2],,y[3]);
$display(z[0],,z[1],,z[2],,z[3]);
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate 3.1.2D always reg_lvalue = # delay_value boolean_expr ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
begin
if(value1 !== 4\'hx)
\t$display("FAILED - always reg_lvalue = # delay_value boolean_expr");
#15 ;
if(value1 != 4\'b1)
\t$display("FAILED - always reg_lvalue = # delay_value boolean_expr");
else
begin
$display("PASSED\
");
$finish ;
end
end
always
value1 <= # 10 1\'b1 && 1\'b1 ;
endmodule
|
// Check that declaring multiple non-ANSI module output ports with an explicit
// type is an error. Even if the types are the same.
module test(x);
output integer x;
output integer x;
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test captures the essence of PR#40, namely the possibility
* that the continuous assign from a reg to a wire may have a delay.
*/
module test;
wire a;
reg b;
assign #10 a = b;
initial begin
b = 0;
# 20 b = 1;
# 5 if (a !== 0) begin
$display("FAILED -- a is %b", a);
$finish;
end
# 6 if (a !== 1) begin
$display("FAILED -- a is %b, should be 1", a);
$finish;
end
$display("PASSED");
end
endmodule
|
// Check that ANSI output ports that have a Verilog data type are elaborated as
// variables and be assigned a value.
module test (
output reg a,
output reg [1:0] b,
output reg signed [1:0] c,
output integer d,
output time e
);
initial begin
a = 0;
b = 0;
c = 0;
d = 0;
e = 0;
$display("PASSED");
end
endmodule
|
module test_logic(input A, B, output reg q_nand, q_nor, q_xnor, q_not);
always @(A, B) begin
q_nand = A ~& B;
q_nor = A ~| B;
q_xnor = A ~^ B;
q_not = ~A;
end
endmodule // test_logic
|
module test();
initial begin
$display("%b", \'h00000001);
$display("%d", \'h00000001);
$display("%b", \'hffffffff);
$display("%d", \'hffffffff);
$display("%b", \'sh00000001);
$display("%d", \'sh00000001);
$display("%b", \'shffffffff);
$display("%d", \'shffffffff);
end
endmodule
|
module test();
string str;
always @(str) begin
$display("str = %s", str);
end
task automatic test_task(input integer delay, input string str1, input string str2);
string str;
fork
begin
@(str) $display("str%0d = %s", delay, str);
@(str) $display("str%0d = %s", delay, str);
end
begin
#delay;
#2 str = str1;
#2 str = str1;
#2 str = str2;
end
join
endtask
initial begin
#1 str = "hello";
#1 str = "hello";
#1 str = "world";
fork
test_task(1, "hello1", "world1");
test_task(2, "hello2", "world2");
join
fork
test_task(1, "world1", "hello1");
test_task(2, "world2", "hello2");
join
#1 $finish(0);
end
endmodule
|
module test;
reg a, b1, b2;
submod m1 (a, b1, c1);
submod m2 (a, b2, c2);
task set;
input [2:0] bits;
reg t1;
begin
\t t1 <= a;
\t #1 {a,b1,b2} <= bits;
end
endtask
initial
begin
\t$dumpfile("work/vcd-dup.vcd");
\t$dumpvars(2, test); // test, test.m1, test.m2
\t$dumpvars(3, m2.c1, m1.mm1.c1); // duplicate signals
\t#0; // does not trip $enddefinitions
\ta = 0; // does not trip $enddefinitions
\t$dumpvars(0, m1); // (test.m1), test.m1.mm1, test.m1.mm2
\t#1; // $enddefinitions called
\t$dumpvars(0, m2); // ignored
end
initial
begin
\t#1 set(3\'d 0);
\t#1;
\t#1 set(3\'d 1);
\t#1;
\t#1 set(3\'d 2);
\t#1 $dumpoff;
\t#1 set(3\'d 3);
\t#1;
\t#1 set(3\'d 4);
\t#1 $dumpon;
\t#1 set(3\'d 5);
\t#1;
\t#1 set(3\'d 6);
\t#1;
\t#1 set(3\'d 7);
\t#1;
\t#1 set(3\'d 0);
\t#1 $dumpall;
\t#1 $finish;
end
endmodule
module submod (a, b, c);
input a, b;
output c;
subsub mm1 (a&b, c1);
subsub mm2 (a|b, c2);
assign c = c1 ^ c2;
endmodule
module subsub (a, c);
input a;
output c;
wire c1 = ~a;
assign c = c1;
endmodule
|
module main;
initial begin
# 32 $display("PASSED");
$finish;
end
// This delay is \'h1_00000010. The idea here is if the delay is
// only treated as 32 bits anywhere in the processing, then the
// high bits are truncated, and it becomes 16, which is less then
// the 32 above and we fail.
initial begin
# 4294967312 $display("FAILED -- time=%d", $time);
$finish;
end
endmodule // main
|
module stimulus (output reg A, B);
initial begin
// both inputs are x
#0 {A, B} = 2\'bxx;
// both inputs are z
#10 {A, B} = 2\'bzz;
// one input is a zero
#10 {A, B} = 2\'b0x;
#10 {A, B} = 2\'bx0;
#10 {A, B} = 2\'b0z;
#10 {A, B} = 2\'bz0;
// one input is a one
#10 {A, B} = 2\'b1x;
#10 {A, B} = 2\'bx1;
#10 {A, B} = 2\'b1z;
#10 {A, B} = 2\'bz1;
// one input x, other z
#10 {A, B} = 2\'bxz;
#10 {A, B} = 2\'bzx;
// normal bit operands
#10 {A, B} = 2\'b00;
#10 {A, B} = 2\'b01;
#10 {A, B} = 2\'b10;
#10 {A, B} = 2\'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
// both inputs are x
2\'bxx: gate_output = 1\'bx;
// both inputs are z
2\'bzz: gate_output = 1\'bx;
// output should be x (one input is a one)
2\'b1x: gate_output = 1\'bx;
2\'bx1: gate_output = 1\'bx;
2\'b1z: gate_output = 1\'bx;
2\'bz1: gate_output = 1\'bx;
// output is x (one input is a zero)
2\'b0x: gate_output = 1\'bx;
2\'bx0: gate_output = 1\'bx;
2\'b0z: gate_output = 1\'bx;
2\'bz0: gate_output = 1\'bx;
// inputs x, z
2\'bxz: gate_output = 1\'bx;
2\'bzx: gate_output = 1\'bx;
// normal operation on bit
2\'b00: gate_output = 0;
2\'b01: gate_output = 1;
2\'b10: gate_output = 1;
2\'b11: gate_output = 0;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in XOR operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
xor_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#200;
$display("PASSED");
$finish;
end
endmodule
|
/*
* This tests a trivial class. This tests that simple user defined
* methods work.
*/
program main;
// Trivial example of a class
class foo_t ;
int value_;
task clear();
\t value_ = 0;
endtask // clear
task add(int x);
\t this.value_ = this.value_ + x;
endtask // add
function int peek();
\t peek = value_;
endfunction // peek
function int is_multiple(int x);
\t if (value_ % x == 0)
\t is_multiple = 1;
\t else
\t is_multiple = 0;
endfunction // is_multiple
endclass : foo_t // foo_t
foo_t obj;
initial begin
obj = new;
obj.clear();
if (obj.peek() != 0) begin
\t $display("FAILED -- obj.value_=%0d after clear.", obj.value_);
\t $finish;
end
obj.add(5);
if (obj.peek() != 5) begin
\t $display("FAILED -- obj.value_=%0d after add(5).", obj.value_);
\t $finish;
end
if (obj.is_multiple(2) != 0) begin
\t $display("FAILED -- obj.is_multipe(2) incorrect result. (5/2)");
\t $finish;
end
obj.add(3);
if (obj.peek() != 8) begin
\t $display("FAILED -- obj.value_=%0d after add(3).", obj.value_);
\t $finish;
end
if (obj.is_multiple(2) == 0) begin
\t $display("FAILED -- obj.is_multipe(2) incorrect result. (8/2)");
\t $finish;
end
obj.clear();
if (obj.peek() != 0) begin
\t $display("FAILED -- obj.value_=%0d after second clear.", obj.value_);
\t $finish;
end
$display("PASSED");
$finish;
end
endprogram // main
|
// Check that it is possible to declare an enum type with a scalar vector type
// as the base type.
module test;
enum reg {
A
} e1;
enum logic {
B
} e2;
enum bit {
C
} e3;
initial begin
if ($bits(e1) == 1 && $bits(e2) == 1 && $bits(e3) == 1) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module main;
reg [7:0] data_i;
reg [2:0] addr;
reg\t clk, rst, wr;
reg [7:0] data_o, buff[0:7];
(* ivl_synthesis_on *)
always @(posedge clk or posedge rst)
begin
\tif (rst)
\t data_o <= 8\'h0;
\telse if (wr) begin
\t buff[addr] <= data_i;
\t data_o <= data_i;
\tend else
\t data_o <= buff[addr];
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
rst = 1;
wr = 1;
addr = 0;
data_i = 8\'hff;
#1 clk = 1;
#1 clk = 0;
if (data_o !== 8\'h00) begin
\t $display("FAILED -- reset data_o=%b", data_o);
\t $finish;
end
rst = 0;
wr = 1;
for (addr = 0; addr < 7; addr = addr+1) begin
\t data_i = addr;
\t #1 clk = 1;
\t #1 clk = 0;
\t if (data_o !== data_i) begin
\t $display("FAILED -- write data_i=%h, data_o=%h", data_i, data_o);
\t $finish;
\t end
end
wr = 0;
data_i = 8\'hff;
for (addr = 0 ; addr < 7; addr = addr+1) begin
\t #1 clk = 1;
\t #1 clk = 0;
\t if (data_o !== {5\'b00000, addr}) begin
\t $display("FAILED -- read addr=%h, data_o=%h", addr, data_o);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
module Main();
logic[2:0] a = 3\'b111;
logic signed[2:0] a_signed = 3\'b111;
logic[2:0] b = 0;
logic[3:0] c0;
logic[3:0] c1;
initial begin
c0 = 4\'($signed(a)) + b;
c1 = 4\'(a_signed) + b;
$display("c0: %b", c0);
$display("c1: %b", c1);
if (c0 === 4\'b1111 && c1 === 4\'b1111)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/* tern9.v
*/
module main;
reg flag;
reg val;
wire test1 = flag? val : 1\'bx;
wire test2 = flag? 1\'b0 : 1\'bx;
wire test3 = flag? 1\'bx : val;
initial begin
flag = 1;
val = 0;
#1 if (test1 !== 1\'b0) begin
\t $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
\t $finish;
end
if (test2 !== 1\'b0) begin
\t $display("FAILED -- flag=%b, test2=%b", flag, test2);
\t $finish;
end
if (test3 !== 1\'bx) begin
\t $display("FAILED -- flag=%b, test3=%b", flag, test3);
\t $finish;
end
val = 1;
#1 if (test1 !== 1\'b1) begin
\t $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
\t $finish;
end
val = 1\'bx;
#1 if (test1 !== 1\'bx) begin
\t $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
\t $finish;
end
val = 1\'bz;
#1 if (test1 !== 1\'bz) begin
\t $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
\t $finish;
end
flag = 0;
val = 0;
#1 if (test1 !== 1\'bx) begin
\t $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
\t $finish;
end
if (test2 !== 1\'bx) begin
\t $display("FAILED -- flag=%b, test2=%b", flag, test2);
\t $finish;
end
if (test3 !== 1\'b0) begin
\t $display("FAILED -- flag=%b, test3=%b", flag, test3);
\t $finish;
end
val = 1;
#1 if (test1 !== 1\'bx) begin
\t $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
\t $finish;
end
if (test3 !== 1\'b1) begin
\t $display("FAILED -- flag=%b, test3=%b", flag, test3);
\t $finish;
end
val = 1\'bx;
#1 if (test3 !== 1\'bx) begin
\t $display("FAILED -- flag=%b, val=%b, test3=%b", flag, val, test3);
\t $finish;
end
val = 1\'bz;
#1 if (test3 !== 1\'bz) begin
\t $display("FAILED -- flag=%b, val=%b, test3=%b", flag, val, test3);
\t $finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule
|
// Check that a complex base type (like a struct) of an array type is evaluated
// in the scope where the array type is declared.
localparam A = 8;
typedef struct packed {
logic [A-1:0] x;
} T[1:0];
module test;
localparam A = 4;
T x;
initial begin
x[0] = 8\'hff;
if (x[0] === 8\'hff) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
// pr1901125
module test();
function integer hallo (input integer x);
hallo = x - 1;
endfunction // hallo
integer foo;
initial begin
foo = hallo(10);
if (foo !== 9) begin
\t $display("FAILED -- foo=%d", foo);
\t $finish;
end
$display("PASSED");
end
endmodule
|
module main;
reg [3:0] count;
reg\t CLOCK;
reg\t RSTn, SETn;
(* ivl_synthesis_off *)
initial begin
CLOCK = 0;
RSTn = 0;
SETn = 1;
#1 CLOCK = 1;
#1 CLOCK = 0;
if (count !== 4\'b0000) begin
\t $display("FAILED -- initial reset doesn\'t");
\t $finish;
end
RSTn = 1;
#1 CLOCK = 1;
#1 CLOCK = 0;
#1 CLOCK = 1;
#1 CLOCK = 0;
if (count !== 4\'b0010) begin
\t $display("FAILED -- count up is %b", count);
\t $finish;
end
SETn = 0;
#1 ;
if (count !== 4\'b1101) begin
\t $display("FAILED -- Aset failed: count=%b", count);
\t $finish;
end
SETn = 1;
#1 CLOCK = 1;
#1 CLOCK = 0;
if (count !== 4\'b1110) begin
\t $display("FAILED -- Aset didn\'t release: count=%b", count);
\t $finish;
end
RSTn = 0;
#1 ;
if (count !== 4\'b0000) begin
\t $display("FAILED -- Aclr failed: count=%b", count);
\t $finish;
end
$display("PASSED");
$finish;
end
(* ivl_synthesis_on *)
always @(posedge CLOCK or negedge RSTn or negedge SETn)
begin
\tif (!RSTn)
\t count =0; //async clear
\telse
\t if (!SETn)
\t count = 4\'b1101; //async set
\t else
\t count = count + 1;
end
endmodule
|
module test();
wire [2:0] var1 = 3\'bx01; // Incorrect results 101 vs x01.
wire [2:0] var2 = 3\'bx10; // Incorrect results 010 vs x10.
wire [2:0] var3 = 3\'bx0z; // Incorrect results zzz vs x0z.
wire [2:0] var4 = 3\'bx1z; // Incorrect results zzz vs x1z.
wire [2:0] var5 = 3\'bxz1; // Incorrect results 1z1 vs xz1.
wire [2:0] var6 = 3\'bxz0; // Incorrect results 0z0 vs xz0.
wire [3:0] var7 = 4\'bx0z0; // Incorrect results 0000 vs x0z0.
wire [2:0] var8 = 3\'bxxx; // This works correctly.
initial begin
$displayb("Should be:\
x01 x10 x0z x1z xz1 xz0 x0z0 xxx");
$strobeb (var1,, var2,, var3,, var4,, var5,, var6,, var7,, var8);
end
endmodule
|
module main;
wire [7:0] bus;
reg [7:0] HiZ;
assign bus = HiZ;
reg\t E;
reg\t D;
reg\t CLK;
BUFT drv (bus[0], D, E, CLK);
bufif0 drv0 (bus[0], D, E);
initial begin
HiZ = 8\'hzz;
D = 1;
E = 1;
CLK = 0;
#1 CLK = 1;
#1 if (bus !== 8\'bzzzzzzz1) begin
\t $display("FAILED");
\t $finish;
end
if (drv.D !== D) begin
\t $display("FAILED (D)");
\t $finish;
end
E = 0;
#1 if (bus !== 8\'bzzzzzzz1) begin
\t $display("FAILED");
\t $finish;
end
D = 0;
CLK = 0;
#1 CLK = 1;
if (drv.D !== D) begin
\t $display("FAILED (D)");
\t $finish;
end
#1 D = 1;
#1 if (bus !== 8\'bzzzzzzz1) begin
\t $display("FAILED");
\t $finish;
end
if (drv.D !== D) begin
\t $display("FAILED (D)");
\t $finish;
end
$display("bus=%b, D=%b, drv.D=%b, E=%b, drv.save=%b", bus, D, drv.D, E, drv.save);
$display("PASSED");
end // initial begin
endmodule // main
module BUFT(inout wire TO, input wire D, input wire E, input wire CLK);
reg save;
assign TO = E? save : 2\'bz;
always @(posedge CLK)
save <= D;
endmodule // BUFT
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg [1:-1][3:0] vec;
initial begin
pass = 1\'b1;
vec[1] = 4\'bxxxx;
vec[0] = 4\'bxxxx;
vec[-1] = 4\'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1\'bx] = 4\'b1001;
`endif
if ((vec[1] !== 4\'bxxx) && (vec[0] !== 4\'bxxxx) &&
(vec[-1] !== 4\'bxxxx)) begin
$display("Failed vec[1\'bx], expected 4\'bxxxx, got %b, %b,%b",
vec[1], vec[0], vec[-1]);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module test;
integer i;
reg [7:0] c;
reg [31:0] fd[15:0];
initial begin
// Open some MCDs and FD\'s to play with
$display("Open some files");
for (i = 0; i < 4; i = i+1) begin
fd[i] = $fopen("/dev/null");
$display("open MCD returned %x", fd[i]);
end
for (i = 4; i < 6; i = i+1) begin
fd[i] = $fopen("/dev/null", "r");
$display("open FD (\'r\') returned %x", fd[i]);
end
for (i = 6; i < 8; i = i+1) begin
fd[i] = $fopen("/dev/null", "w");
$display("open FD (\'w\') returned %x", fd[i]);
end
for (i = 8; i < 10; i = i+1) begin
fd[i] = $fopen("/dev/null", "a");
$display("open FD (\'a\') returned %x", fd[i]);
end
// Show what\'s open
$test;
// Different systems have different buffer sizes so flush here.
$fflush;
// access some of the files
$fdisplay(1, "write to MCD 1");
$fdisplay(2, "write to MCD 2");
$fflush;
$fdisplay(32\'h8000_0000, "write to FD 0"); // stdin so invisible
$fdisplay(32\'h8000_0001, "write to FD 1");
$fdisplay(32\'h8000_0002, "write to FD 2"); // stderr is normally unbuffered
// so will appear before stdout
// close all the stuff we opened
$display("Close some files");
for (i = 0; i < 10; i = i+1) begin
$fclose(fd[i]);
end
// try closing special and already closed
$fclose(1);
$fclose(2);
$fclose(32\'h4000_0000);
$fclose(32\'h8000_0000);
$fclose(32\'h8000_0001);
$fclose(32\'h8000_0002);
$fclose(32\'h8000_0003);
// Now for something really insane
$fclose(32\'h81ca_1ca0);
// Show what\'s open
$test;
// access to null MCD/FD\'s
$fdisplay(32\'h4000_0000, "write to NULL MCD");
$fdisplay(32\'h8000_000f, "write to NULL FD");
end
endmodule
|
module main;
reg pass = 1\'b1;
reg v1 = 1\'b0;
reg v2 = 1\'b0;
reg v3 = 1\'b0;
reg v4 = 1\'b0;
reg v5 = 1\'b0;
reg v6 = 1\'b0;
reg v7 = 1\'b0;
reg v8 = 1\'b0;
reg v9 = 1\'b0;
reg v10 = 1\'b0;
reg v11 = 1\'b0;
reg v12 = 1\'b0;
reg cond = 1\'b1;
reg [1:0] cval = 2\'b00;
always #1 v1 = 1\'b1;
always v2 = #1 1\'b1;
always if (1\'b1) #1 v3 = 1\'b1;
// This will pass since the else is optimized away!
always if (1\'b1) #1 v4 = 1\'b1; else v4 = 1\'b0;
always if (cond) #1 v5 = 1\'b1; else #1 v5 = 1\'b0;
always begin #1 v6 = 1\'b1; end // 1
always begin #1; v7 = 1\'b1; end // 2
always begin #0; #1 v8 = 1\'b1; end // 3
always begin if (cond) #1 v9 = 1\'b0; else v9 = 1\'b0; #1 v9 = 1\'b1; end // 4
always repeat(1) #1 v10 = 1\'b1;
always case(cval)
2\'b00: #1 v11 = 1\'b1;
2\'b01: #1 v11 = 1\'bx;
default: #1 v11 = 1\'bz;
endcase
always definite_delay;
task definite_delay;
#1 v12 = 1\'b1;
endtask
initial begin
#3;
if (v1 != 1\'b1) begin
$display("Failed delayed assignment.");
pass = 1\'b0;
end
if (v2 != 1\'b1) begin
$display("Failed intra-assignment delay.");
pass = 1\'b0;
end
if (v3 != 1\'b1) begin
$display("Failed simple if statement.");
pass = 1\'b0;
end
if (v4 != 1\'b1) begin
$display("Failed constant if/else statement.");
pass = 1\'b0;
end
if (v5 != 1\'b1) begin
$display("Failed if/else statement.");
pass = 1\'b0;
end
if (v6 != 1\'b1) begin
$display("Failed block (1).");
pass = 1\'b0;
end
if (v7 != 1\'b1) begin
$display("Failed block (2).");
pass = 1\'b0;
end
if (v8 != 1\'b1) begin
$display("Failed block (3).");
pass = 1\'b0;
end
if (v9 != 1\'b1) begin
$display("Failed block (4).");
pass = 1\'b0;
end
if (v10 != 1\'b1) begin
$display("Failed repeat.");
pass = 1\'b0;
end
if (v11 != 1\'b1) begin
$display("Failed case.");
pass = 1\'b0;
end
if (v12 != 1\'b1) begin
$display("Failed task.");
pass = 1\'b0;
end
if (pass) $display("PASSED");
$finish;
end
endmodule
|
/*
* Copyright (c) 2000 Steve Wilson ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This checks bit select from/to vectors with odd bit arrangements.
*/
module test;
reg [1:4] a;
reg [4:1] b;
integer i;
initial begin
a = 4\'b1100;
for (i = 1 ; i <= 4 ; i = i + 1)
\tb[i] = a[i];
$display("a=%b, b=%b", a, b);
if (b !== 4\'b0011) begin
\t $display("FAILED -- b == %b", b);
\t $finish;
end
$display("PASSED");
end
endmodule
|
// Check that it is possible to declare the data type for an enum type task port
// before the direction for non-ANSI style port declarations.
module test;
typedef enum integer {
A, B
} T;
task t;
T x;
input x;
if (x == B && $bits(x) == $bits(T)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t(B);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Memory array instantiation, validation
//
// D: First do the declaration, and assignment of bit wide arrays
// D: and 16 bit wide 4 deep arrays. Then assign values and validate
// D: the assignment worked.
module main();
reg\t\tmem_1 [1:0];\t// Define 2 locations, each 1 bit in depth
reg [15:0]\tmem_2 [3:0];\t// Define a 16 bit wide array - 4 in depth
reg [15:0]\twork16;
reg\t\twork1;
initial // Excitation block
begin
\tmem_1 [0] = 0;\t\t// Do the initial assignment of values
\tmem_1 [1] = 1;
\tmem_2 [0] = 16\'h0;
\tmem_2 [1] = 16\'h1;
\tmem_2 [2] = 16\'h2;
\tmem_2 [3] = 16\'h3;
#5 ;
mem_1 [1] = mem_1 [0] ;\t// use the mem array on the rhs
mem_2 [3] = mem_2 [0] ;
#5;
end
initial // Validation block
begin
#1 ;
// Validate initialization
work1 = mem_1[0];
if(work1 != 0)
begin
$display("FAILED - mem_1 [0] init failed\
");
$finish ;
end
work1 = mem_1[1];
if(work1 != 1)
begin
$display("FAILED - mem_1 [1] init failed\
");
$finish ;
end
work16 = mem_2 [0];
if(work16 != 16\'h0)
begin
$display("FAILED - mem_2 [0] init failed\
");
$finish ;
end
work16 = mem_2 [1];
if(work16 != 16\'h1)
begin
$display("FAILED - mem_2 [1] init failed\
");
$finish ;
end
work16 = mem_2 [2];
if(work16 != 16\'h2)
begin
$display("FAILED - mem_2 [2] init failed\
");
$finish ;
end
work16 = mem_2 [3];
if(work16 != 16\'h3)
begin
$display("FAILED - mem_2 [3] init failed\
");
$finish ;
end
#5 ;
work1 = mem_1[1];
if(work1 != 0)
begin
$display("FAILED - mem_1 [1] rhs assignment \
");
$finish ;
end
work16 = mem_2 [3];
if(work16 != 16\'h0)
begin
$display("FAILED - mem_2 [3] rhs assignment\
");
$finish ;
end
$display("PASSED\
");
$finish ;
end
endmodule
|
/*
* Copyright (c) 2000 Guy Hutchison ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module pullupdown;
// declare several bussed wires
wire pull_up_1, pull_down_1;
wire [7:0] pull_up_8, pull_down_8;
reg\t error;
// assign pullups to each wire
/* -----\\/----- EXCLUDED -----\\/-----
pullup (pull_up_1);
pulldown (pull_down_1);
-----/\\----- EXCLUDED -----/\\----- */
assign (pull1, pull0) pull_up_1 = 1\'b1;
assign (pull1, pull0) pull_down_1 = 1\'b0;
assign (pull1, pull0) pull_up_8 = 8\'hff;
assign (pull1, pull0) pull_down_8 = 8\'h00;
/* -----\\/----- EXCLUDED -----\\/-----
pullup (pull_up_8);
pulldown (pull_down_8);
-----/\\----- EXCLUDED -----/\\----- */
// create tristate drivers for each wire
reg\t driver_1;
reg [7:0] driver_8;
reg\t driver_1_en, driver_8_en;
assign pull_up_1 = (driver_1_en) ? driver_1 : 1\'bz;
assign pull_down_1 = (driver_1_en) ? driver_1 : 1\'bz;
assign pull_up_8 = (driver_8_en) ? driver_8 : 8\'bz;
assign pull_down_8 = (driver_8_en) ? driver_8 : 8\'bz;
initial
begin : test_block
integer i;
// turn off all drivers
driver_1_en = 0;
driver_8_en = 0;
error = 0;
#1;
// check default values
if ((pull_up_1 !== 1\'b1) || (pull_down_1 !== 1\'b0) ||
\t (pull_up_8 !== 8\'hFF) || (pull_down_8 !== 8\'h00))
\terror = 1;
// turn on drivers
driver_1_en = 1;
driver_8_en = 1;
for (i=0; i<256; i=i+1)
\tbegin
\t driver_1 = ~driver_1;
\t driver_8 = i;
\t $display ("Testing drivers with value %h", driver_8);
\t #1;
\t check_drivers;
\t #10;
\tend
if (error)
\t$display ("FAILED - pullupdown ");
else $display ("PASSED");
end // block: test_block
task check_drivers;
begin
if ((pull_up_1 !== driver_1) || (pull_down_1 !== driver_1) ||
\t (pull_up_8 !== driver_8) || (pull_down_8 !== driver_8))
\terror = 1;
end
endtask // check_drivers
endmodule // pullupdown
|
// Check that a class constructor declaration without parenthesis after the
// `new` is supported.
module test;
class C;
function new;
$display("PASSED");
endfunction
endclass
C c = new;
endmodule
|
module top;
reg pass;
highz dutz();
pulllow dut0();
pullhigh dut1();
initial begin
pass = 1\'b1;
#10;
if (pass) $display("PASSED");
end
endmodule
module highz(in);
input in;
initial #1 if (in !== 1\'bz) begin
$display("FAILED: high-Z of floating input port (%b)", in);
top.pass = 1\'b0;
end
endmodule
`unconnected_drive pull0
module pulllow(in);
input in;
initial #1 if (in !== 1\'b0) begin
$display("FAILED: pull0 of floating input port (%b)", in);
top.pass = 1\'b0;
end
endmodule
`nounconnected_drive
`unconnected_drive pull1
module pullhigh(in);
input in;
initial #1 if (in !== 1\'b1) begin
$display("FAILED: pull1 of floating input port (%b)", in);
top.pass = 1\'b0;
end
endmodule
`nounconnected_drive
|
module nested_func();
function automatic real sum;
input real a;
input real b;
begin
sum = a + b;
end
endfunction
real r1;
real r2;
real r3;
initial begin
r1 = sum(sum(2, 3), sum(4, 5));
r2 = sum(3, sum(4, sum(5, 6)));
r3 = sum(sum(sum(4, 5), 6), 7);
$display("sum of 2 to 5 = %0d", r1);
$display("sum of 3 to 6 = %0d", r2);
$display("sum of 4 to 7 = %0d", r3);
end
endmodule
|
module test #(
parameter integer i1 = 1.0, i2 = 2,
parameter [7:0] v1 = 3.0, v2 = 4,
parameter real r1 = 5.0, r2 = 6,
parameter u1 = 7.0, u2 = 8\'d8
)(
);
parameter integer i3 = 1.0, i4 = 2;
parameter [7:0] v3 = 3.0, v4 = 4;
parameter real r3 = 5.0, r4 = 6;
parameter u3 = 7.0, u4 = 8\'d8;
localparam integer i5 = 1.0, i6 = 2;
localparam [7:0] v5 = 3.0, v6 = 4;
localparam real r5 = 5.0, r6 = 6;
localparam u5 = 7.0, u6 = 8\'d8;
reg failed = 0;
initial begin
$display("%b", i1);
$display("%b", i2);
$display("%b", v1);
$display("%b", v2);
$display("%f", r1);
$display("%f", r2);
$display("%f", u1);
$display("%b", u2);
if (i1 !== 32\'d1) failed = 1;
if (i2 !== 32\'d2) failed = 1;
if (v1 !== 8\'d3) failed = 1;
if (v2 !== 8\'d4) failed = 1;
if (r1 != 5.0) failed = 1;
if (r2 != 6.0) failed = 1;
if (u1 != 7.0) failed = 1;
if (u2 !== 8\'d8) failed = 1;
$display("%b", i3);
$display("%b", i4);
$display("%b", v3);
$display("%b", v4);
$display("%f", r3);
$display("%f", r4);
$display("%f", u3);
$display("%b", u4);
if (i3 !== 32\'d1) failed = 1;
if (i4 !== 32\'d2) failed = 1;
if (v3 !== 8\'d3) failed = 1;
if (v4 !== 8\'d4) failed = 1;
if (r3 != 5.0) failed = 1;
if (r4 != 6.0) failed = 1;
if (u3 != 7.0) failed = 1;
if (u4 !== 8\'d8) failed = 1;
$display("%b", i5);
$display("%b", i6);
$display("%b", v5);
$display("%b", v6);
$display("%f", r5);
$display("%f", r6);
$display("%f", u5);
$display("%b", u6);
if (i5 !== 32\'d1) failed = 1;
if (i6 !== 32\'d2) failed = 1;
if (v5 !== 8\'d3) failed = 1;
if (v6 !== 8\'d4) failed = 1;
if (r5 != 5.0) failed = 1;
if (r6 != 6.0) failed = 1;
if (u5 != 7.0) failed = 1;
if (u6 !== 8\'d8) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test;
parameter SIZE = 2;
reg [SIZE-1:0] d ;\t// data in
reg\t\t c ;\t// latch control
wire [SIZE-1:0] q ;\t// output
unit_latch u_lat[SIZE-1:0] (.Q(q), .G(c), .D(d));
initial begin
d = 0;
c = 1;
#1 if (q !== 2\'b00) begin
\t $display("FAILED -- Initial load failed.");
\t $finish;
end
d = 2\'b01;
#1 if (q !== 2\'b01) begin
\t $display("FAILED -- Latch follow failed.");
\t $finish;
end
c = 0;
#1 d = 2\'b10;
#1 if (q !== 2\'b01) begin
\t $display("FAILED -- Latch hold failed.");
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule
module unit_latch(output reg Q, input wire D, input wire G);
always @*
if (G) Q = D;
endmodule // unit_latch
|
module test;
reg [7:0] i8, j8;
reg [31:0] i32;
initial begin
i8 = 32\'hf7;
j8 = 32\'h3;
i32 = $signed(i8 / j8);
$write("expected %0h; got %0h\
", 8\'h52, i32);
i8 = 32\'hf7;
j8 = 32\'h1;
i32 = $signed(i8 / j8);
$write("expected %0h; got %0h\
", 32\'hffffff_f7, i32);
end
endmodule
|
module test(CL, Q_data, D);
parameter
Bits = 84;
input CL;
output [Bits-1 : 0] Q_data;
input [Bits-1 : 0] D;
reg WENreg;
reg ICGFlag;
specify
specparam
taa = 1.0;
if (WENreg && !ICGFlag) (CL *> (Q_data[0] : D[0])) = (taa, taa);
endspecify
endmodule
|
module main;
generate
genvar i;
for( i=0; i<4; i=i+2 )
\tbegin : U
\t reg [1:0] a;
\t initial begin : V
\t a = 2\'b0;
\t #10;
\t a = i;
\t end
\tend
endgenerate
initial begin
#5 ;
if (U[0].V.a !== 2\'d0) begin
\t $display("FAILED -- U[0].V.a = %d", U[0].V.a);
\t $finish;
end
if (U[2].V.a !== 2\'d0) begin
\t $display("FAILED -- U[2].V.a = %d", U[2].V.a);
\t $finish;
end
#10 ;
if (U[0].V.a !== 2\'d0) begin
\t $display("FAILED -- U[0].V.a = %d", U[0].V.a);
\t $finish;
end
if (U[2].V.a !== 2\'d2) begin
\t $display("FAILED -- U[2].V.a = %d", U[2].V.a);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_REAL_NETS_IN_IVTEST
`endif
module top;
reg pass = 1\'b1;
integer scale = 2, offset = 1;
real rin;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
wire real ress = scale * rin;
wire real reso = rin + offset;
`endif
initial begin
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
#1 if (ress != 0.0 || reso != 1.0) begin
\t $display("FAILED: initial value, expected 0.0/1.0, got %f/%f", ress, reso);
\t pass = 1\'b0;
end
rin = 2.0;
#1 if (ress != 4.0 || reso != 3.0) begin
\t $display("FAILED: rin=%f, scale=%f, expected 2.0/2.0, got %f/%f", rin, scale, ress, reso);
\t pass = 1\'b0;
end
`endif
if (pass)
\t$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Initial readmemh function - length of data = array size.
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
$readmemh("ivltests/readmemh1.dat",array);
for(count = 0; count <= 7; count = count + 1)
begin
if(array[count[2:0]] !== count)
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count],count);
end
end
if(error == 0)
$display("PASSED\
");
$finish ;
end
endmodule
|
/*
* Test expressions with very wide reg variables.
*/
module test;
parameter idx = 3584; // Anything lower works
reg [69119:0] mem;
reg r;
initial begin
mem[idx] = 1;
r = mem >> idx;
if (r !== 1)
$display("FAILED r = %b", r);
else
$display("PASSED");
end
endmodule
|
module top;
reg [4:0]cntr;
wire done;
wire allone;
// A delayed comparison is only 1 bit wide. If this does not crash
// the run time then the compiler is producing correct code.
assign #1 done = cntr == \'d7;
// The same for a reduction.
assign #1 allone = &cntr;
initial $display("PASSED");
endmodule
|
/*
* Author: Oswaldo Cadenas <[email protected]>
*
* The test checks that an unspecified output type is elaborated as Net.
* If an intial value is given to an unspecified ouput type it does
* not compile.
*/
module clkgen(output logic clk);
logic iclk = \'x;
assign clk = iclk;
initial begin
#100;
disable checking;
disable gen;
$display ("PASSED");
$finish;
end
initial begin
fork
\t checking;
\t gen;
join
end
task gen;
begin
\t iclk = 0;
\t forever #10 iclk = ~iclk;
end
endtask
task checking;
forever begin
\t #1;
\t if (clk === 1\'bx ) begin
\t $display ("FAILED!");
\t $finish;
\t end
end
endtask
endmodule
|
module top;
reg passed;
reg [7:0] val;
reg signed [7:0] sval;
real rval;
initial begin
passed = 1\'b1;
val = 8\'hff;
sval = 8\'hff;
/* Check a constant unsigned value cast to signed. */
rval = $itor($signed(8\'hff));
if (rval != -1.0) begin
$display("Failed unsigned constant cast to signed conversion, ",
"expected -1.0, got %g.", rval);
passed = 1\'b0;
end
/* Check an unsigned variable cast to signed. */
rval = $itor($signed(val));
if (rval != -1.0) begin
$display("Failed unsigned variable cast to signed conversion, ",
"expected -1.0, got %g.", rval);
passed = 1\'b0;
end
/* Check a constant signed value. */
rval = $itor(8\'shff);
if (rval != -1.0) begin
$display("Failed signed constant conversion, ",
"expected -1.0, got %g.", rval);
passed = 1\'b0;
end
/* Check a variable signed value. */
rval = $itor(sval);
if (rval != -1.0) begin
$display("Failed signed variable conversion, ",
"expected -1.0, got %g.", rval);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
module test;
integer i;
initial begin
i = 7+1;
if (i != 8)
$display ("FAILED -- i = %0d != 8", i);
else
$display ("PASSED");
end
endmodule
|
/*
*/
module main;
reg [1:0] sel, in;
reg [1:0] out;
(* ivl_combinational *)
always @* begin
(* ivl_full_case *) case (sel)
2\'b01: out = 2\'b10;
2\'b10: out = in[0];
2\'b11: out = in[1];
endcase // casex(sel)
end
(* ivl_synthesis_off *)
initial begin
in = 2\'b10;
sel = 1;
#1 if (out !== 2\'b10) begin
\t $display("FAILED -- sel=%b, out=%b", sel, out);
\t $finish;
end
sel = 2;
#1 if (out !== 2\'b00) begin
\t $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
\t $finish;
end
sel = 3;
#1 if (out !== 2\'b01) begin
\t $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module stimulus (output reg A, B);
initial begin
// both inputs are x
#0 {A, B} = 2\'bxx;
// both inputs are z
#10 {A, B} = 2\'bzz;
// one input is a zero
#10 {A, B} = 2\'b0x;
#10 {A, B} = 2\'bx0;
#10 {A, B} = 2\'b0z;
#10 {A, B} = 2\'bz0;
// one input is a one
#10 {A, B} = 2\'b1x;
#10 {A, B} = 2\'bx1;
#10 {A, B} = 2\'b1z;
#10 {A, B} = 2\'bz1;
// normal bit operands
#10 {A, B} = 2\'b00;
#10 {A, B} = 2\'b01;
#10 {A, B} = 2\'b10;
#10 {A, B} = 2\'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
// both inputs are x
2\'bxx: gate_output = 1\'bx;
// both inputs are z
2\'bzz: gate_output = 1\'bx;
// output should be one (one input is a zero)
2\'b0x: gate_output = 1;
2\'bx0: gate_output = 1;
2\'b0z: gate_output = 1;
2\'bz0: gate_output = 1;
// output is x (one input is a one)
2\'b1x: gate_output = 1\'bx;
2\'bx1: gate_output = 1\'bx;
2\'b1z: gate_output = 1\'bx;
2\'bz1: gate_output = 1\'bx;
// inputs x, z
2\'bxz: gate_output = 1\'bx;
2\'bzx: gate_output = 1\'bx;
// normal operation on bit
2\'b00: gate_output = 1;
2\'b01: gate_output = 1;
2\'b10: gate_output = 1;
2\'b11: gate_output = 0;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in NAND operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
nand_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#200;
$display("PASSED");
$finish;
end
endmodule
|
`define simple "simple name"
`define \\escaped "escaped name"
`define \\`name "backtick name"
`define \\` "backtick"
`define \\quote (x) `"`\\`"x`\\`"`"
`define \\`\\`" "escaped quote"
module test();
initial begin
$display(`simple);
$display(`\\simple );
$display(`escaped);
$display(`\\escaped );
$display(`\\`name );
$display(`\\` );
$display(`quote(text));
$display(`\\quote (text));
$display(`\\`\\`" );
end
endmodule
|
module top;
reg a, b, c, d, e;
wor out;
assign out = a;
assign out = b;
assign out = c;
assign out = d;
assign out = e;
initial begin
a = 1\'b0;
b = 1\'b0;
c = 1\'b1;
d = 1\'b0;
e = 1\'b0;
#1;
if (out !== 1\'b1) $display("FAILED: expected 1\'b1, got %b", out);
else $display("PASSED");
end
endmodule
|
module top;
localparam [6:0] with_range = 63;
localparam no_range = 1;
initial if (with_range != 63 || no_range != 1) $display("FAILED");
else $display("PASSED");
endmodule
|
/*
* Based on PR#904.
* This test is part of elist, and *should* generate an
* error.
*/
module err ();
reg clk, reset_b;
initial begin
clk = 1'b1;
#3 forever #10 clk=~clk;
end
initial begin
reset_b = 0;
repeat (10) @(posedge clk);
#3 reset_b = 1;
end
reg [31:0] kuku;
always @(posedge clk or negedge reset_b)
if (~reset_b) begin
kuku <= 0;
end
else begin
kuku <= {3'd5,3'd5,,3'd5,3'd5,3'd5};
end
endmodule
|
module test();
wire x, y;
a__a a_(
.b_buf(y),
.b (x)
);
endmodule
module a__a(b_buf, b);
output b_buf;
input b;
endmodule // a__a
|
module top;
reg pass;
reg [3:0] value;
reg [3:0] in;
initial begin
pass = 1\'b1;
value = 4\'b1001;
if (value !== 4\'b1001) begin
$display("Failed: initial value, expected 4\'b1001, got %b", value);
pass = 1\'b0;
end
in = 4\'bzx10;
// This should work since it is really the whole value.
force value[0 +: 4] = in;
if (value !== 4\'bzx10) begin
$display("Failed: force value, expected 4\'bzx10, got %b", value);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
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