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stringlengths 1
2.1M
|
|---|
// Check a local timeprecision that is too large.
`resetall
module ltp_large;
timeunit 1ns/10ns;
endmodule
|
// Test that cast to enum works in continuous assignments
module test();
typedef enum { a, b, c } enum_type;
enum_type enum_value;
assign enum_value = enum_type\'(1);
initial begin
if (enum_value == b) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module top;
initial $display("The following should be a single percent: %");
endmodule
|
/*
* Copyright (c) 1999 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// This example describes a 16x1 RAM that can be synthesized into
// a CLB ram in a Xilinx FPGA.
module ram16x1 (q, d, a, we, wclk);
output q;
input d;
input [3:0] a;
input we;
input wclk;
reg mem[15:0];
assign q = mem[a];
always @(posedge wclk) if (we) mem[a] = d;
endmodule /* ram16x1 */
module main;
wire q;
reg d;
reg [3:0] a;
reg we, wclk;
ram16x1 r1 (q, d, a, we, wclk);
initial begin
wclk = 0;
we = 1;
for (a = 0 ; a < 4\'hf ; a = a + 1) begin
\t d = a[0];
\t #1 wclk = 1;
\t #1 wclk = 0;
\t $display("r1[%h] == %b", a, q);
end
for (a = 0 ; a < 4\'hf ; a = a + 1)
\t #1 if (q !== a[0]) begin
\t $display("FAILED -- mem[%h] !== %b", a, a[0]);
\t $finish;
\t end
$display("PASSED");
end
endmodule /* main */
|
module top;
lower #(1, 2, 3) dut();
endmodule
module lower;
parameter one = 1; // This should be \'sd1
parameter two = 2; // This should be \'sd2
parameter three = 0; // This should be \'sd3
parameter local1 = one - two; // This should be -\'sd1
parameter local_lt0 = local1 < 0; // This should be \'d1
parameter local_le0 = local1 <= 0; // This should be \'d1
parameter local_gt0 = local1 > 0; // This should be \'d0
parameter local_ge0 = local1 >= 0; // This should be \'d0
parameter local_0lt = 0 < local1; // This should be \'d1
parameter local_0le = 0 <= local1; // This should be \'d1
parameter local_0gt = 0 > local1; // This should be \'d0
parameter local_0ge = 0 >= local1; // This should be \'d0
reg err;
initial begin
err = 0;
if (!local_lt0) err = 1;
if (!local_le0) err = 1;
if ( local_gt0) err = 1;
if ( local_ge0) err = 1;
if ( local_0lt) err = 1;
if ( local_0le) err = 1;
if (!local_0gt) err = 1;
if (!local_0ge) err = 1;
if (err == 0) $display("PASSED");
else $display("FAILED");
end
endmodule
|
module test;
wire real array[1:0];
reg [7:0] index;
real value;
initial begin
index = 3;
value = array[index];
if (value == 0.0)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as a vector typed variable and
// the size of the packed dimensions do not match.
module test;
task t;
input [7:0] x;
reg [3:0] x;
$display("FAILED");
endtask
initial begin
t(10);
end
endmodule
|
// pr1661640.v
module test;
reg [112:1] hello1, hello2;
initial begin
hello1 = "Hello world!\
";
hello2 = "Hello world!\\012";
main;
end
task main;
begin
\t $write ("%s\
", "Hello world!"); // Ok
\t $write ("%s", "Hello world!\
"); // bad
\t $write ("\
hello1; escaped NL:\
");
\t $write ("%0s", hello1); // bad
\t $write ("%x", hello1);
\t $write ("\
hello2; octal NL:\
");
\t $write ("%0s", hello2); // bad
\t $write ("%x", hello2);
\t $display();
end
endtask
endmodule
|
module top;
reg clk;
reg pass = 1\'b1;
generate
genvar n;
for (n=0; n<4; n=n+1) begin : loop
reg [n:0] r;
always @(clk) r = n;
end
endgenerate
initial begin
clk = 0;
#1;
if (loop[0].r !== 0) begin
$display("Failed generate instance 0");
pass = 1\'b0;
end
if (loop[1].r !== 1) begin
$display("Failed generate instance 1");
pass = 1\'b0;
end
if (loop[2].r !== 2) begin
$display("Failed generate instance 2");
pass = 1\'b0;
end
if (loop[3].r !== 3) begin
$display("Failed generate instance 3");
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module stimulus;
reg[9:0] foo;
initial
begin
foo <= 0-155;
#1000 if (foo !== 10\'h365) begin
$display("FAILED -- foo = %b", foo);
$finish;
end
$display("PASSED");
end
endmodule
|
module testbench;
foo #(ASDF) bar();
endmodule
module foo #(parameter A=1);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always 3.1.2B always reg_lvalue <= boolean_expression ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
if(value1 != 4\'b1)
\t$display("FAILED - 3.1.2B always reg_lvalue = boolean_expression\
");
else
\tbegin
$display("PASSED\
");
\t $finish;
end
always value1 <= 1\'b1 && 1\'b1 ;
endmodule
|
module top;
initial begin: b_label
$display("PASSED");
end: b_label
initial fork:fj_label
join:fj_label
initial fork:fja_label
join_any:fja_label
initial fork:fjn_label
join_none:fjn_label
task t_label;
endtask: t_label
task twa_label(input arg);
endtask: twa_label
function fn_label;
input arg;
endfunction: fn_label
function fa_label(input in);
endfunction: fa_label
endmodule:top
macromodule extra;
parameter add_inv = 1;
reg a;
wire y, yb;
pbuf dut(y, a);
if (add_inv) begin: g_label
pinv dut2(yb, y);
end: g_label
endmodule: extra
package pkg;
endpackage: pkg
program pgm;
class foo;
endclass: foo
endprogram: pgm
primitive pbuf (out, in);
output out;
input in;
table
0 : 0;
1 : 1;
endtable
endprimitive: pbuf
primitive pinv (output out, input in);
table
0 : 1;
1 : 0;
endtable
endprimitive: pinv
|
/*
* This program tests that enumeration values work and are
* implicitly translated to integer values.
*/
module main;
enum { RED, ORANGE, YELLOW, GREEN, BLUE, VIOLET,
\t BLACK = 10, WHITE = \'d11
\t} color1;
int\tvar1;
initial begin
color1 = RED;
var1 = RED;
$display("color1 = %0d, var1 = %0d", color1, var1);
if (color1 !== 0) begin
\t $display("FAILED");
\t $finish;
end
if (var1 !== 0) begin
\t $display("FAILED");
\t $finish;
end
color1 = GREEN;
var1 = GREEN;
$display("color1 = %0d, var1 = %0d", color1, var1);
if (color1 !== 3) begin
\t $display("FAILED");
\t $finish;
end
if (var1 !== 3) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Check that it is possible to declare the data type for an integer type task
// port before the direction for non-ANSI style port declarations.
module test;
task t;
integer x;
input x;
if (x == 10 && $bits(x) == $bits(integer)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t(10);
endmodule
|
module main;
wire [15:0] out;
reg [16:0] in;
reg [15:0] mask;
mask dut (.\\output (out), .\\input (in[15:0]), .mask(mask));
wire [15:0] out_ref = in[15:0] & mask;
initial begin
for (in = 0 ; in[16] == 0 ; in = in+1) begin
\t mask = $random;
\t #1 if (out !== out_ref) begin
\t $display("FAILED: in=%b, out=%b, mask=%b, out_ref=%b", in, out, mask, out_ref);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
module t();
parameter eh = 11;
parameter mh = 52;
parameter ih2 = 6;
parameter fh = 7;
localparam ih = 1 << ih2;
reg [ih - 1:0] i_abs;
reg at;
reg [ih2 - 1:0] fls;
wire [ih - 1:0] i_norm;
assign i_norm = i_abs << (at ? ih - mh - 1 : fls);
initial
begin
\tat = 1;
\tfls = 123;
\ti_abs = \'h123;
\t#1;
\tif(i_norm !== (\'h123 << 11))
\t\t$display("FAILED");
\telse
\t\t$display("PASSED");
end
endmodule
|
module br993a();
reg clk;
reg a;
reg b;
reg [1:0] q;
(* ivl_synthesis_on *)
always @(posedge clk) begin
if (a) q <= 1;
if (b) q <= 2;
end
(* ivl_synthesis_off *)
reg failed;
initial begin
clk = 0;
a = 1;
b = 1;
#1 clk = 1;
#1 clk = 0;
$display("%d", q);
if (q !== 2\'d2) failed = 1;
a = 0;
b = 0;
#1 clk = 1;
#1 clk = 0;
$display("%d", q);
if (q !== 2\'d2) failed = 1;
a = 1;
b = 0;
#1 clk = 1;
#1 clk = 0;
$display("%d", q);
if (q !== 2\'d1) failed = 1;
a = 0;
b = 0;
#1 clk = 1;
#1 clk = 0;
$display("%d", q);
if (q !== 2\'d1) failed = 1;
a = 0;
b = 1;
#1 clk = 1;
#1 clk = 0;
$display("%d", q);
if (q !== 2\'d2) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// This should generate an error
module main;
reg[7:0] shared;
wire [7:0] not_shared = ~shared;
program test1;
initial shared <= \'h55;
endprogram :test1
program test2;
reg [7:0] tmp;
final begin
if (shared !== \'h55) begin
\t $display("FAILED -- shared=%b is not correct", shared);
\t $finish;
end
tmp <= ~shared; // ERROR: only blocking assign in final block
if (not_shared !== \'haa) begin
\t $display("FAILED -- not_shared is not correct", not_shared);
\t $finish;
end
$display("PASSED");
end
endprogram :test2
endmodule // main
|
// Check whether it is possible to declare a parameter in a generate block
// In Verilog this should fail, in SystemVerilog the parameter is elaborated as
// localparam and the test should pass.
module test;
generate
genvar i;
for (i = 0; i < 2; i = i + 1) begin : loop
parameter A = i;
reg [A:0] r = A+1;
end
endgenerate
initial begin
if (loop[0].r == 1 && loop[1].r == 2) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module top;
reg pass;
integer val;
initial begin
pass = 1\'b1;
// Check ARS in a fully signed context.
// All operands are signed.
val = -1;
val = 7\'sd10 + (val >>> 1);
if (val !== 9) begin
$display("Failed ARS in signed context, got %d", val);
pass = 1\'b0;
end
// Check ARS in a cast signed context.
// This is fully signed as well because of the cast.
val = -1;
val = $signed(7\'d10) + (val >>> 1);
if (val !== 9) begin
$display("Failed ARS in cast signed context, got %d", val);
pass = 1\'b0;
end
// Check ARS in a self determined context.
// The system function is a primary and should create a self-determined
// context for the ARS. The addition is then done in an unsigned
// context, but this should still give the correct result.
//
// The bug is that Icarus is not sign padding the ARS since the
// addition is casting it to be unsigned. It should only be able to
// cast the sign of the result not the actual ARS! This casting is
// happening in suppress_binary_operand_sign_if_needed() defined in
// elab_expr.cc. It looks like $signed and $unsigned need some way
// to protect their argument self-determined context.
val = -1;
val = 7\'d10 + $signed(val >>> 1);
if (val !== 9) begin
$display("Failed ARS in $signed context, got %d", val);
pass = 1\'b0;
end
// Check ARS in a different self determined context.
// See comments above for $signed.
val = -1;
val = 7\'d10 + $unsigned(val >>> 1);
if (val !== 9) begin
$display("Failed ARS in $unsigned context, got %d", val);
pass = 1\'b0;
end
// Check ARS in a different self determined context.
val = -1;
val = 7\'d10 + {val >>> 1};
if (val !== 9) begin
$display("Failed ARS in a concatenation context, got %d", val);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`define DEV_TYPE "DEVICE 2"
module top;
parameter device = `DEV_TYPE;
wire res;
function is_dev1;
input[8*20:1] device;
reg is_device;
begin
if ((device == "DEVICE1") || (device == "DEVICE 1"))
is_device = 1;
else
is_device = 0;
is_dev1 = is_device;
end
endfunction
function is_dev2;
input[8*20:1] device;
reg is_device;
begin
if ((device == "DEVICE2") || (device == "DEVICE 2"))
is_device = 1;
else
is_device = 0;
is_dev2 = is_device;
end
endfunction
function is_dev;
input[8*20:1] device;
reg is_device;
begin
// Changing this to a single item makes things work.
if (is_dev1(device) || is_dev2(device))
is_device = 1;
else
is_device = 0;
is_dev = is_device;
end
endfunction
assign res = (is_dev(device) == 1) ? 1\'b1 : 1\'b0;
initial #1 if (res == 1\'b1) $display("PASSED");
else $display("FAILED");
endmodule
|
// Test unary operators in constant functions
module constfunc4();
function [7:0] LAbs(input signed [7:0] x);
LAbs = abs(x);
endfunction
function real RAbs(input real x);
RAbs = abs(x);
endfunction
localparam [7:0] ResultLAb1 = LAbs(8\'sh01);
localparam [7:0] ResultLAb2 = LAbs(8\'shff);
localparam real ResultRAb1 = RAbs( 2.0);
localparam real ResultRAb2 = RAbs(-2.0);
reg failed;
initial begin
failed = 0;
$display("%h", ResultLAb1);
$display("%h", ResultLAb2);
$display("%g", ResultRAb1);
$display("%g", ResultRAb2);
if (ResultLAb1 !== 8\'h01) failed = 1;
if (ResultLAb2 !== 8\'h01) failed = 1;
if (ResultRAb1 != 2.0) failed = 1;
if (ResultRAb2 != 2.0) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* This tests is based on PR#938. Check here that the
* IEEE1364-2001 format for port declarations works for
* user defined primitives.
*/
`timescale 1ns/100ps
module test;
wire out;
reg A, B, select;
prim_mux2 mux (out, B, A, select);
reg [3:0] cnt;
initial begin
$display("A B S out");
for (cnt = 0 ; cnt <= \'b0111 ; cnt = cnt + 1) begin
\t A <= cnt[0];
\t B <= cnt[1];
\t select <= cnt[2];
\t #1 $display("%b %b %b --> %b", A, B, select, out);
end
end
endmodule
primitive prim_mux2(output out, input in1, input in0, input select);
table
//in1 in0 select : out
0 0 1 : 0;
1 1 ? : 1;
0 ? 1 : 0;
1 ? 1 : 1;
? 0 0 : 0;
? 1 0 : 1;
endtable
endprimitive
|
/*
* For a non-blocking delay the last NB assign in the same thread
* at the same time must set the final result, but you are allowed
* to have multiple assignments in the queue.
*/
module top;
reg passed = 1\'b1;
reg out;
real rout;
integer delay;
initial begin
out <= 1\'b1;
out <= 1\'b0;
rout <= 0.0;
rout <= 1.0;
#1;
if (out !== 1\'b0) begin
$display("FAILED: zero delay, expected 1\'b0, got %b", out);
passed = 1\'b0;
end
if (rout != 1.0) begin
$display("FAILED: zero delay (real), expected 1.0, got %f", rout);
passed = 1\'b0;
end
out <= #1 1\'b0;
out <= #1 1\'b1;
rout <= #1 0.0;
rout <= #1 2.0;
#2;
if (out !== 1\'b1) begin
$display("FAILED: constant delay, expected 1\'b1, got %b", out);
passed = 1\'b0;
end
if (rout != 2.0) begin
$display("FAILED: constant delay (real), expected 2.0, got %f", rout);
passed = 1\'b0;
end
delay = 2;
out <= #(delay) 1\'b1;
out <= #(delay) 1\'b0;
rout <= #(delay) 0.0;
rout <= #(delay) 3.0;
#(delay+1);
if (out !== 1\'b0) begin
$display("FAILED: calculated delay, expected 1\'b0, got %b", out);
passed = 1\'b0;
end
if (rout != 3.0) begin
$display("FAILED: calculated delay (real), expected 3.0, got %f", rout);
passed = 1\'b0;
end
out <= #1 1\'b1;
out <= #3 1\'b0;
out <= #5 1\'b1;
rout <= #1 1.0;
rout <= #3 3.0;
rout <= #5 5.0;
#2;
if (out !== 1\'b1) begin
$display("FAILED: first delay, expected 1\'b1, got %b", out);
passed = 1\'b0;
end
if (rout != 1.0) begin
$display("FAILED: first delay (real), expected 1.0, got %f", rout);
passed = 1\'b0;
end
#2;
if (out !== 1\'b0) begin
$display("FAILED: second delay, expected 1\'b0, got %b", out);
passed = 1\'b0;
end
if (rout != 3.0) begin
$display("FAILED: second delay (real), expected 3.0, got %f", rout);
passed = 1\'b0;
end
#2;
if (out !== 1\'b1) begin
$display("FAILED: third delay, expected 1\'b1, got %b", out);
passed = 1\'b0;
end
if (rout != 5.0) begin
$display("FAILED: third delay (real), expected 5.0, got %f", rout);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for selected assignments.
module vhdl_selected_test;
logic [1:0] sel;
logic [3:0] in;
logic out;
vhdl_selected dut(sel, in, out);
initial begin
in = 4\'b1010;
sel = 1\'b00;
#1;
if(out !== 1\'b0) begin
$display("FAILED 1");
$finish();
end
sel = 1\'b01;
#1;
if(out !== 1\'b1) begin
$display("FAILED 2");
$finish();
end
sel = 1\'b10;
#1;
if(out !== 1\'b0) begin
$display("FAILED 3");
$finish();
end
sel = 1\'b11;
#1;
if(out !== 1\'b1) begin
$display("FAILED 4");
$finish();
end
$display("PASSED");
end
endmodule
|
/* )* */
/* (* /* *) */
module test();
initial $display("PASSED");
endmodule
|
/*
* This demonstrates a basic dynamic array
*/
module main;
shortint foo[];
int idx;
initial begin
if (foo.size() != 0) begin
\t $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
\t $finish;
end
foo = new[10];
if (foo.size() != 10) begin
\t $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
\t $finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
\t foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
\t $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
\t $finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
\t $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
\t $finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
\t if (foo[idx%10] != (idx%10)) begin
\t $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]);
\t $finish;
\t end
end
foo.delete();
if (foo.size() != 0) begin
\t $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// -*- Mode: Verilog -*-
// Filename : cnr_tb.v
// Description : single row corner bender testbench
// Author :
// Created On : Thu Mar 23 16:23:01 2006
// Last Modified By: $Id: pr1492075.v,v 1.1 2006/06/02 05:01:52 stevewilliams Exp $
// Last Modified On: .
// Status : Unknown, Use with caution!
`timescale 1ns / 10ps
module cnr_tb ();
reg clkb;
reg clocken;
integer cntb;
// clock generation clkb
always @ (posedge clocken)
begin
\tfor (cntb=0; cntb<5; cntb=cntb+1)
\t begin
\t #(10 + -2) clkb = 1;
\t #(10 - -2) clkb = 0;
\t end
end
//
initial
begin
\t$monitor("clkb=%b at %t", clkb, $time);
\tclkb = 1\'b0;
\tclocken = 0;
\t#1 clocken = 1;
\t#(10*20) clocken = 0;
\t#100;
\t$finish(0);
end
endmodule // cnr_tb
|
// Check that it is possible to declare the data type for an atom2 type task
// port before the direction for non-ANSI style port declarations.
module test;
task t;
int x;
input x;
if (x == 10 && $bits(x) == $bits(int)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t(10);
endmodule
|
/*
* A simple test of some of the structural elements.
*/
module testbench;
wire o;
reg i0, i1, sel;
mux2 uut(o, i0, i1, sel);
initial begin
i0 <= 1;
i1 <= 0;
sel <= 0;
#1;
sel <= 1;
#1;
i1 <= 1;
#1;
end
always @(o)
$display(o);
endmodule // testbench
module mux2(c, a, b, s);
input a, b, s;
output c;
wire s_bar, a_and_s_bar, b_and_s;
not(s_bar, s);
and(a_and_s_bar, a, s_bar);
and(b_and_s, b, s);
or(c, a_and_s_bar, b_and_s);
endmodule // mux2
|
\r
\r
module test();\r
typedef struct packed {\r
logic [31:0] sub_local;\r
} row_entry_t; \r
\r
typedef struct packed {\r
logic [31:0] row_local;\r
row_entry_t sub;\r
row_entry_t [1:0] sub_list;\r
} row_t; \r
\r
row_t main;\r
\r
initial begin\r
main.row_local = 32\'hCAFE;\t\r
main.sub.sub_local = 32\'h00000001;\r
main.sub_list[0].sub_local = 32\'hACE;\r
main.sub_list[1].sub_local = 32\'hECA;\r
$display("main=0x%08X", main);\r
if (main !== 128\'h0000cafe0000000100000eca00000ace) begin\r
\t $display("FAILED -- main != 128\'h0000cafe0000000100000eca00000ace");\r
\t $finish;\r
end\r
$display("main.row_local=0x%08X", main.row_local); \r
$display("main.sub=0x%08X", main.sub); \r
//$display("0x%08X", main.sub.sub_local); \r
//$display("0x%08X", main.sub_list[0].sub_local); \r
$display("PASSED");\r
$finish();\r
end\r
\r
endmodule\r
|
module top;
initial begin
$display("PASSED");
end;
endmodule;
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always if ( bool_expr) statement else ;
module main ;
reg [3:0] value1 ;
initial
\tbegin
value1 = 0;
# 5 ;
if(value1 != 4\'d4)
$display("FAILED - always 3.1.5E always if ( bool_expr) statementelse ;");
else
$display("PASSED");
\t $finish;
end
always if( 1\'b1 & 1\'b1) begin
# 1;
value1 = value1 + 1;
end
else ;
endmodule
|
module top;
integer lp;
wire signed [5:0] in = lp[5:0];
// If these two are combined "$signed({1\'b0,in[5]})" then this will work
// as expected.
wire [5:0] #1 base = (in + (in >>> 2)) >>> 2;
wire signed [5:0] #1 fix = base + in[5];
// wire [5:0] base; // If this is missing the program will core dump!
// wire signed [5:0] #1 fix = ((in + (in >>> 2)) >>> 2) + $signed({1\'b0,in[5]});
wire [6:0] #1 res = in + fix;
always @(*) $display("%0d: %d %d %d %d", $time, $signed(in), $signed(base),
$signed(fix), $signed(res));
// It appears that the final calculation event is being lost for fix == -1.
initial begin
lp = -7;
#5 lp = -5;
#1 lp = -6;
#5 if ($signed(res) !== -7) $display("FAILED");
else $display("PASSED");
end
endmodule
|
module main;
reg [3:0] cond;
reg [2:0] t, q;
always @* begin
case (cond&4\'b1110)
\'h0: t = 7;
\'h2: t = 6;
\'h4: t = 5;
\'h6: t = 4;
\'h8: t = 3;
\'ha: t = 2;
\'hc: t = 1;
\'he: t = 0;
endcase // case(cond&4\'b1110)
q = ~t;
end // always @ *
integer i;
initial begin
for (i = 0 ; i < 8 ; i = i + 1) begin
\t cond = i << 1;
\t #1 if (q !== ( 3\'b111 & ~(7 - i))) begin
\t $display("FAILED -- i=%d, cond=%b, q=%b", i, cond, q);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
// Check that it is possible to declare the data type for a time type module
// port before the direction for non-ANSI style port declarations.
module test(x);
time x;
output x;
initial begin
if ($bits(x) == 64) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
// Copyright 2008, Martin Whitaker.
// This file may be freely copied for any purpose.
module scan_int_array();
integer f;
integer i;
integer n;
integer v[0:3];
initial begin
f = $fopen("work/temp.txt", "w");
for (i = 0; i < 4; i = i + 1) begin
$fdisplay(f, "%d", i);
end
$fclose(f);
f = $fopen("work/temp.txt", "r");
for (i = 0; i < 4; i = i + 1) begin
n = $fscanf(f, " %d ", v[i]);
end
$fclose(f);
for (i = 0; i < 4; i = i + 1) begin
$display("%1d", v[i]);
end
end
endmodule
|
module main;
localparam width = 8;
reg clk;
reg [1:0] addr;
logic [width-1:0] data [0:3];
reg [width-1:0] Q;
// Does SystemVerilog support continuous assignment
// of unpacked arrays? I think it does, but the LRM
// is really not clear on this.
wire [width-1:0] data_x[0:3];
assign data_x = data;
always @(posedge clk)
Q <= data_x[addr];
reg [2:0]\t idx;
initial begin
clk = 0;
data[0] = 0;
data[1] = 1;
data[2] = 2;
data[3] = 3;
addr = 0;
for (idx = 0 ; idx < 4 ; idx += 1) begin
\t clk = 0;
\t #1 addr = idx[1:0];
\t #1 clk = 1;
\t #1 if (Q !== data[addr]) begin
\t $display("FAILED -- data[%0d]==%h, Q==%h", addr, data[addr], Q);
\t $finish;
\t end
end
$display("PASSED");
end // initial begin
endmodule // main
|
module dut(input wire [7:0] i = 8\'d10, output wire [7:0] o);
assign o = i;
endmodule
module tb();
wire [7:0] result;
dut dut(.o(result));
initial begin
#1;
if (result === 10)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module task_time_arg;
reg pass;
integer result;
task test_it1;
realtime tmp;
begin
tmp = $realtime;
go_busy(tmp);
end
endtask
task test_it2;
go_busy($realtime);
endtask
task go_busy;
input delay;
integer delay;
result = delay;
endtask // go_busy
initial begin
pass = 1\'b1;
#6
test_it1;
if (result !== 6) begin
$display("Failed: testit1, expected 6, got %d", result);
pass = 1\'b0;
end
#1
test_it2;
if (result !== 7) begin
$display("Failed: testit2, expected 7, got %d", result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module connect(inout [1:0] c);
tran(c[0], c[1]);
endmodule
module top();
tri [3:0] a;
reg dir;
connect connect1(a[1:0]);
connect connect2(a[2:1]);
connect connect3(a[3:2]);
assign a[0] = dir ? 1\'bz : 1\'b0;
assign a[3] = dir ? 1\'b1 : 1\'bz;
reg pass = 1;
initial begin
dir = 1\'b0;
#1 $display("%b", a);
if (a !== 4\'b0000) pass = 0;
dir = 1\'b1;
#1 $display("%b", a);
if (a !== 4\'b1111) pass = 0;
if (pass)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
//
// Test for PR#707, NULL UDP port connections
//
primitive mux (x, s, a, b, f);
output x;
input s, a, b, f;
table
// s a b f mux
0 1 ? ? : 1 ; // ? = 0 1 x
0 0 ? ? : 0 ;
1 ? 1 ? : 1 ;
1 ? 0 ? : 0 ;
x 0 0 ? : 0 ;
x 1 1 ? : 1 ;
endtable
endprimitive
module test;
reg r1, r2, r3;
wire w1;
initial begin
\tr1 = 1\'b0;
\tr2 = 1\'b0;
\tr3 = 1\'b0;
\t// If it makes it here, the code compiled
\t$display("PASSED");
end
mux udp1(w1, r1, r2, r3, /* foo */);
endmodule
|
// Copyright 2007, Martin Whitaker.
// This code may be freely copied for any purpose.
module duplicate_names();
localparam up = 1;
generate
if (up)
begin:block1
wire [2:0] count1;
count_up counter(count1);
end
endgenerate
initial begin:block1
reg [2:0] count2;
#1 count2 = 4;
#1 count2 = 5;
#1 count2 = 6;
#1 count2 = 7;
end
endmodule
module count_up(output reg [2:0] count);
initial begin
#1 count = 0;
#1 count = 1;
#1 count = 2;
#1 count = 3;
end
endmodule
|
/*
* Copyright (c) 2014 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
`default_nettype none
module main;
class test_t;
reg [1:0] a;
reg [2:0] b;
function new (int ax, int bx);
\t begin
\t a = ax;
\t b = bx;
\t end
endfunction // new
endclass // test_t
class container_t;
test_t foo [0:3][0:7];
function new();
\t bit [3:0] idx1, idx2;
\t begin
\t for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
\t for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
\t\t foo[idx1][idx2] = new(idx1,idx2);
\t end
\t end
endfunction // new
task run();
\t bit [3:0] idx1, idx2;
\t test_t tmp;
\t foreach (foo[ia,ib]) begin
\t if (ia > 3 || ib > 7) begin
\t $display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib);
\t $finish;
\t end
\t tmp = foo[ia][ib];
\t if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin
\t $display("FAILED -- foo[%0d][%0d] == %b", ia, ib, {tmp.a, tmp.b});
\t $finish;
\t end
\t foo[ia][ib] = null;
\t end
\t for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
\t for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
\t if (foo[idx1][idx2] != null) begin
\t\t $display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2);
\t\t $finish;
\t end
\t end
endtask // run
endclass
container_t dut;
initial begin
dut = new;
dut.run;
$display("PASSED");
end
endmodule // main
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests the ability to take bit and part selects
* of parameters. This is actually not legal in Verilog, but
* Icarus Verilog supports it anyhow, as do many (most?) other
* Verilog compilers.
*/
module main;
parameter vec = 16\'b0000_1001_0111_1010;
initial begin
if (vec[0] !== 0) begin
\t $display("FAILED -- %b[0] !== 0", vec);
\t $finish;
end
if (vec[1] !== 1) begin
\t $display("FAILED -- %b[1] !== 1", vec);
\t $finish;
end
if (vec[3:1] !== 3\'b101) begin
\t $display("FAILED -- %b[3:1] !== b101", vec);
\t $finish;
end
$display("PASSED");
end
endmodule
|
module main;
parameter use_wid = 4;
reg [use_wid-1:0] d;
wire [use_wid-1:0] q;
reg\t\t clk;
defparam\t dut.wid = use_wid;
B dut (.Q(q), .D(d), .C(clk));
initial begin
clk = 0;
d = 4\'b0000;
#1 clk = 1;
#1 clk = 0;
if (q !== 4\'b0000) begin
\t $display("FAILED -- d=%b, q=%b", d, q);
\t $finish;
end
d = 4\'b1111;
#1 clk = 1;
#1 clk = 0;
if (q !== 4\'b1111) begin
\t $display("FAILED -- d=%b, q=%b", d, q);
\t $finish;
end
$display("PASSED");
end
endmodule // main
/*
* although the wid paramter is default to 3 in this module, the point
* of this test is to have the instantiating module (main) give a
* different value and have that value properly handlued in all the
* situations of this module.
*/
module B
#(parameter wid = 3)
(output [wid-1:0] Q,
input [wid-1:0] D,
input C);
// the override from main will cause this to be a width of 4.
prim U [wid-1:0] (Q, D, C);
//prim U [wid-1:0] (.Q(Q), .D(D), .C(C));
endmodule // B
module prim(output reg Q, input D, C);
always @(posedge C)
Q <= D;
endmodule // prim
|
module test;
wire [7:0] o1, o2, o3;
dummy foo(.o1(o1), .o2(o2), .o3(o3));
initial begin
#1 if (o1 !== 8\'h00) begin
\t $display("FAILED -- o1 = %b", o1);
\t $finish;
end
if (o2 !== 8\'h08) begin
\t $display("FAILED -- o2 = %b", o2);
\t $finish;
end
if (o3 !== 8\'h80) begin
\t $display("FAILED == o3 = %b", o3);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Compound ifdef (two) with interior not defined
//
`define DOUBLE
module ifdef1;
reg error ;
`ifdef DOUBLE
`ifdef NOCODE
initial
begin
#20;
error = 1;
#20;
end
`endif\t// NOCODE
`endif // DOUBLE
initial
begin
#1;
error = 0;
#40;
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
/*
* This test verifies vpiPureTransportDelay functionality
*/
`timescale 1 ns / 1 ps
module test;
reg r;
initial begin
\t$monitor("<monitor> r = ", r);
\t#0.1 r = 1\'b0;
\t#100000 $finish(0);
end
always @(r) $display("<display> r = %b @ %0t", r, $time);
endmodule
|
// `define READ read_good
module top;
reg clk;
reg dout;
reg [7:0] data;
integer lp;
always #10 clk = ~clk; // Build a clock generator.
always @(negedge clk) dout = ~dout; // Build a bit stream.
initial begin
clk = 0;
dout = 0;
@(negedge clk);
for (lp=0; lp<4; lp=lp+1) begin
#0 read_bad(data);
$display("Read(%0d) %b from the bit stream.", lp, data);
#20; // For the fun of it skip a clock.
end
#1 $finish(0);
end
// This one locks up on the third call.
task read_bad;
output [7:0] edata;
integer i;
reg [7:0] rddata;
begin
for(i=7; i>=0; i=i-1) begin
@(posedge clk);
$display(" Reading bit %0d", i);
rddata[i] = dout; // <<--- This appears to be the problem line!
end
assign edata = rddata;
end
endtask
// This one works fine.
task read_good;
output [7:0] edata;
integer i;
reg [7:0] edata;
begin
for(i=7; i>=0; i=i-1) begin
@(posedge clk);
$display(" Reading bit %0d", i);
edata[i] = dout;
end
end
endtask
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate function w/ single input
module main ();
reg [31:0] val1,val2 ;
reg error;
function [31:0] myfunc ;
input [31:0] in1 ;
myfunc = in1 ;
endfunction
initial
begin
error = 0;
val1 = myfunc(32\'h0) ;
if(val1 != 32\'h0)
begin
$display("FAILED - function3.11B - func(lit) != lit ");
error = 1;
end
val2 = 32\'h12345678 ;
val1 = myfunc(val2);
if(val1 != val2)
begin
$display("FAILED - function3.11B - func(reg var) != reg var ");
error = 1;
end
if(myfunc(32\'h10101010) != 32\'h10101010)
begin
$display("FAILED - function3.11B - if(func(reg var) != reg var) ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always @ (event_expression) ;
// D:
module main ;
reg [3:0] value1 ;
initial
\tbegin
# 10 ;
value1 = 4\'h5;
# 10 ;
$display("PASSED\
");
\t $finish;
end
always @ (value1) ;
endmodule
|
`begin_keywords "1364-2005"
/*
* This is a general recreation of the VHDL ieee.math_real package.
*/
// Constants for use below and for general reference
// TODO: Bring it out to 12 (or more???) places beyond the decimal?
`define MATH_E 2.7182818284
`define MATH_1_OVER_E 0.3678794411
`define MATH_PI 3.1415926536
`define MATH_2_PI 6.2831853071
`define MATH_1_OVER_PI 0.3183098861
`define MATH_PI_OVER_2 1.5707963267
`define MATH_PI_OVER_3 1.0471975511
`define MATH_PI_OVER_4 0.7853981633
`define MATH_3_PI_OVER_2 4.7123889803
`define MATH_LOG_OF_2 0.6931471805
`define MATH_LOG_OF_10 2.3025850929
`define MATH_LOG2_OF_E 1.4426950408
`define MATH_LOG10_OF_E 0.4342944819
`define MATH_SQRT_2 1.4142135623
`define MATH_1_OVER_SQRT_2 0.7071067811
`define MATH_SQRT_PI 1.7724538509
`define MATH_DEG_TO_RAD 0.0174532925
`define MATH_RAD_TO_DEG 57.2957795130
// The number of iterations to do for the Taylor series approximations
`define EXPLOG_ITERATIONS 50
`define COS_ITERATIONS 13
module math ;
/* Conversion Routines */
// Return the sign of a particular number.
function real sign ;
input real x ;
begin
sign = x < 0.0 ? 1.0 : 0.0 ;
end
endfunction
// Return the trunc function of a number
function real trunc ;
input real x ;
begin
trunc = x - mod(x,1.0) ;
end
endfunction
// Return the ceiling function of a number.
function real ceil ;
input real x ;
real retval ;
begin
retval = mod(x,1.0) ;
if( retval != 0.0 && x > 0.0 ) retval = x+1.0 ;
else retval = x ;
ceil = trunc(retval) ;
end
endfunction
// Return the floor function of a number
function real floor ;
input real x ;
real retval ;
begin
retval = mod(x,1.0) ;
if( retval != 0.0 && x < 0.0 ) retval = x - 1.0 ;
else retval = x ;
floor = trunc(retval) ;
end
endfunction
// Return the round function of a number
function real round ;
input real x ;
real retval ;
begin
retval = x > 0.0 ? x + 0.5 : x - 0.5 ;
round = trunc(retval) ;
end
endfunction
// Return the fractional remainder of (x mod m)
function real mod ;
input real x ;
input real m ;
real retval ;
begin
retval = x ;
if( retval > m ) begin
while( retval > m ) begin
retval = retval - m ;
end
end
else begin
while( retval < -m ) begin
retval = retval + m ;
end
end
mod = retval ;
end
endfunction
// Return the max between two real numbers
function real realmax ;
input real x ;
input real y ;
begin
realmax = x > y ? x : y ;
end
endfunction
// Return the min between two real numbers
function real realmin ;
input real x ;
input real y ;
begin
realmin = x > y ? y : x ;
end
endfunction
/* Random Numbers */
// Generate Gaussian distributed variables
function real gaussian ;
input real mean ;
input real var ;
real u1, u2, v1, v2, s ;
begin
s = 1.0 ;
while( s >= 1.0 ) begin
// Two random numbers between 0 and 1
u1 = $random/pow(2.0,32) ;
u2 = $random/pow(2.0,32) ;
// Adjust to be between -1,1
v1 = 2.0*u1-1.0 ;
v2 = 2.0*u2-1.0 ;
// Polar mag squared
s = v1*v1 + v2*v2 ;
end
gaussian = mean + sqrt(-2.0*log(s)/s) * v1 * sqrt(var) ;
// gaussian2 = mean + sqrt(-2*log(s)/s)*v2 * sqrt(var) ;
end
endfunction
/* Roots and Log Functions */
// Return the square root of a number
function real sqrt ;
input real x ;
real retval ;
begin
// if( x == 0.0 ) retval = 0.0 ;
// else retval = powr(x,0.5) ;
// sqrt = retval ;
sqrt = (x == 0.0) ? 0.0 : powr(x,0.5) ;
end
endfunction
// Return the cube root of a number
function real cbrt ;
input real x ;
real retval ;
begin
// if( x == 0.0 ) retval = 0.0 ;
// else retval = powr(x,1.0/3.0) ;
// cbrt = retval ;
cbrt = (x == 0.0) ? 0.0 : powr(x,1.0/3.0) ;
end
endfunction
// Return the absolute value of a real value
function real abs ;
input real x ;
begin
abs = (x > 0.0) ? x : -x ;
end
endfunction
// Return a real value raised to an integer power
function real pow ;
input real b ;
input integer x ;
integer i ;
integer absx ;
real retval ;
begin
retval = 1.0 ;
absx = abs(x) ;
for( i = 0 ; i < absx ; i = i+1 ) begin
retval = b*retval ;
end
pow = x < 0 ? (1.0/retval) : retval ;
end
endfunction
// Return a real value raised to a real power
function real powr ;
input real b ;
input real x ;
begin
powr = exp(x*log(b)) ;
end
endfunction
// Return the evaluation of e^x where e is the natural logarithm base
// NOTE: This is the Taylor series expansion of e^x
function real exp ;
input real x ;
real retval ;
integer i ;
real nm1_fact ;
real powm1 ;
begin
nm1_fact = 1.0 ;
powm1 = 1.0 ;
retval = 1.0 ;
for( i = 1 ; i < `EXPLOG_ITERATIONS ; i = i + 1 ) begin
powm1 = x*powm1 ;
nm1_fact = nm1_fact * i ;
retval = retval + powm1/nm1_fact ;
end
exp = retval ;
end
endfunction
// Return the evaluation log(x)
function real log ;
input real x ;
integer i ;
real whole ;
real xm1oxp1 ;
real retval ;
real newx ;
begin
retval = 0.0 ;
whole = 0.0 ;
newx = x ;
while( newx > `MATH_E ) begin
whole = whole + 1.0 ;
newx = newx / `MATH_E ;
end
newx = x/pow(`MATH_E,whole) ;
xm1oxp1 = (newx-1.0)/(newx+1.0) ;
for( i = 0 ; i < `EXPLOG_ITERATIONS ; i = i + 1 ) begin
retval = retval + pow(xm1oxp1,2*i+1)/(2.0*i+1.0) ;
end
log = whole+2.0*retval ;
end
endfunction
// Return the evaluation ln(x) (same as log(x))
function real ln ;
input real x ;
begin
ln = log(x) ;
end
endfunction
// Return the evaluation log_2(x)
function real log2 ;
input real x ;
begin
log2 = log(x)/`MATH_LOG_OF_2 ;
end
endfunction
function real log10 ;
input real x ;
begin
log10 = log(x)/`MATH_LOG_OF_10 ;
end
endfunction
function real log_base ;
input real x ;
input real b ;
begin
log_base = log(x)/log(b) ;
end
endfunction
/* Trigonometric Functions */
// Internal function to reduce a value to be between [-pi:pi]
function real reduce ;
input real x ;
real retval ;
begin
retval = x ;
if( x > `MATH_PI ) begin
while( retval >= `MATH_PI ) begin
retval = retval - `MATH_PI ;
end
end
else begin
while( retval <= -`MATH_PI ) begin
retval = retval + `MATH_PI ;
end
end
reduce = retval ;
end
endfunction
// Return the cos of a number in radians
function real cos ;
input real x ;
integer i ;
integer sign ;
real newx ;
real retval ;
real xsqnm1 ;
real twonm1fact ;
begin
newx = reduce(x) ;
xsqnm1 = 1.0 ;
twonm1fact = 1.0 ;
retval = 1.0 ;
for( i = 1 ; i < `COS_ITERATIONS ; i = i + 1 ) begin
sign = -2*(i % 2)+1 ;
xsqnm1 = xsqnm1*newx*newx ;
twonm1fact = twonm1fact * (2.0*i) * (2.0*i-1.0) ;
retval = retval + sign*(xsqnm1/twonm1fact) ;
end
cos = retval ;
end
endfunction
// Return the sin of a number in radians
function real sin ;
input real x ;
begin
sin = cos(x - `MATH_PI_OVER_2) ;
end
endfunction
// Return the tan of a number in radians
function real tan ;
input real x ;
begin
tan = sin(x) / cos(x) ;
end
endfunction
// Return the arcsin in radians of a number
function real arcsin ;
input real x ;
begin
arcsin = 2.0*arctan(x/(1.0+sqrt(1.0-x*x))) ;
end
endfunction
// Return the arccos in radians of a number
function real arccos ;
input real x ;
begin
arccos = `MATH_PI_OVER_2-arcsin(x) ;
end
endfunction
// Return the arctan in radians of a number
// TODO: Make sure this REALLY does work as it is supposed to!
function real arctan ;
input real x ;
real retval ;
real y ;
real newx ;
real twoiotwoip1 ;
integer i ;
integer mult ;
begin
retval = 1.0 ;
twoiotwoip1 = 1.0 ;
mult = 1 ;
newx = abs(x) ;
while( newx > 1.0 ) begin
mult = mult*2 ;
newx = newx/(1.0+sqrt(1.0+newx*newx)) ;
end
y = 1.0 ;
for( i = 1 ; i < 2*`COS_ITERATIONS ; i = i + 1 ) begin
y = y*((newx*newx)/(1+newx*newx)) ;
twoiotwoip1 = twoiotwoip1 * (2.0*i)/(2.0*i+1.0) ;
retval = retval + twoiotwoip1*y ;
end
retval = retval * (newx/(1+newx*newx)) ;
retval = retval * mult ;
arctan = (x > 0.0) ? retval : -retval ;
end
endfunction
// Return the arctan in radians of a ratio x/y
// TODO: Test to make sure this works as it is supposed to!
function real arctan_xy ;
input real x ;
input real y ;
real retval ;
begin
retval = 0.0 ;
if( x < 0.0 ) retval = `MATH_PI - arctan(-abs(y)/x) ;
else if( x > 0.0 ) retval = arctan(abs(y)/x) ;
else if( x == 0.0 ) retval = `MATH_PI_OVER_2 ;
arctan_xy = (y < 0.0) ? -retval : retval ;
end
endfunction
/* Hyperbolic Functions */
// Return the sinh of a number
function real sinh ;
input real x ;
begin
sinh = (exp(x) - exp(-x))/2.0 ;
end
endfunction
// Return the cosh of a number
function real cosh ;
input real x ;
begin
cosh = (exp(x) + exp(-x))/2.0 ;
end
endfunction
// Return the tanh of a number
function real tanh ;
input real x ;
real e2x ;
begin
e2x = exp(2.0*x) ;
tanh = (e2x+1.0)/(e2x-1.0) ;
end
endfunction
// Return the arcsinh of a number
function real arcsinh ;
input real x ;
begin
arcsinh = log(x+sqrt(x*x+1.0)) ;
end
endfunction
// Return the arccosh of a number
function real arccosh ;
input real x ;
begin
arccosh = ln(x+sqrt(x*x-1.0)) ;
end
endfunction
// Return the arctanh of a number
function real arctanh ;
input real x ;
begin
arctanh = 0.5*ln((1.0+x)/(1.0-x)) ;
end
endfunction
initial begin
$display( "cos(MATH_PI_OVER_3): %f", cos(`MATH_PI_OVER_3) ) ;
$display( "sin(MATH_PI_OVER_3): %f", sin(`MATH_PI_OVER_3) ) ;
$display( "sign(-10): %f", sign(-10) ) ;
$display( "realmax(MATH_PI,MATH_E): %f", realmax(`MATH_PI,`MATH_E) ) ;
$display( "realmin(MATH_PI,MATH_E): %f", realmin(`MATH_PI,`MATH_E) ) ;
$display( "mod(MATH_PI,MATH_E): %f", mod(`MATH_PI,`MATH_E) ) ;
$display( "ceil(-MATH_PI): %f", ceil(-`MATH_PI) ) ;
$display( "ceil(4.0): %f", ceil(4.0) ) ;
$display( "ceil(3.99999999999999): %f", ceil(3.99999999999999) ) ;
$display( "pow(MATH_PI,2): %f", pow(`MATH_PI,2) ) ;
$display( "gaussian(1.0,1.0): %f", gaussian(1.0,1.0) ) ;
$display( "round(MATH_PI): %f", round(`MATH_PI) ) ;
$display( "trunc(-MATH_PI): %f", trunc(-`MATH_PI) ) ;
$display( "ceil(-MATH_PI): %f", ceil(-`MATH_PI) ) ;
$display( "floor(MATH_PI): %f", floor(`MATH_PI) ) ;
$display( "round(e): %f", round(`MATH_E)) ;
$display( "ceil(-e): %f", ceil(-`MATH_E)) ;
$display( "exp(MATH_PI): %f", exp(`MATH_PI) ) ;
$display( "log2(MATH_PI): %f", log2(`MATH_PI) ) ;
$display( "log_base(pow(2,32),2): %f", log_base(pow(2,32),2) ) ;
$display( "ln(0.1): %f", log(0.1) ) ;
$display( "cbrt(7): %f", cbrt(7) ) ;
$display( "cos(%s): %f", ``MATH_2_PI, cos(20*`MATH_2_PI) ) ;
$display( "sin(-%s): %f", ``MATH_2_PI, sin(-50*`MATH_2_PI) ) ;
$display( "sinh(%s): %f", ``MATH_E, sinh(`MATH_E) ) ;
$display( "cosh(%s): %f", ``MATH_2_PI, cosh(`MATH_2_PI) ) ;
$display( "arctan_xy(-4,3): %f", arctan_xy(-4,3) ) ;
$display( "arctan(MATH_PI): %f", arctan(`MATH_PI) ) ;
$display( "arctan(-MATH_E/2): %f", arctan(-`MATH_E/2) ) ;
$display( "arctan(MATH_PI_OVER_2): %f", arctan(`MATH_PI_OVER_2) ) ;
$display( "arctan(1/7) = %f", arctan(1.0/7.0) ) ;
$display( "arctan(3/79) = %f", arctan(3.0/79.0) ) ;
$display( "pi/4 ?= %f", 5*arctan(1.0/7.0)+2*arctan(3.0/79.0) ) ;
$display( "arcsin(1.0): %f", arcsin(1.0) ) ;
$display( "cos(pi/2): %f", cos(`MATH_PI_OVER_2)) ;
$display( "arccos(cos(pi/2)): %f", arccos(cos(`MATH_PI_OVER_2)) ) ;
end
endmodule
`end_keywords
|
/*
* blocksyn1.v
* This tests synthesis where statements in a block override previous
* statements in a block and also uses other previous statements in the
* block. Note in this example that the flag assignment is completely
* overruled by the conditional that is directly after it.
*/
module main;
reg [1:0] out;
reg\t flag;
reg [1:0] sel;
(* ivl_synthesis_on, ivl_combinational *)
always @*
begin
\tcase (sel)
\t 2\'b00: out = 2\'b11;
\t 2\'b01: out = 2\'b10;
\t 2\'b10: out = 2\'b01;
\t 2\'b11: out = 2\'b00;
\tendcase // case(sel)
\t// This flag is completely overridden by the contintional, so
\t// the synthesizer should drop it.
\tflag = 1\'b0;
\tif (out == 2\'b00)
\t flag = 1\'b1;
\telse
\t flag = 1\'b0;
end
reg [2:0] idx;
reg\t test;
(* ivl_synthesis_off *)
initial begin
for (idx = 0 ; idx < 7 ; idx = idx + 1) begin
\t sel = idx[1:0];
\t #1 if (out !== ~sel) begin
\t $display("FAILED -- sel=%b, out=%b, flag=%b", sel, out, flag);
\t $finish;
\t end
\t test = (out == 2\'b00)? 1\'b1 : 1\'b0;
\t if (test !== flag) begin
\t $display("FAILED -- test=%b, sel=%b, out=%b, flag=%b",
\t\t test, sel, out, flag);
\t $finish;
\t end
end // for (idx = 0 ; idx < 7 ; idx = idx + 1)
$display("PASSED");
end // initial begin
endmodule // main
|
/*
* This tests the latching of an output that isn\'t really an output,
* but an intermediate symbol that is only used in some clauses.
*/
module main;
reg [15:0] out, a;
reg [7:0] b;
reg\t cy;
reg\t with_carry;
(* ivl_combinational *)
always @(with_carry, a, b, cy)
if (with_carry) begin
\t{cy, out[7:0]} = {1\'b0, a[7:0]} + {1\'b0, b[7:0]};
\tout[15:8] = a[15:8] + {7\'b0, cy};
end else begin
\tout = a + {8\'h00, b};
end
(* ivl_synthesis_off *)
initial begin
a = 16\'h00fe;
b = 8\'h00;
with_carry = 0;
#1 if (out !== 16\'h00fe) begin
\t $display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
\t $finish;
end
with_carry = 1;
#1 if (out !== 16\'h00fe) begin
\t $display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
\t $finish;
end
b = 2;
#1 if (out !== 16\'h0100) begin
\t $display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
\t $finish;
end
with_carry = 0;
#1 if (out !== 16\'h0100) begin
\t $display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module test;
reg [4:0] i;
reg [7:0] j, k, l;
initial
main;
task main;
begin
\t i = 5\'h14;
\t j = $signed(i); // works
\t k = $signed(5\'h14); // doesn\'t work
\t l = 5\'sh14; // works
\t $display("i, j, k, l: \'%b\', \'%b\', \'%b\', \'%b\'", i, j, k, l);
end
endtask
endmodule
|
module test();
parameter signed snv1 = 4\'d1;
parameter signed [2:0] s3v1 = 4\'d1;
parameter signed [3:0] s4v1 = 4\'d1;
parameter signed [4:0] s5v1 = 4\'d1;
parameter signed snv15 = 4\'d15;
parameter signed [2:0] s3v15 = 4\'d15;
parameter signed [3:0] s4v15 = 4\'d15;
parameter signed [4:0] s5v15 = 4\'d15;
parameter signed snvm1 = -4\'sd1;
parameter signed [2:0] s3vm1 = -4\'sd1;
parameter signed [3:0] s4vm1 = -4\'sd1;
parameter signed [4:0] s5vm1 = -4\'sd1;
parameter signed snrm1 = -1.0;
parameter signed [2:0] s3rm1 = -1.0;
parameter signed [3:0] s4rm1 = -1.0;
parameter signed [4:0] s5rm1 = -1.0;
parameter nnv1 = 4\'d1;
parameter [2:0] u3v1 = 4\'d1;
parameter [3:0] u4v1 = 4\'d1;
parameter [4:0] u5v1 = 4\'d1;
parameter nnv15 = 4\'d15;
parameter [2:0] u3v15 = 4\'d15;
parameter [3:0] u4v15 = 4\'d15;
parameter [4:0] u5v15 = 4\'d15;
parameter nnvm1 = -4\'sd1;
parameter [2:0] u3vm1 = -4\'sd1;
parameter [3:0] u4vm1 = -4\'sd1;
parameter [4:0] u5vm1 = -4\'sd1;
parameter nnrm1 = -1.0;
parameter [2:0] u3rm1 = -1.0;
parameter [3:0] u4rm1 = -1.0;
parameter [4:0] u5rm1 = -1.0;
reg fail = 0;
reg match;
initial begin
match = ($bits(snv1) == 4) && (snv1 === 1);
$display("snv1 : %2d (%0d`b%b) %c", snv1, $bits(snv1), snv1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s3v1) == 3) && (s3v1 === 1);
$display("s3v1 : %2d (%0d`b%b) %c", s3v1 , $bits(s3v1), s3v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s4v1) == 4) && (s4v1 === 1);
$display("s4v1 : %2d (%0d`b%b) %c", s4v1 , $bits(s4v1), s4v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s5v1) == 5) && (s5v1 === 1);
$display("s5v1 : %2d (%0d`b%b) %c", s5v1 , $bits(s5v1), s5v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(snv15) == 4) && (snv15 === -1);
$display("snv15 : %2d (%0d`b%b) %c", snv15, $bits(snv15), snv15, match ? " " : "*");
fail = fail || !match;
match = ($bits(s3v15) == 3) && (s3v15 === -1);
$display("s3v15 : %2d (%0d`b%b) %c", s3v15, $bits(s3v15), s3v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(s4v15) == 4) && (s4v15 === -1);
$display("s4v15 : %2d (%0d`b%b) %c", s4v15, $bits(s4v15), s4v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(s5v15) == 5) && (s5v15 === 15);
$display("s5v15 : %2d (%0d`b%b) %c", s5v15, $bits(s5v15), s5v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(snvm1) == 4) && (snvm1 === -1);
$display("snvm1 : %2d (%0d`b%b) %c", snvm1, $bits(snvm1), snvm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s3vm1) == 3) && (s3vm1 === -1);
$display("s3vm1 : %2d (%0d`b%b) %c", s3vm1, $bits(s3vm1), s3vm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s4vm1) == 4) && (s4vm1 === -1);
$display("s4vm1 : %2d (%0d`b%b) %c", s4vm1, $bits(s4vm1), s4vm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s5vm1) == 5) && (s5vm1 === -1);
$display("s5vm1 : %2d (%0d`b%b) %c", s5vm1, $bits(s5vm1), s5vm1, match ? " " : "*");
fail = fail || !match;
match = (snrm1 == -1);
$display("snrm1 : %4.1f %c", snrm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s3rm1) == 3) && (s3rm1 === -1);
$display("s3rm1 : %2d (%0d`b%b) %c", s3rm1, $bits(s3rm1), s3rm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s4rm1) == 4) && (s4rm1 === -1);
$display("s4rm1 : %2d (%0d`b%b) %c", s4rm1, $bits(s4rm1), s4rm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s5rm1) == 5) && (s5rm1 === -1);
$display("s5rm1 : %2d (%0d`b%b) %c", s5rm1, $bits(s5rm1), s5rm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(nnv1) == 4) && (nnv1 === 1);
$display("nnv1 : %2d (%0d`b%b) %c", nnv1, $bits(nnv1), nnv1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u3v1) == 3) && (u3v1 === 1);
$display("u3v1 : %2d (%0d`b%b) %c", u3v1 , $bits(u3v1), u3v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u4v1) == 4) && (u4v1 === 1);
$display("u4v1 : %2d (%0d`b%b) %c", u4v1 , $bits(u4v1), u4v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u5v1) == 5) && (u5v1 === 1);
$display("u5v1 : %2d (%0d`b%b) %c", u5v1 , $bits(u5v1), u5v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(nnv15) == 4) && (nnv15 === 15);
$display("nnv15 : %2d (%0d`b%b) %c", nnv15, $bits(nnv15), nnv15, match ? " " : "*");
fail = fail || !match;
match = ($bits(u3v15) == 3) && (u3v15 === 7);
$display("u3v15 : %2d (%0d`b%b) %c", u3v15, $bits(u3v15), u3v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(u4v15) == 4) && (u4v15 === 15);
$display("u4v15 : %2d (%0d`b%b) %c", u4v15, $bits(u4v15), u4v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(u5v15) == 5) && (u5v15 === 15);
$display("u5v15 : %2d (%0d`b%b) %c", u5v15, $bits(u5v15), u5v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(nnvm1) == 4) && (nnvm1 === -1);
$display("nnvm1 : %2d (%0d`b%b) %c", nnvm1, $bits(nnvm1), nnvm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u3vm1) == 3) && (u3vm1 === 7);
$display("u3vm1 : %2d (%0d`b%b) %c", u3vm1, $bits(u3vm1), u3vm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u4vm1) == 4) && (u4vm1 === 15);
$display("u4vm1 : %2d (%0d`b%b) %c", u4vm1, $bits(u4vm1), u4vm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u5vm1) == 5) && (u5vm1 === 31);
$display("u5vm1 : %2d (%0d`b%b) %c", u5vm1, $bits(u5vm1), u5vm1, match ? " " : "*");
fail = fail || !match;
match = (nnrm1 == -1.0);
$display("nnrm1 : %4.1f %c", nnrm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u3rm1) == 3) && (u3rm1 === 7);
$display("u3rm1 : %2d (%0d`b%b) %c", u3rm1, $bits(u3rm1), u3rm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u4rm1) == 4) && (u4rm1 === 15);
$display("u4rm1 : %2d (%0d`b%b) %c", u4rm1, $bits(u4rm1), u4rm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u5rm1) == 5) && (u5rm1 === 31);
$display("u5rm1 : %2d (%0d`b%b) %c", u5rm1, $bits(u5rm1), u5rm1, match ? " " : "*");
fail = fail || !match;
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Regression test for br962 - based on test case provided in bug report
module qtest;
parameter width = 32;
parameter depth = 32;
reg [width-1:0] values[$];
reg [$clog2(depth)+width-1:0] sum1;
reg [$clog2(depth)+width-1:0] sum2;
task new_sample;
input [width-1:0] data;
int i;
begin
reg [width-1:0] popped;
if (values.size >= depth)
\tsum1 = sum1 - values.pop_back();
sum1 = sum1 + data;
values.push_front(data);
sum2 = 0;
for (i = 0; i < values.size; i++) begin
sum2 = sum2 + values[i];
end
$display("sum1 = %d sum2 = %d", sum1, sum2);
if (sum1 !== sum2) begin
$display("FAILED");
$finish;
end
end
endtask
initial begin
sum1 = 0;
repeat (2*depth) new_sample({$random});
$display("PASSED");
end
endmodule
|
// Check that all sorts of enum dimension declarations are handled correctly and
// do not cause an assert or segfault.
module test;
// These are invalid
enum logic [$] {
\tA
} a;
enum logic [] {
B
} b;
enum logic [-1] {
\tC
} c;
enum logic [0] {
\tD
} d;
enum logic [1:0][3:0] {
\tE
} e;
// These are valid
enum logic [0:2] {
\tF
} f;
enum logic [2:0] {
\tG
} g;
enum logic [-1:-2] {
\tH
} h;
// These are valid as an extension in iverilog
enum logic [16] {
\tI
} i;
int x;
endmodule
|
module test();
a a_(
.b_buf(b),
.b (b)
);
endmodule // test
module a(b, b_buf);
input b, b_buf;
endmodule // a_
|
// Copyright (c) 2014 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for \'range, \'reverse_range, \'left and \'right attributes in VHDL.
module range_test;
range_entity dut();
initial begin
int i;
#1; // wait for signal assignments
if(dut.left_asc !== 2)
begin
$display("FAILED: left_asc should be %2d but is %2d", 2, dut.left_asc);
$finish();
end
if(dut.right_asc !== 4)
begin
$display("FAILED: right_asc should be %2d but is %2d", 2, dut.right_asc);
$finish();
end
if(dut.left_dsc !== 9)
begin
$display("FAILED: left_dsc should be %2d but is %2d", 2, dut.left_dsc);
$finish();
end
if(dut.right_dsc !== 3)
begin
$display("FAILED: right_dsc should be %2d but is %2d", 2, dut.right_dsc);
$finish();
end
if(dut.pow_left !== 16)
begin
$display("FAILED: pow_left should be %2d but is %2d", 16, dut.pow_left);
$finish();
end
if(dut.rem_left !== 2)
begin
$display("FAILED: rem_left should be %2d but is %2d", 2, dut.rem_left);
$finish();
end
for(i = $left(dut.ascending); i <= $right(dut.ascending); i++)
begin
if(2*i !== dut.ascending[i])
begin
$display("FAILED: ascending[%2d] should be %2d but is %2d", i, 2*i, dut.ascending[i]);
$finish();
end
end
for(i = $right(dut.descending); i <= $left(dut.descending); i++)
begin
if(3*i !== dut.descending[i])
begin
$display("FAILED: descending[%2d] should be %2d but is %2d", i, 3*i, dut.descending[i]);
$finish();
end
end
for(i = $left(dut.ascending_rev); i <= $right(dut.ascending_rev); i++)
begin
if(4*i !== dut.ascending_rev[i])
begin
$display("FAILED: ascending_rev[%2d] should be %2d but is %2d", i, 4*i, dut.ascending_rev[i]);
$finish();
end
end
for(i = $right(dut.descending_rev); i <= $left(dut.descending_rev); i++)
begin
if(5*i !== dut.descending_rev[i])
begin
$display("FAILED: descending_rev[%2d] should be %2d but is %2d", i, 5*i, dut.descending_rev[i]);
$finish();
end
end
$display("PASSED");
end
endmodule
|
// Regression test for GitHub issue 15 : Icarus does undef propagation of
// const adds incorrectly
module bug();
wire [3:0] y;
assign y = 4\'bxx00 + 2\'b00;
initial begin
#0 $display("%b", y);
if (y === 4\'bxxxx)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module main;
parameter WID = 4;
parameter SWID = 2;
reg [WID-1:0] D;
reg [SWID-1:0] S;
wire\t\tQ;
muxN dut(.\\D[3] (D[3]), .\\D[2] (D[2]), .\\D[1] (D[1]), .\\D[0] (D[0]),
\t .\\S[1] (S[1]), .\\S[0] (S[0]),
\t .Q(Q));
integer\t idx, sdx;
initial begin
for (idx = 0 ; idx < 50 ; idx += 1) begin
\t D = $random;
\t for (sdx = 0 ; sdx < (1<<SWID) ; sdx = sdx+1) begin
\t S = sdx[SWID-1:0];
\t #1 ;
\t if (Q !== D[S]) begin
\t $display("FAILED = D=%b, S=%0d, Q=%b", D, S, Q);
\t $finish;
\t end
\t end
end // for (idx = 0 ; idx < 50 ; idx += 1)
$display("PASSED");
end // initial begin
endmodule // main
|
module main;
bit pass;
bit signed [7:0] s8[];
bit [7:0] u8[];
string res, fmt;
initial begin
pass = 1\'b1;
s8 = new[2];
u8 = new[2];
s8[0] = -1;
u8[0] = -1;
fmt = "%0d";
$display(fmt, s8[0]);
$sformat(res, fmt, s8[0]);
if (res != "-1") begin
$display("Failed: expected \'-1\', got \'%s\'", res);
pass = 1\'b0;
end
$display(fmt, u8[0]);
$swrite(res, u8[0]);
if (res != "255") begin
$display("Failed: expected \'255\', got \'%s\'", res);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule // main
|
module top;
reg a;
reg q, d;
event foo;
real rl;
int ar [];
int start = 0;
int stop = 1;
int step = 1;
int done = 0;
task a_task;
real trl;
event tevt;
reg tvr;
$display("user task");
endtask
always_comb begin: blk_name
event int1, int2;
real intrl;
q <= d;
-> foo;
rl = 0.0;
rl <= 1.0;
ar = new [2];
for (int idx = start; idx < stop; idx += step) $display("For: %0d", idx);
for (int idx = 0; done; idx = done + 1) $display("Should never run!");
for (int idx = 0; idx; done = done + 1) $display("Should never run!");
for (int idx = 0; idx; {done, idx} = done + 1) $display("Should never run!");
for (int idx = 0; idx; idx <<= 1) $display("Should never run!");
for (int idx = 0; idx; idx = idx << 1) $display("Should never run!");
$display("array size: %0d", ar.size());
ar.delete();
$display("array size: %0d", ar.size());
a_task;
assign a = 1\'b0;
deassign a;
do $display("do/while");
while (a);
force a = 1\'b1;
release a;
while(a) begin
$display("while");
a = 1\'b0;
end
repeat(2) $display("repeat");
disable out_name;
forever begin
$display("forever");
disable blk_name; // This one should not generate a warning
end
end
initial #1 $display("Expect compile warnings!\
PASSED");
initial begin: out_name
#2 $display("FAILED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue <= @ event_identifier constant
// D: There is a dependency here between this and event keyword and ->
module main ;
reg [3:0] value1 ;
event event_ident ;
initial
begin
# 5 -> event_ident ;
end
initial
begin
if(value1 !== 4\'bxxxx)
\t$display("FAILED - always reg_lvalue <= @ event_identifier constant\
");
#10 ;
if(value1 != 4\'h5)
\t$display("FAILED - always reg_lvalue <= @ event_identifier constant\
");
else
begin
$display("PASSED\
");
$finish ;
end
end
always value1 <= @ event_ident 4\'h5;
endmodule
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test is inspired by (and tests) PR#12. The interesting aspect of
* this is the multiply in the parameter passed to module foo instance yak.
*/
`define ONE 1
`define TWO 2
module foo(in,out);
parameter blah = 2;
input in;
output out;
initial begin
if (blah != 4) begin
\t $display("FAILED -- parameter override of blah failed: %d", blah);
\t $finish;
end
$display("PASSED");
end
endmodule
module bar;
\tfoo #(`ONE * 2 + `TWO) yak (,);
endmodule
|
module test;
logic [7:0] i, x[], y[], z[];
initial begin
x = new [4];
for (i = 0; i < 4; i = i + 1) x[i] = 1 + i;
y = x;
z = new [4](x);
for (i = 0; i < 4; i = i + 1) y[i] = 4 - i;
for (i = 0; i < 4; i = i + 1) z[i] = 8 - i;
// Expected output:
// 1 2 3 4
// 4 3 2 1
// 8 7 6 5
$display(x[0],,x[1],,x[2],,x[3]);
$display(y[0],,y[1],,y[2],,y[3]);
$display(z[0],,z[1],,z[2],,z[3]);
end
endmodule
|
// Check that it is possible to copy an empty queue.
module test;
typedef int T[$];
initial begin
T q1;
T q2;
q1 = \'{1, 2, 3};
q1 = q2;
if (q1.size() == 0 && q2.size() == 0) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module top;
function automatic [2:1] f1(input [3:0] i);
begin
f1[0] = i[0];
f1[1] = i[1];
f1[2] = i[2];
f1[3] = i[3];
end
endfunction
function automatic [3:0] f2(input [2:1] i);
begin
f2[0] = i[0];
f2[1] = i[1];
f2[2] = i[2];
f2[3] = i[3];
end
endfunction
function automatic [2:1] f3(input [3:0] i);
begin
f3[1:0] = i[1:0];
f3[3:2] = i[3:2];
end
endfunction
function automatic [3:0] f4(input [2:1] i);
begin
f4[1:0] = i[1:0];
f4[3:2] = i[3:2];
end
endfunction
function automatic [2:1] f5(input [3:0] i);
reg [2:1] tmp;
begin
tmp[3:0] = 4\'b0000;
tmp[3:0] |= i[3:0];
f5 = tmp;
end
endfunction
function automatic [3:0] f6(input [2:1] i);
reg [3:0] tmp;
begin
tmp[3:0] = 4\'b0000;
tmp[3:0] |= i[3:0];
f6 = tmp;
end
endfunction
localparam C1 = f1(4\'b0011);
localparam C2 = f2(2\'b01);
localparam C3 = f3(4\'b0011);
localparam C4 = f4(2\'b01);
localparam C5 = f5(4\'b0011);
localparam C6 = f6(2\'b01);
initial begin
$display("C1 %b", C1);
$display("C2 %b", C2);
$display("C3 %b", C3);
$display("C4 %b", C4);
$display("C5 %b", C5);
$display("C6 %b", C6);
end
endmodule
|
/*
* Exhaustive check of all the compare results.
*/
module main;
wire out;
reg [7:0] A, B;
ge8 dut(.out(out), .A(A), .B(B));
reg\t error = 0;
integer adx, bdx;
initial begin
A = 0;
B = 0;
#1 $display("%b >= %b: %b", A, B, out);
for (adx = 0 ; adx < 256 ; adx = adx + 1) begin
\t A = adx;
\t for (bdx = 0 ; bdx < 256 ; bdx = bdx + 1) begin
\t B = bdx;
\t #1 $write("%b >= %b: %b", A, B, out);
\t if (out === 1) begin
\t if (A < B) begin
\t\t $display(" ERROR");
\t\t error = 1;
\t end else begin
\t\t $display(" OK");
\t end
\t end else if (out === 0) begin
\t if (A < B) begin
\t\t $display(" OK");
\t end else begin
\t\t $display(" ERROR");
\t\t error = 1;
\t end
\t end else begin
\t $display(" ERROR");
\t error = 1;
\t end // else: !if(out === 0)
\t end // for (bdx = 0 ; bdx < 256 ; bdx += 1)
end // for (adx = 0 ; adx < 256 ; adx = adx + 1)
if (error == 0)
\t$display("PASSED");
else
\t$display("FAILED");
end // initial begin
endmodule // main
|
/*
* Copyright (c) 2000 Chris Lattner
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test;
reg [3:0] val, y;
initial begin
val = 2;
y = !{!val};
if (y !== 4\'b0001) begin
\t $display("FAILED -- !!4\'b%b --> 4\'b%b", val, y);
\t $finish;
end
$display("PASSED");
end
endmodule
|
/*
* This module demonstrates the ability to use a defparam to control
* the instantation of an instance array, and to also control
* parameter values within the instance array.
*/
module main;
localparam wid = 5;
reg [wid-1:0] clk;
dut xx (.clk(clk));
// This defparam sets the desired with of the U instance vector.
defparam main.xx.wid = wid;
// These defparams set parameters within U instances.
defparam main.xx.sub[0].U.number = 0;
defparam main.xx.sub[1].U.number = 1;
defparam main.xx.sub[2].U.number = 2;
defparam main.xx.sub[3].U.number = 3;
defparam main.xx.sub[4].U.number = 4;
initial begin
clk = 0;
#1 clk = 1;
while (clk != 0)
\t #1 clk = clk << 1;
$finish(0);
end
endmodule // main
module dut #(parameter wid = 1) (input [wid-1:0] clk);
genvar i;
for (i = 0 ; i < wid ; i = i+1) begin : sub
target U (.clk(clk[i]));
end
endmodule //
module target(input wire clk);
parameter number = 999;
always @(posedge clk)
$display("%m: number=%0d", number);
endmodule // target
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Here we have the canonical "Hello, World" program written in Verilog,
* with VPI. It uses the hello_vpi.vpi module that is compiled from
* the hello_vpi.c program also in this directory. See the
* hello_vpi.c for instructions on how to compile it.
*
* Compile this program with the command:
*
* iverilog -ohello_vpi hello_vpi.vl
*
* After churning for a little while, the program will create the output
* file "hello" which is compiled, linked and ready to run. Run this
* program like so:
*
* vvp -M. -mhello_vpi hello_vpi
*
* and the program will print the message to its output. Easy! For
* more on how to make the iverilog command work, see the iverilog
* manual page.
*/
module main();
initial
begin
$my_hello;
$finish(0);
end
endmodule
|
/*
* This demonstrates a basic dynamic array
*/
module main;
real foo[];
int idx;
initial begin
if (foo.size() != 0) begin
\t $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
\t $finish;
end
foo = new[10];
if (foo.size() != 10) begin
\t $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
\t $finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
\t foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
\t $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
\t $finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
\t $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
\t $finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
\t if (foo[idx%10] != (idx%10)) begin
\t $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]);
\t $finish;
\t end
end
foo.delete();
if (foo.size() != 0) begin
\t $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* $Id: sqrt.v,v 1.1 2003/03/30 03:54:48 stevewilliams Exp $"
*/
/*
* This module approximates the square root of an unsigned 32bit
* number. The algorithm works by doing a bit-wise binary search.
* Starting from the most significant bit, the accumulated value
* tries to put a 1 in the bit position. If that makes the square
* too big for the input, the bit is left zero, otherwise it is set
* in the result. This continues for each bit, decreasing in
* significance, until all the bits are calculated or all the
* remaining bits are zero.
*
* Since the result is an integer, this function really calculates
* value of the expression:
*
* x = floor(sqrt(y))
*
* where sqrt(y) is the exact square root of y and floor(N) is the
* largest integer <= N.
*
* For 32bit numbers, this will never run more then 16 iterations,
* which amounts to 16 clocks.
*/
module sqrt32(clk, rdy, reset, x, .y(acc));
input clk;
output rdy;
input reset;
input [31:0] x;
output [15:0] acc;
// acc holds the accumulated result, and acc2 is the accumulated
// square of the accumulated result.
reg [15:0] acc;
reg [31:0] acc2;
// Keep track of which bit I\'m working on.
reg [4:0] bitl;
wire [15:0] bit = 1 << bitl;
wire [31:0] bit2 = 1 << (bitl << 1);
// The output is ready when the bitl counter underflows.
wire rdy = bitl[4];
// guess holds the potential next values for acc, and guess2 holds
// the square of that guess. The guess2 calculation is a little bit
// subtle. The idea is that:
//
// guess2 = (acc + bit) * (acc + bit)
// = (acc * acc) + 2*acc*bit + bit*bit
// = acc2 + 2*acc*bit + bit2
// = acc2 + 2 * (acc<<bitl) + bit
//
// This works out using shifts because bit and bit2 are known to
// have only a single bit in them.
wire [15:0] guess = acc | bit;
wire [31:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
(* ivl_synthesis_on *)
always @(posedge clk or posedge reset)
if (reset) begin
\t acc = 0;
\t acc2 = 0;
\t bitl = 15;
end else begin
\t if (guess2 <= x) begin
\t acc <= guess;
\t acc2 <= guess2;
\t end
\t bitl <= bitl - 5\'d1;
end
endmodule // sqrt32
/*
* This module represents the chip packaging that we intend to
* generate. We bind pins here, and route the clock to the global
* clock buffer.
*/
module chip_root(clk, rdy, reset, x, y);
input clk;
output rdy;
input reset;
input [31:0] x;
output [15:0] y;
wire\t\t clk_int;
(* cellref="BUFG:O,I" *)
buf gbuf (clk_int, clk);
sqrt32 dut(.clk(clk_int), .reset(reset), .rdy(rdy), .x(x), .y(y));
/* Assign the clk to GCLK0, which is on pin P39. */
$attribute(clk, "PAD", "39");
// We don\'t care where the remaining pins go, so set the pin number
// to 0. This tells the implementation tools that we want a PAD,
// but we don\'t care which. Also note the use of a comma (,)
// separated list to assign pins to the bits of a vector.
$attribute(rdy, "PAD", "0");
$attribute(reset, "PAD", "0");
$attribute(x, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
$attribute(y, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
endmodule // chip_root
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Bit select of a net (a wire) using the index of a for loop.
*/
module main;
// Make a vector of bits, an array of functors in practice, and
// create a net that hooks to that array backwards.
reg [4:0] vect = 5\'b10100;
wire [4:0] tmp = { vect[0], vect[1], vect[2], vect[3], vect[4] };
reg [2:0] idx;
initial begin
#1 $display("vect=%b, tmp=%b", vect, tmp);
for (idx = 0 ; idx < 5 ; idx = idx + 1) begin
\t $display("idx=%d: vect=%b, tmp=%b", idx, vect[idx], tmp[idx]);
\t if (tmp[idx] !== vect[4-idx]) begin
\t $display("FAILED");
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
// Check that a complex base type (like a struct) of a dynamic array type gets
// evaluated in the right scope if the base type is defined in a different scope
// than the array type.
localparam A = 8;
// Use type identifier for the base to force packed array
typedef logic l;
typedef l [A-1:0] Base;
module test;
localparam A = 4;
typedef Base T[];
T x;
initial begin
x = new [1];
x[0] = 8\'hff;
if (x[0] === 8\'hff) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module top;
reg [2:-1] vec;
integer idx;
initial begin
idx = 'bx;
assign vec[idx+:1] = 1'b1;
deassign vec[idx+:1];
end
endmodule
|
module test();
real IN;
wire real OUT;
assign OUT = IN;
initial begin
#1 $peek(IN);
#0 $display("display : %f", OUT);
#1 $force(IN);
#1 $peek(IN);
#0 $display("display : %f", OUT);
#1 $release(IN);
#0 $display("display : %f", OUT);
#1 $force(IN);
#1 $peek(IN);
#0 $display("display : %f", OUT);
#1 $poke(IN);
#1 $peek(IN);
#0 $display("display : %f", OUT);
#1 $release(IN);
#0 $display("display : %f", OUT);
#1 $poke(IN);
#1 $peek(IN);
#0 $display("display : %f", OUT);
end
endmodule
|
/*
* Copyright (c) 2000 Steve Wilson ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This checks bit select from/to vectors with odd bit arrangements.
*/
module test;
reg [4:1] a;
reg [1:4] b;
integer i;
initial begin
a = 4\'b1100;
for (i = 1 ; i <= 4 ; i = i + 1)
\tb[i] = a[i];
$display("a=%b, b=%b", a, b);
if (b !== 4\'b0011) begin
\t $display("FAILED -- b == %b", b);
\t $finish;
end
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: readmemh function - Read less data than length of array
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
/* pre init the array to all zeroes. */
for(count = 0; count <= 7; count = count + 1)
array[count] = 8\'h0;
$readmemh("ivltests/readmemh1.dat",array,0,3);
for(count = 0; count <= 3; count = count + 1)
begin
if(array[count[2:0]] !== count)
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count],count);
end
end
if(array[4] !== 8\'h0)
begin
error = 1;
$display("FAILED - array[4] == %h, s/b 0",
array[count]);
end
if(error == 0)
$display("PASSED\
");
$finish ;
end
endmodule
|
module top;
initial begin
// This will fail at run time.
$fdisplay(32\'h4000_0000, "write to invalid MCD");
end
endmodule
|
// Check that it is possible to declare the data type for a real type task port
// before the direction for non-ANSI style port declarations.
module test;
task t;
real x;
input x;
if (x == 1.23) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t(1.23);
endmodule
|
module check (input unsigned [103:0] a, b, c);
wire [103:0] int_AB;
assign int_AB = a ^ b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [103:0] A, B);
parameter S = 2000;
int unsigned i;
initial begin
A = 0; B= 0;
// values with 0, 1
for (i=0; i<S; i=i+1) begin
#1 A[103:8] = {$random, $random, $random};
A[7:0] =\t$random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
end
// values with x, z
for (i=0; i<S; i=i+1) begin
#1;
A[103:8] = {$random, $random, $random};
A[7:0] =\t$random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
A[103:72] = xz_inject (A[103:72]);
A[71:40] = xz_inject (A[71:40]);
B[71:40] = xz_inject (B[71:40]);
B[39:8] = xz_inject (B[39:8]);
end
end
// injects some x, z values on 32 bits arguments
function [31:0] xz_inject (input unsigned [31:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<32; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [103:0] a, b;
wire unsigned [103:0] r;
stimulus stim (.A(a), .B(b));
xor104 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#120000;
$display("PASSED");
$finish;
end
endmodule
|
module top;
reg q, clk, d;
event foo;
always_ff @(posedge clk) begin
@foo q <= d;
end
initial $display("Expected compile failure!");
endmodule
|
program main;
function real sum_array(real array[]);
int idx;
sum_array = 0.0;
for (idx = 0 ; idx < array.size() ; idx = idx+1)
\tsum_array = sum_array + array[idx];
endfunction // sum_array
real obj[];
real foo;
initial begin
foo = sum_array(\'{});
if (foo != 0.0) begin
\t $display("FAILED -- sum of empty array returns %0d", foo);
\t $finish;
end
obj = new[3];
obj = \'{1,2,3};
foo = sum_array(obj);
if (foo != 6.0) begin
\t $display("FAILED -- sum of \'{%f,%f,%f} is %0d", obj[0], obj[1], obj[2], foo);
\t $finish;
end
obj = new[3] (\'{4,5,6});
foo = sum_array(obj);
if (foo != 15.0) begin
\t $display("FAILED -- sum of \'{4,5,6} is %0d", foo);
\t $finish;
end
$display("PASSED");
end // initial begin
endprogram // main
|
module test;
// parameter j=0;
reg [5:0] j;
reg [5:0] in [7:0];
wire [5:0] out [7:0];
assign out[0][1:0] = 2\'b10;
assign out[0][3:2] = 2\'b01;
assign out[1] = in[j]; // This uses the current j!
assign out[2] = in[2];
assign out[3] = in[3];
initial begin
j = 1;
in[j] = 2\'b10;
in[2][3:2] = 2\'b01;
in[j+2][3:2] = 2\'b10;
#1;
$display("out[0]: %b", out[0]);
$display("out[1]: %b", out[1]);
$display("out[2]: %b", out[2]);
$display("out[3]: %b", out[3]);
for (j=0; j<4; j=j+1) begin
#0; // wait for change to propagate
$display("out[1]-%0d: %b", j, out[1]);
end
end
endmodule
|
module tb;
reg [1:0] i;
reg [3:0] x[0:2];
initial begin
x[1] = 1;
i = 1;
x[i++] += 2;
if (x[1] != 3) $display("FAILED: got %b", x[1]);
else $display("PASSED");
end
endmodule // tb
|
module main;
localparam WID = 4;
reg [WID:0] X;
wire q_and, q_or, q_xor, q_nand, q_nor, q_xnor;
test_logic DUT(.\\A[3] (X[3]), .\\A[2] (X[2]), .\\A[1] (X[1]), .\\A[0] (X[0]),
\t\t .q_and(q_and), .q_or(q_or), .q_xor(q_xor),
\t\t .q_nand(q_nand), .q_nor(q_nor), .q_xnor(q_xnor));
initial begin
for (X = 0 ; X < 16 ; X = X+1) begin
\t #1 /* Let gates settle. */;
\t if (q_and !== & X[WID-1:0]) begin
\t $display("FAILED -- q_and=%b, X=%b", q_and, X[WID-1:0]);
\t $finish;
\t end
\t if (q_or !== | X[WID-1:0]) begin
\t $display("FAILED -- q_or=%b, X=%b", q_or, X[WID-1:0]);
\t $finish;
\t end
\t if (q_xor !== ^ X[WID-1:0]) begin
\t $display("FAILED -- q_xor=%b, X=%b", q_xor, X[WID-1:0]);
\t $finish;
\t end
\t if (q_nand !== ~& X[WID-1:0]) begin
\t $display("FAILED -- q_nand=%b, X=%b", q_nand, X[WID-1:0]);
\t $finish;
\t end
\t if (q_nor !== ~| X[WID-1:0]) begin
\t $display("FAILED -- q_nor=%b, X=%b", q_nor, X[WID-1:0]);
\t $finish;
\t end
\t if (q_xnor !== ~^ X[WID-1:0]) begin
\t $display("FAILED -- q_xnor=%b, X=%b", q_xnor, X[WID-1:0]);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
/*
* Copyright (c) 2001 Stephen Rowland
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module dummy;
reg [7:0] decode_vec;
wire [7:0] data1;
wire [7:0] data2;
// icarus cant handle this statement
assign data1 = (decode_vec[8\'h02>>1] ) ? 8\'h55 : 8\'h00;
assign data2 = (decode_vec[8\'h01 ] ) ? 8\'h55 : 8\'h00;
initial
begin
#0;
$monitor("%h %h %h", decode_vec, data1, data2);
decode_vec = 8\'h02;
#10;
decode_vec = 8\'h80;
#10;
decode_vec = 8\'h02;
#10;
$finish(0);
end
endmodule
|
module test;
reg [1:0] width1[1:0];
reg [2:0] width2[1:0];
reg [1:0] width1_2;
initial
begin
\twidth1[0] = 1;
\twidth2[0] = 2;
\twidth1_2 = width1[0] | width2[0];
\tif(width1_2 !== 3)
\t\t$display("FAILED");
\telse
\t\t$display("PASSED");
end
endmodule
|
`timescale 1ns/1ns
module test;
reg pass = 1;
reg [3 : 0] A = 4\'hf;
wire [3 : 0] a_lls, a_lrs;
reg signed [3 : 0] B = 7;
wire signed [3 : 0] b_als, b_ars;
assign a_lls = A<<4;
assign a_lrs = A>>4;
assign b_als = B<<<4;
assign b_ars = B>>>4;
initial begin
\t#1;
\tif (a_lls !== 4\'b0) begin
\t\t$display("FAILED assigning logical left shift");
\t\tpass = 0;
\tend
\tif (a_lrs !== 4\'b0) begin
\t\t$display("FAILED assigning logical right shift");
\t\tpass = 0;
\tend
\tif (b_als !== 4\'b0) begin
\t\t$display("FAILED assigning arithmetic left shift");
\t\tpass = 0;
\tend
\tif (b_ars !== 4\'h0) begin
\t\t$display("FAILED assigning arithmetic right shift (0)");
\t\tpass = 0;
\tend
\t#1 B = -8;
\t#1;
\tif (b_ars !== 4\'hf) begin
\t\t$display("FAILED assigning arithmetic right shift (1)");
\t\tpass = 0;
\tend
\tif (pass) $display("PASSED");
end
endmodule // test
|
// Check the various variable bit selects (LSB > MSB).
module top;
parameter [-4:-1] ap = 4\'h1;
parameter [-4:-1] bp = 4\'he;
parameter [-3:0] cp = 4\'h1;
parameter [-3:0] dp = 4\'he;
reg passed;
wire [-4:-1] a = 4\'h1;
wire [-4:-1] b = 4\'he;
wire [0:0] s0 = 0;
wire [1:0] s1 = 0;
wire [2:0] s2 = 0;
reg [-4:-1] ar = 4\'h1;
reg [-4:-1] br = 4\'he;
wire [-3:0] c = 4\'h1;
wire [-3:0] d = 4\'he;
wire [0:0] s3 = 0;
wire [1:0] s4 = 0;
reg [-3:0] cr = 4\'h1;
reg [-3:0] dr = 4\'he;
wire res_a0 = a[s0];
wire res_b0 = b[s0];
wire res_a1 = a[s1];
wire res_b1 = b[s1];
wire res_a2 = a[s2];
wire res_b2 = b[s2];
wire res_c3 = c[s3];
wire res_d3 = d[s3];
wire res_c4 = c[s4];
wire res_d4 = d[s4];
reg [-4:-1] res_ab;
reg [-3:0] res_cd;
initial begin
#1;
passed = 1\'b1;
// Check procedural R-value variable bit selects of a net.
$display("a[s0]: %b", a[s0]);
if (a[s0] !== 1\'bx) begin
$display("Failed a[s0], expected 1\'bx, got %b", a[s0]);
passed = 1\'b0;
end
$display("b[s0]: %b", b[s0]);
if (b[s0] !== 1\'bx) begin
$display("Failed b[s0], expected 1\'bx, got %b", b[s0]);
passed = 1\'b0;
end
$display("a[s1]: %b", a[s1]);
if (a[s1] !== 1\'bx) begin
$display("Failed a[s1], expected 1\'bx, got %b", a[s1]);
passed = 1\'b0;
end
$display("b[s1]: %b", b[s1]);
if (b[s1] !== 1\'bx) begin
$display("Failed b[s1], expected 1\'bx, got %b", b[s1]);
passed = 1\'b0;
end
$display("a[s2]: %b", a[s2]);
if (a[s2] !== 1\'bx) begin
$display("Failed a[s2], expected 1\'bx, got %b", a[s2]);
passed = 1\'b0;
end
$display("b[s2]: %b", b[s2]);
if (b[s2] !== 1\'bx) begin
$display("Failed b[s2], expected 1\'bx, got %b", b[s2]);
passed = 1\'b0;
end
$display("c[s3]: %b", c[s3]);
if (c[s3] !== 1\'b1) begin
$display("Failed c[s3], expected 1\'b1, got %b", c[s3]);
passed = 1\'b0;
end
$display("d[s3]: %b", d[s3]);
if (d[s3] !== 1\'b0) begin
$display("Failed d[s3], expected 1\'b0, got %b", d[s3]);
passed = 1\'b0;
end
$display("c[s4]: %b", c[s4]);
if (c[s4] !== 1\'b1) begin
$display("Failed c[s4], expected 1\'b1, got %b", c[s4]);
passed = 1\'b0;
end
$display("d[s4]: %b", d[s4]);
if (d[s4] !== 1\'b0) begin
$display("Failed d[s4], expected 1\'b0, got %b", d[s4]);
passed = 1\'b0;
end
// Check procedural R-value variable bit selects of a parameter.
$display("ap[s0]: %b", ap[s0]);
if (ap[s0] !== 1\'bx) begin
$display("Failed ap[s0], expected 1\'bx, got %b", ap[s0]);
passed = 1\'b0;
end
$display("bp[s0]: %b", bp[s0]);
if (bp[s0] !== 1\'bx) begin
$display("Failed bp[s0], expected 1\'bx, got %b", bp[s0]);
passed = 1\'b0;
end
$display("ap[s1]: %b", ap[s1]);
if (ap[s1] !== 1\'bx) begin
$display("Failed ap[s1], expected 1\'bx, got %b", ap[s1]);
passed = 1\'b0;
end
$display("bp[s1]: %b", bp[s1]);
if (bp[s1] !== 1\'bx) begin
$display("Failed bp[s1], expected 1\'bx, got %b", bp[s1]);
passed = 1\'b0;
end
$display("ap[s2]: %b", ap[s2]);
if (ap[s2] !== 1\'bx) begin
$display("Failed ap[s2], expected 1\'bx, got %b", ap[s2]);
passed = 1\'b0;
end
$display("bp[s2]: %b", bp[s2]);
if (bp[s2] !== 1\'bx) begin
$display("Failed bp[s2], expected 1\'bx, got %b", bp[s2]);
passed = 1\'b0;
end
$display("cp[s3]: %b", cp[s3]);
if (cp[s3] !== 1\'b1) begin
$display("Failed cp[s3], expected 1\'b1, got %b", cp[s3]);
passed = 1\'b0;
end
$display("dp[s3]: %b", dp[s3]);
if (dp[s3] !== 1\'b0) begin
$display("Failed dp[s3], expected 1\'b0, got %b", dp[s3]);
passed = 1\'b0;
end
$display("cp[s4]: %b", cp[s4]);
if (cp[s4] !== 1\'b1) begin
$display("Failed cp[s4], expected 1\'b1, got %b", cp[s4]);
passed = 1\'b0;
end
$display("dp[s4]: %b", dp[s4]);
if (dp[s4] !== 1\'b0) begin
$display("Failed dp[s4], expected 1\'b0, got %b", dp[s4]);
passed = 1\'b0;
end
// Check procedural R-value variable bit selects of a reg.
$display("ar[s0]: %b", ar[s0]);
if (ar[s0] !== 1\'bx) begin
$display("Failed ar[s0], expected 1\'bx, got %b", ar[s0]);
passed = 1\'b0;
end
$display("br[s0]: %b", br[s0]);
if (br[s0] !== 1\'bx) begin
$display("Failed br[s0], expected 1\'bx, got %b", br[s0]);
passed = 1\'b0;
end
$display("ar[s1]: %b", ar[s1]);
if (ar[s1] !== 1\'bx) begin
$display("Failed ar[s1], expected 1\'bx, got %b", ar[s1]);
passed = 1\'b0;
end
$display("br[s1]: %b", br[s1]);
if (br[s1] !== 1\'bx) begin
$display("Failed br[s1], expected 1\'bx, got %b", br[s1]);
passed = 1\'b0;
end
$display("ar[s2]: %b", ar[s2]);
if (ar[s2] !== 1\'bx) begin
$display("Failed ar[s2], expected 1\'bx, got %b", ar[s2]);
passed = 1\'b0;
end
$display("br[s2]: %b", br[s2]);
if (br[s2] !== 1\'bx) begin
$display("Failed br[s2], expected 1\'bx, got %b", br[s2]);
passed = 1\'b0;
end
$display("cr[s3]: %b", cr[s3]);
if (cr[s3] !== 1\'b1) begin
$display("Failed cr[s3], expected 1\'b1, got %b", cr[s3]);
passed = 1\'b0;
end
$display("dr[s3]: %b", dr[s3]);
if (dr[s3] !== 1\'b0) begin
$display("Failed dr[s3], expected 1\'b0, got %b", dr[s3]);
passed = 1\'b0;
end
$display("cr[s4]: %b", cr[s4]);
if (cr[s4] !== 1\'b1) begin
$display("Failed cr[s4], expected 1\'b1, got %b", cr[s4]);
passed = 1\'b0;
end
$display("dr[s4]: %b", dr[s4]);
if (dr[s4] !== 1\'b0) begin
$display("Failed dr[s4], expected 1\'b0, got %b", dr[s4]);
passed = 1\'b0;
end
// Check continuous assignment R-value variable bit selects.
if (res_a0 !== 1\'bx) begin
$display("Failed res_a0, expected 1\'bx, got %b", res_a0);
passed = 1\'b0;
end
if (res_b0 !== 1\'bx) begin
$display("Failed res_b0, expected 1\'bx, got %b", res_b0);
passed = 1\'b0;
end
if (res_a1 !== 1\'bx) begin
$display("Failed res_a1, expected 1\'bx, got %b", res_a1);
passed = 1\'b0;
end
if (res_b1 !== 1\'bx) begin
$display("Failed res_b1, expected 1\'bx, got %b", res_b1);
passed = 1\'b0;
end
if (res_a2 !== 1\'bx) begin
$display("Failed res_a2, expected 1\'bx, got %b", res_a2);
passed = 1\'b0;
end
if (res_b2 !== 1\'bx) begin
$display("Failed res_b2, expected 1\'bx, got %b", res_b2);
passed = 1\'b0;
end
if (res_c3 !== 1\'b1) begin
$display("Failed res_c3, expected 1\'b1, got %b", res_c3);
passed = 1\'b0;
end
if (res_d3 !== 1\'b0) begin
$display("Failed res_d3, expected 1\'b0, got %b", res_d3);
passed = 1\'b0;
end
if (res_c4 !== 1\'b1) begin
$display("Failed res_c4, expected 1\'b1, got %b", res_c4);
passed = 1\'b0;
end
if (res_d4 !== 1\'b0) begin
$display("Failed res_d4, expected 1\'b0, got %b", res_d4);
passed = 1\'b0;
end
// Check procedural L-value variable bit selects.
res_ab = 4\'bxxxx;
res_ab[s0] = 1\'b0;
if (res_ab !== 4\'bxxxx) begin
$display("Failed res_ab[s0], expected 4\'bxxxx, got %b", res_ab);
passed = 1\'b0;
end
res_ab = 4\'bxxxx;
res_ab[s1] = 1\'b0;
if (res_ab !== 4\'bxxxx) begin
$display("Failed res_ab[s1], expected 4\'bxxxx, got %b", res_ab);
passed = 1\'b0;
end
res_ab = 4\'bxxxx;
res_ab[s2] = 1\'b0;
if (res_ab !== 4\'bxxxx) begin
$display("Failed res_ab[s2], expected 4\'bxxxx, got %b", res_ab);
passed = 1\'b0;
end
res_cd = 4\'bxxxx;
res_cd[s3] = 1\'b0;
if (res_cd !== 4\'bxxx0) begin
$display("Failed res_cd[s3], expected 4\'bxxx0, got %b", res_cd);
passed = 1\'b0;
end
res_cd = 4\'bxxxx;
res_cd[s4] = 1\'b0;
if (res_cd !== 4\'bxxx0) begin
$display("Failed res_cd[s4], expected 4\'bxxx0, got %b", res_cd);
passed = 1\'b0;
end
if (passed) $display("Compare tests passed");
end
endmodule
|
// This tests the basic support for default arguments to task/function
// ports. The default port syntax gives SystemVerilog a limited form
// of variable argument lists.
program main;
function int increment(int val, int step = 1, int flag = 1);
increment = val + step*flag;
endfunction // increment
initial begin
if (increment(5) !== 6) begin
\t $display("FAILED -- increment(5) --> %0d", increment(5));
\t $finish;
end
if (increment(5,2) !== 7) begin
\t $display("FAILED -- increment(5,2) --> %0d", increment(5,2));
\t $finish;
end
if (increment(5,,3) !== 8) begin
\t $display("FAILED -- increment(5,,3) --> %0d", increment(5,,3));
\t $finish;
end
$display("PASSED");
end
endprogram // main
|
module top;
parameter NAME = "def";
wire i = 0;
generate
case(NAME)
"test" : assign i = 1\'b1;
default : ;
endcase
endgenerate
initial begin
#1 if (i !== 1\'b0) $display("FAILED");
else $display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* This tests the printing of a string constant. */
module main;
initial
begin
\t$display("%s", "PASSED");
end
endmodule // main
|
module top;
parameter NAME = "test";
wire i = 0;
generate
case(NAME)
"test" : assign i = 1\'b1;
default : ;
endcase
endgenerate
initial begin
#1 if (i !== 1\'bx) $display("FAILED");
else $display("PASSED");
end
endmodule
|
module top;
reg nctl, pctl, b;
wire a, c;
initial begin
$monitor(a,c,,"%v",a,,"%v",c,,b,,nctl,,pctl);
b = 0;
nctl = 0;
pctl = 1;
#1 nctl = 1; pctl = 0;
#1 nctl = 1; pctl = 1;
#1 nctl = 0; pctl = 0;
#1 nctl = 1\'bx; pctl = 0;
#1 nctl = 1; pctl = 1\'bx;
#1 nctl = 1\'bx; pctl = 1;
#1 nctl = 0; pctl = 1\'bx;
#1 nctl = 1\'bx; pctl = 1\'bx;
#1 b = 1; nctl = 0; pctl = 1;
#1 nctl = 1; pctl = 0;
#1 nctl = 1; pctl = 1;
#1 nctl = 0; pctl = 0;
#1 nctl = 1\'bx; pctl = 0;
#1 nctl = 1; pctl = 1\'bx;
#1 nctl = 1\'bx; pctl = 1;
#1 nctl = 0; pctl = 1\'bx;
#1 nctl = 1\'bx; pctl = 1\'bx;
#1 b = 1\'bx; nctl = 0; pctl = 1;
#1 b = 1\'bx; nctl = 1; pctl = 0;
#1 b = 1\'bx; nctl = 1\'bx; pctl = 1\'bx;
#1 b = 1\'bz; nctl = 0; pctl = 1;
#1 b = 1\'bz; nctl = 1; pctl = 0;
#1 b = 1\'bz; nctl = 1\'bx; pctl = 1\'bx;
end
nmos n1 (a, b, nctl);
pmos p1 (a, b, pctl);
cmos c1 (c, b, nctl, pctl);
endmodule
|
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