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// Ten basic tests in here:
// 1. byte must be initialised before any initial or always block
// 2. assignments to (unsigned) bytes with random numbers
// 3. assignments to (unsigned) bytes with random values including X and Z
// 4. converting unsigned integers to unsigned bytes
// 5. converting signed integers to unsigned bytes
// 6. converting integers including X and Z states to unsigned bytes
// 7. trying unsigned sums (procedural, function, task and module)
// 8. trying unsigned (truncated) mults (procedural, function and task)
// 9. trying relational operators
// 10. smaller signed number to unsigned bytes (sign extension)
module mu_add (input byte unsigned a, b, output byte unsigned sc, ss);
assign sc = a + b;
always @(a, b) ss = a + b;
endmodule
module main;
parameter N_REPS = 500; // repetition with random numbers
parameter XZ_REPS = 500; // repetition with \'x \'z values
parameter MAX = 256;
parameter LEN = 8;
// variables used as golden references
reg unsigned [LEN-1:0] ar; // holds numbers
reg unsigned [LEN-1:0] ar_xz; // holds \'x and/or \'z in random positions
reg unsigned [LEN-1:0] ar_expected;
integer unsigned ui;
integer signed si;
reg signed [LEN/2-1:0] slice;
// types to be tested
byte unsigned bu; // holds numbers
byte unsigned bu_xz; // \'x and \'z are attempted on this
byte unsigned bresult; // hold results from sums and mults
byte unsigned mcaresult; // this is permanently wired to a module
byte unsigned mabresult; // this is permanently wired to a module
integer i;
// continuous assigments
// type LHS type RHS
// --------- ---------
// byte 4-value logic
assign bu = ar;
assign bu_xz = ar_xz;
// module instantiation
mu_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) );
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if ( bu !== 8\'b0 || bu_xz !== 8\'b0 || bresult !== 8\'b0 || mcaresult !== 8\'b0 || mabresult !== 8\'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// driving byte type with unsigned random numbers from a variable
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = {$random} % MAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to byte: %b", bu);
$finish;
end
end
# 1;
// attempting to drive variables having \'x \'z values into type unsigned bytes
// \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0
begin
$display ("FAILED - incorrect assigment to byte (when \'x \'z): %b", bu);
$finish;
end
end
// converting unsigned integers to unsigned bytes
// truncation expected (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ui = {$random};
#1;
force bu = ui;
#1;
if (bu !== ui[LEN-1:0])
begin
$display ("FAILED - incorrect truncation from unsigned integer to byte: %b", bu);
$finish;
end
end
release bu;
// converting signed integers to unsigned bytes
// truncation expected (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
si = $random % MAX/2;
#1;
force bu = si;
#1;
if (bu !== si[LEN-1:0])
begin
$display ("FAILED - incorrect truncation from signed integer to byte: %b mismatchs %b", bu, si[7:0]);
$finish;
end
end
release bu;
// converting signed integers having \'x \'z values into type unsigned bytes
// \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM)
// truncation and coercion to zero expected
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
si = $random;
ar_xz = xz_inject (si[LEN-1:0]);
si = {si[31:LEN], ar_xz};
ar_expected = xz_expected (ar_xz);
#1;
force bu_xz = si;
#1;
if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0
begin
$display ("FAILED - incorrect conversion from integer (with \'x \'z) to byte: %b mismatchs %b", bu_xz, ar_expected);
$finish;
end
end
release bu_xz;
// trying unsigned sums
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = {$random} % MAX;
#1;
bresult = bu + bu_xz;
#1;
if ( bresult !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned bytes: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz));
$finish;
end
// invoking byte sum function
if ( fu_sum (bu, bu_xz) !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned bytes in function");
$finish;
end
// invoking byte sum task
tu_sum (bu, bu_xz, bresult);
if ( bresult !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned bytes in task: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz));
$finish;
end
// checking byte sum from module
if ( mcaresult !== u_sum(ar, ar_xz) || mabresult !== u_sum(ar, ar_xz))
begin
$display ("FAILED - incorrect addition of unsigned bytes from module");
$finish;
end
end
// trying unsigned mults: trucation is forced
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = ({$random} % MAX) << LEN/2;
ar_xz = ({$random} % MAX) << (LEN/2 -1);
#1;
bresult = bu * bu_xz;
#1;
if ( bresult !== u_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned bytes: %0d mismatchs %0d", bresult, u_mul(ar, ar_xz));
$finish;
end
// invoking byte mult function
if ( fu_mul (bu, bu_xz) !== u_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect product of unsigned bytes in function");
$finish;
end
// invoking byte mult task
tu_mul (bu, bu_xz, bresult);
if ( bresult !== u_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect product of unsigned bytes in task: %0d mismatchs %0d", bresult, u_mul(ar, ar_xz));
$finish;
end
end
// trying relational operators
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = {$random} % MAX;
#1;
if ( (bu < bu_xz ) !== (ar < ar_xz) )
begin
$display ("FAILED - incorrect \'less than\' on unsigned bytes");
$finish;
end
if ( (bu <= bu_xz ) !== (ar <= ar_xz) )
begin
$display ("FAILED - incorrect \'less than or equal\' on unsigned bytes");
$finish;
end
if ( (bu > bu_xz ) !== (ar > ar_xz) )
begin
$display ("FAILED - incorrect \'greater than\' on unsigned bytes");
$finish;
end
if ( (bu >= bu_xz ) !== (ar >= ar_xz) )
begin
$display ("FAILED - incorrect \'greater than or equal\' than on unsigned bytes");
$finish;
end
if ( (bu == bu_xz ) !== (ar == ar_xz) )
begin
$display ("FAILED - incorrect \'equal to\' on unsigned bytes");
$finish;
end
if ( (bu != bu_xz ) !== (ar != ar_xz) )
begin
$display ("FAILED - incorrect \'not equal to\' on unsigned bytes");
$finish;
end
end
# 1;
// signed small number to unsigned byte
for (i = 0; i < (1<<LEN/2); i = i+1)
begin
#1;
slice = $random % \'h7;
force bu = slice;
ar = slice;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect signed extend to unsigned bytes");
$finish;
end
end
release bu;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [LEN-1:0] xz_inject (input unsigned [LEN-1:0] value);
integer i, temp;
begin
temp = {$random} % MAX;
for (i=0; i<LEN; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random % MAX;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [LEN-1:0] xz_expected (input unsigned [LEN-1:0] value_xz);
integer i;
begin
for (i=0; i<LEN; i=i+1)
begin
if (value_xz[i] === 1\'bx || value_xz[i] === 1\'bz )
value_xz[i] = 1\'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
// unsigned 4-value sum
function unsigned [LEN-1:0] u_sum (input unsigned [LEN-1:0] a, b);
u_sum = a + b;
endfunction
// unsigned byte sum as function
function byte unsigned fu_sum (input byte unsigned a, b);
fu_sum = a + b;
endfunction
// unsigned byte sum as task
task tu_sum (input byte unsigned a, b, output byte unsigned c);
c = a + b;
endtask
// unsigned 4-value mults
function unsigned [LEN-1:0] u_mul (input unsigned [LEN-1:0] a, b);
u_mul = a * b;
endfunction
// unsigned byte mults
function byte unsigned fu_mul (input byte unsigned a, b);
fu_mul = a * b;
endfunction
// unsigned byte mult as task
task tu_mul (input byte unsigned a, b, output byte unsigned c);
c = a * b;
endtask
endmodule
|
module bug;
reg [4:0] a = 5\'b01010;
reg failed = 0;
initial begin
foreach (a[i]) begin
$display("Value of a[%0d]=%0d", i, a[i]);
if (a[i] !== i[0]) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
reg [3:0] b;
wire [1:0] a;
assign a = b[3:2] + 1;
initial begin
b = 4\'b1011;
#1;
if (a===2\'b11)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg [2:0] res [0:7];
reg [2:0] in [0:7];
reg [7:0] dummy [0:6];
time run_time [0:7];
time exp_time [0:7];
integer i;
initial begin
pass = 1\'b1;
#1;
// Initialize the input array.
for (i=0; i<8; i=i+1) begin
in[i] = i[2:0];
end
#1;
for (i=0; i<8; i=i+1) begin
exp_time[i] = $time-1;
end
check;
// We only have 6 dummy items, check that each triggers correctly.
for (i=0; i<7; i=i+1) begin
dummy[i] = 1\'b0;
#1;
exp_time[i] = $time-1;
check;
end
if (pass) $display("PASSED");
end
// Check that the value and time are correct.
task check;
integer j;
begin
for (j=0; j<8; j=j+1) begin
if (res[j] !== j[2:0]) begin
$display("FAILED: index %0d value, at %t, expexted %b, got %b.",
j, $time, j[2:0], res[j]);
pass = 1\'b0;
end
if (run_time[j] !== exp_time[j]) begin
$display("FAILED: index %0d time, at %t, expexted %t, got %t.",
j, $time, exp_time[j], run_time[j]);
pass = 1\'b0;
end
end
end
endtask
genvar m;
generate
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
for (m=0; m<=7; m=m+1) begin: idac_loop
`else
for (m=0; m<=6; m=m+1) begin: idac_loop
`endif
// This should complain that dummy[7] is out of bounds.
always @ (in[m] or dummy[m]) begin
res[m] = in[m];
run_time[m] = $time;
end
end
endgenerate
endmodule
|
`begin_keywords "1364-2005"
module automatic_error();
reg global;
task automatic auto_task;
begin:block
reg local;
global <= @(local) 0;
end
endtask
endmodule
`end_keywords
|
// Check that not providing a value during module instantiation for a parameter
// without a default value generates an error.
module a #(
parameter A
);
initial begin
$display("FAILED");
end
endmodule
module test;
a i_a();
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [7:0] a;
reg [6:-1] b;
initial begin
a = 1;
b = 2;
if (a !== 8\'h01) begin
\t $display("FAILED -- to initialize a: %b", a);
\t $finish;
end
if (b !== 8\'h02) begin
\t $display("FAILED -- to initialize b: %b", b);
\t $finish;
end
b = a;
if (b !== 8\'h01) begin
\t $display("FAILED -- to copy a to b: %b", b);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module counter(out, clk, reset);
parameter WIDTH = 8;
output [WIDTH-1 : 0] out;
input clk, reset;
reg [WIDTH-1 : 0] out;
wire clk, reset;
(* ivl_synthesis_on *)
always @(posedge clk)
out <= out + 1;
always @(posedge reset)
force out = 0;
always @(negedge reset)
release out;
(* ivl_synthesis_off *)
initial $display("PASSED");
endmodule // counter
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: readmemh function - data file length less than array
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
/* pre init the array to all zeroes. */
for(count = 0; count <= 7; count = count + 1)
array[count] = 8\'h0;
$readmemh("ivltests/readmemh2.dat",array);
for(count = 0; count <= 3; count = count + 1)
begin
if(array[count[2:0]] !== count)
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count],count);
end
end
if(array[4] !== 8\'h0)
begin
error = 1;
$display("FAILED - array[4] == %h, s/b 0",
array[count]);
end
if(error == 0)
$display("PASSED\
");
$finish ;
end
endmodule
|
int num1 = 201; string str1 = "unit2";
int num2 = 202; string str2 = "unit2";
int num3 = 203; string str3 = "unit2";
module m3();
int num2 = 232; string str2 = "m3";
initial begin
#2; // allow m1 to go first
m2.m1inst.obj.display;
$display("%d from %s", num1, str1);
$display("%d from %s", num2, str2);
$display("%d from %s", num3, str3);
$display("%d from %s", m4.num4, m4.str4);
end
/* This should not change the result, but Icarus ignores the order in
which variables are declared and used.
int num3 = 113; string str3 = "m3";
*/
endmodule
module m4();
int num1 = 241; string str1 = "m4";
int num2 = 242; string str2 = "m4";
int num3 = 243; string str3 = "m4";
int num4 = 244; string str4 = "m4";
m3 m3inst();
endmodule
|
`begin_keywords "1364-2005"
module automatic_error();
task automatic auto_task;
integer local;
begin
local = 1;
$fstrobe(1, "%0d", local);
end
endtask
initial auto_task;
endmodule
`end_keywords
|
// tests using array elements as indices/selects in an array lval select
`timescale 1ns/100ps
module tb;
reg [7:0] a[7:0];
real r[7:0];
wire [2:0] idx[7:0];
genvar g;
for (g = 0; g < 8; g=g+1)
assign idx[g] = g;
reg pass;
integer i;
initial begin
pass = 1\'b1;
// zero everything out
for (i = 0; i < 8; i = i + 1) begin
a[i] = 8\'h0;
r[i] = 0.0;
end
// test using one in a part select
a[1][idx[1]*4 +: 4] = 4\'ha;
if (a[1] != 8\'ha0) begin
$display("FAILED part select, expected a0, got %x", a[1]);
pass = 1\'b0;
end
// test using one in an index
a[idx[2]] = 8\'hbc;
if (a[2] != 8\'hbc) begin
$display("FAILED word index, expected bc, got %x", a[2]);
pass = 1\'b0;
end
// and now both...
a[idx[3]][idx[0]*4 +: 4] = 4\'hd;
if (a[3] != 8\'h0d) begin
$display("FAILED word index and part select, expected 0d, got %x", a[3]);
pass = 1\'b0;
end
// non-blocking, in part select
a[4][idx[1]*4 +: 4] <= 4\'he;
if (a[4] != 8\'h00) begin
$display("FAILED NB assign with part select 1, expected 00, got %x", a[4]);
pass = 1\'b0;
end
#0.1;
if (a[4] != 8\'he0) begin
$display("FAILED NB assign with part select 2, expected e0, got %x", a[4]);
pass = 1\'b0;
end
// non-blocking, in index
a[idx[5]] <= 8\'h12;
if (a[5] != 8\'h00) begin
$display("FAILED NB assign with word index 1, expected 00, got %x", a[4]);
pass = 1\'b0;
end
#0.1;
if (a[5] != 8\'h12) begin
$display("FAILED NB assign with word index 2, expected 12, got %x", a[4]);
pass = 1\'b0;
end
// non-blocking, index and part select
a[idx[6]][idx[0]*4 +: 4] <= 4\'h3;
if (a[6] != 8\'h00) begin
$display("FAILED NB assign with both 1, expected 00, got %x", a[4]);
pass = 1\'b0;
end
#0.1;
if (a[6] != 8\'h03) begin
$display("FAILED NB assign with both 2, expected 03, got %x", a[4]);
pass = 1\'b0;
end
// NB, both, with a delay
a[idx[7]][idx[1]*4 +: 4] <= #(idx[1]) 4\'h4;
#0.1;
if (a[7] != 8\'h00) begin
$display("FAILED NB assign with both and delay 1, expected 00, got %x", a[4]);
pass = 1\'b0;
end
#1.1;
if (a[7] != 8\'h40) begin
$display("FAILED NB assign with both and delay 2, expected 40, got %x", a[4]);
pass = 1\'b0;
end
// real array index
r[idx[0]] = 1.1;
if (r[0] != 1.1) begin
$display("FAILED real word, expected 1.0, got %f", r[0]);
pass = 1\'b0;
end
// NB to real array
r[idx[1]] <= 2.2;
if (r[1] != 0.0) begin
$display("FAILED NB assign real word 1, expected 0.0 got %f", r[1]);
pass = 1\'b0;
end
#0.1;
if (r[1] != 2.2) begin
$display("FAILED NB assign real word 2, expected 2.2 got %f", r[1]);
pass = 1\'b0;
end
// NB to real array with delay
r[idx[2]] <= #(idx[2]) 3.3;
#1.1;
if (r[2] != 0.0) begin
$display("FAILED NB assign with delay to real word 1, expected 0.0 got %f", r[1]);
pass = 1\'b0;
end
#1.0;
if (r[2] != 3.3) begin
$display("FAILED NB assign with delay to real word 2, expected 3.3 got %f", r[1]);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module top;
parameter one = 1\'b1;
parameter zero = 1\'b0;
// These should fail since a zero replication is invalid in this context.
wire [3:0] ca_tru = one ? 4\'b0001 : {0{1\'b0}};
wire [3:0] ca_fal = zero ? {0{1\'b0}} : 4\'b0010;
// We used to not check for this so just pass for that case
initial $display("PASSED");
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate declared wire and implicit wires displayed.
//
// This circuit has 3 i/os and 3 implicit wires. Both should be
// present in vcd file??
module xorckt (out,in0,in1);
input in0;
input in1;
wire junk;
nand #1 na1 (na1_out,in0,in1);
nand #1 na2 (na2_out,in0,na1_out);
nand #1 na3 (na3_out,in1,na1_out);
nand #1 na4 (out,na2_out,na3_out);
assign junk = in0;
endmodule
module main;
wire xout;
reg i1,i2;
xorckt myckt (.out(xout),.in0(i1),.in1(i2));
initial
begin
$dumpfile("work/test.vcd");
$dumpvars(0,main.myckt);
i1 = 1\'b0;
i2 = 1\'b0;
#5;
$display("%b xor %b = %b",i1,i2,xout);
i1 = 1\'b1;
i2 = 1\'b0;
#5;
$display("%b xor %b = %b",i1,i2,xout);
i1 = 1\'b1;
i2 = 1\'b1;
#5;
$display("%b xor %b = %b",i1,i2,xout);
i1 = 1\'b0;
i2 = 1\'b1;
#5 ;
$display("%b xor %b = %b",i1,i2,xout);
end
endmodule // main
|
//
// Test the number format insanity
//
module test;
integer err;
reg [31:0] i;
// Ugly specification
initial begin
\ti = 659;
\ti = \'h 837FF;
\ti = \'o7460;
\ti = 4\'b1001;
\ti = 5 \'D 3;
\ti = 3\'b01x;
\ti = 12\'hx;
\ti = 16\'hz;
\ti = -8 \'d 6;
\ti = 4 \'shf;
\ti = -4 \'sd15;
end
//always @(i) $display("%0t:\\ti = %d", $time, i);
// Potential ambiguities
initial begin
\terr = 0;
i = # 9 1\'d0;
\ti = # 9_7 \'D 3;
\t#100;
\tif (i != \'d3) begin
\t $display("\'d3 != %0d", i);
\t err = 1;
\tend
\ti = # 1 \'h 123;
\t#100;
\tif (i != \'h123) begin
\t $display("\'h123 != %0h", i);
\t err = 1;
\tend
\ti = #(5 \'D 3) \'D 3;
\t#100;
\tif (i != \'d3) begin
\t $display("\'d3 != %0d", i);
\t err = 1;
\tend
\ti = # 93 \'h 837FF;
\t#100;
\tif (i != \'h837ff) begin
\t $display("\'h837ff != %0h", i);
\t err = 1;
\tend
\ti = # 33 20 \'h 837ff - 1;
\t#100;
\tif (i != \'h837fe) begin
\t $display("\'h837fe != %0h", i);
\t err = 1;
\tend
\ti = # 69 - 20 \'d 255 + 20\'d1;
\t#100;
\tif (i[19:0] != 20\'hf_ff_02) begin
\t $display("- \'d254 != %0d (%h)", i, i);
\t err = 1;
\tend
\ti = #(27 - 20)\'d 254 + 1;
\t#100;
\tif (i != 10\'d255) begin
\t $display("\'d255 != %0d", i);
\t err = 1;
\tend
\ti = # 97.4 \'h abcd;
\t#100;
\tif (i != \'habcd) begin
\t $display("\'abcd != %0h", i);
\t err = 1;
\tend
\tif (err)
\t $display("FAILED");
\telse
\t $display("PASSED");
end
endmodule
|
/*
* This module instantiates the fa4 entity, which in turn
* instantiates other entities. This demonstrates hierarchical
* constructs in VHDL.
*/
module test;
reg [3:0] a, b;
reg cin;
wire [3:0] s;
wire cout;
initial begin
cin = 0;
a = 4\'h2;
b = 4\'h3;
end
initial begin
#1;
if (s !== 4\'h5) begin
$display("Error in trivial sum");
$finish;
end
$display ("PASSED");
end
fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) );
endmodule // test
|
// Check that out-of-bounds access on a 2-state vector dynamic array works and
// returns the correct value.
module test;
bit [7:0] d[];
logic [7:0] x;
initial begin
x = d[1];
if (x === 8\'h00) begin
$display("PASSED");
end else begin
$display("FAILED. Expected 00000000, got %b",x);
end
end
endmodule
|
/*
* Notice how the port direction and type are declared
* together in each statement.
*/
module one_a(sum,co,a,b,ci);
output reg sum;
output reg co;
input wire a;
input wire b;
input wire ci;
always@(a or b or ci)
begin
sum = a ^ b ^ ci;
co = a*b || a*ci || b*ci;
end
endmodule
module main;
wire sum, co;
reg [3:0] in;
one_a dut (sum, co, in[0], in[1], in[2]);
initial begin
in = 0;
#1 for (in = 0 ; in[3] == 0 ; in = in + 1) begin
\t #1 $display("in=%b; co/sum = %b/%b", in, co, sum);
end
end
endmodule // main
|
module pr3561350();
reg [31:0] source;
reg [31:0] result;
initial begin
source = 10;
// the following expression results in a compiler internal error
result = (source * 2) + 2 + 3 + 4;
// check we get the expected result when the bug has been fixed
if (result === 29)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// Check that declaring an unpacked array typed member in a packed struct is an
// error.
module test;
struct packed {
int x[2];
} s;
initial begin
$display("FAILED");
end
endmodule
|
/*
* Copyright (c) 2002 Richard M. Myers
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
`timescale 10 ns/ 10 ns
module top ;
reg clk ;
reg [11:0] x_os_integ, y_os_integ;
reg [5:0] x_os, y_os;
initial
\t begin
//$dumpfile("show_math.vcd");
//$dumpvars(1, top);
\t clk = 1\'h0 ;
x_os = 6\'h01;
y_os = 6\'h3f;
x_os_integ = 12\'h000;
y_os_integ = 12\'h000;
\t end
initial
\t begin
\t#60;
\t forever #3 clk = ~clk ; // 16Mhz
\tend
always @( posedge clk )
begin
// Integration period set above depending on configured modem speed.
x_os_integ <= x_os_integ + {{6{x_os[5]}}, {x_os[5:0]}};
y_os_integ <= y_os_integ + {{6{y_os[5]}}, {y_os[5:0]}};
$display ("%x %x", x_os_integ, y_os_integ);
end
initial
begin
#200 $finish(0);
end
endmodule
|
// Check that it is not possible to perform non-blocking assignments to fields
// of structs with automatic lifetime.
module test;
task automatic auto_task;
struct packed {
logic x;
} s;
s.x <= 10;
$display("FAILED");
endtask
initial begin
auto_task;
end
endmodule
|
/*
* integer4ge - a verilog test for integer greater-or-equal conditional >=
*
* Copyright (C) 2000 Steve Wilson [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
`timescale 100s/1s
module test;
reg [3:0] result;
reg error;
integer num1;
wire [3:0] result1;
assign result1 = 1 + (num1 /4);
initial
begin
error = 0;
num1 = 32\'h24 ;
result = 1 + (num1 / 4);
#1;
if(result !== 4\'ha)
begin
$display("FAILED - division didn\'t work s/b A, is %h",result);
error = 1;
end
if(result1 !== 4\'ha)
begin
$display("FAILED - assign division didn\'t work s/b A, is %h",result1);
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
module test();
a a (.pi(pi));
endmodule // test
module a(input pi);
assign Pi = pi;
b b(.Pi(Pi));
endmodule // a
module b(input Pi);
endmodule
|
module top;
reg in;
wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2;
initial begin
$monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);
in = 0;
#1 in = 1;
#1 in = 0;
end
buf (bf1, bf2, in);
not (nt1, nt2, in);
pulldown (pd1, pd2);
pullup (pu1, pu2);
endmodule
|
/*
* Copyright (c) 2000 Yasuhisa Kato <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module busm ( clk, iB, oB );
input clk ;
input [3:0] iB ;
output [3:0] oB ;
reg [3:0] r ;
assign oB = r ;
always @(posedge clk) r <= iB ;
endmodule
module main;
reg a, b, c, d ;
reg clk ;
initial begin clk = 0 ; forever #5 clk = ~clk ; end
initial begin a = 0 ; c = 0 ; #100 $finish(0); end
wire e0, f0, g0, h0 ;
wire e, f, g, h ;
wire [3:0] ii, oo ;
always @(posedge clk) a <= ~a ;
always @(posedge clk) b <= a ;
always @(posedge clk) c <= c ^ a ;
always @(posedge clk) d <= ~c ;
assign ii = {a, b, c, d} ;
assign {e0, f0, g0, h0} = oo ;
busm M0 ( clk, ii, oo );
busm M1 ( clk, {a,b,c,d}, {e,f,g,h} );
always @(posedge clk)
$display("%h %h %h %h : %b : %h %h %h %h : %b : %h %h %h %h",
a, b, c, d, M0.r, e0, f0, g0, h0,
M1.r, e, f, g, h
);
endmodule
// expecting result
// 0 x 0 x : xxxx : z z z z : xxxx : z z z z
// 1 0 0 1 : 0z0z : 0 z 0 z : 0z0z : 0 z 0 z
// 0 1 1 1 : 1001 : 1 0 0 1 : 1001 : 1 0 0 1
// 1 0 1 0 : 0111 : 0 1 1 1 : 0111 : 0 1 1 1
// 0 1 0 0 : 1010 : 1 0 1 0 : 1010 : 1 0 1 0
// 1 0 0 1 : 0100 : 0 1 0 0 : 0100 : 0 1 0 0
// 0 1 1 1 : 1001 : 1 0 0 1 : 1001 : 1 0 0 1
// 1 0 1 0 : 0111 : 0 1 1 1 : 0111 : 0 1 1 1
// 0 1 0 0 : 1010 : 1 0 1 0 : 1010 : 1 0 1 0
// 1 0 0 1 : 0100 : 0 1 0 0 : 0100 : 0 1 0 0
|
module main;
real foo;
real bar;
initial begin
foo = 1.0;
bar = 1.2;
if (foo >= bar) begin
\t $display("FAILED -- foo < bar?");
\t $finish;
end
if (foo >= 1.2) begin
\t $display("FAILED -- foo < 1.2?");
\t $finish;
end
if (1.0 >= 1.2) begin
\t $display("FAILED -- 1.0 < 1.2?");
\t $finish;
end
if (1 >= 1.2) begin
\t $display("FAILED -- 1 < 1.2?");
\t $finish;
end
if (foo > bar) begin
\t $display("FAILED -- foo < bar?");
\t $finish;
end
if (foo > 1.2) begin
\t $display("FAILED -- foo < 1.2?");
\t $finish;
end
if (1.0 > 1.2) begin
\t $display("FAILED -- 1.0 < 1.2?");
\t $finish;
end
if (1 > 1.2) begin
\t $display("FAILED -- 1 < 1.2?");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module test (D);
input D;
prim p (a, D, D, D);
endmodule
primitive prim (Z, A, B, S);
output Z;
input A, B, S;
table
0 0 x : 0 ;
endtable
endprimitive
|
module test_logic
#(parameter WID = 4)
(input wire [WID-1:0] A,
output reg q_and, q_or, q_xor, q_nand, q_nor, q_xnor);
always @(A) begin
q_and = &A;
q_or = |A;
q_xor = ^A;
q_nand = ~q_and;
q_nor = ~q_or;
q_xnor = ~q_xor;
end
endmodule // test_logic
|
module pr2842185();
// check that dection of signal/genvar name collisions
// observes scope boundaries.
genvar i;
task MyTask;
integer i;
begin
$display("PASSED");
end
endtask
initial MyTask;
endmodule
|
module module1(clock,reset,result);
input clock,reset;
output result;
reg result;
always @ (posedge clock)
if (reset) result <= 0; else result <= 1;
endmodule
// driver
module main;
reg clk,reset;
reg data[1:3]; // ILLEGAL port connection NOT detected
// to fix, use wire data_1,data_2,data_3;
module1 inst1(clk,reset,data[1]);
module1 inst2(clk,reset,data[2]);
module1 inst3(clk,reset,data[3]);
always #50 clk = ~clk;
initial begin
$monitor($time,"clk=%b,reset=%b,%b%b%b",clk,reset,data[1],data[2],data
[3]);
clk = 0;
reset = 1;
#200 reset = 0;
#200 $display("driver timeout"); $finish;
end
endmodule
|
//
// Copyright (c) 2001 Stephan Gehring
//
// (Modified by Stephan Williams to include PASS/FAIL messages.)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg [7:0] x;
initial begin
x = \'h4000 + \'hzz; // iverilog doesn\'t like \'hzz
if (x !== 8\'hxx) begin
\t$display("FAILED -- x = %b", x);
\t$finish;
end
$display("PASSED");
end
endmodule
|
// Copyright (c) 2014 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Tests if dynamic array words are of appropriate size.
module sv_cast_string();
bit [6:1] darr [];
bit [63:0] darr_64 [];
logic [4:10] darr_rev [];
initial begin
darr = new[4];
darr_64 = new[8];
darr_rev = new[3];
if($size(darr[0]) != 6 || $size(darr_64[2]) != 64 || $size(darr_rev[1]) != 7 ||
$size(darr) != 4 || $size(darr_64) != 8 || $size(darr_rev) != 3)
begin
$display("FAILED");
$finish();
end
darr[0] = 6\'b110011;
darr[1] = 6\'b000011;
darr[2] = darr[0] + darr[1];
darr_64[0] = 64\'hcafe0000dead0000;
darr_64[1] = 64\'h0000bad00000d00d;
darr_64[2] = darr_64[0] + darr_64[1];
darr_rev[0] = 7\'b1111000;
darr_rev[1] = 7\'b0000011;
darr_rev[2] = darr_rev[0] + darr_rev[1];
if(darr[2] !== 6\'b110110 || darr_64[2] !== 64\'hcafebad0deadd00d ||
darr_rev[2] !== 7\'b1111011)
begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
module top;
parameter weq1 = 2\'b01 ==? 0.0;
parameter weq2 = 0.0 ==? 2\'b01;
parameter wneq1 = 2\'b01 !=? 0.0;
parameter wneq2 = 0.0 !=? 2\'b01;
initial begin
$display("FAILED");
end
endmodule
|
module top_default;
initial begin
$printtimescale(top_default);
$printtimescale(top_timescale);
$printtimescale(top_resetall);
$printtimescale(top_timescale2);
$printtimescale(top_timescale3);
end
endmodule
`resetall
`timescale 1ns/1ns
module top_timescale;
reg a;
initial a = 1'b1;
endmodule
`resetall
`resetall
module top_resetall;
reg a;
initial a = 1'b0;
endmodule
`resetall
`timescale 1ms/1ms
module top_timescale2;
reg a;
initial a = 1'b1;
endmodule
`resetall
`timescale 1us/1us
module top_timescale3;
reg a;
initial a = 1'bz;
endmodule
|
module top;
reg [7:0] a;
reg [2:0] b;
wire [7:0] y, z;
assign y = a >> b;
assign z = $signed(a) >> $signed(b);
initial begin
// Example vector
a = 8\'b10101010;
b = 3\'b101;
#1;
// Test for correctness
if (y === z && y === 8\'b00000101)
$display("PASSED");
else
$display("FAILED, expected 8\'b00000101, got %b/%b", y, z);
end
endmodule
|
module main;
int unsigned foo, bar = 10;
int signed foos, bars = 10;
int unsigned wire_sum;
int\t\twire_sums;
assign wire_sum = foo + bar;
assign wire_sums = foos + bars;
function int unsigned sum(input int unsigned a, b);
sum = a + b;
endfunction
function int unsigned sums(input int signed a, b);
sums = a + b;
endfunction
initial begin
foo = 9;
$display("%0d * %0d = %0d", foo, bar, foo * bar);
$display("sum(%0d,%0d) = %0d", foo, bar, sum(foo,bar));
if (foo !== 9 || bar !== 10) begin
\t $display("FAILED");
\t $finish;
end
if (foo*bar !== 90) begin
\t $display("FAILED");
\t $finish;
end
if (sum(foo,bar) !== 19) begin
\t $display("FAILED");
\t $finish;
end
foos = -7;
$display("%0d * %0d = %0d", foos, bars, foos * bars);
$display("sums(%0d,%0d) = %0d", foos, bars, sums(foos,bars));
if (foos !== -7 || bars !== 10) begin
\t $display("FAILED");
\t $finish;
end
if (foos*bars !== -70) begin
\t $display("FAILED");
\t $finish;
end
if (sums(foos,bars) !== 3) begin
\t $display("FAILED");
\t $finish;
end
#0; // allow CAs to propagate
$display("wire_sum = %0d", wire_sum);
$display("wire_sums = %0d", wire_sums);
if (wire_sum !== 19) begin
\t $display("FAILED");
\t $finish;
end
if (wire_sums !== 3) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module subN
#(parameter WID = 4)
(input wire [WID-1:0] A,
input wire [WID-1:0] B,
output wire [WID:0] Q
/* */);
assign Q = A - B;
endmodule // add
|
module test();
localparam size1 = 4;
localparam size2 = 6;
localparam size3 = 8;
reg [5:0] value1 = 6\'h3f;
reg signed [5:0] value2 = 6\'h3f;
reg [31:0] result;
reg failed = 0;
initial begin
result = size1\'(value1) + \'d0;
$display("%h", result);
if (result !== 32\'h0000000f) failed = 1;
result = size1\'(value1) + \'sd0;
$display("%h", result);
if (result !== 32\'h0000000f) failed = 1;
result = size1\'(value2) + \'d0;
$display("%h", result);
if (result !== 32\'h0000000f) failed = 1;
result = size1\'(value2) + \'sd0;
$display("%h", result);
if (result !== 32\'hffffffff) failed = 1;
result = size2\'(value1) + \'d0;
$display("%h", result);
if (result !== 32\'h0000003f) failed = 1;
result = size2\'(value1) + \'sd0;
$display("%h", result);
if (result !== 32\'h0000003f) failed = 1;
result = size2\'(value2) + \'d0;
$display("%h", result);
if (result !== 32\'h0000003f) failed = 1;
result = size2\'(value2) + \'sd0;
$display("%h", result);
if (result !== 32\'hffffffff) failed = 1;
result = size3\'(value1) + \'d0;
$display("%h", result);
if (result !== 32\'h0000003f) failed = 1;
result = size3\'(value1) + \'sd0;
$display("%h", result);
if (result !== 32\'h0000003f) failed = 1;
result = size3\'(value2) + \'d0;
$display("%h", result);
if (result !== 32\'h000000ff) failed = 1;
result = size3\'(value2) + \'sd0;
$display("%h", result);
if (result !== 32\'hffffffff) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule // main
|
module check (input unsigned [22:0] a, b, c);
wire unsigned [22:0] int_AB;
assign int_AB = a / b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB != c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B = 1;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX + 1;
B = {$random} % 500 + 1;
end
#1 A = 0;
B = 1;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
end
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [22:0] r;
stimulus stim (.A(a), .B(b));
udiv23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#20000;
$display("PASSED");
$finish;
end
endmodule
|
module test ();
reg[7:0] a;
reg b;
always @*
begin
\tb = 1\'b0;
\tcase (a)
\t 8\'d66: b = 1\'b1;
\t default:\t\t ;
\tendcase
end
initial begin
a = 0;
#1 if (b !== 0) begin
\t $display("FAILED -- a=%h b=%b", a, b);
\t $finish;
end
a = 66;
#1 if (b !== 1) begin
\t $display("FAILED -- a=%h b=%b", a, b);
\t $finish;
end
$display("PASSED");
end
endmodule
|
module main;
parameter WID = 4;
parameter SWID = 2;
reg [WID-1:0] D;
reg [SWID-1:0] S;
wire\t\t Q;
muxN dut(.\\D[3] (D[3]), .\\D[2] (D[2]), .\\D[1] (D[1]), .\\D[0] (D[0]),
\t .\\S[1] (S[1]), .\\S[0] (S[0]),
\t .Q(Q));
integer\t idx, sdx;
initial begin
for (idx = 0 ; idx < 50 ; idx += 1) begin
\t D = $random;
\t for (sdx = 0 ; sdx < (1<<SWID) ; sdx = sdx+1) begin
\t S = sdx[SWID-1:0];
\t #1 ;
\t if (Q !== D[S]) begin
\t $display("FAILED = D=%b, S=%0d, Q=%b", D, S, Q);
\t $finish;
\t end
\t end
end // for (idx = 0 ; idx < 50 ; idx += 1)
$display("PASSED");
end // initial begin
endmodule // main
|
/*
* Copyright (c) 2001 Philip Blundell <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module m;
task t;
input [255:0] s;
begin
$display("%s", s);
end
endtask
initial
begin
t("Hello world of Verilog");
end
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: eeq.v,v 1.1 2001/06/26 01:07:15 sib4 Exp $
// $Log: eeq.v,v $
// Revision 1.1 2001/06/26 01:07:15 sib4
// new test for === and !==
//
//
// Test for === amd !== in structural context.
module eeq;
reg [3:0] a, b;
wire eeq = a === b;
`ifdef DONT_TEST_NEE
wire nee = ~(a === b);
`else
wire nee = a !== b;
`endif
reg\t err;
always
begin
\t#2;
\t$display("%b %b ===%b !==%b", a, b, eeq, nee);
\tif (((a === b) !== eeq) || ((a !== b) !== nee)) err = 1;
end
initial
begin
\terr = 0;
\t#1 a = 4\'b zx10; b = 4\'b zx10; #1;
\t#1 a = 4\'b 1x10; b = 4\'b zx10; #1;
\t#1 a = 4\'b xz10; b = 4\'b zx10; #1;
\t#1 a = 4\'b xz01; b = 4\'b zx10; #1;
\t#1 a = 4\'b 0000; b = 4\'b 0000; #1;
\t#1 a = 4\'b 1111; b = 4\'b 1111; #1;
\t#1 a = 4\'b xxxx; b = 4\'b xxxx; #1;
\t#1 a = 4\'b zzzz; b = 4\'b zzzz; #1;
\t#1;
\tif (err)
\t $display("FAILED");
\telse
\t $display("PASSED");
\t$finish;
end
endmodule
|
// Check that declaring a queue typed member in a packed struct is an error.
module test;
struct packed {
int x[$];
} s;
initial begin
$display("FAILED");
end
endmodule
|
module main;
wire [1:0] a2, b2;
wire [2:0] a3, b3;
target #(.WA(2), .WB(2)) u1 (a2, b2);
target #(.WA(3), .WB(3)) u2 (a3, b3);
initial begin
$display("u1.WA=%d, $bits(u1.A)=%d", u1.WA, $bits(u1.A));
$display("u1.WB=%d, $bits(u1.A)=%d", u1.WB, $bits(u1.B));
if ($bits(u1.A) != 2) begin
\t $display("FAILED -- $bits(u1.A) = %d", $bits(u1.A));
\t $finish;
end
if ($bits(u2.A) != 3) begin
\t $display("FAILED -- $bits(u2.A) = %d", $bits(u2.A));
\t $finish;
end
$display("PASSED");
end
endmodule // main
module target
#(parameter WA = 4, WB = 4)
(input [WA-1:0] A, output [WB-1:0] B);
assign B = A;
endmodule // target
|
module bug();
reg [31:0] d;
reg [31:0] x;
reg [31:0] y;
reg [31:0] z;
initial begin
d = 32\'hffff0000;
x = 32\'hffffffff << d;
y = 32\'hffffffff >> d;
z = 32\'hffffffff >>> d;
$display("%h", x);
$display("%h", y);
$display("%h", z);
if (x === 32\'d0 && y === 32\'d0 && z === 32\'d0)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
`define world World
`define test Hello `world
module test;
initial $display("The `test definition is: `define %s", ``test);
endmodule
|
module top;
wire [3:0][3:0] array1;
wire [3:0][3:0] array2;
wire [3:0][3:0] array3;
wire [3:0][3:0] array4;
wire [3:0][3:0] array5;
wire [3:0][3:0] array6;
assign array1[0+:2] = 8\'h21;
assign array1[2+:2] = 8\'h43;
assign array2[1+:2] = 8\'h32;
assign array3[1-:2] = 8\'h21;
assign array3[3-:2] = 8\'h43;
assign array4[2-:2] = 8\'h32;
assign array5[1:0] = 8\'h21;
assign array5[3:2] = 8\'h43;
assign array6[2:1] = 8\'h32;
reg failed = 0;
initial begin
$display("%h", array1);
if (array1 !== 16\'h4321) failed = 1;
$display("%h", array2);
if (array2 !== 16\'hz32z) failed = 1;
$display("%h", array3);
if (array3 !== 16\'h4321) failed = 1;
$display("%h", array4);
if (array4 !== 16\'hz32z) failed = 1;
$display("%h", array5);
if (array5 !== 16\'h4321) failed = 1;
$display("%h", array6);
if (array6 !== 16\'hz32z) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that a complex base type (like a struct) of an array type gets
// evaluated in the right scope if the base type is defined in a different scope
// than the array type.
localparam A = 8;
typedef struct packed {
logic [A-1:0] x;
} Base;
module test;
localparam A = 4;
typedef Base T[1:0];
T x;
initial begin
x[0] = 8\'hff;
if (x[0] === 8\'hff) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
module main;
reg foo_reg;
byte foo_byte;
int foo_int;
shortint foo_shortint;
longint foo_longint;
bit foo_bit;
bit [13:0] foo14_bit;
logic foo_logic;
logic [10:0] foo11_logic;
initial begin
if ($bits(foo_reg) != 1) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo_byte) != 8) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo_int) != 32) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo_shortint) != 16) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo_longint) != 64) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo_bit) != 1) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo14_bit) != 14) begin
\t $display("FAILED");
\t $finish;
end
\t if ($bits(foo_logic) != 1) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo11_logic) != 11) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Check that non-ANSI output ports that have a SystemVerilog data type are
// elaborated as variables and be assigned a value.
typedef struct packed { int x; } T1;
typedef enum { A } T2;
typedef T1 [1:0] T3;
module test1;
output reg a;
output reg [1:0] b;
output integer c;
output time d;
output bit e;
output logic f;
output shortint g;
output int h;
output longint i;
output real r;
output T1 x;
output T2 y;
output T3 z;
initial begin
a = \'0;
b = \'0;
c = \'0;
d = \'0;
e = \'0;
f = \'0;
g = \'0;
h = \'0;
r = 0.0;
x = \'0;
y = A;
z = \'0;
$display("PASSED");
end
endmodule
|
// test that if the port doesn't exist, an error is thrown
module m(input a, output b);
assign b = a;
endmodule
module top;
reg a;
wire b;
wire c;
m foo(.a, .b, .c);
endmodule
|
module test (
input\t\tclk_dma,
input\t\trst_dma_n,
input\t\twr_valid,
input\t\twr_trans,
input\t\twr_flush,
output\t\twr_ready);
wire buf_wr_wstrb;
assign buf_wr_wstrb = wr_ready && wr_valid;
assign wr_ready = wr_flush ;
endmodule
|
// pr1765789
module main;
reg [32:0] addr = {1\'b1, 32\'h0040_0000 + 32\'h8};
initial begin
#1 ;
if (addr !== 33\'h1_0040_0008) begin
\t $display("FAILED -- addr = %h", addr);
\t $finish;
end
if ($bits({32\'h0040_0000 + 32\'h8}) !== 32) begin
\t $display("FAILED -- bits count wrong");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module check (input signed [22:0] a, b, input signed [45:0] c);
wire signed [45:0] int_AB;
assign int_AB = a * b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB != c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg signed [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
end
#1 A = 0;
B = 0;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 0;
#1 A = -1;
#1 B = -1;
end
endmodule
module test;
wire signed [22:0] a, b;
wire signed [45:0] r;
stimulus stim (.A(a), .B(b));
smul23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#20000;
$display("PASSED");
$finish;
end
endmodule
|
`timescale 1ns/1ps
module test;
reg in, pass;
wire out;
assign #(1?2:1) out = in;
// assign #(1+1) out = in;
initial begin
pass = 1\'b1;
in = 1\'b0;
#1.999;
if (out !== 1\'bx) begin
$display("Failed signal at begining, expected 1\'bx, got %b", out);
pass = 1\'b0;
end
#0.002;
if (out !== in) begin
$display("Failed signal at end, expected %b, got %b", in, out);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate variable right shift in always
module main;
reg globvar;
reg [7:0] var1,var2,var3;
reg error;
reg [7:0] value;
always @(var1 or var2)
value = var1 >> var2;
initial
begin
error = 0;
#1 ;
var1 = 8\'h80;
var2 = 8\'h7;
#1;
if(value !== 8\'h1)
begin
error = 1;
\t$display ("FAILED - 80 >> 7 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h6;
#1;
if(value !== 8\'h2)
begin
error = 1;
\t$display ("FAILED - 80 >> 6 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h5;
#1;
if(value !== 8\'h4)
begin
error = 1;
\t$display ("FAILED - 80 >> 5 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h4;
#1;
if(value !== 8\'h8)
begin
error = 1;
\t$display ("FAILED - 80 >> 4 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h3;
#1;
if(value !== 8\'h10)
begin
error = 1;
\t$display ("FAILED - 80 >> 3 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h2;
#1;
if(value !== 8\'h20)
begin
error = 1;
\t$display ("FAILED - 80 >> 2 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h1;
#1;
if(value !== 8\'h40)
begin
error = 1;
\t$display ("FAILED - 80 >> 1 is %h",value);
end
#1 ;
var1 = 8\'h80;
var2 = 8\'h0;
#1;
if(value !== 8\'h80)
begin
error = 1;
\t$display ("FAILED - 80 >> 0 is %h",value);
end
#1 ;
var1 = 8\'ha5;
var2 = 8\'h7;
#1;
if(value !== 8\'h01)
begin
error = 1;
\t$display ("FAILED - a5 >> 7 is %h",value);
end
#1 ;
var1 = 8\'ha5;
var2 = 8\'h1;
#1;
if(value !== 8\'h52)
begin
error = 1;
\t$display ("FAILED - aa >> 1 is %h",value);
end
if(error === 0)
$display("PASSED");
end
endmodule // main
|
// This simple program tests that a variable can be assigned
// party by continuous assignment, and partly by behavioral
// assignment. As long as the parts don\'t overlap, this is
// legal (in SystemVerilog)
module main;
logic [3:0] foo;
// Part of the vector is assigned by continuous assignment
logic [1:0] bar;
assign foo[2:1] = bar;
initial begin
// Part of the vector is assigned behaviorally.
foo[0:0] = 1\'b1;
foo[3:3] = 1\'b1;
bar = 2\'b00;
#1 if (foo !== 4\'b1001) begin
\t $display("FAILED -- foo=%b", foo);
\t $finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule // main
|
// Copyright (c) 2014 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Basic test for the unbounded arrays in VHDL.
module vhdl_unbounded_array_test;
vhdl_unbounded_array dut();
initial begin
#1; // wait for signal assignment
if(dut.sig_logic != \'b01010101) begin
$display("FAILED 1");
$finish;
end
if(dut.sig_integer[2] != 1) begin
$display("FAILED 2");
$finish;
end
if(dut.sig_real[1] != 2.5) begin
$display("FAILED 3");
$finish;
end
$display("PASSED");
end
endmodule
|
module top;
lower #(0, 0, 1) dut();
endmodule
module lower;
parameter one = 0; // This should be \'sd0
parameter two = 0; // This should be \'sd0
parameter three = 0; // This should be \'sd1
parameter local1 = one - two; // This should be \'sd0
// This line is not working correctly.
// The 1 is not considered signed!
// local1 + 1 is giving \'d1 not \'sd1.
parameter local2 = local1+1-three; // This should be \'sd0
// Even this fails.
// parameter local2 = local1+\'sd1-three; // This should be \'sd0
initial begin
// This should be 2 < -1.
if (2 < local2-1) $display("FAILED");
else $display("PASSED");
end
endmodule
|
// From: Peter Monta <[email protected]>
// Subject: verilog: vvp bug, function or concat related?
// Message-Id: <[email protected]>
// Date: Thu, 26 Jul 2001 00:14:14 -0700 (PDT)
module main();
function [7:0] f;
input [7:0] r;
f = {
r[0]^r[1]^r[2]^r[3]^r[7],
r[3]^r[6]^r[7],
r[2]^r[5]^r[6],
r[1]^r[4]^r[5]^r[7],
r[0]^r[3]^r[4]^r[6]^r[7],
r[0]^r[1]^r[5]^r[6],
r[1]^r[2]^r[3]^r[4]^r[5],
r[0]^r[1]^r[2]^r[3]^r[4] };
endfunction
reg [7:0] data_in;
reg [7:0] r;
reg start_in;
initial begin
data_in = 8\'h23;
r = 0;
start_in = 0;
#2;
r <= #1 start_in ? 0 : f(data_in);
#2;
$display("%b",r);
if (r === 8\'b00101100)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
function int a_func (input int id);
a_func = id;
endfunction
// This should print the following:
// This is func 2.
// This is func 1.
module top;
initial begin
$display("this is func %0d.", a_func(2));
$display("this is func %0d.", a_func(1));
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [7:0] x, y;
initial begin
x = -4;
if (x !== 8\'hfc) begin
\t $display("FAILED -- x = -4 --> %b", x);
\t $finish;
end
x = 4;
if (x !== 8\'h04) begin
\t $display("FAILED");
\t $finish;
end
y = -x;
if (y !== 8\'hfc) begin
\t $display("FAILED -- y = -%b --> %b", x, y);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always # delay_value reg_lvalue = boolean_expr ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
reg err ;
initial
\tbegin
err = 0;
# 1;
if(value1 !== 4\'bxxxx)
begin
$display("FAILED - 3.1.4C - initial value not xxxx;\
");
err = 1;
end
#10 ;
if(value1 != 4\'h5)
begin
$display("FAILED - 3.1.4C - always # delay_value reg_lvalue = boolean_expr\
");
err = 1;
end
#10 ;
if(value1 != 4\'hA)
begin
$display("FAILED - 3.1.4C - always # delay_value reg_lvalue = boolean_expr\
");
err = 1;
end
if (err == 0)
$display("PASSED\
");
$finish;
end
always # 10 value1 = ~value1;
endmodule
|
// pr1868991
module test();
reg [31:0] mpr1[35-1:16];
reg [29:0] dtlreq_addr;
wire [7-1:0] select_mpr_inx = dtlreq_addr[7-1:0];
wire [31:0]\tselect_dcs_mpr = mpr1[select_mpr_inx];
integer\tidx;
initial begin
for (idx = 16 ; idx < 35 ; idx = idx+1)
\tmpr1[idx] = idx;
for (idx = 16 ; idx < 35 ; idx = idx+1) begin
\t dtlreq_addr = idx;
\t #1 if (select_dcs_mpr !== idx) begin
\t $display("FAILED - select_dcs_mpr=%d, idx=%d", select_dcs_mpr, idx);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule
|
module main;
reg [1:0] D0, D1;
reg\t sel;
wire [1:0] Q;
test_mux DUT(.\\S[1] (1\'b0), .\\S[0] (sel),
\t\t.\\D0[1] (D0[1]), .\\D0[0] (D0[0]),
\t\t.\\D1[1] (D1[1]), .\\D1[0] (D1[0]),
\t\t.\\Q[1] (Q[1]), .\\Q[0] (Q[0]));
initial begin
D0 = \'b01;
D1 = \'b10;
sel = 0;
#1 ;
if (Q !== D0) begin
\t $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q);
\t $finish;
end
sel = 1;
#1 ;
if (Q !== D1) begin
\t $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// pr1645277
module test;
initial main;
task main;
integer foo;
begin
\t foo = 0;
\t while(foo < 5) begin: inner
\t foo = foo + 1;
\t end
\t $write("expected %d; got %d\
", 5, foo);
end
endtask
endmodule
|
`begin_keywords "1364-2005"
`timescale 1ns / 1ns
module gentest;
reg [7:0] a=0, b=0;
wire co;
wire [7:0] result;
adder work(a, b, 1\'b0, result, co);
integer cc;
initial begin
\tfor (cc=0; cc<10; cc=cc+1) begin
\t\ta=a+1;
\t\t#10;
\t\t$display("%d %d %d", a, b, result);
\t\tb=result;
\tend
\tif (b==55) $display("PASSED");
\telse $display("FAIL");
end
endmodule
module adder(a, b, ci, out, co);
parameter SIZE=8;
input [SIZE-1:0] a;
input [SIZE-1:0] b;
input ci;
output [SIZE-1:0] out;
output co;
wire [SIZE:0] c;
assign c[0] = ci;
assign co = c[SIZE];
`ifdef NOGENERATE
\tadd1 bit0(a[0], b[0], c[0], out[0], c[0+1]);
\tadd1 bit1(a[1], b[1], c[1], out[1], c[1+1]);
\tadd1 bit2(a[2], b[2], c[2], out[2], c[2+1]);
\tadd1 bit3(a[3], b[3], c[3], out[3], c[3+1]);
\tadd1 bit4(a[4], b[4], c[4], out[4], c[4+1]);
\tadd1 bit5(a[5], b[5], c[5], out[5], c[5+1]);
\tadd1 bit6(a[6], b[6], c[6], out[6], c[6+1]);
\tadd1 bit7(a[7], b[7], c[7], out[7], c[7+1]);
`else
genvar i;
generate for(i=0; i<SIZE; i=i+1) begin:addbit
\tadd1 bit(a[i], b[i], c[i], out[i], c[i+1]);
end endgenerate
`endif
endmodule
module add1(a, b, ci, sum, co);
\tinput a, b, ci;
\toutput sum, co;
\tassign {co,sum} = a + b + ci;
endmodule
`end_keywords
|
/*
* Check the basic parsing.
*/
// A global timeunit and timeprecision are OK
timeunit 100us;
timeprecision 1us;
/*
* Check the various timeunit/precision combinations (this is valid SV syntax).
*/
// A local time unit is OK.
module check_tu;
timeunit 10us;
endmodule
// A local time precision is OK.
module check_tp;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK.
module check_tup;
timeunit 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK (check both orders).
module check_tpu;
timeprecision 10us;
timeunit 10us;
endmodule
/*
* Now do the same with repeat declarations (this is valid SV syntax).
*/
// A global timeunit and timeprecision are OK
timeunit 100us;
timeprecision 1us;
// A local time unit is OK.
module check_tu_d;
timeunit 10us;
timeunit 10us;
endmodule
// A local time precision is OK.
module check_tp_d;
timeprecision 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK.
module check_tup_d;
timeunit 10us;
timeprecision 10us;
timeunit 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK (check both orders).
module check_tpu_d;
timeprecision 10us;
timeunit 10us;
timeprecision 10us;
timeunit 10us;
endmodule
/*
* Now check all the valid timeunit and time precision values.
*/
module check_100s;
timeunit 100s;
timeprecision 100s;
endmodule
module check_10s;
timeunit 10s;
timeprecision 10s;
endmodule
module check_1s;
timeunit 1s;
timeprecision 1s;
endmodule
module check_100ms;
timeunit 100ms;
timeprecision 100ms;
endmodule
module check_10ms;
timeunit 10ms;
timeprecision 10ms;
endmodule
module check_1ms;
timeunit 1ms;
timeprecision 1ms;
endmodule
module check_100us;
timeunit 100us;
timeprecision 100us;
endmodule
module check_10us;
timeunit 10us;
timeprecision 10us;
endmodule
module check_1us;
timeunit 1us;
timeprecision 1us;
endmodule
module check_100ns;
timeunit 100ns;
timeprecision 100ns;
endmodule
module check_10ns;
timeunit 10ns;
timeprecision 10ns;
endmodule
module check_1ns;
timeunit 1ns;
timeprecision 1ns;
endmodule
module check_100ps;
timeunit 100ps;
timeprecision 100ps;
endmodule
module check_10ps;
timeunit 10ps;
timeprecision 10ps;
endmodule
module check_1ps;
timeunit 1ps;
timeprecision 1ps;
endmodule
module check_100fs;
timeunit 100fs;
timeprecision 100fs;
endmodule
module check_10fs;
timeunit 10fs;
timeprecision 10fs;
endmodule
module check_1fs;
timeunit 1fs;
timeprecision 1fs;
endmodule
module check1;
initial begin
$printtimescale(check_100s);
$printtimescale(check_10s);
$printtimescale(check_1s);
$printtimescale(check_100ms);
$printtimescale(check_10ms);
$printtimescale(check_1ms);
$printtimescale(check_100us);
$printtimescale(check_10us);
$printtimescale(check_1us);
$printtimescale(check_100ns);
$printtimescale(check_10ns);
$printtimescale(check_1ns);
$printtimescale(check_100ps);
$printtimescale(check_10ps);
$printtimescale(check_1ps);
$printtimescale(check_100fs);
$printtimescale(check_10fs);
$printtimescale(check_1fs);
$display("");
$printtimescale(check_tu);
$printtimescale(check_tp);
$printtimescale(check_tup);
$printtimescale(check_tpu);
$display("");
$printtimescale(check_tu_d);
$printtimescale(check_tp_d);
$printtimescale(check_tup_d);
$printtimescale(check_tpu_d);
end
endmodule
|
`define MERROR(code, msg) if (code == 0) begin $display(msg); end
module top;
integer return_code;
integer msg_out;
initial begin
// This shows that the macro is okay for the simple case
`MERROR(0, "This message works")
// This one gives a syntax error.
`MERROR($value$plusargs("msgOut=%d", msg_out), "This message does not work")
// This was a workaround
return_code = $value$plusargs("msgOut=%d", msg_out);
`MERROR(return_code, "This last message works")
$display("PASSED");
end
endmodule
|
module test();
reg a, b;
always @* begin // always @(b)
a = b;
$display("Triggered 1 at %0t", $time);
@*;
$display("Triggered 2 at %0t", $time);
end
initial begin
#10 a = 0;
#10 a = 1;
#10 b = 0;
#10 b = 1;
#10 $finish(0);
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always # delay_value reg_lvalue = constant ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
\tbegin
# 1;
if(value1 != 4\'bxxxx)
$display("FAILED - 3.1.4B - initial value not xxxx;\
");
#15 ;
if(value1 != 4\'h5)
$display("FAILED - 3.1.4B - always # delay_value reg_lvalue = constant\
");
else
begin
$display("PASSED\
");
\t $finish;
end
end
always # 10 value1 = 4\'h5;
endmodule
|
module test2 ();
reg [1:0] d;
always @(posedge |d) begin
$display ("PASSED");
end
initial begin
d=0;
# 1;
d=6\'b01;
end
endmodule
|
module check (input unsigned [22:0] a, b, c);
wire [22:0] int_AB;
assign int_AB = ~(a | b);
always @(a, b, int_AB, c) begin
#1;
if (int_AB != c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
end
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [22:0] r;
stimulus stim (.A(a), .B(b));
nor23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#20000;
$display("PASSED");
$finish;
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always 3.1.1A always reg_lvalue = constant ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
always begin
#0; #0; #0;
end
always value1 = 4\'h5 ;
initial
if(value1 != 4\'h5)
\t$display("FAILED - 3.1.1A always reg_lvalue = constant\
");
else
\tbegin
$display("PASSED\
");
\t $finish;
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous sub in assignment..dependent on always - working
//
module main;
reg globvar;
reg [3:0] var1,var2,var3;
wire [3:0] var3a;
reg error;
assign var3a = var1 - var2;
always @( var1 or var2)
var3 = var1 - var2 ;
initial
begin
error = 0;
for ( var1 = 4\'b0; var1 != 4\'hf; var1 = var1 + 1)
for ( var2 = 4\'b0; var2 != 4\'hf; var2 = var2 + 1)
begin
#1 ;
if(var3 !== var3a)
begin
#1 ;
error = 1;
end
#1;
end
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
`timescale 1ns/1ps
//`define DEBUG
module top;
parameter length = 34;
parameter str = "%s";
reg [length*8-1:0] result, fmt;
integer val = 1000;
reg [31:0] eval, uval, zval;
reg [63:0] hval, sval;
real rval = 1234.567;
wire net;
time tm = 234567;
realtime rtm = 2345.678;
reg failed;
`ifdef DEBUG
integer lp;
`endif
assign (pull1, strong0) net = 1\'b1;
task check_result;
input [length*8-1:0] result, value;
input [80*8-1:0] message;
if (result != value) begin
$display("%0s", message);
$display("Got :%s:", result);
$display("Wanted :%s:", value);
`ifdef DEBUG
for (lp=0; lp<length; lp=lp+1) begin
$display("%d - %d, %d", lp, result[lp*8 +: 8], value[lp*8 +: 8]);
end
`endif
failed = 1;
end
endtask
initial begin
$timeformat(-12, 4, " ps", 20);
fmt = "%s";
failed = 0;
// Determine the endian order.
$swrite(result, "%u", "Help");
if (result != "\\000Help") begin
// Big endian so reverse the bytes.
eval = 32\'h22000000;
hval = 64\'h206d652148656c70;
uval = 32\'b010010xz_01100101_01101100_01110000;
zval = 32\'b01z01000_0xx0zx0x_0xx01x0z_01x1000z;
sval = " me!Help";
end else begin
// Little endian.
eval = 32\'h00000022;
hval = 64\'h21656d20706c6548;
uval = 32\'b01110000_01101100_01100101_010010xz;
zval = 32\'b01x1000z_0xx01x0z_0xx0zx0x_01z01000;
sval = "!em pleH";
end
#1;
// Basic variables and functions.
$swrite(result, val);
check_result(result, " 1000", "Decimal in $swrite failed!");
$swriteb(result, val);
check_result(result, "00000000000000000000001111101000",
"Decimal in $swriteb failed!");
$swriteo(result, val);
check_result(result, "00000001750", "Decimal in $swriteo failed!");
$swriteh(result, val);
check_result(result, "000003e8", "Decimal in $swriteo failed!");
$swrite(result, rval);
check_result(result, "1234.57", "Real in $swrite failed!");
$swrite(result, "Normal string.");
check_result(result, "Normal string.", "String in $swrite failed!");
$swrite(result, tm);
check_result(result, " 234567", "Time in $swrite failed!");
$swrite(result, rtm);
check_result(result, "2345.68", "Real time in $swrite failed!");
$swrite(result, $time);
check_result(result, " 1", "$time in $swrite failed!");
$swrite(result, $stime);
check_result(result, " 1", "$stime in $swrite failed!");
$swrite(result, $simtime);
check_result(result, " 1000", "$simtime in $swrite failed!");
$swrite(result, $realtime);
check_result(result, "1.000", "$realtime in $swrite failed!");
// %% and extra variables.
$swrite(result, "%%",, val);
check_result(result, "% 1000", "% and value in $swrite failed!");
// %b
$swrite(result, "%b", net);
check_result(result, "1", "%b in $swrite failed!");
$swrite(result, "%B", net);
check_result(result, "1", "%b in $swrite failed!");
$swrite(result, "%b", 8\'b00001001);
check_result(result, "00001001", "%b in $swrite failed!");
$swrite(result, "%0b", 8\'b00001001);
check_result(result, "1001", "%0b in $swrite failed!");
$swrite(result, "%14b", 8\'b00001001);
check_result(result, " 00001001", "%14b in $swrite failed!");
$swrite(result, "%-14b", 8\'b00001001);
check_result(result, "00001001 ", "%-14b in $swrite failed!");
// %o
$swrite(result, "%o", 8\'b00001001);
check_result(result, "011", "%o in $swrite failed!");
$swrite(result, "%O", 8\'b00001001);
check_result(result, "011", "%O in $swrite failed!");
$swrite(result, "%0o", 8\'b00001001);
check_result(result, "11", "%0o in $swrite failed!");
$swrite(result, "%14o", 8\'b00001001);
check_result(result, " 011", "%14o in $swrite failed!");
$swrite(result, "%-14o", 8\'b00001001);
check_result(result, "011 ", "%-14o in $swrite failed!");
// %h
$swrite(result, "%h", 8\'b00001001);
check_result(result, "09", "%h in $swrite failed!");
$swrite(result, "%H", 8\'b00001001);
check_result(result, "09", "%H in $swrite failed!");
$swrite(result, "%0h", 8\'b00001001);
check_result(result, "9", "%0h in $swrite failed!");
$swrite(result, "%14h", 8\'b00001001);
check_result(result, " 09", "%14h in $swrite failed!");
$swrite(result, "%-14h", 8\'b00001001);
check_result(result, "09 ", "%-14h in $swrite failed!");
// %c
$swrite(result, "%c", "abcd");
check_result(result, "d", "%c in $swrite failed!");
$swrite(result, "%C", "abcd");
check_result(result, "d", "%C in $swrite failed!");
$swrite(result, "%4c", "abcd");
check_result(result, " d", "%4c in $swrite failed!");
$swrite(result, "%-4c", "abcd");
check_result(result, "d ", "%-4c in $swrite failed!");
// %d
$swrite(result, "%d", val);
check_result(result, " 1000", "%d in $swrite failed!");
$swrite(result, "%D", val);
check_result(result, " 1000", "%D in $swrite failed!");
$swrite(result, "%d", length);
`ifdef OLD_UNSIZED
check_result(result, " 34", "%d in $swrite failed!");
`else
check_result(result, " 34", "%d in $swrite failed!");
`endif
$swrite(result, "%d", 31);
`ifdef OLD_UNSIZED
check_result(result, " 31", "%d in $swrite failed!");
`else
check_result(result, " 31", "%d in $swrite failed!");
`endif
$swrite(result, "%d", $unsigned(31));
`ifdef OLD_UNSIZED
check_result(result, "31", "%d in $swrite failed!");
`else
check_result(result, " 31", "%d in $swrite failed!");
`endif
$swrite(result, "%0d", val);
check_result(result, "1000", "%0d in $swrite failed!");
$swrite(result, "%+d", val);
check_result(result, " +1000", "%+d in $swrite failed!");
$swrite(result, "%14d", val);
check_result(result, " 1000", "%14d in $swrite failed!");
$swrite(result, "%-14d", val);
check_result(result, "1000 ", "%-14d in $swrite failed!");
// %e
$swrite(result, "%e", rval);
check_result(result, "1.234567e+03", "%e in $swrite failed!");
$swrite(result, "%E", rval);
check_result(result, "1.234567E+03", "%E in $swrite failed!");
$swrite(result, "%+e", rval);
check_result(result, "+1.234567e+03", "%+e in $swrite failed!");
$swrite(result, "%14.3e", rval);
check_result(result, " 1.235e+03", "%14.3e in $swrite failed!");
$swrite(result, "%-14.3e", rval);
check_result(result, "1.235e+03 ", "%-14.3e in $swrite failed!");
// %f
$swrite(result, "%f", rval);
check_result(result, "1234.567000", "%f in $swrite failed!");
$swrite(result, "%F", rval);
check_result(result, "1234.567000", "%F in $swrite failed!");
$swrite(result, "%+f", rval);
check_result(result, "+1234.567000", "%+f in $swrite failed!");
$swrite(result, "%14.3f", rval);
check_result(result, " 1234.567", "%14.3f in $swrite failed!");
$swrite(result, "%-14.3f", rval);
check_result(result, "1234.567 ", "%-14.3f in $swrite failed!");
// %g
$swrite(result, "%g", rval);
check_result(result, "1234.57", "%g in $swrite failed!");
$swrite(result, "%G", rval);
check_result(result, "1234.57", "%G in $swrite failed!");
$swrite(result, "%+g", rval);
check_result(result, "+1234.57", "%+g in $swrite failed!");
$swrite(result, "%14.3g", rval);
check_result(result, " 1.23e+03", "%14.3g in $swrite failed!");
$swrite(result, "%-14.3G", rval);
check_result(result, "1.23E+03 ", "%-14.3G in $swrite failed!");
// %l is currently unsupported.
$swrite(result, "%l");
check_result(result, "<%l>", "%l in $swrite failed!");
$swrite(result, "%L");
check_result(result, "<%L>", "%L in $swrite failed!");
// %m
$swrite(result, "%m");
check_result(result, "top", "%m in $swrite failed!");
$swrite(result, "%M");
check_result(result, "top", "%M in $swrite failed!");
$swrite(result, "%8m");
check_result(result, " top", "%m in $swrite failed!");
$swrite(result, "%-8m");
check_result(result, "top ", "%m in $swrite failed!");
// %s
$swrite(result, "%s", "Hello");
check_result(result, "Hello", "%s in $swrite failed!");
$swrite(result, "%S", "Hello");
check_result(result, "Hello", "%S in $swrite failed!");
$swrite(result, str, "Hello");
check_result(result, "Hello", "%s in $swrite failed!");
$swrite(result, "%14s", "Hello");
check_result(result, " Hello", "%14s in $swrite failed!");
$swrite(result, "%-14s", "Hello");
check_result(result, "Hello ", "%-14s in $swrite failed!");
// %t
$swrite(result, "%t", 0);
check_result(result, " 0.0000 ps", "%t in $swrite failed!");
$swrite(result, "%t", 1);
check_result(result, " 1000.0000 ps", "%t in $swrite failed!");
$swrite(result, "%T", 1);
check_result(result, " 1000.0000 ps", "%T in $swrite failed!");
$swrite(result, "%t", 10_000);
check_result(result, " 10000000.0000 ps", "%t in $swrite failed!");
$swrite(result, "%t", $time);
check_result(result, " 1000.0000 ps", "%t $time in $swrite failed!");
// $swrite(result, "%t", $simtime);
// check_result(result, " 1000.0000 ps",
// "%t $simtime in $swrite failed!");
$swrite(result, "%-t", 1);
check_result(result, "1000.0000 ps ", "%-t in $swrite failed!");
$swrite(result, "%15t", 1);
check_result(result, " 1000.0000 ps", "%15t in $swrite failed!");
$swrite(result, "%-15t", 1);
check_result(result, "1000.0000 ps ", "%-15t in $swrite failed!");
$swrite(result, "%15.1t", 1);
check_result(result, " 1000.0 ps", "%15.1t in $swrite failed!");
// Real values.
$swrite(result, "%t", 1.1);
check_result(result, " 1100.0000 ps", "%t in $swrite failed!");
$swrite(result, "%t", $realtime);
check_result(result, " 1000.0000 ps",
"%t $realtime in $swrite failed!");
$swrite(result, "%-t", 1.1);
check_result(result, "1100.0000 ps ", "%-t in $swrite failed!");
$swrite(result, "%15t", 1.1);
check_result(result, " 1100.0000 ps", "%15t in $swrite failed!");
$swrite(result, "%-15t", 1.1);
check_result(result, "1100.0000 ps ", "%-15t in $swrite failed!");
$swrite(result, "%15.1t", 1.1);
check_result(result, " 1100.0 ps", "%15.1t in $swrite failed!");
// %u
$swrite(result, "%u", eval);
check_result(result, "\\"", "%u in $swrite failed!");
$swrite(result, "%U", eval);
check_result(result, "\\"", "%U in $swrite failed!");
$swrite(result, "%u", sval);
check_result(result, "Help me!", "%u in $swrite failed!");
// "Help me!"
$swrite(result, "%u", hval);
check_result(result, "Help me!", "%u in $swrite failed!");
// "Help" with check for correct x and z functionality.
$swrite(result, "%u", uval);
check_result(result, "Help", "%u in $swrite failed!");
// %v
$swrite(result, "%v", net);
check_result(result, "Pu1", "%v in $swrite failed!");
$swrite(result, "%V", net);
check_result(result, "Pu1", "%V in $swrite failed!");
$swrite(result, "%14v", net);
check_result(result, " Pu1", "%14v in $swrite failed!");
$swrite(result, "%-14v", net);
check_result(result, "Pu1 ", "%-14v in $swrite failed!");
// %z
$swrite(result, "%z", eval);
check_result(result, "\\"", "%z in $swrite failed!");
$swrite(result, "%Z", eval);
check_result(result, "\\"", "%Z in $swrite failed!");
// "Help me!", but because of NULLs we only get "Help"
$swrite(result, "%z", hval);
check_result(result, "Help", "%z in $swrite failed!");
// "Help me!" encoded using all the states!
$swrite(result, "%z", zval);
check_result(result, "Help me!", "%z in $swrite failed!");
// $sformat()
$sformat(result, "%s", "Hello world");
check_result(result, "Hello world", "String in $sformat failed!");
$sformat(result, str, "Hello world");
check_result(result, "Hello world", "Parameter in $sformat failed!");
$sformat(result, fmt, "Hello world");
check_result(result, "Hello world", "Register in $sformat failed!");
$sformat(result, "%s");
check_result(result, "<%s>", "$sformat missing argument failed!");
$sformat(result, "%s", "Hello world", 2);
check_result(result, "Hello world", "$sformat extra argument failed!");
if (!failed) $display("All tests passed.");
end
endmodule
|
module m;
reg [31:0] count = 0;
function void func1();
count++;
if (count < 10) func2();
endfunction
function void func2();
count++;
if (count < 10) func1();
endfunction
initial begin
func1();
if (count == 10)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* This tests the printing of a string stored in a reg, with leading blanks. */
module main;
reg [8*7:1] foo;
reg [7:0] tmp;
initial
begin
\tfoo = "PASSED";
\ttmp = foo[8*7:8*6+1];
\tif (tmp !== 8\'h00) begin
\t $display("FAILED -- high bits are %b", tmp);
\t $finish;
\tend
\t$display("%s", foo);
end
endmodule // main
|
module br918b();
wire [3:0] w;
assign (pull1,strong0) w[1:0] = 2\'b00;
assign (pull1,strong0) w[1:0] = 2\'b10;
assign (pull1,strong0) w[3:2] = 2\'b11;
assign (pull1,strong0) w[3:2] = 2\'b10;
initial begin
#1 $display("%b", w);
if (w === 4\'b1000)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
//
// Copyright (c) 2002 Philip Blundell <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Disable within named block.
//
module m();
initial
begin
#10;
$display("FAILED");
$finish;
end
task t;
begin
begin:wait_loop
#1;
while(1) begin
#1;
\t disable wait_loop;
end\t\t// while(1)
end\t\t\t// wait_loop
end
endtask
initial begin
t;
$display("PASSED");
$finish;
end
endmodule
|
module check (input unsigned [22:0] a, b, c);
wire unsigned [22:0] int_AB;
assign int_AB = a - b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB != c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
#1 A = 0;
B = 0;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 0;
#1 A = -1;
#1 B = 1;
#1 A = 1;
end
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [22:0] r;
stimulus stim (.A(a), .B(b));
usub23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#20000;
$display("PASSED");
$finish;
end
endmodule
|
module bug;
function [1:0] Copy;
input [1:0] Value;
begin
Copy = Value;
end
endfunction
integer i;
integer j;
reg [1:0] Expect;
reg [1:0] Actual;
reg Failed;
initial begin
Failed = 0;
for (i = 0; i < 4; i = i + 1) begin
for (j = 0; j < 4; j = j + 1) begin
Expect = (i%2)*2 + (j%2);
Actual = Copy((i%2)*2 + (j%2));
if (Actual !== Expect) begin
$display("Failed: %0d,%0d expected %0d, got %0d", i, j, Expect, Actual);
Failed = 1;
end
end
end
if (!Failed) $display("PASSED");
end
endmodule
|
// Check that declaring an integer typed variable for a signal that was previously
// declared as a real typed non-ANSI module port is an error.
module test(x);
output real x;
integer x;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always case ( reg_value) case_item1; case_item2; case_item3; endcase
// D:
module main ;
reg [3:0] value1,value2,value3;
initial
\tbegin
#0;
value3 = 0;
#3 ;\t\t\t\t\t// t=3
value1 = 4\'b0000 ;\t// Picked up at time 4
#5 ;\t\t\t\t // check at time 8
if(value2 != 4\'b0)
begin
$display("FAILED - always3.1.6A - case 0 at %t",$time);
value3 = 1;
end
#1 ;\t\t\t\t\t// Picked up at time 10
value1 = 4\'b0001 ;\t// Set at time 9.
#5 ;\t\t\t\t\t// Check at time 14
if(value2 != 4\'b0001)
begin
$display("FAILED - always3.1.6A - case 1 at %t",$time);
value3 = 1;
end
#1;\t\t\t\t\t// Picked up at time 16
value1 = 4\'b0010;\t// Changed at time 15.
#5;\t\t\t\t\t// Check at time 20...
if(value2 != 4\'b0010)
begin
$display("FAILED - always3.1.6A - case 2 at %t",$time);
value3 = 1;
end
#10;
if(value3 == 0)
$display("PASSED");
\t $finish;
end
always case (value1)
4\'b0000: begin
#3 ;
value2 = 4\'b0000 ;
#3 ;
end
4\'b0001: begin
#3 ;
value2 = 4\'b0001 ;
#3 ;
end
4\'b0010: begin
#3 ;
value2 = 4\'b0010 ;
#3 ;
end
default: #2 ;
endcase
endmodule
|
// Here are two examples of $strobe failing. It appears that thread data
// is being cleaned up too soon for the $strobe to access it.
module test;
reg[4:0] j;
reg [5:0] in [1:0];
wire [5:0] out;
assign out = in[j]; // This uses the current j.
initial begin
in[1] = 6\'b110001;
j = 1;
#1; // Need some delay for the calculations to run.
$display("out: %b, in[%0d] %b:", out, j, in[j]);
$display("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]);
// in[j] is what is failing.
$strobe("out: %b, in[%0d] %b:", out, j, in[j]);
// out[j... is what is failing.
$strobe("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]);
// #1; // Adding this will work around the bug.
end
endmodule
|
module top;
initial begin
// In SystemVerilog a function is not required to return a value or
// to take an argument.
test_fcn();
$display("PASSED");
end
function bit test_fcn();
test_fcn = 1\'b1;
endfunction
endmodule
|
module check (input unsigned [0:22] a, b, c);
wire [0:22] int_AB;
assign int_AB = a & b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB != c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [0:22] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i = i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
end
endmodule
module test;
wire unsigned [0:22] a, b;
wire unsigned [0:22] r;
stimulus stim (.A(a), .B(b));
rand23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#20000;
$display("PASSED");
$finish;
end
endmodule
|
package test_pkg;
class uvm_object;
function new ();
print("new uvm_object");
endfunction : new
virtual function void print (string str);
$display (str);
endfunction : print
endclass : uvm_object
class uvm_report_object extends uvm_object;
function new ();
print("new uvm_report_object");
endfunction : new
endclass : uvm_report_object
endpackage : test_pkg
module m;
import test_pkg::*;
uvm_report_object r_0;
uvm_object u_0;
initial begin : test
#100;
u_0 = new();
r_0 = new();
u_0.print("u_0");
r_0.print("r_0");
end : test
endmodule : m
|
//////////////////////////////////////////////////////////////////////////////
//
// using `timescale, test rounding up to specified precision and
// scaling to specified time unit
//
// run with
// iverilog lrm_eg.v
// vvp a.out
//
// (uncomment $display statements for help in debugging)
//
//////////////////////////////////////////////////////////////////////////////
`timescale 10 ns / 1 ns
module test;
reg set;
parameter d = 1.55;
reg fail;
reg [7:0] ii;
initial begin
fail = 0;
#d set = 0;
//$display("time in units of 10ns: %0t, in ns: %0d, set: %0b",$time,ii,set);
if((ii < 15) || (ii > 16)) fail = 1;
#d set = 1;
//$display("time in units of 10ns: %0t, in ns: %0d, set: %0b",$time,ii,set);
if((ii < 31) || (ii > 32)) fail = 1;
end
initial begin
//$dumpvars;
for(ii = 0; ii < 50; ii = ii + 1) begin
//$display("time in ns: %0d, set: %0b",ii,set);
#0.1;
end
$display("\
\\t\\t**********************************************");
if(fail) $display("\\t\\t********** timescale test FAILED *************");
else $display("\\t\\t********** timescale test PASSED *************");
$display("\\t\\t**********************************************\
");
$finish(0);
end
endmodule
|
module top;
reg a, pass;
wire x, y, ab;
assign (weak1, weak0) x = (a === 1\'b1) ? 1\'b0 : 1\'b1;
assign y = a;
// We need this since Icarus currently has a bug when forcing from
// an expression (it only uses the value when the force ran).
assign ab = ~a;
tran (x, y);
initial begin
// $monitor ($realtime,, x,y,,a);
pass = 1\'b1;
// Check matching values.
#1 if ( x !== 1\'bx || y !== 1\'bx) begin
$display("Failed initial value, expected 1\'bx, 1\'bx, got %b %b", x, y);
pass = 1\'b0;
end
#1 a = 1\'b0;
#1 if ( x !== 1\'b0 || y !== 1\'b0) begin
$display("Failed same value, expected 1\'b0, 1\'b0, got %b %b", x, y);
pass = 1\'b0;
end
#1 a = 1\'b1;
#1 if ( x !== 1\'b1 || y !== 1\'b1) begin
$display("Failed same value, expected 1\'b1, 1\'b1, got %b %b", x, y);
pass = 1\'b0;
end
// Check force with opposite values.
#1 force x = ab;
#1 if ( x !== 1\'b0 || y !== 1\'bx) begin
$display("Failed force value, expected 1\'b0, 1\'bx, got %b %b", x, y);
pass = 1\'b0;
end
#1 a = 1\'b0;
#1 if ( x !== 1\'b1 || y !== 1\'bx) begin
$display("Failed force value, expected 1\'b1, 1\'bx, got %b %b", x, y);
pass = 1\'b0;
end
// Now release.
#1 release x;
#1 if ( x !== 1\'b0 || y !== 1\'b0) begin
$display("Failed release value, expected 1\'b0, 1\'b0, got %b %b", x, y);
pass = 1\'b0;
end
#1 a = 1\'b1;
#1 if ( x !== 1\'b1 || y !== 1\'b1) begin
$display("Failed release value, expected 1\'b1, 1\'b1, got %b %b", x, y);
pass = 1\'b0;
end
// Now force and release the driving signal.
#1 force a = 1\'bx;
#1 if ( x !== 1\'bx || y !== 1\'bx) begin
$display("Failed driver value, expected 1\'bx, 1\'bx, got %b %b", x, y);
pass = 1\'b0;
end
#1 release a;
a = 1\'b0;
#1 if ( x !== 1\'b0 || y !== 1\'b0) begin
$display("Failed driver value, expected 1\'b0, 1\'b0, got %b %b", x, y);
pass = 1\'b0;
end
// Check that the other driver works.
#1 a = 1\'bz;
#1 if ( x !== 1\'b1 || y !== 1\'b1) begin
$display("Failed alt. value, expected 1\'b1, 1\'b1, got %b %b", x, y);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Check that declaring both a net and a variable for a signal that was
// previously declared as a non-ANSI module port is an error.
module test(x);
input x;
wire x;
reg x;
endmodule
|
module test();
localparam [7:0] dly1 = 4;
wire [7:0] dly2 = 3;
reg [7:0] dly3 = 2;
reg i;
wire [6:1] o;
assign #(dly1, dly2, dly3) o[1] = i;
assign #(dly2, dly3, dly1) o[2] = i;
assign #(dly3, dly1, dly2) o[3] = i;
assign #(dly2-1, dly2-2, dly2-3) o[4] = i;
assign #(dly3+1, dly3+2, dly3+3) o[5] = i;
assign #(4, 3, 2) o[6] = i;
function check(input o1, input o2, input o3, input o4, input o5, input o6);
begin
check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3)
&& (o[4] == o4) && (o[5] == o5) && (o[6] == o6);
end
endfunction
reg failed = 0;
initial begin
#1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);
i = 1\'b1;
#0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'b1, 1\'b1, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1;
i = 1\'b0;
#0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b0, 1\'b1, 1\'b1)) failed = 1;
#1; #0 if (!check(1\'b1, 1\'b0, 1\'b1, 1\'b0, 1\'b1, 1\'b1)) failed = 1;
#1; #0 if (!check(1\'b0, 1\'b0, 1\'b1, 1\'b0, 1\'b1, 1\'b0)) failed = 1;
#1; #0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0)) failed = 1;
i = 1\'bx;
#0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'bx, 1\'b0, 1\'b0)) failed = 1;
#1; #0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'bx, 1\'b0, 1\'b0)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'b0, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
i = 1\'bz;
#0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bz, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bz, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bz, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;
#1; #0 if (!check(1\'bz, 1\'bx, 1\'bx, 1\'bz, 1\'bx, 1\'bz)) failed = 1;
#1; #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bx, 1\'bz)) failed = 1;
#1; #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz)) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module mainp_tb;
reg clk=0;
integer usb_stream;
// reg [15:0] out_usb_stream;
always @(posedge clk) begin
// This should generate an error, not crash.
\t$fwrite(usb_stream, "%c", out_usb_stream[7:0]);
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test checks that times within modules are scaled up to the
* precision of the simulation.
*/
`timescale 100us / 1us
module slow (out);
output out;
reg\t out;
initial begin
#0 out = 0;
#1 out = 1;
end
endmodule // slow
`timescale 10us / 1us
module fast (out);
output out;
reg\t out;
initial begin
#0 out = 0;
#1 out = 1;
end
endmodule // fast
`timescale 1us / 1us
module main;
wire slow, fast;
slow m1 (slow);
fast m2 (fast);
initial begin
#5
\tif (slow !== 1\'b0) begin
\t $display("FAILED");
\t $finish;
\tend
if (fast !== 1\'b0) begin
\t $display("FAILED");
\t $finish;
\tend
#10
\tif (slow !== 1\'b0) begin
\t $display("FAILED");
\t $finish;
\tend
if (fast !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
\tend
#80
\tif (slow !== 1\'b0) begin
\t $display("FAILED");
\t $finish;
\tend
if (fast !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
\tend
#10
\tif (slow !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
\tend
if (fast !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
\tend
$display("PASSED");
end // initial begin
endmodule // main
|
// Check variable declarations in unnamed blocks
// All of these should pass in SystemVerilog and all but the last should fail in
// Verilog
module test;
initial begin
integer x;
end
initial begin
integer x;
integer y;
end
initial begin
integer x, y;
end
initial begin
integer x;
integer y;
x = y;
end
initial begin
$display("PASSED");
end
endmodule
|
/*
* This test program should cause the message "Hello, World" to
* display twice. The first when the always thread runs and gets
* stuck in the wait, and the second when the block is disabled,
* and the alwas thread starts it over again.
*/
module main;
always begin :restartable
$display("Test thread runs.");
wait (0);
$display("FAILED: Should never get here.");
end
initial begin
#10 disable restartable;
#10 $finish(0);
end
endmodule // main
|
// Check that out-of-bounds access on a 4-state vector queue works and returns
// the correct value.
module test;
logic [7:0] q[$];
logic [7:0] x;
initial begin
x = q[1];
if (x === 8\'hxx) begin
$display("PASSED");
end else begin
$display("FAILED. Expected xxxxxxxx, got %b", x);
end
end
endmodule
|
`timescale 1ns / 100ps
module main;
integer rc;
reg [7:0] x, y;
reg [23:0] z;
initial begin
rc = $sscanf("a b cd e", "%c %c %s", x, y, z);
if (rc !== 3) begin
\t $display("FAILED -- rc = %d", rc);
\t $finish;
end
if (x != \'h61) begin
\t $display("FAILED -- x=%h", x);
\t $finish;
end
if (y != \'h62) begin
\t $display("FAILED -- y=%h", y);
\t $finish;
end
if (z !== 24\'h00_63_64) begin
\t $display("FAILED == z=%h", z);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
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