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stringlengths 1
2.1M
|
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module bug();
reg flag1;
reg flag2;
task task1(inout integer flag);
begin
#4 flag = 1;
end
endtask
task task2(inout integer flag);
begin
#5 flag = 1;
end
endtask
task task3(inout flag1, inout flag2);
fork
task1(flag1);
task2(flag2);
join
endtask
initial begin
flag1 = 0;
flag2 = 0;
task3(flag1, flag2);
$display("flag1 = %d", flag1);
$display("flag2 = %d", flag2);
if ((flag1 === 1) && (flag2 === 1))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate function called from within function
module main ();
reg [31:0] val1,val2 ;
reg error;
function [31:0] myfunc2 ;
input [31:0] in2 ;
myfunc2 = in2;
endfunction
function [31:0] myfunc1 ;
input [31:0] in1 ;
myfunc1 = myfunc2(in1) ;
endfunction
initial
begin
error = 0;
val1 = myfunc1(32\'h0) ;
if(val1 != 32\'h0)
begin
$display("FAILED - function3.11C - function called from funct(1)");
error = 1;
end
val2 = 32\'h12345678 ;
val1 = myfunc1(val2);
if(val1 != val2)
begin
$display("FAILED - function3.11C - function called from funct(2)");
error = 1;
end
if(myfunc1(32\'h10101010) != 32\'h10101010)
begin
$display("FAILED - function3.11C - function called from funct(3)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
module test();
wire n0;
wire n1;
wire n2;
wire n3;
wire n4;
wand n5;
wor n6;
assign n1 = 1\'b0;
assign n2 = 1\'b1;
assign n3 = 1\'bx;
assign n4 = 1\'b0;
assign n4 = 1\'b0;
assign n4 = 1\'b1;
assign n4 = 1\'b1;
assign n4 = 1\'b1;
assign n4 = 1\'bx;
assign n5 = 1\'b0;
assign n5 = 1\'b0;
assign n5 = 1\'b0;
assign n5 = 1\'b1;
assign n5 = 1\'b1;
assign n5 = 1\'bx;
assign n6 = 1\'b0;
assign n6 = 1\'b1;
assign n6 = 1\'b1;
assign n6 = 1\'bx;
assign n6 = 1\'bx;
assign n6 = 1\'bx;
integer multi;
integer forced;
integer countD;
integer count0;
integer count1;
integer countX;
reg failed = 0;
task check_results;
input integer expected_multi;
input integer expected_forced;
input integer expected_countD;
input integer expected_count0;
input integer expected_count1;
input integer expected_countX;
begin
$write("multi = %0d ", multi);
if (multi !== expected_multi) failed = 1;
if (expected_forced != -1) begin
$write("forced = %0d ", forced);
if (forced !== expected_forced) failed = 1;
end
if (expected_countD != -1) begin
$write("countD = %0d ", countD);
if (countD !== expected_countD) failed = 1;
end
if (expected_count0 != -1) begin
$write("count0 = %0d ", count0);
if (count0 !== expected_count0) failed = 1;
end
if (expected_count1 != -1) begin
$write("count1 = %0d ", count1);
if (count1 !== expected_count1) failed = 1;
end
if (expected_countX != -1) begin
$write("countX = %0d ", countX);
if (countX !== expected_countX) failed = 1;
end
$write("\
");
end
endtask
initial begin
#0; // wait for initial values to propagate
// test undriven net
multi = $countdrivers(n0);
check_results(0, -1, -1, -1, -1, -1);
multi = $countdrivers(n0, forced);
check_results(0, 0, -1, -1, -1, -1);
multi = $countdrivers(n0, forced, countD);
check_results(0, 0, 0, -1, -1, -1);
multi = $countdrivers(n0, forced, countD, count0);
check_results(0, 0, 0, 0, -1, -1);
multi = $countdrivers(n0, forced, countD, count0, count1);
check_results(0, 0, 0, 0, 0, -1);
multi = $countdrivers(n0, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
force n0 = 1\'bx;
multi = $countdrivers(n0, forced, countD, count0, count1, countX);
check_results(0, 1, 0, 0, 0, 0);
// test net driven to 0
multi = $countdrivers(n1);
check_results(0, -1, -1, -1, -1, -1);
multi = $countdrivers(n1, forced);
check_results(0, 0, -1, -1, -1, -1);
multi = $countdrivers(n1, forced, countD);
check_results(0, 0, 1, -1, -1, -1);
multi = $countdrivers(n1, forced, countD, count0);
check_results(0, 0, 1, 1, -1, -1);
multi = $countdrivers(n1, forced, countD, count0, count1);
check_results(0, 0, 1, 1, 0, -1);
multi = $countdrivers(n1, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
force n1 = 1\'bx;
multi = $countdrivers(n1, forced, countD, count0, count1, countX);
check_results(0, 1, 1, 1, 0, 0);
// test net driven to 1
multi = $countdrivers(n2);
check_results(0, -1, -1, -1, -1, -1);
multi = $countdrivers(n2, forced);
check_results(0, 0, -1, -1, -1, -1);
multi = $countdrivers(n2, forced, countD);
check_results(0, 0, 1, -1, -1, -1);
multi = $countdrivers(n2, forced, countD, count0);
check_results(0, 0, 1, 0, -1, -1);
multi = $countdrivers(n2, forced, countD, count0, count1);
check_results(0, 0, 1, 0, 1, -1);
multi = $countdrivers(n2, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
force n2 = 1\'bx;
multi = $countdrivers(n2, forced, countD, count0, count1, countX);
check_results(0, 1, 1, 0, 1, 0);
// test net driven to X
multi = $countdrivers(n3);
check_results(0, -1, -1, -1, -1, -1);
multi = $countdrivers(n3, forced);
check_results(0, 0, -1, -1, -1, -1);
multi = $countdrivers(n3, forced, countD);
check_results(0, 0, 1, -1, -1, -1);
multi = $countdrivers(n3, forced, countD, count0);
check_results(0, 0, 1, 0, -1, -1);
multi = $countdrivers(n3, forced, countD, count0, count1);
check_results(0, 0, 1, 0, 0, -1);
multi = $countdrivers(n3, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 0, 1);
force n3 = 1\'bx;
multi = $countdrivers(n3, forced, countD, count0, count1, countX);
check_results(0, 1, 1, 0, 0, 1);
// test multi-driven net
multi = $countdrivers(n4);
check_results(1, -1, -1, -1, -1, -1);
multi = $countdrivers(n4, forced);
check_results(1, 0, -1, -1, -1, -1);
multi = $countdrivers(n4, forced, countD);
check_results(1, 0, 6, -1, -1, -1);
multi = $countdrivers(n4, forced, countD, count0);
check_results(1, 0, 6, 2, -1, -1);
multi = $countdrivers(n4, forced, countD, count0, count1);
check_results(1, 0, 6, 2, 3, -1);
multi = $countdrivers(n4, forced, countD, count0, count1, countX);
check_results(1, 0, 6, 2, 3, 1);
force n4 = 1\'bx;
multi = $countdrivers(n4, forced, countD, count0, count1, countX);
check_results(1, 1, 6, 2, 3, 1);
// test wire and
multi = $countdrivers(n5);
check_results(1, -1, -1, -1, -1, -1);
multi = $countdrivers(n5, forced);
check_results(1, 0, -1, -1, -1, -1);
multi = $countdrivers(n5, forced, countD);
check_results(1, 0, 6, -1, -1, -1);
multi = $countdrivers(n5, forced, countD, count0);
check_results(1, 0, 6, 3, -1, -1);
multi = $countdrivers(n5, forced, countD, count0, count1);
check_results(1, 0, 6, 3, 2, -1);
multi = $countdrivers(n5, forced, countD, count0, count1, countX);
check_results(1, 0, 6, 3, 2, 1);
force n5 = 1\'bx;
multi = $countdrivers(n5, forced, countD, count0, count1, countX);
check_results(1, 1, 6, 3, 2, 1);
// test wire or
multi = $countdrivers(n6);
check_results(1, -1, -1, -1, -1, -1);
multi = $countdrivers(n6, forced);
check_results(1, 0, -1, -1, -1, -1);
multi = $countdrivers(n6, forced, countD);
check_results(1, 0, 6, -1, -1, -1);
multi = $countdrivers(n6, forced, countD, count0);
check_results(1, 0, 6, 1, -1, -1);
multi = $countdrivers(n6, forced, countD, count0, count1);
check_results(1, 0, 6, 1, 2, -1);
multi = $countdrivers(n6, forced, countD, count0, count1, countX);
check_results(1, 0, 6, 1, 2, 3);
force n6 = 1\'bx;
multi = $countdrivers(n6, forced, countD, count0, count1, countX);
check_results(1, 1, 6, 1, 2, 3);
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Validate always with OR, posedge constructs.
//
// D: New test used to validate always @(value), and
// D: always @(val1 or val2), and always @(posedge val1 or negedge val2)
// D: statements.
//
//
module main ();
reg working;
reg val1, val2, val3, val4, val5;
reg clock ;
reg test_var;
initial\t// Used to generate timing of events
begin
val2 = 0;
val3 = 0;
val4 = 1;
# 1;
test_var = 1;
# 1;
val1 = 1;\t\t// Cause a change in val1 -> test_var to 0.
# 2 ;\t\t// 4ns
test_var = 1;
# 1 ;\t\t// 5ns
val2 = 1;\t\t// Cause posedge on val2 -> test_var to 0
# 2;\t\t// 7ns
test_var = 1;
# 1;\t\t// 8ns
val4 = 0;\t\t// Cause negedge on val4 -> test_var to 0
# 2;\t\t// 10ns
test_var = 1;
# 1;\t\t// 11 ns
val3 = 1;\t\t// Cause val3 change for always @(a or b)
# 2;\t\t// 13 ns
test_var = 1;
# 1;\t\t// 14 ns
val5 = 1;\t\t// Cause val5 cahnge for always @(a or b)
# 2;\t\t// 16 ns
end
always @(val1)\t// Val1 changing clears test_var
test_var = 0;
always @(posedge val2 or negedge val4)
test_var = 0;
always @(val3 or val5)
test_var = 0;
initial // This is the validation block
begin
# 3;\t// 3 ns Check always @(val)
if(test_var)
begin
$display("FAILED - always @(val) wrong \
");
$finish ;
end
# 3;\t// 6 ns Check posedge of always @(posedge val or negedge)
if(test_var)
begin
$display("FAILED - posedge of always @(posedge or negedge) wrong \
");
$finish ;
end
# 3;\t// 9 ns Check negedge of always @(posedge val or negedge)
if(test_var)
begin
$display("FAILED - negedge of always @(posedge or negedge) wrong \
");
$finish ;
end
# 3;\t// 12 ns Check a of always @(a or b)
if(test_var)
begin
$display("FAILED - a of always @(a or b) wrong \
");
$finish ;
end
# 3;\t// 15 ns Check b of always @(a or b)
if(test_var)
begin
$display("FAILED - b of always @(a or b) wrong \
");
$finish ;
end
$display("PASSED\
");
$finish;
end
always @ (posedge clock)
working = 1;
always @ (negedge clock)
working = 1;
endmodule
|
// Check that out-of-bounds access on a string typed queue works and returns the
// right value.
module test;
string q[$];
string x;
initial begin
x = q[1];
if (x == "") begin
$display("PASSED");
end else begin
$display("FAILED. Expected \'\', got \'%s\'", x);
end
end
endmodule
|
module test ( a, b);
output a;
output reg [31:0] b;
reg [1:0] c;
assign a = (b == {16{c}});
initial begin
c = 2\'b01;
b = 32\'h55555555;
#1 if (a !== 1) begin
\t $display("FAILED -- a=%b, b=%h, c=%b", a, b, c);
\t $finish;
end
b = 32\'haaaaaaaa;
#1 if (a !== 0) begin
\t $display("FAILED -- a=%b, b=%h, c=%b", a, b, c);
\t $finish;
end
$display("PASSED");
end
endmodule
|
// This example is rediculous, but legal. However, Icarus Verilog will print
// various warnings about this. The warnings are OK, but Issue#576 saw this
// program assert, which is worse.
module test;
function void fun;
begin
\t $display("PASSED");
\t $finish;
end
endfunction // fun
always_comb fun;
endmodule
|
// This tests SystemVerilog packages
//
// This tests the elaboration infrastructure of packages in
// SystemVerilog. It actually covers a fair number of features,
// given the small size of the program:
//
// *) Parsing of package blocks and import statements
// *) Manage scope of names in package
// *) Actual references of imported names from packages.
//
package pkg;
parameter int foo = 1;
endpackage
module test ();
// import all from p1
//import pkg::foo;
initial begin
$display("pkg::foo = %0d", pkg::foo);
if (pkg::foo != 1) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // test
|
module test();
integer i = 1;
initial begin
assert(i == 1);
assert(i == 0);
assert(i == 1) else $display("Check 3 : this shouldn\'t be displayed");
assert(i == 0) else $display("Check 4 : this should be displayed");
assert(i == 1) $display("Check 5 : this should be displayed");
assert(i == 0) $display("Check 6 : this shouldn\'t be displayed");
assert(i == 1) $display("Check 7 : this should be displayed");
else $display("Check 7 : this shouldn\'t be displayed");
assert(i == 0) $display("Check 8 : this shouldn\'t be displayed");
else $display("Check 8 : this should be displayed");
end
endmodule
|
module top;
logic clk = 0;
int cnt = 0;
always @(posedge clk) begin
fork begin
#(10*2); // Wait 10 clock periods
cnt++;
end
join_none
end
initial begin
$display("Starting test");
repeat (100) begin
#1 clk = 1;
#1 clk = 0;
end
#(10*2); // Wait 10 clock periods
$display("cnt = %0d", cnt);
if (cnt === 100)
$display("PASSED");
else
$display("FAILED");
$finish(0);
end
endmodule
|
//
// Copyright (c) 2000 Steve Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// function3.11E - Validate calling a task in a function causes an error.
//
module test ;
task foo2;
$display("insided foo2");
endtask
function [31:0] foo;
input [31:0] a;
foo = a;
foo2;
endfunction
reg [31:0] b;
initial
begin
$display("hi");
b = foo(123);
end
endmodule
|
// Regression test for GitHub issue #37
module test;
wire [5:0] a;
wire [15:0] y;
assign a = ~0;
assign y = 1 ? ~a >>> 5 : 0;
initial begin
#10 $display("%b", y);
if (y === 16\'b1111111111111110)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module test;
integer i;
initial begin
for (i = 0; i < 1000; i++) begin
$display("%h", $random);
end
end
endmodule
|
// Copyright (c) 2000 Stephen Williams ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// This tests DFF-like behavior. The clocked always block acts like a
// DFF, and if the -Fsynth flag to ivl is used, actually generates an
// LPM_FF device.
module main () ;
reg clk;
reg D, Q;
always #10 clk = ~clk;
always @(posedge clk) Q = D;
initial begin
clk = 0;
D = 0;
@(negedge clk)
if (Q !== 1\'b0)
begin
\t $display("FAILED: %b !== %b", Q, D);
\t $finish;
end
D = 1;
@(negedge clk)
if (Q !== 1\'b1)
begin
\t $display("FAILED: %b !== %b", Q, D);
\t $finish;
end
D = \'bx;
@(negedge clk)
if (Q !== 1\'bx)
begin
\t $display("FAILED: %b !== %b", Q, D);
\t $finish;
end
D = \'bz;
@(negedge clk)
if (Q !== 1\'bz)
begin
\t $display("FAILED: %b !== %b", Q, D);
\t $finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule
|
module top();
always @(sub.i) sub.j = sub.i;
initial begin:sub
static integer i = 1;
static integer j = 0;
#0 $display("%0d %0d", i, j);
if ((i === 1) && (j === 0))
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* Based on PR#564 */
module main( );
parameter [7:0] forwards = 8\'b11110001;
parameter [0:7] backwards = 8\'b10001111;
integer i;
initial begin
for (i = 0 ; i < 8 ; i = i + 1) begin
\t $write("forwards[%0d] === %b, ", i, forwards[i]);
\t $display("backwards[%0d] === %b", i, backwards[i]);
\t if (forwards[i] !== backwards[i]) begin
\t $display("FAILED -- forwards[%0d] !== backwards[%0d]", i, i);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
module top;
task foo();
$display("PASSED");
endtask
initial foo;
endmodule
|
module test;
reg [2:0] ptr;
reg [2:0] size;
reg [2:0] ptr_nxt;
always @*
begin
ptr_nxt = ptr;
if ( ptr + size > 3 )
begin
ptr_nxt = ptr + size - 3;
end
else
begin
ptr_nxt = 0;
end
end
initial
begin
#1;
ptr = 2;
size = 2;
#1
$write("ptr_nxt=%0d ptr=%0d size=%0d", ptr_nxt, ptr, size);
if ( ptr_nxt == 1 )
begin
$display(" OK");
end
else
begin
$display(" ERROR");
\t $finish;
end
ptr = 3;
size = 4;
#1
$write("ptr_nxt=%0d ptr=%0d size=%0d", ptr_nxt, ptr, size);
if ( ptr_nxt == 4 )
begin
$display(" OK");
end
else
begin
$display(" ERROR");
\t $finish;
end
ptr = 3;
size = 5;
#1
$write("ptr_nxt=%0d ptr=%0d size=%0d", ptr_nxt, ptr, size);
if ( ptr_nxt == 5 )
begin
$display(" OK");
end
else
begin
$display(" ERROR");
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule
|
`celldefine
//`timescale 1ns / 1ps
// Description : 2 input XOR
module XOR20 (input A, input B, output Q);
xor (Q,B,A);
specify
(A => Q) = (1,1);
(B => Q) = (1,1);
endspecify
endmodule
`endcelldefine
module tb;
reg a, b;
wire q;
XOR20 dut(.A(a), .B(b), .Q(q));
initial begin
$monitor($time,, "A=%b, B=%b, Q=%b", a, b, q);
$sdf_annotate("ivltests/sdf1.sdf");
#10 ;
a = 1;
b = 1;
#10 ;
b = 0;
#10 $finish(0);
end
endmodule // tb
|
// pr1691599b.v
//
module main;
parameter cnt = 4;
genvar i;
generate
for (i = 0; i < cnt; i = i+1) begin : target
\t reg [1:0] val;
end
endgenerate
initial begin
target[0].val = 0;
target[1].val = 1;
target[2].val = 2;
target[3].val = 3;
end
generate
for (i = 0; i < cnt; i = i+1) begin : sink
\t wire [1:0] val = target[i].val;
\t initial #1
\t if (val !== i) begin
\t $display("FAILED: sink[%0d].val = %b", i, val);
\t $finish;
\t end
end
endgenerate
initial #10 $display("PASSED");
endmodule // main
|
// Check that it is not possible to declare a variable in a package without an explicit data
// type for the variable.
pacakge P;
x; // This is a syntax error
endpackage
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for VHDL procedure calls
module vhdl_procedure_test;
logic run;
vhdl_procedure dut(run);
initial begin
run = 0;
#1 run = 1;
end
endmodule
|
/*
* This tests a trivial class. This tests that properties can be
* given types, and that the types behave properly.
*/
program main;
// Trivial example of a class
class foo_t ;
int signed a;
int unsigned b;
endclass : foo_t // foo_t
foo_t obj;
initial begin
obj = new;
// This is the most trivial assignment of class properties.
obj.a = \'hf_ffffffff;
obj.b = \'hf_ffffffff;
if (obj.a != -1 || obj.b != \'d4_294_967_295) begin
\t $display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
\t $finish;
end
obj.a = obj.a + 1;
obj.b = obj.b + 1;
if (obj.a != 0 || obj.b != 0) begin
\t $display("FAILED -- increment properties: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
\t $finish;
end
$display("PASSED");
$finish;
end
endprogram // main
|
module top;
wire real sml;
wire real big;
wire real prec;
assign sml = 1e-20;
assign big = 1e20;
assign prec = 0.123456789;
initial $display("big: %g, small: %g, precision: %0.11f", big, sml, prec);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous <= in assignment.
//
module main;
reg globvar;
reg [3:0] var1;
reg error;
wire var2 = (var1 == 4\'h02);
initial
begin
error = 0;
var1 = 4\'h0 ;
#1 ;
if(var2 != 1\'b0)
begin
$display("FAILED continuous <= logical op (1)");
error = 1;
end
#1 ;
var1 = 4\'h2;
#1 ;
if(var2 != 1\'b1)
begin
$display("FAILED continuos <= logical op (2)");
error = 1;
end
#1 ;
var1 = 4\'h4;
#1 ;
if(var2 != 1\'b0)
begin
$display("FAILED continuos <= logical op (3)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
module main;
reg [11:0] sum;
wire [10:0] a = 11\'b111_0000_0000;
wire [10:0] b = 11\'b000_0000_1111;
initial begin
#1 sum = $signed(a) + $signed(b);
if (sum == 12\'b1111_0000_1111)
$display("PASSED");
else
$display("failed: %b",sum);
$finish;
end
endmodule
|
module main;
shortint foo, bar = 10;
shortint wire_res;
shortint var_res;
assign wire_res = foo*bar;
initial begin
foo = 9;
var_res = foo * bar;
$display("%0d * %0d = %0d %0d", foo, bar, foo * bar, var_res);
if ((foo * bar) !== 90) begin
\t $display("FAILED");
\t $finish;
end
if (var_res !== 90) begin
\t $display("FAILED");
\t $finish;
end
#0; // allow CA to propagate
$display("%0d * %0d = %0d", foo, bar, wire_res);
if (wire_res !== 90) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Check that using a dynamic array type as the base type for an enum results in
// an error.
module test;
typedef logic T[];
enum T {
A
} e;
initial begin
$display("FAILED");
end
endmodule
|
// Copyright (c) 2006 Stephen Williams
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
parameter foo = 4\'b0101;
parameter str = "String Text";
initial begin
$listparams("foo", "str");
end
endmodule // main
|
// This tests the basic support for default arguments to task/function
// ports. The default port syntax gives SystemVerilog a limited form
// of variable argument lists.
program main;
class foo_t;
int int_val;
logic[3:0] log_val;
string text_val;
function new (int int_init, logic[3:0]log_init = 4\'bzzzz, string text_init = "default text");
\t this.init2(int_init, log_init, text_init);
endfunction : new
function void init2 (int int_init, logic[3:0]log_init, string text_init);
\t int_val = int_init;
\t log_val = log_init;
\t text_val = text_init;
endfunction : init2
endclass : foo_t
foo_t obj1;
initial begin
obj1 = new(4, 4\'b0101, "new text");
if (obj1.int_val != 4 || obj1.log_val !== 4\'b0101 || obj1.text_val != "new text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val);
\t $finish;
end
obj1 = new(5, , "new text");
if (obj1.int_val != 5 || obj1.log_val !== 4\'bzzzz || obj1.text_val != "new text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val);
\t $finish;
end
obj1 = new(6, 4\'b1010);
if (obj1.int_val != 6 || obj1.log_val !== 4\'b1010 || obj1.text_val != "default text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val);
\t $finish;
end
obj1 = new(7);
if (obj1.int_val != 7 || obj1.text_val != "default text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val);
\t $finish;
end
$display("PASSED");
end
endprogram // main
|
/*
* This is a reduced example from comp1001 to demonstrate a problem
* in the Icarus Verilog code generator. If the left && argument is
* replaced with a single 1\'b1 which should be logically equivalent
* this will work correctly. It appears that the width of the
* expression is being calculated incorrectly.
*/
module top;
reg [119:110] r163;
reg [192:162] r222;
initial begin
r163 = 10\'h17d;
r222 = (1\'b1 + (22\'h3a15 && ((^r163) < 4\'h8))) != 1\'bx;
// ... the subexpression ^r163 is the 1-bit value 1\'b1
// = (1\'b1 + (22\'h3a15 && ((1\'b1) < 4\'h8))) != 1\'bx
// ... the operands of && are self determined, but the widths of the
// operands of < must match
// = (1\'b1 + (22\'h3a15 && (4\'h1 < 4\'h8))) != 1\'bx
// ... The && is a 1\'bit result.
// = (1\'b1 + 1\'b1) != 1\'bx
// ... Operands of != are sized to max of i and j, namely 1 in this case.
// = 1\'b0 != 1\'bx
// = 1\'bx
// ... but the result is 31 bits, so the result is...
// = 31\'b0x
if (r222 !== 31\'b0x) $display("FAILED -- r222=%b", r222);
else $display("PASSED");
end
endmodule
|
module top;
integer in;
initial begin
in = 2;
if ($clog2(in) != 1) $display("FAILED");
else $display("PASSED");
end
endmodule
|
`define DEF1 "string1"
`define DEF2 "string2\\""
`define DEF3 a\\b
`define DEF4(a) a
module top;
initial begin
$display("Using ``celldefine gives: %s", ``celldefine);
$display("Plain ``celldefine gives: ", ``celldefine);
$display("Using `DEF1 gives: %s", `DEF1);
$display("Using ``DEF1 gives: %s", ``DEF1);
$display("Plain ``DEF1 gives: ", ``DEF1);
$display("Using `DEF2 gives: %s", `DEF2);
$display("Using ``DEF2 gives: %s", ``DEF2);
$display("Plain ``DEF2 gives: ", ``DEF2);
$display("Using ``DEF3 gives: %s", ``DEF3);
$display("Plain ``DEF3 gives: ", ``DEF3);
$display("Using ``DEF4(\\"tmp\\") gives: %s", ``DEF4("tmp"));
$display("Plain ``DEF4(\\"tmp\\") gives: ", ``DEF4("tmp"));
end
endmodule
|
function int f (int arg);
begin:b // comment to remove bug
int i;
f = 0;
for (i=0; i<arg; i++)
f += i;
end\t // comment to remove bug
endfunction
module bug;
int sum;
assign sum = f(10);
initial begin
#0 $display("sum = %0d", sum);
if (sum === 45)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// pr1913918
module test();
parameter a = 4\'b1000;
b b(a[3]);
endmodule // test
module b(c);
input c;
initial #1 begin
if (c !== 1\'b1) begin
\t $display("FAILED -- c = %b", c);
\t $finish;
end
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
test tt();
defparam tt.foo = 4;
endmodule // main
module test;
parameter foo = 10;
reg [foo-1:0] bar;
initial begin
if ($bits(bar) != 4) begin
\t $display("FAILED -- $bits(bar) = %d", $bits(bar));
\t $finish;
end
$display("PASSED");
end
endmodule // test
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always #1 disable task_identifier ;
module main ;
reg [3:0] value1 ;
task foo ;
value1 = #2 1;
endtask
initial
begin
value1 = 1\'b0;
#5;
foo ;
#4 ;
if(value1 === 1\'b0)
$display("PASSED");
else
$display("FAILED - always3.1.9C always #2 disable foo");
$finish ;
end
always #6 disable foo ;
endmodule
|
module top;
reg [8*80-1:0] str;
integer fd, pos, result;
initial begin
fd = $fopen("ivltests/pr1819452.txt","rb");
result = $fgets(str, fd);
while (!$feof(fd)) begin
pos = $ftell(fd);
$display("Found: %5s currently at byte %0d", str[8*10-1:8], pos);
result = $fgets(str, fd);
end
result = $rewind(fd);
result = $fgets(str, fd);
pos = $ftell(fd);
$display("Found: %5s currently at byte %0d", str[8*10-1:8], pos);
result = $fseek(fd, 0, 0);
result = $fgets(str, fd);
pos = $ftell(fd);
$display("Found: %5s currently at byte %0d", str[8*10-1:8], pos);
result = $fseek(fd, -3, 2);
result = $fgets(str, fd);
pos = $ftell(fd);
$display("Found: %5s currently at byte %0d", str[8*10-1:8], pos);
result = $fseek(fd, -6, 1);
result = $fgets(str, fd);
pos = $ftell(fd);
$display("Found: %5s currently at byte %0d", str[8*10-1:8], pos);
result = $fseek(32\'hffffffff, 0, 0);
$display("Check fseek EOF = %0d", result);
result = $ftell(32\'hffffffff);
$display("Check ftell EOF = %0d", result);
result = $rewind(32\'hffffffff);
$display("Check rewind EOF = %0d", result);
$fclose(fd);
end
endmodule
|
/* pr1636409 */
module top;
wire [3:0] fail, good;
wire eni;
reg [2:0] rg;
reg in, en, clk;
assign #1 eni = en;
assign #1 fail = (eni) ? {rg,in} : \'b0;
assign #1 good = {4{eni}} & {rg,in};
always @(fail or good or eni) begin
$strobe("fail=%b, good=%b, en=%b at %0t", fail, good, eni, $time);
end
always #10 clk = ~clk;
always @(posedge clk) begin
en = ~en;
in = ~in;
rg = ~rg;
end
initial begin
// $dumpfile("results.vcd");
// $dumpvars(0, top);
clk = 0;
en = 0;
in = 0;
rg = 3\'b101;
#50 $finish(0);
end
endmodule
|
module main;
typedef struct packed {
logic [3:0] high;
logic [3:0] low;
} word;
typedef word [1:0] dword;
wire\t\t dword foo;
int\t\t idx;
assign foo[0].low = 1;
assign foo[0].high = 2;
assign foo[1].low = 3;
assign foo[1].high = 4;
initial begin
#1 $display("foo = %h", foo);
if (foo !== 16\'h4321) begin
\t $display("FAILED -- foo=%h", foo);
\t $finish;
end
$display("foo[0] = %h", foo[0]);
if (foo[0] !== 8\'h21) begin
\t $display("FAILED -- foo[0]=%h", foo[0]);
\t $finish;
end
$display("foo[1] = %h", foo[1]);
if (foo[1] !== 8\'h43) begin
\t $display("FAILED -- foo[1]=%h", foo[1]);
\t $finish;
end
$display("foo[0].low = %h", foo[0].low);
if (foo[0].low !== 4\'h1) begin
$display("FAILED -- foo[0].low=%h", foo[0].low);
\t $finish;
end
$display("foo[0].high = %h", foo[0].high);
if (foo[0].high !== 4\'h2) begin
$display("FAILED -- foo[0].high=%h", foo[0].high);
\t $finish;
end
$display("foo[1].low = %h", foo[1].low);
if (foo[1].low !== 4\'h3) begin
$display("FAILED -- foo[1].low=%h", foo[1].low);
\t $finish;
end
$display("foo[1].high = %h", foo[1].high);
if (foo[1].high !== 4\'h4) begin
$display("FAILED -- foo[1].high=%h", foo[1].high);
\t $finish;
end
idx = 0;
$display("foo[idx=0].low = %h", foo[idx].low);
if (foo[idx].low !== 4\'h1) begin
$display("FAILED -- foo[0].low=%h", foo[idx].low);
\t $finish;
end
idx = 1;
$display("foo[idx=1].high = %h", foo[idx].high);
if (foo[idx].high !== 8\'h4) begin
\t $display("FAILED -- foo[1].high=%h", foo[idx].high);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module main;
reg foo_reg;
byte foo_byte;
int foo_int;
shortint foo_shortint;
longint foo_longint;
initial begin
if ($bits(foo_reg) != 1) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo_byte) != 8) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo_int) != 32) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo_shortint) != 16) begin
\t $display("FAILED");
\t $finish;
end
if ($bits(foo_longint) != 64) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* See pr245 in the ivtest test suite.
*/
`timescale 1ns/1ns
module t;
wire [11:0] iodata;
integer i;
initial
begin
$timeformat(-9,0,"ns",5);
\t$display(" TIME:IOD");
\t$monitor( "%7t:%3x",
\t\t $time,iodata);
\t#0
\t force iodata =0;
\tfor (i=0; i<512;i=i+1)
\t #10
\t force iodata =i;
end // initial begin
endmodule // t
|
// Check that using a type identifier that resolves to a type with multiple
// packed dimensions as the base type for an enum results in an error.
module test;
typedef bit [1:0][1:0] T;
enum T {
A
} e;
initial begin
$display("FAILED");
end
endmodule
|
// Check that it is not possible to assign a dynamic array with different
// element type width.
module test;
int d1[];
shortint d2[];
initial begin
d1 = d2;
$dispaly("FAILED");
end
endmodule
|
module main;
wire out;
reg [1:0] A, B;
ge2 dut(.out(out), .A(A), .B(B));
initial begin
A = 0;
B = 0;
#1 $display("%b >= %b: %b", A, B, out);
B = 1;
#1 $display("%b >= %b: %b", A, B, out);
B = 2;
#1 $display("%b >= %b: %b", A, B, out);
B = 3;
#1 $display("%b >= %b: %b", A, B, out);
A = 1;
B = 0;
#1 $display("%b >= %b: %b", A, B, out);
B = 1;
#1 $display("%b >= %b: %b", A, B, out);
B = 2;
#1 $display("%b >= %b: %b", A, B, out);
B = 3;
#1 $display("%b >= %b: %b", A, B, out);
A = 2;
B = 0;
#1 $display("%b >= %b: %b", A, B, out);
B = 1;
#1 $display("%b >= %b: %b", A, B, out);
B = 2;
#1 $display("%b >= %b: %b", A, B, out);
B = 3;
#1 $display("%b >= %b: %b", A, B, out);
A = 3;
B = 0;
#1 $display("%b >= %b: %b", A, B, out);
B = 1;
#1 $display("%b >= %b: %b", A, B, out);
B = 2;
#1 $display("%b >= %b: %b", A, B, out);
B = 3;
#1 $display("%b >= %b: %b", A, B, out);
end // initial begin
endmodule // main
|
module top;
reg pass;
reg result;
reg [3:0] expr;
initial begin
pass = 1\'b1;
result = $onehot0(1\'b0);
if (result != 1) begin
$display("FAILED: for 1\'b0 expected 1, got %b", result);
pass = 1\'b0;
end
result = $onehot0(1\'b1);
if (result != 1) begin
$display("FAILED: for 1\'b1 expected 1, got %b", result);
pass = 1\'b0;
end
result = $onehot0(2\'b01);
if (result != 1) begin
$display("FAILED: for 2\'b01 expected 1, got %b", result);
pass = 1\'b0;
end
result = $onehot0(4\'b0x11);
if (result != 0) begin
$display("FAILED: for 4\'b0x11 expected 0, got %b", result);
pass = 1\'b0;
end
expr = 4\'b1100;
result = $onehot0(expr);
if (result != 0) begin
$display("FAILED: for 4\'b1100 expected 0, got %b", result);
pass = 1\'b0;
end
result = $onehot0(34\'b1100000000000000000000000000000001);
if (result != 0) begin
$display("FAILED: for 34\'1100000000000000000000000000000001 expected 0, got %b", result);
pass = 1\'b0;
end
result = $onehot0(34\'b1000000000000000000000000000000000);
if (result != 1) begin
$display("FAILED: for 34\'1000000000000000000000000000000000 expected 1, got %b", result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module top;
reg pass = 1\'b1;
generate
genvar n;
for (n=0; n<4; n=n+1) begin : loop
reg [2:0] r = n; // This fails.
// wire [2:0] r = n; // This works.
end
endgenerate
initial begin
#1;
if (loop[0].r !== 0) begin
$display("Failed generate instance 0");
pass = 1\'b0;
end
if (loop[1].r !== 1) begin
$display("Failed generate instance 1");
pass = 1\'b0;
end
if (loop[2].r !== 2) begin
$display("Failed generate instance 2");
pass = 1\'b0;
end
if (loop[3].r !== 3) begin
$display("Failed generate instance 3");
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module test;
typedef enum reg { FALSE = 1\'b0, TRUE = 1\'b1 } boolean;
boolean flag;
initial begin
#1 $display("%b", flag);
if (flag === TRUE)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module main;
reg flag;
reg [3:0] a, b;
wire [4:0] Q = flag? a : b;
initial begin
flag = 1;
a = 4\'b1010;
b = 4\'b0101;
#1 $display("%b = %b? %b : %b", Q, flag, a, b);
if (Q !== 5\'b01010) begin
\t $display("FAILED -- Q=%b, flag=%b, a=%b", Q, flag, a);
\t $finish;
end
flag = 0;
#1 if (Q !== 5\'b00101) begin
\t $display("FAILED -- Q=%b, flag=%b, b=%b", Q, flag, b);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Test unary operators in constant functions
module constfunc4();
function [7:0] LInv(input [7:0] x);
LInv = ~x;
endfunction
function [7:0] LNeg(input [7:0] x);
LNeg = -x;
endfunction
function real RNeg(input real x);
RNeg = -x;
endfunction
function LAnd(input [7:0] x);
LAnd = &x;
endfunction
function LNot(input [7:0] x);
LNot = !x;
endfunction
function RNot(input real x);
RNot = !x;
endfunction
localparam [7:0] ResultLInv = LInv(8\'h0f);
localparam [7:0] ResultLNeg = LNeg(8\'h0f);
localparam real ResultRNeg = RNeg(15.0);
localparam ResultLAnd = LAnd(8\'hff);
localparam ResultLNot = LNot(8\'h00);
localparam ResultRNot = RNot(0.0);
reg failed;
initial begin
failed = 0;
$display("%h", ResultLInv);
$display("%h", ResultLNeg);
$display("%g", ResultRNeg);
$display("%b", ResultLAnd);
$display("%b", ResultLNot);
$display("%b", ResultRNot);
if (ResultLNeg !== 8\'hf1) failed = 1;
if (ResultRNeg != -15.0) failed = 1;
if (ResultLAnd !== 1\'b1) failed = 1;
if (ResultLNot !== 1\'b1) failed = 1;
if (ResultRNot !== 1\'b1) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// This tests literal values, from verilog 2001 and SystemVerilog
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test ();
// logic vector
logic unsigned [15:0] luv; // logic unsigned vector
logic signed [15:0] lsv; // logic signed vector
// error counter
bit err = 0;
initial begin
// unsized literals without base
luv = \'0; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != \'0", luv); err=1; end
luv = \'1; if (luv !== 16\'b1111_1111_1111_1111) begin $display("FAILED -- luv = \'b%b != \'1", luv); err=1; end
luv = \'x; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != \'x", luv); err=1; end
luv = \'z; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != \'z", luv); err=1; end
// unsized binary literals single character
luv = \'b0; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != \'b0", luv); err=1; end
luv = \'b1; if (luv !== 16\'b0000_0000_0000_0001) begin $display("FAILED -- luv = \'b%b != \'b1", luv); err=1; end
luv = \'bx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != \'bx", luv); err=1; end
luv = \'bz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != \'bz", luv); err=1; end
// unsized binary literals two characters
luv = \'b00; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != \'b00", luv); err=1; end
luv = \'b11; if (luv !== 16\'b0000_0000_0000_0011) begin $display("FAILED -- luv = \'b%b != \'b11", luv); err=1; end
luv = \'bxx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != \'bxx", luv); err=1; end
luv = \'bzz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != \'bzz", luv); err=1; end
luv = \'b1x; if (luv !== 16\'b0000_0000_0000_001x) begin $display("FAILED -- luv = \'b%b != \'b1x", luv); err=1; end
luv = \'b1z; if (luv !== 16\'b0000_0000_0000_001z) begin $display("FAILED -- luv = \'b%b != \'b1z", luv); err=1; end
luv = \'bx1; if (luv !== 16\'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- luv = \'b%b != \'bx1", luv); err=1; end
luv = \'bz1; if (luv !== 16\'bzzzz_zzzz_zzzz_zzz1) begin $display("FAILED -- luv = \'b%b != \'bz1", luv); err=1; end
// unsized binary literals single character
luv = \'o0; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != \'o0", luv); err=1; end
luv = \'o5; if (luv !== 16\'b0000_0000_0000_0101) begin $display("FAILED -- luv = \'b%b != \'o5", luv); err=1; end
luv = \'ox; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != \'ox", luv); err=1; end
luv = \'oz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != \'oz", luv); err=1; end
// unsized binary literals two characters
luv = \'o00; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != \'o00", luv); err=1; end
luv = \'o55; if (luv !== 16\'b0000_0000_0010_1101) begin $display("FAILED -- luv = \'b%b != \'o55", luv); err=1; end
luv = \'oxx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != \'oxx", luv); err=1; end
luv = \'ozz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != \'ozz", luv); err=1; end
luv = \'o5x; if (luv !== 16\'b0000_0000_0010_1xxx) begin $display("FAILED -- luv = \'b%b != \'o5x", luv); err=1; end
luv = \'o5z; if (luv !== 16\'b0000_0000_0010_1zzz) begin $display("FAILED -- luv = \'b%b != \'o5z", luv); err=1; end
luv = \'ox5; if (luv !== 16\'bxxxx_xxxx_xxxx_x101) begin $display("FAILED -- luv = \'b%b != \'ox5", luv); err=1; end
luv = \'oz5; if (luv !== 16\'bzzzz_zzzz_zzzz_z101) begin $display("FAILED -- luv = \'b%b != \'oz5", luv); err=1; end
// unsized binary literals single character
luv = \'h0; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != \'h0", luv); err=1; end
luv = \'h9; if (luv !== 16\'b0000_0000_0000_1001) begin $display("FAILED -- luv = \'b%b != \'h9", luv); err=1; end
luv = \'hx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != \'hx", luv); err=1; end
luv = \'hz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != \'hz", luv); err=1; end
// unsized binary literals two characters
luv = \'h00; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != \'h00", luv); err=1; end
luv = \'h99; if (luv !== 16\'b0000_0000_1001_1001) begin $display("FAILED -- luv = \'b%b != \'h99", luv); err=1; end
luv = \'hxx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != \'hxx", luv); err=1; end
luv = \'hzz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != \'hzz", luv); err=1; end
luv = \'h9x; if (luv !== 16\'b0000_0000_1001_xxxx) begin $display("FAILED -- luv = \'b%b != \'h9x", luv); err=1; end
luv = \'h9z; if (luv !== 16\'b0000_0000_1001_zzzz) begin $display("FAILED -- luv = \'b%b != \'h9z", luv); err=1; end
luv = \'hx9; if (luv !== 16\'bxxxx_xxxx_xxxx_1001) begin $display("FAILED -- luv = \'b%b != \'hx9", luv); err=1; end
luv = \'hz9; if (luv !== 16\'bzzzz_zzzz_zzzz_1001) begin $display("FAILED -- luv = \'b%b != \'hz9", luv); err=1; end
// unsized binary literals single character
luv = \'d0; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != \'d0", luv); err=1; end
luv = \'d9; if (luv !== 16\'b0000_0000_0000_1001) begin $display("FAILED -- luv = \'b%b != \'d9", luv); err=1; end
luv = \'dx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != \'dx", luv); err=1; end
luv = \'dz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != \'dz", luv); err=1; end
// unsized binary literals two characters
luv = \'d00; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != \'d00", luv); err=1; end
luv = \'d99; if (luv !== 16\'b0000_0000_0110_0011) begin $display("FAILED -- luv = \'b%b != \'d99", luv); err=1; end
// luv = \'dxx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != \'dxx", luv); err=1; end
// luv = \'dzz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != \'dzz", luv); err=1; end
// unsized binary literals single character
luv = 15\'b0; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != 15\'b0", luv); err=1; end
luv = 15\'b1; if (luv !== 16\'b0000_0000_0000_0001) begin $display("FAILED -- luv = \'b%b != 15\'b1", luv); err=1; end
luv = 15\'bx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != 15\'bx", luv); err=1; end
luv = 15\'bz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != 15\'bz", luv); err=1; end
// unsized binary literals two characters
luv = 15\'b00; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != 15\'b00", luv); err=1; end
luv = 15\'b11; if (luv !== 16\'b0000_0000_0000_0011) begin $display("FAILED -- luv = \'b%b != 15\'b11", luv); err=1; end
luv = 15\'bxx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != 15\'bxx", luv); err=1; end
luv = 15\'bzz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != 15\'bzz", luv); err=1; end
luv = 15\'b1x; if (luv !== 16\'b0000_0000_0000_001x) begin $display("FAILED -- luv = \'b%b != 15\'b1x", luv); err=1; end
luv = 15\'b1z; if (luv !== 16\'b0000_0000_0000_001z) begin $display("FAILED -- luv = \'b%b != 15\'b1z", luv); err=1; end
luv = 15\'bx1; if (luv !== 16\'b0xxx_xxxx_xxxx_xxx1) begin $display("FAILED -- luv = \'b%b != 15\'bx1", luv); err=1; end
luv = 15\'bz1; if (luv !== 16\'b0zzz_zzzz_zzzz_zzz1) begin $display("FAILED -- luv = \'b%b != 15\'bz1", luv); err=1; end
// unsized binary literals single character
luv = 15\'o0; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != 15\'o0", luv); err=1; end
luv = 15\'o5; if (luv !== 16\'b0000_0000_0000_0101) begin $display("FAILED -- luv = \'b%b != 15\'o5", luv); err=1; end
luv = 15\'ox; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != 15\'ox", luv); err=1; end
luv = 15\'oz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != 15\'oz", luv); err=1; end
// unsized binary literals two characters
luv = 15\'o00; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != 15\'o00", luv); err=1; end
luv = 15\'o55; if (luv !== 16\'b0000_0000_0010_1101) begin $display("FAILED -- luv = \'b%b != 15\'o55", luv); err=1; end
luv = 15\'oxx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != 15\'oxx", luv); err=1; end
luv = 15\'ozz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != 15\'ozz", luv); err=1; end
luv = 15\'o5x; if (luv !== 16\'b0000_0000_0010_1xxx) begin $display("FAILED -- luv = \'b%b != 15\'o5x", luv); err=1; end
luv = 15\'o5z; if (luv !== 16\'b0000_0000_0010_1zzz) begin $display("FAILED -- luv = \'b%b != 15\'o5z", luv); err=1; end
luv = 15\'ox5; if (luv !== 16\'b0xxx_xxxx_xxxx_x101) begin $display("FAILED -- luv = \'b%b != 15\'ox5", luv); err=1; end
luv = 15\'oz5; if (luv !== 16\'b0zzz_zzzz_zzzz_z101) begin $display("FAILED -- luv = \'b%b != 15\'oz5", luv); err=1; end
// unsized binary literals single character
luv = 15\'h0; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != 15\'h0", luv); err=1; end
luv = 15\'h9; if (luv !== 16\'b0000_0000_0000_1001) begin $display("FAILED -- luv = \'b%b != 15\'h9", luv); err=1; end
luv = 15\'hx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != 15\'hx", luv); err=1; end
luv = 15\'hz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != 15\'hz", luv); err=1; end
// unsized binary literals two characters
luv = 15\'h00; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != 15\'h00", luv); err=1; end
luv = 15\'h99; if (luv !== 16\'b0000_0000_1001_1001) begin $display("FAILED -- luv = \'b%b != 15\'h99", luv); err=1; end
luv = 15\'hxx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != 15\'hxx", luv); err=1; end
luv = 15\'hzz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != 15\'hzz", luv); err=1; end
luv = 15\'h9x; if (luv !== 16\'b0000_0000_1001_xxxx) begin $display("FAILED -- luv = \'b%b != 15\'h9x", luv); err=1; end
luv = 15\'h9z; if (luv !== 16\'b0000_0000_1001_zzzz) begin $display("FAILED -- luv = \'b%b != 15\'h9z", luv); err=1; end
luv = 15\'hx9; if (luv !== 16\'b0xxx_xxxx_xxxx_1001) begin $display("FAILED -- luv = \'b%b != 15\'hx9", luv); err=1; end
luv = 15\'hz9; if (luv !== 16\'b0zzz_zzzz_zzzz_1001) begin $display("FAILED -- luv = \'b%b != 15\'hz9", luv); err=1; end
// unsized binary literals single character
luv = 15\'d0; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != 15\'d0", luv); err=1; end
luv = 15\'d9; if (luv !== 16\'b0000_0000_0000_1001) begin $display("FAILED -- luv = \'b%b != 15\'d9", luv); err=1; end
luv = 15\'dx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != 15\'dx", luv); err=1; end
luv = 15\'dz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != 15\'dz", luv); err=1; end
// unsized binary literals two characters
luv = 15\'d00; if (luv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- luv = \'b%b != 15\'d00", luv); err=1; end
luv = 15\'d99; if (luv !== 16\'b0000_0000_0110_0011) begin $display("FAILED -- luv = \'b%b != 15\'d99", luv); err=1; end
// luv = 15\'dxx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = \'b%b != 15\'dxx", luv); err=1; end
// luv = 15\'dzz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = \'b%b != 15\'dzz", luv); err=1; end
// unsized binary literals single character
lsv = \'sb0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != \'sb0", lsv); err=1; end
lsv = \'sb1; if (lsv !== 16\'b0000_0000_0000_0001) begin $display("FAILED -- lsv = \'b%b != \'sb1", lsv); err=1; end
lsv = \'sbx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != \'sbx", lsv); err=1; end
lsv = \'sbz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != \'sbz", lsv); err=1; end
// unsized binary literals two characters
lsv = \'sb00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != \'sb00", lsv); err=1; end
lsv = \'sb11; if (lsv !== 16\'b0000_0000_0000_0011) begin $display("FAILED -- lsv = \'b%b != \'sb11", lsv); err=1; end
lsv = \'sbxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != \'sbxx", lsv); err=1; end
lsv = \'sbzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != \'sbzz", lsv); err=1; end
lsv = \'sb1x; if (lsv !== 16\'b0000_0000_0000_001x) begin $display("FAILED -- lsv = \'b%b != \'sb1x", lsv); err=1; end
lsv = \'sb1z; if (lsv !== 16\'b0000_0000_0000_001z) begin $display("FAILED -- lsv = \'b%b != \'sb1z", lsv); err=1; end
lsv = \'sbx1; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- lsv = \'b%b != \'sbx1", lsv); err=1; end
lsv = \'sbz1; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzz1) begin $display("FAILED -- lsv = \'b%b != \'sbz1", lsv); err=1; end
// unsized binary literals single character
lsv = \'so0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != \'so0", lsv); err=1; end
lsv = \'so5; if (lsv !== 16\'b0000_0000_0000_0101) begin $display("FAILED -- lsv = \'b%b != \'so5", lsv); err=1; end
lsv = \'sox; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != \'sox", lsv); err=1; end
lsv = \'soz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != \'soz", lsv); err=1; end
// unsized binary literals two characters
lsv = \'so00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != \'so00", lsv); err=1; end
lsv = \'so55; if (lsv !== 16\'b0000_0000_0010_1101) begin $display("FAILED -- lsv = \'b%b != \'so55", lsv); err=1; end
lsv = \'soxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != \'soxx", lsv); err=1; end
lsv = \'sozz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != \'sozz", lsv); err=1; end
lsv = \'so5x; if (lsv !== 16\'b0000_0000_0010_1xxx) begin $display("FAILED -- lsv = \'b%b != \'so5x", lsv); err=1; end
lsv = \'so5z; if (lsv !== 16\'b0000_0000_0010_1zzz) begin $display("FAILED -- lsv = \'b%b != \'so5z", lsv); err=1; end
lsv = \'sox5; if (lsv !== 16\'bxxxx_xxxx_xxxx_x101) begin $display("FAILED -- lsv = \'b%b != \'sox5", lsv); err=1; end
lsv = \'soz5; if (lsv !== 16\'bzzzz_zzzz_zzzz_z101) begin $display("FAILED -- lsv = \'b%b != \'soz5", lsv); err=1; end
// unsized binary literals single character
lsv = \'sh0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != \'sh0", lsv); err=1; end
lsv = \'sh9; if (lsv !== 16\'b0000_0000_0000_1001) begin $display("FAILED -- lsv = \'b%b != \'sh9", lsv); err=1; end
lsv = \'shx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != \'shx", lsv); err=1; end
lsv = \'shz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != \'shz", lsv); err=1; end
// unsized binary literals two characters
lsv = \'sh00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != \'sh00", lsv); err=1; end
lsv = \'sh99; if (lsv !== 16\'b0000_0000_1001_1001) begin $display("FAILED -- lsv = \'b%b != \'sh99", lsv); err=1; end
lsv = \'shxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != \'shxx", lsv); err=1; end
lsv = \'shzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != \'shzz", lsv); err=1; end
lsv = \'sh9x; if (lsv !== 16\'b0000_0000_1001_xxxx) begin $display("FAILED -- lsv = \'b%b != \'sh9x", lsv); err=1; end
lsv = \'sh9z; if (lsv !== 16\'b0000_0000_1001_zzzz) begin $display("FAILED -- lsv = \'b%b != \'sh9z", lsv); err=1; end
lsv = \'shx9; if (lsv !== 16\'bxxxx_xxxx_xxxx_1001) begin $display("FAILED -- lsv = \'b%b != \'shx9", lsv); err=1; end
lsv = \'shz9; if (lsv !== 16\'bzzzz_zzzz_zzzz_1001) begin $display("FAILED -- lsv = \'b%b != \'shz9", lsv); err=1; end
// unsized binary literals single character
lsv = \'sd0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != \'sd0", lsv); err=1; end
lsv = \'sd9; if (lsv !== 16\'b0000_0000_0000_1001) begin $display("FAILED -- lsv = \'b%b != \'sd9", lsv); err=1; end
lsv = \'sdx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != \'sdx", lsv); err=1; end
lsv = \'sdz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != \'sdz", lsv); err=1; end
// unsized binary literals two characters
lsv = \'sd00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != \'sd00", lsv); err=1; end
lsv = \'sd99; if (lsv !== 16\'b0000_0000_0110_0011) begin $display("FAILED -- lsv = \'b%b != \'sd99", lsv); err=1; end
// lsv = \'sdxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != \'sdxx", lsv); err=1; end
// lsv = \'sdzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != \'sdzz", lsv); err=1; end
// unsized binary literals single character
lsv = 15\'sb0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != 15\'sb0", lsv); err=1; end
lsv = 15\'sb1; if (lsv !== 16\'b0000_0000_0000_0001) begin $display("FAILED -- lsv = \'b%b != 15\'sb1", lsv); err=1; end
lsv = 15\'sbx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != 15\'sbx", lsv); err=1; end
lsv = 15\'sbz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != 15\'sbz", lsv); err=1; end
// unsized binary literals two characters
lsv = 15\'sb00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != 15\'sb00", lsv); err=1; end
lsv = 15\'sb11; if (lsv !== 16\'b0000_0000_0000_0011) begin $display("FAILED -- lsv = \'b%b != 15\'sb11", lsv); err=1; end
lsv = 15\'sbxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != 15\'sbxx", lsv); err=1; end
lsv = 15\'sbzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != 15\'sbzz", lsv); err=1; end
lsv = 15\'sb1x; if (lsv !== 16\'b0000_0000_0000_001x) begin $display("FAILED -- lsv = \'b%b != 15\'sb1x", lsv); err=1; end
lsv = 15\'sb1z; if (lsv !== 16\'b0000_0000_0000_001z) begin $display("FAILED -- lsv = \'b%b != 15\'sb1z", lsv); err=1; end
lsv = 15\'sbx1; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- lsv = \'b%b != 15\'sbx1", lsv); err=1; end
lsv = 15\'sbz1; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzz1) begin $display("FAILED -- lsv = \'b%b != 15\'sbz1", lsv); err=1; end
// unsized binary literals single character
lsv = 15\'so0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != 15\'so0", lsv); err=1; end
lsv = 15\'so5; if (lsv !== 16\'b0000_0000_0000_0101) begin $display("FAILED -- lsv = \'b%b != 15\'so5", lsv); err=1; end
lsv = 15\'sox; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != 15\'sox", lsv); err=1; end
lsv = 15\'soz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != 15\'soz", lsv); err=1; end
// unsized binary literals two characters
lsv = 15\'so00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != 15\'so00", lsv); err=1; end
lsv = 15\'so55; if (lsv !== 16\'b0000_0000_0010_1101) begin $display("FAILED -- lsv = \'b%b != 15\'so55", lsv); err=1; end
lsv = 15\'soxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != 15\'soxx", lsv); err=1; end
lsv = 15\'sozz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != 15\'sozz", lsv); err=1; end
lsv = 15\'so5x; if (lsv !== 16\'b0000_0000_0010_1xxx) begin $display("FAILED -- lsv = \'b%b != 15\'so5x", lsv); err=1; end
lsv = 15\'so5z; if (lsv !== 16\'b0000_0000_0010_1zzz) begin $display("FAILED -- lsv = \'b%b != 15\'so5z", lsv); err=1; end
lsv = 15\'sox5; if (lsv !== 16\'bxxxx_xxxx_xxxx_x101) begin $display("FAILED -- lsv = \'b%b != 15\'sox5", lsv); err=1; end
lsv = 15\'soz5; if (lsv !== 16\'bzzzz_zzzz_zzzz_z101) begin $display("FAILED -- lsv = \'b%b != 15\'soz5", lsv); err=1; end
// unsized binary literals single character
lsv = 15\'sh0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != 15\'sh0", lsv); err=1; end
lsv = 15\'sh9; if (lsv !== 16\'b0000_0000_0000_1001) begin $display("FAILED -- lsv = \'b%b != 15\'sh9", lsv); err=1; end
lsv = 15\'shx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != 15\'shx", lsv); err=1; end
lsv = 15\'shz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != 15\'shz", lsv); err=1; end
// unsized binary literals two characters
lsv = 15\'sh00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != 15\'sh00", lsv); err=1; end
lsv = 15\'sh99; if (lsv !== 16\'b0000_0000_1001_1001) begin $display("FAILED -- lsv = \'b%b != 15\'sh99", lsv); err=1; end
lsv = 15\'shxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != 15\'shxx", lsv); err=1; end
lsv = 15\'shzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != 15\'shzz", lsv); err=1; end
lsv = 15\'sh9x; if (lsv !== 16\'b0000_0000_1001_xxxx) begin $display("FAILED -- lsv = \'b%b != 15\'sh9x", lsv); err=1; end
lsv = 15\'sh9z; if (lsv !== 16\'b0000_0000_1001_zzzz) begin $display("FAILED -- lsv = \'b%b != 15\'sh9z", lsv); err=1; end
lsv = 15\'shx9; if (lsv !== 16\'bxxxx_xxxx_xxxx_1001) begin $display("FAILED -- lsv = \'b%b != 15\'shx9", lsv); err=1; end
lsv = 15\'shz9; if (lsv !== 16\'bzzzz_zzzz_zzzz_1001) begin $display("FAILED -- lsv = \'b%b != 15\'shz9", lsv); err=1; end
// unsized binary literals single character
lsv = 15\'sd0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != 15\'sd0", lsv); err=1; end
lsv = 15\'sd9; if (lsv !== 16\'b0000_0000_0000_1001) begin $display("FAILED -- lsv = \'b%b != 15\'sd9", lsv); err=1; end
lsv = 15\'sdx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != 15\'sdx", lsv); err=1; end
lsv = 15\'sdz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != 15\'sdz", lsv); err=1; end
// unsized binary literals two characters
lsv = 15\'sd00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display("FAILED -- lsv = \'b%b != 15\'sd00", lsv); err=1; end
lsv = 15\'sd99; if (lsv !== 16\'b0000_0000_0110_0011) begin $display("FAILED -- lsv = \'b%b != 15\'sd99", lsv); err=1; end
// lsv = 15\'sdxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = \'b%b != 15\'sdxx", lsv); err=1; end
// lsv = 15\'sdzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = \'b%b != 15\'sdzz", lsv); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always block instantiation.
//
// D: Test validate others versions of always block
// D: including posedge, negedge.
//
//
module main ();
reg working;
reg clock ;
initial\t// Used to generate timing of events
begin
working = 0;
clock = 0;
#4 ;
working = 0;
#1 ;
clock = 1;\t// 1ns between setting working and clock edge.
#4 ;
working = 0;
#1 ;
clock = 0;\t// 1ns between setting working and clock edge.
#5 ;
end
always #2
working = 1 ;
initial // This is the validation block
begin
# 3;\t// Check #2 always at 3ns
if(!working)
begin
$display("FAILED - delayed always\
");
$finish ;
end
# 3;\t// Check posedge at 6 ns
if(!working)
begin
$display("FAILED - posedge always\
");
$finish ;
end
# 7;\t// Check negedge at 11ns
if(!working)
begin
$display("FAILED - posedge always\
");
$finish ;
end
$display("PASSED\
");
$finish;
end
always @ (posedge clock)
working = 1;
always @ (negedge clock)
working = 1;
endmodule
|
/*
* This test program catches the essence of PR#1072
*/
module main;
parameter WIDTH = 4;
wire [19:0] foo = { 1<<WIDTH {1\'b1}};
reg [19:0] bar;
initial begin
#1 bar = { 1<<WIDTH {1\'b1}};
if (foo !== 20\'h0ffff) begin
\t $display("FAILED -- foo = %b", foo);
\t $finish;
end
if (bar !== 20\'h0ffff) begin
\t $display("FAILED -- bar = %b", bar);
\t $finish;
end
if (foo !== bar) begin
\t $display("FAILED -- foo !== bar (%h !== %h)", foo, bar);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule
|
module bug();
reg [31:0] n1, d1, q1, m1;
reg [63:0] n2, d2, q2, m2;
initial begin
n1 = 32\'h8000_0000;
d1 = 32\'hFFFF_FFFF;
q1 = $signed(n1) / $signed(d1);
$display("32 bit quotient = 0x%08h;", q1);
m1 = $signed(n1) % $signed(d1);
$display("32 bit modulus = 0x%08h;", m1);
n2 = 64\'h8000_0000_0000_0000;
d2 = 64\'hFFFF_FFFF_FFFF_FFFF;
q2 = $signed(n2) / $signed(d2);
$display("64 bit quotient = 0x%016h;", q2);
m2 = $signed(n2) % $signed(d2);
$display("64 bit modulus = 0x%016h;", m2);
if ((q1 === 32\'h8000_0000) && (q2 === 64\'h8000_0000_0000_0000)
&& (m1 === 32\'h0000_0000) && (m2 === 64\'h0000_0000_0000_0000))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module test();
wire [7:0] value1;
wire bit [7:0] value2;
assign value1[3:0] = 4\'d2;
assign value2 = value1;
initial begin
// value1 gets cast to 2-state, so \'z\' bits are converted to \'0\'.
#2 $display("%b %b", value1, value2);
if (value2 === 8\'b00000010)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* Copyright (c) 2000 Peter Monta <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
parameter foo = { 2\'b01, 2\'b10 };
initial
if (foo==4\'b0110)
$display("PASSED");
else
$display("FAILED");
endmodule
|
// Submitted as PR184 by Matt Welland
module test;
wire foo;
reg [1:49] bar;
function foobar;
input [1:49] a;
begin
foobar = a[1] & a[2] & a[3] & a[4] & a[5] &
a[6] & a[7] & a[8] & a[9] & a[10] &
a[11] & a[12] & a[13] & a[14] & a[15] &
a[16] & a[17] & a[18] & a[19] & a[20] &
a[21] & a[22] & a[23] & a[24] & a[25] &
a[26] & a[27] & a[28] & a[29] & a[30] &
a[31] & a[32] & a[33] & a[34] & a[35] &
a[36] & a[37] & a[38] & a[39] & a[40] &
a[41] & a[42] & a[43] & a[44] & a[45] &
a[46] & a[47] & a[48] & a[49] ;
end
endfunction
assign foo = foobar( bar );
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_REAL_MODULUS_IN_IVTEST
`endif
module top;
reg pass;
real result;
initial begin
pass = 1\'b1;
// This should turn into a just a load of 0.5.
result = 1/2.0;
if (result != 0.5) begin
$display("Failed: int/real, expected 0.5, got %g", result);
pass = 1\'b0;
end
// This should turn into a just a load of 0.5.
result = 1.0/2;
if (result != 0.5) begin
$display("Failed: real/int, expected 0.5, got %g", result);
pass = 1\'b0;
end
`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST
// This should turn into a just a load of 1.0.
result = 1%2.0;
if (result != 1.0) begin
$display("Failed: int%%real, expected 1.0, got %g", result);
pass = 1\'b0;
end
// This should turn into a just a load of 1.0.
result = 1.0%2;
if (result != 1.0) begin
$display("Failed: real%%int, expected 1.0, got %g", result);
pass = 1\'b0;
end
`endif
if (pass) $display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* $Id: realcb.v,v 1.1 2003/02/10 05:14:13 stevewilliams Exp $
*/
module main;
real x, y;
initial begin
$my_watchreal(x, y);
#1 x = 1.0;
#1 y = 2.0;
#1 x = 1.5;
#1 y = 5.1;
end
endmodule // main
|
module main;
localparam int int_lparm = 11;
parameter int int_param = 10;
int\t\t int_var;
initial begin
if (int_lparm != 11) begin
\t $display("FAILED: int_lparm=%b", int_lparm);
\t $finish;
end
if ($bits(int_lparm) != 32) begin
\t $display("FAILED: $bits(int_lparm) = %d", $bits(int_lparm));
\t $finish;
end
if (int_param != 10) begin
\t $display("FAILED: int_param=%b", int_param);
\t $finish;
end
if ($bits(int_param) != 32) begin
\t $display("FAILED: $bits(int_param) = %d", $bits(int_param));
\t $finish;
end
int_var = int_param;
if (int_var != 10) begin
\t $display("FAILED: int_var=%b", int_var);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module main;
parameter NIBBLE = 4;
reg [NIBBLE*4-1:0] array [1:0];
reg [3:0] word;
integer idx;
initial begin
for (idx = 0 ; idx < 4 ; idx = idx+1) begin
\t array[0][idx*NIBBLE +: 4] = +idx;
\t array[1][idx*NIBBLE +: 4] = -idx;
end
if (array[0] !== 16\'h3210) begin
\t $display("FAILED -- array[0] = %h", array[0]);
\t $finish;
end
word = array[0][7:4];
if (word !== 4\'h1) begin
\t $display("FAILED == array[0][7:4] = %h", word);
\t $finish;
end
word = array[1][7:4];
if (word !== 4\'hf) begin
\t $display("FAILED == array[0][7:4] = %h", word);
\t $finish;
end
for (idx = 0 ; idx < 4 ; idx = idx+1) begin
\t word = array[0][idx*NIBBLE +: 4];
\t if (word !== idx) begin
\t $display("FAILED == array[0][nibble=%d] = %h", idx, word);
\t $finish;
\t end
\t word = array[1][idx*NIBBLE +: 4];
\t if (word !== - idx[3:0]) begin
\t $display("FAILED == array[1][nibble=%d] = %h", idx, word);
\t $finish;
\t end
end // for (idx = 0 ; idx < 4 ; idx += 1)
$display("PASSED");
end
endmodule // main
|
/*
* This is a post-wynthesis test for the blif01a.v test. Run this
* simulation in these steps:
*
* $ iverilog -tblif -o foo.blif blif01a.v
* $ abc
* abc 01> read_blif foo.blif
* abc 02> write_verilog foo.v
* abc 03> quit
* $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v
* $ vvp foo.vvp
*/
module main;
parameter WID = 4;
reg [WID-1:0] A, B;
wire [WID:0] Q;
addN usum(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]),
\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]),
\t .\\Q[4] (Q[4]), .\\Q[3] (Q[3]), .\\Q[2] (Q[2]), .\\Q[1] (Q[1]), .\\Q[0] (Q[0]));
int\t\t adx;
int\t\t bdx;
initial begin
for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
\t A <= adx[WID-1:0];
\t B <= bdx[WID-1:0];
\t #1 if (Q !== (adx+bdx)) begin
\t $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q);
\t $finish;
\t end
\t end
end
$display("PASSED");
end
endmodule // main
|
// This tests the basic support for default arguments to task/function
// ports. The default port syntax gives SystemVerilog a limited form
// of variable argument lists.
program main;
class foo_t;
int int_val;
logic[3:0] log_val;
string text_val;
function new (int int_init, logic[3:0]log_init = 4\'bzzzz, string text_init = "default text");
\t int_val = int_init;
\t log_val = log_init;
\t text_val = text_init;
endfunction : new
endclass : foo_t
foo_t obj1;
initial begin
obj1 = new (4, 4\'b0101, "new text");
if (obj1.int_val != 4 || obj1.log_val !== 4\'b0101 || obj1.text_val != "new text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val);
\t $finish;
end
obj1 = new (5, , "new text");
if (obj1.int_val != 5 || obj1.log_val !== 4\'bzzzz || obj1.text_val != "new text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val);
\t $finish;
end
obj1 = new (6, 4\'b1010);
if (obj1.int_val != 6 || obj1.log_val !== 4\'b1010 || obj1.text_val != "default text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val);
\t $finish;
end
obj1 = new (7);
if (obj1.int_val != 7 || obj1.text_val != "default text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val);
\t $finish;
end
$display("PASSED");
end
endprogram // main
|
//
// This tests that the parameter and localparam show up in the vcd dump.
//
module main;
parameter [3:0] foo = 4\'d5;
localparam [3:0] bar = 7;
parameter real PI = 3.14;
wire [3:0] bat = foo + bar;
wire real tau = 2.0 * PI;
initial begin
$dumpfile("work/br_gh156.vcd");
$dumpvars(0, main);
#1 $finish;
end
endmodule // main
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg [9:0] a;
reg b;
initial begin
a = 10\'h3ff;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
b = a[15];
`else
b = 1\'bx;
`endif
$display("A = %h, b = %b", a, b);
end // initial begin
endmodule // top
|
// test that if the signal doesn't exist, an error is thrown
module m(input a, output b);
assign b = a;
endmodule
module top;
reg a;
// wire b;
m foo(.a, .b);
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: mangle.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $
// $Log: mangle.v,v $
// Revision 1.1 2001/06/19 13:52:13 ka6s
// Added 4 tests from Stephan Boettcher
//
//
// Test of \\escaped identifiers
module mangle;
reg \\abc ;
reg \\`~!-_=+\\|[]{};:\'"",./<>? ;
reg cde ;
initial
begin
\tabc <= 1;
\t\\`~!-_=+\\|[]{};:\'"",./<>? <= 1;
\t\\cde <= 1;
\t$display("PASSED");
\t$finish;
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate function within a continuous assignment
module main ();
reg error;
reg [3:0] val2;
function [3:0] myfunc ;
input [31:0] in1 ;
myfunc = in1;
endfunction
wire [3:0] val1;
assign val1 = myfunc(val2);
initial
begin
error = 0;
val2 = 4\'h0;
# 1 ;
if(val1 !== 4\'b0)
begin
$display("FAILED - function3.11D - function within continuous assign(1)");
error = 1;
end
val2 = 32\'h8;
# 1 ;
if(val1 !== val2)
begin
$display("FAILED - function3.11D - function within continuous assign(2)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
module extension_bug();
reg x;
reg [3:0] a, b;
initial begin
x = 1\'b1;
a = ~1\'b1;
b = ~x;
$display("a = %b", a);
if (a !== 4\'b1110) begin
$display("FAILED");
$finish;
end
$display("b = %b", b);
if (b !== 4\'b1110) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
endmodule
|
module test();
wire sig;
reg\ten0, en1;
pullup (sig);
assign sig = en0 ? 1\'b0 : 1\'bz;
assign sig = en1 ? 1\'b1 : 1\'bz;
reg\tsig2;
always @(sig)
sig2 = sig;
initial begin
en0 = 0;
en1 = 1;
#1 en1 = 0;
#1 if (sig2 !== 1\'b1) begin
\t $display("FAILED -- sig2=%b, sig=%b", sig2, sig);
\t $finish;
end
force sig = 0;
#1 if (sig2 !== 1\'b0) begin
\t $display("FAILED -- sig2=%b, sig=%b", sig2, sig);
\t $finish;
end
release sig;
#1 if (sig2 !== 1\'b1) begin
\t $display("FAILED -- sig2=%b, sig=%b", sig2, sig);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule
|
// Check that parameters with a scalar type are handled correctly
module test #(
// This should get truncated to 1\'b1
parameter bit P = 2\'b11
);
bit failed = 1\'b0;
`define check(expr, val) \\
if (expr !== val) begin \\
$display("FAILED: `%s`, expected %0d, got %0d", `"expr`", val, expr); \\
failed = 1\'b1; \\
end
initial begin
`check($bits(P), 1);
`check(P + 1\'b1, 1\'b0);
`check(P, 1\'b1);
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module test;
wire s1;
not(,s1);
not(s1,);
endmodule
|
module test ();
// Note the implicit declaration of w.
assign w = 1\'b1;
initial begin
#1 if (w !== 1\'b1) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule
|
module top;
reg pass = 1\'b1;
integer count;
reg [2:0] icount;
reg clk = 0;
reg [3:0] in = 4\'h0;
reg [3:0] result [1:0];
always #10 clk = ~clk;
always #20 in = in + 4\'h1;
initial begin
count = 3;
result[0] <= repeat(count) @(posedge clk) in;
if ($simtime != 0 || result[0] !== 4\'bx) begin
$display("Failed repeat(3) blocked at %0t, expected 4\'hx, got %h",
$simtime, result[0]);
pass = 1\'b0;
end
@(result[0]);
if ($simtime != 50 || result[0] !== 4\'h0) begin
$display("Failed repeat(3) at %0t, expected 4\'h0, got %h",
$simtime, result[0]);
pass = 1\'b0;
end
#15;
count = 0;
result[0] <= repeat(count) @(posedge clk) in;
@(result[0]); // Reals happen faster they can use an #0, vectors are slower.
if ($simtime != 65 || result[0] !== 4\'h3) begin
$display("Failed repeat(0) at %0t, expected 4\'h3, got %h",
$simtime, result[0]);
pass = 1\'b0;
end
#20;
count = -1;
result[0] <= repeat(count) @(posedge clk) in;
@(result[0]); // Reals happen faster they can use an #0, vectors are slower.
if ($simtime != 85 || result[0] !== 4\'h4) begin
$display("Failed repeat(-1) at %0t, expected 4\'h4, got %h",
$simtime, result[0]);
pass = 1\'b0;
end
#20;
result[0] <= @(posedge clk) 4\'h0;
result[0] <= @(posedge clk) in; // This one sets the final value.
@(result[0]);
if ($simtime != 110 || result[0] !== 4\'h5) begin
$display("Failed @ at %0t, expected 4\'h5, got %h",
$simtime, result[0]);
pass = 1\'b0;
end
icount = 3\'d2;
result[0] <= @(posedge clk) 4\'h1;
result[0] <= repeat(icount) @(posedge clk) 4\'h2;
result[0] <= repeat(3) @(posedge clk) 4\'h3;
@(result[0]);
if ($simtime != 130 || result[0] !== 4\'h1) begin
$display("Failed first @ at %0t, expected 4\'h1, got %h",
$simtime, result[0]);
pass = 1\'b0;
end
@(result[0]);
if ($simtime != 150 || result[0] !== 4\'h2) begin
$display("Failed second @ at %0t, expected 4\'h2, got %h",
$simtime, result[0]);
pass = 1\'b0;
end
@(result[0]);
if ($simtime != 170 || result[0] !== 4\'h3) begin
$display("Failed third @ at %0t, expected 4\'h3, got %h",
$simtime, result[0]);
pass = 1\'b0;
end
if (pass) $display("PASSED");
$finish;
end
endmodule
|
// Check that declaring a module inside a generate block is an error
module test #(
parameter A = 1
);
generate
if (A) begin
// Error
module inner;
initial $display("FAILED");
endmodule
end
endgenerate
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Test non-constant bit selects - causes compile error right now
module test;
reg clk;
reg [1:0] in0;
reg [1:0] in1;
reg sel0,sel1;
wire [1:0] q;
dff2 u1 (q,clk,in0[sel0],in1[sel1]);
initial
begin
clk = 0;
in0 = 2\'b0;
in1 = 2\'b0;
sel0 = 1\'b0;
sel1 = 1\'b1;
#8;
$display("initial val =%x",q);
#8;
if(q == 2\'b0)
\t $display("PASSED");
else
\t $display("FAILED");
$finish ;
end
always #5 clk = ~clk;
endmodule
// This is just a dual dff
module dff2 (q,clk,d0,d1);
input clk,d0,d1;
output [1:0] q;
reg [1:0] q;
always @(posedge clk)
\t q <= {d1,d0};
endmodule
|
/*
* Copyright (c) 2002 Mike Runyan, Michael Ruff
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test;
initial $display("Hello World");
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module main;
reg [7:0] foo;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
wire [3:0] below = foo[2:-1];
wire [3:0] above = foo[8:5];
wire [9:0] span = foo[8:-1];
`else
wire [3:0] below = {foo[2:0], 1\'bx};
wire [3:0] above = {1\'bx, foo[7:5]};
wire [9:0] span = {1\'bx, foo[7:0], 1\'bx};
`endif
initial begin
foo = \'h55;
#1 ;
if (below !== 4\'b101_x) begin
\t $display("FAILED");
\t $finish;
end
if (above !== 4\'bx_010) begin
\t $display("FAILED");
\t $finish;
end
if (span !== 10\'bx_01010101_x) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Checks that the line and file information is correctly attached to a enum
// data type and will be used when printing an error message about the enum.
module test;
// Direct
enum logic {
A, B = A
} e1;
// Used in a struct
typedef enum logic {
C, D = C
} enum1_type;
// Used as a signal type
typedef enum logic {
E, F = E
} enum2_type;
// Unreferenced
typedef enum logic {
G, H = G
} enum3_type;
struct packed {
enum1_type e;
} s;
enum2_type e2;
endmodule
|
/*
* Test case showing the failure of the \'less than or equal\' operator (note
* that the \'greather than or equal\' comparison also fails) on two signed
* values. The \'foo\' module defines inputs \'a\' and \'b\' as signed inputs,
* then performs a LTE comparison of those two values in order to select the
* smaller of the two as the result (via a mux). The generated output for
* this test (via the display call) for icarus and a well known commercial
* Verilog simulator are shown here. It is my belief that the commercial
* simulator results reflect the correct behavior for a simulator.
* Specifically, with signed numbers the value 32\'h7fffffff represents the
* maximum positive value while 32\'h80000000 represents the minimum negative
* value. Thus for Less Than or Equal comparison any negative value (ie
* 32\'h80000000) should evaluate to less than any positive value
* (ie 32\'h7fffffff). Note the difference in the last 4 comparisons between
* the icarus results and the commercial results. The commercial results show
* that the 32\'h8000000? values are less than the 32\'h7ffffff? values as is
* expected.
*
* icarus commercial simulator
* 7ffffff5 7ffffffa = 7ffffff5 # 7ffffff5 7ffffffa = 7ffffff5
* 7ffffff6 7ffffffb = 7ffffff6 # 7ffffff6 7ffffffb = 7ffffff6
* 7ffffff7 7ffffffc = 7ffffff7 # 7ffffff7 7ffffffc = 7ffffff7
* 7ffffff8 7ffffffd = 7ffffff8 # 7ffffff8 7ffffffd = 7ffffff8
* 7ffffff9 7ffffffe = 7ffffff9 # 7ffffff9 7ffffffe = 7ffffff9
* 7ffffffa 7fffffff = 7ffffffa # 7ffffffa 7fffffff = 7ffffffa
* 7ffffffb 80000000 = 7ffffffb # 7ffffffb 80000000 = 80000000
* 7ffffffc 80000001 = 7ffffffc # 7ffffffc 80000001 = 80000001
* 7ffffffd 80000002 = 7ffffffd # 7ffffffd 80000002 = 80000002
* 7ffffffe 80000003 = 7ffffffe # 7ffffffe 80000003 = 80000003
*
* iverilog -version:
* Icarus Verilog version 0.7 ($Name: $)
*
* Compilation
* iverilog -o iverilog.out
* vvp iverilog.out
*/
module test ();
reg clk;
reg [31:0] a_dat;
reg [31:0] b_dat;
wire [31:0] result;
initial begin
\t clk <= 0;
\t a_dat <= 32\'h7fffFFF5;
\t b_dat <= 32\'h7fffFFFA;
\t #500 $finish(0);
end
always #25 clk <= ~clk;
always @(posedge clk)
\t begin
\t\ta_dat <= a_dat + 1;
\t\tb_dat <= b_dat + 1;
\t\t$display("%x %x = %x", a_dat, b_dat, result);
\t end
foo foo_test(.a(a_dat), .b(b_dat), .RESULT(result));
endmodule // test
module foo(a, b, RESULT);
input\tsigned [31:0]\ta;
input\tsigned [31:0]\tb;
output [31:0] RESULT;
wire\t\t\t lessThanEqualTo;
wire [31:0]\t\t mux;
assign\t\t lessThanEqualTo=a<=b;
assign\t\t mux=(lessThanEqualTo)?a:b;
assign\t\t RESULT=mux;
endmodule // foo
|
// Check that declarations for unpacked arrays of dynamic arrays are supported.
module test;
// Unpacked array of dynamic arrays
int q[][10];
endmodule
|
module test();
function [31:0] pre_inc(input [31:0] x);
begin
++x[23:8];
pre_inc = x;
end
endfunction
function [31:0] pre_dec(input [31:0] x);
begin
--x[23:8];
pre_dec = x;
end
endfunction
function [31:0] post_inc(input [31:0] x);
begin
x[23:8]++;
post_inc = x;
end
endfunction
function [31:0] post_dec(input [31:0] x);
begin
x[23:8]--;
post_dec = x;
end
endfunction
localparam pre_inc_5 = pre_inc({8\'h55, 16\'d5, 8\'haa});
localparam pre_dec_5 = pre_dec({8\'h55, 16\'d5, 8\'haa});
localparam post_inc_5 = post_inc({8\'h55, 16\'d5, 8\'haa});
localparam post_dec_5 = post_dec({8\'h55, 16\'d5, 8\'haa});
function [31:0] add2(input [31:0] x);
begin
x[23:8] += 2;
add2 = x;
end
endfunction
function [31:0] sub2(input [31:0] x);
begin
x[23:8] -= 2;
sub2 = x;
end
endfunction
function [31:0] mul2(input [31:0] x);
begin
x[23:8] *= 2;
mul2 = x;
end
endfunction
function [31:0] div2(input [31:0] x);
begin
x[23:8] /= 2;
div2 = x;
end
endfunction
function [31:0] mod2(input [31:0] x);
begin
x[23:8] %= 2;
mod2 = x;
end
endfunction
function [31:0] and6(input [31:0] x);
begin
x[23:8] &= 16\'h6666;
and6 = x;
end
endfunction
function [31:0] or6(input [31:0] x);
begin
x[23:8] |= 16\'h6666;
or6 = x;
end
endfunction
function [31:0] xor6(input [31:0] x);
begin
x[23:8] ^= 16\'h6666;
xor6 = x;
end
endfunction
function [31:0] lsl2(input [31:0] x);
begin
x[23:8] <<= 2;
lsl2 = x;
end
endfunction
function [31:0] lsr2(input [31:0] x);
begin
x[23:8] >>= 2;
lsr2 = x;
end
endfunction
function [31:0] asl2(input [31:0] x);
begin
x[23:8] <<<= 2;
asl2 = x;
end
endfunction
function [31:0] asr2(input [31:0] x);
begin
x[23:8] >>>= 2;
asr2 = x;
end
endfunction
localparam add2_5 = add2({8\'h55, 16\'d5, 8\'haa});
localparam sub2_5 = sub2({8\'h55, 16\'d5, 8\'haa});
localparam mul2_5 = mul2({8\'h55, 16\'d5, 8\'haa});
localparam div2_5 = div2({8\'h55, 16\'d5, 8\'haa});
localparam mod2_5 = mod2({8\'h55, 16\'d5, 8\'haa});
localparam and6_f = and6(32\'h55ffffaa);
localparam or6_0 = or6(32\'h550000aa);
localparam xor6_f = xor6(32\'h55ffffaa);
localparam lsl2_p25 = lsl2({8\'h55, 16\'sd25, 8\'haa});
localparam lsr2_m25 = lsr2({8\'h55, -16\'sd25, 8\'haa});
localparam asl2_m25 = asl2({8\'h55, -16\'sd25, 8\'haa});
localparam asr2_m25 = asr2({8\'h55, -16\'sd25, 8\'haa});
function [31:0] add3(input [31:0] x);
begin
add3 = x;
add3[23:8] += 3;
end
endfunction
function [31:0] sub3(input [31:0] x);
begin
sub3 = x;
sub3[23:8] -= 3;
end
endfunction
function [31:0] mul3(input [31:0] x);
begin
mul3 = x;
mul3[23:8] *= 3;
end
endfunction
function [31:0] div3(input [31:0] x);
begin
div3 = x;
div3[23:8] /= 3;
end
endfunction
function [31:0] mod3(input [31:0] x);
begin
mod3 = x;
mod3[23:8] %= 3;
end
endfunction
function [31:0] and9(input [31:0] x);
begin
and9 = x;
and9[23:8] &= 16\'h9999;
end
endfunction
function [31:0] or9(input [31:0] x);
begin
or9 = x;
or9[23:8] |= 16\'h9999;
end
endfunction
function [31:0] xor9(input [31:0] x);
begin
xor9 = x;
xor9[23:8] ^= 16\'h9999;
end
endfunction
function [31:0] lsl3(input [31:0] x);
begin
lsl3 = x;
lsl3[23:8] <<= 3;
end
endfunction
function [31:0] lsr3(input [31:0] x);
begin
lsr3 = x;
lsr3[23:8] >>= 3;
end
endfunction
function [31:0] asl3(input [31:0] x);
begin
asl3 = x;
asl3[23:8] <<<= 3;
end
endfunction
function [31:0] asr3(input [31:0] x);
begin
asr3 = x;
asr3[23:8] >>>= 3;
end
endfunction
localparam add3_5 = add3({8\'h55, 16\'d5, 8\'haa});
localparam sub3_5 = sub3({8\'h55, 16\'d5, 8\'haa});
localparam mul3_5 = mul3({8\'h55, 16\'d5, 8\'haa});
localparam div3_5 = div3({8\'h55, 16\'d5, 8\'haa});
localparam mod3_5 = mod3({8\'h55, 16\'d5, 8\'haa});
localparam and9_f = and9(32\'h55ffffaa);
localparam or9_0 = or9(32\'h550000aa);
localparam xor9_f = xor9(32\'h55ffffaa);
localparam lsl3_p25 = lsl3({8\'h55, 16\'sd25, 8\'haa});
localparam lsr3_m25 = lsr3({8\'h55, -16\'sd25, 8\'haa});
localparam asl3_m25 = asl3({8\'h55, -16\'sd25, 8\'haa});
localparam asr3_m25 = asr3({8\'h55, -16\'sd25, 8\'haa});
reg failed = 0;
initial begin
$display("pre_inc_5 = %0h", pre_inc_5);
if (pre_inc_5 !== pre_inc({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (pre_inc_5 !== 32\'h550006aa) failed = 1;
$display("pre_dec_5 = %0h", pre_dec_5);
if (pre_dec_5 !== pre_dec({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (pre_dec_5 !== 32\'h550004aa) failed = 1;
$display("post_inc_5 = %0h", post_inc_5);
if (post_inc_5 !== post_inc({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (post_inc_5 !== 32\'h550006aa) failed = 1;
$display("post_dec_5 = %0h", post_dec_5);
if (post_dec_5 !== post_dec({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (post_dec_5 !== 32\'h550004aa) failed = 1;
$display("add2_5 = %0h", add2_5);
if (add2_5 !== add2({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (add2_5 !== 32\'h550007aa) failed = 1;
$display("sub2_5 = %0h", sub2_5);
if (sub2_5 !== sub2({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (sub2_5 !== 32\'h550003aa) failed = 1;
$display("mul2_5 = %0h", mul2_5);
if (mul2_5 !== mul2({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (mul2_5 !== 32\'h55000aaa) failed = 1;
$display("div2_5 = %0h", div2_5);
if (div2_5 !== div2({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (div2_5 !== 32\'h550002aa) failed = 1;
$display("mod2_5 = %0h", mod2_5);
if (mod2_5 !== mod2({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (mod2_5 !== 32\'h550001aa) failed = 1;
$display("and6_f = %h", and6_f);
if (and6_f !== and6(32\'h55ffffaa)) failed = 1;
if (and6_f !== 32\'h556666aa) failed = 1;
$display(" or6_0 = %h", or6_0);
if (or6_0 !== or6(32\'h550000aa)) failed = 1;
if (or6_0 !== 32\'h556666aa) failed = 1;
$display("xor6_f = %h", xor6_f);
if (xor6_f !== xor6(32\'h55ffffaa)) failed = 1;
if (xor6_f !== 32\'h559999aa) failed = 1;
$display("lsl2_p25 = %0h", lsl2_p25);
if (lsl2_p25 !== lsl2({8\'h55, 16\'sd25, 8\'haa})) failed = 1;
if (lsl2_p25 !== 32\'h550064aa) failed = 1;
$display("lsr2_m25 = %0h", lsr2_m25);
if (lsr2_m25 !== lsr2({8\'h55, -16\'sd25, 8\'haa})) failed = 1;
if (lsr2_m25 !== 32\'h553ff9aa) failed = 1;
$display("asl2_m25 = %0h", asl2_m25);
if (asl2_m25 !== asl2({8\'h55, -16\'sd25, 8\'haa})) failed = 1;
if (asl2_m25 !== 32\'h55ff9caa) failed = 1;
$display("asr2_m25 = %0h", asr2_m25);
if (asr2_m25 !== asr2({8\'h55, -16\'sd25, 8\'haa})) failed = 1;
if (asr2_m25 !== 32\'h553ff9aa) failed = 1;
$display("add3_5 = %0h", add3_5);
if (add3_5 !== add3({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (add3_5 !== 32\'h550008aa) failed = 1;
$display("sub3_5 = %0h", sub3_5);
if (sub3_5 !== sub3({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (sub3_5 !== 32\'h550002aa) failed = 1;
$display("mul3_5 = %0h", mul3_5);
if (mul3_5 !== mul3({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (mul3_5 !== 32\'h55000faa) failed = 1;
$display("div3_5 = %0h", div3_5);
if (div3_5 !== div3({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (div3_5 !== 32\'h550001aa) failed = 1;
$display("mod3_5 = %0h", mod3_5);
if (mod3_5 !== mod3({8\'h55, 16\'d5, 8\'haa})) failed = 1;
if (mod3_5 !== 32\'h550002aa) failed = 1;
$display("and9_f = %h", and9_f);
if (and9_f !== and9(32\'h55ffffaa)) failed = 1;
if (and9_f !== 32\'h559999aa) failed = 1;
$display(" or9_0 = %h", or9_0);
if (or9_0 !== or9(32\'h550000aa)) failed = 1;
if (or9_0 !== 32\'h559999aa) failed = 1;
$display("xor9_f = %h", xor9_f);
if (xor9_f !== xor9(32\'h55ffffaa)) failed = 1;
if (xor9_f !== 32\'h556666aa) failed = 1;
$display("lsl3_p25 = %0h", lsl3_p25);
if (lsl3_p25 !== lsl3({8\'h55, 16\'sd25, 8\'haa})) failed = 1;
if (lsl3_p25 !== 32\'h5500c8aa) failed = 1;
$display("lsr3_m25 = %0h", lsr3_m25);
if (lsr3_m25 !== lsr3({8\'h55, -16\'sd25, 8\'haa})) failed = 1;
if (lsr3_m25 !== 32\'h551ffcaa) failed = 1;
$display("asl3_m25 = %0h", asl3_m25);
if (asl3_m25 !== asl3({8\'h55, -16\'sd25, 8\'haa})) failed = 1;
if (asl3_m25 !== 32\'h55ff38aa) failed = 1;
$display("asr3_m25 = %0h", asr3_m25);
if (asr3_m25 !== asr3({8\'h55, -16\'sd25, 8\'haa})) failed = 1;
if (asr3_m25 !== 32\'h551ffcaa) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
`timescale 1ns/10ps
module top;
reg pass, clk;
wire out;
initial begin
$monitor("%f %b %b", $realtime, out, clk);
pass = 1\'b1;
$sdf_annotate("ivltests/pr2972866.sdf", dut);
clk = 1\'b0;
#10 clk = 1\'b1;
#10 clk = 1\'b0;
// Don\'t check for just PASSED since we are looking for modpath
// problems (SDF WARNING)!
#10 if (pass) $display("Simulation ran correctly.");
end
always @(out) if (out !== clk && $time != 0) begin
$display("Failed to match, expected %b, got %b.", clk, out);
pass = 1\'b0;
end
ckt dut (out, clk);
endmodule
module ckt(clk_out, clk_in);
output clk_out;
input clk_in;
wire clk_l1;
CLK_BUF L1 (clk_l1, clk_in);
CLK_BUF L2 (clk_out, clk_l1);
endmodule
module CLK_BUF(out, in);
output out;
input in;
buf b1 (out, in);
specify
(in +=> out) = (0.1:0.1:0.1, 0.1:0.1:0.1);
endspecify
endmodule
|
// Copyright (c) 2014 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for dynamic arrays used as the function parameters and return type.
module sv_darray_function();
typedef logic[7:0] byte_array [];
typedef logic[3*8-1:0] byte_vector;
function byte_array inc_array(byte_array inp);
byte_array tmp;
tmp = new[$size(inp)];
for(int i = 0; i < $size(inp); ++i)
begin
tmp[i] = inp[i] + 1;
end
return tmp;
endfunction
initial begin
byte_array a, b;
byte_vector c;
a = new[3];
a[0] = 10;
a[1] = 11;
a[2] = 12;
b = inc_array(a);
if($size(a) != 3 || a[0] !== 10 || a[1] !== 11 || a[2] !== 12) begin
$display("FAILED 1");
$finish();
end
if($size(b) != 3 || b[0] !== 11 || b[1] !== 12 || b[2] !== 13) begin
$display("FAILED 2");
$finish();
end
// Cast dynamic array returned by function to logic vector
c = byte_vector\'(inc_array(b));
if(c !== 24\'h0c0d0e) begin
$display("FAILED 3");
$finish();
end
$display("PASSED");
end
endmodule
|
module test();
function integer array_value(input integer idx);
reg [31:0] local_array[1:-1];
integer i;
begin
for (i = -2; i <= 2; i = i + 1) local_array[i] = i;
array_value = local_array[idx];
end
endfunction
localparam avm2 = array_value(-2);
localparam avm1 = array_value(-1);
localparam av0 = array_value(0);
localparam avp1 = array_value(1);
localparam avp2 = array_value(2);
initial begin
if (avm2 === \'bx && avm1 === -1 && av0 === 0 && avp1 === 1 && avp2 === \'bx)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// This tests SystemVerilog casting support
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// Extended by Maciej Suminski
// Copied and modified by Martin Whitaker
// Copied and modified again by Lars-Peter Clausen
module test();
typedef struct packed signed { logic [7:0] x; } s08;
typedef struct packed signed { logic [15:0] x; } s16;
typedef struct packed signed { int x; } s32;
typedef struct packed signed { int x; shortint y; byte z; logic [7:0] w; } s64;
// variables used in casting
s08 var_08;
s16 var_16;
s32 var_32;
s64 var_64;
real var_real;
// error counter
bit err = 0;
initial begin
var_08 = s08\'(4\'sh5); if (var_08 !== 8\'sh05) begin $display("FAILED -- var_08 = \'h%0h != 8\'h05", var_08); err=1; end
var_16 = s16\'(var_08); if (var_16 !== 16\'sh05) begin $display("FAILED -- var_16 = \'h%0h != 16\'h05", var_16); err=1; end
var_32 = s32\'(var_16); if (var_32 !== 32\'sh05) begin $display("FAILED -- var_32 = \'h%0h != 32\'h05", var_32); err=1; end
var_64 = s64\'(var_32); if (var_64 !== 64\'sh05) begin $display("FAILED -- var_64 = \'h%0h != 64\'h05", var_64); err=1; end
var_real = 13.4; var_08 = s08\'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
var_real = 14.5; var_16 = s16\'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
var_real = 15.6; var_32 = s32\'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
var_real = -15.6; var_64 = s64\'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
var_08 = s08\'(4\'hf); if (var_08 !== 8\'sh0f) begin $display("FAILED -- var_08 = \'h%0h != 8\'h0f", var_08); err=1; end
var_08 = s08\'(4\'shf); if (var_08 !== 8\'shff) begin $display("FAILED -- var_08 = \'h%0h != 8\'hff", var_08); err=1; end
var_16 = s08\'(16\'h0f0f); if (var_16 !== 16\'sh0f) begin $display("FAILED -- var_16 = \'h%0h != 16\'h0f", var_16); err=1; end
var_16 = s08\'(4\'shf) + \'d0; if (var_16 !== 16\'shff) begin $display("FAILED -- var_16 = \'h%0h != 16\'hff", var_16); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
// Test error handling for duplicate variable declarations.
module bug();
typedef struct packed {
logic value;
} data_t;
typedef enum { A, B } enum_t;
wire w1;
wire w1;
data_t d1;
data_t d1;
enum_t e1;
enum_t e1;
reg r1;
reg r1;
endmodule
|
`timescale 10ns/1ps
module main;
logic [1:0] counter = 2\'b00;
logic clk = 1\'b0;
initial forever #1 clk <= ~clk;
always @(posedge clk) begin
counter <= counter + 2\'d1;
priority case (counter)
2\'d0: $display("case 0");
2\'d1: $display("case 1");
2\'d3: $display("case 3");
endcase // priority case (counter)
if (counter == 2\'d3) begin
$display("PASSED");
$finish(0);
end
end
endmodule
|
module top;
integer result;
initial begin
result = $countbits(top);
result = $countbits("a string");
result = $countbits(1\'bx);
result = $countbits("a string", 1\'bx);
result = $countbits(1\'bx, "a string");
result = $countbits(1\'bx, 1\'bx, "a string");
end
endmodule
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* SDW: Verify expression using logical and in a parameter declaration
*/
module test;
parameter A0 = 2\'b10 && 2\'b01 ;
initial
begin
if(A0 !== 1\'b1)
$display("FAILED - A0 expression && doesn\'t work.");
else
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 2002 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: synth basic state machine form
//
//
module sm ( clk,rst,st);
input clk,rst;
output [1:0] st;
reg [1:0] st;
always @(posedge clk or posedge rst)
if (rst)
st <= 2\'b0;
else
case (st)
2\'b00: st <= 2\'b01;
2\'b01: st <= 2\'b11;
2\'b11: st <= 2\'b10;
2\'b10: st <= 2\'b00;
endcase
endmodule
module test ;
reg clk,rst;
wire [1:0] st;
sm u_sm ( clk,rst,st);
always #5 clk = ~clk;
initial
begin
// $dumpfile("test.vcd");
// $dumpvars(0,test);
clk = 0;
rst = 1;
@(posedge clk);
#1 ;
rst = 0;
if(st !== 2\'b00)
begin
\t $display("FAILED - SM didn\'t initialize");
\t $finish;
end
@(posedge clk);
#1 ;
if(st !== 2\'b01)
begin
\t $display("FAILED - SM didn\'t xsn to 01");
\t $finish;
end
@(posedge clk);
#1 ;
if(st !== 2\'b11)
begin
\t $display("FAILED - SM didn\'t xsn to 11");
\t $finish;
end
@(posedge clk);
#1 ;
if(st !== 2\'b10)
begin
\t $display("FAILED - SM didn\'t xsn to 10");
\t $finish;
end
@(posedge clk);
#1 ;
if(st !== 2\'b00)
begin
\t $display("FAILED - SM didn\'t xsn to 00");
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate OR gate vector
//
module main;
reg globvar;
wire [15:0] out;
reg [15:0] a,b, rslt;
reg error;
// The test gate goes HERE!
or foo [15:0] (out,a,b);
always @(a or b)
rslt = a | b;
initial
begin // {
error = 0;
# 1;
for(a = 16\'h1; a != 16\'h8000; a = (a << 1) )
begin // {
for(b = 16\'h8000; b !== 16\'h0; b = b >> 1)
begin // {
#1 ;
if(out !== rslt)
begin // {
$display("FAILED - GA OR a=%h,b=%h,expct=%h - rcvd=%h",
a,b,rslt,out);
error = 1;
end // }
end // }
end // }
if( error == 0)
$display("PASSED");
end // }
endmodule // main
|
package test_pkg;
// Need to add enumerations to packages.
typedef enum logic[4:0] {
EXC_A = 0,
EXC_B = 1,
EXC_C = 2
} exc_code_t;
// Need to search up the parent scope searching for the enum definition.
function logic func1(exc_code_t c);
logic rVal;
case(c)
EXC_C : rVal = 1;
default: rVal = 0;
endcase
return(rVal);
endfunction
endpackage
module a();
import test_pkg::func1;
import test_pkg::exc_code_t;
exc_code_t exc_code;
logic result;
initial begin
// Need to compare the base enumeration definition to check compatibility.
exc_code = test_pkg::EXC_C;
result = func1(exc_code);
if(result==1\'b1) begin
$display("PASSED");
$finish;
end
$display("FAILED");
$finish;
end
endmodule
|
module br918a();
reg [1:0] v1;
reg [1:0] v2;
reg [1:0] v3;
reg [1:0] v4;
wire [3:0] w;
assign (pull1,strong0) w[1:0] = v1;
assign (pull1,strong0) w[1:0] = v2;
assign (pull1,strong0) w[3:2] = v3;
assign (pull1,strong0) w[3:2] = v4;
initial begin
v1 = 2\'b00;
v2 = 2\'b10;
v3 = 2\'b11;
v4 = 2\'b10;
#1 $display("%b", w);
if (w === 4\'b1000)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module check (input signed [22:0] a, b, c);
wire signed [22:0] int_AB;
assign int_AB = a / b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR: mismatch in div for %d and %d", a , b);
\t $display("VHDL = %d, Verilog = %d", c, int_AB);
$finish;
end
end
endmodule
module stimulus (output reg signed [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 1;
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
\t\t if (B === 23\'b0) B = 1;
end
#1 A = 1;
B = 1;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 1;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = $random % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = $random % MAX;
\t if (B === 23\'b0) B = 1;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input signed [22:0] value);
integer i, temp;
begin
temp = $random;
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire signed [22:0] a, b;
wire signed [22:0] r;
stimulus stim (.A(a), .B(b));
sdiv23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
// The IEEE standard allows the out-of-bounds part-selects to be flagged as
// compile-time errors. If they are not, this test should pass.
module top;
reg [3:0][3:0] array;
reg failed = 0;
initial begin
array = 16\'h4321;
$display("%h", array[-2+:2]); if (array[-2+:2] !== 8\'hxx) failed = 1;
$display("%h", array[-1+:2]); if (array[-1+:2] !== 8\'h1x) failed = 1;
$display("%h", array[ 0+:2]); if (array[ 0+:2] !== 8\'h21) failed = 1;
$display("%h", array[ 1+:2]); if (array[ 1+:2] !== 8\'h32) failed = 1;
$display("%h", array[ 2+:2]); if (array[ 2+:2] !== 8\'h43) failed = 1;
$display("%h", array[ 3+:2]); if (array[ 3+:2] !== 8\'hx4) failed = 1;
$display("%h", array[ 4+:2]); if (array[ 4+:2] !== 8\'hxx) failed = 1;
$display("%h", array[-1-:2]); if (array[-1-:2] !== 8\'hxx) failed = 1;
$display("%h", array[ 0-:2]); if (array[ 0-:2] !== 8\'h1x) failed = 1;
$display("%h", array[ 1-:2]); if (array[ 1-:2] !== 8\'h21) failed = 1;
$display("%h", array[ 2-:2]); if (array[ 2-:2] !== 8\'h32) failed = 1;
$display("%h", array[ 3-:2]); if (array[ 3-:2] !== 8\'h43) failed = 1;
$display("%h", array[ 4-:2]); if (array[ 4-:2] !== 8\'hx4) failed = 1;
$display("%h", array[ 5-:2]); if (array[ 5-:2] !== 8\'hxx) failed = 1;
$display("%h", array[-1:-2]); if (array[-1:-2] !== 8\'hxx) failed = 1;
$display("%h", array[ 0:-1]); if (array[ 0:-1] !== 8\'h1x) failed = 1;
$display("%h", array[ 1:0 ]); if (array[ 1:0 ] !== 8\'h21) failed = 1;
$display("%h", array[ 2:1 ]); if (array[ 2:1 ] !== 8\'h32) failed = 1;
$display("%h", array[ 3:2 ]); if (array[ 3:2 ] !== 8\'h43) failed = 1;
$display("%h", array[ 4:3 ]); if (array[ 4:3 ] !== 8\'hx4) failed = 1;
$display("%h", array[ 5:4 ]); if (array[ 5:4 ] !== 8\'hxx) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module test();
parameter BITS = 4;
parameter C = 1;
wire [BITS-1:0] a;
reg [BITS-1:0] a_bc;
assign\t a = a_bc - 2*C;
initial begin
a_bc = 9;
#1 if (a !== 7) begin
\t $display("FAILED -- a_bc=%d, a=%d", a_bc, a);
\t $finish;
end
$display("PASSED");
end
endmodule
|
module pr3534333();
/* Check compiler accepts null statements in blocks */
integer count = 0;
initial begin
end
initial begin
(* my_attr = 0 *) ;
end
initial begin
(* my_attr = 0 *) ;
#1 count = count + 1;
end
initial begin
#2 count = count + 1;
(* my_attr = 0 *) ;
end
initial begin
;
#3 count = count + 1;
;
end
initial begin
#4;;
if (count === 3)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// Copyright (c) 2001 Stephen Williams ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* This module implements what essentially amounts to an array of DFF
* devices with output enable. This test checks the operation of the
* pmos and nmos devices.
*/
module grayGap (ad, clk, read, write);
output [31:0] ad;
input\t clk, read, write;
reg [15:0] regff;
rpmos ad_drv [31:0] (ad, {16\'b0, regff}, read);
always @(posedge clk)
if (write) regff = ad[15:0];
endmodule
module main;
wire [31:0] ad;
reg\t clk, read, write;
reg [31:0] ad_val;
reg ad_en;
rnmos ad_drv[31:0] (ad, ad_val, ad_en);
grayGap test (ad, clk, read, write);
always #10 clk = ~clk;
initial begin
clk = 1;
read = 1;
write = 0;
$monitor($time, "ad=%b", ad);
// Set up to write a value into the grayGap register.
@(negedge clk)
\tad_val = 32\'haaaa_aaaa;
read = 1;
write = 1;
ad_en = 1;
// The posedge has passed, now set up to read that value
// out. Turn all the drivers off for a moment, to see that the
// line becomes tri-state...
@(negedge clk)
\tad_en = 0;
write = 0;
// Now read the value.
#1 read = 0;
#1 $display("Wrote %h, got %h", ad_val, ad);
if (ad !== 32\'b0000_0000_0000_0000_1010_1010_1010_1010) begin
\t $display("FAILED -- ad is %b", ad);
\t $finish;
end
#2 read = 1;
$display("PASSED");
$finish;
end
endmodule // main
|
module test;
// The SystemVerilog standard requires that the right side of a logical operator
// is not evaluated under certain conditions.
// For && if the left hand side is false the right hand side is not evalualted
// For || if the left hand side is true the right hand side is not evalualted
wire a0 = 1\'b0;
wire a1 = 1\'b1;
wire ax = 1\'bx;
wire az = 1\'bz;
integer b;
logic [1:0] c;
bit failed = 1\'b0;
initial begin
// AND with first parameter 1\'b0
b = 0;
c = 2\'b00;
if (a0 && b++ && ++b)
c = 2\'b01;
failed |= b !== 0;
failed |= c !== 2\'b00;
c = a0 && b++ && ++b;
failed |= b !== 0;
failed |= c !== 2\'b00;
// AND with first parameter 1\'b1
b = 0;
c = 2\'b00;
if (a1 && b++ && ++b)
c = 2\'b01;
failed |= b !== 1;
failed |= c !== 2\'b00;
c = a1 && b++ && ++b;
failed |= b !== 3;
failed |= c !== 2\'b01;
// AND with first parameter 1\'bz
b = 0;
c = 2\'b00;
if (az && b++ && ++b)
c = 2\'b01;
failed |= b !== 1;
failed |= c !== 2\'b00;
c = az && b++ && ++b;
failed |= b !== 3;
failed |= c !== 2\'b0x;
// AND with first parameter 1\'bz
b = 0;
c = 0;
if (ax && b++ && ++b)
c = 2\'b01;
failed |= b !== 1;
failed |= c !== 2\'b00;
c = ax && b++ && ++b;
failed |= b !== 3;
failed |= c !== 2\'b0x;
// OR with first parameter 1\'b0
b = 0;
c = 0;
if (a0 || b++ || ++b)
c = 2\'b01;
failed |= b !== 2;
failed |= c !== 2\'b01;
c = a0 || b++ || ++b;
failed |= b !== 3;
failed |= c !== 2\'b01;
// OR with first parameter 1\'b1
b = 0;
c = 2\'b00;
if (a1 || b++ || ++b)
c = 2\'b01;
failed |= b !== 0;
failed |= c !== 2\'b01;
c = a1 || b++ || ++b;
failed |= b !== 0;
failed |= c !== 2\'b01;
// OR with first parameter 1\'bz
b = 0;
c = 2\'b00;
if (az || b++ || ++b)
c = 2\'b01;
failed |= b !== 2;
failed |= c !== 2\'b01;
b = 0;
c = az || b++;
failed |= b !== 1;
failed |= c !== 2\'b0x;
// OR with first parameter 1\'bz
b = 0;
c = 0;
if (ax || b++ || ++b)
c = 2\'b01;
failed |= b !== 2;
failed |= c !== 2\'b01;
b = 0;
c = ax || b++;
failed |= b !== 1;
failed |= c !== 2\'b0x;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
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