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module top;
initial begin : named_begin
$display("PASSED");
end : named_begin
endmodule
|
//
// Copyright (c) 1999 Stephan Boettcher ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - PR 204 report - validates correct use of blank ports.
module none;
reg x;
endmodule // none
module empty();
reg x;
endmodule // none
module one (a);
input a;
reg x;
endmodule // one
module two (a, b);
input a, b;
reg x;
endmodule // two
module three (a, b, c);
input a, b, c;
reg x;
endmodule // two
module main;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9;
none U1 ();
empty U2 ();
one U3 ();
one U4 (w1);
one U5 (.a(w2));
two U6 ();
two U7 (,);
two U8 (w3,);
two U9 (,w4);
two Ua (w5,w6);
two Ub (.a(w7));
two Uc (.b(w8));
two Ud (.b(w8),.a(w9));
three Ue ();
//three Uf (,); //XXXX I doubt this is legal... ?
three Ug (,,);
initial $display("PASSED");
endmodule // main
|
/*
* Copyright (c) 2000 Peter monta ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
function [3:0] foo;
input [3:0] x;
begin
foo = ~x + 1;
end
endfunction
reg [3:0] x;
wire [3:0] y;
assign y = foo(x);
initial begin
x = 4\'b0110;
#1;
if (y==4\'b1010)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* This tests a trivial class. This tests that properties can be
* given types, and that the types behave properly.
*/
program main;
// Trivial example of a class
class foo_t ;
byte signed a;
byte unsigned b;
endclass : foo_t // foo_t
foo_t obj;
initial begin
obj = new;
// This is the most trivial assignment of class properties.
obj.a = \'hfff;
obj.b = \'hfff;
if (obj.a != -1 || obj.b != 255) begin
\t $display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
\t $finish;
end
obj.a = obj.a + 1;
obj.b = obj.b + 1;
if (obj.a != 0 || obj.b != 0) begin
\t $display("FAILED -- increment properties: obj.a=%0d, obj.b=%0d", obj.a, obj.b);
\t $finish;
end
$display("PASSED");
$finish;
end
endprogram // main
|
// This causes GHDL to fail with \'port "p" cannot be read\'
// since the code generator does not yet identify p as an
// internal signal as well as a port.
module top;
wire ign;
a inst(ign);
endmodule // top
module a(p);
output p;
b inst(p);
initial begin
#1;
if (p !== 1)
$display("FAILED -- p !== 1");
else
$display("PASSED");
$finish;
end
endmodule // a
module b(q);
output q;
assign q = 1;
endmodule // b
|
module top;
reg passed = 1\'b1;
realtime rvar [1:0];
initial begin
#1;
rvar[0] = -1.0;
if (rvar[0] != -1.0) begin
$display("Failed: real time array[0], expected -1.0, got %g", rvar[0]);
passed = 1\'b0;
end
rvar[1] = 2.0;
if (rvar[1] != 2.0) begin
$display("Failed: real time array[1], expected 2.0, got %g", rvar[1]);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
// Regression test for GitHub issue 19 : Icarus only using the lowest 32
// bits of right shift operand.
module bug();
wire [3:0] y = 4\'b1 << 33\'h100000000;
initial begin
#0 $display("%b", y);
if (y === 4\'b0000)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module test();
wire [7:0] value1;
wire [15:0] value2;
assign value1[3:0] = 4\'d2;
assign value2 = {2{value1}};
initial begin
#2 $display("%b %b", value1, value2);
if (value2 === 16\'bzzzz0010zzzz0010)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module test;
reg [31:0] vec;
initial begin
vec = 0; // make sure vec is not pruned
$test;
end
endmodule
|
module test();
reg a, b, en;
wire a1, a2, a3, a4, a5, a6, a7;
assign (supply1, supply0) a1 = a;
tranif1 t1(a1, a2, en);
tranif1 t2(a2, a3, en);
tranif1 t3(a3, a4, en);
tranif1 t4(a4, a5, en);
tranif1 t5(a5, a6, en);
tranif1 t6(a6, a7, en);
wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15;
wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25;
wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35;
wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45;
wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55;
assign (supply1, supply0) a11 = a, b11 = b;
assign (supply1, strong0) a12 = a, b12 = b;
assign (supply1, pull0) a13 = a, b13 = b;
assign (supply1, weak0) a14 = a, b14 = b;
assign (supply1, highz0) a15 = a, b15 = b;
assign (strong1, supply0) a21 = a, b21 = b;
assign (strong1, strong0) a22 = a, b22 = b;
assign (strong1, pull0) a23 = a, b23 = b;
assign (strong1, weak0) a24 = a, b24 = b;
assign (strong1, highz0) a25 = a, b25 = b;
assign ( pull1, supply0) a31 = a, b31 = b;
assign ( pull1, strong0) a32 = a, b32 = b;
assign ( pull1, pull0) a33 = a, b33 = b;
assign ( pull1, weak0) a34 = a, b34 = b;
assign ( pull1, highz0) a35 = a, b35 = b;
assign ( weak1, supply0) a41 = a, b41 = b;
assign ( weak1, strong0) a42 = a, b42 = b;
assign ( weak1, pull0) a43 = a, b43 = b;
assign ( weak1, weak0) a44 = a, b44 = b;
assign ( weak1, highz0) a45 = a, b45 = b;
assign ( highz1, supply0) a51 = a, b51 = b;
assign ( highz1, strong0) a52 = a, b52 = b;
assign ( highz1, pull0) a53 = a, b53 = b;
assign ( highz1, weak0) a54 = a, b54 = b;
tranif1 t11(a11, b11, en);
tranif1 t12(a12, b12, en);
tranif1 t13(a13, b13, en);
tranif1 t14(a14, b14, en);
tranif1 t15(a15, b15, en);
tranif1 t21(a21, b21, en);
tranif1 t22(a22, b22, en);
tranif1 t23(a23, b23, en);
tranif1 t24(a24, b24, en);
tranif1 t25(a25, b25, en);
tranif1 t31(a31, b31, en);
tranif1 t32(a32, b32, en);
tranif1 t33(a33, b33, en);
tranif1 t34(a34, b34, en);
tranif1 t35(a35, b35, en);
tranif1 t41(a41, b41, en);
tranif1 t42(a42, b42, en);
tranif1 t43(a43, b43, en);
tranif1 t44(a44, b44, en);
tranif1 t45(a45, b45, en);
tranif1 t51(a51, b51, en);
tranif1 t52(a52, b52, en);
tranif1 t53(a53, b53, en);
tranif1 t54(a54, b54, en);
tranif1 t55(a55, b55, en);
task display_strengths;
input ta, tb, ten;
begin
a = ta;
b = tb;
en = ten;
#1;
$display("a = %b b = %b en = %b", a, b, en);
$display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7);
$display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15);
$display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25);
$display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35);
$display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45);
$display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55);
end
endtask
initial begin
display_strengths(1\'bz, 1\'bz, 1\'bz);
display_strengths(1\'bz, 1\'bz, 1\'bx);
display_strengths(1\'bz, 1\'bz, 1\'b0);
display_strengths(1\'bz, 1\'bz, 1\'b1);
display_strengths(1\'bx, 1\'bz, 1\'bz);
display_strengths(1\'bx, 1\'bz, 1\'bx);
display_strengths(1\'bx, 1\'bz, 1\'b0);
display_strengths(1\'bx, 1\'bz, 1\'b1);
display_strengths(1\'b0, 1\'bz, 1\'bz);
display_strengths(1\'b0, 1\'bz, 1\'bx);
display_strengths(1\'b0, 1\'bz, 1\'b0);
display_strengths(1\'b0, 1\'bz, 1\'b1);
display_strengths(1\'b1, 1\'bz, 1\'bz);
display_strengths(1\'b1, 1\'bz, 1\'bx);
display_strengths(1\'b1, 1\'bz, 1\'b0);
display_strengths(1\'b1, 1\'bz, 1\'b1);
display_strengths(1\'bz, 1\'bx, 1\'bz);
display_strengths(1\'bz, 1\'bx, 1\'bx);
display_strengths(1\'bz, 1\'bx, 1\'b0);
display_strengths(1\'bz, 1\'bx, 1\'b1);
display_strengths(1\'bx, 1\'bx, 1\'bz);
display_strengths(1\'bx, 1\'bx, 1\'bx);
display_strengths(1\'bx, 1\'bx, 1\'b0);
display_strengths(1\'bx, 1\'bx, 1\'b1);
display_strengths(1\'b0, 1\'bx, 1\'bz);
display_strengths(1\'b0, 1\'bx, 1\'bx);
display_strengths(1\'b0, 1\'bx, 1\'b0);
display_strengths(1\'b0, 1\'bx, 1\'b1);
display_strengths(1\'b1, 1\'bx, 1\'bz);
display_strengths(1\'b1, 1\'bx, 1\'bx);
display_strengths(1\'b1, 1\'bx, 1\'b0);
display_strengths(1\'b1, 1\'bx, 1\'b1);
display_strengths(1\'bz, 1\'b0, 1\'bz);
display_strengths(1\'bz, 1\'b0, 1\'bx);
display_strengths(1\'bz, 1\'b0, 1\'b0);
display_strengths(1\'bz, 1\'b0, 1\'b1);
display_strengths(1\'bx, 1\'b0, 1\'bz);
display_strengths(1\'bx, 1\'b0, 1\'bx);
display_strengths(1\'bx, 1\'b0, 1\'b0);
display_strengths(1\'bx, 1\'b0, 1\'b1);
display_strengths(1\'b0, 1\'b0, 1\'bz);
display_strengths(1\'b0, 1\'b0, 1\'bx);
display_strengths(1\'b0, 1\'b0, 1\'b0);
display_strengths(1\'b0, 1\'b0, 1\'b1);
display_strengths(1\'b1, 1\'b0, 1\'bz);
display_strengths(1\'b1, 1\'b0, 1\'bx);
display_strengths(1\'b1, 1\'b0, 1\'b0);
display_strengths(1\'b1, 1\'b0, 1\'b1);
display_strengths(1\'bz, 1\'b1, 1\'bz);
display_strengths(1\'bz, 1\'b1, 1\'bx);
display_strengths(1\'bz, 1\'b1, 1\'b0);
display_strengths(1\'bz, 1\'b1, 1\'b1);
display_strengths(1\'bx, 1\'b1, 1\'bz);
display_strengths(1\'bx, 1\'b1, 1\'bx);
display_strengths(1\'bx, 1\'b1, 1\'b0);
display_strengths(1\'bx, 1\'b1, 1\'b1);
display_strengths(1\'b0, 1\'b1, 1\'bz);
display_strengths(1\'b0, 1\'b1, 1\'bx);
display_strengths(1\'b0, 1\'b1, 1\'b0);
display_strengths(1\'b0, 1\'b1, 1\'b1);
display_strengths(1\'b1, 1\'b1, 1\'bz);
display_strengths(1\'b1, 1\'b1, 1\'bx);
display_strengths(1\'b1, 1\'b1, 1\'b0);
display_strengths(1\'b1, 1\'b1, 1\'b1);
end
endmodule
|
/*
* This demonstrates a basic dynamic array
*/
module main;
longint foo[];
int idx;
initial begin
if (foo.size() != 0) begin
\t $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
\t $finish;
end
foo = new[10];
if (foo.size() != 10) begin
\t $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
\t $finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
\t foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
\t $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
\t $finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
\t $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
\t $finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
\t if (foo[idx%10] != (idx%10)) begin
\t $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]);
\t $finish;
\t end
end
foo.delete();
if (foo.size() != 0) begin
\t $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous <= in assignment.
//
module main;
reg globvar;
reg [3:0] var1;
reg error;
wire var2 = (4\'h02 >= var1);
initial
begin
error = 0;
var1 = 4\'h0 ;
#1 ;
if(var2 !== 1\'b1)
begin
$display("FAILED continuous >= logical op (1)");
error = 1;
end
#1 ;
var1 = 4\'h2;
#1 ;
if(var2 !== 1\'b1)
begin
$display("FAILED continuos <= logical op (2)");
error = 1;
end
#1 ;
var1 = 4\'h4;
#1 ;
if(var2 !== 1\'b0)
begin
$display("FAILED continuos <= logical op (3)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
// Three basic tests in here:
// 1. byte must be initialised before any initial or always block
// 2. assignments to (unsigned) bytes with random numbers
// 3. assignments to (unsigned) bytes with random values including X and Z
module ibyte_test;
parameter TRIALS = 100;
parameter MAX = \'h7fff;
reg [15:0] ar; // should it be "reg unsigned [7:0] aw"?
reg [15:0] ar_xz; // same as above here?
reg [15:0] ar_expected; // and here
shortint unsigned bu;
shortint unsigned bu_xz;
integer i;
assign bu = ar;
assign bu_xz = ar_xz;
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if (bu !== 16\'b0 | bu_xz != 16\'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// random numbers
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to byte: %b", bu);
$finish;
end
end
# 1;
// with \'x injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0
begin
$display ("FAILED - incorrect assigment to byte (when \'x): %b", bu);
$finish;
end
end
# 1;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [7:0] xz_inject (input [7:0] value); // should it be "input unsigned [7:0]" instead?
integer i, temp;
begin
temp = {$random} % MAX;
for (i=0; i<16; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random % MAX;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [15:0] xz_expected (input [15:0] value_xz); // should it be "input unsigned [7:0] instead?
integer i;
begin
for (i=0; i<16; i=i+1)
begin
if (value_xz[i] === 1\'bx || value_xz[i] === 1\'bz )
value_xz[i] = 1\'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
endmodule
|
module top;
reg pass;
reg [31:0] in2;
integer in1;
reg signed [128:0] res;
initial begin
pass = 1\'b1;
in1 = -2; in2 = 63;
res = in1 ** in2;
if (res !== -128\'sd9223372036854775808) begin
$display("Failed: -2 ** 65, expected -9223372036854775808, got %0d", res);
pass = 1\'b0;
end
in1 = -2; in2 = 65;
res = in1 ** in2;
if (res !== -128\'sd36893488147419103232) begin
$display("Failed: -2 ** 65, expected -36893488147419103232, got %0d", res);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module test;
wire [3:0] a;
reg [1:0] b;
assign a[0+:2] = b;
assign a[3-:2] = b;
initial begin
b = 2\'b01;
#1 if (a !== 4\'b0101) begin
$display("FAILED -- b=%b, a=%b", b, a);
$finish;
end
b=2\'b10;
#1 if (a !== 4\'b1010) begin
$display("FAILED -- b=%b, a=%b", b, a);
$finish;
end
$display("PASSED");
end
endmodule
|
module main;
reg [16:0] in;
wire [15:0] out;
foo_entity dut (.o_high1(out[15:12]), .o_low1(out[11:8]),
\t\t .o_high0(out[7:4]), .o_low0(out[3:0]),
\t\t .i_high1(in[15:12]), .i_low1(in[11:8]),
\t\t .i_high0(in[7:4]), .i_low0(in[3:0]));
initial begin
for (in = 0 ; in < 256 ; in = in+1) begin
\t #1 if (in !== out[15:0]) begin
\t $display("FAILED -- out=%h, in=%h", out, in);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
/*
* This program is explicitly placed in the public domain for any uses
* whatsoever.
*/
module TestMultiplier();
reg clk;
initial begin
clk = 0;
forever #0.5 clk = ~clk;
end
reg[5:0] left, right;
wire[2:0] exp;
Multiplier mul(clk, left, right, exp);
parameter ONE = {3\'b011, 3\'b0}; // 1.000 * 2**(3 - bias of 3) == 1.000
always @ (posedge clk) begin
left = ONE;
right = ONE;
#10
if (exp !== 3\'b011)
$display("FAIL: expected %b, got %b",
3\'b011, exp);
else
$display("PASSED");
$finish();
end
endmodule
/**
* A little bit of an incomplete floating-point multiplier. In/out format is
* [5:3] specify biased exponent (and hidden bit), [2:0] specify fraction.
*
* @param left[5:0], right[5:0]
* values being multiplied
* @param exp[2:0]
* exponent from product of left and right when put in the floating-point
* format of left/right
*/
module Multiplier(clk,
left, right,
exp);
input clk;
input[5:0] left, right;
output[2:0] exp;
reg[2:0] exp;
// IMPLEMENTATION
wire signed[2:0] expl = left[5:3] - 3;
wire signed[2:0] expr = right[5:3] - 3;
/** Sum of unbiased exponents in operands. */
reg signed[3:0] sumExp;
always @ (posedge clk) begin
sumExp <= (expl + expr) < -2 // why can\'t I move -2 to the right-hand side?
? -3
: expl + expr;
exp[2:0] <= sumExp + 3;
end
endmodule
|
module bug;
reg [3:0] r1;
wire [3:0] w1;
wire [3:0] w2;
assign w1 = r1;
assign w2 = w1;
reg fail = 0;
initial begin
r1 = 0;
#1 $display("%b %b %b", r1, w1, w2);
if ((r1 !== 4\'b0000) || (w1 !== 4\'b0000) || (w2 !== 4\'b0000)) fail = 1;
force w1 = 4\'bz;
#1 $display("%b %b %b", r1, w1, w2);
if ((r1 !== 4\'b0000) || (w1 !== 4\'bzzzz) || (w2 !== 4\'bzzzz)) fail = 1;
r1 = 1;
#1 $display("%b %b %b", r1, w1, w2);
if ((r1 !== 4\'b0001) || (w1 !== 4\'bzzzz) || (w2 !== 4\'bzzzz)) fail = 1;
release w1;
#1 $display("%b %b %b", r1, w1, w2);
if ((r1 !== 4\'b0001) || (w1 !== 4\'b0001) || (w2 !== 4\'b0001)) fail = 1;
r1 = 2;
#1 $display("%b %b %b", r1, w1, w2);
if ((r1 !== 4\'b0010) || (w1 !== 4\'b0010) || (w2 !== 4\'b0010)) fail = 1;
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module foo_mod(output reg pass_flag, input wire go_flag);
typedef enum logic [1:0] { W0, W1, W2 } foo_t;
foo_t foo;
always @(posedge go_flag) begin
pass_flag = 0;
if ($bits(foo) !== 2) begin
\t $display("FAILED -- $bits(foo)=%0d", $bits(foo));
\t $finish;
end
if ($bits(foo_t) !== 2) begin
\t $display("FAILED -- $bits(foo_t)=%0d", $bits(foo_t));
\t $finish;
end
pass_flag = 1;
end
endmodule
module main;
logic go_flag = 0;
wire [1:0] pass_flag;
foo_mod dut[1:0] (.pass_flag(pass_flag), .go_flag(go_flag));
initial begin
#1 go_flag = 1;
#1 if (pass_flag !== 2\'b11) begin
\t $display("FAILED -- pass_flag=%b", pass_flag);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* This module instantiates the fa4 entity, which in turn
* instantiates other entities. This demonstrates hierarchical
* constructs in VHDL.
*/
module test;
reg [3:0] a, b;
reg cin;
wire [3:0] s;
wire cout;
initial begin
cin = 0;
a = 4\'h2;
b = 4\'h3;
end
initial begin
#1;
if (s !== 4\'h5) begin
$display("Error in trivial sum");
$finish;
end
$display ("PASSED");
end
fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) );
endmodule // test
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always while (boolean_expression ) statement ;
module main ;
reg [3:0] value1,value2,value3;
initial
\tbegin
value1 = 0;\t\t// Time 0 assignemnt
value2 = 0;
#6 ;
if(value1 != 4\'h1)
begin
$display("FAILED - 3.1.7C always while (1\'b1 )") ;
value2 = 1;
end
#5 ;
if(value1 != 4\'h2)
begin
$display("FAILED - 3.1.7C always while (1\'b1) ");
value2 = 1;
end
#5 ;
if(value1 != 4\'h3)
begin
$display("FAILED - 3.1.7C always while (1\'b1) ");
value2 = 1;
end
if(value2 == 0)
$display("PASSED");
\t $finish;
end
always while (1\'b1 && 1\'b1) begin
#5 ;
value1 = value1 + 1;
\t\t\t end
endmodule
|
/*
* Copyright (c) 2008 Gyorgy Jeney ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module fpu_li_s1();
parameter eh = 11;
parameter [eh - 1:0] alap = 1023;
parameter ih2 = 6;
parameter fh = 7;
parameter [fh - 1:0] falap = 63;
localparam ih = 1 << ih2;
localparam nh = (eh > fh ? eh : fh) + 1;
wire [nh - 1:0] exp_norm;
/* IVL compiles this fine but when trying to run it through vvp, it throws
* this error:
*
* internal error: port 0 expects wid=11, got wid=12
* vvp: concat.cc:56: virtual void vvp_fun_concat::recv_vec4(vvp_net_ptr_t, const
* vvp_vector4_t&): Assertion `0\' failed.
* Aborted
*
* This is a regression caused by this commit:
* commit a914eda5eff8b088837432a6516584b6a075fcd6
* Author: Stephen Williams <[email protected]>
* Date: Tue Apr 8 20:50:36 2008 -0700
*
* Get part select from vectored parameters correct.
*
* Parameters with vector descriptions that are not zero based and
* are used in net contexts should generate the properly ranged
* temporary signals. This causes subsequent part selects to work
* out properly.
*/
assign exp_norm = alap - falap + ih;
initial
begin
\t#1 $display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate task with internal delay
module main;
reg var1,var2;
reg in1;
reg error;
task my_task ;
input in1;
output out1;
out1 = #10 in1;
endtask
initial
begin
var1 = 0;
error = 0;
fork
my_task(1\'b1,var1);
begin
if(var1 != 1\'b0)
begin
$display("FAILED - task3.14F Task with internal delay(1)");
error = 1;
end
#20;
if(var1 != 1\'b1)
begin
$display("FAILED - task3.14F Task with internal delay(2)");
error = 1;
end
end
join
if(error == 0)
$display("PASSED");
end
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate the ? operator
module main;
reg globvar;
reg [3:0] bvec;
reg [3:0] var1,var2,var3;
reg cond, a,b,out1,out2;
reg error;
initial
begin
error = 0;
bvec = 4\'bzx10 ;
for(var1 = 0;var1 <= 4\'h3; var1 = var1+1)
begin
for(var2 = 0;var2 <= 4\'h3;var2 = var2+1)
begin
for(var3= 0; var3 <= 4\'h3;var3 = var3+1)
begin
cond = bvec[var1];
a = bvec[var2];
b = bvec[var3];
out1 = cond ? a: b ;
if(cond)
out2 = a ;
else
out2 = b;
if(out1 != out2)
begin
$display("FAILED - qmark2 - %b %b %b %b %b",
cond,a,b,out1,out2);
error = 1;
end
end
end
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
module top;
reg passed;
// These should be OK
enum {zdef1_[0:1]} zdef1;
enum {zdef2_[1:0]} zdef2;
enum {zdefb_[0:0]} zdef3;
enum {zvalb_[0:0] = 1} zval1;
initial begin
passed = 1\'b1;
if (zdef1_0 !== 0) begin
$display("FAILED: expected zdef1_0 to be 0, got %0d", zdef1_0);
passed = 1\'b0;
end
if (zdef1_1 !== 1) begin
$display("FAILED: expected zdef1_1 to be 1, got %0d", zdef1_1);
passed = 1\'b0;
end
if (zdef2_1 !== 0) begin
$display("FAILED: expected zdef2_1 to be 0, got %0d", zdef2_1);
passed = 1\'b0;
end
if (zdef2_0 !== 1) begin
$display("FAILED: expected zdef2_0 to be 1, got %0d", zdef2_0);
passed = 1\'b0;
end
if (zdefb_0 !== 0) begin
$display("FAILED: expected zdefb_0 to be 0, got %0d", zdefb_0);
passed = 1\'b0;
end
if (zvalb_0 !== 1) begin
$display("FAILED: expected zvalb_0 to be 1, got %0d", zvalb_0);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
`define PERIOD 10
module main;
reg\t CLK;
integer counter;
initial begin\t\t// reset and clock generator
counter = 0;
CLK = 0;
#2;\t\t\t// wait 2, and then...
repeat(10)\t\t// generate 5 clock cycles
\t#(`PERIOD/2) CLK = !CLK;
$display("time %0t; the counter is %0d", $time, counter);
$finish(0);
end
task test1;
begin
\t @(posedge CLK);
\t $display("test1 increment; reading counter as %0d", counter);
\t // the function call is necessary to get the problem
\t counter = _$Fadd32(counter, 1\'b1);
end
endtask
task test2;
begin
\t @(posedge CLK);
\t $display("test2 increment; reading counter as %0d", counter);
\t counter = _$Fadd32(counter, 1\'b1);
end
endtask
function [31:0] _$Fadd32;
input l,r;
reg [31:0] l,r;
_$Fadd32 = l+r;
endfunction
endmodule\t\t\t// main
module trig1;
always begin
#`PERIOD;
top.main.test1;
end
endmodule
module trig2;
always begin
#`PERIOD;
top.main.test2;
end
endmodule
module top;
main main();
trig1 trig1();
trig2 trig2();
endmodule
|
timeunit 10us;
timeprecision 10us;
module fast_g (out);
output out;
reg\t out;
initial begin
#0 out = 0;
#1 out = 1; // 10us
end
endmodule // fast_g
`timescale 100us / 1us
// These will be ignored since a `timescale was already given.
timeunit 10us;
timeprecision 10us;
module slow (out);
output out;
reg\t out;
initial begin
#0 out = 0;
#1 out = 1; // 100us
end
endmodule // slow
module fast (out);
timeunit 10us;
timeprecision 1us;
output out;
reg\t out;
initial begin
#0 out = 0;
#1 out = 1; // 10us
end
endmodule // fast
module saf(out);
output out;
reg\t out;
initial begin
#0 out = 0;
#1 out = 1; // 100us
end
endmodule // saf
`timescale 1us / 1us
module main;
reg pass;
wire slow, fast, fast_g, saf;
slow m1 (slow);
fast_g m2 (fast_g);
fast m3 (fast);
saf m4 (saf);
initial begin
pass = 1\'b1;
#9;
\tif (slow !== 1\'b0) begin
\t $display("FAILED: slow at 9us, expected 1\'b0, got %b.", slow);
\t pass = 1\'b0;
\tend
\tif (saf !== 1\'b0) begin
\t $display("FAILED: saf at 9us, expected 1\'b0, got %b.", saf);
\t pass = 1\'b0;
\tend
if (fast !== 1\'b0) begin
\t $display("FAILED: fast at 9us, expected 1\'b0, got %b.", fast);
\t pass = 1\'b0;
\tend
if (fast_g !== 1\'b0) begin
\t $display("FAILED: fast_g at 9us, expected 1\'b0, got %b.", fast_g);
\t pass = 1\'b0;
\tend
#2 // 11us
\tif (slow !== 1\'b0) begin
\t $display("FAILED: slow at 11us, expected 1\'b0, got %b.", slow);
\t pass = 1\'b0;
\tend
\tif (saf !== 1\'b0) begin
\t $display("FAILED: saf at 11us, expected 1\'b0, got %b.", saf);
\t pass = 1\'b0;
\tend
if (fast !== 1\'b1) begin
\t $display("FAILED: fast at 11us, expected 1\'b1, got %b.", fast);
\t pass = 1\'b0;
\tend
if (fast_g !== 1\'b1) begin
\t $display("FAILED: fast_g at 11us, expected 1\'b1, got %b.", fast_g);
\t pass = 1\'b0;
\tend
#88 // 99 us
\tif (slow !== 1\'b0) begin
\t $display("FAILED: slow at 99us, expected 1\'b0, got %b.", slow);
\t pass = 1\'b0;
\tend
\tif (saf !== 1\'b0) begin
\t $display("FAILED: saf at 99us, expected 1\'b0, got %b.", saf);
\t pass = 1\'b0;
\tend
if (fast !== 1\'b1) begin
\t $display("FAILED: fast at 99us, expected 1\'b1, got %b.", fast);
\t pass = 1\'b0;
\tend
if (fast_g !== 1\'b1) begin
\t $display("FAILED: fast_g at 99us, expected 1\'b1, got %b.", fast_g);
\t pass = 1\'b0;
\tend
#2 // 101 us
\tif (slow !== 1\'b1) begin
\t $display("FAILED: slow at 101us, expected 1\'b1, got %b.", slow);
\t pass = 1\'b0;
\tend
\tif (saf !== 1\'b1) begin
\t $display("FAILED: saf at 101us, expected 1\'b1, got %b.", saf);
\t pass = 1\'b0;
\tend
if (fast !== 1\'b1) begin
\t $display("FAILED: fast at 101us, expected 1\'b1, got %b.", fast);
\t pass = 1\'b0;
\tend
if (fast_g !== 1\'b1) begin
\t $display("FAILED: fast_g at 101us, expected 1\'b1, got %b.", fast_g);
\t pass = 1\'b0;
\tend
if (pass) $display("PASSED");
end // initial begin
endmodule // main
|
module top;
reg passed;
reg [4:1] result;
initial begin
passed = 1\'b1;
result = 4\'b0000;
// Fork some processes and wait for the one with the least delay to finish.
fork
#3 result[3] = 1\'b1;
#4 result[4] = 1\'b1;
join_none
fork
#1 result[1] = 1\'b1;
#2 result[2] = 1\'b1;
join_any
// Disable the rest of the forked processes.
disable fork;
// Only the 1st bit should be set.
if (result !== 4\'b0001) begin
$display("More than one process ran before the disable fork: %b", result);
passed = 1\'b0;
result = 4\'b0001;
end
// Wait to make sure the disabled processes do not run at a later time.
#10;
// Only the 1st bit should still be set.
if (result !== 4\'b0001) begin
$display("Processes ran to completion after being disabled: %b", result);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
// Check that it is an error to declare a non-ANSI module port with implicit
// packed dimensions if it is later redeclared as a time typed variable. Even if
// the size of the packed dimensions matches that of the size of the time type.
module test(x);
output [63:0] x;
time x;
initial begin
$display("FAILED");
end
endmodule
|
module signed_logic_operators_bug();
reg [7:0] a, b;
wire [15:0] yuu, yus, ysu, yss;
wire [15:0] zuu, zus, zsu, zss;
initial begin
// Example vector
a = 8\'b10110110;
b = 8\'b10010010;
// Wait for results to be calculated
#1;
// Display results
$display("a = %b", a);
$display("b = %b", b);
$display("yuu = %b", yuu);
$display("zuu = %b", zuu);
$display("yus = %b", yus);
$display("zus = %b", zus);
$display("ysu = %b", ysu);
$display("zsu = %b", zsu);
$display("yss = %b", yss);
$display("zss = %b", zss);
// Finished
$finish(0);
end
// Calculate signed logical OR
manually_extended_logical_or INST1(.a(a), .b(b), .yuu(yuu), .yus(yus), .ysu(ysu), .yss(yss));
signed_logical_or INST2(.a(a), .b(b), .yuu(zuu), .yus(zus), .ysu(zsu), .yss(zss));
endmodule
module manually_extended_logical_or(a, b, yuu, yus, ysu, yss);
input [7:0] a, b;
output [15:0] yuu, yus, ysu, yss;
// Manually zero or sign extend operands before logic OR
// - Note the operands are zero extended in "yuu", "yus" and "ysu"
// - The operands are sign extended in "yss"
assign yuu = {{8{1\'b0}}, a} | {{8{1\'b0}}, b};
assign yus = {{8{1\'b0}}, a} | {{8{1\'b0}}, b};
assign ysu = {{8{1\'b0}}, a} | {{8{1\'b0}}, b};
assign yss = {{8{a[7]}}, a} | {{8{b[7]}}, b};
endmodule
module signed_logical_or(a, b, yuu, yus, ysu, yss);
input [7:0] a, b;
output [15:0] yuu, yus, ysu, yss;
// Note that the operation is only consider signed if ALL data operands are signed
// - Therefore $signed(a) does NOT sign extend "a" in expression "ysu"
// - But "a" and "b" are both sign extended before the OR in expression "yss"
assign yuu = a | b ;
assign yus = a | $signed(b);
assign ysu = $signed(a) | b ;
assign yss = $signed(a) | $signed(b);
endmodule
|
module top;
task automatic worker(int delay);
#delay $display("worker finished at %0d.", delay);
endtask
initial begin
fork
worker(10);
worker(5);
join_any
$display("fork has joined (any)");
if ($time != 5) begin
$display("FAILED -- time=%0t", $time);
$finish;
end
$display("PASSED");
end
endmodule
|
`define TBMESS(str) $display("PAS%s", str );
// 1364-2001 S19.3 "The text macro facility is not affected by the compiler
// directive `resetall."
`resetall
module main;
initial `TBMESS("SED")
endmodule
|
// Regression test for GitHub issue 19 : Icarus only using the lowest 32
// bits of right shift operand (run-time test)
module bug();
wire a = 1;
wire y = 1 >> {a, 64\'b0};
initial begin
#0 $display("%b", y);
if (y === 1\'b0)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module tb;
string txt_i, txt_r, txt_h;
int\t val_i;
int val_h;
real val_r;
initial begin
txt_i = "123";
txt_r = "1.25";
txt_h = "dead";
val_i = txt_i.atoi();
val_r = txt_r.atoreal();
val_h = txt_h.atohex();
$display("txt_i=%s, val_i=%0d", txt_i, val_i);
if (val_i !== 123) begin
\t $display("FAILED");
\t $finish;
end
$display("txt_r=%s, val_r=%0f", txt_r, val_r);
if (val_r != 1.25) begin
\t $display("FAILED");
\t $finish;
end
$display("txt_h=%s, val_h=%0h", txt_h, val_h);
if (val_h !== \'hdead) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule
|
/*
* 23.2.2.3 Rules for determining port kind, data type, and direction says
*
* For output ports, the default port kind depends on how the data type is
* specified:
* - If the data type is omitted or declared with the implicit_data_type
* syntax, the port kind shall default to a net of default net type.
* - If the data type is declared with the explicit data_type syntax, the port
* kind shall default to variable.
*/
typedef enum { A, B } E;
module main;
E in;
wire E out;
M foo (in, out);
initial begin
in = A;
#1 if (out !== A) begin
\t $display("FAIL: in=%0d, out=%0d", in, out);
\t $finish;
end
in = B;
#1 if (out !== B) begin
\t $display("FAIL: in=%0d, out=%0d", in, out);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
module M (input E ei,
\t output E eo);
always_comb eo = ei;
endmodule // M
|
module top;
reg [10*8-1:0] str [2:0];
reg [31:0] idx [2:0];
reg [4*8-1:0] pvstr, pvstr2;
reg [15:0] pvidx, pvidx2, pvbase;
initial begin
pvstr = "S";
pvstr2 = "SF";
pvidx = \'d2;
pvidx2 = \'d8;
pvbase = \'d0;
str[0] = "FAIL";
str[1] = "PA";
str[2] = "ED";
idx[0] = 0;
idx[1] = 1;
idx[2] = 2;
$write("%0s", str[idx[1]]); // This prints PA or FAIL.
$write("%0s", pvstr[idx[0] +: 16]); // This adds an S.
$write("%0s", pvstr2[pvidx2[pvbase +: 4] +: 8]); // This adds another S.
$display("%0s", str[pvidx[pvbase +: 8]]); // This adds the ED.
end
endmodule
|
module top;
parameter a_res = 16\'b000001xx0xxx0xxx;
parameter o_res = 16\'b01xx1111x1xxx1xx;
parameter x_res = 16\'b01xx10xxxxxxxxxx;
reg pass;
reg [15:0] y, z, a, o, x;
reg [127:0] yl, zl, al, ol, xl;
initial begin
pass = 1\'b1;
y = 16\'b01xz01xz01xz01xz;
z = 16\'b00001111xxxxzzzz;
yl = {8{y}};
zl = {8{z}};
// Check the & results
a = y & z;
if (a !== a_res) begin
$display("FAILED: & test, expected %b, got %b", a_res, a);
pass = 1\'b0;
end
al = yl & zl;
if (al !== {8{a_res}}) begin
$display("FAILED: & (large) test, expected %b, got %b", {8{a_res}}, al);
pass = 1\'b0;
end
// Check the | results
o = y | z;
if (o !== o_res) begin
$display("FAILED: | test, expected %b, got %b", o_res, o);
pass = 1\'b0;
end
ol = yl | zl;
if (ol !== {8{o_res}}) begin
$display("FAILED: | (large) test, expected %b, got %b", {8{o_res}}, ol);
pass = 1\'b0;
end
// Check the ^ results
x = y ^ z;
if (x !== x_res) begin
$display("FAILED: | test, expected %b, got %b", x_res, x);
pass = 1\'b0;
end
xl = yl ^ zl;
if (xl !== {8{x_res}}) begin
$display("FAILED: ^ (large) test, expected %b, got %b", {8{x_res}}, xl);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
////////////////////////////////////////////////////////////////////////
// Copyright 2003 University of Kentucky
//
// This file is released into the public domain
////////////////////////////////////////////////////////////////////////
//
// Top level module
//
module top();
\tparameter tp = \'d1;
\treg a;
\twire b;
\tbot b1(b, a);
\tinitial begin
\t\ta = 0;
\t\t$display("tp = %d in top", tp);
\tend
endmodule
//
// bottom level module
//
`define div 0.100
module bot(a, b);
\tinput b;
\toutput a;
\treal tp;\t// tp is overridden by tp parameter in top
\treal tp2;
\tassign a = b;
\tinitial begin
\t\ttp = 1 / `div;
\t\ttp2 = 1 / `div;
\t\t$display("tp = %f, tp2 = %f", tp, tp2);
\t\tif (tp != 10.0)
\t\t\t$display("tp != 10.0. (tp = %f)", tp);
\t\telse
\t\t\t$display("tp == 10, (expected)");
\t\t#1 $display("tp = %f, tp2 = %f", tp, tp2);
\tend
endmodule
|
`begin_keywords "1364-2005"
/*
* This tests the synthesis of a case statement that has an empty case.
*/
module main;
reg clk, bit, foo, clr;
// Synchronous device that toggles whenever enabled by a high bit.
always @(posedge clk or posedge clr)
if (clr) foo = 0;
else case (bit)
1\'b0: ;
1\'b1: foo <= ~foo;
endcase // case(bit)
(* ivl_synthesis_off *)
always begin
#5 clk = 1;
#5 clk = 0;
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
bit = 0;
clr = 1;
# 6 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 0 || foo !== 0) begin
\t $display("FAILED");
\t $finish;
end
clr = 0;
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 0 || foo !== 0) begin
\t $display("FAILED");
\t $finish;
end
bit <= 1;
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 1 || foo !== 1) begin
\t $display("FAILED");
\t $finish;
end
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 1 || foo !== 0) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
`end_keywords
|
module test_logic
#(parameter WID = 4)
(input wire [WID-1:0] A,
output q_and, q_or, q_xor, q_nand, q_nor, q_xnor);
assign q_and = & A;
assign q_or = | A;
assign q_xor = ^ A;
assign q_nand= ~& A;
assign q_nor = ~| A;
assign q_xnor= ~^ A;
endmodule // test_logic
|
`timescale 100 ps / 10 ps
module test;
reg cdn, cp, d;
wire qr, qp;
initial begin
$timeformat(-9, 2, " ns", 9);
$monitor("%t - cdn=%b, cp=%b, d=%b, qr=%b, qp=%b",$time,cdn,cp,d,qr,qp);
// Reset the FF.
cp = 0; d = 1;
#100 cdn = 0;
#100 cdn = 1;
// Toggle in some data.
#100 cp = 1;
#100 cp = 0; d = 0;
#100 cp = 1;
#100 cp = 0; d = 1;
#100 cp = 1;
end
dff_rtl dutr(qr, d, cp, cdn); // This one works fine.
dff_prm dutp(qp, d, cp, cdn); // This one has no delay.
endmodule
// The RTL version appears to work fine.
module dff_rtl (q, d, cp, cdn);
output q;
input d;
input cp;
input cdn;
reg qi;
always @(posedge cp or negedge cdn) begin
if (~cdn) qi <= 1\'b0;
else qi <= d;
end
buf (q, qi);
specify
specparam tpd_cp_q_lh = 6;
specparam tpd_cp_q_hl = 7;
specparam tpd_cdn_q_lh = 0;
specparam tpd_cdn_q_hl = 3;
if (cdn) (posedge cp => (q +: d)) = (tpd_cp_q_lh, tpd_cp_q_hl);
(negedge cdn => (q +: 1\'b0)) = (tpd_cdn_q_lh, tpd_cdn_q_hl);
endspecify
endmodule
// The primitive version has no delay.
module dff_prm (q, d, cp, cdn);
output q;
input d, cp, cdn;
UDP_DFF G3(q, d, cp, cdn);
specify
specparam tpd_cp_q_lh = 6;
specparam tpd_cp_q_hl = 7;
specparam tpd_cdn_q_lh = 0;
specparam tpd_cdn_q_hl = 3;
if (cdn) (posedge cp => (q +: d)) = (tpd_cp_q_lh, tpd_cp_q_hl);
(negedge cdn => (q +: 1\'b0)) = (tpd_cdn_q_lh, tpd_cdn_q_hl);
endspecify
endmodule
// This is overly simplistic, but it works for this example.
primitive UDP_DFF(q, d, cp, cdn);
output q;
reg q;
input d, cp, cdn;
table
// d cp cdn q0 q
* ? ? : ? : - ;
? n ? : ? : - ;
0 r 1 : ? : 0 ;
1 r 1 : ? : 1 ;
? ? 0 : ? : 0 ;
? ? p : ? : - ;
endtable
endprimitive
|
`begin_keywords "1364-2005"
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass = 1\'b1;
// reg [3:0] var = 4\'b1001;
wire [3:0] var = 4\'b1001;
// parameter [3:0] var = 4\'b1001;
reg [3:0] part;
reg [5:0] big;
initial begin
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = var[1:-2]; // should be 01xx.
if (part !== 4\'b01xx) begin
$display("part select [1:-2] failed, expected 4\'b01xx, got %b", part);
pass = 1\'b0;
end
part = var[5:2]; // should be xx10.
if (part !== 4\'bxx10) begin
$display("part select [5:2] failed, expected 4\'bxx10, got %b", part);
pass = 1\'b0;
end
big = var[4:-1]; // should be x10100101x.
if (big !== 6\'bx1001x) begin
$display("part select [4:-1] failed, expected 6\'bx1001x, got %b", big);
pass = 1\'b0;
end
`endif
if (pass) $display("PASSED");
end
endmodule
`end_keywords
|
module top;
parameter parm = 1.4;
reg [31:0] str;
initial begin
$sformat(str, "R: %d", parm);
if (str !== " 1") $display("FAILED: expected \' 1\', got %s", str);
else $display("PASSED");
end
endmodule
|
module top;
function real copy(input real r);
copy = r;
endfunction
real a, b, c, d, e, f;
initial begin
a = 0.4;
b = 0.5;
c = 0.6;
d = 2.4;
e = 2.5;
f = 2.6;
$display("a: %.1f %0d %0x %0b", copy(a), copy(a), copy(a), copy(a));
$display("b: %.1f %0d %0x %0b", copy(b), copy(b), copy(b), copy(b));
$display("c: %.1f %0d %0x %0b", copy(c), copy(c), copy(c), copy(c));
$display("d: %.1f %0d %0x %0b", copy(d), copy(d), copy(d), copy(d));
$display("e: %.1f %0d %0x %0b", copy(e), copy(e), copy(e), copy(e));
$display("f: %.1f %0d %0x %0b", copy(f), copy(f), copy(f), copy(f));
a = -0.4;
b = -0.5;
c = -0.6;
d = -2.4;
e = -2.5;
f = -2.6;
$display("a: %.1f %0d %0x %0b", copy(a), copy(a), copy(a), copy(a));
$display("b: %.1f %0d %0x %0b", copy(b), copy(b), copy(b), copy(b));
$display("c: %.1f %0d %0x %0b", copy(c), copy(c), copy(c), copy(c));
$display("d: %.1f %0d %0x %0b", copy(d), copy(d), copy(d), copy(d));
$display("e: %.1f %0d %0x %0b", copy(e), copy(e), copy(e), copy(e));
$display("f: %.1f %0d %0x %0b", copy(f), copy(f), copy(f), copy(f));
end
endmodule
|
module top;
// You can\'t have an over range value (compile time error).
enum bit[4:0] {some[4] = 100} val;
initial $display("FAILED");
endmodule
|
// Check that trying to override a parameter that does not exist results in an
// error
module a #(
parameter A = 1
);
initial begin
$display("FAILED");
end
endmodule
module test;
a #(
.Z(10) // Error
) i_a();
endmodule
|
module top;
reg [63:0] str;
reg [31:0] in, out;
integer res;
initial begin
// To avoid embedded NULL bytes each byte must have an x or a 1 and a z.
in = 32\'b000x100z_001z000x_101xxxzz_100z111x;
$sformat(str, "%z", in);
res = $sscanf(str, "%z", out);
if (res !== 1) $display("FAILED: $sscanf() returned %d", res);
else if (in !== out) $display("FAILED: %b !== %b", in, out);
else $display("PASSED");
end
endmodule
|
/*
* This tests the handling of signed/types parameters. This is a test
* of the complaints from pr 1449749.
*/
module main;
parameter foo = -2;
parameter integer bar = -3;
parameter signed [5:0] bat = -7;
initial begin
$display("foo=%d, bar=%d, tmp=%d", foo, bar, bat);
if (foo >= 0) begin
\t $display("FAILED -- -2 > 0");
\t $finish;
end
if (foo != -2) begin
\t $display("FAILED");
\t $finish;
end
if (bar >= 0) begin
\t $display("FAILED -- -3 > 0");
\t $finish;
end
if (bar != -3) begin
\t $display("FAILED");
\t $finish;
end
if (bat >= 0) begin
\t $display("FAILED -- -7 > 0");
\t $finish;
end
if (bat != -7) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Check that it is possible to declare the data type for an integer type module
// port separately from the direction for non-ANSI style port declarations.
// declarations.
module test(x);
output x;
integer x;
initial begin
if ($bits(x) == $bits(integer)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
/*
* This example is based on PR#584 in the bugs database.
*/
module main;
reg clk;
always #50 clk = ~clk;
initial begin
clk = 0;
#100
$display("%d", 1e3*2e-2);
$display("%d", 1e2*0.2);
$display("%d", 1e1*2); // prints ok
$display("%d", 1e0*20.0); // prints ok
$display("%d", 1e-1*200.0);
// bug -- some correctly report "20" and others report "0"
// looks like implicit real2integer conversion for every factor in expression
// problem caused by partial support of reals
$finish(0);
end
endmodule
|
module a;
initial begin : b
reg x;
end
initial fork : c
reg x;
join
initial begin
a.b.x = 1\'b0;
a.c.x = 1\'b1;
$display("PASSED");
end
endmodule
|
/*
* Author: Oswaldo Cadenas <[email protected]>
*
* The test checks the module bit ouput type accepts default
* initialization value.
*/
module clkgen(output bit clk = 0);
initial begin
#100;
disable checking;
disable gen;
$display ("PASSED");
$finish;
end
initial begin
fork
gen;
checking;
join
end
task gen;
forever #10 clk = ~clk;
endtask
task checking;
forever begin
#1;
if (clk ==! 1\'b0 && clk ==! 1\'b1 ) begin
$display ("FAILED!");
\t $finish;
end
end
endtask
endmodule
|
module dff();
reg clk;
reg rst;
reg ce;
reg [3:0] s;
reg [3:0] d;
reg [3:0] q;
always @(negedge clk or posedge rst) begin
if (rst)
q <= s;
else if (ce)
q <= d;
end
(* ivl_synthesis_off *)
reg failed = 0;
initial begin
$monitor("%b %b %b %b", rst, clk, d, q);
clk = 1\'b0;
ce = 1\'b0;
rst = 1\'b0;
s = 4\'b1001;
d = 4\'b0110;
#1;
if (q !== 4\'bxxxx) failed = 1;
rst = 1\'b1;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b1;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b0;
#1;
if (q !== 4\'b1001) failed = 1;
rst = 1\'b0;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b1;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b0;
#1;
if (q !== 4\'b1001) failed = 1;
ce = 1\'b1;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b1;
#1;
if (q !== 4\'b1001) failed = 1;
clk = 1\'b0;
#1;
if (q !== 4\'b0110) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule // dff
|
module test;
parameter TRUE = 1;
genvar i;
genvar j;
for (i = 0; i < 2; i = i + 1) begin : l1
reg r1 = 1;
end
for (i = 0; i < 2; i = i + 1) begin : l2
for (j = 0; j < 2; j = j + 1) begin : l1
reg r2 = 1;
end
end
for (i = 0; i < 2; i = i + 1) begin : l3
case (TRUE)
0: begin : c1
reg r3a = 1;
end
1: begin : c1
reg r3b = 1;
end
endcase
end
for (i = 0; i < 2; i = i + 1) begin : l4
if (TRUE)
begin : i1
reg r4a = 1;
end
else
begin : i1
reg r4b = 1;
end
end
for (i = 0; i < 2; i = i + 1) begin : l5
if (!TRUE)
begin : i1
reg r5a = 1;
end
else
begin : i1
if (TRUE)
begin : i1
reg r5b = 1;
end
else
begin : i1
reg r5c = 1;
end
end
end
for (i = 0; i < 2; i = i + 1) begin : l6
if (!TRUE)
begin : i1
reg r6a = 1;
end
else
begin : i1
if (!TRUE)
begin : i1
reg r6b = 1;
end
else
begin : i1
reg r6c = 1;
end
end
end
case (TRUE)
0: begin : c1
reg r7a = 1;
end
1: begin : c1
reg r7b = 1;
end
endcase
case (TRUE)
0: begin : c2
case (TRUE)
0: begin : c1
reg r8a = 1;
end
1: begin : c1
reg r8b = 1;
end
endcase
end
1: begin : c2
case (TRUE)
0: begin : c1
reg r8c = 1;
end
1: begin : c1
reg r8d = 1;
end
endcase
end
endcase
case (TRUE)
0: begin : c3
if (TRUE)
begin : i1
reg r9a = 1;
end
else
begin : i1
reg r9b = 1;
end
end
1: begin : c3
if (TRUE)
begin : i1
reg r9c = 1;
end
else
begin : i1
reg r9d = 1;
end
end
endcase
case (TRUE)
0: begin : c4
if (!TRUE)
begin : i1
reg r10a = 1;
end
else
begin : i1
if (TRUE)
begin : i1
reg r10b = 1;
end
else
begin : i1
reg r10c = 1;
end
end
end
1: begin : c4
if (!TRUE)
begin : i1
reg r10d = 1;
end
else
begin : i1
if (TRUE)
begin : i1
reg r10e = 1;
end
else
begin : i1
reg r10f = 1;
end
end
end
endcase
case (TRUE)
0: begin : c5
if (!TRUE)
begin : i1
reg r11a = 1;
end
else
begin : i1
if (!TRUE)
begin : i1
reg r11b = 1;
end
else
begin : i1
reg r11c = 1;
end
end
end
1: begin : c5
if (!TRUE)
begin : i1
reg r11d = 1;
end
else
begin : i1
if (!TRUE)
begin : i1
reg r11e = 1;
end
else
begin : i1
reg r11f = 1;
end
end
end
endcase
case (TRUE)
0: begin : c6
if (!TRUE)
begin : i1
reg r12a = 1;
end
else if (TRUE)
begin : i1
reg r12b = 1;
end
else
begin : i1
reg r12c = 1;
end
end
1: begin : c6
if (!TRUE)
begin : i1
reg r12d = 1;
end
else if (TRUE)
begin : i1
reg r12e = 1;
end
else
begin : i1
reg r12f = 1;
end
end
endcase
case (TRUE)
0: begin : c7
if (!TRUE)
begin : i1
reg r13a = 1;
end
else if (!TRUE)
begin : i1
reg r13b = 1;
end
else
begin : i1
reg r13c = 1;
end
end
1: begin : c7
if (!TRUE)
begin : i1
reg r13d = 1;
end
else if (!TRUE)
begin : i1
reg r13e = 1;
end
else
begin : i1
reg r13f = 1;
end
end
endcase
if (TRUE)
begin : i01
reg r14a = 1;
end
else
begin : i01
reg r14b = 1;
end
if (!TRUE)
begin : i02
reg r15a = 1;
end
else
begin : i02
if (TRUE)
begin : i1
reg r15b = 1;
end
else
begin : i1
reg r15c = 1;
end
end
if (!TRUE)
begin : i03
reg r16a = 1;
end
else
begin : i03
if (!TRUE)
begin : i1
reg r16b = 1;
end
else
begin : i1
reg r16c = 1;
end
end
if (!TRUE)
begin : i04
reg r17a = 1;
end
else if (TRUE)
begin : i04
reg r17b = 1;
end
else
begin : i04
reg r17c = 1;
end
if (!TRUE)
begin : i05
reg r18a = 1;
end
else if (!TRUE)
begin : i05
reg r18b = 1;
end
else
begin : i05
reg r18c = 1;
end
if (TRUE)
begin : i06
if (TRUE)
begin : i1
reg r19a = 1;
end
else
begin : i1
reg r19b = 1;
end
end
else
begin : i06
reg r19c = 1;
end
if (TRUE)
begin : i07
if (!TRUE)
begin : i1
reg r20a = 1;
end
else
begin : i1
reg r20b = 1;
end
end
else
begin : i07
reg r20c = 1;
end
if (TRUE)
begin : i08
case (TRUE)
0: begin : c1
reg r21a = 1;
end
1: begin : c1
reg r21b = 1;
end
endcase
end
else
begin : i08
case (TRUE)
0: begin : c1
reg r21c = 1;
end
1: begin : c1
reg r21d = 1;
end
endcase
end
if (!TRUE)
begin : i09
case (TRUE)
0: begin : c1
reg r22a = 1;
end
1: begin : c1
reg r22b = 1;
end
endcase
end
else if (TRUE)
begin : i09
case (TRUE)
0: begin : c1
reg r22c = 1;
end
1: begin : c1
reg r22d = 1;
end
endcase
end
else
begin : i09
case (TRUE)
0: begin : c1
reg r22e = 1;
end
1: begin : c1
reg r22f = 1;
end
endcase
end
if (!TRUE)
begin : i10
case (TRUE)
0: begin : c1
reg r23a = 1;
end
1: begin : c1
reg r23b = 1;
end
endcase
end
else if (!TRUE)
begin : i10
case (TRUE)
0: begin : c1
reg r23c = 1;
end
1: begin : c1
reg r23d = 1;
end
endcase
end
else
begin : i10
case (TRUE)
0: begin : c1
reg r23e = 1;
end
1: begin : c1
reg r23f = 1;
end
endcase
end
initial begin
$list_regs;
end
endmodule
|
module main;
reg [4:0] src;
wire dst;
test dut(.i(src[3:0]), .o(dst));
initial begin
for (src = 0 ; src < 16 ; src = src+1) begin
\t #1 if (dst !== & src[3:0]) begin
\t $display("FAILED: src=%b, dst=%b", src, dst);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
`timescale 1ns/100ps
module top;
reg pass;
reg in;
wire out_bit;
wire [3:0] out_vec, out_arr;
wire real r_bit, r_vec;
wire real r_arr[1:0];
initial begin
pass = 1\'b1;
in <= 1\'b0;
#1 in = 1\'b1;
#0.5 in = 1\'b0;
#0.5 in = 1\'b1;
#0.5 in = 1\'b0;
#0.5 in = 1\'b1;
#0.5 in = 1\'b0;
#0.5 in = 1\'b1;
#1 if (pass) $display("PASSED");
end
real_to_xx u1(out_bit, in);
always @(out_bit) if (out_bit !== ($stime % 2)) begin
$display("Failed real_to_xx, got %b, expected %1b", out_bit, $stime%2);
pass = 1\'b0;
end
real_to_xx u2(out_vec, in);
always @(out_vec) if (out_vec !== $stime) begin
$display("Failed real_to_xx(vec), got %b, expected %2b", out_vec, $stime);
pass = 1\'b0;
end
real_to_xx u3[1:0](out_arr, in);
always @(out_arr) #0.1 if ((out_arr[1:0] !== ($stime % 4)) &&
(out_arr[3:2] !== ($stime % 4))) begin
$display("Failed real_to_xx[1:0], got %b, expected %2b%2b", out_arr,
$stime%4, $stime%4);
pass = 1\'b0;
end
bit_to_real u4(r_bit, in);
always @(r_bit) if (r_bit != ($stime % 2)) begin
$display("Failed bit_to_real, got %f, expected %1b", r_bit, $stime%2);
pass = 1\'b0;
end
vec_to_real u5(r_vec, in);
always @(r_vec) if (r_vec != $stime) begin
$display("Failed vec_to_real, got %f, expected %1b", r_vec, $stime);
pass = 1\'b0;
end
endmodule
// Check a real value going to a various things.
module real_to_xx (output wire real out, input wire in);
real rval;
assign out = rval;
always @(posedge in) rval = rval + 1;
endmodule
module bit_to_real (output wire out, input wire in);
reg rval = 0;
assign out = rval;
always @(posedge in) rval = rval + 1;
endmodule
module vec_to_real (output wire [3:0] out, input wire in);
reg [3:0] rval = 0;
assign out = rval;
always @(posedge in) rval = rval + 1;
endmodule
|
module dut(input EN, input I, inout O);
assign O = EN ? I : 1\'bz;
specify
(I => O) = (2);
(EN *> O) = (4);
endspecify
endmodule
module test();
reg EN;
reg I;
tri O;
pulldown(O);
dut dut(EN, I, O);
reg failed = 0;
initial begin
$monitor($time,,EN,,I,,O);
EN = 0;
#4;
#0 if (O !== 0) failed = 1;
#1 I = 1;
#1 EN = 1;
#3;
#0 if (O !== 0) failed = 1;
#1;
#0 if (O !== 1) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that it is not possible to assign a queue with an enum element type to
// a queue with a packed type. Even if the enum base type is the same as the
// packed type.
module test;
enum logic [31:0] {
A
} q1[$];
logic [31:0] q2[$];
initial begin
q1 = q2;
$dispaly("FAILED");
end
endmodule
|
module top;
integer res;
initial begin
$hello;
$check_sys_task;
res = $check_sys_func;
$hello;
end
endmodule
|
// Check that declaring a variable multiple times for a signal that was
// previously declared as a non-ANSI task output port is an error.
module test;
task t;
output x;
reg x;
reg x;
$display("FAILED");
endtask
reg y;
initial t(y);
endmodule
|
// pr1958001
module s_cmpGe( in00, in01, out00 );
parameter bw_in00 = 32;
parameter bw_in01 = 32;
input signed [bw_in00-1:0] in00;
input signed [bw_in01-1:0] in01;
output out00;
assign out00 = ( in00 >= in01 );
endmodule
module x;
reg signed [31:0] a;
reg signed b;
wire c;
s_cmpGe #(32, 1) inst(a, b, c);
initial
begin
b = 0;
a = -1;
#1;
$display("%d >= %d = %d", a, b, c);
if (c !== 0) begin
\t $display("FAILED");
\t $finish;
\tend
$display("PASSED");
end
endmodule
|
module main;
reg [31:0] a, b, c;
initial begin
a = 1;
b = 1;
b[2] = 1\'bx;
c = a << b;
//$display( "a: %b, b: %b, c: %b", a, b, c );
if (c != 32\'bx) $display("FAILED");
else $display("PASSED");
end
endmodule
|
// test_mis.v - Testbench for mis.bvrl
// 01-22-01 E. Brombaugh
/*
* Copyright (c) 2001 Eric Brombaugh <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* The mis\'\' module was generated by the synopsis module compiler
* and is typical of the modules it generates. The testbench was hand
* coded. This file was merged into a single file using the Verilog
* preprocessor.
*/
`timescale 1ns / 10 ps
module mis( y, a, b );
input [3:0] a;
input [3:0] b;
output [12:0] y;
wire dpa_zero, dpa_one;
wire [5:0] const__1_24_;
wire [7:0] C0;
wire [6:0] const__2_33_;
wire [7:0] C1;
wire [12:0] y_1_;
assign dpa_zero= 1024\'h0;
assign dpa_one= 1024\'h1;
assign const__1_24_=- 1024\'h18;
assign const__2_33_=- 1024\'h21;
/* mis.mcl:4 module mis (y, a, b); */
/* mis.mcl:5 input signed [3:0] a, b; */
/* mis.mcl:10 C0 = -24; */
assign C0= ((const__1_24_[4:0]-(const__1_24_[5]<<5)));
/* mis.mcl:11 C1 = -33; */
assign C1= ((const__2_33_[5:0]-(const__2_33_[6]<<6)));
/* mis.mcl:13 y = C0*a + C1*b; */
assign y_1_= ((C0[6:0]-(C0[7]<<7))*(a[2:0]-(a[3]<<3))+
(C1[6:0]-(C1[7]<<7))*(b[2:0]-(b[3]<<3)));
/* mis.mcl:6 output signed [12:0] y; */
assign y = y_1_[12:0];
/* mis.mcl:4 module mis (y, a, b); */
/* mis.mcl:13 y = C0*a + C1*b; */
/*User Defined Aliases */
endmodule
module test_mis;
reg [10:0] count;
reg clk;
reg [3:0] a, b;
wire [12:0] y;
mis u1(y, a, b);
initial
begin
count = 0;
clk = 0;
a = 0;
b = 0;
end
always
#10 clk = ~clk;
always @(posedge clk)
begin
a = count[3:0];
b = count[7:4];
#10
$display("%h %h %h", a, b, y);
count = count + 1;
if(count == 0)
$finish(0);
end
endmodule
|
// Check that implicit cast works for expressions in assignment patterns. The
// result should be the same as assigning the expression to a variable with the
// same type as the base type of the assignment pattern target.
module test;
int dv[];
real dr[];
int tmpv;
real tmpr;
bit failed = 1\'b0;
`define check_v(expr) \\
dv = \'{expr}; \\
tmpv = expr; \\
if (dv[0] !== tmpv) begin \\
$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", dv[0], tmpv); \\
failed = 1\'b1; \\
end
`define check_r(expr) \\
dr = \'{expr}; \\
tmpr = expr; \\
if (dr[0] != tmpr) begin \\
$display("FAILED: `%s`, got %0d, expected %0d", `"expr`", dr[0], tmpr); \\
failed = 1\'b1; \\
end
real r;
int i;
initial begin
r = 4.56;
i = -11;
// Implicit cast from real to vector
`check_v(1.234e16)
`check_v(r)
// Implicit cast from vector to real
`check_r(32\'hfffffff0)
`check_r(i)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
`begin_keywords "1364-2005"
module top;
reg pass = 1\'b1;
reg [1:0] var = 2\'b0;
real rvar = 0.0;
integer delay = 3;
initial begin
// These should both happen at time 2.
var <= #2 2\'b01;
rvar <= #2 1.0;
#3 if (var !== 2\'b01) begin
$display("FAILED: constant delay (bits)");
pass = 1\'b0;
end
if (rvar != 1.0) begin
$display("FAILED: constant delay (real)");
pass = 1\'b0;
end
// These should both happen at time 6.
var <= #(delay) 2\'b10;
rvar <= #(delay) 2.0;
#4 if (var !== 2\'b10) begin
$display("FAILED: calculated delay (bits)");
pass = 1\'b0;
end
if (rvar != 2.0) begin
$display("FAILED: calculated delay (real)");
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
`end_keywords
|
/*
* Copyright (c) 1998-1999 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test;
wire [3:0] a = 7, b = 13 ;
wire [3:0] sum ;
wire carry ;
assign {carry,sum} = a + b ;
initial begin
#1
if (carry !== 1\'b1) begin
\t $display("FAILED: carry === %b", carry);
\t $finish;
end
if (sum !== 4\'b0100) begin
\t $display("FAILED: sum === %b", sum);
\t $finish;
end
$display("Correct results {carry,sum} === %b,%b", carry, sum);
$display("PASSED");
end
endmodule /* test */
|
// Copyright (c) 2016 CERN
// @author Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Power and division remainder operators test
module vhdl_pow_rem_test;
integer a, b, pow_res, rem_res;
vhdl_pow_rem dut(a, b, pow_res, rem_res);
initial begin
a = 5;
b = 2;
if(pow_res != 25 || rem_res != 1) begin
$display("FAILED 1");
$finish();
end
a = -5;
b = 3;
if(rem_res != -2 || pow_res != -125) begin
$display("FAILED 2");
$finish();
end
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate that arrays spread across the input range of an arrayed
// module instantiation are supported.
//
module my_and (out,a,b);
input [3:0] a,b;
output [3:0] out;
and u0 (out[0],a[0],b[0]);
and u1 (out[1],a[1],b[1]);
and u2 (out[2],a[2],b[2]);
and u3 (out[3],a[3],b[3]);
endmodule
module main;
reg globvar;
wire [15:0] out;
reg [15:0] a,b, rslt;
reg error;
// The test gate goes HERE!
my_and foo [0:3] (out,a,b);
always @(a or b)
rslt = a & b;
initial
begin // {
error = 0;
# 1;
for(a = 16\'h1; a != 16\'hffff; a = (a << 1) | 1)
begin // {
for(b = 16\'hffff; b !== 16\'h0; b = b >> 1)
begin // {
#1 ;
if(out !== rslt)
begin // {
$display("FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h",
a,b,rslt,out);
error = 1;
end // }
end // }
end // }
if( error == 0)
$display("PASSED");
end // }
endmodule // main
|
module main;
reg a, b;
trior net;
assign net = a;
assign net = b;
initial begin
a = \'b0;
b = \'b0;
#1 if (net !== 1\'b0) begin
\t $display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
\t $finish;
end
a = \'b0;
b = \'b1;
#1 if (net !== 1\'b1) begin
\t $display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
\t $finish;
end
a = \'b0;
b = \'bx;
#1 if (net !== 1\'bx) begin
\t $display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
\t $finish;
end
a = \'b0;
b = \'bz;
#1 if (net !== 1\'b0) begin
\t $display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
\t $finish;
end
a = \'b1;
b = \'b1;
#1 if (net !== 1\'b1) begin
\t $display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
\t $finish;
end
a = \'b1;
b = \'bx;
#1 if (net !== 1\'b1) begin
\t $display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
\t $finish;
end
a = \'b1;
b = \'bz;
#1 if (net !== 1\'b1) begin
\t $display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
\t $finish;
end
a = \'bx;
b = \'bx;
#1 if (net !== 1\'bx) begin
\t $display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
\t $finish;
end
a = \'bx;
b = \'bz;
#1 if (net !== 1\'bx) begin
\t $display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
\t $finish;
end
a = \'bz;
b = \'bz;
#1 if (net !== 1\'bz) begin
\t $display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module top;
reg [15:0] array [1:0];
initial begin
array[1] = 15'd48;
// This should display 0003
$displayh(array[1]>>4);
end
endmodule
|
module top();
reg CLK;
reg RST;
reg [3:1] D;
reg EN;
reg [3:1] Q;
always @(posedge CLK or posedge RST) begin
if (RST) begin
Q[1] <= 1\'b0;
Q[2] <= 1\'b1;
Q[3] <= 1\'b0;
end
else if (EN) begin
Q[1] <= D[1];
Q[2] <= ~D[2];
Q[3] <= D[3];
end
end
reg failed;
(* ivl_synthesis_off *)
initial begin
failed = 0;
$monitor("%b %b %b %b", CLK, EN, D, Q);
CLK = 0;
RST = 1;
EN = 0;
D = 3\'b111;
#1 CLK = 1;
#1 CLK = 0;
if (Q !== 3\'b010) failed = 1;
EN = 1;
#1 CLK = 1;
#1 CLK = 0;
if (Q !== 3\'b010) failed = 1;
RST = 0;
EN = 0;
#1 CLK = 1;
#1 CLK = 0;
if (Q !== 3\'b010) failed = 1;
EN = 1;
#1 CLK = 1;
#1 CLK = 0;
if (Q !== 3\'b101) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2000 Steven Wilson ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test looks for == operation in a continuous assignment.
*/
module test;
integer a;
integer b;
wire result;
integer error;
assign result = (a == b);
initial
begin
a = 0;
b = 0;
error = 0;
#5 ;
if( result !== 1\'b1)
error =1;
a = 1;
#5;
if( result !== 1\'b0)
error =1;
b = 1;
#5 ;
if( result !== 1\'b1)
error =1;
a = 1002;
b = 1001;
#5 ;
if( result !== 1\'b0)
error =1;
a = 1001;
#5 ;
if( result !== 1\'b1)
error =1;
if(error === 0)
\t $display("PASSED");
else
\t $display("FAILED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always # (mintypmax_dly) reg_lvalue = constant ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
reg err ;
initial
\tbegin
err = 0;
# 1;
if(value1 !== 4\'bxxxx)
begin
$display("FAILED - 3.1.4E - initial value not xxxx;\
");
err = 1;
end
#15 ;
if(value1 != 4\'h5)
begin
$display("FAILED - 3.1.4E - always # mintypmax_dly reg_lvalue = constant\
");
err = 1;
end
if (err == 0)
$display("PASSED\
");
\t $finish;
end
always # (3:10:15) value1 = 4\'h5;
endmodule
|
module subN
#(parameter WID = 4)
(input wire [WID-1:0] A,
input wire [WID-1:0] B,
output reg [WID:0] Q
/* */);
always @(A or B) Q = A - B;
endmodule // add
|
module stimulus (output reg A);
initial begin
// input is x
#0 A = 1\'bx;
// input is z
#10 A = 1\'bz;
// one input is a zero
#10 A = 1\'b0;
// one input is a one
#10 A = 1\'b1;
end
endmodule
module scoreboard (input Y, A);
function truth_table (input a);
reg gate_operand;
reg gate_output;
begin
gate_operand = a;
case (gate_operand)
// input is x
1\'bx: gate_output = 1\'bx;
// inputs is z
1\'bz: gate_output = 1\'bx;
// normal operation on bit
1\'b0: gate_output = 1;
1\'b1: gate_output = 0;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A) begin
Y_t = truth_table (A);
#1;
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for input %b in NOT operation", A);
$finish;
end
end
endmodule
module test;
stimulus stim (A);
not_gate duv (.a_i(A), .c_o(Y) );
scoreboard mon (Y, A);
initial begin
#200;
$display("PASSED");
$finish;
end
endmodule
|
class example;
int id_;
function new(int id);
id_ = id;
endfunction
task display(int run);
$display(" This is run %0d of class %0d", run, id_);
endtask
function int get_id();
get_id = id_;
endfunction
task work();
/* These method calls work correctly. */
$display("Starting work with class %0d", this.get_id());
this.display(1);
/* Elaboration of these method calls fail. It looks like they are
* being elaborated as a normal user functions/tasks not as a method
* calls. */
display(2);
$display("Done with work for class %0d", get_id());
endtask
endclass
module top;
example test;
initial begin
test = new(1);
$display("Created a class with id: %0d", test.get_id());
test.work();
$display("PASSED");
end
endmodule
|
module test();
wire signed [7:0] value1;
wire [7:0] value2;
assign value1[3:0] = 4\'d2;
assign value2 = abs(value1);
initial begin
#2 $display("%b %b", value1, value2);
if (value2 === 8\'bx)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module main;
reg [3:0] x, y;
wire [3:0] z;
ivtest dut (.\\x[3] (x[3]), .\\x[2] (x[2]), .\\x[1] (x[1]), .\\x[0] (x[0]),
\t .\\y[3] (y[3]), .\\y[2] (y[2]), .\\y[1] (y[1]), .\\y[0] (y[0]),
\t .\\z[3] (z[3]), .\\z[2] (z[2]), .\\z[1] (z[1]), .\\z[0] (z[0]));
integer idx;
initial begin
for (idx = 0 ; idx[8]==0 ; idx = idx+1) begin
\t x = idx[3:0];
\t y = idx[7:4];
\t #1 /* let devices settle. */ ;
\t if (z !== (x ^ y)) begin
\t $display("FAILED -- x=%b, y=%b, x^y=%b", x, y, z);
\t $finish;
\t end
end
$display("PASSED");
end // initial begin
endmodule // main
|
// Check that it is possible to use SV data types for non-ANSI style task ports
module test;
typedef logic [7:0] T1;
typedef struct packed { int i; } T2;
typedef enum { A } T3;
task t;
input reg a;
input logic b;
input bit c;
input logic [3:0] d;
input bit [3:0][3:0] e;
input byte f;
input int g;
input T1 h;
input T2 i;
input T3 j;
input real k;
input shortreal l;
input string m;
input int n[];
input int o[$];
input x;
input [3:0] y;
input signed z;
$display("PASSED");
endtask
initial begin
t(\'0, \'0, \'0, \'0, \'0, \'0, \'0, \'0, \'0, A, 0.0, 0.0, "", \'{0}, \'{0}, \'0, \'0, \'0);
end
endmodule
|
module top;
reg pass;
reg [3:0] val;
reg [3:0] pv_val;
real rval;
initial begin
pass = 1\'b1;
// A release of an unforced variable should not change the variable.
val = 4\'b0110;
release val;
if (val !== 4\'b0110) begin
$display("Failed release of unforced sig, expected 4\'b0110, got %b",
val);
pass = 1\'b0;
end
// Verify that a force/release leaves the variable set correctly.
force val = 4\'b1001;
release val;
if (val !== 4\'b1001) begin
$display("Failed release of forced sig, expected 4\'b1001, got %b",
val);
pass = 1\'b0;
end
// A release of a currently unforced varaible should not change it.
val = 4\'b0110;
release val;
if (val !== 4\'b0110) begin
$display("Failed release of unforced sig(2), expected 4\'b0110, got %b",
val);
pass = 1\'b0;
end
// A release of an unforced variable should not change the variable.
pv_val = 4\'b1001;
release pv_val[1];
if (pv_val !== 4\'b1001) begin
$display("Failed pv release of unforced sig, expected 4\'b1001, got %b",
pv_val);
pass = 1\'b0;
end
// Verify that a force/release leaves the variable set correctly.
force pv_val[1] = 1\'b1;
release pv_val[2:0];
if (pv_val !== 4\'b1011) begin
$display("Failed pv release of forced sig, expected 4\'b1011, got %b",
pv_val);
pass = 1\'b0;
end
// A release of a currently unforced varaible should not change it.
pv_val = 4\'b1001;
release pv_val[1];
if (pv_val !== 4\'b1001) begin
$display("Failed pv release of unforced sig(2), expected 4\'b1001, got %b",
pv_val);
pass = 1\'b0;
end
// A release of an unforced variable should not change the variable.
rval = 1.0;
release rval;
if (rval != 1.0) begin
$display("Failed release of unforced sig, expected 1.0, got %.1f",
rval);
pass = 1\'b0;
end
// Verify that a force/release leaves the variable set correctly.
force rval = 2.0;
release rval;
if (rval != 2.0) begin
$display("Failed release of forced sig, expected 2.0, got %.1f",
rval);
pass = 1\'b0;
end
// A release of a currently unforced varaible should not change it.
rval = 1.0;
release rval;
if (rval != 1.0) begin
$display("Failed release of unforced sig(2), expected 1.0, got %.1f",
rval);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
wire [31:0] A;
wire [24:0] B;
reg [15:0] C;
assign A = B;
assign B = C;
initial begin
C = 0;
#1 if (A !== 32\'h0) begin
\t $display("FAILED -- A === %h", A);
\t $finish;
end
C = -1;
#1 if (A !== 32\'h00_00_ff_ff) begin
\t $display("FAILED -- A == %h instead of 0000ffff", A);
\t $finish;
end
$display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Rewrite of stmt002_bassign.v from vbs test suite.
//
module main;
reg [0:7] var1, var2;\t// Note the obtuse bit ordering.
reg [3:0] var3;\t\t// A more sane ordering on a nibble boundary...
reg var4;\t\t// Single bit.
reg [2:9] var5;\t\t// Use a non-alligned, reversed bit - still 8 bits
reg error;
initial
begin
// First verify that all the defined variables are x\'s.
error = 0;
if(var1 !== 8\'hxx)
begin
$display("FAILED - sdw_stmt002 - var1 not 8\'hxx");
error = 1;
end
if(var2 !== 8\'hxx)
begin
$display("FAILED - sdw_stmt002 -var2 not 8\'hxx");
error = 1;
end
if(var3 !== 4\'bx_xxx)
begin
$display("FAILED - sdw_stmt002 -var3 not 4\'hx");
error = 1;
end
if(var4 !== 1\'bx)
begin
$display("FAILED - sdw_stmt002 -var4 not 1\'bx");
error = 1;
end
if(var5 !== 8\'hxx)
begin
$display("FAILED - sdw_stmt002 -var5 not 8\'hxx");
error = 1;
end
var1 = 8\'b1001_0010;\t// Do some binary bits
var2 = 255;\t\t// Fill it with decimal version of ff
var3 = 4\'hf;\t\t// hex
var4 = 0;
var5 = 8\'h99;\t\t// Still 8 bits
if(var1 != 8\'h92)
begin
$display("FAILED - sdw_stmt002 - var1 not 8\'h96");
error = 1;
end
if(var2 != 8\'hff)
begin
$display("FAILED - sdw_stmt002 -var2 not 8\'hff");
error = 1;
end
if(var3 != 4\'b1111)
begin
$display("FAILED - sdw_stmt002 -var3 not 4\'hf");
error = 1;
end
if(var4 != 1\'b0)
begin
$display("FAILED - sdw_stmt002 -var4 not 1\'b0");
error = 1;
end
if(var5 != 8\'h99)
begin
$display("FAILED - sdw_stmt002 -var5 not 8\'h99");
error = 1;
end
// Next - assign sub-portion of vector
var1 [3:6] = var3;
if(var1 != 8\'h9e)
begin
$display("FAILED - sdw_stmt002 - subfield assign failed");
error = 1;
end
var3 = 4\'o11;\t// Lets try octal now
var4 = 1\'b1;\t// And set that bit to 1, it WAS 0
var5 = 8\'h66;\t// Invert it
if(var3 != 4\'b1001)
begin
$display("FAILED - sdw_stmt002 -var3 octal assign");
error = 1;
end
if(var4 != 1\'b1)
begin
$display("FAILED - sdw_stmt002 -var4 not 1\'b1");
error = 1;
end
if(var5 != 8\'h66)
begin
$display("FAILED - sdw_stmt002 -var5 not 8\'h66");
error = 1;
end
// 9e, 9
var3 = var1[4:7];\t\t// Should be an 4\'he
var1[0:3] = var3[3:2];\t// Now should give 8\'hce
if(var1 != 8\'h3e)
begin
$display("FAILED - sdw_stmt002 - subfield assign(1) w/ 0 extension");
error = 1;
end
if(var3 != 4\'b1110)
begin
$display("FAILED - sdw_stmt002 -subfield assign(2)");
error = 1;
end
var3 = var5;\t\t// 4 bit from 8 bit(4\'h6)
var5[5] = var4;\t\t// Set var5 to 8\'h76
if(var3 != 4\'h6)
begin
$display("FAILED - sdw_stmt002 - 4bit from 8 bit assign");
error = 1;
end
if(var5 != 8\'h76)
begin
$display("FAILED - sdw_stmt002 - single sub-bit assign ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
// Check that the signedness of class properties are handled correctly when
// accessing the property in a class method and passing it to a system function.
module test;
class C;
shortint s = -1;
bit [15:0] u = -1;
task test;
string str;
str = $sformatf("%0d %0d", s, u);
if (str == "-1 65535") begin
$display("PASSED");
end else begin
$display("FAILED s=%s", s);
end
endtask
endclass
C c;
initial begin
c = new;
c.test();
end
endmodule
|
/*
* Copyright (c) 2000 Chris Lattner
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This isn\'t computationally complicated, but can trip up a vvm
* code generation error.
*/
module test;
reg [15:0] is[1:0];
reg [4:0] i;
initial begin
i = 0;
is[0] = i; // Notice the different widths.
if (is[0] !== 16\'d0) begin
\t $display("FAILED -- is[0] --> %b", is[0]);
\t $finish;
end
$display("PASSED");
end
endmodule
|
//
// The output from the display should be:
// i is \'1\'; j is \'111\'; k is \'0\'
//
module test;
reg one = 1;
reg i, k, kr;
reg [2:0] j, jr;
initial
begin
\ti = ($signed(3\'b111) === 3\'b111);
\tj = $signed(3\'b110) >>> 1;
\tjr = $signed(3\'b110) >>> one;
\tk = (($signed(3\'b110) >>> 1) === 3\'b111);
\tkr = (($signed(3\'b110) >>> one) === 3\'b111);
\t$display("i is \'%b\'; j is \'%b\'; k is \'%b\'", i, j, k);
\t$display("runtime ; j is \'%b\'; k is \'%b\'", jr, kr);
end
endmodule
|
module top;
reg pass = 1\'b1;
integer count;
reg clk = 0, in = 0;
reg result;
always #10 clk = ~clk;
always #20 in = ~in;
initial begin
count = 3;
result = repeat(count) @(posedge clk) in;
if ($simtime != 30 && result != 1\'b0) begin
$display("Failed blocking repeat(3) at %0t, expected 1\'b0, got %b",
$simtime, result);
pass = 1\'b0;
end
#15;
count = 0;
result = repeat(count) @(posedge clk) in;
if ($simtime != 45 && result != 1\'b1) begin
$display("Failed blocking repeat(0) at %0t, expected 1\'b1, got %b",
$simtime, result);
pass = 1\'b0;
end
#20;
count = -1;
result = repeat(count) @(posedge clk) in;
if ($simtime != 55 && result != 1\'b0) begin
$display("Failed blocking repeat(0) at %0t, expected 1\'b0, got %b",
$simtime, result);
pass = 1\'b0;
end
if (pass) $display("PASSED");
$finish;
end
endmodule
|
/*
* This is the most basic test of string variables.
*/
module main;
string foo = "PASSED";
initial begin
$display(foo);
$finish;
end
endmodule // main
|
module top;
real rval;
reg [7:0] rgval;
initial begin
rgval = 8\'ha5;
rval = 1234567890;
$display("Checking h and H: %h, %H", rgval, rgval);
$display("Checking x and X: %x, %X", rgval, rgval);
$display("Checking g and G: %g, %G", rval, rval);
$display("Checking e and E: %e, %E", rval, rval);
end
endmodule
|
module top;
reg [31:0] value = 1000000;
integer val = 100;
initial begin
$display("1. The value is %3d", value*100);
$display("2. The value is %3.0f", value*100.0);
$display("3. The value is %3.0f", 100);
$display("4. The value is %3.0f", val);
$display("5. The value is %3.0f", value*100000000); // This fails!
$finish(0);
end
endmodule
|
module top;
reg pass;
wire [1:0] out;
reg [1:0] drive_val;
reg [1:0] oe_n;
reg [2:0] pull_vec;
reg [1:0] base;
bufif0 bufs[1:0] (out, drive_val, oe_n);
assign (pull0, pull1) out = pull_vec[base+:2];
initial begin
pass = 1\'b1;
base = 2\'b00;
pull_vec = 3\'b000;
oe_n = 2\'b00;
// Drive is selected.
drive_val = 2\'b00;
#1;
if (out !== drive_val) begin
$display("Failed to drive 2\'b00, got %b", out);
pass = 1\'b0;
end
drive_val = 1\'b1;
#1;
if (out !== drive_val) begin
$display("Failed to drive 2\'b11, got %b", out);
pass = 1\'b0;
end
// The pull is selected (low).
oe_n = 2\'b11;
drive_val = 2\'b00;
#1;
if (out !== pull_vec[1:0]) begin
$display("Failed pull #1, expected 2\'b00, got %b", out);
pass = 1\'b0;
end
drive_val = 1\'b1;
#1;
if (out !== pull_vec[1:0]) begin
$display("Failed pull #2, expected 2\'b00, got %b", out);
pass = 1\'b0;
end
// The pull is selected (high).
pull_vec = 3\'b111;
drive_val = 2\'b00;
#1;
if (out !== pull_vec[1:0]) begin
$display("Failed pull #3, expected 2\'b11, got %b", out);
pass = 1\'b0;
end
drive_val = 2\'b11;
if (out !== pull_vec[1:0]) begin
$display("Failed pull #4, expected 2\'b11, got %b", out);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`begin_keywords "1364-2005"
module test();
reg [15:0] a;
reg [7:0] b;
reg [31:0] expect;
wire [31:0] actual;
reg [127:0] long_x;
real real_x;
assign actual = a ** b;
initial begin
for (a = 0; a < 65535; a = a + 1) begin:outer_loop
long_x = 1;
for (b = 0; b < 127; b = b + 1) begin:inner_loop
real_x = $itor(a) ** $itor(b);
if (real_x >= 2.0**128.0) disable outer_loop;
expect = long_x;
#0; // wait for net propagation
if (actual !== expect) begin
$display("FAILED : %0d ** %0d = %0d not %0d", a, b, expect, actual);
$finish;
end
long_x = long_x * a;
end
end
$display("PASSED");
end
endmodule
`end_keywords
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Initial readmemb function - length of data = array size.
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
$readmemb("ivltests/readmemb1.dat",array);
for(count = 0; count <= 7; count = count + 1)
begin
if(array[count[2:0]] !== count)
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count],count);
end
end
if(error == 0)
$display("PASSED\
");
$finish ;
end
endmodule
|
// Copyright (c) 2000 Stephen Williams ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* This module implements what essentially amounts to an array of DFF
* devices with output enable. This test checks the operation of the
* bufif0 and bufif1 devices.
*/
module grayGap (ad, clk, read, write);
output [31:0] ad;
input\t clk, read, write;
reg [15:0] regff;
bufif0 ad_drv [31:0] (ad, {16\'b0, regff}, read);
always @(posedge clk)
if (write) regff = ad[15:0];
endmodule
module main;
wire [31:0] ad;
reg\t clk, read, write;
reg [31:0] ad_val;
reg ad_en;
bufif1 ad_drv[31:0] (ad, ad_val, ad_en);
grayGap test (ad, clk, read, write);
always #10 clk = ~clk;
initial begin
clk = 1;
read = 1;
write = 0;
$monitor($time, "ad=%b", ad);
// Set up to write a value into the grayGap register.
@(negedge clk)
\tad_val = 32\'haaaa_aaaa;
read = 1;
write = 1;
ad_en = 1;
// The posedge has passed, now set up to read that value
// out. Turn all the drivers off for a moment, to see that the
// line becomes tri-state...
@(negedge clk)
\tad_en = 0;
write = 0;
// Now read the value.
#1 read = 0;
#1 $display("Wrote %h, got %h", ad_val, ad);
if (ad !== 32\'b0000_0000_0000_0000_1010_1010_1010_1010) begin
\t $display("FAILED -- ad is %b", ad);
\t $finish;
end
#2 read = 1;
$display("PASSED");
$finish;
end
endmodule // main
|
module test;
reg [8:0] t1;
initial
main;
function integer log2;
input [31:0] arg;
for (log2=0; arg > 0; log2=log2+1)
\targ = arg >> 1;
endfunction // log2
task main;
integer temp;
begin
\t t1 = 9\'h0a5;
\t temp = log2($unsigned(t1 - t1 - 1\'b1));
\t $display("%d", temp);
\t temp = log2($signed(t1 - t1 - 1\'b1));
\t $display("%d", temp);
\t temp = log2({t1 - t1 - 1\'b1});
\t $display("%d", temp);
\t temp = $bits(t1 - t1 - 1\'b1);
\t $display("%d", temp);
end
endtask
endmodule
|
/* Extracted from PR#820. */
module main();
wire clk;
wire reset;
reg [3:0] waddr, raddr;
reg [7:0] wdata;
wire [7:0] rdata;
clk_reset_gen cg(clk, reset);
ram_rw #(8,4) r(clk, waddr, wdata, 1\'b1, raddr, rdata);
initial begin
waddr = 4\'d0;
raddr = 4\'d14;
wdata = 0;
#3001;
$finish(0);
end
always @(posedge clk) begin
waddr <= #1 waddr + 1;
raddr <= #1 raddr + 1;
wdata <= #1 wdata + 3;
end
always @(posedge clk)
$display($time,,"waddr wdata %d %d raddr rdata %d %d",waddr,wdata,raddr,rdata);
endmodule
module ram_rw(clk,waddr,wdata,we,raddr,rdata);
parameter WDATA = 8;
parameter WADDR = 11;
input clk;
input [(WADDR-1):0] waddr;
input [(WDATA-1):0] wdata;
input we;
input [(WADDR-1):0] raddr;
output [(WDATA-1):0] rdata;
//local
reg [(WDATA-1):0] mem[0:((1<<WADDR)-1)];
reg [(WADDR-1):0] qraddr;
always @(posedge clk) begin
qraddr <= #1 raddr;
if (we)
mem[waddr] <= #1 wdata;
end
assign rdata = mem[qraddr];
endmodule
module clk_reset_gen(clk, reset);
output clk;
output reset;
reg clk;
reg reset;
initial begin
reset = 1;
#5;
clk = 0;
#5;
clk = 1;
#5;
reset = 0;
clk = 0;
forever #5 clk = ~clk;
end
endmodule
|
module top;
reg pass = 1\'b1;
reg [14:-1] big = 16\'h0123;
reg signed [15:0] a;
wire [3:0] w_big = big[a+:4];
initial begin
#1; // Wait for the assigns above to happen.
/* If this fails it is likely because the index width is less
* than an int width. */
a = -2;
#1;
if (w_big !== 4\'b011x) begin
$display("Failed: .part/v check, expected 4\'b011x, got %b.", w_big);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module top;
wire out;
reg in;
assign out = in;
always @* $display(,out,,in);
initial begin
in = 1\'b0;
#1 in = 1\'b1;
#1 in = 1\'b0;
#1;
$display("PASSED");
end
endmodule
|
module top;
parameter real rpar1 = 1.0;
parameter real rpar2 = 2.0;
parameter real rparb = {rpar1, rpar2};
parameter real rpar = {2.0, 1.0};
endmodule
|
// Ensure the compiler doesn\'t perform some invalid optimisations.
module test();
reg [3:0] unknown;
reg [3:0] result;
reg failed;
initial begin
failed = 0;
unknown = 4\'bx101;
result = unknown + 0;
$display("%b", result);
if (result !== 4\'bxxxx) failed = 1;
result = (unknown >> 1) + 0;
$display("%b", result);
if (result !== 4\'bxxxx) failed = 1;
result = unknown - 0;
$display("%b", result);
if (result !== 4\'bxxxx) failed = 1;
result = unknown * 0;
$display("%b", result);
if (result !== 4\'bxxxx) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module main;
wire [1:0] a2, b2;
wire [2:0] a3, b3;
target #(.WA(2), .WB(2)) u1 (a2, b2);
target #(.WA(3), .WB(3)) u2 (a3, b3);
initial begin
$display("u1.WA=%d, $bits(u1.A)=%d", u1.WA, $bits(u1.A));
$display("u1.WB=%d, $bits(u1.A)=%d", u1.WB, $bits(u1.B));
if ($bits(u1.A) != 2) begin
\t $display("FAILED -- $bits(u1.A) = %d", $bits(u1.A));
\t $finish;
end
if ($bits(u2.A) != 3) begin
\t $display("FAILED -- $bits(u2.A) = %d", $bits(u2.A));
\t $finish;
end
$display("PASSED");
end
endmodule // main
module target
#(parameter WA = 4, parameter WB = 4)
(input [WA-1:0] A, output [WB-1:0] B);
assign B = A;
endmodule // target
|
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