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// Regression test for GitHub issue 26
// This is invalid code and should result in a compile-time error
module tb;
wire [3:0] a, y;
test uut (.a(a), .y(y));
endmodule
module test(a, b, y);
input [3:0] a;
output [3:0] y;
assign y = a;
endmodule
|
// This tests the basic support for default arguments to task/function
// ports. The default port syntax gives SystemVerilog a limited form
// of variable argument lists.
program main;
class foo_t;
int int_val;
string text_val;
task init (int int_init, string text_init = "default text");
\t int_val = int_init;
\t text_val = text_init;
endtask
endclass : foo_t
foo_t obj1;
initial begin
obj1 = new;
obj1.init(5, "new text");
if (obj1.int_val != 5 || obj1.text_val != "new text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val);
\t $finish;
end
obj1 = new;
obj1.init(7);
if (obj1.int_val != 7 || obj1.text_val != "default text") begin
\t $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val);
\t $finish;
end
$display("PASSED");
end
endprogram // main
|
module main;
wire eq1, eq2, eq5;
wire ne1, ne2, ne5;
reg [7:0] x, y;
eqne dut(.eq1(eq1), .eq2(eq2), .eq5(eq5),
\t .ne1(ne1), .ne2(ne2), .ne5(ne5),
\t .x(x), .y(y));
initial begin
for (x = 0 ; x < \'h20 ; x = x+1)
\tfor (y = 0 ; y < \'h20 ; y = y+1) begin
\t #1 $display("x=%h, y=%h: ", x, y,
\t\t "eq1=%b, eq2=%b, eq5=%b, ", eq1, eq2, eq5,
\t\t "ne1=%b, ne2=%b, ne5=%b", ne1, ne2, ne5);
\t if (eq1 !== (x[0] == y[0])) begin
\t $display("FAILED");
\t $finish;
\t end
\t if (eq2 !== (x[1:0] == y[1:0])) begin
\t $display("FAILED");
\t $finish;
\t end
\t if (eq5 !== (x[4:0] == y[4:0])) begin
\t $display("FAILED");
\t $finish;
\t end
\t if (ne1 !== (x[0] != y[0])) begin
\t $display("FAILED");
\t $finish;
\t end
\t if (ne2 !== (x[1:0] != y[1:0])) begin
\t $display("FAILED");
\t $finish;
\t end
\t if (ne5 !== (x[4:0] != y[4:0])) begin
\t $display("FAILED");
\t $finish;
\t end
\tend
$display("PASSED");
end
endmodule // main
|
module test(output [7:0] dataout[1:0]);
assign dataout[0] = 8\'h55;
assign dataout[1] = 8\'haa;
initial begin
#0;
if (dataout[0] === 8\'h55 && dataout[1] === 8\'haa)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module test();
wire [7:0] value1;
wire [7:0] value2;
assign value1[3:0] = 4\'d2;
assign value2 = value1 | 8\'d1;
initial begin
#2 $display("%b %b", value1, value2);
if (value2 === 8\'bxxxx0011)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* SDW: This test is a first expression test inside a parameter declaration.
*/
module test;
parameter A0 = 2\'b10 | 2\'b01 ;
initial
begin
if(A0 !== 2\'b11)
$display("FAILED - A0 expression OR doesn\'t work.");
else
$display("PASSED");
end
endmodule
|
// Check that chained type definitions declared in different scopes work
// correctly.
package P1;
localparam A = 8;
typedef logic [A-1:0] T;
endpackage
package P2;
localparam A = 4;
typedef P1::T T;
endpackage
bit failed = 1\'b0;
`define check(expr, val) \\
if (expr !== val) begin \\
$display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \\
failed = 1\'b1; \\
end
module test;
localparam A = 2;
typedef P2::T T;
T x;
P1::T y;
P2::T z;
initial begin
x = 8\'hff;
y = 8\'hff;
z = 8\'hff;
`check(x, 8\'hff);
`check($bits(T), 8);
`check($bits(x), 8);
`check(y, 8\'hff);
`check($bits(y), 8);
`check($bits(P1::T), 8);
`check(z, 8\'hff);
`check($bits(z), 8);
`check($bits(P2::T), 8);
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
/*
* This is a post-wynthesis test for the blif01a.v test. Run this
* simulation in these steps:
*
* $ iverilog -tblif -o foo.blif blif01a.v
* $ abc
* abc 01> read_blif foo.blif
* abc 02> write_verilog foo.v
* abc 03> quit
* $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v
* $ vvp foo.vvp
*/
module main;
parameter WID = 4;
reg [WID-1:0] A, B;
wire [WID:0] Q;
addN usum(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]),
\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]),
\t .\\Q[4] (Q[4]), .\\Q[3] (Q[3]), .\\Q[2] (Q[2]), .\\Q[1] (Q[1]), .\\Q[0] (Q[0]));
int\t\t adx;
int\t\t bdx;
initial begin
for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
\t A <= adx[WID-1:0];
\t B <= bdx[WID-1:0];
\t #1 if (Q !== (adx+bdx)) begin
\t $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q);
\t $finish;
\t end
\t end
end
$display("PASSED");
end
endmodule // main
|
`begin_keywords "1364-2005"
module main;
wire y1, y2, y3;
reg a;
initial begin
$monitor($time , " y1 = %d, y2 = %d, y3 = %d, a = %d", y1, y2, y3, a);
#1 a = 1;
#1 a = 0;
end
sub s1(y1, y2, y3, a);
endmodule // main
module sub(y1, y2, y3, a);
output y1, y2, y3;
input a;
reg y1, y2, y3;
reg int;
always @(*) begin
y1 <= a;
y2 <= y1;
int <= a;
y3 <= int;
end
endmodule
`end_keywords
|
// Test default value for output port
// This should work, but isn\'t supported yet
module test();
integer a;
integer b;
integer c;
task k(input integer i = a, output integer j = b);
j = i;
endtask
integer result;
reg fail = 0;
initial begin
a = 1;
b = 2;
k(3,c);
$display(a,,b,,c);
if (a !== 1 || b !== 2 || c !== 3) fail = 1;
k(,c);
$display(a,,b,,c);
if (a !== 1 || b !== 2 || c !== 1) fail = 1;
k(4,);
$display(a,,b,,c);
if (a !== 1 || b !== 4 || c !== 1) fail = 1;
k();
$display(a,,b,,c);
if (a !== 1 || b !== 1 || c !== 1) fail = 1;
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test some subtleties of bitwise and and if condition expressions.
*/
module test;
reg [31:0] c;
initial begin
c = 13;
if (c & 4)
\tbegin
\t $display("PASSED");
\t $finish;
\tend
$display("FAILED");
end
endmodule
|
module top;
reg [1:0] q;
wire [4:0] icim[1:0];
integer j;
always @(q) begin
/*
* The following line had the muli problem, the other line has a
* different problem.
*/
icim[0] <= #1 0 + 8 * (0 >> q);
icim[1] <= #1 1 + 8 * (1 >> q);
end
initial begin
q = 2\'d1;
#2;
if (icim[0] !== 0) begin
\t $display("FAILED");
\t $finish;
end
if (icim[1] !== 1) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
end
endmodule
|
module top;
reg passed = 1\'b1;
reg [7:0] in;
lwr dut(in);
initial begin
#1 in = 8\'d1;
#1 in = 8\'d2;
#1 if (passed) $display("PASSED");
end
endmodule
module lwr(input [7:0] xin);
wire [7:0] x1 = {xin,{0{1\'b0}}};
always @(x1) if (x1 != $time) begin
$display("Failed at time %2d, expected %2d, got %2d", $time, $time, x1);
top.passed = 1\'b0;
end
endmodule
|
module top;
reg q, clk, d;
always_ff @(posedge clk) begin
#0 q <= d;
end
initial $display("Expected compile failure!");
endmodule
|
module tb;
reg [1:0] i, j;
reg [3:0] x[0:2];
reg error;
initial begin
error = 0;
i = 0;
j = i++;
if (i !== 2\'b01 || j !== 2\'b00) begin
$display("FAILED j = i++ --> j=%b, i=%b", j, i);
error = 1;
end
i = 0;
x[0] = 4\'dx;
x[1] = 4\'dx;
x[i++] = 0;
if (x[0] !== 4\'d0 || x[1] !== 4\'dx) begin
$display("FAILED x[i++] = 0 --> x[0]=%b, x[1]=%b, i=%b", x[0], x[1], i);
error = 1;
end
i = 0;
x[0] = 1;
x[i++] += 2;
if (x[0] !== 4\'d3) begin
$display("FAILED x[0] should be 3, but it is %d.", x[0]);
error = 1;
end
if (i !== 2\'d1) begin
$display("FAILED i should be 1, but it is %d.", i);
error = 1;
end
if (error == 0)
$display("PASSED");
end
endmodule // tb
|
// Check that using a string type as the base type for an enum results in an
// error.
module test;
enum string {
A
} e;
initial begin
$display("FAILED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always assign reg_lvalue = constant ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
if(value1 != 4\'h5)
\t$display("FAILED - 3.1.3A always assign reg_lvalue = constant\
");
else
\tbegin
$display("PASSED\
");
\t $finish;
end
always assign value1 = 4\'h5 ;
endmodule
|
module test();
`define MACRO 1
`define MACRO 1
`define MACRO 2
`undef MACRO
`define MACRO 1
endmodule
|
//****************************************************************************
//
// MODULE : parameter_multiply_test
//
// DESCRIPTION : Test module to demonstrate parameter multiplication bug.
//
// AUTHOR : Brendan J Simon ([email protected])
//
// DATE : Tuesday 6th January 2001.
//
// NOTES : It seems that Icarus Verilog 0.4 does not evaluate
// parameter multiplication properly.
// The code compiles OK, but gives a runtime error of:
// vpi_const.c:35: vpip_bits_to_dec_str: Assertion `nbits <=
// 8*sizeof(val)\' failed.
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: multiply in parameter
//****************************************************************************
module parameter_multiply_test;
parameter foo_size = 4 * 8;
reg [31:0] testv;
initial begin
testv = foo_size;
if(testv !== 32)
begin
$write("foo_size = %d\
", testv);
\t $display("FAILED");
end
else
begin
$write("foo_size = %d\
", testv);
\t $display("PASSED");
end
$finish;
end
endmodule
//****************************************************************************
// EOF : parameter_multiply_test
//****************************************************************************
|
typedef union packed {
logic [3:0] bits;
struct packed { logic [1:0] hig; logic [1:0] low; } words;
} bits_t;
module main;
bits_t foo;
initial begin
if ($bits(foo) !== 4) begin
\t $display("FAILED -- $bits(foo)=%0d", $bits(foo));
\t $finish;
end
if ($bits(bits_t) !== 4) begin
\t $display("FAILED -- $bits(bits_t)=%0d", $bits(bits_t));
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module test;
reg\td;
wire bar;
// Assign some value to bar with weak drive.
assign (weak0, weak1) bar = d;
// Whatever value is on bar, give that *strong* drive onto foo.
// The strength of an assignment is its own, and does not come
// from the strength contained in the r-value.
tri0 foo = bar;
initial begin
d = 0;
#1 if (d !== bar) begin
\t $display("FAILED -- d=%b, bar=%b", d, bar);
\t $finish;
end
if (d !== foo) begin
\t $display("FAILED -- d=%b, foo=%b", d, foo);
\t $finish;
end
d = 1;
#1 if (d !== bar) begin
\t $display("FAILED -- d=%b, bar=%b", d, bar);
\t $finish;
end
if (d !== foo) begin
\t $display("FAILED -- d=%b, foo=%b", d, foo);
\t $finish;
end
d = \'bz;
#1 if (d !== bar) begin
\t $display("FAILED -- d=%b, bar=%b", d, bar);
\t $finish;
end
if (\'b0 !== foo) begin
\t $display("FAILED -- d=%b, foo=%b", d, foo);
\t $finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule // test
|
module top;
reg [3:0][3:0] array1;
reg [3:0][3:0] array2;
reg [3:0][3:0] array3;
reg [3:0][3:0] array4;
reg [3:0][3:0] array5;
reg [3:0][3:0] array6;
reg failed = 0;
initial begin
array1[0+:2] = 8\'h21;
array1[2+:2] = 8\'h43;
array2[1+:2] = 8\'h32;
array3[1-:2] = 8\'h21;
array3[3-:2] = 8\'h43;
array4[2-:2] = 8\'h32;
array5[1:0] = 8\'h21;
array5[3:2] = 8\'h43;
array6[2:1] = 8\'h32;
$display("%h", array1);
if (array1 !== 16\'h4321) failed = 1;
$display("%h", array2);
if (array2 !== 16\'hx32x) failed = 1;
$display("%h", array3);
if (array3 !== 16\'h4321) failed = 1;
$display("%h", array4);
if (array4 !== 16\'hx32x) failed = 1;
$display("%h", array5);
if (array5 !== 16\'h4321) failed = 1;
$display("%h", array6);
if (array6 !== 16\'hx32x) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Regression test for GitHub issue 19 : Icarus only using the lowest 32
// bits of right shift operand (run-time test)
module bug();
reg a;
reg y;
initial begin
a = 1;
y = 1 >> {a, 64\'b0};
$display("%b", y);
if (y === 1\'b0)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module d();
nand n2(w1,
nand n1(w2);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate that an lvalue concat can receive an assignment.
//
// D: Validate that an lvalue can be a concatenation.
//
module main ();
reg a;
reg b;
reg working;
initial
begin
working = 1;
{a,b} = 2\'b00 ;
if( (a != 0) & (b != 0))
begin
$display("FAILED {a,b} Expected 2\'b00 - received %b%b",a,b);
working = 0;
end
{a,b} = 2\'b01 ;
if( (a != 0) & (b != 1))
begin
$display("FAILED {a,b} Expected 2\'b01 - received %b%b",a,b);
working = 0;
end
{a,b} = 2\'b10 ;
if( (a != 1) & (b != 0))
begin
$display("FAILED {a,b} Expected 2\'b10 - received %b%b",a,b);
working = 0;
end
{a,b} = 2\'b11 ;
if( (a != 1) & (b != 1))
begin
$display("FAILED {a,b} Expected 2\'b11 - received %b%b",a,b);
working = 0;
end
if(working)
$display("PASSED\
");
end
endmodule
|
module macro_args_sub();
\t`BAR(0)
endmodule
|
module top;
reg pass = 1\'b1;
reg in;
wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2;
initial begin
// $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);
#1;
if (bf1 !== 1\'bx && bf2 !== 1\'bx) begin
$display("Buffer failed, expected 2\'bxx, got %b%b", bf1, bf2);
pass = 1\'b0;
end
if (nt1 !== 1\'bx && nt2 !== 1\'bx) begin
$display("Inverter (not) failed, expected 2\'bxx, got %b%b", nt1, nt2);
pass = 1\'b0;
end
if (pd1 !== 1\'b0 && pd2 !== 1\'b0) begin
$display("Pull down failed, expected 2\'b00, got %b%b", pd1, pd2);
pass = 1\'b0;
end
if (pu1 !== 1\'b1 && pu2 !== 1\'b1) begin
$display("Pull up failed, expected 2\'b11, got %b%b", pu1, pu2);
pass = 1\'b0;
end
in = 1\'b0;
#1;
if (bf1 !== 1\'b0 && bf2 !== 1\'b0) begin
$display("Buffer failed, expected 2\'b00, got %b%b", bf1, bf2);
pass = 1\'b0;
end
if (nt1 !== 1\'b1 && nt2 !== 1\'b1) begin
$display("Inverter (not) failed, expected 2\'b11, got %b%b", nt1, nt2);
pass = 1\'b0;
end
if (pd1 !== 1\'b0 && pd2 !== 1\'b0) begin
$display("Pull down failed, expected 2\'b00, got %b%b", pd1, pd2);
pass = 1\'b0;
end
if (pu1 !== 1\'b1 && pu2 !== 1\'b1) begin
$display("Pull up failed, expected 2\'b11, got %b%b", pu1, pu2);
pass = 1\'b0;
end
in = 1\'b1;
#1;
if (bf1 !== 1\'b1 && bf2 !== 1\'b1) begin
$display("Buffer failed, expected 2\'b11, got %b%b", bf1, bf2);
pass = 1\'b0;
end
if (nt1 !== 1\'b0 && nt2 !== 1\'b0) begin
$display("Inverter (not) failed, expected 2\'b00, got %b%b", nt1, nt2);
pass = 1\'b0;
end
if (pd1 !== 1\'b0 && pd2 !== 1\'b0) begin
$display("Pull down failed, expected 2\'b00, got %b%b", pd1, pd2);
pass = 1\'b0;
end
if (pu1 !== 1\'b1 && pu2 !== 1\'b1) begin
$display("Pull up failed, expected 2\'b11, got %b%b", pu1, pu2);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
buf (bf1, bf2, in);
not (nt1, nt2, in);
pulldown (pd1, pd2);
pullup (pu1, pu2);
endmodule
|
// Check that declaring an integer typed variable for a signal that was previously
// declared as a real typed non-ANSI task port is an error.
module test;
task t;
output real x;
integer x;
$display("FAILED");
endtask
initial t();
endmodule
|
/*
* Copyright (c) 2000 Nadim Shaikli
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/***************************************************
*
* Problem: Core dump on \'out of range\' error
* search for \'thing[9]\'
*
***************************************************/
module main;
reg clk;
reg [3:0] sig;
reg [7:0] thing;
// generate a clock
always
#10 clk = ~clk;
initial
begin
$display ("\
<< BEGIN >>");
case ( sig[3:0] )
4\'b0000: thing[0] = 1\'b1;
4\'b0010: thing[2] = 1\'b1;
4\'b0011: thing[9] = 1\'b1;
endcase // case( sig[3:0] )
$display ("<< END >>\
");
$finish;
end
// Waves definition
// initial
// begin
// $dumpfile("out.dump");
// $dumpvars(0, main);
// end
endmodule // main
|
// pr1913918b
module test ( output a);
parameter [9:1] b = 9\'b0_0000_0010;
assign a = b[1] ^ b[9];
initial #1 begin
if (a !== 1\'b0) begin
\t $display("FAILED -- b=%b, a=%b", b, a);
\t $finish;
end
$display("PASSED");
end
endmodule
|
/*
* Based on Request id 1313366 in the iverilog Bugs database, or
* pr699 in the ivl-bugs database.
* Modified to force the comparison net.
*/
module bug;
wire a, b, c, d;
assign c = 1\'b0;
assign a = 1\'b1;
assign b = 1\'b0;
assign d = c ? a : b;
initial
begin
force c = 1\'b1;
#1 if (c !== 1\'b1) begin
$display("FAILED -- b = %b", b);
$finish;
end
if (d !== 1\'b1) begin
$display("FAILED -- d = %b", d);
$finish;
end
release c;
$display("PASSED");
$finish;
end
endmodule // bug
|
// Check that it is not possible to declare a variable in a package without an explicit data
// type for the variable.
pacakge P;
[3:0] x; // This is a syntax error
endpackage
|
module bug();
localparam signed [31:0] n1 = 32\'h8000_0000;
localparam signed [31:0] d1 = 32\'hFFFF_FFFF;
localparam signed [31:0] q1 = n1 / d1;
localparam signed [31:0] m1 = n1 % d1;
localparam signed [63:0] n2 = 64\'h8000_0000_0000_0000;
localparam signed [63:0] d2 = 64\'hFFFF_FFFF_FFFF_FFFF;
localparam signed [63:0] q2 = n2 / d2;
localparam signed [63:0] m2 = n2 % d2;
initial begin
$display("32 bit quotient = 0x%08h;", q1);
$display("32 bit modulus = 0x%08h;", m1);
$display("64 bit quotient = 0x%016h;", q2);
$display("64 bit modulus = 0x%016h;", m2);
if ((q1 === 32\'h8000_0000) && (q2 === 64\'h8000_0000_0000_0000)
&& (m1 === 32\'h0000_0000) && (m2 === 64\'h0000_0000_0000_0000))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// Check that declarations for dynamic arrays of dynamic arrays are supported.
module test;
// Dynamic array of dynamic arrays
int q[][];
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg [2:-1] vec;
integer idx;
initial begin
pass = 1\'b1;
idx = \'bx;
vec = 4\'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1\'bx] = 1\'b1;
`endif
if (vec !== 4\'bxxx) begin
$display("Failed vec[1\'bx], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
vec[idx] = 1\'b1;
if (vec !== 4\'bxxxx) begin
$display("Failed vec[1\'bx], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1\'bx:0] = 1\'b1;
`endif
if (vec !== 4\'bxxxx) begin
$display("Failed vec[1\'bx:0], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[0:1\'bx] = 1\'b1;
`endif
if (vec !== 4\'bxxxx) begin
$display("Failed vec[0:1\'bx], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1\'bx:1\'bx] = 1\'b1;
`endif
if (vec !== 4\'bxxxx) begin
$display("Failed vec[1\'bx:1\'bx], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1\'bx+:1] = 1\'b1;
`endif
if (vec !== 4\'bxxxx) begin
$display("Failed vec[1\'bx+:1], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1\'bx+:2] = 2\'b01;
`endif
if (vec !== 4\'bxxxx) begin
$display("Failed vec[1\'bx+:2], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1\'bx-:1] = 1\'b1;
`endif
if (vec !== 4\'bxxxx) begin
$display("Failed vec[1\'bx-:1], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
vec[1\'bx-:2] = 2\'b01;
`endif
if (vec !== 4\'bxxxx) begin
$display("Failed vec[1\'bx-:2], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
vec[idx+:1] = 1\'b1;
if (vec !== 4\'bxxxx) begin
$display("Failed vec[idx+:1], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
vec[idx+:2] = 2\'b01;
if (vec !== 4\'bxxxx) begin
$display("Failed vec[idx+:2], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
vec[idx-:1] = 1\'b1;
if (vec !== 4\'bxxxx) begin
$display("Failed vec[idx-:1], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
vec = 4\'bxxxx;
vec[idx-:2] = 2\'b01;
if (vec !== 4\'bxxxx) begin
$display("Failed vec[idx-:2], expected 4\'bxxxx, got %b", vec);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module top;
real q_tst [$];
real q_tmp [$];
real elem;
integer idx;
bit passed;
task automatic check_size(integer size,
string fname,
integer lineno);
if (q_tst.size !== size) begin
$display("%s:%0d: Failed: queue size != %0d (%0d)",
fname, lineno, size, q_tst.size);
passed = 1\'b0;
end
endtask
task automatic check_idx_value(integer idx,
real expected,
string fname,
integer lineno);
if (q_tst[idx] != expected) begin
$display("%s:%0d: Failed: element [%0d] != %.1f (%.1f)",
fname, lineno, idx, expected, q_tst[idx]);
passed = 1\'b0;
end
endtask
initial begin
passed = 1\'b1;
q_tst.delete(0); // Warning: skip delete on an empty queue
check_size(0, `__FILE__, `__LINE__);
check_idx_value(0, 0.0, `__FILE__, `__LINE__);
elem = q_tst.pop_front(); // Warning: cannot pop_front() an empty queue
if (elem != 0.0) begin
$display("Failed: pop_front() != 0.0 (%.1f)", elem);
passed = 1\'b0;
end
elem = q_tst.pop_back(); // Warning: cannot pop_back() an empty queue
if (elem != 0.0) begin
$display("Failed: pop_back() != 0.0 (%.1f)", elem);
passed = 1\'b0;
end
q_tst.push_back(2.0);
q_tst.push_front(1.0);
q_tst.push_back(3.0);
q_tst.push_back(100.0);
q_tst.delete(3); // Should $ work here?
q_tst.delete(3); // Warning: skip an out of range delete()
q_tst.delete(-1); // Warning: skip delete with negative index
q_tst.delete(\'X); // Warning: skip delete with undefined index
check_size(3, `__FILE__, `__LINE__);
if (q_tst[0] != 1.0) begin
$display("Failed: element [0] != 1.0 (%.1f)", q_tst[0]);
passed = 1\'b0;
end
if (q_tst[1] != 2.0) begin
$display("Failed: element [1] != 2.0 (%.1f)", q_tst[1]);
passed = 1\'b0;
end
if (q_tst[2] != 3.0) begin
$display("Failed: element [2] != 3.0 (%.1f)", q_tst[2]);
passed = 1\'b0;
end
if (q_tst[3] != 0.0) begin
$display("Failed: element [3] != 0.0 (%.1f)", q_tst[3]);
passed = 1\'b0;
end
if (q_tst[-1] != 0.0) begin
$display("Failed: element [-1] != 0.0 (%.1f)", q_tst[-1]);
passed = 1\'b0;
end
if (q_tst[\'X] != 0.0) begin
$display("Failed: element [\'X] != 0.0 (%.1f)", q_tst[\'X]);
passed = 1\'b0;
end
check_idx_value(-1, 0.0, `__FILE__, `__LINE__);
check_idx_value(\'X, 0.0, `__FILE__, `__LINE__);
elem = q_tst.pop_front();
if (elem != 1.0) begin
$display("Failed: element pop_front() != 1.0 (%.1f)", elem);
passed = 1\'b0;
end
elem = q_tst.pop_back();
if (elem != 3.0) begin
$display("Failed: element pop_back() != 3.0 (%.1f)", elem);
passed = 1\'b0;
end
check_size(1, `__FILE__, `__LINE__);
if ((q_tst[0] != q_tst[$]) || (q_tst[0] != 2.0)) begin
$display("Failed: q_tst[0](%.1f) != q_tst[$](%.1f) != 2.0",
q_tst[0], q_tst[$]);
passed = 1\'b0;
end
q_tst.delete();
check_size(0, `__FILE__, `__LINE__);
q_tst.push_front(5.0);
q_tst.push_front(100.0);
q_tst.push_back(100.0);
elem = q_tst.pop_back;
elem = q_tst.pop_front;
check_size(1, `__FILE__, `__LINE__);
check_idx_value(0, 5.0, `__FILE__, `__LINE__);
q_tst[0] = 1.0;
q_tst[1] = 2.5;
q_tst[1] = 2.0;
q_tst[2] = 3.0;
q_tst[-1] = 10.0; // Warning: will not be added (negative index)
q_tst[\'X] = 10.0; // Warning: will not be added (undefined index)
q_tst[4] = 10.0; // Warning: will not be added (out of range index)
idx = -1;
q_tst[idx] = 10.0; // Warning: will not be added (negative index)
idx = 3\'b0x1;
q_tst[idx] = 10.0; // Warning: will not be added (undefined index)
idx = 4;
q_tst[idx] = 10.0; // Warning: will not be added (out of range index)
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 1.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
check_idx_value(2, 3.0, `__FILE__, `__LINE__);
q_tst.delete();
q_tst[0] = 2.0;
q_tst.insert(1, 4.0);
q_tst.insert(0, 1.0);
q_tst.insert(2, 3.0);
q_tst.insert(-1, 10.0); // Warning: will not be added (negative index)
q_tst.insert(\'X, 10.0); // Warning: will not be added (undefined index)
q_tst.insert(5, 10.0); // Warning: will not be added (out of range index)
check_size(4, `__FILE__, `__LINE__);
check_idx_value(0, 1.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
check_idx_value(2, 3.0, `__FILE__, `__LINE__);
check_idx_value(3, 4.0, `__FILE__, `__LINE__);
q_tst = \'{3.0, 2.0, 1.0};
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 3.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
check_idx_value(2, 1.0, `__FILE__, `__LINE__);
q_tmp = \'{1.0, 2.0};
q_tst = q_tmp;
q_tmp[0] = 3.0;
q_tmp[2] = 1.0;
check_size(2, `__FILE__, `__LINE__);
check_idx_value(0, 1.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
q_tst[2] = 3.0;
check_size(3, `__FILE__, `__LINE__);
check_idx_value(2, 3.0, `__FILE__, `__LINE__);
q_tst = {1.0, 2.0};
check_size(2, `__FILE__, `__LINE__);
check_idx_value(0, 1.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
q_tst = \'{};
check_size(0, `__FILE__, `__LINE__);
if (passed) $display("PASSED");
end
endmodule : top
|
module bug;
enum logic[1:0] {
RST[2],
IDLE,
ACTIVE
} state;
initial begin
state = RST0;
#1 state = IDLE; // A non-blocking works, but IDLE is still a net
#1 state = ACTIVE;
#1 $display("PASSED");
end
other other(state == IDLE); // This is treating IDLE as a net
endmodule
module other(input logic val);
always @(val) $display("%0t %b", $time, val);
endmodule
|
`begin_keywords "1364-2005"
//
// Copyright (c) 1999 Thomas Coonan ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// Behavioral Verilog for CRC16 and CRC32 for use in a testbench.
//
// The specific polynomials and conventions regarding bit-ordering etc.
// are specific to the Cable Modem DOCSIS protocol, but the general scheme
// should be reusable for other types of CRCs with some fiddling.
//
// This CRC code works for a specific type of network protocol, and it
// must do certain byte swappings, etc. You may need to play with it
// for your protocol. Also, make sure the polynomials are what you
// really want. This is obviously, not synthesizable - I just used this
// in a testbench at one point.
//
// These tasks are crude and rely on some global parameters. They should
// also read from a file, yada yada yada. It is probably better to do this
// with a PLI call, but here it is anyway..
//
// The test case includes a golden DOCSIS (Cable Modem) test message that
// was captured in a lab.
//
// tom coonan, 1999.
//
module test_gencrc;
// *** Buffer for the Golden Message ***
reg [7:0]\ttest_packet[0:54];
// *** Global parameter block for the CRC32 calculator.
//
parameter\tCRC32_POLY = 32\'h04C11DB7;
reg [ 7:0]\tcrc32_packet[0:255];
integer\t\tcrc32_length;
reg [31:0]\tcrc32_result;
// *** Global parameter block for the CRC16 calculator.
//
parameter\tCRC16_POLY = 16\'h1020;
reg [ 7:0]\tcrc16_packet[0:255];
integer\t\tcrc16_length;
reg [15:0]\tcrc16_result;
`define TEST_GENCRC
`ifdef TEST_GENCRC
// Call the main test task and then quit.
//
initial begin
main_test;
$finish;
end
`endif
// ****************************************************************
// *
// * GOLDEN MESSAGE
// *
// * The golden message is a DOCSIS frame that was captured off
// * the Broadcom reference design. It is a MAP message. It
// * includes a HCS (crc 16) and a CRC32.
// *
// *
// ****************************************************************
//
task initialize_test_packet;
begin
test_packet[00] = 8\'hC2;\t// FC. HCS coverage starts here.
test_packet[01] = 8\'h00;\t// MACPARAM
test_packet[02] = 8\'h00;\t// MAC LEN
test_packet[03] = 8\'h30;\t// MAC LEN. HCS Coverage includes this byte and ends here.
test_packet[04] = 8\'hF2;\t// CRC16 (also known as HCS)
test_packet[05] = 8\'hCF;\t// CRC16 cont..
test_packet[06] = 8\'h01;\t// Start of the IEEE payload. CRC32 covererage starts here. This is the DA field
test_packet[07] = 8\'hE0;\t// DA field cont..
test_packet[08] = 8\'h2F;\t// DA field cont..
test_packet[09] = 8\'h00;\t// DA field cont..
test_packet[10] = 8\'h00;\t// DA field cont..
test_packet[11] = 8\'h01;\t// DA field cont..
test_packet[12] = 8\'h00;\t// SA field
test_packet[13] = 8\'h80;\t// SA field cont..
test_packet[14] = 8\'h42;\t// SA field cont..
test_packet[15] = 8\'h42;\t// SA field cont..
test_packet[16] = 8\'h20;\t// SA field cont..
test_packet[17] = 8\'h9E;\t// SA field cont..
test_packet[18] = 8\'h00;\t// IEEE LEN field
test_packet[19] = 8\'h1E;\t// IEEE LEN field cont.
test_packet[20] = 8\'h00;\t// LLC field.
test_packet[21] = 8\'h00;\t// LLC field cont...
test_packet[22] = 8\'h03;\t// LLC field cont...
test_packet[23] = 8\'h01;\t// LLC field cont...
test_packet[24] = 8\'h03;\t// LLC field cont... This is also the TYPE, which indicates MAP.
test_packet[25] = 8\'h00;\t// LLC field cont...
test_packet[26] = 8\'h01;\t// Start of MAP message payload.
test_packet[27] = 8\'h01;\t// MAP message payload..
test_packet[28] = 8\'h02;\t// MAP message payload..
test_packet[29] = 8\'h00;\t// MAP message payload..
test_packet[30] = 8\'h00;\t// MAP message payload..
test_packet[31] = 8\'h18;\t// MAP message payload..
test_packet[32] = 8\'hAA;\t// MAP message payload..
test_packet[33] = 8\'h58;\t// MAP message payload..
test_packet[34] = 8\'h00;\t// MAP message payload..
test_packet[35] = 8\'h18;\t// MAP message payload..
test_packet[36] = 8\'hA8;\t// MAP message payload..
test_packet[37] = 8\'hA0;\t// MAP message payload..
test_packet[38] = 8\'h02;\t// MAP message payload..
test_packet[39] = 8\'h03;\t// MAP message payload..
test_packet[40] = 8\'h03;\t// MAP message payload..
test_packet[41] = 8\'h08;\t// MAP message payload..
test_packet[42] = 8\'hFF;\t// MAP message payload..
test_packet[43] = 8\'hFC;\t// MAP message payload..
test_packet[44] = 8\'h40;\t// MAP message payload..
test_packet[45] = 8\'h00;\t// MAP message payload..
test_packet[46] = 8\'h00;\t// MAP message payload..
test_packet[47] = 8\'h01;\t// MAP message payload..
test_packet[48] = 8\'hC0;\t// MAP message payload..
test_packet[49] = 8\'h14;\t// Last byte of MAP payload, last byte covered by CRC32.
test_packet[50] = 8\'hDD;\t// CRC32 Starts here
test_packet[51] = 8\'hBF;\t// CRC32 cont..
test_packet[52] = 8\'hC1;\t// CRC32 cont..
test_packet[53] = 8\'h2E;\t// Last byte of CRC32, last byte of DOCSIS.
end
endtask
// *************************************************************************
// *
// * Main test task.
// *
// * Use our primary "golden packet". Copy into the generic global
// * variables that the low-level \'gencrc16\' and \'gencrc32\' tasks use.
// * Comare against the expected values and report SUCCESS or FAILURE.
// *
// *************************************************************************
//
task main_test;
integer\ti, j;
integer\tnum_errors;
reg [15:0]\tcrc16_expected;
reg [31:0]\tcrc32_expected;
begin
num_errors = 0;
// Initialize the Golden Message!
//
initialize_test_packet;
// **** TEST CRC16
//
//
// Copy golden test_packet into the main crc16 buffer..
for (i=0; i<4; i=i+1) begin
crc16_packet[i] = test_packet[i];
end
crc16_expected = {test_packet[4], test_packet[5]};
crc16_length = 4; // Must tell test function the length
gencrc16; // Call main test function
if (crc16_result !== crc16_expected)
begin
num_errors = num_errors + 1;
$display ("FAILED - Actual crc16_result = %h, Expected = %h",
crc16_result, crc16_expected);
end
// **** TEST CRC16
//
j = 0;
for (i=6; i<50; i=i+1) begin
crc32_packet[j] = test_packet[i];
j = j + 1;
end
crc32_expected = {test_packet[50], test_packet[51], test_packet[52], test_packet[53]};
crc32_length = 44;
gencrc32;
if (crc32_result !== crc32_expected)
begin
$display ("FAILED - Actual crc32_result = %h, Expected = %h",
crc32_result, crc32_expected);
num_errors = num_errors + 1;
end
if(num_errors == 0)
$display("PASSED");
end
endtask
// ****************************************************************
// *
// * Main working CRC tasks are: gencrc16, gencrc32.
// *
// * These tasks rely on some globals (see front of program).
// *
// ****************************************************************
// Generate a (DOCSIS) CRC16.
//
// Uses the GLOBAL variables:
//
// Globals referenced:
// parameter\tCRC16_POLY = 16\'h1020;
// reg [ 7:0]\tcrc16_packet[0:255];
// integer\tcrc16_length;
//
// Globals modified:
// reg [15:0]\tcrc16_result;
//
task gencrc16;
integer\tbyte, bit;
reg\t\tmsb;
reg [7:0]\tcurrent_byte;
reg [15:0]\ttemp;
begin
crc16_result = 16\'hffff;
for (byte = 0; byte < crc16_length; byte = byte + 1) begin
current_byte = crc16_packet[byte];
for (bit = 0; bit < 8; bit = bit + 1) begin
msb = crc16_result[15];
crc16_result = crc16_result << 1;
if (msb != current_byte[bit]) begin
crc16_result = crc16_result ^ CRC16_POLY;
crc16_result[0] = 1;
end
end
end
// Last step is to "mirror" every bit, swap the 2 bytes, and then complement each bit.
//
// Mirror:
for (bit = 0; bit < 16; bit = bit + 1)
temp[15-bit] = crc16_result[bit];
// Swap and Complement:
crc16_result = ~{temp[7:0], temp[15:8]};
end
endtask
// Generate a (DOCSIS) CRC32.
//
// Uses the GLOBAL variables:
//
// Globals referenced:
// parameter\tCRC32_POLY = 32\'h04C11DB7;
// reg [ 7:0]\tcrc32_packet[0:255];
// integer\tcrc32_length;
//
// Globals modified:
// reg [31:0]\tcrc32_result;
//
task gencrc32;
integer\tbyte, bit;
reg\t\tmsb;
reg [7:0]\tcurrent_byte;
reg [31:0]\ttemp;
begin
crc32_result = 32\'hffffffff;
for (byte = 0; byte < crc32_length; byte = byte + 1) begin
current_byte = crc32_packet[byte];
for (bit = 0; bit < 8; bit = bit + 1) begin
msb = crc32_result[31];
crc32_result = crc32_result << 1;
if (msb != current_byte[bit]) begin
crc32_result = crc32_result ^ CRC32_POLY;
crc32_result[0] = 1;
end
end
end
// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
//
// Mirror:
for (bit = 0; bit < 32; bit = bit + 1)
temp[31-bit] = crc32_result[bit];
// Swap and Complement:
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
end
endtask
endmodule
`end_keywords
|
//
// Copyright (c) 1999 Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
reg [3:0] a;
wire b;
assign b = !a;
initial begin
a = 4\'d1;
#1;
if (b!==0) begin
$display("FAILED");
$finish;
end
a = 4\'d0;
#1;
if (b!==1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
// Check that non-ANSI output ports that have a Verilog data type are elaborated
// as variables and be assigned a value.
module test;
output reg a;
output reg [1:0] b;
output reg signed [1:0] c;
output integer d;
output time e;
initial begin
a = 0;
b = 0;
c = 0;
d = 0;
e = 0;
$display("PASSED");
end
endmodule
|
// Check that packed arrays of all sorts get elaborated without an error and
// that the resulting type has the right packed width.
package p;
typedef logic [2:0] vector;
endpackage
module test;
typedef bit bit2;
typedef logic [1:0] vector;
bit2 [1:0] b;
vector [2:0] l;
p::vector [3:0] scoped_pa;
typedef enum logic [7:0] {
A
} E;
typedef E [1:0] EP;
typedef EP [2:0] EPP;
E e;
EP ep1;
E [1:0] ep2;
EP [2:0] epp1;
EPP epp2;
EPP [3:0] eppp;
enum logic [7:0] {
B
} [1:0] ep3;
typedef struct packed {
longint x;
} S1;
typedef struct packed {
time t;
integer i;
logic [1:0] x;
bit [3:0] y;
int z;
shortint w;
E e;
EP ep;
S1 s;
} S2;
localparam S_SIZE = 64 + 32 + 2 + 4 + 32 + 16 + 8 + 8*2 + 64;
typedef S2 [3:0] SP;
typedef SP [9:0] SPP;
S2 s;
SP sp1;
S2 [3:0] sp2;
SP [9:0] spp1;
SPP spp2;
SPP [1:0] sppp;
struct packed {
S2 s;
} [3:0] sp3;
bit failed = 1\'b0;
initial begin
// Packed arrays of basic types
failed |= $bits(b) !== 2;
failed |= $bits(l) !== 2 * 3;
failed |= $bits(scoped_pa) !== 3 * 4;
// Packed arrays of enums
failed |= $bits(e) !== 8;
failed |= $bits(ep1) !== $bits(e) * 2;
failed |= $bits(ep2) !== $bits(ep1);
failed |= $bits(ep3) !== $bits(ep1);
failed |= $bits(epp1) !== $bits(ep1) * 3;
failed |= $bits(epp2) !== $bits(epp1);
failed |= $bits(eppp) !== $bits(epp1) * 4;
// Packed arrays of structs
failed |= $bits(s) !== S_SIZE;
failed |= $bits(sp1) !== $bits(s) * 4;
failed |= $bits(sp2) !== $bits(sp1);
failed |= $bits(sp3) !== $bits(sp1);
failed |= $bits(spp1) !== $bits(sp1) * 10;
failed |= $bits(spp1) !== $bits(spp2);
failed |= $bits(sppp) !== $bits(spp1) * 2;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2000 Chris Lattner
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Really, this only tests the ability to compile the ~i expression as
* a parameter to a system task.
*/
module test;
reg i;
initial begin
i = 0;
$display("~i = %d", ~i);
$display("PASSED");
end
endmodule
|
// Check that it is possible to declare the data type for a time type task port
// separately from the direction for non-ANSI style port declarations.
module test;
task t;
input x;
time x;
if (x == 10 && $bits(x) == $bits(time)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t(10);
endmodule
|
/*
* The base vpi_get() is not returning the correct result for
* a signed value. There are obviously other problems as well.
*/
module top;
reg [7:0] rval;
reg signed [7:0] base; // This fails (no sign extension?).
// reg signed [31:0] base; // This works on a 32 bit machine.
// integer base; // And this works
initial begin
rval = 8\'b10100101;
for (base = 0; base > -8; base = base -1) begin
$displayb("%3d %b ", base, rval[base +: 8], rval[base +: 8]);
end
$display;
for (base = 0; base > -8; base = base -1) begin
$displayb("%3d %b ", base+1, rval[base+1 +: 8], rval[base+1 +: 8]);
end
end
endmodule
|
/*
* udp_dff.v
* This is based on a bug report from Chacko Neroth. The original
* compalint was that the (b0) in the table generated a syntax error
* message.
*/
// Same as udp_dff except use a standard UDP calling syntax.
module test;
reg dd, clk, notifier;
wire qq;
dff d1 (qq, clk, dd, notifier);
initial begin
dd = 1\'b0;
clk= 0;
#1 clk = 1;
#1 if (qq !== 1\'b0) begin
\t $display("FAILED -- D=%b, Q=%b", dd, qq);
\t $finish;
end
dd = 1\'b1;
clk = 0;
#1 if (qq !== 1\'b0) begin
\t $display("FAILED -- D=%b (hold 0), Q=%b", dd, qq);
\t $finish;
end
clk = 1;
#1 if (qq !== 1\'b1) begin
\t $display("FAILED -- D=%b, Q=%b", dd, qq);
\t $finish;
end
dd = 1\'bx;
clk = 0;
#1 if (qq !== 1\'b1) begin
\t $display("FAILED -- D=%b (hold 1), Q=%b", dd, qq);
\t $finish;
end
clk = 1;
#1 if (qq !== 1\'bx) begin
\t $display("FAILED -- D=%b, Q=%b", dd, qq);
\t $finish;
end
dd = 1\'bz;
clk = 0;
#1 if (qq !== 1\'bx) begin
\t $display("FAILED -- D=%b (hold x), Q=%b", dd, qq);
\t $finish;
end
clk = 1;
#1 if (qq !== 1\'bx) begin
\t $display("FAILED -- D=%b, Q=%b", dd, qq);
\t $finish;
end
dd = 1\'b0;
clk = 0;
#1 if (qq !== 1\'bx) begin
\t $display("FAILED -- D=%b (hold x), Q=%b", dd, qq);
\t $finish;
end
$display("PASSED");
end
endmodule
primitive dff (Q, C, D, notifier);
output Q;
reg\t Q;
input C, D, notifier;
table
// C D notifier : Q : Q+
(01) 0 ? : ? : 0 ; //normal clocking case
(01) 1 ? : ? : 1 ; //normal clocking case
(01) x ? : ? : x ; //normal clocking, input undefined
(b0) ? ? : ? : - ; //clock falling or held low
// if the above is changed to the following, it goes thru
// (10) ? ? : ? : - ; //clock falling
// but the following, which (b0) should iterate to fails also
// (00) ? ? : ? : - ; //clock held low
b (??) ? : ? : - ; //hold Q if D changes
? ? * : ? : x ; //notifier case
endtable
endprimitive
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate constant addition in vector range, and rhs.
//
//
module main ();
reg [\'d4 + \'b110 : 0] val1;
reg [10\'h1+ \'d9 : 0 ] val2 ;
initial
begin
val1 = 11\'h1 + \'d4;
val2 = 11\'h2 + 6;
if((val1 === 11\'h5) && (val2 === 11\'h8))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module test();
reg [3:0] IN;
wire [3:0] OUT;
assign OUT = IN;
initial begin
#1 $peek(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $force(IN[2:1]);
#1 $peek(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $release(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $force(IN[2:1]);
#1 $peek(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $poke(IN[2:1]);
#1 $peek(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $release(IN[2:1]);
#0 $display("display :%b", OUT);
#1 $poke(IN[2:1]);
#1 $peek(IN[2:1]);
#0 $display("display :%b", OUT);
end
endmodule
|
module example;
reg [3:0] mem [0:7];
reg [3:0] addr;
wire [3:0] m0 = mem[0];
wire [3:0] m1 = mem[1];
wire [3:0] m2 = mem[2];
wire [3:0] m3 = mem[3];
wire [3:0] m4 = mem[4];
wire [3:0] m5 = mem[5];
wire [3:0] m6 = mem[6];
wire [3:0] m7 = mem[7];
wire [3:0] maddr = mem[addr];
initial begin
$write( " " );
$display(
"time addr maddr m0 m1 m2 m3 m4 m5 m6 m7" );
$write( " " );
$display(
"---- ---- ----- ---- ---- ---- ---- ---- ---- ---- ----" );
$monitor( "%T %b %b %b %b %b %b %b %b %b %b",
$time, addr, maddr,
m0, m1, m2, m3, m4, m5, m6, m7 );
mem[0] = 8;
mem[1] = 1;
mem[2] = 2;
mem[3] = 3;
mem[4] = 4;
mem[5] = 5;
mem[6] = 6;
mem[7] = 7;
addr = 0; // 0
#100 addr = 1; // 100
#100 addr = 2; // 200
#100 addr = 3; // 300
#100 addr = 4; // 400
#100 addr = 5; // 500
#100 addr = 6; // 600
#100 addr = 7; // 700
#100 addr = 8; // 800
#100 addr = 4\'b001x; // 900
#100 addr = 4\'b01x0; // 1000
#100 addr = 4\'b0x01; // 1100
#100 addr = 0; // 1200
#100 mem[addr] = 9; // 1300
#100 addr = 3; // 1400
#100 mem[addr] = 10; // 1500
#100 addr = 6; // 1600
#100 mem[addr] = 11; // 1700
#100 addr = 8; // 1800
#100 mem[addr] = 12; // 1900
#100 addr = 4\'b010x; // 2000
#100 mem[addr] = 13; // 2100
#100 addr = 4\'b00x1; // 2200
#100 mem[addr] = 14; // 2300
#100 addr = 4\'b0x10; // 2400
#100 mem[addr] = 15; // 2500
#100 addr = 4\'bxxxx; // 2600
#100 mem[addr] = 0; // 2700
#100 $display( "Finish at time %T", $time );
end
endmodule
|
module test();
wire [7:0] value1;
wire value2;
assign value1[3:0] = 4\'d2;
assign value2 = |value1;
initial begin
#2 $display("%b %b", value1, value2);
if (value2 === 1\'b1)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* This demonstrates that strings can be used as
* constructed formats in $display et al.
*/
module main;
string foo;
string bar;
initial begin
bar = "PAS";
foo = {bar, "SED"};
if (foo != "PASSED") begin
\t $display("FAILED (1)");
\t $finish;
end
foo = "PAS";
bar = "SED";
$display({foo,bar});
$finish;
end
endmodule // main
|
module ivitest;
reg clock_1x, clock_2x;
reg [31:1] w [0:1];
wire [31:1] w0 = w[0];
wire [31:1] w1 = w[1];
initial begin
#0; //avoid time-0 race
clock_1x = 0;
clock_2x = 0;
$monitor($time,,"w0=%h, w1=%h", w0, w1);
#1;
forever begin
clock_1x = !clock_1x;
clock_2x = !clock_2x;
#5;
clock_2x = !clock_2x;
#5;
end
end
reg phase;
always @(clock_1x) begin
phase = #1 clock_1x;
end
reg [31:1] u;
always @(posedge clock_2x) begin
u <= \'haaaaaaaa;
end
reg [31:1] v;
always @(posedge clock_2x) begin
v <= \'h99999999;
if (phase) begin
w[0] <= v;
w[1] <= u;
end
end
reg [31:1] x0, x1;
always @(posedge clock_1x) begin
x0 <= w[0];
x1 <= w[1];
end
initial begin
// $dumpfile( "test.vcd" );
// $dumpvars;
#100;
$finish(0);
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test while loops in VHDL.
module vhdl_while_test;
logic start;
int out;
vhdl_while dut(start, out);
initial begin
start = 1;
#1;
if(out !== 10) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
module dummy (.B(A[2:1]));
input [2:1] A;
always @(A)
$display (A);
endmodule
module test ();
reg [2:0] A;
dummy dummy(A[1:0]);
integer idx;
initial begin
for (idx = 0 ; idx <= 'h7 ; idx = idx+1)
#1 A <= idx;
#1 $finish(0);
end
endmodule
|
/*
* Copyright (c) 2000 Peter monta ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// Reworked by SDW to be self checking
module main;
reg [7:0] x;
reg [7:0] y;
reg [2:0] i;\t// Was a wire..
reg error;
initial begin
#5;
x[i] <= #1 0;
y[i] = 0;
end
initial
begin
error = 0;
#1;
i = 1;
#7;
if(x[i] !== 1\'b0)
begin
$display("FAILED - x[1] != 0");
error = 1;
end
if(y[i] !== 1\'b0)
begin
$display("FAILED - y[1] != 0");
error = 1;
end
if(error === 0)
$display("PASSED");
end
endmodule
|
// Check that declarations for queues of dynamic arrays are supported.
module test;
// Queue of dynamic arrays
int q[][$];
endmodule
|
module test ();
parameter param = 3;
reg [2:0] dummy;
initial dummy = block.f(0);
generate
if (param==1) begin : block
function [2:0] f;
input i;
begin
$display ("if param==1");
f = param;
end
endfunction
end else if (param==2) begin : block
function [2:0] f;
input i;
begin
$display ("else if param==2");
f = param;
end
endfunction
end
endgenerate
endmodule
module top ();
test #(1) a();
test #(2) b();
initial begin
#1 if (a.dummy !== 1) begin
\t $display("FAILED -- a.dummy = %d", a.dummy);
\t $finish;
end
if (b.dummy !== 2) begin
\t $display("FAILED -- b.dummy = %d", b.dummy);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule
|
// Check that declaring a real typed non-ANSI task port for signal that was
// previously declared as a variable is an error. Even if the types for both
// declarations are the same.
module test;
task t;
real x;
output real x;
$display("FAILED");
endtask
real y;
initial t(y);
endmodule
|
// Copyright 2008, Martin Whitaker
// This file may be freely copied for any purpose
module shift();
reg [5:0] S;
wire [63:0] Y;
assign Y = 1 << S;
initial begin
S = 32;
#1 $display("1 << %0d = %b", S, Y);
end
endmodule
|
// Copyright 2008, Martin Whitaker.
// This file may be freely copied for any purpose.
module sub_module();
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin:gen_block
localparam l = i + 1;
event trigger;
always @trigger $display("generate block %0d triggered", l);
end
endgenerate
initial begin:my_block
parameter p = 0;
localparam l = p + 1;
event trigger;
@trigger $display("block %0d triggered", l);
end
task my_task;
parameter p = 0;
localparam l = p + 1;
event trigger;
@trigger $display("task %0d triggered", l);
endtask
initial my_task;
endmodule
module top_module();
sub_module sub();
defparam sub.my_block.p = 4;
defparam sub.my_task.p = 5;
initial begin
#1 ->sub.gen_block[0].trigger;
#1 ->sub.gen_block[1].trigger;
#1 ->sub.gen_block[2].trigger;
#1 ->sub.gen_block[3].trigger;
#1 ->sub.my_block.trigger;
#1 ->sub.my_task.trigger;
#1 $finish(0);
end
endmodule
|
module top;
real rl1, rl2;
wire eq, ne, gt, ge, lt, le;
reg passed = 1\'b1;
// Check that a decimal constant is converted to a real value.
assign eq = rl2 == 0;
// assign eq = rl2 == rl1;
assign ne = rl2 != rl1;
assign gt = rl2 > rl1;
assign ge = rl2 >= rl1;
assign lt = rl2 < rl1;
assign le = rl2 <= rl1;
initial begin
rl1 = 0.0;
rl2 = 0.0;
#1 if ({eq,ne,gt,ge,lt,le} != 6\'b100101) begin
$display("Failed: expected %b, received %b", 6\'b100101,
{eq,ne,gt,ge,lt,le});
passed = 1\'b0;
end
#1 rl2 = -1.0;
#1 if ({eq,ne,gt,ge,lt,le} != 6\'b010011) begin
$display("Failed: expected %b, received %b", 6\'b010011,
{eq,ne,gt,ge,lt,le});
passed = 1\'b0;
end
#1 rl2 = 1.0;
#1 if ({eq,ne,gt,ge,lt,le} != 6\'b011100) begin
$display("Failed: expected %b, received %b", 6\'b001100,
{eq,ne,gt,ge,lt,le});
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
module naughty_module(
\tinput clk,
\tinput [71:0] pzw,
\tinput [95:0] xy_d,
\tinput [23:0] pbit,
\toutput [95:0] xas,
\toutput [95:0] yas
);
initial $display("PASSED");
function [3:0] xa;
\tinput pbit;
\tinput [1:0] ix_in;
\tinput [1:0] iy_in;
\tinput [3:0] pzw;
begin
\txa =
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h0} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h1} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h2} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h3} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h4} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h5} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h6} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h7} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h0} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h1} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h2} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h3} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h4} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h5} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h6} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h7} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h0} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h1} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h2} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h3} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h4} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h5} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h6} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h7} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h0} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h1} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h2} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h3} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h4} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h5} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h6} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h7} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h0} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h1} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h2} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h3} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h4} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h5} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h6} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h7} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h0} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h1} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h2} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h3} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h4} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h5} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h6} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h7} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h0} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h1} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h2} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h3} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h4} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h5} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h6} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h7} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h0} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h1} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h2} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h3} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h4} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h5} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h6} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h7} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h0} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h1} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h2} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h3} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h4} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h5} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h6} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h7} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h0} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h1} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h2} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h3} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h4} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h5} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h6} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h7} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h0} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h1} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h2} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h3} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h4} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h5} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h6} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h7} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h0} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h1} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h2} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h3} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h4} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h5} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h6} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h7} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h0} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h1} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h2} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h3} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h4} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h5} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h6} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h7} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h0} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h1} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h2} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h3} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h4} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h5} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h6} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h7} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h0} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h1} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h2} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h3} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h4} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h5} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h6} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h7} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h0} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h1} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h2} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h3} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h4} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h5} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h6} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h7} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h0} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h1} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h2} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h3} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h4} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h5} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h6} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h7} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h0} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h1} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h2} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h3} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h4} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h5} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h6} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h7} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h0} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h1} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h2} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h3} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h4} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h5} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h6} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h7} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h0} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h1} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h2} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h3} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h4} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h5} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h6} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h7} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h0} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h1} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h2} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h3} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h4} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h5} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h6} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h7} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h0} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h1} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h2} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h3} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h4} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h5} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h6} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h7} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h0} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h1} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h2} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h3} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h4} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h5} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h6} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h7} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h0} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h1} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h2} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h3} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h4} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h5} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h6} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h7} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h0} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h1} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h2} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h3} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h4} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h5} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h6} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h7} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h0} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h1} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h2} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h3} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h4} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h5} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h6} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h7} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h0} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h1} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h2} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h3} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h4} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h5} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h6} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h7} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h0} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h1} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h2} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h3} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h4} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h5} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h6} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h7} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h0} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h1} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h2} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h3} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h4} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h5} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h6} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h7} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h0} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h1} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h2} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h3} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h4} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h5} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h6} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h7} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h0} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h1} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h2} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h3} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h4} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h5} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h6} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h7} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h0} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h1} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h2} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h3} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h4} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h5} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h6} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h7} ? 4\'h3 :
\t4\'h0;
end
endfunction
function [3:0] ya;
\tinput pbit;
\tinput [1:0] ix_in;
\tinput [1:0] iy_in;
\tinput [3:0] pzw;
begin
\tya =
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h0} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h1} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h2} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h3} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h4} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h5} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h6} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h7} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h0} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h1} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h2} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h3} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h4} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h5} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h6} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h7} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h0} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h1} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h2} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h3} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h4} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h5} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h6} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h7} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h0} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h1} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h2} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h3} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h4} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h5} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h6} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h7} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h0} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h1} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h2} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h3} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h4} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h5} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h6} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h7} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h0} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h1} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h2} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h3} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h4} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h5} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h6} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h7} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h0} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h1} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h2} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h3} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h4} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h5} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h6} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h7} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h0} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h1} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h2} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h3} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h4} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h5} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h6} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h7} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h0} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h1} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h2} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h3} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h4} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h5} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h6} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h7} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h0} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h1} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h2} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h3} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h4} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h5} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h6} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h7} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h0} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h1} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h2} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h3} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h4} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h5} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h6} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h7} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h0} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h1} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h2} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h3} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h4} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h5} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h6} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h7} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h0} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h1} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h2} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h3} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h4} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h5} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h6} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h7} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h0} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h1} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h2} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h3} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h4} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h5} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h6} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h7} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h0} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h1} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h2} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h3} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h4} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h5} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h6} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h7} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h0} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h1} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h2} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h3} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h4} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h5} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h6} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h7} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h0} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h1} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h2} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h3} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h4} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h5} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h6} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h7} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h0} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h1} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h2} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h3} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h4} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h5} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h6} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h7} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h0} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h1} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h2} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h3} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h4} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h5} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h6} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h7} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h0} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h1} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h2} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h3} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h4} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h5} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h6} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h7} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h0} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h1} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h2} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h3} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h4} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h5} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h6} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h7} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h0} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h1} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h2} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h3} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h4} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h5} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h6} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h7} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h0} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h1} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h2} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h3} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h4} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h5} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h6} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h7} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h0} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h1} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h2} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h3} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h4} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h5} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h6} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h7} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h0} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h1} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h2} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h3} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h4} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h5} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h6} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h7} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h0} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h1} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h2} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h3} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h4} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h5} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h6} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h7} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h0} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h1} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h2} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h3} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h4} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h5} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h6} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h7} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h0} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h1} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h2} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h3} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h4} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h5} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h6} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h7} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h0} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h1} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h2} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h3} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h4} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h5} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h6} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h7} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h0} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h1} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h2} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h3} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h4} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h5} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h6} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h7} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h0} ? 4\'h5 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h1} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h2} ? 4\'h8 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h3} ? 4\'h7 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h4} ? 4\'h4 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h5} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h6} ? 4\'h1 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h7} ? 4\'h2 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h0} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h1} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h2} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h3} ? 4\'h9 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h4} ? 4\'h6 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h5} ? 4\'h3 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h6} ? 4\'h0 :
\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h7} ? 4\'h0 :
\t4\'h0;
end
endfunction
\treg [95:0] r_xa;
\treg [95:0] r_ya;
\talways @(posedge clk)
\tbegin
\t\tr_xa[ 3: 0] <= xa(pbit[ 0], xy_d[ 1: 0], xy_d[ 3: 2], pzw[ 2: 0]);
\t\tr_xa[ 7: 4] <= xa(pbit[ 1], xy_d[ 5: 4], xy_d[ 7: 6], pzw[ 5: 3]);
\t\tr_xa[11: 8] <= xa(pbit[ 2], xy_d[ 9: 8], xy_d[11:10], pzw[ 8: 6]);
\t\tr_xa[15: 12] <= xa(pbit[ 3], xy_d[13:12], xy_d[15:14], pzw[11: 9]);
\t\tr_xa[19: 16] <= xa(pbit[ 4], xy_d[17:16], xy_d[19:18], pzw[14:12]);
\t\tr_xa[23: 20] <= xa(pbit[ 5], xy_d[21:20], xy_d[23:22], pzw[17:15]);
\t\tr_xa[27: 24] <= xa(pbit[ 6], xy_d[25:24], xy_d[27:26], pzw[20:18]);
\t\tr_xa[31: 28] <= xa(pbit[ 7], xy_d[29:28], xy_d[31:30], pzw[23:21]);
\t\tr_xa[35: 32] <= xa(pbit[ 8], xy_d[33:32], xy_d[35:34], pzw[26:24]);
\t\tr_xa[39: 36] <= xa(pbit[ 9], xy_d[37:36], xy_d[39:38], pzw[29:27]);
\t\tr_xa[43: 40] <= xa(pbit[10], xy_d[41:40], xy_d[43:42], pzw[32:30]);
\t\tr_xa[47: 44] <= xa(pbit[11], xy_d[45:44], xy_d[47:46], pzw[35:33]);
\t\tr_xa[51: 48] <= xa(pbit[12], xy_d[49:48], xy_d[51:50], pzw[38:36]);
\t\tr_xa[55: 52] <= xa(pbit[13], xy_d[53:52], xy_d[55:54], pzw[41:39]);
\t\tr_xa[59: 56] <= xa(pbit[14], xy_d[57:56], xy_d[59:58], pzw[44:42]);
\t\tr_xa[63: 60] <= xa(pbit[15], xy_d[61:60], xy_d[63:62], pzw[47:45]);
\t\tr_xa[67: 64] <= xa(pbit[16], xy_d[65:64], xy_d[67:66], pzw[50:48]);
\t\tr_xa[71: 68] <= xa(pbit[17], xy_d[69:68], xy_d[71:70], pzw[53:51]);
\t\tr_xa[75: 72] <= xa(pbit[18], xy_d[73:72], xy_d[75:74], pzw[56:54]);
\t\tr_xa[79: 76] <= xa(pbit[19], xy_d[77:76], xy_d[79:78], pzw[59:57]);
\t\tr_xa[83: 80] <= xa(pbit[20], xy_d[81:80], xy_d[83:82], pzw[62:60]);
\t\tr_xa[87: 84] <= xa(pbit[21], xy_d[85:84], xy_d[87:86], pzw[65:63]);
\t\tr_xa[91: 88] <= xa(pbit[22], xy_d[89:88], xy_d[91:90], pzw[68:66]);
\t\tr_xa[95: 92] <= xa(pbit[23], xy_d[93:92], xy_d[95:94], pzw[71:69]);
\t\tr_ya[ 3: 0] <= ya(pbit[ 0], xy_d[ 1: 0], xy_d[ 3: 2], pzw[ 2: 0]);
\t\tr_ya[ 7: 4] <= ya(pbit[ 1], xy_d[ 5: 4], xy_d[ 7: 6], pzw[ 5: 3]);
\t\tr_ya[11: 8] <= ya(pbit[ 2], xy_d[ 9: 8], xy_d[11:10], pzw[ 8: 6]);
\t\tr_ya[15: 12] <= ya(pbit[ 3], xy_d[13:12], xy_d[15:14], pzw[11: 9]);
\t\tr_ya[19: 16] <= ya(pbit[ 4], xy_d[17:16], xy_d[19:18], pzw[14:12]);
\t\tr_ya[23: 20] <= ya(pbit[ 5], xy_d[21:20], xy_d[23:22], pzw[17:15]);
\t\tr_ya[27: 24] <= ya(pbit[ 6], xy_d[25:24], xy_d[27:26], pzw[20:18]);
\t\tr_ya[31: 28] <= ya(pbit[ 7], xy_d[29:28], xy_d[31:30], pzw[23:21]);
\t\tr_ya[35: 32] <= ya(pbit[ 8], xy_d[33:32], xy_d[35:34], pzw[26:24]);
\t\tr_ya[39: 36] <= ya(pbit[ 9], xy_d[37:36], xy_d[39:38], pzw[29:27]);
\t\tr_ya[43: 40] <= ya(pbit[10], xy_d[41:40], xy_d[43:42], pzw[32:30]);
\t\tr_ya[47: 44] <= ya(pbit[11], xy_d[45:44], xy_d[47:46], pzw[35:33]);
\t\tr_ya[51: 48] <= ya(pbit[12], xy_d[49:48], xy_d[51:50], pzw[38:36]);
\t\tr_ya[55: 52] <= ya(pbit[13], xy_d[53:52], xy_d[55:54], pzw[41:39]);
\t\tr_ya[59: 56] <= ya(pbit[14], xy_d[57:56], xy_d[59:58], pzw[44:42]);
\t\tr_ya[63: 60] <= ya(pbit[15], xy_d[61:60], xy_d[63:62], pzw[47:45]);
\t\tr_ya[67: 64] <= ya(pbit[16], xy_d[65:64], xy_d[67:66], pzw[50:48]);
\t\tr_ya[71: 68] <= ya(pbit[17], xy_d[69:68], xy_d[71:70], pzw[53:51]);
\t\tr_ya[75: 72] <= ya(pbit[18], xy_d[73:72], xy_d[75:74], pzw[56:54]);
\t\tr_ya[79: 76] <= ya(pbit[19], xy_d[77:76], xy_d[79:78], pzw[59:57]);
\t\tr_ya[83: 80] <= ya(pbit[20], xy_d[81:80], xy_d[83:82], pzw[62:60]);
\t\tr_ya[87: 84] <= ya(pbit[21], xy_d[85:84], xy_d[87:86], pzw[65:63]);
\t\tr_ya[91: 88] <= ya(pbit[22], xy_d[89:88], xy_d[91:90], pzw[68:66]);
\t\tr_ya[95: 92] <= ya(pbit[23], xy_d[93:92], xy_d[95:94], pzw[71:69]);
\tend
\tassign xas = r_xa;
\tassign yas = r_ya;
endmodule
|
module top;
reg passed;
reg signed[95:0] m_one, m_two, zero, one, two;
// Both argument positive.
reg signed[95:0] rem;
wire signed[95:0] wrem = two / one;
// First argument negative.
reg signed[95:0] rem1n;
wire signed[95:0] wrem1n = m_two / one;
// Second argument negative.
reg signed[95:0] rem2n;
wire signed[95:0] wrem2n = two / m_one;
// Both arguments negative.
reg signed[95:0] rembn;
wire signed[95:0] wrembn = m_two / m_one;
// Divide by zero.
reg signed[95:0] remd0;
wire signed[95:0] wremd0 = one / zero;
initial begin
passed = 1\'b1;
m_one = 96\'hffffffffffffffffffffffff;
m_two = 96\'hfffffffffffffffffffffffe;
zero = 96\'h000000000000000000000000;
one = 96\'h000000000000000000000001;
two = 96\'h000000000000000000000002;
#1;
// Both positive.
if (wrem !== 96\'h000000000000000000000002) begin
$display("Failed: CA divide, expected 96\'h00...02, got %h",
wrem);
passed = 1\'b0;
end
rem = two / one;
if (rem !== 96\'h000000000000000000000002) begin
$display("Failed: divide, expected 96\'h00...02, got %h",
rem);
passed = 1\'b0;
end
// First negative.
if (wrem1n !== 96\'hfffffffffffffffffffffffe) begin
$display("Failed: CA divide (1n), expected 96\'hff...fe, got %h",
wrem1n);
passed = 1\'b0;
end
rem1n = m_two / one;
if (rem1n !== 96\'hfffffffffffffffffffffffe) begin
$display("Failed: divide (1n), expected 96\'hff...fe, got %h",
rem1n);
passed = 1\'b0;
end
// Second negative.
if (wrem2n !== 96\'hfffffffffffffffffffffffe) begin
$display("Failed: CA divide (2n), expected 96\'hff...fe, got %h",
wrem2n);
passed = 1\'b0;
end
rem2n = two / m_one;
if (rem2n !== 96\'hfffffffffffffffffffffffe) begin
$display("Failed: divide (2n), expected 96\'hff...fe, got %h",
rem2n);
passed = 1\'b0;
end
// Both negative.
if (wrembn !== 96\'h000000000000000000000002) begin
$display("Failed: CA divide (bn), expected 96\'h00...02, got %h",
wrembn);
passed = 1\'b0;
end
rembn = m_two / m_one;
if (rembn !== 96\'h000000000000000000000002) begin
$display("Failed: divide (bn), expected 96\'h00...02, got %h",
rembn);
passed = 1\'b0;
end
// Divide by zero.
if (wremd0 !== 96\'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
$display("Failed: CA divide (d0), expected 96\'hxx...xx, got %h",
wremd0);
passed = 1\'b0;
end
remd0 = one / zero;
if (remd0 !== 96\'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
$display("Failed: divide (d0), expected 96\'hxx...xx, got %h",
remd0);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
/* Copyright (C) 2000 Stephen G. Tell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
// SDW - reworked a bit to account for the fact that it HAS to be
/* fopen1 - test $fopen system task */
module fopen1;
reg [31:0] fp;
reg error ;
initial begin
fp = $fopen("work/fopen1.out");
case(fp)
32\'h0000_0001: error = 1;
32\'h0000_0002: error = 0;
32\'h0000_0004: error = 1;
32\'h0000_0008: error = 1;
32\'h0000_0010: error = 1;
32\'h0000_0020: error = 1;
32\'h0000_0040: error = 1;
32\'h0000_0080: error = 1;
32\'h0000_0100: error = 1;
32\'h0000_0200: error = 1;
32\'h0000_0400: error = 1;
32\'h0000_0800: error = 1;
32\'h0000_1000: error = 1;
32\'h0000_2000: error = 1;
32\'h0000_4000: error = 1;
32\'h0000_8000: error = 1;
32\'h0001_0000: error = 1;
32\'h0002_0000: error = 1;
32\'h0004_0000: error = 1;
32\'h0008_0000: error = 1;
32\'h0010_0000: error = 1;
32\'h0020_0000: error = 1;
32\'h0040_0000: error = 1;
32\'h0080_0000: error = 1;
32\'h0100_0000: error = 1;
32\'h0200_0000: error = 1;
32\'h0400_0000: error = 1;
32\'h0800_0000: error = 1;
32\'h1000_0000: error = 1;
32\'h2000_0000: error = 1;
32\'h4000_0000: error = 1;
32\'h8000_0000: error = 1;
default: error = 1;\t\t// std_io!
endcase
$display("fp = %b",fp);
if(error == 0)
$display("PASSED");
else
$display("FAILED");
\t $fclose(fp);
$finish;
end
endmodule
|
// The IEEE standard allows the out-of-bounds part-selects to be flagged as
// compile-time errors. If they are not, this test should pass.
module top;
wire [3:0][3:0] array1;
wire [3:0][3:0] array2;
wire [3:0][3:0] array3;
wire [3:0][3:0] array4;
wire [3:0][3:0] array5;
wire [3:0][3:0] array6;
assign array1[-2+:2] = 8\'h00;
assign array1[ 0+:2] = 8\'h21;
assign array1[ 2+:2] = 8\'h43;
assign array1[ 4+:2] = 8\'h55;
assign array1[-1+:2] = 8\'h10;
assign array2[ 1+:2] = 8\'h32;
assign array2[ 3+:2] = 8\'h54;
assign array3[-1-:2] = 8\'h00;
assign array3[ 1-:2] = 8\'h21;
assign array3[ 3-:2] = 8\'h43;
assign array3[ 5-:2] = 8\'h55;
assign array4[ 0-:2] = 8\'h10;
assign array4[ 2-:2] = 8\'h32;
assign array4[ 4-:2] = 8\'h54;
assign array5[-1:-2] = 8\'h00;
assign array5[ 1:0 ] = 8\'h21;
assign array5[ 3:2 ] = 8\'h43;
assign array5[ 5:4 ] = 8\'h55;
assign array6[ 0:-1] = 8\'h10;
assign array6[ 2:1 ] = 8\'h32;
assign array6[ 4:3 ] = 8\'h54;
reg failed = 0;
initial begin
$display("%h", array1);
if (array1 !== 16\'h4321) failed = 1;
$display("%h", array2);
if (array2 !== 16\'h4321) failed = 1;
$display("%h", array3);
if (array3 !== 16\'h4321) failed = 1;
$display("%h", array4);
if (array4 !== 16\'h4321) failed = 1;
$display("%h", array5);
if (array5 !== 16\'h4321) failed = 1;
$display("%h", array6);
if (array6 !== 16\'h4321) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that it is possible to declare the data type for a packed array type
// task port separately from the direction for non-ANSI style port declarations.
module test;
typedef logic [7:0] T1;
typedef T1 [3:0] T2;
task t;
input x;
T2 x;
if (x[0] == 1 && x[1] == 2 && x[2] == 3 && x[3] == 4 &&
$bits(x) == $bits(T2)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial begin
static T2 val;
val[0] = 8\'h1;
val[1] = 8\'h2;
val[2] = 8\'h3;
val[3] = 8\'h4;
t(val);
end
endmodule
|
/*
* Author: Oswaldo Cadenas <[email protected]>
*/
module test;
parameter S = 9;
parameter K = 3;
parameter L = 2**(S-K);
parameter N = 2**(S-1);
reg signed [S-1:0] a_reg;
bit signed [S-1:0] a_bit;
byte signed a_byte;
shortint signed a_short;
int signed a_int;
longint signed a_long;
byte signed amount;
byte unsigned pos;
int temp;
int i;
initial begin
// test for style "a += some" statement on type reg
for (i = 0; i < N; i = i+1) begin
a_reg = $random % L;
amount = $random % K;
#1;
temp = a_reg + amount;
a_reg += amount;
#1;
//$display ("a = %0d, amount = %0d, temp = %0d", a, amount, temp);
if (temp !== a_reg) begin
$display("FAILED");
$finish;
end
#1;
temp = a_reg - amount;
a_reg -= amount;
#1;
if (temp !== a_reg) begin
$display("FAILED");
$finish;
end
end
// test for style "a += some" statement on type bit
for (i = 0; i < N; i = i+1) begin
a_bit = $random % L;
amount = $random % K;
#1;
temp = a_bit + amount;
a_bit += amount;
#1;
if (temp !== a_bit) begin
$display("FAILED");
$finish;
end
#1;
temp = a_bit - amount;
a_bit -= amount;
#1;
if (temp !== a_bit) begin
$display("FAILED");
$finish;
end
end // for
// test for style "a += some" statement on type byte
for (i = 0; i < N; i = i+1) begin
a_byte = $random % L;
amount = $random % K;
#1;
temp = a_byte + amount;
a_byte += amount;
#1;
if (temp !== a_byte) begin
$display("FAILED");
$finish;
end
#1;
temp = a_byte - amount;
a_byte -= amount;
#1;
if (temp !== a_byte) begin
$display("FAILED");
$finish;
end
end // for
// test for style "a += some" statement on type shortint
for (i = 0; i < N; i = i+1) begin
a_short = 2*($random % L);
amount = 2*($random % K);
#1;
temp = a_short + amount;
a_short += amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short - amount;
a_short -= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short * amount;
a_short *= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short / amount;
a_short /= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short % amount;
a_short %= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short & amount;
a_short &= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short | amount;
a_short |= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short ^ amount;
a_short ^= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
pos = 2*({$random} % K);
temp = a_short << pos;
a_short <<= pos;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short >> pos;
a_short >>= pos;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short <<< pos;
a_short <<<= pos;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short >>> pos;
a_short >>>= pos;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
end // for
// test for style "a += some" statement on type int
for (i = 0; i < N; i = i+1) begin
a_int = 4*($random % L);
amount = 4*($random % K);
#1;
temp = a_int + amount;
a_int += amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int - amount;
a_int -= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int * amount;
a_int *= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int / amount;
a_int /= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int % amount;
a_int %= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int & amount;
a_int &= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int | amount;
a_int |= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int ^ amount;
a_int ^= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
pos = 4*({$random} % K);
temp = a_int << pos;
a_int <<= pos;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int >> pos;
a_int >>= pos;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int <<< pos;
a_int <<<= pos;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int >>> pos;
a_int >>= pos;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
end // for
// test for style "a += some" statement on type longint
for (i = 0; i < N; i = i+1) begin
a_long = 8*($random % L);
amount = 8*($random % K);
#1;
temp = a_long + amount;
a_long += amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long - amount;
a_long -= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long * amount;
a_long *= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long / amount;
a_long /= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long % amount;
a_long %= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long & amount;
a_long &= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long | amount;
a_long |= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long ^ amount;
a_long ^= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
pos = 8*({$random} % K);
temp = a_long << pos;
a_long <<= pos;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long >> pos;
a_long >>= pos;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long <<< pos;
a_long <<<= pos;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long >>> pos;
a_long >>= pos;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
end // for
$display("PASSED");
$finish;
end
endmodule
|
// Check that it is possible to copy an empty dynamic array.
module test;
initial begin
int d1[];
int d2[];
d1 = \'{1, 2, 3};
d1 = d2;
if (d1.size() == 0 && d2.size() == 0) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
// pr2013758
module test;
reg reset;
initial begin
// $dumpfile( "test.vcd" );
// $dumpvars;
reset = 0;
#100;
reset = 1;
#100;
reset = 0;
#100 $display("PASSED");
$finish;
end
submod1 s1 (.reset(reset));
submod2 s2 (.reset(reset));
endmodule
module submod1(input reset);
wire reset2 = 1;
assign reset2 = reset;
endmodule
module submod2(input reset);
always #10 @(reset)
if (reset === 1\'bx) begin
\t$display("FAILED -- X escaped into sibling module!");
\t$finish;
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always casez ( reg_value) case_item1; case_item2; case_item3; endcase
// D:
module main ;
reg [3:0] value1,value2,value3;
initial
\tbegin
#0;
// $dumpfile("test.vcd");
// $dumpvars(0,main);
value3 = 0;
#3 ;\t\t\t\t\t// t=3
value1 = 4\'b0000 ;\t// Picked up at time 4
#5 ;\t\t\t\t // check at time 8
$display("check == 0000:at time=%t value2=%h",$time,value2);
if(value2 != 4\'b0)
begin
$display("FAILED - always3.1.6C - casez 0 at %t",$time);
value3 = 1;
end
#1 ;\t\t\t\t\t// Picked up at time 10
value1 = 4\'b00z1 ;\t// Set at time 9.
#5 ;\t\t\t\t\t// Check at time 14
$display("check == 0001:at time=%t value2=%h",$time,value2);
if(value2 != 4\'b0001)
begin
$display("FAILED - always3.1.6C - casez z1 at %t",$time);
value3 = 1;
end
#1;\t\t\t\t\t// Picked up at time 16
value1 = 4\'b0100;\t// Changed at time 15.
#5;\t\t\t\t\t// Check at time 20...
$display("check == 0010:at time=%t value2=%h",$time,value2);
if(value2 != 4\'b0010)
begin
$display("FAILED - always3.1.6C - casez 4 at %t",$time);
value3 = 1;
end
#10;
if(value3 == 0)
$display("PASSED");
\t $finish;
end
always
begin
$display("Entering case at time=%t value1=%b",$time,value1);
casez (value1)
4\'b0000: begin
#3 ;
value2 = 4\'b0000 ;
$display("case0000: at time=%t",$time);
#3 ;
end
4\'b00z1: begin
#3 ;
value2 = 4\'b0001 ;
$display("case00z1: at time=%t",$time);
#3 ;
end
4\'b0100: begin
#3 ;
value2 = 4\'b0010 ;
$display("case100: at time=%t",$time);
#3 ;
end
default:
begin
#2 ;
$display("default: %t",$time);
end
endcase
$display("Leaving case at time=%t",$time);
end
endmodule
|
/*
* Copyright (c) 2002 Tom Verbeure
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
\tinteger myInt;
\treg [39:0] myReg40;
\treg [0:39] myReg40r;
\treg [0:38] myReg39r;
\treg [13:0] myReg14;
\treg [7:0] myReg8;
\tinitial begin
\t\t$display("============================ myReg8 = 65");
\t\tmyReg8 = 65;
\t\t$display(">|A|");
\t\t$display("*|%s|", myReg8);
\t\t$display("============================ myReg40 = \\"12345\\"");
\t\tmyReg40 = "12345";
\t\t$display(">|12345|");
\t\t$display("*|%s|", myReg40);
\t\t$display(">|5|");
\t\t$display("*|%s|", myReg40[7:0]);
\t\t$display("============================ myReg40r = \\"12345\\"");
\t\tmyReg40r = "12345";
\t\t$display(">|12345|");
\t\t$display("*|%s|", myReg40r);
\t\t$display(">|1|");
\t\t$display("*|%s|", myReg40r[0:7]);
\t\t$display("============================ myReg39r = \\"12345\\"");
\t\tmyReg39r = "12345";
\t\t$display(">|12345|");
\t\t$display("*|%s|", myReg39r);
\t\t$display(">|b|");
\t\t$display("*|%s|", myReg39r[0:7]);
\t\t$display("============================ myReg14 = 65");
\t\tmyReg14 = 65;
\t\t$display(">| A|");
\t\t$display("*|%s|", myReg14);
\t\t$display("============================ myReg14 = 33*356+65");
\t\tmyReg14 = 33*256 + 65;
\t\t$display(">|!A|");
\t\t$display("*|%s|", myReg14);
\t\t$display("============================ myInt = 65");
\t\tmyInt = 65;
\t\t$display(">| A|");
\t\t$display("*|%s|", myInt);
\tend
endmodule
|
// This is the first part of a two-part test that checks that the argument to
// a $signed or $unsigned function is treated as a self-determined expression.
// This part performs tests where the argument is unsigned.
module pr2922063a;
reg [3:0] op1;
reg [2:0] op2;
reg [7:0] result;
reg fail;
task check_result;
input [7:0] value;
begin
$write("Expected %b, got %b", value, result);
if (result !== value) begin
$write(" *");
fail = 1;
end
$write("\
");
end
endtask
initial begin
fail = 0;
$display("-- Addition tests --");
op1 = 4\'b1111; op2 = 3\'b111;
result = 8\'sd0 + $signed(op1 + op2);
check_result(8\'b00000110);
result = 8\'sd0 + $unsigned(op1 + op2);
check_result(8\'b00000110);
op1 = 4\'b1000; op2 = 3\'b011;
result = 8\'sd0 + $signed(op1 + op2);
check_result(8\'b11111011);
result = 8\'sd0 + $unsigned(op1 + op2);
check_result(8\'b00001011);
$display("-- Multiply tests --");
op1 = 4\'b0101; op2 = 3\'b100;
result = 8\'sd0 + $signed(op1 * op2);
check_result(8\'b00000100);
result = 8\'sd0 + $unsigned(op1 * op2);
check_result(8\'b00000100);
op1 = 4\'b0010; op2 = 3\'b100;
result = 8\'sd0 + $signed(op1 * op2);
check_result(8\'b11111000);
result = 8\'sd0 + $unsigned(op1 * op2);
check_result(8\'b00001000);
$display("-- Left ASR tests --");
op1 = 4\'b1010;
result = 8\'sd0 + $signed(op1 <<< 1);
check_result(8\'b00000100);
result = 8\'sd0 + $unsigned(op1 <<< 1);
check_result(8\'b00000100);
op1 = 4\'b0101;
result = 8\'sd0 + $signed(op1 <<< 1);
check_result(8\'b11111010);
result = 8\'sd0 + $unsigned(op1 <<< 1);
check_result(8\'b00001010);
$display("-- Right ASR tests --");
op1 = 4\'b1010;
result = 8\'sd0 + $signed(op1 >>> 1);
check_result(8\'b00000101);
result = 8\'sd0 + $unsigned(op1 >>> 1);
check_result(8\'b00000101);
op1 = 4\'b1010;
result = 8\'sd0 + $signed(op1 >>> 0);
check_result(8\'b11111010);
result = 8\'sd0 + $unsigned(op1 >>> 0);
check_result(8\'b00001010);
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
nature Voltage;
units = "V";
access = V;
idt_nature = Flux;
abstol = 1e-6;
endnature
discipline voltage;
potential Voltage;
enddiscipline
nature Flux;
units = "Wb";
access = Phi;
ddt_nature = Voltage;
abstol = 1e-9;
endnature
`timescale 1s/1s
module main;
real value;
voltage in, out;
analog V(out) <+ transition(value, 0, 4);
initial begin
value = 0.0;
#10 if (V(out) != value) begin
\t $display("FAILED -- value=%g, res=%g", value, V(out));
\t $finish;
end
// Halfway through the rise time, the output should have
// half the input.
value = 2.0;
//#2 if (V(out) != value/2) begin
#2 if (abs(V(out) - value/2) > 1e-6) begin
\t $display("FAILED -- value=%g, value/2=%g, res=%f", value, value/2, V(out));
\t $finish;
end
// After the full transition time, the output should match
// the input.
#2 if (V(out) != value) begin
\t $display("FAILED -- value=%g, res=%f", value, V(out));
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Regression test for GitHub issue 18 : Icarus does undef propagation of
// const multiplies incorrectly.
module bug();
wire [3:0] y = 4\'b0 * 4\'bx;
initial begin
#0 $display("%b", y);
if (y === 4\'bxxxx)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
package ivl_uvm_pkg;
virtual class uvm_test;
task ok;
$display("PASSED");
endtask
endclass : uvm_test
endpackage : ivl_uvm_pkg
package test_pkg;
import ivl_uvm_pkg::*;
class sanity_test extends uvm_test;
endclass : sanity_test
endpackage : test_pkg
module m;
import test_pkg::*;
sanity_test obj;
initial begin
obj = new;
obj.ok;
end
endmodule : m
|
module top;
reg [79:0] str;
integer val;
initial begin
str = "5";
$sscanf(str, "%d", val);
if (val == 5) $display("PASSED");
else $display("Failed to convert string, got %d", val);
end
endmodule
|
module top;
reg pass;
reg [7:0] vec;
integer off;
time delay;
event trig;
initial begin
pass = 1\'b1;
delay = 1;
// Assign before the vector (constant delay).
vec = 8\'hff;
off = -1;
vec[off] <= #1 1\'b0;
#2 if (vec !== 8\'hff) begin
$display("Failed the before vector (C) test, expected 8\'hff, got %h",
vec);
pass = 1\'b0;
end
// Assign after the vector (constant delay).
vec = 8\'hff;
off = 8;
vec[off] <= #1 1\'b0;
#2 if (vec !== 8\'hff) begin
$display("Failed the after vector (C) test, expected 8\'hff, got %h",
vec);
pass = 1\'b0;
end
// Assign before the vector (variable delay).
vec = 8\'hff;
off = -1;
vec[off] <= #(delay) 1\'b0;
#2 if (vec !== 8\'hff) begin
$display("Failed the before vector (V) test, expected 8\'hff, got %h",
vec);
pass = 1\'b0;
end
// Assign after the vector (variable delay).
vec = 8\'hff;
off = 8;
vec[off] <= #(delay) 1\'b0;
#2 if (vec !== 8\'hff) begin
$display("Failed the after vector (V) test, expected 8\'hff, got %h",
vec);
pass = 1\'b0;
end
// Assign before the vector (event trigger).
vec = 8\'hff;
off = -1;
vec[off] <= @(trig) 1\'b0;
->trig;
#1 if (vec !== 8\'hff) begin
$display("Failed the before vector (E) test, expected 8\'hff, got %h",
vec);
pass = 1\'b0;
end
// Assign after the vector (event trigger).
vec = 8\'hff;
off = 8;
vec[off] <= @(trig) 1\'b0;
->trig;
#1 if (vec !== 8\'hff) begin
$display("Failed the after vector (V) test, expected 8\'hff, got %h",
vec);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Check that declaring an integer typed net for a signal that was previously
// declared as a non-ANSI module port is an error. Even if the types for both
// declarations are the same.
module test(x);
input integer x;
wire integer x;
endmodule
|
module top;
reg pass;
reg [3:0] array [1:8];
reg signed [2:0] a;
reg signed [127:0] b;
reg [4*8:1] res;
initial begin
array [7] = 4\'b1001;
pass = 1\'b1;
/* If this fails it is likely because the index width is less
* than an integer width. */
a = -1;
$sformat(res, "%b", array[a]);
if (res !== "xxxx") begin
$display("Failed: &A<> negative, expected 4\'bxxxx, got %s.", res);
pass = 1\'b0;
end
b = 7;
b[120] = 1\'b1; // This should be stripped!
$sformat(res, "%b", array[b]);
if (res !== "1001") begin
$display("Failed: &A<> large, expected 4\'b1001, got %s.", res);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate 3.1.2E always reg_lvalue <= # (mintypmax_expression) constant ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
begin
# 3; /* Wait till here to verify didn\'t see 2ns delay! */
if(value1 !== 4\'hx)
\t$display("FAILED - always reg_lvalue <= # (mintypmax_expression) constant \
");
#12 ;
if(value1 != 4\'h5)
\t$display("FAILED - always reg_lvalue <= # (mintypmax_expression) constant \
");
else
begin
$display("PASSED\
");
$finish ;
end
end
always value1 <= # (2:10:17) 4\'h5 ;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate defparam
module module_a (out0,in0);
input\t\tin0;
output [5:0]\tout0;
parameter [5:0] ident0 = 0;
parameter [5:0] ident1 = 5\'h11;
reg [5:0] out0;
// Basic MUX switches on in0
always @ (in0)
begin
if(in0)
out0 = ident0;
else
out0 = ident1;
end
endmodule // module_a
module module_b (out0,out1,in0,in1);
input\t\tin0;
input\t\tin1;
output [5:0]\tout0;
output [5:0]\tout1;
module_a testmodA (.out0(out0),.in0(in0));
module_a testmodB (.out0(out1),.in0(in1));
endmodule // module_b
module main ();
reg in0,in1;
reg\t error;
wire [5:0] out0,out1;
defparam NameB.testmodA.ident0 = 5\'h4;
defparam NameB.testmodB.ident0 = 5\'h5;
defparam NameB.testmodB.ident1 = 5\'h6;
module_b NameB (.out0(out0),.out1(out1),
.in0(in0),.in1(in1));
initial
begin
error = 0;
#1 ;
in0 = 0;
#1 ;
if(out0 != 5\'h11)
begin
$display("FAILED - defparam3.5A - Defparam testmodA.ident0");
$display("out0 = %h",out0);
error = 1;
end
#1 ;
in0 = 1;
#1 ;
if(out0 != 5\'h4)
begin
$display("FAILED - defparam3.5A - Defparam testmodA.ident0");
error = 1;
end
#1;
in1 = 0;
#1;
if(out0 != 5\'h4)\t// Validate the 0 side didn\'t change!
begin
$display("FAILED - defparam3.5A - Defparam testmodA.ident0");
error = 1;
end
if(out1 != 5\'h6)
begin
$display("FAILED - defparam3.5A - Defparam testmodB.ident1");
error = 1;
end
#1;
in1 = 1;
#1;
if(out1 != 5\'h5)
begin
$display("FAILED - defparam3.5A - Defparam testmodB.ident0");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
//
// Copyright (c) 1999 Thomas Coonan ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// **** Here\'s a simple, sequential multiplier. Very simple, unsigned..
// Not very well tested, play with testbench, use at your own risk, blah blah blah..
//
//
// Unsigned 16-bit multiply (multiply two 16-bit inputs to get a 32-bit output)
//
// Present data and assert start synchronous with clk.
// Assert start for ONLY one cycle.
// Wait N cycles for answer (at most). Answer will remain stable until next start.
// You may use DONE signal as handshake.
//
// Written by tom coonan
//
module mult16 (clk, resetb, start, done, ain, bin, yout);
parameter N = 16;
input\t\t\tclk;
input\t\t\tresetb;
input\t\t\tstart; // Register the ain and bin inputs (they can change afterwards)
//input [N-1:0]\t\tain;
//input [N-1:0]\t\tbin;
//output [2*N-1:0]\tyout;
input [15:0]\t\tain;
input [15:0]\t\tbin;
output [31:0]\tyout;
output\t\t\tdone;
//reg [2*N-1:0]\t\ta;
//reg [N-1:0]\t\tb;
//reg [2*N-1:0]\t\tyout;
reg [31:0]\t\ta;
reg [15:0]\t\tb;
reg [31:0]\t\tyout;
reg\t\tdone;
always @(posedge clk or negedge resetb) begin
if (~resetb) begin
a <= 0;
b <= 0;
yout <= 0;
done <= 1\'b1;
end
else begin
// Load will register the input and clear the counter.
if (start) begin
a <= ain;
b <= bin;
yout <= 0;
done <= 0;
end
else begin
// Go until b is zero
if (~done) begin
if (b != 0) begin
// If \'1\' then add a to sum
if (b[0]) begin
yout <= yout + a;
end
b <= b >> 1;
a <= a << 1;
$display ("a = %h, b = %h, yout = %h", a,b,yout);
end
else begin
done <= 1\'b1;
end
end
end
end
end
endmodule
module mul16;
reg clk, resetb, start;
reg [15:0] a;
reg [15:0] b;
wire [31:0] y;
wire done;
mult16 mult16inst (clk, resetb, start, done, a, b, y);
initial begin
clk = 0;
forever begin
#10 clk = ~clk;
end
end
initial begin
resetb = 0;
#30 resetb = 1;
end
integer num_errors;
parameter MAX_TRIALS = 10;
initial begin
// $dumpfile ("multdiv.vcd");
// $dumpvars (0,a);
// $dumpvars (0,b);
// $dumpvars (0,y);
// $dumpvars (0,resetb);
// $dumpvars (0,done);
num_errors = 0;
#100;
// Do a bunch of random multiplies
repeat (MAX_TRIALS) begin
test_multiply ($random, $random);
end
// Special cases
test_multiply ($random, 1);
test_multiply (1, $random);
test_multiply ($random, 0);
test_multiply (0, $random);
$display ("Done. %0d Errors", num_errors);
if(num_errors == 0)
$display("PASSED");
#800;
$finish;
end
task test_multiply;
input [15:0] aarg;
input [15:0] barg;
integer expected_answer;
begin
if (~done) begin
$display ("Multiplier is Busy!!");
end
else begin
@(negedge clk);
start = 1;
a = aarg;
b = barg;
@(negedge clk) start = 0;
@(posedge done);
expected_answer = a*b;
$display ("%0d * %0d = %0h, Reality = %0h", a, b, y, expected_answer);
if (y !== expected_answer) begin
$display (" FAILED!");
num_errors = num_errors + 1;
end
end
end
endtask
endmodule
|
// Check that declaring an integer typed non-ANSI task port for signal that was
// previously declared as a variable is an error. Even if the types for both
// declarations are the same.
module test;
task t;
integer x;
input integer x;
$display("FAILED");
endtask
integer y;
initial t(y);
endmodule
|
module top;
integer res, idx;
wire [24*8-1:0] wval;
wire [24*8-1:0] warr [0:1];
reg [24*8-1:0] rval;
initial begin
idx = 0;
// res = $sscanf(); // A function must have at least one argument!
res = $sscanf("A string");
res = $sscanf(wval);
res = $sscanf("A string", wval);
res = $sscanf("A string", "%s", top);
res = $sscanf("A string", "%s", wval);
res = $sscanf("A string", "%s %s", rval, warr[0]);
// This is an invalid fd, but it passes the compiletf routine checks.
// It would get caught by the run time if the compiletf routines did
// not fail.
res = $fscanf(1);
res = $fscanf("A string");
res = $fscanf(1, wval);
res = $fscanf(1, "%s", top);
res = $fscanf(1, "%s", wval);
res = $fscanf(1, "%s %s", rval, warr[0]);
end
endmodule
|
// Check that an array type identifier used for a module port is elaborated in
// the correct scope.
localparam A = 2;
localparam B = 4;
typedef logic [A-1:0] T[B];
module test (
input T x
);
localparam A = 5;
localparam B = 10;
bit failed = 1\'b0;
`define check(expr, val) \\
if (expr !== val) begin \\
$display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \\
failed = 1\'b1; \\
end
initial begin
`check($size(x, 1), 4);
`check($size(x, 2), 2);
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue = @ event_identifier constant
// D: There is a dependency here between this and event keyword and ->
module main ;
reg [3:0] value1 ;
event event_ident ;
initial
begin
# 5 -> event_ident ;
end
initial
begin
if(value1 !== 4\'bxxxx)
\t$display("FAILED - always reg_lvalue = @ event_identifier constant\
");
#10 ;
if(value1 != 4\'h5)
\t$display("FAILED - always reg_lvalue = @ event_identifier constant\
");
else
begin
$display("PASSED\
");
$finish ;
end
end
always value1 = @ event_ident 4\'h5;
endmodule
|
/*
* This program tests the synthesis of small memories, including
* aysnchronous read w/ synchronous write.
*/
module main;
reg [3:0] mem [1:0], D;
reg\t rst, clk, wr, wadr, radr;
/*
* This implements the synchronous write port to the memory.
*/
(* ivl_synthesis_on *)
always @(posedge clk)
if (rst) begin
\tmem[0] <= 0;
\tmem[1] <= 0;
end else if (wr) begin
\tmem[wadr] <= D;
end
/* This is the asynchronous read port from the memory. */
wire [3:0] Q = mem[radr];
(* ivl_synthesis_off *)
initial begin
rst = 0;
clk = 0;
wadr = 0;
radr = 0;
wr = 0;
#1 clk = 1;
#1 clk = 0;
// Make sure reset works.
rst = 1;
#1 clk = 1;
#1 clk = 0;
#1 if (mem[0] !== 0 || mem[1] !== 0) begin
\t $display("FAILED -- Reset 1: mem[0]=%b, mem[1]=%b", mem[0], mem[1]);
\t $finish;
end
radr = 0;
#1 if (Q !== mem[radr]) begin
\t $display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q);
\t $finish;
end
radr = 1;
#1 if (Q !== mem[radr]) begin
\t $display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q);
\t $finish;
end
rst = 0;
#1 clk = 1;
#1 clk = 0;
// Make sure memory remembers value.
if (mem[0] !== 0 || mem[1] !== 0) begin
\t $display("FAILED -- Reset 2: mem[0]=%b, mem[1]=%b", mem[0], mem[1]);
\t $finish;
end
D = 7;
wr = 1;
#1 clk = 1;
#1 clk = 0;
// Make sure write works.
if (mem[0] !== 7 || mem[1] !== 0) begin
\t $display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b",
\t\t D, mem[0], mem[1]);
\t $finish;
end
D = 2;
wadr = 1;
#1 clk = 1;
#1 clk = 0;
// Make sure write works.
if (mem[0] !== 7 || mem[1] !== 2) begin
\t $display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b",
\t\t D, mem[0], mem[1]);
\t $finish;
end
radr = 0;
#1 if (Q !== mem[radr]) begin
\t $display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q);
\t $finish;
end
wr = 0;
D = 5;
// Make sure memory remembers written values.
if (mem[0] !== 7 || mem[1] !== 2) begin
\t $display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b",
\t\t D, mem[0], mem[1]);
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
// Check that it is not possible to perform non-blocking assignments to a class
// object variable with automatic lifetime.
module test;
class C;
endclass
task automatic auto_task;
C c1, c2;
c1 <= c2;
$display("FAILED");
endtask
initial begin
auto_task;
end
endmodule
|
module test;
reg a,b;
integer x;
initial begin
x=10;
// ok
a=x;
// fails at run time with
// vvm_func.cc:49: failed assertion `v.nbits == p.nbits\'
// Abort (core dumped)
b = ~x;
if (b === 1\'b1)
\t$display("PASSED");
else
\t$display("FAILED --- b = %b", b);
end // initial begin
endmodule // test
/*
* Copyright (c) 2000 Gerard A. Allan ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests the use of memories within tasks.
*/
module test;
parameter addrsiz = 14;
parameter ramsiz = 1 << addrsiz;
task loadram;
integer i, j;
reg [15:0] memword;
reg [15:0] tempram[0:(2*ramsiz)-1];
begin
\t for (i = 0; i < 16; i = i + 2)
\t tempram[i] = i;
\t for (i = 0; i < 16; i = i + 2)
\t if (tempram[i] !== i) begin
\t $display("FAILED -- %m.tempram[%d] = %b", i, tempram[i]);
\t $finish;
\t end
\t $display("PASSED");
end
endtask // loadram
initial loadram;
endmodule
|
module pr3499807();
supply0 gnd;
wire net1;
wire net2;
tranif0 #(100) sw1(gnd, net1, gnd);
tranif0 #(200) sw2(gnd, net2, gnd);
initial begin
$monitor($time,, gnd,, net1,, net2);
#300;
$finish(0);
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
/*
* This source file demonstrates how to synthesize CLB flip-flops from
* Icarus Verilog, including giving the device an initial value.
*
* To compile this for XNF, try a command like this:
*
* iverilog -txnf -ppart=XC4010XLPQ160 -pncf=clbff.ncf -oclbff.xnf clbff.v
*
* That command causes an clbff.xnf and clbff.ncf file to be created.
* Next, make the clbff.ngd file with the command:
*
* xnf2ngd -l xilinxun -u clbff.xnf clbff.ngo
* ngdbuild clbff.ngo clbff.ngd
*
* Finally, map the file to fully render it in the target part. The
* par command is the step that actually optimizes the design and tries
* to meet timing constraints.
*
* map -o map.ncd clbff.ngd
* par -w map.ncd clbff.ncd
*
* At this point, you can use the FPGA Editor to edit the clbff.ncd
* file. Notice that the design uses two CLB flip-flops (possibly in
* the same CLB) with their outputs ANDed together. If you go into the
* block editor, you will see that the FF connected to main/Q<0> is
* configured so start up reset, and the FF connected to main/Q<1> is
* configured to start up set.
*/
module main;
wire clk, iclk;
wire i0, i1;
wire out;
wire [1:0] D = {i1, i0};
// This statement declares Q to be a 2 bit reg vector. The
// initial assignment will cause the synthesized device to take
// on an initial value specified here. Without the assignment,
// the initial value is unspecified. (Verilog simulates it as 2\'bx.)
reg [1:0] Q = 2\'b10;
// This simple logic gate get turned into a function unit.
// The par program will map this into a CLB F or G unit.
and (out, Q[0], Q[1]);
// This creates a global clock buffer. Notice how I attach an
// attribute to the named gate to force it to be mapped to the
// desired XNF device. This device will not be pulled into the
// IOB associated with iclk because of the attribute.
buf gbuf(clk, iclk);
$attribute(gbuf, "XNF-LCA", "GCLK:O,I");
// This is mapped to a DFF. Since Q and D are two bits wide, the
// code generator actually makes two DFF devices that share a
// clock input.
always @(posedge clk) Q <= D;
// These attribute commands assign pins to the listed wires.
// This can be done to wires and registers, as internally both
// are treated as named signals.
$attribute(out, "PAD", "o150");
$attribute(i0, "PAD", "i152");
$attribute(i1, "PAD", "i153");
$attribute(iclk,"PAD", "i154");
endmodule /* main */
|
module test;
parameter j=0;
reg [3:0] in [7:0];
wire [3:0] out [7:0];
assign out[(j+1)*4 - 1 : j*4] = in[j];
// assign out[j] = in[j]; // This is what was probably wanted.
initial $display("out[0]: %b", out[0]);
endmodule
|
// Check that recursive functions are supported when the `return` statement is
// used.
module recursive_func();
function automatic [15:0] factorial(input [15:0] n);
if (n > 1) begin : recursion
reg [15:0] result;
result = factorial(n - 1) * n;
return result;
end
return n;
endfunction
reg [15:0] r1;
reg [15:0] r2;
reg [15:0] r3;
initial begin
fork
r1 = factorial(3);
r2 = factorial(4);
r3 = factorial(5);
join
$display("factorial 3 = %0d", r1);
$display("factorial 4 = %0d", r2);
$display("factorial 5 = %0d", r3);
end
wire [15:0] r4;
wire [15:0] r5;
wire [15:0] r6;
assign r4 = factorial(6);
assign r5 = factorial(7);
assign r6 = factorial(8);
initial begin
#1;
$display("factorial 6 = %0d", r4);
$display("factorial 7 = %0d", r5);
$display("factorial 8 = %0d", r6);
end
endmodule
|
// This should generate an error reporting the undef_func, but not segfault.
module test1;
function [31:0] func1 (input [31:0] x);
return undef_func(x);
endfunction : func1
localparam X = func1(1);
endmodule : test1
|
/* PR1637208 */
module main;
reg clock;
reg [31:0] pixel0;
reg [31:0] mem [0:1];
always @(posedge clock) begin
mem[0] <= pixel0;
end
always @(posedge clock) begin
mem[1] <= mem[0];
end
reg sel;
wire [31:0] foo = sel? mem[1] : mem[0];
initial begin
clock = 1;
sel = 0;
#1 pixel0 = \'h55555555;
#1 clock = 0;
#1 clock = 1;
#1 pixel0 = \'haaaaaaaa;
#1 clock = 0;
#1 clock = 1;
#1 if (mem[0] !== 32\'haaaaaaaa) begin
\t $display("FAILED -- mem[0] = %h", mem[0]);
\t $finish;
end
if (mem[1] !== 32\'h55555555) begin
\t $display("FAILED == mem[1] = %h", mem[1]);
\t $finish;
end
if (foo !== mem[0]) begin
\t $display("FAILED -- mem[sel=0] != %h", foo);
\t $finish;
end
sel = 1;
#1 if (foo !== mem[1]) begin
\t $display("FAILED -- mem[sel=1] != %h", foo);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
//
// Copyright (c) 2000 Steve Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// force3.17A - Template 1 - force reg_lvalue = constant.
//
module test ;
reg [3:0] val1;
reg [3:0] val2;
initial
begin
val2 = 0;
#50 ;
if(val2 !== 4\'b1010)
$display("FAILED");
else
$display("PASSED");
end
initial
begin
#20;
force val2 = 4\'b1010;
end
endmodule
|
// Check that the signedness of methods on user defined classes is handled
// correctly when passing the result to a system function.
module test;
class C;
function shortint s;
return -1;
endfunction
function bit [15:0] u;
return -1;
endfunction
endclass
C c;
string s;
initial begin
c = new;
s = $sformatf("%0d %0d", c.s(), c.u());
if (s == "-1 65535") begin
$display("PASSED");
end else begin
$display("FAILED s=%s", s);
end
end
endmodule
|
module test(output reg Q, input wire D, input wire OE);
always @* begin
Q = 0;
if (OE)
\tQ = D;
end
endmodule // test
module main;
reg D, OE;
wire Q;
test dut(Q, D, OE);
(* ivl_synthesis_off *) initial begin
OE = 0;
D = 0;
#1 if (Q !== 0) begin
\t $display("FAILED -- Q=%b, D=%b, OE=%b", Q, D, OE);
\t $finish;
end
D = 1;
#1 if (Q !== 0) begin
\t $display("FAILED -- Q=%b, D=%b, OE=%b", Q, D, OE);
\t $finish;
end
OE = 1;
#1 if (Q !== 1) begin
\t $display("FAILED -- Q=%b, D=%b, OE=%b", Q, D, OE);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program is designed to test non-constant bit selects in the
* concatenated l-value of procedural assignment.
*/
module main;
reg [3:0] vec;
reg\t a;
integer i;
initial begin
vec = 4\'b0000;
a = 0;
if (vec !== 4\'b0000) begin
\t $display("FAILED -- initialized vec to %b", vec);
\t $finish;
end
for (i = 0 ; i < 4 ; i = i + 1) begin
\t { a, vec[i] } = i;
end
if (vec !== 4\'b1010) begin
\t $display("FAILED == vec (%b) is not 1010", vec);
\t $finish;
end
if (a !== 1\'b1) begin
\t $display("FAILED -- a (%b) is not 1", a);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module test();
wire [7:0] value1;
reg [7:0] value2;
reg clk;
assign value1[3:0] = 4\'b1010;
always @(posedge clk) begin
value2 <= value1;
end
(* ivl_synthesis_off *)
initial begin
#1 clk = 0;
#1 clk = 1;
#1 clk = 0;
$display("%b %b", value1, value2);
if (value2 === 8\'bzzzz1010)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
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