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// Module to test the messages for out of bound R-value part selects.
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg big_param;
reg [1:0] part;
integer idx;
parameter pvar0 = 0;
parameter pvar1 = 1;
parameter pvar2 = -1;
parameter pvar3 = 4\'b0001;
parameter [4:1] pvar4 = 4\'b0001;
parameter [1:4] pvar5 = 4\'b0001;
reg [4:1] rvar = 4\'b1000;
reg [1:4] rvar2 = 4\'b1000;
reg [4:1] ravar [2:1];
reg [1:4] ravar2 [2:1];
wire [4:1] wvar = 4\'b1010;
wire [1:4] wvar2 = 4\'b1010;
wire [4:1] wavar [2:1];
wire [1:4] wavar2 [2:1];
assign wavar[1] = 4\'b0111;
assign wavar[2] = 4\'b1110;
assign wavar2[1] = 4\'b0111;
assign wavar2[2] = 4\'b1110;
initial begin
pass = 1\'b1;
ravar[1] = 4\'b0111;
ravar[2] = 4\'b1110;
ravar2[1] = 4\'b0111;
ravar2[2] = 4\'b1110;
#1;
// Icarus supports an unlimited size for unsized parameters. The
// following checks the 33rd bit to see if it is 1\'bx. If so we
// assume that the simulator only support 32 bit, otherwise we
// modify our after check for unsized parameters to work (pass)
// with a larger constant.
big_param = 1\'b1;
idx = 32;
if (pvar0[idx] === 1\'bx) big_param = 1\'b0;
// Check a parameter with default size equal to 0.
part = pvar0[31:30]; // At end
if (part !== 2\'b00) begin
$display("Failed at end part select of a parameter (0), got %b", part);
pass = 1\'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = pvar0[33:32]; // May be after all
if (part !== (big_param ? 2\'b00: 2\'bxx)) begin
$display("Failed after part select of a parameter (0), got %b", part);
pass = 1\'b0;
end
part = pvar0[32:31]; // May be partial after
if (part !== (big_param ? 2\'b00 : 2\'bx0)) begin
$display("Failed partial after part select of a parameter (0), got %b",
part);
pass = 1\'b0;
end
part = pvar0[-1:-2]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a parameter (0), got %b", part);
pass = 1\'b0;
end
part = pvar0[0:-1]; // Partial before
if (part !== 2\'b0x) begin
$display("Failed partial before part select of a parameter (0), got %b",
part);
pass = 1\'b0;
end
part = pvar0[1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a parameter (0), got %b",
part);
pass = 1\'b0;
end
part = pvar0[1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a parameter (0), got %b",
part);
pass = 1\'b0;
end
part = pvar0[1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a parameter (0), got %b",
part);
pass = 1\'b0;
end
part = pvar0[1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a parameter (0), got %b",
part);
pass = 1\'b0;
end
`endif
// Check a parameter with default size equal to 1.
part = pvar1[31:30]; // At end
if (part !== 2\'b00) begin
$display("Failed at end part select of a parameter (1), got %b", part);
pass = 1\'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = pvar1[33:32]; // May be after all
if (part !== (big_param ? 2\'b00: 2\'bxx)) begin
$display("Failed after part select of a parameter (1), got %b", part);
pass = 1\'b0;
end
part = pvar1[32:31]; // May be partial after
if (part !== (big_param ? 2\'b00 : 2\'bx0)) begin
$display("Failed partial after part select of a parameter (1), got %b",
part);
pass = 1\'b0;
end
part = pvar1[-1:-2]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a parameter (1), got %b", part);
pass = 1\'b0;
end
part = pvar1[0:-1]; // Partial before
if (part !== 2\'b1x) begin
$display("Failed partial before part select of a parameter (1), got %b",
part);
pass = 1\'b0;
end
part = pvar1[1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a parameter (1), got %b",
part);
pass = 1\'b0;
end
part = pvar1[1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a parameter (1), got %b",
part);
pass = 1\'b0;
end
part = pvar1[1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a parameter (1), got %b",
part);
pass = 1\'b0;
end
part = pvar1[1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a parameter (1), got %b",
part);
pass = 1\'b0;
end
`endif
// Check a parameter with default size equal to -1.
part = pvar2[31:30]; // At end
if (part !== 2\'b11) begin
$display("Failed at end part select of a parameter (2), got %b", part);
pass = 1\'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = pvar2[33:32]; // May be after all
if (part !== (big_param ? 2\'b11: 2\'bxx)) begin
$display("Failed after part select of a parameter (2), got %b", part);
pass = 1\'b0;
end
part = pvar2[32:31]; // May be partial after
if (part !== (big_param ? 2\'b11 : 2\'bx1)) begin
$display("Failed partial after part select of a parameter (2), got %b",
part);
pass = 1\'b0;
end
part = pvar2[-1:-2]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a parameter (2), got %b", part);
pass = 1\'b0;
end
part = pvar2[0:-1]; // Partial before
if (part !== 2\'b1x) begin
$display("Failed partial before part select of a parameter (2), got %b",
part);
pass = 1\'b0;
end
part = pvar2[1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a parameter (2), got %b",
part);
pass = 1\'b0;
end
part = pvar2[1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a parameter (2), got %b",
part);
pass = 1\'b0;
end
part = pvar2[1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a parameter (2), got %b",
part);
pass = 1\'b0;
end
part = pvar2[1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a parameter (2), got %b",
part);
pass = 1\'b0;
end
`endif
// Check a parameter with size four from the value.
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = pvar3[5:4]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of a parameter (3), got %b", part);
pass = 1\'b0;
end
part = pvar3[4:3]; // Partial after
if (part !== 2\'bx0) begin
$display("Failed partial after part select of a parameter (3), got %b",
part);
pass = 1\'b0;
end
part = pvar3[-1:-2]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a parameter (3), got %b", part);
pass = 1\'b0;
end
part = pvar3[0:-1]; // Partial before
if (part !== 2\'b1x) begin
$display("Failed partial before part select of a parameter (3), got %b",
part);
pass = 1\'b0;
end
part = pvar3[1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a parameter (3), got %b",
part);
pass = 1\'b0;
end
part = pvar3[1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a parameter (3), got %b",
part);
pass = 1\'b0;
end
part = pvar3[1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a parameter (3), got %b",
part);
pass = 1\'b0;
end
part = pvar3[1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a parameter (3), got %b",
part);
pass = 1\'b0;
end
`endif
// Check a parameter with size four from the range [4:1].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = pvar4[6:5]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of a parameter (4), got %b", part);
pass = 1\'b0;
end
part = pvar4[5:4]; // Partial after
if (part !== 2\'bx0) begin
$display("Failed partial after part select of a parameter (4), got %b",
part);
pass = 1\'b0;
end
part = pvar4[0:-1]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a parameter (4), got %b", part);
pass = 1\'b0;
end
part = pvar4[1:0]; // Partial before
if (part !== 2\'b1x) begin
$display("Failed partial before part select of a parameter (4), got %b",
part);
pass = 1\'b0;
end
part = pvar4[1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a parameter (4), got %b",
part);
pass = 1\'b0;
end
part = pvar4[1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a parameter (4), got %b",
part);
pass = 1\'b0;
end
part = pvar4[1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a parameter (4), got %b",
part);
pass = 1\'b0;
end
part = pvar4[1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a parameter (4), got %b",
part);
pass = 1\'b0;
end
`endif
// Check a parameter with size four from the range [1:4].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = pvar5[-1:0]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of a parameter (5), got %b", part);
pass = 1\'b0;
end
part = pvar5[0:1]; // Partial after
if (part !== 2\'bx0) begin
$display("Failed partial after part select of a parameter (5), got %b",
part);
pass = 1\'b0;
end
part = pvar5[5:6]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a parameter (5), got %b", part);
pass = 1\'b0;
end
part = pvar5[4:5]; // Partial before
if (part !== 2\'b1x) begin
$display("Failed partial before part select of a parameter (5), got %b",
part);
pass = 1\'b0;
end
part = pvar5[1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a parameter (5), got %b",
part);
pass = 1\'b0;
end
part = pvar5[1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a parameter (5), got %b",
part);
pass = 1\'b0;
end
part = pvar5[1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a parameter (5), got %b",
part);
pass = 1\'b0;
end
part = pvar5[1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a parameter (5), got %b",
part);
pass = 1\'b0;
end
`endif
// Check a register with range [4:1].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = rvar[6:5]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of a register, got %b", part);
pass = 1\'b0;
end
part = rvar[5:4]; // Partial after
if (part !== 2\'bx1) begin
$display("Failed partial after part select of a register, got %b", part);
pass = 1\'b0;
end
part = rvar[0:-1]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a register, got %b", part);
pass = 1\'b0;
end
part = rvar[1:0]; // Partial before
if (part !== 2\'b0x) begin
$display("Failed partial before part select of a register, got %b", part);
pass = 1\'b0;
end
part = rvar[1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a register, got %b", part);
pass = 1\'b0;
end
part = rvar[1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a register, got %b", part);
pass = 1\'b0;
end
part = rvar[1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a register, got %b", part);
pass = 1\'b0;
end
part = rvar[1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a register, got %b", part);
pass = 1\'b0;
end
`endif
// Check a register with range [1:4].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = rvar2[-1:0]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of a register (2), got %b", part);
pass = 1\'b0;
end
part = rvar2[0:1]; // Partial after
if (part !== 2\'bx1) begin
$display("Failed partial after part select of a register (2), got %b",
part);
pass = 1\'b0;
end
part = rvar2[5:6]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a register (2), got %b", part);
pass = 1\'b0;
end
part = rvar2[4:5]; // Partial before
if (part !== 2\'b0x) begin
$display("Failed partial before part select of a register (2), got %b",
part);
pass = 1\'b0;
end
part = rvar2[1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a register (2), got %b",
part);
pass = 1\'b0;
end
part = rvar2[1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a register (2), got %b",
part);
pass = 1\'b0;
end
part = rvar2[1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a register (2), got %b", part);
pass = 1\'b0;
end
part = rvar2[1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a register (2), got %b", part);
pass = 1\'b0;
end
`endif
// Check an array word with range [4:1].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = ravar[1][6:5]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of an array word, got %b", part);
pass = 1\'b0;
end
part = ravar[1][5:4]; // Partial after
if (part !== 2\'bx0) begin
$display("Failed partial after part select of an array word, got %b",
part);
pass = 1\'b0;
end
part = ravar[1][0:-1]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of an array word, got %b", part);
pass = 1\'b0;
end
part = ravar[1][1:0]; // Partial before
if (part !== 2\'b1x) begin
$display("Failed partial before part select of an array word, got %b",
part);
pass = 1\'b0;
end
part = ravar[1][1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of an array word, got %b",
part);
pass = 1\'b0;
end
part = ravar[1][1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of an array word, got %b",
part);
pass = 1\'b0;
end
part = ravar[1][1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of an array word, got %b", part);
pass = 1\'b0;
end
part = ravar[1][1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of an array word, got %b", part);
pass = 1\'b0;
end
`endif
// Check an array word with range [1:4].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = ravar2[1][-1:0]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of an array word (2), got %b", part);
pass = 1\'b0;
end
part = ravar2[1][0:1]; // Partial after
if (part !== 2\'bx0) begin
$display("Failed partial after part select of an array word (2), got %b",
part);
pass = 1\'b0;
end
part = ravar2[1][5:6]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of an array word (2), got %b", part);
pass = 1\'b0;
end
part = ravar2[1][4:5]; // Partial before
if (part !== 2\'b1x) begin
$display("Failed partial before part select of an array word (2), got %b",
part);
pass = 1\'b0;
end
part = ravar2[1][1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of an array word (2), got %b",
part);
pass = 1\'b0;
end
part = ravar2[1][1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of an array word (2), got %b",
part);
pass = 1\'b0;
end
part = ravar2[1][1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of an array word (2), got %b",
part);
pass = 1\'b0;
end
part = ravar2[1][1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of an array word (2), got %b",
part);
pass = 1\'b0;
end
`endif
// Check a wire with range [4:1].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = wvar[6:5]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of a wire, got %b", part);
pass = 1\'b0;
end
part = wvar[5:4]; // Partial after
if (part !== 2\'bx1) begin
$display("Failed partial after part select of a wire, got %b", part);
pass = 1\'b0;
end
part = wvar[0:-1]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a wire, got %b", part);
pass = 1\'b0;
end
part = wvar[1:0]; // Partial before
if (part !== 2\'b0x) begin
$display("Failed partial before part select of a wire, got %b", part);
pass = 1\'b0;
end
part = wvar[1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a wire, got %b", part);
pass = 1\'b0;
end
part = wvar[1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a wire, got %b", part);
pass = 1\'b0;
end
part = wvar[1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a wire, got %b", part);
pass = 1\'b0;
end
part = wvar[1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a wire, got %b", part);
pass = 1\'b0;
end
`endif
// Check a wire with range [1:4].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = wvar2[-1:0]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of a wire (2), got %b", part);
pass = 1\'b0;
end
part = wvar2[0:1]; // Partial after
if (part !== 2\'bx1) begin
$display("Failed partial after part select of a wire (2), got %b", part);
pass = 1\'b0;
end
part = wvar2[5:6]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a wire (2), got %b", part);
pass = 1\'b0;
end
part = wvar2[4:5]; // Partial before
if (part !== 2\'b0x) begin
$display("Failed partial before part select of a wire (2), got %b", part);
pass = 1\'b0;
end
part = wvar2[1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a wire (2), got %b", part);
pass = 1\'b0;
end
part = wvar2[1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a wire (2), got %b", part);
pass = 1\'b0;
end
part = wvar2[1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a wire (2), got %b", part);
pass = 1\'b0;
end
part = wvar2[1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a wire (2), got %b", part);
pass = 1\'b0;
end
`endif
// Check a wire array word with range [4:1].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = wavar[1][6:5]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of a wire array word, got %b", part);
pass = 1\'b0;
end
part = wavar[1][5:4]; // Partial after
if (part !== 2\'bx0) begin
$display("Failed partial after part select of a wire array word, got %b",
part);
pass = 1\'b0;
end
part = wavar[1][0:-1]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a wire array word, got %b", part);
pass = 1\'b0;
end
part = wavar[1][1:0]; // Partial before
if (part !== 2\'b1x) begin
$display("Failed partial before part select of a wire array word, got %b",
part);
pass = 1\'b0;
end
part = wavar[1][1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a wire array word, got %b",
part);
pass = 1\'b0;
end
part = wavar[1][1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a wire array word, got %b",
part);
pass = 1\'b0;
end
part = wavar[1][1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a wire array word, got %b",
part);
pass = 1\'b0;
end
part = wavar[1][1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a wire array word, got %b",
part);
pass = 1\'b0;
end
`endif
// Check a wire array word with range [1:4].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
part = wavar2[1][-1:0]; // After all
if (part !== 2\'bxx) begin
$display("Failed after part select of a wire array word (2), got %b",
part);
pass = 1\'b0;
end
part = wavar2[1][0:1]; // Partial after
if (part !== 2\'bx0) begin
$display("Failed partial after part select of a wire array word (2),",
" got %b", part);
pass = 1\'b0;
end
part = wavar2[1][5:6]; // Before all
if (part !== 2\'bxx) begin
$display("Failed before part select of a wire array word (2), got %b",
part);
pass = 1\'b0;
end
part = wavar2[1][4:5]; // Partial before
if (part !== 2\'b1x) begin
$display("Failed partial before part select of a wire array word (2),",
" got %b", part);
pass = 1\'b0;
end
part = wavar2[1][1\'bx:1]; // Undefined 1st
if (part !== 2\'bxx) begin
$display("Failed undefined 1st part select of a wire array word (2),",
" got %b", part);
pass = 1\'b0;
end
part = wavar2[1][1:1\'bx]; // Undefined 2nd
if (part !== 2\'bxx) begin
$display("Failed undefined 2nd part select of a wire array word (2),",
" got %b", part);
pass = 1\'b0;
end
part = wavar2[1][1\'bz:1]; // High-Z 1st
if (part !== 2\'bxx) begin
$display("Failed high-Z 1st part select of a wire array word (2), got %b",
part);
pass = 1\'b0;
end
part = wavar2[1][1:1\'bz]; // High-Z 2nd
if (part !== 2\'bxx) begin
$display("Failed high-Z 2nd part select of a wire array word (2), got %b",
part);
pass = 1\'b0;
end
`endif
if (pass) $display("PASSED");
end
endmodule
|
`begin_keywords "1364-2005"
// Module to test the messages/results for out of bound R-value constant
// bit selects.
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg big_param;
reg bit;
integer idx;
parameter pvar0 = 0;
parameter pvar1 = 1;
parameter pvar2 = -1;
parameter pvar3 = 4\'b0001;
parameter [4:1] pvar4 = 4\'b0001;
parameter [1:4] pvar5 = 4\'b0001;
reg [4:1] rvar = 4\'b0010;
reg [1:4] rvar2 = 4\'b0010;
reg [4:1] ravar [2:1];
reg [1:4] ravar2 [2:1];
wire [4:1] wvar = 4\'b0100;
wire [1:4] wvar2 = 4\'b0100;
wire [4:1] wavar [2:1];
wire [1:4] wavar2 [2:1];
assign wavar[1] = 4\'b1001;
assign wavar[2] = 4\'b1010;
assign wavar2[1] = 4\'b1001;
assign wavar2[2] = 4\'b1010;
initial begin
pass = 1\'b1;
ravar[1] = 4\'b1101;
ravar[2] = 4\'b1110;
ravar2[1] = 4\'b1101;
ravar2[2] = 4\'b1110;
#1;
// Icarus supports an unlimited size for unsized parameters. The
// following checks the 33rd bit to see if it is 1\'bx. If so we
// assume that the simulator only support 32 bit, otherwise we
// modify our after check for unsized parameters to work (pass)
// with a larger constant.
big_param = 1\'b1;
idx = 32;
if (pvar0[idx] === 1\'bx) big_param = 1\'b0;
// Check a parameter with default size equal to 0.
bit = pvar0[31]; // At end
if (bit !== 1\'b0) begin
$display("Failed at end bit select of a parameter (0), got %b", bit);
pass = 1\'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = pvar0[32]; // May be after
if (bit !== (big_param ? 1\'b0: 1\'bx)) begin
$display("Failed after bit select of a parameter (0), got %b", bit);
pass = 1\'b0;
end
bit = pvar0[-1]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a parameter (0), got %b", bit);
pass = 1\'b0;
end
bit = pvar0[1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a parameter (0), got %b", bit);
pass = 1\'b0;
end
bit = pvar0[1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a parameter (0), got %b", bit);
pass = 1\'b0;
end
`endif
// Check a parameter with default size equal to 1.
bit = pvar1[31]; // At end
if (bit !== 1\'b0) begin
$display("Failed at end bit select of a parameter (1), got %b", bit);
pass = 1\'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = pvar1[32]; // May be after
if (bit !== (big_param ? 1\'b0: 1\'bx)) begin
$display("Failed after bit select of a parameter (1), got %b", bit);
pass = 1\'b0;
end
bit = pvar1[-1]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a parameter (1), got %b", bit);
pass = 1\'b0;
end
bit = pvar1[1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a parameter (1), got %b", bit);
pass = 1\'b0;
end
bit = pvar1[1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a parameter (1), got %b", bit);
pass = 1\'b0;
end
`endif
// Check a parameter with default size equal to -1.
bit = pvar2[31]; // At end
if (bit !== 1\'b1) begin
$display("Failed at end bit select of a parameter (-1), got %b", bit);
pass = 1\'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = pvar2[32]; // May be after
if (bit !== (big_param ? 1\'b1: 1\'bx)) begin
$display("Failed after bit select of a parameter (-1), got %b", bit);
pass = 1\'b0;
end
bit = pvar2[-1]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a parameter (-1), got %b", bit);
pass = 1\'b0;
end
bit = pvar2[1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a parameter (-1), got %b", bit);
pass = 1\'b0;
end
bit = pvar2[1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a parameter (-1), got %b", bit);
pass = 1\'b0;
end
`endif
// Check a parameter with size four from the value.
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = pvar3[4]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of a parameter (3), got %b", bit);
pass = 1\'b0;
end
bit = pvar3[-1]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a parameter (3), got %b", bit);
pass = 1\'b0;
end
bit = pvar3[1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a parameter (3), got %b", bit);
pass = 1\'b0;
end
bit = pvar3[1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a parameter (3), got %b", bit);
pass = 1\'b0;
end
`endif
// Check a parameter with size four from the range [4:1].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = pvar4[5]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of a parameter (4), got %b", bit);
pass = 1\'b0;
end
bit = pvar4[0]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a parameter (4), got %b", bit);
pass = 1\'b0;
end
bit = pvar4[1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a parameter (4), got %b", bit);
pass = 1\'b0;
end
bit = pvar4[1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a parameter (4), got %b", bit);
pass = 1\'b0;
end
`endif
// Check a parameter with size four from the range [1:4].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = pvar5[0]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of a parameter (5), got %b", bit);
pass = 1\'b0;
end
bit = pvar5[5]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a parameter (5), got %b", bit);
pass = 1\'b0;
end
bit = pvar5[1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a parameter (5), got %b", bit);
pass = 1\'b0;
end
bit = pvar5[1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a parameter (5), got %b", bit);
pass = 1\'b0;
end
`endif
// Check a register with range [4:1].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = rvar[5]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of a register, got %b", bit);
pass = 1\'b0;
end
bit = rvar[0]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a register, got %b", bit);
pass = 1\'b0;
end
bit = rvar[1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a register, got %b", bit);
pass = 1\'b0;
end
bit = rvar[1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a register, got %b", bit);
pass = 1\'b0;
end
`endif
// Check a register with range [1:4].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = rvar2[0]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of a register (2), got %b", bit);
pass = 1\'b0;
end
bit = rvar2[5]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a register (2), got %b", bit);
pass = 1\'b0;
end
bit = rvar2[1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a register (2), got %b", bit);
pass = 1\'b0;
end
bit = rvar2[1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a register (2), got %b", bit);
pass = 1\'b0;
end
`endif
// Check an array word with range [4:1].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = ravar[1][5]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of an array word, got %b", bit);
pass = 1\'b0;
end
bit = ravar[1][0]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of an array word, got %b", bit);
pass = 1\'b0;
end
bit = ravar[1][1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of an array word, got %b", bit);
pass = 1\'b0;
end
bit = ravar[1][1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of an array word, got %b", bit);
pass = 1\'b0;
end
`endif
// Check an array word with range [1:4].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = ravar2[1][0]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of an array word (2), got %b", bit);
pass = 1\'b0;
end
bit = ravar2[1][5]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of an array word (2), got %b", bit);
pass = 1\'b0;
end
bit = ravar2[1][1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of an array word (2), got %b", bit);
pass = 1\'b0;
end
bit = ravar2[1][1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of an array word (2), got %b", bit);
pass = 1\'b0;
end
`endif
// Check a wire with range [4:1].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = wvar[5]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of a wire, got %b", bit);
pass = 1\'b0;
end
bit = wvar[0]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a wire, got %b", bit);
pass = 1\'b0;
end
bit = wvar[1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a wire, got %b", bit);
pass = 1\'b0;
end
bit = wvar[1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a wire, got %b", bit);
pass = 1\'b0;
end
`endif
// Check a wire with range [1:4].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = wvar2[0]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of a wire (2), got %b", bit);
pass = 1\'b0;
end
bit = wvar2[5]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a wire (2), got %b", bit);
pass = 1\'b0;
end
bit = wvar2[1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a wire (2), got %b", bit);
pass = 1\'b0;
end
bit = wvar2[1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a wire (2), got %b", bit);
pass = 1\'b0;
end
`endif
// Check a wire array word with range [4:1].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = wavar[1][5]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of a wire array word, got %b", bit);
pass = 1\'b0;
end
bit = wavar[1][0]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a wire array word, got %b", bit);
pass = 1\'b0;
end
bit = wavar[1][1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a wire array word, got %b", bit);
pass = 1\'b0;
end
bit = wavar[1][1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a wire array word, got %b", bit);
pass = 1\'b0;
end
`endif
// Check a wire array word with range [1:4].
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
bit = wavar2[1][0]; // After
if (bit !== 1\'bx) begin
$display("Failed after bit select of a wire array word (2), got %b", bit);
pass = 1\'b0;
end
bit = wavar2[1][5]; // Before
if (bit !== 1\'bx) begin
$display("Failed before bit select of a wire array word (2), got %b",
bit);
pass = 1\'b0;
end
bit = wavar2[1][1\'bx]; // Undefined
if (bit !== 1\'bx) begin
$display("Failed undefined bit select of a wire array word (2), got %b",
bit);
pass = 1\'b0;
end
bit = wavar2[1][1\'bz]; // High-Z
if (bit !== 1\'bx) begin
$display("Failed high-Z bit select of a wire array word (2), got %b",
bit);
pass = 1\'b0;
end
`endif
if (pass) $display("PASSED");
end
endmodule
`end_keywords
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always release reg_lvalue ;
// D: No dependancy
module main ;
reg [3:0] value1 ;
initial
begin
#15;
if(value1 != 4\'h5)
$display("FAILED - 3.1.3H always release rev_lvalue;\
");
else
\tbegin
$display("PASSED\
");
\t $finish;
end
end
always release value1 ;
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test the display of very wide vectors in decimal.
*/
module test;
reg signed [127:0] value;
initial begin
value = 1;
while (value != 0) begin
\t $display("value=%d", value);
\t value = value << 1;
end
value = -1;
while (value != 0) begin
\t $display("value=%d", value);
\t value = value << 1;
end
end
endmodule // test
|
// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
//\t\t Michael Runyan (mrunyan at chiaro.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg [2:0]\taddr;
reg [7:0]\tm_poke[7:0];
reg [7:0]\tm_peek[7:0];
task f_copy;
\tinteger i;
begin
\tfor (i = 0; i < 8; i = i + 1) begin
\t m_peek[i] = m_poke[i];
\tend
end
endtask
task f_dump;
\tinteger i;
begin
\t$display("Verilog compare m_poke <=> m_peek");
\tfor (i = 0; i < 8; i = i + 1) begin
\t $display (" %0d: \'b_%b <=> \'b_%b%s",
\t\ti, m_poke[i], m_peek[i],
\t\tm_poke[i] !== m_peek[i] ? " - ERROR" : "");
\tend
end
endtask
initial begin
\t#0;
\t$mempoke;
\t#10;
\tf_copy;
\t#10;
\t$mempeek;
\t#10;
\tf_dump;
end
endmodule
|
// pr1662508.v
`timescale 1ns / 1ns
module ram(
\tinput clk,
\tinput we,
\tinput [9:0] addr,
\tinput [15:0] data,
\toutput [15:0] read_bus
);
reg [15:0] ram[31:0];
assign read_bus = ram[addr[3:0]];
always @(posedge clk) if (we)
\tram[addr[3:0]] <= data;
endmodule
module ram_test;
reg clk;
reg fail=0;
integer cc;
initial begin
\tfor (cc = 0; cc < 33; cc=cc+1) begin
\t\tclk = 0; #5;
\t\tclk = 1; #5;
\tend
\tif (fail) $display("FAIL");
\telse $display("PASSED");
end
reg we=0;
reg [9:0] addr=0;
reg [15:0] data=0;
always @(posedge clk) begin
\taddr <= cc;
\tdata <= cc*cc;
\twe <= cc<16;
end
wire [15:0] read_bus;
ram ram(clk, we, addr, data, read_bus);
always @(negedge clk) if (~we) begin
\t$display("%d %d", addr, read_bus);
\tif (read_bus !== addr[3:0]*addr[3:0]) fail=1;
end
endmodule
|
module test();
wire [7:0] value1;
reg [7:0] value2;
reg clk;
assign value1[3:0] = 4\'b1010;
always @(posedge clk) begin
value2[3:0] <= value1;
end
(* ivl_synthesis_off *)
initial begin
#1 clk = 0;
#1 clk = 1;
#1 clk = 0;
$display("%b %b", value1, value2);
`ifdef __ICARUS_SYNTH__
if (value2 === 8\'bzzzz1010)
`else
if (value2 === 8\'bxxxx1010)
`endif
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/* PR1645518 */
module testBench;
wire w1, w2, w3, w4, w5;
binaryToESeg d (w1, w2, w3, w4, w5);
test_bToESeg t (w1, w2, w3, w4, w5);
endmodule
module binaryToESeg
(input A, B, C, D,
output eSeg);
nand #1
g1 (p1, C, ~D),
g2 (p2, A, B),
g3 (p3, ~B, ~D),
g4 (p4, A, C),
g5 (eSeg, p1, p2, p3, p4);
endmodule // binaryToESeg
module test_bToESeg
(output reg A, B, C, D, input eSeg);
initial // two slashes introduce a single line comment
begin
$monitor ($time,,
\t\t"A = %b B = %b C = %b D = %b, eSeg = %b",
\t\tA, B, C, D, eSeg);
//waveform for simulating the nand lip lop
#10 A = 0; B = 0; C = 0; D = 0;
#10 D = 1;
#10 C = 1; D = 0;
#10 $finish(0);
end
endmodule
|
module TEST
#(parameter ME = 0)
(input OE,
output wire [3:0] Q
/* */);
assign Q = OE? ME : 4\'d0;
endmodule // TEST
module main;
logic OE;
logic [3:0] Q [0:3];
genvar gidx;
for (gidx = 0 ; gidx < 4 ; gidx = gidx+1) begin : DRV
TEST #(.ME(gidx)) dut (.OE(OE), .Q(Q[gidx]));
end
int idx;
initial begin
OE = 1;
#1 ;
for (idx = 0 ; idx < 4 ; idx = idx+1) begin
\t if (Q[idx] !== idx[3:0]) begin
\t $display("FAILED -- Q[%0d] === %b", idx, Q[idx]);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
module array_assign();
parameter MSB = 1;
integer ii;
reg signed [2:0] ar_reg[0:MSB];
wire signed [4:0] as_wr;
// compiled with "-g2 -g2x"
// FAILED at this line
assign as_wr = {{2{ar_reg[0][2]}},ar_reg[1]};
always @(as_wr)
for(ii=0; ii<(MSB+1); ii=ii+1)
begin
$display(" %t ar_reg=%0d w_assign=%0d", $time, ar_reg[ii], as_wr);
$display(" %t ar_reg[0]=3\'b%3b ar_reg[1]=3\'b%3b", $time, ar_reg[0], ar_reg[1]);
$display(" %t as_wr=5\'b%5b", $time, as_wr);
end
initial
begin
$display("\
*** module %m **************************************");
#10;
for(ii=0; ii<(MSB+1); ii=ii+1)
ar_reg[ii] <= 3\'sd1;
#10;
for(ii=0; ii<(MSB+1); ii=ii+1)
ar_reg[ii] <= 3\'sd0;
$display("\
\
");
end
endmodule
/* expected output - START
module array_assign
10 ar_reg=1 w_assign=1
10 ar_reg[0]=3\'b001 ar_reg[1]=3\'b001
10 as_wr=5\'b00001
10 ar_reg=1 w_assign=1
10 ar_reg[0]=3\'b001 ar_reg[1]=3\'b001
10 as_wr=5\'b00001
20 ar_reg=0 w_assign=0
20 ar_reg[0]=3\'b000 ar_reg[1]=3\'b000
20 as_wr=5\'b00000
20 ar_reg=0 w_assign=0
20 ar_reg[0]=3\'b000 ar_reg[1]=3\'b000
20 as_wr=5\'b00000
expected output - END */
|
// Check variable declarations in unnamed forks
// All of these should pass in SystemVerilog and all should fail in Verilog
module test;
initial fork
integer x;
join
initial fork
integer x;
integer y;
join
initial fork
integer x, y;
join
initial fork
integer x;
integer y;
x = y;
join
initial begin
$display("PASSED");
end
endmodule
|
// Check that it is possible to declare the data type for a struct type module
// port before the direction for non-ANSI style port declarations.
typedef struct packed {
reg [31:0] x;
reg [7:0] y;
} T;
module test(x);
T x;
output x;
initial begin
if ($bits(x) == $bits(T)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
// Check that using a class type as the base type for an enum results in an
// error.
class C;
endclass
module test;
enum C {
A
} e;
initial begin
$display("FAILED");
end
endmodule
|
module top;
reg q, d;
always_comb begin
#0 q = d;
end
initial $display("Expected compile failure!");
endmodule
|
`begin_keywords "1364-2005"
module top;
reg pass;
reg [3:0] var;
integer lp;
initial begin
pass = 1\'b1;
for (lp = 0; lp < 16; lp = lp + 1) begin
var = lp;
// This should bit extend var as unsigned and then
// convert it into a signed value.
if (lp !== $signed(var+5\'b0)) begin
$display("FAILED: expected %2d, got %2d", lp, $signed(var+5\'b0));
pass = 1\'b0;
end
end
if (pass) $display("PASSED");
end
endmodule
`end_keywords
|
module test();
wire net1;
wire net2;
wire net3;
wire net4;
wire net5;
reg src1;
reg src2;
reg src3;
assign net1 = src1;
assign net2 = src2;
assign net3 = src3;
tran(net4, net1);
tran(net4, net2);
tran(net5, net3);
tran(net5, net4);
integer multi;
integer forced;
integer countD;
integer count0;
integer count1;
integer countX;
reg failed = 0;
task check_results;
input integer expected_multi;
input integer expected_forced;
input integer expected_countD;
input integer expected_count0;
input integer expected_count1;
input integer expected_countX;
begin
$write("multi = %0d ", multi);
if (multi !== expected_multi) failed = 1;
if (expected_forced != -1) begin
$write("forced = %0d ", forced);
if (forced !== expected_forced) failed = 1;
end
if (expected_countD != -1) begin
$write("countD = %0d ", countD);
if (countD !== expected_countD) failed = 1;
end
if (expected_count0 != -1) begin
$write("count0 = %0d ", count0);
if (count0 !== expected_count0) failed = 1;
end
if (expected_count1 != -1) begin
$write("count1 = %0d ", count1);
if (count1 !== expected_count1) failed = 1;
end
if (expected_countX != -1) begin
$write("countX = %0d ", countX);
if (countX !== expected_countX) failed = 1;
end
$write("\
");
end
endtask
initial begin
src1 = 1\'b0; src2 = 1\'b0; src3 = 1\'b0;
#1;
multi = $countdrivers(net1, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 2, 0, 0);
multi = $countdrivers(net2, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 2, 0, 0);
multi = $countdrivers(net3, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 2, 0, 0);
multi = $countdrivers(net4, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 3, 0, 0);
multi = $countdrivers(net5, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 2, 0, 0);
$display("");
src1 = 1\'b1; src2 = 1\'b0; src3 = 1\'b0;
#1;
multi = $countdrivers(net1, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 1, 1);
multi = $countdrivers(net2, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 0, 1);
multi = $countdrivers(net3, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 0, 1);
multi = $countdrivers(net4, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 0, 0, 3);
multi = $countdrivers(net5, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 0, 2);
$display("");
src1 = 1\'b1; src2 = 1\'b1; src3 = 1\'b0;
#1;
multi = $countdrivers(net1, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 1, 1);
multi = $countdrivers(net2, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 1, 1);
multi = $countdrivers(net3, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 0, 1);
multi = $countdrivers(net4, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 0, 0, 3);
multi = $countdrivers(net5, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 0, 2);
$display("");
src1 = 1\'b1; src2 = 1\'b1; src3 = 1\'b1;
#1;
multi = $countdrivers(net1, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 2, 0);
multi = $countdrivers(net2, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 2, 0);
multi = $countdrivers(net3, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 2, 0);
multi = $countdrivers(net4, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 0, 3, 0);
multi = $countdrivers(net5, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 2, 0);
$display("");
src1 = 1\'b1; src2 = 1\'bz; src3 = 1\'bz;
#1;
multi = $countdrivers(net1, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 2, 0);
multi = $countdrivers(net2, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
multi = $countdrivers(net3, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
multi = $countdrivers(net4, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 0, 3, 0);
multi = $countdrivers(net5, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 2, 0);
$display("");
src1 = 1\'bz; src2 = 1\'b0; src3 = 1\'bz;
#1;
multi = $countdrivers(net1, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(net2, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 2, 0, 0);
multi = $countdrivers(net3, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(net4, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 3, 0, 0);
multi = $countdrivers(net5, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 2, 0, 0);
$display("");
src1 = 1\'bz; src2 = 1\'bz; src3 = 1\'b1;
#1;
multi = $countdrivers(net1, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
multi = $countdrivers(net2, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
multi = $countdrivers(net3, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 2, 0);
multi = $countdrivers(net4, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 0, 3, 0);
multi = $countdrivers(net5, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 0, 2, 0);
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2001 Philip Blundell
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
primitive p (Q, D);
input D;
output Q;
reg Q;
initial Q = 1'b0;
table
0 : ? : 0;
1 : ? : 1;
endtable
endprimitive
module m;
reg D;
wire Q;
reg A;
wire QQ;
p(Q, D);
buf(QQ, Q);
initial
begin
// The #1 is needed here to allow the initial values to
// settle. Without it, there is a time-0 race.
#1 $display(QQ, Q);
#10
D = 0;
#15
$display(QQ, Q);
#20
D = 1;
#25
$display(QQ, Q);
$finish(0);
end
endmodule
|
/* pr1650842 */
module test;
initial main;
task main;
integer _$ID241, _$ID246, _$ID247, _$ID248, _$ID249, a;
begin
\t a = 0;
\t _$ID241 = a;
\t a = 9;
\t _$ID246 = a;
\t _$ID247 = 3;
\t a = _$ID247;
\t _$ID248 = _$ID246 + _$ID247 ;
\t _$ID249 = _$ID248;
\t a = _$ID249;
\t if( a !== 12 ) begin
\t $write("FAIL: expected 12; got %d\
", a);
\t $display("_$ID241=%d", _$ID241);
\t $display("_$ID246=%d", _$ID246);
\t $display("_$ID247=%d", _$ID247);
\t $display("_$ID248=%d", _$ID248);
\t $display("_$ID249=%d", _$ID249);
\t end else begin
\t $write("PASSED\
");
\t end
end
endtask
endmodule
|
module tb;
reg [1:0] i, j;
reg [3:0] x[0:2];
reg error;
initial begin
error = 0;
i = 0;
j = i++;
if (i !== 2\'b01 || j !== 2\'b00) begin
$display("FAILED j = i++ --> j=%b, i=%b", j, i);
error = 1;
end
i = 0;
x[0] = 4\'dx;
x[1] = 4\'dx;
x[0] = 0;
if (x[0] !== 4\'d0 || x[1] !== 4\'dx) begin
$display("FAILED x[i++] = 0 --> x[0]=%b, x[1]=%b, i=%b", x[0], x[1], i);
error = 1;
end
i = 0;
x[0] = 1;
x[0] += 2;
if (x[0] !== 4\'d3) begin
$display("FAILED x[0] should be 3, but it is %d.", x[0]);
error = 1;
end
if (i !== 2\'d0) begin
$display("FAILED i should be 1, but it is %d.", i);
error = 1;
end
if (error == 0)
$display("PASSED");
end
endmodule // tb
|
module signed_mux_bug();
reg s;
reg [3:0] a, b;
reg [7:0] y, z;
initial begin
// Example vector
s = 1\'b1;
a = 4\'b1010;
b = 4\'b0000;
// Manually sign extend operands before multiplexer
y = s ? {{4{a[3]}}, a} : {{4{b[3]}}, b};
// Use $signed() to sign extend operands before multiplexer
// - Note that Icarus is not sign extending as expected
z = s ? $signed(a) : $signed(b);
// Display results
$display("a = %b", a);
$display("b = %b", b);
$display("y = %b", y);
$display("z = %b", z);
// Finished
$finish(0);
end
endmodule
|
module test();
reg [] illegal;
endmodule
|
module check (input unsigned [22:0] a, b, c);
wire unsigned [22:0] int_AB;
assign int_AB = a / b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 1;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
#1 A = 0;
B = 1;
#1 A = 23\'h7fffff;
#1 B = 23\'h7fffff;
#1 B = 1;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = {$random} % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = {$random} % MAX;
\t if (B === 23\'b0) B = 1;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
\t\t if (B === 23\'b0) B = 1;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input unsigned [22:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [22:0] r;
stimulus stim (.A(a), .B(b));
udiv23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
`timescale 1us/100ns
module top;
reg pass = 1\'b1;
real ra = 1.0, rb = 2.0;
wire real rmod;
/* Real Power. */
assign #1 rmod = ra % rb;
initial begin
#0.9;
if (rmod == 1.0) begin
pass = 1\'b0;
$display("Real: modulus value not delayed.");
end
#0.1;
#0;
if (rmod != 1.0) begin
pass = 1\'b0;
$display("Real: modulus value not correct, expected 1.0 got %g.", rmod);
end
#1 ra = 2.0;
#2;
if (rmod != 0.0) begin
pass = 1\'b0;
$display("Real: modulus value not correct, expected 0.0 got %g.", rmod);
end
#1 rb = 4.0;
#2;
if (rmod != 2.0) begin
pass = 1\'b0;
$display("Real: modulus value not correct, expected 2.0 got %g.", rmod);
end
if (pass) $display("PASSED");
end
endmodule
|
// Check that using a queue type as the base type for an enum results in an
// error
module test;
typedef logic T[$];
enum T {
A
} e;
initial begin
$display("FAILED");
end
endmodule
|
`define MAC(i) $display(i);
module top;
initial begin
if ("$display(in);" != ``MAC(in))
$display("FAILED: expected \\"display(in);\\", got \\"`MAC(in)\\"");
else $display("PASSED");
end
endmodule
|
reg [7:0] v;
module dut(input wire [7:0] i = v, output wire [7:0] o);
assign o = i;
endmodule
module tb();
wire [7:0] result;
dut dut(,result);
initial begin
#1;
if (result === 10)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate assign procedural assign {ident1,ident0} = expr;
module main ;
reg a,b,c,d;
reg control;
reg clock;
reg error;
always @(posedge clock)
{a,b,c,d} = 4\'h3;
always @(control)
if(control)
assign {a,b,c,d} = 4\'h2;
else
deassign {a,b,c,d} ;
// Setup a clock generator.
always begin
#2;
clock = ~clock;
end
initial
begin
clock = 0;
error = 0;
# 3;
if({a,b,c,d} !== 3)
begin
$display("FAILED - assign3.2D - procedural assignment(1)");
error = 1;
end
# 2;
control = 1;
# 1;
if({a,b,c,d} !== 2)
begin
$display("FAILED - assign3.2D - procedural assignment(2)");
error = 1;
end
# 3 ;
control = 0;
# 2;
if({a,b,c,d} !== 3)
begin
$display("FAILED - assign3.2D - procedural assignment(3)");
error = 1;
end
if(error == 0) $display ("PASSED");
$finish ;
end
endmodule
|
// Regression test for GitHub issue 8 : Signedness handling in binary
// bitwise operations of constants.
module bug();
localparam value1 = 4\'sb1010 | 4\'sb0000;
localparam value2 = 4\'sb1010 + 4\'sb0000;
localparam value3 = ~4\'sb0101;
localparam value4 = -4\'sb0101;
reg signed [4:0] result;
reg failed = 0;
initial begin
result = value1;
$display("%b", result);
if (result !== 5\'b11010) failed = 1;
result = value2;
$display("%b", result);
if (result !== 5\'b11010) failed = 1;
result = value3;
$display("%b", result);
if (result !== 5\'b11010) failed = 1;
result = value4;
$display("%b", result);
if (result !== 5\'b11011) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Based on bug report pr772.
*/
module err ();
parameter kuku = "AAAAA";
reg reset_b,clk;
initial begin
reset_b = 0;
repeat (10) @(posedge clk);
#1 reset_b = 1;
end
initial begin
clk = 1\'b1;
#3 forever #10 clk=~clk;
end
always @(posedge clk or negedge reset_b)
if (!reset_b) begin
end
else begin
if ((kuku=="RRRRR") || (kuku=="AAAAA") || (kuku=="BBBBB"))
\t$display("PASSED");
else $display("FAILED");
$finish;
end
endmodule
|
`timescale 1ns/1ns
module sum_test;
reg clk;
wire [10:0] s;
initial begin
clk = 0;
forever #10 clk = ~clk;
end
sum #(5, 8) sum (clk, {8\'d10,8\'d20,8\'d30,8\'d40,8\'d50}, s);
initial begin
$display("Starting...");
repeat (50) @(posedge clk);
$display("sum = %d",s);
if (s !== 150)
$display("FAILED: expected 150, received %0d",s);
else
$display("PASSED");
$finish;
end
endmodule
module sum
#(
parameter n = 4,
parameter width = 8,
parameter log_n = $clog2(n)
)
(
input clk,
input [n*width-1:0]addends,
output reg [log_n+width-1:0] s
);
// This should fail at the first recursion since this is not inside
// a generate block.
wire [$clog2(n/2)+width-1:0] a1;
wire [$clog2(n-n/2)+width-1:0] a2;
sum #(n/2, width) s0 (clk, addends[(n/2)*width-1:0], a1);
sum #(n-n/2, width) s1 (clk, addends[n*width-1:(n/2)*width], a2);
always @(posedge clk) s <= a1 + a2;
endmodule // sum
|
module test;
reg [7:0] value, value;
endmodule
|
// Check that constant recursive functions are supported when the `return`
// statement is used.
module recursive_func();
function automatic [15:0] factorial(input [15:0] n);
if (n > 1) begin
return factorial(n - 1) * n;
end
return n;
endfunction
localparam F3 = factorial(3);
localparam F4 = factorial(4);
localparam F5 = factorial(5);
initial begin
$display("factorial 3 = %0d", F3);
$display("factorial 4 = %0d", F4);
$display("factorial 5 = %0d", F5);
end
endmodule
|
`timescale 1ns/1ps
module top;
initial begin
$timeformat(-9,6,"ns",20);
$display("here");
$display("in top, time: %t",$time);
$finish(0);
end
endmodule
|
typedef union packed {
logic [3:0] bits;
struct packed { logic [1:0] hig; logic [1:0] low; } words;
} bits_t;
module main;
bits_t foo;
initial begin
foo.bits = \'b1001;
if (foo.bits !== \'b1001) begin
\t $display("FAILED -- foo.bits=%b", foo.bits);
\t $finish;
end
if (foo.words !== \'b1001) begin
\t $display("FAILED -- foo.words=%b", foo.words);
\t $finish;
end
//foo.words.low = \'b00;
//foo.words.hig = \'b11;
foo.words = \'b1100;
if (foo.words !== \'b1100) begin
\t $display("FAILED -- foo.words=%b", foo.words);
\t $finish;
end
if (foo.bits !== \'b1100) begin
\t $display("FAILED -- foo.bits=%b", foo.bits);
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
// Check the various variable array selects (small to large).
module top;
reg passed;
wire [1:0] a [1:4];
wire [0:0] s0 = 0;
wire [1:0] s1 = 0;
wire [2:0] s2 = 0;
reg [1:0] ar [1:4];
wire [1:0] c [-3:0];
wire [0:0] s3 = 0;
wire [1:0] s4 = 0;
reg [1:0] cr [-3:0];
wire [1:0] res_a0 = a[s0];
wire [1:0] res_a1 = a[s1];
wire [1:0] res_a2 = a[s2];
wire [1:0] res_c3 = c[s3];
wire [1:0] res_c4 = c[s4];
reg res_a [1:4];
reg res_c [-3:0];
assign a[1] = 2\'d0;
assign a[2] = 2\'b1;
assign a[3] = 2\'d2;
assign a[4] = 2\'d3;
assign c[-3] = 2\'d0;
assign c[-2] = 2\'b1;
assign c[-1] = 2\'d2;
assign c[0] = 2\'d3;
initial begin
#1;
passed = 1\'b1;
ar[1] = 2\'d0;
ar[2] = 2\'b1;
ar[3] = 2\'d2;
ar[4] = 2\'d3;
cr[-3] = 2\'d0;
cr[-2] = 2\'b1;
cr[-1] = 2\'d2;
cr[0] = 2\'d3;
// Check procedural R-value variable bit selects of a net.
$display("a[s0]: %b", a[s0]);
if (a[s0] !== 2\'bxx) begin
$display("Failed a[s0], expected 2\'bxx, got %b", a[s0]);
passed = 1\'b0;
end
$display("a[s1]: %b", a[s1]);
if (a[s1] !== 2\'bxx) begin
$display("Failed a[s1], expected 2\'bxx, got %b", a[s1]);
passed = 1\'b0;
end
$display("a[s2]: %b", a[s2]);
if (a[s2] !== 2\'bxx) begin
$display("Failed a[s2], expected 2\'bxx, got %b", a[s2]);
passed = 1\'b0;
end
$display("c[s3]: %b", c[s3]);
if (c[s3] !== 2\'b11) begin
$display("Failed c[s3], expected 2\'b11, got %b", c[s3]);
passed = 1\'b0;
end
$display("c[s4]: %b", c[s4]);
if (c[s4] !== 2\'b11) begin
$display("Failed c[s4], expected 2\'b11, got %b", c[s4]);
passed = 1\'b0;
end
// Check procedural R-value variable bit selects of a reg.
$display("ar[s0]: %b", ar[s0]);
if (ar[s0] !== 2\'bxx) begin
$display("Failed ar[s0], expected 2\'bxx, got %b", ar[s0]);
passed = 1\'b0;
end
$display("ar[s1]: %b", ar[s1]);
if (ar[s1] !== 2\'bxx) begin
$display("Failed ar[s1], expected 2\'bxx, got %b", ar[s1]);
passed = 1\'b0;
end
$display("ar[s2]: %b", ar[s2]);
if (ar[s2] !== 2\'bxx) begin
$display("Failed ar[s2], expected 2\'bxx, got %b", ar[s2]);
passed = 1\'b0;
end
$display("cr[s3]: %b", cr[s3]);
if (cr[s3] !== 2\'b11) begin
$display("Failed cr[s3], expected 2\'b11, got %b", cr[s3]);
passed = 1\'b0;
end
$display("cr[s4]: %b", cr[s4]);
if (cr[s4] !== 2\'b11) begin
$display("Failed cr[s4], expected 2\'b11, got %b", cr[s4]);
passed = 1\'b0;
end
// Check continuous assignment R-value variable bit selects.
if (res_a0 !== 2\'bxx) begin
$display("Failed res_a0, expected 2\'bxx, got %b", res_a0);
passed = 1\'b0;
end
if (res_a1 !== 2\'bxx) begin
$display("Failed res_a1, expected 2\'bxx, got %b", res_a1);
passed = 1\'b0;
end
if (res_a2 !== 2\'bxx) begin
$display("Failed res_a2, expected 2\'bxx, got %b", res_a2);
passed = 1\'b0;
end
if (res_c3 !== 2\'b11) begin
$display("Failed res_c3, expected 2\'b11, got %b", res_c3);
passed = 1\'b0;
end
if (res_c4 !== 2\'b11) begin
$display("Failed res_c4, expected 2\'b11, got %b", res_c4);
passed = 1\'b0;
end
// Check procedural L-value variable bit selects.
res_a[1] = 1\'bx;
res_a[2] = 1\'bx;
res_a[3] = 1\'bx;
res_a[4] = 1\'bx;
res_a[s0] = 1\'b0;
if (res_a[1] !== 1\'bx) begin
$display("Failed res_a[s0], expected 1\'bx for [1], got %b", res_a[1]);
passed = 1\'b0;
end
if (res_a[2] !== 1\'bx) begin
$display("Failed res_a[s0], expected 1\'bx for [2], got %b", res_a[2]);
passed = 1\'b0;
end
if (res_a[3] !== 1\'bx) begin
$display("Failed res_a[s0], expected 1\'bx for [3], got %b", res_a[3]);
passed = 1\'b0;
end
if (res_a[4] !== 1\'bx) begin
$display("Failed res_a[s0], expected 1\'bx for [4], got %b", res_a[4]);
passed = 1\'b0;
end
res_a[1] = 1\'bx;
res_a[2] = 1\'bx;
res_a[3] = 1\'bx;
res_a[4] = 1\'bx;
res_a[s1] = 1\'b0;
if (res_a[1] !== 1\'bx) begin
$display("Failed res_a[s1], expected 1\'bx for [1], got %b", res_a[1]);
passed = 1\'b0;
end
if (res_a[2] !== 1\'bx) begin
$display("Failed res_a[s1], expected 1\'bx for [2], got %b", res_a[2]);
passed = 1\'b0;
end
if (res_a[3] !== 1\'bx) begin
$display("Failed res_a[s1], expected 1\'bx for [3], got %b", res_a[3]);
passed = 1\'b0;
end
if (res_a[4] !== 1\'bx) begin
$display("Failed res_a[s1], expected 1\'bx for [4], got %b", res_a[4]);
passed = 1\'b0;
end
res_a[1] = 1\'bx;
res_a[2] = 1\'bx;
res_a[3] = 1\'bx;
res_a[4] = 1\'bx;
res_a[s2] = 1\'b0;
if (res_a[1] !== 1\'bx) begin
$display("Failed res_a[s2], expected 1\'bx for [1], got %b", res_a[1]);
passed = 1\'b0;
end
if (res_a[2] !== 1\'bx) begin
$display("Failed res_a[s2], expected 1\'bx for [2], got %b", res_a[2]);
passed = 1\'b0;
end
if (res_a[3] !== 1\'bx) begin
$display("Failed res_a[s2], expected 1\'bx for [3], got %b", res_a[3]);
passed = 1\'b0;
end
if (res_a[4] !== 1\'bx) begin
$display("Failed res_a[s2], expected 1\'bx for [4], got %b", res_a[4]);
passed = 1\'b0;
end
res_c[-3] = 1\'bx;
res_c[-2] = 1\'bx;
res_c[-1] = 1\'bx;
res_c[0] = 1\'bx;
res_c[s3] = 1\'b0;
if (res_c[-3] !== 1\'bx) begin
$display("Failed res_c[s3], expected 1\'bx for [-3], got %b", res_c[-3]);
passed = 1\'b0;
end
if (res_c[-2] !== 1\'bx) begin
$display("Failed res_c[s3], expected 1\'bx for [-2], got %b", res_c[-2]);
passed = 1\'b0;
end
if (res_c[-1] !== 1\'bx) begin
$display("Failed res_c[s3], expected 1\'bx for [-1], got %b", res_c[-1]);
passed = 1\'b0;
end
if (res_c[0] !== 1\'b0) begin
$display("Failed res_c[s3], expected 1\'b0 for [0], got %b", res_c[0]);
passed = 1\'b0;
end
res_c[-3] = 1\'bx;
res_c[-2] = 1\'bx;
res_c[-1] = 1\'bx;
res_c[0] = 1\'bx;
res_c[s4] = 1\'b0;
if (res_c[-3] !== 1\'bx) begin
$display("Failed res_c[s4], expected 1\'bx for [-3], got %b", res_c[-3]);
passed = 1\'b0;
end
if (res_c[-2] !== 1\'bx) begin
$display("Failed res_c[s4], expected 1\'bx for [-2], got %b", res_c[-2]);
passed = 1\'b0;
end
if (res_c[-1] !== 1\'bx) begin
$display("Failed res_c[s4], expected 1\'bx for [-1], got %b", res_c[-1]);
passed = 1\'b0;
end
if (res_c[0] !== 1\'b0) begin
$display("Failed res_c[s4], expected 1\'b0 for [0], got %b", res_c[0]);
passed = 1\'b0;
end
if (passed) $display("Compare tests passed");
end
endmodule
|
module lvl3;
reg [1:0] m[1:0];
initial begin
\tfork: my_fork
\t repeat (1) begin
\t\tm[0] = 2'b0;
\t end
\t repeat (1) begin
\t\tm[1] = 2'b1;
\t end
\tjoin
end
endmodule
module lvl2_0;
reg r;
initial r = $random;
lvl3 lvl3();
endmodule
module lvl1_0;
reg r;
function f_foo;
\tinput bar;
begin
\tf_foo = bar;
end
endfunction
initial r = f_foo(r);
lvl2_0 lvl2();
endmodule
module top0;
reg r;
task t_bar;
\tr = 1'b0;
endtask
initial begin: my_init
\tr = $random;
\tt_bar;
end
lvl1_0 lvl1();
endmodule
module lvl2_1;
integer i;
initial i = $random;
lvl3 lvl3();
endmodule
module lvl1_1;
integer i;
initial i = $random;
lvl2_1 lvl2();
endmodule
module top1;
integer i;
initial i = $random;
lvl1_1 lvl1();
endmodule
module top2;
initial $test;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: readmemh function - Check that MEMNAME [ 0:x] caught as compile error
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
/* pre init the array to all zeroes. */
$readmemh("ivltests/readmemh1.dat",array [0:7]);
end
endmodule
|
/*
* Copyright (c) 2003 Michael Ruff (mruff @ chiaro.com)
*
* This source code is free software; rou can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at rour option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* $Id: real3.v,v 1.1 2003/03/07 05:29:41 stevewilliams Exp $
*/
/*
* Verifies some real values to make sure the real->double conversion
* is properly handled and the values make it into vvp properly.
*
* http://babbage.cs.qc.edu/courses/cs341/IEEE-754.html
*
*/
module main;
real r;
reg errors;
initial begin
errors = 0;
r = 1.0;
if ($realtobits(r) != 64\'h3FF0000000000000) begin
\t $display("%f != \'h%h", r, $realtobits(r));
\t $display("FAIL");
\t errors = 1;
end
r = 1.1;
if ($realtobits(r) != 64\'h3FF199999999999a) begin
\t $display("%f != \'h%h", r, $realtobits(r));
\t $display("FAIL");
\t errors = 1;
end
r = 3.3;
if ($realtobits(r) != 64\'h400A666666666666) begin
\t $display("%f != \'h%h", r, $realtobits(r));
\t $display("FAIL");
\t errors = 1;
end
r = 5.5;
if ($realtobits(r) != 64\'h4016000000000000) begin
\t $display("%f != \'h%h", r, $realtobits(r));
\t $display("FAIL");
\t errors = 1;
end
r = 1.0000000000_0000000001;
if ($realtobits(r) != 64\'h3FF0000000000000) begin
\t $display("%f != \'h%h", r, $realtobits(r));
\t $display("FAIL");
\t errors = 1;
end
r = 3.1415926535_8979323846;
if ($realtobits(r) != 64\'h400921FB54442D18) begin
\t $display("%f != \'h%h", r, $realtobits(r));
\t $display("FAIL");
\t errors = 1;
end
r = 1234567890_1234567890.1;
if ($realtobits(r) != 64\'h43E56A95319D63E1) begin
\t $display("%f != \'h%h", r, $realtobits(r));
\t $display("FAIL");
\t errors = 1;
end
if (errors === 0) $display("PASSED");
end
endmodule
|
/*
* In this example, the set and clr are both synchronous. This checks
* that this complex case is handled correctly.
*/
module main;
reg\t Q, clk, rst, set, clr;
(* ivl_synthesis_on *)
always@(posedge clk or posedge rst)
begin
\tif (rst)
\t Q <= 1\'b0;
\telse if (set)
\t Q <= 1\'b1;
\telse if (clr)
\t Q <= 1\'b0;
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
rst = 0;
set = 0;
clr = 0;
#1 rst = 1;
#1 rst = 0;
if (Q !== 0) begin
\t $display("FAILED -- rst");
\t $finish;
end
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
\t $display("FAILED -- 1 clk");
\t $finish;
end
#1 set = 1;
#1 ;
if (Q !== 0) begin
\t $display("FAILED -- 1 set (no clk)");
\t $finish;
end
#1 clk = 1;
#1 clk = 0;
if (Q !== 1) begin
\t $display("FAILED -- 1 set");
\t $finish;
end
#1 clr = 1;
#1 ;
if (Q !== 1) begin
\t $display("FAILED -- 1 clr+set (no clk)");
\t $finish;
end
#1 clk = 1;
#1 clk = 0;
if (Q !== 1) begin
\t $display("FAILED -- 1 clr+set");
\t $finish;
end
#1 clk = 1;
#1 clk = 0;
if (Q !== 1) begin
\t $display("FAILED -- 2 clr+set");
\t $finish;
end
#1 set = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
\t $display("FAILED -- 1 clr-set");
\t $finish;
end
#1 clr = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
\t $display("FAILED -- 1 set-clr");
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule
|
// Check that a queue return type is supported for functions
module test;
typedef int Q[$];
// Since this is not an automatic function calling this repeatetly will
// append to the same queue.
function Q f1(int x);
f1.push_back(1 + x);
f1.push_back(2 + x);
endfunction
// Since this function is automatic a new queue will be created each time it
// is called.
function automatic Q f2(int x);
f2.push_back(1 + x);
f2.push_back(2 + x);
endfunction
initial begin
Q a, b, c, d;
a = f1(0);
// `a` should be a copy and not affected by the second call
b = f1(2);
c = f2(0);
d = f2(2);
if (a.size() == 2 && a[0] == 1 && a[1] == 2 &&
b.size() == 4 && b[0] == 1 && b[1] == 2 && b[2] == 3 && b[3] == 4 &&
c.size() == 2 && c[0] == 1 && c[1] == 2 &&
d.size() == 2 && d[0] == 3 && d[1] == 4) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
// Check that it is an error to declare a non-ANSI task port with implicit
// packed dimensions if it is later redeclared as a packed array typed variable.
// Even if the size of the packed dimensions matches that of the size of the
// packed array.
typedef reg [7:0] T1;
typedef T1 [3:0] T2;
module test;
task t;
input [31:0] x;
T2 x;
$display("FAILED");
endtask
initial t(10);
endmodule
|
module pr3064375;
reg\t\tCLK;
reg\t\tRST;
reg\t\tReg1;
reg\t\tReg2;
initial begin
CLK = 0;
forever begin
#5 CLK = 1;
#5 CLK = 0;
end
end
initial begin
RST = 1;
#20;
RST = 0;
#101;
$finish(0);
end
always @(posedge CLK or posedge RST) begin
if (RST)
Reg1 <= 0;
else
Reg1 <= !Reg1;
end
always @(negedge CLK or posedge RST) begin
if (RST)
Reg2 <= 0;
else
Reg2 <= Reg1;
end
initial begin
$monitor("CLK %b RST %b Reg1 %b Reg2 %b", CLK, RST, Reg1, Reg2);
end
endmodule
|
`begin_keywords "1364-2005"
// pr1745005
//
module main;
reg [31:0] ref;
reg [3:0] addr;
wire [3:0] out_net1 = ref[{addr,2\'b00} +: 4];
wire [3:0] out_net2 = ref[{addr,2\'b11} -: 4];
reg [3:0] out_reg;
initial begin
ref = 32\'h76543210;
for (addr = 0 ; addr < 8 ; addr = addr+1) begin
\t #1 ;
\t out_reg = ref[{addr,2\'b00} +: 4];
\t if (out_reg !== addr) begin
\t $display("FAILED -- addr=%d, out_reg=%b", addr, out_reg);
\t $finish;
\t end
\t if (out_net1 !== addr) begin
\t $display("FAILED -- addr=%d, out_net1=%b", addr, out_net1);
\t $finish;
\t end
\t if (out_net2 !== addr) begin
\t $display("FAILED -- addr=%d, out_net2=%b", addr, out_net2);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule
`end_keywords
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always repeat (expression) statement ;
module main ;
reg [3:0] value1,value2,value3;
initial
\tbegin
value1 = 0;\t\t// Time 0 assignemnt
value2 = 0;
#6 ;
if(value1 != 4\'h1)
begin
$display("FAILED - 3.1.7B always forever (1) ");
value2 = 1;
end
#5 ;
if(value1 != 4\'h2)
begin
$display("FAILED - 3.1.7B always forever (2) ");
value2 = 1;
end
#5 ;
if(value1 != 4\'h3)
begin
$display("FAILED - 3.1.7B always forever (3) ");
value2 = 1;
end
if(value2 == 0)
$display("PASSED");
\t $finish;
end
always repeat(3) begin
#5 ;
value1 = value1 + 1;
end
endmodule
|
// Test implicit casts during module input assignments.
`ifdef __ICARUS__
`define SUPPORT_REAL_NETS_IN_IVTEST
`define SUPPORT_TWO_STATE_NETS_IN_IVTEST
`endif
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
module cp_r(output wire real dst,
input wire real src);
assign dst = src;
endmodule
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
module cp_u2s(output wire bit unsigned [3:0] dst,
input wire bit unsigned [3:0] src);
assign dst = src;
endmodule
module cp_s2s(output wire bit signed [3:0] dst,
input wire bit signed [3:0] src);
assign dst = src;
endmodule
module cp_u2l(output wire bit unsigned [11:0] dst,
input wire bit unsigned [11:0] src);
assign dst = src;
endmodule
module cp_s2l(output wire bit signed [11:0] dst,
input wire bit signed [11:0] src);
assign dst = src;
endmodule
`endif
module cp_u4s(output wire logic unsigned [3:0] dst,
input wire logic unsigned [3:0] src);
assign dst = src;
endmodule
module cp_s4s(output wire logic signed [3:0] dst,
input wire logic signed [3:0] src);
assign dst = src;
endmodule
module cp_u4l(output wire logic unsigned [11:0] dst,
input wire logic unsigned [11:0] src);
assign dst = src;
endmodule
module cp_s4l(output wire logic signed [11:0] dst,
input wire logic signed [11:0] src);
assign dst = src;
endmodule
module implicit_cast();
real src_r;
bit unsigned [7:0] src_u2;
bit signed [7:0] src_s2;
logic unsigned [7:0] src_u4;
logic signed [7:0] src_s4;
logic unsigned [7:0] src_ux;
logic signed [7:0] src_sx;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
wire real dst1_r;
wire real dst2_r;
wire real dst3_r;
wire real dst4_r;
wire real dst5_r;
wire real dst6_r;
wire real dst7_r;
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
wire bit unsigned [3:0] dst1_u2s;
wire bit unsigned [3:0] dst2_u2s;
wire bit unsigned [3:0] dst3_u2s;
wire bit unsigned [3:0] dst4_u2s;
wire bit unsigned [3:0] dst5_u2s;
wire bit unsigned [3:0] dst6_u2s;
wire bit unsigned [3:0] dst7_u2s;
wire bit signed [3:0] dst1_s2s;
wire bit signed [3:0] dst2_s2s;
wire bit signed [3:0] dst3_s2s;
wire bit signed [3:0] dst4_s2s;
wire bit signed [3:0] dst5_s2s;
wire bit signed [3:0] dst6_s2s;
wire bit signed [3:0] dst7_s2s;
wire bit unsigned [11:0] dst1_u2l;
wire bit unsigned [11:0] dst2_u2l;
wire bit unsigned [11:0] dst3_u2l;
wire bit unsigned [11:0] dst4_u2l;
wire bit unsigned [11:0] dst5_u2l;
wire bit unsigned [11:0] dst6_u2l;
wire bit unsigned [11:0] dst7_u2l;
wire bit signed [11:0] dst1_s2l;
wire bit signed [11:0] dst2_s2l;
wire bit signed [11:0] dst3_s2l;
wire bit signed [11:0] dst4_s2l;
wire bit signed [11:0] dst5_s2l;
wire bit signed [11:0] dst6_s2l;
wire bit signed [11:0] dst7_s2l;
`endif
wire logic unsigned [3:0] dst1_u4s;
wire logic unsigned [3:0] dst2_u4s;
wire logic unsigned [3:0] dst3_u4s;
wire logic unsigned [3:0] dst4_u4s;
wire logic unsigned [3:0] dst5_u4s;
wire logic unsigned [3:0] dst6_u4s;
wire logic unsigned [3:0] dst7_u4s;
wire logic signed [3:0] dst1_s4s;
wire logic signed [3:0] dst2_s4s;
wire logic signed [3:0] dst3_s4s;
wire logic signed [3:0] dst4_s4s;
wire logic signed [3:0] dst5_s4s;
wire logic signed [3:0] dst6_s4s;
wire logic signed [3:0] dst7_s4s;
wire logic unsigned [11:0] dst1_u4l;
wire logic unsigned [11:0] dst2_u4l;
wire logic unsigned [11:0] dst3_u4l;
wire logic unsigned [11:0] dst4_u4l;
wire logic unsigned [11:0] dst5_u4l;
wire logic unsigned [11:0] dst6_u4l;
wire logic unsigned [11:0] dst7_u4l;
wire logic signed [11:0] dst1_s4l;
wire logic signed [11:0] dst2_s4l;
wire logic signed [11:0] dst3_s4l;
wire logic signed [11:0] dst4_s4l;
wire logic signed [11:0] dst5_s4l;
wire logic signed [11:0] dst6_s4l;
wire logic signed [11:0] dst7_s4l;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
cp_r cp1_r(dst1_r, src_r);
cp_r cp2_r(dst2_r, src_u2);
cp_r cp3_r(dst3_r, src_s2);
cp_r cp4_r(dst4_r, src_u4);
cp_r cp5_r(dst5_r, src_s4);
cp_r cp6_r(dst6_r, src_ux);
cp_r cp7_r(dst7_r, src_sx);
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
cp_u2s cp1_u2s(dst1_u2s, src_r);
cp_u2s cp2_u2s(dst2_u2s, src_u2);
cp_u2s cp3_u2s(dst3_u2s, src_s2);
cp_u2s cp4_u2s(dst4_u2s, src_u4);
cp_u2s cp5_u2s(dst5_u2s, src_s4);
cp_u2s cp6_u2s(dst6_u2s, src_ux);
cp_u2s cp7_u2s(dst7_u2s, src_sx);
cp_s2s cp1_s2s(dst1_s2s, src_r);
cp_s2s cp2_s2s(dst2_s2s, src_u2);
cp_s2s cp3_s2s(dst3_s2s, src_s2);
cp_s2s cp4_s2s(dst4_s2s, src_u4);
cp_s2s cp5_s2s(dst5_s2s, src_s4);
cp_s2s cp6_s2s(dst6_s2s, src_ux);
cp_s2s cp7_s2s(dst7_s2s, src_sx);
cp_u2l cp1_u2l(dst1_u2l, src_r);
cp_u2l cp2_u2l(dst2_u2l, src_u2);
cp_u2l cp3_u2l(dst3_u2l, src_s2);
cp_u2l cp4_u2l(dst4_u2l, src_u4);
cp_u2l cp5_u2l(dst5_u2l, src_s4);
cp_u2l cp6_u2l(dst6_u2l, src_ux);
cp_u2l cp7_u2l(dst7_u2l, src_sx);
cp_s2l cp1_s2l(dst1_s2l, src_r);
cp_s2l cp2_s2l(dst2_s2l, src_u2);
cp_s2l cp3_s2l(dst3_s2l, src_s2);
cp_s2l cp4_s2l(dst4_s2l, src_u4);
cp_s2l cp5_s2l(dst5_s2l, src_s4);
cp_s2l cp6_s2l(dst6_s2l, src_ux);
cp_s2l cp7_s2l(dst7_s2l, src_sx);
`endif
cp_u4s cp1_u4s(dst1_u4s, src_r);
cp_u4s cp2_u4s(dst2_u4s, src_u2);
cp_u4s cp3_u4s(dst3_u4s, src_s2);
cp_u4s cp4_u4s(dst4_u4s, src_u4);
cp_u4s cp5_u4s(dst5_u4s, src_s4);
cp_u4s cp6_u4s(dst6_u4s, src_ux);
cp_u4s cp7_u4s(dst7_u4s, src_sx);
cp_s4s cp1_s4s(dst1_s4s, src_r);
cp_s4s cp2_s4s(dst2_s4s, src_u2);
cp_s4s cp3_s4s(dst3_s4s, src_s2);
cp_s4s cp4_s4s(dst4_s4s, src_u4);
cp_s4s cp5_s4s(dst5_s4s, src_s4);
cp_s4s cp6_s4s(dst6_s4s, src_ux);
cp_s4s cp7_s4s(dst7_s4s, src_sx);
cp_u4l cp1_u4l(dst1_u4l, src_r);
cp_u4l cp2_u4l(dst2_u4l, src_u2);
cp_u4l cp3_u4l(dst3_u4l, src_s2);
cp_u4l cp4_u4l(dst4_u4l, src_u4);
cp_u4l cp5_u4l(dst5_u4l, src_s4);
cp_u4l cp6_u4l(dst6_u4l, src_ux);
cp_u4l cp7_u4l(dst7_u4l, src_sx);
cp_s4l cp1_s4l(dst1_s4l, src_r);
cp_s4l cp2_s4l(dst2_s4l, src_u2);
cp_s4l cp3_s4l(dst3_s4l, src_s2);
cp_s4l cp4_s4l(dst4_s4l, src_u4);
cp_s4l cp5_s4l(dst5_s4l, src_s4);
cp_s4l cp6_s4l(dst6_s4l, src_ux);
cp_s4l cp7_s4l(dst7_s4l, src_sx);
bit failed;
initial begin
failed = 0;
src_r = -7;
src_u2 = 7;
src_s2 = -7;
src_u4 = 7;
src_s4 = -7;
src_ux = 8\'bx0z00111;
src_sx = 8\'bx0z00111;
#1;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
$display("cast to real");
$display("%g", dst1_r); if (dst1_r != -7.0) failed = 1;
$display("%g", dst2_r); if (dst2_r != 7.0) failed = 1;
$display("%g", dst3_r); if (dst3_r != -7.0) failed = 1;
$display("%g", dst4_r); if (dst4_r != 7.0) failed = 1;
$display("%g", dst5_r); if (dst5_r != -7.0) failed = 1;
$display("%g", dst6_r); if (dst6_r != 7.0) failed = 1;
$display("%g", dst7_r); if (dst7_r != 7.0) failed = 1;
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
$display("cast to small unsigned bit");
$display("%d", dst1_u2s); if (dst1_u2s !== 4\'d9) failed = 1;
$display("%d", dst2_u2s); if (dst2_u2s !== 4\'d7) failed = 1;
$display("%d", dst3_u2s); if (dst3_u2s !== 4\'d9) failed = 1;
$display("%d", dst4_u2s); if (dst4_u2s !== 4\'d7) failed = 1;
$display("%d", dst5_u2s); if (dst5_u2s !== 4\'d9) failed = 1;
$display("%d", dst6_u2s); if (dst6_u2s !== 4\'d7) failed = 1;
$display("%d", dst7_u2s); if (dst7_u2s !== 4\'d7) failed = 1;
$display("cast to small signed bit");
$display("%d", dst1_s2s); if (dst1_s2s !== -4\'sd7) failed = 1;
$display("%d", dst2_s2s); if (dst2_s2s !== 4\'sd7) failed = 1;
$display("%d", dst3_s2s); if (dst3_s2s !== -4\'sd7) failed = 1;
$display("%d", dst4_s2s); if (dst4_s2s !== 4\'sd7) failed = 1;
$display("%d", dst5_s2s); if (dst5_s2s !== -4\'sd7) failed = 1;
$display("%d", dst6_s2s); if (dst6_s2s !== 4\'sd7) failed = 1;
$display("%d", dst7_s2s); if (dst7_s2s !== 4\'sd7) failed = 1;
$display("cast to large unsigned bit");
$display("%d", dst1_u2l); if (dst1_u2l !== 12\'d4089) failed = 1;
$display("%d", dst2_u2l); if (dst2_u2l !== 12\'d7) failed = 1;
$display("%d", dst3_u2l); if (dst3_u2l !== 12\'d4089) failed = 1;
$display("%d", dst4_u2l); if (dst4_u2l !== 12\'d7) failed = 1;
$display("%d", dst5_u2l); if (dst5_u2l !== 12\'d4089) failed = 1;
$display("%b", dst6_u2l); if (dst6_u2l !== 12\'b000000000111) failed = 1;
$display("%b", dst7_u2l); if (dst7_u2l !== 12\'b000000000111) failed = 1;
$display("cast to large signed bit");
$display("%d", dst1_s2l); if (dst1_s2l !== -12\'sd7) failed = 1;
$display("%d", dst2_s2l); if (dst2_s2l !== 12\'sd7) failed = 1;
$display("%d", dst3_s2l); if (dst3_s2l !== -12\'sd7) failed = 1;
$display("%d", dst4_s2l); if (dst4_s2l !== 12\'sd7) failed = 1;
$display("%d", dst5_s2l); if (dst5_s2l !== -12\'sd7) failed = 1;
$display("%b", dst6_s2l); if (dst6_s2l !== 12\'b000000000111) failed = 1;
$display("%b", dst7_s2l); if (dst7_s2l !== 12\'b000000000111) failed = 1;
`endif
$display("cast to small unsigned logic");
$display("%d", dst1_u4s); if (dst1_u4s !== 4\'d9) failed = 1;
$display("%d", dst2_u4s); if (dst2_u4s !== 4\'d7) failed = 1;
$display("%d", dst3_u4s); if (dst3_u4s !== 4\'d9) failed = 1;
$display("%d", dst4_u4s); if (dst4_u4s !== 4\'d7) failed = 1;
$display("%d", dst5_u4s); if (dst5_u4s !== 4\'d9) failed = 1;
$display("%d", dst6_u4s); if (dst6_u4s !== 4\'d7) failed = 1;
$display("%d", dst7_u4s); if (dst7_u4s !== 4\'d7) failed = 1;
$display("cast to small signed logic");
$display("%d", dst1_s4s); if (dst1_s4s !== -4\'sd7) failed = 1;
$display("%d", dst2_s4s); if (dst2_s4s !== 4\'sd7) failed = 1;
$display("%d", dst3_s4s); if (dst3_s4s !== -4\'sd7) failed = 1;
$display("%d", dst4_s4s); if (dst4_s4s !== 4\'sd7) failed = 1;
$display("%d", dst5_s4s); if (dst5_s4s !== -4\'sd7) failed = 1;
$display("%d", dst6_s4s); if (dst6_s4s !== 4\'sd7) failed = 1;
$display("%d", dst7_s4s); if (dst7_s4s !== 4\'sd7) failed = 1;
$display("cast to large unsigned logic");
$display("%d", dst1_u4l); if (dst1_u4l !== 12\'d4089) failed = 1;
$display("%d", dst2_u4l); if (dst2_u4l !== 12\'d7) failed = 1;
$display("%d", dst3_u4l); if (dst3_u4l !== 12\'d4089) failed = 1;
$display("%d", dst4_u4l); if (dst4_u4l !== 12\'d7) failed = 1;
$display("%d", dst5_u4l); if (dst5_u4l !== 12\'d4089) failed = 1;
$display("%b", dst6_u4l); if (dst6_u4l !== 12\'b0000x0z00111) failed = 1;
$display("%b", dst7_u4l); if (dst7_u4l !== 12\'bxxxxx0z00111) failed = 1;
$display("cast to large signed logic");
$display("%d", dst1_s4l); if (dst1_s4l !== -12\'sd7) failed = 1;
$display("%d", dst2_s4l); if (dst2_s4l !== 12\'sd7) failed = 1;
$display("%d", dst3_s4l); if (dst3_s4l !== -12\'sd7) failed = 1;
$display("%d", dst4_s4l); if (dst4_s4l !== 12\'sd7) failed = 1;
$display("%d", dst5_s4l); if (dst5_s4l !== -12\'sd7) failed = 1;
$display("%b", dst6_s4l); if (dst6_s4l !== 12\'b0000x0z00111) failed = 1;
$display("%b", dst7_s4l); if (dst7_s4l !== 12\'bxxxxx0z00111) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Check that it is possible to declare the data type for a string type task
// port separately from the direction for non-ANSI style port declarations.
module test;
task t;
input x;
string x;
if (x == "TEST") begin
$display("PASSED");
end else begin
$display("FAILED");
end
endtask
initial t("TEST");
endmodule
|
module test_mux
(input wire [1:0] D0, D1,
input wire S,
output wire [1:0] Q);
assign Q = S? D1 : D0;
endmodule // test_mux
|
module test();
wire [3:0] a = 4\'d0;
wire signed [3:0] b[1:0];
assign b[0] = $signed(a);
initial begin
$display("b = [%b %b]", b[1], b[0]);
end
endmodule
|
/*
* This example is a distillation of the essence of PR#993.
* Or at least the essence that led to a bug report.
*/
module main;
integer length;
wire [31:0] length_bits = ((length * 8 )/11)+(((length * 8 )%11) != 0);
reg [31:0] length_bits2;
initial begin
for (length = 1 ; length < 56 ; length = length + 1) begin
\t length_bits2 = ((length * 8 )/11)+(((length * 8 )%11) != 0);
\t #1 $display("length=%3d, length_bits=%3d (%3d)",
\t\t length, length_bits, length_bits2);
\t if (length_bits != length_bits2) begin
\t $display("FAILED - Expressions have different results.");
\t $finish;
\t end
end // for (length = 1 ; length < 56 ; length = length + 1)
$finish(0);
end
endmodule // main
|
module cmpN
#(parameter WID = 4)
(input wire [WID-1:0] A,
input wire [WID-1:0] B,
output reg QE, QN, QGT, QGE
/* */);
always @(A, B)
if (A > B) begin
\t QE = 0;
\t QN = 1;
\t QGT = 1;
\t QGE = 1;
end else if (A == B) begin
\t QE = 1;
\t QN = 0;
\t QGT = 0;
\t QGE = 1;
end else begin
\t QE = 0;
\t QN = 1;
\t QGT = 0;
\t QGE = 0;
end
endmodule // add
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Compound ifdef test with else, exterior define
//
module ifdef1;
reg error ;
`ifdef DOUBLE
initial
begin
#20;
error = 1;
#20;
end
`else
`ifdef NOCODE
initial
begin
#20;
error = 1;
#20;
end
`else
initial
begin
#20;
error = 0;
#20;
end
`endif
`endif
initial
begin
#1;
error = 1;
#40;
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
// pr1831724
module test;
reg [15:0] tmp1, tmp2;
initial
begin
\ttmp1 = 9\'bxxx000000;
\ttmp2 = {9\'bxxx000000};
\t$display("tmp1: \'%b\'; tmp2: \'%b\'", tmp1, tmp2);
end
endmodule
|
module top;
reg pass;
enum bit signed [7:0] {a = 1, b = 2, c = 3, d = 4} enum_var;
initial begin
pass = 1\'b1;
// Add another test that a negative value is not valid.
// Also an out of range value stays out of range.
enum_var = a;
if (enum_var !== enum_var.first) begin
$display("FAILED: initialization, expected %d, got %d", a, enum_var);
pass = 1\'b0;
end
enum_var = enum_var.next;
enum_var = enum_var.prev;
enum_var = enum_var.next();
if (enum_var !== b) begin
$display("FAILED: next(), expected %d, got %d", b, enum_var);
pass = 1\'b0;
end
enum_var = enum_var.next(0);
if (enum_var !== b) begin
$display("FAILED: next(0), expected %d, got %d", b, enum_var);
pass = 1\'b0;
end
enum_var = enum_var.next(1);
if (enum_var !== c) begin
$display("FAILED: next(1), expected %d, got %d", c, enum_var);
pass = 1\'b0;
end
enum_var = enum_var.next(2);
if (enum_var !== a) begin
$display("FAILED: next(2), expected %d, got %d", a, enum_var);
pass = 1\'b0;
end
enum_var = enum_var.prev();
if (enum_var !== d) begin
$display("FAILED: prev(), expected %d, got %d", d, enum_var);
pass = 1\'b0;
end
enum_var = enum_var.prev(0);
if (enum_var !== d) begin
$display("FAILED: prev(0), expected %d, got %d", d, enum_var);
pass = 1\'b0;
end
enum_var = enum_var.prev(1);
if (enum_var !== c) begin
$display("FAILED: prev(1), expected %d, got %d", c, enum_var);
pass = 1\'b0;
end
enum_var = enum_var.prev(2);
if (enum_var !== a) begin
$display("FAILED: prev(2), expected %d, got %d", a, enum_var);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2000 Intrinsity, Inc.
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test_nmos ();
wire t0, t1, t2, t3, t4, t5, t6, t7,
t8, t9, ta, tb, tc, td, te, tf;
reg gnd, vdd, x, z;
reg failed;
wire StH, StL;
assign (strong1, highz0) StH = 1\'bx;
assign (highz1, strong0) StL = 1\'bx;
nmos n0 ( t0, gnd, gnd);
nmos n1 ( t1, gnd, vdd);
nmos n2 ( t2, gnd, x);
nmos n3 ( t3, gnd, z);
nmos n4 ( t4, vdd, gnd);
nmos n5 ( t5, vdd, vdd);
nmos n6 ( t6, vdd, x);
nmos n7 ( t7, vdd, z);
nmos n8 ( t8, x, gnd);
nmos n9 ( t9, x, vdd);
nmos na ( ta, x, x);
nmos nb ( tb, x, z);
nmos nc ( tc, z, gnd);
nmos nd ( td, z, vdd);
nmos ne ( te, z, x);
nmos nf ( tf, z, z);
initial begin
assign gnd = 1\'b1;
assign vdd = 1\'b0;
assign x = 1\'b0;
assign z = 1\'b0;
#10;
assign gnd = 1\'b0;
assign vdd = 1\'b1;
assign x = 1\'b1;
assign z = 1\'b1;
#10;
assign gnd = 1\'b0;
assign vdd = 1\'b1;
assign x = 1\'bx;
assign z = 1\'bz;
#10;
failed = 0;
if (t0 !== z)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", gnd, gnd, t0 );
end
if (t1 !== 0)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:0", gnd, vdd, t1 );
end
if (t2 !== StL)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StL", gnd, x, t2 );
end
if (t3 !== StL)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StL", gnd, z, t3 );
end
if (t4 !== 1\'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", vdd, gnd, t4 );
end
if (t5 !== 1)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:0", vdd, vdd, t5 );
end
if (t6 !== StH)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StH", vdd, x, t6 );
end
if (t7 !== StH)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StH", vdd, z, t7 );
end
if (t8 !== 1\'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", x, gnd, t8 );
end
if (t9 !== 1\'bx)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, vdd, t9 );
end
if (ta !== 1\'bx)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, x, ta );
end
if (tb !== 1\'bx)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, z, tb );
end
if (tc !== 1\'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, gnd, tc );
end
if (td !== 1\'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, vdd, td );
end
if (te !== 1\'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, x, te );
end
if (tf !== 1\'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, z, tf );
end
if (failed == 0)
$display ("PASSED");
end
endmodule
|
/* pr1623097 */
`timescale 1ns/1ns
module top;
reg [3:0] state;
reg [3:0] data;
reg [3:0] clear;
reg clk;
genvar i;
initial begin
#0; // avoid time-0 race
clk = 0; data = 4\'b1111; clear = 4\'b1111;
$monitor($time,,"clk=%b, data=%b, clear=%b, state=%b",
\t clk, data, clear, state);
#10 clear = 4\'b0000;
#10 clk = 1;
#10 clk = 0; clear = 4\'b0010;
#10 clear = 4\'b0000; data = 4\'b1010;
#10 clk = 1;
#10 clk = 0;
end
// This fails!
generate for (i=0; i<4; i=i+1) begin:sm
always @(posedge clk or posedge clear[i]) begin
if (clear[i]) state[i] <= 1\'b0; // Async. clear the flip bit.
else begin
state[i] <= #1 data[i];
end
end
end endgenerate
endmodule
|
primitive passthrough (o, i);
input i;
output o;
table
// i : o
1 : 1;
0 : 0;
? : 0;
endtable
endprimitive
module test;
reg i;
wire o1, o1b, o2, o2b;
initial begin
i = 1\'b0;
#1;
if ((o1 !== 1\'b0) && (o1b !== 1\'b1) &&
(o2 !== 1\'b0) && (o2b !== 1\'b1)) $display("FAILED");
else $display("PASSED");
end
passthrough (o1, i);
passthrough (o1b, !i);
passthrough (o2, i);
passthrough (o2b, ~i);
endmodule
|
module top_module(
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[N:0] = Array[0][7:1];
end
endmodule
|
module top;
reg passed;
reg signed[31:0] m_one, m_two, zero, one, two;
// Both argument positive.
reg signed[31:0] rem;
wire signed[31:0] wrem = two / one;
// First argument negative.
reg signed[31:0] rem1n;
wire signed[31:0] wrem1n = m_two / one;
// Second argument negative.
reg signed[31:0] rem2n;
wire signed[31:0] wrem2n = two / m_one;
// Both arguments negative.
reg signed[31:0] rembn;
wire signed[31:0] wrembn = m_two / m_one;
// Divide by zero.
reg signed[31:0] remd0;
wire signed[31:0] wremd0 = one / zero;
initial begin
passed = 1\'b1;
m_one = 32\'hffffffff;
m_two = 32\'hfffffffe;
zero = 32\'h00000000;
one = 32\'h00000001;
two = 32\'h00000002;
#1;
// Both positive.
if (wrem !== 32\'h00000002) begin
$display("Failed: CA divide, expected 32\'h00...02, got %h",
wrem);
passed = 1\'b0;
end
rem = two / one;
if (rem !== 32\'h00000002) begin
$display("Failed: divide, expected 32\'h00...02, got %h",
rem);
passed = 1\'b0;
end
// First negative.
if (wrem1n !== 32\'hfffffffe) begin
$display("Failed: CA divide (1n), expected 32\'hff...fe, got %h",
wrem1n);
passed = 1\'b0;
end
rem1n = m_two / one;
if (rem1n !== 32\'hfffffffe) begin
$display("Failed: divide (1n), expected 32\'hff...fe, got %h",
rem1n);
passed = 1\'b0;
end
// Second negative.
if (wrem2n !== 32\'hfffffffe) begin
$display("Failed: CA divide (2n), expected 32\'hff...fe, got %h",
wrem2n);
passed = 1\'b0;
end
rem2n = two / m_one;
if (rem2n !== 32\'hfffffffe) begin
$display("Failed: divide (2n), expected 32\'hff...fe, got %h",
rem2n);
passed = 1\'b0;
end
// Both negative.
if (wrembn !== 32\'h00000002) begin
$display("Failed: CA divide (bn), expected 32\'h00...02, got %h",
wrembn);
passed = 1\'b0;
end
rembn = m_two / m_one;
if (rembn !== 32\'h00000002) begin
$display("Failed: divide (bn), expected 32\'h00...02, got %h",
rembn);
passed = 1\'b0;
end
// Divide by zero.
if (wremd0 !== 32\'hxxxxxxxx) begin
$display("Failed: CA divide (d0), expected 32\'hxx...xx, got %h",
wremd0);
passed = 1\'b0;
end
remd0 = one / zero;
if (remd0 !== 32\'hxxxxxxxx) begin
$display("Failed: divide (d0), expected 32\'hxx...xx, got %h",
remd0);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
// We want to print a warning if we find a delay that comes from the
// default timescale (1s) and then one from a given timescale.
// Basically we want to have either the case of no timescales or
// timescales for all delays.
module wo_time;
reg in;
wire #1 out = in;
initial begin
in = 1\'b1;
#2 $finish(0);
end
always @(out) $display("The time in %m is: %e", $abstime);
endmodule
`timescale 1ns/1ns
module w_time;
reg in;
wire #1 out = in;
initial in = 1\'b1;
always @(out) $display("The time in %m is: %e", $abstime);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary nand ~&(value)
//
module main;
reg [3:0] vect;
reg\terror;
wire\tresult;
assign result = ~&(vect);
initial
begin
error = 0;
for(vect=4\'b000;vect<4\'b1111;vect = vect + 1)
begin
#1;
if(result !== 1\'b1)
begin
$display("FAILED - Unary nand ~&(%b)=%b",vect,result);
error = 1\'b1;
end
end
#1;
vect = 4\'b1111;
#1;
if(result !== 1\'b0)
begin
$display("FAILED - Unary nand ~&(%b)=%b",vect,result);
error = 1\'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for or_reduce/and_reduce functions.
module vhdl_reduce_test;
logic [4:0] inp;
logic and_reduced, or_reduced;
vhdl_reduce test(inp, and_reduced, or_reduced);
initial begin
inp = 5\'b00000;
#1 if(and_reduced !== 1\'b0 || or_reduced !== 1\'b0) begin
$display("FAILED 1");
$finish();
end
inp = 5\'b00010;
#1 if(and_reduced !== 1\'b0 || or_reduced !== 1\'b1) begin
$display("FAILED 2");
$finish();
end
inp = 5\'b11111;
#1 if(and_reduced !== 1\'b1 || or_reduced !== 1\'b1) begin
$display("FAILED 3");
$finish();
end
inp = 5\'bzz1xx;
#1 if(and_reduced !== 1\'bx || or_reduced !== 1\'b1) begin
$display(and_reduced);
$display(or_reduced);
$display("FAILED 4");
$finish();
end
inp = 5\'bzz0xx;
#1 if(and_reduced !== 1\'b0 || or_reduced !== 1\'bx) begin
$display(and_reduced);
$display(or_reduced);
$display("FAILED 5");
$finish();
end
inp = 5\'bzzzxx;
#1 if(and_reduced !== 1\'bx || or_reduced !== 1\'bx) begin
$display(and_reduced);
$display(or_reduced);
$display("FAILED 6");
$finish();
end
$display("PASSED");
end
endmodule
|
/*
* Derived from PR#569
*/
module test();
parameter foo = 8\'b01010101;
parameter bar = {foo,{2{foo}}}; // fails
// parameter tmp = {2{foo}}; // this + next line succeed
// parameter bar = {foo,tmp};
reg[23:0] cnt;
reg CLK;
initial $monitor("%b", cnt);
initial CLK = 0;
initial cnt = bar;
endmodule
|
//
// Copyright (c) 1999 Steve Wilson ([email protected])
// Based on code contributed by Peter Monta ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//\tSDW - Validate XOR op using non-blocking assignment
//
module main;
reg [7:0] a;
reg b;
reg c;
reg error;
initial
begin
#1;
error = 0;
for(a = 0; a <= 8\'h1; a = a + 1)
begin
b = 0;
#1 ;
if(a)
begin
if(!c)
begin
$display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
error = 1;
end
end
if(!a)
begin
if(c)
begin
$display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
error = 1;
end
end
b = 1;
#1 ;
if(!a)
begin
if(!c)
begin
$display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
error = 1;
end
end
if(a)
begin
if(c)
begin
$display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
error = 1;
end
end
end
if(!error)
$display("PASSED");
end
always @(a or b)
c <= a ^ b;
endmodule
|
// Extracted from PR#224
module test;
reg clk;
reg [3:0] ack;
task first;
input [1:0] p;
begin
@(posedge clk); $display("got posedge clk");
`ifdef LINE_A
//A: line below compiles under XL/NC - iverilog complains
\t @(posedge ack[p]); $display("got posedge ack[p]");
`else
//B: line below core dumps under vvp - OK under vvm
@(posedge ack); $display("got posedge ack");
`endif
@(posedge clk); $display("got posedge clk");
\t $display("PASSED");
\t $finish;
end
endtask
initial #5 first(1);
initial
begin
\tack <= 0; clk <= 0;
\t#10 clk <= 1;
\t#10 ack <= 3; clk <= 0;
\t#10 clk <= 1;
\t#10 $display("FAILED");
\t$finish;
end
endmodule // test
|
// This tests assigning value lists to packed arrays
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test ();
// parameters for array sizes
localparam WA = 4;
localparam WB = 4;
// 2D packed arrays
logic [WA-1:0] [WB-1:0] abg0, abg1, abg2, abg3, abg4, abg5, abg6, abg7, abg8, abg9; // big endian array
logic [0:WA-1] [0:WB-1] alt0, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8, alt9; // little endian array
// error counter
bit err = 0;
initial begin
abg0 = \'{ 3 ,2 ,1, 0 };
abg1 = \'{0:4, 1:5, 2:6, 3:7};
abg2 = \'{default:13};
abg3 = \'{2:15, default:13};
abg4 = \'{WA { {WB/2 {2\'b10}} }};
abg5 = \'{WA { {3\'b101, {WB/2-1{2\'b10}}} }};
abg6 = \'{WA { {WB/2-1{2\'b10}} }};
abg7 [WA/2-1:0 ] = \'{WA/2{ {WB/2 {2\'b10}} }};
abg8 [WA -1:WA/2] = \'{WA/2{ {WB/2 {2\'b01}} }};
abg9 = \'{err+0, err+1, err+2, err+3};
// check
if (abg0 !== 16\'b0011_0010_0001_0000) begin $display("FAILED -- abg0 = \'b%b", abg0); err=1; end
if (abg1 !== 16\'b0111_0110_0101_0100) begin $display("FAILED -- abg1 = \'b%b", abg1); err=1; end
if (abg2 !== 16\'b1101_1101_1101_1101) begin $display("FAILED -- abg2 = \'b%b", abg2); err=1; end
if (abg3 !== 16\'b1101_1111_1101_1101) begin $display("FAILED -- abg3 = \'b%b", abg3); err=1; end
if (abg4 !== 16\'b1010_1010_1010_1010) begin $display("FAILED -- abg4 = \'b%b", abg4); err=1; end
if (abg5 !== 16\'b0110_0110_0110_0110) begin $display("FAILED -- abg5 = \'b%b", abg5); err=1; end
if (abg6 !== 16\'b0010_0010_0010_0010) begin $display("FAILED -- abg6 = \'b%b", abg6); err=1; end
if (abg7 !== 16\'bxxxx_xxxx_1010_1010) begin $display("FAILED -- abg7 = \'b%b", abg7); err=1; end
if (abg8 !== 16\'b1010_1010_xxxx_xxxx) begin $display("FAILED -- abg8 = \'b%b", abg8); err=1; end
if (abg9 !== 16\'b0000_0001_0010_0011) begin $display("FAILED -- abg9 = \'b%b", abg9); err=1; end
alt0 = \'{ 3 ,2 ,1, 0 };
alt1 = \'{0:4, 1:5, 2:6, 3:7};
alt2 = \'{default:13};
alt3 = \'{2:15, default:13};
alt4 = \'{WA { {WB/2 {2\'b10}} }};
alt5 = \'{WA { {3\'b101, {WB/2-1{2\'b10}}} }};
alt6 = \'{WA { {WB/2-1{2\'b10}} }};
alt7 [0 :WA/2-1] = \'{WA/2{ {WB/2 {2\'b10}} }};
alt8 [WA/2:WA -1] = \'{WA/2{ {WB/2 {2\'b01}} }};
alt9 = \'{err+0, err+1, err+2, err+3};
// check
if (alt0 !== 16\'b0011_0010_0001_0000) begin $display("FAILED -- alt0 = \'b%b", alt0); err=1; end
if (alt1 !== 16\'b0100_0101_0110_0111) begin $display("FAILED -- alt1 = \'b%b", alt1); err=1; end
if (alt2 !== 16\'b1101_1101_1101_1101) begin $display("FAILED -- alt2 = \'b%b", alt2); err=1; end
if (alt3 !== 16\'b1101_1101_1111_1101) begin $display("FAILED -- alt3 = \'b%b", alt3); err=1; end
if (alt4 !== 16\'b1010_1010_1010_1010) begin $display("FAILED -- alt4 = \'b%b", alt4); err=1; end
if (alt5 !== 16\'b0110_0110_0110_0110) begin $display("FAILED -- alt5 = \'b%b", alt5); err=1; end
if (alt6 !== 16\'b0010_0010_0010_0010) begin $display("FAILED -- alt6 = \'b%b", alt6); err=1; end
if (alt7 !== 16\'b1010_1010_xxxx_xxxx) begin $display("FAILED -- alt7 = \'b%b", alt7); err=1; end
if (alt8 !== 16\'bxxxx_xxxx_1010_1010) begin $display("FAILED -- alt8 = \'b%b", alt8); err=1; end
if (alt9 !== 16\'b0000_0001_0010_0011) begin $display("FAILED -- alt9 = \'b%b", alt9); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
module top;
reg res;
reg [1:0] in;
initial begin
in = 2\'b00;
res = ~ |in;
res = ~ ∈
res = ~ ^in;
$display("FAILED: These expressions should be a syntax error.");
end
endmodule
|
// Trigger breakage of Icarus Verilog CVS 2004-06-18
// $ iverilog netnet.v
// netnet.v:7: internal error: pin(3) out of bounds(3)
// netnet.v:7: : typeid=6NetNet
// ivl: netlist.cc:208: Link &NetObj::pin (unsigned int): Assertion `idx < npins_\' failed.
// $
// Larry Doolittle <[email protected]>
`timescale 1ns / 1ns
module netnet();
reg [2:0] s;
wire s_ones;
assign s_ones = (s==7);
initial begin
s = 3\'b111;
#1 if (s_ones !== 1) begin
$display("FAILED -- %b==7 returns %b", s, s_ones);
$finish;
end
s = 3\'b011;
#1 if (s_ones !== 0) begin
$display("FAILED -- %b==7 returns %b", s, s_ones);
$finish;
end
$display("PASSED");
end
endmodule
|
module main;
reg clk, rst, done;
wire [31:0] x;
reg [3:0] a;
reg [23:0] in, out;
reg [2:0] a_fifo_cam_indices[3:0], lt_fifo_cam_indices[3:0];
// Debug signals to see \'em under signalscan
// -- iverilog generates a warning here
wire [2:0] db0_a_fifo_cam_indices = a_fifo_cam_indices[0];
// generate a clock
always
#10 clk = ~clk;
// -- iverilog generates a warning here
assign x[31:0] = { 28\'hfffffff, (~a[3:0] + 4\'d1) };
initial
begin
$display ("\
<< BEGIN >>");
rst = 1\'b0;
a[3:0] = 4\'b0101;
// -- iverilog internal value is not dealt with correctly (see value
out[23:0] = ( rst ? 24\'o7654_3210 : in[23:0] );
casex ( done )
// -- iverilog generate errors - "could not match signal"
1\'b1: { a_fifo_cam_indices[3],
a_fifo_cam_indices[2],
a_fifo_cam_indices[1],
a_fifo_cam_indices[0] } = {3\'b000,
lt_fifo_cam_indices[3],
lt_fifo_cam_indices[2],
lt_fifo_cam_indices[1]};
1\'b0: { a_fifo_cam_indices[3],
a_fifo_cam_indices[2],
a_fifo_cam_indices[1],
a_fifo_cam_indices[0] } = { lt_fifo_cam_indices[3],
lt_fifo_cam_indices[2],
lt_fifo_cam_indices[1],
lt_fifo_cam_indices[0]};
endcase
$display ("\
<< END >>");
$finish(0);
end
// Waves definition
// initial
// begin
// $dumpfile("out.dump");
// $dumpvars(0, main);
// end
endmodule // main
|
module top;
parameter ip = 1;
parameter rp = 2.0;
parameter sp = "\\003";
real rlval;
wire real wreal;
reg [3:0] rval;
wire [3:0] wval;
assign wval = 2;
initial begin
rval = 4\'b1001;
rlval = 2.0;
$check_number(1);
$check_number(ip);
$check_number(2.0);
$check_number(rp);
$check_number("\\003");
$check_number(sp);
$check_number(rlval);
$check_number(rlval+1);
$check_number(wreal);
$check_number(wreal+1);
$check_number(rval);
$check_number(rval+1);
$check_number(wval);
$check_number(wval+1);
end
endmodule
|
// Copyright 2008, Martin Whitaker
// This file may be freely copied for any purpose. No attribution required.
module prXXX();
reg [3:0] value1;
wire [1:0] value2;
assign value2 = (value1 == 0) ? 0 : (value1 == 1) ? 1 : 2;
initial begin
value1 = 0;
#1 if (value2 !== 0) begin
\t $display("FAILED -- value1=%b, value2=%b", value1, value2);
\t $finish;
end
value1 = 1;
#1 if (value2 !== 1) begin
\t $display("FAILED -- value1=%b, value2=%b", value1, value2);
\t $finish;
end
value1 = 2;
#1 if (value2 !== 2) begin
\t $display("FAILED -- value1=%b, value2=%b", value1, value2);
\t $finish;
end
value1 = 3;
#1 if (value2 !== 2) begin
\t $display("FAILED -- value1=%b, value2=%b", value1, value2);
\t $finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule
|
module top;
wire real result;
reg [63:0] bits;
// This generates incorrect code:
// The .net/real temporary is not needed.
// The .alias/real temporary is not needed.
// The .sfunc should connect directly to the "results" net.
// The .part is not needed and is causing a core dump.
assign result = $bitstoreal(bits);
initial begin
$monitor("%g %h", result, bits);
bits = 64\'b0;
#1 bits = {1\'b0,{62{1\'b1}}};
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test;
reg [31:0] arr[1:0];
task writeInto;
output [31:0] into;
begin
\t into = 1;
end
endtask
initial begin
writeInto(arr[1]);
if (arr[1] !== 32\'d0) begin
\t $display("FAILED -- arr[1] = %h", arr[1]);
\t $finish;
end
$display("PASSED");
end
endmodule
|
/*
* This is from iverilog issue # 1313453
* This point is that it should compile.
*/
module test `protect (
a
);
// Input Declarations
input a;
`endprotect
initial $display("PASSED");
endmodule
|
timeunit 100ps / 10ps;
package testpackage;
task delay(output [63:0] t);
begin
$printtimescale(top);
$printtimescale;
#5ns t = $time;
end
endtask
endpackage
module top();
timeunit 1ns / 1ps;
import testpackage::delay;
reg [63:0] t1;
reg [63:0] t2;
initial begin
$printtimescale;
delay(t1);
t2 = $time;
$display("%0d %0d", t1, t2);
if ((t1 === 50) && (t2 === 5))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* Author: Oswaldo Cadenas <[email protected]>
*
* The test checks the module logic ouput type accepts default
* initialization value. If no default value is given to logic output
* type then this test fails.
*/
module clkgen(output logic clk = 0);
initial begin
#100;
disable checking;
disable gen;
$display ("PASSED");
$finish;
end
initial begin
fork
gen;
checking;
join
end
task gen;
forever #10 clk = ~clk;
endtask
task checking;
forever begin
#1;
if (clk === 1\'bx ) begin
$display ("FAILED!");
\t $finish;
end
end
endtask
endmodule
|
/*
* Copyright (c) 2000 Chris Lattner
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test;
reg [3:0] val, y;
initial begin
val = 2;
y = !val;
if (y !== 4\'b0000) begin
$display("FAILED -- !%b --> %b", val, y);
$finish;
end
$display("PASSED");
end
endmodule
|
`timescale 1ns/10ps
module TBUF_X2 (A, EN, Z);
input A;
input EN;
output Z;
bufif1(Z, A, EN);
specify
(A => Z) = (0.1, 0.2);
(EN => Z) = (0.3, 0.4);
endspecify
endmodule
module ckt (out, in, en);
output out;
input in, en;
TBUF_X2 dut (.A ( in ) , .EN ( en ) , .Z ( out ) ) ;
endmodule
module top;
wire out;
reg in, en;
ckt dut(out, in, en);
initial begin
$monitor($realtime,,out,"=",in,,en);
$sdf_annotate("ivltests/br960a.sdf", dut);
in = 1\'b0;
en = 1\'b0;
$display("Max (X->Z)");
// X -> Z = max(enable))
#10;
en = 1\'b1;
$display("Fall (Z->0)");
// Z -> 0 = tf(enable)
#10;
en = 1\'b0;
$display("Rise (0->Z)");
// 0 -> Z = tr(enable)
#5;
in = 1\'b1;
#5;
en = 1\'b1;
$display("Rise (Z->1)");
// Z -> 1 = tr(enable)
#10;
en = 1\'b0;
$display("Fall (1->Z)");
// 1 -> Z = tf(enable)
#10;
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test writing files using std.textio library.
module vhdl_textio_write_test;
reg write;
vhdl_textio_write dut(write);
initial begin
// this test is later verified by vhdl_read_textio
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module assignsigned();
parameter foo = 10;
reg\t signed [15:0] bar = -1;
wire baz;
assign baz = (bar < $signed(foo));
initial begin
#1 $display("bar=%h(%0d), foo=%0d, baz = %b", bar, bar, foo, baz);
if (baz !== 1\'b1) begin
\t $display("FAILED -- Compare returns %b instead of 1.", baz);
\t $finish;
end
$display("PASSED");
end
endmodule
|
module test4;
reg r;
endmodule
module test3;
test4 test4();
endmodule
module test2;
initial begin
\t$dumpvars(1, test3.test4);
end
test3 test3();
endmodule
module test;
initial begin
\t$dumpfile("work/dumpfile.vcd");
\t$dumpvars(1, test2.test3);
\t$display("PASSED");
end
test2 test2();
endmodule
|
module signed_multiplier_test;
reg failed_flag = 0;
reg signed [5:0] s_prod;
wire [2:0] u_pos_two = 3\'b010;
wire signed [2:0] s_pos_two = 3\'sb010;
wire signed [2:0] s_neg_two = 3\'sb110;
wire s = 1\'b1;\t// flag to indicate signed
wire u = 1\'b0;\t// flag to indicate unsigned
initial begin
// unsigned positive two as first argument of multiply
#1 s_prod = u_pos_two * u_pos_two;
check_mult(1,u,u_pos_two,u,u_pos_two,s_prod,6\'sb000100);
#1 s_prod = u_pos_two * s_pos_two;
check_mult(2,u,u_pos_two,s,s_pos_two,s_prod,6\'sb000100);
// This makes an unsigned result.
#1 s_prod = u_pos_two * s_neg_two;
check_mult(3,u,u_pos_two,s,s_neg_two,s_prod,6\'sb001100);
// signed positive two as first argument of multiply
#1 s_prod = s_pos_two * u_pos_two;
check_mult(4,s,s_pos_two,u,u_pos_two,s_prod,6\'sb000100);
#1 s_prod = s_pos_two * s_pos_two;
check_mult(5,s,s_pos_two,s,s_pos_two,s_prod,6\'sb000100);
#1 s_prod = s_pos_two * s_neg_two;
check_mult(6,s,s_pos_two,s,s_neg_two,s_prod,6\'sb111100);
// signed negative two as first argument of multiply
// This makes an unsigned result.
#1 s_prod = s_neg_two * u_pos_two;
check_mult(7,s,s_neg_two,u,u_pos_two,s_prod,6\'sb001100);
#1 s_prod = s_neg_two * s_pos_two;
check_mult(8,s,s_neg_two,s,s_pos_two,s_prod,6\'sb111100);
#1 s_prod = s_neg_two * s_neg_two;
check_mult(9,s,s_neg_two,s,s_neg_two,s_prod,6\'sb000100);
if (failed_flag == 0)
\t$display("PASSED");
$finish;
end
task check_mult;
input [31:0] idx;
input signeda;
input [ 2:0] arga;
input signedb;
input [ 2:0] argb;
input [ 5:0] result,expected;
if (result !== expected) begin
\t failed_flag = 1;
$write("failed: test %0d, ",idx);
if (signeda)
\t $write("3\'sb%b",arga);
\t else
\t $write("3 \'b%b",arga);
$write(" * ");
if (signedb)
\t $write("3\'sb%b",argb);
\t else
\t $write("3 \'b%b",argb);
$write(" = 6\'sb%b (expected 6\'sb%b)\
",result,expected);
end
endtask
endmodule
|
module top;
parameter parg0 = 0.0;
parameter parg1 = 1.0;
parameter parg2 = 2.0;
parameter pargi = 1.0/0.0; // Inf.
parameter pargn = $sqrt(-1.0); // NaN.
real arg0, arg1, arg2, argi, argn;
reg pass;
wire r_p0_b = !parg0;
wire r_p1_b = !parg1;
wire r_p2_b = !parg2;
wire r_pi_b = !pargi;
wire r_pn_b = !pargn;
wire r_0_b = !arg0;
wire r_1_b = !arg1;
wire r_2_b = !arg2;
wire r_i_b = !argi;
wire r_n_b = !argn;
wire r_p01_a = parg0 && parg1;
wire r_p02_a = parg0 && parg2;
wire r_p12_a = parg1 && parg2;
wire r_01_a = arg0 && arg1;
wire r_02_a = arg0 && arg2;
wire r_12_a = arg1 && arg2;
wire r_p00_o = parg0 || 0;
wire r_p01_o = parg0 || parg1;
wire r_p02_o = parg0 || parg2;
wire r_00_o = arg0 || 0;
wire r_01_o = arg0 || arg1;
wire r_02_o = arg0 || arg2;
wire r_p0_t = parg0 ? 1\'b1 : 1\'b0;
wire r_p1_t = parg1 ? 1\'b1 : 1\'b0;
wire r_p2_t = parg2 ? 1\'b1 : 1\'b0;
wire r_pi_t = pargi ? 1\'b1 : 1\'b0;
wire r_pn_t = pargn ? 1\'b1 : 1\'b0;
wire r_0_t = arg0 ? 1\'b1 : 1\'b0;
wire r_1_t = arg1 ? 1\'b1 : 1\'b0;
wire r_2_t = arg2 ? 1\'b1 : 1\'b0;
wire r_i_t = argi ? 1\'b1 : 1\'b0;
wire r_n_t = argn ? 1\'b1 : 1\'b0;
initial begin
pass = 1\'b1;
arg0 = 0.0;
arg1 = 1.0;
arg2 = 2.0;
argi = 1.0/0.0; // Inf.
argn = $sqrt(-1.0); // NaN.
#1;
/* Check ! on a constant real value. */
if (r_p0_b !== 1\'b1) begin
$display("Failed: CA constant !0.0, expected 1\'b1, got %b", r_p0_b);
pass = 1\'b0;
end
if (r_p1_b !== 1\'b0) begin
$display("Failed: CA constant !1.0, expected 1\'b0, got %b", r_p1_b);
pass = 1\'b0;
end
if (r_p2_b !== 1\'b0) begin
$display("Failed: CA constant !2.0, expected 1\'b0, got %b", r_p2_b);
pass = 1\'b0;
end
if (r_pi_b !== 1\'b0) begin
$display("Failed: CA constant !Inf, expected 1\'b0, got %b", r_pi_b);
pass = 1\'b0;
end
if (r_pn_b !== 1\'b0) begin
$display("Failed: CA constant !NaN, expected 1\'b0, got %b", r_pn_b);
pass = 1\'b0;
end
/* Check ! on a real variable. */
if (r_0_b !== 1\'b1) begin
$display("Failed: !0.0, expected 1\'b1, got %b", r_0_b);
pass = 1\'b0;
end
if (r_1_b !== 1\'b0) begin
$display("Failed: !1.0, expected 1\'b0, got %b", r_1_b);
pass = 1\'b0;
end
if (r_2_b !== 1\'b0) begin
$display("Failed: !2.0, expected 1\'b0, got %b", r_2_b);
pass = 1\'b0;
end
if (r_i_b !== 1\'b0) begin
$display("Failed: !Inf, expected 1\'b0, got %b", r_i_b);
pass = 1\'b0;
end
if (r_n_b !== 1\'b0) begin
$display("Failed: !NaN, expected 1\'b0, got %b", r_n_b);
pass = 1\'b0;
end
/* Check && on a constant real value. */
if (r_p01_a !== 1\'b0) begin
$display("Failed: constant 0.0 && 1.0, expected 1\'b0, got %b", r_p01_a);
pass = 1\'b0;
end
if (r_p02_a !== 1\'b0) begin
$display("Failed: constant 0.0 && 2.0, expected 1\'b0, got %b", r_p02_a);
pass = 1\'b0;
end
if (r_p12_a !== 1\'b1) begin
$display("Failed: constant 1.0 && 2.0, expected 1\'b1, got %b", r_p12_a);
pass = 1\'b0;
end
/* Check && on a real variable. */
if (r_01_a !== 1\'b0) begin
$display("Failed: 0.0 && 1.0, expected 1\'b0, got %b", r_01_a);
pass = 1\'b0;
end
if (r_02_a !== 1\'b0) begin
$display("Failed: 0.0 && 2.0, expected 1\'b0, got %b", r_02_a);
pass = 1\'b0;
end
if (r_12_a !== 1\'b1) begin
$display("Failed: 1.0 && 2.0, expected 1\'b1, got %b", r_12_a);
pass = 1\'b0;
end
/* Check || on a constant real value. */
if (r_p00_o !== 1\'b0) begin
$display("Failed: constant 0.0 || 0, expected 1\'b0, got %b", r_p00_o);
pass = 1\'b0;
end
if (r_p01_o !== 1\'b1) begin
$display("Failed: constant 0.0 || 1.0, expected 1\'b1, got %b", r_p01_o);
pass = 1\'b0;
end
if (r_p02_o !== 1\'b1) begin
$display("Failed: constant 0.0 || 2.0, expected 1\'b1, got %b", r_p02_o);
pass = 1\'b0;
end
/* Check || on a real variable. */
if (r_00_o !== 1\'b0) begin
$display("Failed: 0.0 || 0, expected 1\'b0, got %b", r_00_o);
pass = 1\'b0;
end
if (r_01_o !== 1\'b1) begin
$display("Failed: 0.0 || 1.0, expected 1\'b1, got %b", r_01_o);
pass = 1\'b0;
end
if (r_02_o !== 1\'b1) begin
$display("Failed: 0.0 || 2.0, expected 1\'b1, got %b", r_02_o);
pass = 1\'b0;
end
/* Check the ternary with a constant real cond. value. */
if (r_p0_t !== 1\'b0) begin
$display("Failed: constant 0.0 ? ..., expected 1\'b0, got %b", r_p0_t);
pass = 1\'b0;
end
if (r_p1_t !== 1\'b1) begin
$display("Failed: constant 1.0 ? ..., expected 1\'b1, got %b", r_p1_t);
pass = 1\'b0;
end
if (r_p2_t !== 1\'b1) begin
$display("Failed: constant 2.0 ? ..., expected 1\'b1, got %b", r_p2_t);
pass = 1\'b0;
end
if (r_pi_t !== 1\'b1) begin
$display("Failed: constant Inf ? ..., expected 1\'b1, got %b", r_pi_t);
pass = 1\'b0;
end
if (r_pn_t !== 1\'b1) begin
$display("Failed: constant NaN ? ..., expected 1\'b1, got %b", r_pn_t);
pass = 1\'b0;
end
/* Check the ternary with a real cond. variable. */
if (r_0_t !== 1\'b0) begin
$display("Failed: 0.0 ? ..., expected 1\'b0, got %b", r_0_t);
pass = 1\'b0;
end
if (r_1_t !== 1\'b1) begin
$display("Failed: 1.0 ? ..., expected 1\'b1, got %b", r_1_t);
pass = 1\'b0;
end
if (r_2_t !== 1\'b1) begin
$display("Failed: 2.0 ? ..., expected 1\'b1, got %b", r_2_t);
pass = 1\'b0;
end
if (r_i_t !== 1\'b1) begin
$display("Failed: Inf ? ..., expected 1\'b1, got %b", r_i_t);
pass = 1\'b0;
end
if (r_n_t !== 1\'b1) begin
$display("Failed: NaN ? ..., expected 1\'b1, got %b", r_n_t);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate fork template 1
module main ;
reg [3:0] value1,value2 ;
reg [3:0] ret1,ret2 ;
reg error;
always @(value1 or value2)
begin
fork
#10 ret1 = value1;
#22 ret2 = value2;
join
end
initial
begin
error = 0;
#1 ;
value1 = 1;
value2 = 2;
ret1 = 0;
ret2 = 0;
#12;
if(ret1 !== 1)
begin
$display("FAILED - force3.19A first statement didn\'t execute(1)");
error = 1;
end
if(ret2 !== 0)
begin
$display("FAILED - force3.19A second stmt executed? is %d sb %d",
1\'b0,ret2);
error = 1;
end
#10;
if(ret1 !== 1)
begin
$display("FAILED -fork3.19A First statement problem sb 1, is %d",ret1);
error = 1;
end
if(ret2 !== 2)
begin
$display("FAILED -fork3.19A First statement problem sb 2, is %d",ret1);
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
module top;
wire real minus;
real in;
assign minus = -in; // Should be arith/sub.r Cr<0>, <net>
initial begin
$monitor(minus,, in);
in = 3.0;
#1 in = 4.0;
#1 in = 6.0;
end
endmodule
|
module main;
parameter use_wid = 4;
reg [use_wid-1:0] d;
wire [use_wid-1:0] q;
reg\t\t clk;
B #(.wid(use_wid)) dut (.Q(q), .D(d), .C(clk));
initial begin
clk = 0;
d = 4\'b0000;
#1 clk = 1;
#1 clk = 0;
if (q !== 4\'b0000) begin
\t $display("FAILED -- d=%b, q=%b", d, q);
\t $finish;
end
d = 4\'b1111;
#1 clk = 1;
#1 clk = 0;
if (q !== 4\'b1111) begin
\t $display("FAILED -- d=%b, q=%b", d, q);
\t $finish;
end
$display("PASSED");
end
endmodule // main
/*
* although the wid paramter is default to 3 in this module, the point
* of this test is to have the instantiating module (main) give a
* different value and have that value properly handlued in all the
* situations of this module.
*/
module B
#(parameter wid = 3)
(output [wid-1:0] Q,
input [wid-1:0] D,
input C);
// the override from main will cause this to be a width of 4.
prim U [wid-1:0] (Q, D, C);
//prim U [wid-1:0] (.Q(Q), .D(D), .C(C));
endmodule // B
module prim(output reg Q, input D, C);
always @(posedge C)
Q <= D;
endmodule // prim
|
module m;
reg [4\'b1111 + 4\'b0001 >> 1:0] x;
reg [4\'b1111 + 1 >> 1:0] y;
initial
begin
x = -1;
y = -1;
$display("x = %b", x);
$display("y = %b", y);
end
endmodule
|
`begin_keywords "1364-2005"
module top;
reg [31:0] var;
initial begin
$monitor(var);
var = 0;
repeat (60) begin
#1 var = $urandom_range(16,0);
// #1 var = $urandom_range(4294967295,0);
// #1 var = $urandom_range(-1,0);
end
end
endmodule
`end_keywords
|
module test;
initial begin
$display("File %s line %0d", `__FILE__, `__LINE__);
`include "ivltests/br_gh782a.vi" // single line comment
$display("File %s line %0d", `__FILE__, `__LINE__);
`include "ivltests/br_gh782a.vi" /* another single line comment */
$display("File %s line %0d", `__FILE__, `__LINE__);
`include "ivltests/br_gh782a.vi" /* multi-line
comment */
$display("File %s line %0d", `__FILE__, `__LINE__);
`include "ivltests/br_gh782a.vi" /* single */ /* and
multi-line comment */
$display("File %s line %0d", `__FILE__, `__LINE__);
end
endmodule
|
module test();
reg [31:0] a, b;
reg [65:0] a_l, b_l;
wire [31:0] result = a / b;
wire [31:0] mod = a % b;
wire [65:0] result_l = a_l / b_l;
wire [65:0] mod_l = a_l % b_l;
initial begin
a = \'h1;
b = \'h1;
a_l = \'h1;
b_l = \'h1;
#1; // Need some delay for the calculations to run.
// b_l = \'h0; // This will now fail with an error.
$display("Using normal math routines.");
$display("Result: %0d\
Modulus: %h", result, mod);
$display("\
Using wide math routines.");
$display("Result: %0d\
Modulus: %h", result_l, mod_l);
end
endmodule
|
// Check that it is possible to use SV data types for ANSI style task ports
module test;
typedef logic [7:0] T1;
typedef struct packed { int i; } T2;
typedef enum { A } T3;
task t(input reg a,
input logic b,
input bit c,
input logic [3:0] d,
input bit [3:0][3:0] e,
input byte f,
input int g,
input T1 h,
input T2 i,
input T3 j,
input real k,
input shortreal l,
input string m,
input int n[],
input int o[$],
input x,
input [3:0] y,
input signed z
);
$display("PASSED");
endtask
initial begin
t(\'0, \'0, \'0, \'0, \'0, \'0, \'0, \'0, \'0, A, 0.0, 0.0, "", \'{0}, \'{0}, \'0, \'0, \'0);
end
endmodule
|
`begin_keywords "1364-2005"
// Adapted from case6.v
module main;
reg bit, foo;
// Combinational device that sends 1 or 0 to foo, to follow bit.
always @*
begin
\tfoo = 1;
\tcase (bit)
\t 1\'b0: foo = 0;
\tendcase // case(bit)
end
(* ivl_synthesis_off *)
initial begin
bit = 0;
# 6 $display("bit=%b, foo=%b", bit, foo);
if (bit !== 0 || foo !== 0) begin
\t $display("FAILED");
\t $finish;
end
bit <= 1;
#10 $display("bit=%b, foo=%b", bit, foo);
if (bit !== 1 || foo !== 1) begin
\t $display("FAILED");
\t $finish;
end
$display("PASSED");
$finish;
end
endmodule // main
`end_keywords
|
// This program is about testing that the value ranges parse and work for
// integer parameters.
module test(input wire bar);
parameter real foo = 0.0 from [-10.0 : 10.0] exclude [1:2);
parameter real bar = 0 from (-inf:0];
initial begin
$display("foo = %f", foo);
$display("PASSED");
$finish;
end
endmodule // test
module main;
reg rrr = 0;
test #(.foo(1), .bar(-5.0)) dut (rrr);
endmodule // main
|
// A global timeprecision and local time units.
timeprecision 10ps;
module gtp_ltu1;
timeunit 1ns;
endmodule
module gtp_ltu2;
timeunit 1us;
endmodule
`timescale 1s/1s
module check3;
initial begin
$printtimescale(gtp_ltu1);
$printtimescale(gtp_ltu2);
end
endmodule
|
\r
module string_example;\r
\r
function int example( string my_string );\r
if( my_string[1] != 8\'h65 ) begin\r
\t return 1;\r
end else begin\r
\t return 0;\r
end\r
endfunction // example\r
\r
string test_string;\r
initial begin\r
test_string = "Hello, World";\r
if (test_string[0] !== 8\'h48) begin\r
\t $display("FAILED -- test+string[0] = %h", test_string[0]);\r
\t $finish;\r
end\r
if (example(test_string) === 1) begin\r
\t $display("FAILED -- example(test_string) returned error.");\r
\t $finish;\r
end\r
$display("PASSED");\r
$finish;\r
end\r
endmodule\r
|
/*
* Sign extend input
* T can be 0 for <<, 1 for >>, 2 for <<< or 3 for >>>.
*/
module sign_ext
#(parameter WI = 4, WO = 6)
(input wire signed [WI-1:0] D,
output wire signed [WO-1:0] Q
/* */);
assign Q = D;
endmodule
|
/*
* Based on PR#1008
*/
`timescale 1 ps / 1 ps
module star;
reg a;
reg b;
initial begin
$monitor("b = %b", b);
#1;
a = 1;
#2;
a = 0;
#2;
a = 1;
end
/* This generated the error:
:0: internal error: NetProc::nex_output not implemented
Before CVS 20040630 */
always @* begin
b = #1 ~a;
end
endmodule // star
|
module check (input unsigned [22:0] a, b, c);
wire [22:0] int_AB;
assign int_AB = ~(a ^ b);
always @(a, b, int_AB, c) begin
#1;
if (int_AB != c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
end
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [22:0] r;
stimulus stim (.A(a), .B(b));
xnor23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#20000;
$display("PASSED");
$finish;
end
endmodule
|
module \\esc.mod ;
\\esc.sub \\esc.inm (1'b1);
sub inst();
endmodule
module \\esc.sub (input wire \\esc.port );
reg \\esc.val ;
reg normal;
initial begin
$print_if_found();
normal = 1'b0;
\\esc.val = 1'b1;
end
endmodule
module sub;
reg \\esc.id ;
reg normal;
initial begin
normal = 1'b1;
\\esc.id = 1'b0;
end
endmodule
|
module test;
parameter parm1 = 0;
parameter parm2 = parm1 == 0;
initial begin
\t// if got here then we compiled
\tif (parm2)
\t $display("PASSED");
\telse
\t $display("FAILED");
end
endmodule
|
package test_pkg;
virtual class uvm_void;
endclass : uvm_void
class uvm_object extends uvm_void;
string m_name;
function new (string name = "uvm_object");
$display("uvm_object::new(%s)", name); // XXXX
m_name = name;
endfunction : new
virtual function void print ();
$display ("uvm_object::Print: m_name=%s", m_name);
endfunction : print
endclass : uvm_object
class uvm_report_object extends uvm_object;
function new (string name = "uvm_report_object");
super.new (name);
endfunction : new
endclass : uvm_report_object
endpackage : test_pkg
module m;
import test_pkg::*;
uvm_object u0;
uvm_report_object u1;
initial begin : test
#100;
$display ("Hello World");
u0 = new ();
u0.print();
u1 = new ();
u1.print();
end : test
endmodule : m
|
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