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// specify4.v
module top;
reg d, c;
wire q;
initial begin
d = 0;
c = 1;
#10 $monitor($time,,"q=%b, d=%b, c=%b", q, d, c);
#5 c = 0;
#5 c = 1;
#5 c = 0; d = 1;
#5 c = 1;
#5 c = 0; d = 0;
#5 c = 1;
#10 $finish(0);
end
mydff g1 (q, d, c);
endmodule
module mydff (output reg q, input d, input c);
always @(posedge c) q <= d;
specify
(posedge c => (q +: d)) = (3, 2);
endspecify
endmodule
|
// Eleven basic tests in here:
// 1. longint must be initialised before any initial or always block
// 2. assignments to (unsigned) longint with random numbers
// 3. assignments to (unsigned) longint with random values including X and Z
// 4. converting unsigned 64-bit integer time to unsigned longint
// 5. converting signed integers to unsigned longint
// 6. converting 64-bit integers including X and Z states to unsigned longint
// 7. trying unsigned sums (procedural, function, task and module)
// 8. trying unsigned mults (procedural, function and task)
// 9. trying relational operators
// 10. smaller signed numbers to unsigned longint (signed extension)
// 11. trying some concatenations from bytes, shortints, ints to longints
module mu_add (input longint unsigned a, b, output longint unsigned sc, ss);
assign sc = a + b;
always @(a, b) ss = a + b;
endmodule
module main;
parameter N_REPS = 500; // repetition with random numbers
parameter XZ_REPS = 500; // repetition with \'x \'z values
parameter MAX8 = 256;
parameter MAX16 = 65536;
parameter LEN = 64;
// variables used as golden references
reg unsigned [LEN-1:0] ar; // holds numbers
reg unsigned [LEN-1:0] ar_xz; // holds \'x and/or \'z in random positions
reg unsigned [LEN-1:0] ar_expected;
reg unsigned [LEN-1:0] ui; // unsigned 64-bit integer
reg signed [LEN/2-1:0] slice;
// type assumed to be tested before hand
byte unsigned pt1, pt2;
shortint unsigned ps1, ps2;
int unsigned pv1, pv2;
// types to be tested
longint unsigned bu; // holds numbers
longint unsigned bu_xz; // \'x and \'z are attempted on this
longint unsigned bresult; // hold results from sums and mults
longint unsigned mcaresult; // wired to a module instance
longint unsigned mabresult; // also wired to a module instance
integer i;
// continuous assigments
// type LHS type RHS
// --------- ---------
// longint 4-value logic
assign bu = ar;
assign bu_xz = ar_xz;
// module instantiation
mu_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) );
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if (bu !== 64\'b0 || bu_xz != 64\'b0 || bresult !== 64\'b0 || mcaresult !== 64\'b0 || mabresult !== 64\'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// driving longint type with unsigned random numbers from a variable
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = { {$random}, {$random} };
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to int: %b", bu);
$finish;
end
end
# 1;
// attempting to drive variables having \'x \'z values into type unsigned longint
// \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
ar = { {$random}, {$random} };
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0
begin
$display ("FAILED - incorrect assigment to longint (when \'x \'z): %b", bu);
$finish;
end
end
// converting unsigned 64-bit integers (time) to unsigned longint
// this should pass trivially
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ui = { {$random}, {$random} };
#1;
force bu = ui;
#1;
if (bu !== ui)
begin
$display ("FAILED - incorrect assignment from 64-bit integer to longint: %b", bu);
$finish;
end
end
release bu;
// converting signed integers to unsigned ints
// keeping the same bit representation is expected
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ui = { {$random}, {$random} };
#1;
force bu = -ui;
#1;
if (-bu !== ui)
begin
$display ("FAILED - incorrect assignment from 64-bit signed integer to longint: %d mismatchs %d", bu, -ui);
$finish;
end
end
release bu;
// converting integers having \'x \'z values into type unsigned longint
// \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM)
// coercion to zero expected
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
ui = { {$random}, {$random} };
ar_xz = xz_inject (ui);
ui = ar_xz;
ar_expected = xz_expected (ar_xz);
#1;
force bu_xz = ui;
#1;
if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0
begin
$display ("FAILED - incorrect conversion from 64-bit integer (with \'x \'z) to longint: %b mismatchs %b", bu_xz, ar_expected);
$finish;
end
end
release bu_xz;
// trying unsigned sums
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = { {$random}, {$random} };
ar_xz = { {$random}, {$random} };
#1;
bresult = bu + bu_xz;
#1;
if ( bresult !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned longints: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz));
$finish;
end
// invoking longint sum function
if ( fu_sum (bu, bu_xz) !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned longint in function");
$finish;
end
// invoking longint sum task
tu_sum (bu, bu_xz, bresult);
if ( bresult !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned longint in task: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz));
$finish;
end
// checking longint sum from module
if ( mcaresult !== u_sum(ar, ar_xz) || mabresult !== u_sum(ar, ar_xz))
begin
$display ("FAILED - incorrect addition of unsigned longtint from module");
$finish;
end
end
// trying unsigned mults
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = { {$random} % 32\'d65536, {$random} % 32\'d32768 };
ar_xz = { {$random} % 32\'d32768, {$random} % 32\'d65536 };
#1;
bresult = bu * bu_xz; // truncated mult
#1;
if ( bresult !== uh_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect multiplication of unsigned longints: %0d mismatchs %0d", bresult, uh_mul(ar, ar_xz));
$finish;
end
#1;
pv1 = {$random};
pv2 = {$random};
#1;
bresult = pv1 * pv2; // longint = int x int
#1;
if ( bresult !== u_mul(pv1, pv2) )
begin
$display ("FAILED - incorrect multiplication of unsigned longints for int inputs");
$finish;
end
// invoking longint mult function (int*int)
if ( fu_mul (pv1, pv2) !== u_mul(pv1, pv2) )
begin
$display ("FAILED - incorrect product of unsigned ints for a function returning unsigned longint");
$finish;
end
// invoking longint mult task (int*int)
tu_mul (pv1, pv2, bresult);
if ( bresult !== u_mul(pv1, pv2) )
begin
$display ("FAILED - incorrect product of unsigned int in task returning unsigned longint");
$finish;
end
end
// trying relational operators
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = { {$random}, {$random} };
ar_xz = { {$random}, {$random} };
#1;
if ( (bu < bu_xz ) != (ar < ar_xz) )
begin
$display ("FAILED - incorrect \'less than\' on unsigned longints");
$finish;
end
if ( (bu <= bu_xz ) != (ar <= ar_xz) )
begin
$display ("FAILED - incorrect \'less than or equal\' on unsigned longints");
$finish;
end
if ( (bu > bu_xz ) != (ar > ar_xz) )
begin
$display ("FAILED - incorrect \'greater than\' on unsigned longints");
$finish;
end
if ( (bu >= bu_xz ) != (ar >= ar_xz) )
begin
$display ("FAILED - incorrect \'greater than or equal\' than on unsigned longints");
$finish;
end
if ( (bu == bu_xz ) != (ar == ar_xz) )
begin
$display ("FAILED - incorrect \'equal to\' on unsigned longints");
$finish;
end
if ( (bu != bu_xz ) != (ar != ar_xz) )
begin
$display ("FAILED - incorrect \'not equal to\' on unsigned ints");
$finish;
end
end
# 1;
// signed small number to unsigned shorint
for (i = 0; i < N_REPS; i = i+1)
begin
#1;
slice = $random % \'h7fff_ffff;
force bu = slice;
ar = slice;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect signed extend to unsigned longint");
$finish;
end
end
release bu;
// trying concatenations (and replication)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
pt1 = {$random} % MAX8;
pt2 = {$random} % MAX8;
#1;
bresult = { {4{pt1}}, {4{pt2}} };
#1;
if ( bresult[63:56] !== pt1 || bresult[55:48] !== pt1 || bresult[47:40] !== pt1 || bresult[39:32] !== pt1 ||
bresult[31:24] !== pt2 || bresult[23:16] !== pt2 || bresult[15:8] !== pt2 || bresult[7:0] !== pt2)
begin
$display ("FAILED - incorrect concatenation and replication of bytes into unsigned longints");
$finish;
end
#1;
ps1 = {$random} % MAX16;
ps2 = {$random} % MAX16;
#1;
bresult = { {2{ps1}}, {2{ps2}} };
#1;
if ( bresult[63:48] !== ps1 || bresult[47:32] !== ps1 || bresult[31:16] !== ps2 || bresult[15:0] !== ps2)
begin
$display ("FAILED - incorrect concatenation and replication of shortint into unsigned long ints");
$finish;
end
#1;
pv1 = {$random};
pv2 = {$random};
#1;
bresult = { pv1, pv2 };
#1;
if ( bresult[63:32] !== pv1 || bresult[31:0] !== pv2)
begin
$display ("FAILED - incorrect concatenation and replication of int into unsigned longints");
$finish;
end
end
#1;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [LEN-1:0] xz_inject (input unsigned [LEN-1:0] value);
integer i, k;
time temp;
begin
temp = {$random, $random};
for (i=0; i<LEN; i=i+1)
begin
if (temp[i] == 1\'b1)
begin
k = $random;
if (k <= 0)
value[i] = 1\'bx; // \'x noise
else
value[i] = 1\'bz; // \'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [LEN-1:0] xz_expected (input unsigned [LEN-1:0] value_xz);
integer i;
begin
for (i=0; i<LEN; i=i+1)
begin
if (value_xz[i] === 1\'bx || value_xz[i] === 1\'bz )
value_xz[i] = 1\'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
// unsigned 4-value sum
function unsigned [LEN-1:0] u_sum (input unsigned [LEN-1:0] a, b);
u_sum = a + b;
endfunction
// unsigned longint sum as function
function longint unsigned fu_sum (input longint unsigned a, b);
fu_sum = a + b;
endfunction
// unsigned longint sum as task
task tu_sum (input longint unsigned a, b, output longint unsigned c);
c = a + b;
endtask
// unsigned 4-value truncated mults
function unsigned [LEN-1:0] uh_mul (input unsigned [LEN-1:0] a, b);
uh_mul = a * b;
endfunction
// unsigned 4-value mults
function unsigned [LEN-1:0] u_mul (input unsigned [LEN/2-1:0] a, b);
u_mul = a * b;
endfunction
// unsigned longint mult as function
function longint unsigned fu_mul (input int unsigned a, b);
fu_mul = a * b;
endfunction
// unsigned longint mult as task
task tu_mul (input int unsigned a, b, output longint unsigned c);
c = a * b;
endtask
endmodule
|
// This module generate all 8 inputs for three boolean variables
module stimulus #(parameter M = 8, T = 10) (
output reg i0, i1,
output reg s
);
bit [2:0] i;
initial begin
for (i = 0; i < M; i=i+1) begin
#T;
{i0, i1, s} = i;
end
#T;
end
endmodule
// This module always checks the internal generated muxed output complies with the received one
module check (input i0, i1, s, y);
logic y_check;
always @(i0, i1, s)
y_check = s ? i1 : i0;
always @(y, y_check) begin
#1 if (y != y_check) begin
$display("ERROR");
$finish;
end
end
endmodule
module test;
parameter M = 8;
parameter T = 10;
parameter S = (M+1)*T + 40;
wire i0, i1, s, y;
stimulus #(M, T) stim (.i0(i0), .i1(i1), .s(s) );
mux2to1 duv (.i0(i0), .i1(i1), .s(s), .y(y) );
check check (.i0(i0), .i1(i1), .s(s), .y(y) );
initial begin
#S;
$display("PASSED");
$finish;
end
endmodule
|
// Check that a assignment operator on an real array entry with an immediate
// index works if it happes after a comparison that sets vvp flag 4 to 0.
module test;
real r[1:0];
logic a = 1\'b0;
initial begin
r[0] = 8.0;
if (a == 0) begin
// Make sure that this update happens, even though the compare above
// cleared set vvp flag 4
r[0] *= 2.0;
end
if (r[0] == 16.0) begin
$display("PASSED");
end else begin
$display("FAILED. Expected %f, got %f", 16.0, r[0]);
end
end
endmodule
|
// Copyright C(O) 2004 Burnell G West
// The following text may be utilized and / or reproduced by anybody for
// any reason.
//
// verr.v
//
module verr (clk, vout);
input clk;
output vout;
reg vout;
real start_edge;
real end_edge;
wire trigger_en;
wire [9:0] v_value;
initial vout = 1\'b0;
always @( posedge clk)
begin
if (trigger_en)
begin
start_edge = ( v_value[0] * 1.95)
+ ( v_value[1] * 3.9 )
+ ( v_value[2] * 7.8 )
+ ( v_value[3] * 15.6 )
+ ( v_value[4] * 31.2 )
+ ( v_value[5] * 62.5 )
+ ( v_value[6] * 125 )
+ ( v_value[7] * 250 )
+ ( v_value[8] * 0 )
+ ( v_value[9] * 0 )
+ 0;
end_edge = start_edge + 100; // make pulse width = 1ns
end
else
begin
start_edge <= start_edge;
end_edge <= end_edge;
end
end
endmodule
module vtest;
wire vout0, vout1, vout2, vout3, vout4, vout5, vout6, vout7, vout8, vout9;
wire vout10, vout11, vout12, vout13, vout14, vout15, vout16, vout17,
vout18, vout19;
reg clk, bit0;
verr v0 (clk, vout0);
verr v1 (clk, vout1);
verr v2 (clk, vout2);
verr v3 (clk, vout3);
verr v4 (clk, vout4);
verr v5 (clk, vout5);
verr v6 (clk, vout6);
verr v7 (clk, vout7);
verr v8 (clk, vout8);
verr v9 (clk, vout9);
verr v10 (clk, vout10);
verr v11 (clk, vout11);
verr v12 (clk, vout12);
verr v13 (clk, vout13);
verr v14 (clk, vout14);
verr v15 (clk, vout15);
verr v16 (clk, vout16);
verr v17 (clk, vout17);
verr v18 (clk, vout18);
verr v19 (clk, vout19);
initial begin
#10000 $display("This test doesn\'t check itself.");
$display("PASSED");
end
endmodule
|
module top;
reg passed;
reg [1:0] sel;
reg [1:0] A;
wire [1:0] Z;
parent parent(.sel(sel), .A(A), .Z(Z));
initial begin
passed = 1\'b1;
sel = 2\'b11;
A = 2\'b00;
#1 if (Z !== 2\'b00) begin
$display("FAILED: selected, expected 2\'b00, got %b", Z);
passed = 1\'b0;
end
A = 2\'b10;
#1 if (Z !== 2\'b10) begin
$display("FAILED: selected, expected 2\'b10, got %b", Z);
passed = 1\'b0;
end
A = 2\'b01;
#1 if (Z !== 2\'b01) begin
$display("FAILED: selected, expected 2\'b01, got %b", Z);
passed = 1\'b0;
end
sel = 2\'b00;
#1 if (Z !== 2\'bzz) begin
$display("FAILED: deselected, expected 2\'bzz, got %b", Z);
passed = 1\'b0;
end
if (passed) $display("PASSED");
end
endmodule
module parent(input[1:0] sel, input [1:0] A, inout [1:0] Z);
child child[1:0](.sel(sel), .A(A), .Z(Z));
endmodule
module child(input sel, input A, inout Z);
assign Z = (sel) ? A : 1\'bz;
endmodule
|
/***************************************************************
** Author: Oswaldo Cadenas ([email protected])
** Date: September 26 2011
**
** Test: Intended to test parametric counter in timebase.vhd
** the counter has parameters: N for counter length and
VALUE to flag when the count reaches this value
**
** Four counter instances are created here:
** duv1 with counter default parameters for N and VALUE
** duv2 with N1, V1 for parameter N, VALUE respectively
** duv3 with N2, V2 for parameters N, VALUE respectively
** duv4 with N2 replacing N and VALUE left as default
**
** The test for a long time making sure each of the four counter flags TICK become one
**************************************************************************************/
module test;
parameter integer T = 25;
parameter integer N1 = 8;
parameter integer N2 = 17;
parameter integer V1 = 200;
parameter integer V2 = 17\'h16C8A;
bit clk = 0, reset = 0;
wire [11:0] count1;
wire [N1-1:0] count2;
wire [N2-1:0] count3;
wire [N2-1:0] count4;
wire tick1, tick2, tick3, tick4;
reg tick1_reg, tick2_reg, tick3_reg, tick4_reg;
initial forever #(T) clk = !clk;
initial begin
@(negedge clk);
reset = 1\'b1;
repeat(6) @(negedge clk);
reset = 1\'b0;
end
// duv1 switch
always @(posedge clk, posedge reset)
\tif (reset) tick1_reg <= 1\'b0;
\telse if (tick1) tick1_reg <= 1\'b1;
// duv2 switch
always @(posedge clk, posedge reset)
\tif (reset) tick2_reg <= 1\'b0;
\telse if (tick2) tick2_reg <= 1\'b1;
// duv3 switch
always @(posedge clk, posedge reset)
\tif (reset) tick3_reg <= 1\'b0;
\telse if (tick3) tick3_reg <= 1\'b1;
// duv4 switch
always @(posedge clk, posedge reset)
\tif (reset) tick4_reg <= 1\'b0;
\telse if (tick4) tick4_reg <= 1\'b1;
initial begin
#(V2*2*T + 1000);
if (tick1_reg != 1 || tick2_reg != 1 || tick3_reg != 1 || tick4_reg != 1) begin
$display ("Counting FAILED");
$finish;
end
else begin
$display ("PASSED");
#20;
$finish;
end
end
timebase duv1 (.clock(clk), .reset(reset), .enable(1\'b1), .tick(tick1), .count_value(count1) ); // default parameters
timebase #(.n(N1), .value(V1))
duv2 (.clock(clk), .reset(reset), .enable(1\'b1), .tick(tick2), .count_value(count2) ); // N1, V1 parameters
timebase #(N2, V2)
duv3 (.clock(clk), .reset(reset), .enable(1\'b1), .tick(tick3), .count_value(count3) ); // N2, V2 parameters
timebase #(.n(N2))
duv4 (.clock(clk), .reset(reset), .enable(1\'b1), .tick(tick4), .count_value(count4) ); // only one parameter modified
endmodule
|
`begin_keywords "1364-2005"
module top;
reg passed, in, expect, out;
integer lp;
initial begin
passed = 1\'b1;
for (lp=0; lp < 3 ; lp = lp + 1) begin
case (lp)
0: {in,expect} = 2\'b00;
1: {in,expect} = 2\'b11;
2: {in,expect} = 2\'bzx;
3: {in,expect} = 2\'bxx;
endcase
// Check the normal reductions.
// These can fail be need a %buf opcode.
out = ∈
if (out !== expect) begin
$display("FAILED reduction & with input %b, expected %b, got %b",
in, expect, out);
passed = 1\'b0;
end
out = |in;
if (out !== expect) begin
$display("FAILED reduction | with input %b, expected %b, got %b",
in, expect, out);
passed = 1\'b0;
end
out = ^in;
if (out !== expect) begin
$display("FAILED reduction ^ with input %b, expected %b, got %b",
in, expect, out);
passed = 1\'b0;
end
// Check the inverted reductions.
out = ~∈
if (out !== ~expect) begin
$display("FAILED reduction ~& with input %b, expected %b, got %b",
in, ~expect, out);
passed = 1\'b0;
end
out = ~|in;
if (out !== ~expect) begin
$display("FAILED reduction ~| with input %b, expected %b, got %b",
in, ~expect, out);
passed = 1\'b0;
end
out = ~^in;
if (out !== ~expect) begin
$display("FAILED reduction ~^ with input %b, expected %b, got %b",
in, ~expect, out);
passed = 1\'b0;
end
end
if (passed) $display("PASSED");
end
endmodule
`end_keywords
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous xor in assignment..dependent on always ^ working
//
module main;
reg globvar;
reg [3:0] var1,var2,var3;
wire [3:0] var3a;
reg error;
assign var3a = var1 ^ var2;
always @( var1 or var2)
var3 = var1 ^ var2 ;
initial
begin
error = 0;
for ( var1 = 4\'b0; var1 != 4\'hf; var1 = var1 + 1)
for ( var2 = 4\'b0; var2 != 4\'hf; var2 = var2 + 1)
begin
#1 ;
if(var3 != var3a)
begin
$display("FAILED continuous xor 1=%h,2=%h,3=%h,3a=%h",
var1,var2,var3,var3a);
error = 1;
end
#1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
module test();
wire\t d;
wire [5:0]\t f;
b u1 (.c({d, f}));
endmodule
module b (c);
output [6:0] c;
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module bug();
reg [2:1][16:1][8:1] array;
reg failed = 0;
integer i;
reg [3:0] index;
initial begin
i = $bits(array);
$display("width 0 = %0d", i);
if (i !== 256) failed = 1;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
i = $bits(array[0]);
`else
i = $bits(array[1]);
`endif
$display("width 1 = %0d", i);
if (i !== 128) failed = 1;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
i = $bits(array[0][0]);
`else
i = $bits(array[1][1]);
`endif
$display("width 2 = %0d", i);
if (i !== 8) failed = 1;
for (i = 0; i < 16; i++) begin
index = i[3:0];
array[1][5\'d1+index] = {4\'d0, index};
array[2][5\'d1+index] = {4\'d1, index};
end
$display("%h", array);
if (array !== 256\'h1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100)
failed = 1;
for (i = 0; i < 16; i++) begin
index = i[3:0];
$display("%h : %h %h", index, array[1][5\'d1+index], array[2][5\'d1+index]);
if (array[1][5\'d1+index] !== {4\'d0, index}) failed = 1;
if (array[2][5\'d1+index] !== {4\'d1, index}) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* test the signedness of wires.
*/
module main;
reg signed [7:0] val_rs = -5;
wire [7:0] val_w = val_rs + 1;
wire signed [7:0] val_ws = val_rs + 1;
initial begin
#1 /* Let assignments settle. */
\t$display("val_w=%d, val_ws=%d", val_w, val_ws);
if (val_w !== 8\'d252) begin
\t $display("FAILED -- val_w is wrong: %b", val_w);
\t $finish;
end
if (val_ws !== -8\'sd4) begin
\t $display("FAILED == val_ws is wrong: %b", val_ws);
\t $finish;
end
if (val_ws > 0) begin
\t $display("FAILED -- signed test of val_ws failed");
\t $finish;
end
if (val_w < 0) begin
\t $display("FAILED -- signed test of val_w failed");
\t $finish;
end
$display("PASSED");
end
endmodule // main
|
module copy(input [1:0] out, output [1:0] in);
assign out = in;
endmodule
module top();
reg [2:0] r;
wire [1:0] i1;
wire [1:0] i2;
wire [1:0] i3;
wire [0:0] o1;
wire [1:0] o2;
wire [2:0] o3;
assign i1 = r;
assign i2 = r;
assign i3 = r;
copy copy1(o1, i1);
copy copy2(o2, i2);
copy copy3(o3, i3);
reg failed;
initial begin
failed = 0;
for (r = 0; r < 4; r = r + 1) begin
#1 $display("%b : %b %b : %b %b : %b %b", r[1:0], i1, o1, i2, o2, i3, o3);
if (o1 !== r[0]) failed = 1;
if (o2 !== r[1:0]) failed = 1;
if (o3 !== {1\'bz, r[1:0]}) failed = 1;
end
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module automatic test();
task static accumulate1(input integer value, output integer result);
static int acc = 1;
acc = acc + value;
result = acc;
endtask
task accumulate2(input integer value, output integer result);
int acc = 1;
acc = acc + value;
result = acc;
endtask
integer value;
reg failed = 0;
initial begin
accumulate1(2, value);
$display("%d", value);
if (value !== 3) failed = 1;
accumulate1(3, value);
$display("%d", value);
if (value !== 6) failed = 1;
accumulate2(2, value);
$display("%d", value);
if (value !== 3) failed = 1;
accumulate2(3, value);
$display("%d", value);
if (value !== 4) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module top;
reg pass = 1\'b1;
reg [7:0] d_reg = 8\'b10100101;
wire [7:0] d_wire = 8\'b01011010;
test tstr(d_reg);
test tstw(d_wire);
initial begin
#1;
/* Check with a register. */
if (tstr.data_in_array[3] != d_reg) begin
$display("FAILED: with a register value.");
pass = 1\'b0;
end
/* Check with a wire. */
if (tstw.data_in_array[3] != d_wire) begin
$display("FAILED: with a net value.");
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
module test(input [8:1] data_in) ;
wire [7:0] data_in_array[4:3];
assign data_in_array[3] = data_in;
assign data_in_array[4] = 8\'b0;
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: ldelay1.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $
// Test for delays in structural logic. Inertial delays
module test;
wire q;
reg a, b;
and #6 (q, a, b);
task ok;
input qq;
reg error;
begin
\t if (q !== qq)
\t begin
\t error = 1;
\t $display("%0d: FAILED: q=%b, expect %b", $time, q, qq);
\t end
end
endtask
initial
begin
\tok.error = 0;
//\t$dumpvars;
\ta <= 0;
\tb <= 1;
\t#5 ok(1\'b x);
\t#2 ok(1\'b 0);
\ta <= 1;
\t#5 ok(1\'b 0);
\t#2 ok(1\'b 1);
\ta <= 0;
\t#3 ok(1\'b 1);
\ta <= 1;
\t#1 ok(1\'b 1);
\t#1 ok(1\'b 1);
\t#1 ok(1\'b 1);
\t#1 ok(1\'b 1);
\t#1 ok(1\'b 1);
\t#1 ok(1\'b 1);
\t#1 ok(1\'b 1);
\tif (!ok.error)
\t $display("PASSED");
end
endmodule
|
module bts ( z , a , e);
inout z ; wire z ;
input a ; wire a ;
input e ; wire e ;
assign #4 z= ( (e==1\'b1)? a : 1\'bz );
endmodule
module test();
reg [1:0] aa;
wire [1:0] zz;
reg [1:0] ee;
bts sub1 (.z(zz[1]), .a(aa[1]), .e(ee[1]));
bts sub0 (.z(zz[0]), .a(aa[0]), .e(ee[0]));
initial begin
// $dumpvars;
ee=2\'b00;
aa=2\'b00; #100;
if (zz !== 2\'bzz) begin
$display("FAILED -- (1) All disabled, expected HiZ, got %b", zz);
$finish;
end
aa=2\'b11; #100;
if (zz !== 2\'bzz) begin
$display("FAILED -- (2) All disabled, expected HiZ, got %b", zz);
$finish;
end
aa=2\'b00; #100;
if (zz !== 2\'bzz) begin
$display("FAILED -- (3) All disabled, expected HiZ, got %b", zz);
$finish;
end
aa=2\'b11; #100;
if (zz !== 2\'bzz) begin
$display("FAILED -- (4) All disabled, expected HiZ, got %b", zz);
$finish;
end
ee=2\'b11;
aa=2\'b00; #100;
if (zz !== 2\'b00) begin
$display("FAILED -- (5) All enabled, expected 00, got %b", zz);
$finish;
end
aa=2\'b11; #100;
if (zz !== 2\'b11) begin
$display("FAILED -- (6) All enabled, expected 11, got %b", zz);
$finish;
end
aa=2\'b00; #100;
if (zz !== 2\'b00) begin
$display("FAILED -- (7) All enabled, expected 00, got %b", zz);
$finish;
end
aa=2\'b11; #100;
if (zz !== 2\'b11) begin
$display("FAILED -- (8) All enabled, expected 11, got %b", zz);
$finish;
end
$display("PASSED");
end
endmodule
|
// Check that declaring an unpacked array typed member in a packed union is an
// error.
module test;
struct packed {
int x;
shortint y[2];
} s;
initial begin
$display("FAILED");
end
endmodule
|
module example;
reg r, c, e;
reg [4:0] a, b;
wire d;
assign d = ( r | ( a == b ) ) ? 1\'b0 : 1\'b1;
// Change inputs at time n*100
initial begin
#100 r = 1\'bx; a = 5\'bxxxxx; b = 5\'bxxxxx;
#100 r = 1\'b1; a = 5\'bxxxxx; b = 5\'bxxxxx;
#100 r = 1\'b1; a = 5\'b00000; b = 5\'b00000;
#100 r = 1\'b0; a = 5\'b00000; b = 5\'b00000;
#100 $finish(0);
end
// Store c and e at time n*100 + 25.
// Note that the value assigned to c is exactly the same as
// the continuous assignment RHS for d (assigned to e).
initial #25 forever begin
#100
c = ( r | ( a == b ) ) ? 1\'b0 : 1\'b1;
e = d;
end
// Display all values at time n*100 + 50
initial #50 forever begin
#100
$display( "%b,%b,%b = ( %b | ( %b == %b ) ) ? 0 : 1",
c, d, e, r, a, b );
end
endmodule
|
module main;
reg [2:0] X;
wire q_nand, q_nor, q_xnor, q_not;
test_logic DUT(.A(X[0]), .B(X[1]), .q_nand(q_nand), .q_nor(q_nor),
\t\t .q_xnor(q_xnor), .q_not(q_not));
initial begin
for (X = 0 ; X < 4 ; X = X+1) begin
\t #1 /* Let gates settle. */;
\t if (q_nand !== (X[0] ~& X[1])) begin
\t $display("FAILED -- q_nand=%b, X=%b", q_nand, X[1:0]);
\t $finish;
\t end
\t if (q_nor !== (X[0] ~| X[1])) begin
\t $display("FAILED -- q_nor=%b, X=%b", q_nor, X[1:0]);
\t $finish;
\t end
\t if (q_xnor !== (X[0] ~^ X[1])) begin
\t $display("FAILED -- q_xnor=%b, X=%b", q_xnor, X[1:0]);
\t $finish;
\t end
\t if (q_not !== (~X[0])) begin
\t $display("FAILED -- q_not=%b, X=%b", q_not, X[0]);
\t $finish;
\t end
end
$display("PASSED");
end
endmodule // main
|
module test ();
parameter param = 3;
reg [2:0] dummy;
initial dummy = block.f(0);
generate
case (param)
\t 1, 2: if (param==1) begin : block
function [2:0] f;
input i;
begin
$display ("if param==1");
f = param;
end
endfunction
end else begin : block
function [2:0] f;
input i;
begin
$display ("else if param==2");
f = param;
end
endfunction
end
\t 4: begin : block
function [2:0] f;
input i;
begin
$display ("if param==4");
f = param;
end
endfunction // f
\t end
endcase
endgenerate
endmodule
module top ();
test #(1) a();
test #(2) b();
test #(4) c();
initial begin
#1 if (a.dummy !== 1) begin
\t $display("FAILED -- a.dummy = %d", a.dummy);
\t $finish;
end
if (b.dummy !== 2) begin
\t $display("FAILED -- b.dummy = %d", b.dummy);
\t $finish;
end
if (c.dummy !== 4) begin
\t $display("FAILED -- c.dummy = %d", c.dummy);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule
|
/*
* Copyright (c) 2000 Nadim Shaikli <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* This is made up from PR#63 */
module main;
reg one, clk;
reg [1:0] a, b, c, passed;
reg [7:0] count;
always
#1 one = ~one;
// generate a clock
always
#10 clk = ~clk;
initial
begin
$display ("\
<< BEGIN >>");
one = 1\'b1;
clk = 1\'b0;
passed = 2\'b00;
count = 0;
#15 a[1:0] = 2\'b01;
#10 a[1:0] = 2\'b10;
#20 $display ("\
<< END >>");
\tif (passed == 2)
$display ("PASSED");
else
$display ("FAILED");
$finish;
end
always @(clk)
begin
// Problematic lines below -- comment them out to see timing skew
b[1:0] <= #2.5 a[1:0];
c[1:0] <= #7.8 a[1:0];
end
always @(one)
count[7:0] <= count + 1;
always @(count)
begin
case ( count )
\'d25:
if (b[1:0] == 2\'b01)
begin
$display ("@ %0t - Got ONE", $time);
passed = passed + 1;
end
else
$display ("@ %0t - failure", $time);
\'d29:
if (b[1:0] == 2\'b01)
begin
$display ("@ %0t - Got ONE", $time);
passed = passed + 1;
end
else
$display ("@ %0t - failure", $time);
default:
$display ("@ %0t - no count", $time);
endcase
end
// Waves definition
// initial
// begin
// $recordvars("primitives", "drivers");
// $dumpfile("out.dump");
// $dumpvars(5, main);
// Line below ought to work
// $dumpvars;
// end
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate NOR gate vector
//
module main;
reg globvar;
wire [15:0] out;
reg [15:0] a,b, rslt;
reg error;
// The test gate goes HERE!
nor foo [15:0] (out,a,b);
always @(a or b)
rslt = ~(a | b);
initial
begin // {
error = 0;
# 1;
for(a = 16\'h1; a != 16\'h8000; a = (a << 1) )
begin // {
for(b = 16\'h8000; b !== 16\'h0; b = b >> 1)
begin // {
#1 ;
if(out !== rslt)
begin // {
$display("FAILED - GA NOR a=%h,b=%h,expct=%h - rcvd=%h",
a,b,rslt,out);
error = 1;
end // }
end // }
end // }
if( error == 0)
$display("PASSED");
end // }
endmodule // main
|
// Check that it is possible to have a `output reg` in a UDP defintion
module test;
reg clk = 1\'b0;
reg d = 1\'b0;
wire q;
dff ff(q, clk, d);
initial begin
#1
clk = 1\'b1;
#1
clk = 1\'b0;
d = 1\'b1;
if (q === 1\'b0) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
primitive dff(q, c, d);
output reg q;
input c, d;
table
//c d : q : q+
p 0 : ? : 0 ;
p 1 : ? : 1 ;
n ? : ? : - ;
? * : ? : - ;
endtable
endprimitive
|
/*
* Check that the initial value can be out of range and that the next()/prev()
* enumeration methods do not change to a defined state.
*/
module top;
reg pass;
enum bit [3:0] {a2 = 1, b2 = 2, c2 = 3, d2 = 4} evar2;
enum reg [3:0] {a4 = 1, b4 = 2, c4 = 3, d4 = 4} evar4;
initial begin
pass = 1\'b1;
if (evar2 !== 0) begin
$display("Failed initial/2 value should be 0, got %d", evar2);
pass = 1\'b0;
end
if (evar4 !== 4\'bx) begin
$display("Failed initial/4 value should be \'bx, got %d", evar4);
pass = 1\'b0;
end
evar2 = evar2.next;
if (evar2 !== 0) begin
$display("Failed next/2 of an invalid value should be 0, got %d", evar2);
pass = 1\'b0;
end
evar4 = evar4.next;
if (evar4 !== 4\'bx) begin
$display("Failed next/4 of an invalid value should be 0, got %d", evar4);
pass = 1\'b0;
end
evar2 = evar2.prev;
if (evar2 !== 0) begin
$display("Failed prev/2 of an invalid value should be 0, got %d", evar2);
pass = 1\'b0;
end
evar4 = evar4.prev;
if (evar4 !== 4\'bx) begin
$display("Failed prev/4 of an invalid value should be 0, got %d", evar4);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module top;
reg [7:0] result;
initial begin
result = {0{1'b1}}; // This fails top level zero replication.
end
endmodule
|
module top;
integer correct, incorrect;
reg [5:0] bits;
initial begin
bits = 32;
incorrect = -180 + bits*(360.0/63.0);
correct = bits*(360.0/63.0) - 180;
$display("Both of these should be the same (3): %3d, %3d", incorrect,
correct);
$finish(0);
end
endmodule
|
// Check behaviour with variable array indices on LHS of procedural
// continuous (net) assignment. This should be rejected by the compiler.
module top;
wire array1[2:1];
integer index = 1;
initial begin
force array1[index] = 1'b1;
release array1[index];
end
endmodule
|
/*
* This module is a test bench for the sqrt32 module. It runs some
* test input values through the sqrt32 module, and checks that the
* output is valid. If an invalid output is generated, print and
* error message and stop immediately. If all the tested values pass,
* then print PASSED after the test is complete.
*/
module main;
reg [31:0] x;
reg\t clk, reset;
wire [15:0] y;
wire rdy;
chip_root dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
(* ivl_synthesis_off *)
always #5 clk = !clk;
task reset_dut;
begin
\t reset = 1;
\t #1 reset = 0;
\t @(negedge clk) ;
end
endtask // reset_dut
task crank_dut;
begin
\t while (rdy == 0) begin
\t @(posedge clk) /* wait */;
\t end
end
endtask // crank_dut
reg GSR;
assign glbl.GSR = GSR;
integer idx;
(* ivl_synthesis_off *)
initial begin
reset = 0;
clk = 0;
/* If doing a post-map simulation, when we need to wiggle
The GSR bit to simulate chip power-up. */
GSR = 1;
#100 GSR = 0;
#100 x = 1;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
x = 3;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
x = 4;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
for (idx = 0 ; idx < 200 ; idx = idx + 1) begin
\t x = $random;
\t reset_dut;
\t crank_dut;
\t $display("x=%d, y=%d", x, y);
\t if (x < (y * y)) begin
\t $display("ERROR: y is too big");
\t $finish;
\t end
\t if (x > ((y + 1)*(y + 1))) begin
\t $display("ERROR: y is too small");
\t $finish;
\t end
end
$display("PASSED");
$finish;
end
endmodule // main
|
module stimulus (output reg A, B);
initial begin
// both inputs are x
#0 {A, B} = 2\'bxx;
// both inputs are z
#10 {A, B} = 2\'bzz;
// one input is a zero
#10 {A, B} = 2\'b0x;
#10 {A, B} = 2\'bx0;
#10 {A, B} = 2\'b0z;
#10 {A, B} = 2\'bz0;
// one input is a one
#10 {A, B} = 2\'b1x;
#10 {A, B} = 2\'bx1;
#10 {A, B} = 2\'b1z;
#10 {A, B} = 2\'bz1;
// normal bit operands
#10 {A, B} = 2\'b00;
#10 {A, B} = 2\'b01;
#10 {A, B} = 2\'b10;
#10 {A, B} = 2\'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
// both inputs are x
2\'bxx: gate_output = 1\'bx;
// both inputs are z
2\'bzz: gate_output = 1\'bx;
// output should be zero (one input is a zero)
2\'b0x: gate_output = 0;
2\'bx0: gate_output = 0;
2\'b0z: gate_output = 0;
2\'bz0: gate_output = 0;
// output is x (one input is a one)
2\'b1x: gate_output = 1\'bx;
2\'bx1: gate_output = 1\'bx;
2\'b1z: gate_output = 1\'bx;
2\'bz1: gate_output = 1\'bx;
// inputs x, z
2\'bxz: gate_output = 1\'bx;
2\'bzx: gate_output = 1\'bx;
// normal operation on bit
2\'b00: gate_output = 0;
2\'b01: gate_output = 0;
2\'b10: gate_output = 0;
2\'b11: gate_output = 1;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in AND operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
and_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#200;
$display("PASSED");
$finish;
end
endmodule
|
module top;
reg a, enb, q;
reg pass;
always_latch if (enb !== 1\'b1) q <= a !== 1\'bx;
initial begin
pass = 1\'b1;
#1;
if (q !== 1\'b0) begin
$display("Expected q = 1\'b0 with the default 1\'bx input, got %b", q);
pass = 1\'b0;
end
a = 1\'b0;
#1;
if (q !== 1\'b1) begin
$display("Expected q = 1\'b1 with an explicit 1\'b0 input, got %b", q);
pass = 1\'b0;
end
a = 1\'b1;
#1;
if (q !== 1\'b1) begin
$display("Expected q = 1\'b1 with an explicit 1\'b1 input, got %b", q);
pass = 1\'b0;
end
a = 1\'bz;
#1;
if (q !== 1\'b1) begin
$display("Expected q = 1\'b1 with an explicit 1\'bz input, got %b", q);
pass = 1\'b0;
end
a = 1\'bx;
#1;
if (q !== 1\'b0) begin
$display("Expected q = 1\'b0 with an explicit 1\'bx input, got %b", q);
pass = 1\'b0;
end
enb = 1\'b1;
a = 1\'bz;
#1;
if (q !== 1\'b0) begin
$display("Expected q = 1\'b0 with an enb = 1\'b1, got %b", q);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`define _variable 1
module top;
initial begin
if (`_variable == 1) $display("PASSED");
else $display("Fail");
end
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg [7:0] in;
reg [3:0] out;
initial begin
pass = 1\'b1;
in = 8\'b10100101;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in[7:\'dx];
`else
out = 4\'bxxxx;
`endif
if (out !== 4\'bxxxx) begin
$display("FAILED: part select LSB is X, expected 4\'bxxxx, got %b", out);
pass = 1\'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in[\'dx:0];
`else
out = 4\'bxxxx;
`endif
if (out !== 4\'bxxxx) begin
$display("FAILED: part select MSB is X, expected 4\'bxxxx, got %b", out);
pass = 1\'b0;
end
out = 4\'b0000;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out[0] = in[\'dx];
`else
out[0] = 1\'bx;
`endif
if (out !== 4\'b000x) begin
$display("FAILED: bit select is X, expected 4\'b000x, got %b", out);
pass = 1\'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in[7:\'dz];
`else
out = 4\'bxxxx;
`endif
if (out !== 4\'bxxxx) begin
$display("FAILED: part select LSB is Z, expected 4\'bxxxx, got %b", out);
pass = 1\'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in[\'dz:0];
`else
out = 4\'bxxxx;
`endif
if (out !== 4\'bxxxx) begin
$display("FAILED: part select MSB is Z, expected 4\'bxxxx, got %b", out);
pass = 1\'b0;
end
out = 4\'b0000;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out[0] = in[\'dz];
`else
out[0] = 1\'bx;
`endif
if (out !== 4\'b000x) begin
$display("FAILED: bit select is Z, expected 4\'b000x, got %b", out);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module top;
reg pass = 1\'b1;
parameter one = 1\'b1;
parameter zero = 1\'b0;
parameter udef = 1\'bx;
reg [2:0] four = 3\'d4;
reg [2:0] five = 3\'d5;
reg [2:0] six = 3\'d6;
reg [2:0] seven = 3\'d7;
wire real rl1 = one ? four : 4.5; // 4.0
wire real rl2 = zero ? 4.0 : five; // 5.0
wire real rl3 = udef ? six : 6.0; // 6.0
wire real rl4 = udef ? seven : seven; // 7.0
initial begin
#1;
if (rl1 != 4.0) begin
$display("FAILED: real expression one, expected 4.0, got %f", rl1);
pass = 1\'b0;
end
if (rl2 != 5.0) begin
$display("FAILED: real expression two, expected 4.0, got %f", rl2);
pass = 1\'b0;
end
if (rl3 != 6.0) begin
$display("FAILED: real expression three, expected 4.0, got %f", rl3);
pass = 1\'b0;
end
if (rl4 != 7.0) begin
$display("FAILED: real expression four, expected 7.0, got %f", rl4);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module example;
wire y;
reg p01, p01g, s01, s01g;
bufif1 (pull0, pull1 ) ( y, p01, p01g );
bufif1 (strong0, strong1) ( y, s01, s01g );
initial begin
$monitor( "%T Pu:%b/%b St:%b/%b Y:%b,%v",
$time, p01, p01g, s01, s01g, y, y );
{ p01, p01g, s01, s01g } = 4\'b0000;
#100 { p01, p01g, s01, s01g } = 4\'b0x00;
#100 { p01, p01g, s01, s01g } = 4\'b000x;
#100 { p01, p01g, s01, s01g } = 4\'b1x00;
#100 { p01, p01g, s01, s01g } = 4\'b001x;
#100 { p01, p01g, s01, s01g } = 4\'b0100;
#100 { p01, p01g, s01, s01g } = 4\'b0001;
#100 { p01, p01g, s01, s01g } = 4\'b1100;
#100 { p01, p01g, s01, s01g } = 4\'b0011;
#100 { p01, p01g, s01, s01g } = 4\'bx100;
#100 { p01, p01g, s01, s01g } = 4\'b00x1;
#100 { p01, p01g, s01, s01g } = 4\'b010x;
#100 { p01, p01g, s01, s01g } = 4\'bx10x;
#100 { p01, p01g, s01, s01g } = 4\'b111x;
#100 { p01, p01g, s01, s01g } = 4\'bx11x;
#100 ;
end
endmodule
|
// A very simple test to check continuous assignment
// of a constant
module main();
wire p;
assign p = 1;
initial begin
#1;
if (p == 1)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
module main;
\treal x;
\tinitial
\t\tbegin
\t\t\tx = 1.0;
\t\t\t$display("Hello, World");
\t\t\t$display("Positive x is %f", x);
\t\t\t$display("-1.0 * x is %f", -1.0 * x);
\t\t\t$display("0.0 - x is %f", 0.0 - x);
\t\t\t$display("-x is %f", -x);
\t\t\t$finish(0);
\t\tend
endmodule
|
module automatic_error();
task automatic auto_task;
reg local;
begin:block
local <= #1 0;
end
endtask
endmodule
|
/*
* This tests is based on PR#434
*/
`define VAR1 2
`define VAR2 5
module mctrl( reset0, reset1, reset2, reset3, clk, por);
output reset0, reset1, reset2, reset3;
input clk,por;
reg [7:0] cnt;
always @ (posedge por or posedge clk)
if (por)
cnt <= 0;
else
cnt <= cnt+1;
assign reset0 = (cnt == `VAR1);
assign reset1 = (cnt == `VAR2);
assign reset2 = (cnt == `VAR1 + `VAR2);
assign reset3 = (cnt == `VAR1 + `VAR2 + 2);
endmodule
`timescale 1ns/1ps
module test();
reg clk,por;
wire reset0, reset1, reset2, reset3;
mctrl m1(reset0, reset1, reset2, reset3, clk, por);
initial
begin
\tclk = 0;
\tpor = 0;
\t$monitor($time,, "reset0=%b, reset1=%b, reset2=%b, reset3=%b",
\t\t reset0, reset1, reset2, reset3);
\t#1000 $finish(0);
end
always #15 clk = ~clk;
initial
begin
\t#10 por = 1;
\t#10 por = 0;
end
endmodule // test
|
module top_module(
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:N] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
|
// Check that non-blocking event controlled partial writes to a 2-state vector
// are correctly handlded.
module test;
reg failed = 1\'b0;
`define check(val, exp) \\
if (exp !== val) begin \\
$display("FAILED. Got %b, expected %b.", val, exp); \\
failed = 1\'b1; \\
end
bit [3:0] x;
integer i;
event e;
initial begin
// Immediate index
// Within bounds
x = \'h0;
x[2:1] <= @e 2\'b10;
-> e;
`check(x, 4\'b0100)
// Partially oob at high and low side
x = \'h0;
x[4:-1] <= @e 6\'b101010;
-> e;
`check(x, 4\'b0101)
// Partially oob at low side
x = \'h0;
x[0:-1] <= @e 2\'b10;
-> e;
`check(x, 4\'b0001)
// Partially oob at high side
x = \'h0;
x[4:3] <= @e 2\'b01;
-> e;
`check(x, 4\'b1000)
// Fully oob at low side
x = \'h0;
x[-1:-2] <= @e 2\'b11;
-> e;
`check(x, 4\'b0000)
// Fully oob at high side
x = \'h0;
x[6:5] <= @e 2\'b11;
-> e;
`check(x, 4\'b0000)
// Variable index
// Within bounds
i = 1;
x = \'h0;
x[i+:2] <= @e 2\'b10;
-> e;
`check(x, 4\'b0100)
// Partially oob at high and low side
i = -1;
x = \'h0;
x[i+:6] <= @e 6\'b101010;
-> e;
`check(x, 4\'b0101)
// Partially oob at low side
i = -1;
x = \'h0;
x[i+:2] <= @e 2\'b10;
-> e;
`check(x, 4\'b0001)
// Partially oob at high side
i = 3;
x = \'h0;
x[i+:2] <= @e 2\'b01;
-> e;
`check(x, 4\'b1000)
// Fully oob at low side
i = -2;
x = \'h0;
x[i+:2] <= @e 2\'b11;
-> e;
`check(x, 4\'b0000)
// Fully oob at high side
i = 5;
x = \'h0;
x[i+:2] <= @e 2\'b11;
-> e;
`check(x, 4\'b0000)
// Undefined index
i = \'hx;
x = \'h0;
x[i+:2] <= @e 2\'b11;
-> e;
`check(x, 4\'b0000)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
/***********************************************************************
Duplicate input declaration test case
Duplicate port declarations should generate an error
***********************************************************************/
module port_test4 (
\t\t a,\t\t// Input
\t\t b,\t\t// Output
);
input a;
input a;
output b;
assign b=a;
endmodule
|
module top;
reg pass = 1\'b1;
reg signed [7:0] in;
wire real out = in;
initial begin
// $monitor(in,, out);
#1;
if (out != 0.0) begin
$display("Failed: initial value, expected 0.0, got %g", out);
pass = 1\'b0;
end
in = 0;
#1;
if (out != 0.0) begin
$display("Failed: 0 value, expected 0.0, got %g", out);
pass = 1\'b0;
end
in = 1;
#1;
if (out != 1.0) begin
$display("Failed: 1 value, expected 1.0, got %g", out);
pass = 1\'b0;
end
in = -1;
#1;
if (out != -1.0) begin
$display("Failed: -1 value, expected -1.0, got %g", out);
pass = 1\'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//
// Author: Pawel Szostek ([email protected])
// Date: 01.08.2011
`timescale 1ns/1ps
module count_ones_v(input [15:0] vec, output reg [4:0] count);
integer i;
integer result;
always @(vec) begin
result = 0;
for (i=15; i>=0; i=i-1) begin
if(vec[i] == 1\'b1) begin
result = result + 1;
end
end
count = result;
end
endmodule
module check(input [15:0] a, input [4:0] o_vhdl, input [4:0] o_verilog);
reg ena;
initial begin
ena = 0;
#10;
ena = 1;
end
always @(a)begin
#1 if (ena == 0) begin end
else if (o_vhdl !== o_verilog) begin
$display("ERROR!");
$display("VERILOG: ", o_verilog);
$display("VHDL: ", o_vhdl);
end
end
endmodule
module stimulus (output reg [15:0] a);
parameter S = 20000;
int unsigned i,j,k,l;
initial begin //stimulate data
for (i=0; i<S; i=i+1) begin
#5;
for(k=0; k<16; k=k+1) begin
a[k] <= inject();
end
end
end
function inject();
reg [3:0] temp;
begin
temp = $random % 16;
if(temp >= 10)
inject = 1\'b1;
else
inject = 1\'b0;
end
endfunction
endmodule
module main;
wire [15:0] a;
wire [4:0] o_vhdl, o_verilog;
count_ones_v c_vhdl(a,o_vhdl);
count_ones c_verilog(a,o_verilog);
stimulus stim(a);
check c(a,o_vhdl, o_verilog);
initial begin
#120000;
$display("PASSED");
end
endmodule
|
/*
* Verification test for increment/decrement operators
*
* Author: Prasad Joshi <[email protected]>
*/
module main;
logic la;
logic lb;
int ia;
int ib;
bit ba;
bit bb;
real ra;
real rb;
real rc;
\tinitial begin
\t\t/* logic tests */
\t\tla = 0;
\t\t#1
\t\tlb = ++la;
\t\t#1
\t\tif (la != lb) begin
\t\t\t$display("FAILED");
\t\t\t$finish;
\t\tend
\t\tib = 15;
\t\t#1
\t\tia = ++ib;
\t\t#1
\t\tif (ia != ib) begin
\t\t\t$display("FAILED");
\t\t\t$finish;
\t\tend
\t\tia = 15;
\t\t#1
\t\tib = ia++;
\t\t#1
\t\tif (ia != 16 || ib != 15) begin
\t\t\t$display("FAILED");
\t\t\t$finish;
\t\tend
\t\tib = --ia;
\t\tif (ib != ia) begin
\t\t\t$display("FAILED");
\t\t\t$finish;
\t\tend
\t\t/* bit test */
\t\tba = 0;
\t\t#1
\t\tfor (ia = 0; ia < 10; ia = ia + 1) begin
\t\t\tbb = --ba;
\t\t\t#1
\t\t\tif (bb != ba && !(bb == 1 || bb == 0)) begin
\t\t\t\t$display("FAILED");
\t\t\t\t$finish;
\t\t\tend
\t\tend
\t\t/* real decrement test */
\t\tia = 15;
\t\tra = --ia;
\t\tif (ra != ia) begin
\t\t\t$display("FAILED");
\t\t\t$finish;
\t\tend
\t\trb = 19.99;
\t\trc = rb - 2;
\t\tra = --rb;
\t\tif (ra != rb) begin
\t\t\t$display("FAILED");
\t\t\t$finish;
\t\tend
\t\tra = rb--;
\t\tif (ra == rb || rc != rb) begin
\t\t\t$display("FAILED");
\t\t\t$finish;
\t\tend
\t\t/* real increment test */
\t\tia = 15;
\t\tra = ++ia;
\t\tif (ra != ia) begin
\t\t\t$display("FAILED");
\t\t\t$finish;
\t\tend
\t\trb = 19.99;
\t\trc = rb + 2;
\t\tra = ++rb;
\t\tif (ra != rb) begin
\t\t\t$display("FAILED");
\t\t\t$finish;
\t\tend
\t\tra = rb++;
\t\tif (ra == rb || rc != rb) begin
\t\t\t$display("FAILED");
\t\t\t$finish;
\t\tend
\t\t$display("PASSED");
\tend
endmodule
|
module test();
reg a, b, en;
wire a1, a2, a3, a4, a5, a6, a7;
assign (supply1, supply0) a1 = a;
tranif0 t1(a1, a2, en);
tranif0 t2(a2, a3, en);
tranif0 t3(a3, a4, en);
tranif0 t4(a4, a5, en);
tranif0 t5(a5, a6, en);
tranif0 t6(a6, a7, en);
wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15;
wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25;
wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35;
wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45;
wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55;
assign (supply1, supply0) a11 = a, b11 = b;
assign (supply1, strong0) a12 = a, b12 = b;
assign (supply1, pull0) a13 = a, b13 = b;
assign (supply1, weak0) a14 = a, b14 = b;
assign (supply1, highz0) a15 = a, b15 = b;
assign (strong1, supply0) a21 = a, b21 = b;
assign (strong1, strong0) a22 = a, b22 = b;
assign (strong1, pull0) a23 = a, b23 = b;
assign (strong1, weak0) a24 = a, b24 = b;
assign (strong1, highz0) a25 = a, b25 = b;
assign ( pull1, supply0) a31 = a, b31 = b;
assign ( pull1, strong0) a32 = a, b32 = b;
assign ( pull1, pull0) a33 = a, b33 = b;
assign ( pull1, weak0) a34 = a, b34 = b;
assign ( pull1, highz0) a35 = a, b35 = b;
assign ( weak1, supply0) a41 = a, b41 = b;
assign ( weak1, strong0) a42 = a, b42 = b;
assign ( weak1, pull0) a43 = a, b43 = b;
assign ( weak1, weak0) a44 = a, b44 = b;
assign ( weak1, highz0) a45 = a, b45 = b;
assign ( highz1, supply0) a51 = a, b51 = b;
assign ( highz1, strong0) a52 = a, b52 = b;
assign ( highz1, pull0) a53 = a, b53 = b;
assign ( highz1, weak0) a54 = a, b54 = b;
tranif0 t11(a11, b11, en);
tranif0 t12(a12, b12, en);
tranif0 t13(a13, b13, en);
tranif0 t14(a14, b14, en);
tranif0 t15(a15, b15, en);
tranif0 t21(a21, b21, en);
tranif0 t22(a22, b22, en);
tranif0 t23(a23, b23, en);
tranif0 t24(a24, b24, en);
tranif0 t25(a25, b25, en);
tranif0 t31(a31, b31, en);
tranif0 t32(a32, b32, en);
tranif0 t33(a33, b33, en);
tranif0 t34(a34, b34, en);
tranif0 t35(a35, b35, en);
tranif0 t41(a41, b41, en);
tranif0 t42(a42, b42, en);
tranif0 t43(a43, b43, en);
tranif0 t44(a44, b44, en);
tranif0 t45(a45, b45, en);
tranif0 t51(a51, b51, en);
tranif0 t52(a52, b52, en);
tranif0 t53(a53, b53, en);
tranif0 t54(a54, b54, en);
tranif0 t55(a55, b55, en);
task display_strengths;
input ta, tb, ten;
begin
a = ta;
b = tb;
en = ten;
#1;
$display("a = %b b = %b en = %b", a, b, en);
$display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7);
$display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15);
$display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25);
$display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35);
$display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45);
$display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55);
end
endtask
initial begin
display_strengths(1\'bz, 1\'bz, 1\'bz);
display_strengths(1\'bz, 1\'bz, 1\'bx);
display_strengths(1\'bz, 1\'bz, 1\'b0);
display_strengths(1\'bz, 1\'bz, 1\'b1);
display_strengths(1\'bx, 1\'bz, 1\'bz);
display_strengths(1\'bx, 1\'bz, 1\'bx);
display_strengths(1\'bx, 1\'bz, 1\'b0);
display_strengths(1\'bx, 1\'bz, 1\'b1);
display_strengths(1\'b0, 1\'bz, 1\'bz);
display_strengths(1\'b0, 1\'bz, 1\'bx);
display_strengths(1\'b0, 1\'bz, 1\'b0);
display_strengths(1\'b0, 1\'bz, 1\'b1);
display_strengths(1\'b1, 1\'bz, 1\'bz);
display_strengths(1\'b1, 1\'bz, 1\'bx);
display_strengths(1\'b1, 1\'bz, 1\'b0);
display_strengths(1\'b1, 1\'bz, 1\'b1);
display_strengths(1\'bz, 1\'bx, 1\'bz);
display_strengths(1\'bz, 1\'bx, 1\'bx);
display_strengths(1\'bz, 1\'bx, 1\'b0);
display_strengths(1\'bz, 1\'bx, 1\'b1);
display_strengths(1\'bx, 1\'bx, 1\'bz);
display_strengths(1\'bx, 1\'bx, 1\'bx);
display_strengths(1\'bx, 1\'bx, 1\'b0);
display_strengths(1\'bx, 1\'bx, 1\'b1);
display_strengths(1\'b0, 1\'bx, 1\'bz);
display_strengths(1\'b0, 1\'bx, 1\'bx);
display_strengths(1\'b0, 1\'bx, 1\'b0);
display_strengths(1\'b0, 1\'bx, 1\'b1);
display_strengths(1\'b1, 1\'bx, 1\'bz);
display_strengths(1\'b1, 1\'bx, 1\'bx);
display_strengths(1\'b1, 1\'bx, 1\'b0);
display_strengths(1\'b1, 1\'bx, 1\'b1);
display_strengths(1\'bz, 1\'b0, 1\'bz);
display_strengths(1\'bz, 1\'b0, 1\'bx);
display_strengths(1\'bz, 1\'b0, 1\'b0);
display_strengths(1\'bz, 1\'b0, 1\'b1);
display_strengths(1\'bx, 1\'b0, 1\'bz);
display_strengths(1\'bx, 1\'b0, 1\'bx);
display_strengths(1\'bx, 1\'b0, 1\'b0);
display_strengths(1\'bx, 1\'b0, 1\'b1);
display_strengths(1\'b0, 1\'b0, 1\'bz);
display_strengths(1\'b0, 1\'b0, 1\'bx);
display_strengths(1\'b0, 1\'b0, 1\'b0);
display_strengths(1\'b0, 1\'b0, 1\'b1);
display_strengths(1\'b1, 1\'b0, 1\'bz);
display_strengths(1\'b1, 1\'b0, 1\'bx);
display_strengths(1\'b1, 1\'b0, 1\'b0);
display_strengths(1\'b1, 1\'b0, 1\'b1);
display_strengths(1\'bz, 1\'b1, 1\'bz);
display_strengths(1\'bz, 1\'b1, 1\'bx);
display_strengths(1\'bz, 1\'b1, 1\'b0);
display_strengths(1\'bz, 1\'b1, 1\'b1);
display_strengths(1\'bx, 1\'b1, 1\'bz);
display_strengths(1\'bx, 1\'b1, 1\'bx);
display_strengths(1\'bx, 1\'b1, 1\'b0);
display_strengths(1\'bx, 1\'b1, 1\'b1);
display_strengths(1\'b0, 1\'b1, 1\'bz);
display_strengths(1\'b0, 1\'b1, 1\'bx);
display_strengths(1\'b0, 1\'b1, 1\'b0);
display_strengths(1\'b0, 1\'b1, 1\'b1);
display_strengths(1\'b1, 1\'b1, 1\'bz);
display_strengths(1\'b1, 1\'b1, 1\'bx);
display_strengths(1\'b1, 1\'b1, 1\'b0);
display_strengths(1\'b1, 1\'b1, 1\'b1);
end
endmodule
|
// Copyright (c) 2014 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Tests signal initializers.
module vhdl_init_testbench;
vhdl_init dut();
initial begin
// Simply check if the assigned values are correct
if (dut.a !== \'b11101001) begin
$display("FAILED #1: expected 11101001, got %b", dut.a);
$finish;
end
if (dut.b !== \'b1010) begin
$display("FAILED #2: expected 1010, got %b", dut.b);
$finish;
end
if (dut.c !== \'b1000) begin
$display("FAILED #3: expected 1000, got %b", dut.c);
$finish;
end
$display("PASSED");
end
endmodule
|
// Check that it is possible to declare the data type for an atom2 type module
// port before the direction for non-ANSI style port declarations.
module test(x, y, z, w);
byte x;
shortint y;
int z;
longint w;
output x;
output y;
output z;
output w;
initial begin
if ($bits(x) == 8 && $bits(y) == 16 &&
$bits(z) == 32 && $bits(w) == 64) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
|
primitive latch(q, e, d);
output q;
input e;
input d;
reg q;
table
// e d | q | q+ |
1 1 : ? : 1 ;
1 0 : ? : 0 ;
0 ? : ? : - ;
endtable
endprimitive
module test();
wire q;
reg e;
reg d;
reg r;
latch latch(q, e, d);
always @(q) begin
r = 1;
end
initial begin
#1;
$display("%b %b", q, r);
// the \'x\' should propagate to q before the start of simulation
if (r === 1\'bx && q === 1\'bx)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* Based on PR#1000.
*/
module foo20 ();
/* This is reported to return the warning:
warning: Ranges in localparam definition are not supported.
The value is OK, and the compiler chooses a width that holds
whatever value is there. */
localparam [65:0] foo = 0;
initial begin
if ($bits(foo) != 66) begin
\t $display("FAILED -- $bits(foo) --> %0d", $bits(foo));
\t $finish;
end
$display("PASSED");
end
endmodule
|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
|
`timescale 100 ps / 10 ps
module main;
wire Q;
reg\tD, G;
LD u1 (.Q(Q), .D(D), .G(G));
initial begin
D = 0;
G = 1;
#1 if (Q !== 0) begin
\t $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
\t $finish;
end
D = 1;
#1 if (Q !== 1) begin
\t $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
\t $finish;
end
G = 0;
#1 if (Q !== 1) begin
\t $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
\t $finish;
end
D = 0;
#1 if (Q !== 1) begin
\t $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
\t $finish;
end
G = 1;
#1 if (Q !== 0) begin
\t $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
\t $finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module main;
reg [7:0] val;
ornor7 dut (.O_OR(o_or), .O_NOR(o_nor),
\t .I0(val[0]), .I1(val[1]), .I2(val[2]), .I3(val[3]),
\t .I4(val[4]), .I5(val[5]), .I6(val[6]));
initial begin
for (val = 0 ; val[7] == 0 ; val = val+1) begin
\t #1 if (o_or !== |val[6:0]) begin
\t $display("FAILED -- |%b --> %b", val[6:0], o_or);
\t $finish;
\t end
\t if (o_nor !== ~|val[6:0]) begin
\t $display("FAILED -- ~|%b --> %b", val[6:0], o_nor);
\t $finish;
\t end
end
$display("PASSED");
end // initial begin
endmodule // main
|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
|
../../../third_party/VexRiscv_Lite/VexRiscv_Lite.v
|
../../../third_party/minilitex_ddr_arty/minilitex_ddr_arty.v
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input cpu_reset,
input data_in,
output [5:0] data_out
);
wire [5:0] data_out;
wire builder_pll_fb;
wire fdce_0_out, fdce_1_out;
wire main_locked;
wire clk_ibuf;
IBUF ibuf_clk(.I(clk), .O(clk_ibuf));
wire clk_bufg;
BUFG bufg_clk(.I(clk_ibuf), .O(clk_bufg));
FDCE FDCE_0 (
.D (data_in),
.C (clk_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (fdce_0_out)
);
FDCE FDCE_1 (
.D (fdce_0_out),
.C (clk_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[0])
);
PLLE2_ADV #(
.CLKFBOUT_MULT(4\'d12),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(4\'d12),
.CLKOUT0_PHASE(90.0),
.CLKOUT1_DIVIDE(2\'d3),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(3\'d6),
.CLKOUT2_PHASE(90.0),
.DIVCLK_DIVIDE(1\'d1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
.CLKOUT1(main_clkout1),
.CLKOUT2(main_clkout2),
.LOCKED(main_locked)
);
wire main_clkout0_bufg;
wire main_clkout1_bufg;
wire main_clkout2_bufg;
BUFG bufg_clkout0 (.I(main_clkout0), .O(main_clkout0_bufg));
BUFG bufg_clkout1 (.I(main_clkout1), .O(main_clkout1_bufg));
BUFG bufg_clkout2 (.I(main_clkout2), .O(main_clkout2_bufg));
FDCE FDCE_PLLx1_PH90 (
.D (data_in),
.C (main_clkout0_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[1])
);
FDCE FDCE_PLLx4_PH0_0 (
.D (data_in),
.C (main_clkout1_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[2])
);
FDCE FDCE_PLLx4_PH0_1 (
.D (data_in),
.C (main_clkout1_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[3])
);
FDCE FDCE_PLLx4_PH0_2 (
.D (data_in),
.C (main_clkout1_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[4])
);
FDCE FDCE_PLLx2_PH90_0 (
.D (data_in),
.C (main_clkout2_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[5])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1\'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
(* test_attr = "true" *)
.I(LD6),
.O(led[0])
);
(* dont_touch = "true" *) OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
(* dont_touch = "true" *) OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
(* async_reg = "true", mr_ff = "false", dont_touch = "true" *)
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module inv (
output Q,
input A
);
assign Q = A ? 0 : 1;
endmodule
module buff (
output Q,
input A
);
assign Q = A;
endmodule
module logic_0 (
output a
);
assign a = 0;
endmodule
module logic_1 (
output a
);
assign a = 1;
endmodule
(* blackbox *)
module gclkbuff (
input A,
output Z
);
assign Z = A;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module inpad (
output Q,
(* iopad_external_pin *)
input P
);
assign Q = P;
endmodule
module outpad (
(* iopad_external_pin *)
output P,
input A
);
assign P = A;
endmodule
module ckpad (
output Q,
(* iopad_external_pin *)
input P
);
assign Q = P;
endmodule
module bipad (
input A,
input EN,
output Q,
(* iopad_external_pin *)
inout P
);
assign Q = P;
assign P = EN ? A : 1\'bz;
endmodule
module dff (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge CLK) Q <= D;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input cpu_reset,
input data_in,
output [5:0] data_out
);
wire [5:0] data_out;
wire builder_pll_fb;
wire fdce_0_out, fdce_1_out;
wire main_locked;
FDCE FDCE_0 (
.D (data_in),
.C (clk),
.CE (1\'b1),
.CLR(1\'b0),
.Q (fdce_0_out)
);
FDCE FDCE_1 (
.D (fdce_0_out),
.C (clk),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[0])
);
PLLE2_ADV #(
.CLKFBOUT_MULT(4\'d12),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(4\'d12),
.CLKOUT0_PHASE(90.0),
.CLKOUT1_DIVIDE(2\'d3),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(3\'d6),
.CLKOUT2_PHASE(90.0),
.DIVCLK_DIVIDE(2\'d2),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
.CLKOUT1(main_clkout1),
.CLKOUT2(main_clkout2),
.LOCKED(main_locked)
);
FDCE FDCE_PLLx1_PH90 (
.D (data_in),
.C (main_clkout0),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[1])
);
FDCE FDCE_PLLx4_PH0_0 (
.D (data_in),
.C (main_clkout1),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[2])
);
FDCE FDCE_PLLx4_PH0_1 (
.D (data_in),
.C (main_clkout1),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[3])
);
FDCE FDCE_PLLx4_PH0_2 (
.D (data_in),
.C (main_clkout1),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[4])
);
FDCE FDCE_PLLx2_PH90_0 (
.D (data_in),
.C (main_clkout2),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[5])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
module box(
(* invertible_pin="INV_A" *)
input wire [1:0] A,
input wire [1:0] B,
output wire Y
);
parameter [1:0] INV_A = 2\'b00;
endmodule
module top(
input wire [3:0] di,
output wire do
);
wire [3:0] d;
\\$_NOT_ n0 (.A(di[0]), .Y(d[0]));
\\$_NOT_ n1 (.A(di[1]), .Y(d[1]));
\\$_NOT_ n2 (.A(di[2]), .Y(d[2]));
\\$_NOT_ n3 (.A(di[3]), .Y(d[3]));
box #(.INV_A(2\'b01)) the_box (
.A ({d[1], d[0]}),
.B ({d[3], d[2]}),
.Y (do)
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* CLOCK_SIGNAL = "yes", WAVEFORM = "0 5" *)
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[1:0] = {cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
// ============================================================================
// CMT
// PLLE2_ADV_VPR
(* blackbox *)
module PLLE2_ADV_VPR (
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
output CLKFBOUT,
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
input PWRDWN,
input RST,
output LOCKED,
input DCLK,
input DEN,
input DWE,
output DRDY,
input [ 6:0] DADDR,
input [15:0] DI,
output [15:0] DO
);
parameter [0:0] INV_CLKINSEL = 1\'d0;
parameter [0:0] ZINV_PWRDWN = 1\'d0;
parameter [0:0] ZINV_RST = 1\'d1;
parameter [0:0] STARTUP_WAIT = 1\'d0;
// Tables
parameter [9:0] TABLE = 10\'d0;
parameter [39:0] LKTABLE = 40\'d0;
parameter [15:0] POWER_REG = 16\'d0;
parameter [11:0] FILTREG1_RESERVED = 12\'d0;
parameter [9:0] FILTREG2_RESERVED = 10\'d0;
parameter [5:0] LOCKREG1_RESERVED = 6\'d0;
parameter [0:0] LOCKREG2_RESERVED = 1\'b0;
parameter [0:0] LOCKREG3_RESERVED = 1\'b0;
// DIVCLK
parameter [5:0] DIVCLK_DIVCLK_HIGH_TIME = 6\'d0;
parameter [5:0] DIVCLK_DIVCLK_LOW_TIME = 6\'d0;
parameter [0:0] DIVCLK_DIVCLK_NO_COUNT = 1\'b1;
parameter [0:0] DIVCLK_DIVCLK_EDGE = 1\'b0;
// CLKFBOUT
parameter [5:0] CLKFBOUT_CLKOUT1_HIGH_TIME = 6\'d0;
parameter [5:0] CLKFBOUT_CLKOUT1_LOW_TIME = 6\'d0;
parameter [0:0] CLKFBOUT_CLKOUT1_OUTPUT_ENABLE = 1\'b0;
parameter [2:0] CLKFBOUT_CLKOUT1_PHASE_MUX = 3\'d0;
parameter [5:0] CLKFBOUT_CLKOUT2_DELAY_TIME = 6\'d0;
parameter [0:0] CLKFBOUT_CLKOUT2_EDGE = 1\'b0;
parameter [2:0] CLKFBOUT_CLKOUT2_FRAC = 3\'d0;
parameter [0:0] CLKFBOUT_CLKOUT2_FRAC_EN = 1\'b0;
parameter [0:0] CLKFBOUT_CLKOUT2_FRAC_WF_R = 1\'b0;
parameter [0:0] CLKFBOUT_CLKOUT2_NO_COUNT = 1\'b1;
// CLKOUT0
parameter [5:0] CLKOUT0_CLKOUT1_HIGH_TIME = 6\'d0;
parameter [5:0] CLKOUT0_CLKOUT1_LOW_TIME = 6\'d0;
parameter [0:0] CLKOUT0_CLKOUT1_OUTPUT_ENABLE = 1\'b0;
parameter [2:0] CLKOUT0_CLKOUT1_PHASE_MUX = 3\'d0;
parameter [5:0] CLKOUT0_CLKOUT2_DELAY_TIME = 6\'d0;
parameter [0:0] CLKOUT0_CLKOUT2_EDGE = 1\'b0;
parameter [2:0] CLKOUT0_CLKOUT2_FRAC = 3\'d0;
parameter [0:0] CLKOUT0_CLKOUT2_FRAC_EN = 1\'b0;
parameter [0:0] CLKOUT0_CLKOUT2_FRAC_WF_R = 1\'b0;
parameter [0:0] CLKOUT0_CLKOUT2_NO_COUNT = 1\'b1;
// CLKOUT1
parameter [5:0] CLKOUT1_CLKOUT1_HIGH_TIME = 6\'d0;
parameter [5:0] CLKOUT1_CLKOUT1_LOW_TIME = 6\'d0;
parameter [0:0] CLKOUT1_CLKOUT1_OUTPUT_ENABLE = 1\'b0;
parameter [2:0] CLKOUT1_CLKOUT1_PHASE_MUX = 3\'d0;
parameter [5:0] CLKOUT1_CLKOUT2_DELAY_TIME = 6\'d0;
parameter [0:0] CLKOUT1_CLKOUT2_EDGE = 1\'b0;
parameter [2:0] CLKOUT1_CLKOUT2_FRAC = 3\'d0;
parameter [0:0] CLKOUT1_CLKOUT2_FRAC_EN = 1\'b0;
parameter [0:0] CLKOUT1_CLKOUT2_FRAC_WF_R = 1\'b0;
parameter [0:0] CLKOUT1_CLKOUT2_NO_COUNT = 1\'b1;
// CLKOUT2
parameter [5:0] CLKOUT2_CLKOUT1_HIGH_TIME = 6\'d0;
parameter [5:0] CLKOUT2_CLKOUT1_LOW_TIME = 6\'d0;
parameter [0:0] CLKOUT2_CLKOUT1_OUTPUT_ENABLE = 1\'b0;
parameter [2:0] CLKOUT2_CLKOUT1_PHASE_MUX = 3\'d0;
parameter [5:0] CLKOUT2_CLKOUT2_DELAY_TIME = 6\'d0;
parameter [0:0] CLKOUT2_CLKOUT2_EDGE = 1\'b0;
parameter [2:0] CLKOUT2_CLKOUT2_FRAC = 3\'d0;
parameter [0:0] CLKOUT2_CLKOUT2_FRAC_EN = 1\'b0;
parameter [0:0] CLKOUT2_CLKOUT2_FRAC_WF_R = 1\'b0;
parameter [0:0] CLKOUT2_CLKOUT2_NO_COUNT = 1\'b1;
// CLKOUT3
parameter [5:0] CLKOUT3_CLKOUT1_HIGH_TIME = 6\'d0;
parameter [5:0] CLKOUT3_CLKOUT1_LOW_TIME = 6\'d0;
parameter [0:0] CLKOUT3_CLKOUT1_OUTPUT_ENABLE = 1\'b0;
parameter [2:0] CLKOUT3_CLKOUT1_PHASE_MUX = 3\'d0;
parameter [5:0] CLKOUT3_CLKOUT2_DELAY_TIME = 6\'d0;
parameter [0:0] CLKOUT3_CLKOUT2_EDGE = 1\'b0;
parameter [2:0] CLKOUT3_CLKOUT2_FRAC = 3\'d0;
parameter [0:0] CLKOUT3_CLKOUT2_FRAC_EN = 1\'b0;
parameter [0:0] CLKOUT3_CLKOUT2_FRAC_WF_R = 1\'b0;
parameter [0:0] CLKOUT3_CLKOUT2_NO_COUNT = 1\'b1;
// CLKOUT4
parameter [5:0] CLKOUT4_CLKOUT1_HIGH_TIME = 6\'d0;
parameter [5:0] CLKOUT4_CLKOUT1_LOW_TIME = 6\'d0;
parameter [0:0] CLKOUT4_CLKOUT1_OUTPUT_ENABLE = 1\'b0;
parameter [2:0] CLKOUT4_CLKOUT1_PHASE_MUX = 3\'d0;
parameter [5:0] CLKOUT4_CLKOUT2_DELAY_TIME = 6\'d0;
parameter [0:0] CLKOUT4_CLKOUT2_EDGE = 1\'b0;
parameter [2:0] CLKOUT4_CLKOUT2_FRAC = 3\'d0;
parameter [0:0] CLKOUT4_CLKOUT2_FRAC_EN = 1\'b0;
parameter [0:0] CLKOUT4_CLKOUT2_FRAC_WF_R = 1\'b0;
parameter [0:0] CLKOUT4_CLKOUT2_NO_COUNT = 1\'b1;
// CLKOUT5
parameter [5:0] CLKOUT5_CLKOUT1_HIGH_TIME = 6\'d0;
parameter [5:0] CLKOUT5_CLKOUT1_LOW_TIME = 6\'d0;
parameter [0:0] CLKOUT5_CLKOUT1_OUTPUT_ENABLE = 1\'b0;
parameter [2:0] CLKOUT5_CLKOUT1_PHASE_MUX = 3\'d0;
parameter [5:0] CLKOUT5_CLKOUT2_DELAY_TIME = 6\'d0;
parameter [0:0] CLKOUT5_CLKOUT2_EDGE = 1\'b0;
parameter [2:0] CLKOUT5_CLKOUT2_FRAC = 3\'d0;
parameter [0:0] CLKOUT5_CLKOUT2_FRAC_EN = 1\'b0;
parameter [0:0] CLKOUT5_CLKOUT2_FRAC_WF_R = 1\'b0;
parameter [0:0] CLKOUT5_CLKOUT2_NO_COUNT = 1\'b1;
// TODO: Compensation parameters
// TODO: How to simulate a PLL in verilog (i.e. the VCO) ???
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
module box(
(* invertible_pin="INV_A" *)
input wire A,
input wire B,
(* invertible_pin="INV_C" *)
input wire C,
input wire D,
output wire Y
);
parameter [0:0] INV_A = 1\'b0;
parameter [0:0] INV_C = 1\'b0;
endmodule
module top(
input wire [3:0] di,
output wire do
);
wire [3:0] d;
\\$_NOT_ n0 (.A(di[0]), .Y(d[0]));
\\$_NOT_ n1 (.A(di[1]), .Y(d[1]));
\\$_NOT_ n2 (.A(di[2]), .Y(d[2]));
\\$_NOT_ n3 (.A(di[3]), .Y(d[3]));
box #(.INV_A(1\'b1)) the_box (
.A (d[0]),
.B (d[1]),
.C (d[2]),
.D (d[3]),
.Y (do)
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input i,
output o
);
reg [0:0] outff = 0;
assign o = outff;
always @(posedge clk) begin
outff <= i;
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module GTPE2_CHANNEL (
(* iopad_external_pin *)
output GTPTXN,
(* iopad_external_pin *)
output GTPTXP,
(* iopad_external_pin *)
input GTPRXN,
(* iopad_external_pin *)
input GTPRXP
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1\'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`timescale 1ns / 10ps
module fifo_controller_model (
Rst_n,
Push_Clk,
Pop_Clk,
Fifo_Push,
Fifo_Push_Flush,
Fifo_Full,
Fifo_Full_Usr,
Fifo_Pop,
Fifo_Pop_Flush,
Fifo_Empty,
Fifo_Empty_Usr,
Write_Addr,
Read_Addr,
//\t Static Control Signals
Fifo_Ram_Mode,
Fifo_Sync_Mode,
Fifo_Push_Width,
Fifo_Pop_Width
);
//************* PPII 4K Parameters **************************//
parameter MAX_PTR_WIDTH = 12;
parameter DEPTH1 = (1 << (MAX_PTR_WIDTH - 3));
parameter DEPTH2 = (1 << (MAX_PTR_WIDTH - 2));
parameter DEPTH3 = (1 << (MAX_PTR_WIDTH - 1));
parameter D1_QTR_A = MAX_PTR_WIDTH - 5;
parameter D2_QTR_A = MAX_PTR_WIDTH - 4;
parameter D3_QTR_A = MAX_PTR_WIDTH - 3;
input Rst_n;
input Push_Clk;
input Pop_Clk;
input Fifo_Push;
input Fifo_Push_Flush;
output Fifo_Full;
output [3:0] Fifo_Full_Usr;
input Fifo_Pop;
input Fifo_Pop_Flush;
output Fifo_Empty;
output [3:0] Fifo_Empty_Usr;
output [MAX_PTR_WIDTH-2:0] Write_Addr;
output [MAX_PTR_WIDTH-2:0] Read_Addr;
input Fifo_Ram_Mode;
input Fifo_Sync_Mode;
input [1:0] Fifo_Push_Width;
input [1:0] Fifo_Pop_Width;
reg flush_pop_clk_tf;
reg flush_pop2push_clk1;
reg flush_push_clk_tf;
reg flush_push2pop_clk1;
reg pop_local_flush_mask;
reg push_flush_tf_pop_clk;
reg pop2push_ack1;
reg pop2push_ack2;
reg push_local_flush_mask;
reg pop_flush_tf_push_clk;
reg push2pop_ack1;
reg push2pop_ack2;
reg fifo_full_flag_f;
reg [3:0] Fifo_Full_Usr;
reg fifo_empty_flag_f;
reg [3:0] Fifo_Empty_Usr;
reg [MAX_PTR_WIDTH-1:0] push_ptr_push_clk;
reg [MAX_PTR_WIDTH-1:0] pop_ptr_push_clk;
reg [MAX_PTR_WIDTH-1:0] pop_ptr_async;
reg [MAX_PTR_WIDTH-1:0] pop_ptr_pop_clk ;
reg [MAX_PTR_WIDTH-1:0] push_ptr_pop_clk;
reg [MAX_PTR_WIDTH-1:0] push_ptr_async;
reg [1:0] push_ptr_push_clk_mask;
reg [1:0] pop_ptr_pop_clk_mask;
reg [MAX_PTR_WIDTH-1:0] pop_ptr_push_clk_mux;
reg [MAX_PTR_WIDTH-1:0] push_ptr_pop_clk_mux;
reg match_room4none;
reg match_room4one;
reg match_room4half;
reg match_room4quart;
reg match_all_left;
reg match_half_left;
reg match_quart_left;
reg [MAX_PTR_WIDTH-1:0] depth1_reg;
reg [MAX_PTR_WIDTH-1:0] depth2_reg;
reg [MAX_PTR_WIDTH-1:0] depth3_reg;
wire\tpush_clk_rst;
wire\tpush_clk_rst_mux;
wire\tpush_flush_done;
wire\tpop_clk_rst;
wire\tpop_clk_rst_mux;
wire\tpop_flush_done;
wire\tpush_flush_gated;
wire\tpop_flush_gated;
wire\t[MAX_PTR_WIDTH-2:0] Write_Addr;
wire\t[MAX_PTR_WIDTH-2:0] Read_Addr;
wire\t[MAX_PTR_WIDTH-1:0] push_ptr_push_clk_plus1;
wire\t[MAX_PTR_WIDTH-1:0] next_push_ptr_push_clk;
wire\t[MAX_PTR_WIDTH-1:0] pop_ptr_pop_clk_plus1;
wire\t[MAX_PTR_WIDTH-1:0] next_pop_ptr_pop_clk;
wire\t[MAX_PTR_WIDTH-1:0] next_push_ptr_push_clk_mask;
wire\t[MAX_PTR_WIDTH-1:0] next_pop_ptr_pop_clk_mask;
wire\t[MAX_PTR_WIDTH-1:0] pop_ptr_push_clk_l_shift1;
wire\t[MAX_PTR_WIDTH-1:0] pop_ptr_push_clk_l_shift2;
wire\t[MAX_PTR_WIDTH-1:0] pop_ptr_push_clk_r_shift1;
wire\t[MAX_PTR_WIDTH-1:0] pop_ptr_push_clk_r_shift2;
wire\t[MAX_PTR_WIDTH-1:0] push_ptr_pop_clk_l_shift1;
wire\t[MAX_PTR_WIDTH-1:0] push_ptr_pop_clk_l_shift2;
wire\t[MAX_PTR_WIDTH-1:0] push_ptr_pop_clk_r_shift1;
wire\t[MAX_PTR_WIDTH-1:0] push_ptr_pop_clk_r_shift2;
wire\t[MAX_PTR_WIDTH-1:0] push_diff;
wire\t[MAX_PTR_WIDTH-1:0] push_diff_plus_1;
wire\t[MAX_PTR_WIDTH-1:0] pop_diff;
wire\tmatch_room4all;
wire\tmatch_room4eight;
wire\tmatch_one_left;
wire\tmatch_one2eight_left;
integer\tdepth_sel_push;
integer depth_sel_pop;
initial begin
depth1_reg = DEPTH1;
depth2_reg = DEPTH2;
depth3_reg = DEPTH3;
end
initial begin
flush_pop_clk_tf <= 1\'b0;
push2pop_ack1 <= 1\'b0;
push2pop_ack2 <= 1\'b0;
pop_local_flush_mask <= 1\'b0;
flush_push2pop_clk1 <= 1\'b0;
push_flush_tf_pop_clk <= 1\'b0;
flush_push_clk_tf <= 1\'b0;
pop2push_ack1 <= 1\'b0;
pop2push_ack2 <= 1\'b0;
push_local_flush_mask <= 1\'b0;
flush_pop2push_clk1 <= 1\'b0;
pop_flush_tf_push_clk <= 1\'b0;
push_ptr_push_clk <= 0;
pop_ptr_push_clk <= 0;
pop_ptr_async <= 0;
fifo_full_flag_f <= 0;
pop_ptr_pop_clk <= 0;
push_ptr_pop_clk <= 0;
push_ptr_async <= 0;
fifo_empty_flag_f <= 1;
Fifo_Full_Usr <= 4\'b0001;
Fifo_Empty_Usr <= 4\'b0000;
end
assign Fifo_Full = fifo_full_flag_f;
assign Fifo_Empty = fifo_empty_flag_f;
assign Write_Addr = push_ptr_push_clk[MAX_PTR_WIDTH-2:0];
assign Read_Addr = next_pop_ptr_pop_clk[MAX_PTR_WIDTH-2:0];
assign push_ptr_push_clk_plus1 = push_ptr_push_clk + 1;
assign next_push_ptr_push_clk = (Fifo_Push) ? push_ptr_push_clk_plus1 : push_ptr_push_clk;
assign next_push_ptr_push_clk_mask = {
(push_ptr_push_clk_mask & next_push_ptr_push_clk[MAX_PTR_WIDTH-1:MAX_PTR_WIDTH-2]),
next_push_ptr_push_clk[MAX_PTR_WIDTH-3:0]
};
assign pop_ptr_pop_clk_plus1 = pop_ptr_pop_clk + 1;
assign next_pop_ptr_pop_clk = (Fifo_Pop) ? pop_ptr_pop_clk_plus1 : pop_ptr_pop_clk;
assign next_pop_ptr_pop_clk_mask = {
(pop_ptr_pop_clk_mask & next_pop_ptr_pop_clk[MAX_PTR_WIDTH-1:MAX_PTR_WIDTH-2]),
next_pop_ptr_pop_clk[MAX_PTR_WIDTH-3:0]
};
assign pop_ptr_push_clk_l_shift1 = {pop_ptr_push_clk[MAX_PTR_WIDTH-2:0], 1\'b0};
assign pop_ptr_push_clk_l_shift2 = {pop_ptr_push_clk[MAX_PTR_WIDTH-3:0], 2\'b0};
assign pop_ptr_push_clk_r_shift1 = {1\'b0, pop_ptr_push_clk[MAX_PTR_WIDTH-1:1]};
assign pop_ptr_push_clk_r_shift2 = {2\'b0, pop_ptr_push_clk[MAX_PTR_WIDTH-1:2]};
assign push_ptr_pop_clk_l_shift1 = {push_ptr_pop_clk[MAX_PTR_WIDTH-2:0], 1\'b0};
assign push_ptr_pop_clk_l_shift2 = {push_ptr_pop_clk[MAX_PTR_WIDTH-3:0], 2\'b0};
assign push_ptr_pop_clk_r_shift1 = {1\'b0, push_ptr_pop_clk[MAX_PTR_WIDTH-1:1]};
assign push_ptr_pop_clk_r_shift2 = {2\'b0, push_ptr_pop_clk[MAX_PTR_WIDTH-1:2]};
assign push_diff = next_push_ptr_push_clk_mask - pop_ptr_push_clk_mux;
assign push_diff_plus_1 = push_diff + 1;
assign pop_diff = push_ptr_pop_clk_mux - next_pop_ptr_pop_clk_mask;
assign match_room4all = ~|push_diff;
assign\tmatch_room4eight\t= ( depth_sel_push == 3 ) ? ( push_diff >= DEPTH3-8 ) : ( depth_sel_push == 2 ) ? ( push_diff >= DEPTH2-8 ) : ( push_diff >= DEPTH1-8 );
assign match_one_left = (pop_diff == 1);
assign match_one2eight_left = (pop_diff < 8);
assign push_flush_gated = Fifo_Push_Flush & ~push_local_flush_mask;
assign pop_flush_gated = Fifo_Pop_Flush & ~pop_local_flush_mask;
assign push_clk_rst = flush_pop2push_clk1 ^ pop_flush_tf_push_clk;
assign pop_clk_rst = flush_push2pop_clk1 ^ push_flush_tf_pop_clk;
assign pop_flush_done = push2pop_ack1 ^ push2pop_ack2;
assign push_flush_done = pop2push_ack1 ^ pop2push_ack2;
assign\tpush_clk_rst_mux\t= ( Fifo_Sync_Mode ) ? ( Fifo_Push_Flush | Fifo_Pop_Flush ) : ( push_flush_gated | push_clk_rst );
assign\tpop_clk_rst_mux\t\t= ( Fifo_Sync_Mode ) ? ( Fifo_Push_Flush | Fifo_Pop_Flush ) : ( pop_flush_gated | ( pop_local_flush_mask & ~pop_flush_done ) | pop_clk_rst );
reg match_room_at_most63, match_at_most63_left;
always@( push_diff or push_diff_plus_1 or depth_sel_push or match_room4none or match_room4one )
\tbegin
if (depth_sel_push == 1) begin
match_room4none\t\t<= ( push_diff[D1_QTR_A+2:0] == depth1_reg[D1_QTR_A+2:0] );
// syao 2/12/2013
match_room4one\t\t<= ( push_diff_plus_1[D1_QTR_A+2:0] == depth1_reg ) | match_room4none;
match_room4half\t\t<= ( push_diff[D1_QTR_A+1] == 1\'b1 );
match_room4quart\t<= ( push_diff[D1_QTR_A] == 1\'b1 );
match_room_at_most63 <= push_diff[6];
end else if (depth_sel_push == 2) begin
match_room4none\t\t<= ( push_diff[D2_QTR_A+2:0] == depth2_reg[D2_QTR_A+2:0] );
// syao 2/12/2013
match_room4one\t\t<= ( push_diff_plus_1[D2_QTR_A+2:0] == depth2_reg ) | match_room4none;
match_room4half\t\t<= ( push_diff[D2_QTR_A+1] == 1\'b1 );
match_room4quart\t<= ( push_diff[D2_QTR_A] == 1\'b1 );
// syao 2/12/2013
//\t\t\tmatch_room_at_most63 <= push_diff[6];
match_room_at_most63 <= &push_diff[7:6];
end else begin
match_room4none <= (push_diff == depth3_reg);
match_room4one <= (push_diff_plus_1 == depth3_reg) | match_room4none;
match_room4half <= (push_diff[D3_QTR_A+1] == 1\'b1);
match_room4quart <= (push_diff[D3_QTR_A] == 1\'b1);
// syao 2/12/2013
//\t\t\tmatch_room_at_most63\t<= &push_diff[7:6];
match_room_at_most63 <= &push_diff[8:6];
end
end
assign room4_32s = ~push_diff[5];
assign room4_16s = ~push_diff[4];
assign room4_8s = ~push_diff[3];
assign room4_4s = ~push_diff[2];
assign room4_2s = ~push_diff[1];
assign room4_1s = &push_diff[1:0];
always @(depth_sel_pop or pop_diff) begin
if (depth_sel_pop == 1) begin
match_all_left <= (pop_diff[D1_QTR_A+2:0] == depth1_reg[D1_QTR_A+2:0]);
match_half_left <= (pop_diff[D1_QTR_A+1] == 1\'b1);
match_quart_left <= (pop_diff[D1_QTR_A] == 1\'b1);
match_at_most63_left <= ~pop_diff[6];
end else if (depth_sel_pop == 2) begin
match_all_left <= (pop_diff[D2_QTR_A+2:0] == depth2_reg[D2_QTR_A+2:0]);
match_half_left <= (pop_diff[D2_QTR_A+1] == 1\'b1);
match_quart_left <= (pop_diff[D2_QTR_A] == 1\'b1);
// syao 2/12/2013
//\t\t\tmatch_at_most63_left\t<= ~pop_diff[6];\t\t\t
match_at_most63_left <= ~|pop_diff[7:6];
end else begin
match_all_left <= (pop_diff == depth3_reg);
match_half_left <= (pop_diff[D3_QTR_A+1] == 1\'b1);
match_quart_left <= (pop_diff[D3_QTR_A] == 1\'b1);
// syao 2/12/2013
//\t\t\tmatch_at_most63_left\t<= ~|pop_diff[7:6];\t\t\t
match_at_most63_left <= ~|pop_diff[8:6];
end
end
assign at_least_32 = pop_diff[5];
assign at_least_16 = pop_diff[4];
assign at_least_8 = pop_diff[3];
assign at_least_4 = pop_diff[2];
assign at_least_2 = pop_diff[1];
assign one_left = pop_diff[0];
always @(posedge Pop_Clk or negedge Rst_n) begin
if (~Rst_n) begin
push2pop_ack1 <= 1\'b0;
push2pop_ack2 <= 1\'b0;
flush_pop_clk_tf <= 1\'b0;
pop_local_flush_mask <= 1\'b0;
flush_push2pop_clk1 <= 1\'b0;
push_flush_tf_pop_clk <= 1\'b0;
end else begin
push2pop_ack1 <= pop_flush_tf_push_clk;
push2pop_ack2 <= push2pop_ack1;
flush_push2pop_clk1 <= flush_push_clk_tf;
if (pop_flush_gated) begin
flush_pop_clk_tf <= ~flush_pop_clk_tf;
end
if (pop_flush_gated & ~Fifo_Sync_Mode) begin
pop_local_flush_mask <= 1\'b1;
end else if (pop_flush_done) begin
pop_local_flush_mask <= 1\'b0;
end
if (pop_clk_rst) begin
push_flush_tf_pop_clk <= ~push_flush_tf_pop_clk;
end
end
end
always @(posedge Push_Clk or negedge Rst_n) begin
if (~Rst_n) begin
pop2push_ack1 <= 1\'b0;
pop2push_ack2 <= 1\'b0;
flush_push_clk_tf <= 1\'b0;
push_local_flush_mask <= 1\'b0;
flush_pop2push_clk1 <= 1\'b0;
pop_flush_tf_push_clk <= 1\'b0;
end else begin
pop2push_ack1\t\t\t\t<= push_flush_tf_pop_clk;
pop2push_ack2\t\t\t\t<= pop2push_ack1;
flush_pop2push_clk1\t<= flush_pop_clk_tf;
if (push_flush_gated) begin
flush_push_clk_tf <= ~flush_push_clk_tf;
end
if (push_flush_gated & ~Fifo_Sync_Mode) begin
push_local_flush_mask <= 1\'b1;
end else if (push_flush_done) begin
push_local_flush_mask <= 1\'b0;
end
if (push_clk_rst) begin
pop_flush_tf_push_clk <= ~pop_flush_tf_push_clk;
end
end
end
always@( Fifo_Push_Width or Fifo_Pop_Width or pop_ptr_push_clk_l_shift1 or pop_ptr_push_clk_l_shift2 or pop_ptr_push_clk_r_shift1 or
\t\t\t\t\t\tpop_ptr_push_clk_r_shift2 or push_ptr_pop_clk_l_shift1 or push_ptr_pop_clk_l_shift2 or push_ptr_pop_clk_r_shift1 or push_ptr_pop_clk_r_shift2 or
\t\t\t\t\t\tpop_ptr_push_clk or push_ptr_pop_clk )
\tbegin
case ({
Fifo_Push_Width, Fifo_Pop_Width
})
4\'b0001:\t//\tbyte push halfword pop
begin
push_ptr_push_clk_mask <= 2\'b11;
pop_ptr_pop_clk_mask <= 2\'b01;
pop_ptr_push_clk_mux <= pop_ptr_push_clk_l_shift1;
push_ptr_pop_clk_mux <= push_ptr_pop_clk_r_shift1;
end
4\'b0010:\t//\tbyte push word pop
begin
push_ptr_push_clk_mask <= 2\'b11;
pop_ptr_pop_clk_mask <= 2\'b00;
pop_ptr_push_clk_mux <= pop_ptr_push_clk_l_shift2;
push_ptr_pop_clk_mux <= push_ptr_pop_clk_r_shift2;
end
4\'b0100:\t//\thalfword push byte pop
begin
push_ptr_push_clk_mask <= 2\'b01;
pop_ptr_pop_clk_mask <= 2\'b11;
pop_ptr_push_clk_mux <= pop_ptr_push_clk_r_shift1;
push_ptr_pop_clk_mux <= push_ptr_pop_clk_l_shift1;
end
4\'b0110:\t//\thalfword push word pop
begin
push_ptr_push_clk_mask <= 2\'b11;
pop_ptr_pop_clk_mask <= 2\'b01;
pop_ptr_push_clk_mux <= pop_ptr_push_clk_l_shift1;
push_ptr_pop_clk_mux <= push_ptr_pop_clk_r_shift1;
end
4\'b1000:\t//\tword push byte pop
begin
push_ptr_push_clk_mask <= 2\'b00;
pop_ptr_pop_clk_mask <= 2\'b11;
pop_ptr_push_clk_mux <= pop_ptr_push_clk_r_shift2;
push_ptr_pop_clk_mux <= push_ptr_pop_clk_l_shift2;
end
4\'b1001:\t//\tword push halfword pop
begin
push_ptr_push_clk_mask <= 2\'b01;
pop_ptr_pop_clk_mask <= 2\'b11;
pop_ptr_push_clk_mux <= pop_ptr_push_clk_r_shift1;
push_ptr_pop_clk_mux <= push_ptr_pop_clk_l_shift1;
end
default:\t//\tno conversion
begin
push_ptr_push_clk_mask <= 2\'b11;
pop_ptr_pop_clk_mask <= 2\'b11;
pop_ptr_push_clk_mux <= pop_ptr_push_clk;
push_ptr_pop_clk_mux <= push_ptr_pop_clk;
end
endcase
end
always @(Fifo_Ram_Mode or Fifo_Push_Width) begin
if (Fifo_Ram_Mode == Fifo_Push_Width[0]) begin
depth_sel_push <= 2;
end else if (Fifo_Ram_Mode == Fifo_Push_Width[1]) begin
depth_sel_push <= 1;
end else begin
depth_sel_push <= 3;
end
end
always @(Fifo_Ram_Mode or Fifo_Pop_Width) begin
if (Fifo_Ram_Mode == Fifo_Pop_Width[0]) begin
depth_sel_pop <= 2;
end else if (Fifo_Ram_Mode == Fifo_Pop_Width[1]) begin
depth_sel_pop <= 1;
end else begin
depth_sel_pop <= 3;
end
end
always @(posedge Push_Clk or negedge Rst_n) begin
if (~Rst_n) begin
push_ptr_push_clk <= 0;
pop_ptr_push_clk <= 0;
pop_ptr_async <= 0;
fifo_full_flag_f <= 0;
end else begin
if (push_clk_rst_mux) begin
push_ptr_push_clk <= 0;
pop_ptr_push_clk <= 0;
pop_ptr_async <= 0;
fifo_full_flag_f <= 0;
end else begin
push_ptr_push_clk <= next_push_ptr_push_clk;
pop_ptr_push_clk <= (Fifo_Sync_Mode) ? next_pop_ptr_pop_clk : pop_ptr_async;
pop_ptr_async <= pop_ptr_pop_clk;
fifo_full_flag_f <= match_room4one | match_room4none;
end
end
end
always @(posedge Pop_Clk or negedge Rst_n) begin
if (~Rst_n) begin
pop_ptr_pop_clk <= 0;
push_ptr_pop_clk <= 0;
push_ptr_async <= 0;
fifo_empty_flag_f <= 1;
end else begin
if (pop_clk_rst_mux) begin
pop_ptr_pop_clk <= 0;
push_ptr_pop_clk <= 0;
push_ptr_async <= 0;
fifo_empty_flag_f <= 1;
end else begin
pop_ptr_pop_clk <= next_pop_ptr_pop_clk;
push_ptr_pop_clk <= (Fifo_Sync_Mode) ? next_push_ptr_push_clk : push_ptr_async;
push_ptr_async <= push_ptr_push_clk;
fifo_empty_flag_f <= (pop_diff == 1) | (pop_diff == 0);
end
end
end
always @(posedge Push_Clk or negedge Rst_n) begin
if (~Rst_n) begin
//based on rtl, this should be full after reset\t\t
//\t\t\tFifo_Full_Usr\t<= 4\'b1000;
Fifo_Full_Usr <= 4\'b0001;
end else begin
if (match_room4none) begin
Fifo_Full_Usr <= 4\'b0000;
end else if (match_room4all) begin
Fifo_Full_Usr <= 4\'b0001;
end else if (~match_room4half) begin
Fifo_Full_Usr <= 4\'b0010;
end else if (~match_room4quart) begin
Fifo_Full_Usr <= 4\'b0011;
end else begin
if (match_room_at_most63) begin
if (room4_32s) Fifo_Full_Usr <= 4\'b1010;
else if (room4_16s) Fifo_Full_Usr <= 4\'b1011;
else if (room4_8s) Fifo_Full_Usr <= 4\'b1100;
else if (room4_4s) Fifo_Full_Usr <= 4\'b1101;
else if (room4_2s) Fifo_Full_Usr <= 4\'b1110;
else if (room4_1s) Fifo_Full_Usr <= 4\'b1111;
else Fifo_Full_Usr <= 4\'b1110;
end else Fifo_Full_Usr <= 4\'b0100;
end
end
end
always @(posedge Pop_Clk or negedge Rst_n) begin
if (~Rst_n) begin
Fifo_Empty_Usr <= 4\'b0000;
end else begin
if (Fifo_Pop_Flush | (pop_local_flush_mask & ~pop_flush_done) | pop_clk_rst) begin
Fifo_Empty_Usr <= 4\'b0000;
end else if (match_all_left) begin
Fifo_Empty_Usr <= 4\'b1111;
end else if (match_half_left) begin
Fifo_Empty_Usr <= 4\'b1110;
end else if (match_quart_left) begin
Fifo_Empty_Usr <= 4\'b1101;
end else begin
if (match_at_most63_left) begin
if (at_least_32) Fifo_Empty_Usr <= 4\'b0110;
else if (at_least_16) Fifo_Empty_Usr <= 4\'b0101;
else if (at_least_8) Fifo_Empty_Usr <= 4\'b0100;
else if (at_least_4) Fifo_Empty_Usr <= 4\'b0011;
else if (at_least_2) Fifo_Empty_Usr <= 4\'b0010;
else if (one_left) Fifo_Empty_Usr <= 4\'b0001;
else Fifo_Empty_Usr <= 4\'b0000;
end else Fifo_Empty_Usr <= 4\'b1000;
end
end
end
endmodule
`timescale 10 ps / 1 ps
//`define ADDRWID 8
`define DATAWID 18
`define WEWID 2
//`define DEPTH 256
module ram (
AA,
AB,
CLKA,
CLKB,
WENA,
WENB,
CENA,
CENB,
WENBA,
WENBB,
DA,
QA,
DB,
QB
);
parameter ADDRWID = 8;
parameter DEPTH = (1 << ADDRWID);
parameter [9215:0] INIT = 9216\'bx;
parameter INIT_FILE = "init.mem";
parameter init_ad = 0;
parameter data_width_int = 16;
parameter data_depth_int = 1024;
output [`DATAWID-1:0] QA;
input CLKA;
input CENA;
input WENA;
input [`WEWID-1:0] WENBA;
input [ADDRWID-1:0] AA;
input [`DATAWID-1:0] DA;
output [`DATAWID-1:0] QB;
input CLKB;
input CENB;
input WENB;
input [`WEWID-1:0] WENBB;
input [ADDRWID-1:0] AB;
input [`DATAWID-1:0] DB;
integer i, j, k, l, m, n, o;
wire CEN1;
wire OEN1;
wire WEN1;
wire [ `WEWID-1:0] WENB1;
wire [ ADDRWID-1:0] A1;
reg [ ADDRWID-1:0] AddrOut1;
wire [`DATAWID-1:0] I1;
wire CEN2;
wire OEN2;
wire WEN2;
wire [ `WEWID-1:0] WENB2;
wire [ ADDRWID-1:0] A2;
reg [ ADDRWID-1:0] AddrOut2;
wire [`DATAWID-1:0] I2;
reg [`DATAWID-1:0] O1, QAreg;
reg [`DATAWID-1:0] O2, QBreg;
reg WEN1_f;
reg WEN2_f;
reg [ ADDRWID-1:0] A2_f;
reg [ ADDRWID-1:0] A1_f;
wire CEN1_SEL;
wire WEN1_SEL;
wire [ ADDRWID-1:0] A1_SEL;
wire [`DATAWID-1:0] I1_SEL;
wire [ `WEWID-1:0] WENB1_SEL;
wire CEN2_SEL;
wire WEN2_SEL;
wire [ ADDRWID-1:0] A2_SEL;
wire [`DATAWID-1:0] I2_SEL;
wire [ `WEWID-1:0] WENB2_SEL;
wire overlap;
wire CLKA_d, CLKB_d, CEN1_d, CEN2_d;
assign\tA1_SEL = AA;
assign\tI1_SEL = DA;
assign\tCEN1_SEL = CENA;
assign\tWEN1_SEL = WENA;
assign\tWENB1_SEL = WENBA;
assign\tA2_SEL = AB;
assign\tI2_SEL = DB;
assign\tCEN2_SEL = CENB;
assign\tWEN2_SEL = WENB;
assign\tWENB2_SEL = WENBB;
assign\tCEN1\t= CEN1_SEL;
assign\tOEN1\t= 1\'b0;
assign\tWEN1\t= WEN1_SEL;
assign\tWENB1\t= WENB1_SEL;
assign\tA1\t\t= A1_SEL;
assign\tI1\t\t= I1_SEL;
assign\tCEN2\t= CEN2_SEL;
assign\tOEN2\t= 1\'b0;
assign\tWEN2\t= WEN2_SEL;
assign\tWENB2\t= WENB2_SEL;
assign\tA2\t\t= A2_SEL;
assign\tI2\t\t= I2_SEL;
//assign\tQA\t= O1;
//assign\tQB\t= O2;
reg [`DATAWID-1:0] ram[DEPTH-1:0];
reg [data_width_int-1 : 0] ram_dum[data_depth_int-1:0];
reg [`DATAWID-1:0] wrData1;
reg [`DATAWID-1:0] wrData2;
wire [`DATAWID-1:0] tmpData1;
wire [`DATAWID-1:0] tmpData2;
reg CENreg1, CENreg2;
assign #1 CLKA_d = CLKA;
assign #1 CLKB_d = CLKB;
// updated by sya 20130523
assign #2 CEN1_d = CEN1;
assign #2 CEN2_d = CEN2;
assign QA = QAreg | O1;
assign QB = QBreg | O2;
assign tmpData1 = ram[A1];
assign tmpData2 = ram[A2];
assign overlap = (A1_f == A2_f) & WEN1_f & WEN2_f;
initial begin
`ifndef YOSYS
$readmemh(INIT_FILE, ram_dum);
`endif
#10 n = 0;
o = 0;
for (i = 0; i < DEPTH; i = i + 1) begin
if (data_width_int > 16)
ram[i] <= {
1\'b0,
ram_dum[i][((16*init_ad)+16)-1:((16*init_ad)+8)],
1\'b0,
ram_dum[i][((16*init_ad)+8)-1:(16*init_ad)]
};
else if (data_width_int <= 8 && data_depth_int <= 1024)
ram[i] <= {
1\'b0, ram_dum[i+n+1+(1024*init_ad)][7:0], 1\'b0, ram_dum[i+n+(1024*init_ad)][7:0]
};
else if (data_width_int <= 8 && data_depth_int > 1024)
ram[i] <= {1\'b0, ram_dum[i+o+init_ad+1][7:0], 1\'b0, ram_dum[i+o+init_ad][7:0]};
else if (data_width_int > 8 && data_width_int <= 16 && data_depth_int > 512)
ram[i] <= {1\'b0, ram_dum[i+n+init_ad][15:8], 1\'b0, ram_dum[i+n+init_ad][7:0]};
else ram[i] <= {1\'b0, ram_dum[i+(512*init_ad)][15:8], 1\'b0, ram_dum[i+(512*init_ad)][7:0]};
n = n + 1;
o = o + 3;
end
end
always @(WENB1 or I1 or tmpData1) begin
for (j = 0; j < 9; j = j + 1) begin
wrData1[j] <= (WENB1[0]) ? tmpData1[j] : I1[j];
end
for (l = 9; l < 19; l = l + 1) begin
wrData1[l] <= (WENB1[1]) ? tmpData1[l] : I1[l];
end
end
always @(posedge CLKA) begin
if (~WEN1 & ~CEN1) begin
ram[A1] <= wrData1[`DATAWID-1:0];
end
end
//pre-charging to 1 every clock cycle
always @(posedge CLKA_d)
if (~CEN1_d) begin
O1 = 18\'h3ffff;
#100;
O1 = 18\'h00000;
end
always @(posedge CLKA)
if (~CEN1) begin
AddrOut1 <= A1;
end
always @(posedge CLKA_d)
if (~CEN1_d) begin
QAreg <= ram[AddrOut1];
end
always @(posedge CLKA) begin
WEN1_f <= ~WEN1 & ~CEN1;
A1_f <= A1;
end
always @(WENB2 or I2 or tmpData2) begin
for (k = 0; k < 9; k = k + 1) begin
wrData2[k] <= (WENB2[0]) ? tmpData2[k] : I2[k];
end
for (m = 9; m < 19; m = m + 1) begin
wrData2[m] <= (WENB2[1]) ? tmpData2[m] : I2[m];
end
end
always @(posedge CLKB) begin
if (~WEN2 & ~CEN2) begin
ram[A2] <= wrData2[`DATAWID-1:0];
end
end
//pre-charging to 1 every clock cycle
always @(posedge CLKB_d)
if (~CEN2_d) begin
O2 = 18\'h3ffff;
#100;
O2 = 18\'h00000;
end
always @(posedge CLKB)
if (~CEN2) begin
AddrOut2 <= A2;
end
always @(posedge CLKB_d)
if (~CEN2_d) begin
QBreg <= ram[AddrOut2];
end
always @(posedge CLKB) begin
WEN2_f <= ~WEN2 & ~CEN2;
A2_f <= A2;
end
always @(A1_f or A2_f or overlap) begin
if (overlap) begin
ram[A1_f] <= 18\'bxxxxxxxxxxxxxxxxxx;
end
end
endmodule
`timescale 1 ns / 10 ps
//`define ADDRWID 10
`define DATAWID 18
`define WEWID 2
module x2_model (
Concat_En,
ram0_WIDTH_SELA,
ram0_WIDTH_SELB,
ram0_PLRD,
ram0_CEA,
ram0_CEB,
ram0_I,
ram0_O,
ram0_AA,
ram0_AB,
ram0_CSBA,
ram0_CSBB,
ram0_WENBA,
ram1_WIDTH_SELA,
ram1_WIDTH_SELB,
ram1_PLRD,
ram1_CEA,
ram1_CEB,
ram1_I,
ram1_O,
ram1_AA,
ram1_AB,
ram1_CSBA,
ram1_CSBB,
ram1_WENBA
);
parameter ADDRWID = 10;
parameter [18431:0] INIT = 18432\'bx;
parameter INIT_FILE = "init.mem";
parameter data_width_int = 16;
parameter data_depth_int = 1024;
parameter init_ad1 = 0;
parameter init_ad2 = (data_depth_int > 1024) ? 2 : 1;
input Concat_En;
input [1:0] ram0_WIDTH_SELA;
input [1:0] ram0_WIDTH_SELB;
input ram0_PLRD;
input ram0_CEA;
input ram0_CEB;
input [`DATAWID-1:0] ram0_I;
output [`DATAWID-1:0] ram0_O;
input [ADDRWID-1:0] ram0_AA;
input [ADDRWID-1:0] ram0_AB;
input ram0_CSBA;
input ram0_CSBB;
input [`WEWID-1:0] ram0_WENBA;
input [1:0] ram1_WIDTH_SELA;
input [1:0] ram1_WIDTH_SELB;
input ram1_PLRD;
input ram1_CEA;
input ram1_CEB;
input [`DATAWID-1:0] ram1_I;
output [`DATAWID-1:0] ram1_O;
input [ADDRWID-1:0] ram1_AA;
input [ADDRWID-1:0] ram1_AB;
input ram1_CSBA;
input ram1_CSBB;
input [`WEWID-1:0] ram1_WENBA;
reg ram0_PLRDA_SEL;
reg ram0_PLRDB_SEL;
reg ram1_PLRDA_SEL;
reg ram1_PLRDB_SEL;
reg ram_AA_ram_SEL;
reg ram_AB_ram_SEL;
reg [ `WEWID-1:0] ram0_WENBA_SEL;
reg [ `WEWID-1:0] ram0_WENBB_SEL;
reg [ `WEWID-1:0] ram1_WENBA_SEL;
reg [ `WEWID-1:0] ram1_WENBB_SEL;
reg ram0_A_x9_SEL;
reg ram0_B_x9_SEL;
reg ram1_A_x9_SEL;
reg ram1_B_x9_SEL;
reg [ ADDRWID-3:0] ram0_AA_SEL;
reg [ ADDRWID-3:0] ram0_AB_SEL;
reg [ ADDRWID-3:0] ram1_AA_SEL;
reg [ ADDRWID-3:0] ram1_AB_SEL;
reg ram0_AA_byte_SEL;
reg ram0_AB_byte_SEL;
reg ram1_AA_byte_SEL;
reg ram1_AB_byte_SEL;
reg ram0_AA_byte_SEL_Q;
reg ram0_AB_byte_SEL_Q;
reg ram1_AA_byte_SEL_Q;
reg ram1_AB_byte_SEL_Q;
reg ram0_A_mux_ctl_Q;
reg ram0_B_mux_ctl_Q;
reg ram1_A_mux_ctl_Q;
reg ram1_B_mux_ctl_Q;
reg ram0_O_mux_ctrl_Q;
reg ram1_O_mux_ctrl_Q;
reg ram_AA_ram_SEL_Q;
reg ram_AB_ram_SEL_Q;
wire [`DATAWID-1:0] QA_1_SEL3;
wire [`DATAWID-1:0] QB_0_SEL2;
wire [`DATAWID-1:0] QB_1_SEL2;
reg [`DATAWID-1:0] QA_0_Q;
reg [`DATAWID-1:0] QB_0_Q;
reg [`DATAWID-1:0] QA_1_Q;
reg [`DATAWID-1:0] QB_1_Q;
wire [`DATAWID-1:0] QA_0;
wire [`DATAWID-1:0] QB_0;
wire [`DATAWID-1:0] QA_1;
wire [`DATAWID-1:0] QB_1;
wire ram0_CSBA_SEL;
wire ram0_CSBB_SEL;
wire ram1_CSBA_SEL;
wire ram1_CSBB_SEL;
wire [`DATAWID-1:0] ram0_I_SEL1;
wire [`DATAWID-1:0] ram1_I_SEL1;
wire dual_port;
wire ram0_WEBA_SEL;
wire ram0_WEBB_SEL;
wire ram1_WEBA_SEL;
wire ram1_WEBB_SEL;
wire [`DATAWID-1:0] ram1_I_SEL2;
wire [`DATAWID-1:0] QA_1_SEL2;
wire [`DATAWID-1:0] QA_0_SEL1;
wire [`DATAWID-1:0] QB_0_SEL1;
wire [`DATAWID-1:0] QA_1_SEL1;
wire [`DATAWID-1:0] QB_1_SEL1;
wire [`DATAWID-1:0] QB_0_SEL3;
wire [`DATAWID-1:0] QA_0_SEL2;
initial begin
QA_0_Q <= 0;
QB_0_Q <= 0;
QA_1_Q <= 0;
QB_1_Q <= 0;
ram0_AA_byte_SEL_Q <= 0;
ram0_A_mux_ctl_Q <= 0;
ram0_AB_byte_SEL_Q <= 0;
ram0_B_mux_ctl_Q <= 0;
ram1_AA_byte_SEL_Q <= 0;
ram1_A_mux_ctl_Q <= 0;
ram1_AB_byte_SEL_Q <= 0;
ram1_B_mux_ctl_Q <= 0;
ram_AA_ram_SEL_Q <= 0;
ram1_O_mux_ctrl_Q <= 0;
ram_AB_ram_SEL_Q <= 0;
ram0_O_mux_ctrl_Q <= 0;
end
assign dual_port = Concat_En & ~(ram0_WIDTH_SELA[1] | ram0_WIDTH_SELB[1]);
assign ram0_CSBA_SEL = ram0_CSBA;
assign ram0_CSBB_SEL = ram0_CSBB;
assign ram1_CSBA_SEL = Concat_En ? ram0_CSBA : ram1_CSBA;
assign ram1_CSBB_SEL = Concat_En ? ram0_CSBB : ram1_CSBB;
assign ram0_O = QB_0_SEL3;
assign ram1_O = dual_port ? QA_1_SEL3 : QB_1_SEL2;
assign ram0_I_SEL1[8:0] = ram0_I[8:0];
assign ram1_I_SEL1[8:0] = ram1_I[8:0];
assign ram0_I_SEL1[17:9] = ram0_AA_byte_SEL ? ram0_I[8:0] : ram0_I[17:9];
assign ram1_I_SEL1[17:9]\t= ( ( ~Concat_En & ram1_AA_byte_SEL ) | ( dual_port & ram0_AB_byte_SEL ) ) ? ram1_I[8:0] : ram1_I[17:9];
assign ram1_I_SEL2 = (Concat_En & ~ram0_WIDTH_SELA[1]) ? ram0_I_SEL1 : ram1_I_SEL1;
assign ram0_WEBA_SEL = &ram0_WENBA_SEL;
assign ram0_WEBB_SEL = &ram0_WENBB_SEL;
assign ram1_WEBA_SEL = &ram1_WENBA_SEL;
assign ram1_WEBB_SEL = &ram1_WENBB_SEL;
assign QA_0_SEL1 = (ram0_PLRDA_SEL) ? QA_0_Q : QA_0;
assign QB_0_SEL1 = (ram0_PLRDB_SEL) ? QB_0_Q : QB_0;
assign QA_1_SEL1 = (ram1_PLRDA_SEL) ? QA_1_Q : QA_1;
assign QB_1_SEL1 = (ram1_PLRDB_SEL) ? QB_1_Q : QB_1;
assign QA_1_SEL3 = ram1_O_mux_ctrl_Q ? QA_1_SEL2 : QA_0_SEL2;
assign QA_0_SEL2[8:0] = ram0_A_mux_ctl_Q ? QA_0_SEL1[17:9] : QA_0_SEL1[8:0];
assign QB_0_SEL2[8:0] = ram0_B_mux_ctl_Q ? QB_0_SEL1[17:9] : QB_0_SEL1[8:0];
assign QA_1_SEL2[8:0] = ram1_A_mux_ctl_Q ? QA_1_SEL1[17:9] : QA_1_SEL1[8:0];
assign QB_1_SEL2[8:0] = ram1_B_mux_ctl_Q ? QB_1_SEL1[17:9] : QB_1_SEL1[8:0];
assign QA_0_SEL2[17:9] = QA_0_SEL1[17:9];
assign QB_0_SEL2[17:9] = QB_0_SEL1[17:9];
assign QA_1_SEL2[17:9] = QA_1_SEL1[17:9];
assign QB_1_SEL2[17:9] = QB_1_SEL1[17:9];
assign QB_0_SEL3 = ram0_O_mux_ctrl_Q ? QB_1_SEL2 : QB_0_SEL2;
always @(posedge ram0_CEA) begin
QA_0_Q <= QA_0;
end
always @(posedge ram0_CEB) begin
QB_0_Q <= QB_0;
end
always @(posedge ram1_CEA) begin
QA_1_Q <= QA_1;
end
always @(posedge ram1_CEB) begin
QB_1_Q <= QB_1;
end
always @(posedge ram0_CEA) begin
if (ram0_CSBA_SEL == 0) ram0_AA_byte_SEL_Q <= ram0_AA_byte_SEL;
if (ram0_PLRDA_SEL || (ram0_CSBA_SEL == 0))
ram0_A_mux_ctl_Q <= ram0_A_x9_SEL & (ram0_PLRDA_SEL ? ram0_AA_byte_SEL_Q : ram0_AA_byte_SEL);
end
always @(posedge ram0_CEB) begin
if (ram0_CSBB_SEL == 0) ram0_AB_byte_SEL_Q <= ram0_AB_byte_SEL;
if (ram0_PLRDB_SEL || (ram0_CSBB_SEL == 0))
ram0_B_mux_ctl_Q <= ram0_B_x9_SEL & (ram0_PLRDB_SEL ? ram0_AB_byte_SEL_Q : ram0_AB_byte_SEL);
end
always @(posedge ram1_CEA) begin
if (ram1_CSBA_SEL == 0) ram1_AA_byte_SEL_Q <= ram1_AA_byte_SEL;
if (ram1_PLRDA_SEL || (ram1_CSBA_SEL == 0))
ram1_A_mux_ctl_Q <= ram1_A_x9_SEL & (ram1_PLRDA_SEL ? ram1_AA_byte_SEL_Q : ram1_AA_byte_SEL);
end
always @(posedge ram1_CEB) begin
if (ram1_CSBB_SEL == 0) ram1_AB_byte_SEL_Q <= ram1_AB_byte_SEL;
if (ram1_PLRDB_SEL || (ram1_CSBB_SEL == 0))
ram1_B_mux_ctl_Q <= ram1_B_x9_SEL & (ram1_PLRDB_SEL ? ram1_AB_byte_SEL_Q : ram1_AB_byte_SEL);
end
always @(posedge ram0_CEA) begin
ram_AA_ram_SEL_Q <= ram_AA_ram_SEL;
ram1_O_mux_ctrl_Q <= (ram0_PLRDA_SEL ? ram_AA_ram_SEL_Q : ram_AA_ram_SEL);
end
always @(posedge ram0_CEB) begin
ram_AB_ram_SEL_Q <= ram_AB_ram_SEL;
ram0_O_mux_ctrl_Q <= (ram0_PLRDB_SEL ? ram_AB_ram_SEL_Q : ram_AB_ram_SEL);
end
always@( Concat_En or ram0_WIDTH_SELA or ram0_WIDTH_SELB or ram0_AA or ram0_AB or ram0_WENBA or
\t ram1_AA or ram1_AB or ram1_WENBA or ram0_PLRD or ram1_PLRD or ram1_WIDTH_SELA or ram1_WIDTH_SELB )
\tbegin
ram0_A_x9_SEL <= (~|ram0_WIDTH_SELA);
ram1_A_x9_SEL <= (~|ram0_WIDTH_SELA);
ram0_B_x9_SEL <= (~|ram0_WIDTH_SELB);
ram0_AA_byte_SEL <= ram0_AA[0] & (~|ram0_WIDTH_SELA);
ram0_AB_byte_SEL <= ram0_AB[0] & (~|ram0_WIDTH_SELB);
if (~Concat_En) begin
ram_AA_ram_SEL\t<= 1\'b0;
ram_AB_ram_SEL\t<= 1\'b0;
ram1_B_x9_SEL\t\t<= ( ~|ram1_WIDTH_SELB );
ram0_PLRDA_SEL\t<= ram0_PLRD;
ram0_PLRDB_SEL\t<= ram0_PLRD;
ram1_PLRDA_SEL\t<= ram1_PLRD;
ram1_PLRDB_SEL\t<= ram1_PLRD;
ram0_WENBB_SEL\t<= {`WEWID{1\'b1}};
ram1_WENBB_SEL\t<= {`WEWID{1\'b1}};
ram0_AA_SEL\t\t\t\t<= ram0_AA >> ( ~|ram0_WIDTH_SELA );
ram0_WENBA_SEL[0]\t<= ( ram0_AA[0] & ( ~|ram0_WIDTH_SELA ) ) | ram0_WENBA[0];
ram0_WENBA_SEL[1]\t<= ( ~ram0_AA[0] & ( ~|ram0_WIDTH_SELA ) ) | ram0_WENBA[( |ram0_WIDTH_SELA )];
ram0_AB_SEL\t\t\t\t<= ram0_AB >> ( ~|ram0_WIDTH_SELB );
ram1_AA_SEL\t\t\t\t<= ram1_AA >> ( ~|ram1_WIDTH_SELA );
ram1_AA_byte_SEL\t<= ram1_AA[0] & ( ~|ram1_WIDTH_SELA );
ram1_WENBA_SEL[0]\t<= ( ram1_AA[0] & ( ~|ram1_WIDTH_SELA ) ) | ram1_WENBA[0];
ram1_WENBA_SEL[1]\t<= ( ~ram1_AA[0] & ( ~|ram1_WIDTH_SELA ) ) | ram1_WENBA[( |ram1_WIDTH_SELA )];
ram1_AB_SEL\t\t\t\t<= ram1_AB >> ( ~|ram1_WIDTH_SELB );
ram1_AB_byte_SEL\t<= ram1_AB[0] & ( ~|ram1_WIDTH_SELB );
end else begin
ram_AA_ram_SEL <= ~ram0_WIDTH_SELA[1] & ram0_AA[~ram0_WIDTH_SELA[0]];
ram_AB_ram_SEL <= ~ram0_WIDTH_SELB[1] & ram0_AB[~ram0_WIDTH_SELB[0]];
ram1_B_x9_SEL <= (~|ram0_WIDTH_SELB);
ram0_PLRDA_SEL <= ram1_PLRD;
ram1_PLRDA_SEL <= ram1_PLRD;
ram0_PLRDB_SEL <= ram0_PLRD;
ram1_PLRDB_SEL <= ram0_PLRD;
ram0_AA_SEL <= ram0_AA >> {
~ram0_WIDTH_SELA[1] & ~(ram0_WIDTH_SELA[1] ^ ram0_WIDTH_SELA[0]),
~ram0_WIDTH_SELA[1] & ram0_WIDTH_SELA[0]
};
ram1_AA_SEL <= ram0_AA >> {
~ram0_WIDTH_SELA[1] & ~(ram0_WIDTH_SELA[1] ^ ram0_WIDTH_SELA[0]),
~ram0_WIDTH_SELA[1] & ram0_WIDTH_SELA[0]
};
ram1_AA_byte_SEL <= ram0_AA[0] & (~|ram0_WIDTH_SELA);
ram0_WENBA_SEL[0]\t<= ram0_WENBA[0] | ( ~ram0_WIDTH_SELA[1] & ( ram0_AA[0] | ( ~ram0_WIDTH_SELA[0] & ram0_AA[1] ) ) );
ram0_WENBA_SEL[1]\t<= ( ( ~|ram0_WIDTH_SELA & ram0_WENBA[0] ) | ( |ram0_WIDTH_SELA & ram0_WENBA[1] ) ) | ( ~ram0_WIDTH_SELA[1] & ( ( ram0_WIDTH_SELA[0] & ram0_AA[0] ) | ( ~ram0_WIDTH_SELA[0] & ~ram0_AA[0] ) | ( ~ram0_WIDTH_SELA[0] & ram0_AA[1] ) ) );
ram1_WENBA_SEL[0]\t<= ( ( ~ram0_WIDTH_SELA[1] & ram0_WENBA[0] ) | ( ram0_WIDTH_SELA[1] & ram1_WENBA[0] ) ) | ( ~ram0_WIDTH_SELA[1] & ( ( ram0_WIDTH_SELA[0] & ~ram0_AA[0] ) | ( ~ram0_WIDTH_SELA[0] & ram0_AA[0] ) | ( ~ram0_WIDTH_SELA[0] & ~ram0_AA[1] ) ) );
ram1_WENBA_SEL[1]\t<= ( ( ( ram0_WIDTH_SELA == 2\'b00 ) & ram0_WENBA[0] ) | ( ( ram0_WIDTH_SELA[1] == 1\'b1 ) & ram1_WENBA[1] ) | ( ( ram0_WIDTH_SELA == 2\'b01 ) & ram0_WENBA[1] ) ) | ( ~ram0_WIDTH_SELA[1] & ( ~ram0_AA[0] | ( ~ram0_WIDTH_SELA[0] & ~ram0_AA[1] ) ) );
ram0_AB_SEL <= ram0_AB >> {
~ram0_WIDTH_SELB[1] & ~(ram0_WIDTH_SELB[1] ^ ram0_WIDTH_SELB[0]),
~ram0_WIDTH_SELB[1] & ram0_WIDTH_SELB[0]
};
ram1_AB_SEL <= ram0_AB >> {
~ram0_WIDTH_SELB[1] & ~(ram0_WIDTH_SELB[1] ^ ram0_WIDTH_SELB[0]),
~ram0_WIDTH_SELB[1] & ram0_WIDTH_SELB[0]
};
ram1_AB_byte_SEL <= ram0_AB[0] & (~|ram0_WIDTH_SELB);
ram0_WENBB_SEL[0]\t<= ram0_WIDTH_SELB[1] | ( ram0_WIDTH_SELA[1] | ram1_WENBA[0] | ( ram0_AB[0] | ( ~ram0_WIDTH_SELB[0] & ram0_AB[1] ) ) );
ram0_WENBB_SEL[1]\t<= ram0_WIDTH_SELB[1] | ( ram0_WIDTH_SELA[1] | ( ( ~|ram0_WIDTH_SELB & ram1_WENBA[0] ) | ( |ram0_WIDTH_SELB & ram1_WENBA[1] ) ) | ( ( ram0_WIDTH_SELB[0] & ram0_AB[0] ) | ( ~ram0_WIDTH_SELB[0] & ~ram0_AB[0] ) | ( ~ram0_WIDTH_SELB[0] & ram0_AB[1] ) ) );
ram1_WENBB_SEL[0]\t<= ram0_WIDTH_SELB[1] | ( ram0_WIDTH_SELA[1] | ram1_WENBA[0] | ( ( ram0_WIDTH_SELB[0] & ~ram0_AB[0] ) | ( ~ram0_WIDTH_SELB[0] & ram0_AB[0] ) | ( ~ram0_WIDTH_SELB[0] & ~ram0_AB[1] ) ) );
ram1_WENBB_SEL[1]\t<= ram0_WIDTH_SELB[1] | ( ram0_WIDTH_SELA[1] | ( ( ~|ram0_WIDTH_SELB & ram1_WENBA[0] ) | ( |ram0_WIDTH_SELB & ram1_WENBA[1] ) ) | ( ~ram0_AB[0] | ( ~ram0_WIDTH_SELB[0] & ~ram0_AB[1] ) ) );
end
end
ram #(
.ADDRWID(ADDRWID - 2),
.INIT(INIT[0*9216+:9216]),
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int),
.init_ad(init_ad1)
) ram0_inst (
.AA(ram0_AA_SEL),
.AB(ram0_AB_SEL),
.CLKA(ram0_CEA),
.CLKB(ram0_CEB),
.WENA(ram0_WEBA_SEL),
.WENB(ram0_WEBB_SEL),
.CENA(ram0_CSBA_SEL),
.CENB(ram0_CSBB_SEL),
.WENBA(ram0_WENBA_SEL),
.WENBB(ram0_WENBB_SEL),
.DA(ram0_I_SEL1),
.QA(QA_0),
.DB(ram1_I_SEL1),
.QB(QB_0)
);
ram #(
.ADDRWID(ADDRWID - 2),
.INIT(INIT[1*9216+:9216]),
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int),
.init_ad(init_ad2)
) ram1_inst (
.AA(ram1_AA_SEL),
.AB(ram1_AB_SEL),
.CLKA(ram1_CEA),
.CLKB(ram1_CEB),
.WENA(ram1_WEBA_SEL),
.WENB(ram1_WEBB_SEL),
.CENA(ram1_CSBA_SEL),
.CENB(ram1_CSBB_SEL),
.WENBA(ram1_WENBA_SEL),
.WENBB(ram1_WENBB_SEL),
.DA(ram1_I_SEL2),
.QA(QA_1),
.DB(ram1_I_SEL1),
.QB(QB_1)
);
endmodule
`timescale 1 ns / 10 ps
`define ADDRWID 11
`define DATAWID 18
`define WEWID 2
module ram_block_8K (
CLK1_0,
CLK2_0,
WD_0,
RD_0,
A1_0,
A2_0,
CS1_0,
CS2_0,
WEN1_0,
POP_0,
Almost_Full_0,
Almost_Empty_0,
PUSH_FLAG_0,
POP_FLAG_0,
FIFO_EN_0,
SYNC_FIFO_0,
PIPELINE_RD_0,
WIDTH_SELECT1_0,
WIDTH_SELECT2_0,
CLK1_1,
CLK2_1,
WD_1,
RD_1,
A1_1,
A2_1,
CS1_1,
CS2_1,
WEN1_1,
POP_1,
Almost_Empty_1,
Almost_Full_1,
PUSH_FLAG_1,
POP_FLAG_1,
FIFO_EN_1,
SYNC_FIFO_1,
PIPELINE_RD_1,
WIDTH_SELECT1_1,
WIDTH_SELECT2_1,
CONCAT_EN_0,
CONCAT_EN_1,
PUSH_0,
PUSH_1,
aFlushN_0,
aFlushN_1
);
parameter [18431:0] INIT = 18432\'bx;
parameter INIT_FILE = "init.mem";
parameter data_width_int = 16;
parameter data_depth_int = 1024;
input CLK1_0;
input CLK2_0;
input [`DATAWID-1:0] WD_0;
output [`DATAWID-1:0] RD_0;
input [`ADDRWID-1:0] A1_0; //chnge
input [`ADDRWID-1:0] A2_0; //chnge
input CS1_0;
input CS2_0;
input [`WEWID-1:0] WEN1_0;
input POP_0;
output Almost_Full_0;
output Almost_Empty_0;
output [3:0] PUSH_FLAG_0;
output [3:0] POP_FLAG_0;
input FIFO_EN_0;
input SYNC_FIFO_0;
input PIPELINE_RD_0;
input [1:0] WIDTH_SELECT1_0;
input [1:0] WIDTH_SELECT2_0;
input CLK1_1;
input CLK2_1;
input [`DATAWID-1:0] WD_1;
output [`DATAWID-1:0] RD_1;
input [`ADDRWID-1:0] A1_1; //chnge
input [`ADDRWID-1:0] A2_1; //chnge
input CS1_1;
input CS2_1;
input [`WEWID-1:0] WEN1_1;
input POP_1;
output Almost_Full_1;
output Almost_Empty_1;
output [3:0] PUSH_FLAG_1;
output [3:0] POP_FLAG_1;
input FIFO_EN_1;
input SYNC_FIFO_1;
input PIPELINE_RD_1;
input [1:0] WIDTH_SELECT1_1;
input [1:0] WIDTH_SELECT2_1;
input CONCAT_EN_0;
input CONCAT_EN_1;
input PUSH_0;
input PUSH_1;
input aFlushN_0;
input aFlushN_1;
reg rstn;
wire [ `WEWID-1:0] RAM0_WENb1_SEL;
wire [ `WEWID-1:0] RAM1_WENb1_SEL;
wire RAM0_CS1_SEL;
wire RAM0_CS2_SEL;
wire RAM1_CS1_SEL;
wire RAM1_CS2_SEL;
wire [`ADDRWID-1:0] Fifo0_Write_Addr;
wire [`ADDRWID-1:0] Fifo0_Read_Addr;
wire [`ADDRWID-1:0] Fifo1_Write_Addr;
wire [`ADDRWID-1:0] Fifo1_Read_Addr;
wire [`ADDRWID-1:0] RAM0_AA_SEL;
wire [`ADDRWID-1:0] RAM0_AB_SEL;
wire [`ADDRWID-1:0] RAM1_AA_SEL;
wire [`ADDRWID-1:0] RAM1_AB_SEL;
wire Concat_En_SEL;
// To simulate POR
initial begin
rstn = 1\'b0;
#30 rstn = 1\'b1;
end
assign fifo0_rstn = rstn & aFlushN_0;
assign fifo1_rstn = rstn & aFlushN_1;
assign Concat_En_SEL = (CONCAT_EN_0 | WIDTH_SELECT1_0[1] | WIDTH_SELECT2_0[1]) ? 1\'b1 : 1\'b0;
assign RAM0_AA_SEL = FIFO_EN_0 ? Fifo0_Write_Addr : A1_0[`ADDRWID-1:0];
assign RAM0_AB_SEL = FIFO_EN_0 ? Fifo0_Read_Addr : A2_0[`ADDRWID-1:0];
assign RAM1_AA_SEL = FIFO_EN_1 ? Fifo1_Write_Addr : A1_1[`ADDRWID-1:0];
assign RAM1_AB_SEL = FIFO_EN_1 ? Fifo1_Read_Addr : A2_1[`ADDRWID-1:0];
assign RAM0_WENb1_SEL = FIFO_EN_0 ? {`WEWID{~PUSH_0}} : ~WEN1_0;
assign RAM1_WENb1_SEL = ( FIFO_EN_1 & ~Concat_En_SEL ) ? { `WEWID{ ~PUSH_1 } } :
( ( FIFO_EN_0 & Concat_En_SEL ) ? ( WIDTH_SELECT1_0[1] ? { `WEWID{ ~PUSH_0 } } : { `WEWID{ 1\'b1 } } ) : ~WEN1_1 );
assign RAM0_CS1_SEL = (FIFO_EN_0 ? CS1_0 : ~CS1_0);
assign RAM0_CS2_SEL = (FIFO_EN_0 ? CS2_0 : ~CS2_0);
assign RAM1_CS1_SEL = (FIFO_EN_1 ? CS1_1 : ~CS1_1);
assign RAM1_CS2_SEL = (FIFO_EN_1 ? CS2_1 : ~CS2_1);
x2_model #(
.ADDRWID(`ADDRWID),
.INIT(INIT),
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
) x2_8K_model_inst (
.Concat_En(Concat_En_SEL),
.ram0_WIDTH_SELA(WIDTH_SELECT1_0),
.ram0_WIDTH_SELB(WIDTH_SELECT2_0),
.ram0_PLRD(PIPELINE_RD_0),
.ram0_CEA(CLK1_0),
.ram0_CEB(CLK2_0),
.ram0_I(WD_0),
.ram0_O(RD_0),
.ram0_AA(RAM0_AA_SEL),
.ram0_AB(RAM0_AB_SEL),
.ram0_CSBA(RAM0_CS1_SEL),
.ram0_CSBB(RAM0_CS2_SEL),
.ram0_WENBA(RAM0_WENb1_SEL),
.ram1_WIDTH_SELA(WIDTH_SELECT1_1),
.ram1_WIDTH_SELB(WIDTH_SELECT2_1),
.ram1_PLRD(PIPELINE_RD_1),
.ram1_CEA(CLK1_1),
.ram1_CEB(CLK2_1),
.ram1_I(WD_1),
.ram1_O(RD_1),
.ram1_AA(RAM1_AA_SEL),
.ram1_AB(RAM1_AB_SEL),
.ram1_CSBA(RAM1_CS1_SEL),
.ram1_CSBB(RAM1_CS2_SEL),
.ram1_WENBA(RAM1_WENb1_SEL)
);
fifo_controller_model #(
.MAX_PTR_WIDTH(`ADDRWID + 1)
) fifo_controller0_inst (
.Push_Clk(CLK1_0),
.Pop_Clk (CLK2_0),
.Fifo_Push(PUSH_0),
.Fifo_Push_Flush(CS1_0),
.Fifo_Full(Almost_Full_0),
.Fifo_Full_Usr(PUSH_FLAG_0),
.Fifo_Pop(POP_0),
.Fifo_Pop_Flush(CS2_0),
.Fifo_Empty(Almost_Empty_0),
.Fifo_Empty_Usr(POP_FLAG_0),
.Write_Addr(Fifo0_Write_Addr),
.Read_Addr(Fifo0_Read_Addr),
.Fifo_Ram_Mode(Concat_En_SEL),
.Fifo_Sync_Mode(SYNC_FIFO_0),
.Fifo_Push_Width(WIDTH_SELECT1_0),
.Fifo_Pop_Width(WIDTH_SELECT2_0),
.Rst_n(fifo0_rstn)
);
fifo_controller_model #(
.MAX_PTR_WIDTH(`ADDRWID + 1)
) fifo_controller1_inst (
.Push_Clk(CLK1_1),
.Pop_Clk (CLK2_1),
.Fifo_Push(PUSH_1),
.Fifo_Push_Flush(CS1_1),
.Fifo_Full(Almost_Full_1),
.Fifo_Full_Usr(PUSH_FLAG_1),
.Fifo_Pop(POP_1),
.Fifo_Pop_Flush(CS2_1),
.Fifo_Empty(Almost_Empty_1),
.Fifo_Empty_Usr(POP_FLAG_1),
.Write_Addr(Fifo1_Write_Addr),
.Read_Addr(Fifo1_Read_Addr),
.Fifo_Ram_Mode(1\'b0),
.Fifo_Sync_Mode(SYNC_FIFO_1),
.Fifo_Push_Width({1\'b0, WIDTH_SELECT1_1[0]}),
.Fifo_Pop_Width({1\'b0, WIDTH_SELECT2_1[0]}),
.Rst_n(fifo1_rstn)
);
endmodule
module sw_mux (
port_out,
default_port,
alt_port,
switch
);
output port_out;
input default_port;
input alt_port;
input switch;
assign port_out = switch ? alt_port : default_port;
endmodule
`define ADDRWID_8k2 11
`define DATAWID 18
`define WEWID 2
module ram8k_2x1_cell (
CLK1_0,
CLK2_0,
CLK1S_0,
CLK2S_0,
WD_0,
RD_0,
A1_0,
A2_0,
CS1_0,
CS2_0,
WEN1_0,
CLK1EN_0,
CLK2EN_0,
P1_0,
P2_0,
Almost_Full_0,
Almost_Empty_0,
PUSH_FLAG_0,
POP_FLAG_0,
FIFO_EN_0,
SYNC_FIFO_0,
PIPELINE_RD_0,
WIDTH_SELECT1_0,
WIDTH_SELECT2_0,
DIR_0,
ASYNC_FLUSH_0,
ASYNC_FLUSH_S0,
CLK1_1,
CLK2_1,
CLK1S_1,
CLK2S_1,
WD_1,
RD_1,
A1_1,
A2_1,
CS1_1,
CS2_1,
WEN1_1,
CLK1EN_1,
CLK2EN_1,
P1_1,
P2_1,
Almost_Empty_1,
Almost_Full_1,
PUSH_FLAG_1,
POP_FLAG_1,
FIFO_EN_1,
SYNC_FIFO_1,
PIPELINE_RD_1,
WIDTH_SELECT1_1,
WIDTH_SELECT2_1,
DIR_1,
ASYNC_FLUSH_1,
ASYNC_FLUSH_S1,
CONCAT_EN_0,
CONCAT_EN_1
);
parameter [18431:0] INIT = 18432\'bx;
parameter INIT_FILE = "init.mem";
parameter data_width_int = 16;
parameter data_depth_int = 1024;
input CLK1_0;
input CLK2_0;
input CLK1S_0;
input CLK2S_0;
input [`DATAWID-1:0] WD_0;
output [`DATAWID-1:0] RD_0;
input [`ADDRWID_8k2-1:0] A1_0;
input [`ADDRWID_8k2-1:0] A2_0;
input CS1_0;
input CS2_0;
input [`WEWID-1:0] WEN1_0;
input CLK1EN_0;
input CLK2EN_0;
input P1_0;
input P2_0;
output Almost_Full_0;
output Almost_Empty_0;
output [3:0] PUSH_FLAG_0;
output [3:0] POP_FLAG_0;
input FIFO_EN_0;
input SYNC_FIFO_0;
input DIR_0;
input ASYNC_FLUSH_0;
input ASYNC_FLUSH_S0;
input PIPELINE_RD_0;
input [1:0] WIDTH_SELECT1_0;
input [1:0] WIDTH_SELECT2_0;
input CLK1_1;
input CLK2_1;
input CLK1S_1;
input CLK2S_1;
input [`DATAWID-1:0] WD_1;
output [`DATAWID-1:0] RD_1;
input [`ADDRWID_8k2-1:0] A1_1;
input [`ADDRWID_8k2-1:0] A2_1;
input CS1_1;
input CS2_1;
input [`WEWID-1:0] WEN1_1;
input CLK1EN_1;
input CLK2EN_1;
input P1_1;
input P2_1;
output Almost_Full_1;
output Almost_Empty_1;
output [3:0] PUSH_FLAG_1;
output [3:0] POP_FLAG_1;
input FIFO_EN_1;
input SYNC_FIFO_1;
input DIR_1;
input ASYNC_FLUSH_1;
input ASYNC_FLUSH_S1;
input PIPELINE_RD_1;
input [1:0] WIDTH_SELECT1_1;
input [1:0] WIDTH_SELECT2_1;
input CONCAT_EN_0;
input CONCAT_EN_1;
//CODE here
reg RAM0_domain_sw;
reg RAM1_domain_sw;
wire CLK1P_0, CLK1P_1, CLK2P_0, CLK2P_1, ASYNC_FLUSHP_1, ASYNC_FLUSHP_0;
assign 'b'WidSel1_1 = WIDTH_SELECT1_0[1];
assign WidSel2_1 = WIDTH_SELECT2_0[1];
assign CLK1P_0 = CLK1S_0 ? ~CLK1_0 : CLK1_0;
assign CLK1P_1 = CLK1S_1 ? ~CLK1_1 : CLK1_1;
assign CLK2P_0 = CLK2S_0 ? ~CLK2_0 : CLK2_0;
assign CLK2P_1 = CLK2S_1 ? ~CLK2_1 : CLK2_1;
assign ASYNC_FLUSHP_0 = ASYNC_FLUSH_S0 ? ~ASYNC_FLUSH_0 : ASYNC_FLUSH_0;
assign ASYNC_FLUSHP_1 = ASYNC_FLUSH_S1 ? ~ASYNC_FLUSH_1 : ASYNC_FLUSH_1;
/* FIFO mode-only switching */
always @(CONCAT_EN_0 or FIFO_EN_0 or FIFO_EN_1 or WidSel1_1 or WidSel2_1 or DIR_0 or DIR_1) begin
if (CONCAT_EN_0) //CONCAT enabled, only RAM0 ports are checked
\t\tbegin
if (~FIFO_EN_0) //RAM MODE (no switching)
\t\t\tbegin
RAM0_domain_sw = 1\'b0; //Both Switches are on default during RAM mode
RAM1_domain_sw = 1\'b0;
end
\t\telse //FIFO Mode
\t\t\tbegin
RAM0_domain_sw = DIR_0; //Both Switches will get DIR_0 (primary port) during concat
RAM1_domain_sw = DIR_0;
end
end
\telse //CONCAT disabled, RAM0 and RAM1 ports are be checked
\t\tbegin
if (WidSel1_1 || WidSel2_1) //AUTO-CONCAT FIFO/RAM Mode Horizontal Concatenation
\t\t\t\tbegin
if (~FIFO_EN_0) //RAM MODE (no switching)
\t\t\t\t\tbegin
RAM0_domain_sw = 1\'b0; //Both Switches are on default during RAM mode
RAM1_domain_sw = 1\'b0;
end
\t\t\t\telse //FIFO Mode
\t\t\t\t\tbegin
RAM0_domain_sw = DIR_0; //Both Switches will get DIR_0 (primary port) during concat
RAM1_domain_sw = DIR_0;
end
end
\t\t\telse //FIFO/RAM Individual Mode
\t\t\t\tbegin
if (~FIFO_EN_0) //RAM0 Mode
RAM0_domain_sw = 1\'b0;
else //FIFO0 Mode
RAM0_domain_sw = DIR_0;
if (~FIFO_EN_1) //RAM1 Mode
RAM1_domain_sw = 1\'b0;
else //FIFO1 Mode
RAM1_domain_sw = DIR_1;
end
end
end
assign RAM0_Clk1_gated = CLK1EN_0 & CLK1P_0;
assign RAM0_Clk2_gated = CLK2EN_0 & CLK2P_0;
assign RAM1_Clk1_gated = CLK1EN_1 & CLK1P_1;
assign RAM1_Clk2_gated = CLK2EN_1 & CLK2P_1;
//PORT1 of RAMs is designated to PUSH circuitry, while PORT2 gets POP circuitry
sw_mux RAM0_clk_sw_port1 (
.port_out(RAM0_clk_port1),
.default_port(RAM0_Clk1_gated),
.alt_port(RAM0_Clk2_gated),
.switch(RAM0_domain_sw)
);
sw_mux RAM0_P_sw_port1 (
.port_out(RAM0_push_port1),
.default_port(P1_0),
.alt_port(P2_0),
.switch(RAM0_domain_sw)
);
sw_mux RAM0_Flush_sw_port1 (
.port_out(RAM0CS_Sync_Flush_port1),
.default_port(CS1_0),
.alt_port(CS2_0),
.switch(RAM0_domain_sw)
);
sw_mux RAM0_WidSel0_port1 (
.port_out(RAM0_Wid_Sel0_port1),
.default_port(WIDTH_SELECT1_0[0]),
.alt_port(WIDTH_SELECT2_0[0]),
.switch(RAM0_domain_sw)
);
sw_mux RAM0_WidSel1_port1 (
.port_out(RAM0_Wid_Sel1_port1),
.default_port(WIDTH_SELECT1_0[1]),
.alt_port(WIDTH_SELECT2_0[1]),
.switch(RAM0_domain_sw)
);
sw_mux RAM0_clk_sw_port2 (
.port_out(RAM0_clk_port2),
.default_port(RAM0_Clk2_gated),
.alt_port(RAM0_Clk1_gated),
.switch(RAM0_domain_sw)
);
sw_mux RAM0_P_sw_port2 (
.port_out(RAM0_pop_port2),
.default_port(P2_0),
.alt_port(P1_0),
.switch(RAM0_domain_sw)
);
sw_mux RAM0_Flush_sw_port2 (
.port_out(RAM0CS_Sync_Flush_port2),
.default_port(CS2_0),
.alt_port(CS1_0),
.switch(RAM0_domain_sw)
);
sw_mux RAM0_WidSel0_port2 (
.port_out(RAM0_Wid_Sel0_port2),
.default_port(WIDTH_SELECT2_0[0]),
.alt_port(WIDTH_SELECT1_0[0]),
.switch(RAM0_domain_sw)
);
sw_mux RAM0_WidSel1_port2 (
.port_out(RAM0_Wid_Sel1_port2),
.default_port(WIDTH_SELECT2_0[1]),
.alt_port(WIDTH_SELECT1_0[1]),
.switch(RAM0_domain_sw)
);
sw_mux RAM1_clk_sw_port1 (
.port_out(RAM1_clk_port1),
.default_port(RAM1_Clk1_gated),
.alt_port(RAM1_Clk2_gated),
.switch(RAM1_domain_sw)
);
sw_mux RAM1_P_sw_port1 (
.port_out(RAM1_push_port1),
.default_port(P1_1),
.alt_port(P2_1),
.switch(RAM1_domain_sw)
);
sw_mux RAM1_Flush_sw_port1 (
.port_out(RAM1CS_Sync_Flush_port1),
.default_port(CS1_1),
.alt_port(CS2_1),
.switch(RAM1_domain_sw)
);
sw_mux RAM1_WidSel0_port1 (
.port_out(RAM1_Wid_Sel0_port1),
.default_port(WIDTH_SELECT1_1[0]),
.alt_port(WIDTH_SELECT2_1[0]),
.switch(RAM1_domain_sw)
);
sw_mux RAM1_WidSel1_port1 (
.port_out(RAM1_Wid_Sel1_port1),
.default_port(WIDTH_SELECT1_1[1]),
.alt_port(WIDTH_SELECT2_1[1]),
.switch(RAM1_domain_sw)
);
sw_mux RAM1_clk_sw_port2 (
.port_out(RAM1_clk_port2),
.default_port(RAM1_Clk2_gated),
.alt_port(RAM1_Clk1_gated),
.switch(RAM1_domain_sw)
);
sw_mux RAM1_P_sw_port2 (
.port_out(RAM1_pop_port2),
.default_port(P2_1),
.alt_port(P1_1),
.switch(RAM1_domain_sw)
);
sw_mux RAM1_Flush_sw_port2 (
.port_out(RAM1CS_Sync_Flush_port2),
.default_port(CS2_1),
.alt_port(CS1_1),
.switch(RAM1_domain_sw)
);
sw_mux RAM1_WidSel0_port2 (
.port_out(RAM1_Wid_Sel0_port2),
.default_port(WIDTH_SELECT2_1[0]),
.alt_port(WIDTH_SELECT1_1[0]),
.switch(RAM1_domain_sw)
);
sw_mux RAM1_WidSel1_port2 (
.port_out(RAM1_Wid_Sel1_port2),
.default_port(WIDTH_SELECT2_1[1]),
.alt_port(WIDTH_SELECT1_1[1]),
.switch(RAM1_domain_sw)
);
ram_block_8K #(
.INIT(INIT),
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
) ram_block_8K_inst (
.CLK1_0(RAM0_clk_port1),
.CLK2_0(RAM0_clk_port2),
.WD_0(WD_0),
.RD_0(RD_0),
.A1_0(A1_0),
.A2_0(A2_0),
.CS1_0(RAM0CS_Sync_Flush_port1),
.CS2_0(RAM0CS_Sync_Flush_port2),
.WEN1_0(WEN1_0),
.POP_0(RAM0_pop_port2),
.Almost_Full_0(Almost_Full_0),
.Almost_Empty_0(Almost_Empty_0),
.PUSH_FLAG_0(PUSH_FLAG_0),
.POP_FLAG_0(POP_FLAG_0),
.FIFO_EN_0(FIFO_EN_0),
.SYNC_FIFO_0(SYNC_FIFO_0),
.PIPELINE_RD_0(PIPELINE_RD_0),
.WIDTH_SELECT1_0({RAM0_Wid_Sel1_port1, RAM0_Wid_Sel0_port1}),
.WIDTH_SELECT2_0({RAM0_Wid_Sel1_port2, RAM0_Wid_Sel0_port2}),
.CLK1_1(RAM1_clk_port1),
.CLK2_1(RAM1_clk_port2),
.WD_1(WD_1),
.RD_1(RD_1),
.A1_1(A1_1),
.A2_1(A2_1),
.CS1_1(RAM1CS_Sync_Flush_port1),
.CS2_1(RAM1CS_Sync_Flush_port2),
.WEN1_1(WEN1_1),
.POP_1(RAM1_pop_port2),
.Almost_Empty_1(Almost_Empty_1),
.Almost_Full_1(Almost_Full_1),
.PUSH_FLAG_1(PUSH_FLAG_1),
.POP_FLAG_1(POP_FLAG_1),
.FIFO_EN_1(FIFO_EN_1),
.SYNC_FIFO_1(SYNC_FIFO_1),
.PIPELINE_RD_1(PIPELINE_RD_1),
.WIDTH_SELECT1_1({RAM1_Wid_Sel1_port1, RAM1_Wid_Sel0_port1}),
.WIDTH_SELECT2_1({RAM1_Wid_Sel1_port2, RAM1_Wid_Sel0_port2}),
.CONCAT_EN_0(CONCAT_EN_0),
.CONCAT_EN_1(CONCAT_EN_1),
.PUSH_0(RAM0_push_port1),
.PUSH_1(RAM1_push_port1),
.aFlushN_0(~ASYNC_FLUSHP_0),
.aFlushN_1(~ASYNC_FLUSHP_1)
);
endmodule
module ram8k_2x1_cell_macro #(
parameter [18431:0] INIT = 18432\'bx,
parameter INIT_FILE = "init.mem",
parameter data_width_int = 16,
parameter data_depth_int = 1024
) (
input [10:0] A1_0,
input [10:0] A1_1,
input [10:0] A2_0,
input [10:0] A2_1,
(* clkbuf_sink *)
input CLK1_0,
(* clkbuf_sink *)
input CLK1_1,
(* clkbuf_sink *)
input CLK2_0,
(* clkbuf_sink *)
input CLK2_1,
output Almost_Empty_0,
Almost_Empty_1,
Almost_Full_0,
Almost_Full_1,
input ASYNC_FLUSH_0,
ASYNC_FLUSH_1,
ASYNC_FLUSH_S0,
ASYNC_FLUSH_S1,
CLK1EN_0,
CLK1EN_1,
CLK1S_0,
CLK1S_1,
CLK2EN_0,
CLK2EN_1,
CLK2S_0,
CLK2S_1,
CONCAT_EN_0,
CONCAT_EN_1,
CS1_0,
CS1_1,
CS2_0,
CS2_1,
DIR_0,
DIR_1,
FIFO_EN_0,
FIFO_EN_1,
P1_0,
P1_1,
P2_0,
P2_1,
PIPELINE_RD_0,
PIPELINE_RD_1,
output [3:0] POP_FLAG_0,
output [3:0] POP_FLAG_1,
output [3:0] PUSH_FLAG_0,
output [3:0] PUSH_FLAG_1,
output [17:0] RD_0,
output [17:0] RD_1,
input SYNC_FIFO_0,
SYNC_FIFO_1,
input [17:0] WD_0,
input [17:0] WD_1,
input [1:0] WEN1_0,
input [1:0] WEN1_1,
input [1:0] WIDTH_SELECT1_0,
input [1:0] WIDTH_SELECT1_1,
input [1:0] WIDTH_SELECT2_0,
input [1:0] WIDTH_SELECT2_1,
input SD,
DS,
LS,
SD_RB1,
LS_RB1,
DS_RB1,
RMEA,
RMEB,
TEST1A,
TEST1B,
input [3:0] RMA,
input [3:0] RMB
);
ram8k_2x1_cell #(
.INIT(INIT),
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
) I1 (
.A1_0({A1_0[10:0]}),
.A1_1({A1_1[10:0]}),
.A2_0({A2_0[10:0]}),
.A2_1({A2_1[10:0]}),
.Almost_Empty_0(Almost_Empty_0),
.Almost_Empty_1(Almost_Empty_1),
.Almost_Full_0(Almost_Full_0),
.Almost_Full_1(Almost_Full_1),
.ASYNC_FLUSH_0(ASYNC_FLUSH_0),
.ASYNC_FLUSH_1(ASYNC_FLUSH_1),
.ASYNC_FLUSH_S0(ASYNC_FLUSH_S0),
.ASYNC_FLUSH_S1(ASYNC_FLUSH_S1),
.CLK1_0(CLK1_0),
.CLK1_1(CLK1_1),
.CLK1EN_0(CLK1EN_0),
.CLK1EN_1(CLK1EN_1),
.CLK1S_0(CLK1S_0),
.CLK1S_1(CLK1S_1),
.CLK2_0(CLK2_0),
.CLK2_1(CLK2_1),
.CLK2EN_0(CLK2EN_0),
.CLK2EN_1(CLK2EN_1),
.CLK2S_0(CLK2S_0),
.CLK2S_1(CLK2S_1),
.CONCAT_EN_0(CONCAT_EN_0),
.CONCAT_EN_1(CONCAT_EN_1),
.CS1_0(CS1_0),
.CS1_1(CS1_1),
.CS2_0(CS2_0),
.CS2_1(CS2_1),
.DIR_0(DIR_0),
.DIR_1(DIR_1),
.FIFO_EN_0(FIFO_EN_0),
.FIFO_EN_1(FIFO_EN_1),
.P1_0(P1_0),
.P1_1(P1_1),
.P2_0(P2_0),
.P2_1(P2_1),
.PIPELINE_RD_0(PIPELINE_RD_0),
.PIPELINE_RD_1(PIPELINE_RD_1),
.POP_FLAG_0({POP_FLAG_0[3:0]}),
.POP_FLAG_1({POP_FLAG_1[3:0]}),
.PUSH_FLAG_0({PUSH_FLAG_0[3:0]}),
.PUSH_FLAG_1({PUSH_FLAG_1[3:0]}),
.RD_0({RD_0[17:0]}),
.RD_1({RD_1[17:0]}),
.SYNC_FIFO_0(SYNC_FIFO_0),
.SYNC_FIFO_1(SYNC_FIFO_1),
.WD_0({WD_0[17:0]}),
.WD_1({WD_1[17:0]}),
.WEN1_0({WEN1_0[1:0]}),
.WEN1_1({WEN1_1[1:0]}),
.WIDTH_SELECT1_0({WIDTH_SELECT1_0[1:0]}),
.WIDTH_SELECT1_1({WIDTH_SELECT1_1[1:0]}),
.WIDTH_SELECT2_0({WIDTH_SELECT2_0[1:0]}),
.WIDTH_SELECT2_1({WIDTH_SELECT2_1[1:0]})
);
endmodule /* ram8k_2x1_cell_macro */
module RAM_8K_BLK (
WA,
RA,
WD,
WClk,
RClk,
WClk_En,
RClk_En,
WEN,
RD
);
parameter addr_int \t= 9,
data_depth_int = 512,
data_width_int = 18,
wr_enable_int \t= 2,
reg_rd_int \t= 0;
parameter [8191:0] INIT = 8192\'bx;
parameter INIT_FILE = "init.mem";
input [addr_int-1:0] WA;
input [addr_int-1:0] RA;
input WClk, RClk;
input WClk_En, RClk_En;
input [wr_enable_int-1:0] WEN;
input [data_width_int-1:0] WD;
output [data_width_int-1:0] RD;
wire VCC, GND;
wire WClk0_Sel, RClk0_Sel;
wire WClk1_Sel, RClk1_Sel;
wire reg_rd0;
wire reg_rd1;
wire [10:0] addr_wr0, addr_rd0, addr_wr1, addr_rd1;
wire [17:0] in_reg0;
wire [ 2:0] wen_reg0;
wire [15:0] out_reg0;
wire [ 1:0] out_par0;
wire [1:0] WS1_0, WS2_0;
wire [1:0] WS_GND;
wire LS, DS, SD, LS_RB1, DS_RB1, SD_RB1;
wire WD0_SEL, RD0_SEL;
wire WD1_SEL, RD1_SEL;
assign VCC = 1\'b1;
assign GND = 1\'b0;
assign WD0_SEL = 1\'b1;
assign RD0_SEL = 1\'b1;
assign WD1_SEL = 1\'b0;
assign RD1_SEL = 1\'b0;
assign WClk0_Sel = 1\'b0;
assign RClk0_Sel = 1\'b0;
assign WClk1_Sel = 1\'b0;
assign RClk1_Sel = 1\'b0;
assign LS = 1\'b0;
assign DS = 1\'b0;
assign SD = 1\'b0;
assign LS_RB1 = 1\'b0;
assign DS_RB1 = 1\'b0;
assign SD_RB1 = 1\'b0;
assign reg_rd0 = reg_rd_int;
assign WS_GND = 2\'b00;
assign reg_rd1 = 1\'b0;
assign wen_reg0[2:wr_enable_int] = 0;
assign wen_reg0[wr_enable_int-1:0] = WEN;
assign addr_wr1 = 11\'b0000000000;
assign addr_rd1 = 11\'b0000000000;
generate
if (addr_int == 11) begin
assign addr_wr0[10:0] = WA;
assign addr_rd0[10:0] = RA;
end else begin
assign addr_wr0[10:addr_int] = 0;
assign addr_wr0[addr_int-1:0] = WA;
assign addr_rd0[10:addr_int] = 0;
assign addr_rd0[addr_int-1:0] = RA;
end
if (data_width_int == 16) begin
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end else if (data_width_int > 8 && data_width_int < 16) begin
assign in_reg0[15:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end else if (data_width_int <= 8) begin
assign in_reg0[15:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end
if (data_width_int <= 8) begin
assign WS1_0 = 2\'b00;
assign WS2_0 = 2\'b00;
end else if (data_width_int > 8 && data_width_int <= 16) begin
assign WS1_0 = 2\'b01;
assign WS2_0 = 2\'b01;
end else if (data_width_int > 16) begin
assign WS1_0 = 2\'b10;
assign WS2_0 = 2\'b10;
end
endgenerate
ram8k_2x1_cell_macro #(
`include "bram_init_8_16.vh"
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
) U1 (
.A1_0(addr_wr0),
.A1_1(addr_wr1),
.A2_0(addr_rd0),
.A2_1(addr_rd1),
.ASYNC_FLUSH_0(GND), //chk
.ASYNC_FLUSH_1(GND), //chk
.ASYNC_FLUSH_S0(GND),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(WClk),
.CLK1_1(GND),
.CLK1S_0(WClk0_Sel),
.CLK1S_1(WClk1_Sel),
.CLK1EN_0(WClk_En),
.CLK1EN_1(GND),
.CLK2_0(RClk),
.CLK2_1(GND),
.CLK2S_0(RClk0_Sel),
.CLK2S_1(RClk1_Sel),
.CLK2EN_0(RClk_En),
.CLK2EN_1(GND),
.CONCAT_EN_0(GND),
.CONCAT_EN_1(GND),
.CS1_0(WD0_SEL),
.CS1_1(WD1_SEL),
.CS2_0(RD0_SEL),
.CS2_1(RD1_SEL),
.DIR_0(GND),
.DIR_1(GND),
.FIFO_EN_0(GND),
.FIFO_EN_1(GND),
.P1_0(GND), //P1_0
.P1_1(GND), //P1_1
.P2_0(GND), //
.P2_1(GND), //
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(reg_rd1),
.SYNC_FIFO_0(GND),
.SYNC_FIFO_1(GND),
.WD_1({18{GND}}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1(WS_GND),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1(WS_GND),
.WEN1_0(wen_reg0[1:0]),
.WEN1_1({2{GND}}),
.Almost_Empty_0(),
.Almost_Empty_1(),
.Almost_Full_0(),
.Almost_Full_1(),
.POP_FLAG_0(),
.POP_FLAG_1(),
.PUSH_FLAG_0(),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1(),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
assign RD[data_width_int-1 : 0] = out_reg0[data_width_int-1 : 0];
endmodule
module RAM_16K_BLK (
WA,
RA,
WD,
WClk,
RClk,
WClk_En,
RClk_En,
WEN,
RD
);
parameter addr_int \t= 9,
data_depth_int = 512,
\t \t\t data_width_int = 36,
wr_enable_int \t= 4,
\t \t\t reg_rd_int \t= 0;
parameter [16383:0] INIT = 16384\'bx;
parameter INIT_FILE = "init.mem";
input [addr_int-1:0] WA;
input [addr_int-1:0] RA;
input WClk, RClk;
input WClk_En, RClk_En;
input [wr_enable_int-1:0] WEN;
input [data_width_int-1:0] WD;
output [data_width_int-1:0] RD;
wire VCC, GND;
wire WClk0_Sel, RClk0_Sel;
wire WClk1_Sel, RClk1_Sel;
wire reg_rd0;
wire reg_rd1;
wire [10:0] addr_wr0, addr_rd0, addr_wr1, addr_rd1;
wire [31:0] in_reg0;
wire [ 4:0] wen_reg0;
wire [31:0] out_reg0;
wire [ 3:0] out_par0;
wire [1:0] WS1_0, WS2_0;
wire [1:0] WS_GND;
wire LS, DS, SD, LS_RB1, DS_RB1, SD_RB1;
wire WD0_SEL, RD0_SEL;
wire WD1_SEL, RD1_SEL;
assign VCC = 1\'b1;
assign GND = 1\'b0;
assign WD0_SEL = 1\'b1;
assign RD0_SEL = 1\'b1;
assign WD1_SEL = 1\'b1;
assign RD1_SEL = 1\'b1;
assign WClk0_Sel = 1\'b0;
assign RClk0_Sel = 1\'b0;
assign WClk1_Sel = 1\'b0;
assign RClk1_Sel = 1\'b0;
assign LS = 1\'b0;
assign DS = 1\'b0;
assign SD = 1\'b0;
assign LS_RB1 = 1\'b0;
assign DS_RB1 = 1\'b0;
assign SD_RB1 = 1\'b0;
assign reg_rd0 = reg_rd_int;
assign WS_GND = 2\'b00;
assign reg_rd1 = 1\'b0;
assign wen_reg0[4:wr_enable_int] = 0;
assign wen_reg0[wr_enable_int-1:0] = WEN;
assign addr_wr1 = 11\'b0000000000;
assign addr_rd1 = 11\'b0000000000;
generate
if (addr_int == 11) begin
assign addr_wr0[10:0] = WA;
assign addr_rd0[10:0] = RA;
end else begin
assign addr_wr0[10:addr_int] = 0;
assign addr_wr0[addr_int-1:0] = WA;
assign addr_rd0[10:addr_int] = 0;
assign addr_rd0[addr_int-1:0] = RA;
end
if (data_width_int == 32) begin
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end else if (data_width_int > 8 && data_width_int < 32) begin
assign in_reg0[31:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end else if (data_width_int <= 8) begin
assign in_reg0[31:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end
if (data_width_int <= 8) begin
assign WS1_0 = 2\'b00;
assign WS2_0 = 2\'b00;
end else if (data_width_int > 8 && data_width_int <= 16) begin
assign WS1_0 = 2\'b01;
assign WS2_0 = 2\'b01;
end else if (data_width_int > 16) begin
assign WS1_0 = 2\'b10;
assign WS2_0 = 2\'b10;
end
if (data_width_int <= 16) begin
ram8k_2x1_cell_macro #(
`include "bram_init_8_16.vh"
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
) U1 (
.A1_0(addr_wr0),
.A1_1(addr_wr1),
.A2_0(addr_rd0),
.A2_1(addr_rd1),
.ASYNC_FLUSH_0(GND),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(GND),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(WClk),
.CLK1_1(WClk),
.CLK1S_0(WClk0_Sel),
.CLK1S_1(WClk0_Sel),
.CLK1EN_0(WClk_En),
.CLK1EN_1(WClk_En),
.CLK2_0(RClk),
.CLK2_1(RClk),
.CLK2S_0(RClk0_Sel),
.CLK2S_1(RClk0_Sel),
.CLK2EN_0(RClk_En),
.CLK2EN_1(RClk_En),
.CONCAT_EN_0(VCC),
.CONCAT_EN_1(GND),
.CS1_0(WD0_SEL),
.CS1_1(GND),
.CS2_0(RD0_SEL),
.CS2_1(GND),
.DIR_0(GND),
.DIR_1(GND),
.FIFO_EN_0(GND),
.FIFO_EN_1(GND),
.P1_0(GND),
.P1_1(GND),
.P2_0(GND),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(GND),
.SYNC_FIFO_1(GND),
.WD_1({18{GND}}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1(WS_GND),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1(WS_GND),
.WEN1_0(wen_reg0[1:0]),
.WEN1_1(wen_reg0[3:2]),
.Almost_Empty_0(),
.Almost_Empty_1(),
.Almost_Full_0(),
.Almost_Full_1(),
.POP_FLAG_0(),
.POP_FLAG_1(),
.PUSH_FLAG_0(),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1(),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
end else if (data_width_int > 16) begin
ram8k_2x1_cell_macro #(
`include "bram_init_32.vh"
.INIT_FILE(INIT_FILE),
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
) U2 (
.A1_0(addr_wr0),
.A1_1(addr_wr1),
.A2_0(addr_rd0),
.A2_1(addr_rd1),
.ASYNC_FLUSH_0(GND),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(GND),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(WClk),
.CLK1_1(WClk),
.CLK1S_0(WClk0_Sel),
.CLK1S_1(WClk0_Sel),
.CLK1EN_0(WClk_En),
.CLK1EN_1(WClk_En),
.CLK2_0(RClk),
.CLK2_1(RClk),
.CLK2S_0(RClk0_Sel),
.CLK2S_1(RClk0_Sel),
.CLK2EN_0(RClk_En),
.CLK2EN_1(RClk_En),
.CONCAT_EN_0(VCC),
.CONCAT_EN_1(GND),
.CS1_0(WD0_SEL),
.CS1_1(GND),
.CS2_0(RD0_SEL),
.CS2_1(GND),
.DIR_0(GND),
.DIR_1(GND),
.FIFO_EN_0(GND),
.FIFO_EN_1(GND),
.P1_0(GND),
.P1_1(GND),
.P2_0(GND),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(GND),
.SYNC_FIFO_1(GND),
.WD_1({1\'b0, in_reg0[31:24], 1\'b0, in_reg0[23:16]}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1(WS_GND),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1(WS_GND),
.WEN1_0(wen_reg0[1:0]),
.WEN1_1(wen_reg0[3:2]),
.Almost_Empty_0(),
.Almost_Empty_1(),
.Almost_Full_0(),
.Almost_Full_1(),
.POP_FLAG_0(),
.POP_FLAG_1(),
.PUSH_FLAG_0(),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1({out_par0[3], out_reg0[31:24], out_par0[2], out_reg0[23:16]}),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
end
endgenerate
assign RD[data_width_int-1 : 0] = out_reg0[data_width_int-1 : 0];
endmodule
module FIFO_8K_BLK (
DIN,
Fifo_Push_Flush,
Fifo_Pop_Flush,
PUSH,
POP,
Push_Clk,
Pop_Clk,
Push_Clk_En,
Pop_Clk_En,
Fifo_Dir,
Async_Flush,
Almost_Full,
Almost_Empty,
PUSH_FLAG,
POP_FLAG,
DOUT
);
parameter data_depth_int = 512, data_width_int = 36, reg_rd_int = 0, sync_fifo_int = 0;
input Fifo_Push_Flush, Fifo_Pop_Flush;
input Push_Clk, Pop_Clk;
input PUSH, POP;
input [data_width_int-1:0] DIN;
input Push_Clk_En, Pop_Clk_En, Fifo_Dir, Async_Flush;
output [data_width_int-1:0] DOUT;
output [3:0] PUSH_FLAG, POP_FLAG;
output Almost_Full, Almost_Empty;
wire LS, DS, SD, LS_RB1, DS_RB1, SD_RB1;
wire VCC, GND;
wire [10:0] addr_wr, addr_rd;
wire clk1_sig0, clk2_sig0, clk1_sig_en0, clk2_sig_en0, fifo_clk1_flush_sig0, fifo_clk2_flush_sig0, p1_sig0, p2_sig0,clk1_sig_sel0,clk2_sig_sel0;
wire reg_rd0, sync_fifo0;
wire [15:0] in_reg0;
wire [15:0] out_reg0;
wire [ 1:0] WS1_0;
wire [ 1:0] WS2_0;
wire Push_Clk0_Sel, Pop_Clk0_Sel;
wire Async_Flush_Sel0;
wire [1:0] out_par0;
assign LS = 1\'b0;
assign DS = 1\'b0;
assign SD = 1\'b0;
assign LS_RB1 = 1\'b0;
assign DS_RB1 = 1\'b0;
assign SD_RB1 = 1\'b0;
assign VCC = 1\'b1;
assign GND = 1\'b0;
assign Push_Clk0_Sel \t= 1\'b0;
assign Pop_Clk0_Sel \t= 1\'b0;
assign Async_Flush_Sel0 = 1\'b0;
assign reg_rd0 = reg_rd_int;
assign sync_fifo0 = sync_fifo_int;
assign addr_wr=11\'b00000000000;
assign addr_rd=11\'b00000000000;
assign clk1_sig0 = Fifo_Dir ? Pop_Clk : Push_Clk;
assign clk2_sig0 = Fifo_Dir ? Push_Clk : Pop_Clk ;
assign clk1_sig_en0 = Fifo_Dir ? Pop_Clk_En : Push_Clk_En;
assign clk2_sig_en0 = Fifo_Dir ? Push_Clk_En : Pop_Clk_En ;
assign clk1_sig_sel0 = Push_Clk0_Sel;
assign clk2_sig_sel0 = Pop_Clk0_Sel ;
assign fifo_clk1_flush_sig0 = Fifo_Dir ? Fifo_Pop_Flush : Fifo_Push_Flush;
assign fifo_clk2_flush_sig0 = Fifo_Dir ? Fifo_Push_Flush : Fifo_Pop_Flush ;
assign p1_sig0 = Fifo_Dir ? POP : PUSH;
assign p2_sig0 = Fifo_Dir ? PUSH : POP ;
generate
if (data_width_int == 16) begin
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end else if (data_width_int > 8 && data_width_int < 16) begin
assign in_reg0[15:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end else if (data_width_int <= 8) begin
assign in_reg0[15:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end
if (data_width_int <= 8) begin
assign WS1_0 = 2\'b00;
assign WS2_0 = 2\'b00;
end else if (data_width_int > 8 && data_width_int <= 16) begin
assign WS1_0 = 2\'b01;
assign WS2_0 = 2\'b01;
end else if (data_width_int > 16) begin
assign WS1_0 = 2\'b10;
assign WS2_0 = 2\'b10;
end
endgenerate
ram8k_2x1_cell_macro #(
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
) U1 (
.A1_0(addr_wr),
.A1_1(addr_wr),
.A2_0(addr_rd),
.A2_1(addr_rd),
.ASYNC_FLUSH_0(Async_Flush),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(Async_Flush_Sel0),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(clk1_sig0),
.CLK1_1(GND),
.CLK1EN_0(clk1_sig_en0),
.CLK1EN_1(GND),
.CLK2_0(clk2_sig0),
.CLK2_1(GND),
.CLK1S_0(clk1_sig_sel0),
.CLK1S_1(GND),
.CLK2S_0(clk2_sig_sel0),
.CLK2S_1(GND),
.CLK2EN_0(clk2_sig_en0),
.CLK2EN_1(GND),
.CONCAT_EN_0(GND),
.CONCAT_EN_1(GND),
.CS1_0(fifo_clk1_flush_sig0),
.CS1_1(GND),
.CS2_0(fifo_clk2_flush_sig0),
.CS2_1(GND),
.DIR_0(Fifo_Dir),
.DIR_1(GND),
.FIFO_EN_0(VCC),
.FIFO_EN_1(GND),
.P1_0(p1_sig0),
.P1_1(GND),
.P2_0(p2_sig0),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(sync_fifo0),
.SYNC_FIFO_1(GND),
.WD_1({18{GND}}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1({GND, GND}),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1({GND, GND}),
.WEN1_0({GND, GND}),
.WEN1_1({GND, GND}),
.Almost_Empty_0(Almost_Empty),
.Almost_Empty_1(),
.Almost_Full_0(Almost_Full),
.Almost_Full_1(),
.POP_FLAG_0(POP_FLAG),
.POP_FLAG_1(),
.PUSH_FLAG_0(PUSH_FLAG),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1(),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
assign DOUT[data_width_int-1 : 0] = out_reg0[data_width_int-1 : 0];
endmodule
module FIFO_16K_BLK (
DIN,
Fifo_Push_Flush,
Fifo_Pop_Flush,
PUSH,
POP,
Push_Clk,
Pop_Clk,
Push_Clk_En,
Pop_Clk_En,
Fifo_Dir,
Async_Flush,
Almost_Full,
Almost_Empty,
PUSH_FLAG,
POP_FLAG,
DOUT
);
parameter data_depth_int = 512, data_width_int = 36, reg_rd_int = 0, sync_fifo_int = 0;
input Fifo_Push_Flush, Fifo_Pop_Flush;
input Push_Clk, Pop_Clk;
input PUSH, POP;
input [data_width_int-1:0] DIN;
input Push_Clk_En, Pop_Clk_En, Fifo_Dir, Async_Flush;
output [data_width_int-1:0] DOUT;
output [3:0] PUSH_FLAG, POP_FLAG;
output Almost_Full, Almost_Empty;
wire LS, DS, SD, LS_RB1, DS_RB1, SD_RB1;
wire VCC, GND;
wire [10:0] addr_wr, addr_rd;
wire clk1_sig0, clk2_sig0, clk1_sig_en0, clk2_sig_en0, fifo_clk1_flush_sig0, fifo_clk2_flush_sig0, p1_sig0, p2_sig0,clk1_sig_sel0,clk2_sig_sel0;
wire reg_rd0, sync_fifo0;
wire [31:0] in_reg0;
wire [31:0] out_reg0;
wire [ 1:0] WS1_0;
wire [ 1:0] WS2_0;
wire Push_Clk0_Sel, Pop_Clk0_Sel;
wire Async_Flush_Sel0;
wire [3:0] out_par0;
wire [1:0] out_par1;
assign LS = 1\'b0;
assign DS = 1\'b0;
assign SD = 1\'b0;
assign LS_RB1 = 1\'b0;
assign DS_RB1 = 1\'b0;
assign SD_RB1 = 1\'b0;
assign VCC = 1\'b1;
assign GND = 1\'b0;
assign Push_Clk0_Sel \t= 1\'b0;
assign Pop_Clk0_Sel \t= 1\'b0;
assign Async_Flush_Sel0 = 1\'b0;
assign reg_rd0 = reg_rd_int;
assign sync_fifo0 = sync_fifo_int;
assign addr_wr=11\'b00000000000;
assign addr_rd=11\'b00000000000;
assign clk1_sig0 = Fifo_Dir ? Pop_Clk : Push_Clk;
assign clk2_sig0 = Fifo_Dir ? Push_Clk : Pop_Clk ;
assign clk1_sig_en0 = Fifo_Dir ? Pop_Clk_En : Push_Clk_En;
assign clk2_sig_en0 = Fifo_Dir ? Push_Clk_En : Pop_Clk_En ;
assign clk1_sig_sel0 = Push_Clk0_Sel;
assign clk2_sig_sel0 = Pop_Clk0_Sel ;
assign fifo_clk1_flush_sig0 = Fifo_Dir ? Fifo_Pop_Flush : Fifo_Push_Flush;
assign fifo_clk2_flush_sig0 = Fifo_Dir ? Fifo_Push_Flush : Fifo_Pop_Flush ;
assign p1_sig0 = Fifo_Dir ? POP : PUSH;
assign p2_sig0 = Fifo_Dir ? PUSH : POP ;
generate
if (data_width_int == 32) begin
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end else if (data_width_int > 8 && data_width_int < 32) begin
assign in_reg0[31:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end else if (data_width_int <= 8) begin
assign in_reg0[31:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end
if (data_width_int <= 8) begin
assign WS1_0 = 2\'b00;
assign WS2_0 = 2\'b00;
end else if (data_width_int > 8 && data_width_int <= 16) begin
assign WS1_0 = 2\'b01;
assign WS2_0 = 2\'b01;
end else if (data_width_int > 16) begin
assign WS1_0 = 2\'b10;
assign WS2_0 = 2\'b10;
end
if (data_width_int <= 16) begin
ram8k_2x1_cell_macro #(
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
) U1 (
.A1_0(addr_wr),
.A1_1(addr_wr),
.A2_0(addr_rd),
.A2_1(addr_rd),
.ASYNC_FLUSH_0(Async_Flush),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(Async_Flush_Sel0),
.ASYNC_FLUSH_S1(Async_Flush_Sel0),
.CLK1_0(clk1_sig0),
.CLK1_1(clk1_sig0),
.CLK1EN_0(clk1_sig_en0),
.CLK1EN_1(clk1_sig_en0),
.CLK2_0(clk2_sig0),
.CLK2_1(clk2_sig0),
.CLK1S_0(clk1_sig_sel0),
.CLK1S_1(clk1_sig_sel0),
.CLK2S_0(clk2_sig_sel0),
.CLK2S_1(clk2_sig_sel0),
.CLK2EN_0(clk2_sig_en0),
.CLK2EN_1(clk2_sig_en0),
.CONCAT_EN_0(VCC),
.CONCAT_EN_1(GND),
.CS1_0(fifo_clk1_flush_sig0),
.CS1_1(GND),
.CS2_0(fifo_clk2_flush_sig0),
.CS2_1(GND),
.DIR_0(Fifo_Dir),
.DIR_1(GND),
.FIFO_EN_0(VCC),
.FIFO_EN_1(GND),
.P1_0(p1_sig0),
.P1_1(GND),
.P2_0(p2_sig0),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(sync_fifo0),
.SYNC_FIFO_1(GND),
.WD_1({18{GND}}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1({GND, GND}),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1({GND, GND}),
.WEN1_0({GND, GND}),
.WEN1_1({GND, GND}),
.Almost_Empty_0(Almost_Empty),
.Almost_Empty_1(),
.Almost_Full_0(Almost_Full),
.Almost_Full_1(),
.POP_FLAG_0(POP_FLAG),
.POP_FLAG_1(),
.PUSH_FLAG_0(PUSH_FLAG),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1(),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
end else if (data_width_int > 16) begin
ram8k_2x1_cell_macro #(
.data_width_int(data_width_int),
.data_depth_int(data_depth_int)
) U2 (
.A1_0(addr_wr),
.A1_1(addr_wr),
.A2_0(addr_rd),
.A2_1(addr_rd),
.ASYNC_FLUSH_0(Async_Flush),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(Async_Flush_Sel0),
.ASYNC_FLUSH_S1(Async_Flush_Sel0),
.CLK1_0(clk1_sig0),
.CLK1_1(clk1_sig0),
.CLK1EN_0(clk1_sig_en0),
.CLK1EN_1(clk1_sig_en0),
.CLK2_0(clk2_sig0),
.CLK2_1(clk2_sig0),
.CLK1S_0(clk1_sig_sel0),
.CLK1S_1(clk1_sig_sel0),
.CLK2S_0(clk2_sig_sel0),
.CLK2S_1(clk2_sig_sel0),
.CLK2EN_0(clk2_sig_en0),
.CLK2EN_1(clk2_sig_en0),
.CONCAT_EN_0(VCC),
.CONCAT_EN_1(GND),
.CS1_0(fifo_clk1_flush_sig0),
.CS1_1(GND),
.CS2_0(fifo_clk2_flush_sig0),
.CS2_1(GND),
.DIR_0(Fifo_Dir),
.DIR_1(GND),
.FIFO_EN_0(VCC),
.FIFO_EN_1(GND),
.P1_0(p1_sig0),
.P1_1(GND),
.P2_0(p2_sig0),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(sync_fifo0),
.SYNC_FIFO_1(GND),
.WD_1({1\'b0, in_reg0[31:24], 1\'b0, in_reg0[23:16]}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1({GND, GND}),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1({GND, GND}),
.WEN1_0({GND, GND}),
.WEN1_1({GND, GND}),
.Almost_Empty_0(Almost_Empty),
.Almost_Empty_1(),
.Almost_Full_0(Almost_Full),
.Almost_Full_1(),
.POP_FLAG_0(POP_FLAG),
.POP_FLAG_1(),
.PUSH_FLAG_0(PUSH_FLAG),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1({out_par0[3], out_reg0[31:24], out_par0[2], out_reg0[23:16]}),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
end
endgenerate
assign DOUT[data_width_int-1 : 0] = out_reg0[data_width_int-1 : 0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module my_dff (
input d,
clk,
output reg q
);
always @(posedge clk) q <= d;
endmodule
module my_top (
inout wire pad,
input wire i,
input wire t,
output wire o,
input wire clk
);
wire i_r;
wire t_r;
wire o_r;
// IOB
assign pad = (t_r) ? i_r : 1\'bz;
assign o_r = pad;
// DFFs
my_dff dff_i (
i,
clk,
i_r
);
my_dff dff_t (
t,
clk,
t_r
);
my_dff dff_o (
o_r,
clk,
o
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`timescale 1ns / 10ps
module ahb_gen_bfm (
// AHB Slave Interface to AHB Bus Matrix
//
A2F_HCLK,
A2F_HRESET,
A2F_HADDRS,
A2F_HSEL,
A2F_HTRANSS,
A2F_HSIZES,
A2F_HWRITES,
A2F_HREADYS,
A2F_HWDATAS,
A2F_HREADYOUTS,
A2F_HRESPS,
A2F_HRDATAS
);
//------Port Parameters----------------
//
parameter ADDRWIDTH = 32;
parameter DATAWIDTH = 32;
//
// Define the default address between transfers
//
parameter DEFAULT_AHB_ADDRESS = {(ADDRWIDTH) {1\'b1}};
//
// Define the standard delay from clock
//
parameter STD_CLK_DLY = 2;
//
// Define Debug Message Controls
//
parameter ENABLE_AHB_REG_WR_DEBUG_MSG = 1\'b1;
parameter ENABLE_AHB_REG_RD_DEBUG_MSG = 1\'b1;
//
// Define the size of the message arrays
//
parameter TEST_MSG_ARRAY_SIZE = (64 * 8);
//------Port Signals-------------------
//
// AHB connection to master
//
input A2F_HCLK;
input A2F_HRESET;
output [ADDRWIDTH-1:0] A2F_HADDRS;
output A2F_HSEL;
output [1:0] A2F_HTRANSS;
output [2:0] A2F_HSIZES;
output A2F_HWRITES;
output A2F_HREADYS;
output [DATAWIDTH-1:0] A2F_HWDATAS;
input A2F_HREADYOUTS;
input A2F_HRESPS;
input [DATAWIDTH-1:0] A2F_HRDATAS;
wire A2F_HCLK;
wire A2F_HRESET;
reg [ ADDRWIDTH-1:0] A2F_HADDRS;
reg A2F_HSEL;
reg [ 1:0] A2F_HTRANSS;
reg [ 2:0] A2F_HSIZES;
reg A2F_HWRITES;
reg A2F_HREADYS;
reg [ DATAWIDTH-1:0] A2F_HWDATAS;
wire A2F_HREADYOUTS;
wire A2F_HRESPS;
wire [ DATAWIDTH-1:0] A2F_HRDATAS;
//------Define Parameters--------------
//
//
// None at this time
//
//------Internal Signals---------------
//
//\tDefine internal signals
//
reg [TEST_MSG_ARRAY_SIZE-1:0] ahb_bfm_msg1; // Bus used for depositing test messages in ASCI
reg [TEST_MSG_ARRAY_SIZE-1:0] ahb_bfm_msg2; // Bus used for depositing test messages in ASCI
reg [TEST_MSG_ARRAY_SIZE-1:0] ahb_bfm_msg3; // Bus used for depositing test messages in ASCI
reg [TEST_MSG_ARRAY_SIZE-1:0] ahb_bfm_msg4; // Bus used for depositing test messages in ASCI
reg [TEST_MSG_ARRAY_SIZE-1:0] ahb_bfm_msg5; // Bus used for depositing test messages in ASCI
reg [TEST_MSG_ARRAY_SIZE-1:0] ahb_bfm_msg6; // Bus used for depositing test messages in ASCI
//------Logic Operations---------------
//
// Define the intial state of key signals
//
initial begin
A2F_HADDRS <= DEFAULT_AHB_ADDRESS; // Default Address
A2F_HSEL <= 1\'b0; // Bridge not selected
A2F_HTRANSS <= 2\'h0; // "IDLE" State
A2F_HSIZES <= 3\'h0; // "Byte" Transfer Size
A2F_HWRITES <= 1\'b0; // "Read" operation
A2F_HREADYS <= 1\'b0; // Slave is not ready
A2F_HWDATAS <= {(DATAWIDTH) {1\'b0}}; // Write Data Value of "0"
ahb_bfm_msg1 <= "NO ACTIVITY"; // Bus used for depositing test messages in ASCI
ahb_bfm_msg2 <= "NO ACTIVITY"; // Bus used for depositing test messages in ASCI
ahb_bfm_msg3 <= "NO ACTIVITY"; // Bus used for depositing test messages in ASCI
ahb_bfm_msg4 <= "NO ACTIVITY"; // Bus used for depositing test messages in ASCI
ahb_bfm_msg5 <= "NO ACTIVITY"; // Bus used for depositiog test messages in ASCI
ahb_bfm_msg6 <= "NO ACTIVITY"; // Bus used for depositiog test messages in ASCI
end
//------Instantiate Modules------------
//
//
// None at this time
//
//------BFM Routines-------------------
//
`ifndef YOSYS
task ahb_read_al4s3b_fabric;
input [ADDRWIDTH-1:0] TARGET_ADDRESS; // Address to be written on the SPI bus
input [2:0] TARGET_XFR_SIZE; // Transfer Size for AHB bus
output [DATAWIDTH-1:0] TARGET_DATA; // Data to be written on the SPI bus
reg [DATAWIDTH-1:0] read_data;
integer i, j, k;
begin
// Read Command Bit
//
@(posedge A2F_HCLK) #STD_CLK_DLY;
// Issue Diagnostic Messages
//
ahb_bfm_msg1 = "AHB Single Read";
ahb_bfm_msg2 = "Address Phase";
ahb_bfm_msg3 = "SEQ";
A2F_HADDRS = TARGET_ADDRESS; // Transfer Address
// Define the Transfer Request
//
// Transfer decode of: A2F_HTRANS[1] A2F_HTRANS[0] Description
// ------------- ------------- ------------------------------------
// 0 0 IDLE (No Transfer)
// 0 1 BUSY (No Transfer)
// 1 0 NONSEQ (Do Transfer)
// 1 1 SEQ (Do Transfer)
//
// Transfer decode of: A2F_HREADYS Description
// ----------- ------------------------------------
// 0 Slave is not ready (No Transfer)
// 1 Slave is ready (Do Transfer)
//
A2F_HSEL = 1\'b1; // Bridge selected
A2F_HREADYS = 1\'b1; // Slave is ready
A2F_HTRANSS = 2\'h2; // "NONSEQ" State
//
// Define "Transfer Size Encoding" is based on the following:
//
// HSIZE[2] HSIZE[1] HSIZE[0] Bits Description
// -------- -------- -------- ---- -----------
// 0 0 0 8 Byte
// 0 0 1 16 Halfword
// 0 1 0 32 Word
// 0 1 1 64 Doublword
// 1 0 0 128 4-word line
// 1 0 1 256 8-word line
// 1 1 0 512 -
// 1 1 1 1024 -
//
// The fabric design only supports up to 32 bits at a time.
//
A2F_HSIZES = TARGET_XFR_SIZE; // Transfer Size
A2F_HWRITES = 1\'b0; // "Read" operation
A2F_HWDATAS = {(DATAWIDTH) {1\'b0}}; // Write Data Value of "0"
//
// Wait for next clock to sampe the slave\'s response
//
@(posedge A2F_HCLK) #STD_CLK_DLY;
ahb_bfm_msg2 = "Data Phase";
ahb_bfm_msg3 = "IDLE";
ahb_bfm_msg4 = "Waiting for Slave";
// Set the next transfer cycle to "IDLE"
A2F_HADDRS = DEFAULT_AHB_ADDRESS; // Default Address
A2F_HSEL = 1\'b0; // Bridge not selected
A2F_HTRANSS = 2\'h0; // "IDLE" State
A2F_HSIZES = 3\'h0; // "Byte" Transfer Size
//
// Check if the slave has returend data
//
while (A2F_HREADYOUTS == 1\'b0) begin
@(posedge A2F_HCLK) #STD_CLK_DLY;
end
A2F_HREADYS = 1\'b0; // Slave is not ready
TARGET_DATA = A2F_HRDATAS; // Read slave data value
// Clear Diagnostic Messages
//
ahb_bfm_msg1 <= "NO ACTIVITY";
ahb_bfm_msg2 <= "NO ACTIVITY";
ahb_bfm_msg3 <= "NO ACTIVITY";
ahb_bfm_msg4 <= "NO ACTIVITY";
ahb_bfm_msg5 <= "NO ACTIVITY";
ahb_bfm_msg6 <= "NO ACTIVITY";
end
endtask
task ahb_write_al4s3b_fabric;
input [ADDRWIDTH-1:0] TARGET_ADDRESS; // Address to be written on the SPI bus
input [2:0] TARGET_XFR_SIZE; // Transfer Size for AHB bus
input [DATAWIDTH-1:0] TARGET_DATA; // Data to be written on the SPI bus
reg [DATAWIDTH-1:0] read_data;
integer i, j, k;
begin
// Read Command Bit
//
@(posedge A2F_HCLK) #STD_CLK_DLY;
// Issue Diagnostic Messages
//
ahb_bfm_msg1 = "AHB Single Write";
ahb_bfm_msg2 = "Address Phase";
ahb_bfm_msg3 = "SEQ";
A2F_HADDRS = TARGET_ADDRESS; // Transfer Address
// Define the Transfer Request
//
// Transfer decode of: A2F_HTRANS[1] A2F_HTRANS[0] Description
// ------------- ------------- ------------------------------------
// 0 0 IDLE (No Transfer)
// 0 1 BUSY (No Transfer)
// 1 0 NONSEQ (Do Transfer)
// 1 1 SEQ (Do Transfer)
//
// Transfer decode of: A2F_HREADYS Description
// ----------- ------------------------------------
// 0 Slave is not ready (No Transfer)
// 1 Slave is ready (Do Transfer)
//
A2F_HSEL = 1\'b1; // Bridge selected
A2F_HREADYS = 1\'b1; // Slave is ready
A2F_HTRANSS = 2\'h2; // "NONSEQ" State
//
// Define "Transfer Size Encoding" is based on the following:
//
// HSIZE[2] HSIZE[1] HSIZE[0] Bits Description
// -------- -------- -------- ---- -----------
// 0 0 0 8 Byte
// 0 0 1 16 Halfword
// 0 1 0 32 Word
// 0 1 1 64 Doublword
// 1 0 0 128 4-word line
// 1 0 1 256 8-word line
// 1 1 0 512 -
// 1 1 1 1024 -
//
// The fabric design only supports up to 32 bits at a time.
//
A2F_HSIZES = TARGET_XFR_SIZE; // Transfer Size
A2F_HWRITES = 1\'b1; // "Write" operation
A2F_HWDATAS = {(DATAWIDTH) {1\'b0}}; // Write Data Value of "0"
//
// Wait for next clock to sampe the slave\'s response
//
@(posedge A2F_HCLK) #STD_CLK_DLY;
ahb_bfm_msg2 = "Data Phase";
ahb_bfm_msg3 = "IDLE";
ahb_bfm_msg4 = "Waiting for Slave";
// Set the next transfer cycle to "IDLE"
A2F_HADDRS = DEFAULT_AHB_ADDRESS; // Default Address
A2F_HSEL = 1\'b0; // Bridge not selected
A2F_HTRANSS = 2\'h0; // "IDLE" State
A2F_HSIZES = 3\'h0; // "Byte" Transfer Size
A2F_HWDATAS = TARGET_DATA; // Write From test routine
A2F_HWRITES = 1\'b0; // "Read" operation
//
// Check if the slave has returend data
//
while (A2F_HREADYOUTS == 1\'b0) begin
@(posedge A2F_HCLK) #STD_CLK_DLY;
end
A2F_HREADYS = 1\'b0; // Slave is not ready
TARGET_DATA = A2F_HRDATAS; // Read slave data value
// Clear Diagnostic Messages
//
ahb_bfm_msg1 <= "NO ACTIVITY";
ahb_bfm_msg2 <= "NO ACTIVITY";
ahb_bfm_msg3 <= "NO ACTIVITY";
ahb_bfm_msg4 <= "NO ACTIVITY";
ahb_bfm_msg5 <= "NO ACTIVITY";
ahb_bfm_msg6 <= "NO ACTIVITY";
end
endtask
task ahb_read_word_al4s3b_fabric;
input [ADDRWIDTH-1:0] TARGET_ADDRESS; // Address to be written on the SPI bus
output [DATAWIDTH-1:0] TARGET_DATA; // Data to be written on the SPI bus
reg [DATAWIDTH-1:0] read_data;
integer i, j, k;
begin
// Read Command Bit
//
wait(A2F_HRESET == 0);
@(posedge A2F_HCLK) #STD_CLK_DLY;
// Issue Diagnostic Messages
//
ahb_bfm_msg1 = "AHB Single Read";
ahb_bfm_msg2 = "Address Phase";
ahb_bfm_msg3 = "SEQ";
A2F_HADDRS = TARGET_ADDRESS; // Transfer Address
// Define the Transfer Request
//
// Transfer decode of: A2F_HTRANS[1] A2F_HTRANS[0] Description
// ------------- ------------- ------------------------------------
// 0 0 IDLE (No Transfer)
// 0 1 BUSY (No Transfer)
// 1 0 NONSEQ (Do Transfer)
// 1 1 SEQ (Do Transfer)
//
// Transfer decode of: A2F_HREADYS Description
// ----------- ------------------------------------
// 0 Slave is not ready (No Transfer)
// 1 Slave is ready (Do Transfer)
//
A2F_HSEL = 1\'b1; // Bridge selected
A2F_HREADYS = 1\'b1; // Slave is ready
A2F_HTRANSS = 2\'h2; // "NONSEQ" State
//
// Define "Transfer Size Encoding" is based on the following:
//
// HSIZE[2] HSIZE[1] HSIZE[0] Bits Description
// -------- -------- -------- ---- -----------
// 0 0 0 8 Byte
// 0 0 1 16 Halfword
// 0 1 0 32 Word
// 0 1 1 64 Doublword
// 1 0 0 128 4-word line
// 1 0 1 256 8-word line
// 1 1 0 512 -
// 1 1 1 1024 -
//
// The fabric design only supports up to 32 bits at a time.
//
A2F_HSIZES = 3\'b010; // Transfer Size
A2F_HWRITES = 1\'b0; // "Read" operation
A2F_HWDATAS = {(DATAWIDTH) {1\'b0}}; // Write Data Value of "0"
//
// Wait for next clock to sampe the slave\'s response
//
@(posedge A2F_HCLK) #STD_CLK_DLY;
ahb_bfm_msg2 = "Data Phase";
ahb_bfm_msg3 = "IDLE";
ahb_bfm_msg4 = "Waiting for Slave";
// Set the next transfer cycle to "IDLE"
A2F_HADDRS = DEFAULT_AHB_ADDRESS; // Default Address
A2F_HSEL = 1\'b0; // Bridge not selected
A2F_HTRANSS = 2\'h0; // "IDLE" State
A2F_HSIZES = 3\'h0; // "Byte" Transfer Size
//
// Check if the slave has returend data
//
while (A2F_HREADYOUTS == 1\'b0) begin
@(posedge A2F_HCLK) #STD_CLK_DLY;
end
A2F_HREADYS = 1\'b0; // Slave is not ready
TARGET_DATA = A2F_HRDATAS; // Read slave data value
// Clear Diagnostic Messages
//
ahb_bfm_msg1 <= "NO ACTIVITY";
ahb_bfm_msg2 <= "NO ACTIVITY";
ahb_bfm_msg3 <= "NO ACTIVITY";
ahb_bfm_msg4 <= "NO ACTIVITY";
ahb_bfm_msg5 <= "NO ACTIVITY";
ahb_bfm_msg6 <= "NO ACTIVITY";
end
endtask
task ahb_write_word_al4s3b_fabric;
input [ADDRWIDTH-1:0] TARGET_ADDRESS; // Address to be written on the SPI bus
input [DATAWIDTH-1:0] TARGET_DATA; // Data to be written on the SPI bus
reg [DATAWIDTH-1:0] read_data;
integer i, j, k;
begin
// Read Command Bit
//
wait(A2F_HRESET == 0);
@(posedge A2F_HCLK) #STD_CLK_DLY;
// Issue Diagnostic Messages
//
ahb_bfm_msg1 = "AHB Single Write";
ahb_bfm_msg2 = "Address Phase";
ahb_bfm_msg3 = "SEQ";
A2F_HADDRS = TARGET_ADDRESS; // Transfer Address
// Define the Transfer Request
//
// Transfer decode of: A2F_HTRANS[1] A2F_HTRANS[0] Description
// ------------- ------------- ------------------------------------
// 0 0 IDLE (No Transfer)
// 0 1 BUSY (No Transfer)
// 1 0 NONSEQ (Do Transfer)
// 1 1 SEQ (Do Transfer)
//
// Transfer decode of: A2F_HREADYS Description
// ----------- ------------------------------------
// 0 Slave is not ready (No Transfer)
// 1 Slave is ready (Do Transfer)
//
A2F_HSEL = 1\'b1; // Bridge selected
A2F_HREADYS = 1\'b1; // Slave is ready
A2F_HTRANSS = 2\'h2; // "NONSEQ" State
//
// Define "Transfer Size Encoding" is based on the following:
//
// HSIZE[2] HSIZE[1] HSIZE[0] Bits Description
// -------- -------- -------- ---- -----------
// 0 0 0 8 Byte
// 0 0 1 16 Halfword
// 0 1 0 32 Word
// 0 1 1 64 Doublword
// 1 0 0 128 4-word line
// 1 0 1 256 8-word line
// 1 1 0 512 -
// 1 1 1 1024 -
//
// The fabric design only supports up to 32 bits at a time.
//
A2F_HSIZES = 3\'b010; // Transfer Size
A2F_HWRITES = 1\'b1; // "Write" operation
A2F_HWDATAS = {(DATAWIDTH) {1\'b0}}; // Write Data Value of "0"
//
// Wait for next clock to sampe the slave\'s response
//
@(posedge A2F_HCLK) #STD_CLK_DLY;
ahb_bfm_msg2 = "Data Phase";
ahb_bfm_msg3 = "IDLE";
ahb_bfm_msg4 = "Waiting for Slave";
// Set the next transfer cycle to "IDLE"
A2F_HADDRS = DEFAULT_AHB_ADDRESS; // Default Address
A2F_HSEL = 1\'b0; // Bridge not selected
A2F_HTRANSS = 2\'h0; // "IDLE" State
A2F_HSIZES = 3\'h0; // "Byte" Transfer Size
A2F_HWDATAS = TARGET_DATA; // Write From test routine
A2F_HWRITES = 1\'b0; // "Read" operation
//
// Check if the slave has returend data
//
while (A2F_HREADYOUTS == 1\'b0) begin
@(posedge A2F_HCLK) #STD_CLK_DLY;
end
A2F_HREADYS = 1\'b0; // Slave is not ready
TARGET_DATA = A2F_HRDATAS; // Read slave data value
// Clear Diagnostic Messages
//
ahb_bfm_msg1 <= "NO ACTIVITY";
ahb_bfm_msg2 <= "NO ACTIVITY";
ahb_bfm_msg3 <= "NO ACTIVITY";
ahb_bfm_msg4 <= "NO ACTIVITY";
ahb_bfm_msg5 <= "NO ACTIVITY";
ahb_bfm_msg6 <= "NO ACTIVITY";
//$stop();
end
endtask
task ahb_write_al4s3b_fabric_mod;
input [ADDRWIDTH-1:0] TARGET_ADDRESS; // Address to be written on the SPI bus
input [2:0] TARGET_XFR_SIZE; // Transfer Size for AHB bus
input [DATAWIDTH-1:0] TARGET_DATA; // Data to be written on the SPI bus
reg [DATAWIDTH-1:0] read_data;
integer i, j, k;
begin
// Read Command Bit
//
@(posedge A2F_HCLK) #STD_CLK_DLY;
// Issue Diagnostic Messages
//
ahb_bfm_msg1 = "AHB Single Write";
ahb_bfm_msg2 = "Address Phase";
ahb_bfm_msg3 = "SEQ";
//A2F_HADDRS = TARGET_ADDRESS; // Transfer Address
A2F_HADDRS = {
TARGET_ADDRESS[ADDRWIDTH-1:11], (TARGET_ADDRESS[10:0] << 2)
}; // Transfer Address
// Define the Transfer Request
//
// Transfer decode of: A2F_HTRANS[1] A2F_HTRANS[0] Description
// ------------- ------------- ------------------------------------
// 0 0 IDLE (No Transfer)
// 0 1 BUSY (No Transfer)
// 1 0 NONSEQ (Do Transfer)
// 1 1 SEQ (Do Transfer)
//
// Transfer decode of: A2F_HREADYS Description
// ----------- ------------------------------------
// 0 Slave is not ready (No Transfer)
// 1 Slave is ready (Do Transfer)
//
A2F_HSEL = 1\'b1; // Bridge selected
A2F_HREADYS = 1\'b1; // Slave is ready
A2F_HTRANSS = 2\'h2; // "NONSEQ" State
//
// Define "Transfer Size Encoding" is based on the following:
//
// HSIZE[2] HSIZE[1] HSIZE[0] Bits Description
// -------- -------- -------- ---- -----------
// 0 0 0 8 Byte
// 0 0 1 16 Halfword
// 0 1 0 32 Word
// 0 1 1 64 Doublword
// 1 0 0 128 4-word line
// 1 0 1 256 8-word line
// 1 1 0 512 -
// 1 1 1 1024 -
//
// The fabric design only supports up to 32 bits at a time.
//
A2F_HSIZES = TARGET_XFR_SIZE; // Transfer Size
A2F_HWRITES = 1\'b1; // "Write" operation
A2F_HWDATAS = {(DATAWIDTH) {1\'b0}}; // Write Data Value of "0"
//
// Wait for next clock to sampe the slave\'s response
//
@(posedge A2F_HCLK) #STD_CLK_DLY;
ahb_bfm_msg2 = "Data Phase";
ahb_bfm_msg3 = "IDLE";
ahb_bfm_msg4 = "Waiting for Slave";
// Set the next transfer cycle to "IDLE"
A2F_HADDRS = DEFAULT_AHB_ADDRESS; // Default Address
A2F_HSEL = 1\'b0; // Bridge not selected
A2F_HTRANSS = 2\'h0; // "IDLE" State
A2F_HSIZES = 3\'h0; // "Byte" Transfer Size
A2F_HWDATAS = TARGET_DATA; // Write From test routine
A2F_HWRITES = 1\'b0; // "Read" operation
//
// Check if the slave has returend data
//
while (A2F_HREADYOUTS == 1\'b0) begin
@(posedge A2F_HCLK) #STD_CLK_DLY;
end
A2F_HREADYS = 1\'b0; // Slave is not ready
TARGET_DATA = A2F_HRDATAS; // Read slave data value
// Clear Diagnostic Messages
//
ahb_bfm_msg1 <= "NO ACTIVITY";
ahb_bfm_msg2 <= "NO ACTIVITY";
ahb_bfm_msg3 <= "NO ACTIVITY";
ahb_bfm_msg4 <= "NO ACTIVITY";
ahb_bfm_msg5 <= "NO ACTIVITY";
ahb_bfm_msg6 <= "NO ACTIVITY";
end
endtask
task ahb_read_al4s3b_fabric_mod;
input [ADDRWIDTH-1:0] TARGET_ADDRESS; // Address to be written on the SPI bus
input [2:0] TARGET_XFR_SIZE; // Transfer Size for AHB bus
output [DATAWIDTH-1:0] TARGET_DATA; // Data to be written on the SPI bus
reg [DATAWIDTH-1:0] read_data;
integer i, j, k;
begin
// Read Command Bit
//
@(posedge A2F_HCLK) #STD_CLK_DLY;
// Issue Diagnostic Messages
//
ahb_bfm_msg1 = "AHB Single Read";
ahb_bfm_msg2 = "Address Phase";
ahb_bfm_msg3 = "SEQ";
//A2F_HADDRS = TARGET_ADDRESS; // Transfer Address
A2F_HADDRS = {
TARGET_ADDRESS[ADDRWIDTH-1:11], (TARGET_ADDRESS[10:0] << 2)
}; // Transfer Address
// Define the Transfer Request
//
// Transfer decode of: A2F_HTRANS[1] A2F_HTRANS[0] Description
// ------------- ------------- ------------------------------------
// 0 0 IDLE (No Transfer)
// 0 1 BUSY (No Transfer)
// 1 0 NONSEQ (Do Transfer)
// 1 1 SEQ (Do Transfer)
//
// Transfer decode of: A2F_HREADYS Description
// ----------- ------------------------------------
// 0 Slave is not ready (No Transfer)
// 1 Slave is ready (Do Transfer)
//
A2F_HSEL = 1\'b1; // Bridge selected
A2F_HREADYS = 1\'b1; // Slave is ready
A2F_HTRANSS = 2\'h2; // "NONSEQ" State
//
// Define "Transfer Size Encoding" is based on the following:
//
// HSIZE[2] HSIZE[1] HSIZE[0] Bits Description
// -------- -------- -------- ---- -----------
// 0 0 0 8 Byte
// 0 0 1 16 Halfword
// 0 1 0 32 Word
// 0 1 1 64 Doublword
// 1 0 0 128 4-word line
// 1 0 1 256 8-word line
// 1 1 0 512 -
// 1 1 1 1024 -
//
// The fabric design only supports up to 32 bits at a time.
//
A2F_HSIZES = TARGET_XFR_SIZE; // Transfer Size
A2F_HWRITES = 1\'b0; // "Read" operation
A2F_HWDATAS = {(DATAWIDTH) {1\'b0}}; // Write Data Value of "0"
//
// Wait for next clock to sampe the slave\'s response
//
@(posedge A2F_HCLK) #STD_CLK_DLY;
ahb_bfm_msg2 = "Data Phase";
ahb_bfm_msg3 = "IDLE";
ahb_bfm_msg4 = "Waiting for Slave";
// Set the next transfer cycle to "IDLE"
A2F_HADDRS = DEFAULT_AHB_ADDRESS; // Default Address
A2F_HSEL = 1\'b0; // Bridge not selected
A2F_HTRANSS = 2\'h0; // "IDLE" State
A2F_HSIZES = 3\'h0; // "Byte" Transfer Size
//
// Check if the slave has returend data
//
while (A2F_HREADYOUTS == 1\'b0) begin
@(posedge A2F_HCLK) #STD_CLK_DLY;
end
A2F_HREADYS = 1\'b0; // Slave is not ready
TARGET_DATA = A2F_HRDATAS; // Read slave data value
// Clear Diagnostic Messages
//
ahb_bfm_msg1 <= "NO ACTIVITY";
ahb_bfm_msg2 <= "NO ACTIVITY";
ahb_bfm_msg3 <= "NO ACTIVITY";
ahb_bfm_msg4 <= "NO ACTIVITY";
ahb_bfm_msg5 <= "NO ACTIVITY";
ahb_bfm_msg6 <= "NO ACTIVITY";
end
endtask
`endif
endmodule
`timescale 1ns / 10ps
module oscillator_s1 (
OSC_CLK_EN,
OSC_CLK
);
//\tDefine the oscillator\'s frequency
//
//\tNote:\tThe parameter above assumes that values are calculated in units of nS.
//
parameter T_CYCLE_CLK = (1000.0 / 19.2);
input OSC_CLK_EN;
output OSC_CLK;
wire OSC_CLK_EN;
wire OSC_CLK;
reg osc_int_clk;
//\tDefine the output enable
//
assign OSC_CLK = OSC_CLK_EN ? osc_int_clk : 1\'bZ;
// Define the clock oscillator section
//
initial begin
osc_int_clk = 0; // Intialize the clock at time 0ns.
`ifndef YOSYS
forever\t\t\t\t// Generate a clock with an expected frequency.
\tbegin
#(T_CYCLE_CLK / 2) osc_int_clk = 1;
#(T_CYCLE_CLK / 2) osc_int_clk = 0;
end
`endif
end
endmodule
`timescale 1ns / 10ps
module sdma_bfm (
// SDMA Interface Signals
//
sdma_req_i,
sdma_sreq_i,
sdma_done_o,
sdma_active_o
);
input [3:0] sdma_req_i;
input [3:0] sdma_sreq_i;
output [3:0] sdma_done_o;
output [3:0] sdma_active_o;
reg [3:0] sdma_done_sig;
reg [3:0] sdma_active_sig;
assign sdma_done_o = sdma_done_sig;
assign sdma_active_o = sdma_active_sig;
initial begin
sdma_done_sig <= 4\'h0;
sdma_active_sig <= 4\'h0;
end
`ifndef YOSYS
task drive_dma_active;
input [3:0] dma_active_i;
begin
sdma_active_sig <= dma_active_i;
#100;
//sdma_active_sig <= 4\'h0;
end
endtask
`endif
endmodule
`timescale 1ns / 10ps
module ahb2fb_asynbrig_if (
A2F_HCLK, // clock
A2F_HRESET, // reset
// AHB connection to master
//
A2F_HSEL,
A2F_HADDRS,
A2F_HTRANSS,
A2F_HSIZES,
A2F_HWRITES,
A2F_HREADYS,
A2F_HREADYOUTS,
A2F_HRESPS,
// Fabric Interface
//
AHB_ASYNC_ADDR_O,
AHB_ASYNC_READ_EN_O,
AHB_ASYNC_WRITE_EN_O,
AHB_ASYNC_BYTE_STROBE_O,
AHB_ASYNC_STB_TOGGLE_O,
FABRIC_ASYNC_ACK_TOGGLE_I
);
//-----Port Parameters-----------------
//
parameter DATAWIDTH = 32;
parameter APERWIDTH = 17;
parameter STATE_WIDTH = 1;
parameter AHB_ASYNC_IDLE = 0;
parameter AHB_ASYNC_WAIT = 1;
//-----Port Signals--------------------
//
//------------------------------------------
// AHB connection to master
//
input A2F_HCLK; // clock
input A2F_HRESET; // reset
input [APERWIDTH-1:0] A2F_HADDRS;
input A2F_HSEL;
input [1:0] A2F_HTRANSS;
input [2:0] A2F_HSIZES;
input A2F_HWRITES;
input A2F_HREADYS;
output A2F_HREADYOUTS;
output A2F_HRESPS;
//------------------------------------------
// Fabric Interface
//
output [APERWIDTH-1:0] AHB_ASYNC_ADDR_O;
output AHB_ASYNC_READ_EN_O;
output AHB_ASYNC_WRITE_EN_O;
output [3:0] AHB_ASYNC_BYTE_STROBE_O;
output AHB_ASYNC_STB_TOGGLE_O;
input FABRIC_ASYNC_ACK_TOGGLE_I;
//------------------------------------------
// AHB connection to master
//
wire A2F_HCLK; // clock
wire A2F_HRESET; // reset
wire [ APERWIDTH-1:0] A2F_HADDRS;
wire A2F_HSEL;
wire [ 1:0] A2F_HTRANSS;
wire [ 2:0] A2F_HSIZES;
wire A2F_HWRITES;
wire A2F_HREADYS;
reg A2F_HREADYOUTS;
reg A2F_HREADYOUTS_nxt;
wire A2F_HRESPS;
//------------------------------------------
// Fabric Interface
//
reg [ APERWIDTH-1:0] AHB_ASYNC_ADDR_O;
reg AHB_ASYNC_READ_EN_O;
reg AHB_ASYNC_WRITE_EN_O;
reg [ 3:0] AHB_ASYNC_BYTE_STROBE_O;
reg [ 3:0] AHB_ASYNC_BYTE_STROBE_O_nxt;
reg AHB_ASYNC_STB_TOGGLE_O;
reg AHB_ASYNC_STB_TOGGLE_O_nxt;
wire FABRIC_ASYNC_ACK_TOGGLE_I;
//------Define Parameters---------
//
//
// None at this time
//
//-----Internal Signals--------------------
//
wire trans_req; // transfer request
reg [STATE_WIDTH-1:0] ahb_to_fabric_state;
reg [STATE_WIDTH-1:0] ahb_to_fabric_state_nxt;
reg fabric_async_ack_toggle_i_1ff;
reg fabric_async_ack_toggle_i_2ff;
reg fabric_async_ack_toggle_i_3ff;
wire fabric_async_ack;
//------Logic Operations----------
//
// Define the Transfer Request
//
// Transfer decode of: A2F_HTRANS[1] A2F_HTRANS[0] Description
// ------------- ------------- ------------------------------------
// 0 0 IDLE (No Transfer)
// 0 1 BUSY (No Transfer)
// 1 0 NONSEQ (Do Transfer)
// 1 1 SEQ (Do Transfer)
//
// Transfer decode of: A2F_HREADYS Description
// ----------- ------------------------------------
// 0 Slave is not ready (No Transfer)
// 1 Slave is ready (Do Transfer)
//
assign trans_req = A2F_HSEL
\t & A2F_HREADYS
\t\t\t\t\t\t & A2F_HTRANSS[1]; // transfer request issued only in SEQ and NONSEQ status and slave is
// selected and last transfer finish
// Check for acknowldge from the fabric
//
// Note: The fabric is on a different and potentially asynchronous clock.
// Therefore, acknowledge is passed as a toggle signal.
//
assign fabric_async_ack = fabric_async_ack_toggle_i_2ff ^ fabric_async_ack_toggle_i_3ff;
// Issue transfer status
//
// Note: All transfers are considered to have completed successfully.
//
assign A2F_HRESPS = 1\'b0; // OKAY response from slave
// Address signal registering, to make the address and data active at the same cycle
//
always @(posedge A2F_HCLK or posedge A2F_HRESET) begin
if (A2F_HRESET) begin
ahb_to_fabric_state <= AHB_ASYNC_IDLE;
AHB_ASYNC_ADDR_O <= {(APERWIDTH) {1\'b0}}; //default address 0 is selected
AHB_ASYNC_READ_EN_O <= 1\'b0;
AHB_ASYNC_WRITE_EN_O <= 1\'b0;
AHB_ASYNC_BYTE_STROBE_O <= 4\'b0;
AHB_ASYNC_STB_TOGGLE_O <= 1\'b0;
fabric_async_ack_toggle_i_1ff <= 1\'b0;
fabric_async_ack_toggle_i_2ff <= 1\'b0;
fabric_async_ack_toggle_i_3ff <= 1\'b0;
A2F_HREADYOUTS <= 1\'b0;
end else begin
ahb_to_fabric_state <= ahb_to_fabric_state_nxt;
if (trans_req) begin
AHB_ASYNC_ADDR_O <= A2F_HADDRS[APERWIDTH-1:0];
AHB_ASYNC_READ_EN_O <= ~A2F_HWRITES;
AHB_ASYNC_WRITE_EN_O <= A2F_HWRITES;
AHB_ASYNC_BYTE_STROBE_O <= AHB_ASYNC_BYTE_STROBE_O_nxt;
end
AHB_ASYNC_STB_TOGGLE_O <= AHB_ASYNC_STB_TOGGLE_O_nxt;
fabric_async_ack_toggle_i_1ff <= FABRIC_ASYNC_ACK_TOGGLE_I;
fabric_async_ack_toggle_i_2ff <= fabric_async_ack_toggle_i_1ff;
fabric_async_ack_toggle_i_3ff <= fabric_async_ack_toggle_i_2ff;
A2F_HREADYOUTS <= A2F_HREADYOUTS_nxt;
end
end
// Byte Strobe Signal Decode
//
// Note: The "Transfer Size Encoding" is defined as follows:
//
// HSIZE[2] HSIZE[1] HSIZE[0] Bits Description
// -------- -------- -------- ---- -----------
// 0 0 0 8 Byte
// 0 0 1 16 Halfword
// 0 1 0 32 Word
// 0 1 1 64 Doublword
// 1 0 0 128 4-word line
// 1 0 1 256 8-word line
// 1 1 0 512 -
// 1 1 1 1024 -
//
// The fabric design only supports up to 32 bits at a time.
//
always @(A2F_HSIZES or A2F_HADDRS) begin
case (A2F_HSIZES)
3\'b000: //byte
begin
case (A2F_HADDRS[1:0])
2\'b00: AHB_ASYNC_BYTE_STROBE_O_nxt <= 4\'b0001;
2\'b01: AHB_ASYNC_BYTE_STROBE_O_nxt <= 4\'b0010;
2\'b10: AHB_ASYNC_BYTE_STROBE_O_nxt <= 4\'b0100;
2\'b11: AHB_ASYNC_BYTE_STROBE_O_nxt <= 4\'b1000;
default: AHB_ASYNC_BYTE_STROBE_O_nxt <= 4\'b0000;
endcase
end
3\'b001: //half word
begin
case (A2F_HADDRS[1])
1\'b0: AHB_ASYNC_BYTE_STROBE_O_nxt <= 4\'b0011;
1\'b1: AHB_ASYNC_BYTE_STROBE_O_nxt <= 4\'b1100;
default: AHB_ASYNC_BYTE_STROBE_O_nxt <= 4\'b0000;
endcase
end
default: AHB_ASYNC_BYTE_STROBE_O_nxt <= 4\'b1111; // default 32 bits, word
endcase
end
// Define the AHB Interface Statemachine
//
always @(trans_req or fabric_async_ack or AHB_ASYNC_STB_TOGGLE_O or ahb_to_fabric_state) begin
case (ahb_to_fabric_state)
AHB_ASYNC_IDLE: begin
case (trans_req)
1\'b0: // Wait for an AHB Transfer
begin
ahb_to_fabric_state_nxt <= AHB_ASYNC_IDLE;
A2F_HREADYOUTS_nxt <= 1\'b1;
AHB_ASYNC_STB_TOGGLE_O_nxt <= AHB_ASYNC_STB_TOGGLE_O;
end
1\'b1: // AHB Transfer Detected
begin
ahb_to_fabric_state_nxt <= AHB_ASYNC_WAIT;
A2F_HREADYOUTS_nxt <= 1\'b0;
AHB_ASYNC_STB_TOGGLE_O_nxt <= ~AHB_ASYNC_STB_TOGGLE_O;
end
endcase
end
AHB_ASYNC_WAIT: begin
AHB_ASYNC_STB_TOGGLE_O_nxt <= AHB_ASYNC_STB_TOGGLE_O;
case (fabric_async_ack)
1\'b0: // Wait for Acknowledge from Fabric Interface
begin
ahb_to_fabric_state_nxt <= AHB_ASYNC_WAIT;
A2F_HREADYOUTS_nxt <= 1\'b0;
end
1\'b1: // Received Acknowledge from Fabric Interface
begin
ahb_to_fabric_state_nxt <= AHB_ASYNC_IDLE;
A2F_HREADYOUTS_nxt <= 1\'b1;
end
endcase
end
default: begin
ahb_to_fabric_state_nxt <= AHB_ASYNC_IDLE;
A2F_HREADYOUTS_nxt <= 1\'b0;
AHB_ASYNC_STB_TOGGLE_O_nxt <= AHB_ASYNC_STB_TOGGLE_O;
end
endcase
end
endmodule
`timescale 1ns / 10ps
module fb2ahb_asynbrig_if (
A2F_HRDATAS,
// AHB Interface
//
AHB_ASYNC_READ_EN_I,
AHB_ASYNC_WRITE_EN_I,
AHB_ASYNC_BYTE_STROBE_I,
AHB_ASYNC_STB_TOGGLE_I,
// Fabric Interface
//
WB_CLK_I,
WB_RST_I,
WB_ACK_I,
WB_DAT_I,
WB_CYC_O,
WB_BYTE_STB_O,
WB_WE_O,
WB_RD_O,
WB_STB_O,
FABRIC_ASYNC_ACK_TOGGLE_O
);
//-----Port Parameters-----------------
//
parameter DATAWIDTH = 32;
parameter STATE_WIDTH = 1;
parameter FAB_ASYNC_IDLE = 0;
parameter FAB_ASYNC_WAIT = 1;
//-----Port Signals--------------------
//
//------------------------------------------
// AHB connection to master
//
output [DATAWIDTH-1:0] A2F_HRDATAS;
//------------------------------------------
// Fabric Interface
//
input AHB_ASYNC_READ_EN_I;
input AHB_ASYNC_WRITE_EN_I;
input [3:0] AHB_ASYNC_BYTE_STROBE_I;
input AHB_ASYNC_STB_TOGGLE_I;
input WB_CLK_I;
input WB_RST_I;
input WB_ACK_I;
input [DATAWIDTH-1:0] WB_DAT_I;
output WB_CYC_O;
output [3:0] WB_BYTE_STB_O;
output WB_WE_O;
output WB_RD_O;
output WB_STB_O;
output FABRIC_ASYNC_ACK_TOGGLE_O;
//------------------------------------------
// AHB connection to master
//
reg [ DATAWIDTH-1:0] A2F_HRDATAS;
reg [ DATAWIDTH-1:0] A2F_HRDATAS_nxt;
//------------------------------------------
// Fabric Interface
//
wire AHB_ASYNC_READ_EN_I;
wire AHB_ASYNC_WRITE_EN_I;
wire [ 3:0] AHB_ASYNC_BYTE_STROBE_I;
wire AHB_ASYNC_STB_TOGGLE_I;
wire WB_CLK_I;
wire WB_RST_I;
wire WB_ACK_I;
reg WB_CYC_O;
reg WB_CYC_O_nxt;
reg [ 3:0] WB_BYTE_STB_O;
reg [ 3:0] WB_BYTE_STB_O_nxt;
reg WB_WE_O;
reg WB_WE_O_nxt;
reg WB_RD_O;
reg WB_RD_O_nxt;
reg WB_STB_O;
reg WB_STB_O_nxt;
reg FABRIC_ASYNC_ACK_TOGGLE_O;
reg FABRIC_ASYNC_ACK_TOGGLE_O_nxt;
//------Define Parameters---------
//
//
// None at this time
//
//-----Internal Signals--------------------
//
reg [STATE_WIDTH-1:0] fabric_to_ahb_state;
reg [STATE_WIDTH-1:0] fabric_to_ahb_state_nxt;
reg ahb_async_stb_toggle_i_1ff;
reg ahb_async_stb_toggle_i_2ff;
reg ahb_async_stb_toggle_i_3ff;
wire ahb_async_stb;
//------Logic Operations----------
//
// Check for transfer from the AHB
//
// Note: The AHB is on a different and potentially asynchronous clock.
// Therefore, strobe is passed as a toggle signal.
//
assign ahb_async_stb = ahb_async_stb_toggle_i_2ff ^ ahb_async_stb_toggle_i_3ff;
// Address signal registering, to make the address and data active at the same cycle
//
always @(posedge WB_CLK_I or posedge WB_RST_I) begin
if (WB_RST_I) begin
fabric_to_ahb_state <= FAB_ASYNC_IDLE;
A2F_HRDATAS <= {(DATAWIDTH) {1\'b0}};
WB_CYC_O <= 1\'b0;
WB_BYTE_STB_O <= 4\'b0;
WB_WE_O <= 1\'b0;
WB_RD_O <= 1\'b0;
WB_STB_O <= 1\'b0;
FABRIC_ASYNC_ACK_TOGGLE_O <= 1\'b0;
ahb_async_stb_toggle_i_1ff <= 1\'b0;
ahb_async_stb_toggle_i_2ff <= 1\'b0;
ahb_async_stb_toggle_i_3ff <= 1\'b0;
end else begin
fabric_to_ahb_state <= fabric_to_ahb_state_nxt;
A2F_HRDATAS <= A2F_HRDATAS_nxt;
WB_CYC_O <= WB_CYC_O_nxt;
WB_BYTE_STB_O <= WB_BYTE_STB_O_nxt;
WB_WE_O <= WB_WE_O_nxt;
WB_RD_O <= WB_RD_O_nxt;
WB_STB_O <= WB_STB_O_nxt;
FABRIC_ASYNC_ACK_TOGGLE_O <= FABRIC_ASYNC_ACK_TOGGLE_O_nxt;
ahb_async_stb_toggle_i_1ff <= AHB_ASYNC_STB_TOGGLE_I;
ahb_async_stb_toggle_i_2ff <= ahb_async_stb_toggle_i_1ff;
ahb_async_stb_toggle_i_3ff <= ahb_async_stb_toggle_i_2ff;
end
end
// Define the Fabric Interface Statemachine
//
always @(
ahb_async_stb or
AHB_ASYNC_READ_EN_I or
AHB_ASYNC_WRITE_EN_I or
AHB_ASYNC_BYTE_STROBE_I or
A2F_HRDATAS or
WB_ACK_I or
WB_DAT_I or
WB_CYC_O or
WB_BYTE_STB_O or
WB_WE_O or
WB_RD_O or
WB_STB_O or
FABRIC_ASYNC_ACK_TOGGLE_O or
fabric_to_ahb_state
)
begin
case (fabric_to_ahb_state)
FAB_ASYNC_IDLE: begin
FABRIC_ASYNC_ACK_TOGGLE_O_nxt <= FABRIC_ASYNC_ACK_TOGGLE_O;
A2F_HRDATAS_nxt <= A2F_HRDATAS;
case (ahb_async_stb)
1\'b0: // Wait for an AHB Transfer
begin
fabric_to_ahb_state_nxt <= FAB_ASYNC_IDLE;
WB_CYC_O_nxt <= 1\'b0;
WB_BYTE_STB_O_nxt <= 4\'b0;
WB_WE_O_nxt <= 1\'b0;
WB_RD_O_nxt <= 1\'b0;
WB_STB_O_nxt <= 1\'b0;
end
1\'b1: // AHB Transfer Detected
begin
fabric_to_ahb_state_nxt <= FAB_ASYNC_WAIT;
WB_CYC_O_nxt <= 1\'b1;
WB_BYTE_STB_O_nxt <= AHB_ASYNC_BYTE_STROBE_I;
WB_WE_O_nxt <= AHB_ASYNC_WRITE_EN_I;
WB_RD_O_nxt <= AHB_ASYNC_READ_EN_I;
WB_STB_O_nxt <= 1\'b1;
end
endcase
end
FAB_ASYNC_WAIT: begin
case (WB_ACK_I)
1\'b0: // Wait for Acknowledge from Fabric Interface
begin
fabric_to_ahb_state_nxt <= FAB_ASYNC_WAIT;
A2F_HRDATAS_nxt <= A2F_HRDATAS;
WB_CYC_O_nxt <= WB_CYC_O;
WB_BYTE_STB_O_nxt <= WB_BYTE_STB_O;
WB_WE_O_nxt <= WB_WE_O;
WB_RD_O_nxt <= WB_RD_O;
WB_STB_O_nxt <= WB_STB_O;
FABRIC_ASYNC_ACK_TOGGLE_O_nxt <= FABRIC_ASYNC_ACK_TOGGLE_O;
end
1\'b1: // Received Acknowledge from Fabric Interface
begin
fabric_to_ahb_state_nxt <= FAB_ASYNC_IDLE;
A2F_HRDATAS_nxt <= WB_DAT_I;
WB_CYC_O_nxt <= 1\'b0;
WB_BYTE_STB_O_nxt <= 4\'b0;
WB_WE_O_nxt <= 1\'b0;
WB_RD_O_nxt <= 1\'b0;
WB_STB_O_nxt <= 1\'b0;
FABRIC_ASYNC_ACK_TOGGLE_O_nxt <= ~FABRIC_ASYNC_ACK_TOGGLE_O;
end
endcase
end
default: begin
fabric_to_ahb_state_nxt <= FAB_ASYNC_IDLE;
A2F_HRDATAS_nxt <= A2F_HRDATAS;
WB_CYC_O_nxt <= 1\'b0;
WB_BYTE_STB_O_nxt <= 4\'b0;
WB_WE_O_nxt <= 1\'b0;
WB_RD_O_nxt <= 1\'b0;
WB_STB_O_nxt <= 1\'b0;
FABRIC_ASYNC_ACK_TOGGLE_O_nxt <= FABRIC_ASYNC_ACK_TOGGLE_O;
end
endcase
end
endmodule
`timescale 1ns / 10ps
module ahb2fb_asynbrig (
// AHB Slave Interface to AHB Bus Matrix
//
A2F_HCLK,
A2F_HRESET,
A2F_HADDRS,
A2F_HSEL,
A2F_HTRANSS,
A2F_HSIZES,
A2F_HWRITES,
A2F_HREADYS,
A2F_HWDATAS,
A2F_HREADYOUTS,
A2F_HRESPS,
A2F_HRDATAS,
// Fabric Wishbone Bus
//
WB_CLK_I,
WB_RST_I,
WB_DAT_I,
WB_ACK_I,
WB_ADR_O,
WB_CYC_O,
WB_BYTE_STB_O,
WB_WE_O,
WB_RD_O,
WB_STB_O,
WB_DAT_O
);
//-----Port Parameters-----------------
//
parameter ADDRWIDTH = 32;
parameter DATAWIDTH = 32;
parameter APERWIDTH = 17;
//-----Port Signals--------------------
//
input A2F_HCLK; // Clock
input A2F_HRESET; // Reset
// AHB connection to master
//
input [ADDRWIDTH-1:0] A2F_HADDRS;
input A2F_HSEL;
input [1:0] A2F_HTRANSS;
input [2:0] A2F_HSIZES;
input A2F_HWRITES;
input A2F_HREADYS;
input [DATAWIDTH-1:0] A2F_HWDATAS;
output A2F_HREADYOUTS;
output A2F_HRESPS;
output [DATAWIDTH-1:0] A2F_HRDATAS;
// Wishbone connection to Fabric IP
//
input WB_CLK_I; // Fabric Clock Input from Fabric
input WB_RST_I; // Fabric Reset Input from Fabric
input [DATAWIDTH-1:0] WB_DAT_I; // Read Data Bus from Fabric
input WB_ACK_I; // Transfer Cycle Acknowledge from Fabric
output [APERWIDTH-1:0] WB_ADR_O; // Address Bus to Fabric
output WB_CYC_O; // Cycle Chip Select to Fabric
output [3:0] WB_BYTE_STB_O; // Byte Select to Fabric
output WB_WE_O; // Write Enable to Fabric
output WB_RD_O; // Read Enable to Fabric
output WB_STB_O; // Strobe Signal to Fabric
output [DATAWIDTH-1:0] WB_DAT_O; // Write Data Bus to Fabric
wire A2F_HCLK; // Clock
wire A2F_HRESET; // Reset
// AHB connection to master
//
wire [ADDRWIDTH-1:0] A2F_HADDRS;
wire A2F_HSEL;
wire [ 1:0] A2F_HTRANSS;
wire [ 2:0] A2F_HSIZES;
wire A2F_HWRITES;
wire A2F_HREADYS;
wire [DATAWIDTH-1:0] A2F_HWDATAS;
wire A2F_HREADYOUTS;
wire A2F_HRESPS;
wire [DATAWIDTH-1:0] A2F_HRDATAS;
// Wishbone connection to Fabric IP
//
wire WB_CLK_I; // Fabric Clock Input from Fabric
wire WB_RST_I; // Fabric Reset Input from Fabric
wire [DATAWIDTH-1:0] WB_DAT_I; // Read Data Bus from Fabric
wire WB_ACK_I; // Transfer Cycle Acknowledge from Fabric
wire [APERWIDTH-1:0] WB_ADR_O; // Address Bus (128KB) to Fabric
wire WB_CYC_O; // Cycle Chip Select to Fabric
wire [ 3:0] WB_BYTE_STB_O; // Byte Select to Fabric
wire WB_WE_O; // Write Enable to Fabric
wire WB_RD_O; // Read Enable to Fabric
wire WB_STB_O; // Strobe Signal to Fabric
wire [DATAWIDTH-1:0] WB_DAT_O; // Write Data Bus to Fabric
//------Define Parameters---------
//
//
// None at this time
//
//-----Internal Signals--------------------
//
// Register module interface signals
wire [APERWIDTH-1:0] ahb_async_addr;
wire ahb_async_read_en;
wire ahb_async_write_en;
wire [ 3:0] ahb_async_byte_strobe;
wire ahb_async_stb_toggle;
wire fabric_async_ack_toggle;
//------Logic Operations----------
//
// Define the data input from the AHB and output to the fabric
//
// Note: Due to the nature of the bus timing, there is no need to register
// this value locally.
//
assign WB_DAT_O = A2F_HWDATAS;
// Define the Address bus output from the AHB and output to the fabric
//
// Note: Due to the nature of the bus timing, there is no need to register
// this value locally.
//
assign WB_ADR_O = ahb_async_addr;
//------Instantiate Modules----------------
//
// Interface block to convert AHB transfers to simple read/write
// controls.
ahb2fb_asynbrig_if #(
.DATAWIDTH(DATAWIDTH),
.APERWIDTH(APERWIDTH)
) u_FFE_ahb_to_fabric_async_bridge_interface (
.A2F_HCLK (A2F_HCLK),
.A2F_HRESET(A2F_HRESET),
// Input slave port: 32 bit data bus interface
.A2F_HSEL (A2F_HSEL),
.A2F_HADDRS (A2F_HADDRS[APERWIDTH-1:0]),
.A2F_HTRANSS(A2F_HTRANSS),
.A2F_HSIZES (A2F_HSIZES),
.A2F_HWRITES(A2F_HWRITES),
.A2F_HREADYS(A2F_HREADYS),
.A2F_HREADYOUTS(A2F_HREADYOUTS),
.A2F_HRESPS (A2F_HRESPS),
// Register interface
.AHB_ASYNC_ADDR_O (ahb_async_addr),
.AHB_ASYNC_READ_EN_O (ahb_async_read_en),
.AHB_ASYNC_WRITE_EN_O (ahb_async_write_en),
.AHB_ASYNC_BYTE_STROBE_O(ahb_async_byte_strobe),
.AHB_ASYNC_STB_TOGGLE_O (ahb_async_stb_toggle),
.FABRIC_ASYNC_ACK_TOGGLE_I(fabric_async_ack_toggle)
);
fb2ahb_asynbrig_if // #(
// )
u_FFE_fabric_to_ahb_async_bridge_interface (
.A2F_HRDATAS(A2F_HRDATAS),
.AHB_ASYNC_READ_EN_I (ahb_async_read_en),
.AHB_ASYNC_WRITE_EN_I (ahb_async_write_en),
.AHB_ASYNC_BYTE_STROBE_I(ahb_async_byte_strobe),
.AHB_ASYNC_STB_TOGGLE_I (ahb_async_stb_toggle),
.WB_CLK_I(WB_CLK_I), // Fabric Clock Input from Fabric
.WB_RST_I(WB_RST_I), // Fabric Reset Input from Fabric
.WB_ACK_I(WB_ACK_I), // Transfer Cycle Acknowledge from Fabric
.WB_DAT_I(WB_DAT_I), // Data Bus Input from Fabric
.WB_CYC_O (WB_CYC_O), // Cycle Chip Select to Fabric
.WB_BYTE_STB_O(WB_BYTE_STB_O), // Byte Select to Fabric
.WB_WE_O (WB_WE_O), // Write Enable to Fabric
.WB_RD_O (WB_RD_O), // Read Enable to Fabric
.WB_STB_O (WB_STB_O), // Strobe Signal to Fabric
.FABRIC_ASYNC_ACK_TOGGLE_O(fabric_async_ack_toggle)
);
endmodule
`timescale 1ns / 10ps
module qlal4s3b_cell_macro_bfm (
// AHB-To-Fabric Bridge
//
WBs_ADR,
WBs_CYC,
WBs_BYTE_STB,
WBs_WE,
WBs_RD,
WBs_STB,
WBs_WR_DAT,
WB_CLK,
WB_RST,
WBs_RD_DAT,
WBs_ACK,
//
// SDMA Signals
//
SDMA_Req,
SDMA_Sreq,
SDMA_Done,
SDMA_Active,
//
// FB Interrupts
//
FB_msg_out,
FB_Int_Clr,
FB_Start,
FB_Busy,
//
// FB Clocks
//
Sys_Clk0,
Sys_Clk0_Rst,
Sys_Clk1,
Sys_Clk1_Rst,
//
// Packet FIFO
//
Sys_PKfb_Clk,
Sys_PKfb_Rst,
FB_PKfbData,
FB_PKfbPush,
FB_PKfbSOF,
FB_PKfbEOF,
FB_PKfbOverflow,
//
// Sensor Interface
//
Sensor_Int,
TimeStamp,
//
// SPI Master APB Bus
//
Sys_Pclk,
Sys_Pclk_Rst,
Sys_PSel,
SPIm_Paddr,
SPIm_PEnable,
SPIm_PWrite,
SPIm_PWdata,
SPIm_Prdata,
SPIm_PReady,
SPIm_PSlvErr,
//
// Misc
//
Device_ID,
//
// FBIO Signals
//
FBIO_In,
FBIO_In_En,
FBIO_Out,
FBIO_Out_En,
//
// ???
//
SFBIO,
Device_ID_6S,
Device_ID_4S,
SPIm_PWdata_26S,
SPIm_PWdata_24S,
SPIm_PWdata_14S,
SPIm_PWdata_11S,
SPIm_PWdata_0S,
SPIm_Paddr_8S,
SPIm_Paddr_6S,
FB_PKfbPush_1S,
FB_PKfbData_31S,
FB_PKfbData_21S,
FB_PKfbData_19S,
FB_PKfbData_9S,
FB_PKfbData_6S,
Sys_PKfb_ClkS,
FB_BusyS,
WB_CLKS
);
//------Port Parameters----------------
//
//
// None at this time
//
//------Port Signals-------------------
//
//
// AHB-To-Fabric Bridge
//
output [16:0] WBs_ADR;
output WBs_CYC;
output [3:0] WBs_BYTE_STB;
output WBs_WE;
output WBs_RD;
output WBs_STB;
output [31:0] WBs_WR_DAT;
input WB_CLK;
output WB_RST;
input [31:0] WBs_RD_DAT;
input WBs_ACK;
//
// SDMA Signals
//
input [3:0] SDMA_Req;
input [3:0] SDMA_Sreq;
output [3:0] SDMA_Done;
output [3:0] SDMA_Active;
//
// FB Interrupts
//
input [3:0] FB_msg_out;
input [7:0] FB_Int_Clr;
output FB_Start;
input FB_Busy;
//
// FB Clocks
//
output Sys_Clk0;
output Sys_Clk0_Rst;
output Sys_Clk1;
output Sys_Clk1_Rst;
//
// Packet FIFO
//
input Sys_PKfb_Clk;
output Sys_PKfb_Rst;
input [31:0] FB_PKfbData;
input [3:0] FB_PKfbPush;
input FB_PKfbSOF;
input FB_PKfbEOF;
output FB_PKfbOverflow;
//
// Sensor Interface
//
output [7:0] Sensor_Int;
output [23:0] TimeStamp;
//
// SPI Master APB Bus
//
output Sys_Pclk;
output Sys_Pclk_Rst;
input Sys_PSel;
input [15:0] SPIm_Paddr;
input SPIm_PEnable;
input SPIm_PWrite;
input [31:0] SPIm_PWdata;
output [31:0] SPIm_Prdata;
output SPIm_PReady;
output SPIm_PSlvErr;
//
// Misc
//
input [15:0] Device_ID;
//
// FBIO Signals
//
output [13:0] FBIO_In;
input [13:0] FBIO_In_En;
input [13:0] FBIO_Out;
input [13:0] FBIO_Out_En;
//
// ???
//
inout [13:0] SFBIO;
input Device_ID_6S;
input Device_ID_4S;
input SPIm_PWdata_26S;
input SPIm_PWdata_24S;
input SPIm_PWdata_14S;
input SPIm_PWdata_11S;
input SPIm_PWdata_0S;
input SPIm_Paddr_8S;
input SPIm_Paddr_6S;
input FB_PKfbPush_1S;
input FB_PKfbData_31S;
input FB_PKfbData_21S;
input FB_PKfbData_19S;
input FB_PKfbData_9S;
input FB_PKfbData_6S;
input Sys_PKfb_ClkS;
input FB_BusyS;
input WB_CLKS;
wire [16:0] WBs_ADR;
wire WBs_CYC;
wire [ 3:0] WBs_BYTE_STB;
wire WBs_WE;
wire WBs_RD;
wire WBs_STB;
wire [31:0] WBs_WR_DAT;
wire WB_CLK;
reg WB_RST;
wire [31:0] WBs_RD_DAT;
wire WBs_ACK;
wire [ 3:0] SDMA_Req;
wire [ 3:0] SDMA_Sreq;
//reg [3:0] SDMA_Done;//SDMA BFM
//reg [3:0] SDMA_Active;//SDMA BFM
wire [ 3:0] SDMA_Done;
wire [ 3:0] SDMA_Active;
wire [ 3:0] FB_msg_out;
wire [ 7:0] FB_Int_Clr;
reg FB_Start;
wire FB_Busy;
wire Sys_Clk0;
reg Sys_Clk0_Rst;
wire Sys_Clk1;
reg Sys_Clk1_Rst;
wire Sys_PKfb_Clk;
reg Sys_PKfb_Rst;
wire [31:0] FB_PKfbData;
wire [ 3:0] FB_PKfbPush;
wire FB_PKfbSOF;
wire FB_PKfbEOF;
reg FB_PKfbOverflow;
reg [ 7:0] Sensor_Int;
reg [23:0] TimeStamp;
reg Sys_Pclk;
reg Sys_Pclk_Rst;
wire Sys_PSel;
wire [15:0] SPIm_Paddr;
wire SPIm_PEnable;
wire SPIm_PWrite;
wire [31:0] SPIm_PWdata;
reg [31:0] SPIm_Prdata;
reg SPIm_PReady;
reg SPIm_PSlvErr;
wire [15:0] Device_ID;
reg [13:0] FBIO_In;
wire [13:0] FBIO_In_En;
wire [13:0] FBIO_Out;
wire [13:0] FBIO_Out_En;
wire [13:0] SFBIO;
wire Device_ID_6S;
wire Device_ID_4S;
wire SPIm_PWdata_26S;
wire SPIm_PWdata_24S;
wire SPIm_PWdata_14S;
wire SPIm_PWdata_11S;
wire SPIm_PWdata_0S;
wire SPIm_Paddr_8S;
wire SPIm_Paddr_6S;
wire FB_PKfbPush_1S;
wire FB_PKfbData_31S;
wire FB_PKfbData_21S;
wire FB_PKfbData_19S;
wire FB_PKfbData_9S;
wire FB_PKfbData_6S;
wire Sys_PKfb_ClkS;
wire FB_BusyS;
wire WB_CLKS;
//------Define Parameters--------------
//
parameter ADDRWIDTH = 32;
parameter DATAWIDTH = 32;
parameter APERWIDTH = 17;
parameter ENABLE_AHB_REG_WR_DEBUG_MSG = 1\'b1;
parameter ENABLE_AHB_REG_RD_DEBUG_MSG = 1\'b1;
parameter T_CYCLE_CLK_SYS_CLK0 = 200;//230;//ACSLIPTEST-230;//100;//180;//(1000.0/(80.0/16)) ; // Default EOS S3B Clock Rate
parameter T_CYCLE_CLK_SYS_CLK1 = 650;//3906;//650;////83.33;//250;//30517;//(1000.0/(80.0/16)) ; // Default EOS S3B Clock Rate
parameter T_CYCLE_CLK_A2F_HCLK = (1000.0 / (80.0 / 12)); // Default EOS S3B Clock Rate
parameter SYS_CLK0_RESET_LOOP = 5; //4.34;//5;
parameter SYS_CLK1_RESET_LOOP = 5;
parameter WB_CLK_RESET_LOOP = 5;
parameter A2F_HCLK_RESET_LOOP = 5;
//------Internal Signals---------------
//
integer Sys_Clk0_Reset_Loop_Cnt;
integer Sys_Clk1_Reset_Loop_Cnt;
integer WB_CLK_Reset_Loop_Cnt;
integer A2F_HCLK_Reset_Loop_Cnt;
wire A2F_HCLK;
reg A2F_HRESET;
wire [31:0] A2F_HADDRS;
wire A2F_HSEL;
wire [ 1:0] A2F_HTRANSS;
wire [ 2:0] A2F_HSIZES;
wire A2F_HWRITES;
wire A2F_HREADYS;
wire [31:0] A2F_HWDATAS;
wire A2F_HREADYOUTS;
wire A2F_HRESPS;
wire [31:0] A2F_HRDATAS;
//------Logic Operations---------------
//
// Apply Reset to Sys_Clk0 domain
//
initial begin
Sys_Clk0_Rst <= 1\'b1;
`ifndef YOSYS
for (
Sys_Clk0_Reset_Loop_Cnt = 0;
Sys_Clk0_Reset_Loop_Cnt < SYS_CLK0_RESET_LOOP;
Sys_Clk0_Reset_Loop_Cnt = Sys_Clk0_Reset_Loop_Cnt + 1
) begin
wait(Sys_Clk0 == 1\'b1) #1;
wait(Sys_Clk0 == 1\'b0) #1;
end
wait(Sys_Clk0 == 1\'b1) #1;
`endif
Sys_Clk0_Rst <= 1\'b0;
end
// Apply Reset to Sys_Clk1 domain
//
initial begin
Sys_Clk1_Rst <= 1\'b1;
`ifndef YOSYS
for (
Sys_Clk1_Reset_Loop_Cnt = 0;
Sys_Clk1_Reset_Loop_Cnt < SYS_CLK1_RESET_LOOP;
Sys_Clk1_Reset_Loop_Cnt = Sys_Clk1_Reset_Loop_Cnt + 1
) begin
wait(Sys_Clk1 == 1\'b1) #1;
wait(Sys_Clk1 == 1\'b0) #1;
end
wait(Sys_Clk1 == 1\'b1) #1;
`endif
Sys_Clk1_Rst <= 1\'b0;
end
// Apply Reset to the Wishbone domain
//
// Note: In the ASSP, this reset is distict from the reset domains for Sys_Clk[1:0].
//
initial begin
WB_RST <= 1\'b1;
`ifndef YOSYS
for (
WB_CLK_Reset_Loop_Cnt = 0;
WB_CLK_Reset_Loop_Cnt < WB_CLK_RESET_LOOP;
WB_CLK_Reset_Loop_Cnt = WB_CLK_Reset_Loop_Cnt + 1
) begin
wait(WB_CLK == 1\'b1) #1;
wait(WB_CLK == 1\'b0) #1;
end
wait(WB_CLK == 1\'b1) #1;
`endif
WB_RST <= 1\'b0;
end
// Apply Reset to the AHB Bus domain
//
// Note: The AHB bus clock domain is separate from the Sys_Clk[1:0] domains
initial begin
A2F_HRESET <= 1\'b1;
`ifndef YOSYS
for (
A2F_HCLK_Reset_Loop_Cnt = 0;
A2F_HCLK_Reset_Loop_Cnt < A2F_HCLK_RESET_LOOP;
A2F_HCLK_Reset_Loop_Cnt = A2F_HCLK_Reset_Loop_Cnt + 1
) begin
wait(A2F_HCLK == 1\'b1) #1;
wait(A2F_HCLK == 1\'b0) #1;
end
wait(A2F_HCLK == 1\'b1) #1;
`endif
A2F_HRESET <= 1\'b0;
end
// Initialize all outputs
//
// Note: These may be replaced in the future by BFMs as the become available.
//
// These registers allow test bench routines to drive these signals as needed.
//
initial begin
//
// SDMA Signals
//
//SDMA_Done <= 4\'h0;//Added SDMA BFM
// SDMA_Active'b" <= 4'h0;//Added SDMA BFM
//
// FB Interrupts
//
FB_Start <= 1'b0;
//
// Packet FIFO
//
Sys_PKfb_Rst <= 1'b0;
FB_PKfbOverflow <= 1'b0;
//
// Sensor Interface
//
Sensor_Int <= 8'h0;
TimeStamp <= 24'h0;
//
// SPI Master APB Bus
//
Sys_Pclk <= 1'b0;
Sys_Pclk_Rst <= 1'b0;
SPIm_Prdata <= 32'h0;
SPIm_PReady <= 1'b0;
SPIm_PSlvErr <= 1'b0;
//
// FBIO Signals
//
FBIO_In <= 14'h0;
end
//------Instantiate Modules------------
//
ahb2fb_asynbrig #(
.ADDRWIDTH(ADDRWIDTH),
.DATAWIDTH(DATAWIDTH),
.APERWIDTH(APERWIDTH)
) u_ffe_ahb_to_fabric_async_bridge (
// AHB Slave Interface to AHB Bus Matrix
//
.A2F_HCLK (A2F_HCLK),
.A2F_HRESET(A2F_HRESET),
.A2F_HADDRS (A2F_HADDRS),
.A2F_HSEL (A2F_HSEL),
.A2F_HTRANSS(A2F_HTRANSS),
.A2F_HSIZES (A2F_HSIZES),
.A2F_HWRITES(A2F_HWRITES),
.A2F_HREADYS(A2F_HREADYS),
.A2F_HWDATAS(A2F_HWDATAS),
.A2F_HREADYOUTS(A2F_HREADYOUTS),
.A2F_HRESPS (A2F_HRESPS),
.A2F_HRDATAS (A2F_HRDATAS),
// Fabric Wishbone Bus
//
.WB_CLK_I(WB_CLK),
.WB_RST_I(WB_RST),
.WB_DAT_I(WBs_RD_DAT),
.WB_ACK_I(WBs_ACK),
.WB_ADR_O (WBs_ADR),
.WB_CYC_O (WBs_CYC),
.WB_BYTE_STB_O(WBs_BYTE_STB),
.WB_WE_O (WBs_WE),
.WB_RD_O (WBs_RD),
.WB_STB_O (WBs_STB),
.WB_DAT_O (WBs_WR_DAT)
);
ahb_gen_bfm #(
.ADDRWIDTH (ADDRWIDTH),
.DATAWIDTH (DATAWIDTH),
.DEFAULT_AHB_ADDRESS ({(ADDRWIDTH) {1'b1}}),
.STD_CLK_DLY (2),
.ENABLE_AHB_REG_WR_DEBUG_MSG(ENABLE_AHB_REG_WR_DEBUG_MSG),
.ENABLE_AHB_REG_RD_DEBUG_MSG(ENABLE_AHB_REG_RD_DEBUG_MSG)
) u_ahb_gen_bfm (
// AHB Slave Interface to AHB Bus Matrix
//
.A2F_HCLK (A2F_HCLK),
.A2F_HRESET(A2F_HRESET),
.A2F_HADDRS (A2F_HADDRS),
.A2F_HSEL (A2F_HSEL),
.A2F_HTRANSS(A2F_HTRANSS),
.A2F_HSIZES (A2F_HSIZES),
.A2F_HWRITES(A2F_HWRITES),
.A2F_HREADYS(A2F_HREADYS),
.A2F_HWDATAS(A2F_HWDATAS),
.A2F_HREADYOUTS(A2F_HREADYOUTS),
.A2F_HRESPS (A2F_HRESPS),
.A2F_HRDATAS (A2F_HRDATAS)
);
// Define the clock cycle times.
//
// Note: Values are calculated to output in units of nS.
//
oscillator_s1 #(
.T_CYCLE_CLK(T_CYCLE_CLK_SYS_CLK0)
) u_osc_sys_clk0 (
.OSC_CLK_EN(1'b1),
.OSC_CLK(Sys_Clk0)
);
oscillator_s1 #(
.T_CYCLE_CLK(T_CYCLE_CLK_SYS_CLK1)
) u_osc_sys_clk1 (
.OSC_CLK_EN(1'b1),
.OSC_CLK(Sys_Clk1)
);
oscillator_s1 #(
.T_CYCLE_CLK(T_CYCLE_CLK_A2F_HCLK)
) u_osc_a2f_hclk (
.OSC_CLK_EN(1'b1),
.OSC_CLK(A2F_HCLK)
);
//SDMA bfm
sdma_bfm sdma_bfm_inst0 (
.sdma_req_i\t\t\t( SDMA_Req),
.sdma_sreq_i\t\t( SDMA_Sreq),
.sdma_done_o\t\t( SDMA_Done),
.sdma_active_o\t\t( SDMA_Active)
);
endmodule /* qlal4s3b_cell_macro_bfm*/
(* keep *)
module qlal4s3b_cell_macro (
input WB_CLK,
input WBs_ACK,
input [31:0] WBs_RD_DAT,
output [3:0] WBs_BYTE_STB,
output WBs_CYC,
output WBs_WE,
output WBs_RD,
output WBs_STB,
output [16:0] WBs_ADR,
input [3:0] SDMA_Req,
input [3:0] SDMA_Sreq,
output [3:0] SDMA_Done,
output [3:0] SDMA_Active,
input [3:0] FB_msg_out,
input [7:0] FB_Int_Clr,
output FB_Start,
input FB_Busy,
output WB_RST,
output Sys_PKfb_Rst,
output Clk_C16,
output Clk_C16_Rst,
output Clk_C21,
output Clk_C21_Rst,
output Sys_Pclk,
output Sys_Pclk_Rst,
input Sys_PKfb_Clk,
input [31:0] FB_PKfbData,
output [31:0] WBs_WR_DAT,
input [3:0] FB_PKfbPush,
input FB_PKfbSOF,
input FB_PKfbEOF,
output [7:0] Sensor_Int,
output FB_PKfbOverflow,
output [23:0] TimeStamp,
input Sys_PSel,
input [15:0] SPIm_Paddr,
input SPIm_PEnable,
input SPIm_PWrite,
input [31:0] SPIm_PWdata,
output SPIm_PReady,
output SPIm_PSlvErr,
output [31:0] SPIm_Prdata,
input [15:0] Device_ID,
input [13:0] FBIO_In_En,
input [13:0] FBIO_Out,
input [13:0] FBIO_Out_En,
output [13:0] FBIO_In,
inout [13:0] SFBIO,
input Device_ID_6S,
input Device_ID_4S,
input SPIm_PWdata_26S,
input SPIm_PWdata_24S,
input SPIm_PWdata_14S,
input SPIm_PWdata_11S,
input SPIm_PWdata_0S,
input SPIm_Paddr_8S,
input SPIm_Paddr_6S,
input FB_PKfbPush_1S,
input FB_PKfbData_31S,
input FB_PKfbData_21S,
input FB_PKfbData_19S,
input FB_PKfbData_9S,
input FB_PKfbData_6S,
input Sys_PKfb_ClkS,
input FB_BusyS,
input WB_CLKS
);
qlal4s3b_cell_macro_bfm u_ASSP_bfm_inst (
.WBs_ADR (WBs_ADR),
.WBs_CYC (WBs_CYC),
.WBs_BYTE_STB (WBs_BYTE_STB),
.WBs_WE (WBs_WE),
.WBs_RD (WBs_RD),
.WBs_STB (WBs_STB),
.WBs_WR_DAT (WBs_WR_DAT),
.WB_CLK (WB_CLK),
.WB_RST (WB_RST),
.WBs_RD_DAT (WBs_RD_DAT),
.WBs_ACK (WBs_ACK),
//
// SDMA Signals
//
.SDMA_Req (SDMA_Req),
.SDMA_Sreq (SDMA_Sreq),
.SDMA_Done (SDMA_Done),
.SDMA_Active (SDMA_Active),
//
// FB Interrupts
//
.FB_msg_out (FB_msg_out),
.FB_Int_Clr (FB_Int_Clr),
.FB_Start (FB_Start),
.FB_Busy (FB_Busy),
//
// FB Clocks
//
.Sys_Clk0 (Clk_C16),
.Sys_Clk0_Rst (Clk_C16_Rst),
.Sys_Clk1 (Clk_C21),
.Sys_Clk1_Rst (Clk_C21_Rst),
//
// Packet FIFO
//
.Sys_PKfb_Clk (Sys_PKfb_Clk),
.Sys_PKfb_Rst (Sys_PKfb_Rst),
.FB_PKfbData (FB_PKfbData),
.FB_PKfbPush (FB_PKfbPush),
.FB_PKfbSOF (FB_PKfbSOF),
.FB_PKfbEOF (FB_PKfbEOF),
.FB_PKfbOverflow(FB_PKfbOverflow),
//
// Sensor Interface
//
.Sensor_Int (Sensor_Int),
.TimeStamp (TimeStamp),
//
// SPI Master APB Bus
//
.Sys_Pclk (Sys_Pclk),
.Sys_Pclk_Rst (Sys_Pclk_Rst),
.Sys_PSel (Sys_PSel),
.SPIm_Paddr (SPIm_Paddr),
.SPIm_PEnable (SPIm_PEnable),
.SPIm_PWrite (SPIm_PWrite),
.SPIm_PWdata (SPIm_PWdata),
.SPIm_Prdata (SPIm_Prdata),
.SPIm_PReady (SPIm_PReady),
.SPIm_PSlvErr (SPIm_PSlvErr),
//
// Misc
//
.Device_ID (Device_ID),
//
// FBIO Signals
//
.FBIO_In (FBIO_In),
.FBIO_In_En (FBIO_In_En),
.FBIO_Out (FBIO_Out),
.FBIO_Out_En (FBIO_Out_En),
//
// ???
//
.SFBIO (SFBIO),
.Device_ID_6S (Device_ID_6S),
.Device_ID_4S (Device_ID_4S),
.SPIm_PWdata_26S(SPIm_PWdata_26S),
.SPIm_PWdata_24S(SPIm_PWdata_24S),
.SPIm_PWdata_14S(SPIm_PWdata_14S),
.SPIm_PWdata_11S(SPIm_PWdata_11S),
.SPIm_PWdata_0S (SPIm_PWdata_0S),
.SPIm_Paddr_8S (SPIm_Paddr_8S),
.SPIm_Paddr_6S (SPIm_Paddr_6S),
.FB_PKfbPush_1S (FB_PKfbPush_1S),
.FB_PKfbData_31S(FB_PKfbData_31S),
.FB_PKfbData_21S(FB_PKfbData_21S),
.FB_PKfbData_19S(FB_PKfbData_19S),
.FB_PKfbData_9S (FB_PKfbData_9S),
.FB_PKfbData_6S (FB_PKfbData_6S),
.Sys_PKfb_ClkS (Sys_PKfb_ClkS),
.FB_BusyS (FB_BusyS),
.WB_CLKS (WB_CLKS)
);
endmodule /* qlal4s3b_cell_macro */
(* keep *)
module gpio_cell_macro (
ESEL,
IE,
OSEL,
OQI,
OQE,
DS,
FIXHOLD,
IZ,
IQZ,
IQE,
IQC,
IQCS,
IQR,
WPD,
INEN,
IP
);
input ESEL;
input IE;
input OSEL;
input OQI;
input OQE;
input DS;
input FIXHOLD;
output IZ;
output IQZ;
input IQE;
input IQC;
input IQCS;
input INEN;
input IQR;
input WPD;
inout IP;
reg EN_reg, OQ_reg, IQZ;
wire AND_OUT;
assign rstn = ~IQR;
assign IQCP = IQCS ? ~IQC : IQC;
always @(posedge IQCP or negedge rstn)
if (~rstn) EN_reg <= 1'b0;
else EN_reg <= IE;
always @(posedge IQCP or negedge rstn)
if (~rstn) OQ_reg <= 1'b0;
else if (OQE) OQ_reg <= OQI;
always @(posedge IQCP or negedge rstn)
if (~rstn) IQZ <= 1'b0;
else if (IQE) IQZ <= AND_OUT;
assign IZ = AND_OUT;
assign AND_OUT = INEN ? IP : 1'b0;
assign EN = ESEL ? IE : EN_reg;
assign OQ = OSEL ? OQI : OQ_reg;
assign IP = EN ? OQ : 1'bz;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module mult16x16 (
a,
b,
out
);
parameter DATA_WIDTH = 16;
input [DATA_WIDTH - 1 : 0] a, b;
output [2*DATA_WIDTH - 1 : 0] out;
assign out = a * b;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1\'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *)
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1\'b1)
);
(* async_reg = "false", mr_ff = "false", dont_touch = "true" *)
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \\$_DFFSRE_PPPP_ (
input C,
S,
R,
E,
D,
output Q
);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
dffepc _TECHMAP_REPLACE_ (
.CLK(C),
.PRE(S),
.CLR(R),
.EN (E),
.D (D),
.Q (Q)
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1\'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* abc9_box, lib_whitebox *)
module adder_lut4(
output lut4_out,
(* abc9_carry *)
output cout,
input [0:3] in,
(* abc9_carry *)
input cin
);
parameter [0:15] LUT=0;
parameter IN2_IS_CIN = 0;
wire [0:3] li = (IN2_IS_CIN) ? {in[0], in[1], cin, in[3]} : {in[0], in[1], in[2], in[3]};
// Output function
wire [0:7] s1 = li[0] ?
{LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14]}:
{LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15]};
wire [0:3] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6]} :
{s1[1], s1[3], s1[5], s1[7]};
wire [0:1] s3 = li[2] ? {s2[0], s2[2]} : {s2[1], s2[3]};
assign lut4_out = li[3] ? s3[0] : s3[1];
// Carry out function
assign cout = (s2[2]) ? cin : s2[3];
endmodule
(* abc9_lut=1, lib_whitebox *)
module frac_lut4(
input [0:3] in,
output [0:1] lut2_out,
output lut4_out
);
parameter [0:15] LUT = 0;
// Effective LUT input
wire [0:3] li = in;
// Output function
wire [0:7] s1 = li[0] ?
{LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14]}:
{LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15]};
wire [0:3] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6]} :
{s1[1], s1[3], s1[5], s1[7]};
wire [0:1] s3 = li[2] ? {s2[0], s2[2]} : {s2[1], s2[3]};
assign lut2_out[0] = s2[2];
assign lut2_out[1] = s2[3];
assign lut4_out = li[3] ? s3[0] : s3[1];
endmodule
(* abc9_flop, lib_whitebox *)
module scff(
output reg Q,
input D,
input clk
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge clk)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dff(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge C)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge C or negedge R)
if (!R)
Q <= 1\'b0;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module sh_dff(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge C)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffs(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input S
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge C or negedge S)
if (!S)
Q <= 1\'b1;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffn(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(negedge C)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffnr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(negedge C or negedge R)
if (!R)
Q <= 1\'b0;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffns(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input S
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(negedge C or negedge S)
if (!S)
Q <= 1\'b1;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffsr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R,
input S
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge C or negedge S or negedge R)
if (!S)
Q <= 1\'b1;
else if (!R)
Q <= 1\'b0;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffnsr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R,
input S
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(negedge C or negedge S or negedge R)
if (!S)
Q <= 1\'b1;
else if (!R)
Q <= 1\'b0;
else
Q <= D;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* CLOCK_SIGNAL = "yes", PERIOD = "bad value", WAVEFORM = "0 5" *)
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[1:0] = {cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module latchp (
input d,
clk,
en,
output reg q
);
initial q <= 1\'b0;
always @* if (en) q <= d;
endmodule
module latchn (
input d,
clk,
en,
output reg q
);
always @* if (!en) q <= d;
endmodule
module my_latchsre (
input d,
clk,
en,
clr,
pre,
output reg q
);
always @*
if (clr) q <= 1\'b0;
else if (pre) q <= 1\'b1;
else if (en) q <= d;
endmodule
module latchp_noinit (
input d,
clk,
en,
output reg q
);
always @* if (en) q <= d;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* abc9_flop, lib_whitebox *)
module $__PP3_DFFEPC_SYNCONLY (
output Q,
input D,
input CLK,
input EN,
);
dffepc ff (.Q(Q), .D(D), .CLK(CLK), .EN(EN), .PRE(1\'b0), .CLR(1\'b0));
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module inv (
output Q,
input A
);
assign Q = A ? 0 : 1;
endmodule
module buff (
output Q,
input A
);
assign Q = A;
endmodule
module logic_0 (
output a
);
assign a = 0;
endmodule
module logic_1 (
output a
);
assign a = 1;
endmodule
module gclkbuff (
input A,
output Z
);
specify
(A => Z) = 0;
endspecify
assign Z = A;
endmodule
module inpad (
output Q,
(* iopad_external_pin *)
input P
);
specify
(P => Q) = 0;
endspecify
assign Q = P;
endmodule
module outpad (
(* iopad_external_pin *)
output P,
input A
);
specify
(A => P) = 0;
endspecify
assign P = A;
endmodule
module ckpad (
output Q,
(* iopad_external_pin *)
input P
);
specify
(P => Q) = 0;
endspecify
assign Q = P;
endmodule
module bipad (
input A,
input EN,
output Q,
(* iopad_external_pin *)
inout P
);
assign Q = P;
assign P = EN ? A : 1\'bz;
endmodule
module dff (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge CLK) Q <= D;
endmodule
module dffc (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
(* clkbuf_sink *)
input CLR
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge CLK or posedge CLR)
if (CLR) Q <= 1\'b0;
else Q <= D;
endmodule
module dffp (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
(* clkbuf_sink *)
input PRE
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge CLK or posedge PRE)
if (PRE) Q <= 1\'b1;
else Q <= D;
endmodule
module dffpc (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
(* clkbuf_sink *)
input CLR,
(* clkbuf_sink *)
input PRE
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge CLK or posedge CLR or posedge PRE)
if (CLR) Q <= 1\'b0;
else if (PRE) Q <= 1\'b1;
else Q <= D;
endmodule
module dffe (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
input EN
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge CLK) if (EN) Q <= D;
endmodule
module dffec (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
input EN,
(* clkbuf_sink *)
input CLR
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge CLK or posedge CLR)
if (CLR) Q <= 1\'b0;
else if (EN) Q <= D;
endmodule
(* lib_whitebox *)
module dffepc (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
input EN,
(* clkbuf_sink *)
input CLR,
(* clkbuf_sink *)
input PRE
);
parameter [0:0] INIT = 1\'b0;
specify
if (EN) (posedge CLK => (Q : D)) = 1701; // QCK -> QZ
if (CLR) (CLR => Q) = 967; // QRT -> QZ
if (PRE) (PRE => Q) = 1252; // QST -> QZ
$setup(D, posedge CLK, 216); // QCK -> QDS
$setup(EN, posedge CLK, 590); // QCK -> QEN
endspecify
initial Q = INIT;
always @(posedge CLK or posedge CLR or posedge PRE)
if (CLR) Q <= 1\'b0;
else if (PRE) Q <= 1\'b1;
else if (EN) Q <= D;
endmodule
// FZ FS F2 (F1 TO 0)
(* abc9_box, lib_whitebox *)
module AND2I0 (
output Q,
input A,
B
);
specify
(A => Q) = 698; // FS -> FZ
(B => Q) = 639; // F2 -> FZ
endspecify
assign Q = A ? B : 0;
endmodule
(* abc9_box, lib_whitebox *)
module mux2x0 (
output Q,
input S,
A,
B
);
specify
(S => Q) = 698; // FS -> FZ
(A => Q) = 639; // F1 -> FZ
(B => Q) = 639; // F2 -> FZ
endspecify
assign Q = S ? B : A;
endmodule
(* abc9_box, lib_whitebox *)
module mux2x1 (
output Q,
input S,
A,
B
);
specify
(S => Q) = 698; // FS -> FZ
(A => Q) = 639; // F1 -> FZ
(B => Q) = 639; // F2 -> FZ
endspecify
assign Q = S ? B : A;
endmodule
(* abc9_box, lib_whitebox *)
module mux4x0 (
output Q,
input S0,
S1,
A,
B,
C,
D
);
specify
(S0 => Q) = 1251; // TAB -> TZ
(S1 => Q) = 1406; // TSL -> TZ
(A => Q) = 1699; // TA1 -> TZ
(B => Q) = 1687; // TA2 -> TZ
(C => Q) = 1669; // TB1 -> TZ
(D => Q) = 1679; // TB2 -> TZ
endspecify
assign Q = S1 ? (S0 ? D : C) : (S0 ? B : A);
endmodule
// S0 BSL TSL
// S1 BAB TAB
// S2 TBS
// A TA1
// B TA2
// C TB1
// D TB2
// E BA1
// F BA2
// G BB1
// H BB2
// Q CZ
(* abc9_box, lib_whitebox *)
module mux8x0 (
output Q,
input S0,
S1,
S2,
A,
B,
C,
D,
E,
F,
G,
H
);
specify
(S0 => Q) = 1593; // (\'TSL\', \'BSL\') -> CZ
(S1 => Q) = 1437; // (\'TAB\', \'BAB\') -> CZ
(S2 => Q) = 995; // TBS -> CZ
(A => Q) = 1887; // TA1 -> CZ
(B => Q) = 1873; // TA2 -> CZ
(C => Q) = 1856; // TB1 -> CZ
(D => Q) = 1860; // TB2 -> CZ
(E => Q) = 1714; // BA1 -> CZ
(F => Q) = 1773; // BA2 -> CZ
(G => Q) = 1749; // BB1 -> CZ
(H => Q) = 1723; // BB2 -> CZ
endspecify
assign Q = S2 ? (S1 ? (S0 ? H : G) : (S0 ? F : E)) : (S1 ? (S0 ? D : C) : (S0 ? B : A));
endmodule
(* abc9_lut=1, lib_whitebox *)
module LUT1 (
output O,
input I0
);
parameter [1:0] INIT = 0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 698; // FS -> FZ
endspecify
assign O = I0 ? INIT[1] : INIT[0];
endmodule
// TZ TSL TAB
(* abc9_lut=2, lib_whitebox *)
module LUT2 (
output O,
input I0,
I1
);
parameter [3:0] INIT = 4\'h0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 1251; // TAB -> TZ
(I1 => O) = 1406; // TSL -> TZ
endspecify
wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=2, lib_whitebox *)
module LUT3 (
output O,
input I0,
I1,
I2
);
parameter [7:0] INIT = 8\'h0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 1251; // TAB -> TZ
(I1 => O) = 1406; // TSL -> TZ
(I2 => O) = 1699; // (\'TA1\', \'TA2\', \'TB1\', \'TB2\') -> TZ
endspecify
wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=4, lib_whitebox *)
module LUT4 (
output O,
input I0,
I1,
I2,
I3
);
parameter [15:0] INIT = 16\'h0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 995; // TBS -> CZ
(I1 => O) = 1437; // (\'TAB\', \'BAB\') -> CZ
(I2 => O) = 1593; // (\'TSL\', \'BSL\') -> CZ
(I3 => O) = 1887; // (\'TA1\', \'TA2\', \'TB1\', \'TB2\', \'BA1\', \'BA2\', \'BB1\', \'BB2\') -> CZ
endspecify
wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module logic_cell_macro (
input BA1,
input BA2,
input BAB,
input BAS1,
input BAS2,
input BB1,
input BB2,
input BBS1,
input BBS2,
input BSL,
input F1,
input F2,
input FS,
input QCK,
input QCKS,
input QDI,
input QDS,
input QEN,
input QRT,
input QST,
input TA1,
input TA2,
input TAB,
input TAS1,
input TAS2,
input TB1,
input TB2,
input TBS,
input TBS1,
input TBS2,
input TSL,
output CZ,
output FZ,
output QZ,
output TZ
);
wire TAP1, TAP2, TBP1, TBP2, BAP1, BAP2, BBP1, BBP2, QCKP, TAI, TBI, BAI, BBI, TZI, BZI, CZI, QZI;
reg QZ_r;
assign QZ = QZ_r;
assign TAP1 = TAS1 ? ~TA1 : TA1;
assign TAP2 = TAS2 ? ~TA2 : TA2;
assign TBP1 = TBS1 ? ~TB1 : TB1;
assign TBP2 = TBS2 ? ~TB2 : TB2;
assign BAP1 = BAS1 ? ~BA1 : BA1;
assign BAP2 = BAS2 ? ~BA2 : BA2;
assign BBP1 = BBS1 ? ~BB1 : BB1;
assign BBP2 = BBS2 ? ~BB2 : BB2;
assign TAI = TSL ? TAP2 : TAP1;
assign TBI = TSL ? TBP2 : TBP1;
assign BAI = BSL ? BAP2 : BAP1;
assign BBI = BSL ? BBP2 : BBP1;
assign TZI = TAB ? TBI : TAI;
assign BZI = BAB ? BBI : BAI;
assign CZI = TBS ? BZI : TZI;
assign QZI = QDS ? QDI : CZI;
assign FZ = FS ? F2 : F1;
assign TZ = TZI;
assign CZ = CZI;
assign QCKP = QCKS ? QCK : ~QCK;
initial QZ_r <= 1\'b0;
always @(posedge QCKP or posedge QRT or posedge QST) begin
if (QRT)
QZ_r <= 1\'b0;
else if (QST)
QZ_r <= 1\'b1;
else if (QEN)
QZ_r <= QZI;
end
endmodule
// Include simulation models of QLAL4S3B eFPGA interface
`include "qlal4s3b_sim.v"
// Include simulation models for QLAL3 hard blocks
`include "qlal3_sim.v"
// Include BRAM and FIFO simulation models
`include "brams_sim.v"
// Include MULT simulation models
`include "mult_sim.v"
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
module box(
(* invertible_pin="INV_A" *)
input wire A,
input wire B,
output wire Y
);
parameter [0:0] INV_A = 1\'b0;
endmodule
module top(
input wire [1:0] di,
output wire [5:0] do
);
wire [1:0] d;
\\$_NOT_ n0 (.A(di[0]), .Y(d[0]));
box b00 (.A(d[0]), .B( ), .Y(do[0]));
box b01 (.A(d[0]), .B( ), .Y(do[1]));
box b02 (.A( ), .B(d[0]), .Y(do[2]));
\\$_NOT_ n1 (.A(di[1]), .Y(d[1]));
box b10 (.A(d[1]), .B( ), .Y(do[3]));
box b11 (.A(d[1]), .B( ), .Y(do[4]));
box b12 (.A(d[1]), .B( ), .Y(do[5]));
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \\$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule
module \\$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
// This file exists to map purely-synchronous flops to ABC9 flops, while
// mapping flops with asynchronous-set/clear as boxes, this is because ABC9
// doesn\'t support asynchronous-set/clear flops in sequential synthesis.
module dffepc (
output Q,
input D,
input CLK,
input EN,
input CLR,
input PRE
);
parameter INIT = 1\'b0;
parameter _TECHMAP_CONSTMSK_CLR_ = 1\'b0;
parameter _TECHMAP_CONSTMSK_PRE_ = 1\'b0;
parameter _TECHMAP_CONSTVAL_CLR_ = 1\'b0;
parameter _TECHMAP_CONSTVAL_PRE_ = 1\'b0;
if (_TECHMAP_CONSTMSK_CLR_ != 1\'b0 && _TECHMAP_CONSTMSK_PRE_ != 1\'b0 && _TECHMAP_CONSTVAL_CLR_ == 1\'b0 && _TECHMAP_CONSTVAL_PRE_ == 1\'b0)
$__PP3_DFFEPC_SYNCONLY _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CLK(CLK), .EN(EN));
else
wire _TECHMAP_FAIL_ = 1;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[1:0] = {cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* techmap_celltype = "$alu" *)
module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C;
assign CO = C;
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
wire ci;
wire co;
// First in chain
generate if (i == 0) begin
// CI connected to a constant
if (_TECHMAP_CONSTMSK_CI_ == 1) begin
localparam INIT = (_TECHMAP_CONSTVAL_CI_ == 0) ?
16\'b0110_0110_0000_1000:
16\'b1001_1001_0000_1110;
// LUT4 configured as 1-bit adder with CI=const
adder_lut4 #(
.LUT(INIT),
.IN2_IS_CIN(1\'b0)
) lut_ci_adder (
.in({AA[i], BB[i], 1\'b1, 1\'b1}),
.cin(),
.lut4_out(Y[i]),
.cout(ci)
);
// CI connected to a non-const driver
end else begin
// LUT4 configured as passthrough to drive CI of the next stage
adder_lut4 #(
.LUT(16\'b0000_0000_0000_1100),
.IN2_IS_CIN(1\'b0)
) lut_ci (
.in({1\'b1, CI, 1\'b1, 1\'b1}),
.cin(),
.lut4_out(),
.cout(ci)
);
end
// Not first in chain
end else begin
assign ci = C[i-1];
end endgenerate
// ....................................................
// Single 1-bit adder, mid-chain adder or non-const CI
// adder
generate if ((i == 0 && _TECHMAP_CONSTMSK_CI_ == 0) || (i > 0)) begin
// LUT4 configured as full 1-bit adder
adder_lut4 #(
.LUT(16\'b1001_0110_0110_1000),
.IN2_IS_CIN(1\'b1)
) lut_adder (
.in({AA[i], BB[i], 1\'b1, 1\'b1}),
.cin(ci),
.lut4_out(Y[i]),
.cout(co)
);
end else begin
assign co = ci;
end endgenerate
// ....................................................
// Last in chain
generate if (i == Y_WIDTH-1) begin
// LUT4 configured for passing its CI input to output. This should
// get pruned if the actual CO port is not connected anywhere.
adder_lut4 #(
.LUT(16\'b1111_0000_1111_0000),
.IN2_IS_CIN(1\'b1)
) lut_co (
.in({1\'b1, 1\'b1, 1\'b1, 1\'b1}),
.cin(co),
.lut4_out(C[i]),
.cout()
);
// Not last in chain
end else begin
assign C[i] = co;
end endgenerate
end: slice\t
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
//--------------------------------------------------------------------------------
// Auto-generated by Migen (--------) & LiteX (9b11e919) on 2020-02-25 16:47:33
//--------------------------------------------------------------------------------
module top (
output reg serial_tx,
input serial_rx,
(* dont_touch = "true" *) input clk100,
input cpu_reset,
output [13:0] ddram_a,
output [2:0] ddram_ba,
output ddram_ras_n,
output ddram_cas_n,
output ddram_we_n,
output ddram_cs_n,
output [1:0] ddram_dm,
inout [15:0] ddram_dq,
output [1:0] ddram_dqs_p,
output [1:0] ddram_dqs_n,
output ddram_clk_p,
output ddram_clk_n,
output ddram_cke,
output ddram_odt,
output ddram_reset_n,
output [3:0] led
);
wire [3:0] led;
assign led[0] = main_locked;
assign led[1] = idelayctl_rdy;
assign led[2] = 0;
assign led[3] = 0;
// Manually inserted OBUFs
wire [13:0] ddram_a_iob;
wire [ 2:0] ddram_ba_iob;
wire ddram_ras_n_iob;
wire ddram_cas_n_iob;
wire ddram_we_n_iob;
wire ddram_cs_n_iob;
wire [ 1:0] ddram_dm_iob;
wire ddram_cke_iob;
wire ddram_odt_iob;
wire ddram_reset_n_iob;
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a0 (
.I(ddram_a_iob[0]),
.O(ddram_a[0])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a1 (
.I(ddram_a_iob[1]),
.O(ddram_a[1])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a2 (
.I(ddram_a_iob[2]),
.O(ddram_a[2])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a3 (
.I(ddram_a_iob[3]),
.O(ddram_a[3])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a4 (
.I(ddram_a_iob[4]),
.O(ddram_a[4])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a5 (
.I(ddram_a_iob[5]),
.O(ddram_a[5])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a6 (
.I(ddram_a_iob[6]),
.O(ddram_a[6])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a7 (
.I(ddram_a_iob[7]),
.O(ddram_a[7])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a8 (
.I(ddram_a_iob[8]),
.O(ddram_a[8])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a9 (
.I(ddram_a_iob[9]),
.O(ddram_a[9])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a10 (
.I(ddram_a_iob[10]),
.O(ddram_a[10])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a11 (
.I(ddram_a_iob[11]),
.O(ddram_a[11])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a12 (
.I(ddram_a_iob[12]),
.O(ddram_a[12])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_a13 (
.I(ddram_a_iob[13]),
.O(ddram_a[13])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_ba0 (
.I(ddram_ba_iob[0]),
.O(ddram_ba[0])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_ba1 (
.I(ddram_ba_iob[1]),
.O(ddram_ba[1])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_ba2 (
.I(ddram_ba_iob[2]),
.O(ddram_ba[2])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_dm0 (
.I(ddram_dm_iob[0]),
.O(ddram_dm[0])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_dm1 (
.I(ddram_dm_iob[1]),
.O(ddram_dm[1])
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_ras (
.I(ddram_ras_n_iob),
.O(ddram_ras_n)
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_cas (
.I(ddram_cas_n_iob),
.O(ddram_cas_n)
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_we (
.I(ddram_we_n_iob),
.O(ddram_we_n)
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_cs (
.I(ddram_cs_n_iob),
.O(ddram_cs_n)
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_cke (
.I(ddram_cke_iob),
.O(ddram_cke)
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_odt (
.I(ddram_odt_iob),
.O(ddram_odt)
);
OBUF #(
.IOSTANDARD("SSTL135"),
.SLEW("FAST")
) obuf_rst (
.I(ddram_reset_n_iob),
.O(ddram_reset_n)
);
// End manually inserted OBUFs
wire idelayctl_rdy;
reg main_minsoc_ctrl_reset_storage = 1\'d0;
reg main_minsoc_ctrl_reset_re = 1\'d0;
reg [31:0] main_minsoc_ctrl_scratch_storage = 32\'d305419896;
reg main_minsoc_ctrl_scratch_re = 1\'d0;
wire [31:0] main_minsoc_ctrl_bus_errors_status;
wire main_minsoc_ctrl_bus_errors_we;
wire main_minsoc_ctrl_reset;
wire main_minsoc_ctrl_bus_error;
reg [31:0] main_minsoc_ctrl_bus_errors = 32\'d0;
wire main_minsoc_cpu_reset;
wire [29:0] main_minsoc_cpu_ibus_adr;
wire [31:0] main_minsoc_cpu_ibus_dat_w;
wire [31:0] main_minsoc_cpu_ibus_dat_r;
wire [3:0] main_minsoc_cpu_ibus_sel;
wire main_minsoc_cpu_ibus_cyc;
wire main_minsoc_cpu_ibus_stb;
wire main_minsoc_cpu_ibus_ack;
wire main_minsoc_cpu_ibus_we;
wire [2:0] main_minsoc_cpu_ibus_cti;
wire [1:0] main_minsoc_cpu_ibus_bte;
wire main_minsoc_cpu_ibus_err;
wire [29:0] main_minsoc_cpu_dbus_adr;
wire [31:0] main_minsoc_cpu_dbus_dat_w;
wire [31:0] main_minsoc_cpu_dbus_dat_r;
wire [3:0] main_minsoc_cpu_dbus_sel;
wire main_minsoc_cpu_dbus_cyc;
wire main_minsoc_cpu_dbus_stb;
wire main_minsoc_cpu_dbus_ack;
wire main_minsoc_cpu_dbus_we;
wire [2:0] main_minsoc_cpu_dbus_cti;
wire [1:0] main_minsoc_cpu_dbus_bte;
wire main_minsoc_cpu_dbus_err;
reg [31:0] main_minsoc_cpu_interrupt = 32\'d0;
reg [31:0] main_minsoc_vexriscv = 32\'d0;
wire [29:0] main_minsoc_interface0_soc_bus_adr;
wire [31:0] main_minsoc_interface0_soc_bus_dat_w;
wire [31:0] main_minsoc_interface0_soc_bus_dat_r;
wire [3:0] main_minsoc_interface0_soc_bus_sel;
wire main_minsoc_interface0_soc_bus_cyc;
wire main_minsoc_interface0_soc_bus_stb;
wire main_minsoc_interface0_soc_bus_ack;
wire main_minsoc_interface0_soc_bus_we;
wire [2:0] main_minsoc_interface0_soc_bus_cti;
wire [1:0] main_minsoc_interface0_soc_bus_bte;
wire main_minsoc_interface0_soc_bus_err;
wire [29:0] main_minsoc_interface1_soc_bus_adr;
wire [31:0] main_minsoc_interface1_soc_bus_dat_w;
wire [31:0] main_minsoc_interface1_soc_bus_dat_r;
wire [3:0] main_minsoc_interface1_soc_bus_sel;
wire main_minsoc_interface1_soc_bus_cyc;
wire main_minsoc_interface1_soc_bus_stb;
wire main_minsoc_interface1_soc_bus_ack;
wire main_minsoc_interface1_soc_bus_we;
wire [2:0] main_minsoc_interface1_soc_bus_cti;
wire [1:0] main_minsoc_interface1_soc_bus_bte;
wire main_minsoc_interface1_soc_bus_err;
wire [29:0] main_minsoc_rom_bus_adr;
wire [31:0] main_minsoc_rom_bus_dat_w;
wire [31:0] main_minsoc_rom_bus_dat_r;
wire [3:0] main_minsoc_rom_bus_sel;
wire main_minsoc_rom_bus_cyc;
wire main_minsoc_rom_bus_stb;
reg main_minsoc_rom_bus_ack = 1\'d0;
wire main_minsoc_rom_bus_we;
wire [2:0] main_minsoc_rom_bus_cti;
wire [1:0] main_minsoc_rom_bus_bte;
reg main_minsoc_rom_bus_err = 1\'d0;
wire [12:0] main_minsoc_rom_adr;
wire [31:0] main_minsoc_rom_dat_r;
wire [29:0] main_minsoc_sram_bus_adr;
wire [31:0] main_minsoc_sram_bus_dat_w;
wire [31:0] main_minsoc_sram_bus_dat_r;
wire [3:0] main_minsoc_sram_bus_sel;
wire main_minsoc_sram_bus_cyc;
wire main_minsoc_sram_bus_stb;
reg main_minsoc_sram_bus_ack = 1\'d0;
wire main_minsoc_sram_bus_we;
wire [2:0] main_minsoc_sram_bus_cti;
wire [1:0] main_minsoc_sram_bus_bte;
reg main_minsoc_sram_bus_err = 1\'d0;
wire [9:0] main_minsoc_sram_adr;
wire [31:0] main_minsoc_sram_dat_r;
reg [3:0] main_minsoc_sram_we = 4\'d0;
wire [31:0] main_minsoc_sram_dat_w;
reg [31:0] main_minsoc_storage = 32\'d8246337;
reg main_minsoc_re = 1\'d0;
wire main_minsoc_sink_valid;
reg main_minsoc_sink_ready = 1\'d0;
wire main_minsoc_sink_first;
wire main_minsoc_sink_last;
wire [7:0] main_minsoc_sink_payload_data;
reg main_minsoc_uart_clk_txen = 1\'d0;
reg [31:0] main_minsoc_phase_accumulator_tx = 32\'d0;
reg [7:0] main_minsoc_tx_reg = 8\'d0;
reg [3:0] main_minsoc_tx_bitcount = 4\'d0;
reg main_minsoc_tx_busy = 1\'d0;
reg main_minsoc_source_valid = 1\'d0;
wire main_minsoc_source_ready;
reg main_minsoc_source_first = 1\'d0;
reg main_minsoc_source_last = 1\'d0;
reg [7:0] main_minsoc_source_payload_data = 8\'d0;
reg main_minsoc_uart_clk_rxen = 1\'d0;
reg [31:0] main_minsoc_phase_accumulator_rx = 32\'d0;
wire main_minsoc_rx;
reg main_minsoc_rx_r = 1\'d0;
reg [7:0] main_minsoc_rx_reg = 8\'d0;
reg [3:0] main_minsoc_rx_bitcount = 4\'d0;
reg main_minsoc_rx_busy = 1\'d0;
wire main_minsoc_uart_rxtx_re;
wire [7:0] main_minsoc_uart_rxtx_r;
wire main_minsoc_uart_rxtx_we;
wire [7:0] main_minsoc_uart_rxtx_w;
wire main_minsoc_uart_txfull_status;
wire main_minsoc_uart_txfull_we;
wire main_minsoc_uart_rxempty_status;
wire main_minsoc_uart_rxempty_we;
wire main_minsoc_uart_irq;
wire main_minsoc_uart_tx_status;
reg main_minsoc_uart_tx_pending = 1\'d0;
wire main_minsoc_uart_tx_trigger;
reg main_minsoc_uart_tx_clear = 1\'d0;
reg main_minsoc_uart_tx_old_trigger = 1\'d0;
wire main_minsoc_uart_rx_status;
reg main_minsoc_uart_rx_pending = 1\'d0;
wire main_minsoc_uart_rx_trigger;
reg main_minsoc_uart_rx_clear = 1\'d0;
reg main_minsoc_uart_rx_old_trigger = 1\'d0;
wire main_minsoc_uart_eventmanager_status_re;
wire [1:0] main_minsoc_uart_eventmanager_status_r;
wire main_minsoc_uart_eventmanager_status_we;
reg [1:0] main_minsoc_uart_eventmanager_status_w = 2\'d0;
wire main_minsoc_uart_eventmanager_pending_re;
wire [1:0] main_minsoc_uart_eventmanager_pending_r;
wire main_minsoc_uart_eventmanager_pending_we;
reg [1:0] main_minsoc_uart_eventmanager_pending_w = 2\'d0;
reg [1:0] main_minsoc_uart_eventmanager_storage = 2\'d0;
reg main_minsoc_uart_eventmanager_re = 1\'d0;
wire main_minsoc_uart_uart_sink_valid;
wire main_minsoc_uart_uart_sink_ready;
wire main_minsoc_uart_uart_sink_first;
wire main_minsoc_uart_uart_sink_last;
wire [7:0] main_minsoc_uart_uart_sink_payload_data;
wire main_minsoc_uart_uart_source_valid;
wire main_minsoc_uart_uart_source_ready;
wire main_minsoc_uart_uart_source_first;
wire main_minsoc_uart_uart_source_last;
wire [7:0] main_minsoc_uart_uart_source_payload_data;
wire main_minsoc_uart_tx_fifo_sink_valid;
wire main_minsoc_uart_tx_fifo_sink_ready;
reg main_minsoc_uart_tx_fifo_sink_first = 1\'d0;
reg main_minsoc_uart_tx_fifo_sink_last = 1\'d0;
wire [7:0] main_minsoc_uart_tx_fifo_sink_payload_data;
wire main_minsoc_uart_tx_fifo_source_valid;
wire main_minsoc_uart_tx_fifo_source_ready;
wire main_minsoc_uart_tx_fifo_source_first;
wire main_minsoc_uart_tx_fifo_source_last;
wire [7:0] main_minsoc_uart_tx_fifo_source_payload_data;
wire main_minsoc_uart_tx_fifo_re;
reg main_minsoc_uart_tx_fifo_readable = 1\'d0;
wire main_minsoc_uart_tx_fifo_syncfifo_we;
wire main_minsoc_uart_tx_fifo_syncfifo_writable;
wire main_minsoc_uart_tx_fifo_syncfifo_re;
wire main_minsoc_uart_tx_fifo_syncfifo_readable;
wire [9:0] main_minsoc_uart_tx_fifo_syncfifo_din;
wire [9:0] main_minsoc_uart_tx_fifo_syncfifo_dout;
reg [4:0] main_minsoc_uart_tx_fifo_level0 = 5\'d0;
reg main_minsoc_uart_tx_fifo_replace = 1\'d0;
reg [3:0] main_minsoc_uart_tx_fifo_produce = 4\'d0;
reg [3:0] main_minsoc_uart_tx_fifo_consume = 4\'d0;
reg [3:0] main_minsoc_uart_tx_fifo_wrport_adr = 4\'d0;
wire [9:0] main_minsoc_uart_tx_fifo_wrport_dat_r;
wire main_minsoc_uart_tx_fifo_wrport_we;
wire [9:0] main_minsoc_uart_tx_fifo_wrport_dat_w;
wire main_minsoc_uart_tx_fifo_do_read;
wire [3:0] main_minsoc_uart_tx_fifo_rdport_adr;
wire [9:0] main_minsoc_uart_tx_fifo_rdport_dat_r;
wire main_minsoc_uart_tx_fifo_rdport_re;
wire [4:0] main_minsoc_uart_tx_fifo_level1;
wire [7:0] main_minsoc_uart_tx_fifo_fifo_in_payload_data;
wire main_minsoc_uart_tx_fifo_fifo_in_first;
wire main_minsoc_uart_tx_fifo_fifo_in_last;
wire [7:0] main_minsoc_uart_tx_fifo_fifo_out_payload_data;
wire main_minsoc_uart_tx_fifo_fifo_out_first;
wire main_minsoc_uart_tx_fifo_fifo_out_last;
wire main_minsoc_uart_rx_fifo_sink_valid;
wire main_minsoc_uart_rx_fifo_sink_ready;
wire main_minsoc_uart_rx_fifo_sink_first;
wire main_minsoc_uart_rx_fifo_sink_last;
wire [7:0] main_minsoc_uart_rx_fifo_sink_payload_data;
wire main_minsoc_uart_rx_fifo_source_valid;
wire main_minsoc_uart_rx_fifo_source_ready;
wire main_minsoc_uart_rx_fifo_source_first;
wire main_minsoc_uart_rx_fifo_source_last;
wire [7:0] main_minsoc_uart_rx_fifo_source_payload_data;
wire main_minsoc_uart_rx_fifo_re;
reg main_minsoc_uart_rx_fifo_readable = 1\'d0;
wire main_minsoc_uart_rx_fifo_syncfifo_we;
wire main_minsoc_uart_rx_fifo_syncfifo_writable;
wire main_minsoc_uart_rx_fifo_syncfifo_re;
wire main_minsoc_uart_rx_fifo_syncfifo_readable;
wire [9:0] main_minsoc_uart_rx_fifo_syncfifo_din;
wire [9:0] main_minsoc_uart_rx_fifo_syncfifo_dout;
reg [4:0] main_minsoc_uart_rx_fifo_level0 = 5\'d0;
reg main_minsoc_uart_rx_fifo_replace = 1\'d0;
reg [3:0] main_minsoc_uart_rx_fifo_produce = 4\'d0;
reg [3:0] main_minsoc_uart_rx_fifo_consume = 4\'d0;
reg [3:0] main_minsoc_uart_rx_fifo_wrport_adr = 4\'d0;
wire [9:0] main_minsoc_uart_rx_fifo_wrport_dat_r;
wire main_minsoc_uart_rx_fifo_wrport_we;
wire [9:0] main_minsoc_uart_rx_fifo_wrport_dat_w;
wire main_minsoc_uart_rx_fifo_do_read;
wire [3:0] main_minsoc_uart_rx_fifo_rdport_adr;
wire [9:0] main_minsoc_uart_rx_fifo_rdport_dat_r;
wire main_minsoc_uart_rx_fifo_rdport_re;
wire [4:0] main_minsoc_uart_rx_fifo_level1;
wire [7:0] main_minsoc_uart_rx_fifo_fifo_in_payload_data;
wire main_minsoc_uart_rx_fifo_fifo_in_first;
wire main_minsoc_uart_rx_fifo_fifo_in_last;
wire [7:0] main_minsoc_uart_rx_fifo_fifo_out_payload_data;
wire main_minsoc_uart_rx_fifo_fifo_out_first;
wire main_minsoc_uart_rx_fifo_fifo_out_last;
reg main_minsoc_uart_reset = 1\'d0;
reg [31:0] main_minsoc_timer0_load_storage = 32\'d0;
reg main_minsoc_timer0_load_re = 1\'d0;
reg [31:0] main_minsoc_timer0_reload_storage = 32\'d0;
reg main_minsoc_timer0_reload_re = 1\'d0;
reg main_minsoc_timer0_en_storage = 1\'d0;
reg main_minsoc_timer0_en_re = 1\'d0;
reg main_minsoc_timer0_update_value_storage = 1\'d0;
reg main_minsoc_timer0_update_value_re = 1\'d0;
reg [31:0] main_minsoc_timer0_value_status = 32\'d0;
wire main_minsoc_timer0_value_we;
wire main_minsoc_timer0_irq;
wire main_minsoc_timer0_zero_status;
reg main_minsoc_timer0_zero_pending = 1\'d0;
wire main_minsoc_timer0_zero_trigger;
reg main_minsoc_timer0_zero_clear = 1\'d0;
reg main_minsoc_timer0_zero_old_trigger = 1\'d0;
wire main_minsoc_timer0_eventmanager_status_re;
wire main_minsoc_timer0_eventmanager_status_r;
wire main_minsoc_timer0_eventmanager_status_we;
wire main_minsoc_timer0_eventmanager_status_w;
wire main_minsoc_timer0_eventmanager_pending_re;
wire main_minsoc_timer0_eventmanager_pending_r;
wire main_minsoc_timer0_eventmanager_pending_we;
wire main_minsoc_timer0_eventmanager_pending_w;
reg main_minsoc_timer0_eventmanager_storage = 1\'d0;
reg main_minsoc_timer0_eventmanager_re = 1\'d0;
reg [31:0] main_minsoc_timer0_value = 32\'d0;
reg [13:0] main_minsoc_interface_adr = 14\'d0;
reg main_minsoc_interface_we = 1\'d0;
wire [7:0] main_minsoc_interface_dat_w;
wire [7:0] main_minsoc_interface_dat_r;
wire [29:0] main_minsoc_bus_wishbone_adr;
wire [31:0] main_minsoc_bus_wishbone_dat_w;
wire [31:0] main_minsoc_bus_wishbone_dat_r;
wire [3:0] main_minsoc_bus_wishbone_sel;
wire main_minsoc_bus_wishbone_cyc;
wire main_minsoc_bus_wishbone_stb;
reg main_minsoc_bus_wishbone_ack = 1\'d0;
wire main_minsoc_bus_wishbone_we;
wire [2:0] main_minsoc_bus_wishbone_cti;
wire [1:0] main_minsoc_bus_wishbone_bte;
reg main_minsoc_bus_wishbone_err = 1\'d0;
wire [29:0] main_interface0_wb_sdram_adr;
wire [31:0] main_interface0_wb_sdram_dat_w;
reg [31:0] main_interface0_wb_sdram_dat_r = 32\'d0;
wire [3:0] main_interface0_wb_sdram_sel;
wire main_interface0_wb_sdram_cyc;
wire main_interface0_wb_sdram_stb;
reg main_interface0_wb_sdram_ack = 1\'d0;
wire main_interface0_wb_sdram_we;
wire [2:0] main_interface0_wb_sdram_cti;
wire [1:0] main_interface0_wb_sdram_bte;
reg main_interface0_wb_sdram_err = 1\'d0;
wire sys_clk;
wire sys_rst;
wire sys4x_clk;
wire sys4x_dqs_clk;
wire clk200_clk;
wire clk200_rst;
wire main_pll_clkin;
wire main_reset;
wire main_locked;
wire main_clkout0;
wire main_clkout1;
wire main_clkout2;
wire main_clkout3;
reg [3:0] main_reset_counter = 4\'d15;
reg main_ic_reset = 1\'d1;
reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5\'d13;
reg main_a7ddrphy_half_sys8x_taps_re = 1\'d0;
wire main_a7ddrphy_cdly_rst_re;
wire main_a7ddrphy_cdly_rst_r;
wire main_a7ddrphy_cdly_rst_we;
reg main_a7ddrphy_cdly_rst_w = 1\'d0;
wire main_a7ddrphy_cdly_inc_re;
wire main_a7ddrphy_cdly_inc_r;
wire main_a7ddrphy_cdly_inc_we;
reg main_a7ddrphy_cdly_inc_w = 1\'d0;
reg [1:0] main_a7ddrphy_dly_sel_storage = 2\'d0;
reg main_a7ddrphy_dly_sel_re = 1\'d0;
wire main_a7ddrphy_rdly_dq_rst_re;
wire main_a7ddrphy_rdly_dq_rst_r;
wire main_a7ddrphy_rdly_dq_rst_we;
reg main_a7ddrphy_rdly_dq_rst_w = 1\'d0;
wire main_a7ddrphy_rdly_dq_inc_re;
wire main_a7ddrphy_rdly_dq_inc_r;
wire main_a7ddrphy_rdly_dq_inc_we;
reg main_a7ddrphy_rdly_dq_inc_w = 1\'d0;
wire main_a7ddrphy_rdly_dq_bitslip_rst_re;
wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
wire main_a7ddrphy_rdly_dq_bitslip_rst_we;
reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1\'d0;
wire main_a7ddrphy_rdly_dq_bitslip_re;
wire main_a7ddrphy_rdly_dq_bitslip_r;
wire main_a7ddrphy_rdly_dq_bitslip_we;
reg main_a7ddrphy_rdly_dq_bitslip_w = 1\'d0;
wire [13:0] main_a7ddrphy_dfi_p0_address;
wire [2:0] main_a7ddrphy_dfi_p0_bank;
wire main_a7ddrphy_dfi_p0_cas_n;
wire main_a7ddrphy_dfi_p0_cs_n;
wire main_a7ddrphy_dfi_p0_ras_n;
wire main_a7ddrphy_dfi_p0_we_n;
wire main_a7ddrphy_dfi_p0_cke;
wire main_a7ddrphy_dfi_p0_odt;
wire main_a7ddrphy_dfi_p0_reset_n;
wire main_a7ddrphy_dfi_p0_act_n;
wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
wire main_a7ddrphy_dfi_p0_wrdata_en;
wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
wire main_a7ddrphy_dfi_p0_rddata_en;
reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32\'d0;
reg main_a7ddrphy_dfi_p0_rddata_valid = 1\'d0;
wire [13:0] main_a7ddrphy_dfi_p1_address;
wire [2:0] main_a7ddrphy_dfi_p1_bank;
wire main_a7ddrphy_dfi_p1_cas_n;
wire main_a7ddrphy_dfi_p1_cs_n;
wire main_a7ddrphy_dfi_p1_ras_n;
wire main_a7ddrphy_dfi_p1_we_n;
wire main_a7ddrphy_dfi_p1_cke;
wire main_a7ddrphy_dfi_p1_odt;
wire main_a7ddrphy_dfi_p1_reset_n;
wire main_a7ddrphy_dfi_p1_act_n;
wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
wire main_a7ddrphy_dfi_p1_wrdata_en;
wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
wire main_a7ddrphy_dfi_p1_rddata_en;
reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32\'d0;
reg main_a7ddrphy_dfi_p1_rddata_valid = 1\'d0;
wire [13:0] main_a7ddrphy_dfi_p2_address;
wire [2:0] main_a7ddrphy_dfi_p2_bank;
wire main_a7ddrphy_dfi_p2_cas_n;
wire main_a7ddrphy_dfi_p2_cs_n;
wire main_a7ddrphy_dfi_p2_ras_n;
wire main_a7ddrphy_dfi_p2_we_n;
wire main_a7ddrphy_dfi_p2_cke;
wire main_a7ddrphy_dfi_p2_odt;
wire main_a7ddrphy_dfi_p2_reset_n;
wire main_a7ddrphy_dfi_p2_act_n;
wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
wire main_a7ddrphy_dfi_p2_wrdata_en;
wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
wire main_a7ddrphy_dfi_p2_rddata_en;
reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32\'d0;
reg main_a7ddrphy_dfi_p2_rddata_valid = 1\'d0;
wire [13:0] main_a7ddrphy_dfi_p3_address;
wire [2:0] main_a7ddrphy_dfi_p3_bank;
wire main_a7ddrphy_dfi_p3_cas_n;
wire main_a7ddrphy_dfi_p3_cs_n;
wire main_a7ddrphy_dfi_p3_ras_n;
wire main_a7ddrphy_dfi_p3_we_n;
wire main_a7ddrphy_dfi_p3_cke;
wire main_a7ddrphy_dfi_p3_odt;
wire main_a7ddrphy_dfi_p3_reset_n;
wire main_a7ddrphy_dfi_p3_act_n;
wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
wire main_a7ddrphy_dfi_p3_wrdata_en;
wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
wire main_a7ddrphy_dfi_p3_rddata_en;
reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32\'d0;
reg main_a7ddrphy_dfi_p3_rddata_valid = 1\'d0;
wire main_a7ddrphy_sd_clk_se_nodelay;
reg main_a7ddrphy_oe_dqs = 1\'d0;
wire main_a7ddrphy_dqs_preamble;
wire main_a7ddrphy_dqs_postamble;
reg [7:0] main_a7ddrphy_dqs_serdes_pattern = 8\'d85;
wire main_a7ddrphy_dqs_nodelay0;
wire main_a7ddrphy_dqs_t0;
wire main_a7ddrphy0;
wire main_a7ddrphy_dqs_nodelay1;
wire main_a7ddrphy_dqs_t1;
wire main_a7ddrphy1;
reg main_a7ddrphy_oe_dq = 1\'d0;
wire main_a7ddrphy_dq_o_nodelay0;
wire main_a7ddrphy_dq_i_nodelay0;
wire main_a7ddrphy_dq_i_delayed0;
wire main_a7ddrphy_dq_t0;
wire [7:0] main_a7ddrphy_dq_i_data0;
wire [7:0] main_a7ddrphy_bitslip0_i;
reg [7:0] main_a7ddrphy_bitslip0_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip0_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip0_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay1;
wire main_a7ddrphy_dq_i_nodelay1;
wire main_a7ddrphy_dq_i_delayed1;
wire main_a7ddrphy_dq_t1;
wire [7:0] main_a7ddrphy_dq_i_data1;
wire [7:0] main_a7ddrphy_bitslip1_i;
reg [7:0] main_a7ddrphy_bitslip1_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip1_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip1_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay2;
wire main_a7ddrphy_dq_i_nodelay2;
wire main_a7ddrphy_dq_i_delayed2;
wire main_a7ddrphy_dq_t2;
wire [7:0] main_a7ddrphy_dq_i_data2;
wire [7:0] main_a7ddrphy_bitslip2_i;
reg [7:0] main_a7ddrphy_bitslip2_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip2_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip2_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay3;
wire main_a7ddrphy_dq_i_nodelay3;
wire main_a7ddrphy_dq_i_delayed3;
wire main_a7ddrphy_dq_t3;
wire [7:0] main_a7ddrphy_dq_i_data3;
wire [7:0] main_a7ddrphy_bitslip3_i;
reg [7:0] main_a7ddrphy_bitslip3_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip3_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip3_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay4;
wire main_a7ddrphy_dq_i_nodelay4;
wire main_a7ddrphy_dq_i_delayed4;
wire main_a7ddrphy_dq_t4;
wire [7:0] main_a7ddrphy_dq_i_data4;
wire [7:0] main_a7ddrphy_bitslip4_i;
reg [7:0] main_a7ddrphy_bitslip4_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip4_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip4_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay5;
wire main_a7ddrphy_dq_i_nodelay5;
wire main_a7ddrphy_dq_i_delayed5;
wire main_a7ddrphy_dq_t5;
wire [7:0] main_a7ddrphy_dq_i_data5;
wire [7:0] main_a7ddrphy_bitslip5_i;
reg [7:0] main_a7ddrphy_bitslip5_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip5_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip5_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay6;
wire main_a7ddrphy_dq_i_nodelay6;
wire main_a7ddrphy_dq_i_delayed6;
wire main_a7ddrphy_dq_t6;
wire [7:0] main_a7ddrphy_dq_i_data6;
wire [7:0] main_a7ddrphy_bitslip6_i;
reg [7:0] main_a7ddrphy_bitslip6_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip6_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip6_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay7;
wire main_a7ddrphy_dq_i_nodelay7;
wire main_a7ddrphy_dq_i_delayed7;
wire main_a7ddrphy_dq_t7;
wire [7:0] main_a7ddrphy_dq_i_data7;
wire [7:0] main_a7ddrphy_bitslip7_i;
reg [7:0] main_a7ddrphy_bitslip7_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip7_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip7_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay8;
wire main_a7ddrphy_dq_i_nodelay8;
wire main_a7ddrphy_dq_i_delayed8;
wire main_a7ddrphy_dq_t8;
wire [7:0] main_a7ddrphy_dq_i_data8;
wire [7:0] main_a7ddrphy_bitslip8_i;
reg [7:0] main_a7ddrphy_bitslip8_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip8_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip8_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay9;
wire main_a7ddrphy_dq_i_nodelay9;
wire main_a7ddrphy_dq_i_delayed9;
wire main_a7ddrphy_dq_t9;
wire [7:0] main_a7ddrphy_dq_i_data9;
wire [7:0] main_a7ddrphy_bitslip9_i;
reg [7:0] main_a7ddrphy_bitslip9_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip9_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip9_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay10;
wire main_a7ddrphy_dq_i_nodelay10;
wire main_a7ddrphy_dq_i_delayed10;
wire main_a7ddrphy_dq_t10;
wire [7:0] main_a7ddrphy_dq_i_data10;
wire [7:0] main_a7ddrphy_bitslip10_i;
reg [7:0] main_a7ddrphy_bitslip10_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip10_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip10_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay11;
wire main_a7ddrphy_dq_i_nodelay11;
wire main_a7ddrphy_dq_i_delayed11;
wire main_a7ddrphy_dq_t11;
wire [7:0] main_a7ddrphy_dq_i_data11;
wire [7:0] main_a7ddrphy_bitslip11_i;
reg [7:0] main_a7ddrphy_bitslip11_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip11_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip11_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay12;
wire main_a7ddrphy_dq_i_nodelay12;
wire main_a7ddrphy_dq_i_delayed12;
wire main_a7ddrphy_dq_t12;
wire [7:0] main_a7ddrphy_dq_i_data12;
wire [7:0] main_a7ddrphy_bitslip12_i;
reg [7:0] main_a7ddrphy_bitslip12_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip12_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip12_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay13;
wire main_a7ddrphy_dq_i_nodelay13;
wire main_a7ddrphy_dq_i_delayed13;
wire main_a7ddrphy_dq_t13;
wire [7:0] main_a7ddrphy_dq_i_data13;
wire [7:0] main_a7ddrphy_bitslip13_i;
reg [7:0] main_a7ddrphy_bitslip13_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip13_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip13_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay14;
wire main_a7ddrphy_dq_i_nodelay14;
wire main_a7ddrphy_dq_i_delayed14;
wire main_a7ddrphy_dq_t14;
wire [7:0] main_a7ddrphy_dq_i_data14;
wire [7:0] main_a7ddrphy_bitslip14_i;
reg [7:0] main_a7ddrphy_bitslip14_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip14_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip14_r = 16\'d0;
wire main_a7ddrphy_dq_o_nodelay15;
wire main_a7ddrphy_dq_i_nodelay15;
wire main_a7ddrphy_dq_i_delayed15;
wire main_a7ddrphy_dq_t15;
wire [7:0] main_a7ddrphy_dq_i_data15;
wire [7:0] main_a7ddrphy_bitslip15_i;
reg [7:0] main_a7ddrphy_bitslip15_o = 8\'d0;
reg [2:0] main_a7ddrphy_bitslip15_value = 3\'d0;
reg [15:0] main_a7ddrphy_bitslip15_r = 16\'d0;
reg main_a7ddrphy_n_rddata_en0 = 1\'d0;
reg main_a7ddrphy_n_rddata_en1 = 1\'d0;
reg main_a7ddrphy_n_rddata_en2 = 1\'d0;
reg main_a7ddrphy_n_rddata_en3 = 1\'d0;
reg main_a7ddrphy_n_rddata_en4 = 1\'d0;
reg main_a7ddrphy_n_rddata_en5 = 1\'d0;
reg main_a7ddrphy_n_rddata_en6 = 1\'d0;
reg main_a7ddrphy_n_rddata_en7 = 1\'d0;
wire main_a7ddrphy_oe;
reg [3:0] main_a7ddrphy_last_wrdata_en = 4\'d0;
wire [13:0] main_sdram_inti_p0_address;
wire [2:0] main_sdram_inti_p0_bank;
reg main_sdram_inti_p0_cas_n = 1\'d1;
reg main_sdram_inti_p0_cs_n = 1\'d1;
reg main_sdram_inti_p0_ras_n = 1\'d1;
reg main_sdram_inti_p0_we_n = 1\'d1;
wire main_sdram_inti_p0_cke;
wire main_sdram_inti_p0_odt;
wire main_sdram_inti_p0_reset_n;
reg main_sdram_inti_p0_act_n = 1\'d1;
wire [31:0] main_sdram_inti_p0_wrdata;
wire main_sdram_inti_p0_wrdata_en;
wire [3:0] main_sdram_inti_p0_wrdata_mask;
wire main_sdram_inti_p0_rddata_en;
reg [31:0] main_sdram_inti_p0_rddata = 32\'d0;
reg main_sdram_inti_p0_rddata_valid = 1\'d0;
wire [13:0] main_sdram_inti_p1_address;
wire [2:0] main_sdram_inti_p1_bank;
reg main_sdram_inti_p1_cas_n = 1\'d1;
reg main_sdram_inti_p1_cs_n = 1\'d1;
reg main_sdram_inti_p1_ras_n = 1\'d1;
reg main_sdram_inti_p1_we_n = 1\'d1;
wire main_sdram_inti_p1_cke;
wire main_sdram_inti_p1_odt;
wire main_sdram_inti_p1_reset_n;
reg main_sdram_inti_p1_act_n = 1\'d1;
wire [31:0] main_sdram_inti_p1_wrdata;
wire main_sdram_inti_p1_wrdata_en;
wire [3:0] main_sdram_inti_p1_wrdata_mask;
wire main_sdram_inti_p1_rddata_en;
reg [31:0] main_sdram_inti_p1_rddata = 32\'d0;
reg main_sdram_inti_p1_rddata_valid = 1\'d0;
wire [13:0] main_sdram_inti_p2_address;
wire [2:0] main_sdram_inti_p2_bank;
reg main_sdram_inti_p2_cas_n = 1\'d1;
reg main_sdram_inti_p2_cs_n = 1\'d1;
reg main_sdram_inti_p2_ras_n = 1\'d1;
reg main_sdram_inti_p2_we_n = 1\'d1;
wire main_sdram_inti_p2_cke;
wire main_sdram_inti_p2_odt;
wire main_sdram_inti_p2_reset_n;
reg main_sdram_inti_p2_act_n = 1\'d1;
wire [31:0] main_sdram_inti_p2_wrdata;
wire main_sdram_inti_p2_wrdata_en;
wire [3:0] main_sdram_inti_p2_wrdata_mask;
wire main_sdram_inti_p2_rddata_en;
reg [31:0] main_sdram_inti_p2_rddata = 32\'d0;
reg main_sdram_inti_p2_rddata_valid = 1\'d0;
wire [13:0] main_sdram_inti_p3_address;
wire [2:0] main_sdram_inti_p3_bank;
reg main_sdram_inti_p3_cas_n = 1\'d1;
reg main_sdram_inti_p3_cs_n = 1\'d1;
reg main_sdram_inti_p3_ras_n = 1\'d1;
reg main_sdram_inti_p3_we_n = 1\'d1;
wire main_sdram_inti_p3_cke;
wire main_sdram_inti_p3_odt;
wire main_sdram_inti_p3_reset_n;
reg main_sdram_inti_p3_act_n = 1\'d1;
wire [31:0] main_sdram_inti_p3_wrdata;
wire main_sdram_inti_p3_wrdata_en;
wire [3:0] main_sdram_inti_p3_wrdata_mask;
wire main_sdram_inti_p3_rddata_en;
reg [31:0] main_sdram_inti_p3_rddata = 32\'d0;
reg main_sdram_inti_p3_rddata_valid = 1\'d0;
wire [13:0] main_sdram_slave_p0_address;
wire [2:0] main_sdram_slave_p0_bank;
wire main_sdram_slave_p0_cas_n;
wire main_sdram_slave_p0_cs_n;
wire main_sdram_slave_p0_ras_n;
wire main_sdram_slave_p0_we_n;
wire main_sdram_slave_p0_cke;
wire main_sdram_slave_p0_odt;
wire main_sdram_slave_p0_reset_n;
wire main_sdram_slave_p0_act_n;
wire [31:0] main_sdram_slave_p0_wrdata;
wire main_sdram_slave_p0_wrdata_en;
wire [3:0] main_sdram_slave_p0_wrdata_mask;
wire main_sdram_slave_p0_rddata_en;
reg [31:0] main_sdram_slave_p0_rddata = 32\'d0;
reg main_sdram_slave_p0_rddata_valid = 1\'d0;
wire [13:0] main_sdram_slave_p1_address;
wire [2:0] main_sdram_slave_p1_bank;
wire main_sdram_slave_p1_cas_n;
wire main_sdram_slave_p1_cs_n;
wire main_sdram_slave_p1_ras_n;
wire main_sdram_slave_p1_we_n;
wire main_sdram_slave_p1_cke;
wire main_sdram_slave_p1_odt;
wire main_sdram_slave_p1_reset_n;
wire main_sdram_slave_p1_act_n;
wire [31:0] main_sdram_slave_p1_wrdata;
wire main_sdram_slave_p1_wrdata_en;
wire [3:0] main_sdram_slave_p1_wrdata_mask;
wire main_sdram_slave_p1_rddata_en;
reg [31:0] main_sdram_slave_p1_rddata = 32\'d0;
reg main_sdram_slave_p1_rddata_valid = 1\'d0;
wire [13:0] main_sdram_slave_p2_address;
wire [2:0] main_sdram_slave_p2_bank;
wire main_sdram_slave_p2_cas_n;
wire main_sdram_slave_p2_cs_n;
wire main_sdram_slave_p2_ras_n;
wire main_sdram_slave_p2_we_n;
wire main_sdram_slave_p2_cke;
wire main_sdram_slave_p2_odt;
wire main_sdram_slave_p2_reset_n;
wire main_sdram_slave_p2_act_n;
wire [31:0] main_sdram_slave_p2_wrdata;
wire main_sdram_slave_p2_wrdata_en;
wire [3:0] main_sdram_slave_p2_wrdata_mask;
wire main_sdram_slave_p2_rddata_en;
reg [31:0] main_sdram_slave_p2_rddata = 32\'d0;
reg main_sdram_slave_p2_rddata_valid = 1\'d0;
wire [13:0] main_sdram_slave_p3_address;
wire [2:0] main_sdram_slave_p3_bank;
wire main_sdram_slave_p3_cas_n;
wire main_sdram_slave_p3_cs_n;
wire main_sdram_slave_p3_ras_n;
wire main_sdram_slave_p3_we_n;
wire main_sdram_slave_p3_cke;
wire main_sdram_slave_p3_odt;
wire main_sdram_slave_p3_reset_n;
wire main_sdram_slave_p3_act_n;
wire [31:0] main_sdram_slave_p3_wrdata;
wire main_sdram_slave_p3_wrdata_en;
wire [3:0] main_sdram_slave_p3_wrdata_mask;
wire main_sdram_slave_p3_rddata_en;
reg [31:0] main_sdram_slave_p3_rddata = 32\'d0;
reg main_sdram_slave_p3_rddata_valid = 1\'d0;
reg [13:0] main_sdram_master_p0_address = 14\'d0;
reg [2:0] main_sdram_master_p0_bank = 3\'d0;
reg main_sdram_master_p0_cas_n = 1\'d1;
reg main_sdram_master_p0_cs_n = 1\'d1;
reg main_sdram_master_p0_ras_n = 1\'d1;
reg main_sdram_master_p0_we_n = 1\'d1;
reg main_sdram_master_p0_cke = 1\'d0;
reg main_sdram_master_p0_odt = 1\'d0;
reg main_sdram_master_p0_reset_n = 1\'d0;
reg main_sdram_master_p0_act_n = 1\'d1;
reg [31:0] main_sdram_master_p0_wrdata = 32\'d0;
reg main_sdram_master_p0_wrdata_en = 1\'d0;
reg [3:0] main_sdram_master_p0_wrdata_mask = 4\'d0;
reg main_sdram_master_p0_rddata_en = 1\'d0;
wire [31:0] main_sdram_master_p0_rddata;
wire main_sdram_master_p0_rddata_valid;
reg [13:0] main_sdram_master_p1_address = 14\'d0;
reg [2:0] main_sdram_master_p1_bank = 3\'d0;
reg main_sdram_master_p1_cas_n = 1\'d1;
reg main_sdram_master_p1_cs_n = 1\'d1;
reg main_sdram_master_p1_ras_n = 1\'d1;
reg main_sdram_master_p1_we_n = 1\'d1;
reg main_sdram_master_p1_cke = 1\'d0;
reg main_sdram_master_p1_odt = 1\'d0;
reg main_sdram_master_p1_reset_n = 1\'d0;
reg main_sdram_master_p1_act_n = 1\'d1;
reg [31:0] main_sdram_master_p1_wrdata = 32\'d0;
reg main_sdram_master_p1_wrdata_en = 1\'d0;
reg [3:0] main_sdram_master_p1_wrdata_mask = 4\'d0;
reg main_sdram_master_p1_rddata_en = 1\'d0;
wire [31:0] main_sdram_master_p1_rddata;
wire main_sdram_master_p1_rddata_valid;
reg [13:0] main_sdram_master_p2_address = 14\'d0;
reg [2:0] main_sdram_master_p2_bank = 3\'d0;
reg main_sdram_master_p2_cas_n = 1\'d1;
reg main_sdram_master_p2_cs_n = 1\'d1;
reg main_sdram_master_p2_ras_n = 1\'d1;
reg main_sdram_master_p2_we_n = 1\'d1;
reg main_sdram_master_p2_cke = 1\'d0;
reg main_sdram_master_p2_odt = 1\'d0;
reg main_sdram_master_p2_reset_n = 1\'d0;
reg main_sdram_master_p2_act_n = 1\'d1;
reg [31:0] main_sdram_master_p2_wrdata = 32\'d0;
reg main_sdram_master_p2_wrdata_en = 1\'d0;
reg [3:0] main_sdram_master_p2_wrdata_mask = 4\'d0;
reg main_sdram_master_p2_rddata_en = 1\'d0;
wire [31:0] main_sdram_master_p2_rddata;
wire main_sdram_master_p2_rddata_valid;
reg [13:0] main_sdram_master_p3_address = 14\'d0;
reg [2:0] main_sdram_master_p3_bank = 3\'d0;
reg main_sdram_master_p3_cas_n = 1\'d1;
reg main_sdram_master_p3_cs_n = 1\'d1;
reg main_sdram_master_p3_ras_n = 1\'d1;
reg main_sdram_master_p3_we_n = 1\'d1;
reg main_sdram_master_p3_cke = 1\'d0;
reg main_sdram_master_p3_odt = 1\'d0;
reg main_sdram_master_p3_reset_n = 1\'d0;
reg main_sdram_master_p3_act_n = 1\'d1;
reg [31:0] main_sdram_master_p3_wrdata = 32\'d0;
reg main_sdram_master_p3_wrdata_en = 1\'d0;
reg [3:0] main_sdram_master_p3_wrdata_mask = 4\'d0;
reg main_sdram_master_p3_rddata_en = 1\'d0;
wire [31:0] main_sdram_master_p3_rddata;
wire main_sdram_master_p3_rddata_valid;
reg [3:0] main_sdram_storage = 4\'d0;
reg main_sdram_re = 1\'d0;
reg [5:0] main_sdram_phaseinjector0_command_storage = 6\'d0;
reg main_sdram_phaseinjector0_command_re = 1\'d0;
wire main_sdram_phaseinjector0_command_issue_re;
wire main_sdram_phaseinjector0_command_issue_r;
wire main_sdram_phaseinjector0_command_issue_we;
reg main_sdram_phaseinjector0_command_issue_w = 1\'d0;
reg [13:0] main_sdram_phaseinjector0_address_storage = 14\'d0;
reg main_sdram_phaseinjector0_address_re = 1\'d0;
reg [2:0] main_sdram_phaseinjector0_baddress_storage = 3\'d0;
reg main_sdram_phaseinjector0_baddress_re = 1\'d0;
reg [31:0] main_sdram_phaseinjector0_wrdata_storage = 32\'d0;
reg main_sdram_phaseinjector0_wrdata_re = 1\'d0;
reg [31:0] main_sdram_phaseinjector0_status = 32\'d0;
wire main_sdram_phaseinjector0_we;
reg [5:0] main_sdram_phaseinjector1_command_storage = 6\'d0;
reg main_sdram_phaseinjector1_command_re = 1\'d0;
wire main_sdram_phaseinjector1_command_issue_re;
wire main_sdram_phaseinjector1_command_issue_r;
wire main_sdram_phaseinjector1_command_issue_we;
reg main_sdram_phaseinjector1_command_issue_w = 1\'d0;
reg [13:0] main_sdram_phaseinjector1_address_storage = 14\'d0;
reg main_sdram_phaseinjector1_address_re = 1\'d0;
reg [2:0] main_sdram_phaseinjector1_baddress_storage = 3\'d0;
reg main_sdram_phaseinjector1_baddress_re = 1\'d0;
reg [31:0] main_sdram_phaseinjector1_wrdata_storage = 32\'d0;
reg main_sdram_phaseinjector1_wrdata_re = 1\'d0;
reg [31:0] main_sdram_phaseinjector1_status = 32\'d0;
wire main_sdram_phaseinjector1_we;
reg [5:0] main_sdram_phaseinjector2_command_storage = 6\'d0;
reg main_sdram_phaseinjector2_command_re = 1\'d0;
wire main_sdram_phaseinjector2_command_issue_re;
wire main_sdram_phaseinjector2_command_issue_r;
wire main_sdram_phaseinjector2_command_issue_we;
reg main_sdram_phaseinjector2_command_issue_w = 1\'d0;
reg [13:0] main_sdram_phaseinjector2_address_storage = 14\'d0;
reg main_sdram_phaseinjector2_address_re = 1\'d0;
reg [2:0] main_sdram_phaseinjector2_baddress_storage = 3\'d0;
reg main_sdram_phaseinjector2_baddress_re = 1\'d0;
reg [31:0] main_sdram_phaseinjector2_wrdata_storage = 32\'d0;
reg main_sdram_phaseinjector2_wrdata_re = 1\'d0;
reg [31:0] main_sdram_phaseinjector2_status = 32\'d0;
wire main_sdram_phaseinjector2_we;
reg [5:0] main_sdram_phaseinjector3_command_storage = 6\'d0;
reg main_sdram_phaseinjector3_command_re = 1\'d0;
wire main_sdram_phaseinjector3_command_issue_re;
wire main_sdram_phaseinjector3_command_issue_r;
wire main_sdram_phaseinjector3_command_issue_we;
reg main_sdram_phaseinjector3_command_issue_w = 1\'d0;
reg [13:0] main_sdram_phaseinjector3_address_storage = 14\'d0;
reg main_sdram_phaseinjector3_address_re = 1\'d0;
reg [2:0] main_sdram_phaseinjector3_baddress_storage = 3\'d0;
reg main_sdram_phaseinjector3_baddress_re = 1\'d0;
reg [31:0] main_sdram_phaseinjector3_wrdata_storage = 32\'d0;
reg main_sdram_phaseinjector3_wrdata_re = 1\'d0;
reg [31:0] main_sdram_phaseinjector3_status = 32\'d0;
wire main_sdram_phaseinjector3_we;
wire main_sdram_interface_bank0_valid;
wire main_sdram_interface_bank0_ready;
wire main_sdram_interface_bank0_we;
wire [20:0] main_sdram_interface_bank0_addr;
wire main_sdram_interface_bank0_lock;
wire main_sdram_interface_bank0_wdata_ready;
wire main_sdram_interface_bank0_rdata_valid;
wire main_sdram_interface_bank1_valid;
wire main_sdram_interface_bank1_ready;
wire main_sdram_interface_bank1_we;
wire [20:0] main_sdram_interface_bank1_addr;
wire main_sdram_interface_bank1_lock;
wire main_sdram_interface_bank1_wdata_ready;
wire main_sdram_interface_bank1_rdata_valid;
wire main_sdram_interface_bank2_valid;
wire main_sdram_interface_bank2_ready;
wire main_sdram_interface_bank2_we;
wire [20:0] main_sdram_interface_bank2_addr;
wire main_sdram_interface_bank2_lock;
wire main_sdram_interface_bank2_wdata_ready;
wire main_sdram_interface_bank2_rdata_valid;
wire main_sdram_interface_bank3_valid;
wire main_sdram_interface_bank3_ready;
wire main_sdram_interface_bank3_we;
wire [20:0] main_sdram_interface_bank3_addr;
wire main_sdram_interface_bank3_lock;
wire main_sdram_interface_bank3_wdata_ready;
wire main_sdram_interface_bank3_rdata_valid;
wire main_sdram_interface_bank4_valid;
wire main_sdram_interface_bank4_ready;
wire main_sdram_interface_bank4_we;
wire [20:0] main_sdram_interface_bank4_addr;
wire main_sdram_interface_bank4_lock;
wire main_sdram_interface_bank4_wdata_ready;
wire main_sdram_interface_bank4_rdata_valid;
wire main_sdram_interface_bank5_valid;
wire main_sdram_interface_bank5_ready;
wire main_sdram_interface_bank5_we;
wire [20:0] main_sdram_interface_bank5_addr;
wire main_sdram_interface_bank5_lock;
wire main_sdram_interface_bank5_wdata_ready;
wire main_sdram_interface_bank5_rdata_valid;
wire main_sdram_interface_bank6_valid;
wire main_sdram_interface_bank6_ready;
wire main_sdram_interface_bank6_we;
wire [20:0] main_sdram_interface_bank6_addr;
wire main_sdram_interface_bank6_lock;
wire main_sdram_interface_bank6_wdata_ready;
wire main_sdram_interface_bank6_rdata_valid;
wire main_sdram_interface_bank7_valid;
wire main_sdram_interface_bank7_ready;
wire main_sdram_interface_bank7_we;
wire [20:0] main_sdram_interface_bank7_addr;
wire main_sdram_interface_bank7_lock;
wire main_sdram_interface_bank7_wdata_ready;
wire main_sdram_interface_bank7_rdata_valid;
reg [127:0] main_sdram_interface_wdata = 128\'d0;
reg [15:0] main_sdram_interface_wdata_we = 16\'d0;
wire [127:0] main_sdram_interface_rdata;
reg [13:0] main_sdram_dfi_p0_address = 14\'d0;
reg [2:0] main_sdram_dfi_p0_bank = 3\'d0;
reg main_sdram_dfi_p0_cas_n = 1\'d1;
reg main_sdram_dfi_p0_cs_n = 1\'d1;
reg main_sdram_dfi_p0_ras_n = 1\'d1;
reg main_sdram_dfi_p0_we_n = 1\'d1;
wire main_sdram_dfi_p0_cke;
wire main_sdram_dfi_p0_odt;
wire main_sdram_dfi_p0_reset_n;
reg main_sdram_dfi_p0_act_n = 1\'d1;
wire [31:0] main_sdram_dfi_p0_wrdata;
reg main_sdram_dfi_p0_wrdata_en = 1\'d0;
wire [3:0] main_sdram_dfi_p0_wrdata_mask;
reg main_sdram_dfi_p0_rddata_en = 1\'d0;
wire [31:0] main_sdram_dfi_p0_rddata;
wire main_sdram_dfi_p0_rddata_valid;
reg [13:0] main_sdram_dfi_p1_address = 14\'d0;
reg [2:0] main_sdram_dfi_p1_bank = 3\'d0;
reg main_sdram_dfi_p1_cas_n = 1\'d1;
reg main_sdram_dfi_p1_cs_n = 1\'d1;
reg main_sdram_dfi_p1_ras_n = 1\'d1;
reg main_sdram_dfi_p1_we_n = 1\'d1;
wire main_sdram_dfi_p1_cke;
wire main_sdram_dfi_p1_odt;
wire main_sdram_dfi_p1_reset_n;
reg main_sdram_dfi_p1_act_n = 1\'d1;
wire [31:0] main_sdram_dfi_p1_wrdata;
reg main_sdram_dfi_p1_wrdata_en = 1\'d0;
wire [3:0] main_sdram_dfi_p1_wrdata_mask;
reg main_sdram_dfi_p1_rddata_en = 1\'d0;
wire [31:0] main_sdram_dfi_p1_rddata;
wire main_sdram_dfi_p1_rddata_valid;
reg [13:0] main_sdram_dfi_p2_address = 14\'d0;
reg [2:0] main_sdram_dfi_p2_bank = 3\'d0;
reg main_sdram_dfi_p2_cas_n = 1\'d1;
reg main_sdram_dfi_p2_cs_n = 1\'d1;
reg main_sdram_dfi_p2_ras_n = 1\'d1;
reg main_sdram_dfi_p2_we_n = 1\'d1;
wire main_sdram_dfi_p2_cke;
wire main_sdram_dfi_p2_odt;
wire main_sdram_dfi_p2_reset_n;
reg main_sdram_dfi_p2_act_n = 1\'d1;
wire [31:0] main_sdram_dfi_p2_wrdata;
reg main_sdram_dfi_p2_wrdata_en = 1\'d0;
wire [3:0] main_sdram_dfi_p2_wrdata_mask;
reg main_sdram_dfi_p2_rddata_en = 1\'d0;
wire [31:0] main_sdram_dfi_p2_rddata;
wire main_sdram_dfi_p2_rddata_valid;
reg [13:0] main_sdram_dfi_p3_address = 14\'d0;
reg [2:0] main_sdram_dfi_p3_bank = 3\'d0;
reg main_sdram_dfi_p3_cas_n = 1\'d1;
reg main_sdram_dfi_p3_cs_n = 1\'d1;
reg main_sdram_dfi_p3_ras_n = 1\'d1;
reg main_sdram_dfi_p3_we_n = 1\'d1;
wire main_sdram_dfi_p3_cke;
wire main_sdram_dfi_p3_odt;
wire main_sdram_dfi_p3_reset_n;
reg main_sdram_dfi_p3_act_n = 1\'d1;
wire [31:0] main_sdram_dfi_p3_wrdata;
reg main_sdram_dfi_p3_wrdata_en = 1\'d0;
wire [3:0] main_sdram_dfi_p3_wrdata_mask;
reg main_sdram_dfi_p3_rddata_en = 1\'d0;
wire [31:0] main_sdram_dfi_p3_rddata;
wire main_sdram_dfi_p3_rddata_valid;
reg main_sdram_cmd_valid = 1\'d0;
reg main_sdram_cmd_ready = 1\'d0;
reg main_sdram_cmd_last = 1\'d0;
reg [13:0] main_sdram_cmd_payload_a = 14\'d0;
reg [2:0] main_sdram_cmd_payload_ba = 3\'d0;
reg main_sdram_cmd_payload_cas = 1\'d0;
reg main_sdram_cmd_payload_ras = 1\'d0;
reg main_sdram_cmd_payload_we = 1\'d0;
reg main_sdram_cmd_payload_is_read = 1\'d0;
reg main_sdram_cmd_payload_is_write = 1\'d0;
wire main_sdram_wants_refresh;
wire main_sdram_wants_zqcs;
wire main_sdram_timer_wait;
wire main_sdram_timer_done0;
wire [8:0] main_sdram_timer_count0;
wire main_sdram_timer_done1;
reg [8:0] main_sdram_timer_count1 = 9\'d468;
wire main_sdram_postponer_req_i;
reg main_sdram_postponer_req_o = 1\'d0;
reg main_sdram_postponer_count = 1\'d0;
reg main_sdram_sequencer_start0 = 1\'d0;
wire main_sdram_sequencer_done0;
wire main_sdram_sequencer_start1;
reg main_sdram_sequencer_done1 = 1\'d0;
reg [5:0] main_sdram_sequencer_counter = 6\'d0;
reg main_sdram_sequencer_count = 1\'d0;
wire main_sdram_zqcs_timer_wait;
wire main_sdram_zqcs_timer_done0;
wire [25:0] main_sdram_zqcs_timer_count0;
wire main_sdram_zqcs_timer_done1;
reg [25:0] main_sdram_zqcs_timer_count1 = 26\'d59999999;
reg main_sdram_zqcs_executer_start = 1\'d0;
reg main_sdram_zqcs_executer_done = 1\'d0;
reg [4:0] main_sdram_zqcs_executer_counter = 5\'d0;
wire main_sdram_bankmachine0_req_valid;
wire main_sdram_bankmachine0_req_ready;
wire main_sdram_bankmachine0_req_we;
wire [20:0] main_sdram_bankmachine0_req_addr;
wire main_sdram_bankmachine0_req_lock;
reg main_sdram_bankmachine0_req_wdata_ready = 1\'d0;
reg main_sdram_bankmachine0_req_rdata_valid = 1\'d0;
wire main_sdram_bankmachine0_refresh_req;
reg main_sdram_bankmachine0_refresh_gnt = 1\'d0;
reg main_sdram_bankmachine0_cmd_valid = 1\'d0;
reg main_sdram_bankmachine0_cmd_ready = 1\'d0;
reg [13:0] main_sdram_bankmachine0_cmd_payload_a = 14\'d0;
wire [2:0] main_sdram_bankmachine0_cmd_payload_ba;
reg main_sdram_bankmachine0_cmd_payload_cas = 1\'d0;
reg main_sdram_bankmachine0_cmd_payload_ras = 1\'d0;
reg main_sdram_bankmachine0_cmd_payload_we = 1\'d0;
reg main_sdram_bankmachine0_cmd_payload_is_cmd = 1\'d0;
reg main_sdram_bankmachine0_cmd_payload_is_read = 1\'d0;
reg main_sdram_bankmachine0_cmd_payload_is_write = 1\'d0;
reg main_sdram_bankmachine0_auto_precharge = 1\'d0;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1\'d0;
reg main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1\'d0;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
reg [3:0] main_sdram_bankmachine0_cmd_buffer_lookahead_level = 4\'d0;
reg main_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1\'d0;
reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_produce = 3\'d0;
reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_consume = 3\'d0;
reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3\'d0;
wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine0_cmd_buffer_sink_valid;
wire main_sdram_bankmachine0_cmd_buffer_sink_ready;
wire main_sdram_bankmachine0_cmd_buffer_sink_first;
wire main_sdram_bankmachine0_cmd_buffer_sink_last;
wire main_sdram_bankmachine0_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
reg main_sdram_bankmachine0_cmd_buffer_source_valid = 1\'d0;
wire main_sdram_bankmachine0_cmd_buffer_source_ready;
reg main_sdram_bankmachine0_cmd_buffer_source_first = 1\'d0;
reg main_sdram_bankmachine0_cmd_buffer_source_last = 1\'d0;
reg main_sdram_bankmachine0_cmd_buffer_source_payload_we = 1\'d0;
reg [20:0] main_sdram_bankmachine0_cmd_buffer_source_payload_addr = 21\'d0;
reg [13:0] main_sdram_bankmachine0_row = 14\'d0;
reg main_sdram_bankmachine0_row_opened = 1\'d0;
wire main_sdram_bankmachine0_row_hit;
reg main_sdram_bankmachine0_row_open = 1\'d0;
reg main_sdram_bankmachine0_row_close = 1\'d0;
reg main_sdram_bankmachine0_row_col_n_addr_sel = 1\'d0;
wire main_sdram_bankmachine0_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine0_twtpcon_ready = 1\'d1;
reg [2:0] main_sdram_bankmachine0_twtpcon_count = 3\'d0;
wire main_sdram_bankmachine0_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine0_trccon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine0_trccon_count = 2\'d0;
wire main_sdram_bankmachine0_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine0_trascon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine0_trascon_count = 2\'d0;
wire main_sdram_bankmachine1_req_valid;
wire main_sdram_bankmachine1_req_ready;
wire main_sdram_bankmachine1_req_we;
wire [20:0] main_sdram_bankmachine1_req_addr;
wire main_sdram_bankmachine1_req_lock;
reg main_sdram_bankmachine1_req_wdata_ready = 1\'d0;
reg main_sdram_bankmachine1_req_rdata_valid = 1\'d0;
wire main_sdram_bankmachine1_refresh_req;
reg main_sdram_bankmachine1_refresh_gnt = 1\'d0;
reg main_sdram_bankmachine1_cmd_valid = 1\'d0;
reg main_sdram_bankmachine1_cmd_ready = 1\'d0;
reg [13:0] main_sdram_bankmachine1_cmd_payload_a = 14\'d0;
wire [2:0] main_sdram_bankmachine1_cmd_payload_ba;
reg main_sdram_bankmachine1_cmd_payload_cas = 1\'d0;
reg main_sdram_bankmachine1_cmd_payload_ras = 1\'d0;
reg main_sdram_bankmachine1_cmd_payload_we = 1\'d0;
reg main_sdram_bankmachine1_cmd_payload_is_cmd = 1\'d0;
reg main_sdram_bankmachine1_cmd_payload_is_read = 1\'d0;
reg main_sdram_bankmachine1_cmd_payload_is_write = 1\'d0;
reg main_sdram_bankmachine1_auto_precharge = 1\'d0;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1\'d0;
reg main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1\'d0;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
reg [3:0] main_sdram_bankmachine1_cmd_buffer_lookahead_level = 4\'d0;
reg main_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1\'d0;
reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_produce = 3\'d0;
reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_consume = 3\'d0;
reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3\'d0;
wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine1_cmd_buffer_sink_valid;
wire main_sdram_bankmachine1_cmd_buffer_sink_ready;
wire main_sdram_bankmachine1_cmd_buffer_sink_first;
wire main_sdram_bankmachine1_cmd_buffer_sink_last;
wire main_sdram_bankmachine1_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
reg main_sdram_bankmachine1_cmd_buffer_source_valid = 1\'d0;
wire main_sdram_bankmachine1_cmd_buffer_source_ready;
reg main_sdram_bankmachine1_cmd_buffer_source_first = 1\'d0;
reg main_sdram_bankmachine1_cmd_buffer_source_last = 1\'d0;
reg main_sdram_bankmachine1_cmd_buffer_source_payload_we = 1\'d0;
reg [20:0] main_sdram_bankmachine1_cmd_buffer_source_payload_addr = 21\'d0;
reg [13:0] main_sdram_bankmachine1_row = 14\'d0;
reg main_sdram_bankmachine1_row_opened = 1\'d0;
wire main_sdram_bankmachine1_row_hit;
reg main_sdram_bankmachine1_row_open = 1\'d0;
reg main_sdram_bankmachine1_row_close = 1\'d0;
reg main_sdram_bankmachine1_row_col_n_addr_sel = 1\'d0;
wire main_sdram_bankmachine1_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine1_twtpcon_ready = 1\'d1;
reg [2:0] main_sdram_bankmachine1_twtpcon_count = 3\'d0;
wire main_sdram_bankmachine1_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine1_trccon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine1_trccon_count = 2\'d0;
wire main_sdram_bankmachine1_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine1_trascon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine1_trascon_count = 2\'d0;
wire main_sdram_bankmachine2_req_valid;
wire main_sdram_bankmachine2_req_ready;
wire main_sdram_bankmachine2_req_we;
wire [20:0] main_sdram_bankmachine2_req_addr;
wire main_sdram_bankmachine2_req_lock;
reg main_sdram_bankmachine2_req_wdata_ready = 1\'d0;
reg main_sdram_bankmachine2_req_rdata_valid = 1\'d0;
wire main_sdram_bankmachine2_refresh_req;
reg main_sdram_bankmachine2_refresh_gnt = 1\'d0;
reg main_sdram_bankmachine2_cmd_valid = 1\'d0;
reg main_sdram_bankmachine2_cmd_ready = 1\'d0;
reg [13:0] main_sdram_bankmachine2_cmd_payload_a = 14\'d0;
wire [2:0] main_sdram_bankmachine2_cmd_payload_ba;
reg main_sdram_bankmachine2_cmd_payload_cas = 1\'d0;
reg main_sdram_bankmachine2_cmd_payload_ras = 1\'d0;
reg main_sdram_bankmachine2_cmd_payload_we = 1\'d0;
reg main_sdram_bankmachine2_cmd_payload_is_cmd = 1\'d0;
reg main_sdram_bankmachine2_cmd_payload_is_read = 1\'d0;
reg main_sdram_bankmachine2_cmd_payload_is_write = 1\'d0;
reg main_sdram_bankmachine2_auto_precharge = 1\'d0;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1\'d0;
reg main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1\'d0;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
reg [3:0] main_sdram_bankmachine2_cmd_buffer_lookahead_level = 4\'d0;
reg main_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1\'d0;
reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_produce = 3\'d0;
reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_consume = 3\'d0;
reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3\'d0;
wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine2_cmd_buffer_sink_valid;
wire main_sdram_bankmachine2_cmd_buffer_sink_ready;
wire main_sdram_bankmachine2_cmd_buffer_sink_first;
wire main_sdram_bankmachine2_cmd_buffer_sink_last;
wire main_sdram_bankmachine2_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
reg main_sdram_bankmachine2_cmd_buffer_source_valid = 1\'d0;
wire main_sdram_bankmachine2_cmd_buffer_source_ready;
reg main_sdram_bankmachine2_cmd_buffer_source_first = 1\'d0;
reg main_sdram_bankmachine2_cmd_buffer_source_last = 1\'d0;
reg main_sdram_bankmachine2_cmd_buffer_source_payload_we = 1\'d0;
reg [20:0] main_sdram_bankmachine2_cmd_buffer_source_payload_addr = 21\'d0;
reg [13:0] main_sdram_bankmachine2_row = 14\'d0;
reg main_sdram_bankmachine2_row_opened = 1\'d0;
wire main_sdram_bankmachine2_row_hit;
reg main_sdram_bankmachine2_row_open = 1\'d0;
reg main_sdram_bankmachine2_row_close = 1\'d0;
reg main_sdram_bankmachine2_row_col_n_addr_sel = 1\'d0;
wire main_sdram_bankmachine2_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine2_twtpcon_ready = 1\'d1;
reg [2:0] main_sdram_bankmachine2_twtpcon_count = 3\'d0;
wire main_sdram_bankmachine2_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine2_trccon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine2_trccon_count = 2\'d0;
wire main_sdram_bankmachine2_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine2_trascon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine2_trascon_count = 2\'d0;
wire main_sdram_bankmachine3_req_valid;
wire main_sdram_bankmachine3_req_ready;
wire main_sdram_bankmachine3_req_we;
wire [20:0] main_sdram_bankmachine3_req_addr;
wire main_sdram_bankmachine3_req_lock;
reg main_sdram_bankmachine3_req_wdata_ready = 1\'d0;
reg main_sdram_bankmachine3_req_rdata_valid = 1\'d0;
wire main_sdram_bankmachine3_refresh_req;
reg main_sdram_bankmachine3_refresh_gnt = 1\'d0;
reg main_sdram_bankmachine3_cmd_valid = 1\'d0;
reg main_sdram_bankmachine3_cmd_ready = 1\'d0;
reg [13:0] main_sdram_bankmachine3_cmd_payload_a = 14\'d0;
wire [2:0] main_sdram_bankmachine3_cmd_payload_ba;
reg main_sdram_bankmachine3_cmd_payload_cas = 1\'d0;
reg main_sdram_bankmachine3_cmd_payload_ras = 1\'d0;
reg main_sdram_bankmachine3_cmd_payload_we = 1\'d0;
reg main_sdram_bankmachine3_cmd_payload_is_cmd = 1\'d0;
reg main_sdram_bankmachine3_cmd_payload_is_read = 1\'d0;
reg main_sdram_bankmachine3_cmd_payload_is_write = 1\'d0;
reg main_sdram_bankmachine3_auto_precharge = 1\'d0;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1\'d0;
reg main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1\'d0;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
reg [3:0] main_sdram_bankmachine3_cmd_buffer_lookahead_level = 4\'d0;
reg main_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1\'d0;
reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_produce = 3\'d0;
reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_consume = 3\'d0;
reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3\'d0;
wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine3_cmd_buffer_sink_valid;
wire main_sdram_bankmachine3_cmd_buffer_sink_ready;
wire main_sdram_bankmachine3_cmd_buffer_sink_first;
wire main_sdram_bankmachine3_cmd_buffer_sink_last;
wire main_sdram_bankmachine3_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
reg main_sdram_bankmachine3_cmd_buffer_source_valid = 1\'d0;
wire main_sdram_bankmachine3_cmd_buffer_source_ready;
reg main_sdram_bankmachine3_cmd_buffer_source_first = 1\'d0;
reg main_sdram_bankmachine3_cmd_buffer_source_last = 1\'d0;
reg main_sdram_bankmachine3_cmd_buffer_source_payload_we = 1\'d0;
reg [20:0] main_sdram_bankmachine3_cmd_buffer_source_payload_addr = 21\'d0;
reg [13:0] main_sdram_bankmachine3_row = 14\'d0;
reg main_sdram_bankmachine3_row_opened = 1\'d0;
wire main_sdram_bankmachine3_row_hit;
reg main_sdram_bankmachine3_row_open = 1\'d0;
reg main_sdram_bankmachine3_row_close = 1\'d0;
reg main_sdram_bankmachine3_row_col_n_addr_sel = 1\'d0;
wire main_sdram_bankmachine3_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine3_twtpcon_ready = 1\'d1;
reg [2:0] main_sdram_bankmachine3_twtpcon_count = 3\'d0;
wire main_sdram_bankmachine3_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine3_trccon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine3_trccon_count = 2\'d0;
wire main_sdram_bankmachine3_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine3_trascon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine3_trascon_count = 2\'d0;
wire main_sdram_bankmachine4_req_valid;
wire main_sdram_bankmachine4_req_ready;
wire main_sdram_bankmachine4_req_we;
wire [20:0] main_sdram_bankmachine4_req_addr;
wire main_sdram_bankmachine4_req_lock;
reg main_sdram_bankmachine4_req_wdata_ready = 1\'d0;
reg main_sdram_bankmachine4_req_rdata_valid = 1\'d0;
wire main_sdram_bankmachine4_refresh_req;
reg main_sdram_bankmachine4_refresh_gnt = 1\'d0;
reg main_sdram_bankmachine4_cmd_valid = 1\'d0;
reg main_sdram_bankmachine4_cmd_ready = 1\'d0;
reg [13:0] main_sdram_bankmachine4_cmd_payload_a = 14\'d0;
wire [2:0] main_sdram_bankmachine4_cmd_payload_ba;
reg main_sdram_bankmachine4_cmd_payload_cas = 1\'d0;
reg main_sdram_bankmachine4_cmd_payload_ras = 1\'d0;
reg main_sdram_bankmachine4_cmd_payload_we = 1\'d0;
reg main_sdram_bankmachine4_cmd_payload_is_cmd = 1\'d0;
reg main_sdram_bankmachine4_cmd_payload_is_read = 1\'d0;
reg main_sdram_bankmachine4_cmd_payload_is_write = 1\'d0;
reg main_sdram_bankmachine4_auto_precharge = 1\'d0;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1\'d0;
reg main_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1\'d0;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
reg [3:0] main_sdram_bankmachine4_cmd_buffer_lookahead_level = 4\'d0;
reg main_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1\'d0;
reg [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_produce = 3\'d0;
reg [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_consume = 3\'d0;
reg [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 3\'d0;
wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine4_cmd_buffer_sink_valid;
wire main_sdram_bankmachine4_cmd_buffer_sink_ready;
wire main_sdram_bankmachine4_cmd_buffer_sink_first;
wire main_sdram_bankmachine4_cmd_buffer_sink_last;
wire main_sdram_bankmachine4_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
reg main_sdram_bankmachine4_cmd_buffer_source_valid = 1\'d0;
wire main_sdram_bankmachine4_cmd_buffer_source_ready;
reg main_sdram_bankmachine4_cmd_buffer_source_first = 1\'d0;
reg main_sdram_bankmachine4_cmd_buffer_source_last = 1\'d0;
reg main_sdram_bankmachine4_cmd_buffer_source_payload_we = 1\'d0;
reg [20:0] main_sdram_bankmachine4_cmd_buffer_source_payload_addr = 21\'d0;
reg [13:0] main_sdram_bankmachine4_row = 14\'d0;
reg main_sdram_bankmachine4_row_opened = 1\'d0;
wire main_sdram_bankmachine4_row_hit;
reg main_sdram_bankmachine4_row_open = 1\'d0;
reg main_sdram_bankmachine4_row_close = 1\'d0;
reg main_sdram_bankmachine4_row_col_n_addr_sel = 1\'d0;
wire main_sdram_bankmachine4_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine4_twtpcon_ready = 1\'d1;
reg [2:0] main_sdram_bankmachine4_twtpcon_count = 3\'d0;
wire main_sdram_bankmachine4_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine4_trccon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine4_trccon_count = 2\'d0;
wire main_sdram_bankmachine4_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine4_trascon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine4_trascon_count = 2\'d0;
wire main_sdram_bankmachine5_req_valid;
wire main_sdram_bankmachine5_req_ready;
wire main_sdram_bankmachine5_req_we;
wire [20:0] main_sdram_bankmachine5_req_addr;
wire main_sdram_bankmachine5_req_lock;
reg main_sdram_bankmachine5_req_wdata_ready = 1\'d0;
reg main_sdram_bankmachine5_req_rdata_valid = 1\'d0;
wire main_sdram_bankmachine5_refresh_req;
reg main_sdram_bankmachine5_refresh_gnt = 1\'d0;
reg main_sdram_bankmachine5_cmd_valid = 1\'d0;
reg main_sdram_bankmachine5_cmd_ready = 1\'d0;
reg [13:0] main_sdram_bankmachine5_cmd_payload_a = 14\'d0;
wire [2:0] main_sdram_bankmachine5_cmd_payload_ba;
reg main_sdram_bankmachine5_cmd_payload_cas = 1\'d0;
reg main_sdram_bankmachine5_cmd_payload_ras = 1\'d0;
reg main_sdram_bankmachine5_cmd_payload_we = 1\'d0;
reg main_sdram_bankmachine5_cmd_payload_is_cmd = 1\'d0;
reg main_sdram_bankmachine5_cmd_payload_is_read = 1\'d0;
reg main_sdram_bankmachine5_cmd_payload_is_write = 1\'d0;
reg main_sdram_bankmachine5_auto_precharge = 1\'d0;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1\'d0;
reg main_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1\'d0;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
reg [3:0] main_sdram_bankmachine5_cmd_buffer_lookahead_level = 4\'d0;
reg main_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1\'d0;
reg [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_produce = 3\'d0;
reg [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_consume = 3\'d0;
reg [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 3\'d0;
wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine5_cmd_buffer_sink_valid;
wire main_sdram_bankmachine5_cmd_buffer_sink_ready;
wire main_sdram_bankmachine5_cmd_buffer_sink_first;
wire main_sdram_bankmachine5_cmd_buffer_sink_last;
wire main_sdram_bankmachine5_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
reg main_sdram_bankmachine5_cmd_buffer_source_valid = 1\'d0;
wire main_sdram_bankmachine5_cmd_buffer_source_ready;
reg main_sdram_bankmachine5_cmd_buffer_source_first = 1\'d0;
reg main_sdram_bankmachine5_cmd_buffer_source_last = 1\'d0;
reg main_sdram_bankmachine5_cmd_buffer_source_payload_we = 1\'d0;
reg [20:0] main_sdram_bankmachine5_cmd_buffer_source_payload_addr = 21\'d0;
reg [13:0] main_sdram_bankmachine5_row = 14\'d0;
reg main_sdram_bankmachine5_row_opened = 1\'d0;
wire main_sdram_bankmachine5_row_hit;
reg main_sdram_bankmachine5_row_open = 1\'d0;
reg main_sdram_bankmachine5_row_close = 1\'d0;
reg main_sdram_bankmachine5_row_col_n_addr_sel = 1\'d0;
wire main_sdram_bankmachine5_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine5_twtpcon_ready = 1\'d1;
reg [2:0] main_sdram_bankmachine5_twtpcon_count = 3\'d0;
wire main_sdram_bankmachine5_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine5_trccon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine5_trccon_count = 2\'d0;
wire main_sdram_bankmachine5_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine5_trascon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine5_trascon_count = 2\'d0;
wire main_sdram_bankmachine6_req_valid;
wire main_sdram_bankmachine6_req_ready;
wire main_sdram_bankmachine6_req_we;
wire [20:0] main_sdram_bankmachine6_req_addr;
wire main_sdram_bankmachine6_req_lock;
reg main_sdram_bankmachine6_req_wdata_ready = 1\'d0;
reg main_sdram_bankmachine6_req_rdata_valid = 1\'d0;
wire main_sdram_bankmachine6_refresh_req;
reg main_sdram_bankmachine6_refresh_gnt = 1\'d0;
reg main_sdram_bankmachine6_cmd_valid = 1\'d0;
reg main_sdram_bankmachine6_cmd_ready = 1\'d0;
reg [13:0] main_sdram_bankmachine6_cmd_payload_a = 14\'d0;
wire [2:0] main_sdram_bankmachine6_cmd_payload_ba;
reg main_sdram_bankmachine6_cmd_payload_cas = 1\'d0;
reg main_sdram_bankmachine6_cmd_payload_ras = 1\'d0;
reg main_sdram_bankmachine6_cmd_payload_we = 1\'d0;
reg main_sdram_bankmachine6_cmd_payload_is_cmd = 1\'d0;
reg main_sdram_bankmachine6_cmd_payload_is_read = 1\'d0;
reg main_sdram_bankmachine6_cmd_payload_is_write = 1\'d0;
reg main_sdram_bankmachine6_auto_precharge = 1\'d0;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1\'d0;
reg main_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1\'d0;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
reg [3:0] main_sdram_bankmachine6_cmd_buffer_lookahead_level = 4\'d0;
reg main_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1\'d0;
reg [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_produce = 3\'d0;
reg [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_consume = 3\'d0;
reg [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 3\'d0;
wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine6_cmd_buffer_sink_valid;
wire main_sdram_bankmachine6_cmd_buffer_sink_ready;
wire main_sdram_bankmachine6_cmd_buffer_sink_first;
wire main_sdram_bankmachine6_cmd_buffer_sink_last;
wire main_sdram_bankmachine6_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
reg main_sdram_bankmachine6_cmd_buffer_source_valid = 1\'d0;
wire main_sdram_bankmachine6_cmd_buffer_source_ready;
reg main_sdram_bankmachine6_cmd_buffer_source_first = 1\'d0;
reg main_sdram_bankmachine6_cmd_buffer_source_last = 1\'d0;
reg main_sdram_bankmachine6_cmd_buffer_source_payload_we = 1\'d0;
reg [20:0] main_sdram_bankmachine6_cmd_buffer_source_payload_addr = 21\'d0;
reg [13:0] main_sdram_bankmachine6_row = 14\'d0;
reg main_sdram_bankmachine6_row_opened = 1\'d0;
wire main_sdram_bankmachine6_row_hit;
reg main_sdram_bankmachine6_row_open = 1\'d0;
reg main_sdram_bankmachine6_row_close = 1\'d0;
reg main_sdram_bankmachine6_row_col_n_addr_sel = 1\'d0;
wire main_sdram_bankmachine6_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine6_twtpcon_ready = 1\'d1;
reg [2:0] main_sdram_bankmachine6_twtpcon_count = 3\'d0;
wire main_sdram_bankmachine6_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine6_trccon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine6_trccon_count = 2\'d0;
wire main_sdram_bankmachine6_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine6_trascon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine6_trascon_count = 2\'d0;
wire main_sdram_bankmachine7_req_valid;
wire main_sdram_bankmachine7_req_ready;
wire main_sdram_bankmachine7_req_we;
wire [20:0] main_sdram_bankmachine7_req_addr;
wire main_sdram_bankmachine7_req_lock;
reg main_sdram_bankmachine7_req_wdata_ready = 1\'d0;
reg main_sdram_bankmachine7_req_rdata_valid = 1\'d0;
wire main_sdram_bankmachine7_refresh_req;
reg main_sdram_bankmachine7_refresh_gnt = 1\'d0;
reg main_sdram_bankmachine7_cmd_valid = 1\'d0;
reg main_sdram_bankmachine7_cmd_ready = 1\'d0;
reg [13:0] main_sdram_bankmachine7_cmd_payload_a = 14\'d0;
wire [2:0] main_sdram_bankmachine7_cmd_payload_ba;
reg main_sdram_bankmachine7_cmd_payload_cas = 1\'d0;
reg main_sdram_bankmachine7_cmd_payload_ras = 1\'d0;
reg main_sdram_bankmachine7_cmd_payload_we = 1\'d0;
reg main_sdram_bankmachine7_cmd_payload_is_cmd = 1\'d0;
reg main_sdram_bankmachine7_cmd_payload_is_read = 1\'d0;
reg main_sdram_bankmachine7_cmd_payload_is_write = 1\'d0;
reg main_sdram_bankmachine7_auto_precharge = 1\'d0;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1\'d0;
reg main_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1\'d0;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
reg [3:0] main_sdram_bankmachine7_cmd_buffer_lookahead_level = 4\'d0;
reg main_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1\'d0;
reg [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_produce = 3\'d0;
reg [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_consume = 3\'d0;
reg [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 3\'d0;
wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine7_cmd_buffer_sink_valid;
wire main_sdram_bankmachine7_cmd_buffer_sink_ready;
wire main_sdram_bankmachine7_cmd_buffer_sink_first;
wire main_sdram_bankmachine7_cmd_buffer_sink_last;
wire main_sdram_bankmachine7_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
reg main_sdram_bankmachine7_cmd_buffer_source_valid = 1\'d0;
wire main_sdram_bankmachine7_cmd_buffer_source_ready;
reg main_sdram_bankmachine7_cmd_buffer_source_first = 1\'d0;
reg main_sdram_bankmachine7_cmd_buffer_source_last = 1\'d0;
reg main_sdram_bankmachine7_cmd_buffer_source_payload_we = 1\'d0;
reg [20:0] main_sdram_bankmachine7_cmd_buffer_source_payload_addr = 21\'d0;
reg [13:0] main_sdram_bankmachine7_row = 14\'d0;
reg main_sdram_bankmachine7_row_opened = 1\'d0;
wire main_sdram_bankmachine7_row_hit;
reg main_sdram_bankmachine7_row_open = 1\'d0;
reg main_sdram_bankmachine7_row_close = 1\'d0;
reg main_sdram_bankmachine7_row_col_n_addr_sel = 1\'d0;
wire main_sdram_bankmachine7_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine7_twtpcon_ready = 1\'d1;
reg [2:0] main_sdram_bankmachine7_twtpcon_count = 3\'d0;
wire main_sdram_bankmachine7_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine7_trccon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine7_trccon_count = 2\'d0;
wire main_sdram_bankmachine7_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine7_trascon_ready = 1\'d1;
reg [1:0] main_sdram_bankmachine7_trascon_count = 2\'d0;
wire main_sdram_ras_allowed;
wire main_sdram_cas_allowed;
reg main_sdram_choose_cmd_want_reads = 1\'d0;
reg main_sdram_choose_cmd_want_writes = 1\'d0;
reg main_sdram_choose_cmd_want_cmds = 1\'d0;
reg main_sdram_choose_cmd_want_activates = 1\'d0;
wire main_sdram_choose_cmd_cmd_valid;
reg main_sdram_choose_cmd_cmd_ready = 1\'d0;
wire [13:0] main_sdram_choose_cmd_cmd_payload_a;
wire [2:0] main_sdram_choose_cmd_cmd_payload_ba;
reg main_sdram_choose_cmd_cmd_payload_cas = 1\'d0;
reg main_sdram_choose_cmd_cmd_payload_ras = 1\'d0;
reg main_sdram_choose_cmd_cmd_payload_we = 1\'d0;
wire main_sdram_choose_cmd_cmd_payload_is_cmd;
wire main_sdram_choose_cmd_cmd_payload_is_read;
wire main_sdram_choose_cmd_cmd_payload_is_write;
reg [7:0] main_sdram_choose_cmd_valids = 8\'d0;
wire [7:0] main_sdram_choose_cmd_request;
reg [2:0] main_sdram_'b'choose_cmd_grant = 3\'d0;
wire main_sdram_choose_cmd_ce;
reg main_sdram_choose_req_want_reads = 1\'d0;
reg main_sdram_choose_req_want_writes = 1\'d0;
reg main_sdram_choose_req_want_cmds = 1\'d0;
reg main_sdram_choose_req_want_activates = 1\'d0;
wire main_sdram_choose_req_cmd_valid;
reg main_sdram_choose_req_cmd_ready = 1\'d0;
wire [13:0] main_sdram_choose_req_cmd_payload_a;
wire [2:0] main_sdram_choose_req_cmd_payload_ba;
reg main_sdram_choose_req_cmd_payload_cas = 1\'d0;
reg main_sdram_choose_req_cmd_payload_ras = 1\'d0;
reg main_sdram_choose_req_cmd_payload_we = 1\'d0;
wire main_sdram_choose_req_cmd_payload_is_cmd;
wire main_sdram_choose_req_cmd_payload_is_read;
wire main_sdram_choose_req_cmd_payload_is_write;
reg [7:0] main_sdram_choose_req_valids = 8\'d0;
wire [7:0] main_sdram_choose_req_request;
reg [2:0] main_sdram_choose_req_grant = 3\'d0;
wire main_sdram_choose_req_ce;
reg [13:0] main_sdram_nop_a = 14\'d0;
reg [2:0] main_sdram_nop_ba = 3\'d0;
reg [1:0] main_sdram_steerer_sel0 = 2\'d0;
reg [1:0] main_sdram_steerer_sel1 = 2\'d0;
reg [1:0] main_sdram_steerer_sel2 = 2\'d0;
reg [1:0] main_sdram_steerer_sel3 = 2\'d0;
reg main_sdram_steerer0 = 1\'d1;
reg main_sdram_steerer1 = 1\'d1;
reg main_sdram_steerer2 = 1\'d1;
reg main_sdram_steerer3 = 1\'d1;
reg main_sdram_steerer4 = 1\'d1;
reg main_sdram_steerer5 = 1\'d1;
reg main_sdram_steerer6 = 1\'d1;
reg main_sdram_steerer7 = 1\'d1;
wire main_sdram_trrdcon_valid;
(* dont_touch = "true" *) reg main_sdram_trrdcon_ready = 1\'d1;
reg main_sdram_trrdcon_count = 1\'d0;
wire main_sdram_tfawcon_valid;
(* dont_touch = "true" *) reg main_sdram_tfawcon_ready = 1\'d1;
wire [1:0] main_sdram_tfawcon_count;
reg [3:0] main_sdram_tfawcon_window = 4\'d0;
wire main_sdram_tccdcon_valid;
(* dont_touch = "true" *) reg main_sdram_tccdcon_ready = 1\'d1;
reg main_sdram_tccdcon_count = 1\'d0;
wire main_sdram_twtrcon_valid;
(* dont_touch = "true" *) reg main_sdram_twtrcon_ready = 1\'d1;
reg [2:0] main_sdram_twtrcon_count = 3\'d0;
wire main_sdram_read_available;
wire main_sdram_write_available;
reg main_sdram_en0 = 1\'d0;
wire main_sdram_max_time0;
reg [4:0] main_sdram_time0 = 5\'d0;
reg main_sdram_en1 = 1\'d0;
wire main_sdram_max_time1;
reg [3:0] main_sdram_time1 = 4\'d0;
wire main_sdram_go_to_refresh;
reg main_port_cmd_valid = 1\'d0;
wire main_port_cmd_ready;
reg main_port_cmd_payload_we = 1\'d0;
reg [23:0] main_port_cmd_payload_addr = 24\'d0;
wire main_port_wdata_valid;
wire main_port_wdata_ready;
wire main_port_wdata_first;
wire main_port_wdata_last;
wire [127:0] main_port_wdata_payload_data;
wire [15:0] main_port_wdata_payload_we;
wire main_port_rdata_valid;
wire main_port_rdata_ready;
reg main_port_rdata_first = 1\'d0;
reg main_port_rdata_last = 1\'d0;
wire [127:0] main_port_rdata_payload_data;
wire [29:0] main_interface1_wb_sdram_adr;
wire [31:0] main_interface1_wb_sdram_dat_w;
wire [31:0] main_interface1_wb_sdram_dat_r;
wire [3:0] main_interface1_wb_sdram_sel;
wire main_interface1_wb_sdram_cyc;
wire main_interface1_wb_sdram_stb;
wire main_interface1_wb_sdram_ack;
wire main_interface1_wb_sdram_we;
wire [2:0] main_interface1_wb_sdram_cti;
wire [1:0] main_interface1_wb_sdram_bte;
wire main_interface1_wb_sdram_err;
wire [29:0] main_adr;
wire [127:0] main_dat_w;
wire [127:0] main_dat_r;
wire [15:0] main_sel;
reg main_cyc = 1\'d0;
reg main_stb = 1\'d0;
reg main_ack = 1\'d0;
reg main_we = 1\'d0;
wire [8:0] main_data_port_adr;
wire [127:0] main_data_port_dat_r;
reg [15:0] main_data_port_we = 16\'d0;
reg [127:0] main_data_port_dat_w = 128\'d0;
reg main_write_from_slave = 1\'d0;
reg [1:0] main_adr_offset_r = 2\'d0;
wire [8:0] main_tag_port_adr;
wire [23:0] main_tag_port_dat_r;
reg main_tag_port_we = 1\'d0;
wire [23:0] main_tag_port_dat_w;
wire [22:0] main_tag_do_tag;
wire main_tag_do_dirty;
wire [22:0] main_tag_di_tag;
reg main_tag_di_dirty = 1\'d0;
reg main_word_clr = 1\'d0;
reg main_word_inc = 1\'d0;
wire main_wdata_converter_sink_valid;
wire main_wdata_converter_sink_ready;
reg main_wdata_converter_sink_first = 1\'d0;
reg main_wdata_converter_sink_last = 1\'d0;
wire [127:0] main_wdata_converter_sink_payload_data;
wire [15:0] main_wdata_converter_sink_payload_we;
wire main_wdata_converter_source_valid;
wire main_wdata_converter_source_ready;
wire main_wdata_converter_source_first;
wire main_wdata_converter_source_last;
wire [127:0] main_wdata_converter_source_payload_data;
wire [15:0] main_wdata_converter_source_payload_we;
wire main_wdata_converter_converter_sink_valid;
wire main_wdata_converter_converter_sink_ready;
wire main_wdata_converter_converter_sink_first;
wire main_wdata_converter_converter_sink_last;
wire [143:0] main_wdata_converter_converter_sink_payload_data;
wire main_wdata_converter_converter_source_valid;
wire main_wdata_converter_converter_source_ready;
wire main_wdata_converter_converter_source_first;
wire main_wdata_converter_converter_source_last;
wire [143:0] main_wdata_converter_converter_source_payload_data;
wire main_wdata_converter_converter_source_payload_valid_token_count;
wire main_wdata_converter_source_source_valid;
wire main_wdata_converter_source_source_ready;
wire main_wdata_converter_source_source_first;
wire main_wdata_converter_source_source_last;
wire [143:0] main_wdata_converter_source_source_payload_data;
wire main_rdata_converter_sink_valid;
wire main_rdata_converter_sink_ready;
wire main_rdata_converter_sink_first;
wire main_rdata_converter_sink_last;
wire [127:0] main_rdata_converter_sink_payload_data;
wire main_rdata_converter_source_valid;
wire main_rdata_converter_source_ready;
wire main_rdata_converter_source_first;
wire main_rdata_converter_source_last;
wire [127:0] main_rdata_converter_source_payload_data;
wire main_rdata_converter_converter_sink_valid;
wire main_rdata_converter_converter_sink_ready;
wire main_rdata_converter_converter_sink_first;
wire main_rdata_converter_converter_sink_last;
wire [127:0] main_rdata_converter_converter_sink_payload_data;
wire main_rdata_converter_converter_source_valid;
wire main_rdata_converter_converter_source_ready;
wire main_rdata_converter_converter_source_first;
wire main_rdata_converter_converter_source_last;
wire [127:0] main_rdata_converter_converter_source_payload_data;
wire main_rdata_converter_converter_source_payload_valid_token_count;
wire main_rdata_converter_source_source_valid;
wire main_rdata_converter_source_source_ready;
wire main_rdata_converter_source_source_first;
wire main_rdata_converter_source_source_last;
wire [127:0] main_rdata_converter_source_source_payload_data;
reg main_count = 1\'d0;
reg builder_wb2csr_state = 1\'d0;
reg builder_wb2csr_next_state = 1\'d0;
wire builder_pll_fb;
reg [1:0] builder_refresher_state = 2\'d0;
reg [1:0] builder_refresher_next_state = 2\'d0;
reg [2:0] builder_bankmachine0_state = 3\'d0;
reg [2:0] builder_bankmachine0_next_state = 3\'d0;
reg [2:0] builder_bankmachine1_state = 3\'d0;
reg [2:0] builder_bankmachine1_next_state = 3\'d0;
reg [2:0] builder_bankmachine2_state = 3\'d0;
reg [2:0] builder_bankmachine2_next_state = 3\'d0;
reg [2:0] builder_bankmachine3_state = 3\'d0;
reg [2:0] builder_bankmachine3_next_state = 3\'d0;
reg [2:0] builder_bankmachine4_state = 3\'d0;
reg [2:0] builder_bankmachine4_next_state = 3\'d0;
reg [2:0] builder_bankmachine5_state = 3\'d0;
reg [2:0] builder_bankmachine5_next_state = 3\'d0;
reg [2:0] builder_bankmachine6_state = 3\'d0;
reg [2:0] builder_bankmachine6_next_state = 3\'d0;
reg [2:0] builder_bankmachine7_state = 3\'d0;
reg [2:0] builder_bankmachine7_next_state = 3\'d0;
reg [3:0] builder_multiplexer_state = 4\'d0;
reg [3:0] builder_multiplexer_next_state = 4\'d0;
wire builder_roundrobin0_request;
wire builder_roundrobin0_grant;
wire builder_roundrobin0_ce;
wire builder_roundrobin1_request;
wire builder_roundrobin1_grant;
wire builder_roundrobin1_ce;
wire builder_roundrobin2_request;
wire builder_roundrobin2_grant;
wire builder_roundrobin2_ce;
wire builder_roundrobin3_request;
wire builder_roundrobin3_grant;
wire builder_roundrobin3_ce;
wire builder_roundrobin4_request;
wire builder_roundrobin4_grant;
wire builder_roundrobin4_ce;
wire builder_roundrobin5_request;
wire builder_roundrobin5_grant;
wire builder_roundrobin5_ce;
wire builder_roundrobin6_request;
wire builder_roundrobin6_grant;
wire builder_roundrobin6_ce;
wire builder_roundrobin7_request;
wire builder_roundrobin7_grant;
wire builder_roundrobin7_ce;
reg [2:0] builder_rbank = 3\'d0;
reg [2:0] builder_wbank = 3\'d0;
reg builder_locked0 = 1\'d0;
reg builder_locked1 = 1\'d0;
reg builder_locked2 = 1\'d0;
reg builder_locked3 = 1\'d0;
reg builder_locked4 = 1\'d0;
reg builder_locked5 = 1\'d0;
reg builder_locked6 = 1\'d0;
reg builder_locked7 = 1\'d0;
reg builder_new_master_wdata_ready0 = 1\'d0;
reg builder_new_master_wdata_ready1 = 1\'d0;
reg builder_new_master_wdata_ready2 = 1\'d0;
reg builder_new_master_rdata_valid0 = 1\'d0;
reg builder_new_master_rdata_valid1 = 1\'d0;
reg builder_new_master_rdata_valid2 = 1\'d0;
reg builder_new_master_rdata_valid3 = 1\'d0;
reg builder_new_master_rdata_valid4 = 1\'d0;
reg builder_new_master_rdata_valid5 = 1\'d0;
reg builder_new_master_rdata_valid6 = 1\'d0;
reg builder_new_master_rdata_valid7 = 1\'d0;
reg builder_new_master_rdata_valid8 = 1\'d0;
reg builder_new_master_rdata_valid9 = 1\'d0;
reg [1:0] builder_fullmemorywe_state = 2\'d0;
reg [1:0] builder_fullmemorywe_next_state = 2\'d0;
reg [1:0] builder_litedramwishbone2native_state = 2\'d0;
reg [1:0] builder_litedramwishbone2native_next_state = 2\'d0;
reg main_count_next_value = 1\'d0;
reg main_count_next_value_ce = 1\'d0;
wire builder_wb_sdram_con_request;
wire builder_wb_sdram_con_grant;
wire [29:0] builder_minsoc_shared_adr;
wire [31:0] builder_minsoc_shared_dat_w;
reg [31:0] builder_minsoc_shared_dat_r = 32\'d0;
wire [3:0] builder_minsoc_shared_sel;
wire builder_minsoc_shared_cyc;
wire builder_minsoc_shared_stb;
reg builder_minsoc_shared_ack = 1\'d0;
wire builder_minsoc_shared_we;
wire [2:0] builder_minsoc_shared_cti;
wire [1:0] builder_minsoc_shared_bte;
wire builder_minsoc_shared_err;
wire [1:0] builder_minsoc_request;
reg builder_minsoc_grant = 1\'d0;
reg [3:0] builder_minsoc_slave_sel = 4\'d0;
reg [3:0] builder_minsoc_slave_sel_r = 4\'d0;
reg builder_minsoc_error = 1\'d0;
wire builder_minsoc_wait;
wire builder_minsoc_done;
reg [19:0] builder_minsoc_count = 20\'d1000000;
wire [13:0] builder_minsoc_interface0_bank_bus_adr;
wire builder_minsoc_interface0_bank_bus_we;
wire [7:0] builder_minsoc_interface0_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface0_bank_bus_dat_r = 8\'d0;
wire builder_minsoc_csrbank0_reset0_re;
wire builder_minsoc_csrbank0_reset0_r;
wire builder_minsoc_csrbank0_reset0_we;
wire builder_minsoc_csrbank0_reset0_w;
wire builder_minsoc_csrbank0_scratch3_re;
wire [7:0] builder_minsoc_csrbank0_scratch3_r;
wire builder_minsoc_csrbank0_scratch3_we;
wire [7:0] builder_minsoc_csrbank0_scratch3_w;
wire builder_minsoc_csrbank0_scratch2_re;
wire [7:0] builder_minsoc_csrbank0_scratch2_r;
wire builder_minsoc_csrbank0_scratch2_we;
wire [7:0] builder_minsoc_csrbank0_scratch2_w;
wire builder_minsoc_csrbank0_scratch1_re;
wire [7:0] builder_minsoc_csrbank0_scratch1_r;
wire builder_minsoc_csrbank0_scratch1_we;
wire [7:0] builder_minsoc_csrbank0_scratch1_w;
wire builder_minsoc_csrbank0_scratch0_re;
wire [7:0] builder_minsoc_csrbank0_scratch0_r;
wire builder_minsoc_csrbank0_scratch0_we;
wire [7:0] builder_minsoc_csrbank0_scratch0_w;
wire builder_minsoc_csrbank0_bus_errors3_re;
wire [7:0] builder_minsoc_csrbank0_bus_errors3_r;
wire builder_minsoc_csrbank0_bus_errors3_we;
wire [7:0] builder_minsoc_csrbank0_bus_errors3_w;
wire builder_minsoc_csrbank0_bus_errors2_re;
wire [7:0] builder_minsoc_csrbank0_bus_errors2_r;
wire builder_minsoc_csrbank0_bus_errors2_we;
wire [7:0] builder_minsoc_csrbank0_bus_errors2_w;
wire builder_minsoc_csrbank0_bus_errors1_re;
wire [7:0] builder_minsoc_csrbank0_bus_errors1_r;
wire builder_minsoc_csrbank0_bus_errors1_we;
wire [7:0] builder_minsoc_csrbank0_bus_errors1_w;
wire builder_minsoc_csrbank0_bus_errors0_re;
wire [7:0] builder_minsoc_csrbank0_bus_errors0_r;
wire builder_minsoc_csrbank0_bus_errors0_we;
wire [7:0] builder_minsoc_csrbank0_bus_errors0_w;
wire builder_minsoc_csrbank0_sel;
wire [13:0] builder_minsoc_interface1_bank_bus_adr;
wire builder_minsoc_interface1_bank_bus_we;
wire [7:0] builder_minsoc_interface1_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface1_bank_bus_dat_r = 8\'d0;
wire builder_minsoc_csrbank1_half_sys8x_taps0_re;
wire [4:0] builder_minsoc_csrbank1_half_sys8x_taps0_r;
wire builder_minsoc_csrbank1_half_sys8x_taps0_we;
wire [4:0] builder_minsoc_csrbank1_half_sys8x_taps0_w;
wire builder_minsoc_csrbank1_dly_sel0_re;
wire [1:0] builder_minsoc_csrbank1_dly_sel0_r;
wire builder_minsoc_csrbank1_dly_sel0_we;
wire [1:0] builder_minsoc_csrbank1_dly_sel0_w;
wire builder_minsoc_csrbank1_sel;
wire [13:0] builder_minsoc_interface2_bank_bus_adr;
wire builder_minsoc_interface2_bank_bus_we;
wire [7:0] builder_minsoc_interface2_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface2_bank_bus_dat_r = 8\'d0;
wire builder_minsoc_csrbank2_dfii_control0_re;
wire [3:0] builder_minsoc_csrbank2_dfii_control0_r;
wire builder_minsoc_csrbank2_dfii_control0_we;
wire [3:0] builder_minsoc_csrbank2_dfii_control0_w;
wire builder_minsoc_csrbank2_dfii_pi0_command0_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi0_command0_r;
wire builder_minsoc_csrbank2_dfii_pi0_command0_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi0_command0_w;
wire builder_minsoc_csrbank2_dfii_pi0_address1_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi0_address1_r;
wire builder_minsoc_csrbank2_dfii_pi0_address1_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi0_address1_w;
wire builder_minsoc_csrbank2_dfii_pi0_address0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_address0_r;
wire builder_minsoc_csrbank2_dfii_pi0_address0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_address0_w;
wire builder_minsoc_csrbank2_dfii_pi0_baddress0_re;
wire [2:0] builder_minsoc_csrbank2_dfii_pi0_baddress0_r;
wire builder_minsoc_csrbank2_dfii_pi0_baddress0_we;
wire [2:0] builder_minsoc_csrbank2_dfii_pi0_baddress0_w;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata3_r;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata3_w;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata2_r;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata2_w;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata1_r;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata1_w;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata0_r;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata0_w;
wire builder_minsoc_csrbank2_dfii_pi0_rddata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata3_r;
wire builder_minsoc_csrbank2_dfii_pi0_rddata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata3_w;
wire builder_minsoc_csrbank2_dfii_pi0_rddata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata2_r;
wire builder_minsoc_csrbank2_dfii_pi0_rddata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata2_w;
wire builder_minsoc_csrbank2_dfii_pi0_rddata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata1_r;
wire builder_minsoc_csrbank2_dfii_pi0_rddata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata1_w;
wire builder_minsoc_csrbank2_dfii_pi0_rddata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata0_r;
wire builder_minsoc_csrbank2_dfii_pi0_rddata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata0_w;
wire builder_minsoc_csrbank2_dfii_pi1_command0_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi1_command0_r;
wire builder_minsoc_csrbank2_dfii_pi1_command0_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi1_command0_w;
wire builder_minsoc_csrbank2_dfii_pi1_address1_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi1_address1_r;
wire builder_minsoc_csrbank2_dfii_pi1_address1_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi1_address1_w;
wire builder_minsoc_csrbank2_dfii_pi1_address0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_address0_r;
wire builder_minsoc_csrbank2_dfii_pi1_address0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_address0_w;
wire builder_minsoc_csrbank2_dfii_pi1_baddress0_re;
wire [2:0] builder_minsoc_csrbank2_dfii_pi1_baddress0_r;
wire builder_minsoc_csrbank2_dfii_pi1_baddress0_we;
wire [2:0] builder_minsoc_csrbank2_dfii_pi1_baddress0_w;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata3_r;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata3_w;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata2_r;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata2_w;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata1_r;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata1_w;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata0_r;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata0_w;
wire builder_minsoc_csrbank2_dfii_pi1_rddata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata3_r;
wire builder_minsoc_csrbank2_dfii_pi1_rddata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata3_w;
wire builder_minsoc_csrbank2_dfii_pi1_rddata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata2_r;
wire builder_minsoc_csrbank2_dfii_pi1_rddata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata2_w;
wire builder_minsoc_csrbank2_dfii_pi1_rddata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata1_r;
wire builder_minsoc_csrbank2_dfii_pi1_rddata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata1_w;
wire builder_minsoc_csrbank2_dfii_pi1_rddata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata0_r;
wire builder_minsoc_csrbank2_dfii_pi1_rddata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata0_w;
wire builder_minsoc_csrbank2_dfii_pi2_command0_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi2_command0_r;
wire builder_minsoc_csrbank2_dfii_pi2_command0_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi2_command0_w;
wire builder_minsoc_csrbank2_dfii_pi2_address1_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi2_address1_r;
wire builder_minsoc_csrbank2_dfii_pi2_address1_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi2_address1_w;
wire builder_minsoc_csrbank2_dfii_pi2_address0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_address0_r;
wire builder_minsoc_csrbank2_dfii_pi2_address0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_address0_w;
wire builder_minsoc_csrbank2_dfii_pi2_baddress0_re;
wire [2:0] builder_minsoc_csrbank2_dfii_pi2_baddress0_r;
wire builder_minsoc_csrbank2_dfii_pi2_baddress0_we;
wire [2:0] builder_minsoc_csrbank2_dfii_pi2_baddress0_w;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata3_r;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata3_w;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata2_r;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata2_w;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata1_r;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata1_w;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata0_r;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata0_w;
wire builder_minsoc_csrbank2_dfii_pi2_rddata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata3_r;
wire builder_minsoc_csrbank2_dfii_pi2_rddata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata3_w;
wire builder_minsoc_csrbank2_dfii_pi2_rddata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata2_r;
wire builder_minsoc_csrbank2_dfii_pi2_rddata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata2_w;
wire builder_minsoc_csrbank2_dfii_pi2_rddata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata1_r;
wire builder_minsoc_csrbank2_dfii_pi2_rddata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata1_w;
wire builder_minsoc_csrbank2_dfii_pi2_rddata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata0_r;
wire builder_minsoc_csrbank2_dfii_pi2_rddata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata0_w;
wire builder_minsoc_csrbank2_dfii_pi3_command0_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi3_command0_r;
wire builder_minsoc_csrbank2_dfii_pi3_command0_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi3_command0_w;
wire builder_minsoc_csrbank2_dfii_pi3_address1_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi3_address1_r;
wire builder_minsoc_csrbank2_dfii_pi3_address1_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi3_address1_w;
wire builder_minsoc_csrbank2_dfii_pi3_address0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_address0_r;
wire builder_minsoc_csrbank2_dfii_pi3_address0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_address0_w;
wire builder_minsoc_csrbank2_dfii_pi3_baddress0_re;
wire [2:0] builder_minsoc_csrbank2_dfii_pi3_baddress0_r;
wire builder_minsoc_csrbank2_dfii_pi3_baddress0_we;
wire [2:0] builder_minsoc_csrbank2_dfii_pi3_baddress0_w;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata3_r;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata3_w;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata2_r;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata2_w;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata1_r;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata1_w;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata0_r;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata0_w;
wire builder_minsoc_csrbank2_dfii_pi3_rddata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata3_r;
wire builder_minsoc_csrbank2_dfii_pi3_rddata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata3_w;
wire builder_minsoc_csrbank2_dfii_pi3_rddata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata2_r;
wire builder_minsoc_csrbank2_dfii_pi3_rddata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata2_w;
wire builder_minsoc_csrbank2_dfii_pi3_rddata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata1_r;
wire builder_minsoc_csrbank2_dfii_pi3_rddata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata1_w;
wire builder_minsoc_csrbank2_dfii_pi3_rddata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata0_r;
wire builder_minsoc_csrbank2_dfii_pi3_rddata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata0_w;
wire builder_minsoc_csrbank2_sel;
wire [13:0] builder_minsoc_interface3_bank_bus_adr;
wire builder_minsoc_interface3_bank_bus_we;
wire [7:0] builder_minsoc_interface3_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface3_bank_bus_dat_r = 8\'d0;
wire builder_minsoc_csrbank3_load3_re;
wire [7:0] builder_minsoc_csrbank3_load3_r;
wire builder_minsoc_csrbank3_load3_we;
wire [7:0] builder_minsoc_csrbank3_load3_w;
wire builder_minsoc_csrbank3_load2_re;
wire [7:0] builder_minsoc_csrbank3_load2_r;
wire builder_minsoc_csrbank3_load2_we;
wire [7:0] builder_minsoc_csrbank3_load2_w;
wire builder_minsoc_csrbank3_load1_re;
wire [7:0] builder_minsoc_csrbank3_load1_r;
wire builder_minsoc_csrbank3_load1_we;
wire [7:0] builder_minsoc_csrbank3_load1_w;
wire builder_minsoc_csrbank3_load0_re;
wire [7:0] builder_minsoc_csrbank3_load0_r;
wire builder_minsoc_csrbank3_load0_we;
wire [7:0] builder_minsoc_csrbank3_load0_w;
wire builder_minsoc_csrbank3_reload3_re;
wire [7:0] builder_minsoc_csrbank3_reload3_r;
wire builder_minsoc_csrbank3_reload3_we;
wire [7:0] builder_minsoc_csrbank3_reload3_w;
wire builder_minsoc_csrbank3_reload2_re;
wire [7:0] builder_minsoc_csrbank3_reload2_r;
wire builder_minsoc_csrbank3_reload2_we;
wire [7:0] builder_minsoc_csrbank3_reload2_w;
wire builder_minsoc_csrbank3_reload1_re;
wire [7:0] builder_minsoc_csrbank3_reload1_r;
wire builder_minsoc_csrbank3_reload1_we;
wire [7:0] builder_minsoc_csrbank3_reload1_w;
wire builder_minsoc_csrbank3_reload0_re;
wire [7:0] builder_minsoc_csrbank3_reload0_r;
wire builder_minsoc_csrbank3_reload0_we;
wire [7:0] builder_minsoc_csrbank3_reload0_w;
wire builder_minsoc_csrbank3_en0_re;
wire builder_minsoc_csrbank3_en0_r;
wire builder_minsoc_csrbank3_en0_we;
wire builder_minsoc_csrbank3_en0_w;
wire builder_minsoc_csrbank3_update_value0_re;
wire builder_minsoc_csrbank3_update_value0_r;
wire builder_minsoc_csrbank3_update_value0_we;
wire builder_minsoc_csrbank3_update_value0_w;
wire builder_minsoc_csrbank3_value3_re;
wire [7:0] builder_minsoc_csrbank3_value3_r;
wire builder_minsoc_csrbank3_value3_we;
wire [7:0] builder_minsoc_csrbank3_value3_w;
wire builder_minsoc_csrbank3_value2_re;
wire [7:0] builder_minsoc_csrbank3_value2_r;
wire builder_minsoc_csrbank3_value2_we;
wire [7:0] builder_minsoc_csrbank3_value2_w;
wire builder_minsoc_csrbank3_value1_re;
wire [7:0] builder_minsoc_csrbank3_value1_r;
wire builder_minsoc_csrbank3_value1_we;
wire [7:0] builder_minsoc_csrbank3_value1_w;
wire builder_minsoc_csrbank3_value0_re;
wire [7:0] builder_minsoc_csrbank3_value0_r;
wire builder_minsoc_csrbank3_value0_we;
wire [7:0] builder_minsoc_csrbank3_value0_w;
wire builder_minsoc_csrbank3_ev_enable0_re;
wire builder_minsoc_csrbank3_ev_enable0_r;
wire builder_minsoc_csrbank3_ev_enable0_we;
wire builder_minsoc_csrbank3_ev_enable0_w;
wire builder_minsoc_csrbank3_sel;
wire [13:0] builder_minsoc_interface4_bank_bus_adr;
wire builder_minsoc_interface4_bank_bus_we;
wire [7:0] builder_minsoc_interface4_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface4_bank_bus_dat_r = 8\'d0;
wire builder_minsoc_csrbank4_txfull_re;
wire builder_minsoc_csrbank4_txfull_r;
wire builder_minsoc_csrbank4_txfull_we;
wire builder_minsoc_csrbank4_txfull_w;
wire builder_minsoc_csrbank4_rxempty_re;
wire builder_minsoc_csrbank4_rxempty_r;
wire builder_minsoc_csrbank4_rxempty_we;
wire builder_minsoc_csrbank4_rxempty_w;
wire builder_minsoc_csrbank4_ev_enable0_re;
wire [1:0] builder_minsoc_csrbank4_ev_enable0_r;
wire builder_minsoc_csrbank4_ev_enable0_we;
wire [1:0] builder_minsoc_csrbank4_ev_enable0_w;
wire builder_minsoc_csrbank4_sel;
wire [13:0] builder_minsoc_interface5_bank_bus_adr;
wire builder_minsoc_interface5_bank_bus_we;
wire [7:0] builder_minsoc_interface5_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface5_bank_bus_dat_r = 8\'d0;
wire builder_minsoc_csrbank5_tuning_word3_re;
wire [7:0] builder_minsoc_csrbank5_tuning_word3_r;
wire builder_minsoc_csrbank5_tuning_word3_we;
wire [7:0] builder_minsoc_csrbank5_tuning_word3_w;
wire builder_minsoc_csrbank5_tuning_word2_re;
wire [7:0] builder_minsoc_csrbank5_tuning_word2_r;
wire builder_minsoc_csrbank5_tuning_word2_we;
wire [7:0] builder_minsoc_csrbank5_tuning_word2_w;
wire builder_minsoc_csrbank5_tuning_word1_re;
wire [7:0] builder_minsoc_csrbank5_tuning_word1_r;
wire builder_minsoc_csrbank5_tuning_word1_we;
wire [7:0] builder_minsoc_csrbank5_tuning_word1_w;
wire builder_minsoc_csrbank5_tuning_word0_re;
wire [7:0] builder_minsoc_csrbank5_tuning_word0_r;
wire builder_minsoc_csrbank5_tuning_word0_we;
wire [7:0] builder_minsoc_csrbank5_tuning_word0_w;
wire builder_minsoc_csrbank5_sel;
wire [13:0] builder_minsoc_adr;
wire builder_minsoc_we;
wire [7:0] builder_minsoc_dat_w;
wire [7:0] builder_minsoc_dat_r;
reg builder_rhs_array_muxed0 = 1\'d0;
reg [13:0] builder_rhs_array_muxed1 = 14\'d0;
reg [2:0] builder_rhs_array_muxed2 = 3\'d0;
reg builder_rhs_array_muxed3 = 1\'d0;
reg builder_rhs_array_muxed4 = 1\'d0;
reg builder_rhs_array_muxed5 = 1\'d0;
reg builder_t_array_muxed0 = 1\'d0;
reg builder_t_array_muxed1 = 1\'d0;
reg builder_t_array_muxed2 = 1\'d0;
reg builder_rhs_array_muxed6 = 1\'d0;
reg [13:0] builder_rhs_array_muxed7 = 14\'d0;
reg [2:0] builder_rhs_array_muxed8 = 3\'d0;
reg builder_rhs_array_muxed9 = 1\'d0;
reg builder_rhs_array_muxed10 = 1\'d0;
reg builder_rhs_array_muxed11 = 1\'d0;
reg builder_t_array_muxed3 = 1\'d0;
reg builder_t_array_muxed4 = 1\'d0;
reg builder_t_array_muxed5 = 1\'d0;
reg [20:0] builder_rhs_array_muxed12 = 21\'d0;
reg builder_rhs_array_muxed13 = 1\'d0;
reg builder_rhs_array_muxed14 = 1\'d0;
reg [20:0] builder_rhs_array_muxed15 = 21\'d0;
reg builder_rhs_array_muxed16 = 1\'d0;
reg builder_rhs_array_muxed17 = 1\'d0;
reg [20:0] builder_rhs_array_muxed18 = 21\'d0;
reg builder_rhs_array_muxed19 = 1\'d0;
reg builder_rhs_array_muxed20 = 1\'d0;
reg [20:0] builder_rhs_array_muxed21 = 21\'d0;
reg builder_rhs_array_muxed22 = 1\'d0;
reg builder_rhs_array_muxed23 = 1\'d0;
reg [20:0] builder_rhs_array_muxed24 = 21\'d0;
reg builder_rhs_array_muxed25 = 1\'d0;
reg builder_rhs_array_muxed26 = 1\'d0;
reg [20:0] builder_rhs_array_muxed27 = 21\'d0;
reg builder_rhs_array_muxed28 = 1\'d0;
reg builder_rhs_array_muxed29 = 1\'d0;
reg [20:0] builder_rhs_array_muxed30 = 21\'d0;
reg builder_rhs_array_muxed31 = 1\'d0;
reg builder_rhs_array_muxed32 = 1\'d0;
reg [20:0] builder_rhs_array_muxed33 = 21\'d0;
reg builder_rhs_array_muxed34 = 1\'d0;
reg builder_rhs_array_muxed35 = 1\'d0;
reg [29:0] builder_rhs_array_muxed36 = 30\'d0;
reg [31:0] builder_rhs_array_muxed37 = 32\'d0;
reg [3:0] builder_rhs_array_muxed38 = 4\'d0;
reg builder_rhs_array_muxed39 = 1\'d0;
reg builder_rhs_array_muxed40 = 1\'d0;
reg builder_rhs_array_muxed41 = 1\'d0;
reg [2:0] builder_rhs_array_muxed42 = 3\'d0;
reg [1:0] builder_rhs_array_muxed43 = 2\'d0;
reg [29:0] builder_rhs_array_muxed44 = 30\'d0;
reg [31:0] builder_rhs_array_muxed45 = 32\'d0;
reg [3:0] builder_rhs_array_muxed46 = 4\'d0;
reg builder_rhs_array_muxed47 = 1\'d0;
reg builder_rhs_array_muxed48 = 1\'d0;
reg builder_rhs_array_muxed49 = 1\'d0;
reg [2:0] builder_rhs_array_muxed50 = 3\'d0;
reg [1:0] builder_rhs_array_muxed51 = 2\'d0;
reg [2:0] builder_array_muxed0 = 3\'d0;
reg [13:0] builder_array_muxed1 = 14\'d0;
reg builder_array_muxed2 = 1\'d0;
reg builder_array_muxed3 = 1\'d0;
reg builder_array_muxed4 = 1\'d0;
reg builder_array_muxed5 = 1\'d0;
reg builder_array_muxed6 = 1\'d0;
reg [2:0] builder_array_muxed7 = 3\'d0;
reg [13:0] builder_array_muxed8 = 14\'d0;
reg builder_array_muxed9 = 1\'d0;
reg builder_array_muxed10 = 1\'d0;
reg builder_array_muxed11 = 1\'d0;
reg builder_array_muxed12 = 1\'d0;
reg builder_array_muxed13 = 1\'d0;
reg [2:0] builder_array_muxed14 = 3\'d0;
reg [13:0] builder_array_muxed15 = 14\'d0;
reg builder_array_muxed16 = 1\'d0;
reg builder_array_muxed17 = 1\'d0;
reg builder_array_muxed18 = 1\'d0;
reg builder_array_muxed19 = 1\'d0;
reg builder_array_muxed20 = 1\'d0;
reg [2:0] builder_array_muxed21 = 3\'d0;
reg [13:0] builder_array_muxed22 = 14\'d0;
reg builder_array_muxed23 = 1\'d0;
reg builder_array_muxed24 = 1\'d0;
reg builder_array_muxed25 = 1\'d0;
reg builder_array_muxed26 = 1\'d0;
reg builder_array_muxed27 = 1\'d0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_regs0 = 1\'d0;
(* async_reg = "true", dont_touch = "true" *) reg builder_regs1 = 1\'d0;
wire builder_xilinxasyncresetsynchronizerimpl0;
wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
wire builder_xilinxasyncresetsynchronizerimpl1;
wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
wire builder_xilinxasyncresetsynchronizerimpl1_expr;
wire builder_xilinxasyncresetsynchronizerimpl2;
wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
wire builder_xilinxasyncresetsynchronizerimpl2_expr;
wire builder_xilinxasyncresetsynchronizerimpl3;
wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
assign main_minsoc_cpu_reset = main_minsoc_ctrl_reset;
assign main_minsoc_ctrl_bus_error = builder_minsoc_error;
always @(*) begin
main_minsoc_cpu_interrupt <= 32\'d0;
main_minsoc_cpu_interrupt[1] <= main_minsoc_timer0_irq;
main_minsoc_cpu_interrupt[0] <= main_minsoc_uart_irq;
end
assign main_minsoc_ctrl_reset = main_minsoc_ctrl_reset_re;
assign main_minsoc_ctrl_bus_errors_status = main_minsoc_ctrl_bus_errors;
assign main_minsoc_interface0_soc_bus_adr = main_minsoc_cpu_ibus_adr;
assign main_minsoc_interface0_soc_bus_dat_w = main_minsoc_cpu_ibus_dat_w;
assign main_minsoc_cpu_ibus_dat_r = main_minsoc_interface0_soc_bus_dat_r;
assign main_minsoc_interface0_soc_bus_sel = main_minsoc_cpu_ibus_sel;
assign main_minsoc_interface0_soc_bus_cyc = main_minsoc_cpu_ibus_cyc;
assign main_minsoc_interface0_soc_bus_stb = main_minsoc_cpu_ibus_stb;
assign main_minsoc_cpu_ibus_ack = main_minsoc_interface0_soc_bus_ack;
assign main_minsoc_interface0_soc_bus_we = main_minsoc_cpu_ibus_we;
assign main_minsoc_interface0_soc_bus_cti = main_minsoc_cpu_ibus_cti;
assign main_minsoc_interface0_soc_bus_bte = main_minsoc_cpu_ibus_bte;
assign main_minsoc_cpu_ibus_err = main_minsoc_interface0_soc_bus_err;
assign main_minsoc_interface1_soc_bus_adr = main_minsoc_cpu_dbus_adr;
assign main_minsoc_interface1_soc_bus_dat_w = main_minsoc_cpu_dbus_dat_w;
assign main_minsoc_cpu_dbus_dat_r = main_minsoc_interface1_soc_bus_dat_r;
assign main_minsoc_interface1_soc_bus_sel = main_minsoc_cpu_dbus_sel;
assign main_minsoc_interface1_soc_bus_cyc = main_minsoc_cpu_dbus_cyc;
assign main_minsoc_interface1_soc_bus_stb = main_minsoc_cpu_dbus_stb;
assign main_minsoc_cpu_dbus_ack = main_minsoc_interface1_soc_bus_ack;
assign main_minsoc_interface1_soc_bus_we = main_minsoc_cpu_dbus_we;
assign main_minsoc_interface1_soc_bus_cti = main_minsoc_cpu_dbus_cti;
assign main_minsoc_interface1_soc_bus_bte = main_minsoc_cpu_dbus_bte;
assign main_minsoc_cpu_dbus_err = main_minsoc_interface1_soc_bus_err;
assign main_minsoc_rom_adr = main_minsoc_rom_bus_adr[12:0];
assign main_minsoc_rom_bus_dat_r = main_minsoc_rom_dat_r;
always @(*) begin
main_minsoc_sram_we <= 4\'d0;
main_minsoc_sram_we[0] <= (((main_minsoc_sram_bus_cyc & main_minsoc_sram_bus_stb) & main_minsoc_sram_bus_we) & main_minsoc_sram_bus_sel[0]);
main_minsoc_sram_we[1] <= (((main_minsoc_sram_bus_cyc & main_minsoc_sram_bus_stb) & main_minsoc_sram_bus_we) & main_minsoc_sram_bus_sel[1]);
main_minsoc_sram_we[2] <= (((main_minsoc_sram_bus_cyc & main_minsoc_sram_bus_stb) & main_minsoc_sram_bus_we) & main_minsoc_sram_bus_sel[2]);
main_minsoc_sram_we[3] <= (((main_minsoc_sram_bus_cyc & main_minsoc_sram_bus_stb) & main_minsoc_sram_bus_we) & main_minsoc_sram_bus_sel[3]);
end
assign main_minsoc_sram_adr = main_minsoc_sram_bus_adr[9:0];
assign main_minsoc_sram_bus_dat_r = main_minsoc_sram_dat_r;
assign main_minsoc_sram_dat_w = main_minsoc_sram_bus_dat_w;
assign main_minsoc_uart_uart_sink_valid = main_minsoc_source_valid;
assign main_minsoc_source_ready = main_minsoc_uart_uart_sink_ready;
assign main_minsoc_uart_uart_sink_first = main_minsoc_source_first;
assign main_minsoc_uart_uart_sink_last = main_minsoc_source_last;
assign main_minsoc_uart_uart_sink_payload_data = main_minsoc_source_payload_data;
assign main_minsoc_sink_valid = main_minsoc_uart_uart_source_valid;
assign main_minsoc_uart_uart_source_ready = main_minsoc_sink_ready;
assign main_minsoc_sink_first = main_minsoc_uart_uart_source_first;
assign main_minsoc_sink_last = main_minsoc_uart_uart_source_last;
assign main_minsoc_sink_payload_data = main_minsoc_uart_uart_source_payload_data;
assign main_minsoc_uart_tx_fifo_sink_valid = main_minsoc_uart_rxtx_re;
assign main_minsoc_uart_tx_fifo_sink_payload_data = main_minsoc_uart_rxtx_r;
assign main_minsoc_uart_txfull_status = (~main_minsoc_uart_tx_fifo_sink_ready);
assign main_minsoc_uart_uart_source_valid = main_minsoc_uart_tx_fifo_source_valid;
assign main_minsoc_uart_tx_fifo_source_ready = main_minsoc_uart_uart_source_ready;
assign main_minsoc_uart_uart_source_first = main_minsoc_uart_tx_fifo_source_first;
assign main_minsoc_uart_uart_source_last = main_minsoc_uart_tx_fifo_source_last;
assign main_minsoc_uart_uart_source_payload_data = main_minsoc_uart_tx_fifo_source_payload_data;
assign main_minsoc_uart_tx_trigger = (~main_minsoc_uart_tx_fifo_sink_ready);
assign main_minsoc_uart_rx_fifo_sink_valid = main_minsoc_uart_uart_sink_valid;
assign main_minsoc_uart_uart_sink_ready = main_minsoc_uart_rx_fifo_sink_ready;
assign main_minsoc_uart_rx_fifo_sink_first = main_minsoc_uart_uart_sink_first;
assign main_minsoc_uart_rx_fifo_sink_last = main_minsoc_uart_uart_sink_last;
assign main_minsoc_uart_rx_fifo_sink_payload_data = main_minsoc_uart_uart_sink_payload_data;
assign main_minsoc_uart_rxempty_status = (~main_minsoc_uart_rx_fifo_source_valid);
assign main_minsoc_uart_rxtx_w = main_minsoc_uart_rx_fifo_source_payload_data;
assign main_minsoc_uart_rx_fifo_source_ready = (main_minsoc_uart_rx_clear | (1\'d0 & main_minsoc_uart_rxtx_we));
assign main_minsoc_uart_rx_trigger = (~main_minsoc_uart_rx_fifo_source_valid);
always @(*) begin
main_minsoc_uart_tx_clear <= 1\'d0;
if ((main_minsoc_uart_eventmanager_pending_re & main_minsoc_uart_eventmanager_pending_r[0])) begin
main_minsoc_uart_tx_clear <= 1\'d1;
end
end
always @(*) begin
main_minsoc_uart_eventmanager_status_w <= 2\'d0;
main_minsoc_uart_eventmanager_status_w[0] <= main_minsoc_uart_tx_status;
main_minsoc_uart_eventmanager_status_w[1] <= main_minsoc_uart_rx_status;
end
always @(*) begin
main_minsoc_uart_rx_clear <= 1\'d0;
if ((main_minsoc_uart_eventmanager_pending_re & main_minsoc_uart_eventmanager_pending_r[1])) begin
main_minsoc_uart_rx_clear <= 1\'d1;
end
end
always @(*) begin
main_minsoc_uart_eventmanager_pending_w <= 2\'d0;
main_minsoc_uart_eventmanager_pending_w[0] <= main_minsoc_uart_tx_pending;
main_minsoc_uart_eventmanager_pending_w[1] <= main_minsoc_uart_rx_pending;
end
assign main_minsoc_uart_irq = ((main_minsoc_uart_eventmanager_pending_w[0] & main_minsoc_uart_eventmanager_storage[0]) | (main_minsoc_uart_eventmanager_pending_w[1] & main_minsoc_uart_eventmanager_storage[1]));
assign main_minsoc_uart_tx_status = main_minsoc_uart_tx_trigger;
assign main_minsoc_uart_rx_status = main_minsoc_uart_rx_trigger;
assign main_minsoc_uart_tx_fifo_syncfifo_din = {
main_minsoc_uart_tx_fifo_fifo_in_last,
main_minsoc_uart_tx_fifo_fifo_in_first,
main_minsoc_uart_tx_fifo_fifo_in_payload_data
};
assign {main_minsoc_uart_tx_fifo_fifo_out_last, main_minsoc_uart_tx_fifo_fifo_out_first, main_minsoc_uart_tx_fifo_fifo_out_payload_data} = main_minsoc_uart_tx_fifo_syncfifo_dout;
assign main_minsoc_uart_tx_fifo_sink_ready = main_minsoc_uart_tx_fifo_syncfifo_writable;
assign main_minsoc_uart_tx_fifo_syncfifo_we = main_minsoc_uart_tx_fifo_sink_valid;
assign main_minsoc_uart_tx_fifo_fifo_in_first = main_minsoc_uart_tx_fifo_sink_first;
assign main_minsoc_uart_tx_fifo_fifo_in_last = main_minsoc_uart_tx_fifo_sink_last;
assign main_minsoc_uart_tx_fifo_fifo_in_payload_data = main_minsoc_uart_tx_fifo_sink_payload_data;
assign main_minsoc_uart_tx_fifo_source_valid = main_minsoc_uart_tx_fifo_readable;
assign main_minsoc_uart_tx_fifo_source_first = main_minsoc_uart_tx_fifo_fifo_out_first;
assign main_minsoc_uart_tx_fifo_source_last = main_minsoc_uart_tx_fifo_fifo_out_last;
assign main_minsoc_uart_tx_fifo_source_payload_data = main_minsoc_uart_tx_fifo_fifo_out_payload_data;
assign main_minsoc_uart_tx_fifo_re = main_minsoc_uart_tx_fifo_source_ready;
assign main_minsoc_uart_tx_fifo_syncfifo_re = (main_minsoc_uart_tx_fifo_syncfifo_readable & ((~main_minsoc_uart_tx_fifo_readable) | main_minsoc_uart_tx_fifo_re));
assign main_minsoc_uart_tx_fifo_level1 = (main_minsoc_uart_tx_fifo_level0 + main_minsoc_uart_tx_fifo_readable);
always @(*) begin
main_minsoc_uart_tx_fifo_wrport_adr <= 4\'d0;
if (main_minsoc_uart_tx_fifo_replace) begin
main_minsoc_uart_tx_fifo_wrport_adr <= (main_minsoc_uart_tx_fifo_produce - 1\'d1);
end else begin
main_minsoc_uart_tx_fifo_wrport_adr <= main_minsoc_uart_tx_fifo_produce;
end
end
assign main_minsoc_uart_tx_fifo_wrport_dat_w = main_minsoc_uart_tx_fifo_syncfifo_din;
assign main_minsoc_uart_tx_fifo_wrport_we = (main_minsoc_uart_tx_fifo_syncfifo_we & (main_minsoc_uart_tx_fifo_syncfifo_writable | main_minsoc_uart_tx_fifo_replace));
assign main_minsoc_uart_tx_fifo_do_read = (main_minsoc_uart_tx_fifo_syncfifo_readable & main_minsoc_uart_tx_fifo_syncfifo_re);
assign main_minsoc_uart_tx_fifo_rdport_adr = main_minsoc_uart_tx_fifo_consume;
assign main_minsoc_uart_tx_fifo_syncfifo_dout = main_minsoc_uart_tx_fifo_rdport_dat_r;
assign main_minsoc_uart_tx_fifo_rdport_re = main_minsoc_uart_tx_fifo_do_read;
assign main_minsoc_uart_tx_fifo_syncfifo_writable = (main_minsoc_uart_tx_fifo_level0 != 5\'d16);
assign main_minsoc_uart_tx_fifo_syncfifo_readable = (main_minsoc_uart_tx_fifo_level0 != 1\'d0);
assign main_minsoc_uart_rx_fifo_syncfifo_din = {
main_minsoc_uart_rx_fifo_fifo_in_last,
main_minsoc_uart_rx_fifo_fifo_in_first,
main_minsoc_uart_rx_fifo_fifo_in_payload_data
};
assign {main_minsoc_uart_rx_fifo_fifo_out_last, main_minsoc_uart_rx_fifo_fifo_out_first, main_minsoc_uart_rx_fifo_fifo_out_payload_data} = main_minsoc_uart_rx_fifo_syncfifo_dout;
assign main_minsoc_uart_rx_fifo_sink_ready = main_minsoc_uart_rx_fifo_syncfifo_writable;
assign main_minsoc_uart_rx_fifo_syncfifo_we = main_minsoc_uart_rx_fifo_sink_valid;
assign main_minsoc_uart_rx_fifo_fifo_in_first = main_minsoc_uart_rx_fifo_sink_first;
assign main_minsoc_uart_rx_fifo_fifo_in_last = main_minsoc_uart_rx_fifo_sink_last;
assign main_minsoc_uart_rx_fifo_fifo_in_payload_data = main_minsoc_uart_rx_fifo_sink_payload_data;
assign main_minsoc_uart_rx_fifo_source_valid = main_minsoc_uart_rx_fifo_readable;
assign main_minsoc_uart_rx_fifo_source_first = main_minsoc_uart_rx_fifo_fifo_out_first;
assign main_minsoc_uart_rx_fifo_source_last = main_minsoc_uart_rx_fifo_fifo_out_last;
assign main_minsoc_uart_rx_fifo_source_payload_data = main_minsoc_uart_rx_fifo_fifo_out_payload_data;
assign main_minsoc_uart_rx_fifo_re = main_minsoc_uart_rx_fifo_source_ready;
assign main_minsoc_uart_rx_fifo_syncfifo_re = (main_minsoc_uart_rx_fifo_syncfifo_readable & ((~main_minsoc_uart_rx_fifo_readable) | main_minsoc_uart_rx_fifo_re));
assign main_minsoc_uart_rx_fifo_level1 = (main_minsoc_uart_rx_fifo_level0 + main_minsoc_uart_rx_fifo_readable);
always @(*) begin
main_minsoc_uart_rx_fifo_wrport_adr <= 4\'d0;
if (main_minsoc_uart_rx_fifo_replace) begin
main_minsoc_uart_rx_fifo_wrport_adr <= (main_minsoc_uart_rx_fifo_produce - 1\'d1);
end else begin
main_minsoc_uart_rx_fifo_wrport_adr <= main_minsoc_uart_rx_fifo_produce;
end
end
assign main_minsoc_uart_rx_fifo_wrport_dat_w = main_minsoc_uart_rx_fifo_syncfifo_din;
assign main_minsoc_uart_rx_fifo_wrport_we = (main_minsoc_uart_rx_fifo_syncfifo_we & (main_minsoc_uart_rx_fifo_syncfifo_writable | main_minsoc_uart_rx_fifo_replace));
assign main_minsoc_uart_rx_fifo_do_read = (main_minsoc_uart_rx_fifo_syncfifo_readable & main_minsoc_uart_rx_fifo_syncfifo_re);
assign main_minsoc_uart_rx_fifo_rdport_adr = main_minsoc_uart_rx_fifo_consume;
assign main_minsoc_uart_rx_fifo_syncfifo_dout = main_minsoc_uart_rx_fifo_rdport_dat_r;
assign main_minsoc_uart_rx_fifo_rdport_re = main_minsoc_uart_rx_fifo_do_read;
assign main_minsoc_uart_rx_fifo_syncfifo_writable = (main_minsoc_uart_rx_fifo_level0 != 5\'d16);
assign main_minsoc_uart_rx_fifo_syncfifo_readable = (main_minsoc_uart_rx_fifo_level0 != 1\'d0);
assign main_minsoc_timer0_zero_trigger = (main_minsoc_timer0_value != 1\'d0);
assign main_minsoc_timer0_eventmanager_status_w = main_minsoc_timer0_zero_status;
always @(*) begin
main_minsoc_timer0_zero_clear <= 1\'d0;
if ((main_minsoc_timer0_eventmanager_pending_re & main_minsoc_timer0_eventmanager_pending_r)) begin
main_minsoc_timer0_zero_clear <= 1\'d1;
end
end
assign main_minsoc_timer0_eventmanager_pending_w = main_minsoc_timer0_zero_pending;
assign main_minsoc_timer0_irq = (main_minsoc_timer0_eventmanager_pending_w & main_minsoc_timer0_eventmanager_storage);
assign main_minsoc_timer0_zero_status = main_minsoc_timer0_zero_trigger;
assign main_minsoc_interface_dat_w = main_minsoc_bus_wishbone_dat_w;
assign main_minsoc_bus_wishbone_dat_r = main_minsoc_interface_dat_r;
always @(*) begin
main_minsoc_interface_adr <= 14\'d0;
main_minsoc_interface_we <= 1\'d0;
builder_wb2csr_next_state <= 1\'d0;
main_minsoc_bus_wishbone_ack <= 1\'d0;
builder_wb2csr_next_state <= builder_wb2csr_state;
case (builder_wb2csr_state)
1\'d1: begin
main_minsoc_bus_wishbone_ack <= 1\'d1;
builder_wb2csr_next_state <= 1\'d0;
end
default: begin
if ((main_minsoc_bus_wishbone_cyc & main_minsoc_bus_wishbone_stb)) begin
main_minsoc_interface_adr <= main_minsoc_bus_wishbone_adr;
main_minsoc_interface_we <= main_minsoc_bus_wishbone_we;
builder_wb2csr_next_state <= 1\'d1;
end
end
endcase
end
assign main_reset = (~cpu_reset);
always @(*) begin
main_a7ddrphy_dqs_serdes_pattern <= 8\'d85;
main_a7ddrphy_dqs_serdes_pattern <= 7\'d85;
if ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_postamble)) begin
main_a7ddrphy_dqs_serdes_pattern <= 1\'d0;
end
end
assign main_a7ddrphy_bitslip0_i = main_a7ddrphy_dq_i_data0;
assign main_a7ddrphy_bitslip1_i = main_a7ddrphy_dq_i_data1;
assign main_a7ddrphy_bitslip2_i = main_a7ddrphy_dq_i_data2;
assign main_a7ddrphy_bitslip3_i = main_a7ddrphy_dq_i_data3;
assign main_a7ddrphy_bitslip4_i = main_a7ddrphy_dq_i_data4;
assign main_a7ddrphy_bitslip5_i = main_a7ddrphy_dq_i_data5;
assign main_a7ddrphy_bitslip6_i = main_a7ddrphy_dq_i_data6;
assign main_a7ddrphy_bitslip7_i = main_a7ddrphy_dq_i_data7;
assign main_a7ddrphy_bitslip8_i = main_a7ddrphy_dq_i_data8;
assign main_a7ddrphy_bitslip9_i = main_a7ddrphy_dq_i_data9;
assign main_a7ddrphy_bitslip10_i = main_a7ddrphy_dq_i_data10;
assign main_a7ddrphy_bitslip11_i = main_a7ddrphy_dq_i_data11;
assign main_a7ddrphy_bitslip12_i = main_a7ddrphy_dq_i_data12;
assign main_a7ddrphy_bitslip13_i = main_a7ddrphy_dq_i_data13;
assign main_a7ddrphy_bitslip14_i = main_a7ddrphy_dq_i_data14;
assign main_a7ddrphy_bitslip15_i = main_a7ddrphy_dq_i_data15;
always @(*) begin
main_a7ddrphy_dfi_p0_rddata <= 32\'d0;
main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip0_o[0];
main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip0_o[1];
main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip1_o[0];
main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip1_o[1];
main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip2_o[0];
main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip2_o[1];
main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip3_o[0];
main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip3_o[1];
main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip4_o[0];
main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip4_o[1];
main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip5_o[0];
main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip5_o[1];
main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip6_o[0];
main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip6_o[1];
main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip7_o[0];
main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip7_o[1];
main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip8_o[0];
main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip8_o[1];
main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip9_o[0];
main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip9_o[1];
main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip10_o[0];
main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip10_o[1];
main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip11_o[0];
main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip11_o[1];
main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip12_o[0];
main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip12_o[1];
main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip13_o[0];
main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip13_o[1];
main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip14_o[0];
main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip14_o[1];
main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip15_o[0];
main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip15_o[1];
end
always @(*) begin
main_a7ddrphy_dfi_p1_rddata <= 32\'d0;
main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip0_o[2];
main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip0_o[3];
main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip1_o[2];
main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip1_o[3];
main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip2_o[2];
main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip2_o[3];
main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip3_o[2];
main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip3_o[3];
main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip4_o[2];
main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip4_o[3];
main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip5_o[2];
main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip5_o[3];
main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip6_o[2];
main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip6_o[3];
main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip7_o[2];
main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip7_o[3];
main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip8_o[2];
main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip8_o[3];
main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip9_o[2];
main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip9_o[3];
main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip10_o[2];
main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip10_o[3];
main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip11_o[2];
main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip11_o[3];
main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip12_o[2];
main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip12_o[3];
main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip13_o[2];
main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip13_o[3];
main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip14_o[2];
main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip14_o[3];
main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip15_o[2];
main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip15_o[3];
end
always @(*) begin
main_a7ddrphy_dfi_p2_rddata <= 32\'d0;
main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip0_o[4];
main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip0_o[5];
main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip1_o[4];
main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip1_o[5];
main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip2_o[4];
main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip2_o[5];
main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip3_o[4];
main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip3_o[5];
main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip4_o[4];
main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip4_o[5];
main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip5_o[4];
main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip5_o[5];
main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip6_o[4];
main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip6_o[5];
main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip7_o[4];
main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip7_o[5];
main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip8_o[4];
main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip8_o[5];
main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip9_o[4];
main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip9_o[5];
main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip10_o[4];
main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip10_o[5];
main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip11_o[4];
main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip11_o[5];
main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip12_o[4];
main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip12_o[5];
main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip13_o[4];
main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip13_o[5];
main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip14_o[4];
main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip14_o[5];
main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip15_o[4];
main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip15_o[5];
end
always @(*) begin
main_a7ddrphy_dfi_p3_rddata <= 32\'d0;
main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip0_o[6];
main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip0_o[7];
main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip1_o[6];
main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip1_o[7];
main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip2_o[6];
main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip2_o[7];
main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip3_o[6];
main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip3_o[7];
main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip4_o[6];
main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip4_o[7];
main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip5_o[6];
main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip5_o[7];
main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip6_o[6];
main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip6_o[7];
main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip7_o[6];
main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip7_o[7];
main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip8_o[6];
main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip8_o[7];
main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip9_o[6];
main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip9_o[7];
main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip10_o[6];
main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip10_o[7];
main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip11_o[6];
main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip11_o[7];
main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip12_o[6];
main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip12_o[7];
main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip13_o[6];
main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip13_o[7];
main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip14_o[6];
main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip14_o[7];
main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip15_o[6];
main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip15_o[7];
end
assign main_a7ddrphy_oe = ((main_a7ddrphy_last_wrdata_en[1] | main_a7ddrphy_last_wrdata_en[2]) | main_a7ddrphy_last_wrdata_en[3]);
assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_last_wrdata_en[1] & (~main_a7ddrphy_last_wrdata_en[2]));
assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_last_wrdata_en[3] & (~main_a7ddrphy_last_wrdata_en[2]));
assign main_a7ddrphy_dfi_p0_address = main_sdram_master_p0_address;
assign main_a7ddrphy_dfi_p0_bank = main_sdram_master_p0_bank;
assign main_a7ddrphy_dfi_p0_cas_n = main_sdram_master_p0_cas_n;
assign main_a7ddrphy_dfi_p0_cs_n = main_sdram_master_p0_cs_n;
assign main_a7ddrphy_dfi_p0_ras_n = main_sdram_master_p0_ras_n;
assign main_a7ddrphy_dfi_p0_we_n = main_sdram_master_p0_we_n;
assign main_a7ddrphy_dfi_p0_cke = main_sdram_master_p0_cke;
assign main_a7ddrphy_dfi_p0_odt = main_sdram_master_p0_odt;
assign main_a7ddrphy_dfi_p0_reset_n = main_sdram_master_p0_reset_n;
assign main_a7ddrphy_dfi_p0_act_n = main_sdram_master_p0_act_n;
assign main_a7ddrphy_dfi_p0_wrdata = main_sdram_master_p0_wrdata;
assign main_a7ddrphy_dfi_p0_wrdata_en = main_sdram_master_p0_wrdata_en;
assign main_a7ddrphy_dfi_p0_wrdata_mask = main_sdram_master_p0_wrdata_mask;
assign main_a7ddrphy_dfi_p0_rddata_en = main_sdram_master_p0_rddata_en;
assign main_sdram_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
assign main_sdram_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
assign main_a7ddrphy_dfi_p1_address = main_sdram_master_p1_address;
assign main_a7ddrphy_dfi_p1_bank = main_sdram_master_p1_bank;
assign main_a7ddrphy_dfi_p1_cas_n = main_sdram_master_p1_cas_n;
assign main_a7ddrphy_dfi_p1_cs_n = main_sdram_master_p1_cs_n;
assign main_a7ddrphy_dfi_p1_ras_n = main_sdram_master_p1_ras_n;
assign main_a7ddrphy_dfi_p1_we_n = main_sdram_master_p1_we_n;
assign main_a7ddrphy_dfi_p1_cke = main_sdram_master_p1_cke;
assign main_a7ddrphy_dfi_p1_odt = main_sdram_master_p1_odt;
assign main_a7ddrphy_dfi_p1_reset_n = main_sdram_master_p1_reset_n;
assign main_a7ddrphy_dfi_p1_act_n = main_sdram_master_p1_act_n;
assign main_a7ddrphy_dfi_p1_wrdata = main_sdram_master_p1_wrdata;
assign main_a7ddrphy_dfi_p1_wrdata_en = main_sdram_master_p1_wrdata_en;
assign main_a7ddrphy_dfi_p1_wrdata_mask = main_sdram_master_p1_wrdata_mask;
assign main_a7ddrphy_dfi_p1_rddata_en = main_sdram_master_p1_rddata_en;
assign main_sdram_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
assign main_sdram_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
assign main_a7ddrphy_dfi_p2_address = main_sdram_master_p2_address;
assign main_a7ddrphy_dfi_p2_bank = main_sdram_master_p2_bank;
assign main_a7ddrphy_dfi_p2_cas_n = main_sdram_master_p2_cas_n;
assign main_a7ddrphy_dfi_p2_cs_n = main_sdram_master_p2_cs_n;
assign main_a7ddrphy_dfi_p2_ras_n = main_sdram_master_p2_ras_n;
assign main_a7ddrphy_dfi_p2_we_n = main_sdram_master_p2_we_n;
assign main_a7ddrphy_dfi_p2_cke = main_sdram_master_p2_cke;
assign main_a7ddrphy_dfi_p2_odt = main_sdram_master_p2_odt;
assign main_a7ddrphy_dfi_p2_reset_n = main_sdram_master_p2_reset_n;
assign main_a7ddrphy_dfi_p2_act_n = main_sdram_master_p2_act_n;
assign main_a7ddrphy_dfi_p2_wrdata = main_sdram_master_p2_wrdata;
assign main_a7ddrphy_dfi_p2_wrdata_en = main_sdram_master_p2_wrdata_en;
assign main_a7ddrphy_dfi_p2_wrdata_mask = main_sdram_master_p2_wrdata_mask;
assign main_a7ddrphy_dfi_p2_rddata_en = main_sdram_master_p2_rddata_en;
assign main_sdram_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
assign main_sdram_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
assign main_a7ddrphy_dfi_p3_address = main_sdram_master_p3_address;
assign main_a7ddrphy_dfi_p3_bank = main_sdram_master_p3_bank;
assign main_a7ddrphy_dfi_p3_cas_n = main_sdram_master_p3_cas_n;
assign main_a7ddrphy_dfi_p3_cs_n = main_sdram_master_p3_cs_n;
assign main_a7ddrphy_dfi_p3_ras_n = main_sdram_master_p3_ras_n;
assign main_a7ddrphy_dfi_p3_we_n = main_sdram_master_p3_we_n;
assign main_a7ddrphy_dfi_p3_cke = main_sdram_master_p3_cke;
assign main_a7ddrphy_dfi_p3_odt = main_sdram_master_p3_odt;
assign main_a7ddrphy_dfi_p3_reset_n = main_sdram_master_p3_reset_n;
assign main_a7ddrphy_dfi_p3_act_n = main_sdram_master_p3_act_n;
assign main_a7ddrphy_dfi_p3_wrdata = main_sdram_master_p3_wrdata;
assign main_a7ddrphy_dfi_p3_wrdata_en = main_sdram_master_p3_wrdata_en;
assign main_a7ddrphy_dfi_p3_wrdata_mask = main_sdram_master_p3_wrdata_mask;
assign main_a7ddrphy_dfi_p3_rddata_en = main_sdram_master_p3_rddata_en;
assign main_sdram_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
assign main_sdram_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
assign main_sdram_slave_p0_address = main_sdram_dfi_p0_address;
assign main_sdram_slave_p0_bank = main_sdram_dfi_p0_bank;
assign main_sdram_slave_p0_cas_n = main_sdram_dfi_p0_cas_n;
assign main_sdram_slave_p0_cs_n = main_sdram_dfi_p0_cs_n;
assign main_sdram_slave_p0_ras_n = main_sdram_dfi_p0_ras_n;
assign main_sdram_slave_p0_we_n = main_sdram_dfi_p0_we_n;
assign main_sdram_slave_p0_cke = main_sdram_dfi_p0_cke;
assign main_sdram_slave_p0_odt = main_sdram_dfi_p0_odt;
assign main_sdram_slave_p0_reset_n = main_sdram_dfi_p0_reset_n;
assign main_sdram_slave_p0_act_n = main_sdram_dfi_p0_act_n;
assign main_sdram_slave_p0_wrdata = main_sdram_dfi_p0_wrdata;
assign main_sdram_slave_p0_wrdata_en = main_sdram_dfi_p0_wrdata_en;
assign main_sdram_slave_p0_wrdata_mask = main_sdram_dfi_p0_wrdata_mask;
assign main_sdram_slave_p0_rddata_en = main_sdram_dfi_p0_rddata_en;
assign main_sdram_dfi_p0_rddata = main_sdram_slave_p0_rddata;
assign main_sdram_dfi_p0_rddata_valid = main_sdram_slave_p0_rddata_valid;
assign main_sdram_slave_p1_address = main_sdram_dfi_p1_address;
assign main_sdram_slave_p1_bank = main_sdram_dfi_p1_bank;
assign main_sdram_slave_p1_cas_n = main_sdram_dfi_p1_cas_n;
assign main_sdram_slave_p1_cs_n = main_sdram_dfi_p1_cs_n;
assign main_sdram_slave_p1_ras_n = main_sdram_dfi_p1_ras_n;
assign main_sdram_slave_p1_we_n = main_sdram_dfi_p1_we_n;
assign main_sdram_slave_p1_cke = main_sdram_dfi_p1_cke;
assign main_sdram_slave_p1_odt = main_sdram_dfi_p1_odt;
assign main_sdram_slave_p1_reset_n = main_sdram_dfi_p1_reset_n;
assign main_sdram_slave_p1_act_n = main_sdram_dfi_p1_act_n;
assign main_sdram_slave_p1_wrdata = main_sdram_dfi_p1_wrdata;
assign main_sdram_slave_p1_wrdata_en = main_sdram_dfi_p1_wrdata_en;
assign main_sdram_slave_p1_wrdata_mask = main_sdram_dfi_p1_wrdata_mask;
assign main_sdram_slave_p1_rddata_en = main_sdram_dfi_p1_rddata_en;
assign main_sdram_dfi_p1_rddata = main_sdram_slave_p1_rddata;
assign main_sdram_dfi_p1_rddata_valid = main_sdram_slave_p1_rddata_valid;
assign main_sdram_slave_p2_address = main_sdram_dfi_p2_address;
assign main_sdram_slave_p2_bank = main_sdram_dfi_p2_bank;
assign main_sdram_slave_p2_cas_n = main_sdram_dfi_p2_cas_n;
assign main_sdram_slave_p2_cs_n = main_sdram_dfi_p2_cs_n;
assign main_sdram_slave_p2_ras_n = main_sdram_dfi_p2_ras_n;
assign main_sdram_slave_p2_we_n = main_sdram_dfi_p2_we_n;
assign main_sdram_slave_p2_cke = main_sdram_dfi_p2_cke;
assign main_sdram_slave_p2_odt = main_sdram_dfi_p2_odt;
assign main_sdram_slave_p2_reset_n = main_sdram_dfi_p2_reset_n;
assign main_sdram_slave_p2_act_n = main_sdram_dfi_p2_act_n;
assign main_sdram_slave_p2_wrdata = main_sdram_dfi_p2_wrdata;
assign main_sdram_slave_p2_wrdata_en = main_sdram_dfi_p2_wrdata_en;
assign main_sdram_slave_p2_wrdata_mask = main_sdram_dfi_p2_wrdata_mask;
assign main_sdram_slave_p2_rddata_en = main_sdram_dfi_p2_rddata_en;
assign main_sdram_dfi_p2_rddata = main_sdram_slave_p2_rddata;
assign main_sdram_dfi_p2_rddata_valid = main_sdram_slave_p2_rddata_valid;
assign main_sdram_slave_p3_address = main_sdram_dfi_p3_address;
assign main_sdram_slave_p3_bank = main_sdram_dfi_p3_bank;
assign main_sdram_slave_p3_cas_n = main_sdram_dfi_p3_cas_n;
assign main_sdram_slave_p3_cs_n = main_sdram_dfi_p3_cs_n;
assign main_sdram_slave_p3_ras_n = main_sdram_dfi_p3_ras_n;
assign main_sdram_slave_p3_we_n = main_sdram_dfi_p3_we_n;
assign main_sdram_slave_p3_cke = main_sdram_dfi_p3_cke;
assign main_sdram_slave_p3_odt = main_sdram_dfi_p3_odt;
assign main_sdram_slave_p3_reset_n = main_sdram_dfi_p3_reset_n;
assign main_sdram_slave_p3_act_n = main_sdram_dfi_p3_act_n;
assign main_sdram_slave_p3_wrdata = main_sdram_dfi_p3_wrdata;
assign main_sdram_slave_p3_wrdata_en = main_sdram_dfi_p3_wrdata_en;
assign main_sdram_slave_p3_wrdata_mask = main_sdram_dfi_p3_wrdata_mask;
assign main_sdram_slave_p3_rddata_en = main_sdram_dfi_p3_rddata_en;
assign main_sdram_dfi_p3_rddata = main_sdram_slave_p3_rddata;
assign main_sdram_dfi_p3_rddata_valid = main_sdram_slave_p3_rddata_valid;
always @(*) begin
main_sdram_slave_p1_rddata <= 32\'d0;
main_sdram_slave_p1_rddata_valid <= 1\'d0;
main_sdram_slave_p2_rddata <= 32\'d0;
main_sdram_slave_p2_rddata_valid <= 1\'d0;
main_sdram_slave_p3_rddata <= 32\'d0;
main_sdram_slave_p3_rddata_valid <= 1\'d0;
main_sdram_inti_p0_rddata <= 32\'d0;
main_sdram_inti_p0_rddata_valid <= 1\'d0;
main_sdram_master_p0_address <= 14\'d0;
main_sdram_master_p0_bank <= 3\'d0;
main_sdram_master_p0_cas_n <= 1\'d1;
main_sdram_master_p0_cs_n <= 1\'d1;
main_sdram_master_p0_ras_n <= 1\'d1;
main_sdram_master_p0_we_n <= 1\'d1;
main_sdram_master_p0_cke <= 1\'d0;
main_sdram_master_p0_odt <= 1\'d0;
main_sdram_master_p0_reset_n <= 1\'d0;
main_sdram_master_p0_act_n <= 1\'d1;
main_sdram_inti_p1_rddata <= 32\'d0;
main_sdram_master_p0_wrdata <= 32\'d0;
main_sdram_inti_p1_rddata_valid <= 1\'d0;
main_sdram_master_p0_wrdata_en <= 1\'d0;
main_sdram_master_p0_wrdata_mask <= 4\'d0;
main_sdram_master_p0_rddata_en <= 1\'d0;
main_sdram_master_p1_address <= 14\'d0;
main_sdram_master_p1_bank <= 3\'d0;
main_sdram_master_p1_cas_n <= 1\'d1;
main_sdram_master_p1_cs_n <= 1\'d1;
main_sdram_master_p1_ras_n <= 1\'d1;
main_sdram_master_p1_we_n <= 1\'d1;
main_sdram_master_p1_cke <= 1\'d0;
main_sdram_master_p1_odt <= 1\'d0;
main_sdram_master_p1_reset_n <= 1\'d0;
main_sdram_master_p1_act_n <= 1\'d1;
main_sdram_master_p1_wrdata <= 32\'d0;
main_sdram_inti_p2_rddata <= 32\'d0;
main_sdram_master_p1_wrdata_en <= 1\'d0;
main_sdram_inti_p2_rddata_valid <= 1\'d0;
main_sdram_master_p1_wrdata_mask <= 4\'d0;
main_sdram_master_p1_rddata_en <= 1\'d0;
main_sdram_master_p2_address <= 14\'d0;
main_sdram_master_p2_bank <= 3\'d0;
main_sdram_master_p2_cas_n <= 1\'d1;
main_sdram_master_p2_cs_n <= 1\'d1;
main_sdram_master_p2_ras_n <= 1\'d1;
main_sdram_master_p2_we_n <= 1\'d1;
main_sdram_master_p2_cke <= 1\'d0;
main_sdram_master_p2_odt <= 1\'d0;
main_sdram_master_p2_reset_n <= 1\'d0;
main_sdram_master_p2_act_n <= 1\'d1;
main_sdram_master_p2_wrdata <= 32\'d0;
main_sdram_inti_p3_rddata <= 32\'d0;
main_sdram_master_p2_wrdata_en <= 1\'d0;
main_sdram_inti_p3_rddata_valid <= 1\'d0;
main_sdram_master_p2_wrdata_mask <= 4\'d0;
main_sdram_master_p2_rddata_en <= 1\'d0;
main_sdram_master_p3_address <= 14\'d0;
main_sdram_master_p3_bank <= 3\'d0;
main_sdram_master_p3_cas_n <= 1\'d1;
main_sdram_master_p3_cs_n <= 1\'d1;
main_sdram_master_p3_ras_n <= 1\'d1;
main_sdram_master_p3_we_n <= 1\'d1;
main_sdram_master_p3_cke <= 1\'d0;
main_sdram_master_p3_odt <= 1\'d0;
main_sdram_master_p3_reset_n <= 1\'d0;
main_sdram_master_p3_act_n <= 1\'d1;
main_sdram_master_p3_wrdata <= 32\'d0;
main_sdram_master_p3_wrdata_en <= 1\'d0;
main_sdram_master_p3_wrdata_mask <= 4\'d0;
main_sdram_master_p3_rddata_en <= 1\'d0;
main_sdram_slave_p0_rddata <= 32\'d0;
main_sdram_slave_p0_rddata_valid <= 1\'d0;
if (main_sdram_storage[0]) begin
main_sdram_master_p0_address <= main_sdram_slave_p0_address;
main_sdram_master_p0_bank <= main_sdram_slave_p0_bank;
main_sdram_master_p0_cas_n <= main_sdram_slave_p0_cas_n;
main_sdram_master_p0_cs_n <= main_sdram_slave_p0_cs_n;
main_sdram_master_p0_ras_n <= main_sdram_slave_p0_ras_n;
main_sdram_master_p0_we_n <= main_sdram_slave_p0_we_n;
main_sdram_master_p0_cke <= main_sdram_slave_p0_cke;
main_sdram_master_p0_odt <= main_sdram_slave_p0_odt;
main_sdram_master_p0_reset_n <= main_sdram_slave_p0_reset_n;
main_sdram_master_p0_act_n <= main_sdram_slave_p0_act_n;
main_sdram_master_p0_wrdata <= main_sdram_slave_p0_wrdata;
main_sdram_master_p0_wrdata_en <= main_sdram_slave_p0_wrdata_en;
main_sdram_master_p0_wrdata_mask <= main_sdram_slave_p0_wrdata_mask;
main_sdram_master_p0_rddata_en <= main_sdram_slave_p0_rddata_en;
main_sdram_slave_p0_rddata <= main_sdram_master_p0_rddata;
main_sdram_slave_p0_rddata_valid <= main_sdram_master_p0_rddata_valid;
main_sdram_master_p1_address <= main_sdram_slave_p1_address;
main_sdram_master_p1_bank <= main_sdram_slave_p1_bank;
main_sdram_master_p1_cas_n <= main_sdram_slave_p1_cas_n;
main_sdram_master_p1_cs_n <= main_sdram_slave_p1_cs_n;
main_sdram_master_p1_ras_n <= main_sdram_slave_p1_ras_n;
main_sdram_master_p1_we_n <= main_sdram_slave_p1_we_n;
main_sdram_master_p1_cke <= main_sdram_slave_p1_cke;
main_sdram_master_p1_odt <= main_sdram_slave_p1_odt;
main_sdram_master_p1_reset_n <= main_sdram_slave_p1_reset_n;
main_sdram_master_p1_act_n <= main_sdram_slave_p1_act_n;
main_sdram_master_p1_wrdata <= main_sdram_slave_p1_wrdata;
main_sdram_master_p1_wrdata_en <= main_sdram_slave_p1_wrdata_en;
main_sdram_master_p1_wrdata_mask <= main_sdram_slave_p1_wrdata_mask;
main_sdram_master_p1_rddata_en <= main_sdram_slave_p1_rddata_en;
main_sdram_slave_p1_rddata <= main_sdram_master_p1_rddata;
main_sdram_slave_p1_rddata_valid <= main_sdram_master_p1_rddata_valid;
main_sdram_master_p2_address <= main_sdram_slave_p2_address;
main_sdram_master_p2_bank <= main_sdram_slave_p2_bank;
main_sdram_master_p2_cas_n <= main_sdram_slave_p2_cas_n;
main_sdram_master_p2_cs_n <= main_sdram_slave_p2_cs_n;
main_sdram_master_p2_ras_n <= main_sdram_slave_p2_ras_n;
main_sdram_master_p2_we_n <= main_sdram_slave_p2_we_n;
main_sdram_master_p2_cke <= main_sdram_slave_p2_cke;
main_sdram_master_p2_odt <= main_sdram_slave_p2_odt;
main_sdram_master_p2_reset_n <= main_sdram_slave_p2_reset_n;
main_sdram_master_p2_act_n <= main_sdram_slave_p2_act_n;
main_sdram_master_p2_wrdata <= main_sdram_slave_p2_wrdata;
main_sdram_master_p2_wrdata_en <= main_sdram_slave_p2_wrdata_en;
main_sdram_master_p2_wrdata_mask <= main_sdram_slave_p2_wrdata_mask;
main_sdram_master_p2_rddata_en <= main_sdram_slave_p2_rddata_en;
main_sdram_slave_p2_rddata <= main_sdram_master_p2_rddata;
main_sdram_slave_p2_rddata_valid <= main_sdram_master_p2_rddata_valid;
main_sdram_master_p3_address <= main_sdram_slave_p3_address;
main_sdram_master_p3_bank <= main_sdram_slave_p3_bank;
main_sdram_master_p3_cas_n <= main_sdram_slave_p3_cas_n;
main_sdram_master_p3_cs_n <= main_sdram_slave_p3_cs_n;
main_sdram_master_p3_ras_n <= main_sdram_slave_p3_ras_n;
main_sdram_master_p3_we_n <= main_sdram_slave_p3_we_n;
main_sdram_master_p3_cke <= main_sdram_slave_p3_cke;
main_sdram_master_p3_odt <= main_sdram_slave_p3_odt;
main_sdram_master_p3_reset_n <= main_sdram_slave_p3_reset_n;
main_sdram_master_p3_act_n <= main_sdram_slave_p3_act_n;
main_sdram_master_p3_wrdata <= main_sdram_slave_p3_wrdata;
main_sdram_master_p3_wrdata_en <= main_sdram_slave_p3_wrdata_en;
main_sdram_master_p3_wrdata_mask <= main_sdram_slave_p3_wrdata_mask;
main_sdram_master_p3_rddata_en <= main_sdram_slave_p3_rddata_en;
main_sdram_slave_p3_rddata <= main_sdram_master_p3_rddata;
main_sdram_slave_p3_rddata_valid <= main_sdram_master_p3_rddata_valid;
end else begin
main_sdram_master_p0_address <= main_sdram_inti_p0_address;
main_sdram_master_p0_bank <= main_sdram_inti_p0_bank;
main_sdram_master_p0_cas_n <= main_sdram_inti_p0_cas_n;
main_sdram_master_p0_cs_n <= main_sdram_inti_p0_cs_n;
main_sdram_master_p0_ras_n <= main_sdram_inti_p0_ras_n;
main_sdram_master_p0_we_n <= main_sdram_inti_p0_we_n;
main_sdram_master_p0_cke <= main_sdram_inti_p0_cke;
main_sdram_master_p0_odt <= main_sdram_inti_p0_odt;
main_sdram_master_p0_reset_n <= main_sdram_inti_p0_reset_n;
main_sdram_master_p0_act_n <= main_sdram_inti_p0_act_n;
main_sdram_master_p0_wrdata <= main_sdram_inti_p0_wrdata;
main_sdram_master_p0_wrdata_en <= main_sdram_inti_p0_wrdata_en;
main_sdram_master_p0_wrdata_mask <= main_sdram_inti_p0_wrdata_mask;
main_sdram_master_p0_rddata_en <= main_sdram_inti_p0_rddata_en;
main_sdram_inti_p0_rddata <= main_sdram_master_p0_rddata;
main_sdram_inti_p0_rddata_valid <= main_sdram_master_p0_rddata_valid;
main_sdram_master_p1_address <= main_sdram_inti_p1_address;
main_sdram_master_p1_bank <= main_sdram_inti_p1_bank;
main_sdram_master_p1_cas_n <= main_sdram_inti_p1_cas_n;
main_sdram_master_p1_cs_n <= main_sdram_inti_p1_cs_n;
main_sdram_master_p1_ras_n <= main_sdram_inti_p1_ras_n;
main_sdram_master_p1_we_n <= main_sdram_inti_p1_we_n;
main_sdram_master_p1_cke <= main_sdram_inti_p1_cke;
main_sdram_master_p1_odt <= main_sdram_inti_p1_odt;
main_sdram_master_p1_reset_n <= main_sdram_inti_p1_reset_n;
main_sdram_master_p1_act_n <= main_sdram_inti_p1_act_n;
main_sdram_master_p1_wrdata <= main_sdram_inti_p1_wrdata;
main_sdram_master_p1_wrdata_en <= main_sdram_inti_p1_wrdata_en;
main_sdram_master_p1_wrdata_mask <= main_sdram_inti_p1_wrdata_mask;
main_sdram_master_p1_rddata_en <= main_sdram_inti_p1_rddata_en;
main_sdram_inti_p1_rddata <= main_sdram_master_p1_rddata;
main_sdram_inti_p1_rddata_valid <= main_sdram_master_p1_rddata_valid;
main_sdram_master_p2_address <= main_sdram_inti_p2_address;
main_sdram_master_p2_bank <= main_sdram_inti_p2_bank;
main_sdram_master_p2_cas_n <= main_sdram_inti_p2_cas_n;
main_sdram_master_p2_cs_n <= main_sdram_inti_p2_cs_n;
main_sdram_master_p2_ras_n <= main_sdram_inti_p2_ras_n;
main_sdram_master_p2_we_n <= main_sdram_inti_p2_we_n;
main_sdram_master_p2_cke <= main_sdram_inti_p2_cke;
main_sdram_master_p2_odt <= main_sdram_inti_p2_odt;
main_sdram_master_p2_reset_n <= main_sdram_inti_p2_reset_n;
main_sdram_master_p2_act_n <= main_sdram_inti_p2_act_n;
main_sdram_master_p2_wrdata <= main_sdram_inti_p2_wrdata;
main_sdram_master_p2_wrdata_en <= main_sdram_inti_p2_wrdata_en;
main_sdram_master_p2_wrdata_mask <= main_sdram_inti_p2_wrdata_mask;
main_sdram_master_p2_rddata_en <= main_sdram_inti_p2_rddata_en;
main_sdram_inti_p2_rddata <= main_sdram_master_p2_rddata;
main_sdram_inti_p2_rddata_valid <= main_sdram_master_p2_rddata_valid;
main_sdram_master_p3_address <= main_sdram_inti_p3_address;
main_sdram_master_p3_bank <= main_sdram_inti_p3_bank;
main_sdram_master_p3_cas_n <= main_sdram_inti_p3_cas_n;
main_sdram_master_p3_cs_n <= main_sdram_inti_p3_cs_n;
main_sdram_master_p3_ras_n <= main_sdram_inti_p3_ras_n;
main_sdram_master_p3_we_n <= main_sdram_inti_p3_we_n;
main_sdram_master_p3_cke <= main_sdram_inti_p3_cke;
main_sdram_master_p3_odt <= main_sdram_inti_p3_odt;
main_sdram_master_p3_reset_n <= main_sdram_inti_p3_reset_n;
main_sdram_master_p3_act_n <= main_sdram_inti_p3_act_n;
main_sdram_master_p3_wrdata <= main_sdram_inti_p3_wrdata;
main_sdram_master_p3_wrdata_en <= main_sdram_inti_p3_wrdata_en;
main_sdram_master_p3_wrdata_mask <= main_sdram_inti_p3_wrdata_mask;
main_sdram_master_p3_rddata_en <= main_sdram_inti_p3_rddata_en;
main_sdram_inti_p3_rddata <= main_sdram_master_p3_rddata;
main_sdram_inti_p3_rddata_valid <= main_sdram_master_p3_rddata_valid;
end
end
assign main_sdram_inti_p0_cke = main_sdram_storage[1];
assign main_sdram_inti_p1_cke = main_sdram_storage[1];
assign main_sdram_inti_p2_cke = main_sdram_storage[1];
assign main_sdram_inti_p3_cke = main_sdram_storage[1];
assign main_sdram_inti_p0_odt = main_sdram_storage[2];
assign main_sdram_inti_p1_odt = main_sdram_storage[2];
assign main_sdram_inti_p2_odt = main_sdram_storage[2];
assign main_sdram_inti_p3_odt = main_sdram_storage[2];
assign main_sdram_inti_p0_reset_n = main_sdram_storage[3];
assign main_sdram_inti_p1_reset_n = main_sdram_storage[3];
assign main_sdram_inti_p2_reset_n = main_sdram_storage[3];
assign main_sdram_inti_p3_reset_n = main_sdram_storage[3];
always @(*) begin
main_sdram_inti_p0_we_n <= 1\'d1;
main_sdram_inti_p0_cas_n <= 1\'d1;
main_sdram_inti_p0_cs_n <= 1\'d1;
main_sdram_inti_p0_ras_n <= 1\'d1;
if (main_sdram_phaseinjector0_command_issue_re) begin
main_sdram_inti_p0_cs_n <= {1{(~main_sdram_phaseinjector0_command_storage[0])}};
main_sdram_inti_p0_we_n <= (~main_sdram_phaseinjector0_command_storage[1]);
main_sdram_inti_p0_cas_n <= (~main_sdram_phaseinjector0_command_storage[2]);
main_sdram_inti_p0_ras_n <= (~main_sdram_phaseinjector0_command_storage[3]);
end else begin
main_sdram_inti_p0_cs_n <= {1{1\'d1}};
main_sdram_inti_p0_we_n <= 1\'d1;
main_sdram_inti_p0_cas_n <= 1\'d1;
main_sdram_inti_p0_ras_n <= 1\'d1;
end
end
assign main_sdram_inti_p0_address = main_sdram_phaseinjector0_address_storage;
assign main_sdram_inti_p0_bank = main_sdram_phaseinjector0_baddress_storage;
assign main_sdram_inti_p0_wrdata_en = (main_sdram_phaseinjector0_command_issue_re & main_sdram_phaseinjector0_command_storage[4]);
assign main_sdram_inti_p0_rddata_en = (main_sdram_phaseinjector0_command_issue_re & main_sdram_phaseinjector0_command_storage[5]);
assign main_sdram_inti_p0_wrdata = main_sdram_phaseinjector0_wrdata_storage;
assign main_sdram_inti_p0_wrdata_mask = 1\'d0;
always @(*) begin
main_sdram_inti_p1_we_n <= 1\'d1;
main_sdram_inti_p1_cas_n <= 1\'d1;
main_sdram_inti_p1_cs_n <= 1\'d1;
main_sdram_inti_p1_ras_n <= 1\'d1;
if (main_sdram_phaseinjector1_command_issue_re) begin
main_sdram_inti_p1_cs_n <= {1{(~main_sdram_phaseinjector1_command_storage[0])}};
main_sdram_inti_p1_we_n <= (~main_sdram_phaseinjector1_command_storage[1]);
main_sdram_inti_p1_cas_n <= (~main_sdram_phaseinjector1_command_storage[2]);
main_sdram_inti_p1_ras_n <= (~main_sdram_phaseinjector1_command_storage[3]);
end else begin
main_sdram_inti_p1_cs_n <= {1{1\'d1}};
main_sdram_inti_p1_we_n <= 1\'d1;
main_sdram_inti_p1_cas_n <= 1\'d1;
main_sdram_inti_p1_ras_n <= 1\'d1;
end
end
assign main_sdram_inti_p1_address = main_sdram_phaseinjector1_address_storage;
assign main_sdram_inti_p1_bank = main_sdram_phaseinjector1_baddress_storage;
assign main_sdram_inti_p1_wrdata_en = (main_sdram_phaseinjector1_command_issue_re & main_sdram_phaseinjector1_command_storage[4]);
assign main_sdram_inti_p1_rddata_en = (main_sdram_phaseinjector1_command_issue_re & main_sdram_phaseinjector1_command_storage[5]);
assign main_sdram_inti_p1_wrdata = main_sdram_phaseinjector1_wrdata_storage;
assign main_sdram_inti_p1_wrdata_mask = 1\'d0;
always @(*) begin
main_sdram_inti_p2_we_n <= 1\'d1;
main_sdram_inti_p2_cas_n <= 1\'d1;
main_sdram_inti_p2_cs_n <= 1\'d1;
main_sdram_inti_p2_ras_n <= 1\'d1;
if (main_sdram_phaseinjector2_command_issue_re) begin
main_sdram_inti_p2_cs_n <= {1{(~main_sdram_phaseinjector2_command_storage[0])}};
main_sdram_inti_p2_we_n <= (~main_sdram_phaseinjector2_command_storage[1]);
main_sdram_inti_p2_cas_n <= (~main_sdram_phaseinjector2_command_storage[2]);
main_sdram_inti_p2_ras_n <= (~main_sdram_phaseinjector2_command_storage[3]);
end else begin
main_sdram_inti_p2_cs_n <= {1{1\'d1}};
main_sdram_inti_p2_we_n <= 1\'d1;
main_sdram_inti_p2_cas_n <= 1\'d1;
main_sdram_inti_p2_ras_n <= 1\'d1;
end
end
assign main_sdram_inti_p2_address = main_sdram_phaseinjector2_address_storage;
assign main_sdram_inti_p2_bank = main_sdram_phaseinjector2_baddress_storage;
assign main_sdram_inti_p2_wrdata_en = (main_sdram_phaseinjector2_command_issue_re & main_sdram_phaseinjector2_command_storage[4]);
assign main_sdram_inti_p2_rddata_en = (main_sdram_phaseinjector2_command_issue_re & main_sdram_phaseinjector2_command_storage[5]);
assign main_sdram_inti_p2_wrdata = main_sdram_phaseinjector2_wrdata_storage;
assign main_sdram_inti_p2_wrdata_mask = 1\'d0;
always @(*) begin
main_sdram_inti_p3_we_n <= 1\'d1;
main_sdram_inti_p3_cas_n <= 1\'d1;
main_sdram_inti_p3_cs_n <= 1\'d1;
main_sdram_inti_p3_ras_n <= 1\'d1;
if (main_sdram_phaseinjector3_command_issue_re) begin
main_sdram_inti_p3_cs_n <= {1{(~main_sdram_phaseinjector3_command_storage[0])}};
main_sdram_inti_p3_we_n <= (~main_sdram_phaseinjector3_command_storage[1]);
main_sdram_inti_p3_cas_n <= (~main_sdram_phaseinjector3_command_storage[2]);
main_sdram_inti_p3_ras_n <= (~main_sdram_phaseinjector3_command_storage[3]);
end else begin
main_sdram_inti_p3_cs_n <= {1{1\'d1}};
main_sdram_inti_p3_we_n <= 1\'d1;
main_sdram_inti_p3_cas_n <= 1\'d1;
main_sdram_inti_p3_ras_n <= 1\'d1;
end
end
assign main_sdram_inti_p3_address = main_sdram_phaseinjector3_address_storage;
assign main_sdram_inti_p3_bank = main_sdram_phaseinjector3_baddress_storage;
assign main_sdram_inti_p3_wrdata_en = (main_sdram_phaseinjector3_command_issue_re & main_sdram_phaseinjector3_command_storage[4]);
assign main_sdram_inti_p3_rddata_en = (main_sdram_phaseinjector3_command_issue_re & main_sdram_phaseinjector3_command_storage[5]);
assign main_sdram_inti_p3_wrdata = main_sdram_phaseinjector3_wrdata_storage;
assign main_sdram_inti_p3_wrdata_mask = 1\'d0;
assign main_sdram_bankmachine0_req_valid = main_sdram_interface_bank0_valid;
assign main_sdram_interface_bank0_ready = main_sdram_bankmachine0_req_ready;
assign main_sdram_bankmachine0_req_we = main_sdram_interface_bank0_we;
assign main_sdram_bankmachine0_req_addr = main_sdram_interface_bank0_addr;
assign main_sdram_interface_bank0_lock = main_sdram_bankmachine0_req_lock;
assign main_sdram_interface_bank0_wdata_ready = main_sdram_bankmachine0_req_wdata_ready;
assign main_sdram_interface_bank0_rdata_valid = main_sdram_bankmachine0_req_rdata_valid;
'b"assign main_sdram_bankmachine1_req_valid = main_sdram_interface_bank1_valid;
assign main_sdram_interface_bank1_ready = main_sdram_bankmachine1_req_ready;
assign main_sdram_bankmachine1_req_we = main_sdram_interface_bank1_we;
assign main_sdram_bankmachine1_req_addr = main_sdram_interface_bank1_addr;
assign main_sdram_interface_bank1_lock = main_sdram_bankmachine1_req_lock;
assign main_sdram_interface_bank1_wdata_ready = main_sdram_bankmachine1_req_wdata_ready;
assign main_sdram_interface_bank1_rdata_valid = main_sdram_bankmachine1_req_rdata_valid;
assign main_sdram_bankmachine2_req_valid = main_sdram_interface_bank2_valid;
assign main_sdram_interface_bank2_ready = main_sdram_bankmachine2_req_ready;
assign main_sdram_bankmachine2_req_we = main_sdram_interface_bank2_we;
assign main_sdram_bankmachine2_req_addr = main_sdram_interface_bank2_addr;
assign main_sdram_interface_bank2_lock = main_sdram_bankmachine2_req_lock;
assign main_sdram_interface_bank2_wdata_ready = main_sdram_bankmachine2_req_wdata_ready;
assign main_sdram_interface_bank2_rdata_valid = main_sdram_bankmachine2_req_rdata_valid;
assign main_sdram_bankmachine3_req_valid = main_sdram_interface_bank3_valid;
assign main_sdram_interface_bank3_ready = main_sdram_bankmachine3_req_ready;
assign main_sdram_bankmachine3_req_we = main_sdram_interface_bank3_we;
assign main_sdram_bankmachine3_req_addr = main_sdram_interface_bank3_addr;
assign main_sdram_interface_bank3_lock = main_sdram_bankmachine3_req_lock;
assign main_sdram_interface_bank3_wdata_ready = main_sdram_bankmachine3_req_wdata_ready;
assign main_sdram_interface_bank3_rdata_valid = main_sdram_bankmachine3_req_rdata_valid;
assign main_sdram_bankmachine4_req_valid = main_sdram_interface_bank4_valid;
assign main_sdram_interface_bank4_ready = main_sdram_bankmachine4_req_ready;
assign main_sdram_bankmachine4_req_we = main_sdram_interface_bank4_we;
assign main_sdram_bankmachine4_req_addr = main_sdram_interface_bank4_addr;
assign main_sdram_interface_bank4_lock = main_sdram_bankmachine4_req_lock;
assign main_sdram_interface_bank4_wdata_ready = main_sdram_bankmachine4_req_wdata_ready;
assign main_sdram_interface_bank4_rdata_valid = main_sdram_bankmachine4_req_rdata_valid;
assign main_sdram_bankmachine5_req_valid = main_sdram_interface_bank5_valid;
assign main_sdram_interface_bank5_ready = main_sdram_bankmachine5_req_ready;
assign main_sdram_bankmachine5_req_we = main_sdram_interface_bank5_we;
assign main_sdram_bankmachine5_req_addr = main_sdram_interface_bank5_addr;
assign main_sdram_interface_bank5_lock = main_sdram_bankmachine5_req_lock;
assign main_sdram_interface_bank5_wdata_ready = main_sdram_bankmachine5_req_wdata_ready;
assign main_sdram_interface_bank5_rdata_valid = main_sdram_bankmachine5_req_rdata_valid;
assign main_sdram_bankmachine6_req_valid = main_sdram_interface_bank6_valid;
assign main_sdram_interface_bank6_ready = main_sdram_bankmachine6_req_ready;
assign main_sdram_bankmachine6_req_we = main_sdram_interface_bank6_we;
assign main_sdram_bankmachine6_req_addr = main_sdram_interface_bank6_addr;
assign main_sdram_interface_bank6_lock = main_sdram_bankmachine6_req_lock;
assign main_sdram_interface_bank6_wdata_ready = main_sdram_bankmachine6_req_wdata_ready;
assign main_sdram_interface_bank6_rdata_valid = main_sdram_bankmachine6_req_rdata_valid;
assign main_sdram_bankmachine7_req_valid = main_sdram_interface_bank7_valid;
assign main_sdram_interface_bank7_ready = main_sdram_bankmachine7_req_ready;
assign main_sdram_bankmachine7_req_we = main_sdram_interface_bank7_we;
assign main_sdram_bankmachine7_req_addr = main_sdram_interface_bank7_addr;
assign main_sdram_interface_bank7_lock = main_sdram_bankmachine7_req_lock;
assign main_sdram_interface_bank7_wdata_ready = main_sdram_bankmachine7_req_wdata_ready;
assign main_sdram_interface_bank7_rdata_valid = main_sdram_bankmachine7_req_rdata_valid;
assign main_sdram_timer_wait = (~main_sdram_timer_done0);
assign main_sdram_postponer_req_i = main_sdram_timer_done0;
assign main_sdram_wants_refresh = main_sdram_postponer_req_o;
assign main_sdram_wants_zqcs = main_sdram_zqcs_timer_done0;
assign main_sdram_zqcs_timer_wait = (~main_sdram_zqcs_executer_done);
assign main_sdram_timer_done1 = (main_sdram_timer_count1 == 1'd0);
assign main_sdram_timer_done0 = main_sdram_timer_done1;
assign main_sdram_timer_count0 = main_sdram_timer_count1;
assign main_sdram_sequencer_start1 = (main_sdram_sequencer_start0 | (main_sdram_sequencer_count != 1'd0));
assign main_sdram_sequencer_done0 = (main_sdram_sequencer_done1 & (main_sdram_sequencer_count == 1'd0));
assign main_sdram_zqcs_timer_done1 = (main_sdram_zqcs_timer_count1 == 1'd0);
assign main_sdram_zqcs_timer_done0 = main_sdram_zqcs_timer_done1;
assign main_sdram_zqcs_timer_count0 = main_sdram_zqcs_timer_count1;
always @(*) begin
main_sdram_cmd_valid <= 1'd0;
builder_refresher_next_state <= 2'd0;
main_sdram_zqcs_executer_start <= 1'd0;
main_sdram_cmd_last <= 1'd0;
main_sdram_sequencer_start0 <= 1'd0;
builder_refresher_next_state <= builder_refresher_state;
case (builder_refresher_state)
1'd1: begin
main_sdram_cmd_valid <= 1'd1;
if (main_sdram_cmd_ready) begin
main_sdram_sequencer_start0 <= 1'd1;
builder_refresher_next_state <= 2'd2;
end
end
2'd2: begin
main_sdram_cmd_valid <= 1'd1;
if (main_sdram_sequencer_done0) begin
if (main_sdram_wants_zqcs) begin
main_sdram_zqcs_executer_start <= 1'd1;
builder_refresher_next_state <= 2'd3;
end else begin
main_sdram_cmd_valid <= 1'd0;
main_sdram_cmd_last <= 1'd1;
builder_refresher_next_state <= 1'd0;
end
end
end
2'd3: begin
main_sdram_cmd_valid <= 1'd1;
if (main_sdram_zqcs_executer_done) begin
main_sdram_cmd_valid <= 1'd0;
main_sdram_cmd_last <= 1'd1;
builder_refresher_next_state <= 1'd0;
end
end
default: begin
if (1'd1) begin
if (main_sdram_wants_refresh) begin
builder_refresher_next_state <= 1'd1;
end
end
end
endcase
end
assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine0_req_valid;
assign main_sdram_bankmachine0_req_ready = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine0_req_we;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine0_req_addr;
assign main_sdram_bankmachine0_cmd_buffer_sink_valid = main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine0_cmd_buffer_sink_ready;
assign main_sdram_bankmachine0_cmd_buffer_sink_first = main_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine0_cmd_buffer_sink_last = main_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine0_cmd_buffer_sink_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine0_cmd_buffer_sink_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine0_cmd_buffer_source_ready = (main_sdram_bankmachine0_req_wdata_ready | main_sdram_bankmachine0_req_rdata_valid);
assign main_sdram_bankmachine0_req_lock = (main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine0_cmd_buffer_source_valid);
assign main_sdram_bankmachine0_row_hit = (main_sdram_bankmachine0_row == main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
main_sdram_bankmachine0_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine0_row_col_n_addr_sel) begin
main_sdram_bankmachine0_cmd_payload_a <= main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine0_cmd_payload_a <= ((main_sdram_bankmachine0_auto_precharge <<< 4'd10) | {
main_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}
});
end
end
assign main_sdram_bankmachine0_twtpcon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_cmd_payload_is_write);
assign main_sdram_bankmachine0_trccon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_row_open);
assign main_sdram_bankmachine0_trascon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_row_open);
always @(*) begin
main_sdram_bankmachine0_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine0_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine0_auto_precharge <= (main_sdram_bankmachine0_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {
main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last,
main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first,
main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr,
main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we
};
assign {main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_first = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_last = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine0_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_sdram_bankmachine0_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
assign main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine0_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine0_cmd_buffer_sink_ready = ((~main_sdram_bankmachine0_cmd_buffer_source_valid) | main_sdram_bankmachine0_cmd_buffer_source_ready);
always @(*) begin
main_sdram_bankmachine0_row_open <= 1'd0;
main_sdram_bankmachine0_row_close <= 1'd0;
main_sdram_bankmachine0_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine0_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine0_cmd_payload_we <= 1'd0;
main_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine0_req_wdata_ready <= 1'd0;
builder_bankmachine0_next_state <= 3'd0;
main_sdram_bankmachine0_req_rdata_valid <= 1'd0;
main_sdram_bankmachine0_refresh_gnt <= 1'd0;
main_sdram_bankmachine0_cmd_valid <= 1'd0;
builder_bankmachine0_next_state <= builder_bankmachine0_state;
case (builder_bankmachine0_state)
1'd1: begin
if ((main_sdram_bankmachine0_twtpcon_ready & main_sdram_bankmachine0_trascon_ready)) begin
main_sdram_bankmachine0_cmd_valid <= 1'd1;
if (main_sdram_bankmachine0_cmd_ready) begin
builder_bankmachine0_next_state <= 3'd5;
end
main_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine0_cmd_payload_we <= 1'd1;
main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine0_twtpcon_ready & main_sdram_bankmachine0_trascon_ready)) begin
builder_bankmachine0_next_state <= 3'd5;
end
main_sdram_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine0_trccon_ready) begin
main_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine0_row_open <= 1'd1;
main_sdram_bankmachine0_cmd_valid <= 1'd1;
main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine0_cmd_ready) begin
builder_bankmachine0_next_state <= 3'd6;
end
main_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine0_twtpcon_ready) begin
main_sdram_bankmachine0_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine0_row_close <= 1'd1;
main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine0_refresh_req)) begin
builder_bankmachine0_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine0_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine0_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine0_refresh_req) begin
builder_bankmachine0_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine0_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine0_row_opened) begin
if (main_sdram_bankmachine0_row_hit) begin
main_sdram_bankmachine0_cmd_valid <= 1'd1;
if (main_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine0_req_wdata_ready <= main_sdram_bankmachine0_cmd_ready;
main_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine0_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine0_req_rdata_valid <= main_sdram_bankmachine0_cmd_ready;
main_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine0_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine0_cmd_ready & main_sdram_bankmachine0_auto_precharge)) begin
builder_bankmachine0_next_state <= 2'd2;
end
end else begin
builder_bankmachine0_next_state <= 1'd1;
end
end else begin
builder_bankmachine0_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine1_req_valid;
assign main_sdram_bankmachine1_req_ready = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine1_req_we;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine1_req_addr;
assign main_sdram_bankmachine1_cmd_buffer_sink_valid = main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine1_cmd_buffer_sink_ready;
assign main_sdram_bankmachine1_cmd_buffer_sink_first = main_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine1_cmd_buffer_sink_last = main_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine1_cmd_buffer_sink_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine1_cmd_buffer_sink_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine1_cmd_buffer_source_ready = (main_sdram_bankmachine1_req_wdata_ready | main_sdram_bankmachine1_req_rdata_valid);
assign main_sdram_bankmachine1_req_lock = (main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine1_cmd_buffer_source_valid);
assign main_sdram_bankmachine1_row_hit = (main_sdram_bankmachine1_row == main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
main_sdram_bankmachine1_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine1_row_col_n_addr_sel) begin
main_sdram_bankmachine1_cmd_payload_a <= main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine1_cmd_payload_a <= ((main_sdram_bankmachine1_auto_precharge <<< 4'd10) | {
main_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}
});
end
end
assign main_sdram_bankmachine1_twtpcon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_cmd_payload_is_write);
assign main_sdram_bankmachine1_trccon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_row_open);
assign main_sdram_bankmachine1_trascon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_row_open);
always @(*) begin
main_sdram_bankmachine1_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine1_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine1_auto_precharge <= (main_sdram_bankmachine1_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {
main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last,
main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first,
main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr,
main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we
};
assign {main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_first = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_last = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine1_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_sdram_bankmachine1_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
assign main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine1_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine1_cmd_buffer_sink_ready = ((~main_sdram_bankmachine1_cmd_buffer_source_valid) | main_sdram_bankmachine1_cmd_buffer_source_ready);
always @(*) begin
main_sdram_bankmachine1_row_open <= 1'd0;
main_sdram_bankmachine1_row_close <= 1'd0;
main_sdram_bankmachine1_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine1_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine1_cmd_payload_we <= 1'd0;
main_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
builder_bankmachine1_next_state <= 3'd0;
main_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine1_req_wdata_ready <= 1'd0;
main_sdram_bankmachine1_req_rdata_valid <= 1'd0;
main_sdram_bankmachine1_refresh_gnt <= 1'd0;
main_sdram_bankmachine1_cmd_valid <= 1'd0;
builder_bankmachine1_next_state <= builder_bankmachine1_state;
case (builder_bankmachine1_state)
1'd1: begin
if ((main_sdram_bankmachine1_twtpcon_ready & main_sdram_bankmachine1_trascon_ready)) begin
main_sdram_bankmachine1_cmd_valid <= 1'd1;
if (main_sdram_bankmachine1_cmd_ready) begin
builder_bankmachine1_next_state <= 3'd5;
end
main_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine1_cmd_payload_we <= 1'd1;
main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine1_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine1_twtpcon_ready & main_sdram_bankmachine1_trascon_ready)) begin
builder_bankmachine1_next_state <= 3'd5;
end
main_sdram_bankmachine1_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine1_trccon_ready) begin
main_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine1_row_open <= 1'd1;
main_sdram_bankmachine1_cmd_valid <= 1'd1;
main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine1_cmd_ready) begin
builder_bankmachine1_next_state <= 3'd6;
end
main_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine1_twtpcon_ready) begin
main_sdram_bankmachine1_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine1_row_close <= 1'd1;
main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine1_refresh_req)) begin
builder_bankmachine1_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine1_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine1_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine1_refresh_req) begin
builder_bankmachine1_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine1_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine1_row_opened) begin
if (main_sdram_bankmachine1_row_hit) begin
main_sdram_bankmachine1_cmd_valid <= 1'd1;
if (main_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine1_req_wdata_ready <= main_sdram_bankmachine1_cmd_ready;
main_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine1_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine1_req_rdata_valid <= main_sdram_bankmachine1_cmd_ready;
main_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine1_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine1_cmd_ready & main_sdram_bankmachine1_auto_precharge)) begin
builder_bankmachine1_next_state <= 2'd2;
end
end else begin
builder_bankmachine1_next_state <= 1'd1;
end
end else begin
builder_bankmachine1_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine2_req_valid;
assign main_sdram_bankmachine2_req_ready = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine2_req_we;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine2_req_addr;
assign main_sdram_bankmachine2_cmd_buffer_sink_valid = main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine2_cmd_buffer_sink_ready;
assign main_sdram_bankmachine2_cmd_buffer_sink_first = main_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine2_cmd_buffer_sink_last = main_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine2_cmd_buffer_sink_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine2_cmd_buffer_sink_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine2_cmd_buffer_source_ready = (main_sdram_bankmachine2_req_wdata_ready | main_sdram_bankmachine2_req_rdata_valid);
assign main_sdram_bankmachine2_req_lock = (main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine2_cmd_buffer_source_valid);
assign main_sdram_bankmachine2_row_hit = (main_sdram_bankmachine2_row == main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
main_sdram_bankmachine2_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine2_row_col_n_addr_sel) begin
main_sdram_bankmachine2_cmd_payload_a <= main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine2_cmd_payload_a <= ((main_sdram_bankmachine2_auto_precharge <<< 4'd10) | {
main_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}
});
end
end
assign main_sdram_bankmachine2_twtpcon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_cmd_payload_is_write);
assign main_sdram_bankmachine2_trccon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_row_open);
assign main_sdram_bankmachine2_trascon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_row_open);
always @(*) begin
main_sdram_bankmachine2_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine2_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine2_auto_precharge <= (main_sdram_bankmachine2_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {
main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last,
main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first,
main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr,
main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we
};
assign {main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_first = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_last = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine2_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_sdram_bankmachine2_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
assign main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine2_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine2_cmd_buffer_sink_ready = ((~main_sdram_bankmachine2_cmd_buffer_source_valid) | main_sdram_bankmachine2_cmd_buffer_source_ready);
always @(*) begin
main_sdram_bankmachine2_row_open <= 1'd0;
main_sdram_bankmachine2_row_close <= 1'd0;
main_sdram_bankmachine2_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine2_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine2_cmd_payload_we <= 1'd0;
main_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
builder_bankmachine2_next_state <= 3'd0;
main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine2_req_wdata_ready <= 1'd0;
main_sdram_bankmachine2_req_rdata_valid <= 1'd0;
main_sdram_bankmachine2_refresh_gnt <= 1'd0;
main_sdram_bankmachine2_cmd_valid <= 1'd0;
builder_bankmachine2_next_state <= builder_bankmachine2_state;
case (builder_bankmachine2_state)
1'd1: begin
if ((main_sdram_bankmachine2_twtpcon_ready & main_sdram_bankmachine2_trascon_ready)) begin
main_sdram_bankmachine2_cmd_valid <= 1'd1;
if (main_sdram_bankmachine2_cmd_ready) begin
builder_bankmachine2_next_state <= 3'd5;
end
main_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine2_cmd_payload_we <= 1'd1;
main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine2_twtpcon_ready & main_sdram_bankmachine2_trascon_ready)) begin
builder_bankmachine2_next_state <= 3'd5;
end
main_sdram_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine2_trccon_ready) begin
main_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine2_row_open <= 1'd1;
main_sdram_bankmachine2_cmd_valid <= 1'd1;
main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine2_cmd_ready) begin
builder_bankmachine2_next_state <= 3'd6;
end
main_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine2_twtpcon_ready) begin
main_sdram_bankmachine2_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine2_row_close <= 1'd1;
main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine2_refresh_req)) begin
builder_bankmachine2_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine2_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine2_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine2_refresh_req) begin
builder_bankmachine2_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine2_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine2_row_opened) begin
if (main_sdram_bankmachine2_row_hit) begin
main_sdram_bankmachine2_cmd_valid <= 1'd1;
if (main_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine2_req_wdata_ready <= main_sdram_bankmachine2_cmd_ready;
main_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine2_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine2_req_rdata_valid <= main_sdram_bankmachine2_cmd_ready;
main_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine2_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine2_cmd_ready & main_sdram_bankmachine2_auto_precharge)) begin
builder_bankmachine2_next_state <= 2'd2;
end
end else begin
builder_bankmachine2_next_state <= 1'd1;
end
end else begin
builder_bankmachine2_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine3_req_valid;
assign main_sdram_bankmachine3_req_ready = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine3_req_we;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine3_req_addr;
assign main_sdram_bankmachine3_cmd_buffer_sink_valid = main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine3_cmd_buffer_sink_ready;
assign main_sdram_bankmachine3_cmd_buffer_sink_first = main_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine3_cmd_buffer_sink_last = main_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine3_cmd_buffer_sink_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine3_cmd_buffer_sink_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine3_cmd_buffer_source_ready = (main_sdram_bankmachine3_req_wdata_ready | main_sdram_bankmachine3_req_rdata_valid);
assign main_sdram_bankmachine3_req_lock = (main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine3_cmd_buffer_source_valid);
assign main_sdram_bankmachine3_row_hit = (main_sdram_bankmachine3_row == main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
main_sdram_bankmachine3_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine3_row_col_n_addr_sel) begin
main_sdram_bankmachine3_cmd_payload_a <= main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine3_cmd_payload_a <= ((main_sdram_bankmachine3_auto_precharge <<< 4'd10) | {
main_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}
});
end
end
assign main_sdram_bankmachine3_twtpcon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_cmd_payload_is_write);
assign main_sdram_bankmachine3_trccon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_row_open);
assign main_sdram_bankmachine3_trascon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_row_open);
always @(*) begin
main_sdram_bankmachine3_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine3_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine3_auto_precharge <= (main_sdram_bankmachine3_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {
main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last,
main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first,
main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr,
main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we
};
assign {main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_first = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_last = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine3_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_sdram_bankmachine3_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
assign main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine3_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine3_cmd_buffer_sink_ready = ((~main_sdram_bankmachine3_cmd_buffer_source_valid) | main_sdram_bankmachine3_cmd_buffer_source_ready);
always @(*) begin
main_sdram_bankmachine3_row_open <= 1'd0;
main_sdram_bankmachine3_row_close <= 1'd0;
main_sdram_bankmachine3_cmd_payload_cas <= 1'd0;
builder_bankmachine3_next_state <= 3'd0;
main_sdram_bankmachine3_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine3_cmd_payload_we <= 1'd0;
main_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine3_req_wdata_ready <= 1'd0;
main_sdram_bankmachine3_req_rdata_valid <= 1'd0;
main_sdram_bankmachine3_refresh_gnt <= 1'd0;
main_sdram_bankmachine3_cmd_valid <= 1'd0;
builder_bankmachine3_next_state <= builder_bankmachine3_state;
case (builder_bankmachine3_state)
1'd1: begin
if ((main_sdram_bankmachine3_twtpcon_ready & main_sdram_bankmachine3_trascon_ready)) begin
main_sdram_bankmachine3_cmd_valid <= 1'd1;
if (main_sdram_bankmachine3_cmd_ready) begin
builder_bankmachine3_next_state <= 3'd5;
end
main_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine3_cmd_payload_we <= 1'd1;
main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine3_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine3_twtpcon_ready & main_sdram_bankmachine3_trascon_ready)) begin
builder_bankmachine3_next_state <= 3'd5;
end
main_sdram_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine3_trccon_ready) begin
main_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine3_row_open <= 1'd1;
main_sdram_bankmachine3_cmd_valid <= 1'd1;
main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine3_cmd_ready) begin
builder_bankmachine3_next_state <= 3'd6;
end
main_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine3_twtpcon_ready) begin
main_sdram_bankmachine3_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine3_row_close <= 1'd1;
main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine3_refresh_req)) begin
builder_bankmachine3_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine3_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine3_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine3_refresh_req) begin
builder_bankmachine3_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine3_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine3_row_opened) begin
if (main_sdram_bankmachine3_row_hit) begin
main_sdram_bankmachine3_cmd_valid <= 1'd1;
if (main_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine3_req_wdata_ready <= main_sdram_bankmachine3_cmd_ready;
main_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine3_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine3_req_rdata_valid <= main_sdram_bankmachine3_cmd_ready;
main_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine3_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine3_cmd_ready & main_sdram_bankmachine3_auto_precharge)) begin
builder_bankmachine3_next_state <= 2'd2;
end
end else begin
builder_bankmachine3_next_state <= 1'd1;
end
end else begin
builder_bankmachine3_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine4_req_valid;
assign main_sdram_bankmachine4_req_ready = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine4_req_we;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine4_req_addr;
assign main_sdram_bankmachine4_cmd_buffer_sink_valid = main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine4_cmd_buffer_sink_ready;
assign main_sdram_bankmachine4_cmd_buffer_sink_first = main_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine4_cmd_buffer_sink_last = main_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine4_cmd_buffer_sink_payload_we = main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine4_cmd_buffer_sink_payload_addr = main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine4_cmd_buffer_source_ready = (main_sdram_bankmachine4_req_wdata_ready | main_sdram_bankmachine4_req_rdata_valid);
assign main_sdram_bankmachine4_req_lock = (main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine4_cmd_buffer_source_valid);
assign main_sdram_bankmachine4_row_hit = (main_sdram_bankmachine4_row == main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
main_sdram_bankmachine4_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine4_row_col_n_addr_sel) begin
main_sdram_bankmachine4_cmd_payload_a <= main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine4_cmd_payload_a <= ((main_sdram_bankmachine4_auto_precharge <<< 4'd10) | {
main_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}
});
end
end
assign main_sdram_bankmachine4_twtpcon_valid = ((main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_ready) & main_sdram_bankmachine4_cmd_payload_is_write);
assign main_sdram_bankmachine4_trccon_valid = ((main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_ready) & main_sdram_bankmachine4_row_open);
assign main_sdram_bankmachine4_trascon_valid = ((main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_ready) & main_sdram_bankmachine4_row_open);
always @(*) begin
main_sdram_bankmachine4_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine4_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine4_auto_precharge <= (main_sdram_bankmachine4_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {
main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last,
main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first,
main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr,
main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we
};
assign {main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_first = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_last = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine4_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_sdram_bankmachine4_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
assign main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine4_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_sdram_bankmachine4_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine4_cmd_buffer_sink_ready = ((~main_sdram_bankmachine4_cmd_buffer_source_valid) | main_sdram_bankmachine4_cmd_buffer_source_ready);
always @(*) begin
main_sdram_bankmachine4_row_open <= 1'd0;
main_sdram_bankmachine4_row_close <= 1'd0;
builder_bankmachine4_next_state <= 3'd0;
main_sdram_bankmachine4_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine4_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine4_cmd_payload_we <= 1'd0;
main_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine4_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine4_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine4_req_wdata_ready <= 1'd0;
main_sdram_bankmachine4_req_rdata_valid <= 1'd0;
main_sdram_bankmachine4_refresh_gnt <= 1'd0;
main_sdram_bankmachine4_cmd_valid <= 1'd0;
builder_bankmachine4_next_state <= builder_bankmachine4_state;
case (builder_bankmachine4_state)
1'd1: begin
if ((main_sdram_bankmachine4_twtpcon_ready & main_sdram_bankmachine4_trascon_ready)) begin
main_sdram_bankmachine4_cmd_valid <= 1'd1;
if (main_sdram_bankmachine4_cmd_ready) begin
builder_bankmachine4_next_state <= 3'd5;
end
main_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine4_cmd_payload_we <= 1'd1;
main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine4_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine4_twtpcon_ready & main_sdram_bankmachine4_trascon_ready)) begin
builder_bankmachine4_next_state <= 3'd5;
end
main_sdram_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine4_trccon_ready) begin
main_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine4_row_open <= 1'd1;
main_sdram_bankmachine4_cmd_valid <= 1'd1;
main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine4_cmd_ready) begin
builder_bankmachine4_next_state <= 3'd6;
end
main_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine4_twtpcon_ready) begin
main_sdram_bankmachine4_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine4_row_close <= 1'd1;
main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine4_refresh_req)) begin
builder_bankmachine4_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine4_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine4_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine4_refresh_req) begin
builder_bankmachine4_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine4_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine4_row_opened) begin
if (main_sdram_bankmachine4_row_hit) begin
main_sdram_bankmachine4_cmd_valid <= 1'd1;
if (main_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine4_req_wdata_ready <= main_sdram_bankmachine4_cmd_ready;
main_sdram_bankmachine4_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine4_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine4_req_rdata_valid <= main_sdram_bankmachine4_cmd_ready;
main_sdram_bankmachine4_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine4_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine4_cmd_ready & main_sdram_bankmachine4_auto_precharge)) begin
builder_bankmachine4_next_state <= 2'd2;
end
end else begin
builder_bankmachine4_next_state <= 1'd1;
end
end else begin
builder_bankmachine4_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine5_req_valid;
assign main_sdram_bankmachine5_req_ready = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine5_req_we;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine5_req_addr;
assign main_sdram_bankmachine5_cmd_buffer_sink_valid = main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine5_cmd_buffer_sink_ready;
assign main_sdram_bankmachine5_cmd_buffer_sink_first = main_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine5_cmd_buffer_sink_last = main_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine5_cmd_buffer_sink_payload_we = main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine5_cmd_buffer_sink_payload_addr = main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine5_cmd_buffer_source_ready = (main_sdram_bankmachine5_req_wdata_ready | main_sdram_bankmachine5_req_rdata_valid);
assign main_sdram_bankmachine5_req_lock = (main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine5_cmd_buffer_source_valid);
assign main_sdram_bankmachine5_row_hit = (main_sdram_bankmachine5_row == main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
main_sdram_bankmachine5_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine5_row_col_n_addr_sel) begin
main_sdram_bankmachine5_cmd_payload_a <= main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine5_cmd_payload_a <= ((main_sdram_bankmachine5_auto_precharge <<< 4'd10) | {
main_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}
});
end
end
assign main_sdram_bankmachine5_twtpcon_valid = ((main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_ready) & main_sdram_bankmachine5_cmd_payload_is_write);
assign main_sdram_bankmachine5_trccon_valid = ((main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_ready) & main_sdram_bankmachine5_row_open);
assign main_sdram_bankmachine5_trascon_valid = ((main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_ready) & main_sdram_bankmachine5_row_open);
always @(*) begin
main_sdram_bankmachine5_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine5_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine5_auto_precharge <= (main_sdram_bankmachine5_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {
main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last,
main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first,
main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr,
main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we
};
assign {main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_first = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_last = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine5_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_sdram_bankmachine5_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
assign main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine5_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_sdram_bankmachine5_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine5_cmd_buffer_sink_ready = ((~main_sdram_bankmachine5_cmd_buffer_source_valid) | main_sdram_bankmachine5_cmd_buffer_source_ready);
always @(*) begin
builder_bankmachine5_next_state <= 3'd0;
main_sdram_bankmachine5_row_open <= 1'd0;
main_sdram_bankmachine5_row_close <= 1'd0;
main_sdram_bankmachine5_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine5_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine5_cmd_payload_we <= 1'd0;
main_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine5_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine5_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine5_req_wdata_ready <= 1'd0;
main_sdram_bankmachine5_req_rdata_valid <= 1'd0;
main_sdram_bankmachine5_refresh_gnt <= 1'd0;
main_sdram_bankmachine5_cmd_valid <= 1'd0;
builder_bankmachine5_next_state <= builder_bankmachine5_state;
case (builder_bankmachine5_state)
1'd1: begin
if ((main_sdram_bankmachine5_twtpcon_ready & main_sdram_bankmachine5_trascon_ready)) begin
main_sdram_bankmachine5_cmd_valid <= 1'd1;
if (main_sdram_bankmachine5_cmd_ready) begin
builder_bankmachine5_next_state <= 3'd5;
end
main_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine5_cmd_payload_we <= 1'd1;
main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine5_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine5_twtpcon_ready & main_sdram_bankmachine5_trascon_ready)) begin
builder_bankmachine5_next_state <= 3'd5;
end
main_sdram_bankmachine5_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine5_trccon_ready) begin
main_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine5_row_open <= 1'd1;
main_sdram_bankmachine5_cmd_valid <= 1'd1;
main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine5_cmd_ready) begin
builder_bankmachine5_next_state <= 3'd6;
end
main_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine5_twtpcon_ready) begin
main_sdram_bankmachine5_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine5_row_close <= 1'd1;
main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine5_refresh_req)) begin
builder_bankmachine5_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine5_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine5_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine5_refresh_req) begin
builder_bankmachine5_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine5_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine5_row_opened) begin
if (main_sdram_bankmachine5_row_hit) begin
main_sdram_bankmachine5_cmd_valid <= 1'd1;
if (main_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine5_req_wdata_ready <= main_sdram_bankmachine5_cmd_ready;
main_sdram_bankmachine5_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine5_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine5_req_rdata_valid <= main_sdram_bankmachine5_cmd_ready;
main_sdram_bankmachine5_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine5_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine5_cmd_ready & main_sdram_bankmachine5_auto_precharge)) begin
builder_bankmachine5_next_state <= 2'd2;
end
end else begin
builder_bankmachine5_next_state <= 1'd1;
end
end else begin
builder_bankmachine5_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine6_req_valid;
assign main_sdram_bankmachine6_req_ready = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine6_req_we;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine6_req_addr;
assign main_sdram_bankmachine6_cmd_buffer_sink_valid = main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine6_cmd_buffer_sink_ready;
assign main_sdram_bankmachine6_cmd_buffer_sink_first = main_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine6_cmd_buffer_sink_last = main_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine6_cmd_buffer_sink_payload_we = main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine6_cmd_buffer_sink_payload_addr = main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine6_cmd_buffer_source_ready = (main_sdram_bankmachine6_req_wdata_ready | main_sdram_bankmachine6_req_rdata_valid);
assign main_sdram_bankmachine6_req_lock = (main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine6_cmd_buffer_source_valid);
assign main_sdram_bankmachine6_row_hit = (main_sdram_bankmachine6_row == main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
main_sdram_bankmachine6_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine6_row_col_n_addr_sel) begin
main_sdram_bankmachine6_cmd_payload_a <= main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine6_cmd_payload_a <= ((main_sdram_bankmachine6_auto_precharge <<< 4'd10) | {
main_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}
});
end
end
assign main_sdram_bankmachine6_twtpcon_valid = ((main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_ready) & main_sdram_bankmachine6_cmd_payload_is_write);
assign main_sdram_bankmachine6_trccon_valid = ((main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_ready) & main_sdram_bankmachine6_row_open);
assign main_sdram_bankmachine6_trascon_valid = ((main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_ready) & main_sdram_bankmachine6_row_open);
always @(*) begin
main_sdram_bankmachine6_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine6_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine6_auto_precharge <= (main_sdram_bankmachine6_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {
main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last,
main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first,
main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr,
main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we
};
assign {main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_first = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_last = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine6_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_sdram_bankmachine6_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
assign main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine6_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_sdram_bankmachine6_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine6_cmd_buffer_sink_ready = ((~main_sdram_bankmachine6_cmd_buffer_source_valid) | main_sdram_bankmachine6_cmd_buffer_source_ready);
always @(*) begin
main_sdram_bankmachine6_row_open <= 1'd0;
main_sdram_bankmachine6_row_close <= 1'd0;
main_sdram_bankmachine6_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine6_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine6_cmd_payload_we <= 1'd0;
main_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine6_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine6_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine6_req_wdata_ready <= 1'd0;
main_sdram_bankmachine6_req_rdata_valid <= 1'd0;
main_sdram_bankmachine6_refresh_gnt <= 1'd0;
main_sdram_bankmachine6_cmd_valid <= 1'd0;
builder_bankmachine6_next_state <= 3'd0;
builder_bankmachine6_next_state <= builder_bankmachine6_state;
case (builder_bankmachine6_state)
1'd1: begin
if ((main_sdram_bankmachine6_twtpcon_ready & main_sdram_bankmachine6_trascon_ready)) begin
main_sdram_bankmachine6_cmd_valid <= 1'd1;
if (main_sdram_bankmachine6_cmd_ready) begin
builder_bankmachine6_next_state <= 3'd5;
end
main_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine6_cmd_payload_we <= 1'd1;
main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine6_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine6_twtpcon_ready & main_sdram_bankmachine6_trascon_ready)) begin
builder_bankmachine6_next_state <= 3'd5;
end
main_sdram_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine6_trccon_ready) begin
main_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine6_row_open <= 1'd1;
main_sdram_bankmachine6_cmd_valid <= 1'd1;
main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine6_cmd_ready) begin
builder_bankmachine6_next_state <= 3'd6;
end
main_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine6_twtpcon_ready) begin
main_sdram_bankmachine6_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine6_row_close <= 1'd1;
main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine6_refresh_req)) begin
builder_bankmachine6_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine6_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine6_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine6_refresh_req) begin
builder_bankmachine6_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine6_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine6_row_opened) begin
if (main_sdram_bankmachine6_row_hit) begin
main_sdram_bankmachine6_cmd_valid <= 1'd1;
if (main_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine6_req_wdata_ready <= main_sdram_bankmachine6_cmd_ready;
main_sdram_bankmachine6_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine6_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine6_req_rdata_valid <= main_sdram_bankmachine6_cmd_ready;
main_sdram_bankmachine6_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine6_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine6_cmd_ready & main_sdram_bankmachine6_auto_precharge)) begin
builder_bankmachine6_next_state <= 2'd2;
end
end else begin
builder_bankmachine6_next_state <= 1'd1;
end
end else begin
builder_bankmachine6_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine7_req_valid;
assign main_sdram_bankmachine7_req_ready = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine7_req_we;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine7_req_addr;
assign main_sdram_bankmachine7_cmd_buffer_sink_valid = main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine7_cmd_buffer_sink_ready;
assign main_sdram_bankmachine7_cmd_buffer_sink_first = main_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine7_cmd_buffer_sink_last = main_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine7_cmd_buffer_sink_payload_we = main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine7_cmd_buffer_sink_payload_addr = main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine7_cmd_buffer_source_ready = (main_sdram_bankmachine7_req_wdata_ready | main_sdram_bankmachine7_req_rdata_valid);
assign main_sdram_bankmachine7_req_lock = (main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine7_cmd_buffer_source_valid);
assign main_sdram_bankmachine7_row_hit = (main_sdram_bankmachine7_row == main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
main_sdram_bankmachine7_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine7_row_col_n_addr_sel) begin
main_sdram_bankmachine7_cmd_payload_a <= main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine7_cmd_payload_a <= ((main_sdram_bankmachine7_auto_precharge <<< 4'd10) | {
main_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}
});
end
end
assign main_sdram_bankmachine7_twtpcon_valid = ((main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_ready) & main_sdram_bankmachine7_cmd_payload_is_write);
assign main_sdram_bankmachine7_trccon_valid = ((main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_ready) & main_sdram_bankmachine7_row_open);
assign main_sdram_bankmachine7_trascon_valid = ((main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_ready) & main_sdram_bankmachine7_row_open);
always @(*) begin
main_sdram_bankmachine7_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine7_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine7_auto_precharge <= (main_sdram_bankmachine7_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {
main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last,
main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first,
main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr,
main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we
};
assign {main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_first = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_last = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine7_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_sdram_bankmachine7_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
assign main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine7_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_sdram_bankmachine7_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine7_cmd_buffer_sink_ready = ((~main_sdram_bankmachine7_cmd_buffer_source_valid) | main_sdram_bankmachine7_cmd_buffer_source_ready);
always @(*) begin
main_sdram_bankmachine7_row_open <= 1'd0;
main_sdram_bankmachine7_row_close <= 1'd0;
main_sdram_bankmachine7_refresh_gnt <= 1'd0;
main_sdram_bankmachine7_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine7_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine7_cmd_payload_we <= 1'd0;
main_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine7_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine7_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine7_req_wdata_ready <= 1'd0;
main_sdram_bankmachine7_req_rdata_valid <= 1'd0;
builder_bankmachine7_next_state <= 3'd0;
main_sdram_bankmachine7_cmd_valid <= 1'd0;
builder_bankmachine7_next_state <= builder_bankmachine7_state;
case (builder_bankmachine7_state)
1'd1: begin
if ((main_sdram_bankmachine7_twtpcon_ready & main_sdram_bankmachine7_trascon_ready)) begin
main_sdram_bankmachine7_cmd_valid <= 1'd1;
if (main_sdram_bankmachine7_cmd_ready) begin
builder_bankmachine7_next_state <= 3'd5;
end
main_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine7_cmd_payload_we <= 1'd1;
main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine7_twtpcon_ready & main_sdram_bankmachine7_trascon_ready)) begin
builder_bankmachine7_next_state <= 3'd5;
end
main_sdram_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine7_trccon_ready) begin
main_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine7_row_open <= 1'd1;
main_sdram_bankmachine7_cmd_valid <= 1'd1;
main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine7_cmd_ready) begin
builder_bankmachine7_next_state <= 3'd6;
end
main_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine7_twtpcon_ready) begin
main_sdram_bankmachine7_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine7_row_close <= 1'd1;
main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine7_refresh_req)) begin
builder_bankmachine7_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine7_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine7_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine7_refresh_req) begin
builder_bankmachine7_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine7_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine7_row_opened) begin
if (main_sdram_bankmachine7_row_hit) begin
main_sdram_bankmachine7_cmd_valid <= 1'd1;
if (main_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine7_req_wdata_ready <= main_sdram_bankmachine7_cmd_ready;
main_sdram_bankmachine7_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine7_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine7_req_rdata_valid <= main_sdram_bankmachine7_cmd_ready;
main_sdram_bankmachine7_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine7_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine7_cmd_ready & main_sdram_bankmachine7_auto_precharge)) begin
builder_bankmachine7_next_state <= 2'd2;
end
end else begin
builder_bankmachine7_next_state <= 1'd1;
end
end else begin
builder_bankmachine7_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_trrdcon_valid = ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & ((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we)));
assign main_sdram_tfawcon_valid = ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & ((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we)));
assign main_sdram_ras_allowed = (main_sdram_trrdcon_ready & main_sdram_tfawcon_ready);
assign main_sdram_tccdcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_cmd_payload_is_write | main_sdram_choose_req_cmd_payload_is_read));
assign main_sdram_cas_allowed = main_sdram_tccdcon_ready;
assign main_sdram_twtrcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
assign main_sdram_read_available = ((((((((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_payload_is_read) | (main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_payload_is_read)) | (main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_payload_is_read)) | (main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_payload_is_read)) | (main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_payload_is_read)) | (main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_payload_is_read)) | (main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_payload_is_read)) | (main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_payload_is_read));
assign main_sdram_write_available = ((((((((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_payload_is_write) | (main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_payload_is_write)) | (main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_payload_is_write)) | (main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_payload_is_write)) | (main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_payload_is_write)) | (main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_payload_is_write)) | (main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_payload_is_write)) | (main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_payload_is_write));
assign main_sdram_max_time0 = (main_sdram_time0 == 1'd0);
assign main_sdram_max_time1 = (main_sdram_time1 == 1'd0);
assign main_sdram_bankmachine0_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine1_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine2_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine3_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine4_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine5_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine6_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine7_refresh_req = main_sdram_cmd_valid;
assign main_sdram_go_to_refresh = (((((((main_sdram_bankmachine0_refresh_gnt & main_sdram_bankmachine1_refresh_gnt) & main_sdram_bankmachine2_refresh_gnt) & main_sdram_bankmachine3_refresh_gnt) & main_sdram_bankmachine4_refresh_gnt) & main_sdram_bankmachine5_refresh_gnt) & main_sdram_bankmachine6_refresh_gnt) & main_sdram_bankmachine7_refresh_gnt);
assign main_sdram_interface_rdata = {
main_sdram_dfi_p3_rddata,
main_sdram_dfi_p2_rddata,
main_sdram_dfi_p1_rddata,
main_sdram_dfi_p0_rddata
};
assign {main_sdram_dfi_p3_wrdata, main_sdram_dfi_p2_wrdata, main_sdram_dfi_p1_wrdata, main_sdram_dfi_p0_wrdata} = main_sdram_interface_wdata;
assign {main_sdram_dfi_p3_wrdata_mask, main_sdram_dfi_p2_wrdata_mask, main_sdram_dfi_p1_wrdata_mask, main_sdram_dfi_p0_wrdata_mask} = (~main_sdram_interface_wdata_we);
always @(*) begin
main_sdram_choose_cmd_valids <= 8'd0;
main_sdram_choose_cmd_valids[0] <= (main_sdram_bankmachine0_cmd_valid & (((main_sdram_bankmachine0_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine0_cmd_payload_ras & (~main_sdram_bankmachine0_cmd_payload_cas)) & (~main_sdram_bankmachine0_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine0_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine0_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[1] <= (main_sdram_bankmachine1_cmd_valid & (((main_sdram_bankmachine1_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine1_cmd_payload_ras & (~main_sdram_bankmachine1_cmd_payload_cas)) & (~main_sdram_bankmachine1_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine1_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine1_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[2] <= (main_sdram_bankmachine2_cmd_valid & (((main_sdram_bankmachine2_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine2_cmd_payload_ras & (~main_sdram_bankmachine2_cmd_payload_cas)) & (~main_sdram_bankmachine2_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine2_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine2_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[3] <= (main_sdram_bankmachine3_cmd_valid & (((main_sdram_bankmachine3_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine3_cmd_payload_ras & (~main_sdram_bankmachine3_cmd_payload_cas)) & (~main_sdram_bankmachine3_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine3_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine3_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[4] <= (main_sdram_bankmachine4_cmd_valid & (((main_sdram_bankmachine4_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine4_cmd_payload_ras & (~main_sdram_bankmachine4_cmd_payload_cas)) & (~main_sdram_bankmachine4_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine4_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine4_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[5] <= (main_sdram_bankmachine5_cmd_valid & (((main_sdram_bankmachine5_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine5_cmd_payload_ras & (~main_sdram_bankmachine5_cmd_payload_cas)) & (~main_sdram_bankmachine5_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine5_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine5_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[6] <= (main_sdram_bankmachine6_cmd_valid & (((main_sdram_bankmachine6_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine6_cmd_payload_ras & (~main_sdram_bankmachine6_cmd_payload_cas)) & (~main_sdram_bankmachine6_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine6_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine6_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[7] <= (main_sdram_bankmachine7_cmd_valid & (((main_sdram_bankmachine7_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine7_cmd_payload_ras & (~main_sdram_bankmachine7_cmd_payload_cas)) & (~main_sdram_bankmachine7_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine7_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine7_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
end
assign main_sdram_choose_cmd_request = main_sdram_choose_cmd_valids;
assign main_sdram_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
assign main_sdram_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1;
assign main_sdram_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
assign main_sdram_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
assign main_sdram_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
assign main_sdram_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
always @(*) begin
main_sdram_choose_cmd_cmd_payload_cas <= 1'd0;
if (main_sdram_choose_cmd_cmd_valid) begin
main_sdram_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
end
end
always @(*) begin
main_sdram_choose_cmd_cmd_payload_ras <= 1'd0;
if (main_sdram_choose_cmd_cmd_valid) begin
main_sdram_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
end
end
always @(*) begin
main_sdram_choose_cmd_cmd_payload_we <= 1'd0;
if (main_sdram_choose_cmd_cmd_valid) begin
main_sdram_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
end
end
assign main_sdram_choose_cmd_ce = (main_sdram_choose_cmd_cmd_ready | (~main_sdram_choose_cmd_cmd_valid));
always @(*) begin
main_sdram_choose_req_valids <= 8'd0;
main_sdram_choose_req_valids[0] <= (main_sdram_bankmachine0_cmd_valid & (((main_sdram_bankmachine0_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine0_cmd_payload_ras & (~main_sdram_bankmachine0_cmd_payload_cas)) & (~main_sdram_bankmachine0_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine0_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine0_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[1] <= (main_sdram_bankmachine1_cmd_valid & (((main_sdram_bankmachine1_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine1_cmd_payload_ras & (~main_sdram_bankmachine1_cmd_payload_cas)) & (~main_sdram_bankmachine1_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine1_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine1_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[2] <= (main_sdram_bankmachine2_cmd_valid & (((main_sdram_bankmachine2_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine2_cmd_payload_ras & (~main_sdram_bankmachine2_cmd_payload_cas)) & (~main_sdram_bankmachine2_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine2_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine2_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[3] <= (main_sdram_bankmachine3_cmd_valid & (((main_sdram_bankmachine3_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine3_cmd_payload_ras & (~main_sdram_bankmachine3_cmd_payload_cas)) & (~main_sdram_bankmachine3_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine3_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine3_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[4] <= (main_sdram_bankmachine4_cmd_valid & (((main_sdram_bankmachine4_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine4_cmd_payload_ras & (~main_sdram_bankmachine4_cmd_payload_cas)) & (~main_sdram_bankmachine4_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine4_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine4_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[5] <= (main_sdram_bankmachine5_cmd_valid & (((main_sdram_bankmachine5_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine5_cmd_payload_ras & (~main_sdram_bankmachine5_cmd_payload_cas)) & (~main_sdram_bankmachine5_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine5_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine5_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[6] <= (main_sdram_bankmachine6_cmd_valid & (((main_sdram_bankmachine6_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine6_cmd_payload_ras & (~main_sdram_bankmachine6_cmd_payload_cas)) & (~main_sdram_bankmachine6_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine6_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine6_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[7] <= (main_sdram_bankmachine7_cmd_valid & (((main_sdram_bankmachine7_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine7_cmd_payload_ras & (~main_sdram_bankmachine7_cmd_payload_cas)) & (~main_sdram_bankmachine7_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine7_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine7_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
end
assign main_sdram_choose_req_request = main_sdram_choose_req_valids;
assign main_sdram_choose_req_cmd_valid = builder_rhs_array_muxed6;
assign main_sdram_choose_req_cmd_payload_a = builder_rhs_array_muxed7;
assign main_sdram_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
assign main_sdram_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
assign main_sdram_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
assign main_sdram_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
always @(*) begin
main_sdram_choose_req_cmd_payload_cas <= 1'd0;
if (main_sdram_choose_req_cmd_valid) begin
main_sdram_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
end
end
always @(*) begin
main_sdram_choose_req_cmd_payload_ras <= 1'd0;
if (main_sdram_choose_req_cmd_valid) begin
main_sdram_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
end
end
always @(*) begin
main_sdram_choose_req_cmd_payload_we <= 1'd0;
if (main_sdram_choose_req_cmd_valid) begin
main_sdram_choose_req_cmd_payload_we <= builder_t_array_muxed5;
end
end
always @(*) begin
main_sdram_bankmachine0_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 1'd0))) begin
main_sdram_bankmachine0_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 1'd0))) begin
main_sdram_bankmachine0_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine1_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 1'd1))) begin
main_sdram_bankmachine1_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 1'd1))) begin
main_sdram_bankmachine1_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine2_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 2'd2))) begin
main_sdram_bankmachine2_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 2'd2))) begin
main_sdram_bankmachine2_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine3_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 2'd3))) begin
main_sdram_bankmachine3_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 2'd3))) begin
main_sdram_bankmachine3_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine4_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd4))) begin
main_sdram_bankmachine4_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd4))) begin
main_sdram_bankmachine4_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine5_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd5))) begin
main_sdram_bankmachine5_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd5))) begin
main_sdram_bankmachine5_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine6_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd6))) begin
main_sdram_bankmachine6_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd6))) begin
main_sdram_bankmachine6_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine7_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd7))) begin
main_sdram_bankmachine7_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd7))) begin
main_sdram_bankmachine7_cmd_ready <= 1'd1;
end
end
assign main_sdram_choose_req_ce = (main_sdram_choose_req_cmd_ready | (~main_sdram_choose_req_cmd_valid));
assign main_sdram_dfi_p0_reset_n = 1'd1;
assign main_sdram_dfi_p0_cke = {1{main_sdram_steerer0}};
assign main_sdram_dfi_p0_odt = {1{main_sdram_steerer1}};
assign main_sdram_dfi_p1_reset_n = 1'd1;
assign main_sdram_dfi_p1_cke = {1{main_sdram_steerer2}};
assign main_sdram_dfi_p1_odt = {1{main_sdram_steerer3}};
assign main_sdram_dfi_p2_reset_n = 1'd1;
assign main_sdram_dfi_p2_cke = {1{main_sdram_steerer4}};
assign main_sdram_dfi_p2_odt = {1{main_sdram_steerer5}};
assign main_sdram_dfi_p3_reset_n = 1'd1;
assign main_sdram_dfi_p3_cke = {1{main_sdram_steerer6}};
assign main_sdram_dfi_p3_odt = {1{main_sdram_steerer7}};
assign main_sdram_tfawcon_count"b" = (((main_sdram_tfawcon_window[0] + main_sdram_tfawcon_window[1]) + main_sdram_tfawcon_window[2]) + main_sdram_tfawcon_window[3]);
always @(*) begin
main_sdram_choose_req_cmd_ready <= 1'd0;
main_sdram_steerer_sel0 <= 2'd0;
main_sdram_steerer_sel1 <= 2'd0;
main_sdram_steerer_sel2 <= 2'd0;
main_sdram_choose_cmd_want_activates <= 1'd0;
main_sdram_en0 <= 1'd0;
main_sdram_steerer_sel3 <= 2'd0;
builder_multiplexer_next_state <= 4'd0;
main_sdram_choose_cmd_cmd_ready <= 1'd0;
main_sdram_choose_req_want_reads <= 1'd0;
main_sdram_cmd_ready <= 1'd0;
main_sdram_choose_req_want_writes <= 1'd0;
main_sdram_en1 <= 1'd0;
builder_multiplexer_next_state <= builder_multiplexer_state;
case (builder_multiplexer_state)
1'd1: begin
main_sdram_en1 <= 1'd1;
main_sdram_choose_req_want_writes <= 1'd1;
if (1'd0) begin
main_sdram_choose_req_cmd_ready <= (main_sdram_cas_allowed & ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed));
end else begin
main_sdram_choose_cmd_want_activates <= main_sdram_ras_allowed;
main_sdram_choose_cmd_cmd_ready <= ((~((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we))) | main_sdram_ras_allowed);
main_sdram_choose_req_cmd_ready <= main_sdram_cas_allowed;
end
main_sdram_steerer_sel0 <= 1'd0;
main_sdram_steerer_sel1 <= 1'd0;
main_sdram_steerer_sel2 <= 1'd1;
main_sdram_steerer_sel3 <= 2'd2;
if (main_sdram_read_available) begin
if (((~main_sdram_write_available) | main_sdram_max_time1)) begin
builder_multiplexer_next_state <= 2'd3;
end
end
if (main_sdram_go_to_refresh) begin
builder_multiplexer_next_state <= 2'd2;
end
end
2'd2: begin
main_sdram_steerer_sel0 <= 2'd3;
main_sdram_cmd_ready <= 1'd1;
if (main_sdram_cmd_last) begin
builder_multiplexer_next_state <= 1'd0;
end
end
2'd3: begin
if (main_sdram_twtrcon_ready) begin
builder_multiplexer_next_state <= 1'd0;
end
end
3'd4: begin
builder_multiplexer_next_state <= 3'd5;
end
3'd5: begin
builder_multiplexer_next_state <= 3'd6;
end
3'd6: begin
builder_multiplexer_next_state <= 3'd7;
end
3'd7: begin
builder_multiplexer_next_state <= 4'd8;
end
4'd8: begin
builder_multiplexer_next_state <= 4'd9;
end
4'd9: begin
builder_multiplexer_next_state <= 4'd10;
end
4'd10: begin
builder_multiplexer_next_state <= 4'd11;
end
4'd11: begin
builder_multiplexer_next_state <= 1'd1;
end
default: begin
main_sdram_en0 <= 1'd1;
main_sdram_choose_req_want_reads <= 1'd1;
if (1'd0) begin
main_sdram_choose_req_cmd_ready <= (main_sdram_cas_allowed & ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed));
end else begin
main_sdram_choose_cmd_want_activates <= main_sdram_ras_allowed;
main_sdram_choose_cmd_cmd_ready <= ((~((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we))) | main_sdram_ras_allowed);
main_sdram_choose_req_cmd_ready <= main_sdram_cas_allowed;
end
main_sdram_steerer_sel0 <= 1'd0;
main_sdram_steerer_sel1 <= 1'd1;
main_sdram_steerer_sel2 <= 2'd2;
main_sdram_steerer_sel3 <= 1'd0;
if (main_sdram_write_available) begin
if (((~main_sdram_read_available) | main_sdram_max_time0)) begin
builder_multiplexer_next_state <= 3'd4;
end
end
if (main_sdram_go_to_refresh) begin
builder_multiplexer_next_state <= 2'd2;
end
end
endcase
end
assign builder_roundrobin0_request = {
(((main_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)
};
assign builder_roundrobin0_ce = ((~main_sdram_interface_bank0_valid) & (~main_sdram_interface_bank0_lock));
assign main_sdram_interface_bank0_addr = builder_rhs_array_muxed12;
assign main_sdram_interface_bank0_we = builder_rhs_array_muxed13;
assign main_sdram_interface_bank0_valid = builder_rhs_array_muxed14;
assign builder_roundrobin1_request = {
(((main_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)
};
assign builder_roundrobin1_ce = ((~main_sdram_interface_bank1_valid) & (~main_sdram_interface_bank1_lock));
assign main_sdram_interface_bank1_addr = builder_rhs_array_muxed15;
assign main_sdram_interface_bank1_we = builder_rhs_array_muxed16;
assign main_sdram_interface_bank1_valid = builder_rhs_array_muxed17;
assign builder_roundrobin2_request = {
(((main_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)
};
assign builder_roundrobin2_ce = ((~main_sdram_interface_bank2_valid) & (~main_sdram_interface_bank2_lock));
assign main_sdram_interface_bank2_addr = builder_rhs_array_muxed18;
assign main_sdram_interface_bank2_we = builder_rhs_array_muxed19;
assign main_sdram_interface_bank2_valid = builder_rhs_array_muxed20;
assign builder_roundrobin3_request = {
(((main_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)
};
assign builder_roundrobin3_ce = ((~main_sdram_interface_bank3_valid) & (~main_sdram_interface_bank3_lock));
assign main_sdram_interface_bank3_addr = builder_rhs_array_muxed21;
assign main_sdram_interface_bank3_we = builder_rhs_array_muxed22;
assign main_sdram_interface_bank3_valid = builder_rhs_array_muxed23;
assign builder_roundrobin4_request = {
(((main_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)
};
assign builder_roundrobin4_ce = ((~main_sdram_interface_bank4_valid) & (~main_sdram_interface_bank4_lock));
assign main_sdram_interface_bank4_addr = builder_rhs_array_muxed24;
assign main_sdram_interface_bank4_we = builder_rhs_array_muxed25;
assign main_sdram_interface_bank4_valid = builder_rhs_array_muxed26;
assign builder_roundrobin5_request = {
(((main_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)
};
assign builder_roundrobin5_ce = ((~main_sdram_interface_bank5_valid) & (~main_sdram_interface_bank5_lock));
assign main_sdram_interface_bank5_addr = builder_rhs_array_muxed27;
assign main_sdram_interface_bank5_we = builder_rhs_array_muxed28;
assign main_sdram_interface_bank5_valid = builder_rhs_array_muxed29;
assign builder_roundrobin6_request = {
(((main_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)
};
assign builder_roundrobin6_ce = ((~main_sdram_interface_bank6_valid) & (~main_sdram_interface_bank6_lock));
assign main_sdram_interface_bank6_addr = builder_rhs_array_muxed30;
assign main_sdram_interface_bank6_we = builder_rhs_array_muxed31;
assign main_sdram_interface_bank6_valid = builder_rhs_array_muxed32;
assign builder_roundrobin7_request = {
(((main_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_port_cmd_valid)
};
assign builder_roundrobin7_ce = ((~main_sdram_interface_bank7_valid) & (~main_sdram_interface_bank7_lock));
assign main_sdram_interface_bank7_addr = builder_rhs_array_muxed33;
assign main_sdram_interface_bank7_we = builder_rhs_array_muxed34;
assign main_sdram_interface_bank7_valid = builder_rhs_array_muxed35;
assign main_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_sdram_interface_bank7_ready));
assign main_port_wdata_ready = builder_new_master_wdata_ready2;
assign main_port_rdata_valid = builder_new_master_rdata_valid9;
always @(*) begin
main_sdram_interface_wdata <= 128'd0;
main_sdram_interface_wdata_we <= 16'd0;
case ({
builder_new_master_wdata_ready2
})
1'd1: begin
main_sdram_interface_wdata <= main_port_wdata_payload_data;
main_sdram_interface_wdata_we <= main_port_wdata_payload_we;
end
default: begin
main_sdram_interface_wdata <= 1'd0;
main_sdram_interface_wdata_we <= 1'd0;
end
endcase
end
assign main_port_rdata_payload_data = main_sdram_interface_rdata;
assign builder_roundrobin0_grant = 1'd0;
assign builder_roundrobin1_grant = 1'd0;
assign builder_roundrobin2_grant = 1'd0;
assign builder_roundrobin3_grant = 1'd0;
assign builder_roundrobin4_grant = 1'd0;
assign builder_roundrobin5_grant = 1'd0;
assign builder_roundrobin6_grant = 1'd0;
assign builder_roundrobin7_grant = 1'd0;
assign main_data_port_adr = main_interface0_wb_sdram_adr[10:2];
always @(*) begin
main_data_port_we <= 16'd0;
main_data_port_dat_w <= 128'd0;
if (main_write_from_slave) begin
main_data_port_dat_w <= main_dat_r;
main_data_port_we <= {16{1'd1}};
end else begin
main_data_port_dat_w <= {4{main_interface0_wb_sdram_dat_w}};
if ((((main_interface0_wb_sdram_cyc & main_interface0_wb_sdram_stb) & main_interface0_wb_sdram_we) & main_interface0_wb_sdram_ack)) begin
main_data_port_we <= {
({4{(main_interface0_wb_sdram_adr[1:0] == 1'd0)}} & main_interface0_wb_sdram_sel),
({4{(main_interface0_wb_sdram_adr[1:0] == 1'd1)}} & main_interface0_wb_sdram_sel),
({4{(main_interface0_wb_sdram_adr[1:0] == 2'd2)}} & main_interface0_wb_sdram_sel),
({4{(main_interface0_wb_sdram_adr[1:0] == 2'd3)}} & main_interface0_wb_sdram_sel)
};
end
end
end
assign main_dat_w = main_data_port_dat_r;
assign main_sel = 16'd65535;
always @(*) begin
main_interface0_wb_sdram_dat_r <= 32'd0;
case (main_adr_offset_r)
1'd0: begin
main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[127:96];
end
1'd1: begin
main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[95:64];
end
2'd2: begin
main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[63:32];
end
default: begin
main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[31:0];
end
endcase
end
assign {main_tag_do_dirty, main_tag_do_tag} = main_tag_port_dat_r;
assign main_tag_port_dat_w = {main_tag_di_dirty, main_tag_di_tag};
assign main_tag_port_adr = main_interface0_wb_sdram_adr[10:2];
assign main_tag_di_tag = main_interface0_wb_sdram_adr[29:11];
assign main_adr = {main_tag_do_tag, main_interface0_wb_sdram_adr[10:2]};
always @(*) begin
main_tag_di_dirty <= 1'd0;
main_interface0_wb_sdram_ack <= 1'd0;
main_word_clr <= 1'd0;
main_word_inc <= 1'd0;
main_write_from_slave <= 1'd0;
main_cyc <= 1'd0;
main_stb <= 1'd0;
main_tag_port_we <= 1'd0;
main_we <= 1'd0;
builder_fullmemorywe_next_state <= 2'd0;
builder_fullmemorywe_next_state <= builder_fullmemorywe_state;
case (builder_fullmemorywe_state)
1'd1: begin
main_word_clr <= 1'd1;
if ((main_tag_do_tag == main_interface0_wb_sdram_adr[29:11])) begin
main_interface0_wb_sdram_ack <= 1'd1;
if (main_interface0_wb_sdram_we) begin
main_tag_di_dirty <= 1'd1;
main_tag_port_we <= 1'd1;
end
builder_fullmemorywe_next_state <= 1'd0;
end else begin
if (main_tag_do_dirty) begin
builder_fullmemorywe_next_state <= 2'd2;
end else begin
main_tag_port_we <= 1'd1;
main_word_clr <= 1'd1;
builder_fullmemorywe_next_state <= 2'd3;
end
end
end
2'd2: begin
main_stb <= 1'd1;
main_cyc <= 1'd1;
main_we <= 1'd1;
if (main_ack) begin
main_word_inc <= 1'd1;
if (1'd1) begin
main_tag_port_we <= 1'd1;
main_word_clr <= 1'd1;
builder_fullmemorywe_next_state <= 2'd3;
end
end
end
2'd3: begin
main_stb <= 1'd1;
main_cyc <= 1'd1;
main_we <= 1'd0;
if (main_ack) begin
main_write_from_slave <= 1'd1;
main_word_inc <= 1'd1;
if (1'd1) begin
builder_fullmemorywe_next_state <= 1'd1;
end else begin
builder_fullmemorywe_next_state <= 2'd3;
end
end
end
default: begin
if ((main_interface0_wb_sdram_cyc & main_interface0_wb_sdram_stb)) begin
builder_fullmemorywe_next_state <= 1'd1;
end
end
endcase
end
assign main_wdata_converter_sink_valid = ((main_cyc & main_stb) & main_we);
assign main_wdata_converter_sink_payload_data = main_dat_w;
assign main_wdata_converter_sink_payload_we = main_sel;
assign main_port_wdata_valid = main_wdata_converter_source_valid;
assign main_wdata_converter_source_ready = main_port_wdata_ready;
assign main_port_wdata_first = main_wdata_converter_source_first;
assign main_port_wdata_last = main_wdata_converter_source_last;
assign main_port_wdata_payload_data = main_wdata_converter_source_payload_data;
assign main_port_wdata_payload_we = main_wdata_converter_source_payload_we;
assign main_rdata_converter_sink_valid = main_port_rdata_valid;
assign main_port_rdata_ready = main_rdata_converter_sink_ready;
assign main_rdata_converter_sink_first = main_port_rdata_first;
assign main_rdata_converter_sink_last = main_port_rdata_last;
assign main_rdata_converter_sink_payload_data = main_port_rdata_payload_data;
assign main_rdata_converter_source_ready = 1'd1;
assign main_dat_r = main_rdata_converter_source_payload_data;
assign main_wdata_converter_converter_sink_valid = main_wdata_converter_sink_valid;
assign main_wdata_converter_converter_sink_first = main_wdata_converter_sink_first;
assign main_wdata_converter_converter_sink_last = main_wdata_converter_sink_last;
assign main_wdata_converter_sink_ready = main_wdata_converter_converter_sink_ready;
assign main_wdata_converter_converter_sink_payload_data = {
main_wdata_converter_sink_payload_we, main_wdata_converter_sink_payload_data
};
assign main_wdata_converter_source_valid = main_wdata_converter_source_source_valid;
assign main_wdata_converter_source_first = main_wdata_converter_source_source_first;
assign main_wdata_converter_source_last = main_wdata_converter_source_source_last;
assign main_wdata_converter_source_source_ready = main_wdata_converter_source_ready;
assign {main_wdata_converter_source_payload_we, main_wdata_converter_source_payload_data} = main_wdata_converter_source_source_payload_data;
assign main_wdata_converter_source_source_valid = main_wdata_converter_converter_source_valid;
assign main_wdata_converter_converter_source_ready = main_wdata_converter_source_source_ready;
assign main_wdata_converter_source_source_first = main_wdata_converter_converter_source_first;
assign main_wdata_converter_source_source_last = main_wdata_converter_converter_source_last;
assign main_wdata_converter_source_source_payload_data = main_wdata_converter_converter_source_payload_data;
assign main_wdata_converter_converter_source_valid = main_wdata_converter_converter_sink_valid;
assign main_wdata_converter_converter_sink_ready = main_wdata_converter_converter_source_ready;
assign main_wdata_converter_converter_source_first = main_wdata_converter_converter_sink_first;
assign main_wdata_converter_converter_source_last = main_wdata_converter_converter_sink_last;
assign main_wdata_converter_converter_source_payload_data = main_wdata_converter_converter_sink_payload_data;
assign main_wdata_converter_converter_source_payload_valid_token_count = 1'd1;
assign main_rdata_converter_converter_sink_valid = main_rdata_converter_sink_valid;
assign main_rdata_converter_converter_sink_first = main_rdata_converter_sink_first;
assign main_rdata_converter_converter_sink_last = main_rdata_converter_sink_last;
assign main_rdata_converter_sink_ready = main_rdata_converter_converter_sink_ready;
assign main_rdata_converter_converter_sink_payload_data = {
main_rdata_converter_sink_payload_data
};
assign main_rdata_converter_source_valid = main_rdata_converter_source_source_valid;
assign main_rdata_converter_source_first = main_rdata_converter_source_source_first;
assign main_rdata_converter_source_last = main_rdata_converter_source_source_last;
assign main_rdata_converter_source_source_ready = main_rdata_converter_source_ready;
assign {main_rdata_converter_source_payload_data} = main_rdata_converter_source_source_payload_data;
assign main_rdata_converter_source_source_valid = main_rdata_converter_converter_source_valid;
assign main_rdata_converter_converter_source_ready = main_rdata_converter_source_source_ready;
assign main_rdata_converter_source_source_first = main_rdata_converter_converter_source_first;
assign main_rdata_converter_source_source_last = main_rdata_converter_converter_source_last;
assign main_rdata_converter_source_source_payload_data = main_rdata_converter_converter_source_payload_data;
assign main_rdata_converter_converter_source_valid = main_rdata_converter_converter_sink_valid;
assign main_rdata_converter_converter_sink_ready = main_rdata_converter_converter_source_ready;
assign main_rdata_converter_converter_source_first = main_rdata_converter_converter_sink_first;
assign main_rdata_converter_converter_source_last = main_rdata_converter_converter_sink_last;
assign main_rdata_converter_converter_source_payload_data = main_rdata_converter_converter_sink_payload_data;
assign main_rdata_converter_converter_source_payload_valid_token_count = 1'd1;
always @(*) begin
builder_litedramwishbone2native_next_state <= 2'd0;
main_ack <= 1'd0;
main_port_cmd_payload_we <= 1'd0;
main_port_cmd_payload_addr <= 24'd0;
main_count_next_value <= 1'd0;
main_count_next_value_ce <= 1'd0;
main_port_cmd_valid <= 1'd0;
builder_litedramwishbone2native_next_state <= builder_litedramwishbone2native_state;
case (builder_litedramwishbone2native_state)
1'd1: begin
if (main_wdata_converter_sink_ready) begin
main_ack <= 1'd1;
builder_litedramwishbone2native_next_state <= 1'd0;
end
end
2'd2: begin
if (main_rdata_converter_source_valid) begin
main_ack <= 1'd1;
builder_litedramwishbone2native_next_state <= 1'd0;
end
end
default: begin
main_port_cmd_valid <= (main_cyc & main_stb);
main_port_cmd_payload_we <= main_we;
main_port_cmd_payload_addr <= (((main_adr * 1'd1) + main_count) - 1'd0);
if ((main_port_cmd_valid & main_port_cmd_ready)) begin
main_count_next_value <= (main_count + 1'd1);
main_count_next_value_ce <= 1'd1;
if ((main_count == 1'd0)) begin
main_count_next_value <= 1'd0;
main_count_next_value_ce <= 1'd1;
if (main_we) begin
builder_litedramwishbone2native_next_state <= 1'd1;
end else begin
builder_litedramwishbone2native_next_state <= 2'd2;
end
end
end
end
endcase
end
assign main_interface0_wb_sdram_adr = builder_rhs_array_muxed36;
assign main_interface0_wb_sdram_dat_w = builder_rhs_array_muxed37;
assign main_interface0_wb_sdram_sel = builder_rhs_array_muxed38;
assign main_interface0_wb_sdram_cyc = builder_rhs_array_muxed39;
assign main_interface0_wb_sdram_stb = builder_rhs_array_muxed40;
assign main_interface0_wb_sdram_we = builder_rhs_array_muxed41;
assign main_interface0_wb_sdram_cti = builder_rhs_array_muxed42;
assign main_interface0_wb_sdram_bte = builder_rhs_array_muxed43;
assign main_interface1_wb_sdram_dat_r = main_interface0_wb_sdram_dat_r;
assign main_interface1_wb_sdram_ack = (main_interface0_wb_sdram_ack & (builder_wb_sdram_con_grant == 1'd0));
assign main_interface1_wb_sdram_err = (main_interface0_wb_sdram_err & (builder_wb_sdram_con_grant == 1'd0));
assign builder_wb_sdram_con_request = {main_interface1_wb_sdram_cyc};
assign builder_wb_sdram_con_grant = 1'd0;
assign builder_minsoc_shared_adr = builder_rhs_array_muxed44;
assign builder_minsoc_shared_dat_w = builder_rhs_array_muxed45;
assign builder_minsoc_shared_sel = builder_rhs_array_muxed46;
assign builder_minsoc_shared_cyc = builder_rhs_array_muxed47;
assign builder_minsoc_shared_stb = builder_rhs_array_muxed48;
assign builder_minsoc_shared_we = builder_rhs_array_muxed49;
assign builder_minsoc_shared_cti = builder_rhs_array_muxed50;
assign builder_minsoc_shared_bte = builder_rhs_array_muxed51;
assign main_minsoc_interface0_soc_bus_dat_r = builder_minsoc_shared_dat_r;
assign main_minsoc_interface1_soc_bus_dat_r = builder_minsoc_shared_dat_r;
assign main_minsoc_interface0_soc_bus_ack = (builder_minsoc_shared_ack & (builder_minsoc_grant == 1'd0));
assign main_minsoc_interface1_soc_bus_ack = (builder_minsoc_shared_ack & (builder_minsoc_grant == 1'd1));
assign main_minsoc_interface0_soc_bus_err = (builder_minsoc_shared_err & (builder_minsoc_grant == 1'd0));
assign main_minsoc_interface1_soc_bus_err = (builder_minsoc_shared_err & (builder_minsoc_grant == 1'd1));
assign builder_minsoc_request = {
main_minsoc_interface1_soc_bus_cyc, main_minsoc_interface0_soc_bus_cyc
};
always @(*) begin
builder_minsoc_slave_sel <= 4'd0;
builder_minsoc_slave_sel[0] <= (builder_minsoc_shared_adr[28:13] == 1'd0);
builder_minsoc_slave_sel[1] <= (builder_minsoc_shared_adr[28:10] == 13'd4096);
builder_minsoc_slave_sel[2] <= (builder_minsoc_shared_adr[28:14] == 10'd512);
builder_minsoc_slave_sel[3] <= (builder_minsoc_shared_adr[28:26] == 3'd4);
end
assign main_minsoc_rom_bus_adr = builder_minsoc_shared_adr;
assign main_minsoc_rom_bus_dat_w = builder_minsoc_shared_dat_w;
assign main_minsoc_rom_bus_sel = builder_minsoc_shared_sel;
assign main_minsoc_rom_bus_stb = builder_minsoc_shared_stb;
assign main_minsoc_rom_bus_we = builder_minsoc_shared_we;
assign main_minsoc_rom_bus_cti = builder_minsoc_shared_cti;
assign main_minsoc_rom_bus_bte = builder_minsoc_shared_bte;
assign main_minsoc_sram_bus_adr = builder_minsoc_shared_adr;
assign main_minsoc_sram_bus_dat_w = builder_minsoc_shared_dat_w;
assign main_minsoc_sram_bus_sel = builder_minsoc_shared_sel;
assign main_minsoc_sram_bus_stb = builder_minsoc_shared_stb;
assign main_minsoc_sram_bus_we = builder_minsoc_shared_we;
assign main_minsoc_sram_bus_cti = builder_minsoc_shared_cti;
assign main_minsoc_sram_bus_bte = builder_minsoc_shared_bte;
assign main_minsoc_bus_wishbone_adr = builder_minsoc_shared_adr;
assign main_minsoc_bus_wishbone_dat_w = builder_minsoc_shared_dat_w;
assign main_minsoc_bus_wishbone_sel = builder_minsoc_shared_sel;
assign main_minsoc_bus_wishbone_stb = builder_minsoc_shared_stb;
assign main_minsoc_bus_wishbone_we = builder_minsoc_shared_we;
assign main_minsoc_bus_wishbone_cti = builder_minsoc_shared_cti;
assign main_minsoc_bus_wishbone_bte = builder_minsoc_shared_bte;
assign main_interface1_wb_sdram_adr = builder_minsoc_shared_adr;
assign main_interface1_wb_sdram_dat_w = builder_minsoc_shared_dat_w;
assign main_interface1_wb_sdram_sel = builder_minsoc_shared_sel;
assign main_interface1_wb_sdram_stb = builder_minsoc_shared_stb;
assign main_interface1_wb_sdram_we = builder_minsoc_shared_we;
assign main_interface1_wb_sdram_cti = builder_minsoc_shared_cti;
assign main_interface1_wb_sdram_bte = builder_minsoc_shared_bte;
assign main_minsoc_rom_bus_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[0]);
assign main_minsoc_sram_bus_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[1]);
assign main_minsoc_bus_wishbone_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[2]);
assign main_interface1_wb_sdram_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[3]);
assign builder_minsoc_shared_err = (((main_minsoc_rom_bus_err | main_minsoc_sram_bus_err) | main_minsoc_bus_wishbone_err) | main_interface1_wb_sdram_err);
assign builder_minsoc_wait = ((builder_minsoc_shared_stb & builder_minsoc_shared_cyc) & (~builder_minsoc_shared_ack));
always @(*) begin
builder_minsoc_shared_ack <= 1'd0;
builder_minsoc_error <= 1'd0;
builder_minsoc_shared_dat_r <= 32'd0;
builder_minsoc_shared_ack <= (((main_minsoc_rom_bus_ack | main_minsoc_sram_bus_ack) | main_minsoc_bus_wishbone_ack) | main_interface1_wb_sdram_ack);
builder_minsoc_shared_dat_r <= (((({32{builder_minsoc_slave_sel_r[0]}} & main_minsoc_rom_bus_dat_r) | ({32{builder_minsoc_slave_sel_r[1]}} & main_minsoc_sram_bus_dat_r)) | ({32{builder_minsoc_slave_sel_r[2]}} & main_minsoc_bus_wishbone_dat_r)) | ({32{builder_minsoc_slave_sel_r[3]}} & main_interface1_wb_sdram_dat_r));
if (builder_minsoc_done) begin
builder_minsoc_shared_dat_r <= 32'd4294967295;
builder_minsoc_shared_ack <= 1'd1;
builder_minsoc_error <= 1'd1;
end
end
assign builder_minsoc_done = (builder_minsoc_count == 1'd0);
assign builder_minsoc_csrbank0_sel = (builder_minsoc_interface0_bank_bus_adr[13:9] == 1'd0);
assign builder_minsoc_csrbank0_reset0_r = builder_minsoc_interface0_bank_bus_dat_w[0];
assign builder_minsoc_csrbank0_reset0_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd0));
assign builder_minsoc_csrbank0_reset0_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd0));
assign builder_minsoc_csrbank0_scratch3_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_scratch3_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd1));
assign builder_minsoc_csrbank0_scratch3_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd1));
assign builder_minsoc_csrbank0_scratch2_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_scratch2_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd2));
assign builder_minsoc_csrbank0_scratch2_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd2));
assign builder_minsoc_csrbank0_scratch1_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_scratch1_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd3));
assign builder_minsoc_csrbank0_scratch1_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd3));
assign builder_minsoc_csrbank0_scratch0_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_scratch0_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd4));
assign builder_minsoc_csrbank0_scratch0_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd4));
assign builder_minsoc_csrbank0_bus_errors3_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_bus_errors3_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd5));
assign builder_minsoc_csrbank0_bus_errors3_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd5));
assign builder_minsoc_csrbank0_bus_errors2_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_bus_errors2_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd6));
assign builder_minsoc_csrbank0_bus_errors2_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd6));
assign builder_minsoc_csrbank0_bus_errors1_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_bus_errors1_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd7));
assign builder_minsoc_csrbank0_bus_errors1_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd7));
assign builder_minsoc_csrbank0_bus_errors0_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_bus_errors0_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 4'd8));
assign builder_minsoc_csrbank0_bus_errors0_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 4'd8));
assign builder_minsoc_csrbank0_reset0_w = main_minsoc_ctrl_reset_storage;
assign builder_minsoc_csrbank0_scratch3_w = main_minsoc_ctrl_scratch_storage[31:24];
assign builder_minsoc_csrbank0_scratch2_w = main_minsoc_ctrl_scratch_storage[23:16];
assign builder_minsoc_csrbank0_scratch1_w = main_minsoc_ctrl_scratch_storage[15:8];
assign builder_minsoc_csrbank0_scratch0_w = main_minsoc_ctrl_scratch_storage[7:0];
assign builder_minsoc_csrbank0_bus_errors3_w = main_minsoc_ctrl_bus_errors_status[31:24];
assign builder_minsoc_csrbank0_bus_errors2_w = main_minsoc_ctrl_bus_errors_status[23:16];
assign builder_minsoc_csrbank0_bus_errors1_w = main_minsoc_ctrl_bus_errors_status[15:8];
assign builder_minsoc_csrbank0_bus_errors0_w = main_minsoc_ctrl_bus_errors_status[7:0];
assign main_minsoc_ctrl_bus_errors_we = builder_minsoc_csrbank0_bus_errors0_we;
assign builder_minsoc_csrbank1_sel = (builder_minsoc_interface1_bank_bus_adr[13:9] == 3'd5);
assign builder_minsoc_csrbank1_half_sys8x_taps0_r = builder_minsoc_interface1_bank_bus_dat_w[4:0];
assign builder_minsoc_csrbank1_half_sys8x_taps0_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd0));
assign builder_minsoc_csrbank1_half_sys8x_taps0_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd0));
assign main_a7ddrphy_cdly_rst_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_cdly_rst_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd1));
assign main_a7ddrphy_cdly_rst_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd1));
assign main_a7ddrphy_cdly_inc_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_cdly_inc_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd2));
assign main_a7ddrphy_cdly_inc_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd2));
assign builder_minsoc_csrbank1_dly_sel0_r = builder_minsoc_interface1_bank_bus_dat_w[1:0];
assign builder_minsoc_csrbank1_dly_sel0_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd3));
assign builder_minsoc_csrbank1_dly_sel0_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd3));
assign main_a7ddrphy_rdly_dq_rst_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_rdly_dq_rst_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd4));
assign main_a7ddrphy_rdly_dq_rst_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd4));
assign main_a7ddrphy_rdly_dq_inc_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_rdly_dq_inc_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd5));
assign main_a7ddrphy_rdly_dq_inc_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd5));
assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_rdly_dq_bitslip_rst_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd6));
assign main_a7ddrphy_rdly_dq_bitslip_rst_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd6));
assign main_a7ddrphy_rdly_dq_bitslip_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_rdly_dq_bitslip_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd7));
assign main_a7ddrphy_rdly_dq_bitslip_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd7));
assign builder_minsoc_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
assign builder_minsoc_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
assign builder_minsoc_csrbank2_sel = (builder_minsoc_interface2_bank_bus_adr[13:9] == 4'd8);
assign builder_minsoc_csrbank2_dfii_control0_r = builder_minsoc_interface2_bank_bus_dat_w[3:0];
assign builder_minsoc_csrbank2_dfii_control0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd0));
assign builder_minsoc_csrbank2_dfii_control0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd0));
assign builder_minsoc_csrbank2_dfii_pi0_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi0_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd1));
assign builder_minsoc_csrbank2_dfii_pi0_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd1));
assign main_sdram_phaseinjector0_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0];
assign main_sdram_phaseinjector0_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd2));
assign main_sdram_phaseinjector0_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd2));
assign builder_minsoc_csrbank2_dfii_pi0_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi0_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd3));
assign builder_minsoc_csrbank2_dfii_pi0_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd3));
assign builder_minsoc_csrbank2_dfii_pi0_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd4));
assign builder_minsoc_csrbank2_dfii_pi0_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd4));
assign builder_minsoc_csrbank2_dfii_pi0_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0];
assign builder_minsoc_csrbank2_dfii_pi0_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd5));
assign builder_minsoc_csrbank2_dfii_pi0_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd5));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd6));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd6));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd7));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd7));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd8));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd8));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd9));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd9));
assign builder_minsoc_csrbank2_dfii_pi0_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd10));
assign builder_minsoc_csrbank2_dfii_pi0_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd10));
assign builder_minsoc_csrbank2_dfii_pi0_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd11));
assign builder_minsoc_csrbank2_dfii_pi0_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd11));
assign builder_minsoc_csrbank2_dfii_pi0_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd12));
assign builder_minsoc_csrbank2_dfii_pi0_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd12));
assign builder_minsoc_csrbank2_dfii_pi0_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd13));
assign builder_minsoc_csrbank2_dfii_pi0_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd13));
assign builder_minsoc_csrbank2_dfii_pi1_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi1_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd14));
assign builder_minsoc_csrbank2_dfii_pi1_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd14));
assign main_sdram_phaseinjector1_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0];
assign main_sdram_phaseinjector1_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd15));
assign main_sdram_phaseinjector1_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd15));
assign builder_minsoc_csrbank2_dfii_pi1_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi1_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd16));
assign builder_minsoc_csrbank2_dfii_pi1_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd16));
assign builder_minsoc_csrbank2_dfii_pi1_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd17));
assign builder_minsoc_csrbank2_dfii_pi1_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd17));
assign builder_minsoc_csrbank2_dfii_pi1_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0];
assign builder_minsoc_csrbank2_dfii_pi1_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd18));
assign builder_minsoc_csrbank2_dfii_pi1_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd18));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd19));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd19));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd20));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd20));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd21));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd21));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd22));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd22));
assign builder_minsoc_csrbank2_dfii_pi1_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd23));
assign builder_minsoc_csrbank2_dfii_pi1_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd23));
assign builder_minsoc_csrbank2_dfii_pi1_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd24));
assign builder_minsoc_csrbank2_dfii_pi1_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd24));
assign builder_minsoc_csrbank2_dfii_pi1_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd25));
assign builder_minsoc_csrbank2_dfii_pi1_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd25));
assign builder_minsoc_csrbank2_dfii_pi1_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd26));
assign builder_minsoc_csrbank2_dfii_pi1_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd26));
assign builder_minsoc_csrbank2_dfii_pi2_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi2_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd27));
assign builder_minsoc_csrbank2_dfii_pi2_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd27));
assign main_sdram_phaseinjector2_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0];
assign main_sdram_phaseinjector2_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd28));
assign main_sdram_phaseinjector2_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd28));
assign builder_minsoc_csrbank2_dfii_pi2_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi2_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd29));
assign builder_minsoc_csrbank2_dfii_pi2_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd29));
assign builder_minsoc_csrbank2_dfii_pi2_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd30));
assign builder_minsoc_csrbank2_dfii_pi2_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd30));
assign builder_minsoc_csrbank2_dfii_pi2_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0];
assign builder_minsoc_csrbank2_dfii_pi2_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd31));
assign builder_minsoc_csrbank2_dfii_pi2_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd31));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd32));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd32));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd33));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd33));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd34));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd34));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd35));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd35));
assign builder_minsoc_csrbank2_dfii_pi2_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd36));
assign builder_minsoc_csrbank2_dfii_pi2_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd36));
assign builder_minsoc_csrbank2_dfii_pi2_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd37));
assign builder_minsoc_csrbank2_dfii_pi2_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd37));
assign builder_minsoc_csrbank2_dfii_pi2_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd38));
assign builder_minsoc_csrbank2_dfii_pi2_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd38));
assign builder_minsoc_csrbank2_dfii_pi2_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd39));
assign builder_minsoc_csrbank2_dfii_pi2_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd39));
assign builder_minsoc_csrbank2_dfii_pi3_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi3_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd40));
assign builder_minsoc_csrbank2_dfii_pi3_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd40));
assign main_sdram_phaseinjector3_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0];
assign main_sdram_phaseinjector3_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd41));
assign main_sdram_phaseinjector3_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd41));
assign builder_minsoc_csrbank2_dfii_pi3_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi3_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd42));
assign builder_minsoc_csrbank2_dfii_pi3_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd42));
assign builder_minsoc_csrbank2_dfii_pi3_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd43));
assign builder_minsoc_csrbank2_dfii_pi3_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd43));
assign builder_minsoc_csrbank2_dfii_pi3_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0];
assign builder_minsoc_csrbank2_dfii_pi3_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd44));
assign builder_minsoc_csrbank2_dfii_pi3_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd44));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd45));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd45));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd46));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd46));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd47));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd47));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd48));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd48));
assign builder_minsoc_csrbank2_dfii_pi3_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd49));
assign builder_minsoc_csrbank2_dfii_pi3_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd49));
assign builder_minsoc_csrbank2_dfii_pi3_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd50));
assign builder_minsoc_csrbank2_dfii_pi3_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd50));
assign builder_minsoc_csrbank2_dfii_pi3_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd51));
assign builder_minsoc_csrbank2_dfii_pi3_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd51));
assign builder_minsoc_csrbank2_dfii_pi3_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd52));
assign builder_minsoc_csrbank2_dfii_pi3_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd52));
assign builder_minsoc_csrbank2_dfii_control0_w = main_sdram_storage[3:0];
assign builder_minsoc_csrbank2_dfii_pi0_command0_w = main_sdram_phaseinjector0_command_storage[5:0];
assign builder_minsoc_csrbank2_dfii_pi0_address1_w = main_sdram_phaseinjector0_address_storage[13:8];
assign builder_minsoc_csrbank2_dfii_pi0_address0_w = main_sdram_phaseinjector0_address_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_baddress0_w = main_sdram_phaseinjector0_baddress_storage[2:0];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_w = main_sdram_phaseinjector0_wrdata_storage[31:24];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_w = main_sdram_phaseinjector0_wrdata_storage[23:16];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_w = main_sdram_phaseinjector0_wrdata_storage[15:8];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_w = main_sdram_phaseinjector0_wrdata_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_rddata3_w = main_sdram_phaseinjector0_status[31:24];
assign builder_minsoc_csrbank2_dfii_pi0_rddata2_w = main_sdram_phaseinjector0_status[23:16];
assign builder_minsoc_csrbank2_dfii_pi0_rddata1_w = main_sdram_phaseinjector0_status[15:8];
assign builder_minsoc_csrbank2_dfii_pi0_rddata0_w = main_sdram_phaseinjector0_status[7:0];
assign main_sdram_phaseinjector0_we = builder_minsoc_csrbank2_dfii_pi0_rddata0_we;
assign builder_minsoc_csrbank2_dfii_pi1_command0_w = main_sdram_phaseinjector1_command_storage[5:0];
assign builder_minsoc_csrbank2_dfii_pi1_address1_w = main_sdram_phaseinjector1_address_storage[13:8];
assign builder_minsoc_csrbank2_dfii_pi1_address0_w = main_sdram_phaseinjector1_address_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_baddress0_w = main_sdram_phaseinjector1_baddress_storage[2:0];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_w = main_sdram_phaseinjector1_wrdata_storage[31:24];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_w = main_sdram_phaseinjector1_wrdata_storage[23:16];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_w = main_sdram_phaseinjector1_wrdata_storage[15:8];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_w = main_sdram_phaseinjector1_wrdata_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_rddata3_w = main_sdram_phaseinjector1_status[31:24];
assign builder_minsoc_csrbank2_dfii_pi1_rddata2_w = main_sdram_phaseinjector1_status[23:16];
assign builder_minsoc_csrbank2_dfii_pi1_rddata1_w = main_sdram_phaseinjector1_status[15:8];
assign builder_minsoc_csrbank2_dfii_pi1_rddata0_w = main_sdram_phaseinjector1_status[7:0];
assign main_sdram_phaseinjector1_we = builder_minsoc_csrbank2_dfii_pi1_rddata0_we;
assign builder_minsoc_csrbank2_dfii_pi2_command0_w = main_sdram_phaseinjector2_command_storage[5:0];
assign builder_minsoc_csrbank2_dfii_pi2_address1_w = main_sdram_phaseinjector2_address_storage[13:8];
assign builder_minsoc_csrbank2_dfii_pi2_address0_w = main_sdram_phaseinjector2_address_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_baddress0_w = main_sdram_phaseinjector2_baddress_storage[2:0];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_w = main_sdram_phaseinjector2_wrdata_storage[31:24];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_w = main_sdram_phaseinjector2_wrdata_storage[23:16];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_w = main_sdram_phaseinjector2_wrdata_storage[15:8];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_w = main_sdram_phaseinjector2_wrdata_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_rddata3_w = main_sdram_phaseinjector2_status[31:24];
assign builder_minsoc_csrbank2_dfii_pi2_rddata2_w = main_sdram_phaseinjector2_status[23:16];
assign builder_minsoc_csrbank2_dfii_pi2_rddata1_w = main_sdram_phaseinjector2_status[15:8];
assign builder_minsoc_csrbank2_dfii_pi2_rddata0_w = main_sdram_phaseinjector2_status[7:0];
assign main_sdram_phaseinjector2_we = builder_minsoc_csrbank2_dfii_pi2_rddata0_we;
assign builder_minsoc_csrbank2_dfii_pi3_command0_w = main_sdram_phaseinjector3_command_storage[5:0];
assign builder_minsoc_csrbank2_dfii_pi3_address1_w = main_sdram_phaseinjector3_address_storage[13:8];
assign builder_minsoc_csrbank2_dfii_pi3_address0_w = main_sdram_phaseinjector3_address_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_baddress0_w = main_sdram_phaseinjector3_baddress_storage[2:0];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_w = main_sdram_phaseinjector3_wrdata_storage[31:24];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_w = main_sdram_phaseinjector3_wrdata_storage[23:16];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_w = main_sdram_phaseinjector3_wrdata_storage[15:8];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_w = main_sdram_phaseinjector3_wrdata_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_rddata3_w = main_sdram_phaseinjector3_status[31:24];
assign builder_minsoc_csrbank2_dfii_pi3_rddata2_w = main_sdram_phaseinjector3_status[23:16];
assign builder_minsoc_csrbank2_dfii_pi3_rddata1_w = main_sdram_phaseinjector3_status[15:8];
assign builder_minsoc_csrbank2_dfii_pi3_rddata0_w = main_sdram_phaseinjector3_status[7:0];
assign main_sdram_phaseinjector3_we = builder_minsoc_csrbank2_dfii_pi3_rddata0_we;
assign builder_minsoc_csrbank3_sel = (builder_minsoc_interface3_bank_bus_adr[13:9] == 3'd4);
assign builder_minsoc_csrbank3_load3_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_load3_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd0));
assign builder_minsoc_csrbank3_load3_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd0));
assign builder_minsoc_csrbank3_load2_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_load2_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd1));
assign builder_minsoc_csrbank3_load2_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd1));
assign builder_minsoc_csrbank3_load1_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_load1_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd2));
assign builder_minsoc_csrbank3_load1_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd2));
assign builder_minsoc_csrbank3_load0_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_load0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd3));
assign builder_minsoc_csrbank3_load0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd3));
assign builder_minsoc_csrbank3_reload3_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_reload3_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd4));
assign builder_minsoc_csrbank3_reload3_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd4));
assign builder_minsoc_csrbank3_reload2_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_reload2_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd5));
assign builder_minsoc_csrbank3_reload2_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd5));
assign builder_minsoc_csrbank3_reload1_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_reload1_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd6));
assign builder_minsoc_csrbank3_reload1_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd6));
assign builder_minsoc_csrbank3_reload0_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_reload0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd7));
assign builder_minsoc_csrbank3_reload0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd7));
assign builder_minsoc_csrbank3_en0_r = builder_minsoc_interface3_bank_bus_dat_w[0];
assign builder_minsoc_csrbank3_en0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd8));
assign builder_minsoc_csrbank3_en0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd8));
assign builder_minsoc_csrbank3_update_value0_r = builder_minsoc_interface3_bank_bus_dat_w[0];
assign builder_minsoc_csrbank3_update_value0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd9));
assign builder_minsoc_csrbank3_update_value0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd9));
assign builder_minsoc_csrbank3_value3_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_value3_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd10));
assign builder_minsoc_csrbank3_value3_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd10));
assign builder_minsoc_csrbank3_value2_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_value2_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd11));
assign builder_minsoc_csrbank3_value2_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd11));
assign builder_minsoc_csrbank3_value1_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_value1_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd12));
assign builder_minsoc_csrbank3_value1_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd12));
assign builder_minsoc_csrbank3_value0_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_value0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd13));
assign builder_minsoc_csrbank3_value0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd13));
assign main_minsoc_timer0_eventmanager_status_r = builder_minsoc_interface3_bank_bus_dat_w[0];
assign main_minsoc_timer0_eventmanager_status_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd14));
assign main_minsoc_timer0_eventmanager_status_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd14));
assign main_minsoc_timer0_eventmanager_pending_r = builder_minsoc_interface3_bank_bus_dat_w[0];
assign main_minsoc_timer0_eventmanager_pending_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd15));
assign main_minsoc_timer0_eventmanager_pending_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd15));
assign builder_minsoc_csrbank3_ev_enable0_r = builder_minsoc_interface3_bank_bus_dat_w[0];
assign builder_minsoc_csrbank3_ev_enable0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 5'd16));
assign builder_minsoc_csrbank3_ev_enable0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 5'd16));
assign builder_minsoc_csrbank3_load3_w = main_minsoc_timer0_load_storage[31:24];
assign builder_minsoc_csrbank3_load2_w = main_minsoc_timer0_load_storage[23:16];
assign builder_minsoc_csrbank3_load1_w = main_minsoc_timer0_load_storage[15:8];
assign builder_minsoc_csrbank3_load0_w = main_minsoc_timer0_load_storage[7:0];
assign builder_minsoc_csrbank3_reload3_w = main_minsoc_timer0_reload_storage[31:24];
assign builder_minsoc_csrbank3_reload2_w = main_minsoc_timer0_reload_storage[23:16];
assign builder_minsoc_csrbank3_reload1_w = main_minsoc_timer0_reload_storage[15:8];
assign builder_minsoc_csrbank3_reload0_w = main_minsoc_timer0_reload_storage[7:0];
assign builder_minsoc_csrbank3_en0_w = main_minsoc_timer0_en_storage;
assign builder_minsoc_csrbank3_update_value0_w = main_minsoc_timer0_update_value_storage;
assign builder_minsoc_csrbank3_value3_w = main_minsoc_timer0_value_status[31:24];
assign builder_minsoc_csrbank3_value2_w = main_minsoc_timer0_value_status[23:16];
assign builder_minsoc_csrbank3_value1_w = main_minsoc_timer0_value_status[15:8];
assign builder_minsoc_csrbank3_value0_w = main_minsoc_timer0_value_status[7:0];
assign main_minsoc_timer0_value_we = builder_minsoc_csrbank3_value0_we;
assign builder_minsoc_csrbank3_ev_enable0_w = main_minsoc_timer0_eventmanager_storage;
assign builder_minsoc_csrbank4_sel = (builder_minsoc_interface4_bank_bus_adr[13:9] == 2'd3);
assign main_minsoc_uart_rxtx_r = builder_minsoc_interface4_bank_bus_dat_w[7:0];
assign main_minsoc_uart_rxtx_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd0));
assign main_minsoc_uart_rxtx_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd0));
assign builder_minsoc_csrbank4_txfull_r = builder_minsoc_interface4_bank_bus_dat_w[0];
assign builder_minsoc_csrbank4_txfull_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd1));
assign builder_minsoc_csrbank4_txfull_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd1));
assign builder_minsoc_csrbank4_rxempty_r = builder_minsoc_interface4_bank_bus_dat_w[0];
assign builder_minsoc_csrbank4_rxempty_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd2));
assign builder_minsoc_csrbank4_rxempty_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd2));
assign main_minsoc_uart_eventmanager_status_r = builder_minsoc_interface4_bank_bus_dat_w[1:0];
assign main_minsoc_uart_eventmanager_status_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd3));
assign main_minsoc_uart_eventmanager_status_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd3));
assign main_minsoc_uart_eventmanager_pending_r = builder_minsoc_interface4_bank_bus_dat_w[1:0];
assign main_minsoc_uart_eventmanager_pending_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd4));
assign main_minsoc_uart_eventmanager_pending_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd4));
assign builder_minsoc_csrbank4_ev_enable0_r = builder_minsoc_interface4_bank_bus_dat_w[1:0];
assign builder_minsoc_csrbank4_ev_enable0_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd5));
assign builder_minsoc_csrbank4_ev_enable0_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd5));
assign builder_minsoc_csrbank4_txfull_w = main_minsoc_uart_txfull_status;
assign main_minsoc_uart_txfull_we = builder_minsoc_csrbank4_txfull_we;
assign builder_minsoc_csrbank4_rxempty_w = main_minsoc_uart_rxempty_status;
assign main_minsoc_uart_rxempty_we = builder_minsoc_csrbank4_rxempty_we;
assign builder_minsoc_csrbank4_ev_enable0_w = main_minsoc_uart_eventmanager_storage[1:0];
assign builder_minsoc_csrbank5_sel = (builder_minsoc_interface5_bank_bus_adr[13:9] == 2'd2);
assign builder_minsoc_csrbank5_tuning_word3_r = builder_minsoc_interface5_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank5_tuning_word3_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd0));
assign builder_minsoc_csrbank5_tuning_word3_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd0));
assign builder_minsoc_csrbank5_tuning_word2_r = builder_minsoc_interface5_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank5_tuning_word2_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd1));
assign builder_minsoc_csrbank5_tuning_word2_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd1));
assign builder_minsoc_csrbank5_tuning_word1_r = builder_minsoc_interface5_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank5_tuning_word1_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd2));
assign builder_minsoc_csrbank5_tuning_word1_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd2));
assign builder_minsoc_csrbank5_tuning_word0_r = builder_minsoc_interface5_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank5_tuning_word0_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd3));
assign builder_minsoc_csrbank5_tuning_word0_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd3));
assign builder_minsoc_csrbank5_tuning_word3_w = main_minsoc_storage[31:24];
assign builder_minsoc_csrbank5_tuning_word2_w = main_minsoc_storage[23:16];
assign builder_minsoc_csrbank5_tuning_word1_w = main_minsoc_storage[15:8];
assign builder_minsoc_csrbank5_tuning_word0_w = main_minsoc_storage[7:0];
assign builder_minsoc_adr = main_minsoc_interface_adr;
assign builder_minsoc_we = main_minsoc_interface_we;
assign builder_minsoc_dat_w = main_minsoc_interface_dat_w;
assign main_minsoc_interface_dat_r = builder_minsoc_dat_r;
assign builder_minsoc_interface0_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface1_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface2_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface3_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface4_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface5_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface0_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface1_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface2_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface3_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface4_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface5_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface0_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_interface1_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_interface2_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_interface3_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_interface4_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_interface5_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_dat_r = (((((builder_minsoc_interface0_bank_bus_dat_r | builder_minsoc_interface1_bank_bus_dat_r) | builder_minsoc_interface2_bank_bus_dat_r) | builder_minsoc_interface3_bank_bus_dat_r) | builder_minsoc_interface4_bank_bus_dat_r) | builder_minsoc_interface5_bank_bus_dat_r);
always @(*) begin
builder_rhs_array_muxed0 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[0];
end
1'd1: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[1];
end
2'd2: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[2];
end
2'd3: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[3];
end
3'd4: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[4];
end
3'd5: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[5];
end
3'd6: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[6];
end
default: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[7];
end
endcase
end
always @(*) begin
builder_rhs_array_muxed1 <= 14'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine0_cmd_payload_a;
end
1'd1: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine1_cmd_payload_a;
end
2'd2: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine2_cmd_payload_a;
end
2'd3: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine3_cmd_payload_a;
end
3'd4: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine4_cmd_payload_a;
end
3'd5: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine5_cmd_payload_a;
end
3'd6: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine6_cmd_payload_a;
end
default: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine7_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed2 <= 3'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine0_cmd_payload_ba;
end
1'd1: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine1_cmd_payload_ba;
end
2'd2: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine2_cmd_payload_ba;
end
2'd3: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine3_cmd_payload_ba;
end
3'd4: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine4_cmd_payload_ba;
end
3'd5: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine5_cmd_payload_ba;
end
3'd6: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine6_cmd_payload_ba;
end
default: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine7_cmd_payload_ba;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed3 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine6_cmd_payload_is_read;
end
default: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine7_cmd_payload_is_read;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed4 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine6_cmd_payload_is_write;
end
default: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine7_cmd_payload_is_write;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed5 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine6_cmd_payload_is_cmd;
end
default: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine7_cmd_payload_is_cmd;
end
endcase
end
always @(*) begin
builder_t_array_muxed0 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_t_array_muxed0 <= main_sdram_bankmachine0_cmd_payload_cas;
end
1'd1: begin
builder_t_array_muxed0 <= main_sdram_bankmachine1_cmd_payload_cas;
end
2'd2: begin
builder_t_array_muxed0 <= main_sdram_bankmachine2_cmd_payload_cas;
end
2'd3: begin
builder_t_array_muxed0 <= main_sdram_bankmachine3_cmd_payload_cas;
end
3'd4: begin
builder_t_array_muxed0 <= main_sdram_bankmachine4_cmd_payload_cas;
end
3'd5: begin
builder_t_array_muxed0 <= main_sdram_bankmachine5_cmd_payload_cas;
end
3'd6: begin
builder_t_array_muxed0 <= main_sdram_bankmachine6_cmd_payload_cas;
end
default: begin
builder_t_array_muxed0 <= main_sdram_bankmachine7_cmd_payload_cas;
end
endcase
end
always @(*) begin
builder_t_array_muxed1 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_t_array_muxed1 <= main_sdram_bankmachine0_cmd_payload_ras;
end
1'd1: begin
builder_t_array_muxed1 <= main_sdram_bankmachine1_cmd_payload_ras;
end
2'd2: begin
builder_t_array_muxed1 <= main_sdram_bankmachine2_cmd_payload_ras;
end
2'd3: begin
builder_t_array_muxed1 <= main_sdram_bankmachine3_cmd_payload_ras;
end
3'd4: begin
builder_t_array_muxed1 <= main_sdram_bankmachine4_cmd_payload_ras;
end
3'd5: begin
builder_t_array_muxed1 <= main_sdram_bankmachine5_cmd_payload_ras;
end
3'd6: begin
builder_t_array_muxed1 <= main_sdram_bankmachine6_cmd_payload_ras;
end
default: begin
builder_t_array_muxed1 <= main_sdram_bankmachine7_cmd_payload_ras;
end
endcase
end
always @(*) begin
builder_t_array_muxed2 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_t_array_muxed2 <= main_sdram_bankmachine0_cmd_payload_we;
end
1'd1: begin
builder_t_array_muxed2 <= main_sdram_bankmachine1_cmd_payload_we;
end
2'd2: begin
builder_t_array_muxed2 <= main_sdram_bankmachine2_cmd_payload_we;
end
2'd3: begin
builder_t_array_muxed2 <= main_sdram_bankmachine3_cmd_payload_we;
end
3'd4: begin
builder_t_array_muxed2 <= main_sdram_bankmachine4_cmd_payload_we;
end
3'd5: begin
builder_t_array_muxed2 <= main_sdram_bankmachine5_cmd_payload_we;
end
3'd6: begin
builder_t_array_muxed2 <= main_sdram_bankmachine6_cmd_payload_we;
end
default: begin
builder_t_array_muxed2 <= main_sdram_bankmachine7_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed6 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[0];
end
1'd1: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[1];
end
2'd2: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[2];
end
2'd3: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[3];
end
3'd4: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[4];
end
3'd5: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[5];
end
3'd6: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[6];
end
default: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[7];
end
endcase
end
always @(*) begin
builder_rhs_array_muxed7 <= 14'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine0_cmd_payload_a;
end
1'd1: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine1_cmd_payload_a;
end
2'd2: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine2_cmd_payload_a;
end
2'd3: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine3_cmd_payload_a;
end
3'd4: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine4_cmd_payload_a;
end
3'd5: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine5_cmd_payload_a;
end
3'd6: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine6_cmd_payload_a;
end
default: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine7_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed8 <= 3'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine0_cmd_payload_ba;
end
1'd1: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine1_cmd_payload_ba;
end
2'd2: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine2_cmd_payload_ba;
end
2'd3: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine3_cmd_payload_ba;
end
3'd4: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine4_cmd_payload_ba;
end
3'd5: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine5_cmd_payload_ba;
end
3'd6: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine6_cmd_payload_ba;
end
default: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine7_cmd_payload_ba;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed9 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine6_cmd_payload_is_read;
end
default: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine7_cmd_payload_is_read;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed10 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine6_cmd_payload_is_write;
end
default: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine7_cmd_payload_is_write;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed11 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine6_cmd_payload_is_cmd;
end
default: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine7_cmd_payload_is_cmd;
end
endcase
end
always @(*) begin
builder_t_array_muxed3 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_t_array_muxed3 <= main_sdram_bankmachine0_cmd_payload_cas;
end
1'd1: begin
builder_t_array_muxed3 <= main_sdram_bankmachine1_cmd_payload_cas;
end
2'd2: begin
builder_t_array_muxed3 <= main_sdram_bankmachine2_cmd_payload_cas;
end
2'd3: begin
builder_t_array_muxed3 <= main_sdram_bankmachine3_cmd_payload_cas;
end
3'd4: begin
builder_t_array_muxed3 <= main_sdram_bankmachine4_cmd_payload_cas;
end
3'd5: begin
builder_t_array_muxed3 <= main_sdram_bankmachine5_cmd_payload_cas;
end
3'd6: begin
builder_t_array_muxed3 <= main_sdram_bankmachine6_cmd_payload_cas;
end
default: begin
builder_t_array_muxed3 <= main_sdram_bankmachine7_cmd_payload_cas;
end
endcase
end
always @(*) begin
builder_t_array_muxed4 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_t_array_muxed4 <= main_sdram_bankmachine0_cmd_payload_ras;
end
1'd1: begin
builder_t_array_muxed4 <= main_sdram_bankmachine1_cmd_payload_ras;
end
2'd2: begin
builder_t_array_muxed4 <= main_sdram_bankmachine2_cmd_payload_ras;
end
2'd3: begin
builder_t_array_muxed4 <= main_sdram_bankmachine3_cmd_payload_ras;
end
3'd4: begin
builder_t_array_muxed4 <= main_sdram_bankmachine4_cmd_payload_ras;
end
3'd5: begin
builder_t_array_muxed4 <= main_sdram_bankmachine5_cmd_payload_ras;
end
3'd6: begin
builder_t_array_muxed4 <= main_sdram_bankmachine6_cmd_payload_ras;
end
default: begin
builder_t_array_muxed4 <= main_sdram_bankmachine7_cmd_payload_ras;
end
endcase
end
always @(*) begin
builder_t_array_muxed5 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_t_array_muxed5 <= main_sdram_bankmachine0_cmd_payload_we;
end
1'd1: begin
builder_t_array_muxed5 <= main_sdram_bankmachine1_cmd_payload_we;
end
2'd2: begin
builder_t_array_muxed5 <= main_sdram_bankmachine2_cmd_payload_we;
end
2'd3: begin
builder_t_array_muxed5 <= main_sdram_bankmachine3_cmd_payload_we;
end
3'd4: begin
builder_t_array_muxed5 <= main_sdram_bankmachine4_cmd_payload_we;
end
3'd5: begin
builder_t_array_muxed5 <= main_sdram_bankmachine5_cmd_payload_we;
end
3'd6: begin
builder_t_array_muxed5 <= main_sdram_bankmachine6_cmd_payload_we;
end
default: begin
builder_t_array_muxed5 <= main_sdram_bankmachine7_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed12 <= 21'd0;
case (builder_roundrobin0_grant)
default: begin
builder_rhs_array_muxed12 <= {
main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]
};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed13 <= 1'd0;
case (builder_roundrobin0_grant)
default: begin
builder_rhs_array_muxed13 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed14 <= 1'd0;
case (builder_roundrobin0_grant)
default: begin
builder_rhs_array_muxed14 <= (((main_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed15 <= 21'd0;
case (builder_roundrobin1_grant)
default: begin
builder_rhs_array_muxed15 <= {
main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]
};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed16 <= 1'd0;
case (builder_roundrobin1_grant)
default: begin
builder_rhs_array_muxed16 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed17 <= 1'd0;
case (builder_roundrobin1_grant)
default: begin
builder_rhs_array_muxed17 <= (((main_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed18 <= 21'd0;
case (builder_roundrobin2_grant)
default: begin
builder_rhs_array_muxed18 <= {
main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]
};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed19 <= 1'd0;
case (builder_roundrobin2_grant)
default: begin
builder_rhs_array_muxed19 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed20 <= 1'd0;
case (builder_roundrobin2_grant)
default: begin
builder_rhs_array_muxed20 <= (((main_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed21 <= 21'd0;
case (builder_roundrobin3_grant)
default: begin
builder_rhs_array_muxed21 <= {
main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]
};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed22 <= 1'd0;
case (builder_roundrobin3_grant)
default: begin
builder_rhs_array_muxed22 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed23 <= 1'd0;
case (builder_roundrobin3_grant)
default: begin
builder_rhs_array_muxed23 <= (((main_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed24 <= 21'd0;
case (builder_roundrobin4_grant)
default: begin
builder_rhs_array_muxed24 <= {
main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]
};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed25 <= 1'd0;
case (builder_roundrobin4_grant)
default: begin
builder_rhs_array_muxed25 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed26 <= 1'd0;
case (builder_roundrobin4_grant)
default: begin
builder_rhs_array_muxed26 <= (((main_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed27 <= 21'd0;
case (builder_roundrobin5_grant)
default: begin
builder_rhs_array_muxed27 <= {
main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]
};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed28 <= 1'd0;
case (builder_roundrobin5_grant)
default: begin
builder_rhs_array_muxed28 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed29 <= 1'd0;
case (builder_roundrobin5_grant)
default: begin
builder_rhs_array_muxed29 <= (((main_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed30 <= 21'd0;
case (builder_roundrobin6_grant)
default: begin
builder_rhs_array_muxed30 <= {
main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]
};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed31 <= 1'd0;
case (builder_roundrobin6_grant)
default: begin
builder_rhs_array_muxed31 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed32 <= 1'd0;
case (builder_roundrobin6_grant)
default: begin
builder_rhs_array_muxed32 <= (((main_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed33 <= 21'd0;
case (builder_roundrobin7_grant)
default: begin
builder_rhs_array_muxed33 <= {
main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]
};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed34 <= 1'd0;
case (builder_roundrobin7_grant)
default: begin
builder_rhs_array_muxed34 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed35 <= 1'd0;
case (builder_roundrobin7_grant)
default: begin
builder_rhs_array_muxed35 <= (((main_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed36 <= 30'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed36 <= main_interface1_wb_sdram_adr;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed37 <= 32'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed37 <= main_interface1_wb_sdram_dat_w;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed38 <= 4'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed38 <= main_interface1_wb_sdram_sel;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed39 <= 1'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed39 <= main_interface1_wb_sdram_cyc;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed40 <= 1'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed40 <= main_interface1_wb_sdram_stb;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed41 <= 1'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed41 <= main_interface1_wb_sdram_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed42 <= 3'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed42 <= main_interface1_wb_sdram_cti;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed43 <= 2'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed43 <= main_interface1_wb_sdram_bte;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed44 <= 30'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed44 <= main_minsoc_interface0_soc_bus_adr;
end
default: begin
builder_rhs_array_muxed44 <= main_minsoc_interface1_soc_bus_adr;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed45 <= 32'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed45 <= main_minsoc_interface0_soc_bus_dat_w;
end
default: begin
builder_rhs_array_muxed45 <= main_minsoc_interface1_soc_bus_dat_w;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed46 <= 4'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed46 <= main_minsoc_interface0_soc_bus_sel;
end
default: begin
builder_rhs_array_muxed46 <= main_minsoc_interface1_soc_bus_sel;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed47 <= 1'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed47 <= main_minsoc_interface0_soc_bus_cyc;
end
default: begin
builder_rhs_array_muxed47 <= main_minsoc_interface1_soc_bus_cyc;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed48 <= 1'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed48 <= main_minsoc_interface0_soc_bus_stb;
end
default: begin
builder_rhs_array_muxed48 <= main_minsoc_interface1_soc_bus_stb;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed49 <= 1'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed49 <= main_minsoc_interface0_soc_bus_we;
end
default: begin
builder_rhs_array_muxed49 <= main_minsoc_interface1_soc_bus_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed50 <= 3'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed50 <= main_minsoc_interface0_soc_bus_cti;
end
default: begin
builder_rhs_array_muxed50 <= main_minsoc_interface1_soc_bus_cti;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed51 <= 2'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed51 <= main_minsoc_interface0_soc_bus_"b"bte;
end
default: begin
builder_rhs_array_muxed51 <= main_minsoc_interface1_soc_bus_bte;
end
endcase
end
always @(*) begin
builder_array_muxed0 <= 3'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed0 <= main_sdram_nop_ba[2:0];
end
1'd1: begin
builder_array_muxed0 <= main_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
builder_array_muxed0 <= main_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
builder_array_muxed0 <= main_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
builder_array_muxed1 <= 14'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed1 <= main_sdram_nop_a;
end
1'd1: begin
builder_array_muxed1 <= main_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
builder_array_muxed1 <= main_sdram_choose_req_cmd_payload_a;
end
default: begin
builder_array_muxed1 <= main_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_array_muxed2 <= 1'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed2 <= 1'd0;
end
1'd1: begin
builder_array_muxed2 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
builder_array_muxed2 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);
end
default: begin
builder_array_muxed2 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
builder_array_muxed3 <= 1'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed3 <= 1'd0;
end
1'd1: begin
builder_array_muxed3 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
builder_array_muxed3 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);
end
default: begin
builder_array_muxed3 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
builder_array_muxed4 <= 1'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed4 <= 1'd0;
end
1'd1: begin
builder_array_muxed4 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
builder_array_muxed4 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);
end
default: begin
builder_array_muxed4 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
builder_array_muxed5 <= 1'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed5 <= 1'd0;
end
1'd1: begin
builder_array_muxed5 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
builder_array_muxed5 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);
end
default: begin
builder_array_muxed5 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
builder_array_muxed6 <= 1'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed6 <= 1'd0;
end
1'd1: begin
builder_array_muxed6 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
builder_array_muxed6 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
end
default: begin
builder_array_muxed6 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write);
end
endcase
end
always @(*) begin
builder_array_muxed7 <= 3'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed7 <= main_sdram_nop_ba[2:0];
end
1'd1: begin
builder_array_muxed7 <= main_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
builder_array_muxed7 <= main_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
builder_array_muxed7 <= main_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
builder_array_muxed8 <= 14'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed8 <= main_sdram_nop_a;
end
1'd1: begin
builder_array_muxed8 <= main_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
builder_array_muxed8 <= main_sdram_choose_req_cmd_payload_a;
end
default: begin
builder_array_muxed8 <= main_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_array_muxed9 <= 1'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed9 <= 1'd0;
end
1'd1: begin
builder_array_muxed9 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
builder_array_muxed9 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);
end
default: begin
builder_array_muxed9 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
builder_array_muxed10 <= 1'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed10 <= 1'd0;
end
1'd1: begin
builder_array_muxed10 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
builder_array_muxed10 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);
end
default: begin
builder_array_muxed10 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
builder_array_muxed11 <= 1'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed11 <= 1'd0;
end
1'd1: begin
builder_array_muxed11 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
builder_array_muxed11 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);
end
default: begin
builder_array_muxed11 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
builder_array_muxed12 <= 1'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed12 <= 1'd0;
end
1'd1: begin
builder_array_muxed12 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
builder_array_muxed12 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);
end
default: begin
builder_array_muxed12 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
builder_array_muxed13 <= 1'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed13 <= 1'd0;
end
1'd1: begin
builder_array_muxed13 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
builder_array_muxed13 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
end
default: begin
builder_array_muxed13 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write);
end
endcase
end
always @(*) begin
builder_array_muxed14 <= 3'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed14 <= main_sdram_nop_ba[2:0];
end
1'd1: begin
builder_array_muxed14 <= main_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
builder_array_muxed14 <= main_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
builder_array_muxed14 <= main_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
builder_array_muxed15 <= 14'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed15 <= main_sdram_nop_a;
end
1'd1: begin
builder_array_muxed15 <= main_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
builder_array_muxed15 <= main_sdram_choose_req_cmd_payload_a;
end
default: begin
builder_array_muxed15 <= main_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_array_muxed16 <= 1'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed16 <= 1'd0;
end
1'd1: begin
builder_array_muxed16 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
builder_array_muxed16 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);
end
default: begin
builder_array_muxed16 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
builder_array_muxed17 <= 1'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed17 <= 1'd0;
end
1'd1: begin
builder_array_muxed17 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
builder_array_muxed17 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);
end
default: begin
builder_array_muxed17 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
builder_array_muxed18 <= 1'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed18 <= 1'd0;
end
1'd1: begin
builder_array_muxed18 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
builder_array_muxed18 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);
end
default: begin
builder_array_muxed18 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
builder_array_muxed19 <= 1'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed19 <= 1'd0;
end
1'd1: begin
builder_array_muxed19 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
builder_array_muxed19 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);
end
default: begin
builder_array_muxed19 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
builder_array_muxed20 <= 1'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed20 <= 1'd0;
end
1'd1: begin
builder_array_muxed20 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
builder_array_muxed20 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
end
default: begin
builder_array_muxed20 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write);
end
endcase
end
always @(*) begin
builder_array_muxed21 <= 3'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed21 <= main_sdram_nop_ba[2:0];
end
1'd1: begin
builder_array_muxed21 <= main_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
builder_array_muxed21 <= main_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
builder_array_muxed21 <= main_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
builder_array_muxed22 <= 14'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed22 <= main_sdram_nop_a;
end
1'd1: begin
builder_array_muxed22 <= main_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
builder_array_muxed22 <= main_sdram_choose_req_cmd_payload_a;
end
default: begin
builder_array_muxed22 <= main_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_array_muxed23 <= 1'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed23 <= 1'd0;
end
1'd1: begin
builder_array_muxed23 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
builder_array_muxed23 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);
end
default: begin
builder_array_muxed23 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
builder_array_muxed24 <= 1'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed24 <= 1'd0;
end
1'd1: begin
builder_array_muxed24 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
builder_array_muxed24 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);
end
default: begin
builder_array_muxed24 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
builder_array_muxed25 <= 1'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed25 <= 1'd0;
end
1'd1: begin
builder_array_muxed25 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
builder_array_muxed25 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);
end
default: begin
builder_array_muxed25 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
builder_array_muxed26 <= 1'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed26 <= 1'd0;
end
1'd1: begin
builder_array_muxed26 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
builder_array_muxed26 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);
end
default: begin
builder_array_muxed26 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
builder_array_muxed27 <= 1'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed27 <= 1'd0;
end
1'd1: begin
builder_array_muxed27 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
builder_array_muxed27 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
end
default: begin
builder_array_muxed27 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write);
end
endcase
end
assign main_minsoc_rx = builder_regs1;
assign builder_xilinxasyncresetsynchronizerimpl0 = ((~main_locked) | main_reset);
assign builder_xilinxasyncresetsynchronizerimpl1 = ((~main_locked) | main_reset);
assign builder_xilinxasyncresetsynchronizerimpl2 = ((~main_locked) | main_reset);
assign builder_xilinxasyncresetsynchronizerimpl3 = ((~main_locked) | main_reset);
always @(posedge clk200_clk) begin
if ((main_reset_counter != 1'd0)) begin
main_reset_counter <= (main_reset_counter - 1'd1);
end else begin
main_ic_reset <= 1'd0;
end
if (clk200_rst) begin
main_reset_counter <= 4'd15;
main_ic_reset <= 1'd1;
end
end
always @(posedge sys_clk) begin
if ((main_minsoc_ctrl_bus_errors != 32'd4294967295)) begin
if (main_minsoc_ctrl_bus_error) begin
main_minsoc_ctrl_bus_errors <= (main_minsoc_ctrl_bus_errors + 1'd1);
end
end
main_minsoc_rom_bus_ack <= 1'd0;
if (((main_minsoc_rom_bus_cyc & main_minsoc_rom_bus_stb) & (~main_minsoc_rom_bus_ack))) begin
main_minsoc_rom_bus_ack <= 1'd1;
end
main_minsoc_sram_bus_ack <= 1'd0;
if (((main_minsoc_sram_bus_cyc & main_minsoc_sram_bus_stb) & (~main_minsoc_sram_bus_ack))) begin
main_minsoc_sram_bus_ack <= 1'd1;
end
main_minsoc_sink_ready <= 1'd0;
if (((main_minsoc_sink_valid & (~main_minsoc_tx_busy)) & (~main_minsoc_sink_ready))) begin
main_minsoc_tx_reg <= main_minsoc_sink_payload_data;
main_minsoc_tx_bitcount <= 1'd0;
main_minsoc_tx_busy <= 1'd1;
serial_tx <= 1'd0;
end else begin
if ((main_minsoc_uart_clk_txen & main_minsoc_tx_busy)) begin
main_minsoc_tx_bitcount <= (main_minsoc_tx_bitcount + 1'd1);
if ((main_minsoc_tx_bitcount == 4'd8)) begin
serial_tx <= 1'd1;
end else begin
if ((main_minsoc_tx_bitcount == 4'd9)) begin
serial_tx <= 1'd1;
main_minsoc_tx_busy <= 1'd0;
main_minsoc_sink_ready <= 1'd1;
end else begin
serial_tx <= main_minsoc_tx_reg[0];
main_minsoc_tx_reg <= {1'd0, main_minsoc_tx_reg[7:1]};
end
end
end
end
if (main_minsoc_tx_busy) begin
{main_minsoc_uart_clk_txen, main_minsoc_phase_accumulator_tx} <= (main_minsoc_phase_accumulator_tx + main_minsoc_storage);
end else begin
{main_minsoc_uart_clk_txen, main_minsoc_phase_accumulator_tx} <= 1'd0;
end
main_minsoc_source_valid <= 1'd0;
main_minsoc_rx_r <= main_minsoc_rx;
if ((~main_minsoc_rx_busy)) begin
if (((~main_minsoc_rx) & main_minsoc_rx_r)) begin
main_minsoc_rx_busy <= 1'd1;
main_minsoc_rx_bitcount <= 1'd0;
end
end else begin
if (main_minsoc_uart_clk_rxen) begin
main_minsoc_rx_bitcount <= (main_minsoc_rx_bitcount + 1'd1);
if ((main_minsoc_rx_bitcount == 1'd0)) begin
if (main_minsoc_rx) begin
main_minsoc_rx_busy <= 1'd0;
end
end else begin
if ((main_minsoc_rx_bitcount == 4'd9)) begin
main_minsoc_rx_busy <= 1'd0;
if (main_minsoc_rx) begin
main_minsoc_source_payload_data <= main_minsoc_rx_reg;
main_minsoc_source_valid <= 1'd1;
end
end else begin
main_minsoc_rx_reg <= {main_minsoc_rx, main_minsoc_rx_reg[7:1]};
end
end
end
end
if (main_minsoc_rx_busy) begin
{main_minsoc_uart_clk_rxen, main_minsoc_phase_accumulator_rx} <= (main_minsoc_phase_accumulator_rx + main_minsoc_storage);
end else begin
{main_minsoc_uart_clk_rxen, main_minsoc_phase_accumulator_rx} <= 32'd2147483648;
end
if (main_minsoc_uart_tx_clear) begin
main_minsoc_uart_tx_pending <= 1'd0;
end
main_minsoc_uart_tx_old_trigger <= main_minsoc_uart_tx_trigger;
if (((~main_minsoc_uart_tx_trigger) & main_minsoc_uart_tx_old_trigger)) begin
main_minsoc_uart_tx_pending <= 1'd1;
end
if (main_minsoc_uart_rx_clear) begin
main_minsoc_uart_rx_pending <= 1'd0;
end
main_minsoc_uart_rx_old_trigger <= main_minsoc_uart_rx_trigger;
if (((~main_minsoc_uart_rx_trigger) & main_minsoc_uart_rx_old_trigger)) begin
main_minsoc_uart_rx_pending <= 1'd1;
end
if (main_minsoc_uart_tx_fifo_syncfifo_re) begin
main_minsoc_uart_tx_fifo_readable <= 1'd1;
end else begin
if (main_minsoc_uart_tx_fifo_re) begin
main_minsoc_uart_tx_fifo_readable <= 1'd0;
end
end
if (((main_minsoc_uart_tx_fifo_syncfifo_we & main_minsoc_uart_tx_fifo_syncfifo_writable) & (~main_minsoc_uart_tx_fifo_replace))) begin
main_minsoc_uart_tx_fifo_produce <= (main_minsoc_uart_tx_fifo_produce + 1'd1);
end
if (main_minsoc_uart_tx_fifo_do_read) begin
main_minsoc_uart_tx_fifo_consume <= (main_minsoc_uart_tx_fifo_consume + 1'd1);
end
if (((main_minsoc_uart_tx_fifo_syncfifo_we & main_minsoc_uart_tx_fifo_syncfifo_writable) & (~main_minsoc_uart_tx_fifo_replace))) begin
if ((~main_minsoc_uart_tx_fifo_do_read)) begin
main_minsoc_uart_tx_fifo_level0 <= (main_minsoc_uart_tx_fifo_level0 + 1'd1);
end
end else begin
if (main_minsoc_uart_tx_fifo_do_read) begin
main_minsoc_uart_tx_fifo_level0 <= (main_minsoc_uart_tx_fifo_level0 - 1'd1);
end
end
if (main_minsoc_uart_rx_fifo_syncfifo_re) begin
main_minsoc_uart_rx_fifo_readable <= 1'd1;
end else begin
if (main_minsoc_uart_rx_fifo_re) begin
main_minsoc_uart_rx_fifo_readable <= 1'd0;
end
end
if (((main_minsoc_uart_rx_fifo_syncfifo_we & main_minsoc_uart_rx_fifo_syncfifo_writable) & (~main_minsoc_uart_rx_fifo_replace))) begin
main_minsoc_uart_rx_fifo_produce <= (main_minsoc_uart_rx_fifo_produce + 1'd1);
end
if (main_minsoc_uart_rx_fifo_do_read) begin
main_minsoc_uart_rx_fifo_consume <= (main_minsoc_uart_rx_fifo_consume + 1'd1);
end
if (((main_minsoc_uart_rx_fifo_syncfifo_we & main_minsoc_uart_rx_fifo_syncfifo_writable) & (~main_minsoc_uart_rx_fifo_replace))) begin
if ((~main_minsoc_uart_rx_fifo_do_read)) begin
main_minsoc_uart_rx_fifo_level0 <= (main_minsoc_uart_rx_fifo_level0 + 1'd1);
end
end else begin
if (main_minsoc_uart_rx_fifo_do_read) begin
main_minsoc_uart_rx_fifo_level0 <= (main_minsoc_uart_rx_fifo_level0 - 1'd1);
end
end
if (main_minsoc_uart_reset) begin
main_minsoc_uart_tx_pending <= 1'd0;
main_minsoc_uart_tx_old_trigger <= 1'd0;
main_minsoc_uart_rx_pending <= 1'd0;
main_minsoc_uart_rx_old_trigger <= 1'd0;
main_minsoc_uart_tx_fifo_readable <= 1'd0;
main_minsoc_uart_tx_fifo_level0 <= 5'd0;
main_minsoc_uart_tx_fifo_produce <= 4'd0;
main_minsoc_uart_tx_fifo_consume <= 4'd0;
main_minsoc_uart_rx_fifo_readable <= 1'd0;
main_minsoc_uart_rx_fifo_level0 <= 5'd0;
main_minsoc_uart_rx_fifo_produce <= 4'd0;
main_minsoc_uart_rx_fifo_consume <= 4'd0;
end
if (main_minsoc_timer0_en_storage) begin
if ((main_minsoc_timer0_value == 1'd0)) begin
main_minsoc_timer0_value <= main_minsoc_timer0_reload_storage;
end else begin
main_minsoc_timer0_value <= (main_minsoc_timer0_value - 1'd1);
end
end else begin
main_minsoc_timer0_value <= main_minsoc_timer0_load_storage;
end
if (main_minsoc_timer0_update_value_re) begin
main_minsoc_timer0_value_status <= main_minsoc_timer0_value;
end
if (main_minsoc_timer0_zero_clear) begin
main_minsoc_timer0_zero_pending <= 1'd0;
end
main_minsoc_timer0_zero_old_trigger <= main_minsoc_timer0_zero_trigger;
if (((~main_minsoc_timer0_zero_trigger) & main_minsoc_timer0_zero_old_trigger)) begin
main_minsoc_timer0_zero_pending <= 1'd1;
end
builder_wb2csr_state <= builder_wb2csr_next_state;
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip0_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip0_value <= (main_a7ddrphy_bitslip0_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip1_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip1_value <= (main_a7ddrphy_bitslip1_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip2_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip2_value <= (main_a7ddrphy_bitslip2_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip3_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip3_value <= (main_a7ddrphy_bitslip3_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip4_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip4_value <= (main_a7ddrphy_bitslip4_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip5_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip5_value <= (main_a7ddrphy_bitslip5_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip6_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip6_value <= (main_a7ddrphy_bitslip6_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip7_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip7_value <= (main_a7ddrphy_bitslip7_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip8_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip8_value <= (main_a7ddrphy_bitslip8_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip9_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip9_value <= (main_a7ddrphy_bitslip9_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip10_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip10_value <= (main_a7ddrphy_bitslip10_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip11_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip11_value <= (main_a7ddrphy_bitslip11_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip12_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip12_value <= (main_a7ddrphy_bitslip12_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip13_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip13_value <= (main_a7ddrphy_bitslip13_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip14_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip14_value <= (main_a7ddrphy_bitslip14_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip15_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip15_value <= (main_a7ddrphy_bitslip15_value + 1'd1);
end
end
end
main_a7ddrphy_n_rddata_en0 <= main_a7ddrphy_dfi_p2_rddata_en;
main_a7ddrphy_n_rddata_en1 <= main_a7ddrphy_n_rddata_en0;
main_a7ddrphy_n_rddata_en2 <= main_a7ddrphy_n_rddata_en1;
main_a7ddrphy_n_rddata_en3 <= main_a7ddrphy_n_rddata_en2;
main_a7ddrphy_n_rddata_en4 <= main_a7ddrphy_n_rddata_en3;
main_a7ddrphy_n_rddata_en5 <= main_a7ddrphy_n_rddata_en4;
main_a7ddrphy_n_rddata_en6 <= main_a7ddrphy_n_rddata_en5;
main_a7ddrphy_n_rddata_en7 <= main_a7ddrphy_n_rddata_en6;
main_a7ddrphy_dfi_p0_rddata_valid <= main_a7ddrphy_n_rddata_en7;
main_a7ddrphy_dfi_p1_rddata_valid <= main_a7ddrphy_n_rddata_en7;
main_a7ddrphy_dfi_p2_rddata_valid <= main_a7ddrphy_n_rddata_en7;
main_a7ddrphy_dfi_p3_rddata_valid <= main_a7ddrphy_n_rddata_en7;
main_a7ddrphy_last_wrdata_en <= {
main_a7ddrphy_last_wrdata_en[2:0], main_a7ddrphy_dfi_p3_wrdata_en
};
main_a7ddrphy_oe_dqs <= main_a7ddrphy_oe;
main_a7ddrphy_oe_dq <= main_a7ddrphy_oe;
main_a7ddrphy_bitslip0_r <= {main_a7ddrphy_bitslip0_i, main_a7ddrphy_bitslip0_r[15:8]};
case (main_a7ddrphy_bitslip0_value)
1'd0: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[14:7];
end
endcase
main_a7ddrphy_bitslip1_r <= {main_a7ddrphy_bitslip1_i, main_a7ddrphy_bitslip1_r[15:8]};
case (main_a7ddrphy_bitslip1_value)
1'd0: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[14:7];
end
endcase
main_a7ddrphy_bitslip2_r <= {main_a7ddrphy_bitslip2_i, main_a7ddrphy_bitslip2_r[15:8]};
case (main_a7ddrphy_bitslip2_value)
1'd0: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[14:7];
end
endcase
main_a7ddrphy_bitslip3_r <= {main_a7ddrphy_bitslip3_i, main_a7ddrphy_bitslip3_r[15:8]};
case (main_a7ddrphy_bitslip3_value)
1'd0: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[14:7];
end
endcase
main_a7ddrphy_bitslip4_r <= {main_a7ddrphy_bitslip4_i, main_a7ddrphy_bitslip4_r[15:8]};
case (main_a7ddrphy_bitslip4_value)
1'd0: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[14:7];
end
endcase
main_a7ddrphy_bitslip5_r <= {main_a7ddrphy_bitslip5_i, main_a7ddrphy_bitslip5_r[15:8]};
case (main_a7ddrphy_bitslip5_value)
1'd0: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[14:7];
end
endcase
main_a7ddrphy_bitslip6_r <= {main_a7ddrphy_bitslip6_i, main_a7ddrphy_bitslip6_r[15:8]};
case (main_a7ddrphy_bitslip6_value)
1'd0: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[14:7];
end
endcase
main_a7ddrphy_bitslip7_r <= {main_a7ddrphy_bitslip7_i, main_a7ddrphy_bitslip7_r[15:8]};
case (main_a7ddrphy_bitslip7_value)
1'd0: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[14:7];
end
endcase
main_a7ddrphy_bitslip8_r <= {main_a7ddrphy_bitslip8_i, main_a7ddrphy_bitslip8_r[15:8]};
case (main_a7ddrphy_bitslip8_value)
1'd0: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[14:7];
end
endcase
main_a7ddrphy_bitslip9_r <= {main_a7ddrphy_bitslip9_i, main_a7ddrphy_bitslip9_r[15:8]};
case (main_a7ddrphy_bitslip9_value)
1'd0: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[14:7];
end
endcase
main_a7ddrphy_bitslip10_r <= {main_a7ddrphy_bitslip10_i, main_a7ddrphy_bitslip10_r[15:8]};
case (main_a7ddrphy_bitslip10_value)
1'd0: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[14:7];
end
endcase
main_a7ddrphy_bitslip11_r <= {main_a7ddrphy_bitslip11_i, main_a7ddrphy_bitslip11_r[15:8]};
case (main_a7ddrphy_bitslip11_value)
1'd0: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[14:7];
end
endcase
main_a7ddrphy_bitslip12_r <= {main_a7ddrphy_bitslip12_i, main_a7ddrphy_bitslip12_r[15:8]};
case (main_a7ddrphy_bitslip12_value)
1'd0: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[14:7];
end
endcase
main_a7ddrphy_bitslip13_r <= {main_a7ddrphy_bitslip13_i, main_a7ddrphy_bitslip13_r[15:8]};
case (main_a7ddrphy_bitslip13_value)
1'd0: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[14:7];
end
endcase
main_a7ddrphy_bitslip14_r <= {main_a7ddrphy_bitslip14_i, main_a7ddrphy_bitslip14_r[15:8]};
case (main_a7ddrphy_bitslip14_value)
1'd0: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[14:7];
end
endcase
main_a7ddrphy_bitslip15_r <= {main_a7ddrphy_bitslip15_i, main_a7ddrphy_bitslip15_r[15:8]};
case (main_a7ddrphy_bitslip15_value)
1'd0: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[14:7];
end
endcase
if (main_sdram_inti_p0_rddata_valid) begin
main_sdram_phaseinjector0_status <= main_sdram_inti_p0_rddata;
end
if (main_sdram_inti_p1_rddata_valid) begin
main_sdram_phaseinjector1_status <= main_sdram_inti_p1_rddata;
end
if (main_sdram_inti_p2_rddata_valid) begin
main_sdram_phaseinjector2_status <= main_sdram_inti_p2_rddata;
end
if (main_sdram_inti_p3_rddata_valid) begin
main_sdram_phaseinjector3_status <= main_sdram_inti_p3_rddata;
end
if ((main_sdram_timer_wait & (~main_sdram_timer_done0))) begin
main_sdram_timer_count1 <= (main_sdram_timer_count1 - 1'd1);
end else begin
main_sdram_timer_count1 <= 9'd468;
end
main_sdram_postponer_req_o <= 1'd0;
if (main_sdram_postponer_req_i) begin
main_sdram_postponer_count <= (main_sdram_postponer_count - 1'd1);
if ((main_sdram_postponer_count == 1'd0)) begin
main_sdram_postponer_count <= 1'd0;
main_sdram_postponer_req_o <= 1'd1;
end
end
if (main_sdram_sequencer_start0) begin
main_sdram_sequencer_count <= 1'd0;
end else begin
if (main_sdram_sequencer_done1) begin
if ((main_sdram_sequencer_count != 1'd0)) begin
main_sdram_sequencer_count <= (main_sdram_sequencer_count - 1'd1);
end
end
end
main_sdram_cmd_payload_a <= 1'd0;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd0;
main_sdram_cmd_payload_we <= 1'd0;
main_sdram_sequencer_done1 <= 1'd0;
if ((main_sdram_sequencer_start1 & (main_sdram_sequencer_counter == 1'd0))) begin
main_sdram_cmd_payload_a <= 11'd1024;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd1;
main_sdram_cmd_payload_we <= 1'd1;
end
if ((main_sdram_sequencer_counter == 2'd2)) begin
main_sdram_cmd_payload_a <= 1'd0;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd1;
main_sdram_cmd_payload_ras <= 1'd1;
main_sdram_cmd_payload_we <= 1'd0;
end
if ((main_sdram_sequencer_counter == 6'd34)) begin
main_sdram_cmd_payload_a <= 1'd0;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd0;
main_sdram_cmd_payload_we <= 1'd0;
main_sdram_sequencer_done1 <= 1'd1;
end
if ((main_sdram_sequencer_counter == 6'd34)) begin
main_sdram_sequencer_counter <= 1'd0;
end else begin
if ((main_sdram_sequencer_counter != 1'd0)) begin
main_sdram_sequencer_counter <= (main_sdram_sequencer_counter + 1'd1);
end else begin
if (main_sdram_sequencer_start1) begin
main_sdram_sequencer_counter <= 1'd1;
end
end
end
if ((main_sdram_zqcs_timer_wait & (~main_sdram_zqcs_timer_done0))) begin
main_sdram_zqcs_timer_count1 <= (main_sdram_zqcs_timer_count1 - 1'd1);
end else begin
main_sdram_zqcs_timer_count1 <= 26'd59999999;
end
main_sdram_zqcs_executer_done <= 1'd0;
if ((main_sdram_zqcs_executer_start & (main_sdram_zqcs_executer_counter == 1'd0))) begin
main_sdram_cmd_payload_a <= 11'd1024;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd1;
main_sdram_cmd_payload_we <= 1'd1;
end
if ((main_sdram_zqcs_executer_counter == 2'd2)) begin
main_sdram_cmd_payload_a <= 1'd0;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd0;
main_sdram_cmd_payload_we <= 1'd1;
end
if ((main_sdram_zqcs_executer_counter == 5'd18)) begin
main_sdram_cmd_payload_a <= 1'd0;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd0;
main_sdram_cmd_payload_we <= 1'd0;
main_sdram_zqcs_executer_done <= 1'd1;
end
if ((main_sdram_zqcs_executer_counter == 5'd18)) begin
main_sdram_zqcs_executer_counter <= 1'd0;
end else begin
if ((main_sdram_zqcs_executer_counter != 1'd0)) begin
main_sdram_zqcs_executer_counter <= (main_sdram_zqcs_executer_counter + 1'd1);
end else begin
if (main_sdram_zqcs_executer_start) begin
main_sdram_zqcs_executer_counter <= 1'd1;
end
end
end
builder_refresher_state <= builder_refresher_next_state;
if (main_sdram_bankmachine0_row_close) begin
main_sdram_bankmachine0_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine0_row_open) begin
main_sdram_bankmachine0_row_opened <= 1'd1;
main_sdram_bankmachine0_row <= main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_level <= (main_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_level <= (main_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~main_sdram_bankmachine0_cmd_buffer_source_valid) | main_sdram_bankmachine0_cmd_buffer_source_ready)) begin
main_sdram_bankmachine0_cmd_buffer_source_valid <= main_sdram_bankmachine0_cmd_buffer_sink_valid;
main_sdram_bankmachine0_cmd_buffer_source_first <= main_sdram_bankmachine0_cmd_buffer_sink_first;
main_sdram_bankmachine0_cmd_buffer_source_last <= main_sdram_bankmachine0_cmd_buffer_sink_last;
main_sdram_bankmachine0_cmd_buffer_source_payload_we <= main_sdram_bankmachine0_cmd_buffer_sink_payload_we;
main_sdram_bankmachine0_cmd_buffer_source_payload_addr <= main_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine0_twtpcon_valid) begin
main_sdram_bankmachine0_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine0_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine0_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine0_twtpcon_ready)) begin
main_sdram_bankmachine0_twtpcon_count <= (main_sdram_bankmachine0_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine0_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine0_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine0_trccon_valid) begin
main_sdram_bankmachine0_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine0_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine0_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine0_trccon_ready)) begin
main_sdram_bankmachine0_trccon_count <= (main_sdram_bankmachine0_trccon_count - 1'd1);
if ((main_sdram_bankmachine0_trccon_count == 1'd1)) begin
main_sdram_bankmachine0_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine0_trascon_valid) begin
main_sdram_bankmachine0_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine0_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine0_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine0_trascon_ready)) begin
main_sdram_bankmachine0_trascon_count <= (main_sdram_bankmachine0_trascon_count - 1'd1);
if ((main_sdram_bankmachine0_trascon_count == 1'd1)) begin
main_sdram_bankmachine0_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine0_state <= builder_bankmachine0_next_state;
if (main_sdram_bankmachine1_row_close) begin
main_sdram_bankmachine1_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine1_row_open) begin
main_sdram_bankmachine1_row_opened <= 1'd1;
main_sdram_bankmachine1_row <= main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_level <= (main_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_level <= (main_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~main_sdram_bankmachine1_cmd_buffer_source_valid) | main_sdram_bankmachine1_cmd_buffer_source_ready)) begin
main_sdram_bankmachine1_cmd_buffer_source_valid <= main_sdram_bankmachine1_cmd_buffer_sink_valid;
main_sdram_bankmachine1_cmd_buffer_source_first <= main_sdram_bankmachine1_cmd_buffer_sink_first;
main_sdram_bankmachine1_cmd_buffer_source_last <= main_sdram_bankmachine1_cmd_buffer_sink_last;
main_sdram_bankmachine1_cmd_buffer_source_payload_we <= main_sdram_bankmachine1_cmd_buffer_sink_payload_we;
main_sdram_bankmachine1_cmd_buffer_source_payload_addr <= main_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine1_twtpcon_valid) begin
main_sdram_bankmachine1_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine1_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine1_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine1_twtpcon_ready)) begin
main_sdram_bankmachine1_twtpcon_count <= (main_sdram_bankmachine1_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine1_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine1_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine1_trccon_valid) begin
main_sdram_bankmachine1_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine1_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine1_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine1_trccon_ready)) begin
main_sdram_bankmachine1_trccon_count <= (main_sdram_bankmachine1_trccon_count - 1'd1);
if ((main_sdram_bankmachine1_trccon_count == 1'd1)) begin
main_sdram_bankmachine1_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine1_trascon_valid) begin
main_sdram_bankmachine1_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine1_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine1_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine1_trascon_ready)) begin
main_sdram_bankmachine1_trascon_count <= (main_sdram_bankmachine1_trascon_count - 1'd1);
if ((main_sdram_bankmachine1_trascon_count == 1'd1)) begin
main_sdram_bankmachine1_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine1_state <= builder_bankmachine1_next_state;
if (main_sdram_bankmachine2_row_close) begin
main_sdram_bankmachine2_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine2_row_open) begin
main_sdram_bankmachine2_row_opened <= 1'd1;
main_sdram_bankmachine2_row <= main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_level <= (main_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_level <= (main_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~main_sdram_bankmachine2_cmd_buffer_source_valid) | main_sdram_bankmachine2_cmd_buffer_source_ready)) begin
main_sdram_bankmachine2_cmd_buffer_source_valid <= main_sdram_bankmachine2_cmd_buffer_sink_valid;
main_sdram_bankmachine2_cmd_buffer_source_first <= main_sdram_bankmachine2_cmd_buffer_sink_first;
main_sdram_bankmachine2_cmd_buffer_source_last <= main_sdram_bankmachine2_cmd_buffer_sink_last;
main_sdram_bankmachine2_cmd_buffer_source_payload_we <= main_sdram_bankmachine2_cmd_buffer_sink_payload_we;
main_sdram_bankmachine2_cmd_buffer_source_payload_addr <= main_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine2_twtpcon_valid) begin
main_sdram_bankmachine2_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine2_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine2_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine2_twtpcon_ready)) begin
main_sdram_bankmachine2_twtpcon_count <= (main_sdram_bankmachine2_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine2_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine2_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine2_trccon_valid) begin
main_sdram_bankmachine2_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine2_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine2_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine2_trccon_ready)) begin
main_sdram_bankmachine2_trccon_count <= (main_sdram_bankmachine2_trccon_count - 1'd1);
if ((main_sdram_bankmachine2_trccon_count == 1'd1)) begin
main_sdram_bankmachine2_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine2_trascon_valid) begin
main_sdram_bankmachine2_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine2_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine2_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine2_trascon_ready)) begin
main_sdram_bankmachine2_trascon_count <= (main_sdram_bankmachine2_trascon_count - 1'd1);
if ((main_sdram_bankmachine2_trascon_count == 1'd1)) begin
main_sdram_bankmachine2_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine2_state <= builder_bankmachine2_next_state;
if (main_sdram_bankmachine3_row_close) begin
main_sdram_bankmachine3_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine3_row_open) begin
main_sdram_bankmachine3_row_opened <= 1'd1;
main_sdram_bankmachine3_row <= main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_level <= (main_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_level <= (main_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~main_sdram_bankmachine3_cmd_buffer_source_valid) | main_sdram_bankmachine3_cmd_buffer_source_ready)) begin
main_sdram_bankmachine3_cmd_buffer_source_valid <= main_sdram_bankmachine3_cmd_buffer_sink_valid;
main_sdram_bankmachine3_cmd_buffer_source_first <= main_sdram_bankmachine3_cmd_buffer_sink_first;
main_sdram_bankmachine3_cmd_buffer_source_last <= main_sdram_bankmachine3_cmd_buffer_sink_last;
main_sdram_bankmachine3_cmd_buffer_source_payload_we <= main_sdram_bankmachine3_cmd_buffer_sink_payload_we;
main_sdram_bankmachine3_cmd_buffer_source_payload_addr <= main_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine3_twtpcon_valid) begin
main_sdram_bankmachine3_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine3_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine3_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine3_twtpcon_ready)) begin
main_sdram_bankmachine3_twtpcon_count <= (main_sdram_bankmachine3_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine3_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine3_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine3_trccon_valid) begin
main_sdram_bankmachine3_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine3_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine3_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine3_trccon_ready)) begin
main_sdram_bankmachine3_trccon_count <= (main_sdram_bankmachine3_trccon_count - 1'd1);
if ((main_sdram_bankmachine3_trccon_count == 1'd1)) begin
main_sdram_bankmachine3_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine3_trascon_valid) begin
main_sdram_bankmachine3_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine3_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine3_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine3_trascon_ready)) begin
main_sdram_bankmachine3_trascon_count <= (main_sdram_bankmachine3_trascon_count - 1'd1);
if ((main_sdram_bankmachine3_trascon_count == 1'd1)) begin
main_sdram_bankmachine3_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine3_state <= builder_bankmachine3_next_state;
if (main_sdram_bankmachine4_row_close) begin
main_sdram_bankmachine4_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine4_row_open) begin
main_sdram_bankmachine4_row_opened <= 1'd1;
main_sdram_bankmachine4_row <= main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_level <= (main_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_level <= (main_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~main_sdram_bankmachine4_cmd_buffer_source_valid) | main_sdram_bankmachine4_cmd_buffer_source_ready)) begin
main_sdram_bankmachine4_cmd_buffer_source_valid <= main_sdram_bankmachine4_cmd_buffer_sink_valid;
main_sdram_bankmachine4_cmd_buffer_source_first <= main_sdram_bankmachine4_cmd_buffer_sink_first;
main_sdram_bankmachine4_cmd_buffer_source_last <= main_sdram_bankmachine4_cmd_buffer_sink_last;
main_sdram_bankmachine4_cmd_buffer_source_payload_we <= main_sdram_bankmachine4_cmd_buffer_sink_payload_we;
main_sdram_bankmachine4_cmd_buffer_source_payload_addr <= main_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine4_twtpcon_valid) begin
main_sdram_bankmachine4_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine4_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine4_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine4_twtpcon_ready)) begin
main_sdram_bankmachine4_twtpcon_count <= (main_sdram_bankmachine4_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine4_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine4_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine4_trccon_valid) begin
main_sdram_bankmachine4_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine4_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine4_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine4_trccon_ready)) begin
main_sdram_bankmachine4_trccon_count <= (main_sdram_bankmachine4_trccon_count - 1'd1);
if ((main_sdram_bankmachine4_trccon_count == 1'd1)) begin
main_sdram_bankmachine4_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine4_trascon_valid) begin
main_sdram_bankmachine4_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine4_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine4_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine4_trascon_ready)) begin
main_sdram_bankmachine4_trascon_count <= (main_sdram_bankmachine4_trascon_count - 1'd1);
if ((main_sdram_bankmachine4_trascon_count == 1'd1)) begin
main_sdram_bankmachine4_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine4_state <= builder_bankmachine4_next_state;
if (main_sdram_bankmachine5_row_close) begin
main_sdram_bankmachine5_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine5_row_open) begin
main_sdram_bankmachine5_row_opened <= 1'd1;
main_sdram_bankmachine5_row <= main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_level <= (main_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_level <= (main_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~main_sdram_bankmachine5_cmd_buffer_source_valid) | main_sdram_bankmachine5_cmd_buffer_source_ready)) begin
main_sdram_bankmachine5_cmd_buffer_source_valid <= main_sdram_bankmachine5_cmd_buffer_sink_valid;
main_sdram_bankmachine5_cmd_buffer_source_first <= main_sdram_bankmachine5_cmd_buffer_sink_first;
main_sdram_bankmachine5_cmd_buffer_source_last <= main_sdram_bankmachine5_cmd_buffer_sink_last;
main_sdram_bankmachine5_cmd_buffer_source_payload_we <= main_sdram_bankmachine5_cmd_buffer_sink_payload_we;
main_sdram_bankmachine5_cmd_buffer_source_payload_addr <= main_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine5_twtpcon_valid) begin
main_sdram_bankmachine5_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine5_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine5_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine5_twtpcon_ready)) begin
main_sdram_bankmachine5_twtpcon_count <= (main_sdram_bankmachine5_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine5_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine5_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine5_trccon_valid) begin
main_sdram_bankmachine5_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine5_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine5_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine5_trccon_ready)) begin
main_sdram_bankmachine5_trccon_count <= (main_sdram_bankmachine5_trccon_count - 1'd1);
if ((main_sdram_bankmachine5_trccon_count == 1'd1)) begin
main_sdram_bankmachine5_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine5_trascon_valid) begin
main_sdram_bankmachine5_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine5_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine5_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine5_trascon_ready)) begin
main_sdram_bankmachine5_trascon_count <= (main_sdram_bankmachine5_trascon_count - 1'd1);
if ((main_sdram_bankmachine5_trascon_count == 1'd1)) begin
main_sdram_bankmachine5_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine5_state <= builder_bankmachine5_next_state;
if (main_sdram_bankmachine6_row_close) begin
main_sdram_bankmachine6_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine6_row_open) begin
main_sdram_bankmachine6_row_opened <= 1'd1;
main_sdram_bankmachine6_row <= main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_level <= (main_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_level <= (main_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~main_sdram_bankmachine6_cmd_buffer_source_valid) | main_sdram_bankmachine6_cmd_buffer_source_ready)) begin
main_sdram_bankmachine6_cmd_buffer_source_valid <= main_sdram_bankmachine6_cmd_buffer_sink_valid;
main_sdram_bankmachine6_cmd_buffer_source_first <= main_sdram_bankmachine6_cmd_buffer_sink_first;
main_sdram_bankmachine6_cmd_buffer_source_last <= main_sdram_bankmachine6_cmd_buffer_sink_last;
main_sdram_bankmachine6_cmd_buffer_source_payload_we <= main_sdram_bankmachine6_cmd_buffer_sink_payload_we;
main_sdram_bankmachine6_cmd_buffer_source_payload_addr <= main_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine6_twtpcon_valid) begin
main_sdram_bankmachine6_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine6_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine6_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine6_twtpcon_ready)) begin
main_sdram_bankmachine6_twtpcon_count <= (main_sdram_bankmachine6_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine6_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine6_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine6_trccon_valid) begin
main_sdram_bankmachine6_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine6_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine6_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine6_trccon_ready)) begin
main_sdram_bankmachine6_trccon_count <= (main_sdram_bankmachine6_trccon_count - 1'd1);
if ((main_sdram_bankmachine6_trccon_count == 1'd1)) begin
main_sdram_bankmachine6_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine6_trascon_valid) begin
main_sdram_bankmachine6_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine6_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine6_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine6_trascon_ready)) begin
main_sdram_bankmachine6_trascon_count <= (main_sdram_bankmachine6_trascon_count - 1'd1);
if ((main_sdram_bankmachine6_trascon_count == 1'd1)) begin
main_sdram_bankmachine6_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine6_state <= builder_bankmachine6_next_state;
if (main_sdram_bankmachine7_row_close) begin
main_sdram_bankmachine7_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine7_row_open) begin
main_sdram_bankmachine7_row_opened <= 1'd1;
main_sdram_bankmachine7_row <= main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_level <= (main_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_level <= (main_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~main_sdram_bankmachine7_cmd_buffer_source_valid) | main_sdram_bankmachine7_cmd_buffer_source_ready)) begin
main_sdram_bankmachine7_cmd_buffer_source_valid <= main_sdram_bankmachine7_cmd_buffer_sink_valid;
main_sdram_bankmachine7_cmd_buffer_source_first <= main_sdram_bankmachine7_cmd_buffer_sink_first;
main_sdram_bankmachine7_cmd_buffer_source_last <= main_sdram_bankmachine7_cmd_buffer_sink_last;
main_sdram_bankmachine7_cmd_buffer_source_payload_we <= main_sdram_bankmachine7_cmd_buffer_sink_payload_we;
main_sdram_bankmachine7_cmd_buffer_source_payload_addr <= main_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine7_twtpcon_valid) begin
main_sdram_bankmachine7_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine7_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine7_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine7_twtpcon_ready)) begin
main_sdram_bankmachine7_twtpcon_count <= (main_sdram_bankmachine7_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine7_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine7_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine7_trccon_valid) begin
main_sdram_bankmachine7_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine7_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine7_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine7_trccon_ready)) begin
main_sdram_bankmachine7_trccon_count <= (main_sdram_bankmachine7_trccon_count - 1'd1);
if ((main_sdram_bankmachine7_trccon_count == 1'd1)) begin
main_sdram_bankmachine7_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine7_trascon_valid) begin
main_sdram_bankmachine7_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine7_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine7_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine7_trascon_ready)) begin
main_sdram_bankmachine7_trascon_count <= (main_sdram_bankmachine7_trascon_count - 1'd1);
if ((main_sdram_bankmachine7_trascon_count == 1'd1)) begin
main_sdram_bankmachine7_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine7_state <= builder_bankmachine7_next_state;
if ((~main_sdram_en0)) begin
main_sdram_time0 <= 5'd31;
end else begin
if ((~main_sdram_max_time0)) begin
main_sdram_time0 <= (main_sdram_time0 - 1'd1);
end
end
if ((~main_sdram_en1)) begin
main_sdram_time1 <= 4'd15;
end else begin
if ((~main_sdram_max_time1)) begin
main_sdram_time1 <= (main_sdram_time1 - 1'd1);
end
end
if (main_sdram_choose_cmd_ce) begin
case (main_sdram_choose_cmd_grant)
1'd0: begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end
end
end
end
end
end
end
end
1'd1: begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end
end
end
end
end
end
end
end
2'd2: begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end
end
end
end
end
end
end
end
2'd3: begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end
end
end
end
end
end
end
end
3'd4: begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end
end
end
end
end
end
end
end
3'd5: begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end
end
end
end
end
end
end
end
3'd6: begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end
end
end
end
end
end
end
end
3'd7: begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end
end
end
end
end
end
end
end
endcase
end
if (main_sdram_choose_req_ce) begin
case (main_sdram_choose_req_grant)
1'd0: begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end
end
end
end
end
end
end
end
1'd1: begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end
end
end
end
end
end
end
end
2'd2: begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end
end
end
end
end
end
end
end
2'd3: begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end
end
end
end
end
end
end
end
3'd4: begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end
end
end
end
end
end
end
end
3'd5: begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end
end
end
end
end
end
end
end
3'd6: begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end
end
end
end
end
end
end
end
3'd7: begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end
end
end
end
end
end
end
end
endcase
end
main_sdram_dfi_p0_cs_n <= 1'd0;
main_sdram_dfi_p0_bank <= builder_array_muxed0;
main_sdram_dfi_p0_address <= builder_array_muxed1;
main_sdram_dfi_p0_cas_n <= (~builder_array_muxed2);
main_sdram_dfi_p0_ras_n <= (~builder_array_muxed3);
main_sdram_dfi_p0_we_n <= (~builder_array_muxed4);
main_sdram_dfi_p0_rddata_en <= builder_array_muxed5;
main_sdram_dfi_p0_wrdata_en <= builder_array_muxed6;
main_sdram_dfi_p1_cs_n <= 1'd0;
main_sdram_dfi_p1_bank <= builder_array_muxed7;
main_sdram_dfi_p1_address <= builder_array_muxed8;
main_sdram_dfi_p1_cas_n <= (~builder_array_muxed9);
main_sdram_dfi_p1_ras_n <= (~builder_array_muxed10);
main_sdram_dfi_p1_we_n <= (~builder_array_muxed11);
main_sdram_dfi_p1_rddata_en <= builder_array_muxed12;
main_sdram_dfi_p1_wrdata_en <= builder_array_muxed13;
main_sdram_dfi_p2_cs_n <= 1'd0;
main_sdram_dfi_p2_bank <= builder_array_muxed14;
main_sdram_dfi_p2_address <= builder_array_muxed15;
main_sdram_dfi_p2_cas_n <= (~builder_array_muxed16);
main_sdram_dfi_p2_ras_n <= (~builder_array_muxed17);
main_sdram_dfi_p2_we_n <= (~builder_array_muxed18);
main_sdram_dfi_p2_rddata_en <= builder_array_muxed19;
main_sdram_dfi_p2_wrdata_en <= builder_array_muxed20;
main_sdram_dfi_p3_cs_n <= 1'd0;
main_sdram_dfi_p3_bank <= builder_array_muxed21;
main_sdram_dfi_p3_address <= builder_array_muxed22;
main_sdram_dfi_p3_cas_n <= (~builder_array_muxed23);
main_sdram_dfi_p3_ras_n <= (~builder_array_muxed24);
main_sdram_dfi_p3_we_n <= (~builder_array_muxed25);
main_sdram_dfi_p3_rddata_en <= builder_array_muxed26;
main_sdram_dfi_p3_wrdata_en <= builder_array_muxed27;
if (main_sdram_trrdcon_valid) begin
main_sdram_trrdcon_count <= 1'd1;
if (1'd0) begin
main_sdram_trrdcon_ready <= 1'd1;
end else begin
main_sdram_trrdcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_trrdcon_ready)) begin
main_sdram_trrdcon_count <= (main_sdram_trrdcon_count - 1'd1);
if ((main_sdram_trrdcon_count == 1'd1)) begin
main_sdram_trrdcon_ready <= 1'd1;
end
end
end
main_sdram_tfawcon_window <= {main_sdram_tfawcon_window, main_sdram_tfawcon_valid};
if ((main_sdram_tfawcon_count < 3'd4)) begin
if ((main_sdram_tfawcon_count == 2'd3)) begin
main_sdram_tfawcon_ready <= (~main_sdram_tfawcon_valid);
end else begin
main_sdram_tfawcon_ready <= 1'd1;
end
end
if (main_sdram_tccdcon_valid) begin
main_sdram_tccdcon_count <= 1'd0;
if (1'd1) begin
main_sdram_tccdcon_ready <= 1'd1;
end else begin
main_sdram_tccdcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_tccdcon_ready)) begin
main_sdram_tccdcon_count <= (main_sdram_tccdcon_count - 1'd1);
if ((main_sdram_tccdcon_count == 1'd1)) begin
main_sdram_tccdcon_ready <= 1'd1;
end
end
end
if (main_sdram_twtrcon_valid) begin
main_sdram_twtrcon_count <= 3'd4;
if (1'd0) begin
main_sdram_twtrcon_ready <= 1'd1;
end else begin
main_sdram_twtrcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_twtrcon_ready)) begin
main_sdram_twtrcon_count <= (main_sdram_twtrcon_count - 1'd1);
if ((main_sdram_twtrcon_count == 1'd1)) begin
main_sdram_twtrcon_ready <= 1'd1;
end
end
end
builder_multiplexer_state <= builder_multiplexer_next_state;
if (((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_rdata_valid)) begin
builder_rbank <= 1'd0;
end
if (((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_wdata_ready)) begin
builder_wbank <= 1'd0;
end
if (((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_rdata_valid)) begin
builder_rbank <= 1'd1;
end
if (((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_wdata_ready)) begin
builder_wbank <= 1'd1;
end
if (((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_rdata_valid)) begin
builder_rbank <= 2'd2;
end
if (((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_wdata_ready)) begin
builder_wbank <= 2'd2;
end
if (((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_rdata_valid)) begin
builder_rbank <= 2'd3;
end
if (((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_wdata_ready)) begin
builder_wbank <= 2'd3;
end
if (((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_rdata_valid)) begin
builder_rbank <= 3'd4;
end
if (((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_wdata_ready)) begin
builder_wbank <= 3'd4;
end
if (((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_rdata_valid)) begin
builder_rbank <= 3'd5;
end
if (((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_wdata_ready)) begin
builder_wbank <= 3'd5;
end
if (((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_rdata_valid)) begin
builder_rbank <= 3'd6;
end
if (((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_wdata_ready)) begin
builder_wbank <= 3'd6;
end
if (((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_rdata_valid)) begin
builder_rbank <= 3'd7;
end
if (((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_wdata_ready)) begin
builder_wbank <= 3'd7;
end
builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_wdata_ready));
builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
builder_new_master_wdata_ready2 <= builder_new_master_wdata_ready1;
builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_rdata_valid));
builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
builder_new_master_rdata_valid9 <= builder_new_master_rdata_valid8;
main_adr_offset_r <= main_interface0_wb_sdram_adr[1:0];
builder_fullmemorywe_state <= builder_fullmemorywe_next_state;
builder_litedramwishbone2native_state <= builder_litedramwishbone2native_next_state;
if (main_count_next_value_ce) begin
main_count <= main_count_next_value;
end
case (builder_minsoc_grant)
1'd0: begin
if ((~builder_minsoc_request[0])) begin
if (builder_minsoc_request[1]) begin
builder_minsoc_grant <= 1'd1;
end
end
end
1'd1: begin
if ((~builder_minsoc_request[1])) begin
if (builder_minsoc_request[0]) begin
builder_minsoc_grant <= 1'd0;
end
end
end
endcase
builder_minsoc_slave_sel_r <= builder_minsoc_slave_sel;
if (builder_minsoc_wait) begin
if ((~builder_minsoc_done)) begin
builder_minsoc_count <= (builder_minsoc_count - 1'd1);
end
end else begin
builder_minsoc_count <= 20'd1000000;
end
builder_minsoc_interface0_bank_bus_dat_r <= 1'd0;
if (builder_minsoc_csrbank0_sel) begin
case (builder_minsoc_interface0_bank_bus_adr[3:0])
1'd0: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_reset0_w;
end
1'd1: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch3_w;
end
2'd2: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch2_w;
end
2'd3: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch1_w;
end
3'd4: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch0_w;
end
3'd5: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors3_w;
end
3'd6: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors2_w;
end
3'd7: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors1_w;
end
4'd8: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors0_w;
end
endcase
end
if (builder_minsoc_csrbank0_reset0_re) begin
main_minsoc_ctrl_reset_storage <= builder_minsoc_csrbank0_reset0_r;
end
main_minsoc_ctrl_reset_re <= builder_minsoc_csrbank0_reset0_re;
if (builder_minsoc_csrbank0_scratch3_re) begin
main_minsoc_ctrl_scratch_storage[31:24] <= builder_minsoc_csrbank0_scratch3_r;
end
if (builder_minsoc_csrbank0_scratch2_re) begin
main_minsoc_ctrl_scratch_storage[23:16] <= builder_minsoc_csrbank0_scratch2_r;
end
if (builder_minsoc_csrbank0_scratch1_re) begin
main_minsoc_ctrl_scratch_storage[15:8] <= builder_minsoc_csrbank0_scratch1_r;
end
if (builder_minsoc_csrbank0_scratch0_re) begin
main_minsoc_ctrl_scratch_storage[7:0] <= builder_minsoc_csrbank0_scratch0_r;
end
main_minsoc_ctrl_scratch_re <= builder_minsoc_csrbank0_scratch0_re;
builder_minsoc_interface1_bank_bus_dat_r <= 1'd0;
if (builder_minsoc_csrbank1_sel) begin
case (builder_minsoc_interface1_bank_bus_adr[2:0])
1'd0: begin
builder_minsoc_interface1_bank_bus_dat_r <= builder_minsoc_csrbank1_half_sys8x_taps0_w;
end
1'd1: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7d"b'drphy_cdly_rst_w;
end
2\'d2: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_cdly_inc_w;
end
2\'d3: begin
builder_minsoc_interface1_bank_bus_dat_r <= builder_minsoc_csrbank1_dly_sel0_w;
end
3\'d4: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
end
3\'d5: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
end
3\'d6: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
end
3\'d7: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
end
endcase
end
if (builder_minsoc_csrbank1_half_sys8x_taps0_re) begin
main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_minsoc_csrbank1_half_sys8x_taps0_r;
end
main_a7ddrphy_half_sys8x_taps_re <= builder_minsoc_csrbank1_half_sys8x_taps0_re;
if (builder_minsoc_csrbank1_dly_sel0_re) begin
main_a7ddrphy_dly_sel_storage[1:0] <= builder_minsoc_csrbank1_dly_sel0_r;
end
main_a7ddrphy_dly_sel_re <= builder_minsoc_csrbank1_dly_sel0_re;
builder_minsoc_interface2_bank_bus_dat_r <= 1\'d0;
if (builder_minsoc_csrbank2_sel) begin
case (builder_minsoc_interface2_bank_bus_adr[5:0])
1\'d0: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_control0_w;
end
1\'d1: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_command0_w;
end
2\'d2: begin
builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector0_command_issue_w;
end
2\'d3: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_address1_w;
end
3\'d4: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_address0_w;
end
3\'d5: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_baddress0_w;
end
3\'d6: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata3_w;
end
3\'d7: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata2_w;
end
4\'d8: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata1_w;
end
4\'d9: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata0_w;
end
4\'d10: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata3_w;
end
4\'d11: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata2_w;
end
4\'d12: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata1_w;
end
4\'d13: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata0_w;
end
4\'d14: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_command0_w;
end
4\'d15: begin
builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector1_command_issue_w;
end
5\'d16: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_address1_w;
end
5\'d17: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_address0_w;
end
5\'d18: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_baddress0_w;
end
5\'d19: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata3_w;
end
5\'d20: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata2_w;
end
5\'d21: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata1_w;
end
5\'d22: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata0_w;
end
5\'d23: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata3_w;
end
5\'d24: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata2_w;
end
5\'d25: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata1_w;
end
5\'d26: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata0_w;
end
5\'d27: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_command0_w;
end
5\'d28: begin
builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector2_command_issue_w;
end
5\'d29: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_address1_w;
end
5\'d30: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_address0_w;
end
5\'d31: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_baddress0_w;
end
6\'d32: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata3_w;
end
6\'d33: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata2_w;
end
6\'d34: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata1_w;
end
6\'d35: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata0_w;
end
6\'d36: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata3_w;
end
6\'d37: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata2_w;
end
6\'d38: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata1_w;
end
6\'d39: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata0_w;
end
6\'d40: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_command0_w;
end
6\'d41: begin
builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector3_command_issue_w;
end
6\'d42: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_address1_w;
end
6\'d43: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_address0_w;
end
6\'d44: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_baddress0_w;
end
6\'d45: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata3_w;
end
6\'d46: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata2_w;
end
6\'d47: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata1_w;
end
6\'d48: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata0_w;
end
6\'d49: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata3_w;
end
6\'d50: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata2_w;
end
6\'d51: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata1_w;
end
6\'d52: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata0_w;
end
endcase
end
if (builder_minsoc_csrbank2_dfii_control0_re) begin
main_sdram_storage[3:0] <= builder_minsoc_csrbank2_dfii_control0_r;
end
main_sdram_re <= builder_minsoc_csrbank2_dfii_control0_re;
if (builder_minsoc_csrbank2_dfii_pi0_command0_re) begin
main_sdram_phaseinjector0_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi0_command0_r;
end
main_sdram_phaseinjector0_command_re <= builder_minsoc_csrbank2_dfii_pi0_command0_re;
if (builder_minsoc_csrbank2_dfii_pi0_address1_re) begin
main_sdram_phaseinjector0_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi0_address1_r;
end
if (builder_minsoc_csrbank2_dfii_pi0_address0_re) begin
main_sdram_phaseinjector0_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi0_address0_r;
end
main_sdram_phaseinjector0_address_re <= builder_minsoc_csrbank2_dfii_pi0_address0_re;
if (builder_minsoc_csrbank2_dfii_pi0_baddress0_re) begin
main_sdram_phaseinjector0_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi0_baddress0_r;
end
main_sdram_phaseinjector0_baddress_re <= builder_minsoc_csrbank2_dfii_pi0_baddress0_re;
if (builder_minsoc_csrbank2_dfii_pi0_wrdata3_re) begin
main_sdram_phaseinjector0_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi0_wrdata3_r;
end
if (builder_minsoc_csrbank2_dfii_pi0_wrdata2_re) begin
main_sdram_phaseinjector0_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi0_wrdata2_r;
end
if (builder_minsoc_csrbank2_dfii_pi0_wrdata1_re) begin
main_sdram_phaseinjector0_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi0_wrdata1_r;
end
if (builder_minsoc_csrbank2_dfii_pi0_wrdata0_re) begin
main_sdram_phaseinjector0_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi0_wrdata0_r;
end
main_sdram_phaseinjector0_wrdata_re <= builder_minsoc_csrbank2_dfii_pi0_wrdata0_re;
if (builder_minsoc_csrbank2_dfii_pi1_command0_re) begin
main_sdram_phaseinjector1_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi1_command0_r;
end
main_sdram_phaseinjector1_command_re <= builder_minsoc_csrbank2_dfii_pi1_command0_re;
if (builder_minsoc_csrbank2_dfii_pi1_address1_re) begin
main_sdram_phaseinjector1_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi1_address1_r;
end
if (builder_minsoc_csrbank2_dfii_pi1_address0_re) begin
main_sdram_phaseinjector1_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi1_address0_r;
end
main_sdram_phaseinjector1_address_re <= builder_minsoc_csrbank2_dfii_pi1_address0_re;
if (builder_minsoc_csrbank2_dfii_pi1_baddress0_re) begin
main_sdram_phaseinjector1_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi1_baddress0_r;
end
main_sdram_phaseinjector1_baddress_re <= builder_minsoc_csrbank2_dfii_pi1_baddress0_re;
if (builder_minsoc_csrbank2_dfii_pi1_wrdata3_re) begin
main_sdram_phaseinjector1_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi1_wrdata3_r;
end
if (builder_minsoc_csrbank2_dfii_pi1_wrdata2_re) begin
main_sdram_phaseinjector1_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi1_wrdata2_r;
end
if (builder_minsoc_csrbank2_dfii_pi1_wrdata1_re) begin
main_sdram_phaseinjector1_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi1_wrdata1_r;
end
if (builder_minsoc_csrbank2_dfii_pi1_wrdata0_re) begin
main_sdram_phaseinjector1_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi1_wrdata0_r;
end
main_sdram_phaseinjector1_wrdata_re <= builder_minsoc_csrbank2_dfii_pi1_wrdata0_re;
if (builder_minsoc_csrbank2_dfii_pi2_command0_re) begin
main_sdram_phaseinjector2_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi2_command0_r;
end
main_sdram_phaseinjector2_command_re <= builder_minsoc_csrbank2_dfii_pi2_command0_re;
if (builder_minsoc_csrbank2_dfii_pi2_address1_re) begin
main_sdram_phaseinjector2_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi2_address1_r;
end
if (builder_minsoc_csrbank2_dfii_pi2_address0_re) begin
main_sdram_phaseinjector2_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi2_address0_r;
end
main_sdram_phaseinjector2_address_re <= builder_minsoc_csrbank2_dfii_pi2_address0_re;
if (builder_minsoc_csrbank2_dfii_pi2_baddress0_re) begin
main_sdram_phaseinjector2_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi2_baddress0_r;
end
main_sdram_phaseinjector2_baddress_re <= builder_minsoc_csrbank2_dfii_pi2_baddress0_re;
if (builder_minsoc_csrbank2_dfii_pi2_wrdata3_re) begin
main_sdram_phaseinjector2_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi2_wrdata3_r;
end
if (builder_minsoc_csrbank2_dfii_pi2_wrdata2_re) begin
main_sdram_phaseinjector2_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi2_wrdata2_r;
end
if (builder_minsoc_csrbank2_dfii_pi2_wrdata1_re) begin
main_sdram_phaseinjector2_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi2_wrdata1_r;
end
if (builder_minsoc_csrbank2_dfii_pi2_wrdata0_re) begin
main_sdram_phaseinjector2_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi2_wrdata0_r;
end
main_sdram_phaseinjector2_wrdata_re <= builder_minsoc_csrbank2_dfii_pi2_wrdata0_re;
if (builder_minsoc_csrbank2_dfii_pi3_command0_re) begin
main_sdram_phaseinjector3_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi3_command0_r;
end
main_sdram_phaseinjector3_command_re <= builder_minsoc_csrbank2_dfii_pi3_command0_re;
if (builder_minsoc_csrbank2_dfii_pi3_address1_re) begin
main_sdram_phaseinjector3_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi3_address1_r;
end
if (builder_minsoc_csrbank2_dfii_pi3_address0_re) begin
main_sdram_phaseinjector3_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi3_address0_r;
end
main_sdram_phaseinjector3_address_re <= builder_minsoc_csrbank2_dfii_pi3_address0_re;
if (builder_minsoc_csrbank2_dfii_pi3_baddress0_re) begin
main_sdram_phaseinjector3_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi3_baddress0_r;
end
main_sdram_phaseinjector3_baddress_re <= builder_minsoc_csrbank2_dfii_pi3_baddress0_re;
if (builder_minsoc_csrbank2_dfii_pi3_wrdata3_re) begin
main_sdram_phaseinjector3_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi3_wrdata3_r;
end
if (builder_minsoc_csrbank2_dfii_pi3_wrdata2_re) begin
main_sdram_phaseinjector3_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi3_wrdata2_r;
end
if (builder_minsoc_csrbank2_dfii_pi3_wrdata1_re) begin
main_sdram_phaseinjector3_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi3_wrdata1_r;
end
if (builder_minsoc_csrbank2_dfii_pi3_wrdata0_re) begin
main_sdram_phaseinjector3_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi3_wrdata0_r;
end
main_sdram_phaseinjector3_wrdata_re <= builder_minsoc_csrbank2_dfii_pi3_wrdata0_re;
builder_minsoc_interface3_bank_bus_dat_r <= 1\'d0;
if (builder_minsoc_csrbank3_sel) begin
case (builder_minsoc_interface3_bank_bus_adr[4:0])
1\'d0: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load3_w;
end
1\'d1: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load2_w;
end
2\'d2: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load1_w;
end
2\'d3: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load0_w;
end
3\'d4: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload3_w;
end
3\'d5: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload2_w;
end
3\'d6: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload1_w;
end
3\'d7: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload0_w;
end
4\'d8: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_en0_w;
end
4\'d9: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_update_value0_w;
end
4\'d10: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value3_w;
end
4\'d11: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value2_w;
end
4\'d12: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value1_w;
end
4\'d13: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value0_w;
end
4\'d14: begin
builder_minsoc_interface3_bank_bus_dat_r <= main_minsoc_timer0_eventmanager_status_w;
end
4\'d15: begin
builder_minsoc_interface3_bank_bus_dat_r <= main_minsoc_timer0_eventmanager_pending_w;
end
5\'d16: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_ev_enable0_w;
end
endcase
end
if (builder_minsoc_csrbank3_load3_re) begin
main_minsoc_timer0_load_storage[31:24] <= builder_minsoc_csrbank3_load3_r;
end
if (builder_minsoc_csrbank3_load2_re) begin
main_minsoc_timer0_load_storage[23:16] <= builder_minsoc_csrbank3_load2_r;
end
if (builder_minsoc_csrbank3_load1_re) begin
main_minsoc_timer0_load_storage[15:8] <= builder_minsoc_csrbank3_load1_r;
end
if (builder_minsoc_csrbank3_load0_re) begin
main_minsoc_timer0_load_storage[7:0] <= builder_minsoc_csrbank3_load0_r;
end
main_minsoc_timer0_load_re <= builder_minsoc_csrbank3_load0_re;
if (builder_minsoc_csrbank3_reload3_re) begin
main_minsoc_timer0_reload_storage[31:24] <= builder_minsoc_csrbank3_reload3_r;
end
if (builder_minsoc_csrbank3_reload2_re) begin
main_minsoc_timer0_reload_storage[23:16] <= builder_minsoc_csrbank3_reload2_r;
end
if (builder_minsoc_csrbank3_reload1_re) begin
main_minsoc_timer0_reload_storage[15:8] <= builder_minsoc_csrbank3_reload1_r;
end
if (builder_minsoc_csrbank3_reload0_re) begin
main_minsoc_timer0_reload_storage[7:0] <= builder_minsoc_csrbank3_reload0_r;
end
main_minsoc_timer0_reload_re <= builder_minsoc_csrbank3_reload0_re;
if (builder_minsoc_csrbank3_en0_re) begin
main_minsoc_timer0_en_storage <= builder_minsoc_csrbank3_en0_r;
end
main_minsoc_timer0_en_re <= builder_minsoc_csrbank3_en0_re;
if (builder_minsoc_csrbank3_update_value0_re) begin
main_minsoc_timer0_update_value_storage <= builder_minsoc_csrbank3_update_value0_r;
end
main_minsoc_timer0_update_value_re <= builder_minsoc_csrbank3_update_value0_re;
if (builder_minsoc_csrbank3_ev_enable0_re) begin
main_minsoc_timer0_eventmanager_storage <= builder_minsoc_csrbank3_ev_enable0_r;
end
main_minsoc_timer0_eventmanager_re <= builder_minsoc_csrbank3_ev_enable0_re;
builder_minsoc_interface4_bank_bus_dat_r <= 1\'d0;
if (builder_minsoc_csrbank4_sel) begin
case (builder_minsoc_interface4_bank_bus_adr[2:0])
1\'d0: begin
builder_minsoc_interface4_bank_bus_dat_r <= main_minsoc_uart_rxtx_w;
end
1\'d1: begin
builder_minsoc_interface4_bank_bus_dat_r <= builder_minsoc_csrbank4_txfull_w;
end
2\'d2: begin
builder_minsoc_interface4_bank_bus_dat_r <= builder_minsoc_csrbank4_rxempty_w;
end
2\'d3: begin
builder_minsoc_interface4_bank_bus_dat_r <= main_minsoc_uart_eventmanager_status_w;
end
3\'d4: begin
builder_minsoc_interface4_bank_bus_dat_r <= main_minsoc_uart_eventmanager_pending_w;
end
3\'d5: begin
builder_minsoc_interface4_bank_bus_dat_r <= builder_minsoc_csrbank4_ev_enable0_w;
end
endcase
end
if (builder_minsoc_csrbank4_ev_enable0_re) begin
main_minsoc_uart_eventmanager_storage[1:0] <= builder_minsoc_csrbank4_ev_enable0_r;
end
main_minsoc_uart_eventmanager_re <= builder_minsoc_csrbank4_ev_enable0_re;
builder_minsoc_interface5_bank_bus_dat_r <= 1\'d0;
if (builder_minsoc_csrbank5_sel) begin
case (builder_minsoc_interface5_bank_bus_adr[1:0])
1\'d0: begin
builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word3_w;
end
1\'d1: begin
builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word2_w;
end
2\'d2: begin
builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word1_w;
end
2\'d3: begin
builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word0_w;
end
endcase
end
if (builder_minsoc_csrbank5_tuning_word3_re) begin
main_minsoc_storage[31:24] <= builder_minsoc_csrbank5_tuning_word3_r;
end
if (builder_minsoc_csrbank5_tuning_word2_re) begin
main_minsoc_storage[23:16] <= builder_minsoc_csrbank5_tuning_word2_r;
end
if (builder_minsoc_csrbank5_tuning_word1_re) begin
main_minsoc_storage[15:8] <= builder_minsoc_csrbank5_tuning_word1_r;
end
if (builder_minsoc_csrbank5_tuning_word0_re) begin
main_minsoc_storage[7:0] <= builder_minsoc_csrbank5_tuning_word0_r;
end
main_minsoc_re <= builder_minsoc_csrbank5_tuning_word0_re;
if (sys_rst) begin
main_minsoc_ctrl_reset_storage <= 1\'d0;
main_minsoc_ctrl_reset_re <= 1\'d0;
main_minsoc_ctrl_scratch_storage <= 32\'d305419896;
main_minsoc_ctrl_scratch_re <= 1\'d0;
main_minsoc_ctrl_bus_errors <= 32\'d0;
main_minsoc_rom_bus_ack <= 1\'d0;
main_minsoc_sram_bus_ack <= 1\'d0;
serial_tx <= 1\'d1;
main_minsoc_storage <= 32\'d8246337;
main_minsoc_re <= 1\'d0;
main_minsoc_sink_ready <= 1\'d0;
main_minsoc_uart_clk_txen <= 1\'d0;
main_minsoc_phase_accumulator_tx <= 32\'d0;
main_minsoc_tx_reg <= 8\'d0;
main_minsoc_tx_bitcount <= 4\'d0;
main_minsoc_tx_busy <= 1\'d0;
main_minsoc_source_valid <= 1\'d0;
main_minsoc_source_payload_data <= 8\'d0;
main_minsoc_uart_clk_rxen <= 1\'d0;
main_minsoc_phase_accumulator_rx <= 32\'d0;
main_minsoc_rx_r <= 1\'d0;
main_minsoc_rx_reg <= 8\'d0;
main_minsoc_rx_bitcount <= 4\'d0;
main_minsoc_rx_busy <= 1\'d0;
main_minsoc_uart_tx_pending <= 1\'d0;
main_minsoc_uart_tx_old_trigger <= 1\'d0;
main_minsoc_uart_rx_pending <= 1\'d0;
main_minsoc_uart_rx_old_trigger <= 1\'d0;
main_minsoc_uart_eventmanager_storage <= 2\'d0;
main_minsoc_uart_eventmanager_re <= 1\'d0;
main_minsoc_uart_tx_fifo_readable <= 1\'d0;
main_minsoc_uart_tx_fifo_level0 <= 5\'d0;
main_minsoc_uart_tx_fifo_produce <= 4\'d0;
main_minsoc_uart_tx_fifo_consume <= 4\'d0;
main_minsoc_uart_rx_fifo_readable <= 1\'d0;
main_minsoc_uart_rx_fifo_level0 <= 5\'d0;
main_minsoc_uart_rx_fifo_produce <= 4\'d0;
main_minsoc_uart_rx_fifo_consume <= 4\'d0;
main_minsoc_timer0_load_storage <= 32\'d0;
main_minsoc_timer0_load_re <= 1\'d0;
main_minsoc_timer0_reload_storage <= 32\'d0;
main_minsoc_timer0_reload_re <= 1\'d0;
main_minsoc_timer0_en_storage <= 1\'d0;
main_minsoc_timer0_en_re <= 1\'d0;
main_minsoc_timer0_update_value_storage <= 1\'d0;
main_minsoc_timer0_update_value_re <= 1\'d0;
main_minsoc_timer0_value_status <= 32\'d0;
main_minsoc_timer0_zero_pending <= 1\'d0;
main_minsoc_timer0_zero_old_trigger <= 1\'d0;
main_minsoc_timer0_eventmanager_storage <= 1\'d0;
main_minsoc_timer0_eventmanager_re <= 1\'d0;
main_minsoc_timer0_value <= 32\'d0;
main_a7ddrphy_half_sys8x_taps_storage <= 5\'d13;
main_a7ddrphy_half_sys8x_taps_re <= 1\'d0;
main_a7ddrphy_dly_sel_storage <= 2\'d0;
main_a7ddrphy_dly_sel_re <= 1\'d0;
main_a7ddrphy_dfi_p0_rddata_valid <= 1\'d0;
main_a7ddrphy_dfi_p1_rddata_valid <= 1\'d0;
main_a7ddrphy_dfi_p2_rddata_valid <= 1\'d0;
main_a7ddrphy_dfi_p3_rddata_valid <= 1\'d0;
main_a7ddrphy_oe_dqs <= 1\'d0;
main_a7ddrphy_oe_dq <= 1\'d0;
main_a7ddrphy_bitslip0_o <= 8\'d0;
main_a7ddrphy_bitslip0_value <= 3\'d0;
main_a7ddrphy_bitslip0_r <= 16\'d0;
main_a7ddrphy_bitslip1_o <= 8\'d0;
main_a7ddrphy_bitslip1_value <= 3\'d0;
main_a7ddrphy_bitslip1_r <= 16\'d0;
main_a7ddrphy_bitslip2_o <= 8\'d0;
main_a7ddrphy_bitslip2_value <= 3\'d0;
main_a7ddrphy_bitslip2_r <= 16\'d0;
main_a7ddrphy_bitslip3_o <= 8\'d0;
main_a7ddrphy_bitslip3_value <= 3\'d0;
main_a7ddrphy_bitslip3_r <= 16\'d0;
main_a7ddrphy_bitslip4_o <= 8\'d0;
main_a7ddrphy_bitslip4_value <= 3\'d0;
main_a7ddrphy_bitslip4_r <= 16\'d0;
main_a7ddrphy_bitslip5_o <= 8\'d0;
main_a7ddrphy_bitslip5_value <= 3\'d0;
main_a7ddrphy_bitslip5_r <= 16\'d0;
main_a7ddrphy_bitslip6_o <= 8\'d0;
main_a7ddrphy_bitslip6_value <= 3\'d0;
main_a7ddrphy_bitslip6_r <= 16\'d0;
main_a7ddrphy_bitslip7_o <= 8\'d0;
main_a7ddrphy_bitslip7_value <= 3\'d0;
main_a7ddrphy_bitslip7_r <= 16\'d0;
main_a7ddrphy_bitslip8_o <= 8\'d0;
main_a7ddrphy_bitslip8_value <= 3\'d0;
main_a7ddrphy_bitslip8_r <= 16\'d0;
main_a7ddrphy_bitslip9_o <= 8\'d0;
main_a7ddrphy_bitslip9_value <= 3\'d0;
main_a7ddrphy_bitslip9_r <= 16\'d0;
main_a7ddrphy_bitslip10_o <= 8\'d0;
main_a7ddrphy_bitslip10_value <= 3\'d0;
main_a7ddrphy_bitslip10_r <= 16\'d0;
main_a7ddrphy_bitslip11_o <= 8\'d0;
main_a7ddrphy_bitslip11_value <= 3\'d0;
main_a7ddrphy_bitslip11_r <= 16\'d0;
main_a7ddrphy_bitslip12_o <= 8\'d0;
main_a7ddrphy_bitslip12_value <= 3\'d0;
main_a7ddrphy_bitslip12_r <= 16\'d0;
main_a7ddrphy_bitslip13_o <= 8\'d0;
main_a7ddrphy_bitslip13_value <= 3\'d0;
main_a7ddrphy_bitslip13_r <= 16\'d0;
main_a7ddrphy_bitslip14_o <= 8\'d0;
main_a7ddrphy_bitslip14_value <= 3\'d0;
main_a7ddrphy_bitslip14_r <= 16\'d0;
main_a7ddrphy_bitslip15_o <= 8\'d0;
main_a7ddrphy_bitslip15_value <= 3\'d0;
main_a7ddrphy_bitslip15_r <= 16\'d0;
main_a7ddrphy_n_rddata_en0 <= 1\'d0;
main_a7ddrphy_n_rddata_en1 <= 1\'d0;
main_a7ddrphy_n_rddata_en2 <= 1\'d0;
main_a7ddrphy_n_rddata_en3 <= 1\'d0;
main_a7ddrphy_n_rddata_en4 <= 1\'d0;
main_a7ddrphy_n_rddata_en5 <= 1\'d0;
main_a7ddrphy_n_rddata_en6 <= 1\'d0;
main_a7ddrphy_n_rddata_en7 <= 1\'d0;
main_a7ddrphy_last_wrdata_en <= 4\'d0;
main_sdram_storage <= 4\'d0;
main_sdram_re <= 1\'d0;
main_sdram_phaseinjector0_command_storage <= 6\'d0;
main_sdram_phaseinjector0_command_re <= 1\'d0;
main_sdram_phaseinjector0_address_storage <= 14\'d0;
main_sdram_phaseinjector0_address_re <= 1\'d0;
main_sdram_phaseinjector0_baddress_storage <= 3\'d0;
main_sdram_phaseinjector0_baddress_re <= 1\'d0;
main_sdram_phaseinjector0_wrdata_storage <= 32\'d0;
main_sdram_phaseinjector0_wrdata_re <= 1\'d0;
main_sdram_phaseinjector0_status <= 32\'d0;
main_sdram_phaseinjector1_command_storage <= 6\'d0;
main_sdram_phaseinjector1_command_re <= 1\'d0;
main_sdram_phaseinjector1_address_storage <= 14\'d0;
main_sdram_phaseinjector1_address_re <= 1\'d0;
main_sdram_phaseinjector1_baddress_storage <= 3\'d0;
main_sdram_phaseinjector1_baddress_re <= 1\'d0;
main_sdram_phaseinjector1_wrdata_storage <= 32\'d0;
main_sdram_phaseinjector1_wrdata_re <= 1\'d0;
main_sdram_phaseinjector1_status <= 32\'d0;
main_sdram_phaseinjector2_command_storage <= 6\'d0;
main_sdram_phaseinjector2_command_re <= 1\'d0;
main_sdram_phaseinjector2_address_storage <= 14\'d0;
main_sdram_phaseinjector2_address_re <= 1\'d0;
main_sdram_phaseinjector2_baddress_storage <= 3\'d0;
main_sdram_phaseinjector2_baddress_re <= 1\'d0;
main_sdram_phaseinjector2_wrdata_storage <= 32\'d0;
main_sdram_phaseinjector2_wrdata_re <= 1\'d0;
main_sdram_phaseinjector2_status <= 32\'d0;
main_sdram_phaseinjector3_command_storage <= 6\'d0;
main_sdram_phaseinjector3_command_re <= 1\'d0;
main_sdram_phaseinjector3_address_storage <= 14\'d0;
main_sdram_phaseinjector3_address_re <= 1\'d0;
main_sdram_phaseinjector3_baddress_storage <= 3\'d0;
main_sdram_phaseinjector3_baddress_re <= 1\'d0;
main_sdram_phaseinjector3_wrdata_storage <= 32\'d0;
main_sdram_phaseinjector3_wrdata_re <= 1\'d0;
main_sdram_phaseinjector3_status <= 32\'d0;
main_sdram_dfi_p0_address <= 14\'d0;
main_sdram_dfi_p0_bank <= 3\'d0;
main_sdram_dfi_p0_cas_n <= 1\'d1;
main_sdram_dfi_p0_cs_n <= 1\'d1;
main_sdram_dfi_p0_ras_n <= 1\'d1;
main_sdram_dfi_p0_we_n <= 1\'d1;
main_sdram_dfi_p0_wrdata_en <= 1\'d0;
main_sdram_dfi_p0_rddata_en <= 1\'d0;
main_sdram_dfi_p1_address <= 14\'d0;
main_sdram_dfi_p1_bank <= 3\'d0;
main_sdram_dfi_p1_cas_n <= 1\'d1;
main_sdram_dfi_p1_cs_n <= 1\'d1;
main_sdram_dfi_p1_ras_n <= 1\'d1;
main_sdram_dfi_p1_we_n <= 1\'d1;
main_sdram_dfi_p1_wrdata_en <= 1\'d0;
main_sdram_dfi_p1_rddata_en <= 1\'d0;
main_sdram_dfi_p2_address <= 14\'d0;
main_sdram_dfi_p2_bank <= 3\'d0;
main_sdram_dfi_p2_cas_n <= 1\'d1;
main_sdram_dfi_p2_cs_n <= 1\'d1;
main_sdram_dfi_p2_ras_n <= 1\'d1;
main_sdram_dfi_p2_we_n <= 1\'d1;
main_sdram_dfi_p2_wrdata_en <= 1\'d0;
main_sdram_dfi_p2_rddata_en <= 1\'d0;
main_sdram_dfi_p3_address <= 14\'d0;
main_sdram_dfi_p3_bank <= 3\'d0;
main_sdram_dfi_p3_cas_n <= 1\'d1;
main_sdram_dfi_p3_cs_n <= 1\'d1;
main_sdram_dfi_p3_ras_n <= 1\'d1;
main_sdram_dfi_p3_we_n <= 1\'d1;
main_sdram_dfi_p3_wrdata_en <= 1\'d0;
main_sdram_dfi_p3_rddata_en <= 1\'d0;
main_sdram_cmd_payload_a <= 14\'d0;
main_sdram_cmd_payload_ba <= 3\'d0;
main_sdram_cmd_payload_cas <= 1\'d0;
main_sdram_cmd_payload_ras <= 1\'d0;
main_sdram_cmd_payload_we <= 1\'d0;
main_sdram_timer_count1 <= 9\'d468;
main_sdram_postponer_req_o <= 1\'d0;
main_sdram_postponer_count <= 1\'d0;
main_sdram_sequencer_done1 <= 1\'d0;
main_sdram_sequencer_counter <= 6\'d0;
main_sdram_sequencer_count <= 1\'d0;
main_sdram_zqcs_timer_count1 <= 26\'d59999999;
main_sdram_zqcs_executer_done <= 1\'d0;
main_sdram_zqcs_executer_counter <= 5\'d0;
main_sdram_bankmachine0_cmd_buffer_lookahead_level <= 4\'d0;
main_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3\'d0;
main_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3\'d0;
main_sdram_bankmachine0_cmd_buffer_source_valid <= 1\'d0;
main_sdram_bankmachine0_cmd_buffer_source_first <= 1\'d0;
main_sdram_bankmachine0_cmd_buffer_source_last <= 1\'d0;
main_sdram_bankmachine0_cmd_buffer_source_payload_we <= 1\'d0;
main_sdram_bankmachine0_cmd_buffer_source_payload_addr <= 21\'d0;
main_sdram_bankmachine0_row <= 14\'d0;
main_sdram_bankmachine0_row_opened <= 1\'d0;
main_sdram_bankmachine0_twtpcon_ready <= 1\'d1;
main_sdram_bankmachine0_twtpcon_count <= 3\'d0;
main_sdram_bankmachine0_trccon_ready <= 1\'d1;
main_sdram_bankmachine0_trccon_count <= 2\'d0;
main_sdram_bankmachine0_trascon_ready <= 1\'d1;
main_sdram_bankmachine0_trascon_count <= 2\'d0;
main_sdram_bankmachine1_cmd_buffer_lookahead_level <= 4\'d0;
main_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3\'d0;
main_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3\'d0;
main_sdram_bankmachine1_cmd_buffer_source_valid <= 1\'d0;
main_sdram_bankmachine1_cmd_buffer_source_first <= 1\'d0;
main_sdram_bankmachine1_cmd_buffer_source_last <= 1\'d0;
main_sdram_bankmachine1_cmd_buffer_source_payload_we <= 1\'d0;
main_sdram_bankmachine1_cmd_buffer_source_payload_addr <= 21\'d0;
main_sdram_bankmachine1_row <= 14\'d0;
main_sdram_bankmachine1_row_opened <= 1\'d0;
main_sdram_bankmachine1_twtpcon_ready <= 1\'d1;
main_sdram_bankmachine1_twtpcon_count <= 3\'d0;
main_sdram_bankmachine1_trccon_ready <= 1\'d1;
main_sdram_bankmachine1_trccon_count <= 2\'d0;
main_sdram_bankmachine1_trascon_ready <= 1\'d1;
main_sdram_bankmachine1_trascon_count <= 2\'d0;
main_sdram_bankmachine2_cmd_buffer_lookahead_level <= 4\'d0;
main_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3\'d0;
main_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3\'d0;
main_sdram_bankmachine2_cmd_buffer_source_valid <= 1\'d0;
main_sdram_bankmachine2_cmd_buffer_source_first <= 1\'d0;
main_sdram_bankmachine2_cmd_buffer_source_last <= 1\'d0;
main_sdram_bankmachine2_cmd_buffer_source_payload_we <= 1\'d0;
main_sdram_bankmachine2_cmd_buffer_source_payload_addr <= 21\'d0;
main_sdram_bankmachine2_row <= 14\'d0;
main_sdram_bankmachine2_row_opened <= 1\'d0;
main_sdram_bankmachine2_twtpcon_ready <= 1\'d1;
main_sdram_bankmachine2_twtpcon_count <= 3\'d0;
main_sdram_bankmachine2_trccon_ready <= 1\'d1;
main_sdram_bankmachine2_trccon_count <= 2\'d0;
main_sdram_bankmachine2_trascon_ready <= 1\'d1;
main_sdram_bankmachine2_trascon_count <= 2\'d0;
main_sdram_bankmachine3_cmd_buffer_lookahead_level <= 4\'d0;
main_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3\'d0;
main_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3\'d0;
main_sdram_bankmachine3_cmd_buffer_source_valid <= 1\'d0;
main_sdram_bankmachine3_cmd_buffer_source_first <= 1\'d0;
main_sdram_bankmachine3_cmd_buffer_source_last <= 1\'d0;
main_sdram_bankmachine3_cmd_buffer_source_payload_we <= 1\'d0;
main_sdram_bankmachine3_cmd_buffer_source_payload_addr <= 21\'d0;
main_sdram_bankmachine3_row <= 14\'d0;
main_sdram_bankmachine3_row_opened <= 1\'d0;
main_sdram_bankmachine3_twtpcon_ready <= 1\'d1;
main_sdram_bankmachine3_twtpcon_count <= 3\'d0;
main_sdram_bankmachine3_trccon_ready <= 1\'d1;
main_sdram_bankmachine3_trccon_count <= 2\'d0;
main_sdram_bankmachine3_trascon_ready <= 1\'d1;
main_sdram_bankmachine3_trascon_count <= 2\'d0;
main_sdram_bankmachine4_cmd_buffer_lookahead_level <= 4\'d0;
main_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 3\'d0;
main_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 3\'d0;
main_sdram_bankmachine4_cmd_buffer_source_valid <= 1\'d0;
main_sdram_bankmachine4_cmd_buffer_source_first <= 1\'d0;
main_sdram_bankmachine4_cmd_buffer_source_last <= 1\'d0;
main_sdram_bankmachine4_cmd_buffer_source_payload_we <= 1\'d0;
main_sdram_bankmachine4_cmd_buffer_source_payload_addr <= 21\'d0;
main_sdram_bankmachine4_row <= 14\'d0;
main_sdram_bankmachine4_row_opened <= 1\'d0;
main_sdram_bankmachine4_twtpcon_ready <= 1\'d1;
main_sdram_bankmachine4_twtpcon_count <= 3\'d0;
main_sdram_bankmachine4_trccon_ready <= 1\'d1;
main_sdram_bankmachine4_trccon_count <= 2\'d0;
main_sdram_bankmachine4_trascon_ready <= 1\'d1;
main_sdram_bankmachine4_trascon_count <= 2\'d0;
main_sdram_bankmachine5_cmd_buffer_lookahead_level <= 4\'d0;
main_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 3\'d0;
main_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 3\'d0;
main_sdram_bankmachine5_cmd_buffer_source_valid <= 1\'d0;
main_sdram_bankmachine5_cmd_buffer_source_first <= 1\'d0;
main_sdram_bankmachine5_cmd_buffer_source_last <= 1\'d0;
main_sdram_bankmachine5_cmd_buffer_source_payload_we <= 1\'d0;
main_sdram_bankmachine5_cmd_buffer_source_payload_addr <= 21\'d0;
main_sdram_bankmachine5_row <= 14\'d0;
main_sdram_bankmachine5_row_opened <= 1\'d0;
main_sdram_bankmachine5_twtpcon_ready <= 1\'d1;
main_sdram_bankmachine5_twtpcon_count <= 3\'d0;
main_sdram_bankmachine5_trccon_ready <= 1\'d1;
main_sdram_bankmachine5_trccon_count <= 2\'d0;
main_sdram_bankmachine5_trascon_ready <= 1\'d1;
main_sdram_bankmachine5_trascon_count <= 2\'d0;
main_sdram_bankmachine6_cmd_buffer_lookahead_level <= 4\'d0;
main_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 3\'d0;
main_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 3\'d0;
main_sdram_bankmachine6_cmd_buffer_source_valid <= 1\'d0;
main_sdram_bankmachine6_cmd_buffer_source_first <= 1\'d0;
main_sdram_bankmachine6_cmd_buffer_source_last <= 1\'d0;
main_sdram_bankmachine6_cmd_buffer_source_payload_we <= 1\'d0;
main_sdram_bankmachine6_cmd_buffer_source_payload_addr <= 21\'d0;
main_sdram_bankmachine6_row <= 14\'d0;
main_sdram_bankmachine6_row_opened <= 1\'d0;
main_sdram_bankmachine6_twtpcon_ready <= 1\'d1;
main_sdram_bankmachine6_twtpcon_count <= 3\'d0;
main_sdram_bankmachine6_trccon_ready <= 1\'d1;
main_sdram_bankmachine6_trccon_count <= 2\'d0;
main_sdram_bankmachine6_trascon_ready <= 1\'d1;
main_sdram_bankmachine6_trascon_count <= 2\'d0;
main_sdram_bankmachine7_cmd_buffer_lookahead_level <= 4\'d0;
main_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 3\'d0;
main_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 3\'d0;
main_sdram_bankmachine7_cmd_buffer_source_valid <= 1\'d0;
main_sdram_bankmachine7_cmd_buffer_source_first <= 1\'d0;
main_sdram_bankmachine7_cmd_buffer_source_last <= 1\'d0;
main_sdram_bankmachine7_cmd_buffer_source_payload_we <= 1\'d0;
main_sdram_bankmachine7_cmd_buffer_source_payload_addr <= 21\'d0;
main_sdram_bankmachine7_row <= 14\'d0;
main_sdram_bankmachine7_row_opened <= 1\'d0;
main_sdram_bankmachine7_twtpcon_ready <= 1\'d1;
main_sdram_bankmachine7_twtpcon_count <= 3\'d0;
main_sdram_bankmachine7_trccon_ready <= 1\'d1;
main_sdram_bankmachine7_trccon_count <= 2\'d0;
main_sdram_bankmachine7_trascon_ready <= 1\'d1;
main_sdram_bankmachine7_trascon_count <= 2\'d0;
main_sdram_choose_cmd_grant <= 3\'d0;
main_sdram_choose_req_grant <= 3\'d0;
main_sdram_trrdcon_ready <= 1\'d1;
main_sdram_trrdcon_count <= 1\'d0;
main_sdram_tfawcon_ready <= 1\'d1;
main_sdram_tfawcon_window <= 4\'d0;
main_sdram_tccdcon_ready <= 1\'d1;
main_sdram_tccdcon_count <= 1\'d0;
main_sdram_twtrcon_ready <= 1\'d1;
main_sdram_twtrcon_count <= 3\'d0;
main_sdram_time0 <= 5\'d0;
main_sdram_time1 <= 4\'d0;
main_adr_offset_r <= 2\'d0;
main_count <= 1\'d0;
builder_wb2csr_state <= 1\'d0;
builder_refresher_state <= 2\'d0;
builder_bankmachine0_state <= 3\'d0;
builder_bankmachine1_state <= 3\'d0;
builder_bankmachine2_state <= 3\'d0;
builder_bankmachine3_state <= 3\'d0;
builder_bankmachine4_state <= 3\'d0;
builder_bankmachine5_state <= 3\'d0;
builder_bankmachine6_state <= 3\'d0;
builder_bankmachine7_state <= 3\'d0;
builder_multiplexer_state <= 4\'d0;
builder_rbank <= 3\'d0;
builder_wbank <= 3\'d0;
builder_new_master_wdata_ready0 <= 1\'d0;
builder_new_master_wdata_ready1 <= 1\'d0;
builder_new_master_wdata_ready2 <= 1\'d0;
builder_new_master_rdata_valid0 <= 1\'d0;
builder_new_master_rdata_valid1 <= 1\'d0;
builder_new_master_rdata_valid2 <= 1\'d0;
builder_new_master_rdata_valid3 <= 1\'d0;
builder_new_master_rdata_valid4 <= 1\'d0;
builder_new_master_rdata_valid5 <= 1\'d0;
builder_new_master_rdata_valid6 <= 1\'d0;
builder_new_master_rdata_valid7 <= 1\'d0;
builder_new_master_rdata_valid8 <= 1\'d0;
builder_new_master_rdata_valid9 <= 1\'d0;
builder_fullmemorywe_state <= 2\'d0;
builder_litedramwishbone2native_state <= 2\'d0;
builder_minsoc_grant <= 1\'d0;
builder_minsoc_slave_sel_r <= 4\'d0;
builder_minsoc_count <= 20\'d1000000;
builder_minsoc_interface0_bank_bus_dat_r <= 8\'d0;
builder_minsoc_interface1_bank_bus_dat_r <= 8\'d0;
builder_minsoc_interface2_bank_bus_dat_r <= 8\'d0;
builder_minsoc_interface3_bank_bus_dat_r <= 8\'d0;
builder_minsoc_interface4_bank_bus_dat_r <= 8\'d0;
builder_minsoc_interface5_bank_bus_dat_r <= 8\'d0;
end
builder_regs0 <= serial_rx;
builder_regs1 <= builder_regs0;
end
reg [31:0] mem[0:8191];
reg [31:0] memdat;
always @(posedge sys_clk) begin
memdat <= mem[main_minsoc_rom_adr];
end
assign main_minsoc_rom_dat_r = memdat;
initial begin
$readmemh("mem.init", mem);
end
reg [31:0] mem_1 [0:1023];
reg [ 9:0] memadr;
always @(posedge sys_clk) begin
if (main_minsoc_sram_we[0]) mem_1[main_minsoc_sram_adr][7:0] <= main_minsoc_sram_dat_w[7:0];
if (main_minsoc_sram_we[1]) mem_1[main_minsoc_sram_adr][15:8] <= main_minsoc_sram_dat_w[15:8];
if (main_minsoc_sram_we[2]) mem_1[main_minsoc_sram_adr][23:16] <= main_minsoc_sram_dat_w[23:16];
if (main_minsoc_sram_we[3]) mem_1[main_minsoc_sram_adr][31:24] <= main_minsoc_sram_dat_w[31:24];
memadr <= main_minsoc_sram_adr;
end
assign main_minsoc_sram_dat_r = mem_1[memadr];
initial begin
$readmemh("mem_1.init", mem_1);
end
reg [9:0] storage [0:15];
reg [9:0] memdat_1;
reg [9:0] memdat_2;
always @(posedge sys_clk) begin
if (main_minsoc_uart_tx_fifo_wrport_we)
storage[main_minsoc_uart_tx_fifo_wrport_adr] <= main_minsoc_uart_tx_fifo_wrport_dat_w;
memdat_1 <= storage[main_minsoc_uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (main_minsoc_uart_tx_fifo_rdport_re)
memdat_2 <= storage[main_minsoc_uart_tx_fifo_rdport_adr];
end
assign main_minsoc_uart_tx_fifo_wrport_dat_r = memdat_1;
assign main_minsoc_uart_tx_fifo_rdport_dat_r = memdat_2;
reg [9:0] storage_1[0:15];
reg [9:0] memdat_3;
reg [9:0] memdat_4;
always @(posedge sys_clk) begin
if (main_minsoc_uart_rx_fifo_wrport_we)
storage_1[main_minsoc_uart_rx_fifo_wrport_adr] <= main_minsoc_uart_rx_fifo_wrport_dat_w;
memdat_3 <= storage_1[main_minsoc_uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (main_minsoc_uart_rx_fifo_rdport_re)
memdat_4 <= storage_1[main_minsoc_uart_rx_fifo_rdport_adr];
end
assign main_minsoc_uart_rx_fifo_wrport_dat_r = memdat_3;
assign main_minsoc_uart_rx_fifo_rdport_dat_r = memdat_4;
wire clk100_ibuf;
IBUF clkbuf (
.I(clk100),
.O(clk100_ibuf)
);
BUFG BUFG (
.I(clk100_ibuf),
.O(main_pll_clkin)
);
BUFG BUFG_1 (
.I(main_clkout0),
.O(sys_clk)
);
BUFG BUFG_2 (
.I(main_clkout1),
.O(sys4x_clk)
);
BUFG BUFG_3 (
.I(main_clkout2),
.O(sys4x_dqs_clk)
);
BUFG BUFG_4 (
.I(main_clkout3),
.O(clk200_clk)
);
(* LOC="IDELAYCTRL_X1Y0" *)
IDELAYCTRL IDELAYCTRL (
.REFCLK(clk200_clk),
.RST(main_ic_reset),
.RDY(idelayctl_rdy)
);
wire tq;
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(1\'d0),
.D2(1\'d1),
.D3(1\'d0),
.D4(1\'d1),
.D5(1\'d0),
.D6(1\'d1),
.D7(1\'d0),
.D8(1\'d1),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(main_a7ddrphy_sd_clk_se_nodelay),
.TQ(tq),
.TCE(1\'b1),
.T1(1\'b0)
);
OBUFTDS OBUFTDS_2 (
.I (main_a7ddrphy_sd_clk_se_nodelay),
.O (ddram_clk_p),
.OB(ddram_clk_n),
.T (tq)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_1 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[0]),
.D2(main_a7ddrphy_dfi_p0_address[0]),
.D3(main_a7ddrphy_dfi_p1_address[0]),
.D4(main_a7ddrphy_dfi_p1_address[0]),
.D5(main_a7ddrphy_dfi_p2_address[0]),
.D6(main_a7ddrphy_dfi_p2_address[0]),
.D7(main_a7ddrphy_dfi_p3_address[0]),
.D8(main_a7ddrphy_dfi_p3_address[0]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_2 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[1]),
.D2(main_a7ddrphy_dfi_p0_address[1]),
.D3(main_a7ddrphy_dfi_p1_address[1]),
.D4(main_a7ddrphy_dfi_p1_address[1]),
.D5(main_a7ddrphy_dfi_p2_address[1]),
.D6(main_a7ddrphy_dfi_p2_address[1]),
.D7(main_a7ddrphy_dfi_p3_address[1]),
.D8(main_a7ddrphy_dfi_p3_address[1]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_3 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[2]),
.D2(main_a7ddrphy_dfi_p0_address[2]),
.D3(main_a7ddrphy_dfi_p1_address[2]),
.D4(main_a7ddrphy_dfi_p1_address[2]),
.D5(main_a7ddrphy_dfi_p2_address[2]),
.D6(main_a7ddrphy_dfi_p2_address[2]),
.D7(main_a7ddrphy_dfi_p3_address[2]),
.D8(main_a7ddrphy_dfi_p3_address[2]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[2])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_4 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[3]),
.D2(main_a7ddrphy_dfi_p0_address[3]),
.D3(main_a7ddrphy_dfi_p1_address[3]),
.D4(main_a7ddrphy_dfi_p1_address[3]),
.D5(main_a7ddrphy_dfi_p2_address[3]),
.D6(main_a7ddrphy_dfi_p2_address[3]),
.D7(main_a7ddrphy_dfi_p3_address[3]),
.D8(main_a7ddrphy_dfi_p3_address[3]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[3])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_5 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[4]),
.D2(main_a7ddrphy_dfi_p0_address[4]),
.D3(main_a7ddrphy_dfi_p1_address[4]),
.D4(main_a7ddrphy_dfi_p1_address[4]),
.D5(main_a7ddrphy_dfi_p2_address[4]),
.D6(main_a7ddrphy_dfi_p2_address[4]),
.D7(main_a7ddrphy_dfi_p3_address[4]),
.D8(main_a7ddrphy_dfi_p3_address[4]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[4])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_6 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[5]),
.D2(main_a7ddrphy_dfi_p0_address[5]),
.D3(main_a7ddrphy_dfi_p1_address[5]),
.D4(main_a7ddrphy_dfi_p1_address[5]),
.D5(main_a7ddrphy_dfi_p2_address[5]),
.D6(main_a7ddrphy_dfi_p2_address[5]),
.D7(main_a7ddrphy_dfi_p3_address[5]),
.D8(main_a7ddrphy_dfi_p3_address[5]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[5])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_7 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[6]),
.D2(main_a7ddrphy_dfi_p0_address[6]),
.D3(main_a7ddrphy_dfi_p1_address[6]),
.D4(main_a7ddrphy_dfi_p1_address[6]),
.D5(main_a7ddrphy_dfi_p2_address[6]),
.D6(main_a7ddrphy_dfi_p2_address[6]),
.D7(main_a7ddrphy_dfi_p3_address[6]),
.D8(main_a7ddrphy_dfi_p3_address[6]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[6])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_8 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[7]),
.D2(main_a7ddrphy_dfi_p0_address[7]),
.D3(main_a7ddrphy_dfi_p1_address[7]),
.D4(main_a7ddrphy_dfi_p1_address[7]),
.D5(main_a7ddrphy_dfi_p2_address[7]),
.D6(main_a7ddrphy_dfi_p2_address[7]),
.D7(main_a7ddrphy_dfi_p3_address[7]),
.D8(main_a7ddrphy_dfi_p3_address[7]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[7])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_9 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[8]),
.D2(main_a7ddrphy_dfi_p0_address[8]),
.D3(main_a7ddrphy_dfi_p1_address[8]),
.D4(main_a7ddrphy_dfi_p1_address[8]),
.D5(main_a7ddrphy_dfi_p2_address[8]),
.D6(main_a7ddrphy_dfi_p2_address[8]),
.D7(main_a7ddrphy_dfi_p3_address[8]),
.D8(main_a7ddrphy_dfi_p3_address[8]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[8])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_10 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[9]),
.D2(main_a7ddrphy_dfi_p0_address[9]),
.D3(main_a7ddrphy_dfi_p1_address[9]),
.D4(main_a7ddrphy_dfi_p1_address[9]),
.D5(main_a7ddrphy_dfi_p2_address[9]),
.D6(main_a7ddrphy_dfi_p2_address[9]),
.D7(main_a7ddrphy_dfi_p3_address[9]),
.D8(main_a7ddrphy_dfi_p3_address[9]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[9])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_11 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[10]),
.D2(main_a7ddrphy_dfi_p0_address[10]),
.D3(main_a7ddrphy_dfi_p1_address[10]),
.D4(main_a7ddrphy_dfi_p1_address[10]),
.D5(main_a7ddrphy_dfi_p2_address[10]),
.D6(main_a7ddrphy_dfi_p2_address[10]),
.D7(main_a7ddrphy_dfi_p3_address[10]),
.D8(main_a7ddrphy_dfi_p3_address[10]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[10])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_12 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[11]),
.D2(main_a7ddrphy_dfi_p0_address[11]),
.D3(main_a7ddrphy_dfi_p1_address[11]),
.D4(main_a7ddrphy_dfi_p1_address[11]),
.D5(main_a7ddrphy_dfi_p2_address[11]),
.D6(main_a7ddrphy_dfi_p2_address[11]),
.D7(main_a7ddrphy_dfi_p3_address[11]),
.D8(main_a7ddrphy_dfi_p3_address[11]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[11])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_13 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[12]),
.D2(main_a7ddrphy_dfi_p0_address[12]),
.D3(main_a7ddrphy_dfi_p1_address[12]),
.D4(main_a7ddrphy_dfi_p1_address[12]),
.D5(main_a7ddrphy_dfi_p2_address[12]),
.D6(main_a7ddrphy_dfi_p2_address[12]),
.D7(main_a7ddrphy_dfi_p3_address[12]),
.D8(main_a7ddrphy_dfi_p3_address[12]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[12])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_14 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[13]),
.D2(main_a7ddrphy_dfi_p0_address[13]),
.D3(main_a7ddrphy_dfi_p1_address[13]),
.D4(main_a7ddrphy_dfi_p1_address[13]),
.D5(main_a7ddrphy_dfi_p2_address[13]),
.D6(main_a7ddrphy_dfi_p2_address[13]),
.D7(main_a7ddrphy_dfi_p3_address[13]),
.D8(main_a7ddrphy_dfi_p3_address[13]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_a_iob[13])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_15 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_bank[0]),
.D2(main_a7ddrphy_dfi_p0_bank[0]),
.D3(main_a7ddrphy_dfi_p1_bank[0]),
.D4(main_a7ddrphy_dfi_p1_bank[0]),
.D5(main_a7ddrphy_dfi_p2_bank[0]),
.D6(main_a7ddrphy_dfi_p2_bank[0]),
.D7(main_a7ddrphy_dfi_p3_bank[0]),
.D8(main_a7ddrphy_dfi_p3_bank[0]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_ba_iob[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_16 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_bank[1]),
.D2(main_a7ddrphy_dfi_p0_bank[1]),
.D3(main_a7ddrphy_dfi_p1_bank[1]),
.D4(main_a7ddrphy_dfi_p1_bank[1]),
.D5(main_a7ddrphy_dfi_p2_bank[1]),
.D6(main_a7ddrphy_dfi_p2_bank[1]),
.D7(main_a7ddrphy_dfi_p3_bank[1]),
.D8(main_a7ddrphy_dfi_p3_bank[1]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_ba_iob[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_17 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_bank[2]),
.D2(main_a7ddrphy_dfi_p0_bank[2]),
.D3(main_a7ddrphy_dfi_p1_bank[2]),
.D4(main_a7ddrphy_dfi_p1_bank[2]),
.D5(main_a7ddrphy_dfi_p2_bank[2]),
.D6(main_a7ddrphy_dfi_p2_bank[2]),
.D7(main_a7ddrphy_dfi_p3_bank[2]),
.D8(main_a7ddrphy_dfi_p3_bank[2]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_ba_iob[2])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_18 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_ras_n),
.D2(main_a7ddrphy_dfi_p0_ras_n),
.D3(main_a7ddrphy_dfi_p1_ras_n),
.D4(main_a7ddrphy_dfi_p1_ras_n),
.D5(main_a7ddrphy_dfi_p2_ras_n),
.D6(main_a7ddrphy_dfi_p2_ras_n),
.D7(main_a7ddrphy_dfi_p3_ras_n),
.D8(main_a7ddrphy_dfi_p3_ras_n),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_ras_n_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_19 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_cas_n),
.D2(main_a7ddrphy_dfi_p0_cas_n),
.D3(main_a7ddrphy_dfi_p1_cas_n),
.D4(main_a7ddrphy_dfi_p1_cas_n),
.D5(main_a7ddrphy_dfi_p2_cas_n),
.D6(main_a7ddrphy_dfi_p2_cas_n),
.D7(main_a7ddrphy_dfi_p3_cas_n),
.D8(main_a7ddrphy_dfi_p3_cas_n),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_cas_n_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_20 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_we_n),
.D2(main_a7ddrphy_dfi_p0_we_n),
.D3(main_a7ddrphy_dfi_p1_we_n),
.D4(main_a7ddrphy_dfi_p1_we_n),
.D5(main_a7ddrphy_dfi_p2_we_n),
.D6(main_a7ddrphy_dfi_p2_we_n),
.D7(main_a7ddrphy_dfi_p3_we_n),
.D8(main_a7ddrphy_dfi_p3_we_n),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_we_n_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_21 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_cke),
.D2(main_a7ddrphy_dfi_p0_cke),
.D3(main_a7ddrphy_dfi_p1_cke),
.D4(main_a7ddrphy_dfi_p1_cke),
.D5(main_a7ddrphy_dfi_p2_cke),
.D6(main_a7ddrphy_dfi_p2_cke),
.D7(main_a7ddrphy_dfi_p3_cke),
.D8(main_a7ddrphy_dfi_p3_cke),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_cke_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_22 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_odt),
.D2(main_a7ddrphy_dfi_p0_odt),
.D3(main_a7ddrphy_dfi_p1_odt),
.D4(main_a7ddrphy_dfi_p1_odt),
.D5(main_a7ddrphy_dfi_p2_odt),
.D6(main_a7ddrphy_dfi_p2_odt),
.D7(main_a7ddrphy_dfi_p3_odt),
.D8(main_a7ddrphy_dfi_p3_odt),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_odt_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_23 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_reset_n),
.D2(main_a7ddrphy_dfi_p0_reset_n),
.D3(main_a7ddrphy_dfi_p1_reset_n),
.D4(main_a7ddrphy_dfi_p1_reset_n),
.D5(main_a7ddrphy_dfi_p2_reset_n),
.D6(main_a7ddrphy_dfi_p2_reset_n),
.D7(main_a7ddrphy_dfi_p3_reset_n),
.D8(main_a7ddrphy_dfi_p3_reset_n),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_reset_n_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_24 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_cs_n),
.D2(main_a7ddrphy_dfi_p0_cs_n),
.D3(main_a7ddrphy_dfi_p1_cs_n),
.D4(main_a7ddrphy_dfi_p1_cs_n),
.D5(main_a7ddrphy_dfi_p2_cs_n),
.D6(main_a7ddrphy_dfi_p2_cs_n),
.D7(main_a7ddrphy_dfi_p3_cs_n),
.D8(main_a7ddrphy_dfi_p3_cs_n),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_cs_n_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_25 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata_mask[0]),
.D2(main_a7ddrphy_dfi_p0_wrdata_mask[2]),
.D3(main_a7ddrphy_dfi_p1_wrdata_mask[0]),
.D4(main_a7ddrphy_dfi_p1_wrdata_mask[2]),
.D5(main_a7ddrphy_dfi_p2_wrdata_mask[0]),
.D6(main_a7ddrphy_dfi_p2_wrdata_mask[2]),
.D7(main_a7ddrphy_dfi_p3_wrdata_mask[0]),
.D8(main_a7ddrphy_dfi_p3_wrdata_mask[2]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_dm_iob[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_26 (
.CLK(sys4x_dqs_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dqs_serdes_pattern[0]),
.D2(main_a7ddrphy_dqs_serdes_pattern[1]),
.D3(main_a7ddrphy_dqs_serdes_pattern[2]),
.D4(main_a7ddrphy_dqs_serdes_pattern[3]),
.D5(main_a7ddrphy_dqs_serdes_pattern[4]),
.D6(main_a7ddrphy_dqs_serdes_pattern[5]),
.D7(main_a7ddrphy_dqs_serdes_pattern[6]),
.D8(main_a7ddrphy_dqs_serdes_pattern[7]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dqs)),
.TCE(1\'d1),
.OFB(main_a7ddrphy0),
.OQ(main_a7ddrphy_dqs_nodelay0),
.TQ(main_a7ddrphy_dqs_t0)
);
OBUFTDS OBUFTDS (
.I (main_a7ddrphy_dqs_nodelay0),
.T (main_a7ddrphy_dqs_t0),
.O (ddram_dqs_p[0]),
.OB(ddram_dqs_n[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_27 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata_mask[1]),
.D2(main_a7ddrphy_dfi_p0_wrdata_mask[3]),
.D3(main_a7ddrphy_dfi_p1_wrdata_mask[1]),
.D4(main_a7ddrphy_dfi_p1_wrdata_mask[3]),
.D5(main_a7ddrphy_dfi_p2_wrdata_mask[1]),
.D6(main_a7ddrphy_dfi_p2_wrdata_mask[3]),
.D7(main_a7ddrphy_dfi_p3_wrdata_mask[1]),
.D8(main_a7ddrphy_dfi_p3_wrdata_mask[3]),
.OCE(1\'d1),
.RST(sys_rst),
.OQ(ddram_dm_iob[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_28 (
.CLK(sys4x_dqs_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dqs_serdes_pattern[0]),
.D2(main_a7ddrphy_dqs_serdes_pattern[1]),
.D3(main_a7ddrphy_dqs_serdes_pattern[2]),
.D4(main_a7ddrphy_dqs_serdes_pattern[3]),
.D5(main_a7ddrphy_dqs_serdes_pattern[4]),
.D6(main_a7ddrphy_dqs_serdes_pattern[5]),
.D7(main_a7ddrphy_dqs_serdes_pattern[6]),
.D8(main_a7ddrphy_dqs_serdes_pattern[7]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dqs)),
.TCE(1\'d1),
.OFB(main_a7ddrphy1),
.OQ(main_a7ddrphy_dqs_nodelay1),
.TQ(main_a7ddrphy_dqs_t1)
);
OBUFTDS OBUFTDS_1 (
.I (main_a7ddrphy_dqs_nodelay1),
.T (main_a7ddrphy_dqs_t1),
.O (ddram_dqs_p[1]),
.OB(ddram_dqs_n[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_29 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[0]),
.D2(main_a7ddrphy_dfi_p0_wrdata[16]),
.D3(main_a7ddrphy_dfi_p1_wrdata[0]),
.D4(main_a7ddrphy_dfi_p1_wrdata[16]),
.D5(main_a7ddrphy_dfi_p2_wrdata[0]),
.D6(main_a7ddrphy_dfi_p2_wrdata[16]),
.D7(main_a7ddrphy_dfi_p3_wrdata[0]),
.D8(main_a7ddrphy_dfi_p3_wrdata[16]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay0),
.TQ(main_a7ddrphy_dq_t0)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed0),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data0[7]),
.Q2(main_a7ddrphy_dq_i_data0[6]),
.Q3(main_a7ddrphy_dq_i_data0[5]),
.Q4(main_a7ddrphy_dq_i_data0[4]),
.Q5(main_a7ddrphy_dq_i_data0[3]),
.Q6(main_a7ddrphy_dq_i_data0[2]),
.Q7(main_a7ddrphy_dq_i_data0[1]),
.Q8(main_a7ddrphy_dq_i_data0[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay0),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed0)
);
IOBUF IOBUF (
.I (main_a7ddrphy_dq_o_nodelay0),
.T (main_a7ddrphy_dq_t0),
.IO(ddram_dq[0]),
.O (main_a7ddrphy_dq_i_nodelay0)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_30 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[1]),
.D2(main_a7ddrphy_dfi_p0_wrdata[17]),
.D3(main_a7ddrphy_dfi_p1_wrdata[1]),
.D4(main_a7ddrphy_dfi_p1_wrdata[17]),
.D5(main_a7ddrphy_dfi_p2_wrdata[1]),
.D6(main_a7ddrphy_dfi_p2_wrdata[17]),
.D7(main_a7ddrphy_dfi_p3_wrdata[1]),
.D8(main_a7ddrphy_dfi_p3_wrdata[17]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay1),
.TQ(main_a7ddrphy_dq_t1)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_1 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed1),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data1[7]),
.Q2(main_a7ddrphy_dq_i_data1[6]),
.Q3(main_a7ddrphy_dq_i_data1[5]),
.Q4(main_a7ddrphy_dq_i_data1[4]),
.Q5(main_a7ddrphy_dq_i_data1[3]),
.Q6(main_a7ddrphy_dq_i_data1[2]),
.Q7(main_a7ddrphy_dq_i_data1[1]),
.Q8(main_a7ddrphy_dq_i_data1[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_1 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay1),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed1)
);
IOBUF IOBUF_1 (
.I (main_a7ddrphy_dq_o_nodelay1),
.T (main_a7ddrphy_dq_t1),
.IO(ddram_dq[1]),
.O (main_a7ddrphy_dq_i_nodelay1)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_31 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[2]),
.D2(main_a7ddrphy_dfi_p0_wrdata[18]),
.D3(main_a7ddrphy_dfi_p1_wrdata[2]),
.D4(main_a7ddrphy_dfi_p1_wrdata[18]),
.D5(main_a7ddrphy_dfi_p2_wrdata[2]),
.D6(main_a7ddrphy_dfi_p2_wrdata[18]),
.D7(main_a7ddrphy_dfi_p3_wrdata[2]),
.D8(main_a7ddrphy_dfi_p3_wrdata[18]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay2),
.TQ(main_a7ddrphy_dq_t2)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_2 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed2),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data2[7]),
.Q2(main_a7ddrphy_dq_i_data2[6]),
.Q3(main_a7ddrphy_dq_i_data2[5]),
.Q4(main_a7ddrphy_dq_i_data2[4]),
.Q5(main_a7ddrphy_dq_i_data2[3]),
.Q6(main_a7ddrphy_dq_i_data2[2]),
.Q7(main_a7ddrphy_dq_i_data2[1]),
.Q8(main_a7ddrphy_dq_i_data2[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_2 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay2),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed2)
);
IOBUF IOBUF_2 (
.I (main_a7ddrphy_dq_o_nodelay2),
.T (main_a7ddrphy_dq_t2),
.IO(ddram_dq[2]),
.O (main_a7ddrphy_dq_i_nodelay2)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_32 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[3]),
.D2(main_a7ddrphy_dfi_p0_wrdata[19]),
.D3(main_a7ddrphy_dfi_p1_wrdata[3]),
.D4(main_a7ddrphy_dfi_p1_wrdata[19]),
.D5(main_a7ddrphy_dfi_p2_wrdata[3]),
.D6(main_a7ddrphy_dfi_p2_wrdata[19]),
.D7(main_a7ddrphy_dfi_p3_wrdata[3]),
.D8(main_a7ddrphy_dfi_p3_wrdata[19]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay3),
.TQ(main_a7ddrphy_dq_t3)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_3 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed3),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data3[7]),
.Q2(main_a7ddrphy_dq_i_data3[6]),
.Q3(main_a7ddrphy_dq_i_data3[5]),
.Q4(main_a7ddrphy_dq_i_data3[4]),
.Q5(main_a7ddrphy_dq_i_data3[3]),
.Q6(main_a7ddrphy_dq_i_data3[2]),
.Q7(main_a7ddrphy_dq_i_data3[1]),
.Q8(main_a7ddrphy_dq_i_data3[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_3 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay3),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed3)
);
IOBUF IOBUF_3 (
.I (main_a7ddrphy_dq_o_nodelay3),
.T (main_a7ddrphy_dq_t3),
.IO(ddram_dq[3]),
.O (main_a7ddrphy_dq_i_nodelay3)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_33 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[4]),
.D2(main_a7ddrphy_dfi_p0_wrdata[20]),
.D3(main_a7ddrphy_dfi_p1_wrdata[4]),
.D4(main_a7ddrphy_dfi_p1_wrdata[20]),
.D5(main_a7ddrphy_dfi_p2_wrdata[4]),
.D6(main_a7ddrphy_dfi_p2_wrdata[20]),
.D7(main_a7ddrphy_dfi_p3_wrdata[4]),
.D8(main_a7ddrphy_dfi_p3_wrdata[20]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay4),
.TQ(main_a7ddrphy_dq_t4)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_4 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed4),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data4[7]),
.Q2(main_a7ddrphy_dq_i_data4[6]),
.Q3(main_a7ddrphy_dq_i_data4[5]),
.Q4(main_a7ddrphy_dq_i_data4[4]),
.Q5(main_a7ddrphy_dq_i_data4[3]),
.Q6(main_a7ddrphy_dq_i_data4[2]),
.Q7(main_a7ddrphy_dq_i_data4[1]),
.Q8(main_a7ddrphy_dq_i_data4[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_4 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay4),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed4)
);
IOBUF IOBUF_4 (
.I (main_a7ddrphy_dq_o_nodelay4),
.T (main_a7ddrphy_dq_t4),
.IO(ddram_dq[4]),
.O (main_a7ddrphy_dq_i_nodelay4)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_34 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[5]),
.D2(main_a7ddrphy_dfi_p0_wrdata[21]),
.D3(main_a7ddrphy_dfi_p1_wrdata[5]),
.D4(main_a7ddrphy_dfi_p1_wrdata[21]),
.D5(main_a7ddrphy_dfi_p2_wrdata[5]),
.D6(main_a7ddrphy_dfi_p2_wrdata[21]),
.D7(main_a7ddrphy_dfi_p3_wrdata[5]),
.D8(main_a7ddrphy_dfi_p3_wrdata[21]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay5),
.TQ(main_a7ddrphy_dq_t5)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_5 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed5),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data5[7]),
.Q2(main_a7ddrphy_dq_i_data5[6]),
.Q3(main_a7ddrphy_dq_i_data5[5]),
.Q4(main_a7ddrphy_dq_i_data5[4]),
.Q5(main_a7ddrphy_dq_i_data5[3]),
.Q6(main_a7ddrphy_dq_i_data5[2]),
.Q7(main_a7ddrphy_dq_i_data5[1]),
.Q8(main_a7ddrphy_dq_i_data5[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_5 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay5),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed5)
);
IOBUF IOBUF_5 (
.I (main_a7ddrphy_dq_o_nodelay5),
.T (main_a7ddrphy_dq_t5),
.IO(ddram_dq[5]),
.O (main_a7ddrphy_dq_i_nodelay5)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_35 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[6]),
.D2(main_a7ddrphy_dfi_p0_wrdata[22]),
.D3(main_a7ddrphy_dfi_p1_wrdata[6]),
.D4(main_a7ddrphy_dfi_p1_wrdata[22]),
.D5(main_a7ddrphy_dfi_p2_wrdata[6]),
.D6(main_a7ddrphy_dfi_p2_wrdata[22]),
.D7(main_a7ddrphy_dfi_p3_wrdata[6]),
.D8(main_a7ddrphy_dfi_p3_wrdata[22]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay6),
.TQ(main_a7ddrphy_dq_t6)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_6 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed6),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data6[7]),
.Q2(main_a7ddrphy_dq_i_data6[6]),
.Q3(main_a7ddrphy_dq_i_data6[5]),
.Q4(main_a7ddrphy_dq_i_data6[4]),
.Q5(main_a7ddrphy_dq_i_data6[3]),
.Q6(main_a7ddrphy_dq_i_data6[2]),
.Q7(main_a7ddrphy_dq_i_data6[1]),
.Q8(main_a7ddrphy_dq_i_data6[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_6 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay6),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed6)
);
IOBUF IOBUF_6 (
.I (main_a7ddrphy_dq_o_nodelay6),
.T (main_a7ddrphy_dq_t6),
.IO(ddram_dq[6]),
.O (main_a7ddrphy_dq_i_nodelay6)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_36 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[7]),
.D2(main_a7ddrphy_dfi_p0_wrdata[23]),
.D3(main_a7ddrphy_dfi_p1_wrdata[7]),
.D4(main_a7ddrphy_dfi_p1_wrdata[23]),
.D5(main_a7ddrphy_dfi_p2_wrdata[7]),
.D6(main_a7ddrphy_dfi_p2_wrdata[23]),
.D7(main_a7ddrphy_dfi_p3_wrdata[7]),
.D8(main_a7ddrphy_dfi_p3_wrdata[23]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay7),
.TQ(main_a7ddrphy_dq_t7)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_7 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed7),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data7[7]),
.Q2(main_a7ddrphy_dq_i_data7[6]),
.Q3(main_a7ddrphy_dq_i_data7[5]),
.Q4(main_a7ddrphy_dq_i_data7[4]),
.Q5(main_a7ddrphy_dq_i_data7[3]),
.Q6(main_a7ddrphy_dq_i_data7[2]),
.Q7(main_a7ddrphy_dq_i_data7[1]),
.Q8(main_a7ddrphy_dq_i_data7[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_7 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay7),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed7)
);
IOBUF IOBUF_7 (
.I (main_a7ddrphy_dq_o_nodelay7),
.T (main_a7ddrphy_dq_t7),
.IO(ddram_dq[7]),
.O (main_a7ddrphy_dq_i_nodelay7)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_37 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[8]),
.D2(main_a7ddrphy_dfi_p0_wrdata[24]),
.D3(main_a7ddrphy_dfi_p1_wrdata[8]),
.D4(main_a7ddrphy_dfi_p1_wrdata[24]),
.D5(main_a7ddrphy_dfi_p2_wrdata[8]),
.D6(main_a7ddrphy_dfi_p2_wrdata[24]),
.D7(main_a7ddrphy_dfi_p3_wrdata[8]),
.D8(main_a7ddrphy_dfi_p3_wrdata[24]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay8),
.TQ(main_a7ddrphy_dq_t8)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_8 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed8),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data8[7]),
.Q2(main_a7ddrphy_dq_i_data8[6]),
.Q3(main_a7ddrphy_dq_i_data8[5]),
.Q4(main_a7ddrphy_dq_i_data8[4]),
.Q5(main_a7ddrphy_dq_i_data8[3]),
.Q6(main_a7ddrphy_dq_i_data8[2]),
.Q7(main_a7ddrphy_dq_i_data8[1]),
.Q8(main_a7ddrphy_dq_i_data8[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_8 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay8),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed8)
);
IOBUF IOBUF_8 (
.I (main_a7ddrphy_dq_o_nodelay8),
.T (main_a7ddrphy_dq_t8),
.IO(ddram_dq[8]),
.O (main_a7ddrphy_dq_i_nodelay8)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_38 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[9]),
.D2(main_a7ddrphy_dfi_p0_wrdata[25]),
.D3(main_a7ddrphy_dfi_p1_wrdata[9]),
.D4(main_a7ddrphy_dfi_p1_wrdata[25]),
.D5(main_a7ddrphy_dfi_p2_wrdata[9]),
.D6(main_a7ddrphy_dfi_p2_wrdata[25]),
.D7(main_a7ddrphy_dfi_p3_wrdata[9]),
.D8(main_a7ddrphy_dfi_p3_wrdata[25]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay9),
.TQ(main_a7ddrphy_dq_t9)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_9 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed9),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data9[7]),
.Q2(main_a7ddrphy_dq_i_data9[6]),
.Q3(main_a7ddrphy_dq_i_data9[5]),
.Q4(main_a7ddrphy_dq_i_data9[4]),
.Q5(main_a7ddrphy_dq_i_data9[3]),
.Q6(main_a7ddrphy_dq_i_data9[2]),
.Q7(main_a7ddrphy_dq_i_data9[1]),
.Q8(main_a7ddrphy_dq_i_data9[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_9 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay9),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed9)
);
IOBUF IOBUF_9 (
.I (main_a7ddrphy_dq_o_nodelay9),
.T (main_a7ddrphy_dq_t9),
.IO(ddram_dq[9]),
.O (main_a7ddrphy_dq_i_nodelay9)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_39 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[10]),
.D2(main_a7ddrphy_dfi_p0_wrdata[26]),
.D3(main_a7ddrphy_dfi_p1_wrdata[10]),
.D4(main_a7ddrphy_dfi_p1_wrdata[26]),
.D5(main_a7ddrphy_dfi_p2_wrdata[10]),
.D6(main_a7ddrphy_dfi_p2_wrdata[26]),
.D7(main_a7ddrphy_dfi_p3_wrdata[10]),
.D8(main_a7ddrphy_dfi_p3_wrdata[26]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay10),
.TQ(main_a7ddrphy_dq_t10)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_10 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed10),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data10[7]),
.Q2(main_a7ddrphy_dq_i_data10[6]),
.Q3(main_a7ddrphy_dq_i_data10[5]),
.Q4(main_a7ddrphy_dq_i_data10[4]),
.Q5(main_a7ddrphy_dq_i_data10[3]),
.Q6(main_a7ddrphy_dq_i_data10[2]),
.Q7(main_a7ddrphy_dq_i_data10[1]),
.Q8(main_a7ddrphy_dq_i_data10[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_10 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay10),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed10)
);
IOBUF IOBUF_10 (
.I (main_a7ddrphy_dq_o_nodelay10),
.T (main_a7ddrphy_dq_t10),
.IO(ddram_dq[10]),
.O (main_a7ddrphy_dq_i_nodelay10)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_40 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[11]),
.D2(main_a7ddrphy_dfi_p0_wrdata[27]),
.D3(main_a7ddrphy_dfi_p1_wrdata[11]),
.D4(main_a7ddrphy_dfi_p1_wrdata[27]),
.D5(main_a7ddrphy_dfi_p2_wrdata[11]),
.D6(main_a7ddrphy_dfi_p2_wrdata[27]),
.D7(main_a7ddrphy_dfi_p3_wrdata[11]),
.D8(main_a7ddrphy_dfi_p3_wrdata[27]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay11),
.TQ(main_a7ddrphy_dq_t11)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_11 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed11),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data11[7]),
.Q2(main_a7ddrphy_dq_i_data11[6]),
.Q3(main_a7ddrphy_dq_i_data11[5]),
.Q4(main_a7ddrphy_dq_i_data11[4]),
.Q5(main_a7ddrphy_dq_i_data11[3]),
.Q6(main_a7ddrphy_dq_i_data11[2]),
.Q7(main_a7ddrphy_dq_i_data11[1]),
.Q8(main_a7ddrphy_dq_i_data11[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_11 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay11),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed11)
);
IOBUF IOBUF_11 (
.I (main_a7ddrphy_dq_o_nodelay11),
.T (main_a7ddrphy_dq_t11),
.IO(ddram_dq[11]),
.O (main_a7ddrphy_dq_i_nodelay11)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_41 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[12]),
.D2(main_a7ddrphy_dfi_p0_wrdata[28]),
.D3(main_a7ddrphy_dfi_p1_wrdata[12]),
.D4(main_a7ddrphy_dfi_p1_wrdata[28]),
.D5(main_a7ddrphy_dfi_p2_wrdata[12]),
.D6(main_a7ddrphy_dfi_p2_wrdata[28]),
.D7(main_a7ddrphy_dfi_p3_wrdata[12]),
.D8(main_a7ddrphy_dfi_p3_wrdata[28]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay12),
.TQ(main_a7ddrphy_dq_t12)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_12 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed12),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data12[7]),
.Q2(main_a7ddrphy_dq_i_data12[6]),
.Q3(main_a7ddrphy_dq_i_data12[5]),
.Q4(main_a7ddrphy_dq_i_data12[4]),
.Q5(main_a7ddrphy_dq_i_data12[3]),
.Q6(main_a7ddrphy_dq_i_data12[2]),
.Q7(main_a7ddrphy_dq_i_data12[1]),
.Q8(main_a7ddrphy_dq_i_data12[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_12 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay12),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed12)
);
IOBUF IOBUF_12 (
.I (main_a7ddrphy_dq_o_nodelay12),
.T (main_a7ddrphy_dq_t12),
.IO(ddram_dq[12]),
.O (main_a7ddrphy_dq_i_nodelay12)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_42 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[13]),
.D2(main_a7ddrphy_dfi_p0_wrdata[29]),
.D3(main_a7ddrphy_dfi_p1_wrdata[13]),
.D4(main_a7ddrphy_dfi_p1_wrdata[29]),
.D5(main_a7ddrphy_dfi_p2_wrdata[13]),
.D6(main_a7ddrphy_dfi_p2_wrdata[29]),
.D7(main_a7ddrphy_dfi_p3_wrdata[13]),
.D8(main_a7ddrphy_dfi_p3_wrdata[29]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay13),
.TQ(main_a7ddrphy_dq_t13)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_13 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed13),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data13[7]),
.Q2(main_a7ddrphy_dq_i_data13[6]),
.Q3(main_a7ddrphy_dq_i_data13[5]),
.Q4(main_a7ddrphy_dq_i_data13[4]),
.Q5(main_a7ddrphy_dq_i_data13[3]),
.Q6(main_a7ddrphy_dq_i_data13[2]),
.Q7(main_a7ddrphy_dq_i_data13[1]),
.Q8(main_a7ddrphy_dq_i_data13[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_13 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay13),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed13)
);
IOBUF IOBUF_13 (
.I (main_a7ddrphy_dq_o_nodelay13),
.T (main_a7ddrphy_dq_t13),
.IO(ddram_dq[13]),
.O (main_a7ddrphy_dq_i_nodelay13)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_43 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[14]),
.D2(main_a7ddrphy_dfi_p0_wrdata[30]),
.D3(main_a7ddrphy_dfi_p1_wrdata[14]),
.D4(main_a7ddrphy_dfi_p1_wrdata[30]),
.D5(main_a7ddrphy_dfi_p2_wrdata[14]),
.D6(main_a7ddrphy_dfi_p2_wrdata[30]),
.D7(main_a7ddrphy_dfi_p3_wrdata[14]),
.D8(main_a7ddrphy_dfi_p3_wrdata[30]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay14),
.TQ(main_a7ddrphy_dq_t14)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_14 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed14),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data14[7]),
.Q2(main_a7ddrphy_dq_i_data14[6]),
.Q3(main_a7ddrphy_dq_i_data14[5]),
.Q4(main_a7ddrphy_dq_i_data14[4]),
.Q5(main_a7ddrphy_dq_i_data14[3]),
.Q6(main_a7ddrphy_dq_i_data14[2]),
.Q7(main_a7ddrphy_dq_i_data14[1]),
.Q8(main_a7ddrphy_dq_i_data14[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_14 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay14),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed14)
);
IOBUF IOBUF_14 (
.I (main_a7ddrphy_dq_o_nodelay14),
.T (main_a7ddrphy_dq_t14),
.IO(ddram_dq[14]),
.O (main_a7ddrphy_dq_i_nodelay14)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4\'d8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1\'d1)
) OSERDESE2_44 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[15]),
.D2(main_a7ddrphy_dfi_p0_wrdata[31]),
.D3(main_a7ddrphy_dfi_p1_wrdata[15]),
.D4(main_a7ddrphy_dfi_p1_wrdata[31]),
.D5(main_a7ddrphy_dfi_p2_wrdata[15]),
.D6(main_a7ddrphy_dfi_p2_wrdata[31]),
.D7(main_a7ddrphy_dfi_p3_wrdata[15]),
.D8(main_a7ddrphy_dfi_p3_wrdata[31]),
.OCE(1\'d1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1\'d1),
.OQ(main_a7ddrphy_dq_o_nodelay15),
.TQ(main_a7ddrphy_dq_t15)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4\'d8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1\'d1),
.SERDES_MODE("MASTER")
) ISERDESE2_15 (
.BITSLIP(1\'d0),
.CE1(1\'d1),
.CLK(sys4x_clk),
.CLKB(sys4x_clk),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed15),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data15[7]),
.Q2(main_a7ddrphy_dq_i_data15[6]),
.Q3(main_a7ddrphy_dq_i_data15[5]),
.Q4(main_a7ddrphy_dq_i_data15[4]),
.Q5(main_a7ddrphy_dq_i_data15[3]),
.Q6(main_a7ddrphy_dq_i_data15[2]),
.Q7(main_a7ddrphy_dq_i_data15[1]),
.Q8(main_a7ddrphy_dq_i_data15[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1\'d0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_15 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay15),
.INC(1\'d1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1\'d0),
.DATAOUT(main_a7ddrphy_dq_i_delayed15)
);
IOBUF IOBUF_15 (
.I (main_a7ddrphy_dq_o_nodelay15),
.T (main_a7ddrphy_dq_t15),
.IO(ddram_dq[15]),
.O (main_a7ddrphy_dq_i_nodelay15)
);
reg [23:0] storage_2[0:7];
reg [23:0] memdat_5;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
memdat_5 <= storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_3[0:7];
reg [23:0] memdat_6;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
memdat_6 <= storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_4[0:7];
reg [23:0] memdat_7;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
memdat_7 <= storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_5[0:7];
reg [23:0] memdat_8;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
memdat_8 <= storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_6[0:7];
reg [23:0] memdat_9;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we)
storage_6[main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
memdat_9 <= storage_6[main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_7 [0:7];
reg [23:0] memdat_10;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we)
storage_7[main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
memdat_10 <= storage_7[main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_8 [0:7];
reg [23:0] memdat_11;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we)
storage_8[main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
memdat_11 <= storage_8[main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_9 [0:7];
reg [23:0] memdat_12;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we)
storage_9[main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
memdat_12 <= storage_9[main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr];
reg [23:0] tag_mem [0:511];
reg ['b' 8:0] memadr_1;
always @(posedge sys_clk) begin
if (main_tag_port_we) tag_mem[main_tag_port_adr] <= main_tag_port_dat_w;
memadr_1 <= main_tag_port_adr;
end
assign main_tag_port_dat_r = tag_mem[memadr_1];
VexRiscv VexRiscv (
.clk(sys_clk),
.dBusWishbone_ACK(main_minsoc_cpu_dbus_ack),
.dBusWishbone_DAT_MISO(main_minsoc_cpu_dbus_dat_r),
.dBusWishbone_ERR(main_minsoc_cpu_dbus_err),
.externalInterruptArray(main_minsoc_cpu_interrupt),
.externalResetVector(main_minsoc_vexriscv),
.iBusWishbone_ACK(main_minsoc_cpu_ibus_ack),
.iBusWishbone_DAT_MISO(main_minsoc_cpu_ibus_dat_r),
.iBusWishbone_ERR(main_minsoc_cpu_ibus_err),
.reset((sys_rst | main_minsoc_cpu_reset)),
.softwareInterrupt(1\'d0),
.timerInterrupt(1\'d0),
.dBusWishbone_ADR(main_minsoc_cpu_dbus_adr),
.dBusWishbone_BTE(main_minsoc_cpu_dbus_bte),
.dBusWishbone_CTI(main_minsoc_cpu_dbus_cti),
.dBusWishbone_CYC(main_minsoc_cpu_dbus_cyc),
.dBusWishbone_DAT_MOSI(main_minsoc_cpu_dbus_dat_w),
.dBusWishbone_SEL(main_minsoc_cpu_dbus_sel),
.dBusWishbone_STB(main_minsoc_cpu_dbus_stb),
.dBusWishbone_WE(main_minsoc_cpu_dbus_we),
.iBusWishbone_ADR(main_minsoc_cpu_ibus_adr),
.iBusWishbone_BTE(main_minsoc_cpu_ibus_bte),
.iBusWishbone_CTI(main_minsoc_cpu_ibus_cti),
.iBusWishbone_CYC(main_minsoc_cpu_ibus_cyc),
.iBusWishbone_DAT_MOSI(main_minsoc_cpu_ibus_dat_w),
.iBusWishbone_SEL(main_minsoc_cpu_ibus_sel),
.iBusWishbone_STB(main_minsoc_cpu_ibus_stb),
.iBusWishbone_WE(main_minsoc_cpu_ibus_we)
);
PLLE2_ADV #(
.CLKFBOUT_MULT(4\'d12),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(5\'d20),
.CLKOUT0_PHASE(1\'d0),
.CLKOUT1_DIVIDE(3\'d5),
.CLKOUT1_PHASE(1\'d0),
.CLKOUT2_DIVIDE(3\'d5),
.CLKOUT2_PHASE(90000),
.CLKOUT3_DIVIDE(3\'d6),
.CLKOUT3_PHASE(1\'d0),
.DIVCLK_DIVIDE(1\'d1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(main_pll_clkin),
.RST(main_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
.CLKOUT1(main_clkout1),
.CLKOUT2(main_clkout2),
.CLKOUT3(main_clkout3),
.LOCKED(main_locked)
);
reg [7:0] data_mem_grain0[0:511];
reg [8:0] memadr_2;
always @(posedge sys_clk) begin
if (main_data_port_we[0]) data_mem_grain0[main_data_port_adr] <= main_data_port_dat_w[7:0];
memadr_2 <= main_data_port_adr;
end
assign main_data_port_dat_r[7:0] = data_mem_grain0[memadr_2];
reg [7:0] data_mem_grain1[0:511];
reg [8:0] memadr_3;
always @(posedge sys_clk) begin
if (main_data_port_we[1]) data_mem_grain1[main_data_port_adr] <= main_data_port_dat_w[15:8];
memadr_3 <= main_data_port_adr;
end
assign main_data_port_dat_r[15:8] = data_mem_grain1[memadr_3];
reg [7:0] data_mem_grain2[0:511];
reg [8:0] memadr_4;
always @(posedge sys_clk) begin
if (main_data_port_we[2]) data_mem_grain2[main_data_port_adr] <= main_data_port_dat_w[23:16];
memadr_4 <= main_data_port_adr;
end
assign main_data_port_dat_r[23:16] = data_mem_grain2[memadr_4];
reg [7:0] data_mem_grain3[0:511];
reg [8:0] memadr_5;
always @(posedge sys_clk) begin
if (main_data_port_we[3]) data_mem_grain3[main_data_port_adr] <= main_data_port_dat_w[31:24];
memadr_5 <= main_data_port_adr;
end
assign main_data_port_dat_r[31:24] = data_mem_grain3[memadr_5];
reg [7:0] data_mem_grain4[0:511];
reg [8:0] memadr_6;
always @(posedge sys_clk) begin
if (main_data_port_we[4]) data_mem_grain4[main_data_port_adr] <= main_data_port_dat_w[39:32];
memadr_6 <= main_data_port_adr;
end
assign main_data_port_dat_r[39:32] = data_mem_grain4[memadr_6];
reg [7:0] data_mem_grain5[0:511];
reg [8:0] memadr_7;
always @(posedge sys_clk) begin
if (main_data_port_we[5]) data_mem_grain5[main_data_port_adr] <= main_data_port_dat_w[47:40];
memadr_7 <= main_data_port_adr;
end
assign main_data_port_dat_r[47:40] = data_mem_grain5[memadr_7];
reg [7:0] data_mem_grain6[0:511];
reg [8:0] memadr_8;
always @(posedge sys_clk) begin
if (main_data_port_we[6]) data_mem_grain6[main_data_port_adr] <= main_data_port_dat_w[55:48];
memadr_8 <= main_data_port_adr;
end
assign main_data_port_dat_r[55:48] = data_mem_grain6[memadr_8];
reg [7:0] data_mem_grain7[0:511];
reg [8:0] memadr_9;
always @(posedge sys_clk) begin
if (main_data_port_we[7]) data_mem_grain7[main_data_port_adr] <= main_data_port_dat_w[63:56];
memadr_9 <= main_data_port_adr;
end
assign main_data_port_dat_r[63:56] = data_mem_grain7[memadr_9];
reg [7:0] data_mem_grain8[0:511];
reg [8:0] memadr_10;
always @(posedge sys_clk) begin
if (main_data_port_we[8]) data_mem_grain8[main_data_port_adr] <= main_data_port_dat_w[71:64];
memadr_10 <= main_data_port_adr;
end
assign main_data_port_dat_r[71:64] = data_mem_grain8[memadr_10];
reg [7:0] data_mem_grain9[0:511];
reg [8:0] memadr_11;
always @(posedge sys_clk) begin
if (main_data_port_we[9]) data_mem_grain9[main_data_port_adr] <= main_data_port_dat_w[79:72];
memadr_11 <= main_data_port_adr;
end
assign main_data_port_dat_r[79:72] = data_mem_grain9[memadr_11];
reg [7:0] data_mem_grain10[0:511];
reg [8:0] memadr_12;
always @(posedge sys_clk) begin
if (main_data_port_we[10]) data_mem_grain10[main_data_port_adr] <= main_data_port_dat_w[87:80];
memadr_12 <= main_data_port_adr;
end
assign main_data_port_dat_r[87:80] = data_mem_grain10[memadr_12];
reg [7:0] data_mem_grain11[0:511];
reg [8:0] memadr_13;
always @(posedge sys_clk) begin
if (main_data_port_we[11]) data_mem_grain11[main_data_port_adr] <= main_data_port_dat_w[95:88];
memadr_13 <= main_data_port_adr;
end
assign main_data_port_dat_r[95:88] = data_mem_grain11[memadr_13];
reg [7:0] data_mem_grain12[0:511];
reg [8:0] memadr_14;
always @(posedge sys_clk) begin
if (main_data_port_we[12]) data_mem_grain12[main_data_port_adr] <= main_data_port_dat_w[103:96];
memadr_14 <= main_data_port_adr;
end
assign main_data_port_dat_r[103:96] = data_mem_grain12[memadr_14];
reg [7:0] data_mem_grain13[0:511];
reg [8:0] memadr_15;
always @(posedge sys_clk) begin
if (main_data_port_we[13])
data_mem_grain13[main_data_port_adr] <= main_data_port_dat_w[111:104];
memadr_15 <= main_data_port_adr;
end
assign main_data_port_dat_r[111:104] = data_mem_grain13[memadr_15];
reg [7:0] data_mem_grain14[0:511];
reg [8:0] memadr_16;
always @(posedge sys_clk) begin
if (main_data_port_we[14])
data_mem_grain14[main_data_port_adr] <= main_data_port_dat_w[119:112];
memadr_16 <= main_data_port_adr;
end
assign main_data_port_dat_r[119:112] = data_mem_grain14[memadr_16];
reg [7:0] data_mem_grain15[0:511];
reg [8:0] memadr_17;
always @(posedge sys_clk) begin
if (main_data_port_we[15])
data_mem_grain15[main_data_port_adr] <= main_data_port_dat_w[127:120];
memadr_17 <= main_data_port_adr;
end
assign main_data_port_dat_r[127:120] = data_mem_grain15[memadr_17];
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1\'d1)
) FDPE (
.C (sys_clk),
.CE (1\'d1),
.D (1\'d0),
.PRE(builder_xilinxasyncresetsynchronizerimpl0),
.Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1\'d1)
) FDPE_1 (
.C (sys_clk),
.CE (1\'d1),
.D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
.PRE(builder_xilinxasyncresetsynchronizerimpl0),
.Q (sys_rst)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1\'d1)
) FDPE_2 (
.C (sys4x_clk),
.CE (1\'d1),
.D (1\'d0),
.PRE(builder_xilinxasyncresetsynchronizerimpl1),
.Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1\'d1)
) FDPE_3 (
.C (sys4x_clk),
.CE (1\'d1),
.D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
.PRE(builder_xilinxasyncresetsynchronizerimpl1),
.Q (builder_xilinxasyncresetsynchronizerimpl1_expr)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1\'d1)
) FDPE_4 (
.C (sys4x_dqs_clk),
.CE (1\'d1),
.D (1\'d0),
.PRE(builder_xilinxasyncresetsynchronizerimpl2),
.Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1\'d1)
) FDPE_5 (
.C (sys4x_dqs_clk),
.CE (1\'d1),
.D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
.PRE(builder_xilinxasyncresetsynchronizerimpl2),
.Q (builder_xilinxasyncresetsynchronizerimpl2_expr)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1\'d1)
) FDPE_6 (
.C (clk200_clk),
.CE (1\'d1),
.D (1\'d0),
.PRE(builder_xilinxasyncresetsynchronizerimpl3),
.Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1\'d1)
) FDPE_7 (
.C (clk200_clk),
.CE (1\'d1),
.D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
.PRE(builder_xilinxasyncresetsynchronizerimpl3),
.Q (clk200_rst)
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* keep_hierarchy *)
module my_lut (
input wire [3:0] i,
output wire o
);
LUT4 #(
.INIT(16\'hAAAA)
) my_lut (
.I0(i[0]),
.I1(i[1]),
.I2(i[2]),
.I3(1\'bx),
.O (o)
);
endmodule
module my_top (
input wire i,
output wire o
);
my_lut my_lut (
.i({1\'b0, 1\'b1, i}),
.o(o)
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1\'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \\$__QLF_RAM16K (
\toutput [31:0] RDATA,
\tinput RCLK, RE,
\tinput [8:0] RADDR,
\tinput WCLK, WE,
\tinput [8:0] WADDR,
\tinput [31:0] WENB,
\tinput [31:0] WDATA
);
\tgenerate
\t\tDP_RAM16K #()
\t\t\t_TECHMAP_REPLACE_ (
\t\t\t.d_out(RDATA),
\t\t\t.rclk (RCLK ),
\t\t\t.wclk (WCLK ),
\t\t\t.ren (RE ),
\t\t\t.raddr(RADDR),
\t\t\t.wen (WE ),
\t\t\t.waddr(WADDR),
\t\t\t.wenb (WENB ),
\t\t\t.d_in (WDATA)
\t\t);
\tendgenerate
endmodule
module \\$__QLF_RAM16K_M0 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
\tparameter [4095:0] INIT = 4096\'bx;
\tinput CLK1;
\tinput [8:0] A1ADDR;
\toutput [31:0] A1DATA;
\tinput A1EN;
\tinput [8:0] B1ADDR;
\tinput [31:0] B1DATA;
\tinput B1EN;
\twire [31:0] WENB;
\tassign WENB = 32\'hFFFFFFFF;
\t\\$__QLF_RAM16K #()
\t\t _TECHMAP_REPLACE_ (
\t\t.RDATA(A1DATA),
\t\t.RADDR(A1ADDR),
\t\t.RCLK (CLK1 ),
\t\t.RE (A1EN ),
\t\t.WDATA(B1DATA),
\t\t.WADDR(B1ADDR),
\t\t.WCLK (CLK1 ),
\t\t.WE (B1EN ),
\t\t.WENB (WENB )
\t);
endmodule
module \\$__QLF_RAM16K_M1 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
\tparameter [4095:0] INIT = 4096\'bx;
\tinput CLK1;
\tinput [9:0] A1ADDR;
\toutput [31:0] A1DATA;
\tinput A1EN;
\tinput [9:0] B1ADDR;
\tinput [31:0] B1DATA;
\tinput B1EN;
\twire [31:0] WENB;
\twire [31:0] WDATA;
\tgenerate
\t\twire A1BAR;
\t\tassign A1BAR = ~A1ADDR[0];
\t\tassign WDATA = { {2{B1DATA[15:0]}}};
\tendgenerate
\tassign WENB = { {16{A1ADDR[0]}} , {16{A1BAR}}};
\t\\$__QLF_RAM16K #()
\t\t _TECHMAP_REPLACE_ (
\t\t.RDATA(A1DATA ),
\t\t.RADDR(A1ADDR ),
\t\t.RCLK (CLK1 ),
\t\t.RE (A1EN ),
\t\t.WDATA(WDATA ),
\t\t.WADDR(B1ADDR[9:1]),
\t\t.WCLK (CLK1 ),
\t\t.WENB (WENB ),
\t\t.WE (B1EN )
\t);
endmodule
module \\$__QLF_RAM16K_M2 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
\tparameter [4095:0] INIT = 4096\'bx;
\tinput CLK1;
\tinput [10:0] A1ADDR;
\toutput [31:0] A1DATA;
\tinput A1EN;
\tinput [10:0] B1ADDR;
\tinput [7:0] B1DATA;
\tinput B1EN;
\twire [31:0] WENB;
\twire [31:0] WDATA;
\tgenerate
\t\twire A1BAR0, A1BAR1;
\t\tassign A1BAR0 = ~A1ADDR[0];
\t\tassign A1BAR1 = ~A1ADDR[1];
\t\tassign WDATA = { {4{B1DATA[7:0]}}};
\tendgenerate
\tassign WENB = { {8{A1ADDR[1]& A1ADDR[0]}},
\t\t\t{8{A1ADDR[1]& A1BAR0}} ,
\t\t\t{8{A1BAR1 & A1ADDR[0]}},
\t\t\t{8{A1BAR1 & A1BAR0}}}\t ;
\t\\$__QLF_RAM16K #()
\t\t _TECHMAP_REPLACE_ (
\t\t.RDATA(A1DATA ),
\t\t.RADDR(A1ADDR ),
\t\t.RCLK (CLK1 ),
\t\t.RE (A1EN ),
\t\t.WDATA(B1DATA ),
\t\t.WADDR(B1ADDR[10:2]),
\t\t.WCLK (CLK1 ),
\t\t.WENB (WENB ),
\t\t.WE (B1EN )
\t);
endmodule
module \\$__QLF_RAM16K_M3 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
\tparameter [4095:0] INIT = 4096\'bx;
\tinput CLK1;
\tinput [11:0] A1ADDR;
\toutput [31:0] A1DATA;
\tinput A1EN;
\tinput [11:0] B1ADDR;
\tinput [3:0] B1DATA;
\tinput B1EN;
\twire [31:0] WENB;
\twire [31:0] WDATA;
\tgenerate
\t\tassign WDATA = { {8{B1DATA[3:0]}}};
\t\twire A1BAR0, A1BAR1, A1BAR2;
\t\tassign A1BAR0 = ~A1ADDR[0];
\t\tassign A1BAR1 = ~A1ADDR[1];
\t\tassign A1BAR2 = ~A1ADDR[2];
\tendgenerate
\t\tassign WENB = { {4{A1ADDR[2] &A1ADDR[1] & A1ADDR[0]}},
\t\t\t\t{4{A1ADDR[2] &A1ADDR[1] & A1BAR0}} ,
\t\t\t\t{4{A1ADDR[2] &A1BAR1 & A1ADDR[0]}},
\t\t\t\t{4{A1ADDR[2] &A1BAR1 & A1BAR0}} ,
\t\t\t\t{4{A1BAR2 &A1ADDR[1] & A1ADDR[0]}},
\t\t\t\t{4{A1BAR2 &A1ADDR[1] & A1BAR0}} ,
\t\t\t\t{4{A1BAR2 &A1BAR1 & A1ADDR[0]}},
\t\t\t\t{4{A1BAR2 &A1BAR1 & A1BAR0}}} ;
\t\\$__QLF_RAM16K #()
\t\t _TECHMAP_REPLACE_ (
\t\t.RDATA(A1DATA ),
\t\t.RADDR(A1ADDR ),
\t\t.RCLK (CLK1 ),
\t\t.RE (A1EN ),
\t\t.WDATA(B1DATA ),
\t\t.WADDR(B1ADDR[11:3]),
\t\t.WCLK (CLK1 ),
\t\t.WENB (WENB ),
\t\t.WE (B1EN )
\t);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`ifndef NO_LUT
module \\$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
\t if (WIDTH == 6) begin
\t frac_lut6 #(.LUT(LUT)) _TECHMAP_REPLACE_ (.lut6_out(Y),.in(A));
\t end else begin
\t wire _TECHMAP_FAIL_ = 1;
\t end
endgenerate
endmodule
`endif
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
module box(
(* invertible_pin="INV_A" *)
input wire A,
output wire Y
);
parameter [0:0] INV_A = 1\'b0;
endmodule
module top(
input wire [1:0] di,
output wire [2:0] do
);
wire [1:0] d;
\\$_NOT_ n0 (.A(di[0]), .Y(d[0]));
\\$_NOT_ n1 (.A(di[1]), .Y(d[1]));
box b0 (.A(d[0]), .Y(do[0]));
box b1 (.A(d[1]), .Y(do[1]));
assign do[0] = d[0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock, reset, req_0, req_1;
output gnt_0, gnt_1;
wire clock, reset, req_0, req_1;
reg gnt_0, gnt_1;
parameter SIZE = 3;
parameter IDLE = 3\'b001;
parameter GNT0 = 3\'b010;
parameter GNT1 = 3\'b100;
parameter GNT2 = 3\'b101;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @(posedge clock) begin : FSM
if (reset == 1\'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case (state)
IDLE:
if (req_0 == 1\'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1\'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0:
if (req_0 == 1\'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1:
if (req_1 == 1\'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2:
if (req_0 == 1\'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default: state <= #1 IDLE;
endcase
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
//////////////////////////
// arithmetic //
//////////////////////////
(* techmap_celltype = "$alu" *)
module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
\tparameter A_SIGNED = 0;
\tparameter B_SIGNED = 0;
\tparameter A_WIDTH = 1;
\tparameter B_WIDTH = 1;
\tparameter Y_WIDTH = 1;
\tinput [A_WIDTH-1:0] A;
\tinput [B_WIDTH-1:0] B;
\toutput [Y_WIDTH-1:0] X, Y;
\tinput CI, BI;
\toutput [Y_WIDTH-1:0] CO;
\twire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
\twire [Y_WIDTH: 0 ] CARRY;
\tassign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1];
\t// Due to VPR limitations regarding IO connexion to carry chain,
\t// we generate the carry chain input signal using an intermediate adder
\t// since we can connect a & b from io pads, but not cin & cout
\tgenerate
\t adder intermediate_adder (
\t .cin ( ),
\t .cout (CARRY[0]),
\t .a (CI ),
\t .b (CI ),
\t .sumout ( )
\t );
\t adder first_adder (
\t .cin (CARRY[0]),
\t .cout (CARRY[1]),
\t .a (AA[0] ),
\t .b (BB[0] ),
\t .sumout (Y[0] )
\t );
\tendgenerate
\tgenvar i;
\tgenerate for (i = 1; i < Y_WIDTH ; i = i+1) begin:gen3
\t adder my_adder (
\t .cin (CARRY[i] ),
\t .cout (CARRY[i+1]),
\t .a (AA[i] ),
\t .b (BB[i] ),
\t .sumout (Y[i] )
\t );
\tend endgenerate
\tassign X = AA ^ BB;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input wire clk,
output wire [3:0] led,
inout wire io
);
reg [3:0] r;
initial r <= 0;
always @(posedge clk) r <= r + io;
assign led = {r[0], r[1], r[2], r[3]};
assign io = r[0] ? 1 : 1\'bz;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module mux2 (
S,
A,
B,
Y
);
input S;
input A, B;
output reg Y;
always @(*) Y = (S) ? B : A;
endmodule
module mux4 (
S,
D,
Y
);
input [1:0] S;
input [3:0] D;
output Y;
reg Y;
wire [1:0] S;
wire [3:0] D;
always @* begin
case (S)
0: Y = D[0];
1: Y = D[1];
2: Y = D[2];
3: Y = D[3];
endcase
end
endmodule
module mux8 (
S,
D,
Y
);
input [2:0] S;
input [7:0] D;
output Y;
reg Y;
wire [2:0] S;
wire [7:0] D;
always @* begin
case (S)
0: Y = D[0];
1: Y = D[1];
2: Y = D[2];
3: Y = D[3];
4: Y = D[4];
5: Y = D[5];
6: Y = D[6];
7: Y = D[7];
endcase
end
endmodule
module mux16 (
D,
S,
Y
);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input [0:7] in,
output B1,
B2,
B3,
B4,
B5,
B6,
B7,
B8,
B9,
B10
);
assign B1 = in[0] & in[1];
assign B2 = in[0] | in[1];
assign B3 = in[0]~&in[1];
assign B4 = in[0]~|in[1];
assign B5 = in[0] ^ in[1];
assign B6 = in[0] ~^ in[1];
assign B7 = ~in[0];
assign B8 = in[0];
assign B9 = in[0:1] && in[2:3];
assign B10 = in[0:1] || in[2:3];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module my_dff (
input d,
clk,
output reg q
);
always @(posedge clk) q <= d;
endmodule
module my_dffe (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
module my_dffr_p (
input d,
clk,
clr,
output reg q
);
always @(posedge clk or posedge clr)
if (clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffr_p_2 (
input d1,
input d2,
clk,
clr,
output reg q1,
output reg q2
);
always @(posedge clk or posedge clr)
if (clr) begin
q1 <= 1\'b0;
q2 <= 1\'b0;
end else begin
q1 <= d1;
q2 <= d2;
end
endmodule
module my_dffr_n (
input d,
clk,
clr,
output reg q
);
always @(posedge clk or negedge clr)
if (!clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffre_p (
input d,
clk,
clr,
en,
output reg q
);
always @(posedge clk or posedge clr)
if (clr) q <= 1\'b0;
else if (en) q <= d;
endmodule
module my_dffre_n (
input d,
clk,
clr,
en,
output reg q
);
always @(posedge clk or negedge clr)
if (!clr) q <= 1\'b0;
else if (en) q <= d;
endmodule
module my_dffs_p (
input d,
clk,
pre,
output reg q
);
always @(posedge clk or posedge pre)
if (pre) q <= 1\'b1;
else q <= d;
endmodule
module my_dffs_n (
input d,
clk,
pre,
output reg q
);
always @(posedge clk or negedge pre)
if (!pre) q <= 1\'b1;
else q <= d;
endmodule
module my_dffse_p (
input d,
clk,
pre,
en,
output reg q
);
always @(posedge clk or posedge pre)
if (pre) q <= 1\'b1;
else if (en) q <= d;
endmodule
module my_dffse_n (
input d,
clk,
pre,
en,
output reg q
);
always @(posedge clk or negedge pre)
if (!pre) q <= 1\'b1;
else if (en) q <= d;
endmodule
module my_dffn (
input d,
clk,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk) q <= d;
endmodule
module my_dffnr_p (
input d,
clk,
clr,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or posedge clr)
if (clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffnr_n (
input d,
clk,
clr,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or negedge clr)
if (!clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffns_p (
input d,
clk,
pre,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or posedge pre)
if (pre) q <= 1\'b1;
else q <= d;
endmodule
module my_dffns_n (
input d,
clk,
pre,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or negedge pre)
if (!pre) q <= 1\'b1;
else q <= d;
endmodule
module my_dffsr_ppp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1\'b0;
always @(posedge clk or posedge pre or posedge clr)
if (pre) q <= 1\'b1;
else if (clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffsr_pnp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1\'b0;
always @(posedge clk or negedge pre or posedge clr)
if (!pre) q <= 1\'b1;
else if (clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffsr_ppn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1\'b0;
always @(posedge clk or posedge pre or negedge clr)
if (pre) q <= 1\'b1;
else if (!clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffsr_pnn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1\'b0;
always @(posedge clk or negedge pre or negedge clr)
if (!pre) q <= 1\'b1;
else if (!clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffsr_npp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or posedge pre or posedge clr)
if (pre) q <= 1\'b1;
else if (clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffsr_nnp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or negedge pre or posedge clr)
if (!pre) q <= 1\'b1;
else if (clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffsr_npn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or posedge pre or negedge clr)
if (pre) q <= 1\'b1;
else if (!clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffsr_nnn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or negedge pre or negedge clr)
if (!pre) q <= 1\'b1;
else if (!clr) q <= 1\'b0;
else q <= d;
endmodule
module my_dffsre_ppp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1\'b0;
always @(posedge clk or posedge pre or posedge clr)
if (pre) q <= 1\'b1;
else if (clr) q <= 1\'b0;
else if (en) q <= d;
endmodule
module my_dffsre_pnp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1\'b0;
always @(posedge clk or negedge pre or posedge clr)
if (!pre) q <= 1\'b1;
else if (clr) q <= 1\'b0;
else if (en) q <= d;
endmodule
module my_dffsre_ppn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1\'b0;
always @(posedge clk or posedge pre or negedge clr)
if (pre) q <= 1\'b1;
else if (!clr) q <= 1\'b0;
else if (en) q <= d;
endmodule
module my_dffsre_pnn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1\'b0;
always @(posedge clk or negedge pre or negedge clr)
if (!pre) q <= 1\'b1;
else if (!clr) q <= 1\'b0;
else if (en) q <= d;
endmodule
module my_dffsre_npp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or posedge pre or posedge clr)
if (pre) q <= 1\'b1;
else if (clr) q <= 1\'b0;
else if (en) q <= d;
endmodule
module my_dffsre_nnp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or negedge pre or posedge clr)
if (!pre) q <= 1\'b1;
else if (clr) q <= 1\'b0;
else if (en) q <= d;
endmodule
module my_dffsre_npn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or posedge pre or negedge clr)
if (pre) q <= 1\'b1;
else if (!clr) q <= 1\'b0;
else if (en) q <= d;
endmodule
module my_dffsre_nnn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1\'b0;
always @(negedge clk or negedge pre or negedge clr)
if (!pre) q <= 1\'b1;
else if (!clr) q <= 1\'b0;
else if (en) q <= d;
endmodule
module my_sdffr_n (
input d,
clk,
clr,
output reg q
);
initial q <= 0;
always @(posedge clk)
if (!clr) q <= 1\'b0;
else q <= d;
endmodule
module my_sdffs_n (
input d,
clk,
pre,
output reg q
);
initial q <= 0;
always @(posedge clk)
if (!pre) q <= 1\'b1;
else q <= d;
endmodule
module my_sdffnr_n (
input d,
clk,
clr,
output reg q
);
initial q <= 0;
always @(negedge clk)
if (!clr) q <= 1\'b0;
else q <= d;
endmodule
module my_sdffns_n(
input d,
clk,
pre,
output reg q
);
initial q <= 0;
always @(negedge clk)
if (!pre) q <= 1\'b1;
else q <= d;
endmodule
module my_sdffr_p (
input d,
clk,
clr,
output reg q
);
initial q <= 0;
always @(posedge clk)
if (clr) q <= 1\'b0;
else q <= d;
endmodule
module my_sdffs_p (
input d,
clk,
pre,
output reg q
);
initial q <= 0;
always @(posedge clk)
if (pre) q <= 1\'b1;
else q <= d;
endmodule
module my_sdffnr_p (
input d,
clk,
clr,
output reg q
);
initial q <= 0;
always @(negedge clk)
if (clr) q <= 1\'b0;
else q <= d;
endmodule
module my_sdffns_p (
input d,
clk,
pre,
output reg q
);
initial q <= 0;
always @(negedge clk)
if (pre) q <= 1\'b1;
else q <= d;
endmodule
module my_latch (
input wire d, g,
output reg q
);
always @(*)
if (g) q <= d;
endmodule
module my_latchn (
input wire d, g,
output reg q
);
always @(*)
if (!g) q <= d;
endmodule
module my_latchs_p (
input wire d, g, s,
output reg q
);
always @(*)
if (s)
q <= 1\'b1;
else if (g)
q <= d;
endmodule
module my_latchs_n (
input wire d, g, s,
output reg q
);
always @(*)
if (!s)
q <= 1\'b1;
else if (g)
q <= d;
endmodule
module my_latchr_p (
input wire d, g, r,
output reg q
);
always @(*)
if (r)
q <= 1\'b0;
else if (g)
q <= d;
endmodule
module my_latchr_n (
input wire d, g, r,
output reg q
);
always @(*)
if (!r)
q <= 1\'b0;
else if (g)
q <= d;
endmodule
module my_latchns_p (
input wire d, g, s,
output reg q
);
always @(*)
if (s)
q <= 1\'b1;
else if (!g)
q <= d;
endmodule
module my_latchns_n (
input wire d, g, s,
output reg q
);
always @(*)
if (!s)
q <= 1\'b1;
else if (!g)
q <= d;
endmodule
module my_latchnr_p (
input wire d, g, r,
output reg q
);
always @(*)
if (r)
q <= 1\'b0;
else if (!g)
q <= d;
endmodule
module my_latchnr_n (
input wire d, g, r,
output reg q
);
always @(*)
if (!r)
q <= 1\'b0;
else if (!g)
q <= d;
endmodule
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