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// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
module qlal4s3_mult_32x32_cell (
input [31:0] Amult,
input [31:0] Bmult,
input [ 1:0] Valid_mult,
output [63:0] Cmult
);
endmodule /* qlal4s3_32x32_mult_cell */
(* blackbox *)
module qlal4s3_mult_16x16_cell (
input [15:0] Amult,
input [15:0] Bmult,
input Valid_mult,
output [31:0] Cmult
);
endmodule /* qlal4s3_16x16_mult_cell */
/* Verilog model of QLAL4S3 Multiplier */
/*qlal4s3_mult_cell*/
module signed_mult (
A,
B,
Valid,
C
);
parameter WIDTH = 32;
parameter CWIDTH = 2 * WIDTH;
input [WIDTH-1:0] A, B;
input Valid;
output [CWIDTH-1:0] C;
reg signed [WIDTH-1:0] A_q, B_q;
wire signed [CWIDTH-1:0] C_int;
assign C_int = A_q * B_q;
assign valid_int = Valid;
assign C = C_int;
always @(*) if (valid_int == 1\'b1) A_q <= A;
always @(*) if (valid_int == 1\'b1) B_q <= B;
endmodule
module qlal4s3_mult_cell_macro (
Amult,
Bmult,
Valid_mult,
sel_mul_32x32,
Cmult
);
input [31:0] Amult;
input [31:0] Bmult;
input [1:0] Valid_mult;
input sel_mul_32x32;
output [63:0] Cmult;
wire [15:0] A_mult_16_0;
wire [15:0] B_mult_16_0;
wire [31:0] C_mult_16_0;
wire [15:0] A_mult_16_1;
wire [15:0] B_mult_16_1;
wire [31:0] C_mult_16_1;
wire [31:0] A_mult_32;
wire [31:0] B_mult_32;
wire [63:0] C_mult_32;
wire Valid_mult_16_0;
wire Valid_mult_16_1;
wire Valid_mult_32;
assign Cmult = sel_mul_32x32 ? C_mult_32 : {C_mult_16_1, C_mult_16_0};
assign A_mult_16_0 = sel_mul_32x32 ? 16\'h0 : Amult[15:0];
assign B_mult_16_0 = sel_mul_32x32 ? 16\'h0 : Bmult[15:0];
assign A_mult_16_1 = sel_mul_32x32 ? 16\'h0 : Amult[31:16];
assign B_mult_16_1 = sel_mul_32x32 ? 16\'h0 : Bmult[31:16];
assign A_mult_32 = sel_mul_32x32 ? Amult : 32\'h0;
assign B_mult_32 = sel_mul_32x32 ? Bmult : 32\'h0;
assign Valid_mult_16_0 = sel_mul_32x32 ? 1\'b0 : Valid_mult[0];
assign Valid_mult_16_1 = sel_mul_32x32 ? 1\'b0 : Valid_mult[1];
assign Valid_mult_32 = sel_mul_32x32 ? Valid_mult[0] : 1\'b0;
signed_mult #(
.WIDTH(16)
) u_signed_mult_16_0 (
.A (A_mult_16_0), //I: 16 bits
.B (B_mult_16_0), //I: 16 bits
.Valid(Valid_mult_16_0), //I
.C (C_mult_16_0) //O: 32 bits
);
signed_mult #(
.WIDTH(16)
) u_signed_mult_16_1 (
.A (A_mult_16_1), //I: 16 bits
.B (B_mult_16_1), //I: 16 bits
.Valid(Valid_mult_16_1), //I
.C (C_mult_16_1) //O: 32 bits
);
signed_mult #(
.WIDTH(32)
) u_signed_mult_32 (
.A (A_mult_32), //I: 32 bits
.B (B_mult_32), //I: 32 bits
.Valid(Valid_mult_32), //I
.C (C_mult_32) //O: 64 bits
);
endmodule
/*qlal4s3_mult_cell*/
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
module box(
(* invertible_pin="INV_A" *)
input wire A,
output wire Y
);
parameter [0:0] INV_A = 1\'b0;
endmodule
(* keep_hierarchy *)
module child (
input wire I,
output wire [1:0] O
);
wire d;
\\$_NOT_ n (.A(I), .Y(d));
box b0 (.A(I), .Y(O[0]));
box b1 (.A(d), .Y(O[1]));
endmodule
module top(
input wire di,
output wire [4:0] do
);
wire [1:0] d;
\\$_NOT_ n0 (.A(di), .Y(d[0]));
\\$_NOT_ n1 (.A(di), .Y(d[1]));
box b0 (.A(d[0]), .Y(do[0]));
box b1 (.A(d[1]), .Y(do[1]));
child c (.I(d[1]), .O({do[3], do[2]}));
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \\$_DFF_P_ (
D,
Q,
C
);
input D;
input C;
output Q;
dff _TECHMAP_REPLACE_ (
.Q (Q),
.D (D),
.CLK(C)
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* CLOCK_SIGNAL = "yes", PERIOD = "10", WAVEFORM = "bad value" *)
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[1:0] = {cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \\$__MUL16X16 (input [15:0] A, input [15:0] B, output [31:0] Y);
\tparameter A_SIGNED = 0;
\tparameter B_SIGNED = 0;
\tparameter A_WIDTH = 0;
\tparameter B_WIDTH = 0;
\tparameter Y_WIDTH = 0;
\tQL_DSP #(
\t\t.A_REG(1\'b0),
\t\t.B_REG(1\'b0),
\t\t.C_REG(1\'b0),
\t\t.D_REG(1\'b0),
\t\t.ENABLE_DSP(1\'b1),
\t) _TECHMAP_REPLACE_ (
\t\t.A(A),
\t\t.B(B),
\t\t.O(Y),
\t);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1\'bZ;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk1,
clk2,
output led1,
led2
);
reg [15:0] counter1 = 0;
reg [15:0] counter2 = 0;
assign led1 = counter1[15];
assign led2 = counter2[15];
always @(posedge clk1) counter1 <= counter1 + 1;
always @(posedge clk2) counter2 <= counter2 + 1;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[1:0] = {cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
// Basic DFF
module \\$_DFF_P_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1\'bx;
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
// Async reset
module \\$_DFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1\'bx;
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Async set
module \\$_DFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Async reset, enable
module \\$_DFFE_PP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1\'bx;
dffre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
endmodule
// Async set, enable
module \\$_DFFE_PP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1\'bx;
dffse _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(S));
endmodule
// Async set & reset
module \\$_DFFSR_PPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
// Async set, reset & enable
module \\$_DFFSRE_PPPP_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
// Latch with async set and reset
module \\$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1\'bx;
latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1\'b1), .G(E), .R(R), .S(S));
endmodule
// The following techmap operation are not performed right now
// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
// but in case we implement clock inversion in the future, the support is ready for it.
module \\$_DFF_N_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1\'bx;
dff #(.IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
module \\$_DFF_NP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1\'bx;
dffr #(.IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
module \\$_DFF_NP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffs #(.IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
module \\$_DFFE_NP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1\'bx;
dffre #(.IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
endmodule
module \\$_DFFE_NP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1\'bx;
dffse #(.IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(S));
endmodule
module \\$_DFFSR_NPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsr #(.IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
module \\$_DFFSRE_PPPP_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre #(.IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1\'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8
// Date : 16/06/2019, 23:18:37
// Component : VexRiscv
`define AluCtrlEnum_defaultEncoding_type [1:0]
`define AluCtrlEnum_defaultEncoding_ADD_SUB 2\'b00
`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2\'b01
`define AluCtrlEnum_defaultEncoding_BITWISE 2\'b10
`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2\'b00
`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2\'b01
`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2\'b10
`define Src2CtrlEnum_defaultEncoding_type [1:0]
`define Src2CtrlEnum_defaultEncoding_RS 2\'b00
`define Src2CtrlEnum_defaultEncoding_IMI 2\'b01
`define Src2CtrlEnum_defaultEncoding_IMS 2\'b10
`define Src2CtrlEnum_defaultEncoding_PC 2\'b11
`define BranchCtrlEnum_defaultEncoding_type [1:0]
`define BranchCtrlEnum_defaultEncoding_INC 2\'b00
`define BranchCtrlEnum_defaultEncoding_B 2\'b01
`define BranchCtrlEnum_defaultEncoding_JAL 2\'b10
`define BranchCtrlEnum_defaultEncoding_JALR 2\'b11
`define Src1CtrlEnum_defaultEncoding_type [1:0]
`define Src1CtrlEnum_defaultEncoding_RS 2\'b00
`define Src1CtrlEnum_defaultEncoding_IMU 2\'b01
`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2\'b10
`define Src1CtrlEnum_defaultEncoding_URS1 2\'b11
`define EnvCtrlEnum_defaultEncoding_type [0:0]
`define EnvCtrlEnum_defaultEncoding_NONE 1\'b0
`define EnvCtrlEnum_defaultEncoding_XRET 1\'b1
`define ShiftCtrlEnum_defaultEncoding_type [1:0]
`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2\'b00
`define ShiftCtrlEnum_defaultEncoding_SLL_1 2\'b01
`define ShiftCtrlEnum_defaultEncoding_SRL_1 2\'b10
`define ShiftCtrlEnum_defaultEncoding_SRA_1 2\'b11
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input io_cpu_fetch_dataBypassValid,
input [31:0] io_cpu_fetch_dataBypass,
output io_cpu_fetch_mmuBus_cmd_isValid,
output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress,
output io_cpu_fetch_mmuBus_cmd_bypassTranslation,
input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress,
input io_cpu_fetch_mmuBus_rsp_isIoAccess,
input io_cpu_fetch_mmuBus_rsp_allowRead,
input io_cpu_fetch_mmuBus_rsp_allowWrite,
input io_cpu_fetch_mmuBus_rsp_allowExecute,
input io_cpu_fetch_mmuBus_rsp_exception,
input io_cpu_fetch_mmuBus_rsp_refilling,
output io_cpu_fetch_mmuBus_end,
input io_cpu_fetch_mmuBus_busy,
output [31:0] io_cpu_fetch_physicalAddress,
output io_cpu_fetch_haltIt,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset);
reg [22:0] _zz_10_;
reg [31:0] _zz_11_;
wire _zz_12_;
wire _zz_13_;
wire [0:0] _zz_14_;
wire [0:0] _zz_15_;
wire [22:0] _zz_16_;
reg _zz_1_;
reg _zz_2_;
reg lineLoader_fire;
reg lineLoader_valid;
reg [31:0] lineLoader_address;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [6:0] lineLoader_flushCounter;
reg _zz_3_;
reg lineLoader_cmdSent;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
reg [2:0] lineLoader_wordIndex;
wire lineLoader_write_tag_0_valid;
wire [5:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [20:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [8:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire _zz_4_;
wire [5:0] _zz_5_;
wire _zz_6_;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [20:0] fetchStage_read_waysValues_0_tag_address;
wire [22:0] _zz_7_;
wire [8:0] _zz_8_;
wire _zz_9_;
wire [31:0] fetchStage_read_waysValues_0_data;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
reg [31:0] io_cpu_fetch_data_regNextWhen;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_hit_valid;
reg decodeStage_hit_error;
(* ram_style = "block" *) reg [22:0] ways_0_tags [0:63];
(* ram_style = "block" *) reg [31:0] ways_0_datas [0:511];
assign _zz_12_ = (! lineLoader_flushCounter[6]);
assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign _zz_14_ = _zz_7_[0 : 0];
assign _zz_15_ = _zz_7_[1 : 1];
assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @ (posedge clk) begin
if(_zz_2_) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_;
end
end
always @ (posedge clk) begin
if(_zz_6_) begin
_zz_10_ <= ways_0_tags[_zz_5_];
end
end
always @ (posedge clk) begin
if(_zz_1_) begin
ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @ (posedge clk) begin
if(_zz_9_) begin
_zz_11_ <= ways_0_datas[_zz_8_];
end
end
always @ (*) begin
_zz_1_ = 1\'b0;
if(lineLoader_write_data_0_valid)begin
_zz_1_ = 1\'b1;
end
end
always @ (*) begin
_zz_2_ = 1\'b0;
if(lineLoader_write_tag_0_valid)begin
_zz_2_ = 1\'b1;
end
end
assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy;
always @ (*) begin
lineLoader_fire = 1\'b0;
if(io_mem_rsp_valid)begin
if((lineLoader_wordIndex == (3\'b111)))begin
lineLoader_fire = 1\'b1;
end
end
end
always @ (*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(_zz_12_)begin
io_cpu_prefetch_haltIt = 1\'b1;
end
if((! _zz_3_))begin
io_cpu_prefetch_haltIt = 1\'b1;
end
if(io_flush)begin
io_cpu_prefetch_haltIt = 1\'b1;
end
end
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5\'b00000)};
assign io_mem_cmd_payload_size = (3\'b101);
always @ (*) begin
lineLoader_wayToAllocate_willIncrement = 1\'b0;
if((! lineLoader_valid))begin
lineLoader_wayToAllocate_willIncrement = 1\'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1\'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1\'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign _zz_4_ = 1\'b1;
assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign _zz_5_ = io_cpu_prefetch_pc[10 : 5];
assign _zz_6_ = (! io_cpu_fetch_isStuck);
assign _zz_7_ = _zz_10_;
assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0];
assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2];
assign _zz_8_ = io_cpu_prefetch_pc[10 : 2];
assign _zz_9_ = (! io_cpu_fetch_isStuck);
assign fetchStage_read_waysValues_0_data = _zz_11_;
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1\'b0));
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_waysValues_0_data;
assign fetchStage_hit_word = fetchStage_hit_data[31 : 0];
assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid;
assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc;
assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1\'b0;
assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved);
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress;
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = decodeStage_hit_error;
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @ (posedge clk) begin
if(reset) begin
lineLoader_valid <= 1\'b0;
lineLoader_hadError <= 1\'b0;
lineLoader_flushPending <= 1\'b1;
lineLoader_cmdSent <= 1\'b0;
lineLoader_wordIndex <= (3\'b000);
end else begin
if(lineLoader_fire)begin
lineLoader_valid <= 1\'b0;
end
if(lineLoader_fire)begin
lineLoader_hadError <= 1\'b0;
end
if(io_cpu_fill_valid)begin
lineLoader_valid <= 1\'b1;
end
if(io_flush)begin
lineLoader_flushPending <= 1\'b1;
end
if(_zz_13_)begin
lineLoader_flushPending <= 1\'b0;
end
if((io_mem_cmd_valid && io_mem_cmd_ready))begin
lineLoader_cmdSent <= 1\'b1;
end
if(lineLoader_fire)begin
lineLoader_cmdSent <= 1\'b0;
end
if(io_mem_rsp_valid)begin
lineLoader_wordIndex <= (lineLoader_wordIndex + (3\'b001));
if(io_mem_rsp_payload_error)begin
lineLoader_hadError <= 1\'b1;
end
end
end
end
always @ (posedge clk) begin
if(io_cpu_fill_valid)begin
lineLoader_address <= io_cpu_fill_payload;
end
if(_zz_12_)begin
lineLoader_flushCounter <= (lineLoader_flushCounter + (7\'b0000001));
end
_zz_3_ <= lineLoader_flushCounter[6];
if(_zz_13_)begin
lineLoader_flushCounter <= (7\'b0000000);
end
if((! io_cpu_decode_isStuck))begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if((! io_cpu_decode_isStuck))begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling;
end
if((! io_cpu_decode_isStuck))begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if((! io_cpu_decode_isStuck))begin
decodeStage_hit_error <= fetchStage_hit_error;
end
end
endmodule
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [1:0] iBusWishbone_BTE,
output [2:0] iBusWishbone_CTI,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output reg [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [1:0] dBusWishbone_BTE,
output [2:0] dBusWishbone_CTI,
input clk,
input reset);
wire _zz_205_;
wire _zz_206_;
wire _zz_207_;
wire _zz_208_;
wire [31:0] _zz_209_;
wire _zz_210_;
wire _zz_211_;
wire _zz_212_;
reg _zz_213_;
reg [31:0] _zz_214_;
reg [31:0] _zz_215_;
reg [31:0] _zz_216_;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt;
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire _zz_217_;
wire _zz_218_;
wire _zz_219_;
wire _zz_220_;
wire _zz_221_;
wire _zz_222_;
wire _zz_223_;
wire _zz_224_;
wire _zz_225_;
wire _zz_226_;
wire _zz_227_;
wire _zz_228_;
wire _zz_229_;
wire _zz_230_;
wire _zz_231_;
wire _zz_232_;
wire _zz_233_;
wire _zz_234_;
wire _zz_235_;
wire [1:0] _zz_236_;
wire _zz_237_;
wire _zz_238_;
wire _zz_239_;
wire _zz_240_;
wire _zz_241_;
wire _zz_242_;
wire _zz_243_;
wire _zz_244_;
wire _zz_245_;
wire _zz_246_;
wire _zz_247_;
wire _zz_248_;
wire _zz_249_;
wire _zz_250_;
wire _zz_251_;
wire _zz_252_;
wire [1:0] _zz_253_;
wire _zz_254_;
wire [4:0] _zz_255_;
wire [2:0] _zz_256_;
wire [31:0] _zz_257_;
wire [11:0] _zz_258_;
wire [31:0] _zz_259_;
wire [19:0] _zz_260_;
wire [11:0] _zz_261_;
wire [31:0] _zz_262_;
wire [31:0] _zz_263_;
wire [19:0] _zz_264_;
wire [11:0] _zz_265_;
wire [2:0] _zz_266_;
wire [0:0] _zz_267_;
wire [0:0] _zz_268_;
wire [0:0] _zz_269_;
wire [0:0] _zz_270_;
wire [0:0] _zz_271_;
wire [0:0] _zz_272_;
wire [0:0] _zz_273_;
wire [0:0] _zz_274_;
wire [0:0] _zz_275_;
wire [0:0] _zz_276_;
wire [0:0] _zz_277_;
wire [0:0] _zz_278_;
wire [0:0] _zz_279_;
wire [0:0] _zz_280_;
wire [0:0] _zz_281_;
wire [0:0] _zz_282_;
wire [0:0] _zz_283_;
wire [2:0] _zz_284_;
wire [4:0] _zz_285_;
wire [11:0] _zz_286_;
wire [11:0] _zz_287_;
wire [31:0] _zz_288_;
wire [31:0] _zz_289_;
wire [31:0] _zz_290_;
wire [31:0] _zz_291_;
wire [31:0] _zz_292_;
wire [31:0] _zz_293_;
wire [31:0] _zz_294_;
wire [31:0] _zz_295_;
wire [32:0] _zz_296_;
wire [11:0] _zz_297_;
wire [19:0] _zz_298_;
wire [11:0] _zz_299_;
wire [31:0] _zz_300_;
wire [31:0] _zz_301_;
wire [31:0] _zz_302_;
wire [11:0] _zz_303_;
wire [19:0] _zz_304_;
wire [11:0] _zz_305_;
wire [2:0] _zz_306_;
wire [1:0] _zz_307_;
wire [1:0] _zz_308_;
wire [1:0] _zz_309_;
wire [1:0] _zz_310_;
wire [0:0] _zz_311_;
wire [5:0] _zz_312_;
wire [33:0] _zz_313_;
wire [32:0] _zz_314_;
wire [33:0] _zz_315_;
wire [32:0] _zz_316_;
wire [33:0] _zz_317_;
wire [32:0] _zz_318_;
wire [0:0] _zz_319_;
wire [5:0] _zz_320_;
wire [32:0] _zz_321_;
wire [32:0] _zz_322_;
wire [31:0] _zz_323_;
wire [31:0] _zz_324_;
wire [32:0] _zz_325_;
wire [32:0] _zz_326_;
wire [32:0] _zz_327_;
wire [0:0] _zz_328_;
wire [32:0] _zz_329_;
wire [0:0] _zz_330_;
wire [32:0] _zz_331_;
wire [0:0] _zz_332_;
wire [31:0] _zz_333_;
wire [0:0] _zz_334_;
wire [0:0] _zz_335_;
wire [0:0] _zz_336_;
wire [0:0] _zz_337_;
wire [0:0] _zz_338_;
wire [0:0] _zz_339_;
wire [26:0] _zz_340_;
wire [6:0] _zz_341_;
wire _zz_342_;
wire _zz_343_;
wire [2:0] _zz_344_;
wire _zz_345_;
wire _zz_346_;
wire _zz_347_;
wire _zz_348_;
wire [0:0] _zz_349_;
wire [0:0] _zz_350_;
wire [0:0] _zz_351_;
wire [0:0] _zz_352_;
wire _zz_353_;
wire [0:0] _zz_354_;
wire [23:0] _zz_355_;
wire [31:0] _zz_356_;
wire [31:0] _zz_357_;
wire _zz_358_;
wire [0:0] _zz_359_;
wire [0:0] _zz_360_;
wire [0:0] _zz_361_;
wire [0:0] _zz_362_;
wire [1:0] _zz_363_;
wire [1:0] _zz_364_;
wire _zz_365_;
wire [0:0] _zz_366_;
wire [20:0] _zz_367_;
wire [31:0] _zz_368_;
wire [31:0] _zz_369_;
wire [31:0] _zz_370_;
wire [31:0] _zz_371_;
wire _zz_372_;
wire [0:0] _zz_373_;
wire [1:0] _zz_374_;
wire [0:0] _zz_375_;
wire [0:0] _zz_376_;
wire _zz_377_;
wire [0:0] _zz_378_;
wire [17:0] _zz_379_;
wire [31:0] _zz_380_;
wire [31:0] _zz_381_;
wire [31:0] _zz_382_;
wire [31:0] _zz_383_;
wire [31:0] _zz_384_;
wire [31:0] _zz_385_;
wire [31:0] _zz_386_;
wire [31:0] _zz_387_;
wire [0:0] _zz_388_;
wire [0:0] _zz_389_;
wire [5:0] _zz_390_;
wire [5:0] _zz_391_;
wire _zz_392_;
wire [0:0] _zz_393_;
wire [14:0] _zz_394_;
wire [31:0] _zz_395_;
wire [31:0] _zz_396_;
wire _zz_397_;
wire [0:0] _zz_398_;
wire [2:0] _zz_399_;
wire _zz_400_;
wire _zz_401_;
wire [0:0] _zz_402_;
wire [2:0] _zz_403_;
wire [0:0] _zz_404_;
wire [0:0] _zz_405_;
wire _zz_406_;
wire [0:0] _zz_407_;
wire [11:0] _zz_408_;
wire [31:0] _zz_409_;
wire [31:0] _zz_410_;
wire [31:0] _zz_411_;
wire _zz_412_;
wire [0:0] _zz_413_;
wire [0:0] _zz_414_;
wire [31:0] _zz_415_;
wire [31:0] _zz_416_;
wire [31:0] _zz_417_;
wire [31:0] _zz_418_;
wire _zz_419_;
wire [0:0] _zz_420_;
wire [0:0] _zz_421_;
wire [31:0] _zz_422_;
wire [31:0] _zz_423_;
wire [0:0] _zz_424_;
wire [0:0] _zz_425_;
wire [0:0] _zz_426_;
wire [0:0] _zz_427_;
wire _zz_428_;
wire [0:0] _zz_429_;
wire [9:0] _zz_430_;
wire [31:0] _zz_431_;
wire [31:0] _zz_432_;
wire [31:0] _zz_433_;
wire [31:0] _zz_434_;
wire [31:0] _zz_435_;
wire [31:0] _zz_436_;
wire [31:0] _zz_437_;
wire [31:0] _zz_438_;
wire [31:0] _zz_439_;
wire [31:0] _zz_440_;
wire [31:0] _zz_441_;
wire [31:0] _zz_442_;
wire [31:0] _zz_443_;
wire [31:0] _zz_444_;
wire _zz_445_;
wire [0:0] _zz_446_;
wire [0:0] _zz_447_;
wire _zz_448_;
wire [0:0] _zz_449_;
wire [7:0] _zz_450_;
wire _zz_451_;
wire [0:0] _zz_452_;
wire [0:0] _zz_453_;
wire [0:0] _zz_454_;
wire [0:0] _zz_455_;
wire [0:0] _zz_456_;
wire [0:0] _zz_457_;
wire _zz_458_;
wire [0:0] _zz_459_;
wire [3:0] _zz_460_;
wire [31:0] _zz_461_;
wire [31:0] _zz_462_;
wire [31:0] _zz_463_;
wire [31:0] _zz_464_;
wire [31:0] _zz_465_;
wire _zz_466_;
wire _zz_467_;
wire [0:0] _zz_468_;
wire [1:0] _zz_469_;
wire [2:0] _zz_470_;
wire [2:0] _zz_471_;
wire _zz_472_;
wire [0:0] _zz_473_;
wire [0:0] _zz_474_;
wire [31:0] _zz_475_;
wire [31:0] _zz_476_;
wire [31:0] _zz_477_;
wire [31:0] _zz_478_;
wire [31:0] _zz_479_;
wire _zz_480_;
wire _zz_481_;
wire [31:0] _zz_482_;
wire [31:0] _zz_483_;
wire [0:0] _zz_484_;
wire [0:0] _zz_485_;
wire _zz_486_;
wire [31:0] _zz_487_;
wire [31:0] _zz_488_;
wire [31:0] _zz_489_;
wire _zz_490_;
wire [0:0] _zz_491_;
wire [10:0] _zz_492_;
wire [31:0] _zz_493_;
wire [31:0] _zz_494_;
wire [31:0] _zz_495_;
wire _zz_496_;
wire [0:0] _zz_497_;
wire [4:0] _zz_498_;
wire [31:0] _zz_499_;
wire [31:0] _zz_500_;
wire [31:0] _zz_501_;
wire [31:0] _zz_502_;
wire [31:0] _zz_503_;
wire _zz_504_;
wire _zz_505_;
wire _zz_506_;
wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
wire `AluCtrlEnum_defaultEncoding_type _zz_1_;
wire `AluCtrlEnum_defaultEncoding_type _zz_2_;
wire `AluCtrlEnum_defaultEncoding_type _zz_3_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_;
wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_defaultEncoding_type _zz_7_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_8_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_9_;
wire decode_IS_RS2_SIGNED;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire decode_IS_RS1_SIGNED;
wire decode_CSR_READ_OPCODE;
wire decode_IS_DIV;
wire [1:0] memory_MEMORY_ADDRESS_LOW;
wire [1:0] execute_MEMORY_ADDRESS_LOW;
wire decode_IS_MUL;
wire [31:0] execute_BRANCH_CALC;
wire `BranchCtrlEnum_defaultEncoding_type _zz_10_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_11_;
wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_defaultEncoding_type _zz_12_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_13_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_14_;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_SRC2_FORCE_ZERO;
wire decode_CSR_WRITE_OPCODE;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire execute_BRANCH_DO;
wire decode_SRC_LESS_UNSIGNED;
wire `EnvCtrlEnum_defaultEncoding_type _zz_15_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_16_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_17_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_18_;
wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_19_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_20_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_21_;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire decode_MEMORY_STORE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_IS_CSR;
wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_24_;
wire [31:0] memory_MEMORY_READ_DATA;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_MUL;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire memory_IS_MUL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_25_;
wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_26_;
wire _zz_27_;
wire _zz_28_;
wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_29_;
wire [31:0] memory_BRANCH_CALC;
wire memory_BRANCH_DO;
wire [31:0] _zz_30_;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
wire _zz_31_;
wire [31:0] execute_RS1;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_defaultEncoding_type _zz_32_;
wire _zz_33_;
wire _zz_34_;
wire decode_RS2_USE;
wire decode_RS1_USE;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
reg [31:0] _zz_35_;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
reg [31:0] _zz_36_;
wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_37_;
wire _zz_38_;
wire [31:0] _zz_39_;
wire [31:0] _zz_40_;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_41_;
wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_defaultEncoding_type _zz_42_;
wire [31:0] _zz_43_;
wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_defaultEncoding_type _zz_44_;
wire [31:0] _zz_45_;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire _zz_46_;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
wire `AluCtrlEnum_defaultEncoding_type _zz_47_;
wire [31:0] _zz_48_;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_49_;
wire [31:0] _zz_50_;
wire _zz_51_;
reg _zz_52_;
wire [31:0] _zz_53_;
wire [31:0] _zz_54_;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire decode_INSTRUCTION_READY;
wire _zz_55_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_56_;
wire _zz_57_;
wire _zz_58_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_59_;
wire _zz_60_;
wire _zz_61_;
wire _zz_62_;
wire _zz_63_;
wire _zz_64_;
wire _zz_65_;
wire _zz_66_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_67_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_68_;
wire _zz_69_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_70_;
wire _zz_71_;
wire `AluCtrlEnum_defaultEncoding_type _zz_72_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_73_;
wire _zz_74_;
wire _zz_75_;
wire _zz_76_;
wire _zz_77_;
wire _zz_78_;
wire writeBack_MEMORY_STORE;
reg [31:0] _zz_79_;
wire writeBack_MEMORY_ENABLE;
wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
wire [31:0] writeBack_MEMORY_READ_DATA;
wire memory_MMU_FAULT;
wire [31:0] memory_MMU_RSP_physicalAddress;
wire memory_MMU_RSP_isIoAccess;
wire memory_MMU_RSP_allowRead;
wire memory_MMU_RSP_allowWrite;
wire memory_MMU_RSP_allowExecute;
wire memory_MMU_RSP_exception;
wire memory_MMU_RSP_refilling;
wire [31:0] memory_PC;
wire memory_ALIGNEMENT_FAULT;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_STORE;
wire memory_MEMORY_ENABLE;
wire [31:0] _zz_80_;
wire [31:0] _zz_81_;
wire _zz_82_;
wire _zz_83_;
wire _zz_84_;
wire _zz_85_;
wire _zz_86_;
wire _zz_87_;
wire execute_MMU_FAULT;
wire [31:0] execute_MMU_RSP_physicalAddress;
wire execute_MMU_RSP_isIoAccess;
wire execute_MMU_RSP_allowRead;
wire execute_MMU_RSP_allowWrite;
wire execute_MMU_RSP_allowExecute;
wire execute_MMU_RSP_exception;
wire execute_MMU_RSP_refilling;
wire _zz_88_;
wire [31:0] execute_SRC_ADD;
wire [1:0] _zz_89_;
wire [31:0] execute_RS2;
wire [31:0] execute_INSTRUCTION;
wire execute_MEMORY_STORE;
wire execute_MEMORY_ENABLE;
wire execute_ALIGNEMENT_FAULT;
wire _zz_90_;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected;
reg _zz_91_;
reg _zz_92_;
reg _zz_93_;
wire [31:0] _zz_94_;
wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_defaultEncoding_type _zz_95_;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_96_;
reg [31:0] _zz_97_;
wire [31:0] decode_PC;
wire [31:0] _zz_98_;
wire [31:0] _zz_99_;
wire [31:0] _zz_100_;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
wire execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
wire execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
reg memory_arbitration_flushIt;
reg memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
wire writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
wire writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_fetcherflushIt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* syn_keep , keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
wire IBusCachedPlugin_redoBranch_valid;
wire [31:0] IBusCachedPlugin_redoBranch_payload;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_isValid;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
reg DBusSimplePlugin_memoryExceptionPort_valid;
reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code;
wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr;
wire DBusSimplePlugin_mmuBus_cmd_isValid;
wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress;
wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation;
wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress;
wire DBusSimplePlugin_mmuBus_rsp_isIoAccess;
wire DBusSimplePlugin_mmuBus_rsp_allowRead;
wire DBusSimplePlugin_mmuBus_rsp_allowWrite;
wire DBusSimplePlugin_mmuBus_rsp_allowExecute;
wire DBusSimplePlugin_mmuBus_rsp_exception;
wire DBusSimplePlugin_mmuBus_rsp_refilling;
wire DBusSimplePlugin_mmuBus_end;
wire DBusSimplePlugin_mmuBus_busy;
reg DBusSimplePlugin_redoBranch_valid;
wire [31:0] DBusSimplePlugin_redoBranch_payload;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
wire BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [4:0] _zz_101_;
wire [4:0] _zz_102_;
wire _zz_103_;
wire _zz_104_;
wire _zz_105_;
wire _zz_106_;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_0_inputSample;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_inputSample;
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid;
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt;
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample;
wire _zz_107_;
wire _zz_108_;
wire _zz_109_;
wire _zz_110_;
wire _zz_111_;
reg _zz_112_;
wire _zz_113_;
reg _zz_114_;
reg [31:0] _zz_115_;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_decodeInput_valid;
wire IBusCachedPlugin_iBusRsp_decodeInput_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc;
wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
reg IBusCachedPlugin_injector_decodeRemoved;
wire _zz_116_;
reg [18:0] _zz_117_;
wire _zz_118_;
reg [10:0] _zz_119_;
wire _zz_120_;
reg [18:0] _zz_121_;
reg _zz_122_;
wire _zz_123_;
reg [10:0] _zz_124_;
wire _zz_125_;
reg [18:0] _zz_126_;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_127_;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
reg IBusCachedPlugin_rsp_redoFetch;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [1:0] dBus_cmd_payload_size;
wire dBus_rsp_ready;
wire dBus_rsp_error;
wire [31:0] dBus_rsp_data;
wire _zz_128_;
reg execute_DBusSimplePlugin_skipCmd;
reg [31:0] _zz_129_;
reg [3:0] _zz_130_;
wire [3:0] execute_DBusSimplePlugin_formalMask;
reg [31:0] writeBack_DBusSimplePlugin_rspShifted;
wire _zz_131_;
reg [31:0] _zz_132_;
wire _zz_133_;
reg [31:0] _zz_134_;
reg [31:0] writeBack_DBusSimplePlugin_rspFormated;
wire [29:0] _zz_135_;
wire _zz_136_;
wire _zz_137_;
wire _zz_138_;
wire _zz_139_;
wire _zz_140_;
wire _zz_141_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_142_;
wire `AluCtrlEnum_defaultEncoding_type _zz_143_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_144_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_145_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_146_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_147_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_148_;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_149_;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_150_;
reg [31:0] _zz_151_;
wire _zz_152_;
reg [19:0] _zz_153_;
wire _zz_154_;
reg [19:0] _zz_155_;
reg [31:0] _zz_156_;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
reg execute_LightShifterPlugin_isActive;
wire execute_LightShifterPlugin_isShift;
reg [4:0] execute_LightShifterPlugin_amplitudeReg;
wire [4:0] execute_LightShifterPlugin_amplitude;
wire [31:0] execute_LightShifterPlugin_shiftInput;
wire execute_LightShifterPlugin_done;
reg [31:0] _zz_157_;
reg _zz_158_;
reg _zz_159_;
wire _zz_160_;
reg _zz_161_;
reg [4:0] _zz_162_;
reg [31:0] _zz_163_;
wire _zz_164_;
wire _zz_165_;
wire _zz_166_;
wire _zz_167_;
wire _zz_168_;
wire _zz_169_;
wire execute_BranchPlugin_eq;
wire [2:0] _zz_170_;
reg _zz_171_;
reg _zz_172_;
wire _zz_173_;
reg [19:0] _zz_174_;
wire _zz_175_;
reg [10:0] _zz_176_;
wire _zz_177_;
reg [18:0] _zz_178_;
reg _zz_179_;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_180_;
reg [19:0] _zz_181_;
wire _zz_182_;
reg [10:0] _zz_183_;
wire _zz_184_;
reg [18:0] _zz_185_;
wire [31:0] execute_BranchPlugin_branchAdder;
wire [1:0] CsrPlugin_misa_base;
wire [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64\'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64\'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_186_;
wire _zz_187_;
wire _zz_188_;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_189_;
wire _zz_190_;
wire [1:0] _zz_191_;
wire _zz_192_;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire CsrPlugin_exception;
wire CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_done;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire execute_CsrPlugin_inWfi /* verilator public */ ;
reg execute_CsrPlugin_wfiWake;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
reg [31:0] execute_CsrPlugin_readData;
wire execute_CsrPlugin_writeInstruction;
wire execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
reg [31:0] execute_CsrPlugin_writeData;
wire [11:0] execute_CsrPlugin_csrAddress;
reg [32:0] memory_MulDivIterativePlugin_rs1;
reg [31:0] memory_MulDivIterativePlugin_rs2;
reg [64:0] memory_MulDivIterativePlugin_accumulator;
reg memory_MulDivIterativePlugin_mul_counter_willIncrement;
reg memory_MulDivIterativePlugin_mul_counter_willClear;
reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext;
reg [5:0] memory_MulDivIterativePlugin_mul_counter_value;
wire memory_MulDivIterativePlugin_mul_willOverflowIfInc;
wire memory_MulDivIterativePlugin_mul_counter_willOverflow;
reg memory_MulDivIterativePlugin_div_needRevert;
reg memory_MulDivIterativePlugin_div_counter_willIncrement;
reg memory_MulDivIterativePlugin_div_counter_willClear;
reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext;
reg [5:0] memory_MulDivIterativePlugin_div_counter_value;
wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc;
wire memory_MulDivIterativePlugin_div_counter_willOverflow;
reg memory_MulDivIterativePlugin_div_done;
reg [31:0] memory_MulDivIterativePlugin_div_result;
wire [31:0] _zz_193_;
wire [32:0] _zz_194_;
wire [32:0] _zz_195_;
wire [31:0] _zz_196_;
wire _zz_197_;
wire _zz_198_;
reg [32:0] _zz_199_;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_200_;
wire [31:0] _zz_201_;
reg [31:0] decode_to_execute_INSTRUCTION;
reg [31:0] execute_to_memory_INSTRUCTION;
reg [31:0] memory_to_writeBack_INSTRUCTION;
reg execute_to_memory_ALIGNEMENT_FAULT;
reg [31:0] memory_to_writeBack_MEMORY_READ_DATA;
reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
reg decode_to_execute_IS_CSR;
reg [31:0] decode_to_execute_PC;
reg [31:0] execute_to_memory_PC;
reg [31:0] memory_to_writeBack_PC;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
reg decode_to_execute_MEMORY_STORE;
reg execute_to_memory_MEMORY_STORE;
reg memory_to_writeBack_MEMORY_STORE;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL;
reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL;
reg decode_to_execute_REGFILE_WRITE_VALID;
reg execute_to_memory_REGFILE_WRITE_VALID;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
reg decode_to_execute_SRC_LESS_UNSIGNED;
reg execute_to_memory_BRANCH_DO;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
reg decode_to_execute_CSR_WRITE_OPCODE;
reg [31:0] decode_to_execute_RS1;
reg decode_to_execute_SRC2_FORCE_ZERO;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL;
reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
reg decode_to_execute_MEMORY_ENABLE;
reg execute_to_memory_MEMORY_ENABLE;
reg memory_to_writeBack_MEMORY_ENABLE;
reg decode_to_execute_SRC_USE_SUB_LESS;
reg execute_to_memory_MMU_FAULT;
reg [31:0] execute_to_memory_BRANCH_CALC;
reg [31:0] decode_to_execute_RS2;
reg decode_to_execute_IS_MUL;
reg execute_to_memory_IS_MUL;
reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
reg decode_to_execute_IS_DIV;
reg execute_to_memory_IS_DIV;
reg decode_to_execute_CSR_READ_OPCODE;
reg decode_to_execute_IS_RS1_SIGNED;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
reg [31:0] execute_to_memory_MMU_RSP_physicalAddress;
reg execute_to_memory_MMU_RSP_isIoAccess;
reg execute_to_memory_MMU_RSP_allowRead;
reg execute_to_memory_MMU_RSP_allowWrite;
reg execute_to_memory_MMU_RSP_allowExecute;
reg execute_to_memory_MMU_RSP_exception;
reg execute_to_memory_MMU_RSP_refilling;
reg decode_to_execute_IS_RS2_SIGNED;
reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL;
reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
reg [2:0] _zz_202_;
reg _zz_203_;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
wire dBus_cmd_halfPipe_valid;
wire dBus_cmd_halfPipe_ready;
wire dBus_cmd_halfPipe_payload_wr;
wire [31:0] dBus_cmd_halfPipe_payload_address;
wire [31:0] dBus_cmd_halfPipe_payload_data;
wire [1:0] dBus_cmd_halfPipe_payload_size;
reg dBus_cmd_halfPipe_regs_valid;
reg dBus_cmd_halfPipe_regs_ready;
reg dBus_cmd_halfPipe_regs_payload_wr;
reg [31:0] dBus_cmd_halfPipe_regs_payload_address;
reg [31:0] dBus_cmd_halfPipe_regs_payload_data;
reg [1:0] dBus_cmd_halfPipe_regs_payload_size;
reg [3:0] _zz_204_;
`ifndef SYNTHESIS
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_1__string;
reg [63:0] _zz_2__string;
reg [63:0] _zz_3__string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_4__string;
reg [39:0] _zz_5__string;
reg [39:0] _zz_6__string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_7__string;
reg [23:0] _zz_8__string;
reg [23:0] _zz_9__string;
reg [31:0] _zz_10__string;
reg [31:0] _zz_11__string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_12__string;
reg [95:0] _zz_13__string;
reg [95:0] _zz_14__string;
reg [31:0] _zz_15__string;
reg [31:0] _zz_16__string;
reg [31:0] _zz_17__string;
reg [31:0] _zz_18__string;
reg [31:0] decode_ENV_CTRL_string;
reg [31:0] _zz_19__string;
reg [31:0] _zz_20__string;
reg [31:0] _zz_21__string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_22__string;
reg [71:0] _zz_23__string;
reg [71:0] _zz_24__string;
reg [31:0] memory_ENV_CTRL_string;
reg [31:0] _zz_25__string;
reg [31:0] execute_ENV_CTRL_string;
reg [31:0] _zz_26__string;
reg [31:0] writeBack_ENV_CTRL_string;
reg [31:0] _zz_29__string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_32__string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_37__string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_42__string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_44__string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_47__string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_49__string;
reg [95:0] _zz_56__string;
reg [23:0] _zz_59__string;
reg [31:0] _zz_67__string;
reg [31:0] _zz_68__string;
reg [39:0] _zz_70__string;
reg [63:0] _zz_72__string;
reg [71:0] _zz_73__string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_95__string;
reg [71:0] _zz_142__string;
reg [63:0] _zz_143__string;
reg [39:0] _zz_144__string;
reg [31:0] _zz_145__string;
reg [31:0] _zz_146__string;
reg [23:0] _zz_147__string;
reg [95:0] _zz_148__string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_ENV_CTRL_string;
reg [31:0] execute_to_memory_ENV_CTRL_string;
reg [31:0] memory_to_writeBack_ENV_CTRL_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_217_ = (memory_arbitration_isValid && memory_IS_MUL);
assign _zz_218_ = (memory_arbitration_isValid && memory_IS_DIV);
assign _zz_219_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign _zz_220_ = 1\'b1;
assign _zz_221_ = (memory_arbitration_isValid && memory_'b'REGFILE_WRITE_VALID);
assign _zz_222_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign _zz_223_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5\'b00000)));
assign _zz_224_ = (execute_arbitration_isValid && execute_IS_CSR);
assign _zz_225_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_91_));
assign _zz_226_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_92_));
assign _zz_227_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_93_));
assign _zz_228_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1\'b0));
assign _zz_229_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2\'b00));
assign _zz_230_ = (! execute_arbitration_isStuckByOthers);
assign _zz_231_ = (! memory_MulDivIterativePlugin_mul_willOverflowIfInc);
assign _zz_232_ = (! memory_MulDivIterativePlugin_div_done);
assign _zz_233_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2\'b00));
assign _zz_234_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign _zz_235_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
assign _zz_236_ = writeBack_INSTRUCTION[29 : 28];
assign _zz_237_ = (! IBusCachedPlugin_iBusRsp_readyForError);
assign _zz_238_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE));
assign _zz_239_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1\'b1 || (! memory_arbitration_isStuckByOthers))));
assign _zz_240_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign _zz_241_ = (1\'b0 || (! 1\'b1));
assign _zz_242_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign _zz_243_ = (1\'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign _zz_244_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign _zz_245_ = (1\'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign _zz_246_ = (! memory_arbitration_isStuck);
assign _zz_247_ = (iBus_cmd_valid || (_zz_202_ != (3\'b000)));
assign _zz_248_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2\'b11)));
assign _zz_249_ = ((_zz_186_ && 1\'b1) && (! 1\'b0));
assign _zz_250_ = ((_zz_187_ && 1\'b1) && (! 1\'b0));
assign _zz_251_ = ((_zz_188_ && 1\'b1) && (! 1\'b0));
assign _zz_252_ = (! dBus_cmd_halfPipe_regs_valid);
assign _zz_253_ = writeBack_INSTRUCTION[13 : 12];
assign _zz_254_ = execute_INSTRUCTION[13];
assign _zz_255_ = (_zz_101_ - (5\'b00001));
assign _zz_256_ = {IBusCachedPlugin_fetchPc_inc,(2\'b00)};
assign _zz_257_ = {29\'d0, _zz_256_};
assign _zz_258_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_259_ = {{_zz_117_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1\'b0};
assign _zz_260_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz_261_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_262_ = {{_zz_119_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1\'b0};
assign _zz_263_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1\'b0};
assign _zz_264_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz_265_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_266_ = (memory_MEMORY_STORE ? (3\'b110) : (3\'b100));
assign _zz_267_ = _zz_135_[0 : 0];
assign _zz_268_ = _zz_135_[1 : 1];
assign _zz_269_ = _zz_135_[2 : 2];
assign _zz_270_ = _zz_135_[3 : 3];
assign _zz_271_ = _zz_135_[8 : 8];
assign _zz_272_ = _zz_135_[11 : 11];
assign _zz_273_ = _zz_135_[15 : 15];
assign _zz_274_ = _zz_135_[16 : 16];
assign _zz_275_ = _zz_135_[17 : 17];
assign _zz_276_ = _zz_135_[18 : 18];
assign _zz_277_ = _zz_135_[19 : 19];
assign _zz_278_ = _zz_135_[20 : 20];
assign _zz_279_ = _zz_135_[21 : 21];
assign _zz_280_ = _zz_135_[24 : 24];
assign _zz_281_ = _zz_135_[26 : 26];
assign _zz_282_ = _zz_135_[29 : 29];
assign _zz_283_ = execute_SRC_LESS;
assign _zz_284_ = (3\'b100);
assign _zz_285_ = execute_INSTRUCTION[19 : 15];
assign _zz_286_ = execute_INSTRUCTION[31 : 20];
assign _zz_287_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_288_ = ($signed(_zz_289_) + $signed(_zz_292_));
assign _zz_289_ = ($signed(_zz_290_) + $signed(_zz_291_));
assign _zz_290_ = execute_SRC1;
assign _zz_291_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_292_ = (execute_SRC_USE_SUB_LESS ? _zz_293_ : _zz_294_);
assign _zz_293_ = (32\'b00000000000000000000000000000001);
assign _zz_294_ = (32\'b00000000000000000000000000000000);
assign _zz_295_ = (_zz_296_ >>> 1);
assign _zz_296_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
assign _zz_297_ = execute_INSTRUCTION[31 : 20];
assign _zz_298_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz_299_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_300_ = {_zz_174_,execute_INSTRUCTION[31 : 20]};
assign _zz_301_ = {{_zz_176_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1\'b0};
assign _zz_302_ = {{_zz_178_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1\'b0};
assign _zz_303_ = execute_INSTRUCTION[31 : 20];
assign _zz_304_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz_305_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_306_ = (3\'b100);
assign _zz_307_ = (_zz_189_ & (~ _zz_308_));
assign _zz_308_ = (_zz_189_ - (2\'b01));
assign _zz_309_ = (_zz_191_ & (~ _zz_310_));
assign _zz_310_ = (_zz_191_ - (2\'b01));
assign _zz_311_ = memory_MulDivIterativePlugin_mul_counter_willIncrement;
assign _zz_312_ = {5\'d0, _zz_311_};
assign _zz_313_ = (_zz_315_ + _zz_317_);
assign _zz_314_ = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : (33\'b000000000000000000000000000000000));
assign _zz_315_ = {{1{_zz_314_[32]}}, _zz_314_};
assign _zz_316_ = _zz_318_;
assign _zz_317_ = {{1{_zz_316_[32]}}, _zz_316_};
assign _zz_318_ = (memory_MulDivIterativePlugin_accumulator >>> 32);
assign _zz_319_ = memory_MulDivIterativePlugin_div_counter_willIncrement;
assign _zz_320_ = {5\'d0, _zz_319_};
assign _zz_321_ = {1\'d0, memory_MulDivIterativePlugin_rs2};
assign _zz_322_ = {_zz_193_,(! _zz_195_[32])};
assign _zz_323_ = _zz_195_[31:0];
assign _zz_324_ = _zz_194_[31:0];
assign _zz_325_ = _zz_326_;
assign _zz_326_ = _zz_327_;
assign _zz_327_ = ({1\'b0,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_196_) : _zz_196_)} + _zz_329_);
assign _zz_328_ = memory_MulDivIterativePlugin_div_needRevert;
assign _zz_329_ = {32\'d0, _zz_328_};
assign _zz_330_ = _zz_198_;
assign _zz_331_ = {32\'d0, _zz_330_};
assign _zz_332_ = _zz_197_;
assign _zz_333_ = {31\'d0, _zz_332_};
assign _zz_334_ = execute_CsrPlugin_writeData[7 : 7];
assign _zz_335_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_336_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_337_ = execute_CsrPlugin_writeData[11 : 11];
assign _zz_338_ = execute_CsrPlugin_writeData[7 : 7];
assign _zz_339_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_340_ = (iBus_cmd_payload_address >>> 5);
assign _zz_341_ = ({3\'d0,_zz_204_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]);
assign _zz_342_ = 1\'b1;
assign _zz_343_ = 1\'b1;
assign _zz_344_ = {_zz_104_,{_zz_106_,_zz_105_}};
assign _zz_345_ = decode_INSTRUCTION[31];
assign _zz_346_ = decode_INSTRUCTION[31];
assign _zz_347_ = decode_INSTRUCTION[7];
assign _zz_348_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000000010100)) == (32\'b00000000000000000000000000000100));
assign _zz_349_ = ((decode_INSTRUCTION & _zz_356_) == (32\'b00000000000000000000000000000100));
assign _zz_350_ = _zz_141_;
assign _zz_351_ = ((decode_INSTRUCTION & _zz_357_) == (32\'b00000010000000000100000000100000));
assign _zz_352_ = (1\'b0);
assign _zz_353_ = ({_zz_358_,{_zz_359_,_zz_360_}} != (3\'b000));
assign _zz_354_ = ({_zz_361_,_zz_362_} != (2\'b00));
assign _zz_355_ = {(_zz_363_ != _zz_364_),{_zz_365_,{_zz_366_,_zz_367_}}};
assign _zz_356_ = (32\'b00000000000000000000000001000100);
assign _zz_357_ = (32\'b00000010000000000100000001100100);
assign _zz_358_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000001010000)) == (32\'b00000000000000000000000001000000));
assign _zz_359_ = ((decode_INSTRUCTION & _zz_368_) == (32\'b00000000000000000000000001000000));
assign _zz_360_ = ((decode_INSTRUCTION & _zz_369_) == (32\'b00000000000000000000000000000000));
assign _zz_361_ = _zz_140_;
assign _zz_362_ = _zz_139_;
assign _zz_363_ = {_zz_136_,(_zz_370_ == _zz_371_)};
assign _zz_364_ = (2\'b00);
assign _zz_365_ = ({_zz_136_,_zz_372_} != (2\'b00));
assign _zz_366_ = ({_zz_373_,_zz_374_} != (3\'b000));
assign _zz_367_ = {(_zz_375_ != _zz_376_),{_zz_377_,{_zz_378_,_zz_379_}}};
assign _zz_368_ = (32\'b00000000000000000011000001000000);
assign _zz_369_ = (32\'b00000000000000000000000000111000);
assign _zz_370_ = (decode_INSTRUCTION & (32\'b00000000000000000000000001110000));
assign _zz_371_ = (32\'b00000000000000000000000000100000);
assign _zz_372_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000000100000)) == (32\'b00000000000000000000000000000000));
assign _zz_373_ = ((decode_INSTRUCTION & _zz_380_) == (32\'b00000000000000000000000001000000));
assign _zz_374_ = {(_zz_381_ == _zz_382_),(_zz_383_ == _zz_384_)};
assign _zz_375_ = ((decode_INSTRUCTION & _zz_385_) == (32\'b00000000000000000000000000100000));
assign _zz_376_ = (1\'b0);
assign _zz_377_ = ((_zz_386_ == _zz_387_) != (1\'b0));
assign _zz_378_ = ({_zz_388_,_zz_389_} != (2\'b00));
assign _zz_379_ = {(_zz_390_ != _zz_391_),{_zz_392_,{_zz_393_,_zz_394_}}};
assign _zz_380_ = (32\'b00000000000000000000000001000100);
assign _zz_381_ = (decode_INSTRUCTION & (32\'b00000000000000000010000000010100));
assign _zz_382_ = (32\'b00000000000000000010000000010000);
assign _zz_383_ = (decode_INSTRUCTION & (32\'b01000000000000000100000000110100));
assign _zz_384_ = (32\'b01000000000000000000000000110000);
assign _zz_385_ = (32\'b00000000000000000000000000100000);
assign _zz_386_ = (decode_INSTRUCTION & (32\'b00000000000000000001000001001000));
assign _zz_387_ = (32\'b00000000000000000001000000001000);
assign _zz_388_ = ((decode_INSTRUCTION & _zz_395_) == (32\'b00000000000000000000000000100000));
assign _zz_389_ = ((decode_INSTRUCTION & _zz_396_) == (32\'b00000000000000000000000000100000));
assign _zz_390_ = {_zz_138_,{_zz_397_,{_zz_398_,_zz_399_}}};
assign _zz_391_ = (6\'b000000);
assign _zz_392_ = ({_zz_400_,_zz_401_} != (2\'b00));
assign _zz_393_ = ({_zz_402_,_zz_403_} != (4\'b0000));
assign _zz_394_ = {(_zz_404_ != _zz_405_),{_zz_406_,{_zz_407_,_zz_408_}}};
assign _zz_395_ = (32\'b00000000000000000000000000110100);
assign _zz_396_ = (32\'b00000000000000000000000001100100);
assign _zz_397_ = ((decode_INSTRUCTION & _zz_409_) == (32\'b00000000000000000001000000010000));
assign _zz_398_ = (_zz_410_ == _zz_411_);
assign _zz_399_ = {_zz_412_,{_zz_413_,_zz_414_}};
assign _zz_400_ = ((decode_INSTRUCTION & _zz_415_) == (32\'b00000000000000000010000000000000));
assign _zz_401_ = ((decode_INSTRUCTION & _zz_416_) == (32\'b00000000000000000001000000000000));
assign _zz_402_ = (_zz_417_ == _zz_418_);
assign _zz_403_ = {_zz_419_,{_zz_420_,_zz_421_}};
assign _zz_404_ = (_zz_422_ == _zz_423_);
assign _zz_405_ = (1\'b0);
assign _zz_406_ = ({_zz_424_,_zz_425_} != (2\'b00));
assign _zz_407_ = (_zz_426_ != _zz_427_);
assign _zz_408_ = {_zz_428_,{_zz_429_,_zz_430_}};
assign _zz_409_ = (32\'b00000000000000000001000000010000);
assign _zz_410_ = (decode_INSTRUCTION & (32\'b00000000000000000010000000010000));
assign _zz_411_ = (32\'b00000000000000000010000000010000);
assign _zz_412_ = ((decode_INSTRUCTION & _zz_431_) == (32\'b00000000000000000000000000010000));
assign _zz_413_ = (_zz_432_ == _zz_433_);
assign _zz_414_ = (_zz_434_ == _zz_435_);
assign _zz_415_ = (32\'b00000000000000000010000000010000);
assign _zz_416_ = (32\'b00000000000000000101000000000000);
assign _zz_417_ = (decode_INSTRUCTION & (32\'b00000000000000000000000001000100));
assign _zz_418_ = (32\'b00000000000000000000000000000000);
assign _zz_419_ = ((decode_INSTRUCTION & _zz_436_) == (32\'b00000000000000000000000000000000));
assign _zz_420_ = (_zz_437_ == _zz_438_);
assign _zz_421_ = (_zz_439_ == _zz_440_);
assign _zz_422_ = (decode_INSTRUCTION & (32\'b00000000000000000011000001010000));
assign _zz_423_ = (32\'b00000000000000000000000001010000);
assign _zz_424_ = _zz_138_;
assign _zz_425_ = (_zz_441_ == _zz_442_);
assign _zz_426_ = (_zz_443_ == _zz_444_);
assign _zz_427_ = (1\'b0);
assign _zz_428_ = (_zz_445_ != (1\'b0));
assign _zz_429_ = (_zz_446_ != _zz_447_);
assign _zz_430_ = {_zz_448_,{_zz_449_,_zz_450_}};
assign _zz_431_ = (32\'b00000000000000000000000001010000);
assign _zz_432_ = (decode_INSTRUCTION & (32\'b00000000000000000000000000001100));
assign _zz_433_ = (32\'b00000000000000000000000000000100);
assign _zz_434_ = (decode_INSTRUCTION & (32\'b00000000000000000000000000101000));
assign _zz_435_ = (32\'b00000000000000000000000000000000);
assign _zz_436_ = (32\'b00000000000000000000000000011000);
assign _zz_437_ = (decode_INSTRUCTION & (32\'b00000000000000000110000000000100));
assign _zz_438_ = (32\'b00000000000000000010000000000000);
assign _zz_439_ = (decode_INSTRUCTION & (32\'b00000000000000000101000000000100));
assign _zz_440_ = (32\'b00000000000000000001000000000000);
assign _zz_441_ = (decode_INSTRUCTION & (32\'b00000000000000000000000000011100));
assign _zz_442_ = (32\'b00000000000000000000000000000100);
assign _zz_443_ = (decode_INSTRUCTION & (32\'b00000000000000000000000001011000));
assign _zz_444_ = (32\'b00000000000000000000000001000000);
assign _zz_445_ = ((decode_INSTRUCTION & (32\'b00000010000000000100000001110100)) == (32\'b00000010000000000000000000110000));
assign _zz_446_ = ((decode_INSTRUCTION & (32\'b00000000000000000001000000000000)) == (32\'b00000000000000000001000000000000));
assign _zz_447_ = (1\'b0);
assign _zz_448_ = (_zz_137_ != (1\'b0));
assign _zz_449_ = ({_zz_451_,{_zz_452_,_zz_453_}} != (3\'b000));
assign _zz_450_ = {({_zz_454_,_zz_455_} != (2\'b00)),{(_zz_456_ != _zz_457_),{_zz_458_,{_zz_459_,_zz_460_}}}};
assign _zz_451_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000001100100)) == (32\'b00000000000000000000000000100100));
assign _zz_452_ = ((decode_INSTRUCTION & _zz_461_) == (32\'b00000000000000000001000000010000));
assign _zz_453_ = ((decode_INSTRUCTION & _zz_462_) == (32\'b00000000000000000001000000010000));
assign _zz_454_ = ((decode_INSTRUCTION & _zz_463_) == (32\'b00000000000000000110000000010000));
assign _zz_455_ = ((decode_INSTRUCTION & _zz_464_) == (32\'b00000000000000000100000000010000));
assign _zz_456_ = ((decode_INSTRUCTION & _zz_465_) == (32\'b00000000000000000010000000010000));
assign _zz_457_ = (1\'b0);
assign _zz_458_ = ({_zz_466_,_zz_467_} != (2\'b00));
assign _zz_459_ = ({_zz_468_,_zz_469_} != (3\'b000));
assign _zz_460_ = {(_zz_470_ != _zz_471_),{_zz_472_,{_zz_473_,_zz_474_}}};
assign _zz_461_ = (32\'b00000000000000000011000000110100);
assign _zz_462_ = (32\'b00000010000000000011000001010100);
assign _zz_463_ = (32\'b00000000000000000110000000010100);
assign _zz_464_ = (32\'b00000000000000000101000000010100);
assign _zz_465_ = (32\'b00000000000000000110000000010100);
assign _zz_466_ = ((decode_INSTRUCTION & (32\'b00000000000000000111000000110100)) == (32\'b00000000000000000101000000010000));
assign _zz_467_ = ((decode_INSTRUCTION & (32\'b00000010000000000111000001100100)) == (32\'b00000000000000000101000000100000));
assign _zz_468_ = ((decode_INSTRUCTION & _zz_475_) == (32\'b01000000000000000001000000010000));
assign _zz_469_ = {(_zz_476_ == _zz_477_),(_zz_478_ == _zz_479_)};
assign _zz_470_ = {_zz_136_,{_zz_480_,_zz_481_}};
assign _zz_471_ = (3\'b000);
assign _zz_472_ = ((_zz_482_ == _zz_483_) != (1\'b0));
assign _zz_473_ = ({_zz_484_,_zz_485_} != (2\'b00));
assign _zz_474_ = (_zz_486_ != (1\'b0));
assign _zz_475_ = (32\'b01000000000000000011000001010100);
assign _zz_476_ = (decode_INSTRUCTION & (32\'b00000000000000000111000000110100));
assign _zz_477_ = (32\'b00000000000000000001000000010000);
assign _zz_478_ = (decode_INSTRUCTION & (32\'b00000010000000000111000001010100));
assign _zz_479_ = (32\'b00000000000000000001000000010000);
assign _zz_480_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000000110000)) == (32\'b00000000000000000000000000010000));
assign _zz_481_ = ((decode_INSTRUCTION & (32\'b00000010000000000000000001100000)) == (32\'b00000000000000000000000000100000));
assign _zz_482_ = (decode_INSTRUCTION & (32\'b00000000000000000000000001011000));
assign _zz_483_ = (32\'b00000000000000000000000000000000);
assign _zz_484_ = ((decode_INSTRUCTION & (32\'b00000000000000000001000001010000)) == (32\'b00000000000000000001000001010000));
assign _zz_485_ = ((decode_INSTRUCTION & (32\'b00000000000000000010000001010000)) == (32\'b00000000000000000010000001010000));
assign _zz_486_ = ((decode_INSTRUCTION & (32\'b00000000000000000000000000010000)) == (32\'b00000000000000000000000000010000));
assign _zz_487_ = (32\'b00000000000000000001000001111111);
assign _zz_488_ = (decode_INSTRUCTION & (32\'b00000000000000000010000001111111));
assign _zz_489_ = (32\'b00000000000000000010000001110011);
assign _zz_490_ = ((decode_INSTRUCTION & (32\'b00000000000000000100000001111111)) == (32\'b00000000000000000100000001100011));
assign _zz_491_ = ((decode_INSTRUCTION & (32\'b00000000000000000010000001111111)) == (32\'b00000000000000000010000000010011));
assign _zz_492_ = {((decode_INSTRUCTION & (32\'b00000000000000000110000000111111)) == (32\'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32\'b00000000000000000010000001111111)) == (32\'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_493_) == (32\'b00000000000000000000000000000011)),{(_zz_494_ == _zz_495_),{_zz_496_,{_zz_497_,_zz_498_}}}}}};
assign _zz_493_ = (32\'b00000000000000000101000001011111);
assign _zz_494_ = (decode_INSTRUCTION & (32\'b00000000000000000111000001111011));
assign _zz_495_ = (32\'b00000000000000000000000001100011);
assign _zz_496_ = ((decode_INSTRUCTION & (32\'b00000000000000000110000001111111)) == (32\'b00000000000000000000000000001111));
assign _zz_497_ = ((decode_INSTRUCTION & (32\'b11111100000000000000000001111111)) == (32\'b00000000000000000000000000110011));
assign _zz_498_ = {((decode_INSTRUCTION & (32\'b11111100000000000011000001011111)) == (32\'b00000000000000000001000000010011)),{((decode_INSTRUCTION & (32\'b10111100000000000111000001111111)) == (32\'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_499_) == (32\'b00000000000000000101000000110011)),{(_zz_500_ == _zz_501_),(_zz_502_ == _zz_503_)}}}};
assign _zz_499_ = (32\'b10111110000000000111000001111111);
assign _zz_500_ = (decode_INSTRUCTION & (32\'b10111110000000000111000001111111));
assign _zz_501_ = (32\'b00000000000000000000000000110011);
assign _zz_502_ = (decode_INSTRUCTION & (32\'b11011111111111111111111111111111));
assign _zz_503_ = (32\'b00010000001000000000000001110011);
assign _zz_504_ = execute_INSTRUCTION[31];
assign _zz_505_ = execute_INSTRUCTION[31];
assign _zz_506_ = execute_INSTRUCTION[7];
always @ (posedge clk) begin
if(_zz_52_) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
always @ (posedge clk) begin
if(_zz_342_) begin
_zz_214_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @ (posedge clk) begin
if(_zz_343_) begin
_zz_215_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush(_zz_205_),
.io_cpu_prefetch_isValid(_zz_206_),
.io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt),
.io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload),
.io_cpu_fetch_isValid(_zz_207_),
.io_cpu_fetch_isStuck(_zz_208_),
.io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt),
.io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload),
.io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data),
.io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit),
.io_cpu_fetch_dataBypass(_zz_209_),
.io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid),
.io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress),
.io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation),
.io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress),
.io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess),
.io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead),
.io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite),
.io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute),
.io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception),
.io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling),
.io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end),
.io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy),
.io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress),
.io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt),
.io_cpu_decode_isValid(_zz_210_),
.io_cpu_decode_isStuck(_zz_211_),
.io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload),
.io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress),
.io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data),
.io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss),
.io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error),
.io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling),
.io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException),
.io_cpu_decode_isUser(_zz_212_),
.io_cpu_fill_valid(_zz_213_),
.io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress),
.io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid),
.io_mem_cmd_ready(iBus_cmd_ready),
.io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address),
.io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size),
.io_mem_rsp_valid(iBus_rsp_valid),
.io_mem_rsp_payload_data(iBus_rsp_payload_data),
.io_mem_rsp_payload_error(iBus_rsp_payload_error),
.clk(clk),
.reset(reset)
);
always @(*) begin
case(_zz_344_)
3\'b000 : begin
_zz_216_ = CsrPlugin_jumpInterface_payload;
end
3\'b001 : begin
_zz_216_ = DBusSimplePlugin_redoBranch_payload;
end
3\'b010 : begin
_zz_216_ = BranchPlugin_jumpInterface_payload;
end
3\'b011 : begin
_zz_216_ = IBusCachedPlugin_redoBranch_payload;
end
default : begin
_zz_216_ = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_1_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_1__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_1__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_1__string = "BITWISE ";
default : _zz_1__string = "????????";
endcase
end
always @(*) begin
case(_zz_2_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_2__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_2__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_2__string = "BITWISE ";
default : _zz_2__string = "????????";
endcase
end
always @(*) begin
case(_zz_3_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_3__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_3__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_3__string = "BITWISE ";
default : _zz_3__string = "????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_4_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1";
default : _zz_4__string = "?????";
endcase
end
always @(*) begin
case(_zz_5_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1";
default : _zz_5__string = "?????";
endcase
end
always @(*) begin
case(_zz_6_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1";
default : _zz_6__string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_7_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_7__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_7__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_7__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_7__string = "PC ";
default : _zz_7__string = "???";
endcase
end
always @(*) begin
case(_zz_8_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_8__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_8__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_8__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_8__string = "PC ";
default : _zz_8__string = "???";
endcase
end
always @(*) begin
case(_zz_9_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_9__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_9__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_9__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_9__string = "PC ";
default : _zz_9__string = "???";
endcase
end
always @(*) begin
case(_zz_10_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_10__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_10__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_10__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_10__string = "JALR";
default : _zz_10__string = "????";
endcase
end
always @(*) begin
case(_zz_11_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR";
default : _zz_11__string = "????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_12_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 ";
default : _zz_12__string = "????????????";
endcase
end
always @(*) begin
case(_zz_13_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 ";
default : _zz_13__string = "????????????";
endcase
end
always @(*) begin
case(_zz_14_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_14__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_14__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_14__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_14__string = "URS1 ";
default : _zz_14__string = "????????????";
endcase
end
always @(*) begin
case(_zz_15_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_15__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_15__string = "XRET";
default : _zz_15__string = "????";
endcase
end
always @(*) begin
case(_zz_16_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET";
default : _zz_16__string = "????";
endcase
end
always @(*) begin
case(_zz_17_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_17__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_17__string = "XRET";
default : _zz_17__string = "????";
endcase
end
always @(*) begin
case(_zz_18_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_18__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_18__string = "XRET";
default : _zz_18__string = "????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET";
default : decode_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_19_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_19__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_19__string = "XRET";
default : _zz_19__string = "????";
endcase
end
always @(*) begin
case(_zz_20_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET";
default : _zz_20__string = "????";
endcase
end
always @(*) begin
case(_zz_21_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET";
default : _zz_21__string = "????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_22_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 ";
default : _zz_22__string = "?????????";
endcase
end
always @(*) begin
case(_zz_23_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 ";
default : _zz_23__string = "?????????";
endcase
end
always @(*) begin
case(_zz_24_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1 ";
default : _zz_24__string = "?????????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET";
default : memory_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_25_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET";
default : _zz_25__string = "????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET";
default : execute_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_26_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET";
default : _zz_26__string = "????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET";
default : writeBack_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_29_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_29__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_29__string = "XRET";
default : _zz_29__string = "????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_32_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR";
default : _zz_32__string = "????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_37_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_37__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_37__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_37__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_37__string = "SRA_1 ";
default : _zz_37__string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_42_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_42__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_42__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_42__string = "PC ";
default : _zz_42__string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_44_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_44__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_44__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_44__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_44__string = "URS1 ";
default : _zz_44__string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_47_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_47__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_47__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_47__string = "BITWISE ";
default : _zz_47__string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_49_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_49__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_49__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_49__string = "AND_1";
default : _zz_49__string = "?????";
endcase
end
always @(*) begin
case(_zz_56_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_56__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_56__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_56__string = "URS1 ";
default : _zz_56__string = "????????????";
endcase
end
always @(*) begin
case(_zz_59_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_59__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_59__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_59__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_59__string = "PC ";
default : _zz_59__string = "???";
endcase
end
always @(*) begin
case(_zz_67_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_67__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_67__string = "XRET";
default : _zz_67__string = "????";
endcase
end
always @(*) begin
case(_zz_68_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_68__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_68__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_68__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_68__string = "JALR";
default : _zz_68__string = "????";
endcase
end
always @(*) begin
case(_zz_70_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_70__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_70__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_70__string = "AND_1";
default : _zz_70__string = "?????";
endcase
end
always @(*) begin
case(_zz_72_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_72__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_72__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_72__string = "BITWISE ";
default : _zz_72__string = "????????";
endcase
end
always @(*) begin
case(_zz_73_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_73__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_73__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_73__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_73__string = "SRA_1 ";
default : _zz_73__string = "?????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_95_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR";
default : _zz_95__string = "????";
endcase
end
always @(*) begin
case(_zz_142_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_142__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_142__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_142__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_142__string = "SRA_1 ";
default : _zz_142__string = "?????????";
endcase
end
always @(*) begin
case(_zz_143_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_143__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_143__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_143__string = "BITWISE ";
default : _zz_143__string = "????????";
endcase
end
always @(*) begin
case(_zz_144_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_144__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_144__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_144__string = "AND_1";
default : _zz_144__string = "?????";
endcase
end
always @(*) begin
case(_zz_145_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_145__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_145__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_145__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_145__string = "JALR";
default : _zz_145__string = "????";
endcase
end
always @(*) begin
case(_zz_146_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_146__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_146__string = "XRET";
default : _zz_146__string = "????";
endcase
end
always @(*) begin
case(_zz_147_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_147__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_147__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_147__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_147__string = "PC ";
default : _zz_147__string = "???";
endcase
end
always @(*) begin
case(_zz_148_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_148__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_148__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_148__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_148__string = "URS1 ";
default : _zz_148__string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET";
default : decode_to_execute_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET";
default : execute_to_memory_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET";
default : memory_to_writeBack_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
`endif
assign decode_ALU_CTRL = _zz_1_;
assign _zz_2_ = _zz_3_;
assign decode_ALU_BITWISE_CTRL = _zz_4_;
assign _zz_5_ = _zz_6_;
assign decode_SRC2_CTRL = _zz_7_;
assign _zz_8_ = _zz_9_;
assign decode_IS_RS2_SIGNED = _zz_58_;
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_74_;
assign decode_IS_RS1_SIGNED = _zz_55_;
assign decode_CSR_READ_OPCODE = _zz_27_;
assign decode_IS_DIV = _zz_57_;
assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;
assign execute_MEMORY_ADDRESS_LOW = _zz_89_;
assign decode_IS_MUL = _zz_69_;
assign execute_BRANCH_CALC = _zz_30_;
assign _zz_10_ = _zz_11_;
assign decode_SRC1_CTRL = _zz_12_;
assign _zz_13_ = _zz_14_;
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_77_;
assign decode_SRC2_FORCE_ZERO = _zz_46_;
assign decode_CSR_WRITE_OPCODE = _zz_28_;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign execute_REGFILE_WRITE_DATA = _zz_48_;
assign execute_BRANCH_DO = _zz_31_;
assign decode_SRC_LESS_UNSIGNED = _zz_65_;
assign _zz_15_ = _zz_16_;
assign _zz_17_ = _zz_18_;
assign decode_ENV_CTRL = _zz_19_;
assign _zz_20_ = _zz_21_;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = _zz_98_;
assign decode_MEMORY_STORE = _zz_61_;
assign decode_PREDICTION_HAD_BRANCHED2 = _zz_34_;
assign decode_IS_CSR = _zz_76_;
assign decode_SHIFT_CTRL = _zz_22_;
assign _zz_23_ = _zz_24_;
assign memory_MEMORY_READ_DATA = _zz_80_;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_25_;
assign execute_ENV_CTRL = _zz_26_;
assign writeBack_ENV_CTRL = _zz_29_;
assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC;
assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO;
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_33_;
assign execute_BRANCH_CTRL = _zz_32_;
assign decode_RS2_USE = _zz_63_;
assign decode_RS1_USE = _zz_66_;
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
always @ (*) begin
_zz_35_ = memory_REGFILE_WRITE_DATA;
if(_zz_217_)begin
_zz_35_ = ((memory_INSTRUCTION[13 : 12] == (2\'b00)) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]);
end
if(_zz_218_)begin
_zz_35_ = memory_MulDivIterativePlugin_div_result;
end
end
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @ (*) begin
decode_RS2 = _zz_53_;
if(_zz_161_)begin
if((_zz_162_ == decode_INSTRUCTION[24 : 20]))begin
decode_RS2 = _zz_163_;
end
end
if(_zz_219_)begin
if(_zz_220_)begin
if(_zz_165_)begin
decode_RS2 = _zz_79_;
end
end
end
if(_zz_221_)begin
if(memory_BYPASSABLE_MEMORY_STAGE)begin
if(_zz_167_)begin
decode_RS2 = _zz_35_;
end
end
end
if(_zz_222_)begin
if(execute_BYPASSABLE_EXECUTE_STAGE)begin
if(_zz_169_)begin
decode_RS2 = _zz_36_;
end
end
end
end
always @ (*) begin
decode_RS1 = _zz_54_;
if(_zz_161_)begin
if((_zz_162_ == decode_INSTRUCTION[19 : 15]))begin
decode_RS1 = _zz_163_;
end
end
if(_zz_219_)begin
if(_zz_220_)begin
if(_zz_164_)begin
decode_RS1 = _zz_79_;
end
end
end
if(_zz_221_)begin
if(memory_BYPASSABLE_MEMORY_STAGE)begin
if(_zz_166_)begin
decode_RS1 = _zz_35_;
end
end
end
if(_zz_222_)begin
if(execute_BYPASSABLE_EXECUTE_STAGE)begin
if(_zz_168_)begin
decode_RS1 = _zz_36_;
end
end
end
end
always @ (*) begin
_zz_36_ = execute_REGFILE_WRITE_DATA;
if(_zz_223_)begin
_zz_36_ = _zz_157_;
end
if(_zz_224_)begin
_zz_36_ = execute_CsrPlugin_readData;
end
end
assign execute_SHIFT_CTRL = _zz_37_;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_41_ = execute_PC;
assign execute_SRC2_CTRL = _zz_42_;
assign execute_SRC1_CTRL = _zz_44_;
assign decode_SRC_USE_SUB_LESS = _zz_60_;
assign decode_SRC_ADD_ZERO = _zz_71_;
assign execute_SRC_ADD_SUB = _zz_40_;
assign execute_SRC_LESS = _zz_38_;
assign execute_ALU_CTRL = _zz_47_;
assign execute_SRC2 = _zz_43_;
assign execute_SRC1 = _zz_45_;
assign execute_ALU_BITWISE_CTRL = _zz_49_;
assign _zz_50_ = writeBack_INSTRUCTION;
assign _zz_51_ = writeBack_REGFILE_WRITE_VALID;
always @ (*) begin
_zz_52_ = 1\'b0;
if(lastStageRegFileWrite_valid)begin
_zz_52_ = 1\'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = _zz_94_;
always @ (*) begin
decode_REGFILE_WRITE_VALID = _zz_64_;
if((decode_INSTRUCTION[11 : 7] == (5\'b00000)))begin
decode_REGFILE_WRITE_VALID = 1\'b0;
end
end
assign decode_LEGAL_INSTRUCTION = _zz_78_;
assign decode_INSTRUCTION_READY = 1\'b1;
assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE;
always @ (*) begin
_zz_79_ = writeBack_REGFILE_WRITE_DATA;
if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin
_zz_79_ = writeBack_DBusSimplePlugin_rspFormated;
end
end
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW;
assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA;
assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT;
assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress;
assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess;
assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead;
assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite;
assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute;
assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception;
assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling;
assign memory_PC = execute_to_memory_PC;
assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MMU_FAULT = _zz_88_;
assign execute_MMU_RSP_physicalAddress = _zz_81_;
assign execute_MMU_RSP_isIoAccess = _zz_82_;
assign execute_MMU_RSP_allowRead = _zz_83_;
assign execute_MMU_RSP_allowWrite = _zz_84_;
assign execute_MMU_RSP_allowExecute = _zz_85_;
assign execute_MMU_RSP_exception = _zz_86_;
assign execute_MMU_RSP_refilling = _zz_87_;
assign execute_SRC_ADD = _zz_39_;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_ALIGNEMENT_FAULT = _zz_90_;
assign decode_MEMORY_ENABLE = _zz_75_;
assign decode_FLUSH_ALL = _zz_62_;
always @ (*) begin
IBusCachedPlugin_rsp_issueDetected = _zz_91_;
if(_zz_225_)begin
IBusCachedPlugin_rsp_issueDetected = 1\'b1;
end
end
always @ (*) begin
_zz_91_ = _zz_92_;
if(_zz_226_)begin
_zz_91_ = 1\'b1;
end
end
always @ (*) begin
_zz_92_ = _zz_93_;
if(_zz_227_)begin
_zz_92_ = 1\'b1;
end
end
always @ (*) begin
_zz_93_ = 1\'b0;
if(_zz_228_)begin
_zz_93_ = 1\'b1;
end
end
assign decode_BRANCH_CTRL = _zz_95_;
assign decode_INSTRUCTION = _zz_99_;
always @ (*) begin
_zz_96_ = memory_FORMAL_PC_NEXT;
if(DBusSimplePlugin_redoBranch_valid)begin
_zz_96_ = DBusSimplePlugin_redoBranch_payload;
end
if(BranchPlugin_jumpInterface_valid)begin
_zz_96_ = BranchPlugin_jumpInterface_payload;
end
end
always @ (*) begin
_zz_97_ = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid)begin
_zz_97_ = IBusCachedPlugin_predictionJumpInterface_payload;
end
if(IBusCachedPlugin_redoBranch_valid)begin
_zz_97_ = IBusCachedPlugin_redoBranch_payload;
end
end
assign decode_PC = _zz_100_;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @ (*) begin
decode_arbitration_haltItself = 1\'b0;
if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin
decode_arbitration_haltItself = 1\'b1;
end
end
always @ (*) begin
decode_arbitration_haltByOther = 1\'b0;
if((decode_arbitration_isValid && (_zz_158_ || _zz_159_)))begin
decode_arbitration_haltByOther = 1\'b1;
end
if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin
decode_arbitration_haltByOther = decode_arbitration_isValid;
end
if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3\'b000)))begin
decode_arbitration_haltByOther = 1\'b1;
end
end
always @ (*) begin
decode_arbitration_removeIt = 1\'b0;
if(_zz_229_)begin
decode_arbitration_removeIt = 1\'b1;
end
if(decode_arbitration_isFlushed)begin
decode_arbitration_removeIt = 1\'b1;
end
end
assign decode_arbitration_flushIt = 1\'b0;
always @ (*) begin
decode_arbitration_flushNext = 1\'b0;
if(IBusCachedPlugin_redoBranch_valid)begin
decode_arbitration_flushNext = 1\'b1;
end
if(_zz_229_)begin
decode_arbitration_flushNext = 1\'b1;
end
end
always @ (*) begin
execute_arbitration_haltItself = 1\'b0;
if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_128_)))begin
execute_arbitration_haltItself = 1\'b1;
end
if(_zz_223_)begin
if(_zz_230_)begin
if(! execute_LightShifterPlugin_done) begin
execute_arbitration_haltItself = 1\'b1;
end
end
end
if(_zz_224_)begin
if(execute_CsrPlugin_blockedBySideEffects)begin
execute_arbitration_haltItself = 1\'b1;
end
end
end
assign execute_arbitration_haltByOther = 1\'b0;
always @ (*) begin
execute_arbitration_removeIt = 1\'b0;
if(execute_arbitration_isFlushed)begin
execute_arbitration_removeIt = 1\'b1;
end
end
assign execute_arbitration_flushIt = 1\'b0;
assign execute_arbitration_flushNext = 1\'b0;
always @ (*) begin
memory_arbitration_haltItself = 1\'b0;
if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1\'b0)))begin
memory_arbitration_haltItself = 1\'b1;
end
if(_zz_217_)begin
if(_zz_231_)begin
memory_arbitration_haltItself = 1\'b1;
end
end
if(_zz_218_)begin
if(_zz_232_)begin
memory_arbitration_haltItself = 1\'b1;
end
end
end
assign memory_arbitration_haltByOther = 1\'b0;
always @ (*) begin
memory_arbitration_removeIt = 1\'b0;
if(_zz_233_)begin
memory_arbitration_removeIt = 1\'b1;
end
if(memory_arbitration_isFlushed)begin
memory_arbitration_removeIt = 1\'b1;
end
end
always @ (*) begin
memory_arbitration_flushIt = 1\'b0;
if(DBusSimplePlugin_redoBranch_valid)begin
memory_arbitration_flushIt = 1\'b1;
end
end
always @ (*) begin
memory_arbitration_flushNext = 1\'b0;
if(DBusSimplePlugin_redoBranch_valid)begin
memory_arbitration_flushNext = 1\'b1;
end
if(BranchPlugin_jumpInterface_valid)begin
memory_arbitration_flushNext = 1\'b1;
end
if(_zz_233_)begin
memory_arbitration_flushNext = 1\'b1;
end
end
assign writeBack_arbitration_haltItself = 1\'b0;
assign writeBack_arbitration_haltByOther = 1\'b0;
always @ (*) begin
writeBack_arbitration_removeIt = 1\'b0;
if(writeBack_arbitration_isFlushed)begin
writeBack_arbitration_removeIt = 1\'b1;
end
end
assign writeBack_arbitration_flushIt = 1\'b0;
always @ (*) begin
writeBack_arbitration_flushNext = 1\'b0;
if(_zz_234_)begin
writeBack_arbitration_flushNext = 1\'b1;
end
if(_zz_235_)begin
writeBack_arbitration_flushNext = 1\'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @ (*) begin
IBusCachedPlugin_fetcherHalt = 1\'b0;
if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4\'b0000)))begin
IBusCachedPlugin_fetcherHalt = 1\'b1;
end
if(_zz_234_)begin
IBusCachedPlugin_fetcherHalt = 1\'b1;
end
if(_zz_235_)begin
IBusCachedPlugin_fetcherHalt = 1\'b1;
end
end
always @ (*) begin
IBusCachedPlugin_fetcherflushIt = 1\'b0;
if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4\'b0000)))begin
IBusCachedPlugin_fetcherflushIt = 1\'b1;
end
if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin
IBusCachedPlugin_fetcherflushIt = 1\'b1;
end
end
always @ (*) begin
IBusCachedPlugin_incomingInstruction = 1\'b0;
if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin
IBusCachedPlugin_incomingInstruction = 1\'b1;
end
end
always @ (*) begin
CsrPlugin_jumpInterface_valid = 1\'b0;
if(_zz_234_)begin
CsrPlugin_jumpInterface_valid = 1\'b1;
end
if(_zz_235_)begin
CsrPlugin_jumpInterface_valid = 1\'b1;
end
end
always @ (*) begin
CsrPlugin_jumpInterface_payload = (32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
if(_zz_234_)begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtve'b"c_base,(2'b00)};
end
if(_zz_235_)begin
case(_zz_236_)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000));
assign _zz_101_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}};
assign _zz_102_ = (_zz_101_ & (~ _zz_255_));
assign _zz_103_ = _zz_102_[3];
assign _zz_104_ = _zz_102_[4];
assign _zz_105_ = (_zz_102_[1] || _zz_103_);
assign _zz_106_ = (_zz_102_[2] || _zz_103_);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_216_;
always @ (*) begin
IBusCachedPlugin_fetchPc_corrected = 1'b0;
if(IBusCachedPlugin_jump_pcLoad_valid)begin
IBusCachedPlugin_fetchPc_corrected = 1'b1;
end
end
always @ (*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
always @ (*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_257_);
if(IBusCachedPlugin_jump_pcLoad_valid)begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1;
always @ (*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_107_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_107_);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_107_);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @ (*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_108_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_108_);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_108_);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @ (*) begin
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0;
if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1;
end
end
assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt);
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_109_);
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_109_);
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_110_;
assign _zz_110_ = ((1'b0 && (! _zz_111_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_111_ = _zz_112_;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_111_;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
assign _zz_113_ = _zz_114_;
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_113_;
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_115_;
always @ (*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if((! IBusCachedPlugin_pcValids_0))begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved));
assign _zz_100_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc;
assign _zz_99_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst;
assign _zz_98_ = (decode_PC + (32'b00000000000000000000000000000100));
assign _zz_116_ = _zz_258_[11];
always @ (*) begin
_zz_117_[18] = _zz_116_;
_zz_117_[17] = _zz_116_;
_zz_117_[16] = _zz_116_;
_zz_117_[15] = _zz_116_;
_zz_117_[14] = _zz_116_;
_zz_117_[13] = _zz_116_;
_zz_117_[12] = _zz_116_;
_zz_117_[11] = _zz_116_;
_zz_117_[10] = _zz_116_;
_zz_117_[9] = _zz_116_;
_zz_117_[8] = _zz_116_;
_zz_117_[7] = _zz_116_;
_zz_117_[6] = _zz_116_;
_zz_117_[5] = _zz_116_;
_zz_117_[4] = _zz_116_;
_zz_117_[3] = _zz_116_;
_zz_117_[2] = _zz_116_;
_zz_117_[1] = _zz_116_;
_zz_117_[0] = _zz_116_;
end
always @ (*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_259_[31]));
if(_zz_122_)begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_118_ = _zz_260_[19];
always @ (*) begin
_zz_119_[10] = _zz_118_;
_zz_119_[9] = _zz_118_;
_zz_119_[8] = _zz_118_;
_zz_119_[7] = _zz_118_;
_zz_119_[6] = _zz_118_;
_zz_119_[5] = _zz_118_;
_zz_119_[4] = _zz_118_;
_zz_119_[3] = _zz_118_;
_zz_119_[2] = _zz_118_;
_zz_119_[1] = _zz_118_;
_zz_119_[0] = _zz_118_;
end
assign _zz_120_ = _zz_261_[11];
always @ (*) begin
_zz_121_[18] = _zz_120_;
_zz_121_[17] = _zz_120_;
_zz_121_[16] = _zz_120_;
_zz_121_[15] = _zz_120_;
_zz_121_[14] = _zz_120_;
_zz_121_[13] = _zz_120_;
_zz_121_[12] = _zz_120_;
_zz_121_[11] = _zz_120_;
_zz_121_[10] = _zz_120_;
_zz_121_[9] = _zz_120_;
_zz_121_[8] = _zz_120_;
_zz_121_[7] = _zz_120_;
_zz_121_[6] = _zz_120_;
_zz_121_[5] = _zz_120_;
_zz_121_[4] = _zz_120_;
_zz_121_[3] = _zz_120_;
_zz_121_[2] = _zz_120_;
_zz_121_[1] = _zz_120_;
_zz_121_[0] = _zz_120_;
end
always @ (*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_JAL : begin
_zz_122_ = _zz_262_[1];
end
default : begin
_zz_122_ = _zz_263_[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_123_ = _zz_264_[19];
always @ (*) begin
_zz_124_[10] = _zz_123_;
_zz_124_[9] = _zz_123_;
_zz_124_[8] = _zz_123_;
_zz_124_[7] = _zz_123_;
_zz_124_[6] = _zz_123_;
_zz_124_[5] = _zz_123_;
_zz_124_[4] = _zz_123_;
_zz_124_[3] = _zz_123_;
_zz_124_[2] = _zz_123_;
_zz_124_[1] = _zz_123_;
_zz_124_[0] = _zz_123_;
end
assign _zz_125_ = _zz_265_[11];
always @ (*) begin
_zz_126_[18] = _zz_125_;
_zz_126_[17] = _zz_125_;
_zz_126_[16] = _zz_125_;
_zz_126_[15] = _zz_125_;
_zz_126_[14] = _zz_125_;
_zz_126_[13] = _zz_125_;
_zz_126_[12] = _zz_125_;
_zz_126_[11] = _zz_125_;
_zz_126_[10] = _zz_125_;
_zz_126_[9] = _zz_125_;
_zz_126_[8] = _zz_125_;
_zz_126_[7] = _zz_125_;
_zz_126_[6] = _zz_125_;
_zz_126_[5] = _zz_125_;
_zz_126_[4] = _zz_125_;
_zz_126_[3] = _zz_125_;
_zz_126_[2] = _zz_125_;
_zz_126_[1] = _zz_125_;
_zz_126_[0] = _zz_125_;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_124_,{{{_zz_345_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_126_,{{{_zz_346_,_zz_347_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @ (*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign _zz_206_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign _zz_209_ = (32'b00000000000000000000000000000000);
assign _zz_207_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign _zz_208_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_210_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign _zz_211_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
assign _zz_212_ = (CsrPlugin_privilege == (2'b00));
assign _zz_94_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
always @ (*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(_zz_228_)begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(_zz_226_)begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(_zz_237_)begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
end
end
always @ (*) begin
_zz_213_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(_zz_226_)begin
_zz_213_ = 1'b1;
end
if(_zz_237_)begin
_zz_213_ = 1'b0;
end
end
always @ (*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(_zz_227_)begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(_zz_225_)begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @ (*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx);
if(_zz_227_)begin
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100);
end
if(_zz_225_)begin
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001);
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)};
assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch;
assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready;
assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
assign _zz_205_ = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign _zz_128_ = 1'b0;
assign _zz_90_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0))));
always @ (*) begin
execute_DBusSimplePlugin_skipCmd = 1'b0;
if(execute_ALIGNEMENT_FAULT)begin
execute_DBusSimplePlugin_skipCmd = 1'b1;
end
if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin
execute_DBusSimplePlugin_skipCmd = 1'b1;
end
end
assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_128_));
assign dBus_cmd_payload_wr = execute_MEMORY_STORE;
assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];
always @ (*) begin
case(dBus_cmd_payload_size)
2'b00 : begin
_zz_129_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_129_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_129_ = execute_RS2[31 : 0];
end
endcase
end
assign dBus_cmd_payload_data = _zz_129_;
assign _zz_89_ = dBus_cmd_payload_address[1 : 0];
always @ (*) begin
case(dBus_cmd_payload_size)
2'b00 : begin
_zz_130_ = (4'b0001);
end
2'b01 : begin
_zz_130_ = (4'b0011);
end
default : begin
_zz_130_ = (4'b1111);
end
endcase
end
assign execute_DBusSimplePlugin_formalMask = (_zz_130_ <<< dBus_cmd_payload_address[1 : 0]);
assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD;
assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0;
assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
assign _zz_88_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE)));
assign _zz_81_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
assign _zz_82_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess;
assign _zz_83_ = DBusSimplePlugin_mmuBus_rsp_allowRead;
assign _zz_84_ = DBusSimplePlugin_mmuBus_rsp_allowWrite;
assign _zz_85_ = DBusSimplePlugin_mmuBus_rsp_allowExecute;
assign _zz_86_ = DBusSimplePlugin_mmuBus_rsp_exception;
assign _zz_87_ = DBusSimplePlugin_mmuBus_rsp_refilling;
assign _zz_80_ = dBus_rsp_data;
always @ (*) begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
if(_zz_238_)begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
end
if(memory_ALIGNEMENT_FAULT)begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
end
if(memory_MMU_RSP_refilling)begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
end else begin
if(memory_MMU_FAULT)begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
end
end
if(_zz_239_)begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
end
end
always @ (*) begin
DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx);
if(_zz_238_)begin
DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101);
end
if(memory_ALIGNEMENT_FAULT)begin
DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_266_};
end
if(! memory_MMU_RSP_refilling) begin
if(memory_MMU_FAULT)begin
DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101));
end
end
end
assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA;
always @ (*) begin
DBusSimplePlugin_redoBranch_valid = 1'b0;
if(memory_MMU_RSP_refilling)begin
DBusSimplePlugin_redoBranch_valid = 1'b1;
end
if(_zz_239_)begin
DBusSimplePlugin_redoBranch_valid = 1'b0;
end
end
assign DBusSimplePlugin_redoBranch_payload = memory_PC;
always @ (*) begin
writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA;
case(writeBack_MEMORY_ADDRESS_LOW)
2'b01 : begin
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8];
end
2'b10 : begin
writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16];
end
2'b11 : begin
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24];
end
default : begin
end
endcase
end
assign _zz_131_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14]));
always @ (*) begin
_zz_132_[31] = _zz_131_;
_zz_132_[30] = _zz_131_;
_zz_132_[29] = _zz_131_;
_zz_132_[28] = _zz_131_;
_zz_132_[27] = _zz_131_;
_zz_132_[26] = _zz_131_;
_zz_132_[25] = _zz_131_;
_zz_132_[24] = _zz_131_;
_zz_132_[23] = _zz_131_;
_zz_132_[22] = _zz_131_;
_zz_132_[21] = _zz_131_;
_zz_132_[20] = _zz_131_;
_zz_132_[19] = _zz_131_;
_zz_132_[18] = _zz_131_;
_zz_132_[17] = _zz_131_;
_zz_132_[16] = _zz_131_;
_zz_132_[15] = _zz_131_;
_zz_132_[14] = _zz_131_;
_zz_132_[13] = _zz_131_;
_zz_132_[12] = _zz_131_;
_zz_132_[11] = _zz_131_;
_zz_132_[10] = _zz_131_;
_zz_132_[9] = _zz_131_;
_zz_132_[8] = _zz_131_;
_zz_132_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0];
end
assign _zz_133_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14]));
always @ (*) begin
_zz_134_[31] = _zz_133_;
_zz_134_[30] = _zz_133_;
_zz_134_[29] = _zz_133_;
_zz_134_[28] = _zz_133_;
_zz_134_[27] = _zz_133_;
_zz_134_[26] = _zz_133_;
_zz_134_[25] = _zz_133_;
_zz_134_[24] = _zz_133_;
_zz_134_[23] = _zz_133_;
_zz_134_[22] = _zz_133_;
_zz_134_[21] = _zz_133_;
_zz_134_[20] = _zz_133_;
_zz_134_[19] = _zz_133_;
_zz_134_[18] = _zz_133_;
_zz_134_[17] = _zz_133_;
_zz_134_[16] = _zz_133_;
_zz_134_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0];
end
always @ (*) begin
case(_zz_253_)
2'b00 : begin
writeBack_DBusSimplePlugin_rspFormated = _zz_132_;
end
2'b01 : begin
writeBack_DBusSimplePlugin_rspFormated = _zz_134_;
end
default : begin
writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted;
end
endcase
end
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress;
assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31];
assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0;
assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusSimplePlugin_mmuBus_busy = 1'b0;
assign _zz_136_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100));
assign _zz_137_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000));
assign _zz_138_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000));
assign _zz_139_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000000000)) == (32'b00000000000000000001000000000000));
assign _zz_140_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000100000000000000));
assign _zz_141_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000));
assign _zz_135_ = {({_zz_140_,{_zz_137_,_zz_139_}} != (3'b000)),{({_zz_348_,_zz_141_} != (2'b00)),{({_zz_349_,_zz_350_} != (2'b00)),{(_zz_351_ != _zz_352_),{_zz_353_,{_zz_354_,_zz_355_}}}}}};
assign _zz_78_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_487_) == (32'b00000000000000000001000001110011)),{(_zz_488_ == _zz_489_),{_zz_490_,{_zz_491_,_zz_492_}}}}}}} != (18'b000000000000000000));
assign _zz_77_ = _zz_267_[0];
assign _zz_76_ = _zz_268_[0];
assign _zz_75_ = _zz_269_[0];
assign _zz_74_ = _zz_270_[0];
assign _zz_142_ = _zz_135_[5 : 4];
assign _zz_73_ = _zz_142_;
assign _zz_143_ = _zz_135_[7 : 6];
assign _zz_72_ = _zz_143_;
assign _zz_71_ = _zz_271_[0];
assign _zz_144_ = _zz_135_[10 : 9];
assign _zz_70_ = _zz_144_;
assign _zz_69_ = _zz_272_[0];
assign _zz_145_ = _zz_135_[13 : 12];
assign _zz_68_ = _zz_145_;
assign _zz_146_ = _zz_135_[14 : 14];
assign _zz_67_ = _zz_146_;
assign _zz_66_ = _zz_273_[0];
assign _zz_65_ = _zz_274_[0];
assign _zz_64_ = _zz_275_[0];
assign _zz_63_ = _zz_276_[0];
assign _zz_62_ = _zz_277_[0];
assign _zz_61_ = _zz_278_[0];
assign _zz_60_ = _zz_279_[0];
assign _zz_147_ = _zz_135_[23 : 22];
assign _zz_59_ = _zz_147_;
assign _zz_58_ = _zz_280_[0];
assign _zz_57_ = _zz_281_[0];
assign _zz_148_ = _zz_135_[28 : 27];
assign _zz_56_ = _zz_148_;
assign _zz_55_ = _zz_282_[0];
assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = (4'b0010);
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_214_;
assign decode_RegFilePlugin_rs2Data = _zz_215_;
assign _zz_54_ = decode_RegFilePlugin_rs1Data;
assign _zz_53_ = decode_RegFilePlugin_rs2Data;
always @ (*) begin
lastStageRegFileWrite_valid = (_zz_51_ && writeBack_arbitration_isFiring);
if(_zz_149_)begin
lastStageRegFileWrite_valid = 1'b1;
end
end
assign lastStageRegFileWrite_payload_address = _zz_50_[11 : 7];
assign lastStageRegFileWrite_payload_data = _zz_79_;
always @ (*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @ (*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_BITWISE : begin
_zz_150_ = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
_zz_150_ = {31'd0, _zz_283_};
end
default : begin
_zz_150_ = execute_SRC_ADD_SUB;
end
endcase
end
assign _zz_48_ = _zz_150_;
assign _zz_46_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
always @ (*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : begin
_zz_151_ = execute_RS1;
end
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
_zz_151_ = {29'd0, _zz_284_};
end
`Src1CtrlEnum_defaultEncoding_IMU : begin
_zz_151_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)};
end
default : begin
_zz_151_ = {27'd0, _zz_285_};
end
endcase
end
assign _zz_45_ = _zz_151_;
assign _zz_152_ = _zz_286_[11];
always @ (*) begin
_zz_153_[19] = _zz_152_;
_zz_153_[18] = _zz_152_;
_zz_153_[17] = _zz_152_;
_zz_153_[16] = _zz_152_;
_zz_153_[15] = _zz_152_;
_zz_153_[14] = _zz_152_;
_zz_153_[13] = _zz_152_;
_zz_153_[12] = _zz_152_;
_zz_153_[11] = _zz_152_;
_zz_153_[10] = _zz_152_;
_zz_153_[9] = _zz_152_;
_zz_153_[8] = _zz_152_;
_zz_153_[7] = _zz_152_;
_zz_153_[6] = _zz_152_;
_zz_153_[5] = _zz_152_;
_zz_153_[4] = _zz_152_;
_zz_153_[3] = _zz_152_;
_zz_153_[2] = _zz_152_;
_zz_153_[1] = _zz_152_;
_zz_153_[0] = _zz_152_;
end
assign _zz_154_ = _zz_287_[11];
always @ (*) begin
_zz_155_[19] = _zz_154_;
_zz_155_[18] = _zz_154_;
_zz_155_[17] = _zz_154_;
_zz_155_[16] = _zz_154_;
_zz_155_[15] = _zz_154_;
_zz_155_[14] = _zz_154_;
_zz_155_[13] = _zz_154_;
_zz_155_[12] = _zz_154_;
_zz_155_[11] = _zz_154_;
_zz_155_[10] = _zz_154_;
_zz_155_[9] = _zz_154_;
_zz_155_[8] = _zz_154_;
_zz_155_[7] = _zz_154_;
_zz_155_[6] = _zz_154_;
_zz_155_[5] = _zz_154_;
_zz_155_[4] = _zz_154_;
_zz_155_[3] = _zz_154_;
_zz_155_[2] = _zz_154_;
_zz_155_[1] = _zz_154_;
_zz_155_[0] = _zz_154_;
end
always @ (*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : begin
_zz_156_ = execute_RS2;
end
`Src2CtrlEnum_defaultEncoding_IMI : begin
_zz_156_ = {_zz_153_,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_defaultEncoding_IMS : begin
_zz_156_ = {_zz_155_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_156_ = _zz_41_;
end
endcase
end
assign _zz_43_ = _zz_156_;
always @ (*) begin
execute_SrcPlugin_addSub = _zz_288_;
if(execute_SRC2_FORCE_ZERO)begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign _zz_40_ = execute_SrcPlugin_addSub;
assign _zz_39_ = execute_SrcPlugin_addSub;
assign _zz_38_ = execute_SrcPlugin_less;
assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1);
assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]);
assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1);
assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000));
always @ (*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
_zz_157_ = (execute_LightShifterPlugin_shiftInput <<< 1);
end
default : begin
_zz_157_ = _zz_295_;
end
endcase
end
always @ (*) begin
_zz_158_ = 1'b0;
if(_zz_240_)begin
if(_zz_241_)begin
if(_zz_164_)begin
_zz_158_ = 1'b1;
end
end
end
if(_zz_242_)begin
if(_zz_243_)begin
if(_zz_166_)begin
_zz_158_ = 1'b1;
end
end
end
if(_zz_244_)begin
if(_zz_245_)begin
if(_zz_168_)begin
_zz_158_ = 1'b1;
end
end
end
if((! decode_RS1_USE))begin
_zz_158_ = 1'b0;
end
end
always @ (*) begin
_zz_159_ = 1'b0;
if(_zz_240_)begin
if(_zz_241_)begin
if(_zz_165_)begin
_zz_159_ = 1'b1;
end
end
end
if(_zz_242_)begin
if(_zz_243_)begin
if(_zz_167_)begin
_zz_159_ = 1'b1;
end
end
end
if(_zz_244_)begin
if(_zz_245_)begin
if(_zz_169_)begin
_zz_159_ = 1'b1;
end
end
end
if((! decode_RS2_USE))begin
_zz_159_ = 1'b0;
end
end
assign _zz_160_ = (_zz_51_ && writeBack_arbitration_isFiring);
assign _zz_164_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign _zz_165_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign _zz_166_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign _zz_167_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign _zz_168_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign _zz_169_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign _zz_34_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign _zz_170_ = execute_INSTRUCTION[14 : 12];
always @ (*) begin
if((_zz_170_ == (3'b000))) begin
_zz_171_ = execute_BranchPlugin_eq;
end else if((_zz_170_ == (3'b001))) begin
_zz_171_ = (! execute_BranchPlugin_eq);
end else if((((_zz_170_ & (3'b101)) == (3'b101)))) begin
_zz_171_ = (! execute_SRC_LESS);
end else begin
_zz_171_ = execute_SRC_LESS;
end
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : begin
_zz_172_ = 1'b0;
end
`BranchCtrlEnum_defaultEncoding_JAL : begin
_zz_172_ = 1'b1;
end
`BranchCtrlEnum_defaultEncoding_JALR : begin
_zz_172_ = 1'b1;
end
default : begin
_zz_172_ = _zz_171_;
end
endcase
end
assign _zz_33_ = _zz_172_;
assign _zz_173_ = _zz_297_[11];
always @ (*) begin
_zz_174_[19] = _zz_173_;
_zz_174_[18] = _zz_173_;
_zz_174_[17] = _zz_173_;
_zz_174_[16] = _zz_173_;
_zz_174_[15] = _zz_173_;
_zz_174_[14] = _zz_173_;
_zz_174_[13] = _zz_173_;
_zz_174_[12] = _zz_173_;
_zz_174_[11] = _zz_173_;
_zz_174_[10] = _zz_173_;
_zz_174_[9] = _zz_173_;
_zz_174_[8] = _zz_173_;
_zz_174_[7] = _zz_173_;
_zz_174_[6] = _zz_173_;
_zz_174_[5] = _zz_173_;
_zz_174_[4] = _zz_173_;
_zz_174_[3] = _zz_173_;
_zz_174_[2] = _zz_173_;
_zz_174_[1] = _zz_173_;
_zz_174_[0] = _zz_173_;
end
assign _zz_175_ = _zz_298_[19];
always @ (*) begin
_zz_176_[10] = _zz_175_;
_zz_176_[9] = _zz_175_;
_zz_176_[8] = _zz_175_;
_zz_176_[7] = _zz_175_;
_zz_176_[6] = _zz_175_;
_zz_176_[5] = _zz_175_;
_zz_176_[4] = _zz_175_;
_zz_176_[3] = _zz_175_;
_zz_176_[2] = _zz_175_;
_zz_176_[1] = _zz_175_;
_zz_176_[0] = _zz_175_;
end
assign _zz_177_ = _zz_299_[11];
always @ (*) begin
_zz_178_[18] = _zz_177_;
_zz_178_[17] = _zz_177_;
_zz_178_[16] = _zz_177_;
_zz_178_[15] = _zz_177_;
_zz_178_[14] = _zz_177_;
_zz_178_[13] = _zz_177_;
_zz_178_[12] = _zz_177_;
_zz_178_[11] = _zz_177_;
_zz_178_[10] = _zz_177_;
_zz_178_[9] = _zz_177_;
_zz_178_[8] = _zz_177_;
_zz_178_[7] = _zz_177_;
_zz_178_[6] = _zz_177_;
_zz_178_[5] = _zz_177_;
_zz_178_[4] = _zz_177_;
_zz_178_[3] = _zz_177_;
_zz_178_[2] = _zz_177_;
_zz_178_[1] = _zz_177_;
_zz_178_[0] = _zz_177_;
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_JALR : begin
_zz_179_ = (_zz_300_[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_defaultEncoding_JAL : begin
_zz_179_ = _zz_301_[1];
end
default : begin
_zz_179_ = _zz_302_[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_179_);
assign _zz_31_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_180_ = _zz_303_[11];
always @ (*) begin
_zz_181_[19] = _zz_180_;
_zz_181_[18] = _zz_180_;
_zz_181_[17] = _zz_180_;
_zz_181_[16] = _zz_180_;
_zz_181_[15] = _zz_180_;
_zz_181_[14] = _zz_180_;
_zz_181_[13] = _zz_180_;
_zz_181_[12] = _zz_180_;
_zz_181_[11] = _zz_180_;
_zz_181_[10] = _zz_180_;
_zz_181_[9] = _zz_180_;
_zz_181_[8] = _zz_180_;
_zz_181_[7] = _zz_180_;
_zz_181_[6] = _zz_180_;
_zz_181_[5] = _zz_180_;
_zz_181_[4] = _zz_180_;
_zz_181_[3] = _zz_180_;
_zz_181_[2] = _zz_180_;
_zz_181_[1] = _zz_180_;
_zz_181_[0] = _zz_180_;
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_181_,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_183_,{{{_zz_504_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_185_,{{{_zz_505_,_zz_506_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2)begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_306_};
end
end
endcase
end
assign _zz_182_ = _zz_304_[19];
always @ (*) begin
_zz_183_[10] = _zz_182_;
_zz_183_[9] = _zz_182_;
_zz_183_[8] = _zz_182_;
_zz_183_[7] = _zz_182_;
_zz_183_[6] = _zz_182_;
_zz_183_[5] = _zz_182_;
_zz_183_[4] = _zz_182_;
_zz_183_[3] = _zz_182_;
_zz_183_[2] = _zz_182_;
_zz_183_[1] = _zz_182_;
_zz_183_[0] = _zz_182_;
end
assign _zz_184_ = _zz_305_[11];
always @ (*) begin
_zz_185_[18] = _zz_184_;
_zz_185_[17] = _zz_184_;
_zz_185_[16] = _zz_184_;
_zz_185_[15] = _zz_184_;
_zz_185_[14] = _zz_184_;
_zz_185_[13] = _zz_184_;
_zz_185_[12] = _zz_184_;
_zz_185_[11] = _zz_184_;
_zz_185_[10] = _zz_184_;
_zz_185_[9] = _zz_184_;
_zz_185_[8] = _zz_184_;
_zz_185_[7] = _zz_184_;
_zz_185_[6] = _zz_184_;
_zz_185_[5] = _zz_184_;
_zz_185_[4] = _zz_184_;
_zz_185_[3] = _zz_184_;
_zz_185_[2] = _zz_184_;
_zz_185_[1] = _zz_184_;
_zz_185_[0] = _zz_184_;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign _zz_30_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)};
assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC;
assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1]));
assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000);
assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @ (*) begin
CsrPlugin_privilege = (2'b11);
if(CsrPlugin_forceMachineWire)begin
CsrPlugin_privilege = (2'b11);
end
end
assign CsrPlugin_misa_base = (2'b01);
assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010);
assign _zz_186_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_187_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_188_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_189_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_190_ = _zz_307_[0];
assign _zz_191_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid};
assign _zz_192_ = _zz_309_[0];
always @ (*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_229_)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @ (*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(execute_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @ (*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(_zz_233_)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1;
end
if(memory_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @ (*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(writeBack_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_lastStageWasWfi = 1'b0;
always @ (*) begin
CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3);
if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException)begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @ (*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException)begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @ (*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException)begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @ (*) begin
CsrPlugin_xtvec_mode = (2'bxx);
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @ (*) begin
CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign _zz_28_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
assign _zz_27_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
assign execute_CsrPlugin_inWfi = 1'b0;
assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00));
always @ (*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
case(execute_CsrPlugin_csrAddress)
12'b101111000000 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
12'b001100000000 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
12'b001101000001 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
12'b001100000101 : begin
if(execute_CSR_WRITE_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
12'b001101000100 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
12'b001101000011 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
12'b111111000000 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
12'b001100000100 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
12'b001101000010 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
default : begin
end
endcase
if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @ (*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin
if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @ (*) begin
execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
case(execute_CsrPlugin_csrAddress)
12'b101111000000 : begin
execute_CsrPlugin_readData[31 : 0] = _zz_200_;
end
12'b001100000000 : begin
execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
end
12'b001101000001 : begin
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc;
end
12'b001100000101 : begin
end
12'b001101000100 : begin
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
end
12'b001101000011 : begin
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval;
end
12'b111111000000 : begin
execute_CsrPlugin_readData[31 : 0] = _zz_201_;
end
12'b001100000100 : begin
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
end
12'b001101000010 : begin
execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
default : begin
end
endcase
end
assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData;
always @ (*) begin
case(_zz_254_)
1'b0 : begin
execute_CsrPlugin_writeData = execute_SRC1;
end
default : begin
execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
always @ (*) begin
memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0;
if(_zz_217_)begin
if(_zz_231_)begin
memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1;
end
end
end
always @ (*) begin
memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0;
if((! memory_arbitration_isStuck))begin
memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1;
end
end
assign memory_MulDivIterativePlugin_mul_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == (6'b100000));
assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement);
always @ (*) begin
if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin
memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000);
end else begin
memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_312_);
end
if(memory_MulDivIterativePlugin_mul_counter_willClear)begin
memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000);
end
end
always @ (*) begin
memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0;
if(_zz_218_)begin
if(_zz_232_)begin
memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @ (*) begin
memory_MulDivIterativePlugin_div_counter_willClear = 1'b0;
if(_zz_246_)begin
memory_MulDivIterativePlugin_div_counter_willClear = 1'b1;
end
end
assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == (6'b100001));
assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement);
always @ (*) begin
if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin
memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000);
end else begin
memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_320_);
end
if(memory_MulDivIterativePlugin_div_counter_willClear)begin
memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000);
end
end
assign _zz_193_ = memory_MulDivIterativePlugin_rs1[31 : 0];
assign _zz_194_ = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_193_[31]};
assign _zz_195_ = (_zz_194_ - _zz_321_);
assign _zz_196_ = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]);
assign _zz_197_ = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_198_ = ((execute_IS_MUL && _zz_197_) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @ (*) begin
_zz_199_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_199_[31 : 0] = execute_RS1;
end
assign _zz_201_ = (_zz_200_ & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_201_ != (32'b00000000000000000000000000000000));
assign _zz_24_ = decode_SHIFT_CTRL;
assign _zz_22_ = _zz_73_;
assign _zz_37_ = decode_to_execute_SHIFT_CTRL;
assign _zz_21_ = decode_ENV_CTRL;
assign _zz_18_ = execute_ENV_CTRL;
assign _zz_16_ = memory_ENV_CTRL;
assign _zz_19_ = _zz_67_;
assign _zz_26_ = decode_to_execute_ENV_CTRL;
assign _zz_25_ = execute_to_memory_ENV_CTRL;
assign _zz_29_ = memory_to_writeBack_ENV_CTRL;
assign _zz_14_ = decode_SRC1_CTRL;
assign _zz_12_ = _zz_56_;
assign _zz_44_ = decode_to_execute_SRC1_CTRL;
assign _zz_11_ = decode_BRANCH_CTRL;
assign _zz_95_ = _zz_68_;
assign _zz_32_ = decode_to_execute_BRANCH_CTRL;
assign _zz_9_ = decode_SRC2_CTRL;
assign _zz_7_ = _zz_59_;
assign _zz_42_ = decode_to_execute_SRC2_CTRL;
assign _zz_6_ = decode_ALU_BITWISE_CTRL;
assign _zz_4_ = _zz_70_;
assign _zz_49_ = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_3_ = decode_ALU_CTRL;
assign _zz_1_ = _zz_72_;
assign _zz_47_ = decode_to_execute_ALU_CTRL;
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000)));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000)));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00)));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0)));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign iBusWishbone_ADR = {_zz_340_,_zz_202_};
assign iBusWishbone_CTI = ((_zz_202_ == (3'b111)) ? (3'b111) : (3'b010));
assign iBusWishbone_BTE = (2'b00);
assign iBusWishbone_SEL = (4'b1111);
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
always @ (*) begin
iBusWishbone_CYC = 1'b0;
if(_zz_247_)begin
iBusWishbone_CYC = 1'b1;
end
end
always @ (*) begin
iBusWishbone_STB = 1'b0;
if(_zz_247_)begin
iBusWishbone_STB = 1'b1;
end
end
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_203_;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid;
assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr;
assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address;
assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data;
assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size;
assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready;
assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2);
assign dBusWishbone_CTI = (3'b000);
assign dBusWishbone_BTE = (2'b00);
always @ (*) begin
case(dBus_cmd_halfPipe_payload_size)
2'b00 : begin
_zz_204_ = (4'b0001);
end
2'b01 : begin
_zz_204_ = (4'b0011);
end
default : begin
_zz_204_ = (4'b1111);
end
endcase
end
always @ (*) begin
dBusWishbone_SEL = _zz_341_[3:0];
if((! dBus_cmd_halfPipe_payload_wr))begin
dBusWishbone_SEL = (4'b1111);
end
end
assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr;
assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data;
assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK);
assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid;
assign dBusWishbone_STB = dBus_cmd_halfPipe_valid;
assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
assign dBus_rsp_data = dBusWishbone_DAT_MISO;
assign dBus_rsp_error = 1'b0;
always @ (posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_112_ <= 1'b0;
_zz_114_ <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_127_;
IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000);
_zz_149_ <= 1'b1;
execute_LightShifterPlugin_isActive <= 1'b0;
_zz_161_ <= 1'b0;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= (2'b11);
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_MulDivIterativePlugin_mul_counter_value <= (6'b000000);
memory_MulDivIterativePlugin_div_counter_value <= (6'b000000);
_zz_200_ <= (32'b00000000000000000000000000000000);
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000);
memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000);
_zz_202_ <= (3'b000);
_zz_203_ <= 1'b0;
dBus_cmd_halfPipe_regs_valid <= 1'b0;
dBus_cmd_halfPipe_regs_ready <= 1'b1;
end else begin
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_fetcherflushIt)begin
_zz_112_ <= 1'b0;
end
if(_zz_110_)begin
_zz_112_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin
_zz_114_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid;
end
if(IBusCachedPlugin_fetcherflushIt)begin
_zz_114_ <= 1'b0;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if((! execute_arbitration_isStuck))begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if((! memory_arbitration_isStuck))begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if((! writeBack_arbitration_isStuck))begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(decode_arbitration_removeIt)begin
IBusCachedPlugin_injector_decodeRemoved <= 1'b1;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
end
if(iBus_rsp_valid)begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001));
end
_zz_149_ <= 1'b0;
if(_zz_223_)begin
if(_zz_230_)begin
execute_LightShifterPlugin_isActive <= 1'b1;
if(execute_LightShifterPlugin_done)begin
execute_LightShifterPlugin_isActive <= 1'b0;
end
end
end
if(execute_arbitration_removeIt)begin
execute_LightShifterPlugin_isActive <= 1'b0;
end
_zz_161_ <= _zz_160_;
if((! decode_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if((! execute_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if((! memory_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if((! writeBack_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(_zz_248_)begin
if(_zz_249_)begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(_zz_250_)begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(_zz_251_)begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(_zz_234_)begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP"b' <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(_zz_235_)begin
case(_zz_236_)
2\'b11 : begin
CsrPlugin_mstatus_MPP <= (2\'b00);
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1\'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= ({_zz_188_,{_zz_187_,_zz_186_}} != (3\'b000));
memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext;
memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext;
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_35_;
end
if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
execute_arbitration_isValid <= 1\'b0;
end
if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin
memory_arbitration_isValid <= 1\'b0;
end
if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin
writeBack_arbitration_isValid <= 1\'b0;
end
if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
case(execute_CsrPlugin_csrAddress)
12\'b101111000000 : begin
if(execute_CsrPlugin_writeEnable)begin
_zz_200_ <= execute_CsrPlugin_writeData[31 : 0];
end
end
12\'b001100000000 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
CsrPlugin_mstatus_MPIE <= _zz_334_[0];
CsrPlugin_mstatus_MIE <= _zz_335_[0];
end
end
12\'b001101000001 : begin
end
12\'b001100000101 : begin
end
12\'b001101000100 : begin
end
12\'b001101000011 : begin
end
12\'b111111000000 : begin
end
12\'b001100000100 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mie_MEIE <= _zz_337_[0];
CsrPlugin_mie_MTIE <= _zz_338_[0];
CsrPlugin_mie_MSIE <= _zz_339_[0];
end
end
12\'b001101000010 : begin
end
default : begin
end
endcase
if(_zz_247_)begin
if(iBusWishbone_ACK)begin
_zz_202_ <= (_zz_202_ + (3\'b001));
end
end
_zz_203_ <= (iBusWishbone_CYC && iBusWishbone_ACK);
if(_zz_252_)begin
dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid;
dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid);
end else begin
dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready);
dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready;
end
end
end
always @ (posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin
_zz_115_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin
$display("ERROR DBusSimplePlugin doesn\'t allow memory stage stall when read happend");
end
if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin
$display("ERROR DBusSimplePlugin doesn\'t allow writeback stage stall when read happend");
end
if(_zz_223_)begin
if(_zz_230_)begin
execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5\'b00001));
end
end
if(_zz_160_)begin
_zz_162_ <= _zz_50_[11 : 7];
_zz_163_ <= _zz_79_;
end
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64\'b0000000000000000000000000000000000000000000000000000000000000001));
if(writeBack_arbitration_isFiring)begin
CsrPlugin_minstret <= (CsrPlugin_minstret + (64\'b0000000000000000000000000000000000000000000000000000000000000001));
end
if(_zz_229_)begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_190_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_190_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_233_)begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_192_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_192_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr);
end
if(_zz_248_)begin
if(_zz_249_)begin
CsrPlugin_interrupt_code <= (4\'b0111);
CsrPlugin_interrupt_targetPrivilege <= (2\'b11);
end
if(_zz_250_)begin
CsrPlugin_interrupt_code <= (4\'b0011);
CsrPlugin_interrupt_targetPrivilege <= (2\'b11);
end
if(_zz_251_)begin
CsrPlugin_interrupt_code <= (4\'b1011);
CsrPlugin_interrupt_targetPrivilege <= (2\'b11);
end
end
if(_zz_234_)begin
case(CsrPlugin_targetPrivilege)
2\'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException)begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(_zz_217_)begin
if(_zz_231_)begin
memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1);
memory_MulDivIterativePlugin_accumulator <= ({_zz_313_,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1);
end
end
if((memory_MulDivIterativePlugin_div_counter_value == (6\'b100000)))begin
memory_MulDivIterativePlugin_div_done <= 1\'b1;
end
if((! memory_arbitration_isStuck))begin
memory_MulDivIterativePlugin_div_done <= 1\'b0;
end
if(_zz_218_)begin
if(_zz_232_)begin
memory_MulDivIterativePlugin_rs1[31 : 0] <= _zz_322_[31:0];
memory_MulDivIterativePlugin_accumulator[31 : 0] <= ((! _zz_195_[32]) ? _zz_323_ : _zz_324_);
if((memory_MulDivIterativePlugin_div_counter_value == (6\'b100000)))begin
memory_MulDivIterativePlugin_div_result <= _zz_325_[31:0];
end
end
end
if(_zz_246_)begin
memory_MulDivIterativePlugin_accumulator <= (65\'b00000000000000000000000000000000000000000000000000000000000000000);
memory_MulDivIterativePlugin_rs1 <= ((_zz_198_ ? (~ _zz_199_) : _zz_199_) + _zz_331_);
memory_MulDivIterativePlugin_rs2 <= ((_zz_197_ ? (~ execute_RS2) : execute_RS2) + _zz_333_);
memory_MulDivIterativePlugin_div_needRevert <= ((_zz_198_ ^ (_zz_197_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32\'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if((! execute_arbitration_isStuck))begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SHIFT_CTRL <= _zz_23_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_PC <= decode_PC;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_PC <= _zz_41_;
end
if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin
memory_to_writeBack_PC <= memory_PC;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_97_;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_FORMAL_PC_NEXT <= _zz_96_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ENV_CTRL <= _zz_20_;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_ENV_CTRL <= _zz_17_;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_ENV_CTRL <= _zz_15_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;
end
if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_36_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_RS1 <= decode_RS1;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC1_CTRL <= _zz_13_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BRANCH_CTRL <= _zz_10_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MMU_FAULT <= execute_MMU_FAULT;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_RS2 <= decode_RS2;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress;
execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess;
execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead;
execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite;
execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute;
execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception;
execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC2_CTRL <= _zz_8_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ALU_CTRL <= _zz_2_;
end
case(execute_CsrPlugin_csrAddress)
12\'b101111000000 : begin
end
12\'b001100000000 : begin
end
12\'b001101000001 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0];
end
end
12\'b001100000101 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2];
CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0];
end
end
12\'b001101000100 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mip_MSIP <= _zz_336_[0];
end
end
12\'b001101000011 : begin
end
12\'b111111000000 : begin
end
12\'b001100000100 : begin
end
12\'b001101000010 : begin
end
default : begin
end
endcase
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
if(_zz_252_)begin
dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr;
dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address;
dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data;
dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size;
end
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* dont_touch = "true" *) input clk100,
input cpu_reset,
output [2:0] led
);
wire [2:0] led;
wire builder_pll_fb;
assign led[0] = main_locked;
assign led[1] = main_clkout0;
assign led[2] = main_clkout1;
PLLE2_ADV #(
.CLKFBOUT_MULT(4\'d12),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(5\'d20),
.CLKOUT0_PHASE(1\'d0),
.CLKOUT1_DIVIDE(3\'d5),
.CLKOUT1_PHASE(1\'d0),
.CLKOUT2_DIVIDE(3\'d5),
.CLKOUT2_PHASE(7\'d70),
.CLKOUT3_DIVIDE(3\'d6),
.CLKOUT3_PHASE(1\'d0),
.DIVCLK_DIVIDE(1\'d1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV_0 (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk100),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
.CLKOUT1(main_clkout1),
.LOCKED(main_locked)
);
PLLE2_ADV #(
.CLKFBOUT_MULT(4\'d12),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(5\'d20),
.CLKOUT0_PHASE(1\'d0),
.CLKOUT1_DIVIDE(3\'d5),
.CLKOUT1_PHASE(1\'d0),
.CLKOUT2_DIVIDE(3\'d5),
.CLKOUT2_PHASE(7\'d90),
.CLKOUT3_DIVIDE(3\'d6),
.CLKOUT3_PHASE(1\'d0),
.DIVCLK_DIVIDE(1\'d1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk100),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
.CLKOUT1(main_clkout1),
.LOCKED(main_locked)
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module full_adder (
input wire [`WIDTH-1:0] A,
input wire [`WIDTH-1:0] B,
output wire [`WIDTH :0] S,
);
// Implicit adder
assign S = A + B;
endmodule
module subtractor (
input wire [`WIDTH-1:0] A,
input wire [`WIDTH-1:0] B,
output wire [`WIDTH :0] S,
);
// Implicit subtractor
assign S = A - B;
endmodule
module comparator (
input wire [`WIDTH-1:0] A,
input wire [`WIDTH-1:0] B,
output wire CO,
);
assign CO = (A <= B) ? 1\'b1 : 1\'b0;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1\'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
reg [1:0] cnt2 = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_inst (
.I(clk),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
PLLE2_ADV #(
.CLKFBOUT_MULT(4\'d12),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(4\'d12),
.CLKOUT0_PHASE(90.0),
.DIVCLK_DIVIDE(1\'d1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
);
wire main_clkout0_bufg;
BUFG bufg (.I(main_clkout0), .O(main_clkout0_bufg));
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
always @(posedge main_clkout0_bufg) begin
cnt2 <= cnt2 + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[2:0] = {cnt2[0], cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \\$_DFF_P_ (D, Q, C);
input D;
input C;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(1\'b1), .S(1\'b1));
endmodule
module \\$_DFF_PN0_ (D, Q, C, R);
input D;
input C;
input R;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(1\'b1));
endmodule
module \\$_DFF_PP0_ (D, Q, C, R);
input D;
input C;
input R;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(!R), .S(1\'b1));
endmodule
module \\$_DFF_PN1_ (D, Q, C, R);
input D;
input C;
input R;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(1\'b1), .S(R));
endmodule
module \\$_DFF_PP1_ (D, Q, C, R);
input D;
input C;
input R;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(1\'b1), .S(!R));
endmodule
module \\$_DFF_N_ (D, Q, C);
input D;
input C;
output Q;
dffnsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(1\'b1), .S(1\'b1));
endmodule
module \\$_DFF_NN0_ (D, Q, C, R);
input D;
input C;
input R;
output Q;
dffnsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(1\'b1));
endmodule
module \\$_DFF_NP0_ (D, Q, C, R);
input D;
input C;
input R;
output Q;
dffnsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(!R), .S(1\'b1));
endmodule
module \\$_DFF_NN1_ (D, Q, C, R);
input D;
input C;
input R;
output Q;
dffnsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(1\'b1), .S(R));
endmodule
module \\$_DFF_NP1_ (D, Q, C, R);
input D;
input C;
input R;
output Q;
dffnsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(1\'b1), .S(!R));
endmodule
module \\$_DFFSR_PPP_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(!R), .S(!S));
endmodule
module \\$_DFFSR_PNP_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(!R), .S(S));
endmodule
module \\$_DFFSR_PNN_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
module \\$_DFFSR_PPN_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(!S));
endmodule
module \\$_DFFSR_NPP_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffnsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(!R), .S(!S));
endmodule
module \\$_DFFSR_NNP_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffnsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(!R), .S(S));
endmodule
module \\$_DFFSR_NNN_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffnsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
module \\$_DFFSR_NPN_ (D, Q, C, R, S);
input D;
input C;
input R;
input S;
output Q;
dffnsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(!S));
endmodule
module \\$__SHREG_DFF_P_ (D, Q, C);
input D;
input C;
output Q;
parameter DEPTH = 2;
reg [DEPTH-2:0] q;
genvar i;
generate for (i = 0; i < DEPTH; i = i + 1) begin: slice
// First in chain
generate if (i == 0) begin
sh_dff #() shreg_beg (
.Q(q[i]),
.D(D),
.C(C)
);
end endgenerate
// Middle in chain
generate if (i > 0 && i != DEPTH-1) begin
sh_dff #() shreg_mid (
.Q(q[i]),
.D(q[i-1]),
.C(C)
);
end endgenerate
// Last in chain
generate if (i == DEPTH-1) begin
sh_dff #() shreg_end (
.Q(Q),
.D(q[i-1]),
.C(C)
);
end endgenerate
end: slice
endgenerate
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
// ============================================================================
// CMT
`define PLL_FRAC_PRECISION 10
`define PLL_FIXED_WIDTH 32
// Rounds a fixed point number to a given precision
function [`PLL_FIXED_WIDTH:1] pll_round_frac(input [`PLL_FIXED_WIDTH:1] decimal,
input [`PLL_FIXED_WIDTH:1] precision);
if (decimal[(`PLL_FRAC_PRECISION-precision)] == 1\'b1) begin
pll_round_frac = decimal + (1\'b1 << (`PLL_FRAC_PRECISION - precision));
end else begin
pll_round_frac = decimal;
end
endfunction
// Computes content of the PLLs divider registers
function [13:0] pll_divider_regs(input [7:0] divide, // Max divide is 128
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
);
reg [`PLL_FIXED_WIDTH:1] duty_cycle_fix;
reg [`PLL_FIXED_WIDTH:1] duty_cycle_min;
reg [`PLL_FIXED_WIDTH:1] duty_cycle_max;
reg [ 6:0] high_time;
reg [ 6:0] low_time;
reg w_edge;
reg no_count;
reg [`PLL_FIXED_WIDTH:1] temp;
if (divide >= 64) begin
duty_cycle_min = ((divide - 64) * 100_000) / divide;
duty_cycle_max = (645 / divide) * 100_00;
if (duty_cycle > duty_cycle_max) duty_cycle = duty_cycle_max;
if (duty_cycle < duty_cycle_min) duty_cycle = duty_cycle_min;
end
duty_cycle_fix = (duty_cycle << `PLL_FRAC_PRECISION) / 100_000;
if (divide == 7\'h01) begin
high_time = 7\'h01;
w_edge = 1\'b0;
low_time = 7\'h01;
no_count = 1\'b1;
end else begin
temp = pll_round_frac(duty_cycle_fix*divide, 1);
high_time = temp[`PLL_FRAC_PRECISION+7:`PLL_FRAC_PRECISION+1];
w_edge = temp[`PLL_FRAC_PRECISION];
if (high_time == 7\'h00) begin
high_time = 7\'h01;
w_edge = 1\'b0;
end
if (high_time == divide) begin
high_time = divide - 1;
w_edge = 1\'b1;
end
low_time = divide - high_time;
no_count = 1\'b0;
end
pll_divider_regs = {w_edge, no_count, high_time[5:0], low_time[5:0]};
endfunction
// Computes the PLLs phase shift registers
function [10:0] pll_phase_regs(input [7:0] divide, input signed [31:0] phase);
reg [`PLL_FIXED_WIDTH:1] phase_in_cycles;
reg [`PLL_FIXED_WIDTH:1] phase_fixed;
reg [1:0] mx;
reg [5:0] delay_time;
reg [2:0] phase_mux;
reg [`PLL_FIXED_WIDTH:1] temp;
if (phase < 0) begin
phase_fixed = ((phase + 360000) << `PLL_FRAC_PRECISION) / 1000;
end else begin
phase_fixed = (phase << `PLL_FRAC_PRECISION) / 1000;
end
phase_in_cycles = (phase_fixed * divide) / 360;
temp = pll_round_frac(phase_in_cycles, 3);
mx = 2\'b00;
phase_mux = temp[`PLL_FRAC_PRECISION:`PLL_FRAC_PRECISION-2];
delay_time = temp[`PLL_FRAC_PRECISION+6:`PLL_FRAC_PRECISION+1];
pll_phase_regs = {mx, phase_mux, delay_time};
endfunction
// Given PLL/MMCM divide, duty_cycle and phase calculates content of the
// CLKREG1 and CLKREG2.
function [37:0] pll_clkregs(input [7:0] divide, // Max divide is 128
input [31:0] duty_cycle, // Multiplied by 100,000
input signed [31:0] phase // Phase is given in degrees (-360,000 to 360,000)
);
reg [13:0] pll_div; // EDGE, NO_COUNT, HIGH_TIME[5:0], LOW_TIME[5:0]
reg [10:0] pll_phase; // MX, PHASE_MUX[2:0], DELAY_TIME[5:0]
pll_div = pll_divider_regs(divide, duty_cycle);
pll_phase = pll_phase_regs(divide, phase);
pll_clkregs = {
// CLKREG2: RESERVED[6:0], MX[1:0], EDGE, NO_COUNT, DELAY_TIME[5:0]
6\'h00,
pll_phase[10:9],
pll_div[13:12],
pll_phase[5:0],
// CLKREG1: PHASE_MUX[3:0], RESERVED, HIGH_TIME[5:0], LOW_TIME[5:0]
pll_phase[8:6],
1\'b0,
pll_div[11:0]
};
endfunction
// This function takes the divide value and outputs the necessary lock values
function [39:0] pll_lktable_lookup(input [6:0] divide // Max divide is 64
);
reg [2559:0] lookup;
lookup = {
// This table is composed of:
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
40\'b00110_00110_1111101000_1111101001_0000000001,
40\'b00110_00110_1111101000_1111101001_0000000001,
40\'b01000_01000_1111101000_1111101001_0000000001,
40\'b01011_01011_1111101000_1111101001_0000000001,
40\'b01110_01110_1111101000_1111101001_0000000001,
40\'b10001_10001_1111101000_1111101001_0000000001,
40\'b10011_10011_1111101000_1111101001_0000000001,
40\'b10110_10110_1111101000_1111101001_0000000001,
40\'b11001_11001_1111101000_1111101001_0000000001,
40\'b11100_11100_1111101000_1111101001_0000000001,
40\'b11111_11111_1110000100_1111101001_0000000001,
40\'b11111_11111_1100111001_1111101001_0000000001,
40\'b11111_11111_1011101110_1111101001_0000000001,
40\'b11111_11111_1010111100_1111101001_0000000001,
40\'b11111_11111_1010001010_1111101001_0000000001,
40\'b11111_11111_1001110001_1111101001_0000000001,
40\'b11111_11111_1000111111_1111101001_0000000001,
40\'b11111_11111_1000100110_1111101001_0000000001,
40\'b11111_11111_1000001101_1111101001_0000000001,
40\'b11111_11111_0111110100_1111101001_0000000001,
40\'b11111_11111_0111011011_1111101001_0000000001,
40\'b11111_11111_0111000010_1111101001_0000000001,
40\'b11111_11111_0110101001_1111101001_0000000001,
40\'b11111_11111_0110010000_1111101001_0000000001,
40\'b11111_11111_0110010000_1111101001_0000000001,
40\'b11111_11111_0101110111_1111101001_0000000001,
40\'b11111_11111_0101011110_1111101001_0000000001,
40\'b11111_11111_0101011110_1111101001_0000000001,
40\'b11111_11111_0101000101_1111101001_0000000001,
40\'b11111_11111_0101000101_1111101001_0000000001,
40\'b11111_11111_0100101100_1111101001_0000000001,
40\'b11111_11111_0100101100_1111101001_0000000001,
40\'b11111_11111_0100101100_1111101001_0000000001,
40\'b11111_11111_0100010011_1111101001_0000000001,
40\'b11111_11111_0100010011_1111101001_0000000001,
40\'b11111_11111_0100010011_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001,
40\'b11111_11111_0011111010_1111101001_0000000001
};
pll_lktable_lookup = lookup[((64-divide)*40)+:40];
endfunction
// This function takes the divide value and the bandwidth setting of the PLL
// and outputs the digital filter settings necessary.
function [9:0] pll_table_lookup(input [6:0] divide, // Max divide is 64
input [8*9:0] BANDWIDTH);
reg [639:0] lookup_low;
reg [639:0] lookup_high;
reg [639:0] lookup_optimized;
reg [ 9:0] lookup_entry;
lookup_low = {
// CP_RES_LFHF
10\'b0010_1111_00,
10\'b0010_1111_00,
10\'b0010_0111_00,
10\'b0010_1101_00,
10\'b0010_0101_00,
10\'b0010_0101_00,
10\'b0010_1001_00,
10\'b0010_1110_00,
10\'b0010_1110_00,
10\'b0010_0001_00,
10\'b0010_0001_00,
10\'b0010_0110_00,
10\'b0010_0110_00,
10\'b0010_0110_00,
10\'b0010_0110_00,
10\'b0010_1010_00,
10\'b0010_1010_00,
10\'b0010_1010_00,
10\'b0010_1010_00,
10\'b0010_1100_00,
10\'b0010_1100_00,
10\'b0010_1100_00,
10\'b0010_1100_00,
10\'b0010_1100_00,
10\'b0010_1100_00,
10\'b0010_1100_00,
10\'b0010_1100_00,
10\'b0010_1100_00,
10\'b0010_1100_00,
10\'b0010_1100_00,
10\'b0010_0010_00,
10\'b0010_0010_00,
10\'b0010_0010_00,
10\'b0010_0010_00,
10\'b0010_0010_00,
10\'b0010_0010_00,
10\'b0010_0010_00,
10\'b0010_0010_00,
10\'b0010_0010_00,
10\'b0010_0010_00,
10\'b0011_1100_00,
10\'b0011_1100_00,
10\'b0011_1100_00,
10\'b0011_1100_00,
10\'b0011_1100_00,
10\'b0011_1100_00,
10\'b0011_1100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00
};
lookup_high = {
// CP_RES_LFHF
10\'b0011_0111_00,
10\'b0011_0111_00,
10\'b0101_1111_00,
10\'b0111_1111_00,
10\'b0111_1011_00,
10\'b1101_0111_00,
10\'b1110_1011_00,
10\'b1110_1101_00,
10\'b1111_1101_00,
10\'b1111_0111_00,
10\'b1111_1011_00,
10\'b1111_1101_00,
10\'b1111_0011_00,
10\'b1110_0101_00,
10\'b1111_0101_00,
10\'b1111_0101_00,
10\'b1111_0101_00,
10\'b1111_0101_00,
10\'b0111_0110_00,
10\'b0111_0110_00,
10\'b0111_0110_00,
10\'b0111_0110_00,
10\'b0101_1100_00,
10\'b0101_1100_00,
10\'b0101_1100_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b0100_0010_00,
10\'b0100_0010_00,
10\'b0100_0010_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0011_0100_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00
};
lookup_optimized = {
// CP_RES_LFHF
10\'b0011_0111_00,
10\'b0011_0111_00,
10\'b0101_1111_00,
10\'b0111_1111_00,
10\'b0111_1011_00,
10\'b1101_0111_00,
10\'b1110_1011_00,
10\'b1110_1101_00,
10\'b1111_1101_00,
10\'b1111_0111_00,
10\'b1111_1011_00,
10\'b1111_1101_00,
10\'b1111_0011_00,
10\'b1110_0101_00,
10\'b1111_0101_00,
10\'b1111_0101_00,
10\'b1111_0101_00,
10\'b1111_0101_00,
10\'b0111_0110_00,
10\'b0111_0110_00,
10\'b0111_0110_00,
10\'b0111_0110_00,
10\'b0101_1100_00,
10\'b0101_1100_00,
10\'b0101_1100_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b1100_0001_00,
10\'b0100_0010_00,
10\'b0100_0010_00,
10\'b0100_0010_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0011_0100_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0010_1000_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0100_1100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00,
10\'b0010_0100_00
};
if (BANDWIDTH == "LOW") begin
pll_table_lookup = lookup_low[((64-divide)*10)+:10];
end else if (BANDWIDTH == "HIGH") begin
pll_table_lookup = lookup_high[((64-divide)*10)+:10];
end else if (BANDWIDTH == "OPTIMIZED") begin
pll_table_lookup = lookup_optimized[((64-divide)*10)+:10];
end
endfunction
// ............................................................................
// IMPORTANT NOTE: Due to lack of support for real type parameters in Yosys
// the PLL parameters that define duty cycles and phase shifts have to be
// provided as integers! The DUTY_CYCLE is expressed as % of high time times
// 1000 whereas the PHASE is expressed in degrees times 1000.
// PLLE2_ADV
module PLLE2_ADV (
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
output CLKFBOUT,
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
input PWRDWN,
input RST,
output LOCKED,
input DCLK,
input DEN,
input DWE,
output DRDY,
input [ 6:0] DADDR,
input [15:0] DI,
output [15:0] DO
);
parameter _TECHMAP_CONSTMSK_CLKINSEL_ = 0;
parameter _TECHMAP_CONSTVAL_CLKINSEL_ = 0;
parameter _TECHMAP_CONSTMSK_RST_ = 0;
parameter _TECHMAP_CONSTVAL_RST_ = 0;
parameter _TECHMAP_CONSTMSK_PWRDWN_ = 0;
parameter _TECHMAP_CONSTVAL_PWRDWN_ = 0;
parameter _TECHMAP_CONSTMSK_CLKFBOUT_ = 0;
parameter _TECHMAP_CONSTVAL_CLKFBOUT_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT0_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT0_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT1_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT1_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT2_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT2_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT3_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT3_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT4_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT4_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT5_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT5_ = 0;
parameter _TECHMAP_CONSTMSK_DCLK_ = 0;
parameter _TECHMAP_CONSTVAL_DCLK_ = 0;
parameter _TECHMAP_CONSTMSK_DEN_ = 0;
parameter _TECHMAP_CONSTVAL_DEN_ = 0;
parameter _TECHMAP_CONSTMSK_DWE_ = 0;
parameter _TECHMAP_CONSTVAL_DWE_ = 0;
parameter IS_CLKINSEL_INVERTED = 1\'b0;
parameter IS_RST_INVERTED = 1\'b0;
parameter IS_PWRDWN_INVERTED = 1\'b0;
parameter BANDWIDTH = "OPTIMIZED";
parameter STARTUP_WAIT = "FALSE";
parameter COMPENSATION = "ZHOLD";
parameter CLKIN1_PERIOD = 0.0;
parameter REF_JITTER1 = 0.01;
parameter CLKIN2_PERIOD = 0.0;
parameter REF_JITTER2 = 0.01;
parameter [5:0] DIVCLK_DIVIDE = 1;
parameter [5:0] CLKFBOUT_MULT = 1;
parameter CLKFBOUT_PHASE = 0;
parameter [6:0] CLKOUT0_DIVIDE = 1;
parameter CLKOUT0_DUTY_CYCLE = 50000;
parameter signed CLKOUT0_PHASE = 0;
parameter [6:0] CLKOUT1_DIVIDE = 1;
parameter CLKOUT1_DUTY_CYCLE = 50000;
parameter signed CLKOUT1_PHASE = 0;
parameter [6:0] CLKOUT2_DIVIDE = 1;
parameter CLKOUT2_DUTY_CYCLE = 50000;
parameter signed CLKOUT2_PHASE = 0;
parameter [6:0] CLKOUT3_DIVIDE = 1;
parameter CLKOUT3_DUTY_CYCLE = 50000;
parameter signed CLKOUT3_PHASE = 0;
parameter [6:0] CLKOUT4_DIVIDE = 1;
parameter CLKOUT4_DUTY_CYCLE = 50000;
parameter signed CLKOUT4_PHASE = 0;
parameter [6:0] CLKOUT5_DIVIDE = 1;
parameter CLKOUT5_DUTY_CYCLE = 50000;
parameter signed CLKOUT5_PHASE = 0;
// Compute PLL\'s registers content
localparam CLKFBOUT_REGS = pll_clkregs(CLKFBOUT_MULT, 50000, CLKFBOUT_PHASE);
localparam DIVCLK_REGS = pll_clkregs(DIVCLK_DIVIDE, 50000, 0);
localparam CLKOUT0_REGS = pll_clkregs(CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, CLKOUT0_PHASE);
localparam CLKOUT1_REGS = pll_clkregs(CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, CLKOUT1_PHASE);
localparam CLKOUT2_REGS = pll_clkregs(CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, CLKOUT2_PHASE);
localparam CLKOUT3_REGS = pll_clkregs(CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, CLKOUT3_PHASE);
localparam CLKOUT4_REGS = pll_clkregs(CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, CLKOUT4_PHASE);
localparam CLKOUT5_REGS = pll_clkregs(CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, CLKOUT5_PHASE);
// Handle inputs that should have certain logic levels when left unconnected
localparam INV_CLKINSEL = (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) ? !_TECHMAP_CONSTVAL_CLKINSEL_ :
\t\t\t (_TECHMAP_CONSTVAL_CLKINSEL_ == 0) ? IS_CLKINSEL_INVERTED :
\t\t\t IS_CLKINSEL_INVERTED;
generate
if (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) begin
wire clkinsel = 1\'b1;
end else if (_TECHMAP_CONSTVAL_CLKINSEL_ == 0) begin
wire clkinsel = 1\'b1;
end else begin
wire clkinsel = CLKINSEL;
end
endgenerate
localparam INV_PWRDWN = (_TECHMAP_CONSTMSK_PWRDWN_ == 1) ? !_TECHMAP_CONSTVAL_PWRDWN_ :
\t\t\t (_TECHMAP_CONSTVAL_PWRDWN_ == 0) ? ~IS_PWRDWN_INVERTED :
\t\t\t IS_PWRDWN_INVERTED;
generate
if (_TECHMAP_CONSTMSK_PWRDWN_ == 1) begin
wire pwrdwn = 1\'b1;
end else if (_TECHMAP_CONSTVAL_PWRDWN_ == 0) begin
wire pwrdwn = 1\'b1;
end else begin
wire pwrdwn = PWRDWN;
end
endgenerate
localparam INV_RST = (_TECHMAP_CONSTMSK_RST_ == 1) ? !_TECHMAP_CONSTVAL_PWRDWN_ :
\t\t (_TECHMAP_CONSTVAL_RST_ == 0) ? ~IS_RST_INVERTED : IS_RST_INVERTED;
generate
if (_TECHMAP_CONSTMSK_RST_ == 1) begin
wire rst = 1\'b1;
end else if (_TECHMAP_CONSTVAL_RST_ == 0) begin
wire rst = 1\'b1;
end else begin
wire rst = RST;
end
endgenerate
generate
if (_TECHMAP_CONSTMSK_DCLK_ == 1) wire dclk = _TECHMAP_CONSTVAL_DCLK_;
else if (_TECHMAP_CONSTVAL_DCLK_ == 0) wire dclk = 1\'b0;
else wire dclk = DCLK;
endgenerate
generate
if (_TECHMAP_CONSTMSK_DEN_ == 1) wire den = _TECHMAP_CONSTVAL_DEN_;
else if (_TECHMAP_CONSTVAL_DEN_ == 0) wire den = 1\'b0;
else wire den = DEN;
endgenerate
generate
if (_TECHMAP_CONSTMSK_DWE_ == 1) wire dwe = _TECHMAP_CONSTVAL_DWE_;
else if (_TECHMAP_CONSTVAL_DWE_ == 0) wire dwe = 1\'b0;
else wire dwe = DWE;
endgenerate
// The substituted cell
PLLE2_ADV_VPR #(
// Inverters
.INV_CLKINSEL(INV_CLKINSEL),
.ZINV_PWRDWN (INV_PWRDWN),
.ZINV_RST (INV_RST),
// Straight mapped parameters
.STARTUP_WAIT(STARTUP_WAIT == "TRUE"),
// Lookup tables
.LKTABLE(pll_lktable_lookup(CLKFBOUT_MULT)),
.TABLE (pll_table_lookup(CLKFBOUT_MULT, BANDWIDTH)),
// FIXME: How to compute values the two below ?
.FILTREG1_RESERVED(12\'b0000_00001000),
.LOCKREG3_RESERVED(1\'b1),
// Clock feedback settings
.CLKFBOUT_CLKOUT1_HIGH_TIME (CLKFBOUT_REGS[11:6]),
.CLKFBOUT_CLKOUT1_LOW_TIME (CLKFBOUT_REGS[5:0]),
.CLKFBOUT_CLKOUT1_PHASE_MUX (CLKFBOUT_REGS[15:13]),
.CLKFBOUT_CLKOUT2_DELAY_TIME(CLKFBOUT_REGS[21:16]),
.CLKFBOUT_CLKOUT2_EDGE (CLKFBOUT_REGS[23]),
.CLKFBOUT_CLKOUT2_NO_COUNT (CLKFBOUT_REGS[22]),
// Internal VCO divider settings
.DIVCLK_DIVCLK_HIGH_TIME(DIVCLK_REGS[11:6]),
.DIVCLK_DIVCLK_LOW_TIME (DIVCLK_REGS[5:0]),
.DIVCLK_DIVCLK_NO_COUNT (DIVCLK_REGS[22]),
.DIVCLK_DIVCLK_EDGE (DIVCLK_REGS[23]),
// CLKOUT0
.CLKOUT0_CLKOUT1_HIGH_TIME (CLKOUT0_REGS[11:6]),
.CLKOUT0_CLKOUT1_LOW_TIME (CLKOUT0_REGS[5:0]),
.CLKOUT0_CLKOUT1_PHASE_MUX (CLKOUT0_REGS[15:13]),
.CLKOUT0_CLKOUT2_DELAY_TIME(CLKOUT0_REGS[21:16]),
.CLKOUT0_CLKOUT2_EDGE (CLKOUT0_REGS[23]),
.CLKOUT0_CLKOUT2_NO_COUNT (CLKOUT0_REGS[22]),
// CLKOUT1
.CLKOUT1_CLKOUT1_HIGH_TIME (CLKOUT1_REGS[11:6]),
.CLKOUT1_CLKOUT1_LOW_TIME (CLKOUT1_REGS[5:0]),
.CLKOUT1_CLKOUT1_PHASE_MUX (CLKOUT1_REGS[15:13]),
.CLKOUT1_CLKOUT2_DELAY_TIME(CLKOUT1_REGS[21:16]),
.CLKOUT1_CLKOUT2_EDGE (CLKOUT1_REGS[23]),
.CLKOUT1_CLKOUT2_NO_COUNT (CLKOUT1_REGS[22]),
// CLKOUT2
.CLKOUT2_CLKOUT1_HIGH_TIME (CLKOUT2_REGS[11:6]),
.CLKOUT2_CLKOUT1_LOW_TIME (CLKOUT2_REGS[5:0]),
.CLKOUT2_CLKOUT1_PHASE_MUX (CLKOUT2_REGS[15:13]),
.CLKOUT2_CLKOUT2_DELAY_TIME(CLKOUT2_REGS[21:16]),
.CLKOUT2_CLKOUT2_EDGE (CLKOUT2_REGS[23]),
.CLKOUT2_CLKOUT2_NO_COUNT (CLKOUT2_REGS[22]),
// CLKOUT3
.CLKOUT3_CLKOUT1_HIGH_TIME (CLKOUT3_REGS[11:6]),
.CLKOUT3_CLKOUT1_LOW_TIME (CLKOUT3_REGS[5:0]),
.CLKOUT3_CLKOUT1_PHASE_MUX (CLKOUT3_REGS[15:13]),
.CLKOUT3_CLKOUT2_DELAY_TIME(CLKOUT3_REGS[21:16]),
.CLKOUT3_CLKOUT2_EDGE (CLKOUT3_REGS[23]),
.CLKOUT3_CLKOUT2_NO_COUNT (CLKOUT3_REGS[22]),
// CLKOUT4
.CLKOUT4_CLKOUT1_HIGH_TIME (CLKOUT4_REGS[11:6]),
.CLKOUT4_CLKOUT1_LOW_TIME (CLKOUT4_REGS[5:0]),
.CLKOUT4_CLKOUT1_PHASE_MUX (CLKOUT4_REGS[15:13]),
.CLKOUT4_CLKOUT2_DELAY_TIME(CLKOUT4_REGS[21:16]),
.CLKOUT4_CLKOUT2_EDGE (CLKOUT4_REGS[23]),
.CLKOUT4_CLKOUT2_NO_COUNT (CLKOUT4_REGS[22]),
// CLKOUT5
.CLKOUT5_CLKOUT1_HIGH_TIME (CLKOUT5_REGS[11:6]),
.CLKOUT5_CLKOUT1_LOW_TIME (CLKOUT5_REGS[5:0]),
.CLKOUT5_CLKOUT1_PHASE_MUX (CLKOUT5_REGS[15:13]),
.CLKOUT5_CLKOUT2_DELAY_TIME(CLKOUT5_REGS[21:16]),
.CLKOUT5_CLKOUT2_EDGE (CLKOUT5_REGS[23]),
.CLKOUT5_CLKOUT2_NO_COUNT (CLKOUT5_REGS[22]),
// Clock output enable controls
.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKFBOUT_ === 1\'bX),
.CLKOUT0_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT0_ === 1\'bX),
.CLKOUT1_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT1_ === 1\'bX),
.CLKOUT2_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT2_ === 1\'bX),
.CLKOUT3_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT3_ === 1\'bX),
.CLKOUT4_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT4_ === 1\'bX),
.CLKOUT5_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT5_ === 1\'bX)
) _TECHMAP_REPLACE_ (
.CLKFBIN (CLKFBIN),
.CLKIN1 (CLKIN1),
.CLKIN2 (CLKIN2),
.CLKFBOUT(CLKFBOUT),
.CLKOUT0 (CLKOUT0),
.CLKOUT1 (CLKOUT1),
.CLKOUT2 (CLKOUT2),
.CLKOUT3 (CLKOUT3),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKINSEL(clkinsel),
.PWRDWN(pwrdwn),
.RST (rst),
.LOCKED(LOCKED),
.DCLK (dclk),
.DEN (den),
.DWE (dwe),
.DRDY (DRDY),
.DADDR(DADDR),
.DI (DI),
.DO (DO)
);
endmodule
// PLLE2_BASE
module PLLE2_BASE (
input CLKFBIN,
input CLKIN,
output CLKFBOUT,
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
input RST,
output LOCKED
);
parameter IS_CLKINSEL_INVERTED = 1\'b0;
parameter IS_RST_INVERTED = 1\'b0;
parameter BANDWIDTH = "OPTIMIZED";
parameter STARTUP_WAIT = "FALSE";
parameter CLKIN1_PERIOD = 0.0;
parameter REF_JITTER1 = 0.1;
parameter [5:0] DIVCLK_DIVIDE = 1;
parameter [5:0] CLKFBOUT_MULT = 1;
parameter signed CLKFBOUT_PHASE = 0;
parameter [6:0] CLKOUT0_DIVIDE = 1;
parameter CLKOUT0_DUTY_CYCLE = 50000;
parameter signed CLKOUT0_PHASE = 0;
parameter [6:0] CLKOUT1_DIVIDE = 1;
parameter CLKOUT1_DUTY_CYCLE = 50000;
parameter signed CLKOUT1_PHASE = 0;
parameter [6:0] CLKOUT2_DIVIDE = 1;
parameter CLKOUT2_DUTY_CYCLE = 50000;
parameter signed CLKOUT2_PHASE = 0;
parameter [6:0] CLKOUT3_DIVIDE = 1;
parameter CLKOUT3_DUTY_CYCLE = 50000;
parameter signed CLKOUT3_PHASE = 0;
parameter [6:0] CLKOUT4_DIVIDE = 1;
parameter CLKOUT4_DUTY_CYCLE = 50000;
parameter signed CLKOUT4_PHASE = 0;
parameter [6:0] CLKOUT5_DIVIDE = 1;
parameter CLKOUT5_DUTY_CYCLE = 50000;
parameter signed CLKOUT5_PHASE = 0;
// The substituted cell
PLLE2_ADV #(
.IS_CLKINSEL_INVERTED(IS_CLKINSEL_INVERTED),
.IS_RST_INVERTED(IS_RST_INVERTED),
.IS_PWRDWN_INVERTED(1\'b0),
.BANDWIDTH(BANDWIDTH),
.STARTUP_WAIT(STARTUP_WAIT),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.REF_JITTER1 (REF_JITTER1),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE)
) _TECHMAP_REPLACE_ (
.CLKFBIN (CLKFBIN),
.CLKIN1 (CLKIN),
.CLKINSEL(1\'b1),
.CLKFBOUT(CLKFBOUT),
.CLKOUT0 (CLKOUT0),
.CLKOUT1 (CLKOUT1),
.CLKOUT2 (CLKOUT2),
.CLKOUT3 (CLKOUT3),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.PWRDWN(1\'b0),
.RST(RST),
.LOCKED(LOCKED),
.DCLK(1\'b0),
.DEN(1\'b0),
.DWE(1\'b0),
.DRDY(),
.DADDR(7\'d0),
.DI(16\'d0),
.DO()
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \\$lut (
A,
Y
);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0])
);
end else if (WIDTH == 2) begin
LUT2 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0]),
.I1(A[1])
);
end else if (WIDTH == 3) begin
LUT3 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0]),
.I1(A[1]),
.I2(A[2])
);
end else if (WIDTH == 4) begin
LUT4 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0]),
.I1(A[1]),
.I2(A[2]),
.I3(A[3])
);
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n,
input rx_n,
input rx_p,
output tx_n,
output tx_p,
input ibufds_gte2_i,
input ibufds_gte2_ib
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1\'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
GTPE2_CHANNEL GTPE2_CHANNEL (
.GTPRXP(rx_p),
.GTPRXN(rx_n),
.GTPTXP(tx_p),
.GTPTXN(tx_n)
);
(* keep *)
IBUFDS_GTE2 IBUFDS_GTE2 (
.I (ibufds_gte2_i),
.IB(ibufds_gte2_ib)
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input cpu_reset,
input data_in,
output [5:0] data_out
);
wire [5:0] data_out;
wire builder_pll_fb;
wire fdce_0_out, fdce_1_out;
wire main_locked;
FDCE FDCE_0 (
.D (data_in),
.C (clk),
.CE (1\'b1),
.CLR(1\'b0),
.Q (fdce_0_out)
);
FDCE FDCE_1 (
.D (fdce_0_out),
.C (clk),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[0])
);
PLLE2_ADV #(
.CLKFBOUT_MULT(4\'d12),
.CLKFBOUT_PHASE(90.0),
.CLKIN1_PERIOD(9.99999),
.CLKOUT0_DIVIDE(4\'d12),
.CLKOUT0_PHASE(90.0),
.CLKOUT1_DIVIDE(3\'d6),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(2\'d3),
.CLKOUT2_PHASE(90.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout_x1),
.CLKOUT1(main_clkout_x2),
.CLKOUT2(main_clkout_x4),
.LOCKED(main_locked)
);
FDCE FDCE_PLLx1_PH90 (
.D (data_in),
.C (main_clkout_x1),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[1])
);
FDCE FDCE_PLLx4_PH0_0 (
.D (data_in),
.C (main_clkout_x2),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[2])
);
FDCE FDCE_PLLx4_PH0_1 (
.D (data_in),
.C (main_clkout_x2),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[3])
);
FDCE FDCE_PLLx4_PH0_2 (
.D (data_in),
.C (main_clkout_x2),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[4])
);
FDCE FDCE_PLLx2_PH90_0 (
.D (data_in),
.C (main_clkout_x4),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[5])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input cpu_reset,
input data_in,
output [5:0] data_out
);
wire [5:0] data_out;
wire builder_pll_fb;
wire fdce_0_out, fdce_1_out;
wire main_locked;
FDCE FDCE_0 (
.D (data_in),
.C (clk),
.CE (1\'b1),
.CLR(1\'b0),
.Q (fdce_0_out)
);
FDCE FDCE_1 (
.D (fdce_0_out),
.C (clk),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[0])
);
PLLE2_ADV #(
.CLKFBOUT_MULT(4\'d12),
.CLKFBOUT_PHASE(90.0),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(4\'d12),
.CLKOUT0_PHASE(90.0),
.CLKOUT1_DIVIDE(3\'d6),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(2\'d3),
.CLKOUT2_PHASE(90.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout_x1),
.CLKOUT1(main_clkout_x2),
.CLKOUT2(main_clkout_x4),
.LOCKED(main_locked)
);
FDCE FDCE_PLLx1_PH90 (
.D (data_in),
.C (main_clkout_x1),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[1])
);
FDCE FDCE_PLLx4_PH0_0 (
.D (data_in),
.C (main_clkout_x2),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[2])
);
FDCE FDCE_PLLx4_PH0_1 (
.D (data_in),
.C (main_clkout_x2),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[3])
);
FDCE FDCE_PLLx4_PH0_2 (
.D (data_in),
.C (main_clkout_x2),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[4])
);
FDCE FDCE_PLLx2_PH90_0 (
.D (data_in),
.C (main_clkout_x4),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[5])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module my_ram (
CLK,
WADR,
WDAT,
WEN,
RADR,
RDAT,
REN
);
parameter DBITS = 36;
parameter ABITS = 9;
input wire CLK;
input wire [ABITS-1:0] WADR;
input wire [DBITS-1:0] WDAT;
input wire WEN;
input wire [ABITS-1:0] RADR;
output reg [DBITS-1:0] RDAT;
input wire REN;
localparam SIZE = 1 << ABITS;
reg [DBITS-1:0] mem[0:SIZE-1];
always @(posedge CLK) begin
if (WEN) mem[WADR] <= WDAT;
end
always @(posedge CLK) begin
RDAT <= mem[RADR];
end
endmodule
// ============================================================================
module top_bram_9_16 (
CLK,
WADR,
WDAT,
WEN,
RADR,
RDAT
);
input wire CLK;
input wire [8 : 0] WADR;
input wire [15:0] WDAT;
input wire WEN;
input wire [8 : 0] RADR;
output wire [15:0] RDAT;
my_ram #(
.DBITS(16),
.ABITS(9)
) the_ram (
.CLK (CLK),
.WADR(WADR),
.WDAT(WDAT),
.WEN (WEN),
.RADR(RADR),
.RDAT(RDAT),
.REN (1\'b0)
);
endmodule
module top_bram_9_32 (
CLK,
WADR,
WDAT,
WEN,
RADR,
RDAT
);
input wire CLK;
input wire [8 : 0] WADR;
input wire [31:0] WDAT;
input wire WEN;
input wire [8 : 0] RADR;
output wire [31:0] RDAT;
my_ram #(
.DBITS(32),
.ABITS(9)
) the_ram (
.CLK (CLK),
.WADR(WADR),
.WDAT(WDAT),
.WEN (WEN),
.RADR(RADR),
.RDAT(RDAT),
.REN (1\'b0)
);
endmodule
module top_bram_10_16 (
CLK,
WADR,
WDAT,
WEN,
RADR,
RDAT
);
input wire CLK;
input wire [9 : 0] WADR;
input wire [15:0] WDAT;
input wire WEN;
input wire [9 : 0] RADR;
output wire [15:0] RDAT;
my_ram #(
.DBITS(16),
.ABITS(10)
) the_ram (
.CLK (CLK),
.WADR(WADR),
.WDAT(WDAT),
.WEN (WEN),
.RADR(RADR),
.RDAT(RDAT),
.REN (1\'b0)
);
endmodule
module top_bram_init (
CLK,
WADR,
WDAT,
WEN,
RADR,
RDAT
);
input wire CLK;
input wire [9 : 0] WADR;
input wire [17:0] WDAT;
input wire WEN;
input wire [9 : 0] RADR;
output wire [17:0] RDAT;
RAM_8K_BLK #(
.INIT_FILE ("init.txt"),
.addr_int (9),
.data_depth_int(1 << 9),
.data_width_int(16)
) the_ram (
.WClk (CLK),
.RClk (CLK),
.WClk_En(1\'b1),
.RClk_En(1\'b1),
.WA (WADR),
.WD (WDAT),
.WEN (WEN),
.RA (RADR),
.RD (RDAT)
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \\$__QUICKLOGIC_RAMB16K (
CLK2,
CLK3,
A1ADDR,
A1DATA,
A1EN,
B1ADDR,
B1DATA,
B1EN
);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [16383:0] INIT = 16384\'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire VCC = 1\'b1;
wire GND = 1\'b0;
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
wire [31:0] DOB;
wire [ 3:0] DOPB;
wire [ 1:0] WS1_0;
wire [ 1:0] WS1_1;
wire [ 1:0] WS2_0;
wire [ 1:0] WS2_1;
wire [ 4:0] wen_reg;
assign wen_reg[4:CFG_ENABLE_B] = 0;
assign wen_reg[CFG_ENABLE_B-1:0] = B1EN;
assign A1DATA = DO;
assign DI = B1DATA;
if (CFG_DBITS <= 8) begin
assign WS1_0 = 2\'b00;
assign WS2_0 = 2\'b00;
end else if (CFG_DBITS > 8 && CFG_DBITS <= 16) begin
assign WS1_0 = 2\'b01;
assign WS2_0 = 2\'b01;
end else if (CFG_DBITS > 16) begin
assign WS1_0 = 2\'b10;
assign WS2_0 = 2\'b10;
end
generate
if (CFG_DBITS <= 16) begin
ram8k_2x1_cell_macro #(
`include "bram_init_32.vh"
) _TECHMAP_REPLACE_ (
.A1_0(B1ADDR),
.A1_1(GND),
.A2_0(A1ADDR),
.A2_1(GND),
.ASYNC_FLUSH_0(GND),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(GND),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(CLK2),
.CLK1_1(CLK2),
.CLK1S_0(!CLKPOL2),
.CLK1S_1(!CLKPOL2),
.CLK1EN_0(VCC),
.CLK1EN_1(VCC),
.CLK2_0(CLK3),
.CLK2_1(CLK3),
.CLK2S_0(!CLKPOL3),
.CLK2S_1(!CLKPOL3),
.CLK2EN_0(A1EN),
.CLK2EN_1(A1EN),
.CONCAT_EN_0(VCC),
.CONCAT_EN_1(GND),
.CS1_0(VCC),
.CS1_1(GND),
.CS2_0(VCC),
.CS2_1(GND),
.DIR_0(GND),
.DIR_1(GND),
.FIFO_EN_0(GND),
.FIFO_EN_1(GND),
.P1_0(GND),
.P1_1(GND),
.P2_0(GND),
.P2_1(GND),
.PIPELINE_RD_0(GND),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(GND),
.SYNC_FIFO_1(GND),
.WD_1(GND),
.WD_0({GND, DI[15:8], GND, DI[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1(GND),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1(GND),
.WEN1_0(wen_reg[1:0]),
.WEN1_1(wen_reg[3:2]),
.Almost_Empty_0(),
.Almost_Empty_1(),
.Almost_Full_0(),
.Almost_Full_1(),
.POP_FLAG_0(),
.POP_FLAG_1(),
.PUSH_FLAG_0(),
.PUSH_FLAG_1(),
.RD_0({DOP[1], DO[15:8], DOP[0], DO[7:0]}),
.RD_1(),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
end else if (CFG_DBITS <= 32) begin
ram8k_2x1_cell_macro #(
`include "bram_init_32.vh"
) _TECHMAP_REPLACE_ (
.A1_0(B1ADDR),
.A1_1(GND),
.A2_0(A1ADDR),
.A2_1(GND),
.ASYNC_FLUSH_0(GND),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(GND),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(CLK2),
.CLK1_1(CLK2),
.CLK1S_0(!CLKPOL2),
.CLK1S_1(!CLKPOL2),
.CLK1EN_0(VCC),
.CLK1EN_1(VCC),
.CLK2_0(CLK3),
.CLK2_1(CLK3),
.CLK2S_0(!CLKPOL3),
.CLK2S_1(!CLKPOL3),
.CLK2EN_0(A1EN),
.CLK2EN_1(A1EN),
.CONCAT_EN_0(VCC),
.CONCAT_EN_1(GND),
.CS1_0(VCC),
.CS1_1(GND),
.CS2_0(VCC),
.CS2_1(GND),
.DIR_0(GND),
.DIR_1(GND),
.FIFO_EN_0(GND),
.FIFO_EN_1(GND),
.P1_0(GND),
.P1_1(GND),
.P2_0(GND),
.P2_1(GND),
.PIPELINE_RD_0(GND),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(GND),
.SYNC_FIFO_1(GND),
.WD_1({GND, DI[31:24], GND, DI[23:16]}),
.WD_0({GND, DI[15:8], GND, DI[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1(GND),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1(GND),
.WEN1_0(wen_reg[1:0]),
.WEN1_1(wen_reg[3:2]),
.Almost_Empty_0(),
.Almost_Empty_1(),
.Almost_Full_0(),
.Almost_Full_1(),
.POP_FLAG_0(),
.POP_FLAG_1(),
.PUSH_FLAG_0(),
.PUSH_FLAG_1(),
.RD_0({DOP[1], DO[15:8], DOP[0], DO[7:0]}),
.RD_1({DOP[3], DO[31:24], DOP[2], DO[23:16]}),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
end else begin
wire TECHMAP_FAIL = 1\'b1;
end
endgenerate
endmodule
// ------------------------------------------------------------------------
module \\$__QUICKLOGIC_RAMB8K (
CLK2,
CLK3,
A1ADDR,
A1DATA,
A1EN,
B1ADDR,
B1DATA,
B1EN
);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 18;
parameter CFG_ENABLE_B = 2;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [8191:0] INIT = 8192\'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [10:0] A1ADDR_11;
wire [10:0] B1ADDR_11;
wire [1:0] DIP, DOP;
wire [15:0] DI, DO;
wire [15:0] DOBDO;
wire [ 1:0] DOPBDOP;
wire [ 1:0] WS1_0;
wire [ 1:0] WS1_1;
wire [ 1:0] WS2_0;
wire [ 1:0] WS2_1;
wire [ 2:0] wen_reg;
assign wen_reg[2:CFG_ENABLE_B] = 0;
assign wen_reg[CFG_ENABLE_B-1:0] = B1EN;
wire GND = 1\'b0;
wire VCC = 1\'b1;
assign A1DATA = DO;
assign DI = B1DATA;
if (CFG_ABITS == 11) begin
assign A1ADDR_11[CFG_ABITS-1:0] = A1ADDR;
assign B1ADDR_11[CFG_ABITS-1:0] = B1ADDR;
end else begin
assign A1ADDR_11[10:CFG_ABITS] = 0;
assign A1ADDR_11[CFG_ABITS-1:0] = A1ADDR;
assign B1ADDR_11[10:CFG_ABITS] = 0;
assign B1ADDR_11[CFG_ABITS-1:0] = B1ADDR;
end
if (CFG_DBITS <= 9) begin
assign WS1_0 = 2\'b00;
assign WS2_0 = 2\'b00;
end else if (CFG_DBITS > 9 && CFG_DBITS <= 18) begin
assign WS1_0 = 2\'b01;
assign WS2_0 = 2\'b01;
end else if (CFG_DBITS > 18) begin
assign WS1_0 = 2\'b10;
assign WS2_0 = 2\'b10;
end
ram8k_2x1_cell_macro #(
`include "bram_init_8_16.vh"
) _TECHMAP_REPLACE_ (
.A1_0(B1ADDR_11),
.A1_1(GND),
.A2_0(A1ADDR_11),
.A2_1(GND),
.ASYNC_FLUSH_0(GND),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(GND),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(CLK2),
.CLK1_1(GND),
.CLK1S_0(!CLKPOL2),
.CLK1S_1(GND),
.CLK1EN_0(VCC),
.CLK1EN_1(VCC),
.CLK2_0(CLK3),
.CLK2_1(GND),
.CLK2S_0(!CLKPOL3),
.CLK2S_1(GND),
.CLK2EN_0(A1EN),
.CLK2EN_1(GND),
.CONCAT_EN_0(GND),
.CONCAT_EN_1(GND),
.CS1_0(VCC),
.CS1_1(GND),
.CS2_0(VCC),
.CS2_1(GND),
.DIR_0(GND),
.DIR_1(GND),
.FIFO_EN_0(GND),
.FIFO_EN_1(GND),
.P1_0(GND),
.P1_1(GND),
.P2_0(GND),
.P2_1(GND),
.PIPELINE_RD_0(GND),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(GND),
.SYNC_FIFO_1(GND),
.WD_1(GND),
.WD_0({GND, DI[15:8], GND, DI[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1(GND),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1(GND),
.WEN1_0(wen_reg[1:0]),
.WEN1_1(GND),
.Almost_Empty_0(),
.Almost_Empty_1(),
.Almost_Full_0(),
.Almost_Full_1(),
.POP_FLAG_0(),
.POP_FLAG_1(),
.PUSH_FLAG_0(),
.PUSH_FLAG_1(),
.RD_0({DOP[1], DO[15:8], DOP[0], DO[7:0]}),
.RD_1(),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
endmodule
module RAM_8K_BLK (
WA,
RA,
WD,
WClk,
RClk,
WClk_En,
RClk_En,
WEN,
RD
);
parameter addr_int \t= 9,
data_depth_int = 512,
data_width_int = 18,
wr_enable_int \t= 2,
reg_rd_int \t= 0;
parameter [8191:0] INIT = 8192\'bx;
parameter INIT_FILE = "init.mem";
input [addr_int-1:0] WA;
input [addr_int-1:0] RA;
input WClk, RClk;
input WClk_En, RClk_En;
input [wr_enable_int-1:0] WEN;
input [data_width_int-1:0] WD;
output [data_width_int-1:0] RD;
wire VCC, GND;
wire WClk0_Sel, RClk0_Sel;
wire WClk1_Sel, RClk1_Sel;
wire reg_rd0;
wire reg_rd1;
wire [10:0] addr_wr0, addr_rd0, addr_wr1, addr_rd1;
wire [17:0] in_reg0;
wire [ 2:0] wen_reg0;
wire [15:0] out_reg0;
wire [ 1:0] out_par0;
wire [1:0] WS1_0, WS2_0;
wire [1:0] WS_GND;
wire LS, DS, SD, LS_RB1, DS_RB1, SD_RB1;
wire WD0_SEL, RD0_SEL;
wire WD1_SEL, RD1_SEL;
assign VCC = 1\'b1;
assign GND = 1\'b0;
assign WD0_SEL = 1\'b1;
assign RD0_SEL = 1\'b1;
assign WD1_SEL = 1\'b0;
assign RD1_SEL = 1\'b0;
assign WClk0_Sel = 1\'b0;
assign RClk0_Sel = 1\'b0;
assign WClk1_Sel = 1\'b0;
assign RClk1_Sel = 1\'b0;
assign LS = 1\'b0;
assign DS = 1\'b0;
assign SD = 1\'b0;
assign LS_RB1 = 1\'b0;
assign DS_RB1 = 1\'b0;
assign SD_RB1 = 1\'b0;
assign reg_rd0 = reg_rd_int;
assign WS_GND = 2\'b00;
assign reg_rd1 = 1\'b0;
assign wen_reg0[2:wr_enable_int] = 0;
assign wen_reg0[wr_enable_int-1:0] = WEN;
assign addr_wr1 = 11\'b0000000000;
assign addr_rd1 = 11\'b0000000000;
generate
if (addr_int == 11) begin
assign addr_wr0[10:0] = WA;
assign addr_rd0[10:0] = RA;
end else begin
assign addr_wr0[10:addr_int] = 0;
assign addr_wr0[addr_int-1:0] = WA;
assign addr_rd0[10:addr_int] = 0;
assign addr_rd0[addr_int-1:0] = RA;
end
if (data_width_int == 16) begin
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end else if (data_width_int > 8 && data_width_int < 16) begin
assign in_reg0[15:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end else if (data_width_int <= 8) begin
assign in_reg0[15:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end
if (data_width_int <= 8) begin
assign WS1_0 = 2\'b00;
assign WS2_0 = 2\'b00;
end else if (data_width_int > 8 && data_width_int <= 16) begin
assign WS1_0 = 2\'b01;
assign WS2_0 = 2\'b01;
end else if (data_width_int > 16) begin
assign WS1_0 = 2\'b10;
assign WS2_0 = 2\'b10;
end
endgenerate
ram8k_2x1_cell_macro #(
.INIT(INIT)
) _TECHMAP_REPLACE_ (
.A1_0(addr_wr0),
.A1_1(addr_wr1),
.A2_0(addr_rd0),
.A2_1(addr_rd1),
.ASYNC_FLUSH_0(GND),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(GND),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(WClk),
.CLK1_1(GND),
.CLK1S_0(WClk0_Sel),
.CLK1S_1(WClk1_Sel),
.CLK1EN_0(WClk_En),
.CLK1EN_1(GND),
.CLK2_0(RClk),
.CLK2_1(GND),
.CLK2S_0(RClk0_Sel),
.CLK2S_1(RClk1_Sel),
.CLK2EN_0(RClk_En),
.CLK2EN_1(GND),
.CONCAT_EN_0(GND),
.CONCAT_EN_1(GND),
.CS1_0(WD0_SEL),
.CS1_1(WD1_SEL),
.CS2_0(RD0_SEL),
.CS2_1(RD1_SEL),
.DIR_0(GND),
.DIR_1(GND),
.FIFO_EN_0(GND),
.FIFO_EN_1(GND),
.P1_0(GND),
.P1_1(GND),
.P2_0(GND),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(reg_rd1),
.SYNC_FIFO_0(GND),
.SYNC_FIFO_1(GND),
.WD_1({18{GND}}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1(WS_GND),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1(WS_GND),
.WEN1_0(wen_reg0[1:0]),
.WEN1_1({2{GND}}),
.Almost_Empty_0(),
.Almost_Empty_1(),
.Almost_Full_0(),
.Almost_Full_1(),
.POP_FLAG_0(),
.POP_FLAG_1(),
.PUSH_FLAG_0(),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1(),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
assign RD[data_width_int-1 : 0] = {out_par0, out_reg0};
endmodule
module RAM_16K_BLK (
WA,
RA,
WD,
WClk,
RClk,
WClk_En,
RClk_En,
WEN,
RD
);
parameter addr_int = 9,
data_depth_int = 512,
\t data_width_int = 36,
wr_enable_int = 4,
\t reg_rd_int \t = 0;
parameter [16383:0] INIT = 16384\'bx;
parameter INIT_FILE = "init.mem";
input [addr_int-1:0] WA;
input [addr_int-1:0] RA;
input WClk, RClk;
input WClk_En, RClk_En;
input [wr_enable_int-1:0] WEN;
input [data_width_int-1:0] WD;
output [data_width_int-1:0] RD;
wire VCC, GND;
wire WClk0_Sel, RClk0_Sel;
wire WClk1_Sel, RClk1_Sel;
wire reg_rd0;
wire reg_rd1;
wire [10:0] addr_wr0, addr_rd0, addr_wr1, addr_rd1;
wire [31:0] in_reg0;
wire [ 4:0] wen_reg0;
wire [31:0] out_reg0;
wire [ 3:0] out_par0;
wire [1:0] WS1_0, WS2_0;
wire [1:0] WS_GND;
wire LS, DS, SD, LS_RB1, DS_RB1, SD_RB1;
wire WD0_SEL, RD0_SEL;
wire WD1_SEL, RD1_SEL;
assign VCC = 1\'b1;
assign GND = 1\'b0;
assign WD0_SEL = 1\'b1;
assign RD0_SEL = 1\'b1;
assign WD1_SEL = 1\'b1;
assign RD1_SEL = 1\'b1;
assign WClk0_Sel = 1\'b0;
assign RClk0_Sel = 1\'b0;
assign WClk1_Sel = 1\'b0;
assign RClk1_Sel = 1\'b0;
assign LS = 1\'b0;
assign DS = 1\'b0;
assign SD = 1\'b0;
assign LS_RB1 = 1\'b0;
assign DS_RB1 = 1\'b0;
assign SD_RB1 = 1\'b0;
assign reg_rd0 = reg_rd_int;
assign WS_GND = 2\'b00;
assign reg_rd1 = 1\'b0;
assign wen_reg0[4:wr_enable_int] = 0;
assign wen_reg0[wr_enable_int-1:0] = WEN;
assign addr_wr1 = 11\'b0000000000;
assign addr_rd1 = 11\'b0000000000;
generate
if (addr_int == 11) begin
assign addr_wr0[10:0] = WA;
assign addr_rd0[10:0] = RA;
end else begin
assign addr_wr0[10:addr_int] = 0;
assign addr_wr0[addr_int-1:0] = WA;
assign addr_rd0[10:addr_int] = 0;
assign addr_rd0[addr_int-1:0] = RA;
end
if (data_width_int == 32) begin
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end else if (data_width_int > 8 && data_width_int < 32) begin
assign in_reg0[31:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end else if (data_width_int <= 8) begin
assign in_reg0[31:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = WD[data_width_int-1:0];
end
if (data_width_int <= 8) begin
assign WS1_0 = 2\'b00;
assign WS2_0 = 2\'b00;
end else if (data_width_int > 8 && data_width_int <= 16) begin
assign WS1_0 = 2\'b01;
assign WS2_0 = 2\'b01;
end else if (data_width_int > 16) begin
assign WS1_0 = 2\'b10;
assign WS2_0 = 2\'b10;
end
if (data_width_int <= 16) begin
ram8k_2x1_cell_macro #(
.INIT(INIT)
) _TECHMAP_REPLACE_ (
.A1_0(addr_wr0),
.A1_1(addr_wr1),
.A2_0(addr_rd0),
.A2_1(addr_rd1),
.ASYNC_FLUSH_0(GND),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(GND),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(WClk),
.CLK1_1(WClk),
.CLK1S_0(WClk0_Sel),
.CLK1S_1(WClk0_Sel),
.CLK1EN_0(WClk_En),
.CLK1EN_1(WClk_En),
.CLK2_0(RClk),
.CLK2_1(RClk),
.CLK2S_0(RClk0_Sel),
.CLK2S_1(RClk0_Sel),
.CLK2EN_0(RClk_En),
.CLK2EN_1(RClk_En),
.CONCAT_EN_0(VCC),
.CONCAT_EN_1(GND),
.CS1_0(WD0_SEL),
.CS1_1(GND),
.CS2_0(RD0_SEL),
.CS2_1(GND),
.DIR_0(GND),
.DIR_1(GND),
.FIFO_EN_0(GND),
.FIFO_EN_1(GND),
.P1_0(GND),
.P1_1(GND),
.P2_0(GND),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(GND),
.SYNC_FIFO_1(GND),
.WD_1({18{GND}}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1(WS_GND),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1(WS_GND),
.WEN1_0(wen_reg0[1:0]),
.WEN1_1(wen_reg0[3:2]),
.Almost_Empty_0(),
.Almost_Empty_1(),
.Almost_Full_0(),
.Almost_Full_1(),
.POP_FLAG_0(),
.POP_FLAG_1(),
.PUSH_FLAG_0(),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1(),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
end else if (data_width_int > 16) begin
ram8k_2x1_cell_macro #(
.INIT(INIT)
) _TECHMAP_REPLACE_ (
.A1_0(addr_wr0),
.A1_1(addr_wr1),
.A2_0(addr_rd0),
.A2_1(addr_rd1),
.ASYNC_FLUSH_0(GND),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(GND),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(WClk),
.CLK1_1(WClk),
.CLK1S_0(WClk0_Sel),
.CLK1S_1(WClk0_Sel),
.CLK1EN_0(WClk_En),
.CLK1EN_1(WClk_En),
.CLK2_0(RClk),
.CLK2_1(RClk),
.CLK2S_0(RClk0_Sel),
.CLK2S_1(RClk0_Sel),
.CLK2EN_0(RClk_En),
.CLK2EN_1(RClk_En),
.CONCAT_EN_0(VCC),
.CONCAT_EN_1(GND),
.CS1_0(WD0_SEL),
.CS1_1(GND),
.CS2_0(RD0_SEL),
.CS2_1(GND),
.DIR_0(GND),
.DIR_1(GND),
.FIFO_EN_0(GND),
.FIFO_EN_1(GND),
.P1_0(GND),
.P1_1(GND),
.P2_0(GND),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(GND),
.SYNC_FIFO_1(GND),
.WD_1({1\'b0, in_reg0[31:24], 1\'b0, in_reg0[23:16]}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1(WS_GND),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1(WS_GND),
.WEN1_0(wen_reg0[1:0]),
.WEN1_1(wen_reg0[3:2]),
.Almost_Empty_0(),
.Almost_Empty_1(),
.Almost_Full_0(),
.Almost_Full_1(),
.POP_FLAG_0(),
.POP_FLAG_1(),
.PUSH_FLAG_0(),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1({out_par0[3], out_reg0[31:24], out_par0[2], out_reg0[23:16]}),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
end else begin
wire TECHMAP_FAIL = 1\'b1;
end
endgenerate
assign RD[data_width_int-1 : 0] = {out_par0, out_reg0};
endmodule
module FIFO_8K_BLK (
DIN,
Fifo_Push_Flush,
Fifo_Pop_Flush,
PUSH,
POP,
Push_Clk,
Pop_Clk,
Push_Clk_En,
Pop_Clk_En,
Fifo_Dir,
Async_Flush,
Almost_Full,
Almost_Empty,
PUSH_FLAG,
POP_FLAG,
DOUT
);
parameter data_depth_int = 512, data_width_int = 18, reg_rd_int = 0, sync_fifo_int = 0;
input Fifo_Push_Flush, Fifo_Pop_Flush;
input Push_Clk, Pop_Clk;
input PUSH, POP;
input [data_width_int-1:0] DIN;
input Push_Clk_En, Pop_Clk_En, Fifo_Dir, Async_Flush;
output [data_width_int-1:0] DOUT;
output [3:0] PUSH_FLAG, POP_FLAG;
output Almost_Full, Almost_Empty;
wire LS, DS, SD, LS_RB1, DS_RB1, SD_RB1;
wire VCC, GND;
wire [10:0] addr_wr, addr_rd;
wire clk1_sig0, clk2_sig0, clk1_sig_en0, clk2_sig_en0, fifo_clk1_flush_sig0, fifo_clk2_flush_sig0, p1_sig0, p2_sig0,clk1_sig_sel0,clk2_sig_sel0;
wire reg_rd0, sync_fifo0;
wire [15:0] in_reg0;
wire [15:0] out_reg0;
wire [ 1:0] WS1_0;
wire [ 1:0] WS2_0;
wire Push_Clk0_Sel, Pop_Clk0_Sel;
wire Async_Flush_Sel0;
wire [1:0] out_par0;
assign LS = 1\'b0;
assign DS = 1\'b0;
assign SD = 1\'b0;
assign LS_RB1 = 1\'b0;
assign DS_RB1 = 1\'b0;
assign SD_RB1 = 1\'b0;
assign VCC = 1\'b1;
assign GND = 1\'b0;
assign Push_Clk0_Sel \t= 1\'b0;
assign Pop_Clk0_Sel \t= 1\'b0;
assign Async_Flush_Sel0 = 1\'b0;
assign reg_rd0 = reg_rd_int;
assign sync_fifo0 = sync_fifo_int;
assign addr_wr=11\'b00000000000;
assign addr_rd=11\'b00000000000;
assign clk1_sig0 = Fifo_Dir ? Pop_Clk : Push_Clk;
assign clk2_sig0 = Fifo_Dir ? Push_Clk : Pop_Clk ;
assign clk1_sig_en0 = Fifo_Dir ? Pop_Clk_En : Push_Clk_En;
assign clk2_sig_en0 = Fifo_Dir ? Push_Clk_En : Pop_Clk_En ;
assign clk1_sig_sel0 = Push_Clk0_Sel;
assign clk2_sig_sel0 = Pop_Clk0_Sel ;
assign fifo_clk1_flush_sig0 = Fifo_Dir ? Fifo_Pop_Flush : Fifo_Push_Flush;
assign fifo_clk2_flush_sig0 = Fifo_Dir ? Fifo_Push_Flush : Fifo_Pop_Flush ;
assign p1_sig0 = Fifo_Dir ? POP : PUSH;
assign p2_sig0 = Fifo_Dir ? PUSH : POP ;
generate
if (data_width_int == 16) begin
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end else if (data_width_int > 8 && data_width_int < 16) begin
assign in_reg0[15:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end else if (data_width_int <= 8) begin
assign in_reg0[15:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end
if (data_width_int <= 8) begin
assign WS1_0 = 2\'b00;
assign WS2_0 = 2\'b00;
end else if (data_width_int > 8 && data_width_int <= 16) begin
assign WS1_0 = 2\'b01;
assign WS2_0 = 2\'b01;
end else if (data_width_int > 16) begin
assign WS1_0 = 2\'b10;
assign WS2_0 = 2\'b10;
end
endgenerate
ram8k_2x1_cell_macro _TECHMAP_REPLACE_ (
.A1_0(addr_wr),
.A1_1(addr_wr),
.A2_0(addr_rd),
.A2_1(addr_rd),
.ASYNC_FLUSH_0(Async_Flush),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(Async_Flush_Sel0),
.ASYNC_FLUSH_S1(GND),
.CLK1_0(clk1_sig0),
.CLK1_1(GND),
.CLK1EN_0(clk1_sig_en0),
.CLK1EN_1(GND),
.CLK2_0(clk2_sig0),
.CLK2_1(GND),
.CLK1S_0(clk1_sig_sel0),
.CLK1S_1(GND),
.CLK2S_0(clk2_sig_sel0),
.CLK2S_1(GND),
.CLK2EN_0(clk2_sig_en0),
.CLK2EN_1(GND),
.CONCAT_EN_0(GND),
.CONCAT_EN_1(GND),
.CS1_0(fifo_clk1_flush_sig0),
.CS1_1(GND),
.CS2_0(fifo_clk2_flush_sig0),
.CS2_1(GND),
.DIR_0(Fifo_Dir),
.DIR_1(GND),
.FIFO_EN_0(VCC),
.FIFO_EN_1(GND),
.P1_0(p1_sig0),
.P1_1(GND),
.P2_0(p2_sig0),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(sync_fifo0),
.SYNC_FIFO_1(GND),
.WD_1({18{GND}}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1({GND, GND}),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1({GND, GND}),
.WEN1_0({GND, GND}),
.WEN1_1({GND, GND}),
.Almost_Empty_0(Almost_Empty),
.Almost_Empty_1(),
.Almost_Full_0(Almost_Full),
.Almost_Full_1(),
.POP_FLAG_0(POP_FLAG),
.POP_FLAG_1(),
.PUSH_FLAG_0(PUSH_FLAG),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1(),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
assign DOUT[data_width_int-1 : 0] = {out_par0, out_reg0};
endmodule
module FIFO_16K_BLK (
DIN,
Fifo_Push_Flush,
Fifo_Pop_Flush,
PUSH,
POP,
Push_Clk,
Pop_Clk,
Push_Clk_En,
Pop_Clk_En,
Fifo_Dir,
Async_Flush,
Almost_Full,
Almost_Empty,
PUSH_FLAG,
POP_FLAG,
DOUT
);
parameter data_depth_int = 512, data_width_int = 36, reg_rd_int = 0, sync_fifo_int = 0;
input Fifo_Push_Flush, Fifo_Pop_Flush;
input Push_Clk, Pop_Clk;
input PUSH, POP;
input [data_width_int-1:0] DIN;
input Push_Clk_En, Pop_Clk_En, Fifo_Dir, Async_Flush;
output [data_width_int-1:0] DOUT;
output [3:0] PUSH_FLAG, POP_FLAG;
output Almost_Full, Almost_Empty;
wire LS, DS, SD, LS_RB1, DS_RB1, SD_RB1;
wire VCC, GND;
wire [10:0] addr_wr, addr_rd;
wire clk1_sig0, clk2_sig0, clk1_sig_en0, clk2_sig_en0, fifo_clk1_flush_sig0, fifo_clk2_flush_sig0, p1_sig0, p2_sig0,clk1_sig_sel0,clk2_sig_sel0;
wire reg_rd0, sync_fifo0;
wire [31:0] in_reg0;
wire [31:0] out_reg0;
wire [ 1:0] WS1_0;
wire [ 1:0] WS2_0;
wire Push_Clk0_Sel, Pop_Clk0_Sel;
wire Async_Flush_Sel0;
wire [3:0] out_par0;
wire [1:0] out_par1;
assign LS = 1\'b0;
assign DS = 1\'b0;
assign SD = 1\'b0;
assign LS_RB1 = 1\'b0;
assign DS_RB1 = 1\'b0;
assign SD_RB1 = 1\'b0;
assign VCC = 1\'b1;
assign GND = 1\'b0;
assign Push_Clk0_Sel \t= 1\'b0;
assign Pop_Clk0_Sel \t= 1\'b0;
assign Async_Flush_Sel0 = 1\'b0;
assign reg_rd0 = reg_rd_int;
assign sync_fifo0 = sync_fifo_int;
assign addr_wr=11\'b00000000000;
assign addr_rd=11\'b00000000000;
assign clk1_sig0 = Fifo_Dir ? Pop_Clk : Push_Clk;
assign clk2_sig0 = Fifo_Dir ? Push_Clk : Pop_Clk ;
assign clk1_sig_en0 = Fifo_Dir ? Pop_Clk_En : Push_Clk_En;
assign clk2_sig_en0 = Fifo_Dir ? Push_Clk_En : Pop_Clk_En ;
assign clk1_sig_sel0 = Push_Clk0_Sel;
assign clk2_sig_sel0 = Pop_Clk0_Sel ;
assign fifo_clk1_flush_sig0 = Fifo_Dir ? Fifo_Pop_Flush : Fifo_Push_Flush;
assign fifo_clk2_flush_sig0 = Fifo_Dir ? Fifo_Push_Flush : Fifo_Pop_Flush ;
assign p1_sig0 = Fifo_Dir ? POP : PUSH;
assign p2_sig0 = Fifo_Dir ? PUSH : POP ;
generate
if (data_width_int == 32) begin
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end else if (data_width_int > 8 && data_width_int < 32) begin
assign in_reg0[31:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end else if (data_width_int <= 8) begin
assign in_reg0[31:data_width_int] = 0;
assign in_reg0[data_width_int-1:0] = DIN[data_width_int-1:0];
end
if (data_width_int <= 8) begin
assign WS1_0 = 2\'b00;
assign WS2_0 = 2\'b00;
end else if (data_width_int > 8 && data_width_int <= 16) begin
assign WS1_0 = 2\'b01;
assign WS2_0 = 2\'b01;
end else if (data_width_int > 16) begin
assign WS1_0 = 2\'b10;
assign WS2_0 = 2\'b10;
end
if (data_width_int <= 16) begin
ram8k_2x1_cell_macro _TECHMAP_REPLACE_ (
.A1_0(addr_wr),
.A1_1(addr_wr),
.A2_0(addr_rd),
.A2_1(addr_rd),
.ASYNC_FLUSH_0(Async_Flush),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(Async_Flush_Sel0),
.ASYNC_FLUSH_S1(Async_Flush_Sel0),
.CLK1_0(clk1_sig0),
.CLK1_1(clk1_sig0),
.CLK1EN_0(clk1_sig_en0),
.CLK1EN_1(clk1_sig_en0),
.CLK2_0(clk2_sig0),
.CLK2_1(clk2_sig0),
.CLK1S_0(clk1_sig_sel0),
.CLK1S_1(clk1_sig_sel0),
.CLK2S_0(clk2_sig_sel0),
.CLK2S_1(clk2_sig_sel0),
.CLK2EN_0(clk2_sig_en0),
.CLK2EN_1(clk2_sig_en0),
.CONCAT_EN_0(VCC),
.CONCAT_EN_1(GND),
.CS1_0(fifo_clk1_flush_sig0),
.CS1_1(GND),
.CS2_0(fifo_clk2_flush_sig0),
.CS2_1(GND),
.DIR_0(Fifo_Dir),
.DIR_1(GND),
.FIFO_EN_0(VCC),
.FIFO_EN_1(GND),
.P1_0(p1_sig0),
.P1_1(GND),
.P2_0(p2_sig0),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(sync_fifo0),
.SYNC_FIFO_1(GND),
.WD_1({18{GND}}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1({GND, GND}),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1({GND, GND}),
.WEN1_0({GND, GND}),
.WEN1_1({GND, GND}),
.Almost_Empty_0(Almost_Empty),
.Almost_Empty_1(),
.Almost_Full_0(Almost_Full),
.Almost_Full_1(),
.POP_FLAG_0(POP_FLAG),
.POP_FLAG_1(),
.PUSH_FLAG_0(PUSH_FLAG),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1(),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
end else if (data_width_int > 16) begin
ram8k_2x1_cell_macro _TECHMAP_REPLACE_ (
.A1_0(addr_wr),
.A1_1(addr_wr),
.A2_0(addr_rd),
.A2_1(addr_rd),
.ASYNC_FLUSH_0(Async_Flush),
.ASYNC_FLUSH_1(GND),
.ASYNC_FLUSH_S0(Async_Flush_Sel0),
.ASYNC_FLUSH_S1(Async_Flush_Sel0),
.CLK1_0(clk1_sig0),
.CLK1_1(clk1_sig0),
.CLK1EN_0(clk1_sig_en0),
.CLK1EN_1(clk1_sig_en0),
.CLK2_0(clk2_sig0),
.CLK2_1(clk2_sig0),
.CLK1S_0(clk1_sig_sel0),
.CLK1S_1(clk1_sig_sel0),
.CLK2S_0(clk2_sig_sel0),
.CLK2S_1(clk2_sig_sel0),
.CLK2EN_0(clk2_sig_en0),
.CLK2EN_1(clk2_sig_en0),
.CONCAT_EN_0(VCC),
.CONCAT_EN_1(GND),
.CS1_0(fifo_clk1_flush_sig0),
.CS1_1(GND),
.CS2_0(fifo_clk2_flush_sig0),
.CS2_1(GND),
.DIR_0(Fifo_Dir),
.DIR_1(GND),
.FIFO_EN_0(VCC),
.FIFO_EN_1(GND),
.P1_0(p1_sig0),
.P1_1(GND),
.P2_0(p2_sig0),
.P2_1(GND),
.PIPELINE_RD_0(reg_rd0),
.PIPELINE_RD_1(GND),
.SYNC_FIFO_0(sync_fifo0),
.SYNC_FIFO_1(GND),
.WD_1({1\'b0, in_reg0[31:24], 1\'b0, in_reg0[23:16]}),
.WD_0({1\'b0, in_reg0[15:8], 1\'b0, in_reg0[7:0]}),
.WIDTH_SELECT1_0(WS1_0),
.WIDTH_SELECT1_1({GND, GND}),
.WIDTH_SELECT2_0(WS2_0),
.WIDTH_SELECT2_1({GND, GND}),
.WEN1_0({GND, GND}),
.WEN1_1({GND, GND}),
.Almost_Empty_0(Almost_Empty),
.Almost_Empty_1(),
.Almost_Full_0(Almost_Full),
.Almost_Full_1(),
.POP_FLAG_0(POP_FLAG),
.POP_FLAG_1(),
.PUSH_FLAG_0(PUSH_FLAG),
.PUSH_FLAG_1(),
.RD_0({out_par0[1], out_reg0[15:8], out_par0[0], out_reg0[7:0]}),
.RD_1({out_par0[3], out_reg0[31:24], out_par0[2], out_reg0[23:16]}),
.SD(SD),
.SD_RB1(SD_RB1),
.LS(LS),
.LS_RB1(LS_RB1),
.DS(DS),
.DS_RB1(DS_RB1),
.TEST1A(GND),
.TEST1B(GND),
.RMA(4\'d0),
.RMB(4\'d0),
.RMEA(GND),
.RMEB(GND)
);
end
endgenerate
assign DOUT[data_width_int-1 : 0] = {out_par0, out_reg0};
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input wire I,
input wire C,
output wire O
);
reg [7:0] shift_register;
always @(posedge C) shift_register <= {shift_register[6:0], I};
assign O = shift_register[7];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* abc9_box, lib_whitebox *)
module adder(
output sumout,
output cout,
input a,
input b,
input cin
);
assign sumout = a ^ b ^ cin;
assign cout = (a & b) | ((a | b) & cin);
endmodule
(* abc9_lut=1, lib_whitebox *)
module frac_lut6(
input [0:5] in,
output [0:3] lut4_out,
output [0:1] lut5_out,
output lut6_out
);
parameter [0:63] LUT = 0;
// Effective LUT input
wire [0:5] li = in;
// Output function
wire [0:31] s1 = li[0] ?
{LUT[0] , LUT[2] , LUT[4] , LUT[6] , LUT[8] , LUT[10], LUT[12], LUT[14],
LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30],
LUT[32], LUT[34], LUT[36], LUT[38], LUT[40], LUT[42], LUT[44], LUT[46],
LUT[48], LUT[50], LUT[52], LUT[54], LUT[56], LUT[58], LUT[60], LUT[62]}:
{LUT[1] , LUT[3] , LUT[5] , LUT[7] , LUT[9] , LUT[11], LUT[13], LUT[15],
LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31],
LUT[33], LUT[35], LUT[37], LUT[39], LUT[41], LUT[43], LUT[45], LUT[47],
LUT[49], LUT[51], LUT[53], LUT[55], LUT[57], LUT[59], LUT[61], LUT[63]};
wire [0:15] s2 = li[1] ?
{s1[0] , s1[2] , s1[4] , s1[6] , s1[8] , s1[10], s1[12], s1[14],
s1[16], s1[18], s1[20], s1[22], s1[24], s1[26], s1[28], s1[30]}:
{s1[1] , s1[3] , s1[5] , s1[7] , s1[9] , s1[11], s1[13], s1[15],
s1[17], s1[19], s1[21], s1[23], s1[25], s1[27], s1[29], s1[31]};
wire [0:7] s3 = li[2] ?
{s2[0], s2[2], s2[4], s2[6], s2[8], s2[10], s2[12], s2[14]}:
{s2[1], s2[3], s2[5], s2[7], s2[9], s2[11], s2[13], s2[15]};
wire [0:3] s4 = li[3] ? {s3[0], s3[2], s3[4], s3[6]}:
{s3[1], s3[3], s3[5], s3[7]};
wire [0:1] s5 = li[4] ? {s4[0], s4[2]} : {s4[1], s4[3]};
assign lut4_out[0] = s4[0];
assign lut4_out[1] = s4[1];
assign lut4_out[2] = s4[2];
assign lut4_out[3] = s4[3];
assign lut5_out[0] = s5[0];
assign lut5_out[1] = s5[1];
assign lut6_out = li[5] ? s5[0] : s5[1];
endmodule
(* abc9_flop, lib_whitebox *)
module dff(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1\'b0;
parameter [0:0] IS_C_INVERTED = 1\'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1\'b0:
always @(posedge C)
Q <= D;
1\'b1:
always @(negedge C)
Q <= D;
endcase
endmodule
(* abc9_flop, lib_whitebox *)
module dffr(
output reg Q,
input D,
input R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1\'b0;
parameter [0:0] IS_C_INVERTED = 1\'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1\'b0:
always @(posedge C or posedge R)
if (R)
Q <= 1\'b0;
else
Q <= D;
1\'b1:
always @(negedge C or posedge R)
if (R)
Q <= 1\'b0;
else
Q <= D;
endcase
endmodule
(* abc9_flop, lib_whitebox *)
module dffre(
output reg Q,
input D,
input R,
input E,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1\'b0;
parameter [0:0] IS_C_INVERTED = 1\'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1\'b0:
always @(posedge C or posedge R)
if (R)
Q <= 1\'b0;
else if(E)
Q <= D;
1\'b1:
always @(negedge C or posedge R)
if (R)
Q <= 1\'b0;
else if(E)
Q <= D;
endcase
endmodule
module dffs(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input S
);
parameter [0:0] INIT = 1\'b0;
parameter [0:0] IS_C_INVERTED = 1\'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1\'b0:
always @(posedge C or negedge S)
if (S)
Q <= 1\'b1;
else
Q <= D;
1\'b1:
always @(negedge C or negedge S)
if (S)
Q <= 1\'b1;
else
Q <= D;
endcase
endmodule
module dffse(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input S,
input E
);
parameter [0:0] INIT = 1\'b0;
parameter [0:0] IS_C_INVERTED = 1\'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1\'b0:
always @(posedge C or negedge S)
if (S)
Q <= 1\'b1;
else if(E)
Q <= D;
1\'b1:
always @(negedge C or negedge S)
if (S)
Q <= 1\'b1;
else if(E)
Q <= D;
endcase
endmodule
module dffsr(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input R,
input S
);
parameter [0:0] INIT = 1\'b0;
parameter [0:0] IS_C_INVERTED = 1\'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1\'b0:
always @(posedge C or negedge S or negedge R)
if (S)
Q <= 1\'b1;
else if (R)
Q <= 1\'b0;
else
Q <= D;
1\'b1:
always @(negedge C or negedge S or negedge R)
if (S)
Q <= 1\'b1;
else if (R)
Q <= 1\'b0;
else
Q <= D;
endcase
endmodule
module dffsre(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input E,
input R,
input S
);
parameter [0:0] INIT = 1\'b0;
parameter [0:0] IS_C_INVERTED = 1\'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1\'b0:
always @(posedge C or posedge S or posedge R)
if (S)
Q <= 1\'b1;
else if (R)
Q <= 1\'b0;
else if (E)
Q <= D;
endcase
endmodule
(* abc9_flop, lib_whitebox *)
module latchsre (
output reg Q,
input S,
input R,
input D,
input G,
input E
);
parameter [0:0] INIT = 1\'b0;
parameter [0:0] IS_C_INVERTED = 1\'b0;
initial Q = INIT;
always @*
begin
if (R) Q <= 1\'b0;
if (S) Q <= 1\'b1;
else if (E && G) Q <= D;
end
endmodule
(* abc9_flop, lib_whitebox *)
module scff(
output reg Q,
input D,
input clk
);
parameter [0:0] INIT = 1\'b0;
initial Q = INIT;
always @(posedge clk)
Q <= D;
endmodule
module DP_RAM16K (
input rclk,
input wclk,
input wen,
input ren,
input[8:0] waddr,
input[8:0] raddr,
input[31:0] d_in,
input[31:0] wenb,
output[31:0] d_out );
_dual_port_sram memory_0 (
.wclk (wclk),
.wen (wen),
.waddr (waddr),
.data_in (d_in),
.rclk (rclk),
.ren (ren),
.raddr (raddr),
.wenb\t\t(wenb),
.d_out (d_out) );
endmodule
module _dual_port_sram (
input wclk,
input wen,
input[8:0] waddr,
input[31:0] data_in,
input rclk,
input ren,
input[8:0] raddr,
input[31:0] wenb,
output[31:0] d_out );
// MODE 0: 512 x 32
// MODE 1: 1024 x 16
// MODE 2: 1024 x 8
// MODE 3: 2048 x 4
integer i;
reg[31:0] ram[512:0];
reg[31:0] internal;
// The memory is self initialised
initial begin
for (i=0;i<=512;i=i+1)
begin
ram[i] = 0;
end
internal = 31\'b0;
end
wire [31:0] WMASK;
assign d_out = internal;
assign WMASK = wenb;
always @(posedge wclk) begin
if(!wen) begin
if (WMASK[ 0]) ram[waddr][ 0] <= data_in[ 0];
if (WMASK[ 1]) ram[waddr][ 1] <= data_in[ 1];
if (WMASK[ 2]) ram[waddr][ 2] <= data_in[ 2];
if (WMASK[ 3]) ram[waddr][ 3] <= data_in[ 3];
if (WMASK[ 4]) ram[waddr][ 4] <= data_in[ 4];
if (WMASK[ 5]) ram[waddr][ 5] <= data_in[ 5];
if (WMASK[ 6]) ram[waddr][ 6] <= data_in[ 6];
if (WMASK[ 7]) ram[waddr][ 7] <= data_in[ 7];
if (WMASK[ 8]) ram[waddr][ 8] <= data_in[ 8];
if (WMASK[ 9]) ram[waddr][ 9] <= data_in[ 9];
if (WMASK[10]) ram[waddr][10] <= data_in[10];
if (WMASK[11]) ram[waddr][11] <= data_in[11];
if (WMASK[12]) ram[waddr][12] <= data_in[12];
if (WMASK[13]) ram[waddr][13] <= data_in[13];
if (WMASK[14]) ram[waddr][14] <= data_in[14];
if (WMASK[15]) ram[waddr][15] <= data_in[15];
if (WMASK[16]) ram[waddr][16] <= data_in[16];
if (WMASK[17]) ram[waddr][17] <= data_in[17];
if (WMASK[18]) ram[waddr][18] <= data_in[18];
if (WMASK[19]) ram[waddr][19] <= data_in[19];
if (WMASK[20]) ram[waddr][20] <= data_in[20];
if (WMASK[21]) ram[waddr][21] <= data_in[21];
if (WMASK[22]) ram[waddr][22] <= data_in[22];
if (WMASK[23]) ram[waddr][23] <= data_in[23];
if (WMASK[24]) ram[waddr][24] <= data_in[24];
if (WMASK[25]) ram[waddr][25] <= data_in[25];
if (WMASK[26]) ram[waddr][26] <= data_in[26];
if (WMASK[27]) ram[waddr][27] <= data_in[27];
if (WMASK[28]) ram[waddr][28] <= data_in[28];
if (WMASK[29]) ram[waddr][29] <= data_in[29];
if (WMASK[30]) ram[waddr][30] <= data_in[30];
if (WMASK[31]) ram[waddr][31] <= data_in[31];
end
end
always @(posedge rclk) begin
if(!ren) begin
internal <= ram[raddr];
end
end
endmodule
module QL_DSP (
input CLK,
input [15:0] A, B, C, D,
output [31:0] O,
output CO // Currently unused, left in case we want to support signed operations in the future.
);
parameter [0:0] A_REG = 0;
parameter [0:0] B_REG = 0;
parameter [0:0] C_REG = 0;
parameter [0:0] D_REG = 0;
parameter [0:0] ENABLE_DSP = 0;
parameter [0:0] A_SIGNED = 0;
parameter [0:0] B_SIGNED = 0;
wire [15:0] iA, iB, iC, iD;
wire [15:0] iF, iJ, iK, iG;
// Regs C and A, currently unused
reg [15:0] rC, rA;
assign iC = C_REG ? rC : C;
assign iA = A_REG ? rA : A;
// Regs B and D, currently unused
reg [15:0] rB, rD;
assign iB = B_REG ? rB : B;
assign iD = D_REG ? rD : D;
// Multiplier Stage
wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
wire [15:0] Ah, Al, Bh, Bl;
assign Ah = {A_SIGNED ? {8{iA[15]}} : 8\'b0, iA[15: 8]};
assign Al = {8\'b0, iA[ 7: 0]};
assign Bh = {B_SIGNED ? {8{iB[15]}} : 8\'b0, iB[15: 8]};
assign Bl = {8\'b0, iB[ 7: 0]};
assign p_Ah_Bh = Ah * Bh; // F
assign p_Al_Bh = {8\'b0, Al[7:0]} * Bh; // J
assign p_Ah_Bl = Ah * {8\'b0, Bl[7:0]}; // K
assign p_Al_Bl = Al * Bl; // G
assign iF = p_Ah_Bh;
assign iJ = p_Al_Bh;
assign iK = p_Ah_Bl;
assign iG = p_Al_Bl;
// Adder Stage
wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8\'b0, iK};
wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8\'b0, iJ};
assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
// Output Stage
assign O = iL;
endmodule
|
module top (
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[1:0] = {cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module BANK();
\tparameter FASM_EXTRA = "INTERNAL_VREF";
\tparameter NUMBER = 0;
\tparameter INTERNAL_VREF = 600;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input wire clk0,
input wire clk1,
(* clkbuf_inhibit *)
input wire clk2,
(* clkbuf_inhibit *)
input wire clk3,
input wire [3:0] d,
output reg [3:0] q
);
always @(posedge clk0) q[0] <= d[0];
always @(posedge clk1) q[1] <= d[1];
always @(posedge clk2) q[2] <= d[2];
always @(posedge clk3) q[3] <= d[3];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input cpu_reset,
input data_in,
output [5:0] data_out
);
wire [5:0] data_out;
wire builder_pll_fb;
wire fdce_0_out, fdce_1_out;
wire main_locked;
wire clk_ibuf;
IBUF ibuf_clk(.I(clk), .O(clk_ibuf));
wire clk_bufg;
BUFG bufg_clk(.I(clk_ibuf), .O(clk_bufg));
FDCE FDCE_0 (
.D (data_in),
.C (clk_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (fdce_0_out)
);
FDCE FDCE_1 (
.D (fdce_0_out),
.C (clk_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[0])
);
PLLE2_ADV #(
.CLKFBOUT_MULT(4\'d12),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(4\'d12),
.CLKOUT0_PHASE(90.0),
.CLKOUT1_DIVIDE(2\'d3),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(3\'d6),
.CLKOUT2_PHASE(90.0),
.DIVCLK_DIVIDE(1\'d1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
.CLKOUT1(main_clkout1),
.CLKOUT2(main_clkout2),
.LOCKED(main_locked)
);
wire main_clkout0_bufg;
wire main_clkout1_bufg;
wire main_clkout2_bufg;
BUFG bufg_clkout0 (.I(main_clkout0), .O(main_clkout0_bufg));
BUFG bufg_clkout1 (.I(main_clkout1), .O(main_clkout1_bufg));
BUFG bufg_clkout2 (.I(main_clkout2), .O(main_clkout2_bufg));
FDCE FDCE_PLLx1_PH90 (
.D (data_in),
.C (main_clkout0_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[1])
);
FDCE FDCE_PLLx4_PH0_0 (
.D (data_in),
.C (main_clkout1_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[2])
);
FDCE FDCE_PLLx4_PH0_1 (
.D (data_in),
.C (main_clkout1_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[3])
);
FDCE FDCE_PLLx4_PH0_2 (
.D (data_in),
.C (main_clkout1_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[4])
);
FDCE FDCE_PLLx2_PH90_0 (
.D (data_in),
.C (main_clkout2_bufg),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out[5])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \\$_MUX8_ (
A,
B,
C,
D,
E,
F,
G,
H,
S,
T,
U,
Y
);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
mux8x0 _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.C (C),
.D (D),
.E (E),
.F (F),
.G (G),
.H (H),
.S0(S),
.S1(T),
.S2(U),
.Q (Y)
);
endmodule
module \\$_MUX4_ (
A,
B,
C,
D,
S,
T,
U,
Y
);
input A, B, C, D, S, T, U;
output Y;
mux4x0 _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.C (C),
.D (D),
.S0(S),
.S1(T),
.Q (Y)
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module BRAM #(parameter AWIDTH = 9,
parameter DWIDTH = 32)
(clk,
rce,
ra,
rq,
wce,
wa,
wd);
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
reg [DWIDTH-1:0] memory[0:AWIDTH-1];
always @(posedge clk) begin
if (rce)
rq <= memory[ra];
if (wce)
memory[wa] <= wd;
end
integer i;
initial
begin
for(i = 0; i < AWIDTH-1; i = i + 1)
memory[i] = 0;
end
endmodule
module BRAM_32x512(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 9;
parameter DWIDTH = 32;
input \t\t\tclk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_32x512 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
module BRAM_16x1024(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 10;
parameter DWIDTH = 16;
input \t\t\tclk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_16x1024 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
module BRAM_8x2048(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 11;
parameter DWIDTH = 8;
input \t\t\tclk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_8x2048 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
module BRAM_4x4096(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 12;
parameter DWIDTH = 4;
input \t\t\tclk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_4x4096 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1\'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input cpu_reset,
input data_in,
output data_out
);
wire data_out;
wire builder_pll_fb;
wire main_locked;
PLLE2_ADV #(
.CLKFBOUT_MULT(4\'d12),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(4\'d12),
.CLKOUT0_PHASE(0.0),
.DIVCLK_DIVIDE(1\'d1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
.CLKOUT1(main_clkout1),
.CLKOUT2(main_clkout2),
.CLKOUT3(main_clkout3),
.CLKOUT4(main_clkout4),
.LOCKED(main_locked)
);
FDCE FDCE_PLLx1_PH0 (
.D (data_in),
.C (main_clkout0),
.CE (1\'b1),
.CLR(1\'b0),
.Q (data_out)
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
(* keep *)
module qlal3_left_assp_macro (
input A2F_ACK,
output [ 7:0] A2F_ADDR,
output [ 7:0] A2F_Control,
input [ 7:0] A2F_GP_IN,
output [ 7:0] A2F_GP_OUT,
input [ 7:0] A2F_RD_DATA,
output A2F_REQ,
output A2F_RWn,
input [ 6:0] A2F_Status,
output [ 7:0] A2F_WR_DATA,
input [31:0] Amult0,
input [31:0] Bmult0,
output [63:0] Cmult0,
input [ 8:0] RAM0_ADDR,
input RAM0_CLK,
input RAM0_CLKS,
output [35:0] RAM0_RD_DATA,
input RAM0_RD_EN,
input RAM0_RME_af,
input [ 3:0] RAM0_RM_af,
input RAM0_TEST1_af,
input [ 3:0] RAM0_WR_BE,
input [35:0] RAM0_WR_DATA,
input RAM0_WR_EN,
input [11:0] RAM8K_P0_ADDR,
input RAM8K_P0_CLK,
input RAM8K_P0_CLKS,
input [ 1:0] RAM8K_P0_WR_BE,
input [16:0] RAM8K_P0_WR_DATA,
input RAM8K_P0_WR_EN,
input [11:0] RAM8K_P1_ADDR,
input RAM8K_P1_CLK,
input RAM8K_P1_CLKS,
output [16:0] RAM8K_P1_RD_DATA,
input RAM8K_P1_RD_EN,
input RAM8K_P1_mux,
input RAM8K_RME_af,
input [ 3:0] RAM8K_RM_af,
input RAM8K_TEST1_af,
output RAM8K_fifo_almost_empty,
output RAM8K_fifo_almost_full,
output [ 3:0] RAM8K_fifo_empty_flag,
input RAM8K_fifo_en,
output [ 3:0] RAM8K_fifo_full_flag,
input RESET_n,
input RESET_nS,
input SEL_18_bottom,
input SEL_18_left,
input SEL_18_right,
input SEL_18_top,
input SPI_CLK,
input SPI_CLKS,
output SPI_MISO,
output SPI_MISOe,
input SPI_MOSI,
input SPI_SSn,
output SYSCLK,
output SYSCLK_x2,
input Valid_mult0,
input [ 3:0] af_burnin_mode,
input [31:0] af_dev_id,
input af_fpga_int_en,
input af_opt_0,
input af_opt_1,
input \\af_plat_id[0] ,
input \\af_plat_id[1] ,
input \\af_plat_id[2] ,
input \\af_plat_id[3] ,
input \\af_plat_id[4] ,
input \\af_plat_id[5] ,
input \\af_plat_id[6] ,
input \\af_plat_id[7] ,
input af_spi_cpha,
input af_spi_cpol,
input af_spi_lsbf,
input default_SPI_IO_mux,
input drive_io_en_0,
input drive_io_en_1,
input drive_io_en_2,
input drive_io_en_3,
input drive_io_en_4,
input drive_io_en_5,
output fast_clk_out,
input [ 7:0] int_i,
output int_o,
input osc_en,
input osc_fsel,
input [ 2:0] osc_sel,
input [ 1:0] reg_addr_int,
input reg_clk_int,
input reg_clk_intS,
output [ 7:0] reg_rd_data_int,
input reg_rd_en_int,
input [ 7:0] reg_wr_data_int,
input reg_wr_en_int
);
endmodule
(* blackbox *)
(* keep *)
module qlal3_right_assp_macro (
input [31:0] Amult1,
input [31:0] Bmult1,
output [63:0] Cmult1,
output DrivingI2cBusOut,
input [ 8:0] RAM1_ADDR,
input RAM1_CLK,
input RAM1_CLKS,
output [35:0] RAM1_RD_DATA,
input RAM1_RD_EN,
input RAM1_RME_af,
input [ 3:0] RAM1_RM_af,
input RAM1_TEST1_af,
input [ 3:0] RAM1_WR_BE,
input [35:0] RAM1_WR_DATA,
input RAM1_WR_EN,
input [ 8:0] RAM2_P0_ADDR,
input RAM2_P0_CLK,
input RAM2_P0_CLKS,
input [ 3:0] RAM2_P0_WR_BE,
input [31:0] RAM2_P0_WR_DATA,
input RAM2_P0_WR_EN,
input [ 8:0] RAM2_P1_ADDR,
input RAM2_P1_CLK,
input RAM2_P1_CLKS,
output [31:0] RAM2_P1_RD_DATA,
input RAM2_P1_RD_EN,
input RAM2_RME_af,
input [ 3:0] RAM2_RM_af,
input RAM2_TEST1_af,
input [ 8:0] RAM3_P0_ADDR,
input RAM3_P0_CLK,
input RAM3_P0_CLKS,
input [31:0] RAM3_P0_WR_DATA,
input [ 3:0] RAM3_P0_WR_EN,
input [ 8:0] RAM3_P1_ADDR,
input RAM3_P1_CLK,
input RAM3_P1_CLKS,
output [31:0] RAM3_P1_RD_DATA,
input RAM3_P1_RD_EN,
input RAM3_RME_af,
input [ 3:0] RAM3_RM_af,
input RAM3_TEST1_af,
input SCL_i,
output SCL_o,
output SCL_oen,
input SDA_i,
output SDA_o,
output SDA_oen,
input Valid_mult1,
input al_clr_i,
output al_o,
input al_stick_en_i,
input arst,
input arstS,
output i2c_busy_o,
input rxack_clr_i,
output rxack_o,
input rxack_stick_en_i,
output tip_o,
output wb_ack,
input [ 2:0] wb_adr,
input wb_clk,
input wb_clkS,
input wb_cyc,
input [ 7:0] wb_dat_i,
output [ 7:0] wb_dat_o,
output wb_inta,
input wb_rst,
input wb_rstS,
input wb_stb,
input wb_we
);
endmodule
// ============================================================================
// Cells common to ASSPL and ASSPR
(* blackbox *)
module qlal3_mult_32x32_cell (
input [31:0] Amult,
input [31:0] Bmult,
input Valid_mult,
output [63:0] Cmult
);
endmodule
(* blackbox *)
module qlal3_ram_512x36_cell (
input [ 8:0] RAM_ADDR,
input RAM_CLK,
input RAM_CLKS,
output [35:0] RAM_RD_DATA,
input RAM_RD_EN,
input RAM_RME_af,
input [ 3:0] RAM_RM_af,
input RAM_TEST1_af,
input [ 3:0] RAM_WR_BE,
input [35:0] RAM_WR_DATA,
input RAM_WR_EN
);
endmodule
(* blackbox *)
module qlal3_ram_512x32_cell (
input [ 8:0] RAM_P0_ADDR,
input RAM_P0_CLK,
input RAM_P0_CLKS,
input [ 3:0] RAM_P0_WR_BE,
input [31:0] RAM_P0_WR_DATA,
input RAM_P0_WR_EN,
input [ 8:0] RAM_P1_ADDR,
input RAM_P1_CLK,
input RAM_P1_CLKS,
output [31:0] RAM_P1_RD_DATA,
input RAM_P1_RD_EN,
input RAM_RME_af,
input [ 3:0] RAM_RM_af,
input RAM_TEST1_af,
);
endmodule
(* blackbox *)
module qlal3_ram_4096x17_cell (
input [11:0] RAM_P0_ADDR,
input RAM_P0_CLK,
input RAM_P0_CLKS,
input [ 1:0] RAM_P0_WR_BE,
input [16:0] RAM_P0_WR_DATA,
input RAM_P0_WR_EN,
input [11:0] RAM_P1_ADDR,
input RAM_P1_CLK,
input RAM_P1_CLKS,
output [16:0] RAM_P1_RD_DATA,
input RAM_P1_RD_EN,
input RAM_P1_mux,
input RAM_RME_af,
input [ 3:0] RAM_RM_af,
input RAM_TEST1_af,
output RAM_fifo_almost_empty,
output RAM_fifo_almost_full,
output [ 3:0] RAM_fifo_empty_flag,
input RAM_fifo_en,
output [ 3:0] RAM_fifo_full_flag
);
endmodule
// ============================================================================
// Cells specific to ASSPL
(* blackbox *)
module qlal3_spi_cell (
input A2F_ACK,
output [ 7:0] A2F_ADDR,
output [ 7:0] A2F_Control,
input [ 7:0] A2F_GP_IN,
output [ 7:0] A2F_GP_OUT,
input [ 7:0] A2F_RD_DATA,
output A2F_REQ,
output A2F_RWn,
input [ 6:0] A2F_Status,
output [ 7:0] A2F_WR_DATA,
input af_spi_cpha,
input af_spi_cpol,
input af_spi_lsbf,
input SPI_CLK,
input SPI_CLKS,
output SPI_MISO,
output SPI_MISOe,
input SPI_MOSI,
input SPI_SSn
);
endmodule
(* blackbox *)
module qlal3_interrupt_controller_cell (
input af_fpga_int_en,
input [ 7:0] int_i,
output int_o,
input [ 1:0] reg_addr_int,
input reg_clk_int,
input reg_clk_intS,
output [ 7:0] reg_rd_data_int,
input reg_rd_en_int,
input [ 7:0] reg_wr_data_int,
input reg_wr_en_int
);
endmodule
(* blackbox *)
module qlal3_oscillator_cell (
input osc_en,
input osc_fsel,
input [ 2:0] osc_sel,
output fast_clk_out
);
endmodule
(* blackbox *)
module qlal3_io_control_cell (
input default_SPI_IO_mux,
input drive_io_en_0,
input drive_io_en_1,
input drive_io_en_2,
input drive_io_en_3,
input drive_io_en_4,
input drive_io_en_5
);
endmodule
(* blackbox *)
module qlal3_system_cell (
input RESET_n,
input RESET_nS,
input SEL_18_bottom,
input SEL_18_left,
input SEL_18_right,
input SEL_18_top,
output SYSCLK,
output SYSCLK_x2,
input [ 3:0] af_burnin_mode,
input [31:0] af_dev_id,
input af_opt_0,
input af_opt_1,
input \\af_plat_id[0] ,
input \\af_plat_id[1] ,
input \\af_plat_id[2] ,
input \\af_plat_id[3] ,
input \\af_plat_id[4] ,
input \\af_plat_id[5] ,
input \\af_plat_id[6] ,
input \\af_plat_id[7]
);
endmodule
// ============================================================================
// Cells specific to ASSPR
(* blackbox *)
module qlal3_i2c_cell (
input arst,
input arstS,
output wb_ack,
input [ 2:0] wb_adr,
input wb_clk,
input wb_clkS,
input wb_cyc,
input [ 7:0] wb_dat_i,
output [ 7:0] wb_dat_o,
output wb_inta,
input wb_rst,
input wb_rstS,
input wb_stb,
input wb_we,
input al_clr_i,
output al_o,
input al_stick_en_i,
output i2c_busy_o,
input rxack_clr_i,
output rxack_o,
input rxack_stick_en_i,
output tip_o,
output DrivingI2cBusOut,
input SCL_i,
output SCL_o,
output SCL_oen,
input SDA_i,
output SDA_o,
output SDA_oen
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module my_gate (
input wire A,
output wire Y
);
assign Y = ~A;
endmodule
module top (
input wire [7:0] di,
output wire [7:0] do
);
my_gate c0 (.A(di[0]), .Y(do[0]));
\\$_BUF_ c1 (.A(di[1]), .Y(do[1]));
\\$_BUF_ c2 (.A(di[2]), .Y(do[2]));
\\$_BUF_ c3 (.A(di[3]), .Y(do[3]));
\\$_BUF_ c4 (.A(di[4]), .Y(do[4]));
\\$_NOT_ c5 (.A(di[5]), .Y(do[5]));
\\$_NOT_ c6 (.A(di[6]), .Y(do[6]));
\\$_NOT_ c7 (.A(di[7]), .Y(do[7]));
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module mac_unit (
a,
b,
out
);
parameter DATA_WIDTH = 16;
input [DATA_WIDTH - 1 : 0] a, b;
output [2*DATA_WIDTH - 1 : 0] out;
assign out = a * b + out;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module $__PP3_DFFEPC_SYNCONLY (
output Q,
input D,
input CLK,
input EN,
);
// For some reason ABC9 adds init attributes to wires even though they were removed before mapping.
// As a workaround, remove any init attributes that get reintroduced.
wire _TECHMAP_REMOVEINIT_Q_ = 1;
dffepc _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CLK(CLK), .EN(EN), .PRE(1\'b0), .CLR(1\'b0));
endmodule
|
`timescale 1ns/100ps
module TB_dimmer();
\treg clock_50;
\treg up_n;
\treg down_n;
\treg test;
\treg mode;
\treg clr_n;
\twire [9:0] leds;
\twire [3:0] stepcounter;
\twire [17:0] cyclecounter;
\tdimmer U1(clock_50, clr_n, up_n, down_n, test, mode, leds, stepcounter, cyclecounter);
\tinitial begin
\t\tclock_50 = 0;
\t\tclr_n = 1;
\t\tup_n = 1;
\t\tdown_n = 1;
\t\ttest = 0;
\t\tmode = 0;
\t\t#100 clr_n = 0;
\t\t#50 clr_n = 1;
\t\t#100 up_n = 0;
\t\t#20 up_n = 1;
\tend
\talways begin
\t\t#20 clock_50 = ~clock_50;
\tend
endmodule
|
//==================================================================================================
// Filename : dimmer.v
// Created On : 2015-09-08 23:27:20
// Last Modified : 2015-09-08 23:41:34
// Revision : 1
// Author : Danny Dutton
// Class : ECE4514
//
// Description : This Verilog module will cycle through 16 different duty cycles for a set of
//\t\t\t\t\tLEDs using PWM. KEY0 raises the duty cycle, KEY1 lowers the duty cycle. KEY3 is
//\t\t\t\t\tan asynchronus reset. SW0 controls the test mode which scales the speed of
//\t\t\t\t\tcycling through duty cycles by a factor of 10. SW9 controls the Kitt mode which
//\t\t\t\t\tis not present in this current code.
//\t\t\t\t\t
//\t\t\t\t\tRefresh period = 200 Hz = .005 s
// \t\t\t\t\tWave Period = .005 s * 50 MHz = 250000
// \t\t\t\t\tStep Count = 16
// \t\t\t\t\tStep Delay = 250000/16 = 15625
// \t\t\t\t\tlog2(Wave Period) = log2(250000) = 18 bits
//
// \t\t\t\t\tSo we will refresh the LEDs every 200 Hz (.005 sec). This refresh period will be controlled by a counter going from 0 to 2^(18)-1.
// \t\t\t\t\tThe counter will be compared to the StepDelay*StepCount.
// \t\t\t\t\tDutyCycle = StepDelay*StepCount/CycleCount
//
//==================================================================================================
module dimmer(clock_50, clr_n, up_n, down_n, test, mode, leds);
\tinput clock_50;\t\t\t// 50 MHz clock on board
\tinput clr_n;\t\t\t// System reset, active low, KEY[3]
\tinput up_n;\t\t\t\t// KEY0, raises duty cycle
\tinput down_n;\t\t\t// KEY1, lowers duty cycle
\tinput test;\t\t\t\t// SW0, scales time factors
\tinput mode;\t\t\t\t// SW9, controls Kitt mode
\toutput [9:0] leds;\t\t// 10 LEDs
\treg [3:0] scale;\t\t\t\t// Time scale value, either 1 or 10
\treg buttonpressed;\t\t\t\t// Current state of either KEY0 or 1 being pressed
\treg nextbuttonpressed;\t\t\t// Next state of either KEY0 or 1 being pressed
\treg [4:0] stepcounter;\t\t\t// Step of LED brightness, 0-15
\treg [4:0] nextstepcounter;\t\t// Next step of LED brightness, 0-15
\treg [17:0] cyclecounter;\t\t// LED refresh rate cycle counter, 0-249999
\treg [25:0] upbuttoncounter;\t\t// Timer tracking hold time of up button, 0-49999999
\treg [25:0] downbuttoncounter;\t// Timer tracking hold time of down button, 0-49999999
\t// Logic for next button state, set 1 when buttons pressed
\talways @(negedge up_n or negedge down_n) begin\t\t
\t\t// Reset button counters and turn flag on to denote a button is being pushed
\t\tif (up_n == 0) begin
\t\t\tnextbuttonpressed <= 1;
\t\tend
\t\telse if (down_n == 0) begin
\t\t\tnextbuttonpressed <= 1;
\t\tend
\t\t// No more buttons are being pushed so reset the flag state
\t\telse begin
\t\t\tnextbuttonpressed <= 0;
\t\tend
\tend
\t
\t// Logic for next step count state
\talways @(upbuttoncounter or downbuttoncounter) begin
\t\t// Up button is being pushed so turn up the brightness
\t\tif (!up_n && (upbuttoncounter == 0) && buttonpressed) begin
\t\t\tnextstepcounter <= (stepcounter < 4'd15) ? stepcounter + 4'b1 : stepcounter;
\t\tend
\t\t// Down button is being pushed so turn down the brightness
\t\telse if (!down_n && (downbuttoncounter == 0) && buttonpressed) begin
\t\t\tnextstepcounter <= (stepcounter > 0) ? stepcounter - 4'b1 : stepcounter;
\t\tend
\t\t// Nothing is being pushed anymore so keep state
\t\telse begin
\t\t\tnextstepcounter <= stepcounter;
\t\tend
\tend
\t// Logic for next counter state
\talways @(posedge clock_50 or negedge clr_n) begin
\t\t
\t\t// Reset count values
\t\tif (clr_n == 0) begin
\t\t\tcyclecounter <= 0;
\t\t\tstepcounter <= 0;
\t\t\tbuttonpressed <= 0;
\t\t\tupbuttoncounter <= 0;
\t\t\tdownbuttoncounter <= 0;\t
\t\tend
\t\telse begin
\t\t\t// Set state to the next state
\t\t\tscale = test ? 4'b1010 : 1'b1;
\t\t\tstepcounter <= nextstepcounter;
\t\t\tbuttonpressed <= nextbuttonpressed;
\t\t\t// Increment cycle count always
\t\t\tcyclecounter <= cyclecounter + 13'b1;
\t\t\t// Cycle counter next state
\t\t\tif (cyclecounter >= (250000/scale)) begin
\t\t\t\tcyclecounter <= 0;
\t\t\tend
\t\t\t\t\t\t
\t\t\t// Set up button counter next state
\t\t\tif (upbuttoncounter >= (50000000/scale) || (up_n == 1)) begin
\t\t\t\tupbuttoncounter <= 0;
\t\t\tend
\t\t\telse begin
\t\t\t\tupbuttoncounter <= upbuttoncounter + 18'b1;
\t\t\tend
\t\t\t
\t\t\t// Set down button counter next state
\t\t\tif (downbuttoncounter >= (50000000/scale) || (down_n == 1)) begin
\t\t\t\tdownbuttoncounter <= 0;
\t\t\tend
\t\t\telse begin
\t\t\t\tdownbuttoncounter <= downbuttoncounter + 18'b1;
\t\t\tend
\t\tend
\tend
// Turn on LEDs if cycle count is within the duty cycle
assign leds = (cyclecounter < stepcounter*(15625/scale)) ? 10'b1111111111 : 10'b0;
endmodule
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_parsedata_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_parsedata_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_specialdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_tts_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_parsedata_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_parsedata_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_tts_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_misc_plugin_init;
\t\t\tstardict_misc_plugin_on_mainwin_finish;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_parsedata_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_netdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
|
`default_nettype none
//`include "gci_std_display_parameter.h"
module gci_std_display_top #(
\t\tparameter P_VRAM_SIZE = 307200,
\t\tparameter P_VRAM_INDEX = 0,
\t\tparameter P_AREA_H = 640,
\t\tparameter P_AREA_V = 480,
\t\tparameter P_AREAA_HV_N = 19,
\t\tparameter P_MEM_ADDR_N = 23
\t)(
\t\t//System
\t\tinput wire iCLOCK,
\t\tinput wire inRESET,
\t\tinput wire iRESET_SYNC,
\t\t//Display Clock
\t\tinput wire iDISP_CLOCK,\t\t\t\t
\t\t//Write Reqest
\t\tinput wire iIF_WR_REQ,
\t\toutput wire oIF_WR_BUSY,
\t\tinput wire iIF_WR_RW,
\t\tinput wire [31:0] iIF_WR_ADDR,
\t\tinput wire [31:0] iIF_WR_DATA,
\t\t//Read
\t\toutput wire oIF_RD_VALID,
\t\tinput wire iIF_RD_BUSY,
\t\toutput wire oIF_RD_DATA,
\t\t//VRAM IF
\t\toutput wire oVRAM_ARBIT_REQ,
\t\tinput wire iVRAM_ARBIT_ACK,
\t\toutput wire oVRAM_ARBIT_FINISH,
\t\toutput wire oVRAM_ENA,
\t\tinput wire iVRAM_BUSY,
\t\toutput wire oVRAM_RW,
\t\toutput wire [P_MEM_ADDR_N-1:0] oVRAM_ADDR,
\t\toutput wire [31:0] oVRAM_DATA,
\t\tinput wire iVRAM_VALID,
\t\toutput wire oVRAM_BUSY,
\t\tinput wire [31:0] iVRAM_DATA,
\t\t//Display
\t\toutput wire oDISP_CLOCK,
\t\toutput wire onDISP_RESET,
\t\toutput wire oDISP_ENA,
\t\toutput wire oDISP_BLANK,
\t\toutput wire onDISP_HSYNC,
\t\toutput wire onDISP_VSYNC,
\t\toutput wire [9:0] oDISP_DATA_R,
\t\toutput wire [9:0] oDISP_DATA_G,
\t\toutput wire [9:0] oDISP_DATA_B
\t);
\t
\t
\t/****************************************************************
\tHub Interface Controller
\t****************************************************************/
\tgci_std_display_hub_interface HUB_IF_CTRL(
\t\t//System
\t\t.iCLOCK(),
\t\t.inRESET(),
\t\t.iRESET_SYNC(),\t\t\t
\t\t//HUB(Reqest/Write)
\t\t.iHUB_REQ(),
\t\t.oHUB_BUSY(),
\t\t.iHUB_RW(),
\t\t.iHUB_ADDR(),
\t\t.iHUB_DATA(),
\t\t//HUB(Read)
\t\t.oHUB_VALID(),
\t\t.iHUB_BUSY(),
\t\t.oHUB_DATA(),
\t\t//Register(Request/Write)
\t\t.oREG_ENA(),
\t\t.oREG_RW(),
\t\t.oREG_ADDR(),
\t\t.oREG_DATA(),
\t\t//Register(Read)
\t\t.iREG_VALID(),
\t\t.oREG_BUSY(),
\t\t.iREG_DATA(),
\t\t//Command(Request/Write)
\t\t.oCOMM_VALID(),
\t\t.oCOMM_SEQ(),
\t\t.iCOMM_BUSY(),
\t\t.oCOMM_RW(),
\t\t.oCOMM_ADDR(),
\t\t.oCOMM_DATA(),
\t\t//Command(Read)
\t\t.iCOMM_VALID(),
\t\t.oCOMM_BUSY(),
\t\t.iCOMM_ADDR(),
\t\t.iCOMM_DATA()
\t);
\t
\t/****************************************************************
\tDisplay Struct Register
\t****************************************************************/
\twire register_info_charactor;
\twire [1:0] register_info_color;
\tgci_std_display_register #(P_VRAM_SIZE) REGISTER(
\t\t.iCLOCK(iCLOCK),
\t\t.inRESET(inRESET),
\t\t.iRESET_SYNC(1\'b0),
\t\t//Write
\t\t.iWR_VALID(register_ctrl_condition && !register_busy_condition && iIF_WR_RW),
\t\t.iWR_ADDR(iIF_WR_ADDR[3:0]),
\t\t.iWR_DATA(iIF_WR_DATA),
\t\t//Read
\t\t.iRD_VALID(register_ctrl_condition && !register_busy_condition && !iIF_WR_RW),
\t\t.oRD_BUSY(),
\t\t.iRD_ADDR(iIF_WR_ADDR[3:0]),
\t\t.oRD_VALID(),
\t\t.iRD_BUSY(),
\t\t.oRD_DATA(),
\t\t//Info
\t\t.oINFO_CHARACTER(register_info_charactor),
\t\t.oINFO_COLOR(register_info_color)
\t);
\t
\t/****************************************************************
\tDisplay Command Decoder
\t****************************************************************/
\twire command2request_valid;
\twire request2command_busy;
\twire [P_MEM_ADDR_N:0] command2request_addr;
\twire [23:0] command2request_data;
\tgci_std_display_command #(
\t\tP_AREA_H,
\t\tP_AREA_V,
\t\tP_AREAA_HV_N,
\t\tP_MEM_ADDR_N
\t)COMMAND(
\t\t.iCLOCK(),
\t\t.inRESET(),
\t\t//Register
\t\t.iREG_MODE(register_info_charactor), //[0]Bitmap | [1]Charactor
\t\t//BUS
\t\t.iIF_VALID(display_ctrl_condition && !display_busy_condition || sequence_ctrl_condition && !sequence_busy_condition),
\t\t.iIF_SEQ(sequence_ctrl_condition),
\t\t.oIF_BUSY(),
\t\t.iIF_RW(),
\t\t.iIF_ADDR(),
\t\t.iIF_DATA(),
\t\t//Output
\t\t.oIF_VALID(command2request_valid),
\t\t.iIF_BUSY(request2command_busy),
\t\t.oIF_ADDR(command2request_addr),
\t\t.oIF_DATA(command2request_data)
\t);
\t
\t/****************************************************************
\tDisplay Write/Read Controller
\t****************************************************************/
\twire request2vramif_req;
\twire vramif2request_ack;
\twire request2vramif_finish;
\twire vramif2request_break;
\twire vramif2request_busy;
\twire request2vramif_ena;
\twire request2vramif_rw;
\twire [P_MEM_ADDR_N-1:0] request2vramif_addr;
\twire [7:0] request2vramif_r;
\twire [7:0] request2vramif_g;
\twire [7:0] request2vramif_b;
\twire vramif2request_valid;
\twire request2vramif_busy;
\twire [31:0] vramif2request_data;
\t
\tgci_std_display_request_controller #(
\t\tP_AREA_H,
\t\tP_AREA_V,
\t\tP_AREAA_HV_N,
\t\tP_MEM_ADDR_N
\t)(
\t\t.iCLOCK(iCLOCK),
\t\t.inRESET(inRESET),
\t\t//BUS
\t\t.iRQ_VALID(command2request_valid),
\t\t.oRQ_BUSY(request2command_busy),
\t\t.iRQ_ADDR(command2request_addr),
\t\t.iRQ_DATA(command2request_data),
\t\t//VRAM
\t\t.oRQ_VALID(),
\t\t.oRQ_BUSY(),
\t\t.oRQ_DATA(),
\t\t//VRAM IF
\t\t.oIF_REQ(request2vramif_req),
\t\t.iIF_ACK(vramif2request_ack),
\t\t.oIF_FINISH(request2vramif_finish),
\t\t.iIF_BREAK(vramif2request_break),
\t\t.iIF_BUSY(vramif2request_busy),
\t\t.oIF_ENA(request2vramif_ena),
\t\t.oIF_RW(request2vramif_rw),
\t\t.oIF_ADDR(request2vramif_addr),
\t\t.oIF_R(request2vramif_r),
\t\t.oIF_G(request2vramif_g),
\t\t.oIF_B(request2vramif_b),
\t\t.iIF_VALID(vramif2request_valid),
\t\t.oIF_BUSY(request2vramif_busy),
\t\t.iIF_DATA(vramif2request_data)
\t);
\t
\t/****************************************************************
\tVram Interface Controller
\t****************************************************************/
\tgci_std_display_vram_interface VRAM_IF_CTRL(
\t\t.iGCI_CLOCK(iGCI_CLOCK),
\t\t.inRESET(inRESET),
\t\t.iRESET_SYNC(1\'b0),
\t\t//IF0 (Priority IF0>IF1)
\t\t.iIF0_REQ(vramread2vramif_req),
\t\t.oIF0_ACK(vramif2vramread_ack),
\t\t.iIF0_FINISH(vramread2vramif_finish),
\t\t.iIF0_ENA(vramread2vramif_ena),
\t\t.oIF0_BUSY(vramif2vramread_busy),
\t\t.iIF0_RW(1\'b0),
\t\t.iIF0_ADDR(vramread2vramif_addr + P_VRAM_INDEX),
\t\t.iIF0_DATA(32\'h0),
\t\t.oIF0_VALID(vramif2vramread_valid),
\t\t.iIF0_BUSY(1\'b0),
\t\t.oIF0_DATA(vramif2vramread_data),
\t\t//IF1
\t\t.iIF1_REQ(request2vramif_req),
\t\t.oIF1_ACK(vramif2request_ack),
\t\t.iIF1_FINISH(request2vramif_finish),
\t\t.oIF1_BREAK(vramif2request_break),
\t\t.iIF1_ENA(request2vramif_ena),
\t\t.oIF1_BUSY(vramif2request_busy),
\t\t.iIF1_RW(request2vramif_rw),
\t\t.iIF1_ADDR(request2vramif_addr + P_VRAM_INDEX),
\t\t.iIF1_DATA(request2vramif_data),
\t\t.oIF1_VALID(vramif2request_valid),
\t\t.iIF1_BUSY(request2vramif_busy),
\t\t.oIF1_DATA(vramif2request_data),
\t\t//Vram Interface
\t\t.oVRAM_ARBIT_REQ(oVRAM_ARBIT_REQ),
\t\t.iVRAM_ARBIT_ACK(iVRAM_ARBIT_ACK),
\t\t.oVRAM_ARBIT_FINISH(oVRAM_ARBIT_FINISH),
\t\t.oVRAM_ENA(oVRAM_ENA),
\t\t.iVRAM_BUSY(iVRAM_BUSY),
\t\t.oVRAM_RW(oVRAM_RW),
\t\t.oVRAM_ADDR(oVRAM_ADDR),
\t\t.oVRAM_DATA(oVRAM_DATA),
\t\t.iVRAM_VALID(iVRAM_VALID),
\t\t.oVRAM_BUSY(oVRAM_BUSY),
\t\t.iVRAM_DATA(iVRAM_DATAs)
\t);
\t
\t/****************************************************************
\tDisplay Data Read Controller
\t****************************************************************/
\twire vramread2vramif_req;
\twire vramif2vramread_ack;
\twire vramread2vramif_finish;
\twire vramread2vramif_ena;
\twire vramif2vramread_busy;
\twire [P_MEM_ADDR_N-:0] vramread2vramif_addr;
\twire vramif2vramread_valid;
\twire [31:0] vramif2vramread_data;
\t
\tgci_std_display_data_read VRAM_READ_CTRL(
\t\t.iGCI_CLOCK(iGCI_CLOCK),
\t\t.iDISP_CLOCK(iDISP_CLOCK),
\t\t.inRESET(inRESET),
\t\t.iRESET_SYNC(iRESET_SYNC),
\t\t//Read Request
\t\t.iRD_ENA(disptiming_data_req),
\t\t.iRD_SYNC(disptiming_data_sync),
\t\t.oRD_VALID(),
\t\t.oRD_DATA_R(oDISP_DATA_R),
\t\t.oRD_DATA_G(oDISP_DATA_G),
\t\t.oRD_DATA_B(oDISP_DATA_B),
\t\t//Memory IF
\t\t.oIF_REQ(vramread2vramif_req),
\t\t.iIF_ACK(vramif2vramread_ack),
\t\t.oIF_FINISH(vramread2vramif_finish),
\t\t.oIF_ENA(vramread2vramif_ena),
\t\t.iIF_BUSY(vramif2vramread_busy),
\t\t.oIF_ADDR(vramread2vramif_addr),
\t\t.iIF_VALID(vramif2vramread_valid),
\t\t.iIF_DATA(vramif2vramread_data)
\t);
\t
\t
\t/****************************************************************
\tDisplay Timing Generator
\t****************************************************************/
\t//Display timing
\tgci_std_display_timing_generator DISPLAY_TIMING(
\t\t.iDISP_CLOCK(iDISP_CLOCK),
\t\t.inRESET(inRESET),
\t\t.iRESET_SYNC(1\'b0),
\t\t.oDATA_REQ(disptiming_data_req),
\t\t.oDATA_SYNC(disptiming_data_sync),
\t\t.onDISP_RESET(onDISP_RESET),
\t\t.oDISP_ENA(oDISP_ENA),
\t\t.oDISP_BLANK(oDISP_BLANK),
\t\t.onDISP_VSYNC(onDISP_VSYNC),
\t\t.onDISP_HSYNC(onDISP_HSYNC)
\t);
\t
\t//Assign
\tassign oDISP_CLOCK = iDISP_CLOCK;\t\t
\tassign oIF_WR_BUSY = bus_req_wait;
\t
endmodule
\t
`default_nettype wire
|
`default_nettype none
module gci_std_display_command #(
\t\tparameter P_AREA_H = 640,
\t\tparameter P_AREA_V = 480,
\t\tparameter P_AREAA_HV_N = 19,
\t\tparameter P_MEM_ADDR_N = 23
\t)(
\t\tinput wire iCLOCK,
\t\tinput wire inRESET,
\t\t//Register
\t\tinput wire iREG_MODE, //[0]Bitmap | [1]Charactor
\t\t//BUS
\t\tinput wire iIF_VALID,
\t\tinput wire iIF_SEQ,
\t\toutput wire oIF_BUSY,
\t\tinput wire iIF_RW,
\t\tinput wire [P_MEM_ADDR_N-1:0] iIF_ADDR,
\t\tinput wire [31:0] iIF_DATA,
\t\t//Output
\t\toutput wire oIF_VALID,
\t\tinput wire iIF_BUSY,
\t\toutput wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
\t\toutput wire [23:0] oIF_DATA
\t);
\t
\tlocalparam P_L_REQ_STT_BITMAP = 3'h0;
\tlocalparam P_L_REQ_STT_CLARACTER = 3'h1;
\tlocalparam P_L_REQ_STT_CLARACTER_WAIT = 3'h2;
\tlocalparam P_L_REQ_STT_SEAQUENCER = 3'h3;
\tlocalparam P_L_REQ_STT_SEAQUENCER_WAIT = 3'h4;
\t
\t//State
\treg [2:0] b_req_state;
\t//FIFO
\twire reqfifo_wr_full;
\twire reqfifo_rd_empty;
\twire reqfifo_rd_mode;
\twire reqfifo_rd_seq;
\twire reqfifo_rd_rw;
\twire [31:0] reqfifo_rd_data;
\twire [P_MEM_ADDR_N-1:0] reqfifo_rd_addr;
\t//Bitmap Latch
\treg b_req_valid;
\treg [P_MEM_ADDR_N-1:0] b_req_addr;
\treg [23:0] b_req_data;
\t//Charactor
\twire character_busy;
\twire character_finish;
\twire character_out_valid;
\twire [P_MEM_ADDR_N-1:0] character_out_addr;
\twire [23:0] character_out_data;
\t//Sequencer
\twire sequencer_busy;
\twire sequencer_finish;
\twire sequencer_out_valid;
\twire [P_MEM_ADDR_N-1:0] sequencer_out_addr;
\twire [23:0] sequencer_out_data;
\t
\t//Condition
\treg fifo_read_condition;\t\t\t\t\t\t
\talways @* begin
\t\tcase(b_req_state)
\t\t\tP_L_REQ_STT_BITMAP : fifo_read_condition = !reqfifo_rd_empty && !iIF_BUSY;
\t\t\tP_L_REQ_STT_CLARACTER : fifo_read_condition = !reqfifo_rd_empty && !character_busy;
\t\t\tP_L_REQ_STT_CLARACTER_WAIT : fifo_read_condition = 1'b0;
\t\t\tP_L_REQ_STT_SEAQUENCER : fifo_read_condition = !reqfifo_rd_empty && !sequencer_busy;
\t\t\tP_L_REQ_STT_SEAQUENCER_WAIT : fifo_read_condition = 1'b0;
\t\t\tdefault : fifo_read_condition = 1'b0;
\t\tendcase
\tend //conb\t\t\t\t
\t
\twire seaquencer_start_condition = fifo_read_condition && reqfifo_rd_seq;
\twire charactor_start_condition = fifo_read_condition && reqfifo_rd_mode && !reqfifo_rd_seq;
\t
\t
\tgci_std_display_sync_fifo #(35+P_MEM_ADDR_N, 16, 4) REQ_FIFO
\t\t.iCLOCK(iCLOCK),
\t\t.inRESET(inRESET),
\t\t.iREMOVE(1'b0),
\t\t//Counter
\t\t.oCOUNT(),
\t\t//WR
\t\t.iWR_EN(iIF_VALID && !reqfifo_wr_full),
\t\t.iWR_DATA({iREG_MODE, iIF_SEQ, iIF_RW, iIF_DATA, iIF_DATA}),
\t\t.oWR_FULL(reqfifo_wr_full),
\t\t.oWR_ALMOST_FULL(),
\t\t//RD
\t\t.iRD_EN(fifo_read_condition),
\t\t.oRD_DATA({reqfifo_rd_mode, reqfifo_rd_seq, reqfifo_rd_rw, reqfifo_rd_addr, reqfifo_rd_data}),
\t\t.oRD_EMPTY(reqfifo_rd_empty),
\t\t.oRD_ALMOST_EMPTY()
\t);
\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_req_state <= P_L_REQ_STT_BITMAP;
\t\tend
\t\telse begin
\t\t\tcase(b_req_state)
\t\t\t\tP_L_REQ_STT_BITMAP:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(seaquencer_start_condition)begin
\t\t\t\t\t\t\tb_req_state <= P_L_REQ_STT_SEAQUENCER;
\t\t\t\t\t\tend
\t\t\t\t\t\telse if(charactor_start_condition)begin
\t\t\t\t\t\t\tb_req_state <= P_L_REQ_STT_CLARACTER;
\t\t\t\t\t\tend
\t\t\t\t\t\telse begin
\t\t\t\t\t\t\tb_req_state <= P_L_REQ_STT_BITMAP;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_REQ_STT_CLARACTER:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(!character_busy)begin
\t\t\t\t\t\t\tb_req_state <= P_L_REQ_STT_CLARACTER_WAIT;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_REQ_STT_CLARACTER_WAIT:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(character_finish)begin
\t\t\t\t\t\t\tb_req_state <= P_L_REQ_STT_BITMAP;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_REQ_STT_SEAQUENCER:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(!sequencer_busy)begin
\t\t\t\t\t\t\tb_req_state <= P_L_REQ_STT_SEAQUENCER_WAIT;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_REQ_STT_SEAQUENCER_WAIT:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(sequencer_finish)begin
\t\t\t\t\t\t\tb_req_state <= P_L_REQ_STT_BITMAP;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_req_state <= P_L_REQ_STT_BITMAP;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_req_valid <= 1'b0;
\t\t\tb_req_addr <= {P_MEM_ADDR_N{1'b0}};
\t\t\tb_req_data <= 24'h0;
\t\tend
\t\telse begin
\t\t\tif(!iIF_BUSY)begin
\t\t\t\tb_req_valid <= !reqfifo_rd_empty;
\t\t\t\tb_req_addr <= reqfifo_rd_addr;
\t\t\t\tb_req_data <= reqfifo_rd_data[23:0];
\t\t\tend
\t\tend
\tend
\t
\tgci_std_display_character #(P_AREA_H, P_AREA_V, P_AREAA_HV_N, P_MEM_ADDR_N) CHARACTER_CONTROLLER(
\t\t.iCLOCK(iCLOCK),
\t\t.inRESET(inRESET),
\t\t.iRESET_SYNC(1'b0),
\t\t//Req
\t\t.iIF_VALID(b_req_state == P_L_REQ_STT_CLARACTER),
\t\t.oIF_BUSY(character_busy),
\t\t.iIF_ADDR(reqfifo_rd_addr),\t//Charactor Addr
\t\t.iIF_DATA(reqfifo_rd_data),
\t\t//Out
\t\t.oIF_FINISH(character_finish)
\t\t.oIF_VALID(character_out_valid),
\t\t.iIF_BUSY(iIF_BUSY),
\t\t.oIF_ADDR(character_out_addr),
\t\t.oIF_DATA(character_out_data)
\t);
\t
\tgci_std_display_sequencer #(P_AREA_H, P_AREA_V, P_AREAA_HV_N, P_MEM_ADDR_N) SEQUENCER_CONTROLLER(
\t\t.iCLOCK(iCLOCK),
\t\t.inRESET(inRESET),
\t\t.iRESET_SYNC(1'b0),
\t\t//Req
\t\t.iIF_VALID(b_req_state == P_L_REQ_STT_SEAQUENCER),
\t\t.oIF_BUSY(sequencer_busy),
\t\t.iIF_DATA(reqfifo_rd_data),
\t\t//Out
\t\t.oIF_FINISH(sequencer_finish)
\t\t.oIF_VALID(sequencer_out_valid),
\t\t.iIF_BUSY(iIF_BUSY),
\t\t.oIF_ADDR(sequencer_out_addr),
\t\t.oIF_DATA(sequencer_out_data)
\t);
\t
\treg if_out_valid;
\treg [P_MEM_ADDR_N-1:0] if_out_addr;
\treg [23:0] if_out_data;
\talways @* begin
\t\tcase(b_req_state)
\t\t\tP_L_REQ_STT_BITMAP:
\t\t\t\tbegin
\t\t\t\t\tif_out_valid = b_req_valid;
\t\t\t\t\tif_out_addr = b_req_addr;
\t\t\t\t\tif_out_data = b_req_data;
\t\t\t\tend
\t\t\tP_L_REQ_STT_CLARACTER_WAIT:
\t\t\t\tbegin
\t\t\t\t\tif_out_valid = character_out_valid;
\t\t\t\t\tif_out_addr = character_out_addr;
\t\t\t\t\tif_out_data = character_out_data;
\t\t\t\tend
\t\t\tP_L_REQ_STT_SEAQUENCER_WAIT:
\t\t\t\tbegin
\t\t\t\t\tif_out_valid = sequencer_out_valid;
\t\t\t\t\tif_out_addr = sequencer_out_addr;
\t\t\t\t\tif_out_data = sequencer_out_data;
\t\t\t\tend
\t\t\tdefault:
\t\t\t\tbegin
\t\t\t\t\tif_out_valid = b_req_valid;
\t\t\t\t\tif_out_addr = b_req_addr;
\t\t\t\t\tif_out_data = b_req_data;
\t\t\t\tend
\t\tendcase
\tend
\t
\tassign oIF_BUSY = reqfifo_wr_full;
\tassign oIF_VALID = !iIF_BUSY && if_out_valid;
\tassign oIF_ADDR = if_out_addr;
\tassign oIF_DATA = if_out_data;
\t
endmodule
`default_nettype wire
|
/**************************************************************************
Sync FIFO
\t
-parameter P_N
\tQueue data vector width
\tExample : DATA[3:0] is P_N=4
-parameter P_DEPTH
\tQueue entry depth
\tExample P_DEPTH 16 is P_DEPTH=16
-parameter P_DEPTH_N
\tQueue entry depth n size
\tExample PARAMETER_DEPTH16 is 4
\t
-Make\t: 2013/2/13
-Update\t:
Takahiro Ito
**************************************************************************/
`default_nettype none
module gci_std_display_sync_fifo #(
\t\tparameter P_N = 16,
\t\tparameter P_DEPTH = 4,
\t\tparameter P_DEPTH_N = 2
\t)(
\t\t//System
\t\tinput iCLOCK,
\t\tinput inRESET,
\t\tinput iREMOVE,
\t\t//Counter
\t\toutput [P_DEPTH_N:0] oCOUNT,
\t\t//WR
\t\tinput iWR_EN,
\t\tinput [P_N-1:0] iWR_DATA,
\t\toutput oWR_FULL,
\t\toutput oWR_ALMOST_FULL,
\t\t//RD
\t\tinput iRD_EN,
\t\toutput [P_N-1:0] oRD_DATA,
\t\toutput oRD_EMPTY,
\t\toutput oRD_ALMOST_EMPTY
\t);
\t
\t//Reg
\treg [P_DEPTH_N:0] b_write_pointer;
\treg [P_DEPTH_N:0] b_read_pointer;
\treg [P_N-1:0] b_memory [0:P_DEPTH-1];
\t
\t//Wire
\twire [P_DEPTH_N:0] count = b_write_pointer - b_read_pointer;
\twire full = count[P_DEPTH_N];
\twire empty = (count == {P_DEPTH_N+1{1'b0}})? 1'b1 : 1'b0;
\twire almost_full = full || (count[P_DEPTH_N-1:0] == {P_DEPTH_N{1'b1}});
\twire almost_empty = empty || (count[P_DEPTH_N:0] == {{P_DEPTH_N{1'b0}}, 1'b1});
\twire read_condition = iRD_EN && !empty;
\twire write_condition = iWR_EN && !full;
\t
\t/****************************************
\tMemory / Counter
\t****************************************/
\t//Memory
\talways@(posedge iCLOCK)begin
\t\tif(write_condition)begin
\t\t\tb_memory [b_write_pointer[P_DEPTH_N-1:0]] <= iWR_DATA;
\t\tend
\tend //Memory
\t
\t//Write
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_write_pointer <= {P_DEPTH_N+1{1'b0}};
\t\tend
\t\telse if(iREMOVE)begin
\t\t\tb_write_pointer <= {P_DEPTH_N+1{1'b0}};
\t\tend
\t\telse begin
\t\t\tif(write_condition)begin
\t\t\t\tb_write_pointer <= b_write_pointer + {{P_DEPTH_N-1{1'b0}}, 1'b1};\t\t\t\t
\t\t\tend
\t\tend
\tend //Write always
\t
\t//Read
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_read_pointer <= {P_DEPTH_N+1{1'b0}};
\t\tend
\t\telse if(iREMOVE)begin
\t\t\tb_read_pointer <= {P_DEPTH_N+1{1'b0}};
\t\tend
\t\telse begin
\t\t\tif(read_condition)begin
\t\t\t\tb_read_pointer <= b_read_pointer + {{P_DEPTH_N-1{1'b0}}, 1'b1};
\t\t\tend
\t\tend
\tend //Read always
\t
\t//Assign
\tassign oRD_DATA = b_memory[b_read_pointer[P_DEPTH_N-1:0]];
\tassign oRD_EMPTY = empty;
\tassign oRD_ALMOST_EMPTY = almost_empty;
\t
\tassign oWR_FULL = full;
\tassign oWR_ALMOST_FULL = almost_full;
\tassign oCOUNT = count[P_DEPTH_N:0];
\t
endmodule
`default_nettype wire
|
`default_nettype none
//Display Clock = NCLK is 25MHz
module gci_std_display_timing_generator #(
\t\t/**********************************************
\t\t640x480 60Hz VGA Monitor for default parameter
\t\t**********************************************/
\t\t//Counter Width
\t\tparameter P_H_WIDTH = 10,
\t\tparameter P_V_WIDTH = 10,
\t\t//Area
\t\tparameter P_AREA_H = 640,
\t\tparameter P_AREA_V = 480,
\t\t//Hsync
\t\tparameter P_THP = 95,\t//Hsync pulse width.(Unit:NCLK)
\t\tparameter P_THB = 48,\t//To Hsync - data width.(Unit:NCLK)
\t\tparameter P_THF = 15,\t//To data - next Hsync width.(Unit:NCLK)
\t\t//Vsync
\t\tparameter P_TVP = 2,\t//Vsync pulse width.(Unit:HSYNC)
\t\tparameter P_TVB = 33,\t//To Vsync - active data area width.(Unit:HSYNC)
\t\tparameter P_TVF = 10\t//To active data area - next Vsync width.(Unit:HSYNC)
\t)(
\t\tinput wire iDISP_CLOCK,\t//25MHz @640x480 60Hz
\t\tinput wire inRESET,
\t\tinput wire iRESET_SYNC,
\t\t//PIXCEL
\t\toutput wire oDATA_REQ,
\t\toutput wire oDATA_SYNC,\t
\t\t//DISP Out
\t\toutput wire onDISP_RESET,
\t\toutput wire oDISP_ENA,\t
\t\toutput wire oDISP_BLANK,
\t\toutput wire onDISP_VSYNC,
\t\toutput wire onDISP_HSYNC
\t);
\t
\treg [P_H_WIDTH-1:0] b_hsync_counter;
\treg [P_V_WIDTH-1:0] b_vsync_counter;
\treg bn_disp_reset;
\treg b_buff_sync;
\treg b_buff_ena;
\treg bn_buff_blank;
\treg bn_buff_hsync;
\treg bn_buff_vsync;
\t
\twire hsync_restart_condition = !(b_hsync_counter < (P_THP + P_THB + P_AREA_H + P_THF-1));
\twire vsync_restart_condition = !(b_vsync_counter < (P_TVP + P_TVB + P_AREA_V + P_TVF-1));
\twire data_active_condition = func_data_enable_area(b_hsync_counter, b_vsync_counter);
\twire hsync_active_condition = func_hsync_enable_area(b_hsync_counter);
\twire vsync_active_condition = func_vsync_enable_area(b_vsync_counter);
\t
\tfunction func_data_enable_area;
\t\tinput [P_H_WIDTH-1:0] func_hsync;
\t\tinput [P_V_WIDTH-1:0] func_vsync;
\t\tbegin
\t\t\t//HSYNC Check
\t\t\tif(func_hsync >= (P_THP + P_THB) && func_hsync < (P_THP + P_THB + P_AREA_H))begin
\t\t\t\t//VSYNC Check
\t\t\t\tif(func_vsync >= (P_TVP + P_TVB) && func_vsync < (P_TVP + P_TVB + P_AREA_V))begin
\t\t\t\t\tfunc_data_enable_area = 1\'b1;
\t\t\t\tend
\t\t\t\telse begin
\t\t\t\t\tfunc_data_enable_area = 1\'b0;
\t\t\t\tend
\t\t\tend
\t\t\telse begin
\t\t\t\tfunc_data_enable_area = 1\'b0;
\t\t\tend
\t\tend
\tendfunction
\t
\tfunction func_hsync_enable_area;
\t\tinput [P_H_WIDTH-1:0] func_hsync;
\t\tbegin
\t\t\t//HSYNC Check
\t\t\tif(func_hsync < P_THP)begin
\t\t\t\tfunc_hsync_enable_area = 1\'b1;
\t\t\tend
\t\t\telse begin
\t\t\t\tfunc_hsync_enable_area = 1\'b0;
\t\t\tend
\t\tend
\tendfunction
\t
\tfunction func_vsync_enable_area;
\t\tinput [P_H_WIDTH-1:0] func_vsync;
\t\tbegin
\t\t\t//HSYNC Check
\t\t\tif(func_vsync < P_TVP)begin
\t\t\t\tfunc_vsync_enable_area = 1\'b1;
\t\t\tend
\t\t\telse begin
\t\t\t\tfunc_vsync_enable_area = 1\'b0;
\t\t\tend
\t\tend
\tendfunction
\t
\t\t
\t/*********************************
\tSync Counter
\t*********************************/
\t//H-SYNC Cunter\t
\talways@(posedge iDISP_CLOCK or negedge inRESET)begin\t
\t\tif(!inRESET)begin\t
\t\t\tb_hsync_counter <= {P_H_WIDTH{1\'b0}};
\t\tend
\t\telse if(iRESET_SYNC)begin\t
\t\t\tb_hsync_counter <= {P_H_WIDTH{1\'b0}};
\t\tend
\t\telse begin
\t\t\tif(hsync_restart_condition)begin
\t\t\t\tb_hsync_counter <= {P_H_WIDTH{1\'b0}};
\t\t\tend
\t\t\telse begin
\t\t\t\tb_hsync_counter <= b_hsync_counter + {{P_H_WIDTH-1{1\'b0}}, 1\'b1};
\t\t\tend
\t\tend
\tend
\t
\t//VSYNC Counter
\talways@(posedge iDISP_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_vsync_counter <= {P_V_WIDTH{1\'b0}};
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_vsync_counter <= {P_V_WIDTH{1\'b0}};
\t\tend
\t\telse begin
\t\t\tif(hsync_restart_condition)begin
\t\t\t\tif(vsync_restart_condition)begin
\t\t\t\t\tb_vsync_counter <= {P_V_WIDTH{1\'b0}};
\t\t\t\tend
\t\t\t\telse begin
\t\t\t\t\tb_vsync_counter <= b_vsync_counter + {{P_V_WIDTH-1{1\'b0}}, 1\'b1};
\t\t\t\tend
\t\t\tend
\t\tend
\tend
\t
\t
\t/*********************************
\tOutput Buffer
\t*********************************/
\t//Display Reset
\talways@(posedge iDISP_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tbn_disp_reset <= 1\'b0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tbn_disp_reset <= 1\'b0;
\t\tend
\t\telse begin
\t\t\tbn_disp_reset <= 1\'b1;
\t\tend
\tend
\t
\talways@(posedge iDISP_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_buff_sync <= 1\'b0;
\t\t\tb_buff_ena <= 1\'b0;
\t\t\tbn_buff_blank <= 1\'b0;
\t\t\tbn_buff_hsync <= 1\'b0;
\t\t\tbn_buff_vsync <= 1\'b0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_buff_sync <= 1\'b0;
\t\t\tb_buff_ena <= 1\'b0;
\t\t\tbn_buff_blank <= 1\'b0;
\t\t\tbn_buff_hsync <= 1\'b0;
\t\t\tbn_buff_vsync <= 1\'b0;
\t\tend
\t\telse begin
\t\t\tb_buff_sync <= vsync_restart_condition;
\t\t\tb_buff_ena <= data_active_condition;
\t\t\tbn_buff_blank <= data_active_condition;
\t\t\tbn_buff_hsync <= hsync_active_condition;
\t\t\tbn_buff_vsync <= vsync_active_condition;
\t\tend
\tend
\t
\tassign oDATA_REQ = data_active_condition;
\tassign oDATA_SYNC = b_buff_sync;
\tassign onDISP_RESET = bn_disp_reset;
\tassign oDISP_ENA = b_buff_ena;
\tassign oDISP_BLANK = !bn_buff_blank;
\tassign onDISP_HSYNC = !bn_buff_hsync;
\tassign onDISP_VSYNC = !bn_buff_vsync;
\t
\t
\t/*********************************
\tProperty Check
\t*********************************/
\t//`define GCI_STD_DISPLAY_SVA_ASSERTION
\t`ifdef GCI_STD_DISPLAY_SVA_ASSERTION
\t\t//THP Check
\t\tproperty THP_CHECK;
\t\t\t@(posedge iDISP_CLOCK)
\t\t\t\tdisable iff (!inRESET)
\t\t\t\t($past(onDISP_HSYNC, 1) and !onDISP_HSYNC) |-> (!onDISP_HSYNC[*P_THP] and ##(P_THP)onDISP_HSYNC);
\t\tendproperty
\t\t
\t\tassert property(THP_CHECK)else begin
\t\t\t$display("[Error][Assertion] : THP - Start%d, End%d", $past(onDISP_HSYNC, P_THP), onDISP_HSYNC);
\t\t\t$stop;
\t\tend\t
\t\t//THB + P_AREA_H + P_THF Check
\t\tproperty THB_HAREA_THF_CHECK;
\t\t\t@(posedge iDISP_CLOCK)
\t\t\t\tdisable iff (!inRESET)
\t\t\t\t(!$past(oDISP_ENA, 1) and oDISP_ENA) |-> (onDISP_HSYNC[*(P_THB+P_AREA_H+P_THF)]);// and ##(P_THB+P_AREA_H+P_THF)!onDISP_HSYNC);
\t\tendproperty
\t\tassert property(THB_HAREA_THF_CHECK)else begin
\t\t\t$display("[Error][Assertion] : Display Area-H - Start%d, End%d", $past(onDISP_HSYNC, (P_THB+P_AREA_H+P_THF)), onDISP_HSYNC);
\t\t\t$stop;
\t\tend\t
\t\t//P_AREA_H Check
\t\tproperty HAREA_CHECK;
\t\t\t@(posedge iDISP_CLOCK)
\t\t\t\tdisable iff (!inRESET)
\t\t\t\t(!$past(oDISP_ENA, 1) and oDISP_ENA) |-> (oDISP_ENA[*P_AREA_H] and ##(P_AREA_H)!oDISP_ENA);
\t\tendproperty
\t\t
\t\tassert property(HAREA_CHECK)else begin
\t\t\t$display("[Error][Assertion] : Display Area-H - Start%d, End%d", $past(oDISP_ENA, P_THP), oDISP_ENA);
\t\t\t$stop;
\t\tend\t
\t\t
\t\t//TVP Check
\t\tproperty TVP_CHECK;
\t\t\t@(posedge iDISP_CLOCK)
\t\t\t\tdisable iff (!inRESET)
\t\t\t\t($past(onDISP_VSYNC, 1) and !onDISP_VSYNC) |-> (!onDISP_VSYNC[*(P_TVP*(P_THP+P_THB+P_AREA_H+P_THF))] and ##((P_TVP*(P_THP+P_THB+P_AREA_H+P_THF)))onDISP_VSYNC);
\t\tendproperty
\t\t
\t\tassert property(TVP_CHECK)else begin
\t\t\t$display("[Error][Assertion] : TVP - Start%d, End%d", $past(onDISP_VSYNC, (P_TVP*(P_THP+P_THB+P_AREA_H+P_THF))), onDISP_VSYNC);
\t\t\t$stop;
\t\tend\t
\t\t\t
\t\t
\t`endif
\t
endmodule
`default_nettype wire
|
`default_nettype none
module gci_std_display_request_controller #(
\t\tparameter P_AREA_H = 640,
\t\tparameter P_AREA_V = 480,
\t\tparameter P_AREAA_HV_N = 19,
\t\tparameter P_MEM_ADDR_N = 23
\t)(
\t\tinput wire iCLOCK,
\t\tinput wire inRESET,
\t\t//BUS
\t\tinput wire iRQ_VALID,
\t\toutput wire oRQ_BUSY,
\t\tinput wire [P_MEM_ADDR_N-1:0] iRQ_ADDR,
\t\tinput wire [23:0] iRQ_DATA,
\t\t//VRAM
\t\toutput wire oRQ_VALID,
\t\tinput wire iRQ_BUSY,
\t\toutput wire [23:0] oRQ_DATA,
\t\t//New
\t\toutput wire oIF_REQ,
\t\tinput wire iIF_ACK,
\t\toutput wire oIF_FINISH,
\t\tinput wire iIF_BREAK,
\t\tinput wire iIF_BUSY,
\t\toutput wire oIF_ENA,
\t\toutput wire oIF_RW,
\t\toutput wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
\t\toutput wire [7:0] oIF_R,
\t\toutput wire [7:0] oIF_G,
\t\toutput wire [7:0] oIF_B,
\t\tinput wire iIF_VALID,
\t\toutput wire oIF_BUSY,
\t\tinput wire [31:0] iIF_DATA
\t);
\t
\t
\tassign oBUSMOD_WAIT = reqfifo_wr_full;
\t
\twire request_break_condition = iIF_BREAK || ;
\twire reqfifo_read_condition =
\t
\t
\t
\tgci_std_sync_fifo #(24, 16, 4) VRAM_REQ_FIFO(
\t\t.inRESET(inRESET),
\t\t.iREMOVE(1'b0),
\t\t.iCLOCK(iCLOCK),
\t\t.iWR_EN(iRQ_VALID && !read_fifo_wr_full),
\t\t.iWR_DATA(iIF_DATA[23:0]),
\t\t.oWR_FULL(read_fifo_wr_full),
\t\t.oWR_ALMOST_FULL(),
\t\t.iRD_EN(!read_fifo_rd_empty && !iRQ_BUSY),
\t\t.oRD_DATA(read_fifo_rd_data),
\t\t.oRD_EMPTY(read_fifo_rd_empty)
\t);
\t
\t
\t
\t
\tlocalparam P_L_MAIN_STT_IDLE = 3'h0;
\tlocalparam P_L_MAIN_STT_IF_REQ = 3'h1;
\tlocalparam P_L_MAIN_STT_IF_WORK = 3'h2;
\tlocalparam P_L_MAIN_STT_IF_READ_WAIT = 3'h3;
\tlocalparam P_L_MAIN_STT_IF_END = 3'h4;
\t
\treg [2:0] b_main_state;
\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\tend
\t\telse begin
\t\t\tcase(b_main_state)
\t\t\t\tP_L_MAIN_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iRQ_VALID)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IF_REQ;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_IF_REQ:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iIF_ACK)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IF_WORK;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_IF_WORK:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(request_break_condition)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IF_END;
\t\t\t\t\t\tend
\t\t\t\t\t\telse if()begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IF_READ_WAIT;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_IF_READ_WAIT:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iIF_VALID && !read_fifo_wr_full)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IF_END;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_IF_END:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend //main(vram-interface) state always
\t
\t
\twire read_fifo_wr_full;
\twire read_fifo_rd_empty;
\twire [23:0] read_fifo_rd_data;
\t
\tgci_std_sync_fifo #(24, 4, 2) VRAM_RESULT_FIFO(
\t\t.inRESET(inRESET),
\t\t.iREMOVE(1'b0),
\t\t.iCLOCK(iCLOCK),
\t\t.iWR_EN(iIF_VALID && !read_fifo_wr_full),
\t\t.iWR_DATA(iIF_DATA[23:0]),
\t\t.oWR_FULL(read_fifo_wr_full),
\t\t.oWR_ALMOST_FULL(),
\t\t.iRD_EN(!read_fifo_rd_empty && !iRQ_BUSY),
\t\t.oRD_DATA(read_fifo_rd_data),
\t\t.oRD_EMPTY(read_fifo_rd_empty)
\t);
\t
\t
\tassign oRQ_VALID = !read_fifo_rd_empty && !iRQ_BUSY;
\tassign oRQ_DATA = read_fifo_rd_data;
\t
\tassign oIF_BUSY = read_fifo_wr_full;
\t
\t/***************************************************
\tAssertion
\t***************************************************/
\t/*
\t`ifdef GCI_STD_DISP_SVA_ASSERTION
\t\tproterty PRO_FIFO_NEVER_NOT_FULL;
\t\t\t@(posedge iCLOCK) disable iff (!inRESET) (!read_fifo_wr_full);
\t\tendproperty
\t\tassert property(PRO_FIFO_NEVER_NOT_FULL);
\t`endif
\t*/
\t
\xe3\x80\x80
endmodule
`default_nettype wire
\t\t\t\t
|
`default_nettype none
module gci_std_display_register #(
\t\tparameter P_VRAM_SIZE = 307200\t//VGA
\t(
\t\tinput wire iCLOCK,
\t\tinput wire inRESET,
\t\tinput wire iRESET_SYNC,
\t\t//Write
\t\tinput wire iWR_VALID,
\t\tinput wire [3:0] iWR_ADDR,
\t\tinput wire [31:0] iWR_DATA,
\t\t//Read
\t\tinput wire iRD_VALID,
\t\toutput wire oRD_BUSY,
\t\tinput wire [3:0] iRD_ADDR,
\t\toutput wire oRD_VALID,
\t\tinput wire iRD_BUSY,
\t\toutput wire [31:0] oRD_DATA,
\t\t//Info
\t\toutput oINFO_CHARACTER,
\t\toutput [1:0] oINFO_COLOR
\t);
\t
\tlocalparam P_L_REG_ADDR_RESOLUT = 4'h0;
\tlocalparam P_L_REG_ADDR_MODE = 4'h2;
\tlocalparam P_L_REG_ADDR_SIZE = 4'h3;
\t
\twire ds_resolut_write_condition = iWR_VALID && iWR_ADDR == P_L_REG_ADDR_RESOLUT;
\twire ds_mode_write_condition = iWR_VALID && iWR_ADDR == P_L_REG_ADDR_MODE;
\t
\t
\t//RESOLUTION
\treg [11:0] b_ds_resolut_h;
\treg [11:0] b_ds_resolut_v;
\treg [6:0] b_ds_resolut_refresh;
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_ds_resolut_h <= 12'h0;
\t\t\tb_ds_resolut_v <= 12'h0;
\t\t\tb_ds_resolut_refresh <= 7'h0;
\t\tend
\t\telse if(!iRESET_SYNC)begin
\t\t\tb_ds_resolut_h <= 12'h0;
\t\t\tb_ds_resolut_v <= 12'h0;
\t\t\tb_ds_resolut_refresh <= 7'h0;
\t\tend
\t\telse begin
\t\t\tif(ds_resolut_write_condition)begin
\t\t\t\tb_ds_resolut_h <= iWR_DATA[11:1];
\t\t\t\tb_ds_resolut_v <= iWR_DATA[23:12];
\t\t\t\tb_ds_resolut_refresh <= iWR_DATA[30:24];
\t\t\tend
\t\tend
\tend
\twire [31:0] ds_resolut_data = {1'b0, b_ds_resolut_refresh, b_ds_resolut_v, b_ds_resolut_h};
\t
\t//MODE
\treg [1:0] b_ds_mode_color;
\treg b_ds_mode_character;
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_ds_mode_color <= 2'h0;
\t\t\tb_ds_mode_character <= 1'b0;
\t\tend
\t\telse if(!iRESET_SYNC)begin
\t\t\tb_ds_mode_color <= 2'h0;
\t\t\tb_ds_mode_character <= 1'b0;
\t\tend
\t\telse begin
\t\t\tif(ds_mode_write_condition)begin
\t\t\t\tb_ds_mode_color <= iWR_DATA[2:1];
\t\t\t\tb_ds_mode_character <= iWR_DATA[0];
\t\t\tend
\t\tend
\tend
\twire [31:0] ds_mode_data = {29'h0, b_ds_mode_color, b_ds_mode_character};
\t
\t//SIZE
\twire [31:0] ds_size_data = P_VRAM_SIZE;
\t
\t/************************************************
\tRead
\t************************************************/
\treg b_read_valid;
\treg [31:0] b_read_buffer;
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_read_valid <= 1'b0;
\t\t\tb_read_buffer <= 32'h0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_read_valid <= 1'b0;
\t\t\tb_read_buffer <= 32'h0;
\t\tend
\t\telse begin
\t\t\tif(!iRD_BUSY)begin
\t\t\t\tb_read_valid <= iRD_VALID;
\t\t\t\tcase(iRD_ADDR)
\t\t\t\t\tP_L_REG_ADDR_RESOLUT : b_read_buffer <= ds_resolut_data;
\t\t\t\t\tP_L_REG_ADDR_MODE : b_read_buffer <= ds_mode_data;
\t\t\t\t\tP_L_REG_ADDR_SIZE : b_read_buffer <= ds_size_data;
\t\t\t\t\tdefault : b_read_buffer <= 32'h0;
\t\t\t\tendcase
\t\t\tend
\t\tend
\tend
\t
\tassign oRD_BUSY = iRD_BUSY;
\tassign oRD_VALID = !iRD_BUSY && b_read_valid;
\tassign oRD_DATA = b_read_buffer;
\tassign oINFO_CHARACTER = b_ds_mode_character;
\tassign oINFO_COLOR = b_ds_mode_color;
\t
endmodule
`default_nettype wire
\t
|
`default_nettype none
module gci_std_display_vram_controller_sram #(
\t\tparameter P_MEM_ADDR_N = 20,
\t\tparameter P_AREA_H = 640,
\t\tparameter P_AREA_V = 480
\t)(
\t\t//System
\t\tinput wire iGCI_CLOCK,
\t\tinput wire iDISP_CLOCK,
\t\tinput wire inRESET,
\t\t//IF\t
\t\tinput wire iIF_WRITE_REQ,
\t\tinput wire [P_MEM_ADDR_N-1:0] iIF_WRITE_ADDR,
\t\tinput wire [15:0] iIF_WRITE_DATA,
\t\toutput wire oIF_WRITE_FULL,
\t\tinput wire iDISP_REQ,
\t\tinput wire iDISP_SYNC,
\t\toutput wire [9:0] oDISP_DATA_R,
\t\toutput wire [9:0] oDISP_DATA_G,
\t\toutput wire [9:0] oDISP_DATA_B,
\t\t//SRAM
\t\toutput wire onSRAM_CE,
\t\toutput wire onSRAM_WE,
\t\toutput wire onSRAM_OE,
\t\toutput wire onSRAM_UB,
\t\toutput wire onSRAM_LB,
\t\toutput wire [P_MEM_ADDR_N-1:0] oSRAM_ADDR,
\t\tinout wire [15:0] ioSRAM_DATA
\t);
\t
\t
\t//Write FIFO Wire
\twire writefifo_empty;
\twire [P_MEM_ADDR_N-1:0] writefifo_addr;
\twire [15:0] writefifo_data;
\t//Read FIFO Wire
\twire vramfifo0_full;
\twire [15:0] vramfifo0_data;
\twire vramfifo0_empty;
\twire vramfifo1_full;
\t\t
\t/********************************************
\t//Memory Assignment
\t********************************************/
\t//Assignment Buffer
\treg b_buff_osram_rw;\t\t//R=0 | W=1
\treg b_buff_onsram_we;
\treg b_buff_onsram_oe;
\treg b_buff_onsram_ub;
\treg b_buff_onsram_lb;
\treg [P_MEM_ADDR_N-1:0] b_buff_osram_addr;
\treg [15:0] b_buff_osram_data;
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_buff_osram_rw <= 1'b0;
\t\t\tb_buff_onsram_we <= 1'b0;
\t\t\tb_buff_onsram_oe <= 1'b0;
\t\t\tb_buff_onsram_ub <= 1'b0;
\t\t\tb_buff_onsram_lb <= 1'b0;
\t\t\tb_buff_osram_addr <= {P_MEM_ADDR_N{1'b0}};
\t\t\tb_buff_osram_data <= 16'h0;
\t\tend
\t\telse begin
\t\t\tb_buff_onsram_oe <= 1'b0;
\t\t\tcase(b_main_state)
\t\t\t\tL_PARAM_MAIN_STT_READ:
\t\t\t\t\tbegin
\t\t\t\t\t\tcase(b_rd_req_state)
\t\t\t\t\t\t\tL_PARAM_READ_REQ_STT_ADDR_SET:
\t\t\t\t\t\t\t\tbegin
\t\t\t\t\t\t\t\t\tb_buff_osram_rw <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_onsram_we <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_onsram_ub <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_onsram_lb <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_osram_addr <= b_rd_req_addr;
\t\t\t\t\t\t\t\t\tb_buff_osram_data <= b_buff_osram_data;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tdefault:
\t\t\t\t\t\t\t\tbegin
\t\t\t\t\t\t\t\t\tb_buff_osram_rw <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_onsram_we <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_onsram_ub <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_onsram_lb <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_osram_addr <= {P_MEM_ADDR_N{1'h0}};
\t\t\t\t\t\t\t\t\tb_buff_osram_data <= 16'h0;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\tendcase
\t\t\t\t\tend
\t\t\t\tL_PARAM_MAIN_STT_WRITE:
\t\t\t\t\tbegin
\t\t\t\t\t\tcase(b_wr_state)
\t\t\t\t\t\t\tL_PARAM_WRITE_STT_ADDR_SET:
\t\t\t\t\t\t\t\tbegin\t//CE=H, WE=H, Addr=Active
\t\t\t\t\t\t\t\t\tb_buff_osram_rw <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_onsram_we <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_onsram_ub <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_onsram_lb <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_osram_addr <= writefifo_addr;
\t\t\t\t\t\t\t\t\tb_buff_osram_data <= writefifo_data;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tL_PARAM_WRITE_STT_LATCH_CONDITION:
\t\t\t\t\t\t\t\tbegin\t//CE=L, WE=L
\t\t\t\t\t\t\t\t\tb_buff_osram_rw <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_onsram_we <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_onsram_ub <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_onsram_lb <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_osram_addr <= b_buff_osram_addr;
\t\t\t\t\t\t\t\t\tb_buff_osram_data <= b_buff_osram_data;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tL_PARAM_WRITE_STT_DATA_SET:
\t\t\t\t\t\t\t\tbegin\t//CE=L, WE=L, Data=Active
\t\t\t\t\t\t\t\t\tb_buff_osram_rw <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_onsram_we <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_onsram_ub <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_onsram_lb <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_osram_addr <= b_buff_osram_addr;
\t\t\t\t\t\t\t\t\tb_buff_osram_data <= b_buff_osram_data;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tdefault:\t//Idle or other
\t\t\t\t\t\t\t\tbegin
\t\t\t\t\t\t\t\t\tb_buff_osram_rw <= 1'b0;
\t\t\t\t\t\t\t\t\tb_buff_onsram_we <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_onsram_ub <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_onsram_lb <= 1'b1;
\t\t\t\t\t\t\t\t\tb_buff_osram_addr <= {P_MEM_ADDR_N{1'h0}};
\t\t\t\t\t\t\t\t\tb_buff_osram_data <= 16'h0;
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\tendcase
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_buff_osram_rw <= 1'b0;
\t\t\t\t\t\tb_buff_onsram_we <= 1'b1;
\t\t\t\t\t\tb_buff_onsram_ub <= 1'b1;
\t\t\t\t\t\tb_buff_onsram_lb <= 1'b1;
\t\t\t\t\t\tb_buff_osram_addr <= {P_MEM_ADDR_N{1'h0}};
\t\t\t\t\t\tb_buff_osram_data <= 16'h0;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\t
\tassign onSRAM_CE = 1'b0;//b_buff_onsram_ce;
\tassign onSRAM_WE = b_buff_onsram_we;
\tassign onSRAM_OE = b_buff_onsram_oe;
\tassign onSRAM_UB = b_buff_onsram_ub;
\tassign onSRAM_LB = b_buff_onsram_lb;
\tassign oSRAM_ADDR = b_buff_osram_addr;
\tassign ioSRAM_DATA = (b_buff_osram_rw)? b_buff_osram_data : 16'hzzzz;
\t
\t
\t/********************************************
\t//Main State
\t********************************************/
\tlocalparam L_PARAM_MAIN_STT_IDLE = 2'h0;
\tlocalparam L_PARAM_MAIN_STT_READ = 2'h1;
\tlocalparam L_PARAM_MAIN_STT_WRITE = 2'h2;
\t
\treg [1:0] b_main_state;
\treg b_main_wait;\t
\treg b_main_req;
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_main_state <= L_PARAM_MAIN_STT_IDLE;
\t\t\tb_main_wait <= 1'b0;
\t\t\tb_main_req <= 1'b0;
\t\tend
\t\telse if(b_main_wait)begin
\t\t\tb_main_req <= 1'b0;
\t\t\tif(b_wr_end || b_rd_req_end)begin
\t\t\t\tb_main_state <= L_PARAM_MAIN_STT_IDLE;
\t\t\t\tb_main_wait <= 1'b0;
\t\t\tend
\t\tend
\t\telse begin
\t\t\tcase(b_main_state)
\t\t\t\tL_PARAM_MAIN_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(vramfifo0_empty)begin
\t\t\t\t\t\t\tb_main_state <= L_PARAM_MAIN_STT_READ;
\t\t\t\t\t\t\tb_main_req <= 1'b1;
\t\t\t\t\t\tend
\t\t\t\t\t\telse if(!writefifo_empty)begin
\t\t\t\t\t\t\tb_main_state <= L_PARAM_MAIN_STT_WRITE;
\t\t\t\t\t\t\tb_main_req <= 1'b1;
\t\t\t\t\t\tend
\t\t\t\t\t\telse begin
\t\t\t\t\t\t\tb_main_state <= L_PARAM_MAIN_STT_IDLE;
\t\t\t\t\t\t\tb_main_wait <= 1'b0;
\t\t\t\t\t\t\tb_main_req <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tL_PARAM_MAIN_STT_READ:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_main_state <= L_PARAM_MAIN_STT_READ;
\t\t\t\t\t\tb_main_wait <= 1;
\t\t\t\t\t\tb_main_req <= 1'b0;
\t\t\t\t\tend
\t\t\t\tL_PARAM_MAIN_STT_WRITE:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_main_state <= L_PARAM_MAIN_STT_WRITE;
\t\t\t\t\t\tb_main_wait <= 1;
\t\t\t\t\t\tb_main_req <= 1'b0;
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_main_state <= L_PARAM_MAIN_STT_IDLE;
\t\t\t\t\t\tb_main_wait <= 1'b0;
\t\t\t\t\t\tb_main_req <= 1'b0;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t\t
\t
\t
\t/********************************************
\t//Write State
\t********************************************/
\tlocalparam L_PARAM_WRITE_STT_IDLE = 3'h0;\t
\tlocalparam L_PARAM_WRITE_STT_ADDR_SET = 3'h1;\t\t\t//CE=H, WE=H, Addr=Active
\tlocalparam L_PARAM_WRITE_STT_LATCH_CONDITION = 3'h2;\t//CE=L, WE=L
\tlocalparam L_PARAM_WRITE_STT_DATA_SET = 3'h3;\t\t\t//CE=L, WE=L, Data=Active
\tlocalparam L_PARAM_WRITE_STT_END = 3'h4;
\t
\tgci_std_sync_fifo #(16+P_MEM_ADDR_N, 64, 6)\tVRAMWRITE_FIFO(
\t\t.inRESET(inRESET),
\t\t.iCLOCK(iGCI_CLOCK),
\t\t.iREMOVE(1'b0),
\t\t.oCOUNT(),
\t\t.iWR_EN(iIF_WRITE_REQ),
\t\t.iWR_DATA({iIF_WRITE_ADDR, iIF_WRITE_DATA}),
\t\t.oWR_FULL(oIF_WRITE_FULL),
\t\t.iRD_EN(b_wr_state == L_PARAM_WRITE_STT_DATA_SET && !writefifo_empty),
\t\t.oRD_DATA({writefifo_addr, writefifo_data}),
\t\t.oRD_EMPTY(writefifo_empty)
\t);
\t
\t
\treg [2:0] b_wr_state;
\treg b_wr_end;
\t
\t
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_wr_state <= L_PARAM_WRITE_STT_IDLE;
\t\t\tb_wr_end <= 1'b0;
\t\tend
\t\telse begin
\t\t\tcase(b_wr_state)
\t\t\t\tL_PARAM_WRITE_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(b_main_req && (b_main_state == L_PARAM_MAIN_STT_WRITE))begin
\t\t\t\t\t\t\tb_wr_state <= L_PARAM_WRITE_STT_ADDR_SET;
\t\t\t\t\t\tend
\t\t\t\t\t\tb_wr_end <= 1'b0;
\t\t\t\t\tend
\t\t\t\tL_PARAM_WRITE_STT_ADDR_SET:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_wr_state <= L_PARAM_WRITE_STT_LATCH_CONDITION;
\t\t\t\t\tend
\t\t\t\tL_PARAM_WRITE_STT_LATCH_CONDITION:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_wr_state <= L_PARAM_WRITE_STT_DATA_SET;
\t\t\t\t\tend
\t\t\t\tL_PARAM_WRITE_STT_DATA_SET:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(writefifo_empty || vramfifo0_empty)begin
\t\t\t\t\t\t\tb_wr_state <= L_PARAM_WRITE_STT_END;
\t\t\t\t\t\tend
\t\t\t\t\t\telse begin
\t\t\t\t\t\t\tb_wr_state <= L_PARAM_WRITE_STT_ADDR_SET;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tL_PARAM_WRITE_STT_END:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_wr_state <= L_PARAM_WRITE_STT_IDLE;
\t\t\t\t\t\tb_wr_end <= 1'b1;
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_wr_state <= L_PARAM_WRITE_STT_IDLE;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\t
\t/********************************************
\t//Read State (RD FIFO)
\t********************************************/
\t//Request State
\tlocalparam L_PARAM_READ_REQ_STT_IDLE = 2'h0;
\tlocalparam L_PARAM_READ_REQ_STT_ADDR_SET = 2'h1;
\tlocalparam L_PARAM_READ_REQ_STT_RD_END = 2'h2;
\t
\t
\treg [1:0] b_rd_req_state;
\treg [P_MEM_ADDR_N-1:0] b_rd_req_addr;
\treg b_rd_req_end;
\t
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_rd_req_state <= L_PARAM_READ_REQ_STT_IDLE;
\t\t\tb_rd_req_addr <= 20'h0;
\t\t\tb_rd_req_end <= 1'b0;
\t\tend
\t\telse begin
\t\t\tcase(b_rd_req_state)
\t\t\t\tL_PARAM_READ_REQ_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(b_main_req && (b_main_state == L_PARAM_MAIN_STT_READ))begin
\t\t\t\t\t\t\tb_rd_req_state <= L_PARAM_READ_REQ_STT_ADDR_SET;
\t\t\t\t\t\tend
\t\t\t\t\t\tb_rd_req_end <= 1'b0;
\t\t\t\t\tend
\t\t\t\tL_PARAM_READ_REQ_STT_ADDR_SET:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(vramfifo0_full)begin
\t\t\t\t\t\t\t//b_rd_req_addr <= func_read_next_addr_640x480(b_rd_req_addr);
\t\t\t\t\t\t\tb_rd_req_state <= L_PARAM_READ_REQ_STT_RD_END;
\t\t\t\t\t\tend
\t\t\t\t\t\telse begin
\t\t\t\t\t\t\tb_rd_req_addr <= func_read_next_addr(b_rd_req_addr);
\t\t\t\t\t\t\tb_rd_req_state <= L_PARAM_READ_REQ_STT_ADDR_SET;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tL_PARAM_READ_REQ_STT_RD_END:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_rd_req_state <= L_PARAM_READ_REQ_STT_IDLE;
\t\t\t\t\t\tb_rd_req_end <= 1'b1;
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_rd_req_state <= L_PARAM_READ_REQ_STT_IDLE;
\t\t\t\t\t\tb_rd_req_end <= 1'b0;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\t
\tfunction [P_MEM_ADDR_N-1:0] func_read_next_addr;
\t\tinput [P_MEM_ADDR_N-1:0] func_now_addr;
\t\tbegin
\t\t\tif(func_now_addr < (P_AREA_H*P_AREA_V)-1)begin
\t\t\t\tfunc_read_next_addr = func_now_addr + 1;
\t\t\tend
\t\t\telse begin
\t\t\t\tfunc_read_next_addr = {P_MEM_ADDR_N{1'b0}};
\t\t\tend
\t\tend
\tendfunction
\t
\t//latch State
\tlocalparam L_PARAM_READ_LATCH_STT_IDLE = 2'h0;
\tlocalparam L_PARAM_READ_LATCH_STT_ADDR_SET = 2'h1;
\tlocalparam L_PARAM_READ_LATCH_STT_RD = 2'h2;
\tlocalparam L_PARAM_READ_LATCH_STT_RD_END = 2'h3;
\t
\treg b_rd_latch_condition;
\t
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_rd_latch_condition <= 1'b0;
\t\tend
\t\telse begin
\t\t\tb_rd_latch_condition <= (b_rd_req_state == L_PARAM_READ_REQ_STT_ADDR_SET) && !vramfifo0_full;
\t\tend
\tend
\twire [15:0] vramfifo1_data;
\t
\tgci_std_sync_fifo #(16, 16, 4) VRAMREAD_FIFO0(
\t\t.inRESET(inRESET),
\t\t.iREMOVE(1'b0),
\t\t.iCLOCK(iGCI_CLOCK),
\t\t.iWR_EN(b_rd_latch_condition),
\t\t.iWR_DATA(ioSRAM_DATA),
\t\t.oWR_FULL(),
\t\t.oWR_ALMOST_FULL(vramfifo0_full),
\t\t.iRD_EN(!vramfifo0_empty && !vramfifo1_full),
\t\t.oRD_DATA(vramfifo0_data),
\t\t.oRD_EMPTY(vramfifo0_empty)
\t);
\tgci_std_async_fifo #(16, 16, 4)\tVRAMREAD_FIFO1(
\t\t.inRESET(inRESET),
\t\t.iREMOVE(1'b0),
\t\t.iWR_CLOCK(iGCI_CLOCK),
\t\t.iWR_EN(!vramfifo0_empty && !vramfifo1_full),
\t\t.iWR_DATA(vramfifo0_data),
\t\t.oWR_FULL(vramfifo1_full),
\t\t.iRD_CLOCK(iDISP_CLOCK),
\t\t.iRD_EN(iDISP_REQ),
\t\t.oRD_DATA(vramfifo1_data),
\t\t.oRD_EMPTY()
\t);
\t
\tassign oDISP_DATA_R = {vramfifo1_data[15:11], {5{vramfifo1_data[11]}}};
\tassign oDISP_DATA_G = {vramfifo1_data[10:5], {4{vramfifo1_data[5]}}};
\tassign oDISP_DATA_B = {vramfifo1_data[4:0], {5{vramfifo1_data[0]}}};
\t
\t
endmodule
`default_nettype wire
|
//IS61WV102416BLL-10 Simulation Model
// `define OEb
`timescale 1ns/10ps
module is61wv102416bll (A, IO, CE_, OE_, WE_, LB_, UB_);
parameter SPEED_RANK = 10;
/*
generate
\tif(SPEED_RANK == 8)begin
\t\tlocalparam dqbits = 16;
\t\tlocalparam memdepth = 1048576;\t//1M bit
\t\tlocalparam addbits = 20;
\t\tlocalparam Taa = 8;
\t\tlocalparam Toha = 3;
\t\tlocalparam Thzce = 3;
\t\tlocalparam Tsa = 0;
\t\tlocalparam Thzwe = 4;
\tend
\telse if(SPEED_RANK == 10)begin
\t\tlocalparam dqbits = 16;
\t\tlocalparam memdepth = 1048576;\t//1M bit
\t\tlocalparam addbits = 20;
\t\tlocalparam Taa = 10;
\t\tlocalparam Toha = 3;
\t\tlocalparam Thzce = 4;
\t\tlocalparam Tsa = 0;
\t\tlocalparam Thzwe = 5;
\tend
\telse begin\t//20ns
\t\tlocalparam dqbits = 16;
\t\tlocalparam memdepth = 1048576;\t//1M bit
\t\tlocalparam addbits = 20;
\t\tlocalparam Taa = 20;
\t\tlocalparam Toha = 3;
\t\tlocalparam Thzce = 8;
\t\tlocalparam Tsa = 0;
\t\tlocalparam Thzwe = 9;
\tend
endgenerate
*/
\t\tlocalparam dqbits = 16;
\t\tlocalparam memdepth = 1048576;\t//1M bit
\t\tlocalparam addbits = 20;
\t\tlocalparam Taa = 10;
\t\tlocalparam Toha = 3;
\t\tlocalparam Thzce = 4;
\t\tlocalparam Tsa = 0;
\t\tlocalparam Thzwe = 5;
/*
parameter dqbits = 16;
parameter memdepth = 1048576;\t//1M bit
parameter addbits = 20;
parameter Taa = 10;
parameter Toha = 3;
parameter Thzce = 4;
parameter Tsa = 0;
parameter Thzwe = 5;
*/
input CE_, OE_, WE_, LB_, UB_;
input [(addbits - 1) : 0] A;
inout [(dqbits - 1) : 0] IO;
wire [(dqbits - 1) : 0] dout;
reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];
reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
// wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
wire r_en = WE_ & (~CE_) & (~OE_);
wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_));
assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;
assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A];
assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A];
/*
int i;
initial
#0 begin
\tfor(i = 0; i < 640*480; i = i + 1)begin
\t\tif(i < (640*480)/2)begin
\t\t\t{bank1[i], bank0[i]} = {5'hFF, 6'h00, 5'h00};
\t\tend
\t\telse begin
\t\t\t{bank1[i], bank0[i]} = {5'h0, 6'h00, 5'hFF};
\t\tend
\tend
end
*/
always @(A or w_en)
begin
#Tsa
if (w_en)
#Thzwe
begin
bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];
bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];
\t\t
end
end
specify
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 8,
tPWE1 = 8,
tPBW = 8;
$setup (A, negedge CE_, tSA);
$setup (A, posedge CE_, tAW);
$setup (IO, posedge CE_, tSD);
$setup (A, negedge WE_, tSA);
$setup (IO, posedge WE_, tSD);
$setup (A, negedge LB_, tSA);
$setup (A, negedge UB_, tSA);
$width (negedge CE_, tSCE);
$width (negedge LB_, tPBW);
$width (negedge UB_, tPBW);
`ifdef OEb
$width (negedge WE_, tPWE1);
`else
$width (negedge WE_, tPWE2);
`endif
endspecify
endmodule
|
/**************************************************************************
Async Fifo
\t
-parameter P_N
\tQueue data vector width
\tExample : DATA[3:0] is P_N=4
-parameter P_DEPTH
\tQueue entry depth
\tExample P_DEPTH 16 is P_DEPTH=16
-parameter P_DEPTH_N
\tQueue entry depth n size
\tExample PARAMETER_DEPTH16 is 4
\t
-SDF Settings
\tAsynchronus Clock : iWR_CLOCK - iRD_CLOCK
\t
-Make\t: 2013/2/13
-Update\t:
Takahiro Ito
**************************************************************************/
`default_nettype none
module gci_std_display_async_fifo #(
\t\tparameter P_N = 16,
\t\tparameter P_DEPTH = 4,
\t\tparameter P_DEPTH_N = 2
\t)(
\t\t//System
\t\tinput inRESET,
\t\t//Remove
\t\tinput iREMOVE,
\t\t//WR
\t\tinput iWR_CLOCK,
\t\tinput iWR_EN,
\t\tinput [P_N-1:0] iWR_DATA,
\t\toutput oWR_FULL,
\t\t//RD
\t\tinput iRD_CLOCK,
\t\tinput iRD_EN,
\t\toutput [P_N-1:0] oRD_DATA,
\t\toutput oRD_EMPTY
\t);\t
\t//Full
\twire [P_DEPTH_N:0] full_count;
\twire full;
\twire [P_DEPTH_N:0] empty_count;
\twire empty;
\t//Memory
\treg [P_N-1:0] b_memory[0:P_DEPTH-1];
\t//Counter
\treg [P_DEPTH_N:0] b_wr_counter/* synthesis preserve = 1 */;\t\t//Altera QuartusII Option
\treg [P_DEPTH_N:0] b_rd_counter/* synthesis preserve = 1 */;\t\t//Altera QuartusII Option
\twire [P_DEPTH_N:0] gray_d_fifo_rd_counter;
\twire [P_DEPTH_N:0] binary_d_fifo_rd_counter;
\twire [P_DEPTH_N:0] gray_d_fifo_wr_counter;
\twire [P_DEPTH_N:0] binary_d_fifo_wr_counter;
\t
\t//Assign
\tassign full_count = b_wr_counter - binary_d_fifo_rd_counter;
\tassign full = full_count[P_DEPTH_N] || (full_count[P_DEPTH_N-1:0] == {P_DEPTH_N{1'b1}})? 1'b1 : 1'b0;
\t//Empty
\tassign empty_count = binary_d_fifo_wr_counter - (b_rd_counter);\t
\tassign empty = (empty_count == {P_DEPTH_N+1{1'b0}})? 1'b1 : 1'b0;
\t
\t/***************************************************
\tMemory
\t***************************************************/\t
\t//Write
\talways@(posedge iWR_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_wr_counter <= {P_DEPTH_N{1'b0}};
\t\tend
\t\telse if(iREMOVE)begin
\t\t\tb_wr_counter <= {P_DEPTH_N{1'b0}};
\t\tend
\t\telse begin
\t\t\tif(iWR_EN && !full)begin
\t\t\t\tb_memory[b_wr_counter[P_DEPTH_N-1:0]] <= iWR_DATA;
\t\t\t\tb_wr_counter <= b_wr_counter + {{P_DEPTH_N-1{1'b0}}, 1'b1};
\t\t\tend
\t\tend
\tend
\t
\t//Read Pointer
\talways@(posedge iRD_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_rd_counter <= {P_DEPTH_N{1'b0}};
\t\tend
\t\telse if(iREMOVE)begin
\t\t\tb_rd_counter <= {P_DEPTH_N{1'b0}};
\t\tend
\t\telse begin
\t\t\tif(iRD_EN && !empty)begin
\t\t\t\tb_rd_counter <= b_rd_counter + {{P_DEPTH_N-1{1'b0}}, 1'b1};
\t\t\tend
\t\tend
\tend
\t
\t
\t/***************************************************
\tCounter Buffer
\t***************************************************/\t
\tgci_std_display_async_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_READ(
\t\t.iCLOCK(iWR_CLOCK),
\t\t.inRESET(inRESET),
\t\t.iREQ_DATA(bin2gray(b_rd_counter)),
\t\t.oOUT_DATA(gray_d_fifo_rd_counter)
\t);
\tassign binary_d_fifo_rd_counter = gray2bin(gray_d_fifo_rd_counter);
\t
\t
\tgci_std_async_display_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_WRITE(
\t\t.iCLOCK(iRD_CLOCK),
\t\t.inRESET(inRESET),
\t\t.iREQ_DATA(bin2gray(b_wr_counter)),
\t\t.oOUT_DATA(gray_d_fifo_wr_counter)
\t);
\tassign binary_d_fifo_wr_counter = gray2bin(gray_d_fifo_wr_counter);
\t
\t/***************************************************
\tFunction
\t***************************************************/
\tfunction [P_DEPTH_N:0] bin2gray;
\t\tinput [P_DEPTH_N:0] binary;
\t\tbegin
\t\t\tbin2gray = binary ^ (binary >> 1'b1);
\t\tend
\tendfunction
\t
\tfunction[P_DEPTH_N:0] gray2bin(input[P_DEPTH_N:0] gray);
\t\tinteger i;
\t\tfor(i=P_DEPTH_N; i>=0; i=i-1)begin
\t\t\tif(i==P_DEPTH_N)begin
\t\t\t\tgray2bin[i] = gray[i];
\t\t\tend
\t\t\telse begin
\t\t\t\tgray2bin[i] = gray[i] ^ gray2bin[i+1];
\t\t\tend
\t\tend
\tendfunction
\t
\t
\t/***************************************************
\tOutput Assign
\t***************************************************/\t
\tassign oWR_FULL = full;
\tassign oRD_EMPTY = empty;
\tassign oRD_DATA = b_memory[b_rd_counter[P_DEPTH_N-1:0]];
\t
\t\t\t\t
endmodule
`default_nettype wire
|
/*******************************************************
\tMIST32 GCI Special Memory : Device Using
\t
\tMake\t:\t2011/09/27
\tUpdate\t:\t2011/0
*******************************************************/
`default_nettype none
module gci_std_display_device_special_memory
\t#(
\t\tparameter USEMEMSIZE = 32'h00000000,
\t\tparameter PRIORITY = 32'h00000000,
\t\tparameter DEVICECAT = 32'h00000000
\t)(\t\t\t\t\t\t\t
\t\t//System
\t\tinput wire iCLOCK,
\t\tinput wire inRESET,
\t\t//Special Addr Access
\t\tinput wire iSPECIAL_REQ,
\t\tinput wire iSPECIAL_RW,
\t\tinput wire [7:0] iSPECIAL_ADDR,
\t\tinput wire [31:0] iSPECIAL_DATA,
\t\toutput wire [31:0] oSPECIAL_DATA
\t);
\t
\tinteger\ti;
\t
\treg [31:0] b_mem[0:255];\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tfor(i = 0; i < 256; i = i + 1)begin
\t\t\t\tif(i == 0)begin
\t\t\t\t\t//USEMEMSIZE
\t\t\t\t\tb_mem[i] <= USEMEMSIZE;
\t\t\t\tend
\t\t\t\telse if(i == 1)begin
\t\t\t\t\t//PRIORITY
\t\t\t\t\tb_mem[i] <= PRIORITY;
\t\t\t\tend
\t\t\t\telse begin
\t\t\t\t\t//Other
\t\t\t\t\tb_mem[i] <= 32'h00000000;
\t\t\t\tend
\t\t\tend\t\t
\t\tend
\t\telse begin
\t\t\tif(iSPECIAL_REQ && iSPECIAL_RW)begin
\t\t\t\tb_mem [iSPECIAL_ADDR] <= iSPECIAL_ADDR;
\t\t\tend\t
\t\tend
\tend //always
\t
\tassign oSPECIAL_DATA = b_mem[iSPECIAL_ADDR];
\t
\t
endmodule
`default_nettype wire
|
/****************************************************************************************
*
* File Name: CY7C1380_PL_SCD.v
* Version: 1.0
* Date: July 28th, 2004
* Model: BUS Functional
* Simulator: Verilog-XL (CADENCE)
*
*
* Queries: MPD Applications
* Website: www.cypress.com/support
* Company: Cypress Semiconductor
* Part #: CY7C1380D (512K x 36)
*
* Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
*
*
* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
* WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
*\tCopyright(c) Cypress Semiconductor, 2004
*\tAll rights reserved
*
* Rev Date Changes
* --- ---------- ---------------------------------------
* 1.0 07/28/2004 - New Model
* - New Test Bench
* - New Test Vectors
*
****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
`timescale 1ns / 10ps
// Timings for Different Speed Bins (sb):\t250MHz, 225MHz, 200MHz, 167MHz, 133MHz
`define sb200
`ifdef sb250
`define tCO \t2.6\t// Data Output Valid After CLK Rise
`define tCYC \t4.0\t// Clock cycle time
`define tCH \t1.7\t// Clock HIGH time
`define tCL \t1.7\t// Clock LOW time
`define tCHZ \t2.6\t// Clock to High-Z
`define tCLZ \t1.0\t// Clock to Low-Z
`define tOEHZ 2.6\t// OE# HIGH to Output High-Z
`define tOELZ 0.0\t// OE# LOW to Output Low-Z
`define tOEV \t2.6\t// OE# LOW to Output Valid
`define tAS \t1.2\t// Address Set-up Before CLK Rise
`define tADS \t1.2\t// ADSC#, ADSP# Set-up Before CLK Rise
`define tADVS 1.2\t// ADV# Set-up Before CLK Rise
`define tWES \t1.2\t// BWx#, GW#, BWE# Set-up Before CLK Rise
`define tDS \t1.2\t// Data Input Set-up Before CLK Rise
`define tCES \t1.2\t// Chip Enable Set-up
`define tAH \t0.3\t// Address Hold After CLK Rise
`define tADH \t0.3\t// ADSC#, ADSP# Hold After CLK Rise
`define tADVH 0.3\t// ADV# Hold After CLK Rise
`define tWEH \t0.3\t// BWx#, GW#, BWE# Hold After CLK Rise
`define tDH \t0.3\t// Data Input Hold After CLK Rise
`define tCEH \t0.3\t// Chip Enable Hold After CLK Rise
`endif
`ifdef sb225
`define tCO 2.8 // Data Output Valid After CLK Rise
`define tCYC 4.4 // Clock cycle time
`define tCH 2.0 // Clock HIGH time
`define tCL 2.0 // Clock LOW time
`define tCHZ 2.8 // Clock to High-Z
`define tCLZ 1.0 // Clock to Low-Z
`define tOEHZ 2.8 // OE# HIGH to Output High-Z
`define tOELZ 0.0 // OE# LOW to Output Low-Z
`define tOEV 2.8 // OE# LOW to Output Valid
`define tAS 1.4 // Address Set-up Before CLK Rise
`define tADS 1.4 // ADSC#, ADSP# Set-up Before CLK Rise
`define tADVS 1.4 // ADV# Set-up Before CLK Rise
`define tWES 1.4 // BWx#, GW#, BWE# Set-up Before CLK Rise
`define tDS 1.4 // Data Input Set-up Before CLK Rise
`define tCES 1.4 // Chip Enable Set-up
`define tAH 0.4 // Address Hold After CLK Rise
`define tADH 0.4 // ADSC#, ADSP# Hold After CLK Rise
`define tADVH 0.4 // ADV# Hold After CLK Rise
`define tWEH 0.4 // BWx#, GW#, BWE# Hold After CLK Rise
`define tDH 0.4 // Data Input Hold After CLK Rise
`define tCEH 0.4 // Chip Enable Hold After CLK Rise
`endif
`ifdef sb200
`define tCO 3.0\t// Data Output Valid After CLK Rise
`define tCYC 5.0 // Clock cycle time
`define tCH 2.0 // Clock HIGH time
`define tCL 2.0 // Clock LOW time
`define tCHZ 3.0 // Clock to High-Z
`define tCLZ 1.3 // Clock to Low-Z
`define tOEHZ 3.0 // OE# HIGH to Output High-Z
`define tOELZ 0.0 // OE# LOW to Output Low-Z
`define tOEV 3.0 // OE# LOW to Output Valid
`define tAS 1.4 // Address Set-up Before CLK Rise
`define tADS 1.4 // ADSC#, ADSP# Set-up Before CLK Rise
`define tADVS 1.4 // ADV# Set-up Before CLK Rise
`define tWES 1.4 // BWx#, GW#, BWE# Set-up Before CLK Rise
`define tDS 1.4 // Data Input Set-up Before CLK Rise
`define tCES 1.4 // Chip Enable Set-up
`define tAH 0.4 // Address Hold After CLK Rise
`define tADH 0.4 // ADSC#, ADSP# Hold After CLK Rise
`define tADVH 0.4 // ADV# Hold After CLK Rise
`define tWEH 0.4 // BWx#, GW#, BWE# Hold After CLK Rise
`define tDH 0.4 // Data Input Hold After CLK Rise
`define tCEH 0.4 // Chip Enable Hold After CLK Rise
`endif
`ifdef sb167
`define tCO 3.4\t// Data Output Valid After CLK Rise
`define tCYC 6.0 // Clock cycle time
`define tCH 2.2 // Clock HIGH time
`define tCL 2.2 // Clock LOW time
`define tCHZ 3.4 // Clock to High-Z
`define tCLZ 1.3 // Clock to Low-Z
`define tOEHZ 3.4 // OE# HIGH to Output High-Z
`define tOELZ 0.0 // OE# LOW to Output Low-Z
`define tOEV 3.4 // OE# LOW to Output Valid
`define tAS 1.5 // Address Set-up Before CLK Rise
`define tADS 1.5 // ADSC#, ADSP# Set-up Before CLK Rise
`define tADVS 1.5 // ADV# Set-up Before CLK Rise
`define tWES 1.5 // BWx#, GW#, BWE# Set-up Before CLK Rise
`define tDS 1.5 // Data Input Set-up Before CLK Rise
`define tCES 1.5 // Chip Enable Set-up
`define tAH 0.5 // Address Hold After CLK Rise
`define tADH 0.5 // ADSC#, ADSP# Hold After CLK Rise
`define tADVH 0.5 // ADV# Hold After CLK Rise
`define tWEH 0.5 // BWx#, GW#, BWE# Hold After CLK Rise
`define tDH 0.5 // Data Input Hold After CLK Rise
`define tCEH 0.5 // Chip Enable Hold After CLK Rise
`endif
`ifdef sb133
`define tCO 4.2 // Data Output Valid After CLK Rise
`define tCYC 7.5 // Clock cycle time
`define tCH 2.5 // Clock HIGH time
`define tCL 2.5 // Clock LOW time
`define tCHZ 3.4 // Clock to High-Z
`define tCLZ 1.3 // Clock to Low-Z
`define tOEHZ 4.0 // OE# HIGH to Output High-Z
`define tOELZ 0.0 // OE# LOW to Output Low-Z
`define tOEV 4.2 // OE# LOW to Output Valid
`define tAS 1.5 // Address Set-up Before CLK Rise
`define tADS 1.5 // ADSC#, ADSP# Set-up Before CLK Rise
`define tADVS 1.5 // ADV# Set-up Before CLK Rise
`define tWES 1.5 // BWx#, GW#, BWE# Set-up Before CLK Rise
`define tDS 1.5 // Data Input Set-up Before CLK Rise
`define tCES 1.5 // Chip Enable Set-up
`define tAH 0.5 // Address Hold After CLK Rise
`define tADH 0.5 // ADSC#, ADSP# Hold After CLK Rise
`define tADVH 0.5 // ADV# Hold After CLK Rise
`define tWEH 0.5 // BWx#, GW#, BWE# Hold After CLK Rise
`define tDH 0.5 // Data Input Hold After CLK Rise
`define tCEH 0.5 // Chip Enable Hold After CLK Rise
`endif
module CY7C1380_PLSCD (ZZ, Mode, ADDR, GW_N, BWE_N, BWd_N, BWc_N, BWb_N, BWa_N, CE1_N, CE2, CE3_N, ADSP_N, ADSC_N, ADV_N, OE_N, DQ, CLK);
parameter addr_bits = 19; // \t19 bits
parameter data_bits = 36; // \t36 bits
parameter mem_sizes = 524288; // \t512K
inout [(data_bits - 1) : 0] DQ; // Data IO
input [(addr_bits - 1) : 0] ADDR; // ADDRess
input Mode; // Burst Mode
input ADV_N; // Synchronous ADDRess Advance
input CLK; // Clock
input ADSC_N; // Synchronous ADDRess Status Controller
input ADSP_N; // Synchronous ADDRess Status Processor
input BWa_N; // Synchronous Byte Write Enables
input BWb_N; // Synchronous Byte Write Enables
input BWc_N; // Synchronous Byte Write Enables
input BWd_N; // Synchronous Byte Write Enables
input BWE_N; // Byte Write Enable
input GW_N; // Global Write
input CE1_N; // Synchronous Chip Enable
input CE2; // Synchronous Chip Enable
input CE3_N; // Synchronous Chip Enable
input OE_N; // Output Enable
input ZZ; // Snooze Mode
reg [((data_bits / 4) - 1) : 0] bank0 [0 : mem_sizes]; // Memory Bank 0
reg [((data_bits / 4) - 1) : 0] bank1 [0 : mem_sizes]; // Memory Bank 1
reg [((data_bits / 4) - 1) : 0] bank2 [0 : mem_sizes]; // Memory Bank 2
reg [((data_bits / 4) - 1) : 0] bank3 [0 : mem_sizes]; // Memory Bank 3
reg [(data_bits - 1) : 0] din; // Data In
reg [(data_bits - 1) : 0] dout; // Data Out
reg [(addr_bits - 1) : 0] addr_reg_in; // ADDRess Register In
reg [(addr_bits - 1) : 0] addr_reg_read; // ADDRess Register for Read
reg [(addr_bits - 1) : 0] addr_reg_write; // ADDRess Register for Write
reg [1 : 0] bcount; // 2-bit Burst Counter
reg [1 : 0] first_addr; // 2-bit Burst Counter
reg ce_reg;
reg Read_reg;
reg Read_reg_o;
reg WrN_reg;
reg ADSP_N_o;
reg pipe_reg;
reg bwa_reg;
reg bwb_reg;
reg bwc_reg;
reg bwd_reg;
reg Sys_clk;
reg test;
reg pcsr_write;
reg ctlr_write;
reg latch_addr_current;
reg latch_addr_old;
wire ce = (~CE1_N & CE2 & ~CE3_N);
wire Write_n = ~(((~BWa_N | ~BWb_N | ~BWc_N | ~BWd_N) & ~BWE_N) | ~GW_N ) ;
wire Read = (((BWa_N & BWb_N & BWc_N & BWd_N) & ~BWE_N) | (GW_N & BWE_N) | (~ADSP_N & ce)) ;
wire bwa_n = ~(~Write_n & (~GW_N | (~BWE_N & ~BWa_N )));\t\t
wire bwb_n = ~(~Write_n & (~GW_N | (~BWE_N & ~BWb_N )));\t\t
wire bwc_n = ~(~Write_n & (~GW_N | (~BWE_N & ~BWc_N )));\t\t
wire bwd_n = ~(~Write_n & (~GW_N | (~BWE_N & ~BWd_N )));\t\t
wire latch_addr = (~ADSC_N | (~ADSP_N & ~CE1_N));
wire #`tOEHZ \t\t\tOeN_HZ = OE_N ? 1 : 0;
wire #`tOEV \t\t\tOeN_DataValid = ~OE_N ? 0 : 1;
wire OeN_efct = \t\t~OE_N ? OeN_DataValid : OeN_HZ;
wire #`tCHZ \t\t\tWR_HZ = WrN_reg ? 1 : 0;
wire #`tCLZ \t\t\tWR_LZ = ~WrN_reg ? 0 : 1;
wire WR_efct = \t\t~WrN_reg ? WR_LZ : WR_HZ;
wire #`tCHZ\t\t\tCE_HZ = (~ce_reg | ~pipe_reg) ? 0 : 1 ;
wire #`tCLZ\t\t\tCE_LZ = pipe_reg ? 1 : 0 ;
wire Pipe_efct = \t\t(ce_reg & pipe_reg) ? CE_LZ : CE_HZ ;
wire #`tCHZ\t\t\tRD_HZ = ~Read_reg_o ? 0 : 1 ;
wire #`tCLZ\t\t\tRD_LZ = Read_reg_o ? 1 : 0 ;
wire RD_efct = \t\tRead_reg_o ? CE_LZ : CE_HZ ;
\t
\t
\t
\t
\t//Test
\tint i;
\tinitial
\t #0 begin
\t \tfor(i = 0; i < 640*480/2; i = i + 1)begin
\t \t\tif(i < (640*480)/4)begin
\t\t\t\t{bank3[i], bank2[i], bank1[i], bank0[i]} = func_data(i*2);//t_test({2{5\'hFF, 6\'h00, 5\'h00}});
\t\t\tend
\t\t\telse begin
\t\t\t\t{bank3[i], bank2[i], bank1[i], bank0[i]} = func_data(i*2);//t_test({2{5\'h0, 6\'h00, 5\'hFF}});
\t\t\tend
\t\tend
\tend
\t
\tfunction [35:0] func_data;
\t\tinput [15:0] data;
\t\treg [15:0] r_data0;
\t\treg [15:0] r_data1;
\t\tbegin
\t\t\tr_data0 = data;
\t\t\tr_data1 = data + 1;
\t\t\tfunc_data = {1\'b0, r_data1[15:8], 1\'b0, r_data1[7:0], 1\'b0, r_data0[15:8], 1\'b0, r_data0[7:0]};
\t\tend
\tendfunction
\t\t
\tfunction [35:0] t_test;
\t\tinput [31:0] data;
\t\tbegin
\t\t\tt_test = {1\'b0, data[31:24], 1\'b0, data[23:16], 1\'b0, data[15:8], 1\'b0, data[7:0]};
\t\tend
\tendfunction
// Initialize
initial begin
ce_reg = 1\'b0;
pipe_reg = 1\'b0;
Sys_clk = 1\'b0;
$timeformat (-9, 1, " ns", 10); // Format time unit
end
// System Clock Decode
always begin
@ (posedge CLK) begin
Sys_clk = ~ZZ;
end
@ (negedge CLK) begin
Sys_clk = 1\'b0;
end
end
always @ (posedge Sys_clk) begin
\t// Read Register
if (~Write_n) Read_reg_o = 1\'b0;
else Read_reg_o = Read_reg;
if (~Write_n) Read_reg = 1\'b0;
\telse Read_reg = Read;
if (Read_reg == 1\'b1) begin
\t\tpcsr_write = 1\'b0;
\t\tctlr_write = 1\'b0;
\tend
\t// Write Register
\tif (Read_reg_o == 1\'b1)\tWrN_reg = 1\'b1;
\telse WrN_reg = Write_n;
\tlatch_addr_old = latch_addr_current;
\tlatch_addr_current = latch_addr;
if (latch_addr_old == 1\'b1 & ~Write_n & ADSP_N_o == 1\'b0)
\t\t\tpcsr_write = 1\'b1; //Ctlr Write = 0; Pcsr Write = 1;
else if (latch_addr_current == 1\'b1 & ~Write_n & ADSP_N & ~ADSC_N)
\t\t\tctlr_write = 1\'b1; //Ctlr Write = 0; Pcsr Write = 1;
// ADDRess Register
if (latch_addr)
\t\tbegin
\t\t\taddr_reg_in = ADDR;
\t\tbcount = ADDR [1 : 0];
\t\tfirst_addr = ADDR [1 : 0];
\t\tend
// ADSP_N Previous-Cycle Register
ADSP_N_o <= ADSP_N;
// Binary Counter and Logic
\t\tif (~Mode & ~ADV_N & ~latch_addr) \t// Linear Burst
\t\tbcount = (bcount + 1); \t// Advance Counter\t
\t\telse if (Mode & ~ADV_N & ~latch_addr) \t// Interleaved Burst
\t\tbegin
\t\t\tif (first_addr % 2 == 0)
\t\t\tbcount = (bcount + 1); // Increment Counter
\t\t\telse if (first_addr % 2 == 1)
\t\t\tbcount = (bcount - 1); // Decrement Counter
\t\tend
// Read ADDRess
addr_reg_read = addr_reg_write;
// Write ADDRess
addr_reg_write = {addr_reg_in [(addr_bits - 1) : 2], bcount[1], bcount[0]};
// Byte Write Register
bwa_reg = ~bwa_n;
bwb_reg = ~bwb_n;
bwc_reg = ~bwc_n;
bwd_reg = ~bwd_n;
// Enable Register
pipe_reg = ce_reg;
\t
// Enable Register
if (latch_addr) ce_reg = ce;
// Input Register
if (ce_reg & (~bwa_n | ~bwb_n | ~bwc_n | ~bwd_n) & (pcsr_write | ctlr_write)) begin
din = DQ;
end
// Byte Write Driver
if (ce_reg & bwa_reg) begin
bank0 [addr_reg_write] = din [ 8 : 0];
end
if (ce_reg & bwb_reg) begin
bank1 [addr_reg_write] = din [17 : 9];
end
if (ce_reg & bwc_reg) begin
bank2 [addr_reg_write] = din [26 : 18];
end
if (ce_reg & bwd_reg) begin
bank3 [addr_reg_write] = din [35 : 27];
end
\t\t
// Output Registers
if (~Write_n | pipe_reg == 1\'b0)
dout [ 35 : 0] <= #`tCHZ 36\'bZ;
else if (Read_reg_o == 1\'b1) begin
dout [ 8 : 0] <= #`tCO bank0 [addr_reg_read];
dout [17 : 9] <= #`tCO bank1 [addr_reg_read];
dout [26 : 18] <= #`tCO bank2 [addr_reg_read];
dout [35 : 27] <= #`tCO bank3 [addr_reg_read];
end
end
\t
\t
// Output Buffers
assign DQ = (~OE_N & ~ZZ & Pipe_efct & RD_efct & WR_efct) ? dout : 36\'bz;
// Timing Check
specify
$width (negedge CLK, `tCL);
$width (posedge CLK, `tCH);
$period (negedge CLK, `tCYC);
$period (posedge CLK, `tCYC);
$setuphold (posedge CLK, ADSP_N, `tADS, `tADH);
$setuphold (posedge CLK, ADSC_N, `tADS, `tADH);
$setuphold (posedge CLK, ADDR, `tAS, `tAH);
$setuphold (posedge CLK, BWa_N, `tWES, `tWEH);
$setuphold (posedge CLK, BWb_N, `tWES, `tWEH);
$setuphold (posedge CLK, BWc_N, `tWES, `tWEH);
$setuphold (posedge CLK, BWd_N, `tWES, `tWEH);
$setuphold (posedge CLK, BWE_N, `tWES, `tWEH);
$setuphold (posedge CLK, GW_N, `tWES, `tWEH);
$setuphold (posedge CLK, CE1_N, `tCES, `tCEH);
$setuphold (posedge CLK, CE2, `tCES, `tCEH);
$setuphold (posedge CLK, CE3_N, `tCES, `tCEH);
$setuphold (posedge CLK, ADV_N, `tADVS, `tADVH);
endspecify
endmodule
|
/*******************************************************
\tMIST32 Standard Device : Display Device
\t- Support Display Area
\t\t-640*480 (60Hz) : 25MHz
\t\t-800x480 (60Hz) : 33.2MHz
\t\t-800x600 (75Hz) : 49MHz
\t\t-1024x768 (70Hz) : 75MHz
\t- Charactor Size : 14*8
\t- Display Size(Charactor Count)
\t\t\t\t80
\t\t|---------------|
\t\t|\t\t\t\t|
\t34\t|\t\t\t\t|
\t\t|\t\t\t\t|
\t\t|---------------|
\t\t
\t- Memory MAP
\t\t0~3FF\t\t\t: Node Special Memory
\t\t400\t\t\t\t: 1Line Charactor Set (Data : ANSI Charactor = 7bit) {BackColor[31:20], CharactorColor[19:8], none[7], Charactor[6:0]}
\t\t800\t\t\t\t: 2Line Charactor Set (Data : ANSI Charactor = 7bit) {BackColor[31:20], CharactorColor[19:8], none[7], Charactor[6:0]}
\t\t~
\t\t8400\t\t\t: 32Line Charactor Set (Data : ANSI Charactor = 7bit) {BackColor[31:20], CharactorColor[19:8], none[7], Charactor[6:0]}
\t\tC000\t\t\t: Display Clear CMD (Data : Collor 16bit = 5R6G5B) {none[31:16], Color[15:0]}
\t\tC400\t\t\t: Bitmap 0 (Data : Collor 15bit = 5R6G5B) {none[31:16], Color[15:0]}
\t\t~
\t\t1383FC\t\t\t: Bitmap 307199 (Data : Collor 15bit = 5R6G5B) {none[31:16], Color[15:0]}
\t\t
\t\t
\t
\tMake\t:\t2011/07/17
\tUpdate\t:\t2011/10/08
\t
\t2011/10/08
\t\tBug Fix : (Final Line Bug)
\t\tCharactor Color & Charactor Back Color Adding
\t2011/10/01
\t\tMemory Access Timing Miss Fix
\t2011/09/25
\t\tMemory Write Timing Optimization
*******************************************************/
`default_nettype none
/*
`define\t\tIRQCODE_MEMOVER\t\t\t24'h000000\t\t\t//Charactor Display Device Memory Size Over Access
`define\t\tIRQCODE_READACC\t\t\t24'h000001\t\t\t//Read Access
*/
module gci_std_display(
\t\t//System
\t\tinput wire iCLOCK,
\t\tinput wire inRESET,
\t\t//BUS(DATA)-Input
\t\tinput wire iDEV_REQ,\t\t
\t\toutput wire oDEV_BUSY,
\t\tinput wire iDEV_RW,
\t\tinput wire [31:0] iDEV_ADDR,\t//Byte Address
\t\tinput wire [31:0] iDEV_DATA,
\t\t//BUS(DATA)-Output
\t\toutput wire oDEV_REQ,\t\t
\t\tinput wire iDEV_BUSY,
\t\toutput wire [31:0] oDEV_DATA,
\t\t//IRQ
\t\toutput wire oDEV_IRQ_REQ,\t\t
\t\tinput wire iDEV_IRQ_BUSY,
\t\toutput wire [23:0] oDEV_IRQ_DATA, \t
\t\tinput wire iDEV_IRQ_ACK,
\t\t//Display Clock
\t\tinput wire iVGA_CLOCK,
\t\t`ifdef GCI_STD_DISPLAY_SRAM
\t\t\t//SRAM
\t\t\toutput wire onSRAM_CE,
\t\t\toutput wire onSRAM_WE,
\t\t\toutput wire onSRAM_OE,
\t\t\toutput wire onSRAM_UB,
\t\t\toutput wire onSRAM_LB,
\t\t\toutput wire [19:0] oSRAM_ADDR,
\t\t\tinout wire [15:0] ioSRAM_DATA,
\t\t`elsif GCI_STD_DISPLAY_SSRAM
\t\t\t//SSRAM
\t\t\toutput wire oSSRAM_CLOCK,
\t\t\toutput wire onSSRAM_ADSC,
\t\t\toutput wire onSSRAM_ADSP,
\t\t\toutput wire onSSRAM_ADV,
\t\t\toutput wire onSSRAM_GW,
\t\t\toutput wire onSSRAM_OE,
\t\t\toutput wire onSSRAM_WE,
\t\t\toutput wire [3:0] onSSRAM_BE,
\t\t\toutput wire onSSRAM_CE1,
\t\t\toutput wire oSSRAM_CE2,
\t\t\toutput wire onSSRAM_CE3,
\t\t\toutput wire [18:0] oSSRAM_ADDR,
\t\t\tinout wire [31:0] ioSSRAM_DATA,
\t\t\tinout wire [3:0] ioSSRAM_PARITY,
\t\t`endif
\t\t//Display\t\t
\t\toutput wire oDISP_CLOCK,
\t\toutput wire onDISP_RESET,
\t\toutput wire oDISP_ENA,
\t\toutput wire oDISP_BLANK,
\t\toutput wire onDISP_HSYNC,
\t\toutput wire onDISP_VSYNC,
\t\toutput wire [9:0] oDISP_DATA_R,
\t\toutput wire [9:0] oDISP_DATA_G,
\t\toutput wire [9:0] oDISP_DATA_B\t
\t);\t\t\t\t\t
\t
\t/************************************************************
\tWire
\t************************************************************/
\t//Display Controllor
\twire displaycontroller_wait;
\t//Condition
\twire special_addr_use_condition;
\twire display_addr_wr_condition;
\t//Special Memory
\twire [31:0] special_memory_rd_data;
\t//Data Output Buffer
\treg b_req;
\treg [31:0] b_data;
\t
\t/************************************************************
\tCondition
\t************************************************************/
\tassign special_addr_use_condition = iDEV_REQ && (iDEV_ADDR < 32'h00000400) && !displaycontroller_wait;
\tassign display_addr_wr_condition = iDEV_REQ && (iDEV_ADDR >= 32'h00000400) && !displaycontroller_wait;
\t
\t
\t/************************************************************
\tSpecial Memory
\t************************************************************/\t
\tgci_std_display_device_special_memory #(32'h001383FC + 32'h4, 32'h00000000, 32'h00000002) VGA640X480_60HZ_SPECIAL_MEM(
\t\t.iCLOCK(iCLOCK),
\t\t.inRESET(inRESET),
\t\t.iSPECIAL_REQ(special_addr_use_condition),
\t\t.iSPECIAL_RW(iDEV_RW),
\t\t.iSPECIAL_ADDR(iDEV_ADDR[9:2]),
\t\t.iSPECIAL_DATA(iDEV_DATA),
\t\t.oSPECIAL_DATA(special_memory_rd_data)
\t);
\t
\t/************************************************************
\tDisplay Controller
\t************************************************************/\t\t
\tgci_std_display_display_controller DISPLAY_MODULE(
\t\t//System
\t\t.iCLOCK(iCLOCK),
\t\t.inRESET(inRESET),\t\t
\t\t//Display Clock
\t\t.iDISP_CLOCK(iVGA_CLOCK),\t\t
\t\t//Write Reqest
\t\t.iIF_WR_REQ(display_addr_wr_condition),
\t\t.oIF_WR_BUSY(displaycontroller_wait),
\t\t.iIF_WR_ADDR({2'h0, iDEV_ADDR[31:2]}),
\t\t.iIF_WR_DATA(iDEV_DATA),
\t\t//SRAM
\t\t`ifdef GCI_STD_DISPLAY_SRAM
\t\t\t.onSRAM_CE(onSRAM_CE),
\t\t\t.onSRAM_WE(onSRAM_WE),
\t\t\t.onSRAM_OE(onSRAM_OE),
\t\t\t.onSRAM_UB(onSRAM_UB),
\t\t\t.onSRAM_LB(onSRAM_LB),
\t\t\t.oSRAM_ADDR(oSRAM_ADDR),
\t\t\t.ioSRAM_DATA(ioSRAM_DATA),
\t\t//SSRAM
\t\t`elsif GCI_STD_DISPLAY_SSRAM
\t\t\t.oSSRAM_CLOCK(oSSRAM_CLOCK),
\t\t\t.onSSRAM_ADSC(onSSRAM_ADSC),
\t\t\t.onSSRAM_ADSP(onSSRAM_ADSP),
\t\t\t.onSSRAM_ADV(onSSRAM_ADV),
\t\t\t.onSSRAM_GW(onSSRAM_GW),
\t\t\t.onSSRAM_OE(onSSRAM_OE),
\t\t\t.onSSRAM_WE(onSSRAM_WE),
\t\t\t.onSSRAM_BE(onSSRAM_BE),
\t\t\t.onSSRAM_CE1(onSSRAM_CE1),
\t\t\t.oSSRAM_CE2(oSSRAM_CE2),
\t\t\t.onSSRAM_CE3(onSSRAM_CE3),
\t\t\t.oSSRAM_ADDR(oSSRAM_ADDR),
\t\t\t.ioSSRAM_DATA(ioSSRAM_DATA),
\t\t\t.ioSSRAM_PARITY(ioSSRAM_PARITY),
\t\t`endif
\t\t//Display
\t\t.oDISP_CLOCK(oDISP_CLOCK),
\t\t.onDISP_RESET(onDISP_RESET),
\t\t.oDISP_ENA(oDISP_ENA),
\t\t.oDISP_BLANK(oDISP_BLANK),
\t\t.onDISP_HSYNC(onDISP_HSYNC),
\t\t.onDISP_VSYNC(onDISP_VSYNC),
\t\t.oDISP_DATA_R(oDISP_DATA_R),
\t\t.oDISP_DATA_G(oDISP_DATA_G),
\t\t.oDISP_DATA_B(oDISP_DATA_B)\t
\t);\t
\t
\t/************************************************************
\tOutput Buffer
\t************************************************************/\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_req <= 1'b0;
\t\t\tb_data <= {32{1'b0}};
\t\tend
\t\telse begin
\t\t\tb_req <= (special_addr_use_condition || display_addr_wr_condition);
\t\t\tb_data <= (special_addr_use_condition)? special_memory_rd_data : {32{1'b0}};
\t\tend
\tend
\t
\t
\t/************************************************************
\tAssign
\t************************************************************/\t
\tassign oDEV_BUSY = displaycontroller_wait;
\tassign oDEV_REQ = b_req;
\tassign oDEV_DATA = b_data;
\tassign oDEV_IRQ_REQ = 1'b0;
\tassign oDEV_IRQ_DATA = {24{1'b0}};
\t
endmodule
`default_nettype wire
|
`default_nettype none
module gci_std_display_vram_interface #(
\t\tparameter P_MEM_ADDR_N = 19
\t)(
\t\tinput wire iGCI_CLOCK,
\t\tinput wire inRESET,
\t\tinput wire iRESET_SYNC,
\t\t//IF0 (Priority IF0>IF1)
\t\tinput wire iIF0_REQ,
\t\toutput wire oIF0_ACK,
\t\tinput wire iIF0_FINISH,
\t\tinput wire iIF0_ENA,
\t\toutput wire oIF0_BUSY,
\t\tinput wire iIF0_RW,
\t\tinput wire [P_MEM_ADDR_N-1:0] iIF0_ADDR,
\t\tinput wire [31:0] iIF0_DATA,
\t\toutput wire oIF0_VALID,
\t\tinput wire iIF0_BUSY,
\t\toutput wire [31:0] oIF0_DATA,
\t\t//IF1
\t\tinput wire iIF1_REQ,
\t\toutput wire oIF1_ACK,
\t\tinput wire iIF1_FINISH,
\t\toutput wire oIF1_BREAK,
\t\tinput wire iIF1_ENA,
\t\toutput wire oIF1_BUSY,
\t\tinput wire iIF1_RW,
\t\tinput wire [P_MEM_ADDR_N-1:0] iIF1_ADDR,
\t\tinput wire [31:0] iIF1_DATA,
\t\toutput wire oIF1_VALID,
\t\tinput wire iIF1_BUSY,
\t\toutput wire [31:0] oIF1_DATA,
\t\t//Vram Interface
\t\toutput wire oVRAM_ARBIT_REQ,
\t\tinput wire iVRAM_ARBIT_ACK,
\t\toutput wire oVRAM_ARBIT_FINISH,
\t\toutput wire oVRAM_ENA,
\t\tinput wire iVRAM_BUSY,
\t\toutput wire oVRAM_RW,
\t\toutput wire [P_MEM_ADDR_N-1:0] oVRAM_ADDR,
\t\toutput wire [31:0] oVRAM_DATA,
\t\tinput wire iVRAM_VALID,
\t\toutput wire oVRAM_BUSY,
\t\tinput wire [31:0] iVRAM_DATA
\t);
\t
\t//Main State
\tparameter P_L_MAIN_STT_IDLE = 2'h0;
\tparameter P_L_MAIN_STT_REQ = 2'h1;
\tparameter P_L_MAIN_STT_IF0 = 2'h2;
\tparameter P_L_MAIN_STT_IF1 = 2'h3;
\t
\t
\t//Main State
\treg [1:0] b_main_state;
\treg [1:0] b_main_if_select;
\t//IF 2 Memory
\treg b_if2vram_req;
\treg b_if2vram_finish;
\treg b_if2vram_ena;
\treg b_if2vram_rw;
\treg [P_MEM_ADDR_N-1:0] b_if2vram_addr;
\treg [31:0] b_if2vram_data;
\treg b_if2vram_busy;
\t//Memory 2 IF0
\treg b_vram2if0_ack;
\treg b_vram2if0_busy;
\treg b_vram2if0_valid;
\treg [31:0] b_vram2if0_data;\t
\t//Memory 2 IF1
\treg b_vram2if1_ack;
\treg b_vram2if1_busy;
\treg b_vram2if1_valid;
\treg [31:0] b_vram2if1_data;
\t//IF0 Pryority
\treg b_if0_break;
\t
\t/***************************************************
\tState
\t***************************************************/
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\tb_main_if_select <= P_L_PARAM_STT_IDLE;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_main_state <= P_L_PARAM_STT_IDLE;
\t\t\tb_main_if_select <= P_L_PARAM_STT_IDLE;
\t\tend
\t\telse begin
\t\t\tcase(b_main_state)
\t\t\t\tP_L_MAIN_STT_IDLE:
\t\t\t\t\tbegin\t\t\t
\t\t\t\t\t\tif(iIF0_REQ)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_REQ;
\t\t\t\t\t\t\tb_main_if_select <= P_L_MAIN_STT_IF0;
\t\t\t\t\t\tend
\t\t\t\t\t\telse if(iIF1_REQ)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_REQ;
\t\t\t\t\t\t\tb_main_if_select <= P_L_MAIN_STT_IF1;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_REQ:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iVRAM_ARBIT_ACK)begin
\t\t\t\t\t\t\tb_main_state <= b_main_if_select;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_IF0:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iIF0_FINISH)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_IF1:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iIF1_FINISH)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend //main state
\t
\t
\t//IF 2 Memory
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin\t
\t\tif(!inRESET)begin\t\t\t
\t\t\tb_if2vram_req <= 1'b0;
\t\t\tb_if2vram_finish <= 1'b0;
\t\t\tb_if2vram_ena <= 1'b0;
\t\t\tb_if2vram_rw <= 1'b0;
\t\t\tb_if2vram_addr <= {P_MEM_ADDR_N{1'b0}};
\t\t\tb_if2vram_data <= 32'h0;
\t\t\tb_if2vram_busy <= 1'b0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_if2vram_req <= 1'b0;
\t\t\tb_if2vram_finish <= 1'b0;
\t\t\tb_if2vram_ena <= 1'b0;
\t\t\tb_if2vram_rw <= 1'b0;
\t\t\tb_if2vram_addr <= {P_MEM_ADDR_N{1'b0}};
\t\t\tb_if2vram_data <= 32'h0;
\t\t\tb_if2vram_busy <= 1'b0;
\t\tend
\t\telse begin
\t\t\tif(b_main_state == P_L_MAIN_STT_IF0)begin
\t\t\t\tb_if2vram_req <= iIF0_REQ;
\t\t\t\tb_if2vram_finish <= iIF0_FINISH;
\t\t\t\tb_if2vram_ena <= iIF0_ENA;
\t\t\t\tb_if2vram_rw <= iIF0_RW;
\t\t\t\tb_if2vram_addr <= iIF0_ADDR;
\t\t\t\tb_if2vram_data <= iIF0_DATA;
\t\t\t\tb_if2vram_busy <= iIF0_BUSY;
\t\t\tend
\t\t\telse if(b_main_state == P_L_MAIN_STT_IF1)begin
\t\t\t\tb_if2vram_req <= iIF1_REQ;
\t\t\t\tb_if2vram_finish <= iIF1_FINISH;
\t\t\t\tb_if2vram_ena <= iIF1_ENA;
\t\t\t\tb_if2vram_rw <= iIF1_RW;
\t\t\t\tb_if2vram_addr <= iIF1_ADDR;
\t\t\t\tb_if2vram_data <= iIF1_DATA;
\t\t\t\tb_if2vram_busy <= iIF1_BUSY;
\t\t\tend
\t\t\telse begin
\t\t\t\tb_if2vram_req <= 1'b0;
\t\t\t\tb_if2vram_finish <= 1'b0;
\t\t\t\tb_if2vram_ena <= 1'b0;
\t\t\t\tb_if2vram_rw <= 1'b0;
\t\t\t\tb_if2vram_addr <= {P_MEM_ADDR_N{1'b0}};
\t\t\t\tb_if2vram_busy <= 1'b0;
\t\t\t\tb_if2vram_data <= 32'h0;
\t\t\t\tb_if2vram_busy <= 1'b0;
\t\t\tend
\t\tend
\tend //Output buffer alwyas
\t
\t
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_vram2if0_ack <= 1'b0;
\t\t\tb_vram2if0_busy <= 1'b0;
\t\t\tb_vram2if0_valid <= 1'b0;
\t\t\tb_vram2if0_data <= 32'h0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_vram2if0_ack <= 1'b0;
\t\t\tb_vram2if0_busy <= 1'b0;
\t\t\tb_vram2if0_valid <= 1'b0;
\t\t\tb_vram2if0_data <= 32'h0;
\t\tend
\t\telse begin
\t\t\tif(b_main_state == P_L_MAIN_STT_IF0)begin
\t\t\t\tb_vram2if0_ack <= iVRAM_ARBIT_ACK;
\t\t\t\tb_vram2if0_busy <= iVRAM_BUSY;
\t\t\t\tb_vram2if0_valid <= iVRAM_VALID;
\t\t\t\tb_vram2if0_data <= iVRAM_DATA;
\t\t\tend
\t\t\telse begin
\t\t\t\tb_vram2if0_ack <= 1'b0;
\t\t\t\tb_vram2if0_busy <= 1'b0;
\t\t\t\tb_vram2if0_valid <= 1'b0;
\t\t\t\tb_vram2if0_data <= 32'h0;
\t\t\tend
\t\tend
\tend
\t
\t
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_vram2if1_ack <= 1'b0;
\t\t\tb_vram2if1_busy <= 1'b0;
\t\t\tb_vram2if1_valid <= 1'b0;
\t\t\tb_vram2if1_data <= 32'h0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_vram2if1_ack <= 1'b0;
\t\t\tb_vram2if1_busy <= 1'b0;
\t\t\tb_vram2if1_valid <= 1'b0;
\t\t\tb_vram2if1_data <= 32'h0;
\t\tend
\t\telse begin
\t\t\tif(b_main_state == P_L_MAIN_STT_IF1)begin
\t\t\t\tb_vram2if1_ack <= iVRAM_ARBIT_ACK;
\t\t\t\tb_vram2if1_busy <= iVRAM_BUSY;
\t\t\t\tb_vram2if1_valid <= iVRAM_VALID;
\t\t\t\tb_vram2if1_data <= iVRAM_DATA;
\t\t\tend
\t\t\telse begin
\t\t\t\tb_vram2if1_ack <= 1'b0;
\t\t\t\tb_vram2if1_busy <= 1'b0;
\t\t\t\tb_vram2if1_valid <= 1'b0;
\t\t\t\tb_vram2if1_data <= 32'h0;
\t\t\tend
\t\tend
\tend
\t
\t
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_if0_break <= 1'b0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_if0_break <= 1'b0;
\t\tend
\t\telse begin
\t\t\tb_if0_break <= (b_main_state == P_L_MAIN_STT_IF1) && iIF0_REQ;
\t\tend
\tend //Priority
\t
\t
\t
\tassign oVRAM_ARBIT_REQ = b_if2vram_req;
\tassign oVRAM_ARBIT_FINISH = b_if2vram_finish;
\tassign oVRAM_ENA = b_if2vram_ena;
\tassign oVRAM_RW = b_if2vram_rw;
\tassign oVRAM_ADDR = b_if2vram_addr;
\tassign oVRAM_DATA = b_if2vram_data;
\tassign oVRAM_BUSY = b_if2vram_busy;
\t\t
\tassign oIF0_ACK = b_vram2if0_ack;
\tassign oIF0_BUSY = b_vram2if0_busy;
\tassign oIF0_VALID = b_vram2if0_valid;
\tassign oIF0_DATA = b_vram2if0_data;
\tassign oIF1_ACK = b_vram2if1_ack;
\tassign oIF1_BREAK = b_if0_break;
\tassign oIF1_BUSY = b_vram2if1_busy;
\tassign oIF1_VALID = b_vram2if1_valid;
\tassign oIF1_DATA = b_vram2if1_data;
\t
\t
endmodule
`default_nettype wire
|
`timescale 1ns/10ps
`default_nettype none
module display_model #(
\t\t/**********************************************
\t\t640x480 60Hz VGA Monitor for default parameter
\t\t**********************************************/
\t\tparameter P_DOT_CYCLE = 40,\t//25MHz
\t\t//Counter Width
\t\tparameter P_H_AREA = 640,
\t\tparameter P_V_AREA = 480,
\t\t//Hsync
\t\tparameter P_THP = 95,\t//Hsync pulse width.(Unit:NCLK)
\t\tparameter P_THB = 48,\t//To Hsync - data width.(Unit:NCLK)
\t\tparameter P_THF = 15,\t//To data - next Hsync width.(Unit:NCLK)
\t\t//Vsync
\t\tparameter P_TVP = 2,\t//Vsync pulse width.(Unit:HSYNC)
\t\tparameter P_TVB = 33,\t//To Vsync - active data area width.(Unit:HSYNC)
\t\tparameter P_TVF = 10\t//To active data area - next Vsync width.(Unit:HSYNC)
\t)(
\t\tinput wire iFILE_DUMP,
\t\tinput wire inSYNC_H,
\t\tinput wire inSYNC_V,
\t\tinput wire [7:0] iDISP_R,
\t\tinput wire [7:0] iDISP_G,
\t\tinput wire [7:0] iDISP_B
\t);
\t
\tinteger i, j;
\treg [7:0] b_disp_r[0:(P_H_AREA*P_V_AREA)-1];
\treg [7:0] b_disp_g[0:(P_H_AREA*P_V_AREA)-1];
\treg [7:0] b_disp_b[0:(P_H_AREA*P_V_AREA)-1];
\t
\t//Hsync-THP Check
\tinteger hsync_thp_time;
\treg hsync_thp_check_end;
\tinitial begin
\t\thsync_thp_time = 0;
\t\thsync_thp_check_end = 0;
\t\t//Wait
\t\t#(P_DOT_CYCLE/2);
\t\twhile(inSYNC_H == 0 || inSYNC_H == 1\'bx)begin
\t\t\t#(P_DOT_CYCLE);
\t\tend
\t\twhile(inSYNC_H == 1)begin
\t\t\t#(P_DOT_CYCLE);
\t\tend
\t\t//THP
\t\twhile(!inSYNC_H)begin
\t\t\thsync_thp_time = hsync_thp_time + 1;
\t\t\t#(P_DOT_CYCLE);
\t\tend
\t\tif(hsync_thp_time != P_THP)begin
\t\t\t$display("[ERROR][display_model] : THP Error. Correct%d, Fact%d", P_THP, hsync_thp_time);
\t\t\t$stop;
\t\tend
\t\t$display("[OK][display_model] : HSYNC THP Timing OK");
\t\thsync_thp_check_end = 1;
\tend
\t
\t//Hsync-other timing Check
\tinteger hsync_other_time;
\treg hsync_other_check_end;
\tinitial begin
\t\thsync_other_time = 0;
\t\thsync_other_check_end = 0;
\t\t//Wait
\t\t#(P_DOT_CYCLE/2);
\t\twhile(inSYNC_H == 0 || inSYNC_H == 1\'bx)begin
\t\t\t#(P_DOT_CYCLE);
\t\tend
\t\t//THB or P_H_AREA or THF
\t\twhile(inSYNC_H)begin
\t\t\thsync_other_time = hsync_other_time + 1;
\t\t\t#(P_DOT_CYCLE);
\t\tend
\t\tif(hsync_other_time != (P_THB+P_H_AREA+P_THF))begin
\t\t\t$display("[ERROR][display_model] : THB or P_H_AREA or THF Error. Correct%d, Fact%d", (P_THB+P_H_AREA+P_THF), hsync_other_time);
\t\t\t$stop;
\t\tend
\t\t$display("[OK][display_model] : HSYNC THP, P_H_AREA, THF OK");
\t\thsync_other_check_end = 1;
\tend
\t\t
\t\t
\t//Vsync Check
\tinteger vsync_time;
\treg vsync_check_end;
\tinitial begin
\t\tvsync_time = 0;
\t\tvsync_check_end = 0;
\t\t//Wait
\t\t#(P_DOT_CYCLE);
\t\twhile(!inSYNC_V || inSYNC_V == 1\'bx)begin
\t\t\t#(P_DOT_CYCLE);
\t\tend
\t\twhile(inSYNC_V)begin
\t\t\t#(P_DOT_CYCLE);
\t\tend
\t\t//TVP
\t\twhile(!inSYNC_V)begin
\t\t\t#(P_DOT_CYCLE);
\t\t\tvsync_time = vsync_time + 1;
\t\tend
\t\tif(vsync_time != P_TVP*(P_THP+P_THB+P_H_AREA+P_THF))begin
\t\t\t$display("[ERROR][display_model] : TVP Error. Correct%d, Fact%d", P_TVP*(P_THP+P_THB+P_H_AREA+P_THF), vsync_time);
\t\t\t$stop;
\t\tend
\t\telse begin
\t\t\t$display("[OK][display_model] : TVP OK");
\t\tend
\t\tvsync_time = 0;
\t\t//TVB, P_V_AREA, TVF
\t\twhile(inSYNC_V)begin
\t\t\t#(P_DOT_CYCLE);
\t\t\tvsync_time = vsync_time + 1;
\t\tend
\t\tif(vsync_time != (P_TVB+P_V_AREA+P_TVF)*(P_THP+P_THB+P_H_AREA+P_THF))begin
\t\t\t$display("[ERROR][display_model] : TVB or P_V_AREA or TVF Error. Correct%d, Fact%d", (P_TVB+P_V_AREA+P_TVF)*(P_THP+P_THB+P_H_AREA+P_THF), vsync_time);
\t\t\t$stop;
\t\tend
\t\telse begin
\t\t\t$display("[OK][display_model] : TVP, P_V_AREA, TVF OK");
\t\tend
\t\t$display("[OK][display_model] : Hsync Timing OK");
\t\tvsync_check_end = 1;
\tend
\tinteger fp;
\tinitial begin
\t\t#(P_DOT_CYCLE);
\t\t\t//File Dump Start
\t\twhile(!iFILE_DUMP)begin\t
\t\t\t#(P_DOT_CYCLE);
\t\tend
\t\t//H, V sync check wait
\t\twhile(!hsync_thp_check_end ||!hsync_other_check_end || !vsync_check_end)begin\t
\t\t\t#(P_DOT_CYCLE);
\t\tend
\t\t//File Open
\t\tfp = $fopen("dump_disp.bmp", "wb");
\t\tif(!fp)begin
\t\t\t$display("File open error");
\t\t\t$stop;
\t\tend
\t\t//Memory Reset
\t\tfor(i = 0; i < P_H_AREA*P_V_AREA; i = i + 1)begin : MEM_RESET
\t\t\tb_disp_r[i] = 8\'h0;
\t\t\tb_disp_g[i] = 8\'h0;
\t\t\tb_disp_b[i] = 8\'h0;
\t\tend
\t\ti = 0;
\t\t//Waif Vsync
\t\twhile(inSYNC_V || inSYNC_V == 1\'bx)begin
\t\t\t#(P_DOT_CYCLE);
\t\tend
\t\t#(P_DOT_CYCLE*(P_THP+P_THB+P_H_AREA+P_THF)*P_TVB);
\t\t//Get Data
\t\twhile(i < P_H_AREA*P_V_AREA)begin
\t\t\tj = 0;
\t\t\twhile(j < P_H_AREA)begin
\t\t\t\tb_disp_r[i] = iDISP_R;
\t\t\t\tb_disp_g[i] = iDISP_G;
\t\t\t\tb_disp_b[i] = iDISP_B;
\t\t\t\ti = i + 1;
\t\t\t\tj = j + 1;
\t\t\t\t#(P_DOT_CYCLE);
\t\t\tend
\t\t\t//Hsync Wait
\t\t\twhile(inSYNC_H)begin
\t\t\t\t#(P_DOT_CYCLE);
\t\t\tend
\t\t\twhile(!inSYNC_H)begin
\t\t\t\t#(P_DOT_CYCLE);
\t\t\tend
\t\t\t#(P_DOT_CYCLE*P_THB);
\t\tend
\t\t//File dump
\t\ttsk_write_bmp();
\t\t$fclose(fp);
\t\t$stop;
\tend
\t
\t
\t//File Header
\treg [15:0] bfType = "BM";
\treg [31:0] bfSize = 14+40+(P_V_AREA*P_H_AREA*4);\t//File Header + Info Header + PixcelData32bit
\treg [15:0] bfReserved1 = 0;
\treg [15:0] bfReserved2 = 0;
\treg [31:0] bfOffBits = 14+40;\t\t\t\t\t\t//File Header + Info Header
\t//Info Header
\treg [31:0] biSize = 40;
\treg [31:0] biWidth = P_H_AREA;
\treg [31:0] biHeight = P_V_AREA;
\treg [15:0] biPlanes = 1;
\treg [15:0] biBitCount = 32;
\treg [31:0] biCopmression = 0;
\treg [31:0] biSizeImage = 3780;
\treg [31:0] biXPixPerMeter = 3780;
\treg [31:0] biYPixPerMeter = 3780;
\treg [31:0] biClrUsed = 0;
\treg [31:0] biCirImportant = 0;
\t//ReserveData
\treg [7:0] bBitReserved = 0;
\t
\ttask tsk_write_bmp;
\t\tbegin
\t\t\t//Write File Header\t
\t\t\t$fwrite(fp, "%s", bfType);
\t\t\t$fwrite(fp, "%c", bfSize[7:0]);
\t\t\t$fwrite(fp, "%c", bfSize[15:8]);
\t\t\t$fwrite(fp, "%c", bfSize[23:16]);
\t\t\t$fwrite(fp, "%c", bfSize[31:24]);
\t\t\t$fwrite(fp, "%c", bfReserved1[7:0]);
\t\t\t$fwrite(fp, "%c", bfReserved1[15:8]);
\t\t\t$fwrite(fp, "%c", bfReserved2[7:0]);
\t\t\t$fwrite(fp, "%c", bfReserved2[15:8]);
\t\t\t$fwrite(fp, "%c", bfOffBits[7:0]);
\t\t\t$fwrite(fp, "%c", bfOffBits[15:8]);
\t\t\t$fwrite(fp, "%c", bfOffBits[23:16]);
\t\t\t$fwrite(fp, "%c", bfOffBits[31:24]);
\t\t\t//Write Info Header
\t\t\t$fwrite(fp, "%c", biSize[7:0]);
\t\t\t$fwrite(fp, "%c", biSize[15:8]);
\t\t\t$fwrite(fp, "%c", biSize[23:16]);
\t\t\t$fwrite(fp, "%c", biSize[31:24]);
\t\t\t$fwrite(fp, "%c", biWidth[7:0]);
\t\t\t$fwrite(fp, "%c", biWidth[15:8]);
\t\t\t$fwrite(fp, "%c", biWidth[23:16]);
\t\t\t$fwrite(fp, "%c", biWidth[31:24]);
\t\t\t$fwrite(fp, "%c", biHeight[7:0]);
\t\t\t$fwrite(fp, "%c", biHeight[15:8]);
\t\t\t$fwrite(fp, "%c", biHeight[23:16]);
\t\t\t$fwrite(fp, "%c", biHeight[31:24]);
\t\t\t$fwrite(fp, "%c", biPlanes[7:0]);
\t\t\t$fwrite(fp, "%c", biPlanes[15:8]);
\t\t\t$fwrite(fp, "%c", biBitCount[7:0]);
\t\t\t$fwrite(fp, "%c", biBitCount[15:8]);
\t\t\t$fwrite(fp, "%c", biCopmression[7:0]);
\t\t\t$fwrite(fp, "%c", biCopmression[15:8]);
\t\t\t$fwrite(fp, "%c", biCopmression[23:16]);
\t\t\t$fwrite(fp, "%c", biCopmression[31:24]);
\t\t\t$fwrite(fp, "%c", biSizeImage[7:0]);
\t\t\t$fwrite(fp, "%c", biSizeImage[15:8]);
\t\t\t$fwrite(fp, "%c", biSizeImage[23:16]);
\t\t\t$fwrite(fp, "%c", biSizeImage[31:24]);
\t\t\t$fwrite(fp, "%c", biXPixPerMeter[7:0]);
\t\t\t$fwrite(fp, "%c", biXPixPerMeter[15:8]);
\t\t\t$fwrite(fp, "%c", biXPixPerMeter[23:16]);
\t\t\t$fwrite(fp, "%c", biXPixPerMeter[31:24]);
\t\t\t$fwrite(fp, "%c", biYPixPerMeter[7:0]);
\t\t\t$fwrite(fp, "%c", biYPixPerMeter[15:8]);
\t\t\t$fwrite(fp, "%c", biYPixPerMeter[23:16]);
\t\t\t$fwrite(fp, "%c", biYPixPerMeter[31:24]);
\t\t\t$fwrite(fp, "%c", biClrUsed[7:0]);
\t\t\t$fwrite(fp, "%c", biClrUsed[15:8]);
\t\t\t$fwrite(fp, "%c", biClrUsed[23:16]);
\t\t\t$fwrite(fp, "%c", biClrUsed[31:24]);
\t\t\t$fwrite(fp, "%c", biCirImportant[7:0]);
\t\t\t$fwrite(fp, "%c", biCirImportant[15:8]);
\t\t\t$fwrite(fp, "%c", biCirImportant[23:16]);
\t\t\t$fwrite(fp, "%c", biCirImportant[31:24]);
\t\t\t//Write Pixcel Data
\t\t\tfor(i = (P_V_AREA*P_H_AREA)-1; i >= 0 ; i = i - 1)begin : F_DATA_OUT
\t\t\t\t$fwrite(fp, "%c%c%c%c", b_disp_b[i], b_disp_g[i], b_disp_r[i], bBitReserved);
\t\t\tend
\t\tend
\tendtask
\t
endmodule
`default_nettype wire
|
`default_nettype none
module gci_std_display_character #(
\t\t//Area
\t\tparameter P_AREA_H = 640,
\t\tparameter P_AREA_V = 480,
\t\tparameter P_AREAA_HV_N = 19,
\t\tparameter P_MEM_ADDR_N = 23
\t)(
\t\tinput wire iCLOCK,
\t\tinput wire inRESET,
\t\tinput wire iRESET_SYNC,
\t\t//Req
\t\tinput wire iIF_VALID,
\t\toutput wire oIF_BUSY,
\t\tinput wire [13:0] iIF_ADDR,\t//Charactor Addr
\t\tinput wire [31:0] iIF_DATA,
\t\t//Out
\t\toutput wire oIF_FINISH,
\t\toutput wire oIF_VALID,
\t\tinput wire iIF_BUSY,
\t\toutput wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
\t\toutput wire [23:0] oIF_DATA
\t);
\t
\t/********************************************
\tCharactor Output
\t********************************************/
\tlocalparam P_L_CHARACT_STT_IDLE = 2'h0;
\tlocalparam P_L_CHARACT_STT_OUT = 2'h1;
\tlocalparam P_L_CHARACT_STT_END = 2'h2;
\t
\treg [1:0] b_charact_state;
\treg [7:0] b_charact_font_color_r;
\treg [7:0] b_charact_font_color_g;
\treg [7:0] b_charact_font_color_b;
\treg [7:0] b_charact_back_color_r;
\treg [7:0] b_charact_back_color_g;
\treg [7:0] b_charact_back_color_b;
\treg [13:0] b_charact_base_addr;
\treg [6:0] b_charact_font;
\t
\treg [P_AREAA_HV_N-1:0] b_charact_counter;
\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_charact_state <= P_L_CHARACT_STT_IDLE;
\t\t\tb_charact_font_color_r <= 8'h0;
\t\t\tb_charact_font_color_g <= 8'h0;
\t\t\tb_charact_font_color_b <= 8'h0;
\t\t\tb_charact_back_color_r <= 8'h0;
\t\t\tb_charact_back_color_g <= 8'h0;
\t\t\tb_charact_back_color_b <= 8'h0;
\t\t\tb_charact_base_addr <= 14'h0;
\t\t\tb_charact_font <= 7'h0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_charact_state <= P_L_CHARACT_STT_IDLE;
\t\t\tb_charact_font_color_r <= 8'h0;
\t\t\tb_charact_font_color_g <= 8'h0;
\t\t\tb_charact_font_color_b <= 8'h0;
\t\t\tb_charact_back_color_r <= 8'h0;
\t\t\tb_charact_back_color_g <= 8'h0;
\t\t\tb_charact_back_color_b <= 8'h0;
\t\t\tb_charact_base_addr <= 14'h0;
\t\t\tb_charact_font <= 7'h0;
\t\tend
\t\telse begin
\t\t\tcase(b_charact_state)
\t\t\t\tP_L_CHARACT_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iIF_VALID)begin
\t\t\t\t\t\t\tb_charact_state <= P_L_CHARACT_STT_OUT;
\t\t\t\t\t\t\t{b_charact_font_color_r,
\t\t\t\t\t\t\tb_charact_font_color_g,
\t\t\t\t\t\t\tb_charact_font_color_b} <= {iIF_DATA[19:16], iIF_DATA[16], iIF_DATA[15:12], {2{iIF_DATA[12]}}, iIF_DATA[11:8], iIF_DATA[8]};//iBUSMOD_DATA[19:8];
\t\t\t\t\t\t\t{b_charact_back_color_r,
\t\t\t\t\t\t\tb_charact_back_color_g,
\t\t\t\t\t\t\tb_charact_back_color_b} <= {iIF_DATA[31:28], iIF_DATA[28], iIF_DATA[27:24], {2{iIF_DATA[24]}}, iIF_DATA[23:20], iIF_DATA[20]};//iBUSMOD_DATA[31:20];
\t\t\t\t\t\t\tb_charact_base_addr <= iIF_ADDR;
\t\t\t\t\t\t\tb_charact_font <= iIF_DATA[6:0];\t
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_CHARACT_STT_OUT:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(b_charact_counter == 7'd112)begin
\t\t\t\t\t\t\tb_charact_state <= P_L_CHARACT_STT_END;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_CHARACT_STT_END:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_charact_state <= P_L_CLEAR_STT_IDLE;
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_charact_state <= P_L_CLEAR_STT_IDLE;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_charact_counter <= 7'h0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_charact_counter <= 7'h0;
\t\tend
\t\telse begin
\t\t\tif(b_charact_state == P_L_CHARACT_STT_OUT)begin
\t\t\t\tif(!iIF_BUSY)begin
\t\t\t\t\tb_charact_counter <= b_charact_counter + 7'h1;
\t\t\t\tend
\t\t\tend
\t\t\telse begin
\t\t\t\tb_charact_counter <= 7'h0;
\t\t\tend
\t\tend
\tend
\t
\t//Font ROM
\twire [111:0] font_rom_data;
\tgci_std_display_font FONT14X8(
\t\t.iADDR(b_charact_font),
\t\t.oDATA(font_rom_data)
\t);
\t
\t
\tassign oIF_BUSY = b_charact_state != P_L_CHARACT_STT_IDLE;
\t
\tassign oIF_FINISH = b_charact_state == P_L_CHARACT_STT_END;
\tassign oIF_VALID = !iIF_BUSY && (b_clear_state == P_L_CLEAR_STT_CLEAR || b_charact_state == P_L_CHARACT_STT_OUT);
\tassign oIF_ADDR = charact_addr = b_charact_base_addr[13:8]*(640*14) + (b_charact_counter/8)*640 + b_charact_base_addr[7:0]*8 + b_charact_counter[2:0];;
\tassign oIF_DATA = ((font_rom_data[7'd111 - b_charact_counter + 7'h01])? (
\t\t\t{b_charact_font_color_r, b_charact_font_color_g, b_charact_font_color_b} :
\t\t\t{b_charact_back_color_r, b_charact_back_color_g, b_charact_back_color_b}
\t\t);
\t
endmodule
`default_nettype wire
|
`default_nettype none
module gci_std_display_vram_controller_ssram #(\t\t
\t\tparameter P_MEM_ADDR_N = 20,
\t\tparameter P_AREA_H = 640,
\t\tparameter P_AREA_V = 480,
\t\tparameter P_WRITE_FIFO_DEPTH = 64,
\t\tparameter P_WRITE_FIFO_DEPTH_N = 6,
\t\tparameter P_READ_SYNC_FIFO_DEPTH = 64,
\t\tparameter P_READ_SYNC_FIFO_DEPTH_N = 6,
\t\tparameter P_READ_ASYNC_FIFO_DEPTH = 16,
\t\tparameter P_READ_ASYNC_FIFO_DEPTH_N = 4
\t)(
\t\t//System
\t\tinput wire iGCI_CLOCK,
\t\tinput wire iDISP_CLOCK,
\t\tinput wire inRESET,
\t\tinput wire iRESET_SYNC,
\t\t//Write\t
\t\tinput wire iIF_WRITE_REQ,
\t\tinput wire [19:0] iIF_WRITE_ADDR,
\t\tinput wire [15:0] iIF_WRITE_DATA,
\t\toutput wire oIF_WRITE_FULL,
\t\t//Timing Sync
\t\tinput wire iDISP_REQ,
\t\tinput wire iDISP_SYNC,
\t\t//Output VGA Data
\t\t//output wire oDISP_DATA_VALID,
\t\t//output wire [15:0] oDISP_DATA,
\t\toutput [9:0] oDISP_DATA_R,
\t\toutput [9:0] oDISP_DATA_G,
\t\toutput [9:0] oDISP_DATA_B,
\t\t//SSRAM
\t\toutput wire oSSRAM_CLOCK,
\t\toutput wire onSSRAM_ADSC,
\t\toutput wire onSSRAM_ADSP,
\t\toutput wire onSSRAM_ADV,
\t\toutput wire onSSRAM_GW,
\t\toutput wire onSSRAM_OE,
\t\toutput wire onSSRAM_WE,
\t\toutput wire [3:0] onSSRAM_BE,
\t\toutput wire onSSRAM_CE1,
\t\toutput wire oSSRAM_CE2,
\t\toutput wire onSSRAM_CE3,
\t\toutput wire [18:0] oSSRAM_ADDR,
\t\tinout wire [31:0] ioSSRAM_DATA,
\t\tinout wire [3:0] ioSSRAM_PARITY
\t);
\t
\t//Main State
\tlocalparam P_L_MAIN_STT_IDLE = 2'h0;
\tlocalparam P_L_MAIN_STT_READ = 2'h1;
\tlocalparam P_L_MAIN_STT_WRITE = 2'h2;
\t//Read State
\tlocalparam P_L_READ_STT_IDLE = 2'h0;
\tlocalparam P_L_READ_STT_SET_ADDR = 2'h1;
\tlocalparam P_L_READ_STT_WAIT = 2'h2;
\tlocalparam P_L_READ_STT_GET_DATA = 2'h3;
\t//Write State
\tlocalparam P_L_WRITE_STT_IDLE = 2'h0;
\tlocalparam P_L_WRITE_STT_WRITE = 2'h1;
\tlocalparam P_L_WRITE_STT_STOP = 2'h2;
\t
\t/***************************************************
\tWire & Reg
\t***************************************************/
\t//Write FIFO
\twire [19:0] writefifo_addr;
\twire [15:0] writefifo_data;
\twire writefifo_empty;
\t//Main State
\treg [1:0] b_main_state;
\treg b_main_job_start;
\t//Read State
\treg [1:0] b_read_state;
\treg [18:0] b_read_addr;
\treg b_read_finish;
\t//Write State
\treg [1:0] b_write_state;
\treg b_write_finish;
\t//Vram Data-Receive
\treg b_get_data_valid;
\t//READ FIFO
\twire vramfifo0_almost_full;
\twire vramfifo0_empty;
\twire [31:0] vramfifo0_data;
\twire vramfifo1_full;
\t
\t
\t/***************************************************
\tCondition
\t***************************************************/
\twire vram_read_start_condition = b_main_job_start && (b_main_state == P_L_MAIN_STT_READ);
\twire vram_write_start_condition = b_main_job_start && (b_main_state == P_L_MAIN_STT_WRITE);
\twire vram_read_sequence_condition = (b_read_state == P_L_READ_STT_GET_DATA);
\twire vram_write_sequence_condition = (b_write_state == P_L_WRITE_STT_WRITE);
\t
\t/***************************************************
\tInput FIFO
\t***************************************************/
\tgci_std_sync_fifo #(36, P_WRITE_FIFO_DEPTH, P_WRITE_FIFO_DEPTH_N) VRAMWRITE_FIFO(
\t\t.inRESET(inRESET),
\t\t.iCLOCK(iGCI_CLOCK),
\t\t.iREMOVE(iRESET_SYNC),
\t\t.oCOUNT(),
\t\t.iWR_EN(iIF_WRITE_REQ),
\t\t.iWR_DATA({iIF_WRITE_ADDR, iIF_WRITE_DATA}),
\t\t.oWR_FULL(oIF_WRITE_FULL),
\t\t.iRD_EN(vram_write_sequence_condition),
\t\t.oRD_DATA({writefifo_addr, writefifo_data}),
\t\t.oRD_EMPTY(writefifo_empty),
\t\t.oRD_ALMOST_EMPTY()
\t);
\t
\t
\t/***************************************************
\tState
\t***************************************************/
\t//Main State
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin\t
\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\tb_main_job_start <= 1'b0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\tb_main_job_start <= 1'b0;
\t\tend
\t\telse begin
\t\t\tcase(b_main_state)
\t\t\t\tP_L_MAIN_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(vramfifo0_empty)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_READ;
\t\t\t\t\t\t\tb_main_job_start <= 1'b1;
\t\t\t\t\t\tend
\t\t\t\t\t\telse if(!writefifo_empty)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_WRITE;
\t\t\t\t\t\t\tb_main_job_start <= 1'b1;
\t\t\t\t\t\tend
\t\t\t\t\t\telse begin
\t\t\t\t\t\t\tb_main_job_start <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_READ:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_main_job_start <= 1'b0;
\t\t\t\t\t\tif(b_read_finish)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_WRITE:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_main_job_start <= 1'b0;
\t\t\t\t\t\tif(b_write_finish)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_main_job_start <= 1'b0;
\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\t\t\tend
\t\t\tendcase\t\t\t
\t\tend
\tend //main state
\t
\t
\t//Memory Read State
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_read_state <= P_L_READ_STT_IDLE;
\t\t\tb_read_addr <= 19'h0;
\t\t\tb_read_finish <= 1'b0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_read_state <= P_L_READ_STT_IDLE;
\t\t\tb_read_addr <= 19'h0;
\t\t\tb_read_finish <= 1'b0;
\t\tend
\t\telse begin
\t\t\tcase(b_read_state)
\t\t\t\tP_L_READ_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_read_finish <= 1'b0;
\t\t\t\t\t\tif(vram_read_start_condition)begin
\t\t\t\t\t\t\tb_read_state <= P_L_READ_STT_SET_ADDR;
\t\t\t\t\t\tend
\t\t\t\t\tend\t\t
\t\t\t\tP_L_READ_STT_SET_ADDR:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_read_state <= P_L_READ_STT_WAIT;
\t\t\t\t\t\tb_read_addr <= func_read_next_addr(b_read_addr);
\t\t\t\t\tend
\t\t\t\tP_L_READ_STT_WAIT:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_read_state <= P_L_READ_STT_GET_DATA;
\t\t\t\t\t\tb_read_addr <= func_read_next_addr(b_read_addr);
\t\t\t\t\tend
\t\t\t\tP_L_READ_STT_GET_DATA:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(vramfifo0_almost_full)begin
\t\t\t\t\t\t\tb_read_state <= P_L_READ_STT_IDLE;
\t\t\t\t\t\t\tb_read_addr <= func_read_2prev_addr(b_read_addr);// - 19'h1;
\t\t\t\t\t\t\tb_read_finish <= 1'b1;
\t\t\t\t\t\tend
\t\t\t\t\t\telse begin
\t\t\t\t\t\t\tb_read_addr <= func_read_next_addr(b_read_addr);//b_read_addr + 19'h1;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend //Read State
\t
\tfunction [P_MEM_ADDR_N-1:0] func_read_next_addr;
\t\tinput [P_MEM_ADDR_N-1:0] func_now_addr;
\t\tbegin
\t\t\tif(func_now_addr < ((P_AREA_H*P_AREA_V)/2)-1)begin
\t\t\t\tfunc_read_next_addr = func_now_addr + 1;
\t\t\tend
\t\t\telse begin
\t\t\t\tfunc_read_next_addr = {P_MEM_ADDR_N{1'b0}};
\t\t\tend
\t\tend
\tendfunction
\t
\tfunction [P_MEM_ADDR_N-1:0] func_read_2prev_addr;
\t\tinput [P_MEM_ADDR_N-1:0] func_now_addr;
\t\tbegin
\t\t\tif(func_now_addr == {P_MEM_ADDR_N{1'b0}})begin
\t\t\t\tfunc_read_2prev_addr = ((P_AREA_H*P_AREA_V)/2)-2;
\t\t\tend
\t\t\telse if(func_now_addr == {{P_MEM_ADDR_N-1{1'b0}}, 1'b1})begin\t
\t\t\t\tfunc_read_2prev_addr = ((P_AREA_H*P_AREA_V)/2)-1;
\t\t\tend
\t\t\telse begin
\t\t\t\tfunc_read_2prev_addr = func_now_addr - 2;
\t\t\tend
\t\tend
\tendfunction
\t
\t
\t//Memory Write State
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_write_state <= P_L_WRITE_STT_IDLE;
\t\t\tb_write_finish <= 1'b0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_write_state <= P_L_WRITE_STT_IDLE;
\t\t\tb_write_finish <= 1'b0;
\t\tend
\t\telse begin
\t\t\tcase(b_write_state)
\t\t\t\tP_L_WRITE_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_write_finish <= 1'b0;
\t\t\t\t\t\tif(vram_write_start_condition)begin
\t\t\t\t\t\t\tb_write_state <= P_L_WRITE_STT_WRITE;
\t\t\t\t\t\tend
\t\t\t\t\tend\t\t
\t\t\t\tP_L_WRITE_STT_WRITE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(writefifo_empty || vramfifo0_empty)begin
\t\t\t\t\t\t\tb_write_state <= P_L_WRITE_STT_STOP;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_WRITE_STT_STOP:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_write_state <= P_L_WRITE_STT_IDLE;
\t\t\t\t\t\tb_write_finish <= 1'b1;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend //Read State
\t
\t/***************************************************
\tVRAM Data Receive
\t***************************************************/
\treg b_get_data_tmp;
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_get_data_valid <= 1'b0;
\t\t\tb_get_data_tmp <= 1'b0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_get_data_valid <= 1'b0;
\t\t\tb_get_data_tmp <= 1'b0;
\t\tend
\t\telse begin
\t\t\tb_get_data_tmp <= vram_read_sequence_condition;
\t\t\tb_get_data_valid <= vram_read_sequence_condition;//b_get_data_tmp;
\t\tend
\tend
\t
\t/***************************************************
\tOutput FIFO
\t***************************************************/
\twire [31:0] vramfifo1_data;
\twire vramfifo0_full;
\twire vramfifo1_empty;
\tgci_std_sync_fifo #(32, P_READ_SYNC_FIFO_DEPTH, P_READ_SYNC_FIFO_DEPTH_N) VRAMREAD_FIFO0(
\t\t.inRESET(inRESET),
\t\t.iREMOVE(iRESET_SYNC),
\t\t.iCLOCK(iGCI_CLOCK),
\t\t.iWR_EN(b_get_data_valid && !vramfifo0_full),
\t\t.iWR_DATA(ioSSRAM_DATA),
\t\t.oWR_FULL(vramfifo0_full),
\t\t.oWR_ALMOST_FULL(vramfifo0_almost_full),
\t\t.iRD_EN(!vramfifo0_empty && !vramfifo1_full),
\t\t.oRD_DATA(vramfifo0_data),
\t\t.oRD_EMPTY(vramfifo0_empty)
\t);
\tgci_std_async_fifo #(32, P_READ_ASYNC_FIFO_DEPTH, P_READ_ASYNC_FIFO_DEPTH_N) VRAMREAD_FIFO1(
\t\t.inRESET(inRESET),
\t\t.iREMOVE(iRESET_SYNC),
\t\t.iWR_CLOCK(iGCI_CLOCK),
\t\t.iWR_EN(!vramfifo0_empty && !vramfifo1_full),
\t\t.iWR_DATA(vramfifo0_data),
\t\t.oWR_FULL(vramfifo1_full),
\t\t.iRD_CLOCK(iDISP_CLOCK),
\t\t.iRD_EN(!vramfifo1_empty && b_dispout_state == P_L_DISPOUT_STT_1ST),
\t\t.oRD_DATA(vramfifo1_data),
\t\t.oRD_EMPTY(vramfifo1_empty)
\t);
\t
\t
\tparameter P_L_DISPOUT_STT_1ST = 1'b0;
\tparameter P_L_DISPOUT_STT_2RD = 1'b1;
\t
\treg b_dispout_state;
\treg [15:0] b_dispout_current_data;
\treg [15:0] b_dispout_next_data;
\t
\talways@(posedge iDISP_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_dispout_state <= P_L_DISPOUT_STT_1ST;
\t\t\tb_dispout_current_data <= 16'h0;
\t\t\tb_dispout_next_data <= 16'h0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_dispout_state <= P_L_DISPOUT_STT_1ST;
\t\t\tb_dispout_current_data <= 16'h0;
\t\t\tb_dispout_next_data <= 16'h0;
\t\tend
\t\telse begin
\t\t\tcase(b_dispout_state)
\t\t\t\tP_L_DISPOUT_STT_1ST:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(!vramfifo1_empty)begin
\t\t\t\t\t\t\t{b_dispout_next_data, b_dispout_current_data} <= vramfifo1_data;
\t\t\t\t\t\t\tb_dispout_state <= P_L_DISPOUT_STT_2RD;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_DISPOUT_STT_2RD:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iDISP_REQ)begin
\t\t\t\t\t\t\tb_dispout_current_data <= b_dispout_next_data;
\t\t\t\t\t\t\tb_dispout_state <= P_L_DISPOUT_STT_1ST;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\t
\t/***************************************************
\tMemory Port Buffer
\t***************************************************/\t\t
\treg bn_ram_buff_adsc;
\treg bn_ram_buff_adsp;
\treg bn_ram_buff_adv;
\treg bn_ram_buff_gw;
\treg bn_ram_buff_oe;
\treg bn_ram_buff_we;
\treg [3:0] bn_ram_buff_be;
\t//reg bn_ram_buff_ce1;
\t//reg b_ram_buff_ce2;
\treg bn_ram_buff_ce3;
\treg [18:0] b_ram_buff_addr;
\treg [31:0] b_ram_buff_data;
\treg [3:0] b_ram_buff_parity;
\treg b_ram_buff_rw;
\t
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tbn_ram_buff_adsc <= 1'b0;
\t\t\tbn_ram_buff_adsp <= 1'b0;
\t\t\tbn_ram_buff_adv <= 1'b0;
\t\t\tbn_ram_buff_gw <= 1'b0;
\t\t\tbn_ram_buff_oe <= 1'b0;
\t\t\tbn_ram_buff_we <= 1'b0;
\t\t\tbn_ram_buff_be <= {4{1'b0}};
\t\t\t//bn_ram_buff_ce1 <= 1'b0;
\t\t\t//b_ram_buff_ce2 <= 1'b0;
\t\t\tbn_ram_buff_ce3 <= 1'b0;
\t\t\tb_ram_buff_addr <= {19{1'b0}};
\t\t\tb_ram_buff_data <= {32{1'b0}};
\t\t\tb_ram_buff_parity <= {4{1'b0}};
\t\t\tb_ram_buff_rw <= 1'b0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tbn_ram_buff_adsc <= 1'b0;
\t\t\tbn_ram_buff_adsp <= 1'b0;
\t\t\tbn_ram_buff_adv <= 1'b0;
\t\t\tbn_ram_buff_gw <= 1'b0;
\t\t\tbn_ram_buff_oe <= 1'b0;
\t\t\tbn_ram_buff_we <= 1'b0;
\t\t\tbn_ram_buff_be <= {4{1'b0}};
\t\t\t//bn_ram_buff_ce1 <= 1'b0;
\t\t\t//b_ram_buff_ce2 <= 1'b0;
\t\t\tbn_ram_buff_ce3 <= 1'b0;
\t\t\tb_ram_buff_addr <= {19{1'b0}};
\t\t\tb_ram_buff_data <= {32{1'b0}};
\t\t\tb_ram_buff_parity <= {4{1'b0}};
\t\t\tb_ram_buff_rw <= 1'b0;
\t\tend
\t\telse begin
\t\t\tif(vram_write_sequence_condition)begin
\t\t\t\tcase(b_write_state)
\t\t\t\t\tP_L_WRITE_STT_IDLE:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tbn_ram_buff_adsc <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_adsp <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_adv <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_gw <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_oe <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_we <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_be <= {4{1'b0}};
\t\t\t\t\t\t\t//bn_ram_buff_ce1 <= 1'b0;
\t\t\t\t\t\t\t//b_ram_buff_ce2 <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_ce3 <= 1'b0;
\t\t\t\t\t\t\tb_ram_buff_addr <= {19{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_data <= {32{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_parity <= {4{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_rw <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\tP_L_WRITE_STT_WRITE:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tbn_ram_buff_adsc <= 1'b1;
\t\t\t\t\t\t\tbn_ram_buff_adsp <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_adv <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_gw <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_oe <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_we <= 1'b1;
\t\t\t\t\t\t\tbn_ram_buff_be <= (!writefifo_addr[0])? 4'b0011 : 4'b1100;
\t\t\t\t\t\t\t//bn_ram_buff_ce1 <= 1'b0;
\t\t\t\t\t\t\t//b_ram_buff_ce2 <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_ce3 <= 1'b1;
\t\t\t\t\t\t\tb_ram_buff_addr <= writefifo_addr[19:1];
\t\t\t\t\t\t\tb_ram_buff_data <= {writefifo_data, writefifo_data};
\t\t\t\t\t\t\tb_ram_buff_parity <= {4{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_rw <= 1'b1;
\t\t\t\t\t\tend
\t\t\t\t\tP_L_WRITE_STT_STOP:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tbn_ram_buff_adsc <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_adsp <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_adv <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_gw <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_oe <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_we <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_be <= {4{1'b0}};
\t\t\t\t\t\t\t//bn_ram_buff_ce1 <= 1'b0;
\t\t\t\t\t\t\t//b_ram_buff_ce2 <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_ce3 <= 1'b1;
\t\t\t\t\t\t\tb_ram_buff_addr <= {19{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_data <= {32{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_parity <= {4{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_rw <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\tendcase
\t\t\tend
\t\t\telse if(b_main_state == P_L_MAIN_STT_READ)begin\t
\t\t\t\tcase(b_read_state)
\t\t\t\t\tP_L_READ_STT_IDLE:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tbn_ram_buff_adsc <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_adsp <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_adv <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_gw <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_oe <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_we <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_be <= {4{1'b0}};
\t\t\t\t\t\t\t//bn_ram_buff_ce1 <= 1'b0;
\t\t\t\t\t\t\t//b_ram_buff_ce2 <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_ce3 <= 1'b0;
\t\t\t\t\t\t\tb_ram_buff_addr <= {19{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_data <= {32{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_parity <= {4{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_rw <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\tP_L_READ_STT_SET_ADDR:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tbn_ram_buff_adsc <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_adsp <= 1'b1;
\t\t\t\t\t\t\tbn_ram_buff_adv <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_gw <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_oe <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_we <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_be <= {4{1'b0}};
\t\t\t\t\t\t\t//bn_ram_buff_ce1 <= 1'b0;
\t\t\t\t\t\t\t//b_ram_buff_ce2 <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_ce3 <= 1'b1;
\t\t\t\t\t\t\tb_ram_buff_addr <= b_read_addr;
\t\t\t\t\t\t\tb_ram_buff_data <= {32{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_parity <= {4{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_rw <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\tP_L_READ_STT_WAIT:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tbn_ram_buff_adsc <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_adsp <= 1'b1;
\t\t\t\t\t\t\tbn_ram_buff_adv <= 1'b1;
\t\t\t\t\t\t\tbn_ram_buff_gw <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_oe <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_we <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_be <= {4{1'b0}};
\t\t\t\t\t\t\t//bn_ram_buff_ce1 <= 1'b0;
\t\t\t\t\t\t\t//b_ram_buff_ce2 <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_ce3 <= 1'b1;
\t\t\t\t\t\t\tb_ram_buff_addr <= b_read_addr;
\t\t\t\t\t\t\tb_ram_buff_data <= {32{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_parity <= {4{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_rw <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\tP_L_READ_STT_GET_DATA:
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tbn_ram_buff_adsc <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_adsp <= 1'b1;
\t\t\t\t\t\t\tbn_ram_buff_adv <= 1'b1;
\t\t\t\t\t\t\tbn_ram_buff_gw <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_oe <= 1'b1;
\t\t\t\t\t\t\tbn_ram_buff_we <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_be <= {4{1'b0}};
\t\t\t\t\t\t\t//bn_ram_buff_ce1 <= 1'b0;
\t\t\t\t\t\t\t//b_ram_buff_ce2 <= 1'b0;
\t\t\t\t\t\t\tbn_ram_buff_ce3 <= 1'b1;
\t\t\t\t\t\t\tb_ram_buff_addr <= b_read_addr;//{19{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_data <= {32{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_parity <= {4{1'b0}};
\t\t\t\t\t\t\tb_ram_buff_rw <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\tendcase
\t\t\tend
\t\t\telse begin
\t\t\t\tbn_ram_buff_adsc <= 1'b0;
\t\t\t\tbn_ram_buff_adsp <= 1'b0;
\t\t\t\tbn_ram_buff_adv <= 1'b0;
\t\t\t\tbn_ram_buff_gw <= 1'b0;
\t\t\t\tbn_ram_buff_oe <= 1'b0;
\t\t\t\tbn_ram_buff_we <= 1'b0;
\t\t\t\tbn_ram_buff_be <= {4{1'b0}};
\t\t\t\t//bn_ram_buff_ce1 <= 1'b0;
\t\t\t\t//b_ram_buff_ce2 <= 1'b0;
\t\t\t\tbn_ram_buff_ce3 <= 1'b0;
\t\t\t\tb_ram_buff_addr <= {19{1'b0}};
\t\t\t\tb_ram_buff_data <= {32{1'b0}};
\t\t\t\tb_ram_buff_parity <= {4{1'b0}};
\t\t\t\tb_ram_buff_rw <= 1'b0;
\t\t\tend
\t\tend
\tend
\t
\t/***************************************************
\tAssign
\t***************************************************/
\tassign oSSRAM_CLOCK = iGCI_CLOCK;
\tassign onSSRAM_ADSC = !bn_ram_buff_adsc;
\tassign onSSRAM_ADSP = !bn_ram_buff_adsp;
\tassign onSSRAM_ADV = !bn_ram_buff_adv;
\tassign onSSRAM_GW = !bn_ram_buff_gw;
\tassign onSSRAM_OE = !bn_ram_buff_oe;
\tassign onSSRAM_WE = !bn_ram_buff_we;
\tassign onSSRAM_BE = ~bn_ram_buff_be;
\tassign onSSRAM_CE1 = 1'b0; //bn_ram_buff_ce1;
\tassign oSSRAM_CE2 = 1'b1; //b_ram_buff_ce2;
\tassign onSSRAM_CE3 = !bn_ram_buff_ce3;
\tassign oSSRAM_ADDR = b_ram_buff_addr;
\tassign ioSSRAM_DATA = (b_ram_buff_rw)? b_ram_buff_data : {32{1'bz}};
\tassign ioSSRAM_PARITY = (b_ram_buff_rw)? b_ram_buff_parity : {4{1'bz}};
\t
\t//assign oDISP_DATA_VALID = iDISP_REQ;
\t//assign oDISP_DATA = b_dispout_current_data;
\t/*
\tassign oDISP_DATA_R = {b_dispout_current_data[15:11], {5{b_dispout_current_data[11]}}};
\tassign oDISP_DATA_G = {b_dispout_current_data[10:5], {4{b_dispout_current_data[5]}}};
\tassign oDISP_DATA_B = {b_dispout_current_data[4:0], {5{b_dispout_current_data[0]}}};
\t*/
\tassign oDISP_DATA_B = {b_dispout_current_data[15:11], {5{b_dispout_current_data[11]}}};
\tassign oDISP_DATA_G = {b_dispout_current_data[10:5], {4{b_dispout_current_data[5]}}};
\tassign oDISP_DATA_R = {b_dispout_current_data[4:0], {5{b_dispout_current_data[0]}}};
\t
\t
endmodule
`default_nettype wire
|
`timescale 1ns/ 10ps
`default_nettype none
module tb_gci_std_display;
\tparameter SYS_CYCLE = 20;\t//50MHz
\tparameter DISP_CYCLE = 40;\t//525MHz
\treg iCLOCK;
\treg inRESET;
\t//BUS(DATA)-Input
\treg iDEV_REQ;\t\t
\twire oDEV_BUSY;
\treg iDEV_RW;
\treg [31:0] iDEV_ADDR;
\treg [31:0] iDEV_DATA;
\t//BUS(DATA)-Output
\twire oDEV_REQ;\t\t
\treg iDEV_BUSY;
\twire [31:0] oDEV_DATA;
\t//IRQ
\twire oDEV_IRQ_REQ;\t\t
\treg iDEV_IRQ_BUSY;
\twire [23:0] oDEV_IRQ_DATA; \t
\treg iDEV_IRQ_ACK;
\t//Display Clock
\treg iVGA_CLOCK;
\t`ifdef GCI_STD_DISPLAY_SRAM
\t\t//SRAM
\t\twire onSRAM_CE;
\t\twire onSRAM_WE;
\t\twire onSRAM_OE;
\t\twire onSRAM_UB;
\t\twire onSRAM_LB;
\t\twire [19:0] oSRAM_ADDR;
\t\twire [15:0] ioSRAM_DATA;
\t`elsif GCI_STD_DISPLAY_SSRAM
\t\t//SSRAM
\t\twire oSSRAM_CLOCK;
\t\twire onSSRAM_ADSC;
\t\twire onSSRAM_ADSP;
\t\twire onSSRAM_ADC;
\t\twire onSSRAM_GW;
\t\twire onSSRAM_OE;
\t\twire onSSRAM_WE;
\t\twire [3:0] onSSRAM_BE;
\t\twire onSSRAM_CE1;
\t\twire oSSRAM_CE2;
\t\twire onSSRAM_CE3;
\t\twire [18:0] oSSRAM_ADDR;
\t\twire [31:0] ioSSRAM_DATA;
\t\twire [3:0] ioSSRAM_PARITY;
\t`endif
\t//Display
\twire oDISP_CLOCK;
\twire onDISP_RESET;
\twire oDISP_ENA;
\twire oDISP_BLANK;
\twire onDISP_HSYNC;
\twire onDISP_VSYNC;
\twire [9:0] oDISP_DATA_R;
\twire [9:0] oDISP_DATA_G;
\twire [9:0] oDISP_DATA_B;
\t
\t/********************************
\tModel
\t********************************/
\t//VGA
\treg display_model_file_dump;
\tinitial display_model_file_dump = 0;
\tdisplay_model VGA_MODEL(
\t\t.iFILE_DUMP(display_model_file_dump),
\t\t.inSYNC_H(onDISP_HSYNC),
\t\t.inSYNC_V(onDISP_VSYNC),
\t\t.iDISP_R(oDISP_DATA_R),
\t\t.iDISP_G(oDISP_DATA_G),
\t\t.iDISP_B(oDISP_DATA_B)
\t);
\t
\t//Memory
\t`ifdef GCI_STD_DISPLAY_SRAM
\t\t//SRAM
\t\tis61wv102416bll #(10) SRAM_MODEL(
\t\t\t.A(oSRAM_ADDR),
\t\t\t.IO(ioSRAM_DATA),
\t\t\t.CE_(onSRAM_CE),
\t\t\t.OE_(onSRAM_OE),
\t\t\t.WE_(onSRAM_WE),
\t\t\t.LB_(onSRAM_LB),
\t\t\t.UB_(onSRAM_UB)
\t\t);
\t`elsif GCI_STD_DISPLAY_SSRAM
\t\t//SSRAM
\t\tCY7C1380_PLSCD SSRAM_MODEL(
\t\t\t.ZZ(1\'b0),
\t\t\t.Mode(1\'b0),\t//Lenear Burst
\t\t\t.ADDR(oSSRAM_ADDR),
\t\t\t.GW_N(onSSRAM_GW),
\t\t\t.BWE_N(onSSRAM_WE),
\t\t\t.BWd_N(onSSRAM_BE[3]),
\t\t\t.BWc_N(onSSRAM_BE[2]),
\t\t\t.BWb_N(onSSRAM_BE[1]),
\t\t\t.BWa_N(onSSRAM_BE[0]),
\t\t\t.CE1_N(onSSRAM_CE1),
\t\t\t.CE2(oSSRAM_CE2),
\t\t\t.CE3_N(onSSRAM_CE3),
\t\t\t.ADSP_N(onSSRAM_ADSP),
\t\t\t.ADSC_N(onSSRAM_ADSC),
\t\t\t.ADV_N(onSSRAM_ADC),
\t\t\t.OE_N(onSSRAM_OE),
\t\t\t.DQ({ioSSRAM_PARITY[3], ioSSRAM_DATA[31:24], ioSSRAM_PARITY[2], ioSSRAM_DATA[23:16], ioSSRAM_PARITY[1], ioSSRAM_DATA[15:8], ioSSRAM_PARITY[0], ioSSRAM_DATA[7:0]}),
\t\t\t.CLK(oSSRAM_CLOCK)
\t\t);
\t`endif
\t
\t
\tinteger i = 0;
\t
\t//Port Initial
\tinitial begin\t
\t\t#(SYS_CYCLE/2)begin\t
\t\t\tiCLOCK = 1\'b1;
\t\t\tinRESET = 1\'b0;
\t\t\tiDEV_REQ = 1\'b0;
\t\t\tiDEV_RW = 1\'b0;
\t\t\tiDEV_ADDR = 32\'h0;
\t\t\tiDEV_DATA = 32\'h0;
\t\t\tiDEV_BUSY = 1\'b0;
\t\t\tiDEV_IRQ_BUSY = 1\'b0;
\t\t\tiDEV_IRQ_ACK = 1\'b0;
\t\t\tiVGA_CLOCK = 1\'b0;\t\t
\t\tend
\t\t#(SYS_CYCLE) begin\t
\t\t\tinRESET = 1\'b1;\t
\t\t\t#SYS_CYCLE;
\t\t\tinRESET = 1\'b0;
\t\t\t#SYS_CYCLE;
\t\t\tinRESET = 1\'b1;
\t\tend
\tend
\t
\t/**************************************
\tTest Vector
\t**************************************/
\t
\treg [7:0] b_disp_b[0:(640*480)-1];
\treg [7:0] b_disp_g[0:(640*480)-1];
\treg [7:0] b_disp_r[0:(640*480)-1];
\t
\tfunction [7:0] f_test_r;
\t\tinput [15:0] data;
\t\tbegin
\t\t\tf_test_r = {data[4:0], {3{data[0]}}};
\t\tend
\tendfunction
\t
\tfunction [7:0] f_test_g;
\t\tinput [15:0] data;
\t\tbegin
\t\t\tf_test_g = {data[10:5], {2{data[5]}}};
\t\tend
\tendfunction
\t
\t
\tfunction [7:0] f_test_b;
\t\tinput [15:0] data;
\t\tbegin
\t\t\tf_test_b = {data[15:11], {3{data[11]}}};
\t\tend
\tendfunction
\t
\tfunction [7:0] func_mask;
\t\tinput [8:0] data;
\t\tbegin
\t\t\tfunc_mask = data[7:0];
\t\tend
\tendfunction
\t
\t
\tinteger fp;
\tinteger l;
\tinitial begin
\t\t#(500);
\t\t\t//File Dump Start
\t\twhile(!vram_writend_flag)begin\t
\t\t\t#(200);
\t\tend
\t\t
\t\tfor(l = 0; l < 640*480; l = l + 1)begin
\t\t\tif(!l[0])begin
\t\t\t\tb_disp_r[l] = f_test_r({func_mask(SSRAM_MODEL.bank1[l>>1]), func_mask(SSRAM_MODEL.bank0[l>>1])});
\t\t\t\tb_disp_g[l] = f_test_g({func_mask(SSRAM_MODEL.bank1[l>>1]), func_mask(SSRAM_MODEL.bank0[l>>1])});
\t\t\t\tb_disp_b[l] = f_test_b({func_mask(SSRAM_MODEL.bank1[l>>1]), func_mask(SSRAM_MODEL.bank0[l>>1])});
\t\t\tend
\t\t\telse begin\t
\t\t\t\tb_disp_r[l] = f_test_r({func_mask(SSRAM_MODEL.bank3[l>>1]), func_mask(SSRAM_MODEL.bank2[l>>1])});
\t\t\t\tb_disp_g[l] = f_test_g({func_mask(SSRAM_MODEL.bank3[l>>1]), func_mask(SSRAM_MODEL.bank2[l>>1])});
\t\t\t\tb_disp_b[l] = f_test_b({func_mask(SSRAM_MODEL.bank3[l>>1]), func_mask(SSRAM_MODEL.bank2[l>>1])});
\t\t\tend
\t\tend
\t\t
\t\t
\t\t
\t\t//File Open
\t\tfp = $fopen("dump_disp_memory.bmp", "wb");
\t\tif(!fp)begin
\t\t\t$display("File open error");
\t\t\t$stop;
\t\tend
\t\t//File dump
\t\ttsk_write_bmp();
\t\t$fclose(fp);
\t\t$stop;
\t\t
\tend
\t
\t
\t//File Header
\treg [15:0] bfType = "BM";
\treg [31:0] bfSize = 14+40+(640*480*4);\t//File Header + Info Header + PixcelData32bit
\treg [15:0] bfReserved1 = 0;
\treg [15:0] bfReserved2 = 0;
\treg [31:0] bfOffBits = 14+40;\t\t\t\t\t\t//File Header + Info Header
\t//Info Header
\treg [31:0] biSize = 40;
\treg [31:0] biWidth = 640;
\treg [31:0] biHeight = 480;
\treg [15:0] biPlanes = 1;
\treg [15:0] biBitCount = 32;
\treg [31:0] biCopmression = 0;
\treg [31:0] biSizeImage = 3780;
\treg [31:0] biXPixPerMeter = 3780;
\treg [31:0] biYPixPerMeter = 3780;
\treg [31:0] biClrUsed = 0;
\treg [31:0] biCirImportant = 0;
\t//ReserveData
\treg [7:0] bBitReserved = 0;
\t
\ttask tsk_write_bmp;
\t\tbegin
\t\t\t//Write File Header\t
\t\t\t$fwrite(fp, "%s", bfType);
\t\t\t$fwrite(fp, "%c", bfSize[7:0]);
\t\t\t$fwrite(fp, "%c", bfSize[15:8]);
\t\t\t$fwrite(fp, "%c", bfSize[23:16]);
\t\t\t$fwrite(fp, "%c", bfSize[31:24]);
\t\t\t$fwrite(fp, "%c", bfReserved1[7:0]);
\t\t\t$fwrite(fp, "%c", bfReserved1[15:8]);
\t\t\t$fwrite(fp, "%c", bfReserved2[7:0]);
\t\t\t$fwrite(fp, "%c", bfReserved2[15:8]);
\t\t\t$fwrite(fp, "%c", bfOffBits[7:0]);
\t\t\t$fwrite(fp, "%c", bfOffBits[15:8]);
\t\t\t$fwrite(fp, "%c", bfOffBits[23:16]);
\t\t\t$fwrite(fp, "%c", bfOffBits[31:24]);
\t\t\t//Write Info Header
\t\t\t$fwrite(fp, "%c", biSize[7:0]);
\t\t\t$fwrite(fp, "%c", biSize[15:8]);
\t\t\t$fwrite(fp, "%c", biSize[23:16]);
\t\t\t$fwrite(fp, "%c", biSize[31:24]);
\t\t\t$fwrite(fp, "%c", biWidth[7:0]);
\t\t\t$fwrite(fp, "%c", biWidth[15:8]);
\t\t\t$fwrite(fp, "%c", biWidth[23:16]);
\t\t\t$fwrite(fp, "%c", biWidth[31:24]);
\t\t\t$fwrite(fp, "%c", biHeight[7:0]);
\t\t\t$fwrite(fp, "%c", biHeight[15:8]);
\t\t\t$fwrite(fp, "%c", biHeight[23:16]);
\t\t\t$fwrite(fp, "%c", biHeight[31:24]);
\t\t\t$fwrite(fp, "%c", biPlanes[7:0]);
\t\t\t$fwrite(fp, "%c", biPlanes[15:8]);
\t\t\t$fwrite(fp, "%c", biBitCount[7:0]);
\t\t\t$fwrite(fp, "%c", biBitCount[15:8]);
\t\t\t$fwrite(fp, "%c", biCopmression[7:0]);
\t\t\t$fwrite(fp, "%c", biCopmression[15:8]);
\t\t\t$fwrite(fp, "%c", biCopmression[23:16]);
\t\t\t$fwrite(fp, "%c", biCopmression[31:24]);
\t\t\t$fwrite(fp, "%c", biSizeImage[7:0]);
\t\t\t$fwrite(fp, "%c", biSizeImage[15:8]);
\t\t\t$fwrite(fp, "%c", biSizeImage[23:16]);
\t\t\t$fwrite(fp, "%c", biSizeImage[31:24]);
\t\t\t$fwrite(fp, "%c", biXPixPerMeter[7:0]);
\t\t\t$fwrite(fp, "%c", biXPixPerMeter[15:8]);
\t\t\t$fwrite(fp, "%c", biXPixPerMeter[23:16]);
\t\t\t$fwrite(fp, "%c", biXPixPerMeter[31:24]);
\t\t\t$fwrite(fp, "%c", biYPixPerMeter[7:0]);
\t\t\t$fwrite(fp, "%c", biYPixPerMeter[15:8]);
\t\t\t$fwrite(fp, "%c", biYPixPerMeter[23:16]);
\t\t\t$fwrite(fp, "%c", biYPixPerMeter[31:24]);
\t\t\t$fwrite(fp, "%c", biClrUsed[7:0]);
\t\t\t$fwrite(fp, "%c", biClrUsed[15:8]);
\t\t\t$fwrite(fp, "%c", biClrUsed[23:16]);
\t\t\t$fwrite(fp, "%c", biClrUsed[31:24]);
\t\t\t$fwrite(fp, "%c", biCirImportant[7:0]);
\t\t\t$fwrite(fp, "%c", biCirImportant[15:8]);
\t\t\t$fwrite(fp, "%c", biCirImportant[23:16]);
\t\t\t$fwrite(fp, "%c", biCirImportant[31:24]);
\t\t\t//Write Pixcel Data
\t\t\tfor(i = (640*480)-1; i >= 0 ; i = i - 1)begin : F_DATA_OUT
\t\t\t\t$fwrite(fp, "%c%c%c%c", b_disp_b[i], b_disp_g[i], b_disp_r[i], bBitReserved);
\t\t\tend
\t\tend
\tendtask
\t
\t
\t
\t
\t
\t
\t
\t
\t
\t
\t
\t//VRAM Write
\treg vram_writend_flag;
\tinitial begin
\t\t#0 begin
\t\t\tvram_writend_flag = 0;
\t\tend
\t\t#(SYS_CYCLE/2)
\t\t//Write VRAM
\t\t#(SYS_CYCLE*20)begin
\t\t\tfor(i = 0; i < 640*480; i = i+1)begin
\t\t\t\ttsk_write_data(32\'hc400 + i*4, func_patgen(i%640, i/640));
\t\t\tend
\t\t\tvram_writend_flag = 1;
\t\t\t$display("VRAM Write END");
\t\t\tdisplay_model_file_dump = 1;
\t\tend
\t\t
\tend
\t
\ttask tsk_write_data;
\t\tinput [31:0] addr;
\t\tinput [31:0] data;
\t\tbegin\t
\t\t\tiDEV_REQ = 1\'b1;
\t\t\tiDEV_RW = 1\'b1;
\t\t\tiDEV_ADDR = addr;
\t\t\tiDEV_DATA = data;
\t\t\t#(SYS_CYCLE);
\t\t\twhile(oDEV_BUSY)begin\t
\t\t\t\t#(SYS_CYCLE);
\t\t\tend
\t\t\tiDEV_REQ = 1\'b0;
\t\t\t#(SYS_CYCLE);
\t\tend
\tendtask
\t
\t
\t
\t
\tfunction [15:0] func_patgen;
\t\tinput [9:0] func_h_addr;
\t\tinput [8:0] func_v_addr;
\t\treg [2:0] pri_h_case;
\t\treg [1:0] pri_v_case;
\t\treg [2:0] pri_puttern_case;
\t\tbegin
\t\t\t//h
\t\t\tif(func_h_addr[9:4] < 6\'h5)begin
\t\t\t\tpri_h_case = 3\'H0;
\t\t\tend
\t\t\telse if(func_h_addr[9:4] < 6\'ha)begin
\t\t\t\tpri_h_case = 3\'h1;
\t\t\tend
\t\t\telse if(func_h_addr[9:4] < 6\'hf)begin
\t\t\t\tpri_h_case = 3\'h2;
\t\t\tend
\t\t\telse if(func_h_addr[9:4] < 6\'h14)begin
\t\t\t\tpri_h_case = 3\'h3;
\t\t\tend
\t\t\telse if(func_h_addr[9:4] < 6\'h19)begin
\t\t\t\tpri_h_case = 3\'h4;
\t\t\tend
\t\t\telse if(func_h_addr[9:4] < 6\'h1e)begin
\t\t\t\tpri_h_case = 3\'h5;
\t\t\tend
\t\t\telse if(func_h_addr[9:4] < 6\'h23)begin
\t\t\t\tpri_h_case = 3\'h6;
\t\t\tend
\t\t\telse begin
\t\t\t\tpri_h_case = 3\'h7;
\t\t\tend
\t\t\t//v
\t\t\tif(func_v_addr < 9\'h78)begin
\t\t\t\tpri_v_case = 2\'h0;
\t\t\tend
\t\t\telse if(func_v_addr < 9\'hf0)begin
\t\t\t\tpri_v_case = 2\'h1;
\t\t\tend
\t\t\telse if(func_v_addr < 9\'h168)begin
\t\t\t\tpri_v_case = 2\'h2;
\t\t\tend
\t\t\telse begin
\t\t\t\tpri_v_case = 2\'h3;
\t\t\tend
\t\t\tpri_puttern_case = pri_h_case + pri_v_case;
\t\t\tcase(pri_puttern_case)
\t\t\t\t3\'h0 : func_patgen = {5\'hFF, 6\'h00, 5\'h00};
\t\t\t\t3\'h1 : func_patgen = {5\'h00, 6\'hFF, 5\'h00};
\t\t\t\t3\'h2 : func_patgen = {5\'h00, 6\'h00, 5\'hFF};
\t\t\t\t3\'h3 : func_patgen = {5\'hFF, 6\'h00, 5\'hFF};
\t\t\t\t3\'h4 : func_patgen = {5\'hFF, 6\'hFF, 5\'h00};
\t\t\t\t3\'h5 : func_patgen = {5\'h00, 6\'hFF, 5\'hFF};
\t\t\t\t3\'h6 : func_patgen = {5\'h00, 6\'h00, 5\'h00};
\t\t\t\tdefault : func_patgen = {5\'hFF, 6\'hFF, 5\'hFF};
\t\t\tendcase
\t\tend
\tendfunction
\t
\t//System CLock
\talways#(SYS_CYCLE/2)begin
\t\tiCLOCK = !iCLOCK;
\tend
\t
\t//Display Clock
\talways#(DISP_CYCLE/2)begin\t
\t\tiVGA_CLOCK = !iVGA_CLOCK;
\tend
\tgci_std_display TARGET(
\t\t//System
\t\t.iCLOCK(iCLOCK),
\t\t.inRESET(inRESET),
\t\t//BUS(DATA)-Input
\t\t.iDEV_REQ(iDEV_REQ),\t\t
\t\t.oDEV_BUSY(oDEV_BUSY),
\t\t.iDEV_RW(iDEV_RW),
\t\t.iDEV_ADDR(iDEV_ADDR),
\t\t.iDEV_DATA(iDEV_DATA),
\t\t//BUS(DATA)-Output
\t\t.oDEV_REQ(oDEV_REQ),\t\t
\t\t.iDEV_BUSY(iDEV_BUSY),
\t\t.oDEV_DATA(oDEV_DATA),
\t\t//IRQ
\t\t.oDEV_IRQ_REQ(oDEV_IRQ_REQ),\t\t
\t\t.iDEV_IRQ_BUSY(iDEV_IRQ_BUSY),
\t\t.oDEV_IRQ_DATA(oDEV_IRQ_DATA), \t
\t\t.iDEV_IRQ_ACK(iDEV_IRQ_ACK),
\t\t//Display Clock
\t\t.iVGA_CLOCK(iVGA_CLOCK),
\t\t//SRAM
\t\t`ifdef GCI_STD_DISPLAY_SRAM
\t\t\t.onSRAM_CE(onSRAM_CE),
\t\t\t.onSRAM_WE(onSRAM_WE),
\t\t\t.onSRAM_OE(onSRAM_OE),
\t\t\t.onSRAM_UB(onSRAM_UB),
\t\t\t.onSRAM_LB(onSRAM_LB),
\t\t\t.oSRAM_ADDR(oSRAM_ADDR),
\t\t\t.ioSRAM_DATA(ioSRAM_DATA),
\t\t`elsif GCI_STD_DISPLAY_SSRAM\t\t\t
\t\t\t.oSSRAM_CLOCK(oSSRAM_CLOCK),
\t\t\t.onSSRAM_ADSC(onSSRAM_ADSC),
\t\t\t.onSSRAM_ADSP(onSSRAM_ADSP),
\t\t\t.onSSRAM_ADV(onSSRAM_ADC),
\t\t\t.onSSRAM_GW(onSSRAM_GW),
\t\t\t.onSSRAM_OE(onSSRAM_OE),
\t\t\t.onSSRAM_WE(onSSRAM_WE),
\t\t\t.onSSRAM_BE(onSSRAM_BE),
\t\t\t.onSSRAM_CE1(onSSRAM_CE1),
\t\t\t.oSSRAM_CE2(oSSRAM_CE2),
\t\t\t.onSSRAM_CE3(onSSRAM_CE3),
\t\t\t.oSSRAM_ADDR(oSSRAM_ADDR),
\t\t\t.ioSSRAM_DATA(ioSSRAM_DATA),
\t\t\t.ioSSRAM_PARITY(ioSSRAM_PARITY),
\t\t`endif
\t\t//Display
\t\t.oDISP_CLOCK(oDISP_CLOCK),
\t\t.onDISP_RESET(onDISP_RESET),
\t\t.oDISP_ENA(oDISP_ENA),
\t\t.oDISP_BLANK(oDISP_BLANK),
\t\t.onDISP_HSYNC(onDISP_HSYNC),
\t\t.onDISP_VSYNC(onDISP_VSYNC),
\t\t.oDISP_DATA_R(oDISP_DATA_R),
\t\t.oDISP_DATA_G(oDISP_DATA_G),
\t\t.oDISP_DATA_B(oDISP_DATA_B)\t
\t\t
\t);
endmodule
`default_nettype wire
|
`default_nettype none
\t
module gci_std_display_font(
\t\tinput wire [6:0] iADDR,
\t\toutput wire [111:0] oDATA
\t);\t
\tfunction [111:0] rom;\t//Offset 0x20
\t\tinput [6:0] funcADDR;
\t\tbegin
\t\t\tcase(funcADDR)
\t\t\t\t7'd0:\trom\t=\t112'h0000000000000000000000000000;
\t\t\t\t7'd1:\trom\t=\t112'h0000181818181010100000181800;
\t\t\t\t7'd2:\trom\t=\t112'h006c6c2448000000000000000000;
\t\t\t\t7'd3:\trom\t=\t112'h00002424247e2424487e48484800;
\t\t\t\t7'd4:\trom\t=\t112'h0000103c525250381452523c1000;
\t\t\t\t7'd5:\trom\t=\t112'h0000225254542818142a2a4A4400;
\t\t\t\t7'd6:\trom\t=\t112'h0000102828102652524c442a1000;
\t\t\t\t7'd7:\trom\t=\t112'h0030301020000000000000000000;
\t\t\t\t7'd8:\trom\t=\t112'h0004081010202020202010100804;
\t\t\t\t7'd9:\trom\t=\t112'h0020100808040404040408081020;
\t\t\t\t7'd10:\trom\t=\t112'h0000001010d6543854d610100000;
\t\t\t\t7'd11:\trom\t=\t112'h000000101010107e101010100000;
\t\t\t\t7'd12:\trom\t=\t112'h0000000000000000000030301020;
\t\t\t\t7'd13:\trom\t=\t112'h000000000000007e000000000000;
\t\t\t\t7'd14:\trom\t=\t112'h0000000000000000000000303000;
\t\t\t\t7'd15:\trom\t=\t112'h0202040408081010202040408080;
\t\t\t\t7'd16:\trom\t=\t112'h0000182424424242411224180000;\t//0
\t\t\t\t7'd17:\trom\t=\t112'h00001070101010101010107c0000;
\t\t\t\t7'd18:\trom\t=\t112'h00001824422204081020227e0000;
\t\t\t\t7'd19:\trom\t=\t112'h0000182442441804424112180000;
\t\t\t\t7'd20:\trom\t=\t112'h0000040C141424247e04040e0000;
\t\t\t\t7'd21:\trom\t=\t112'h00007c4040586442024112180000;
\t\t\t\t7'd22:\trom\t=\t112'h00001c1122586442424112180000;
\t\t\t\t7'd23:\trom\t=\t112'h00003e1122040408080808080000;
\t\t\t\t7'd24:\trom\t=\t112'h0000182441121824424112180000;
\t\t\t\t7'd25:\trom\t=\t112'h000018244242261a024424180000;
\t\t\t\t7'd26:\trom\t=\t112'h0000000018180000001818000000;
\t\t\t\t7'd27:\trom\t=\t112'h0000000018180000001818081000;
\t\t\t\t7'd28:\trom\t=\t112'h0000020408102040201008040200;
\t\t\t\t7'd29:\trom\t=\t112'h000000007e0000007E0000000000;
\t\t\t\t7'd30:\trom\t=\t112'h0000402010080402040810204000;
\t\t\t\t7'd31:\trom\t=\t112'h0000182442420408101000181800;
\t\t\t\t7'd32:\trom\t=\t112'h00001824112A5656564A20221C00;
\t\t\t\t7'd33:\trom\t=\t112'h00001010282828247c4444ee0000;
\t\t\t\t7'd34:\trom\t=\t112'h0000782424283c22222112780000;
\t\t\t\t7'd35:\trom\t=\t112'h00001a2611224040402226180000;
\t\t\t\t7'd36:\trom\t=\t112'h0000782424222222211224780000;
\t\t\t\t7'd37:\trom\t=\t112'h00007c2220243c242020227e0000;
\t\t\t\t7'd38:\trom\t=\t112'h00007c2220243c24202020780000;
\t\t\t\t7'd39:\trom\t=\t112'h00001a261122404e4222261a0000;
\t\t\t\t7'd40:\trom\t=\t112'h0000ee4444447c44444444ee0000;
\t\t\t\t7'd41:\trom\t=\t112'h00007c10101010101010107c0000;
\t\t\t\t7'd42:\trom\t=\t112'h00001e0404040404444448300000;
\t\t\t\t7'd43:\trom\t=\t112'h00006e2428283028242422760000;
\t\t\t\t7'd44:\trom\t=\t112'h00007020202020202020227c0000;
\t\t\t\t7'd45:\trom\t=\t112'h00004266666a5a52524242660000;
\t\t\t\t7'd46:\trom\t=\t112'h000046626252524A4a4646620000;
\t\t\t\t7'd47:\trom\t=\t112'h0000182442424242424112180000;
\t\t\t\t7'd48:\trom\t=\t112'h0000782422211238202020700000;
\t\t\t\t7'd49:\trom\t=\t112'h0000182442424242724e24180600;
\t\t\t\t7'd50:\trom\t=\t112'h0000782422211238282424720000;
\t\t\t\t7'd51:\trom\t=\t112'h00001a2642201804024264580000;
\t\t\t\t7'd52:\trom\t=\t112'h00007e5210101010101010380000;
\t\t\t\t7'd53:\trom\t=\t112'h0000762222222222222214080000;
\t\t\t\t7'd54:\trom\t=\t112'h0000664112242428181010100000;
\t\t\t\t7'd55:\trom\t=\t112'h0000929292525A6A6c2424240000;
\t\t\t\t7'd56:\trom\t=\t112'h00006244242810182824444e0000;
\t\t\t\t7'd57:\trom\t=\t112'h0000e64112281810101010380000;
\t\t\t\t7'd58:\trom\t=\t112'h00003e44040808102020427c0000;
\t\t\t\t7'd59:\trom\t=\t112'h003c20202020202020202020203C;
\t\t\t\t7'd60:\trom\t=\t112'h8080404020201010080804040202;
\t\t\t\t7'd61:\trom\t=\t112'h003c04040404040404040404043C;
\t\t\t\t7'd62:\trom\t=\t112'h0010284482000000000000000000;
\t\t\t\t7'd63:\trom\t=\t112'h00000000000000000000000000FE;
\t\t\t\t7'd64:\trom\t=\t112'h0018181008000000000000000000;
\t\t\t\t7'd65:\trom\t=\t112'h000000003844441c2444443a0000;
\t\t\t\t7'd66:\trom\t=\t112'h0000602028342222222112380000;
\t\t\t\t7'd67:\trom\t=\t112'h000000001a264240404226180000;
\t\t\t\t7'd68:\trom\t=\t112'h00000c04142c44444444241e0000;
\t\t\t\t7'd69:\trom\t=\t112'h000000001824427e4042221c0000;
\t\t\t\t7'd70:\trom\t=\t112'h00000c12127c1010101010380000;
\t\t\t\t7'd71:\trom\t=\t112'h000000001a24242418205c42423C;
\t\t\t\t7'd72:\trom\t=\t112'h0000c04050684444444444c60000;
\t\t\t\t7'd73:\trom\t=\t112'h00001818003808080808083c0000;
\t\t\t\t7'd74:\trom\t=\t112'h00000c0c001c0404040404444830;
\t\t\t\t7'd75:\trom\t=\t112'h0000c04046444858684444ce0000;
\t\t\t\t7'd76:\trom\t=\t112'h00003808080808080808083e0000;
\t\t\t\t7'd77:\trom\t=\t112'h00000000acd29292929292920000;
\t\t\t\t7'd78:\trom\t=\t112'h00000000d8644444444444c60000;
\t\t\t\t7'd79:\trom\t=\t112'h0000000018244242424112180000;
\t\t\t\t7'd80:\trom\t=\t112'h0000000058242222222112382070;
\t\t\t\t7'd81:\trom\t=\t112'h000000001a2444444444241c040E;
\t\t\t\t7'd82:\trom\t=\t112'h000000005c222220202020700000;
\t\t\t\t7'd83:\trom\t=\t112'h000000003c4440300c42625c0000;
\t\t\t\t7'd84:\trom\t=\t112'h00001010107c10101010120c0000;
\t\t\t\t7'd85:\trom\t=\t112'h00000000cc44444444444c320000;
\t\t\t\t7'd86:\trom\t=\t112'h0000000066424424281810100000;
\t\t\t\t7'd87:\trom\t=\t112'h00000000929292925A6c24240000;
\t\t\t\t7'd88:\trom\t=\t112'h0000000066242818181424660000;
\t\t\t\t7'd89:\trom\t=\t112'h0000000066222214140808485020;
\t\t\t\t7'd90:\trom\t=\t112'h000000003e4408081010227e0000;
\t\t\t\t7'd91:\trom\t=\t112'h0006081010101020101010100806;
\t\t\t\t7'd92:\trom\t=\t112'h0010101010101010101010101010;
\t\t\t\t7'd93:\trom\t=\t112'h0060100808080804080808081060;
\t\t\t\tdefault:\trom\t=\t112'h0000000000000000000000000000;
\t\t\tendcase
\t\tend
\tendfunction
\t
\tassign oDATA = rom(iADDR - 8'h20);\t
\t
endmodule
`default_nettype wire
|
`default_nettype none
module gci_std_display_sequencer #(
\t\t//Area
\t\tparameter P_AREA_H = 640,
\t\tparameter P_AREA_V = 480,
\t\tparameter P_AREAA_HV_N = 19,
\t\tparameter P_MEM_ADDR_N = 23
\t)(
\t\tinput wire iCLOCK,
\t\tinput wire inRESET,
\t\tinput wire iRESET_SYNC,
\t\t//Req
\t\tinput wire iIF_VALID,
\t\toutput wire oIF_BUSY,
\t\tinput wire [31:0] iIF_DATA,
\t\t//Out
\t\toutput wire oIF_FINISH,
\t\toutput wire oIF_VALID,
\t\tinput wire iIF_BUSY,
\t\toutput wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
\t\toutput wire [23:0] oIF_DATA
\t);
\t
\t/********************************************
\tDisplay Clear
\t********************************************/
\tlocalparam P_L_CLEAR_STT_IDLE = 2'h0;
\tlocalparam P_L_CLEAR_STT_CLEAR = 2'h1;
\tlocalparam P_L_CLEAR_STT_END = 2'h2;
\t
\treg [1:0] b_clear_state;
\treg [7:0] b_clear_color_r;
\treg [7:0] b_clear_color_g;
\treg [7:0] b_clear_color_b;
\treg [P_AREAA_HV_N-1:0] b_clear_counter;
\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_clear_state <= P_L_CLEAR_STT_IDLE;
\t\t\tb_clear_color_r <= 8'h0;
\t\t\tb_clear_color_g <= 8'h0;
\t\t\tb_clear_color_b <= 8'h0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_clear_state <= P_L_CLEAR_STT_IDLE;
\t\t\tb_clear_color_r <= 8'h0;
\t\t\tb_clear_color_g <= 8'h0;
\t\t\tb_clear_color_b <= 8'h0;
\t\tend
\t\telse begin
\t\t\tcase(b_clear_state)
\t\t\t\tP_L_CLEAR_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iIF_VALID)begin
\t\t\t\t\t\t\tb_clear_state <= P_L_CLEAR_STT_CLEAR;
\t\t\t\t\t\t\t{b_clear_color_r,
\t\t\t\t\t\t\tb_clear_color_g,
\t\t\t\t\t\t\tb_clear_color_b} <= iIF_DATA[23:0];
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_CLEAR_STT_CLEAR:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(b_clear_counter == (P_AREA_H*P_AREA_V))begin
\t\t\t\t\t\t\tb_clear_state <= P_L_CLEAR_STT_END;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_CLEAR_STT_END:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_clear_state <= P_L_CLEAR_STT_IDLE;
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_clear_state <= P_L_CLEAR_STT_IDLE;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_clear_counter <= {P_AREAA_HV_N{1'b0}};
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_clear_counter <= {P_AREAA_HV_N{1'b0}};
\t\tend
\t\telse begin
\t\t\tif(b_clear_state == P_L_CLEAR_STT_CLEAR)begin
\t\t\t\tif(!iIF_BUSY)begin
\t\t\t\t\tb_clear_counter <= b_clear_counter + {{P_AREAA_HV_N-1{1'b0}}, 1'b1};
\t\t\t\tend
\t\t\tend
\t\t\telse begin
\t\t\t\tb_clear_counter <= {P_AREAA_HV_N{1'b0}};
\t\t\tend
\t\tend
\tend
\t
\tassign oIF_BUSY = b_clear_state != P_L_CLEAR_STT_IDLE;
\t
\tassign oIF_FINISH = b_clear_state == P_L_CLEAR_STT_END;
\tassign oIF_VALID = !iIF_BUSY && (b_clear_state == P_L_CLEAR_STT_CLEAR);
\tassign oIF_ADDR = b_clear_counter;
\tassign oIF_DATA = {b_clear_color_r, b_clear_color_g, b_clear_color_b};
endmodule
`default_nettype wire
|
`default_nettype none
module gci_std_display_data_read #(
\t\tparameter P_AREA_H = 640,
\t\tparameter P_AREA_Y = 480,
\t\tparameter P_READ_FIFO_DEPTH = 64,
\t\tparameter P_READ_FIFO_DEPTH_N = 6,
\t\tparameter P_MEM_ADDR_N = 19
\t)(
\t\t//System
\t\tinput wire iGCI_CLOCK,
\t\tinput wire iDISP_CLOCK,
\t\tinput wire inRESET,
\t\tinput wire iRESET_SYNC,
\t\t//Read Request
\t\tinput wire iRD_ENA,
\t\tinput wire iRD_SYNC,
\t\toutput wire oRD_VALID,
\t\toutput wire [7:0] oRD_DATA_R,
\t\toutput wire [7:0] oRD_DATA_G,
\t\toutput wire [7:0] oRD_DATA_B,
\t\t//Memory IF
\t\toutput wire oIF_REQ,
\t\tinput wire iIF_ACK,
\t\toutput wire oIF_FINISH,
\t\toutput wire oIF_ENA,
\t\tinput wire iIF_BUSY,
\t\toutput wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
\t\tinput wire iIF_VALID,
\t\tinput wire [31:0] iIF_DATA
\t);
\t
\t//Main State
\tlocalparam P_L_MAIN_STT_IDLE = 2'h0;
\tlocalparam P_L_MAIN_STT_IF_REQ = 2'h1;
\tlocalparam P_L_MAIN_STT_WORK = 2'h2;
\tlocalparam P_L_MAIN_STT_IF_FINISH = 2'h3;
\t//Read State
\tlocalparam P_L_READ_STT_IDLE = 1'h0;
\tlocalparam P_L_READ_STT_READ = 1'h1;
\tlocalparam P_L_READ_STT_END = 1'h2;
\t
\t//Main State
\treg [1:0] b_main_state;
\t//Read State
\treg b_read_state;
\treg [P_MEM_ADDR_N-1:0] b_read_addr;
\treg [P_READ_FIFO_DEPTH_N-1:0] b_read_count;
\t//FIFO
\twire vramfifo0_full;
\twire vramfifo0_empty;
\twire [23:0] vramfifo0_data;
\twire vramfifo1_full;
\twire vramfifo1_empty;\t
\twire [7:0] vramfifo1_data_r, vramfifo1_data_g, vramfifo1_data_b;
\t//Output Buffer
\treg b_out_buff_valid;
\treg [7:0] b_out_buff_r, b_out_buff_g, b_out_buff_b;
\t
\t//Condition
\twire if_request_condition = vramfifo0_empty;
\twire read_state_start_condition = (b_main_state == P_L_MAIN_STT_WORK);
\t
\t/***************************************************
\tMain State
\t***************************************************/
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\tend
\t\telse begin
\t\t\tcase(b_main_state)
\t\t\t\tP_L_MAIN_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(if_request_condition)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IF_REQ;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_IF_REQ:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iIF_ACK)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_WORK;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_WORK:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(b_read_state == P_L_READ_STT_END)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IF_FINISH;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_IF_FINISH:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_IDLE;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\t/***************************************************
\tRead State
\t***************************************************/\t
\talways@(posedge iGCI_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_read_state <= P_L_READ_STT_IDLE;
\t\t\tb_read_addr <= {P_MEM_ADDR_N{1'b0}};
\t\t\tb_read_count <= {P_READ_FIFO_DEPTH_N{1'b0}};
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_read_state <= P_L_READ_STT_IDLE;
\t\t\tb_read_addr <= {P_MEM_ADDR_N{1'b0}};
\t\t\tb_read_count <= {P_READ_FIFO_DEPTH_N{1'b0}};
\t\tend
\t\telse begin
\t\t\tcase(b_read_state)
\t\t\t\tP_L_READ_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_read_count <= {P_READ_FIFO_DEPTH_N{1'b0}};
\t\t\t\t\t\tif(read_state_start_condition)begin
\t\t\t\t\t\t\tb_read_state <= P_L_READ_STT_READ;
\t\t\t\t\t\tend
\t\t\t\t\tend\t\t
\t\t\t\tP_L_READ_STT_READ:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(b_read_count < {P_READ_FIFO_DEPTH_N{1'b0}})begin
\t\t\t\t\t\t\tif(!iIF_BUSY)begin\t//Busy Check
\t\t\t\t\t\t\t\tb_read_addr <= func_read_next_addr(b_read_addr);
\t\t\t\t\t\t\t\tb_read_count <= b_read_count + {{P_READ_FIFO_DEPTH_N-1{1'b0}}, 1'b1};
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\telse begin
\t\t\t\t\t\t\tb_read_state <= P_L_READ_STT_END;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_READ_STT_END:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_read_state <= P_L_READ_STT_IDLE;
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_read_state <= P_L_READ_STT_IDLE;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend //Read State
\t
\tfunction [P_MEM_ADDR_N-1:0] func_read_next_addr;
\t\tinput [P_MEM_ADDR_N-1:0] func_now_addr;
\t\tbegin
\t\t\tif(func_now_addr < (P_AREA_H*P_AREA_V)-1)begin
\t\t\t\tfunc_read_next_addr = func_now_addr + 1;
\t\t\tend
\t\t\telse begin
\t\t\t\tfunc_read_next_addr = {P_MEM_ADDR_N{1'b0}};
\t\t\tend
\t\tend
\tendfunction
\t/***************************************************
\tOutput FIFO
\t***************************************************/
\tgci_std_sync_fifo #(24, P_READ_FIFO_DEPTH, P_READ_FIFO_DEPTH_N) VRAMREAD_FIFO0(
\t\t.inRESET(inRESET),
\t\t.iREMOVE(iRESET_SYNC),
\t\t.iCLOCK(iGCI_CLOCK),
\t\t.iWR_EN(iIF_VALID && !vramfifo0_full),
\t\t.iWR_DATA(iIF_DATA[23:0]),
\t\t.oWR_FULL(vramfifo0_full),
\t\t.oWR_ALMOST_FULL(),
\t\t.iRD_EN(!vramfifo0_empty && !vramfifo1_full),
\t\t.oRD_DATA(vramfifo0_data),
\t\t.oRD_EMPTY(vramfifo0_empty)
\t);
\tgci_std_async_fifo #(24, P_READ_FIFO_DEPTH, P_READ_FIFO_DEPTH_N) VRAMREAD_FIFO1(
\t\t.inRESET(inRESET),
\t\t.iREMOVE(iRESET_SYNC),
\t\t.iWR_CLOCK(iGCI_CLOCK),
\t\t.iWR_EN(!vramfifo0_empty && !vramfifo1_full),
\t\t.iWR_DATA(vramfifo0_data),
\t\t.oWR_FULL(vramfifo1_full),
\t\t.iRD_CLOCK(iDISP_CLOCK),
\t\t.iRD_EN(!vramfifo1_empty && iRD_ENA),
\t\t.oRD_DATA({vramfifo1_data_r, vramfifo1_data_g, vramfifo1_data_b}),
\t\t.oRD_EMPTY(vramfifo1_empty)
\t);
\t
\t/***************************************************
\tOutput Buffer
\t***************************************************/\t
\talways@(posedge iDISP_CLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_out_buff_valid <= 1'b0;
\t\t\tb_out_buff_r <= 8'h0;
\t\t\tb_out_buff_g <= 8'h0;
\t\t\tb_out_buff_b <= 8'h0;
\t\tend
\t\telse begin
\t\t\tb_out_buff_valid <= iRD_ENA;
\t\t\tb_out_buff_r <= vramfifo1_data_r;
\t\t\tb_out_buff_g <= vramfifo1_data_g;
\t\t\tb_out_buff_b <= vramfifo1_data_b;
\t\tend
\tend
\t
\t/***************************************************
\tAssign
\t***************************************************/
\tassign oRD_VALID = b_out_buff_valid;
\tassign oRD_DATA_R = b_out_buff_r;
\tassign oRD_DATA_G = b_out_buff_g;
\tassign oRD_DATA_B = b_out_buff_b;
\t
\tassign oIF_REQ = (b_main_state == P_L_MAIN_STT_IF_REQ);
\tassign oIF_FINISH = (b_main_state == P_L_MAIN_STT_IF_FINISH);
\tassign oIF_ENA = !iIF_BUSY && (b_read_state == P_L_READ_STT_READ);
\tassign oIF_ADDR = b_read_addr;
\t
\t/***************************************************
\tAssertion
\t***************************************************/
\t`ifdef GCI_STD_DISP_SVA_ASSERTION
\t\tproterty PRO_FIFO_NEVER_NOT_EMPTY;
\t\t\t@(posedge iDISP_CLOCK) disable iff (!inRESET) (!vramfifo1_empty |=> !vramfifo1_empty);
\t\tendproperty
\t\tassert property(PRO_FIFO_NEVER_NOT_EMPTY);
\t`endif
\t
endmodule
`default_nettype wire
|
`default_nettype none
module gci_std_display_async_fifo_double_flipflop #(
\t\tparameter N = 1
\t)(
\t\tinput iCLOCK,
\t\tinput inRESET,
\t\t//Input
\t\tinput [N-1:0] iREQ_DATA,
\t\t//Output
\t\toutput [N-1:0] oOUT_DATA
\t);
\t
\treg [N-1:0] b_data0/* synthesis preserve = 1 */;\t\t//Altera QuartusII Option
\treg [N-1:0] b_data1/* synthesis preserve = 1 */;\t\t//Altera QuartusII Option
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_data0 <= {N{1'b0}};
\t\t\tb_data1 <= {N{1'b0}};
\t\tend
\t\telse begin
\t\t\tb_data0 <= iREQ_DATA;
\t\t\tb_data1 <= b_data0;
\t\tend
\tend
\t
\tassign oOUT_DATA = b_data1;
\t
endmodule
`default_nettype wire
\t
|
`default_netype none
module memory_resource_controller #(
\t\tparameter P_MEM_ADDR_N = 22
\t)(
\t\tinput wire iCLOCK,
\t\tinput wire inRESET,
\t\tinput wire iRESET_SYNC,
\t\t//IF0
\t\tinput wire iIF0_ARBIT_REQ,
\t\toutput wire oIF0_ARBIT_ACK,
\t\tinput wire iIF0_ARBIT_FINISH,
\t\tinput wire iIF0_ENA,
\t\toutput wire oIF0_BUSY,
\t\tinput wire iIF0_RW,
\t\tinput wire [P_MEM_ADDR_N-1:0] iIF0_ADDR,
\t\tinput wire [31:0] iIF0_DATA,
\t\toutput wire oIF0_VALID,
\t\tinput wire iIF0_BUSY,
\t\toutput wire [31:0] oIF0_DATA,
\t\t//IF1
\t\tinput wire iIF1_ARBIT_REQ,
\t\toutput wire oIF1_ARBIT_ACK,
\t\tinput wire iIF1_ARBIT_FINISH,
\t\tinput wire iIF1_ENA,
\t\toutput wire oIF1_BUSY,
\t\tinput wire iIF1_RW,
\t\tinput wire [P_MEM_ADDR_N-1:0] iIF1_ADDR,
\t\tinput wire [31:0] iIF1_DATA,
\t\toutput wire oIF1_VALID,
\t\tinput wire iIF1_BUSY,
\t\toutput wire [31:0] oIF1_DATA,
\t\t//Memory Controller
\t\toutput wire oMEM_ENA,
\t\tinput wire iMEM_BUSY,
\t\toutput wire oMEM_RW,
\t\toutput wire [P_MEM_ADDR_N-1:0] oMEM_ADDR,
\t\toutput wire [31:0] oMEM_DATA,
\t\tinput wire iMEM_VALID,
\t\toutput wire oMEM_BUSY,
\t\tinput wire [31:0] iMEM_DATA
\t);
\t
\tlocalparam L_PARAM_STT_IDLE = 2'h0;
\tlocalparam L_PARAM_STT_ACK = 2'h1;
\tlocalparam L_PARAM_STT_WORK = 2'h2;
\t
\treg [1:0] b_state;
\treg b_authority;
\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_state <= L_PARAM_STT_IDLE;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_state <= L_PARAM_STT_IDLE;
\t\tend
\t\telse begin
\t\t\tcase(b_state)
\t\t\t\tL_PARAM_STT_IDLE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(iIF0_ARBIT_REQ || iIF1_ARBIT_REQ)begin
\t\t\t\t\t\t\tb_state <= L_PARAM_STT_ACK;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tL_PARAM_STT_ACK:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_state <= L_PARAM_STT_WORK;
\t\t\t\t\tend
\t\t\t\tL_PARAM_STT_WORK:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(func_if_finish_check(b_authority, iIF0_ARBIT_FINISH, iIF1_ARBIT_FINISH))begin
\t\t\t\t\t\t\tb_state <= L_PARAM_STT_IDLE;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tdefault:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_state <= L_PARAM_STT_IDLE;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_authority <= 1'b0;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_authority <= 1'b0;
\t\tend
\t\telse begin
\t\t\tif(b_state == L_PARAM_STT_IDLE)begin
\t\t\t\tb_authority <= func_priority_encoder(b_authority, iIF0_ARBIT_REQ, iIF1_ARBIT_REQ);
\t\t\tend
\t\tend
\tend
\t
\tfunction func_if_finish_check;
\t\tinput func_now;
\t\tinput func_if0_finish;
\t\tinput func_if1_finish;
\t\tbegin
\t\t\tif(!func_now && func_if0_finish)begin
\t\t\t\tfunc_if_finish_check = 1'b1;
\t\t\tend
\t\t\telse if(func_now && func_if1_finish)begin
\t\t\t\tfunc_if_finish_check = 1'b1;
\t\t\tend
\t\t\telse begin
\t\t\t\tfunc_if_finish_check = 1'b0;
\t\t\tend
\t\tend
\tendfunction
\t
\t
\t//Interface
\tfunction func_priority_encoder;
\t\tinput func_now;
\t\tinput func_if0_req;
\t\tinput func_if1_req;
\t\tbegin
\t\t\tcase(func_now)
\t\t\t\t1'b0:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(func_if1_req)begin
\t\t\t\t\t\t\tfunc_priority_encoder = 1'b1;
\t\t\t\t\t\tend
\t\t\t\t\t\telse if(func_if0_req)begin
\t\t\t\t\t\t\tfunc_priority_encoder = 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\t\telse begin
\t\t\t\t\t\t\tfunc_priority_encoder = 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\t1'b1:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(func_if0_req)begin
\t\t\t\t\t\t\tfunc_priority_encoder = 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\t\telse if(func_if1_req)begin
\t\t\t\t\t\t\tfunc_priority_encoder = 1'b1;
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\telse begin
\t\t\t\t\t\t\tfunc_priority_encoder = 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tendfunction
\t
\t
\treg b_if2mem_ena;
\treg b_if2mem_rw;
\treg [P_MEM_ADDR_N-1:0] b_if2mem_addr;
\treg [31:0] b_if2mem_data;
\treg b_mem2if0_valid;
\treg [31:0] b_mem2if0_data;
\treg b_mem2if1_valid;
\treg [31:0] b_mem2if1_data;
\t
\t
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_if2mem_ena <= 1'b0;
\t\t\tb_if2mem_rw <= 1'b0;
\t\t\tb_if2mem_addr <= {P_MEM_ADDR_N{1'b0}};
\t\t\tb_if2mem_data <= 32'h0;
\t\t\tb_mem2if0_valid <= 1'b0;
\t\t\tb_mem2if0_data <= 32'h0;
\t\t\tb_mem2if1_valid <= 1'b0;
\t\t\tb_mem2if1_data <= 32'h0;
\t\tend
\t\telse if(b_state != L_PARAM_STT_WORK || iRESET_SYNC)begin
\t\t\tb_if2mem_ena <= 1'b0;
\t\t\tb_if2mem_rw <= 1'b0;
\t\t\tb_if2mem_addr <= {P_MEM_ADDR_N{1'b0}};
\t\t\tb_if2mem_data <= 32'h0;
\t\t\tb_mem2if0_valid <= 1'b0;
\t\t\tb_mem2if0_data <= 32'h0;
\t\t\tb_mem2if1_valid <= 1'b0;
\t\t\tb_mem2if1_data <= 32'h0;
\t\tend
\t\telse begin
\t\t\tcase(b_authority)
\t\t\t\t1'b0:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_if2mem_ena <= iIF0_ENA;
\t\t\t\t\t\tb_if2mem_rw <= iIF0_RW;
\t\t\t\t\t\tb_if2mem_addr <= iIF0_ADDR;
\t\t\t\t\t\tb_if2mem_data <= iIF0_DATA;
\t\t\t\t\t\tb_mem2if0_valid <= iMEM_VALID;
\t\t\t\t\t\tb_mem2if0_data <= iMEM_DATA;
\t\t\t\t\t\tb_mem2if1_valid <= 1'b0;
\t\t\t\t\t\tb_mem2if1_data <= 32'h0;
\t\t\t\t\tend
\t\t\t\t1'b1:
\t\t\t\t\tbegin
\t\t\t\t\t\tb_if2mem_ena <= iIF1_ENA;
\t\t\t\t\t\tb_if2mem_rw <= iIF1_RW;
\t\t\t\t\t\tb_if2mem_addr <= iIF1_ADDR;
\t\t\t\t\t\tb_if2mem_data <= iIF1_DATA;
\t\t\t\t\t\tb_mem2if0_valid <= 1'b0;
\t\t\t\t\t\tb_mem2if0_data <= 32'h0;
\t\t\t\t\t\tb_mem2if1_valid <= iMEM_VALID;
\t\t\t\t\t\tb_mem2if1_data <= iMEM_DATA;
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\tassign oIF0_ARBIT_ACK = (b_state == L_PARAM_STT_ACK) && !b_authority;
\tassign oIF1_ARBIT_ACK = (b_state == L_PARAM_STT_ACK) && b_authority;
\tassign oIF0_VALID = b_mem2if0_valid;
\tassign oIF0_DATA = b_mem2if0_data;
\tassign oIF1_VALID = b_mem2if1_valid;
\tassign oIF1_DATA = b_mem2if1_data;
\t
\tassign oMEM_ENA = b_if2mem_ena;
\tassign oMEM_RW = b_if2mem_rw;
\tassign oMEM_ADDR = b_if2mem_addr;
\tassign oMEM_DATA = b_if2mem_data;
\t
\t
endmodule
`default_nettype wire
|
`default_nettype none
module gci_std_display_hub_interface(
\t\t//System
\t\tinput wire iCLOCK,
\t\tinput wire inRESET,
\t\tinput wire iRESET_SYNC,\t\t\t
\t\t//HUB(Reqest/Write)
\t\tinput wire iHUB_REQ,
\t\toutput wire oHUB_BUSY,
\t\tinput wire iHUB_RW,
\t\tinput wire [31:0] iHUB_ADDR,
\t\tinput wire [31:0] iHUB_DATA,
\t\t//HUB(Read)
\t\toutput wire oHUB_VALID,
\t\tinput wire iHUB_BUSY,
\t\toutput wire oHUB_DATA,
\t\t//Register(Request/Write)
\t\toutput wire oREG_ENA,
\t\toutput wire oREG_RW,
\t\toutput wire [3:0] oREG_ADDR,
\t\toutput wire [31:0] oREG_DATA,
\t\t//Register(Read)
\t\tinput wire iREG_VALID,
\t\toutput wire oREG_BUSY,
\t\tinput wire [31:0] iREG_DATA,
\t\t//Command(Request/Write)
\t\toutput wire oCOMM_VALID,
\t\toutput wire oCOMM_SEQ,
\t\tinput wire iCOMM_BUSY,
\t\toutput wire oCOMM_RW,
\t\toutput wire [31:0] oCOMM_ADDR,
\t\toutput wire [31:0] oCOMM_DATA,
\t\t//Command(Read)
\t\tinput wire iCOMM_VALID,
\t\toutput wire oCOMM_BUSY,
\t\tinput wire [31:0] iCOMM_ADDR,
\t\tinput wire [23:0] iCOMM_DATA
\t);
\t//Register / Command -> Hub
\tassign oHUB_BUSY =
\tassign oHUB_VALID =
\tassign oHUB_DATA =
\t//Hub -> Register
\tassign oREG_ENA = register_ctrl_condition;
\tassign oREG_RW = iHUB_RW;
\tassign oREG_ADDR = iHUB_ADDR;
\tassign oREG_DATA = iHUB_DATA;
\tassign oREG_BUSY =
\t//Hub -> Command
\tassign oCOMM_VALID = display_ctrl_condition || sequence_ctrl_condition;
\tassign oCOMM_SEQ = sequence_ctrl_condition;
\tassign oCOMM_RW = iHUB_RW;
\tassign oCOMM_ADDR = iHUB_ADDR;
\tassign oCOMM_DATA = iHUB_DATA;
\tassign oCOMM_BUSY =
\t
\t
\t
\t
\twire register_busy_condition =
\twire display_busy_condition =
\twire sequence_busy_condition =
\t
\twire register_ctrl_condition = iHUB_ADDR <= 32'hF && (iHUB_ADDR == 32'h4)? !iHUB_RW : 1'b1;
\twire display_ctrl_condition = iHUB_ADDR > 32'hF;
\twire sequence_ctrl_condition = (iHUB_ADDR == 32'h4) && iHUB_RW;
\t
\tlocalparam P_L_MAIN_STT_WRITE = 1'b0;
\tlocalparam P_L_MAIN_STT_READ_WAIT = 1'b1;
\t
\t
\treg b_main_state;
\talways@(posedge iCLOCK or negedge inRESET)begin
\t\tif(!inRESET)begin
\t\t\tb_main_state <= P_L_MAIN_STT_WRITE;
\t\tend
\t\telse if(iRESET_SYNC)begin
\t\t\tb_main_state <= P_L_MAIN_STT_WRITE;
\t\tend
\t\telse begin
\t\t\tcase(b_main_state)
\t\t\t\tP_L_MAIN_STT_WRITE:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(!iHUB_RW)begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_READ_WAIT;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tP_L_MAIN_STT_READ_WAIT:
\t\t\t\t\tbegin
\t\t\t\t\t\tif(!iHUB_BUSY && ())begin
\t\t\t\t\t\t\tb_main_state <= P_L_MAIN_STT_WRITE;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\tendcase
\t\tend
\tend
\t
\t
\tassign oIF_WR_BUSY = (iIF_WR_RW)? ??? :
\t
\t
\t
endmodule
`default_nettype wire
|
LIBAVDEVICE_$MAJOR {
global: avdevice_*;
local: *;
};
|
LIBSWSCALE_$MAJOR {
global: swscale_*; sws_*; ff_*;
local: *;
};
|
LIBAVUTIL_$MAJOR {
global: av_*; ff_*; avutil_*;
local: *;
};
|
LIBSWRESAMPLE_$MAJOR {
global: swr_*; ff_*; swresample_*;
local: *;
};
|
LIBAVFILTER_$MAJOR {
global: avfilter_*; av_*;
local: *;
};
|
LIBAVFORMAT_$MAJOR {
global: av*;
#FIXME those are for ffserver
ff_inet_aton;
ff_socket_nonblock;
ffm_set_write_index;
ffm_read_write_index;
ffm_write_write_index;
ff_rtsp_parse_line;
ff_rtp_get_local_rtp_port;
ff_rtp_get_local_rtcp_port;
ffio_open_dyn_packet_buf;
ffurl_close;
ffurl_open;
ffurl_write;
url_open;
url_close;
url_write;
url_get_max_packet_size;
#those are deprecated, remove on next bump
find_info_tag;
parse_date;
dump_format;
url_*;
ff_timefilter_destroy;
ff_timefilter_new;
ff_timefilter_update;
ff_timefilter_reset;
get_*;
put_*;
udp_set_remote_url;
udp_get_local_port;
init_checksum;
init_put_byte;
local: *;
};
|
LIBAVCODEC_$MAJOR {
global: av*;
audio_resample;
audio_resample_close;
#deprecated, remove after next bump
img_get_alpha_info;
dsputil_init;
ff_find_pix_fmt;
ff_framenum_to_drop_timecode;
ff_framenum_to_smtpe_timecode;
ff_raw_pix_fmt_tags;
ff_init_smtpe_timecode;
ff_fft*;
ff_mdct*;
ff_dct*;
ff_rdft*;
ff_prores_idct_put_10_sse2;
ff_simple_idct*;
ff_aanscales;
ff_faan*;
ff_mmx_idct;
ff_fdct*;
fdct_ifast;
j_rev_dct;
ff_mmxext_idct;
ff_idct_xvid*;
ff_jpeg_fdct*;
#XBMC's configure checks for ff_vdpau_vc1_decode_picture()
ff_vdpau_vc1_decode_picture;
local: *;
};
|
LIBPOSTPROC_$MAJOR {
global: postproc_*; pp_*;
local: *;
};
|
`include "DEF.v"
/*
DCACHE_BLOCK_SIZE 64*4 byte
DMEMORY_SIZE 26\'h4000000 byte
DCACHE_SIZE 16\'h10000 byte
*/
module dmemory(address, data, /*enable,*/ read, write);
input [31:0] address;
inout [31:0] data;
//input enable;
input read, write;
reg [31:0] dmemory [24\'hFFFFFF:0];
assign data = (/*enable &&*/ read) ? dmemory[address] : 32\'hz;
/*
always @(posedge read)
begin
if(address === 14999)
begin
$display("MREAD!!!!!! %d %d\
", address, dmemory[address]);
$stop;
end
end
*/
always @(posedge write)
begin
dmemory[address] <= data;
/*
if(address === 14999)
begin
$display("MWRITE!!!!! %d %d %d\
", address, address*4, data);
$stop;
end
*/
end
endmodule
|
`include "DEF.v"
module cdb(databus, data, write, databus2, data2, write2);
output [63:0] databus, databus2;
input [63:0] data, data2;
input write, write2;
reg [63:0] r_databus, r_databus2;
assign databus = r_databus;
assign databus2 = r_databus2;
always @(posedge write)
begin
r_databus <= data;
/*
$display("CDB!!!!!! %d %d\
", data[63:48], data[31:0]);
$stop;
*/
end
always @(posedge write2)
begin
r_databus2 <= data2;
/*
$display("CDB!!!!!! %d %d\
", data[63:48], data[31:0]);
$stop;
*/
end
endmodule
|
/*
Is not working :-(
*/
/*
`include "DEF.v"
module dcachel2(clock, address, data, read, write, rs_ex_ok, out_address, out_data, out_read, out_write, in_databus, out_databus, write_databus);
input [31:0] address;
inout [31:0] data, out_data;
input read, write;
input [63:0] in_databus;
input clock;
output [31:0] out_address;
output out_read, out_write;
output [63:0] out_databus;
output write_databus;
output rs_ex_ok;
reg [31:0] dcache [19\'h7FFFF:0];
reg [31:0] tag [19\'h7FFFF:0];
reg dirty [19\'h7FFFF:0];
reg [31:0] r_out_address;
reg [31:0] r_out_data;
reg r_out_read, r_out_write;
reg [31:0] r_data;
reg [63:0] r_out_databus;
reg r_write_databus;
reg signed [31:0] r_status;
reg [31:0] r_address;
reg r_lw_or_sw;
reg r_rs_ex_ok;
integer i;
assign data = r_data;
assign out_read = r_out_read;
assign out_write = r_out_write;
assign out_address = r_out_address;
assign out_data = r_out_data;
assign out_databus = r_out_databus;
assign write_databus = r_write_databus;
assign rs_ex_ok = r_rs_ex_ok;
always @(negedge clock)
begin
if(r_status === `DELAY_MEMORY)
begin
r_write_databus <= 1;
end
#0.001
r_status = r_status - 1;
//#0.001 $display("r_status: %d\
", r_status);
#0.001
if(r_status <= 0)
begin
r_write_databus <= 0;
r_out_databus <= 64\'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
#0.001
r_write_databus <= 1;
end
end
always @(posedge read)
begin
r_out_read <= 0;
r_out_write <= 0;
r_write_databus <= 0;
if(tag[address % 20\'h80000] === address)
begin
r_data <= dcache[address % 20\'h80000];
r_out_databus <= 64\'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= 1;
r_address <= address;
r_lw_or_sw <= 0;
r_rs_ex_ok <= 1;
end
else
begin
r_rs_ex_ok <= 0;
//$display("miss \
");
//$stop;
if(dirty[address % 20\'h80000] === 1)
begin
r_out_address <= tag[address % 20\'h80000];
r_out_data <= dcache[address % 20\'h80000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address;
r_out_write <= 0;
r_out_data <= 32\'hz;
r_out_read <= 1;
#0.001
dcache[address % 20\'h80000] <= out_data;
tag[address % 20\'h80000] <= address;
dirty[address % 20\'h80000] <= 0;
r_data <= out_data;
for(i=0; i<64; i=i+1)
begin
#0.001
r_out_read <= 0;
#0.001
if(dirty[address / 64 * 64 + i] === 1)
begin
r_out_address <= tag[(address / 64 * 64 + i) % 20\'h80000];
r_out_data <= dcache[(address / 64 * 64 + i) % 20\'h80000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address / 64 * 64 + i;
r_out_write <= 0;
r_out_data <= 32\'hz;
r_out_read <= 1;
#0.001
dcache[out_address % 20\'h80000] <= out_data;
tag[out_address % 20\'h80000] <= out_address;
dirty[out_address % 20\'h80000] <= 0;
end
r_out_databus <= 64\'b100000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
//r_out_databus <= 64\'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= `DELAY_MEMORY;
r_address <= address;
r_lw_or_sw <= 0;
end
end
always @(negedge read)
begin
r_data <= 32\'hz;
end
always @(posedge write)
begin
r_write_databus <= 0;
if(tag[address % 20\'h80000] === address)
begin
dcache[address % 20\'h80000] <= data;
dirty[address % 20\'h80000] <= 1;
r_out_databus <= 64\'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= 1;
r_address <= address;
r_lw_or_sw <= 1;
r_rs_ex_ok <= 1;
end
else
begin
r_rs_ex_ok <= 0;
if(dirty[address % 20\'h80000] === 1)
begin
r_out_address <= tag[address % 20\'h80000];
r_out_data <= dcache[address % 20\'h80000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_write <= 0;
dcache[address % 20\'h80000] <= data;
tag[address % 20\'h80000] <= address;
dirty[address % 20\'h80000] <= 0;
for(i=0; i<64; i=i+1)
begin
if(address / 64 * 64 + i !== address)
begin
#0.001
if(dirty[address / 64 * 64 + i] === 1)
begin
r_out_address <= tag[(address / 64 * 64 + i) % 20\'h80000];
r_out_data <= dcache[(address / 64 * 64 + i) % 20\'h80000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address / 64 * 64 + i;
r_out_write <= 0;
r_out_data <= 32\'hz;
r_out_read <= 1;
#0.001
dcache[out_address % 20\'h80000] <= out_data;
tag[out_address % 20\'h80000] <= out_address;
dirty[address % 20\'h80000] <= 0;
end
end
r_out_databus <= 64\'b100000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
//r_out_databus <= 64\'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= `DELAY_MEMORY;
r_address <= address;
r_lw_or_sw <= 1;
end
end
endmodule
*/
|
/* Is not working :-( */
`include "DEF.v"
/*
module icachel2(address, data, read, out_address, out_data, out_read);
input [31:0] address;
input [127:0] out_data;
output [127:0] data;
output [31:0] out_address;
input read;
output out_read;
reg [127:0] icache [12\'hFFF:0];
reg [31:0] tag [12\'hFFF:0];
reg [127:0] r_data;
reg [31:0] r_out_address;
reg r_out_read;
integer i;
assign data = r_data;
assign out_read = r_out_read;
assign out_address = r_out_address;
always @(posedge read)
begin
r_out_read <= 0;
if(tag[address % 13\'h1000] === address)
begin
r_data <= icache[address % 13\'h1000];
end
else
begin
r_out_read <= 1;
r_out_address <= address;
#0.001
icache[address % 13\'h1000] <= out_data;
tag[address % 13\'h1000] <= address;
r_data <= out_data;
for(i=0; i<64; i=i+1)
begin
#0.001
r_out_address <= address / 64 * 64 + i;
#0.001
icache[out_address % 13\'h1000] <= out_data;
tag[out_address % 13\'h1000] <= out_address;
end
end
end
endmodule
*/
|
`include "DEF.v"
module excute(clock,
in_op, in_src1, in_src2, in_dst, in_imm,
out_dst, out_dst_data, write_dst,
dmem_address, dmem_data, dmem_write, dmem_read,
cnt_ex, cnt_read, in_databus, in_databus2
);
input clock;
input [31:0] in_op;
input signed [31:0] in_src1, in_src2;
input [4:0] in_dst;
input [31:0] in_imm;
inout [31:0] dmem_data;
input [63:0] in_databus, in_databus2;
output [31:0] dmem_address;
output [4:0] out_dst;
output [31:0] out_dst_data;
output write_dst;
output dmem_write;
output dmem_read;
output cnt_read;
output cnt_ex;
reg [31:0] opcode;
reg signed [31:0] source1, source2;
reg [4:0] destination;
reg signed [31:0] immediate;
reg signed [31:0] result;
reg r_write_dst;
reg r_dmem_write, r_dmem_read;
reg r_cnt_read;
reg r_cnt_ex;
assign out_dst = destination;
assign out_dst_data = result;
assign write_dst = r_write_dst;
assign dmem_write = r_dmem_write;
assign dmem_read = r_dmem_read;
assign dmem_address = immediate;
assign dmem_data = r_dmem_read ? 32\'hz : source2;
assign cnt_read = r_cnt_read;
assign cnt_ex = r_cnt_ex;
always @(posedge clock)
begin
r_cnt_read <= 0;
r_cnt_ex <= 0;
if(in_databus[63:48] !== 16\'b100000_00000_00000 &&
in_databus2[63:48] !== 16\'b100000_00000_00000)
begin
//$display("cycle=%d\
instruction=%d\
", count_cycle, count_instr);
//$stop;
/*#0.001
$display("op:%d result:%d source1:%d source2:%d imm:%d dst:%d\
", opcode, result, source1, source2, immediate, destination);
*/
//$monitor("op:%d result:%d source1:%d source2:%d imm:%d dst:%d\
", opcode, result, source1, source2, immediate, destination);
//$display("r_dmem_write:%d %d\
", r_dmem_write, dmem_write);
//$monitor("r_dmem_write:%d %d\
", r_dmem_write, dmem_write);
#0.001
if(!(opcode === 1 && source2 === 0 && immediate === 0))
begin
r_cnt_ex <= 1;
end
casex(opcode)
1: /* sll */
begin
result <= source2 << immediate;
#0.010 r_write_dst <= 1;
end
2: /* addi */
begin
result <= immediate[15:15]===1 ? source1 - (~{16\'b1111111111111111,immediate[15:0]}+1) : source1 + immediate;
#0.010 r_write_dst <= 1;
end
3: /* mul */
begin
result <= source1 * source2;
/*
#0.001 $display("MUL !!!! %d %d %d\
", result, source1, source2);
$stop;
*/
#0.010 r_write_dst <= 1;
end
4: /* move */
begin
result <= source1;
#0.010 r_write_dst <= 1;
end
5: /* movei */
begin
result <= immediate;
#0.010 r_write_dst <= 1;
end
6: /* add */
begin
result <= source1 + source2;
#0.010 r_write_dst <= 1;
end
9: /* lw */
begin
r_dmem_read <= 1;
//#0.010 $display("dmem_data:%d dmem_read:%d dmem_address:%d\
", dmem_data, dmem_read, dmem_address);
#0.010 result <= dmem_data;
/*
$display("dmem_data:%d dmem_read:%d dmem_address:%d\
", dmem_data, dmem_read, dmem_address);
$stop;
*/
#0.010 r_write_dst <= 1;
end
10: /* sw */
begin
#0.010 r_dmem_write <= 1;
//$display("r_dmem_write:%d %d\
", r_dmem_write, dmem_write);
//$monitor("r_dmem_write:%d %d\
", r_dmem_write, dmem_write);
end
12: /* halt */
begin
#0.001
r_cnt_read <= 1;
#0.498
$display("halt\
");
$stop;
end
13: /* muli */
begin
result <= source1 * (immediate[15:15]==1 ? -(~{16\'b1111111111111111,immediate[15:0]}+1) : immediate);
#0.010 r_write_dst <= 1;
end
14: /* jal */
begin
result <= immediate;
#0.010 r_write_dst <= 1;
//$display("jal31: %d %d\
", destination, result);
//$stop;
end
15: /* ori */
begin
result <= source1 | immediate;
//$display("ori miao!!!!!!! %d %d %d\
", source1, immediate, source1 | immediate);
#0.010 r_write_dst <= 1;
end
16: /* lui */
begin
result <= immediate << 16;
//$display("lui miao!!!!!!! %d %d\
", immediate, immediate << 16);
#0.010 r_write_dst <= 1;
end
endcase
end
end
always @(negedge clock)
begin
#0.010
if(in_databus[63:48] !== 16\'b100000_00000_00000)
begin
opcode <= in_op;
source1 <= in_src1;
source2 <= in_src2;
immediate <= in_imm;
destination <= in_dst;
r_write_dst <= 0;
r_dmem_write <= 0;
r_dmem_read <= 0;
end
end
endmodule
|
`include "DEF.v"
module clock(clk);
output clk;
reg clock;
assign clk = clock;
initial
begin
clock = 0;
end
always #0.500
begin
clock = ~clock;
end
endmodule
|
`include "DEF.v"
module icache(clock, address, data, read, out_address, out_data, out_read, in_databus, out_databus, write_databus);
input clock;
input [31:0] address;
input [127:0] out_data;
input [63:0] in_databus;
output [127:0] data;
output [31:0] out_address;
input read;
output out_read;
output [63:0] out_databus;
output write_databus;
reg [127:0] icache [12\'hFFF:0];
reg [31:0] tag [12\'hFFF:0];
reg [127:0] r_data;
reg [31:0] r_out_address;
reg r_out_read;
reg signed [31:0] r_status;
reg [63:0] r_out_databus;
reg r_write_databus;
integer i;
assign data = r_data;
assign out_read = r_out_read;
assign out_address = r_out_address;
assign out_databus = r_out_databus;
assign write_databus = r_write_databus;
always @(negedge clock)
begin
if(r_status === `DELAY_MEMORY)
begin
r_write_databus <= 1;
end
#0.001
r_status = r_status - 1;
#0.001
if(r_status <= 0)
begin
r_write_databus <= 0;
if(r_status === 0)
begin
if(in_databus[31:0] === 0)
r_out_databus <= 64\'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
else
r_out_databus <= in_databus - 1;
end
#0.001
r_write_databus <= 1;
end
end
always @(posedge read)
begin
r_out_read <= 0;
r_write_databus <= 0;
if(tag[address % 13\'h1000] === address)
begin
r_data <= icache[address % 13\'h1000];
r_out_databus <= in_databus;
r_status <= 0;
end
else
begin
r_out_read <= 1;
r_out_address <= address;
#0.001
icache[address % 13\'h1000] <= out_data;
tag[address % 13\'h1000] <= address;
r_data <= out_data;
for(i=0; i<64; i=i+1)
begin
#0.001
r_out_address <= address / 64 * 64 + i;
#0.001
icache[out_address % 13\'h1000] <= out_data;
tag[out_address % 13\'h1000] <= out_address;
end
if(in_databus[63:48] === 16\'b100000_00000_00000)
r_out_databus <= in_databus + 1;
else
r_out_databus <= 64\'b100000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= `DELAY_MEMORY;
end
end
endmodule
|
`include "DEF.v"
module dcache(clock, address, data, read, write, rs_ex_ok, out_address, out_data, out_read, out_write, in_databus, out_databus, write_databus);
input [31:0] address;
inout [31:0] data, out_data;
input read, write;
input [63:0] in_databus;
input clock;
output [31:0] out_address;
output out_read, out_write;
output [63:0] out_databus;
output write_databus;
output rs_ex_ok;
reg [31:0] dcache [14\'h3FFF:0];
reg [31:0] tag [14\'h3FFF:0];
reg dirty [14\'h3FFF:0];
reg [31:0] r_out_address;
reg [31:0] r_out_data;
reg r_out_read, r_out_write;
reg [31:0] r_data;
reg [63:0] r_out_databus;
reg r_write_databus;
reg signed [31:0] r_status;
reg [31:0] r_address;
reg r_lw_or_sw;
reg r_rs_ex_ok;
integer i;
assign data = r_data;
assign out_read = r_out_read;
assign out_write = r_out_write;
assign out_address = r_out_address;
assign out_data = r_out_data;
assign out_databus = r_out_databus;
assign write_databus = r_write_databus;
assign rs_ex_ok = r_rs_ex_ok;
always @(negedge clock)
begin
if(r_status === `DELAY_MEMORY)
begin
r_write_databus <= 1;
end
#0.001
r_status = r_status - 1;
//#0.001 $display("r_status: %d\
", r_status);
#0.001
if(r_status <= 0)
begin
r_write_databus <= 0;
/*
if(r_status === 0)
begin
if(r_lw_or_sw === 0)
r_out_databus <= {16\'b000000_00000_00001, 16\'b000000_00000_00000, r_address};
else
r_out_databus <= {16\'b000000_00000_00010, 16\'b000000_00000_00000, r_address};
end
else
*/
if(r_status === 0)
begin
if(in_databus[31:0] === 0)
r_out_databus <= 64\'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
else
r_out_databus <= in_databus - 1;
end
#0.001
r_write_databus <= 1;
end
end
always @(posedge read)
begin
r_out_read <= 0;
r_out_write <= 0;
r_write_databus <= 0;
/*
$display("READ!!!!! %d [%d %d %d]\
", address, tag[address % 15\'h4000], dcache[address % 15\'h4000], dirty[address % 15\'h4000]);
$stop;
*/
if(tag[address % 15\'h4000] === address)
begin
r_data <= dcache[address % 15\'h4000];
r_out_databus <= in_databus;
r_status <= 0;
r_address <= address;
r_lw_or_sw <= 0;
r_rs_ex_ok <= 1;
end
else
begin
r_rs_ex_ok <= 0;
//$display("miss \
");
//$stop;
if(dirty[address % 15\'h4000] === 1)
begin
r_out_address <= tag[address % 15\'h4000];
r_out_data <= dcache[address % 15\'h4000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address;
r_out_write <= 0;
r_out_data <= 32\'hz;
r_out_read <= 1;
#0.001
/*
if(address === 14999)
begin
$display("INFO READ!!!! %d %d %d\
", r_out_address, r_out_write, r_out_data);
$stop;
end
*/
dcache[address % 15\'h4000] <= out_data;
tag[address % 15\'h4000] <= address;
dirty[address % 15\'h4000] <= 0;
r_data <= out_data;
/*
$display("READ!!!!!!! %d %d\
", address, out_data);
$stop;
*/
for(i=0; i<64; i=i+1)
begin
#0.001
r_out_read <= 0;
#0.001
if(dirty[address / 64 * 64 + i] === 1)
begin
r_out_address <= tag[(address / 64 * 64 + i) % 15\'h4000];
r_out_data <= dcache[(address / 64 * 64 + i) % 15\'h4000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address / 64 * 64 + i;
r_out_write <= 0;
r_out_data <= 32\'hz;
r_out_read <= 1;
#0.001
dcache[out_address % 15\'h4000] <= out_data;
tag[out_address % 15\'h4000] <= out_address;
dirty[out_address % 15\'h4000] <= 0;
end
if(in_databus[63:48] === 16\'b100000_00000_00000)
r_out_databus <= in_databus + 1;
else
r_out_databus <= 64\'b100000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
//r_out_databus <= 64\'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= `DELAY_MEMORY;
r_address <= address;
r_lw_or_sw <= 0;
end
end
always @(negedge read)
begin
r_data <= 32\'hz;
end
always @(posedge write)
begin
/*
$display("WRITE!!!!! %d %d %d %d\
", address, address*4, data, tag[address % 15\'h4000]);
$stop;
*/
r_write_databus <= 0;
if(tag[address % 15\'h4000] === address)
begin
dcache[address % 15\'h4000] <= data;
dirty[address % 15\'h4000] <= 1;
r_out_databus <= in_databus;
r_status <= 1;
r_address <= address;
r_lw_or_sw <= 1;
r_rs_ex_ok <= 1;
end
else
begin
r_rs_ex_ok <= 0;
if(dirty[address % 15\'h4000] === 1)
begin
r_out_address <= tag[address % 15\'h4000];
r_out_data <= dcache[address % 15\'h4000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_write <= 0;
dcache[address % 15\'h4000] <= data;
tag[address % 15\'h4000] <= address;
dirty[address % 15\'h4000] <= 0;
for(i=0; i<64; i=i+1)
begin
if(address / 64 * 64 + i !== address)
begin
#0.001
if(dirty[address / 64 * 64 + i] === 1)
begin
r_out_address <= tag[(address / 64 * 64 + i) % 15\'h4000];
r_out_data <= dcache[(address / 64 * 64 + i) % 15\'h4000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address / 64 * 64 + i;
r_out_write <= 0;
r_out_data <= 32\'hz;
r_out_read <= 1;
#0.001
dcache[out_address % 15\'h4000] <= out_data;
tag[out_address % 15\'h4000] <= out_address;
dirty[address % 15\'h4000] <= 0;
end
end
if(in_databus[63:48] === 16\'b100000_00000_00000)
r_out_databus <= in_databus + 1;
else
r_out_databus <= 64\'b100000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
//r_out_databus <= 64\'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= `DELAY_MEMORY;
r_address <= address;
r_lw_or_sw <= 1;
end
end
endmodule
|
`include "DEF.v"
module register(data1, reg_number1, /*enable1,*/ read1,
data2, reg_number2, /*enable2,*/ read2,
data3, reg_number3, /*enable3,*/ write3,
data4, reg_number4, /*enable1,*/ read4,
data5, reg_number5, /*enable2,*/ read5,
data6, reg_number6, /*enable3,*/ write6,
data7, reg_number7, /*enable1,*/ read7,
data8, reg_number8, /*enable2,*/ read8,
data9, reg_number9, /*enable3,*/ write9,
data10, reg_number10, /*enable1,*/ read10,
data11, reg_number11, /*enable2,*/ read11,
data12, reg_number12, /*enable3,*/ write12,
data13, reg_number13, write13
);
output [31:0] data1, data2, data4, data5, data7, data8, data10, data11;
input [31:0] data3, data6, data9, data12, data13;
input [4:0] reg_number1, reg_number2, reg_number3, reg_number4, reg_number5, reg_number6,
reg_number7, reg_number8, reg_number9, reg_number10, reg_number11, reg_number12,
reg_number13;
//input enable1, enable2, enable3;
input read1, read2, read4, read5, read7, read8, read10, read11;
input write3, write6, write9, write12, write13;
reg signed [31:0] register [31:0];
assign data1 = (/*enable1 &&*/ read1) ? register[reg_number1] : 32\'hz;
assign data2 = (/*enable2 &&*/ read2) ? register[reg_number2] : 32\'hz;
assign data4 = (/*enable1 &&*/ read4) ? register[reg_number4] : 32\'hz;
assign data5 = (/*enable2 &&*/ read5) ? register[reg_number5] : 32\'hz;
assign data7 = (/*enable1 &&*/ read7) ? register[reg_number7] : 32\'hz;
assign data8 = (/*enable2 &&*/ read8) ? register[reg_number8] : 32\'hz;
assign data10 = (/*enable1 &&*/ read10) ? register[reg_number10] : 32\'hz;
assign data11 = (/*enable2 &&*/ read11) ? register[reg_number11] : 32\'hz;
always @(posedge write3)
begin
//$display("reg%d data:%d\
", reg_number3, data3);
/*
if(data3 === \'bx)
begin
$display("reg%d: %d\
", reg_number3, data3);
$stop;
end
*/
/*
if(reg_number3 === 31)
$display("reg ra data: %d\
", data3);
*/
register[reg_number3] <= data3;
end
always @(posedge write6)
begin
//$display("reg%d data:%d\
", reg_number6, data6);
register[reg_number6] <= data6;
end
always @(posedge write9)
begin
//$display("reg%d data:%d\
", reg_number9, data9);
register[reg_number9] <= data9;
end
always @(posedge write12)
begin
//$display("reg%d data:%d\
", reg_number12, data12);
register[reg_number12] <= data12;
end
always @(posedge write13)
begin
//$display("reg%d data:%d\
", reg_number13, data13);
register[reg_number13] <= data13;
end
endmodule
|
`include "CLOCK.v"
`include "DCACHE.v"
`include "DMEMORY.v"
`include "ICACHE.v"
`include "IMEMORY.v"
`include "EX.v"
`include "IF.v"
`include "PC.v"
`include "REGISTER.v"
`include "DEF.v"
`include "RS.v"
`include "DCACHEL2.v"
`include "ICACHEL2.v"
`include "CNT.v"
module cpu();
wire clock;
wire [31:0] pc_address, nxt_address;
wire [31:0] if_out_op1, if_out_op2, if_out_op3, if_out_op4;
wire [31:0] if_out_src11, if_out_src12;
wire [31:0] if_out_src21, if_out_src22;
wire [31:0] if_out_src31, if_out_src32;
wire [31:0] if_out_src41, if_out_src42;
wire [31:0] if_out_imm1, if_out_imm2, if_out_imm3, if_out_imm4;
wire [4:0] if_out_dst1, if_out_dst2, if_out_dst3, if_out_dst4;
wire [31:0] if_in_src11, if_in_src12;
wire [31:0] if_in_src21, if_in_src22;
wire [31:0] if_in_src31, if_in_src32;
wire [31:0] if_in_src41, if_in_src42;
wire [127:0] imem_data;
wire [31:0] imem_address;
wire imem_read;
wire [127:0] imem_out_data;
wire [31:0] imem_out_address;
wire imem_out_read;
wire if_read_src11, if_read_src12;
wire if_read_src21, if_read_src22;
wire if_read_src31, if_read_src32;
wire if_read_src41, if_read_src42;
wire [4:0] if_out_srcn11, if_out_srcn12;
wire [4:0] if_out_srcn21, if_out_srcn22;
wire [4:0] if_out_srcn31, if_out_srcn32;
wire [4:0] if_out_srcn41, if_out_srcn42;
wire write_pc;
wire [31:0] dmem_data, dmem_address;
wire [31:0] dmem_out_data, dmem_out_address;
wire [31:0] dmem_out_datal2, dmem_out_addressl2;
wire [4:0] ex_out_dst1, ex_out_dst2, ex_out_dst3, ex_out_dst4;
wire [31:0] ex_out_dst_data1, ex_out_dst_data2, ex_out_dst_data3, ex_out_dst_data4;
wire write_dst1, write_dst2, write_dst3, write_dst4;
wire dmem_write4, dmem_read4;
wire dmem_out_write, dmem_out_read;
wire dmem_out_writel2, dmem_out_readl2;
wire [63:0] cdb_databus, cdb_data;
wire [63:0] cdb_databus2, cdb_data2;
wire cdb_write;
wire cdb_write2;
wire [31:0] rs_in_op, rs_in_address;
wire [4:0] rs_rg_num, rs_in_reg, rs_in_reg2;
wire rs_rg_ok, rs_rs_free, rs_rg_check, rs_write;
wire rs_ex_ok;
wire cnt_ex1, cnt_ex2, cnt_ex3, cnt_ex4;
wire cnt_read1, cnt_read2, cnt_read3, cnt_read4;
integer i;
reg [7:0] tmp [26\'h3FFFFFF:0];
clock cpu_clock(.clk(clock));
//dmemory cpu_dmemory(.address(dmem_address), .data(dmem_data), /*.enable*/.read(dmem_read), .write(dmem_write));
//dmemory cpu_dmemory(.address(dmem_out_addressl2), .data(dmem_out_datal2), /*.enable*/.read(dmem_out_readl2), .write(dmem_out_writel2));
dmemory cpu_dmemory(.address(dmem_out_address), .data(dmem_out_data), /*.enable*/.read(dmem_out_read), .write(dmem_out_write));
//imemory cpu_imemory(.address(imem_address), .data(imem_data), /*.enable*/.read(imem_read));
imemory cpu_imemory(.address(imem_out_address), .data(imem_out_data), /*.enable*/.read(imem_out_read));
excute cpu_excute1(.clock(clock),
.in_op(if_out_op1), .in_src1(if_out_src11), .in_src2(if_out_src12),
.in_dst(if_out_dst1), .in_imm(if_out_imm1),
.out_dst(ex_out_dst1), .out_dst_data(ex_out_dst_data1), .write_dst(write_dst1), .cnt_ex(cnt_ex1), .cnt_read(cnt_read1),
/*.dmem_address(dmem_address), .dmem_data(dmem_data),*/ .in_databus(cdb_databus), .in_databus2(cdb_databus2));
excute cpu_excute2(.clock(clock),
.in_op(if_out_op2), .in_src1(if_out_src21), .in_src2(if_out_src22),
.in_dst(if_out_dst2), .in_imm(if_out_imm2),
.out_dst(ex_out_dst2), .out_dst_data(ex_out_dst_data2), .write_dst(write_dst2), .cnt_ex(cnt_ex2), .cnt_read(cnt_read2),
/*.dmem_address(dmem_address), .dmem_data(dmem_data),*/ .in_databus(cdb_databus), .in_databus2(cdb_databus2));
excute cpu_excute3(.clock(clock),
.in_op(if_out_op3), .in_src1(if_out_src31), .in_src2(if_out_src32),
.in_dst(if_out_dst3), .in_imm(if_out_imm3),
.out_dst(ex_out_dst3), .out_dst_data(ex_out_dst_data3), .write_dst(write_dst3), .cnt_ex(cnt_ex3), .cnt_read(cnt_read3),
/*.dmem_address(dmem_address), .dmem_data(dmem_data),*/ .in_databus(cdb_databus), .in_databus2(cdb_databus2));
excute cpu_excute4(.clock(clock),
.in_op(if_out_op4), .in_src1(if_out_src41), .in_src2(if_out_src42),
.in_dst(if_out_dst4), .in_imm(if_out_imm4),
.out_dst(ex_out_dst4), .out_dst_data(ex_out_dst_data4), .write_dst(write_dst4), .cnt_ex(cnt_ex4), .cnt_read(cnt_read4),
.dmem_address(dmem_address), .dmem_data(dmem_data), .dmem_write(dmem_write4), .dmem_read(dmem_read4), .in_databus(cdb_databus), .in_databus2(cdb_databus2));
ifetch cpu_ifetch(.clock(clock),
.imem_address(imem_address), .imem_data(imem_data), .imem_read(imem_read),
.pc_address(pc_address), .nxt_address(nxt_address), .write_pc(write_pc),
.out_op1(if_out_op1), .out_src11(if_out_src11), .out_src12(if_out_src12), .out_dst1(if_out_dst1), .out_imm1(if_out_imm1),
.out_srcn11(if_out_srcn11), .out_srcn12(if_out_srcn12), .in_src11(if_in_src11), .in_src12(if_in_src12), .read_src11(if_read_src11), .read_src12(if_read_src12),
.out_op2(if_out_op2), .out_src21(if_out_src21), .out_src22(if_out_src22), .out_dst2(if_out_dst2), .out_imm2(if_out_imm2),
.out_srcn21(if_out_srcn21), .out_srcn22(if_out_srcn22), .in_src21(if_in_src21), .in_src22(if_in_src22), .read_src21(if_read_src21), .read_src22(if_read_src22),
.out_op3(if_out_op3), .out_src31(if_out_src31), .out_src32(if_out_src32), .out_dst3(if_out_dst3), .out_imm3(if_out_imm3),
.out_srcn31(if_out_srcn31), .out_srcn32(if_out_srcn32), .in_src31(if_in_src31), .in_src32(if_in_src32), .read_src31(if_read_src31), .read_src32(if_read_src32),
.out_op4(if_out_op4), .out_src41(if_out_src41), .out_src42(if_out_src42), .out_dst4(if_out_dst4), .out_imm4(if_out_imm4),
.out_srcn41(if_out_srcn41), .out_srcn42(if_out_srcn42), .in_src41(if_in_src41), .in_src42(if_in_src42), .read_src41(if_read_src41), .read_src42(if_read_src42),
.rg_check_ok(rs_rg_ok), .rg_check_num(rs_rg_num), .rg_check(rs_rg_check), .rs_op(rs_in_op), .rs_address(rs_in_address), .rs_reg(rs_in_reg), .rs_reg2(rs_in_reg2), .rs_write(rs_write), .rs_free(rs_rs_free), .rs_ex_ok(rs_ex_ok), .in_databus(cdb_databus), .in_databus2(cdb_databus2));
register cpu_register(.data1(if_in_src11), .reg_number1(if_out_srcn11), /*.enable1*/.read1(if_read_src11),
.data2(if_in_src12), .reg_number2(if_out_srcn12), /*.enable2*/.read2(if_read_src12),
.data4(if_in_src21), .reg_number4(if_out_srcn21), /*.enable1*/.read4(if_read_src21),
.data5(if_in_src22), .reg_number5(if_out_srcn22), /*.enable2*/.read5(if_read_src22),
.data7(if_in_src31), .reg_number7(if_out_srcn31), /*.enable1*/.read7(if_read_src31),
.data8(if_in_src32), .reg_number8(if_out_srcn32), /*.enable2*/.read8(if_read_src32),
.data10(if_in_src41), .reg_number10(if_out_srcn41), /*.enable1*/.read10(if_read_src41),
.data11(if_in_src42), .reg_number11(if_out_srcn42), /*.enable2*/.read11(if_read_src42),
.data3(ex_out_dst_data1), .reg_number3(ex_out_dst1), /*.enable3*/.write3(write_dst1),
.data6(ex_out_dst_data2), .reg_number6(ex_out_dst2), /*.enable3*/.write6(write_dst2),
.data9(ex_out_dst_data3), .reg_number9(ex_out_dst3), /*.enable3*/.write9(write_dst3),
.data12(ex_out_dst_data4), .reg_number12(ex_out_dst4), /*.enable3*/.write12(write_dst4)
);
pc cpu_pc(.pc_address(pc_address), .nxt_address(nxt_address), .write(write_pc));
icache cpu_icache(.clock(clock), .address(imem_address), .data(imem_data), .read(imem_read), .out_address(imem_out_address), .out_data(imem_out_data), .out_read(imem_out_read), .in_databus(cdb_databus2), .out_databus(cdb_data2), .write_databus(cdb_write2));
dcache cpu_dcache(.clock(clock), .address(dmem_address), .data(dmem_data), .read(dmem_read4), .write(dmem_write4), .out_address(dmem_out_address), .out_data(dmem_out_data), .out_read(dmem_out_read), .out_write(dmem_out_write), .rs_ex_ok(rs_ex_ok), .in_databus(cdb_databus), .out_databus(cdb_data), .write_databus(cdb_write));
cdb cpu_cdb(.databus(cdb_databus), .data(cdb_data), .write(cdb_write), .databus2(cdb_databus2),.data2(cdb_data2), .write2(cdb_write2));
rs cpu_rs(.clock(clock), .rs_free(rs_rs_free), .rg_ok(rs_rg_ok), .rg_num(rs_rg_num), .rg_check(rs_rg_check), .in_op(rs_in_op), .in_address(rs_in_address), .in_reg(rs_in_reg), .in_reg2(rs_in_reg2), .write(rs_write), .in_databus(cdb_databus));
// dcachel2 cpu_dcachel2(.clock(clock), .address(dmem_out_address), .data(dmem_out_data), .read(dmem_out_read), .write(dmem_out_write), .out_address(dmem_out_addressl2), .out_data(dmem_out_datal2), .out_read(dmem_out_readl2), .out_write(dmem_out_writel2), .rs_ex_ok(rs_ex_ok), .in_databus(cdb_databus), .out_databus(cdb_data), .write_databus(cdb_write));
cnt cpu_cnt(.clock(clock), .ex1(cnt_ex1), .ex2(cnt_ex2), .ex3(cnt_ex3), .ex4(cnt_ex4), .read1(cnt_read1), .read2(cnt_read2), .read3(cnt_read3), .read4(cnt_read4));
task program;
begin
cpu_pc.r_pc_address = 0;
cpu_register.register[0] = 0;
cpu_register.register[28] = 0;
for(i=0; i<24\'hFFFFFF; i=i+1)
begin
tmp[i*4] = 0;
tmp[i*4+1] = 0;
tmp[i*4+2] = 0;
tmp[i*4+3] = 0;
end
cpu_rs.r_rs_lok = 0;
cpu_rs.r_rs_sok = 0;
cpu_rs.r_rs_free = 1;
for(i=0; i<32; i=i+1)
begin
cpu_rs.reg_status[i] = 0;
end
for(i=0; i<4; i=i+1)
begin
cpu_rs.rs_load_busy[i] = 0;
cpu_rs.rs_store_busy[i] = 0;
end
$readmemb("program.s", cpu_imemory.imemory);
$readmemh("ram_data.txt", tmp);
for(i=0; i<24\'hFFFFFF; i=i+1)
begin
cpu_dmemory.dmemory[i] = {tmp[i*4+0], tmp[i*4+1], tmp[i*4+2], tmp[i*4+3]};
end
//$monitor("mem: %d %d", cpu_dmemory.dmemory[0], cpu_dmemory.dmemory[2]);
//$monitor("dmem_write: %d\
", dmem_write);
//$display("%d %d %d\
", cpu_imemory.imemory[0], cpu_imemory.imemory[1], cpu_imemory.imemory[2]);
//$monitor("register: (pc=%d) %d %d\
", cpu_pc.pc_address, cpu_register.register[0], cpu_register.register[1]);
//$monitor("if_out_srcn1: %d if_out_srcn2: %d\
", if_out_srcn1, if_out_srcn2);
//$monitor("if_in_src1: %d if_in_src2: %d\
", if_in_src1, if_in_src2);
//#1.000;
end
endtask
initial
begin
program;
end
always #0.001
begin
if(imem_data[127:96] === 32\'b111111_11111_11111_1111111111111111 ||
imem_data[95:64] === 32\'b111111_11111_11111_1111111111111111 ||
imem_data[63:32] === 32\'b111111_11111_11111_1111111111111111 ||
imem_data[31:0] === 32\'b111111_11111_11111_1111111111111111)
begin
/*
for(i=0; i<20\'h80000; i=i+1)
begin
if(cpu_dcachel2.dirty[i] === 1)
begin
cpu_dmemory.dmemory[cpu_dcachel2.tag[i]] <= cpu_dcachel2.dcache[i];
cpu_dcachel2.dirty[i] <= 0;
end
end
*/
for(i=0; i<15\'h4000; i=i+1)
begin
if(cpu_dcache.dirty[i] === 1)
begin
cpu_dmemory.dmemory[cpu_dcache.tag[i]] <= cpu_dcache.dcache[i];
cpu_dcache.dirty[i] <= 0;
end
end
#0.001
$display("writing to file...\
");
$writememh("output.d", cpu_dmemory.dmemory);
#1.000;
end
end
endmodule
|
module cnt(clock, ex1, ex2, ex3, ex4, read1, read2, read3, read4);
input clock;
input ex1, ex2, ex3, ex4;
input read1, read2, read3, read4;
real cycle; //should be set to zero
real instr1, instr2, instr3, instr4; //should be set to zero
always @(posedge clock)
begin
cycle <= cycle + 1;
end
always @(posedge ex1)
begin
instr1 <= instr1 + 1;
end
always @(posedge ex2)
begin
instr2 <= instr2 + 1;
end
always @(posedge ex3)
begin
instr3 <= instr3 + 1;
end
always @(posedge ex4)
begin
instr4 <= instr4 + 1;
end
always @(posedge read1 or posedge read2 or posedge read3 or posedge read4)
begin
$display("The number of instructions: %.0f\
", instr1+instr2+instr3+instr4);
$display("The number of cycles: %.0f\
", cycle);
$display("IPC(Instructions Per Cycle) = %f\
", (instr1+instr2+instr3+instr4)/cycle);
end
endmodule
|
`include "DEF.v"
module ifetch(clock,
imem_address, imem_data, imem_read,
pc_address, nxt_address, write_pc,
out_op1, out_src11, out_src12, out_dst1, out_imm1,
out_srcn11, out_srcn12, in_src11, in_src12, read_src11, read_src12,
out_op2, out_src21, out_src22, out_dst2, out_imm2,
out_srcn21, out_srcn22, in_src21, in_src22, read_src21, read_src22,
out_op3, out_src31, out_src32, out_dst3, out_imm3,
out_srcn31, out_srcn32, in_src31, in_src32, read_src31, read_src32,
out_op4, out_src41, out_src42, out_dst4, out_imm4,
out_srcn41, out_srcn42, in_src41, in_src42, read_src41, read_src42,
rg_check_ok, rg_check_num, rg_check, rs_op, rs_address, rs_reg, rs_reg2, rs_write, rs_free, rs_ex_ok, in_databus, in_databus2);
input clock;
input [31:0] pc_address;
input signed [31:0] in_src11, in_src12;
input signed [31:0] in_src21, in_src22;
input signed [31:0] in_src31, in_src32;
input signed [31:0] in_src41, in_src42;
input signed [127:0] imem_data;
input [63:0] in_databus, in_databus2;
input rg_check_ok;
input rs_free;
input rs_ex_ok;
output [31:0] nxt_address;
output write_pc;
output [31:0] out_op1, out_op2, out_op3, out_op4;
output [31:0] out_src11, out_src12;
output [31:0] out_src21, out_src22;
output [31:0] out_src31, out_src32;
output [31:0] out_src41, out_src42;
output [4:0] out_dst1, out_dst2, out_dst3, out_dst4;
output [31:0] out_imm1, out_imm2, out_imm3, out_imm4;
output [4:0] out_srcn11, out_srcn12;
output [4:0] out_srcn21, out_srcn22;
output [4:0] out_srcn31, out_srcn32;
output [4:0] out_srcn41, out_srcn42;
output read_src11, read_src12;
output read_src21, read_src22;
output read_src31, read_src32;
output read_src41, read_src42;
output [31:0] imem_address;
output imem_read;
output [4:0] rg_check_num;
output rg_check;
output [31:0] rs_op, rs_address;
output [4:0] rs_reg, rs_reg2;
output rs_write;
reg [31:0] opcode[3:0];
reg [4:0] source1[3:0];
reg [4:0] source2[3:0];
reg [4:0] destination[3:0];
reg signed [31:0] immediate[3:0];
reg [31:0] address;
reg r_write_pc, r_read_src1[3:0], r_read_src2[3:0];
reg r_imem_read;
reg jmp_status;
reg r_rg_check;
reg [4:0] r_rg_check_num;
reg r_rg_check_result;
reg r_rs_write;
reg [4:0] r_rs_reg, r_rs_reg2;
assign out_op1 = opcode[0];
assign out_op2 = opcode[1];
assign out_op3 = opcode[2];
assign out_op4 = opcode[3];
assign out_srcn11 = source1[0];
assign out_srcn12 = source2[0];
assign out_srcn21 = source1[1];
assign out_srcn22 = source2[1];
assign out_srcn31 = source1[2];
assign out_srcn32 = source2[2];
assign out_srcn41 = source1[3];
assign out_srcn42 = source2[3];
assign out_src11 = in_src11;
assign out_src12 = in_src12;
assign out_src21 = in_src21;
assign out_src22 = in_src22;
assign out_src31 = in_src31;
assign out_src32 = in_src32;
assign out_src41 = in_src41;
assign out_src42 = in_src42;
assign out_dst1 = destination[0];
assign out_dst2 = destination[1];
assign out_dst3 = destination[2];
assign out_dst4 = destination[3];
assign out_imm1 = immediate[0];
assign out_imm2 = immediate[1];
assign out_imm3 = immediate[2];
assign out_imm4 = immediate[3];
assign imem_address = pc_address;
assign nxt_address = address;
assign write_pc = r_write_pc;
assign read_src11 = r_read_src1[0];
assign read_src12 = r_read_src2[0];
assign read_src21 = r_read_src1[1];
assign read_src22 = r_read_src2[1];
assign read_src31 = r_read_src1[2];
assign read_src32 = r_read_src2[2];
assign read_src41 = r_read_src1[3];
assign read_src42 = r_read_src2[3];
assign imem_read = r_imem_read;
assign rg_check = r_rg_check;
assign rg_check_num = r_rg_check_num;
assign rs_write = r_rs_write;
assign rs_reg = r_rs_reg;
assign rs_reg2 = r_rs_reg2;
assign rs_address = immediate[3];
assign rs_op = opcode[3];
task check_source10;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= source1[0];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_source11;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= source1[1];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_source12;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= source1[2];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_source13;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= source1[3];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_source20;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= source2[0];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_source21;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= source2[1];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_source22;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= source2[2];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_source23;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= source2[3];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_destination0;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= destination[0];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_destination1;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= destination[1];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_destination2;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= destination[2];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
task check_destination3;
begin
#0.001
r_rg_check <= 0;
r_rg_check_num <= destination[3];
#0.001 r_rg_check <= 1;
#0.001 r_rg_check_result <= r_rg_check_result | rg_check_ok;
end
endtask
always @(posedge clock)
begin
r_rs_write <= 0;
if(in_databus[63:48] !== 16\'b100000_00000_00000 &&
in_databus2[63:48] !== 16\'b100000_00000_00000)
begin
r_imem_read <= 0;
#0.010
r_read_src1[0] <= 1;
r_read_src2[0] <= 1;
r_read_src1[1] <= 1;
r_read_src2[1] <= 1;
r_read_src1[2] <= 1;
r_read_src2[2] <= 1;
r_read_src1[3] <= 1;
r_read_src2[3] <= 1;
r_imem_read <= 1;
jmp_status <= 0;
r_rg_check_result <= 0;
/*
#0.001
$display("%d %d\
", pc_address, imem_data);
$stop;
*/
#0.010 casex(imem_data[31:0])
/* //nop
32\'b000000_00000_00000_00000_00000_000000:
begin
opcode <= 0;
r_write_pc <= 0;
address <= pc_address + 1;
#0.010 r_write_pc <= 1;
end
*/
32\'b000000_xxxxx_xxxxx_xxxxx_xxxxx_000000: /* sll rt rd shamt */
begin
opcode[0] <= 1;
source2[0] <= imem_data[20:16];
destination[0] <= imem_data[15:11];
immediate[0] <= imem_data[10:6];
check_source20;
check_destination0;
end
32\'b000000_xxxxx_xxxxx_xxxxx_00000_100000: /* add rs rt rd */
begin
opcode[0] <= 6;
source1[0] <= imem_data[25:21];
source2[0] <= imem_data[20:16];
destination[0] <= imem_data[15:11];
check_source10;
check_source20;
check_destination0;
end
32\'b000000_xxxxx_000000000000000_001000: /* jr rs */
begin
opcode[0] <= 7;
source1[0] <= imem_data[25:21];
#0.010 address <= in_src11;
jmp_status <= 1;
check_source10;
end
32\'b000010_xxxxxxxxxxxxxxxxxxxxxxxxxx: /* j target */
begin
opcode[0] <= 11;
immediate[0] <= imem_data[25:0];
address <= imem_data[25:0];
jmp_status <= 1;
end
32\'b000011_xxxxxxxxxxxxxxxxxxxxxxxxxx: /* jal target */
begin
opcode[0] <= 14;
immediate[0] <= pc_address + 1;
destination[0] <= 31;
address <= imem_data[25:0];
jmp_status <= 1;
check_destination0;
end
32\'b001000_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* addi rs rt imm */
begin
opcode[0] <= 2;
source1[0] <= imem_data[25:21];
destination[0] <= imem_data[20:16];
immediate[0] <= imem_data[15:0];
check_source10;
check_destination0;
end
32\'b011000_xxxxx_xxxxx_xxxxx_00000000000: /* mul rs rt rd */
begin
opcode[0] <= 3;
source1[0] <= imem_data[25:21];
source2[0] <= imem_data[20:16];
destination[0] <= imem_data[15:11];
/*
#0.001 $display("MUL IF !!!! %d %d %d\
", source1[0], source2[0], destination[0]);
$stop;
*/
check_source10;
check_source20;
check_destination0;
end
32\'b001111_00000_xxxxx_xxxxxxxxxxxxxxxx: /* lui rt imm */
begin
opcode[0] <= 16;
destination[0] <= imem_data[20:16];
immediate[0] <= imem_data[15:0];
check_destination0;
end
32\'b011011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* muli rs rt imm */
begin
opcode[0] <= 13;
source1[0] <= imem_data[25:21];
destination[0] <= imem_data[20:16];
immediate[0] <= imem_data[15:0];
check_source10;
check_destination0;
end
32\'b001101_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* ori rs rt imm */
begin
opcode[0] <= 15;
source1[0] <= imem_data[25:21];
destination[0] <= imem_data[20:16];
immediate[0] <= imem_data[15:0];
check_source10;
check_destination0;
end
32\'b011001_xxxxx_xxxxx_000000000000000_0: /* move rs rt */
begin
opcode[0] <= 4;
source1[0] <= imem_data[25:21];
destination[0] <= imem_data[20:16];
check_source10;
check_destination0;
end
32\'b011001_xxxxx_xxxxxxxxxxxxxxxxxxxx_1: /* movei rs imm */
begin
opcode[0] <= 5;
destination[0] <= imem_data[25:21];
immediate[0] <= imem_data[20:1];
check_destination0;
end
32\'b011010_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* bge rs rt offset */
begin
opcode[0] <= 8;
source1[0] <= imem_data[25:21];
source2[0] <= imem_data[20:16];
immediate[0] <= imem_data[15:0];
#0.010 if(in_src11 >= in_src12)
begin
address <= imem_data[15:15] == 1 ? pc_address - (~{16\'b1111111111111111, imem_data[15:0]}+1) + 1 : pc_address + {16\'b0, imem_data[15:0]} + 1;
jmp_status <= 1;
end
check_source10;
check_source20;
end
32\'b100011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* lw rs rt offset */
begin
opcode[0] <= 9;
destination[0] <= imem_data[20:16];
source1[0] <= imem_data[25:21];
#0.010 immediate[0] <= imem_data[15:15] == 1 ? in_src11/4 - (~{16\'b1111111111111111, imem_data[15:0]}+1) : in_src11/4 + {16\'b0, imem_data[15:0]};
check_source10;
check_destination0;
end
32\'b101011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* sw rs rt offset */
begin
opcode[0] <= 10;
source1[0] <= imem_data[25:21];
source2[0] <= imem_data[20:16];
#0.010
immediate[0] <= imem_data[15:15] == 1 ? in_src11/32\'h4 - (~{16\'b1111111111111111, imem_data[15:0]}+32\'h1) : in_src11/32\'h4 + {16\'b0, imem_data[15:0]};
check_source10;
check_source20;
end
32\'b111111_11111_11111_1111111111111111: /* halt */
begin
opcode[0] <= 12;
address <= pc_address;
jmp_status <= 1;
end
default:
begin
opcode[0] <= 0;
end
endcase
#0.010 casex(imem_data[31+32:0+32])
/* //nop
32\'b000000_00000_00000_00000_00000_000000:
begin
opcode <= 0;
r_write_pc <= 0;
address <= pc_address + 1;
#0.010 r_write_pc <= 1;
end
*/
32\'b000000_xxxxx_xxxxx_xxxxx_xxxxx_000000: /* sll rt rd shamt */
begin
opcode[1] <= 1;
source2[1] <= imem_data[20+32:16+32];
destination[1] <= imem_data[15+32:11+32];
immediate[1] <= imem_data[10+32:6+32];
check_source21;
check_destination1;
end
32\'b000000_xxxxx_xxxxx_xxxxx_00000_100000: /* add rs rt rd */
begin
opcode[1] <= 6;
source1[1] <= imem_data[25+32:21+32];
source2[1] <= imem_data[20+32:16+32];
destination[1] <= imem_data[15+32:11+32];
check_source11;
check_source21;
check_destination1;
end
32\'b000000_xxxxx_000000000000000_001000: /* jr rs */
begin
opcode[1] <= 7;
source1[1] <= imem_data[25+32:21+32];
#0.010 address <= in_src21;
jmp_status <= 1;
check_source11;
end
32\'b000010_xxxxxxxxxxxxxxxxxxxxxxxxxx: /* j target */
begin
opcode[1] <= 11;
immediate[1] <= imem_data[25+32:0+32];
address <= imem_data[25+32:0+32];
jmp_status <= 1;
end
32\'b000011_xxxxxxxxxxxxxxxxxxxxxxxxxx: /* jal target */
begin
opcode[1] <= 14;
immediate[1] <= pc_address + 1;
destination[1] <= 31;
address <= imem_data[25+32:0+32];
jmp_status <= 1;
check_destination1;
end
32\'b001000_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* addi rs rt imm */
begin
opcode[1] <= 2;
source1[1] <= imem_data[25+32:21+32];
destination[1] <= imem_data[20+32:16+32];
immediate[1] <= imem_data[15+32:0+32];
check_source11;
check_destination1;
end
32\'b011000_xxxxx_xxxxx_xxxxx_00000000000: /* mul rs rt rd */
begin
opcode[1] <= 3;
source1[1] <= imem_data[25+32:21+32];
source2[1] <= imem_data[20+32:16+32];
destination[1] <= imem_data[15+32:11+32];
/*
#0.001 $display("MUL IF !!!! %d %d %d\
", source1[1], source2[1], destination[1]);
$stop;
*/
check_source11;
check_source21;
check_destination1;
end
32\'b001111_00000_xxxxx_xxxxxxxxxxxxxxxx: /* lui rt imm */
begin
opcode[1] <= 16;
destination[1] <= imem_data[20+32:16+32];
immediate[1] <= imem_data[15+32:0+32];
check_destination1;
end
32\'b011011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* muli rs rt imm */
begin
opcode[1] <= 13;
source1[1] <= imem_data[25+32:21+32];
destination[1] <= imem_data[20+32:16+32];
immediate[1] <= imem_data[15+32:0+32];
check_source11;
check_destination1;
end
32\'b001101_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* ori rs rt imm */
begin
opcode[1] <= 15;
source1[1] <= imem_data[25+32:21+32];
destination[1] <= imem_data[20+32:16+32];
immediate[1] <= imem_data[15+32:0+32];
check_source11;
check_destination1;
end
32\'b011001_xxxxx_xxxxx_000000000000000_0: /* move rs rt */
begin
opcode[1] <= 4;
source1[1] <= imem_data[25+32:21+32];
destination[1] <= imem_data[20+32:16+32];
check_source11;
check_destination1;
end
32\'b011001_xxxxx_xxxxxxxxxxxxxxxxxxxx_1: /* movei rs imm */
begin
opcode[1] <= 5;
destination[1] <= imem_data[25+32:21+32];
immediate[1] <= imem_data[20+32:1+32];
check_destination1;
end
32\'b011010_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* bge rs rt offset */
begin
opcode[1] <= 8;
source1[1] <= imem_data[25+32:21+32];
source2[1] <= imem_data[20+32:16+32];
immediate[1] <= imem_data[15+32:0+32];
#0.010 if(in_src21 >= in_src22)
begin
address <= imem_data[15+32:15+32] == 1 ? pc_address - (~{16\'b1111111111111111, imem_data[15+32:0+32]}+1) + 1 : pc_address + {16\'b0, imem_data[15+32:0+32]} + 1;
jmp_status <= 1;
end
check_source11;
check_source21;
end
32\'b100011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* lw rs rt offset */
begin
opcode[1] <= 9;
destination[1] <= imem_data[20+32:16+32];
source1[1] <= imem_data[25+32:21+32];
#0.010 immediate[1] <= imem_data[15+32:15+32] == 1 ? in_src21/4 - (~{16\'b1111111111111111, imem_data[15+32:0+32]}+1) : in_src21/4 + {16\'b0, imem_data[15+32:0+32]};
check_source11;
check_destination1;
end
32\'b101011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* sw rs rt offset */
begin
opcode[1] <= 10;
source1[1] <= imem_data[25+32:21+32];
source2[1] <= imem_data[20+32:16+32];
#0.010
immediate[1] <= imem_data[15+32:15+32] == 1 ? in_src21/32\'h4 - (~{16\'b1111111111111111, imem_data[15+32:0+32]}+32\'h1) : in_src21/32\'h4 + {16\'b0, imem_data[15+32:0+32]};
check_source11;
check_source21;
end
32\'b111111_11111_11111_1111111111111111: /* halt */
begin
opcode[1] <= 12;
address <= pc_address;
jmp_status <= 1;
end
default:
begin
opcode[1] <= 0;
end
endcase
#0.010 casex(imem_data[31+64:0+64])
/* //nop
32\'b000000_00000_00000_00000_00000_000000:
begin
opcode <= 0;
r_write_pc <= 0;
address <= pc_address + 1;
#0.010 r_write_pc <= 1;
end
*/
32\'b000000_xxxxx_xxxxx_xxxxx_xxxxx_000000: /* sll rt rd shamt */
begin
opcode[2] <= 1;
source2[2] <= imem_data[20+64:16+64];
destination[2] <= imem_data[15+64:11+64];
immediate[2] <= imem_data[10+64:6+64];
check_source22;
check_destination2;
end
32\'b000000_xxxxx_xxxxx_xxxxx_00000_100000: /* add rs rt rd */
begin
opcode[2] <= 6;
source1[2] <= imem_data[25+64:21+64];
source2[2] <= imem_data[20+64:16+64];
destination[2] <= imem_data[15+64:11+64];
check_source12;
check_source22;
check_destination2;
end
32\'b000000_xxxxx_000000000000000_001000: /* jr rs */
begin
opcode[2] <= 7;
source1[2] <= imem_data[25+64:21+64];
#0.010 address <= in_src31;
jmp_status <= 1;
check_source12;
end
32\'b000010_xxxxxxxxxxxxxxxxxxxxxxxxxx: /* j target */
begin
opcode[2] <= 11;
immediate[2] <= imem_data[25+64:0+64];
address <= imem_data[25+64:0+64];
jmp_status <= 1;
end
32\'b000011_xxxxxxxxxxxxxxxxxxxxxxxxxx: /* jal target */
begin
opcode[2] <= 14;
immediate[2] <= pc_address + 1;
destination[2] <= 31;
address <= imem_data[25+64:0+64];
jmp_status <= 1;
check_destination2;
end
32\'b001000_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* addi rs rt imm */
begin
opcode[2] <= 2;
source1[2] <= imem_data[25+64:21+64];
destination[2] <= imem_data[20+64:16+64];
immediate[2] <= imem_data[15+64:0+64];
check_source12;
check_destination2;
end
32\'b011000_xxxxx_xxxxx_xxxxx_00000000000: /* mul rs rt rd */
begin
opcode[2] <= 3;
source1[2] <= imem_data[25+64:21+64];
source2[2] <= imem_data[20+64:16+64];
destination[2] <= imem_data[15+64:11+64];
/*
#0.001 $display("MUL IF !!!! %d %d %d\
", source1[2], source2[2], destination[2]);
$stop;
*/
check_source12;
check_source22;
check_destination2;
end
32\'b001111_00000_xxxxx_xxxxxxxxxxxxxxxx: /* lui rt imm */
begin
opcode[2] <= 16;
destination[2] <= imem_data[20+64:16+64];
immediate[2] <= imem_data[15+64:0+64];
check_destination2;
end
32\'b011011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* muli rs rt imm */
begin
opcode[2] <= 13;
source1[2] <= imem_data[25+64:21+64];
destination[2] <= imem_data[20+64:16+64];
immediate[2] <= imem_data[15+64:0+64];
check_source12;
check_destination2;
end
32\'b001101_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* ori rs rt imm */
begin
opcode[2] <= 15;
source1[2] <= imem_data[25+64:21+64];
destination[2] <= imem_data[20+64:16+64];
immediate[2] <= imem_data[15+64:0+64];
check_source12;
check_destination2;
end
32\'b011001_xxxxx_xxxxx_000000000000000_0: /* move rs rt */
begin
opcode[2] <= 4;
source1[2] <= imem_data[25+64:21+64];
destination[2] <= imem_data[20+64:16+64];
check_source12;
check_destination2;
end
32\'b011001_xxxxx_xxxxxxxxxxxxxxxxxxxx_1: /* movei rs imm */
begin
opcode[2] <= 5;
destination[2] <= imem_data[25+64:21+64];
immediate[2] <= imem_data[20+64:1+64];
check_destination2;
end
32\'b011010_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* bge rs rt offset */
begin
opcode[2] <= 8;
source1[2] <= imem_data[25+64:21+64];
source2[2] <= imem_data[20+64:16+64];
immediate[2] <= imem_data[15+64:0+64];
#0.010 if(in_src31 >= in_src32)
begin
address <= imem_data[15+64:15+64] == 1 ? pc_address - (~{16\'b1111111111111111, imem_data[15+64:0+64]}+1) + 1 : pc_address + {16\'b0, imem_data[15+64:0+64]} + 1;
jmp_status <= 1;
end
check_source12;
check_source22;
end
32\'b100011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* lw rs rt offset */
begin
opcode[2] <= 9;
destination[2] <= imem_data[20+64:16+64];
source1[2] <= imem_data[25+64:21+64];
#0.010 immediate[2] <= imem_data[15+64:15+64] == 1 ? in_src31/4 - (~{16\'b1111111111111111, imem_data[15+64:0+64]}+1) : in_src31/4 + {16\'b0, imem_data[15+64:0+64]};
check_source12;
check_destination2;
end
32\'b101011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* sw rs rt offset */
begin
opcode[2] <= 10;
source1[2] <= imem_data[25+64:21+64];
source2[2] <= imem_data[20+64:16+64];
#0.010
immediate[2] <= imem_data[15+64:15+64] == 1 ? in_src31/32\'h4 - (~{16\'b1111111111111111, imem_data[15+64:0+64]}+32\'h1) : in_src31/32\'h4 + {16\'b0, imem_data[15+64:0+64]};
check_source12;
check_source22;
end
32\'b111111_11111_11111_1111111111111111: /* halt */
begin
opcode[2] <= 12;
address <= pc_address;
jmp_status <= 1;
end
default:
begin
opcode[2] <= 0;
end
endcase
#0.010 casex(imem_data[31+96:0+96])
/* //nop
32\'b000000_00000_00000_00000_00000_000000:
begin
opcode <= 0;
r_write_pc <= 0;
address <= pc_address + 1;
#0.010 r_write_pc <= 1;
end
*/
32\'b000000_xxxxx_xxxxx_xxxxx_xxxxx_000000: /* sll rt rd shamt */
begin
opcode[3] <= 1;
source2[3] <= imem_data[20+96:16+96];
destination[3] <= imem_data[15+96:11+96];
immediate[3] <= imem_data[10+96:6+96];
check_source23;
check_destination3;
end
32\'b000000_xxxxx_xxxxx_xxxxx_00000_100000: /* add rs rt rd */
begin
opcode[3] <= 6;
source1[3] <= imem_data[25+96:21+96];
source2[3] <= imem_data[20+96:16+96];
destination[3] <= imem_data[15+96:11+96];
check_source13;
check_source23;
check_destination3;
end
32\'b000000_xxxxx_000000000000000_001000: /* jr rs */
begin
opcode[3] <= 7;
source1[3] <= imem_data[25+96:21+96];
#0.010 address <= in_src41;
jmp_status <= 1;
check_source13;
end
32\'b000010_xxxxxxxxxxxxxxxxxxxxxxxxxx: /* j target */
begin
opcode[3] <= 11;
immediate[3] <= imem_data[25+96:0+96];
address <= imem_data[25+96:0+96];
jmp_status <= 1;
end
32\'b000011_xxxxxxxxxxxxxxxxxxxxxxxxxx: /* jal target */
begin
opcode[3] <= 14;
immediate[3] <= pc_address + 1;
destination[3] <= 31;
address <= imem_data[25+96:0+96];
jmp_status <= 1;
check_destination3;
end
32\'b001000_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* addi rs rt imm */
begin
opcode[3] <= 2;
source1[3] <= imem_data[25+96:21+96];
destination[3] <= imem_data[20+96:16+96];
immediate[3] <= imem_data[15+96:0+96];
check_source13;
check_destination3;
end
32\'b011000_xxxxx_xxxxx_xxxxx_00000000000: /* mul rs rt rd */
begin
opcode[3] <= 3;
source1[3] <= imem_data[25+96:21+96];
source2[3] <= imem_data[20+96:16+96];
destination[3] <= imem_data[15+96:11+96];
/*
#0.001 $display("MUL IF !!!! %d %d %d\
", source1[3], source2[3], destination[3]);
$stop;
*/
check_source13;
check_source23;
check_destination3;
end
32\'b001111_00000_xxxxx_xxxxxxxxxxxxxxxx: /* lui rt imm */
begin
opcode[3] <= 16;
destination[3] <= imem_data[20+96:16+96];
immediate[3] <= imem_data[15+96:0+96];
check_destination3;
end
32\'b011011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* muli rs rt imm */
begin
opcode[3] <= 13;
source1[3] <= imem_data[25+96:21+96];
destination[3] <= imem_data[20+96:16+96];
immediate[3] <= imem_data[15+96:0+96];
check_source13;
check_destination3;
end
32\'b001101_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* ori rs rt imm */
begin
opcode[3] <= 15;
source1[3] <= imem_data[25+96:21+96];
destination[3] <= imem_data[20+96:16+96];
immediate[3] <= imem_data[15+96:0+96];
check_source13;
check_destination3;
end
32\'b011001_xxxxx_xxxxx_000000000000000_0: /* move rs rt */
begin
opcode[3] <= 4;
source1[3] <= imem_data[25+96:21+96];
destination[3] <= imem_data[20+96:16+96];
check_source13;
check_destination3;
end
32\'b011001_xxxxx_xxxxxxxxxxxxxxxxxxxx_1: /* movei rs imm */
begin
opcode[3] <= 5;
destination[3] <= imem_data[25+96:21+96];
immediate[3] <= imem_data[20+96:1+96];
check_destination3;
end
32\'b011010_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* bge rs rt offset */
begin
opcode[3] <= 8;
source1[3] <= imem_data[25+96:21+96];
source2[3] <= imem_data[20+96:16+96];
immediate[3] <= imem_data[15+96:0+96];
#0.010 if(in_src41 >= in_src42)
begin
address <= imem_data[15+96:15+96] == 1 ? pc_address - (~{16\'b1111111111111111, imem_data[15+96:0+96]}+1) + 1 : pc_address + {16\'b0, imem_data[15+96:0+96]} + 1;
jmp_status <= 1;
end
check_source13;
check_source23;
end
32\'b100011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* lw rs rt offset */
begin
opcode[3] <= 9;
destination[3] <= imem_data[20+96:16+96];
source1[3] <= imem_data[25+96:21+96];
#0.010 immediate[3] <= imem_data[15+96:15+96] == 1 ? in_src41/4 - (~{16\'b1111111111111111, imem_data[15+96:0+96]}+1) : in_src41/4 + {16\'b0, imem_data[15+96:0+96]};
check_source13;
check_destination3;
if(rs_free === 1 /*|| rs_ex_ok === 1*/)
begin
r_rs_reg <= source1[3];
r_rs_reg2 <= destination[3];
#0.001 r_rs_write <= 1;
end
else
begin
r_rg_check_result <= 1;
end
end
32\'b101011_xxxxx_xxxxx_xxxxxxxxxxxxxxxx: /* sw rs rt offset */
begin
opcode[3] <= 10;
source1[3] <= imem_data[25+96:21+96];
source2[3] <= imem_data[20+96:16+96];
#0.010
immediate[3] <= imem_data[15+96:15+96] == 1 ? in_src41/32\'h4 - (~{16\'b1111111111111111, imem_data[15+96:0+96]}+32\'h1) : in_src41/32\'h4 + {16\'b0, imem_data[15+96:0+96]};
check_source13;
check_source23;
//#0.001 $display("jiong %d %d\
", r_rg_check_result, rs_free);
if(rs_free === 1 /*|| rs_ex_ok === 1*/)
begin
r_rs_reg <= source1[3];
r_rs_reg2 <= source2[3];
#0.001 r_rs_write <= 1;
end
else
begin
r_rg_check_result <= 1;
end
end
32\'b111111_11111_11111_1111111111111111: /* halt */
begin
opcode[3] <= 12;
address <= pc_address;
jmp_status <= 1;
end
default:
begin
opcode[3] <= 0;
end
endcase
r_write_pc <= 0;
#0.010
/*
$display("rg_check_result: %d %d %d %d %d %d %d\
", r_rg_check_result, opcode[0], opcode[1], opcode[2], opcode[3], rs_free, jmp_status);
$stop;
*/
/*
if(r_rg_check_result === 1)
begin
opcode[0] <= 0;
opcode[1] <= 0;
opcode[2] <= 0;
opcode[3] <= 0;
address <= pc_address;
#0.010
r_write_pc <= 1;
end
else
begin
*/
if(jmp_status !== 1)
begin
address <= pc_address + 1;
end
#0.010
r_write_pc <= 1;
/*
end
*/
end
end
endmodule
|
`timescale 1ns / 1ps
`define DELAY_MEMORY 100 /* DELAY_MEMORY >= 1 */
//`define DELAY_CACHEL2 100 /* DELAY_CACHEL2 >= 1 */
|
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