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/*
* Wishbone master interface module for Zet
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_wb_master (
input cpu_byte_o,
input cpu_memop,
input cpu_m_io,
input [19:0] cpu_adr_o,
output reg cpu_block,
output reg [15:0] cpu_dat_i,
input [15:0] cpu_dat_o,
input cpu_we_o,
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
output reg [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o,
output reg [ 1:0] wb_sel_o,
output reg wb_stb_o,
output wb_cyc_o,
input wb_ack_i
);
// Register and nets declarations
reg [ 1:0] cs; // current state
reg [ 1:0] ns; // next state
reg [19:1] adr1; // next address (for unaligned acc)
wire op; // in an operation
wire odd_word; // unaligned word
wire a0; // address 0 pin
wire [15:0] blw; // low byte (sign extended)
wire [15:0] bhw; // high byte (sign extended)
wire [ 1:0] sel_o; // bus byte select
// Declare the symbolic names for states
localparam [1:0]
IDLE = 2'd0,
stb1_hi = 2'd1,
stb2_hi = 2'd2,
bloc_lo = 2'd3;
// Assignments
assign op = (cpu_memop | cpu_m_io);
assign odd_word = (cpu_adr_o[0] & !cpu_byte_o);
assign a0 = cpu_adr_o[0];
assign blw = { {8{wb_dat_i[7]}}, wb_dat_i[7:0] };
assign bhw = { {8{wb_dat_i[15]}}, wb_dat_i[15:8] };
assign wb_we_o = cpu_we_o;
assign wb_tga_o = cpu_m_io;
assign sel_o = a0 ? 2'b10 : (cpu_byte_o ? 2'b01 : 2'b11);
assign wb_cyc_o = wb_stb_o;
// Behaviour
// cpu_dat_i
always @(posedge wb_clk_i)
cpu_dat_i <= cpu_we_o ? cpu_dat_i : ((cs == stb1_hi) ?
(wb_ack_i ?
(a0 ? bhw : (cpu_byte_o ? blw : wb_dat_i))
: cpu_dat_i)
: ((cs == stb2_hi && wb_ack_i) ?
{ wb_dat_i[7:0], cpu_dat_i[7:0] }
: cpu_dat_i));
// adr1
always @(posedge wb_clk_i)
adr1 <= cpu_adr_o[19:1] + 1'b1;
// wb_adr_o
always @(posedge wb_clk_i)
wb_adr_o <= (ns==stb2_hi) ? adr1 : cpu_adr_o[19:1];
// wb_sel_o
always @(posedge wb_clk_i)
wb_sel_o <= (ns==stb1_hi) ? sel_o : 2'b01;
// wb_stb_o
always @(posedge wb_clk_i)
wb_stb_o <= (ns==stb1_hi || ns==stb2_hi);
// wb_dat_o
always @(posedge wb_clk_i)
wb_dat_o <= a0 ? { cpu_dat_o[7:0], cpu_dat_o[15:8] }
: cpu_dat_o;
// cpu_block
always @(*)
case (cs)
IDLE: cpu_block <= op;
default: cpu_block <= 1'b1;
bloc_lo: cpu_block <= wb_ack_i;
endcase
// state machine
// cs - current state
always @(posedge wb_clk_i)
cs <= wb_rst_i ? IDLE : ns;
// ns - next state
always @(*)
case (cs)
default: ns <= wb_ack_i ? IDLE : (op ? stb1_hi : IDLE);
stb1_hi: ns <= wb_ack_i ? (odd_word ? stb2_hi : bloc_lo) : stb1_hi;
stb2_hi: ns <= wb_ack_i ? bloc_lo : stb2_hi;
bloc_lo: ns <= wb_ack_i ? bloc_lo : IDLE;
endcase
endmodule
|
/*
* 1-bit 8-way multiplexor
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_mux8_1(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
input [2:0] sel;
input in0, in1, in2, in3, in4, in5, in6, in7;
output out;
reg out;
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
case(sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
3'd7: out = in7;
endcase
endmodule
|
/*
* Instruction decoder for Zet
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_decode (
input clk,
input rst,
input [7:0] opcode,
input [7:0] modrm,
input rep,
input block,
input exec_st,
input div_exc,
input ld_base,
input div,
input tfl,
output tflm,
output need_modrm,
output need_off,
output need_imm,
output off_size,
output imm_size,
input [2:0] sop_l,
input intr,
input ifl,
output iflm,
output reg inta,
output reg ext_int,
input nmir,
output reg nmia,
input wr_ss,
output iflss,
// to microcode
output [`MICRO_ADDR_WIDTH-1:0] seq_addr,
output [3:0] src,
output [3:0] dst,
output [3:0] base,
output [3:0] index,
output [1:0] seg,
output [2:0] f,
// from microcode
input end_seq
);
// Net declarations
wire [`MICRO_ADDR_WIDTH-1:0] base_addr;
reg [`MICRO_ADDR_WIDTH-1:0] seq;
reg dive;
reg tfle;
reg tfld;
reg ifld;
reg iflssd;
reg old_ext_int;
reg [4:0] div_cnt;
// Module instantiations
zet_opcode_deco opcode_deco (opcode, modrm, rep, sop_l, base_addr, need_modrm,
need_off, need_imm, off_size, imm_size, src, dst,
base, index, seg);
// Assignments
assign seq_addr = (tfle ? `INTT : (dive ? `INTD
: (ext_int ? (rep ? `EINTP : `EINT) : base_addr))) + seq;
assign f = opcode[7] ? modrm[5:3] : opcode[5:3];
assign iflm = ifl & ifld;
assign tflm = tfl & tfld;
assign iflss = !wr_ss & iflssd;
// Behaviour
always @(posedge clk)
ifld <= rst ? 1\'b0 : (exec_st ? ifld : ifl);
always @(posedge clk)
tfld <= rst ? 1\'b0 : (exec_st ? tfld : tfl);
always @(posedge clk)
if (rst)
iflssd <= 1\'b0;
else
begin
if (!exec_st)
iflssd <= 1\'b1;
else if (wr_ss)
iflssd <= 1\'b0;
end
// seq
always @(posedge clk)
seq <= rst ? `MICRO_ADDR_WIDTH\'d0
: block ? seq
: end_seq ? `MICRO_ADDR_WIDTH\'d0
: |div_cnt ? seq
: exec_st ? (seq + `MICRO_ADDR_WIDTH\'d1) : `MICRO_ADDR_WIDTH\'d0;
// div_cnt - divisor counter
always @(posedge clk)
div_cnt <= rst ? 5\'d0
: ((div & exec_st) ? (div_cnt==5\'d0 ? 5\'d18 : div_cnt - 5\'d1) : 5\'d0);
// dive
always @(posedge clk)
if (rst) dive <= 1\'b0;
else dive <= block ? dive
: (div_exc ? 1\'b1 : (dive ? !end_seq : 1\'b0));
// tfle
always @(posedge clk)
if (rst) tfle <= 1\'b0;
else tfle <= block ? tfle
: ((((tflm & !tfle) & iflss) & exec_st & end_seq) ? 1\'b1 : (tfle ? !end_seq : 1\'b0));
// ext_int
always @(posedge clk)
if (rst) ext_int <= 1\'b0;
else ext_int <= block ? ext_int
: ((((nmir | (intr & iflm)) & iflss) & exec_st & end_seq) ? 1\'b1
: (ext_int ? !end_seq : 1\'b0));
// old_ext_int
always @(posedge clk) old_ext_int <= rst ? 1\'b0 : ext_int;
// inta
always @(posedge clk)
inta <= rst ? 1\'b0 : (!nmir & (!old_ext_int & ext_int));
// nmia
always @(posedge clk)
nmia <= rst ? 1\'b0 : (nmir & (!old_ext_int & ext_int));
endmodule
|
/*
* Opcode decoder lookup table for Zet
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_opcode_deco (
input [7:0] op,
input [7:0] modrm,
input rep,
input [2:0] sovr_pr,
output reg [`MICRO_ADDR_WIDTH-1:0] seq_addr,
output reg need_modrm,
output reg need_off,
output reg need_imm,
output off_size,
output reg imm_size,
output reg [3:0] src,
output reg [3:0] dst,
output [3:0] base,
output [3:0] index,
output [1:0] seg
);
// Net declarations
wire [1:0] mod;
wire [2:0] regm;
wire [2:0] rm;
wire d, b, sm, dm;
wire off_size_mod, need_off_mod;
wire [2:0] srcm, dstm;
wire off_size_from_mod;
// Module instantiations
zet_memory_regs memory_regs (rm, mod, sovr_pr, base, index, seg);
// Assignments
assign mod = modrm[7:6];
assign regm = modrm[5:3];
assign rm = modrm[2:0];
assign d = op[1];
assign dstm = d ? regm : rm;
assign sm = d & (mod != 2\'b11);
assign dm = ~d & (mod != 2\'b11);
assign srcm = d ? rm : regm;
assign b = ~op[0];
assign off_size_mod = (base == 4\'b1100 && index == 4\'b1100) ? 1\'b1 : mod[1];
assign need_off_mod = (base == 4\'b1100 && index == 4\'b1100) || ^mod;
assign off_size_from_mod = !op[7] | (!op[5] & !op[4]) | (op[6] & op[4]);
assign off_size = !off_size_from_mod | off_size_mod;
// Behaviour
always @(op or dm or b or need_off_mod or srcm or sm or dstm
or mod or rm or regm or rep or modrm)
casex (op)
8\'b00xx_x00x: // add/or/adc/sbb/and/sub/xor/cmp r->r, r->m
begin
seq_addr <= (mod==2\'b11) ? (b ? `LOGRRB : `LOGRRW)
: (b ? `LOGRMB : `LOGRMW);
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= { 1\'b0, dstm };
src <= { 1\'b0, srcm };
end
8\'b00xx_x01x: // add/or/adc/sbb/and/sub/xor/cmp r->r, m->r
begin
seq_addr <= (mod==2\'b11) ? (b ? `LOGRRB : `LOGRRW)
: (b ? `LOGMRB : `LOGMRW);
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= { 1\'b0, dstm };
src <= { 1\'b0, srcm };
end
8\'b00xx_x10x: // add/or/adc/sbb/and/sub/xor/cmp i->r
begin
seq_addr <= b ? `LOGIRB : `LOGIRW;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= ~b;
dst <= 4\'b0;
src <= 4\'b0;
end
8\'b000x_x110: // push seg
begin
seq_addr <= `PUSHR;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= { 2\'b10, op[4:3] };
dst <= 4\'b0;
end
8\'b000x_x111: // pop seg
begin
seq_addr <= `POPR;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= { 2\'b10, op[4:3] };
end
8\'b0010_0111: // daa
begin
seq_addr <= `DAA;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= 4\'b0;
src <= 4\'b0;
end
8\'b0010_1111: // das
begin
seq_addr <= `DAS;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= 4\'b0;
src <= 4\'b0;
end
8\'b0011_0111: // aaa
begin
seq_addr <= `AAA;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= 4\'b0;
src <= 4\'b0;
end
8\'b0011_1111: // aas
begin
seq_addr <= `AAS;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= 4\'b0;
src <= 4\'b0;
end
8\'b0100_0xxx: // inc
begin
seq_addr <= `INCRW;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= 4\'b0;
src <= { 1\'b0, op[2:0] };
end
8\'b0100_1xxx: // dec
begin
seq_addr <= `DECRW;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= 4\'b0;
src <= { 1\'b0, op[2:0] };
end
8\'b0101_0xxx: // push reg
begin
seq_addr <= `PUSHR;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= { 1\'b0, op[2:0] };
dst <= 4\'b0;
end
8\'b0101_1xxx: // pop reg
begin
seq_addr <= `POPR;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= { 1\'b0, op[2:0] };
end
8\'b0110_0000: // pusha
begin
seq_addr <= `PUSHA;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b0110_0001: // popa
begin
seq_addr <= `POPA;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b0110_10x0: // push imm
begin
seq_addr <= `PUSHI;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= !op[1];
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b0110_10x1: // imul imm
begin
seq_addr <= (mod==2\'b11) ? `IMULIR : `IMULIM;
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b1;
imm_size <= !op[1];
src <= { 1\'b0, rm };
dst <= { 1\'b0, regm };
end
8\'b0111_xxxx: // jcc
begin
seq_addr <= `JCC;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= { op[3:0] };
dst <= 4\'b0;
end
8\'b1000_00xx: // add/or/adc/sbb/and/sub/xor/cmp imm
begin
seq_addr <= (mod==2\'b11) ? (b ? `LOGIRB : `LOGIRW)
: (b ? `LOGIMB : `LOGIMW);
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b1;
imm_size <= !op[1] & op[0];
dst <= { 1\'b0, modrm[2:0] };
src <= 4\'b0;
end
8\'b1000_010x: // test r->r, r->m
begin
seq_addr <= (mod==2\'b11) ? (b ? `TSTRRB : `TSTRRW)
: (b ? `TSTMRB : `TSTMRW);
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= { 1\'b0, srcm };
src <= { 1\'b0, dstm };
end
8\'b1000_011x: // xchg
begin
seq_addr <= (mod==2\'b11) ? (b ? `XCHRRB : `XCHRRW)
: (b ? `XCHRMB : `XCHRMW);
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= { 1\'b0, dstm };
src <= { 1\'b0, srcm };
end
8\'b1000_10xx: // mov: r->r, r->m, m->r
begin
if (dm) // r->m
begin
seq_addr <= b ? `MOVRMB : `MOVRMW;
need_off <= need_off_mod;
src <= { 1\'b0, srcm };
dst <= 4\'b0;
end
else if(sm) // m->r
begin
seq_addr <= b ? `MOVMRB : `MOVMRW;
need_off <= need_off_mod;
src <= 4\'b0;
dst <= { 1\'b0, dstm };
end
else // r->r
begin
seq_addr <= b ? `MOVRRB : `MOVRRW;
need_off <= 1\'b0;
dst <= { 1\'b0, dstm };
src <= { 1\'b0, srcm };
end
need_imm <= 1\'b0;
need_modrm <= 1\'b1;
imm_size <= 1\'b0;
end
8\'b1000_1100: // mov: s->m, s->r
begin
if (dm) // s->m
begin
seq_addr <= `MOVRMW;
need_off <= need_off_mod;
src <= { 1\'b1, srcm };
dst <= 4\'b0;
end
else // s->r
begin
seq_addr <= `MOVRRW;
need_off <= 1\'b0;
src <= { 1\'b1, srcm };
dst <= { 1\'b0, dstm };
end
need_imm <= 1\'b0;
need_modrm <= 1\'b1;
imm_size <= 1\'b0;
end
8\'b1000_1101: // lea
begin
seq_addr <= `LEA;
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= { 1\'b0, srcm };
dst <= 4\'b0;
end
8\'b1000_1110: // mov: m->s, r->s
begin
if (sm) // m->s
begin
seq_addr <= `MOVMRW;
need_off <= need_off_mod;
src <= 4\'b0;
dst <= { 1\'b1, dstm };
end
else // r->s
begin
seq_addr <= `MOVRRW;
need_off <= 1\'b0;
src <= { 1\'b0, srcm };
dst <= { 1\'b1, dstm };
end
need_modrm <= 1\'b1;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
end
8\'b1000_1111: // pop mem or (pop reg non-standard)
begin
seq_addr <= (mod==2\'b11) ? `POPR : `POPM;
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= { 1\'b0, rm };
end
8\'b1001_0xxx: // nop, xchg acum
begin
seq_addr <= `XCHRRW;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0000;
dst <= { 1\'b0, op[2:0] };
end
8\'b1001_1000: // cbw
begin
seq_addr <= `CBW;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= 4\'b0;
src <= 4\'b0;
end
8\'b1001_1001: // cwd
begin
seq_addr <= `CWD;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
dst <= 4\'b0;
src <= 4\'b0;
end
8\'b1001_1010: // call different seg
begin
seq_addr <= `CALLF;
need_modrm <= 1\'b0;
need_off <= 1\'b1;
need_imm <= 1\'b1;
imm_size <= 1\'b1;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1001_1011: // wait
begin
seq_addr <= `NOP;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1001_1100: // pushf
begin
seq_addr <= `PUSHF;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1001_1101: // popf
begin
seq_addr <= `POPF;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1001_1110: // sahf
begin
seq_addr <= `SAHF;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1001_1111: // lahf
begin
seq_addr <= `LAHF;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1010_000x: // mov: m->a
begin
seq_addr <= b ? `MOVMAB : `MOVMAW;
need_modrm <= 1\'b0;
need_off <= 1\'b1;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1010_001x: // mov: a->m
begin
seq_addr <= b ? `MOVAMB : `MOVAMW;
need_modrm <= 1\'b0;
need_off <= 1\'b1;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1010_010x: // movs
begin
seq_addr <= rep ? (b ? `MOVSBR : `MOVSWR) : (b ? `MOVSB : `MOVSW);
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1010_011x: // cmps
begin
seq_addr <= rep ? (b ? `CMPSBR : `CMPSWR) : (b ? `CMPSB : `CMPSW);
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1010_100x: // test i->r
begin
seq_addr <= b ? `TSTIRB : `TSTIRW;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= ~b;
dst <= 4\'b0;
src <= 4\'b0;
end
8\'b1010_101x: // stos
begin
seq_addr <= rep ? (b ? `STOSBR : `STOSWR) : (b ? `STOSB : `STOSW);
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1010_110x: // lods
begin
seq_addr <= rep ? (b ? `LODSBR : `LODSWR) : (b ? `LODSB : `LODSW);
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1010_111x: // scas
begin
seq_addr <= rep ? (b ? `SCASBR : `SCASWR) : (b ? `SCASB : `SCASW);
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1011_xxxx: // mov: i->r
begin
seq_addr <= op[3] ? `MOVIRW : `MOVIRB;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= op[3];
src <= 4\'b0;
dst <= { 1\'b0, op[2:0] };
end
8\'b1100_000x: // ror/rol/rcr/rcl/sal/shl/sar/shr imm8/imm16
begin
seq_addr <= (mod==2\'b11) ? (b ? `RSHIRB : `RSHIRW)
: (b ? `RSHIMB : `RSHIMW);
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= rm;
dst <= rm;
end
8\'b1100_0010: // ret near with value
begin
seq_addr <= `RETNV;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b1;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1100_0011: // ret near
begin
seq_addr <= `RETN0;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1100_0100: // les
begin
seq_addr <= `LES;
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= { 1\'b0, srcm };
dst <= 4\'b0;
end
8\'b1100_0101: // lds
begin
seq_addr <= `LDS;
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= { 1\'b0, srcm };
dst <= 4\'b0;
end
8\'b1100_011x: // mov: i->m (or i->r non-standard)
begin
seq_addr <= (mod==2\'b11) ? (b ? `MOVIRB : `MOVIRW)
: (b ? `MOVIMB : `MOVIMW);
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b1;
imm_size <= ~b;
src <= 4\'b0;
dst <= { 1\'b0, rm };
end
8\'b1100_1000: // enter
begin
seq_addr <= `ENTER;
need_modrm <= 1\'b0;
need_off <= need_off_mod;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1100_1001: // leave
begin
seq_addr <= `LEAVE;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1100_1010: // ret far with value
begin
seq_addr <= `RETFV;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b1;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1100_1011: // ret far
begin
seq_addr <= `RETF0;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1100_1100: // int 3
begin
seq_addr <= `INT3;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1100_1101: // int
begin
seq_addr <= `INT;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1100_1110: // into
begin
seq_addr <= `INTO;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1100_1111: // iret
begin
seq_addr <= `IRET;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1101_00xx: // sal/shl
begin
seq_addr <= (mod==2\'b11) ? (op[1] ? (b ? `RSHCRB : `RSHCRW)
: (b ? `RSH1RB : `RSH1RW))
: (op[1] ? (b ? `RSHCMB : `RSHCMW)
: (b ? `RSH1MB : `RSH1MW));
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= rm;
dst <= rm;
end
8\'b1101_0100: // aam
begin
seq_addr <= `AAM;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1101_0101: // aad
begin
seq_addr <= `AAD;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1101_0111: // xlat
begin
seq_addr <= `XLAT;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1101_1xxx: // esc
begin
seq_addr <= (mod==2\'b11) ? `ESCRW : `ESCMW;
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= { 1\'b0, modrm[2:0] };
dst <= 4\'b0;
end
8\'b1110_0000: // loopne
begin
seq_addr <= `LOOPNE;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1110_0001: // loope
begin
seq_addr <= `LOOPE;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1110_0010: // loop
begin
seq_addr <= `LOOP;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1110_0011: // jcxz
begin
seq_addr <= `JCXZ;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1110_010x: // in imm
begin
seq_addr <= b ? `INIB : `INIW;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1110_011x: // out imm
begin
seq_addr <= b ? `OUTIB : `OUTIW;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1110_1000: // call same segment
begin
seq_addr <= `CALLN;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= 1\'b1;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1110_10x1: // jmp direct
begin
seq_addr <= `JMPI;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b1;
imm_size <= ~op[1];
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1110_1010: // jmp indirect different segment
begin
seq_addr <= `LJMPI;
need_modrm <= 1\'b0;
need_off <= 1\'b1;
need_imm <= 1\'b1;
imm_size <= 1\'b1;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1110_110x: // in dx
begin
seq_addr <= b ? `INRB : `INRW;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1110_111x: // out dx
begin
seq_addr <= b ? `OUTRB : `OUTRW;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1111_0100: // hlt
begin
seq_addr <= `NOP; // hlt processing is in zet_core.v
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1111_0101: // cmc
begin
seq_addr <= `CMC;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1111_011x: // test, not, neg, mul, imul
begin
case (regm)
3\'b000: seq_addr <= (mod==2\'b11) ?
(b ? `TSTIRB : `TSTIRW) : (b ? `TSTIMB : `TSTIMW);
3\'b010: seq_addr <= (mod==2\'b11) ?
(b ? `NOTRB : `NOTRW) : (b ? `NOTMB : `NOTMW);
3\'b011: seq_addr <= (mod==2\'b11) ?
(b ? `NEGRB : `NEGRW) : (b ? `NEGMB : `NEGMW);
3\'b100: seq_addr <= (mod==2\'b11) ?
(b ? `MULRB : `MULRW) : (b ? `MULMB : `MULMW);
3\'b101: seq_addr <= (mod==2\'b11) ?
(b ? `IMULRB : `IMULRW) : (b ? `IMULMB : `IMULMW);
3\'b110: seq_addr <= (mod==2\'b11) ?
(b ? `DIVRB : `DIVRW) : (b ? `DIVMB : `DIVMW);
3\'b111: seq_addr <= (mod==2\'b11) ?
(b ? `IDIVRB : `IDIVRW) : (b ? `IDIVMB : `IDIVMW);
default: seq_addr <= `INVOP;
endcase
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= (regm == 3\'b000); // imm on test
imm_size <= ~b;
dst <= { 1\'b0, modrm[2:0] };
src <= { 1\'b0, modrm[2:0] };
end
8\'b1111_1000: // clc
begin
seq_addr <= `CLC;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1111_1001: // stc
begin
seq_addr <= `STC;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1111_1010: // cli
begin
seq_addr <= `CLI;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1111_1011: // sti
begin
seq_addr <= `STI;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1111_1100: // cld
begin
seq_addr <= `CLD;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1111_1101: // std
begin
seq_addr <= `STD;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
8\'b1111_1110: // inc
begin
case (regm)
3\'b000: seq_addr <= (mod==2\'b11) ? `INCRB : `INCMB;
3\'b001: seq_addr <= (mod==2\'b11) ? `DECRB : `DECMB;
default: seq_addr <= `INVOP;
endcase
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= { 1\'b0, rm };
dst <= 4\'b0;
end
8\'b1111_1111:
begin
case (regm)
3\'b000: seq_addr <= (mod==2\'b11) ? `INCRW : `INCMW;
3\'b001: seq_addr <= (mod==2\'b11) ? `DECRW : `DECMW;
3\'b010: seq_addr <= (mod==2\'b11) ? `CALLNR : `CALLNM;
3\'b011: seq_addr <= `CALLFM;
3\'b100: seq_addr <= (mod==2\'b11) ? `JMPR : `JMPM;
3\'b101: seq_addr <= `LJMPM;
3\'b110: seq_addr <= (mod==2\'b11) ? `PUSHR : `PUSHM;
default: seq_addr <= `INVOP;
endcase
need_modrm <= 1\'b1;
need_off <= need_off_mod;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= { 1\'b0, rm };
dst <= 4\'b0;
end
default: // invalid opcode
begin
seq_addr <= `INVOP;
need_modrm <= 1\'b0;
need_off <= 1\'b0;
need_imm <= 1\'b0;
imm_size <= 1\'b0;
src <= 4\'b0;
dst <= 4\'b0;
end
endcase
endmodule
|
/*
* Wishbone Flash RAM core for Altera DE1 board
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module flash8 (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_we_i,
input wb_adr_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// Pad signals
output [21:0] flash_addr_,
input [ 7:0] flash_data_,
output flash_we_n_,
output flash_oe_n_,
output flash_ce_n_,
output flash_rst_n_
);
// Registers and nets
wire op;
wire wr_command;
reg [20:0] address;
wire word;
wire op_word;
reg st;
reg [ 7:0] lb;
// Combinatorial logic
assign op = wb_stb_i & wb_cyc_i;
assign word = wb_sel_i==2'b11;
assign op_word = op & word & !wb_we_i;
assign flash_rst_n_ = 1'b1;
assign flash_we_n_ = 1'b1;
assign flash_oe_n_ = !op;
assign flash_ce_n_ = !op;
assign flash_addr_[21:1] = address;
assign flash_addr_[0] = (wb_sel_i==2'b10) | (word & st);
assign wr_command = op & wb_we_i; // Wishbone write access Signal
assign wb_ack_o = op & (op_word ? st : 1'b1);
assign wb_dat_o = wb_sel_i[1] ? { flash_data_, lb }
: { 8'h0, flash_data_ };
// Behaviour
// st - state
always @(posedge wb_clk_i)
st <= wb_rst_i ? 1'b0 : op_word;
// lb - low byte
always @(posedge wb_clk_i)
lb <= wb_rst_i ? 8'h0 : (op_word ? flash_data_ : 8'h0);
// --------------------------------------------------------------------
// Register addresses and defaults
// --------------------------------------------------------------------
`define FLASH_ALO 1'h0 // Lower 16 bits of address lines
`define FLASH_AHI 1'h1 // Upper 6 bits of address lines
always @(posedge wb_clk_i) // Synchrounous
if(wb_rst_i)
address <= 21'h000000; // Interupt Enable default
else
if(wr_command) // If a write was requested
case(wb_adr_i) // Determine which register was writen to
`FLASH_ALO: address[15: 0] <= wb_dat_i;
`FLASH_AHI: address[20:16] <= wb_dat_i[4:0];
default: ; // Default
endcase // End of case
endmodule
|
/*\r
* Planar mode graphics for VGA\r
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
module vga_planar_fml (\r
input clk,\r
input rst,\r
\r
input enable,\r
\r
// CSR slave interface for reading\r
output [17:1] fml_adr_o,\r
input [15:0] fml_dat_i,\r
output fml_stb_o,\r
\r
// Controller registers\r
input [3:0] attr_plane_enable,\r
input x_dotclockdiv2,\r
\r
input [9:0] h_count,\r
input [9:0] v_count,\r
input horiz_sync_i,\r
input video_on_h_i,\r
output video_on_h_o,\r
\r
output reg [3:0] attr,\r
output horiz_sync_o\r
);\r
\r
// Registers and net\r
reg [11:0] row_addr;\r
reg [ 5:0] col_addr;\r
reg [14:0] word_offset;\r
reg [ 1:0] plane_addr0;\r
reg [ 1:0] plane_addr;\r
reg [15:0] plane0;\r
reg [15:0] plane0_tmp;\r
reg [15:0] plane1;\r
reg [15:0] plane1_tmp;\r
reg [15:0] plane2;\r
reg [15:0] plane2_tmp;\r
reg [15:0] plane3;\r
reg [ 7:0] bit_mask0;\r
reg [ 7:0] bit_mask1;\r
\r
wire [15:0] bit_mask;\r
wire v_count0;\r
\r
wire bit3, bit2, bit1, bit0;\r
\r
reg [9:0] video_on_h;\r
reg [9:0] horiz_sync;\r
reg [7:0] pipe;\r
\r
// Continous assignments\r
assign fml_adr_o = { word_offset, plane_addr };\r
assign bit_mask = { bit_mask1, bit_mask0 };\r
\r
assign bit0 = |(bit_mask & plane0);\r
assign bit1 = |(bit_mask & plane1);\r
assign bit2 = |(bit_mask & plane2);\r
assign bit3 = |(bit_mask & plane3);\r
\r
assign video_on_h_o = video_on_h[9];\r
assign horiz_sync_o = horiz_sync[9];\r
assign fml_stb_o = |pipe[4:1];\r
assign v_count0 = x_dotclockdiv2 ? 1'b0 : v_count[0];\r
\r
// Behaviour\r
// Pipeline count\r
always @(posedge clk)\r
if (rst)\r
begin\r
pipe <= 8'b0;\r
end\r
else\r
if (enable)\r
begin\r
pipe <= { pipe[6:0],\r
x_dotclockdiv2 ? (h_count[4:0]==5'h0) : (h_count[3:0]==4'h0) }; \r
end\r
\r
// video_on_h\r
always @(posedge clk)\r
if (rst)\r
begin\r
video_on_h <= 10'b0;\r
end\r
else\r
if (enable)\r
begin\r
video_on_h <= { video_on_h[8:0], video_on_h_i };\r
end\r
\r
// horiz_sync\r
always @(posedge clk)\r
if (rst)\r
begin\r
horiz_sync <= 10'b0;\r
end\r
else\r
if (enable)\r
begin\r
horiz_sync <= { horiz_sync[8:0], horiz_sync_i };\r
end\r
\r
// Address generation\r
always @(posedge clk)\r
if (rst)\r
begin\r
row_addr <= 12'h0;\r
col_addr <= 6'h0;\r
plane_addr0 <= 2'b00;\r
word_offset <= 15'h0;\r
plane_addr <= 2'b00;\r
end\r
else\r
if (enable)\r
begin\r
// Loading new row_addr and col_addr when h_count[3:0]==4'h0\r
// v_count * 40 or 22 (depending on x_dotclockdiv2)\r
row_addr <= { v_count[9:1], v_count0, 2'b00 } + { v_count[9:1], v_count0 }\r
+ (x_dotclockdiv2 ? v_count[9:1] : 9'h0);\r
col_addr <= x_dotclockdiv2 ? h_count[9:5] : h_count[9:4];\r
plane_addr0 <= h_count[1:0];\r
\r
// Load new word_offset at +1\r
word_offset <= (x_dotclockdiv2 ? { row_addr, 1'b0 }\r
: { row_addr, 3'b000 }) + col_addr;\r
plane_addr <= plane_addr0;\r
end\r
\r
// Temporary plane data\r
always @(posedge clk)\r
if (rst)\r
begin\r
plane0_tmp <= 16'h0;\r
plane1_tmp <= 16'h0;\r
plane2_tmp <= 16'h0;\r
end\r
else\r
if (enable)\r
begin\r
// Load plane0 when pipe == 4\r
plane0_tmp <= pipe[4] ? fml_dat_i : plane0_tmp;\r
plane1_tmp <= pipe[5] ? fml_dat_i : plane1_tmp;\r
plane2_tmp <= pipe[6] ? fml_dat_i : plane2_tmp; \r
end\r
\r
// Plane data\r
always @(posedge clk)\r
if (rst)\r
begin\r
plane0 <= 16'h0;\r
plane1 <= 16'h0;\r
plane2 <= 16'h0;\r
plane3 <= 16'h0;\r
end\r
else\r
if (enable) \r
begin\r
plane0 <= pipe[7] ? plane0_tmp : plane0;\r
plane1 <= pipe[7] ? plane1_tmp : plane1;\r
plane2 <= pipe[7] ? plane2_tmp : plane2;\r
plane3 <= pipe[7] ? fml_dat_i : plane3;\r
end\r
\r
// Bit masks\r
always @(posedge clk)\r
if (rst)\r
begin\r
bit_mask0 <= 8'h0;\r
bit_mask1 <= 8'h0;\r
end\r
else\r
if (enable) \r
begin\r
bit_mask0 <= (h_count[0] & x_dotclockdiv2) ? bit_mask0\r
: { pipe[7], bit_mask0[7:1] };\r
bit_mask1 <= (h_count[0] & x_dotclockdiv2) ? bit_mask1\r
: { bit_mask0[0], bit_mask1[7:1] };\r
end\r
\r
// attr\r
always @(posedge clk)\r
if (rst)\r
begin\r
attr <= 4'h0; \r
end\r
else\r
if (enable)\r
begin\r
attr <= (attr_plane_enable & { bit3, bit2, bit1, bit0 });\r
end \r
\r
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>
* updated to include Direct Cache Bus by Charley Picker <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlbrg_datamem #(
\tparameter depth = 8
) (
\tinput sys_clk,
\t/* Primary port (read-write) */
\tinput [depth-1:0] a,
\tinput [1:0] we,
\tinput [15:0] di,
\toutput [15:0] dout,
\t/* Secondary port (read-only) */
\tinput [depth-1:0] a2,
\toutput [15:0] do2
);
reg [7:0] ram0[0:(1 << depth)-1];
reg [7:0] ram1[0:(1 << depth)-1];
wire [7:0] ram0di;
wire [7:0] ram1di;
wire [7:0] ram0do;
wire [7:0] ram1do;
wire [7:0] ram0do2;
wire [7:0] ram1do2;
reg [depth-1:0] a_r;
reg [depth-1:0] a2_r;
always @(posedge sys_clk) begin
\ta_r <= a;
\ta2_r <= a2;
end
/*
* Workaround for a strange Xst 11.4 bug with Spartan-6
* We must specify the RAMs in this order, otherwise,
* ram1 "disappears" from the netlist. The typical
* first symptom is a Bitgen DRC failure because of
* dangling I/O pins going to the SDRAM.
* Problem reported to Xilinx.
*/
always @(posedge sys_clk) begin
\tif(we[1])
\t\tram1[a] <= ram1di;
end
assign ram1do = ram1[a_r];
assign ram1do2 = ram1[a2_r];
always @(posedge sys_clk) begin
\tif(we[0])
\t\tram0[a] <= ram0di;
end
assign ram0do = ram0[a_r];
assign ram0do2 = ram0[a2_r];
assign ram0di = di[7:0];
assign ram1di = di[15:8];
assign dout = {ram1do, ram0do};
assign do2 = {ram1do2, ram0do2};
endmodule
|
/**************************************************************************
*
* File Name: MT48LC16M16A2.V
* Version: 2.1
* Date: June 6th, 2002
* Model: BUS Functional
* Simulator: Model Technology
*
* Dependencies: None
*
* Email: [email protected]
* Company: Micron Technology, Inc.
* Model: MT48LC16M16A2 (4Meg x 16 x 4 Banks)
* Altera DE1: PSC A2V64S40CTP (1048576 addresses/bank
* x 16 bits/address
* x 4 Banks = 64 Mbits = 8 Mbytes)
*
* Description: Micron 256Mb SDRAM Verilog model
*
* Limitation: - Doesn\'t check for 8192 cycle refresh
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
* Copyright \xef\xbf\xbd 2001 Micron Semiconductor Products, Inc.
* All rights researved
*
* Rev Author Date Changes
* --- -------------------------- ---------------------------------------
* 2.1 SH 06/06/2002 - Typo in bank multiplex
* Micron Technology Inc.
*
* 2.0 SH 04/30/2002 - Second release
* Micron Technology Inc.
*
**************************************************************************/
`timescale 1ns / 1ps
module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
parameter addr_bits = 12; // 12 PSC, 13 MT
parameter data_bits = 16;
parameter col_bits = 8; // 8 in PSC, 9 MT
parameter mem_sizes = 1048575; // 1048575 PSC, 4194303 MT
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [1 : 0] Dqm;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank)
reg Read_precharge [0 : 3]; // R Auto Precharge
reg Write_precharge [0 : 3]; // W Auto Precharge
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank
integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter
integer Count_precharge [0 : 3]; // RW Auto Precharge Counter
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Prev_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
wire Debug = 1\'b1; // Debug messages : 1 = On
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
assign Dq = Dq_reg; // DQ buffer
/* Dump the content of the memory after some delay */
/*
integer dumpi;
initial begin
\t#206640
\t$display("Contents of bank 0");
\tfor(dumpi=0;dumpi<20;dumpi=dumpi+1) begin
\t\t$display("%h: %h", dumpi, Bank0[dumpi]);
\tend
\t$display("Contents of bank 1");
\tfor(dumpi=0;dumpi<20;dumpi=dumpi+1) begin
\t\t$display("%h: %h", dumpi, Bank1[dumpi]);
\tend
\t$display("Contents of bank 2");
\tfor(dumpi=0;dumpi<20;dumpi=dumpi+1) begin
\t\t$display("%h: %h", dumpi, Bank2[dumpi]);
\tend
\t$display("Contents of bank 3");
\tfor(dumpi=0;dumpi<20;dumpi=dumpi+1) begin
\t\t$display("%h: %h", dumpi, Bank3[dumpi]);
\tend
end
*/
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define WRITE 3
`define PRECH 4
`define A_REF 5
`define BST 6
`define LMR 7
// Timing Parameters for -7E PC133 CL2
parameter tAC = 5.4;
parameter tHZ = 5.4;
parameter tOH = 3.0;
parameter tMRD = 2.0; // 2 Clk Cycles
parameter tRAS = 37.0;
parameter tRC = 60.0;
parameter tRCD = 15.0;
parameter tRFC = 66.0;
parameter tRP = 15.0;
parameter tRRD = 14.0;
parameter tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns)
parameter tWRm = 14.0; // A2 Version - Manual precharge mode (14 ns)
// Timing Check variable
time MRD_chk;
time WR_chkm [0 : 3];
time RFC_chk, RRD_chk;
time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
initial begin
Dq_reg = {data_bits{1\'bz}};
Data_in_enable = 0; Data_out_enable = 0;
Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0;
RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
$timeformat (-9, 1, " ns", 12);
end
// System clock generator
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1\'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1\'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2\'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2\'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1\'b0;
// Dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = Dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] === 1\'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] === 1\'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] === 1\'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] === 1\'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// Read or Write Interrupt Counter
if (RW_interrupt_write[0] === 1\'b1) begin
RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
end
if (RW_interrupt_write[1] === 1\'b1) begin
RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
end
if (RW_interrupt_write[2] === 1\'b1) begin
RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
end
if (RW_interrupt_write[3] === 1\'b1) begin
RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// Auto Refresh
if (Aref_enable === 1\'b1) begin
if (Debug) begin
$display ("%m : at time %t AREF : Auto Refresh", $time);
end
// Auto Refresh to Auto Refresh
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 === 1\'b0 || Pc_b1 === 1\'b0 || Pc_b2 === 1\'b0 || Pc_b3 === 1\'b0) begin
$display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Load Mode Register to Auto Refresh
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Record Current tRFC time
RFC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable === 1\'b1) begin
// Register Mode
Mode_reg = Addr;
// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
if (Debug) begin
$display ("%m : at time %t LMR : Load Mode Register", $time);
// CAS Latency
case (Addr[6 : 4])
3\'b010 : $display ("%m : CAS Latency = 2");
3\'b011 : $display ("%m : CAS Latency = 3");
default : $display ("%m : CAS Latency = Reserved");
endcase
// Burst Length
case (Addr[2 : 0])
3\'b000 : $display ("%m : Burst Length = 1");
3\'b001 : $display ("%m : Burst Length = 2");
3\'b010 : $display ("%m : Burst Length = 4");
3\'b011 : $display ("%m : Burst Length = 8");
3\'b111 : $display ("%m : Burst Length = Full");
default : $display ("%m : Burst Length = Reserved");
endcase
// Burst Type
if (Addr[3] === 1\'b0) begin
$display ("%m : Burst Type = Sequential");
end else if (Addr[3] === 1\'b1) begin
$display ("%m : Burst Type = Interleaved");
end else begin
$display ("%m : Burst Type = Reserved");
end
// Write Burst Mode
if (Addr[9] === 1\'b0) begin
$display ("%m : Write Burst Mode = Programmed Burst Length");
end else if (Addr[9] === 1\'b1) begin
$display ("%m : Write Burst Mode = Single Location Access");
end else begin
$display ("%m : Write Burst Mode = Reserved");
end
end
// Precharge to Load Mode Register
if (Pc_b0 === 1\'b0 && Pc_b1 === 1\'b0 && Pc_b2 === 1\'b0 && Pc_b3 === 1\'b0) begin
$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// Precharge to Load Mode Register
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time);
end
// Auto Refresh to Load Mode Register
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time);
end
// Load Mode Register to Load Mode Register
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Reset MRD Counter
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable === 1\'b1) begin
// Activate an open bank can corrupt data
if ((Ba === 2\'b00 && Act_b0 === 1\'b1) || (Ba === 2\'b01 && Act_b1 === 1\'b1) ||
(Ba === 2\'b10 && Act_b2 === 1\'b1) || (Ba === 2\'b11 && Act_b3 === 1\'b1)) begin
$display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time);
end
// Activate Bank 0
if (Ba === 2\'b00 && Pc_b0 === 1\'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 0 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk0 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time);
end
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time);
end
// Record variables
Act_b0 = 1\'b1;
Pc_b0 = 1\'b0;
B0_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk0 = $time;
RC_chk0 = $time;
RCD_chk0 = $time;
end
if (Ba == 2\'b01 && Pc_b1 == 1\'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 1 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk1 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time);
end
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time);
end
// Record variables
Act_b1 = 1\'b1;
Pc_b1 = 1\'b0;
B1_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk1 = $time;
RC_chk1 = $time;
RCD_chk1 = $time;
end
if (Ba == 2\'b10 && Pc_b2 == 1\'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 2 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk2 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time);
end
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time);
end
// Record variables
Act_b2 = 1\'b1;
Pc_b2 = 1\'b0;
B2_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk2 = $time;
RC_chk2 = $time;
RCD_chk2 = $time;
end
if (Ba == 2\'b11 && Pc_b3 == 1\'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 3 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk3 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time);
end
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time);
end
// Record variables
Act_b3 = 1\'b1;
Pc_b3 = 1\'b0;
B3_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk3 = $time;
RC_chk3 = $time;
RCD_chk3 = $time;
end
// Active Bank A to Active Bank B
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
$display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
RRD_chk = $time;
Prev_bank = Ba;
end
// Precharge Block
if (Prech_enable == 1\'b1) begin
// Load Mode Register to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time);
end
// Precharge Bank 0
if ((Addr[10] === 1\'b1 || (Addr[10] === 1\'b0 && Ba === 2\'b00)) && Act_b0 === 1\'b1) begin
Act_b0 = 1\'b0;
Pc_b0 = 1\'b1;
RP_chk0 = $time;
// Activate to Precharge
if ($time - RAS_chk0 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[0] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 1
if ((Addr[10] === 1\'b1 || (Addr[10] === 1\'b0 && Ba === 2\'b01)) && Act_b1 === 1\'b1) begin
Act_b1 = 1\'b0;
Pc_b1 = 1\'b1;
RP_chk1 = $time;
// Activate to Precharge
if ($time - RAS_chk1 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[1] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 2
if ((Addr[10] === 1\'b1 || (Addr[10] === 1\'b0 && Ba === 2\'b10)) && Act_b2 === 1\'b1) begin
Act_b2 = 1\'b0;
Pc_b2 = 1\'b1;
RP_chk2 = $time;
// Activate to Precharge
if ($time - RAS_chk2 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[2] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 3
if ((Addr[10] === 1\'b1 || (Addr[10] === 1\'b0 && Ba === 2\'b11)) && Act_b3 === 1\'b1) begin
Act_b3 = 1\'b0;
Pc_b3 = 1\'b1;
RP_chk3 = $time;
// Activate to Precharge
if ($time - RAS_chk3 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[3] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable === 1\'b1 && (Bank === Ba || Addr[10] === 1\'b1)) begin
Data_in_enable = 1\'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 === 1\'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = Ba;
A10_precharge[2] = Addr[10];
end else if (Cas_latency_2 === 1\'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = Ba;
A10_precharge[1] = Addr[10];
end
end
// Burst terminate
if (Burst_term === 1\'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1\'b1) begin
Data_in_enable = 1\'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 === 1\'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1\'b1) begin
Command[1] = `BST;
end
// Display debug message
if (Debug) begin
$display ("%m : at time %t BST : Burst Terminate",$time);
end
end
// Read, Write, Column Latch
if (Read_enable === 1\'b1) begin
// Check to see if bank is open (ACT)
if ((Ba == 2\'b00 && Pc_b0 == 1\'b1) || (Ba == 2\'b01 && Pc_b1 == 1\'b1) ||
(Ba == 2\'b10 && Pc_b2 == 1\'b1) || (Ba == 2\'b11 && Pc_b3 == 1\'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Read", $time);
end
// Activate to Read or Write
if ((Ba == 2\'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2\'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2\'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2\'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// CAS Latency pipeline
if (Cas_latency_3 == 1\'b1) begin
Command[2] = `READ;
Col_addr[2] = Addr;
Bank_addr[2] = Ba;
end else if (Cas_latency_2 == 1\'b1) begin
Command[1] = `READ;
Col_addr[1] = Addr;
Bank_addr[1] = Ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1\'b1) begin
Data_in_enable = 1\'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1\'b1 && Write_precharge[RW_interrupt_bank] == 1\'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1\'b1;
RW_interrupt_counter[RW_interrupt_bank] = 0;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time);
end
end
end
// Write with Auto Precharge
if (Addr[10] == 1\'b1) begin
Auto_precharge[Ba] = 1\'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Read_precharge[Ba] = 1\'b1;
end
end
// Write Command
if (Write_enable == 1\'b1) begin
// Activate to Write
if ((Ba == 2\'b00 && Pc_b0 == 1\'b1) || (Ba == 2\'b01 && Pc_b1 == 1\'b1) ||
(Ba == 2\'b10 && Pc_b2 == 1\'b1) || (Ba == 2\'b11 && Pc_b3 == 1\'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Write", $time);
end
// Activate to Read or Write
if ((Ba == 2\'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2\'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2\'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2\'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// Latch Write command, Bank, and Column
Command[0] = `WRITE;
Col_addr[0] = Addr;
Bank_addr[0] = Ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1\'b1) begin
Data_in_enable = 1\'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1\'b1 && Write_precharge[RW_interrupt_bank] == 1\'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1\'b1;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Read Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
end
end
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1\'b1) begin
Data_out_enable = 1\'b0;
// Interrupting a Read with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1\'b1 && Read_precharge[RW_interrupt_bank] == 1\'b1) begin
RW_interrupt_read[RW_interrupt_bank] = 1\'b1;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
end
end
end
// Write with Auto Precharge
if (Addr[10] == 1\'b1) begin
Auto_precharge[Ba] = 1\'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Write_precharge[Ba] = 1\'b1;
end
end
/*
Write with Auto Precharge Calculation
The device start internal precharge when:
1. Meet minimum tRAS requirement
and 2. tWR cycle(s) after last valid data
or 3. Interrupt by a Read or Write (with or without Auto Precharge)
Note: Model is starting the internal precharge 1 cycle after they meet all the
requirement but tRP will be compensate for the time after the 1 cycle.
*/
if ((Auto_precharge[0] == 1\'b1) && (Write_precharge[0] == 1\'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 1
(((Burst_length_1 == 1\'b1 || Write_burst_mode == 1\'b1) && Count_precharge [0] >= 1) || // Case 2
(Burst_length_2 == 1\'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1\'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1\'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1\'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3
Auto_precharge[0] = 1\'b0;
Write_precharge[0] = 1\'b0;
RW_interrupt_write[0] = 1\'b0;
Pc_b0 = 1\'b1;
Act_b0 = 1\'b0;
RP_chk0 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
if ((Auto_precharge[1] == 1\'b1) && (Write_precharge[1] == 1\'b1)) begin
if ((($time - RAS_chk1 >= tRAS) && // Case 1
(((Burst_length_1 == 1\'b1 || Write_burst_mode == 1\'b1) && Count_precharge [1] >= 1) || // Case 2
(Burst_length_2 == 1\'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1\'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1\'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1\'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3
Auto_precharge[1] = 1\'b0;
Write_precharge[1] = 1\'b0;
RW_interrupt_write[1] = 1\'b0;
Pc_b1 = 1\'b1;
Act_b1 = 1\'b0;
RP_chk1 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
if ((Auto_precharge[2] == 1\'b1) && (Write_precharge[2] == 1\'b1)) begin
if ((($time - RAS_chk2 >= tRAS) && // Case 1
(((Burst_length_1 == 1\'b1 || Write_burst_mode == 1\'b1) && Count_precharge [2] >= 1) || // Case 2
(Burst_length_2 == 1\'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1\'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1\'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1\'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3
Auto_precharge[2] = 1\'b0;
Write_precharge[2] = 1\'b0;
RW_interrupt_write[2] = 1\'b0;
Pc_b2 = 1\'b1;
Act_b2 = 1\'b0;
RP_chk2 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
if ((Auto_precharge[3] == 1\'b1) && (Write_precharge[3] == 1\'b1)) begin
if ((($time - RAS_chk3 >= tRAS) && // Case 1
(((Burst_length_1 == 1\'b1 || Write_burst_mode == 1\'b1) && Count_precharge [3] >= 1) || // Case 2
(Burst_length_2 == 1\'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1\'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1\'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1\'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3
Auto_precharge[3] = 1\'b0;
Write_precharge[3] = 1\'b0;
RW_interrupt_write[3] = 1\'b0;
Pc_b3 = 1\'b1;
Act_b3 = 1\'b0;
RP_chk3 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. Meet minimum tRAS requirement
// and 2. CAS Latency - 1 cycles before last burst
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1\'b1) && (Read_precharge[0] == 1\'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 1
((Burst_length_1 == 1\'b1 && Count_precharge[0] >= 1) || // Case 2
(Burst_length_2 == 1\'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1\'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1\'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1\'b1)) begin // Case 3
Pc_b0 = 1\'b1;
Act_b0 = 1\'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1\'b0;
Read_precharge[0] = 1\'b0;
RW_interrupt_read[0] = 1\'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
if ((Auto_precharge[1] == 1\'b1) && (Read_precharge[1] == 1\'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1\'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1\'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1\'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1\'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1\'b1)) begin
Pc_b1 = 1\'b1;
Act_b1 = 1\'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1\'b0;
Read_precharge[1] = 1\'b0;
RW_interrupt_read[1] = 1\'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
if ((Auto_precharge[2] == 1\'b1) && (Read_precharge[2] == 1\'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1\'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1\'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1\'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1\'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1\'b1)) begin
Pc_b2 = 1\'b1;
Act_b2 = 1\'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1\'b0;
Read_precharge[2] = 1\'b0;
RW_interrupt_read[2] = 1\'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
if ((Auto_precharge[3] == 1\'b1) && (Read_precharge[3] == 1\'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1\'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1\'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1\'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1\'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1\'b1)) begin
Pc_b3 = 1\'b1;
Act_b3 = 1\'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1\'b0;
Read_precharge[3] = 1\'b0;
RW_interrupt_read[3] = 1\'b0;
if (Debug) begin
$display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1\'b1) begin
if (Data_out_enable == 1\'b1) begin
Data_out_enable = 1\'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1\'b1) begin
Data_out_enable = 1\'b0;
end
end
if (Data_out_enable == 1\'b0) begin
Dq_reg <= #tOH {data_bits{1\'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2\'b00 : Row = B0_row_addr;
2\'b01 : Row = B1_row_addr;
2\'b10 : Row = B2_row_addr;
2\'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1\'b0;
Data_out_enable = 1\'b1;
end else if (Command[0] == `WRITE) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2\'b00 : Row = B0_row_addr;
2\'b01 : Row = B1_row_addr;
2\'b10 : Row = B2_row_addr;
2\'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1\'b1;
Data_out_enable = 1\'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1\'b1) begin // Writing Data to Memory
// Array buffer
case (Bank)
2\'b00 : Dq_dqm = Bank0 [{Row, Col}];
2\'b01 : Dq_dqm = Bank1 [{Row, Col}];
2\'b10 : Dq_dqm = Bank2 [{Row, Col}];
2\'b11 : Dq_dqm = Bank3 [{Row, Col}];
endcase
// Dqm operation
if (Dqm[0] == 1\'b0) begin
Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
end
if (Dqm[1] == 1\'b0) begin
Dq_dqm [15 : 8] = Dq [15 : 8];
end
// Write to memory
case (Bank)
2\'b00 : Bank0 [{Row, Col}] = Dq_dqm;
2\'b01 : Bank1 [{Row, Col}] = Dq_dqm;
2\'b10 : Bank2 [{Row, Col}] = Dq_dqm;
2\'b11 : Bank3 [{Row, Col}] = Dq_dqm;
endcase
// Display debug message
if (Dqm !== 2\'b11) begin
// Record tWR for manual precharge
WR_chkm [Bank] = $time;
if (Debug) begin
$display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_dqm);
end
end else begin
if (Debug) begin
$display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end
end
// Advance burst counter subroutine
#tHZ Burst_decode;
end else if (Data_out_enable == 1\'b1) begin // Reading Data from Memory
// Array buffer
case (Bank)
2\'b00 : Dq_dqm = Bank0[{Row, Col}];
2\'b01 : Dq_dqm = Bank1[{Row, Col}];
2\'b10 : Dq_dqm = Bank2[{Row, Col}];
2\'b11 : Dq_dqm = Bank3[{Row, Col}];
endcase
// Dqm operation
if (Dqm_reg0 [0] == 1\'b1) begin
Dq_dqm [ 7 : 0] = 8\'bz;
end
if (Dqm_reg0 [1] == 1\'b1) begin
Dq_dqm [15 : 8] = 8\'bz;
end
// Display debug message
if (Dqm_reg0 !== 2\'b11) begin
Dq_reg = #tAC Dq_dqm; //XXX
if (Debug) begin
$display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_reg);
end
end else begin
Dq_reg = #tHZ {data_bits{1\'bz}};
if (Debug) begin
$display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end
end
// Advance burst counter subroutine
Burst_decode;
end
end
// Burst counter decode
task Burst_decode;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1\'b0) begin // Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1\'b1) begin // Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin // Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin // Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin // Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin // Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1\'b1) begin
Data_in_enable = 1\'b0;
end
// Data Counter
if (Burst_length_1 == 1\'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1\'b0;
Data_out_enable = 1\'b0;
end
end else if (Burst_length_2 == 1\'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1\'b0;
Data_out_enable = 1\'b0;
end
end else if (Burst_length_4 == 1\'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1\'b0;
Data_out_enable = 1\'b0;
end
end else if (Burst_length_8 == 1\'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1\'b0;
Data_out_enable = 1\'b0;
end
end
end
endtask
// Timing Parameters for -7E (133 MHz @ CL2)
specify
specparam
tAH = 0.8, // Addr, Ba Hold Time
tAS = 1.5, // Addr, Ba Setup Time
tCH = 2.5, // Clock High-Level Width
tCL = 2.5, // Clock Low-Level Width
tCK = 7.0, // Clock Cycle Time
tDH = 0.8, // Data-in Hold Time
tDS = 1.5, // Data-in Setup Time
tCKH = 0.8, // CKE Hold Time
tCKS = 1.5, // CKE Setup Time
tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
$width (posedge Clk, tCH);
$width (negedge Clk, tCL);
$period (negedge Clk, tCK);
$period (posedge Clk, tCK);
$setuphold(posedge Clk, Cke, tCKS, tCKH);
$setuphold(posedge Clk, Cs_n, tCMS, tCMH);
$setuphold(posedge Clk, Cas_n, tCMS, tCMH);
$setuphold(posedge Clk, Ras_n, tCMS, tCMH);
$setuphold(posedge Clk, We_n, tCMS, tCMH);
$setuphold(posedge Clk, Addr, tAS, tAH);
$setuphold(posedge Clk, Ba, tAS, tAH);
$setuphold(posedge Clk, Dqm, tCMS, tCMH);
$setuphold(posedge Dq_chk, Dq, tDS, tDH);
endspecify
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// generic FIFO, uses LFSRs for read/write pointers ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS\'\' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: vga_fifo.v,v 1.8 2003-08-01 11:46:38 rherveille Exp $
//
// $Date: 2003-08-01 11:46:38 $
// $Revision: 1.8 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/05/07 09:48:54 rherveille
// Fixed some Wishbone RevB.3 related bugs.
// Changed layout of the core. Blocks are located more logically now.
// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.
//
// Revision 1.6 2002/02/07 05:42:10 rherveille
// Fixed some bugs discovered by modified testbench
// Removed / Changed some strange logic constructions
// Started work on hardware cursor support (not finished yet)
// Changed top-level name to vga_enh_top.v
//
/*
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
*/
`timescale 1ns / 1ps
// set FIFO_RW_CHECK to prevent writing to a full and reading from an empty FIFO
//`define FIFO_RW_CHECK
// Long Pseudo Random Generators can generate (N^2 -1) combinations. This means
// 1 FIFO entry is unavailable. This might be a problem, especially for small
// FIFOs. Setting VGA_FIFO_ALL_ENTRIES creates additional logic that ensures that
// all FIFO entries are used at the expense of some additional logic.
`define VGA_FIFO_ALL_ENTRIES
module vga_fifo (
\tclk,
\taclr,
\tsclr,
\twreq,
\trreq,
\td,
\tq,
\tnword,
\tempty,
\tfull,
\taempty,
\tafull
\t);
\t//
\t// parameters
\t//
\tparameter aw = 3; // no.of entries (in bits; 2^7=128 entries)
\tparameter dw = 8; // datawidth (in bits)
\t//
\t// inputs & outputs
\t//
\tinput clk; // master clock
\tinput aclr; // asynchronous active low reset
\tinput sclr; // synchronous active high reset
\tinput wreq; // write request
\tinput rreq; // read request
\tinput [dw:1] d; // data-input
\toutput [dw:1] q; // data-output
\toutput [aw:0] nword; // number of words in FIFO
\toutput empty; // fifo empty
\toutput full; // fifo full
\toutput aempty; // fifo asynchronous/almost empty (1 entry left)
\toutput afull; // fifo asynchronous/almost full (1 entry left)
\treg [aw:0] nword;
\treg empty, full;
\t//
\t// Module body
\t//
\treg [aw:1] rp, wp;
\twire [dw:1] ramq;
\twire fwreq, frreq;
`ifdef VGA_FIFO_ALL_ENTRIES
\tfunction lsb;
\t input [aw:1] q;
\t case (aw)
\t 2: lsb = ~q[2];
\t 3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);
\t 4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);
\t 5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);
\t 6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);
\t 7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);
\t 8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
\t 9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);
\t 10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);
\t 11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);
\t 12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
\t 13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
\t 14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
\t 15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);
\t 16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
\t endcase
\tendfunction
`else
\tfunction lsb;
\t input [aw:1] q;
\t case (aw)
\t 2: lsb = ~q[2];
\t 3: lsb = ~(q[3] ^ q[2]);
\t 4: lsb = ~(q[4] ^ q[3]);
\t 5: lsb = ~(q[5] ^ q[3]);
\t 6: lsb = ~(q[6] ^ q[5]);
\t 7: lsb = ~(q[7] ^ q[6]);
\t 8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
\t 9: lsb = ~(q[9] ^ q[5]);
\t 10: lsb = ~(q[10] ^ q[7]);
\t 11: lsb = ~(q[11] ^ q[9]);
\t 12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
\t 13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
\t 14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
\t 15: lsb = ~(q[15] ^ q[14]);
\t 16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
\t endcase
\tendfunction
`endif
`ifdef RW_CHECK
assign fwreq = wreq & ~full;
assign frreq = rreq & ~empty;
`else
assign fwreq = wreq;
assign frreq = rreq;
`endif
\t//
\t// hookup read-pointer
\t//
\talways @(posedge clk or negedge aclr)
\t if (~aclr) rp <= #1 0;
\t else if (sclr) rp <= #1 0;
\t else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)};
\t//
\t// hookup write-pointer
\t//
\talways @(posedge clk or negedge aclr)
\t if (~aclr) wp <= #1 0;
\t else if (sclr) wp <= #1 0;
\t else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)};
\t//
\t// hookup memory-block
\t//
\treg [dw:1] mem [(1<<aw) -1:0];
\t// memory array operations
\talways @(posedge clk)
\t if (fwreq)
\t mem[wp] <= #1 d;
\tassign q = mem[rp];
\t// generate full/empty signals
\tassign aempty = (rp[aw-1:1] == wp[aw:2]) & (lsb(rp) == wp[1]) & frreq & ~fwreq;
\talways @(posedge clk or negedge aclr)
\t if (~aclr)
\t empty <= #1 1\'b1;
\t else if (sclr)
\t empty <= #1 1\'b1;
\t else
\t empty <= #1 aempty | (empty & (~fwreq + frreq));
\tassign afull = (wp[aw-1:1] == rp[aw:2]) & (lsb(wp) == rp[1]) & fwreq & ~frreq;
\talways @(posedge clk or negedge aclr)
\t if (~aclr)
\t full <= #1 1\'b0;
\t else if (sclr)
\t full <= #1 1\'b0;
\t else
\t full <= #1 afull | ( full & (~frreq + fwreq) );
\t// number of words in fifo
\talways @(posedge clk or negedge aclr)
\t if (~aclr)
\t nword <= #1 0;
\t else if (sclr)
\t nword <= #1 0;
\t else
\t begin
\t if (wreq & !rreq)
\t nword <= #1 nword +1;
\t else if (rreq & !wreq)
\t nword <= #1 nword -1;
\t end
\t//
\t// Simulation checks
\t//
\t// synopsys translate_off
\talways @(posedge clk)
\t if (full & fwreq)
\t $display("Writing while FIFO full (%m)\
");
\talways @(posedge clk)
\t if (empty & frreq)
\t $display("Reading while FIFO empty (%m)\
");
\t// synopsys translate_on
endmodule
|
/*
* Internal RAM for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vdu_ram_2k_attr (
input clk,
input rst,
input we,
input [10:0] addr,
output [ 7:0] rdata,
input [ 7:0] wdata
);
// Registers and nets
reg [ 7:0] mem[0:2047];
reg [10:0] addr_reg;
always @(posedge clk)
begin
if (we) mem[addr] <= wdata;
addr_reg <= addr;
end
// Combinatorial logic
assign rdata = mem[addr_reg];
initial $readmemh("attr_rom.dat", mem);
endmodule
|
/*
* Wishbone Flash RAM core for Altera DE0 board
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module flash16 (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_we_i,
input wb_adr_i, // Wishbone address line
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// Pad signals
output [21:0] flash_addr_,
input [15:0] flash_data_,
output flash_we_n_,
output flash_oe_n_,
output flash_ce_n_,
output flash_rst_n_
);
// Registers and nets
wire op;
wire wr_command;
reg [21:0] address;
// Combinatorial logic
assign op = wb_stb_i & wb_cyc_i;
assign flash_rst_n_ = 1'b1;
assign flash_we_n_ = 1'b1;
assign flash_oe_n_ = !op;
assign flash_ce_n_ = !op;
assign flash_addr_ = address;
assign wr_command = op & wb_we_i; // Wishbone write access Signal
assign wb_ack_o = op;
assign wb_dat_o = flash_data_;
// --------------------------------------------------------------------
// Register addresses and defaults
// --------------------------------------------------------------------
`define FLASH_ALO 1'h0 // Lower 16 bits of address lines
`define FLASH_AHI 1'h1 // Upper 6 bits of address lines
always @(posedge wb_clk_i) // Synchrounous
if(wb_rst_i)
address <= 22'h000000; // Interupt Enable default
else
if(wr_command) // If a write was requested
case(wb_adr_i) // Determine which register was writen to
`FLASH_ALO: address[15: 0] <= wb_dat_i;
`FLASH_AHI: address[21:16] <= wb_dat_i[5:0];
default: ; // Default
endcase // End of case
endmodule
|
/*
* Character ROM for text mode fonts
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// altera message_off 10030
// get rid of the warning about
// not initializing the ROM
module vga_char_rom (
input clk,
input [11:0] addr,
output reg [ 7:0] q
);
// Registers, nets and parameters
reg [7:0] rom[0:4095];
// Behaviour
always @(posedge clk) q <= rom[addr];
initial $readmemh("char_rom.dat", rom);
endmodule
|
/*\r
* PS2 Wishbone 8042 compatible keyboard controller\r
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>\r
* adapted from the opencores keyboard controller from John Clayton\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
// --------------------------------------------------------------------\r
// PS2 8042 partially compatible keyboard controller\r
// (can not receive commands from host)\r
// --------------------------------------------------------------------\r
\r
`define TOTAL_BITS 11\r
`define RELEASE_CODE 16\'hF0\r
`define LEFT_SHIFT 16\'h12\r
`define RIGHT_SHIFT 16\'h59\r
\r
module ps2_keyb (\r
output released,\r
output rx_shifting_done,\r
output tx_shifting_done,\r
input reset, // Main reset line\r
input clk, // Main Clock\r
output [7:0] scancode, // scancode\r
output rx_output_strobe, // Signals a key presseed\r
input ps2_clk_, // PS2 PAD signals\r
inout ps2_data_\r
);\r
\r
// --------------------------------------------------------------------\r
// Parameter declarations, the timer value can be up to (2^bits) inclusive.\r
// --------------------------------------------------------------------\r
parameter TIMER_60USEC_VALUE_PP = 1920; // Number of sys_clks for 60usec.\r
parameter TIMER_60USEC_BITS_PP = 11; // Number of bits needed for timer\r
parameter TIMER_5USEC_VALUE_PP = 186; // Number of sys_clks for debounce\r
parameter TIMER_5USEC_BITS_PP = 8; // Number of bits needed for timer\r
parameter TRAP_SHIFT_KEYS_PP = 0; // Default: No shift key trap.\r
\r
// --------------------------------------------------------------------\r
// State encodings, provided as parametersf or flexibility to the one\r
// instantiating the module. In general, the default values need not be changed.\r
//\r
// State "m1_rx_clk_l" has been chosen on purpose. Since the inputs ynchronizing\r
// flip-flops initially contain zero, it takes one clkfor them to update to reflect\r
// the actual (idle = high) status oft he I/O lines from the keyboard. Therefore,\r
// choosing 0 for m1_rx_clk_la llows the state machine to transition to m1_rx_clk_h\r
// when the true values of the input signals become present at the outputs of the\r
// synchronizing flip-flops. This initial transition is harmless, and it\r
// eliminates the need for a "reset" pulse before the interface can operate.\r
// --------------------------------------------------------------------\r
parameter m1_rx_clk_h = 1;\r
parameter m1_rx_clk_l = 0;\r
parameter m1_rx_falling_edge_marker = 13;\r
parameter m1_rx_rising_edge_marker = 14;\r
parameter m1_tx_force_clk_l = 3;\r
parameter m1_tx_first_wait_clk_h = 10;\r
parameter m1_tx_first_wait_clk_l = 11;\r
parameter m1_tx_reset_timer = 12;\r
parameter m1_tx_wait_clk_h = 2;\r
parameter m1_tx_clk_h = 4;\r
parameter m1_tx_clk_l = 5;\r
parameter m1_tx_wait_keyboard_ack = 6;\r
parameter m1_tx_done_recovery = 7;\r
parameter m1_tx_error_no_keyboard_ack = 8;\r
parameter m1_tx_rising_edge_marker = 9;\r
\r
// --------------------------------------------------------------------\r
// Nets and registers\r
// --------------------------------------------------------------------\r
wire rx_output_event;\r
//assign tx_shifting_done;\r
wire timer_60usec_done;\r
wire timer_5usec_done;\r
wire [6:0] xt_code;\r
reg [7:0] dat_o;\r
reg [3:0] bit_count;\r
reg [3:0] m1_state;\r
reg [3:0] m1_next_state;\r
//reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.\r
reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.\r
reg ps2_clk_s; // Synchronous version of this input\r
reg ps2_data_s; // Synchronous version of this input\r
reg enable_timer_60usec;\r
reg enable_timer_5usec;\r
reg hold_released; // Holds prior value, cleared at rx_output_strobe\r
\r
reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;\r
reg [TIMER_5USEC_BITS_PP-1 :0] timer_5usec_count;\r
reg [`TOTAL_BITS-1:0] q_r;\r
wire [`TOTAL_BITS-1:0] q;\r
\r
// hack for the F5-F7 key bug\r
assign q = (q_r[8:1]==8\'h83)?{q_r[`TOTAL_BITS-1:9],8\'h02,q_r[0]} : q_r;\r
\r
// --------------------------------------------------------------------\r
// Module instantiation\r
// --------------------------------------------------------------------\r
ps2_keyb_xtcodes keyb_xtcodes (\r
.at_code (q[7:1]),\r
.xt_code (xt_code)\r
);\r
\r
// --------------------------------------------------------------------\r
// Continuous assignments\r
// This signal is high for one clock at the end of the timer count.\r
// --------------------------------------------------------------------\r
assign rx_shifting_done = (bit_count == `TOTAL_BITS);\r
assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);\r
assign rx_output_event = (rx_shifting_done && ~released );\r
assign rx_output_strobe = (rx_shifting_done && ~released\r
&& ( (TRAP_SHIFT_KEYS_PP == 0) || ( (q[8:1] != `RIGHT_SHIFT)\r
&&(q[8:1] != `LEFT_SHIFT) ) ) );\r
\r
//assign ps2_clk_ = ps2_clk_hi_z ? 1\'bZ : 1\'b0;\r
assign ps2_data_ = ps2_data_hi_z ? 1\'bZ : 1\'b0;\r
assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));\r
assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);\r
\r
assign scancode = dat_o;\r
\r
// --------------------------------------------------------------------\r
// Create the signals which indicate special scan codes received.\r
// These are the "unlatched versions."\r
// assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done;\r
// --------------------------------------------------------------------\r
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;\r
\r
// --------------------------------------------------------------------\r
// This is the shift register\r
// --------------------------------------------------------------------\r
always @(posedge clk)\r
if(reset) q_r <= 0;\r
else \r
if((m1_state == m1_rx_falling_edge_marker) ||(m1_state == m1_tx_rising_edge_marker)) q_r <= {ps2_data_s,q_r[`TOTAL_BITS-1:1]};\r
\r
// This is the 60usec timer counter\r
always @(posedge clk)\r
if(~enable_timer_60usec) timer_60usec_count <= 0;\r
else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 10\'d1;\r
\r
// This is the 5usec timer counter\r
always @(posedge clk)\r
if (~enable_timer_5usec) timer_5usec_count <= 0;\r
else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 6\'d1;\r
\r
// --------------------------------------------------------------------\r
// Input "synchronizing" logic -- synchronizes the inputs to the state\r
// machine clock, thus avoiding errors related to spurious state machine transitions.\r
//\r
// Since the initial state of registers is zero, and the idle state\r
// of the ps2_clk and ps2_data lines is "1" (due to pullups), the\r
// "sense" of the ps2_clk_s signal is inverted from the true signal.\r
// This allows the state machine to "come up" in the correct\r
always @(posedge clk) begin\r
ps2_clk_s <= ps2_clk_;\r
ps2_data_s <= ps2_data_;\r
end\r
\r
// State transition logic\r
always @(m1_state\r
or q\r
or tx_shifting_done\r
or ps2_clk_s\r
or ps2_data_s\r
or timer_60usec_done\r
or timer_5usec_done\r
)\r
begin : m1_state_logic\r
\r
// Output signals default to this value,\r
// unless changed in a state condition.\r
//ps2_clk_hi_z <= 1;\r
ps2_data_hi_z <= 1;\r
enable_timer_60usec <= 0;\r
enable_timer_5usec <= 0;\r
\r
case (m1_state)\r
\r
m1_rx_clk_h :\r
begin\r
enable_timer_60usec <= 1;\r
if (~ps2_clk_s)\r
m1_next_state <= m1_rx_falling_edge_marker;\r
else m1_next_state <= m1_rx_clk_h;\r
end\r
\r
m1_rx_falling_edge_marker :\r
begin\r
enable_timer_60usec <= 0;\r
m1_next_state <= m1_rx_clk_l;\r
end\r
\r
m1_rx_rising_edge_marker :\r
begin\r
enable_timer_60usec <= 0;\r
m1_next_state <= m1_rx_clk_h;\r
end\r
\r
m1_rx_clk_l :\r
begin\r
enable_timer_60usec <= 1;\r
if (ps2_clk_s)\r
m1_next_state <= m1_rx_rising_edge_marker;\r
else m1_next_state <= m1_rx_clk_l;\r
end\r
\r
m1_tx_reset_timer :\r
begin\r
enable_timer_60usec <= 0;\r
m1_next_state <= m1_tx_force_clk_l;\r
end\r
\r
m1_tx_force_clk_l :\r
begin\r
enable_timer_60usec <= 1;\r
//ps2_clk_hi_z <= 0; // Force the ps2_clk line low.\r
if (timer_60usec_done)\r
m1_next_state <= m1_tx_first_wait_clk_h;\r
else m1_next_state <= m1_tx_force_clk_l;\r
end\r
\r
m1_tx_first_wait_clk_h :\r
begin\r
enable_timer_5usec <= 1;\r
ps2_data_hi_z <= 0; // Start bit.\r
if (~ps2_clk_s && timer_5usec_done)\r
m1_next_state <= m1_tx_clk_l;\r
else\r
m1_next_state <= m1_tx_first_wait_clk_h;\r
end\r
\r
// This state must be included because the device might possibly\r
// delay for up to 10 milliseconds before beginning its clock pulses.\r
// During that waiting time, we cannot drive the data (q[0]) because it\r
// is possibly 1, which would cause the keyboard to abort its receive\r
// and the expected clocks would then never be generated.\r
m1_tx_first_wait_clk_l :\r
begin\r
ps2_data_hi_z <= 0;\r
if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;\r
else m1_next_state <= m1_tx_first_wait_clk_l;\r
end\r
\r
m1_tx_wait_clk_h :\r
begin\r
enable_timer_5usec <= 1;\r
ps2_data_hi_z <= q[0];\r
if (ps2_clk_s && timer_5usec_done)\r
m1_next_state <= m1_tx_rising_edge_marker;\r
else\r
m1_next_state <= m1_tx_wait_clk_h;\r
end\r
\r
m1_tx_rising_edge_marker :\r
begin\r
ps2_data_hi_z <= q[0];\r
m1_next_state <= m1_tx_clk_h;\r
end\r
\r
m1_tx_clk_h :\r
begin\r
ps2_data_hi_z <= q[0];\r
if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;\r
else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;\r
else m1_next_state <= m1_tx_clk_h;\r
end\r
\r
m1_tx_clk_l :\r
begin\r
ps2_data_hi_z <= q[0];\r
if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;\r
else m1_next_state <= m1_tx_clk_l;\r
end\r
\r
m1_tx_wait_keyboard_ack :\r
begin\r
if (~ps2_clk_s && ps2_data_s)\r
m1_next_state <= m1_tx_error_no_keyboard_ack;\r
else if (~ps2_clk_s && ~ps2_data_s)\r
m1_next_state <= m1_tx_done_recovery;\r
else m1_next_state <= m1_tx_wait_keyboard_ack;\r
end\r
\r
m1_tx_done_recovery :\r
begin\r
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;\r
else m1_next_state <= m1_tx_done_recovery;\r
end\r
\r
m1_tx_error_no_keyboard_ack :\r
begin\r
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;\r
else m1_next_state <= m1_tx_error_no_keyboard_ack;\r
end\r
\r
default : m1_next_state <= m1_rx_clk_h;\r
endcase\r
end\r
\r
// State register\r
always @(posedge clk)\r
begin : m1_state_register\r
if(reset) m1_state <= m1_rx_clk_h;\r
else m1_state <= m1_next_state;\r
end\r
\r
// dat_o - scancode\r
always @(posedge clk)\r
if(reset) dat_o <= 8\'b0;\r
else dat_o <= (rx_output_strobe && q[8:1]) ? (q[8] ? q[8:1] : {hold_released,xt_code}) : dat_o;\r
\r
// This is the bit counter\r
always @(posedge clk)\r
begin\r
if(reset || rx_shifting_done || (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.\r
) bit_count <= 0; // normal reset\r
else if (timer_60usec_done && (m1_state == m1_rx_clk_h) && (ps2_clk_s)\r
) bit_count <= 0; // rx watchdog timer reset\r
else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx\r
||(m1_state == m1_tx_rising_edge_marker) // increment for tx\r
)\r
bit_count <= bit_count + 4\'d1;\r
end\r
\r
// Store the special scan code status bits\r
// Not the final output, but an intermediate storage place,\r
// until the entire set of output data can be assembled.\r
always @(posedge clk)\r
if(reset || rx_output_event) hold_released <= 0;\r
else if (rx_shifting_done && released) hold_released <= 1;\r
\r
endmodule\r
|
/*\r
* DUT VGA LCD FML\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
//`timescale 1ns/10ps\r
`timescale 1ns/1ps\r
\r
module tb_vga_lcd_fml;\r
\r
// Registers and nets\r
reg clk_100;\r
reg rst;\r
\r
reg shift_reg1; // if set: 320x200\r
reg graphics_alpha; // if not set: 640x400 text mode\r
\r
// VGA LCD FML master interface\r
wire [20-1:0] fml_adr;\r
wire fml_stb;\r
reg fml_we;\r
reg fml_ack;\r
wire [1:0] fml_sel;\r
wire [15:0] fml_do;\r
reg [15:0] fml_di;\r
\r
// VGA LCD Direct Cache Bus\r
wire dcb_stb;\r
wire [20-1:0] dcb_adr;\r
reg [15:0] dcb_dat;\r
reg dcb_hit;\r
\t\r
// attribute_ctrl\r
reg [3:0] pal_addr;\r
reg pal_we;\r
wire [7:0] pal_read;\r
reg [7:0] pal_write;\r
\r
// dac_regs\r
reg dac_we;\r
reg [1:0] dac_read_data_cycle;\r
reg [7:0] dac_read_data_register;\r
wire [3:0] dac_read_data;\r
reg [1:0] dac_write_data_cycle;\r
reg [7:0] dac_write_data_register;\r
reg [3:0] dac_write_data;\r
\r
// VGA pad signals\r
wire [3:0] vga_red_o;\r
wire [3:0] vga_green_o;\r
wire [3:0] vga_blue_o;\r
wire horiz_sync;\r
wire vert_sync;\r
\r
// Base address of video memory\r
reg [15:0] start_addr;\r
\r
// CRTC\r
reg [5:0] cur_start;\r
reg [5:0] cur_end;\r
reg [4:0] vcursor;\r
reg [6:0] hcursor;\r
\r
reg [6:0] horiz_total;\r
reg [6:0] end_horiz;\r
reg [6:0] st_hor_retr;\r
reg [4:0] end_hor_retr;\r
reg [9:0] vert_total;\r
reg [9:0] end_vert;\r
reg [9:0] st_ver_retr;\r
reg [3:0] end_ver_retr;\r
\r
reg x_dotclockdiv2;\r
\r
// retrace signals\r
wire v_retrace;\r
wire vh_retrace;\r
\r
wire vga_clk;\r
\r
/* Process FML requests */\r
reg [2:0] fml_wcount;\r
reg [2:0] fml_rcount;\r
reg [3:0] fml_pipe;\r
initial begin\r
\t fml_ack = 1\'b0;\r
\t fml_wcount = 0;\r
\t fml_rcount = 0;\r
end\r
\r
always @(posedge clk_100)\r
fml_pipe <= rst ? 4\'b0 : { fml_pipe[2:0], fml_stb };\r
\r
always @(posedge clk_100) begin\r
\t if(fml_stb & (fml_wcount == 0) & (fml_rcount == 0)) begin\r
\t\t fml_ack <= 1\'b1;\r
\t\t if(fml_we) begin\r
\t\t\t //$display("%t FML W addr %x data %x", $time, fml_adr, fml_dw);\r
\t\t\t fml_wcount <= 7;\r
\t\t end else begin\r
\t\t\t fml_di = 16\'hbeef;\r
\t\t\t //$display("%t FML R addr %x data %x", $time, fml_adr, fml_di);\r
\t\t\t fml_rcount <= 7;\r
\t\t end\r
\t end else\r
\t\t fml_ack <= 1\'b0;\r
\t if(fml_wcount != 0) begin\r
\t\t //#1 $display("%t FML W continuing %x / %d", $time, fml_dw, fml_wcount);\r
\t\t fml_wcount <= fml_wcount - 1;\r
\t end\r
\t if(fml_rcount != 0) begin\r
\t\t //fml_di = #1 {13\'h1eba, fml_rcount};\r
\t\t fml_di = {13\'h1eba, fml_rcount};\r
\t\t //$display("%t FML R continuing %x / %d", $time, fml_di, fml_rcount);\r
\t\t fml_rcount <= fml_rcount - 1;\r
\t end\r
end\r
\r
/* Process DCB requests */\r
//reg [15:0] dcb_dat;\r
reg [2:0] dcb_rcount;\r
reg [3:0] dcb_pipe;\r
initial begin\r
\t dcb_hit = 1\'b0;\t \r
\t dcb_rcount = 0;\r
end\r
\r
always @(posedge clk_100)\r
dcb_pipe <= rst ? 4\'b0 : { dcb_pipe[2:0], dcb_stb };\r
\r
always @(posedge clk_100) begin\r
//if (dcb_stb)\r
//$display("%t DCB R addr %x", $time, dcb_adr);\r
if (dcb_stb & (dcb_rcount == 0))\r
begin\r
dcb_hit <= 1\'b1;\r
//dcb_hit <= 1\'b0;\r
\t\t dcb_dat = 16\'hbeef;\r
\t\t\t //$display("%t DCB R addr %x data %x", $time, dcb_adr, dcb_dat);\r
\t\t\t dcb_rcount <= 7;\r
\t\t end else\r
\t\t dcb_hit <= 1\'b0;\t\t\r
\t if(dcb_stb & (dcb_rcount != 0)) begin\r
\t\t //dcb_dat = #1 {13\'h1eba, dcb_rcount};\r
\t\t dcb_dat = {13\'h1eba, dcb_rcount};\r
\t\t //$display("%t DCB R continuing %x / %d", $time, dcb_dat, dcb_rcount);\r
\t\t dcb_rcount <= dcb_rcount - 1;\r
\t end\t \r
end\r
\r
// Module instantiations\r
vga_lcd_fml #(\r
.fml_depth (20) // 8086 can only address 1 MB \r
) dut (\r
.clk(clk_100), // 100 Mhz clock\r
.rst(rst),\r
\r
.shift_reg1(shift_reg1), // if set: 320x200\r
.graphics_alpha(graphics_alpha), // if not set: 640x400 text mode\r
\r
// VGA LCD FML master interface\r
.fml_adr(fml_adr),\r
.fml_stb(fml_stb),\r
.fml_we(fml_we),\r
.fml_ack(fml_ack),\r
.fml_sel(fml_sel),\r
.fml_do(fml_do),\r
.fml_di(fml_di),\r
\r
// VGA LCD Direct Cache Bus\r
.dcb_stb(dcb_stb),\r
.dcb_adr(dcb_adr),\r
.dcb_dat(dcb_dat),\r
.dcb_hit(dcb_hit),\r
\r
// attribute_ctrl\r
.pal_addr(pal_addr),\r
.pal_we(pal_we),\r
.pal_read(pal_read),\r
.pal_write(pal_write),\r
\r
// dac_regs\r
.dac_we(dac_we),\r
.dac_read_data_cycle(dac_read_data_cycle),\r
.dac_read_data_register(dac_read_data_register),\r
.dac_read_data(dac_read_data),\r
.dac_write_data_cycle(dac_write_data_cycle),\r
.dac_write_data_register(dac_write_data_register),\r
.dac_write_data(dac_write_data),\r
\r
// VGA pad signals\r
.vga_red_o(vga_red_o),\r
.vga_green_o(vga_green_o),\r
.vga_blue_o(vga_blue_o),\r
.horiz_sync(horiz_sync),\r
.vert_sync(vert_sync),\r
\r
// Base address of video memory\r
.start_addr(start_addr),\r
\r
// CRTC\r
.cur_start(cur_start),\r
.cur_end(cur_end),\r
.vcursor(vcursor),\r
.hcursor(hcursor),\r
\r
.horiz_total(horiz_total),\r
.end_horiz(end_horiz),\r
.st_hor_retr(st_hor_retr),\r
.end_hor_retr(end_hor_retr),\r
.vert_total(vert_total),\r
.end_vert(end_vert),\r
.st_ver_retr(st_ver_retr),\r
.end_ver_retr(end_ver_retr),\r
\r
.x_dotclockdiv2(x_dotclockdiv2),\r
\r
// retrace signals\r
.v_retrace(v_retrace),\r
.vh_retrace(vh_retrace),\r
\r
.vga_clk(vga_clk)\r
);\r
\r
// Continuous assignments\r
\r
\r
// Behaviour\r
// Clock generation\r
//always #10 clk_100 <= !clk_100;\r
initial clk_100 = 1\'b0;\r
always #5 clk_100 = ~clk_100;\r
\r
task waitclock;\r
begin\r
\t@(posedge clk_100);\r
\t#1;\r
end\r
endtask\r
\r
always begin\r
// Initialize to a known state\r
rst = 1\'b1; // reset is active \r
\r
waitclock; \r
\r
rst = 1\'b0;\r
\r
waitclock;\r
\r
/* \r
// Set Text Mode\r
shift_reg1 = 1\'b0; // if set: 320x200\r
graphics_alpha = 1\'b0; // if not set: 640x400 text mode\r
*/\r
\r
\r
\r
// Set Linear Mode\r
shift_reg1 = 1\'b1; // if set: 320x200\r
graphics_alpha = 1\'b1; // if not set: 640x400 text mode\r
\r
\r
// Base address of video memory\r
start_addr = 16\'h1000; \r
\r
// CRTC configuration signals\r
\r
cur_start = 5\'d0; // reg [5:0] cur_start,\r
cur_end = 5\'d0; // reg [5:0] cur_end,\r
vcursor = 4\'d0; // reg [4:0] vcursor,\r
hcursor = 6\'d0; // reg [6:0] hcursor,\r
\r
\r
horiz_total = 7\'d79; // reg [6:0] horiz_total,\r
//horiz_total = 7\'d639; // reg [6:0] horiz_total,\r
end_horiz = 7\'d750; // reg [6:0] end_horiz,\r
st_hor_retr = 7\'d760; // reg [6:0] st_hor_retr,\r
st_hor_retr = 7\'d656; // reg [6:0] st_hor_retr,\r
//end_hor_retr = 5\'d10; // reg [4:0] end_hor_retr,\r
end_hor_retr = 5\'d750; // reg [4:0] end_hor_retr,\r
end_hor_retr = 5\'d752; // reg [4:0] end_hor_retr,\r
vert_total = 10\'d399; // reg [9:0] vert_total,\r
end_vert = 10\'d550; // reg [9:0] end_vert,\r
st_ver_retr = 10\'d560; // reg [9:0] st_ver_retr,\r
//end_ver_retr = 4\'d10; // reg [3:0] end_ver_retr,\r
end_ver_retr = 4\'d750; // reg [3:0] end_ver_retr,\r
\r
x_dotclockdiv2 = 1\'b0; // reg x_dotclockdiv2\r
\r
repeat (20000) begin\r
waitclock;\r
end\r
\r
$stop;\r
\r
end \r
\r
endmodule
|
/*
* LCD controller for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_lcd (
input clk, // 25 Mhz clock
input rst,
input shift_reg1, // if set: 320x200
input graphics_alpha, // if not set: 640x400 text mode
// CSR slave interface for reading
output [17:1] csr_adr_o,
input [15:0] csr_dat_i,
output csr_stb_o,
// attribute_ctrl
input [3:0] pal_addr,
input pal_we,
output [7:0] pal_read,
input [7:0] pal_write,
// dac_regs
input dac_we,
input [1:0] dac_read_data_cycle,
input [7:0] dac_read_data_register,
output [3:0] dac_read_data,
input [1:0] dac_write_data_cycle,
input [7:0] dac_write_data_register,
input [3:0] dac_write_data,
// VGA pad signals
output reg [3:0] vga_red_o,
output reg [3:0] vga_green_o,
output reg [3:0] vga_blue_o,
output reg horiz_sync,
output reg vert_sync,
// CRTC
input [5:0] cur_start,
input [5:0] cur_end,
input [4:0] vcursor,
input [6:0] hcursor,
input [6:0] horiz_total,
input [6:0] end_horiz,
input [6:0] st_hor_retr,
input [4:0] end_hor_retr,
input [9:0] vert_total,
input [9:0] end_vert,
input [9:0] st_ver_retr,
input [3:0] end_ver_retr,
input x_dotclockdiv2,
// retrace signals
output v_retrace,
output vh_retrace
);
// Registers and nets
reg video_on_v;
reg video_on_h_i;
reg [1:0] video_on_h_p;
reg [9:0] h_count; // Horizontal pipeline delay is 2 cycles
reg [9:0] v_count; // 0 to VER_SCAN_END
wire [9:0] hor_disp_end;
wire [9:0] hor_scan_end;
wire [9:0] ver_disp_end;
wire [9:0] ver_sync_beg;
wire [3:0] ver_sync_end;
wire [9:0] ver_scan_end;
wire video_on;
wire [3:0] attr_wm;
wire [3:0] attr_tm;
wire [3:0] attr;
wire [7:0] index;
wire [7:0] index_pal;
wire [7:0] color;
reg [7:0] index_gm;
wire video_on_h_tm;
wire video_on_h_wm;
wire video_on_h_gm;
wire video_on_h;
reg horiz_sync_i;
reg [1:0] horiz_sync_p;
wire horiz_sync_tm;
wire horiz_sync_wm;
wire horiz_sync_gm;
wire [16:1] csr_tm_adr_o;
wire csr_tm_stb_o;
wire [17:1] csr_wm_adr_o;
wire csr_wm_stb_o;
wire [17:1] csr_gm_adr_o;
wire csr_gm_stb_o;
wire csr_stb_o_tmp;
wire [3:0] red;
wire [3:0] green;
wire [3:0] blue;
// Module instances
vga_text_mode text_mode (
.clk (clk),
.rst (rst),
// CSR slave interface for reading
.csr_adr_o (csr_tm_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_tm_stb_o),
.h_count (h_count),
.v_count (v_count),
.horiz_sync_i (horiz_sync_i),
.video_on_h_i (video_on_h_i),
.video_on_h_o (video_on_h_tm),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.attr (attr_tm),
.horiz_sync_o (horiz_sync_tm)
);
vga_planar planar (
.clk (clk),
.rst (rst),
// CSR slave interface for reading
.csr_adr_o (csr_wm_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_wm_stb_o),
.attr_plane_enable (4'hf),
.x_dotclockdiv2 (x_dotclockdiv2),
.h_count (h_count),
.v_count (v_count),
.horiz_sync_i (horiz_sync_i),
.video_on_h_i (video_on_h_i),
.video_on_h_o (video_on_h_wm),
.attr (attr_wm),
.horiz_sync_o (horiz_sync_wm)
);
vga_linear linear (
.clk (clk),
.rst (rst),
// CSR slave interface for reading
.csr_adr_o (csr_gm_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_gm_stb_o),
.h_count (h_count),
.v_count (v_count),
.horiz_sync_i (horiz_sync_i),
.video_on_h_i (video_on_h_i),
.video_on_h_o (video_on_h_gm),
.color (color),
.horiz_sync_o (horiz_sync_gm)
);
vga_palette_regs palette_regs (
.clk (clk),
.attr (attr),
.index (index_pal),
.address (pal_addr),
.write (pal_we),
.read_data (pal_read),
.write_data (pal_write)
);
vga_dac_regs dac_regs (
.clk (clk),
.index (index),
.red (red),
.green (green),
.blue (blue),
.write (dac_we),
.read_data_cycle (dac_read_data_cycle),
.read_data_register (dac_read_data_register),
.read_data (dac_read_data),
.write_data_cycle (dac_write_data_cycle),
.write_data_register (dac_write_data_register),
.write_data (dac_write_data)
);
// Continuous assignments
assign hor_scan_end = { horiz_total[6:2] + 1'b1, horiz_total[1:0], 3'h7 };
assign hor_disp_end = { end_horiz, 3'h7 };
assign ver_scan_end = vert_total + 10'd1;
assign ver_disp_end = end_vert + 10'd1;
assign ver_sync_beg = st_ver_retr;
assign ver_sync_end = end_ver_retr + 4'd1;
assign video_on = video_on_h && video_on_v;
assign attr = graphics_alpha ? attr_wm : attr_tm;
assign index = (graphics_alpha & shift_reg1) ? index_gm : index_pal;
assign video_on_h = video_on_h_p[1];
assign csr_adr_o = graphics_alpha ?
(shift_reg1 ? csr_gm_adr_o : csr_wm_adr_o) : { 1'b0, csr_tm_adr_o };
assign csr_stb_o_tmp = graphics_alpha ?
(shift_reg1 ? csr_gm_stb_o : csr_wm_stb_o) : csr_tm_stb_o;
assign csr_stb_o = csr_stb_o_tmp & (video_on_h_i | video_on_h) & video_on_v;
assign v_retrace = !video_on_v;
assign vh_retrace = v_retrace | !video_on_h;
// index_gm
always @(posedge clk)
index_gm <= rst ? 8'h0 : color;
// Sync generation & timing process
// Generate horizontal and vertical timing signals for video signal
always @(posedge clk)
if (rst)
begin
h_count <= 10'b0;
horiz_sync_i <= 1'b1;
v_count <= 10'b0;
vert_sync <= 1'b1;
video_on_h_i <= 1'b1;
video_on_v <= 1'b1;
end
else
begin
h_count <= (h_count==hor_scan_end) ? 10'b0 : h_count + 10'b1;
horiz_sync_i <= horiz_sync_i ? (h_count[9:3]!=st_hor_retr)
: (h_count[7:3]==end_hor_retr);
v_count <= (v_count==ver_scan_end && h_count==hor_scan_end) ? 10'b0
: ((h_count==hor_scan_end) ? v_count + 10'b1 : v_count);
vert_sync <= vert_sync ? (v_count!=ver_sync_beg)
: (v_count[3:0]==ver_sync_end);
video_on_h_i <= (h_count==hor_scan_end) ? 1'b1
: ((h_count==hor_disp_end) ? 1'b0 : video_on_h_i);
video_on_v <= (v_count==10'h0) ? 1'b1
: ((v_count==ver_disp_end) ? 1'b0 : video_on_v);
end
// Horiz sync
always @(posedge clk)
{ horiz_sync, horiz_sync_p } <= rst ? 3'b0
: { horiz_sync_p[1:0], graphics_alpha ?
(shift_reg1 ? horiz_sync_gm : horiz_sync_wm) : horiz_sync_tm };
// Video_on pipe
always @(posedge clk)
video_on_h_p <= rst ? 2'b0 : { video_on_h_p[0],
graphics_alpha ? (shift_reg1 ? video_on_h_gm : video_on_h_wm)
: video_on_h_tm };
// Colour signals
always @(posedge clk)
if (rst)
begin
vga_red_o <= 4'b0;
vga_green_o <= 4'b0;
vga_blue_o <= 4'b0;
end
else
begin
vga_blue_o <= video_on ? blue : 4'h0;
vga_green_o <= video_on ? green : 4'h0;
vga_red_o <= video_on ? red : 4'h0;
end
endmodule
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
`include "defines.v"
module zet_regfile (
output [15:0] a,
output [15:0] b,
output [15:0] c,
output [15:0] cs,
output [15:0] ip,
input [31:0] d,
output [15:0] s,
output reg [8:0] flags,
input wr,
input wrfl,
input wrhi,
input clk,
input rst,
input [ 3:0] addr_a,
input [ 3:0] addr_b,
input [ 3:0] addr_c,
input [ 3:0] addr_d,
input [ 1:0] addr_s,
input [ 8:0] iflags,
input word_op,
input a_byte,
input b_byte,
input c_byte,
output cx_zero,
input wr_ip0
);
// Net declarations
reg [15:0] r[15:0];
wire [7:0] a8, b8, c8;
wire [3:0] addr_a_8;
wire [3:0] addr_b_8;
wire [3:0] addr_c_8;
// Assignments
assign addr_a_8 = { 2\'b00, addr_a[1:0] };
assign addr_b_8 = { 2\'b00, addr_b[1:0] };
assign addr_c_8 = { 2\'b00, addr_c[1:0] };
assign a = (a_byte & ~addr_a[3]) ? { {8{a8[7]}}, a8} : r[addr_a];
assign a8 = addr_a[2] ? r[addr_a_8][15:8] : r[addr_a][7:0];
assign b = (b_byte & ~addr_b[3]) ? { {8{b8[7]}}, b8} : r[addr_b];
assign b8 = addr_b[2] ? r[addr_b_8][15:8] : r[addr_b][7:0];
assign c = (c_byte & ~addr_c[3]) ? { {8{c8[7]}}, c8} : r[addr_c];
assign c8 = addr_c[2] ? r[addr_c_8][15:8] : r[addr_c][7:0];
assign s = r[{2\'b10,addr_s}];
assign cs = r[9];
assign cx_zero = (addr_d==4\'d1) ? (d==16\'d0) : (r[1]==16\'d0);
assign ip = r[15];
// Behaviour
always @(posedge clk)
if (rst) begin
r[0] <= 16\'d0; r[1] <= 16\'d0;
r[2] <= 16\'d0; r[3] <= 16\'d0;
r[4] <= 16\'d0; r[5] <= 16\'d0;
r[6] <= 16\'d0; r[7] <= 16\'d0;
r[8] <= 16\'d0; r[9] <= 16\'hf000;
r[10] <= 16\'d0; r[11] <= 16\'d0;
r[12] <= 16\'d0; r[13] <= 16\'d0;
r[14] <= 16\'d0; r[15] <= 16\'hfff0;
flags <= 9\'d0;
end else
begin
if (wr) begin
if (word_op | addr_d[3:2]==2\'b10)
r[addr_d] <= word_op ? d[15:0] : {{8{d[7]}},d[7:0]};
else if (addr_d[3]~^addr_d[2]) r[addr_d][7:0] <= d[7:0];
else r[{2\'b0,addr_d[1:0]}][15:8] <= d[7:0];
end
if (wrfl) flags <= iflags;
if (wrhi) r[4\'d2] <= d[31:16];
if (wr_ip0) r[14] <= ip;
end
endmodule
|
/*\r
* Text mode graphics for VGA\r
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
/*\r
* Pipeline description\r
* h_count[3:0]\r
* 000\r
* 001 col_addr, row_addr\r
* 010 ver_addr, hor_addr\r
* 011 csr_adr_o\r
* 100 csr_adr_i\r
* 101 sram_addr_\r
* 110 csr_dat_o\r
* 111 char_data_out, attr_data_out\r
* 000 vga_shift\r
* 001 vga_blue_o <= vga_shift[7]\r
*/\r
\r
module vga_text_mode_fml (\r
input clk,\r
input rst,\r
\r
input enable,\r
\r
// CSR slave interface for reading\r
output reg [16:1] fml_adr_o,\r
input [15:0] fml_dat_i,\r
output fml_stb_o,\r
\r
input [9:0] h_count,\r
input [9:0] v_count,\r
input horiz_sync_i,\r
input video_on_h_i,\r
output video_on_h_o,\r
\r
// CRTC\r
input [5:0] cur_start,\r
input [5:0] cur_end,\r
input [4:0] vcursor,\r
input [6:0] hcursor,\r
\r
output reg [3:0] attr,\r
output horiz_sync_o\r
);\r
\r
// Registers and nets\r
reg [ 6:0] col_addr;\r
reg [ 4:0] row_addr;\r
reg [ 6:0] hor_addr;\r
reg [ 6:0] ver_addr;\r
wire [10:0] vga_addr;\r
\r
reg [ 15:0] fml1_dat;\r
\r
wire [11:0] char_addr;\r
wire [ 7:0] char_data_out;\r
reg [ 7:0] attr_data_out;\r
reg [ 7:0] char_addr_in;\r
\r
reg [15:0] pipe;\r
wire load_shift;\r
\r
reg [7:0] video_on_h;\r
reg [7:0] horiz_sync;\r
\r
wire fg_or_bg;\r
wire brown_bg;\r
wire brown_fg;\r
\r
reg [ 7:0] vga_shift;\r
reg [ 3:0] fg_colour;\r
reg [ 2:0] bg_colour;\r
reg [22:0] blink_count;\r
\r
// Cursor\r
reg cursor_on_v;\r
reg cursor_on_h;\r
reg cursor_on;\r
wire cursor_on1;\r
\r
// Module instances\r
vga_char_rom char_rom (\r
.clk (clk),\r
.addr (char_addr),\r
.q (char_data_out)\r
);\r
\r
// Continuous assignments\r
assign vga_addr = { 4'b0, hor_addr } + { ver_addr, 4'b0 };\r
assign char_addr = { char_addr_in, v_count[3:0] };\r
assign load_shift = pipe[7] | pipe[15];\r
assign video_on_h_o = video_on_h[7];\r
assign horiz_sync_o = horiz_sync[7];\r
assign fml_stb_o = pipe[2];\r
\r
assign fg_or_bg = vga_shift[7] ^ cursor_on;\r
\r
assign cursor_on1 = cursor_on_h && cursor_on_v;\r
\r
// Behaviour\r
// Address generation\r
always @(posedge clk)\r
if (rst)\r
begin\r
col_addr <= 7'h0;\r
row_addr <= 5'h0;\r
ver_addr <= 7'h0;\r
hor_addr <= 7'h0;\r
fml_adr_o <= 16'h0;\r
end\r
else\r
if (enable)\r
begin\r
// h_count[2:0] == 001\r
col_addr <= h_count[9:3];\r
row_addr <= v_count[8:4];\r
\r
// h_count[2:0] == 010\r
ver_addr <= { 2'b00, row_addr } + { row_addr, 2'b00 };\r
// ver_addr = row_addr x 5\r
hor_addr <= col_addr;\r
\r
// h_count[2:0] == 011\r
// vga_addr = row_addr * 80 + hor_addr\r
fml_adr_o <= { 3'h0, vga_addr, 2'b00 };\r
end\r
\r
// cursor\r
always @(posedge clk)\r
if (rst)\r
begin\r
cursor_on_v <= 1'b0;\r
cursor_on_h <= 1'b0;\r
end\r
else\r
if (enable)\r
begin\r
cursor_on_h <= (h_count[9:3] == hcursor[6:0]);\r
cursor_on_v <= (v_count[8:4] == vcursor[4:0])\r
&& ({2'b00, v_count[3:0]} >= cur_start)\r
&& ({2'b00, v_count[3:0]} <= cur_end);\r
end\r
\r
// FML 8x16 pipeline count\r
always @(posedge clk)\r
if (rst)\r
begin\r
pipe <= 15'b0;\r
end\r
else\r
if (enable)\r
begin\r
pipe <= { pipe[14:0], (h_count[3:0]==3'b0) };\r
end\r
\r
// Load FML 8x16 burst\r
always @(posedge clk)\r
if (enable)\r
begin\r
fml1_dat <= pipe[9] ? fml_dat_i[15:0] : fml1_dat;\r
end\r
\r
// attr_data_out\r
always @(posedge clk)\r
if (enable)\r
begin\r
if (pipe[5])\r
attr_data_out <= fml_dat_i[15:8];\r
else\r
if (pipe[13])\r
attr_data_out <= fml1_dat[15:8];\r
end\r
\r
// char_addr_in\r
always @(posedge clk)\r
if (enable)\r
begin\r
if (pipe[5])\r
char_addr_in <= fml_dat_i[7:0];\r
else\r
if (pipe[13])\r
char_addr_in <= fml1_dat[7:0];\r
end\r
\r
// video_on_h\r
always @(posedge clk)\r
if (rst)\r
begin\r
video_on_h <= 8'b0;\r
end\r
else\r
if (enable)\r
begin\r
video_on_h <= { video_on_h[6:0], video_on_h_i };\r
end\r
\r
// horiz_sync\r
always @(posedge clk)\r
if (rst)\r
begin\r
horiz_sync <= 8'b0;\r
end\r
else\r
if (enable)\r
begin\r
horiz_sync <= { horiz_sync[6:0], horiz_sync_i };\r
end\r
\r
// blink_count\r
always @(posedge clk)\r
if (rst)\r
begin\r
blink_count <= 23'h0;\r
end\r
else\r
if (enable)\r
begin\r
blink_count <= (blink_count + 23'h1);\r
end\r
\r
// Video shift register\r
always @(posedge clk)\r
if (rst)\r
begin\r
fg_colour <= 4'b0;\r
bg_colour <= 3'b0;\r
vga_shift <= 8'h0;\r
end\r
else\r
if (enable)\r
begin\r
if (load_shift)\r
begin\r
fg_colour <= attr_data_out[3:0];\r
bg_colour <= attr_data_out[6:4];\r
cursor_on <= (cursor_on1 | attr_data_out[7]) & blink_count[22];\r
vga_shift <= char_data_out;\r
end\r
else vga_shift <= { vga_shift[6:0], 1'b0 };\r
end\r
\r
// pixel attribute\r
always @(posedge clk)\r
if (rst)\r
begin\r
attr <= 4'h0;\r
end\r
else\r
if (enable)\r
begin\r
attr <= fg_or_bg ? fg_colour : { 1'b0, bg_colour };\r
end\r
\r
endmodule\r
|
/*
* 16-bit 8-way multiplexor
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_mux8_16(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
input [2:0] sel;
input [15:0] in0, in1, in2, in3, in4, in5, in6, in7;
output [15:0] out;
reg [15:0] out;
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
case(sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
3'd7: out = in7;
endcase
endmodule
|
/*
* Bitwise logical operations for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_bitlog (
input [15:0] x,
output [15:0] o,
output cfo,
output ofo
);
// Assignments
assign o = ~x; // Now we only do NEG
assign cfo = 1'b0;
assign ofo = 1'b0;
endmodule
|
/*\r
* Sequencer controller for VGA\r
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
module vga_sequencer_fml (\r
input clk, // 100 Mhz clock\r
input rst,\r
\r
input enable_sequencer,\r
\r
// Sequencer input signals\r
\r
input [9:0] h_count,\r
input horiz_sync_i,\r
\r
input [9:0] v_count,\r
input vert_sync,\r
\r
input video_on_h_i,\r
input video_on_v,\r
\r
// Sequencer configuration signals\r
\r
input shift_reg1, // if set: 320x200\r
input graphics_alpha, // if not set: 640x400 text mode\r
\r
// CSR slave interface for reading\r
output [17:1] fml_adr_o,\r
input [15:0] fml_dat_i,\r
output fml_stb_o,\r
\r
// CRTC\r
input [5:0] cur_start,\r
input [5:0] cur_end,\r
input [4:0] vcursor,\r
input [6:0] hcursor,\r
\r
input x_dotclockdiv2,\r
\r
// Sequencer output signals\r
\r
output horiz_sync_seq_o,\r
output vert_sync_seq_o,\r
output video_on_h_seq_o,\r
output video_on_v_seq_o,\r
output [7:0] character_seq_o \r
\r
);\r
\r
// Registers and nets \r
reg [1:0] video_on_h_p;\r
\r
wire [3:0] attr_wm;\r
wire [3:0] attr_tm;\r
wire [7:0] color;\r
\r
wire video_on_h_tm;\r
wire video_on_h_wm;\r
wire video_on_h_gm;\r
wire video_on_h;\r
\r
wire horiz_sync_tm;\r
wire horiz_sync_wm;\r
wire horiz_sync_gm;\r
\r
wire [16:1] csr_tm_adr_o;\r
wire csr_tm_stb_o;\r
wire [17:1] csr_wm_adr_o;\r
wire csr_wm_stb_o;\r
wire [17:1] csr_gm_adr_o;\r
wire csr_gm_stb_o;\r
wire fml_stb_o_tmp;\r
\r
// Module instances\r
vga_text_mode_fml text_mode (\r
.clk (clk),\r
.rst (rst),\r
\r
.enable (enable_sequencer),\r
\r
// CSR slave interface for reading\r
.fml_adr_o (csr_tm_adr_o),\r
.fml_dat_i (fml_dat_i),\r
.fml_stb_o (csr_tm_stb_o),\r
\r
.h_count (h_count),\r
.v_count (v_count),\r
.horiz_sync_i (horiz_sync_i),\r
.video_on_h_i (video_on_h_i),\r
.video_on_h_o (video_on_h_tm),\r
\r
.cur_start (cur_start),\r
.cur_end (cur_end),\r
.vcursor (vcursor),\r
.hcursor (hcursor),\r
\r
.attr (attr_tm),\r
.horiz_sync_o (horiz_sync_tm)\r
);\r
\r
vga_planar_fml planar (\r
.clk (clk),\r
.rst (rst),\r
\r
.enable (enable_sequencer),\r
\r
// CSR slave interface for reading\r
.fml_adr_o (csr_wm_adr_o),\r
.fml_dat_i (fml_dat_i),\r
.fml_stb_o (csr_wm_stb_o),\r
\r
.attr_plane_enable (4'hf),\r
.x_dotclockdiv2 (x_dotclockdiv2),\r
\r
.h_count (h_count),\r
.v_count (v_count),\r
.horiz_sync_i (horiz_sync_i),\r
.video_on_h_i (video_on_h_i),\r
.video_on_h_o (video_on_h_wm),\r
\r
.attr (attr_wm),\r
.horiz_sync_o (horiz_sync_wm)\r
);\r
\r
vga_linear_fml linear (\r
.clk (clk),\r
.rst (rst),\r
\r
.enable (enable_sequencer),\r
\r
// CSR slave interface for reading\r
.fml_adr_o (csr_gm_adr_o),\r
.fml_dat_i (fml_dat_i),\r
.fml_stb_o (csr_gm_stb_o),\r
\r
.h_count (h_count),\r
.v_count (v_count),\r
.horiz_sync_i (horiz_sync_i),\r
.video_on_h_i (video_on_h_i),\r
.video_on_h_o (video_on_h_gm),\r
\r
.color (color),\r
.horiz_sync_o (horiz_sync_gm)\r
);\r
\r
// Continuous assignments\r
assign video_on_h = video_on_h_p[1];\r
\r
assign fml_adr_o = graphics_alpha ?\r
(shift_reg1 ? csr_gm_adr_o : csr_wm_adr_o) : { 1'b0, csr_tm_adr_o };\r
\r
assign fml_stb_o_tmp = graphics_alpha ?\r
(shift_reg1 ? csr_gm_stb_o : csr_wm_stb_o) : csr_tm_stb_o;\r
assign fml_stb_o = fml_stb_o_tmp & (video_on_h_i | video_on_h) & video_on_v;\r
\r
// Video mode sequencer horiz_sync that will be passed to next stage\r
assign horiz_sync_seq_o = graphics_alpha ?\r
(shift_reg1 ? horiz_sync_gm : horiz_sync_wm) : horiz_sync_tm;\r
\r
// Pass through vert_sync to next stage\r
assign vert_sync_seq_o = vert_sync;\r
\r
// Video mode sequencer video_on_h that will be passed to next stage\r
assign video_on_h_seq_o = graphics_alpha ?\r
(shift_reg1 ? video_on_h_gm : video_on_h_wm) : video_on_h_tm;\r
\r
// Pass through video_on_v to next stage\r
assign video_on_v_seq_o = video_on_v;\r
\r
// Video mode sequencer character that will be passed to next stage\r
assign character_seq_o = graphics_alpha ?\r
(shift_reg1 ? color : { 4'b0, attr_wm }) : { 4'b0, attr_tm };\r
\r
// Video_on pipe used only for video_on_h signal \r
always @(posedge clk)\r
if (rst)\r
begin\r
video_on_h_p <= 2'b0;\r
end\r
else\r
if (enable_sequencer)\r
begin\r
video_on_h_p <= { video_on_h_p[0],\r
graphics_alpha ? (shift_reg1 ? video_on_h_gm : video_on_h_wm)\r
: video_on_h_tm }; \r
end\r
\r
endmodule\r
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module test_kotku;
// Registers and nets
reg clk_50;
wire [9:0] ledr;
wire [7:0] ledg;
reg [7:0] sw;
integer i;
wire [21:0] flash_addr;
wire [ 7:0] flash_data;
wire flash_we_n;
wire flash_oe_n;
wire flash_rst_n;
wire flash_ry;
wire [11:0] sdram_addr;
wire [15:0] sdram_data;
wire [ 1:0] sdram_ba;
wire [ 1:0] sdram_dqm;
wire sdram_ras_n;
wire sdram_cas_n;
wire sdram_ce;
wire sdram_clk;
wire sdram_we_n;
wire sdram_cs_n;
wire [16:0] sram_addr_;
wire [15:0] sram_data_;
wire sram_we_n_;
wire sram_oe_n_;
wire sram_ce_n_;
wire [ 1:0] sram_bw_n_;
// Module instantiations
kotku kotku (
.clk_50_ (clk_50),
.ledr_ (ledr),
.ledg_ (ledg),
.sw_ (sw),
// flash signals
.flash_addr_ (flash_addr),
.flash_data_ (flash_data),
.flash_oe_n_ (flash_oe_n),
// sdram signals
.sdram_addr_ (sdram_addr),
.sdram_data_ (sdram_data),
.sdram_ba_ (sdram_ba),
.sdram_ras_n_ (sdram_ras_n),
.sdram_cas_n_ (sdram_cas_n),
.sdram_ce_ (sdram_ce),
.sdram_clk_ (sdram_clk),
.sdram_we_n_ (sdram_we_n),
.sdram_cs_n_ (sdram_cs_n),
// sram signals
.sram_addr_ (sram_addr_),
.sram_data_ (sram_data_),
.sram_we_n_ (sram_we_n_),
.sram_oe_n_ (sram_oe_n_),
.sram_bw_n_ (sram_bw_n_)
);
s29al032d_00 flash (
.A21 (flash_addr[21]),
.A20 (flash_addr[20]),
.A19 (flash_addr[19]),
.A18 (flash_addr[18]),
.A17 (flash_addr[17]),
.A16 (flash_addr[16]),
.A15 (flash_addr[15]),
.A14 (flash_addr[14]),
.A13 (flash_addr[13]),
.A12 (flash_addr[12]),
.A11 (flash_addr[11]),
.A10 (flash_addr[10]),
.A9 (flash_addr[ 9]),
.A8 (flash_addr[ 8]),
.A7 (flash_addr[ 7]),
.A6 (flash_addr[ 6]),
.A5 (flash_addr[ 5]),
.A4 (flash_addr[ 4]),
.A3 (flash_addr[ 3]),
.A2 (flash_addr[ 2]),
.A1 (flash_addr[ 1]),
.A0 (flash_addr[ 0]),
.DQ7 (flash_data[7]),
.DQ6 (flash_data[6]),
.DQ5 (flash_data[5]),
.DQ4 (flash_data[4]),
.DQ3 (flash_data[3]),
.DQ2 (flash_data[2]),
.DQ1 (flash_data[1]),
.DQ0 (flash_data[0]),
.CENeg (1\'b0),
.OENeg (flash_oe_n),
.WENeg (1\'b1),
.RESETNeg (1\'b1),
.ACC (1\'b1),
.RY (flash_ry)
);
mt48lc16m16a2 sdram (
.Dq (sdram_data),
.Addr (sdram_addr),
.Ba (sdram_ba),
.Clk (sdram_clk),
.Cke (sdram_ce),
.Cs_n (sdram_cs_n),
.Ras_n (sdram_ras_n),
.Cas_n (sdram_cas_n),
.We_n (sdram_we_n),
.Dqm (2\'b00)
);
is61lv25616 sram (
.A ({1\'b0,sram_addr_}),
.IO (sram_data_),
.CE_ (1\'b0),
.OE_ (sram_oe_n_),
.WE_ (sram_we_n_),
.LB_ (sram_bw_n_[0]),
.UB_ (sram_bw_n_[1])
);
// Behaviour
// Clock generation
always #10 clk_50 <= !clk_50;
initial
begin
$readmemh("../../../cores/flash/bios.dat",flash.Mem);
$readmemb("../../../cores/zet/rtl/micro_rom.dat",
kotku.zet.core.micro_data.micro_rom.rom);
$readmemh("../../../cores/vga/rtl/char_rom.dat",
kotku.vga.lcd.text_mode.char_rom.rom);
// $readmemh("../../../cores/ps2/rtl/xt_codes.dat",
// kotku.ps2.keyb.keyb_xtcodes.rom);
$readmemh("../../../cores/flash/bootrom.dat",
kotku.bootrom.rom);
clk_50 <= 1\'b0;
sw <= 8\'h1;
#300 sw <= 8\'h0;
end
endmodule
|
/*
* This module accepts incoming data from PS2 interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse_datain (
input clk,
input reset,
input wait_for_incoming_data,
input start_receiving_data,
input ps2_clk_posedge,
input ps2_clk_negedge,
input ps2_data,
output reg [7:0] received_data,
output reg received_data_en // If 1, new data has been received
);
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if (reset == 1'b1) s_ps2_receiver <= PS2_STATE_0_IDLE;
else s_ps2_receiver <= ns_ps2_receiver;
end
always @(*) begin // Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if((wait_for_incoming_data == 1'b1) && (received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) && (received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if (reset == 1'b1) data_count <= 3'h0;
else if((s_ps2_receiver == PS2_STATE_2_DATA_IN) && (ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if(s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk) begin
if(reset == 1'b1) data_shift_reg <= 8'h00;
else if((s_ps2_receiver == PS2_STATE_2_DATA_IN) && (ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk) begin
if(reset == 1'b1) received_data <= 8'h00;
else if(s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk) begin
if(reset == 1'b1) received_data_en <= 1'b0;
else if((s_ps2_receiver == PS2_STATE_4_STOP_IN) && (ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
endmodule
|
/*
* Microcode instruction generator for Zet
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_micro_data (
input [`MICRO_ADDR_WIDTH-1:0] n_micro,
input [15:0] off_i,
input [15:0] imm_i,
input [ 3:0] src,
input [ 3:0] dst,
input [ 3:0] base,
input [ 3:0] index,
input [ 1:0] seg,
input [ 2:0] fdec,
output div,
output end_seq,
output [`IR_SIZE-1:0] ir,
output [15:0] off_o,
output [15:0] imm_o
);
// Net declarations
wire [`MICRO_DATA_WIDTH-1:0] micro_o;
wire [ 6:0] ir1;
wire [ 1:0] ir0;
wire var_s, var_off;
wire [1:0] var_a, var_b, var_c, var_d;
wire [2:0] var_imm;
wire [3:0] addr_a, addr_b, addr_c, addr_d;
wire [3:0] micro_a, micro_b, micro_c, micro_d;
wire [1:0] addr_s, micro_s;
wire [2:0] t;
wire [2:0] f;
wire [2:0] f_rom;
wire wr_flag;
wire wr_mem;
wire wr_rom;
wire wr_d;
// Module instantiations
zet_micro_rom micro_rom (n_micro, micro_o);
// Assignments
assign micro_s = micro_o[1:0];
assign micro_a = micro_o[5:2];
assign micro_b = micro_o[9:6];
assign micro_c = micro_o[13:10];
assign micro_d = micro_o[17:14];
assign wr_flag = micro_o[18];
assign wr_mem = micro_o[19];
assign wr_rom = micro_o[20];
assign ir0 = micro_o[22:21];
assign t = micro_o[25:23];
assign f_rom = micro_o[28:26];
assign ir1 = micro_o[35:29];
assign var_s = micro_o[36];
assign var_a = micro_o[38:37];
assign var_b = micro_o[40:39];
assign var_c = micro_o[42:41];
assign var_d = micro_o[44:43];
assign var_off = micro_o[45];
assign var_imm = micro_o[48:46];
assign end_seq = micro_o[49];
assign imm_o = var_imm == 3\'d0 ? (16\'h0000)
: (var_imm == 3\'d1 ? (16\'h0002)
: (var_imm == 3\'d2 ? (16\'h0004)
: (var_imm == 3\'d3 ? off_i
: (var_imm == 3\'d4 ? imm_i
: (var_imm == 3\'d5 ? 16\'hffff
: (var_imm == 3\'d6 ? 16\'b11 : 16\'d1))))));
assign off_o = var_off ? off_i : 16\'h0000;
assign addr_a = var_a == 2\'d0 ? micro_a
: (var_a == 2\'d1 ? base
: (var_a == 2\'d2 ? dst : src ));
assign addr_b = var_b == 2\'d0 ? micro_b
: (var_b == 2\'d1 ? index : src);
assign addr_c = var_c == 2\'d0 ? micro_c
: (var_c == 2\'d1 ? dst : src);
assign addr_d = var_d == 2\'d0 ? micro_d
: (var_d == 2\'d1 ? dst : src);
assign addr_s = var_s ? seg : micro_s;
assign div = (t==3\'d3 && (f_rom[2]|f_rom[1]) && !wr_rom);
assign f = (t==3\'d6 && wr_flag || t==3\'d5 && wr_rom) ? fdec : f_rom;
assign wr_d = (t==3\'d5 && f==3\'d7) ? 1\'b0 : wr_rom; /* CMP doesn\'t write */
assign ir = { ir1, f, t, ir0, wr_d, wr_mem, wr_flag, addr_d,
addr_c, addr_b, addr_a, addr_s };
endmodule
|
/*
* Integer multiply/divide module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_muldiv (
input [31:0] x, // 16 MSb for division
input [15:0] y,
output [31:0] o,
input [ 2:0] f,
input word_op,
output cfo,
output ofo,
input clk,
output exc
);
// Net declarations
wire as, bs, cfs, cfu;
wire [16:0] a, b;
wire [33:0] p;
wire div0, over, ovf, mint;
wire [33:0] zi;
wire [16:0] di;
wire [17:0] q;
wire [17:0] s;
// Module instantiations
zet_signmul17 signmul17 (
.clk (clk),
.a (a),
.b (b),
.p (p)
);
zet_div_su #(
.z_width(34)
) div_su (
.clk (clk),
.ena (1'b1),
.z (zi),
.d (di),
.q (q),
.s (s),
.ovf (ovf)
);
// Sign ext. for imul
assign as = f[0] & (word_op ? x[15] : x[7]);
assign bs = f[0] & (word_op ? y[15] : y[7]);
assign a = word_op ? { as, x[15:0] }
: { {9{as}}, x[7:0] };
assign b = word_op ? { bs, y } : { {9{bs}}, y[7:0] };
assign zi = f[2] ? { 26'h0, x[7:0] }
: (word_op ? (f[0] ? { {2{x[31]}}, x }
: { 2'b0, x })
: (f[0] ? { {18{x[15]}}, x[15:0] }
: { 18'b0, x[15:0] }));
assign di = word_op ? (f[0] ? { y[15], y } : { 1'b0, y })
: (f[0] ? { {9{y[7]}}, y[7:0] }
: { 9'h000, y[7:0] });
assign o = f[2] ? { 16'h0, q[7:0], s[7:0] }
: (f[1] ? ( word_op ? {s[15:0], q[15:0]}
: {16'h0, s[7:0], q[7:0]})
: p[31:0]);
assign ofo = f[1] ? 1'b0 : cfo;
assign cfo = f[1] ? 1'b0 : !(f[0] ? cfs : cfu);
assign cfu = word_op ? (o[31:16] == 16'h0)
: (o[15:8] == 8'h0);
assign cfs = word_op ? (o[31:16] == {16{o[15]}})
: (o[15:8] == {8{o[7]}});
// Exceptions
assign over = word_op ? (f[0] ? (q[17:16]!={2{q[15]}})
: (q[17:16]!=2'b0) )
: (f[0] ? (q[17:8]!={10{q[7]}})
: (q[17:8]!=10'h000));
assign mint = f[0] & (word_op ? (x==32'h80000000)
: (x==16'h8000));
assign div0 = ~|di;
assign exc = div0 | (!f[2] & (ovf | over | mint));
endmodule
|
/*
* PS2 Mouse without FIFO buffer
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse_nofifo (
input clk,
input reset,
input [7:0] writedata, // data to send
input write, // signal to send it
input inhibit,
output [7:0] readdata, // data read
output irq, // signal data has arrived
output command_was_sent,
output error_sending_command,
output buffer_overrun_error,
inout ps2_clk,
inout ps2_dat
);
// Unused outputs
wire start_receiving_data;
wire wait_for_incoming_data;
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse mouse (
.clk (clk),
.reset (reset),
.the_command (writedata),
.send_command (write),
.received_data (readdata),
.received_data_en (irq),
.inhibit (inhibit),
.command_was_sent (command_was_sent),
.error_communication_timed_out (error_sending_command),
.start_receiving_data (start_receiving_data),
.wait_for_incoming_data (wait_for_incoming_data),
.ps2_clk (ps2_clk),
.ps2_dat (ps2_dat)
);
// Continous assignments
assign buffer_overrun_error = error_sending_command;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Simple FML interface for HPDMC */
module hpdmc_busif #(
\tparameter sdram_depth = 23
) (
\tinput sys_clk,
\tinput sdram_rst,
\t
\tinput [sdram_depth-1:0] fml_adr,
\tinput fml_stb,
\tinput fml_we,
\toutput fml_ack,
\t
\toutput mgmt_stb,
\toutput mgmt_we,
\toutput [sdram_depth-1-1:0] mgmt_address, /* in 16-bit words */
\tinput mgmt_ack,
\t
\tinput data_ack
);
reg mgmt_stb_en;
assign mgmt_stb = fml_stb & mgmt_stb_en;
assign mgmt_we = fml_we;
assign mgmt_address = fml_adr[sdram_depth-1:1];
assign fml_ack = data_ack;
always @(posedge sys_clk) begin
\tif(sdram_rst)
\t\tmgmt_stb_en = 1'b1;
\telse begin
\t\tif(mgmt_ack)
\t\t\tmgmt_stb_en = 1'b0;
\t\tif(data_ack)
\t\t\tmgmt_stb_en = 1'b1;
\tend
end
endmodule
|
/*
* Wishbone register slice
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module wb_regslice (
input clk,
input rst,
// Wishbone slave interface
input [19:1] wbs_adr_i,
input [15:0] wbs_dat_i,
output reg [15:0] wbs_dat_o,
input [ 1:0] wbs_sel_i,
input wbs_tga_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
output reg wbs_ack_o,
// Wishbone master interface
output reg [19:1] wbm_adr_o,
output reg [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output reg [ 1:0] wbm_sel_o,
output reg wbm_tga_o,
output reg wbm_stb_o,
output reg wbm_cyc_o,
output reg wbm_we_o,
input wbm_ack_i
);
// Net declarations
wire ack_st;
// Combinational logic
assign ack_st = wbm_ack_i | wbs_ack_o;
// Sequential logic
always @(posedge clk)
wbm_stb_o <= rst ? 1'b0
: (ack_st ? 1'b0 : wbs_stb_i);
always @(posedge clk)
begin
wbm_adr_o <= wbs_adr_i;
wbm_dat_o <= wbs_dat_i;
wbm_sel_o <= wbs_sel_i;
wbm_tga_o <= wbs_tga_i;
wbm_cyc_o <= wbs_cyc_i;
wbm_we_o <= wbs_we_i;
end
always @(posedge clk)
begin
wbs_dat_o <= wbm_dat_i;
wbs_ack_o <= wbm_ack_i;
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring unsigned divider ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS\'\' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_uu.v,v 1.3 2003/09/17 13:08:53 rherveille Exp $
//
// $Date: 2003/09/17 13:08:53 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: div_uu.v,v $
// Revision 1.3 2003/09/17 13:08:53 rherveille
// Fixed a bug in the remainder output. Changed a hard value into the required parameter.
// Fixed a bug in the testbench.
//
// Revision 1.2 2002/10/31 13:54:58 rherveille
// Fixed a bug in the remainder output of div_su.v
//
// Revision 1.1.1.1 2002/10/29 20:29:10 rherveille
//
//
//
//synopsys translate_off
`timescale 1ns/10ps
//synopsys translate_on
module zet_div_uu(clk, ena, z, d, q, s, div0, ovf);
\t//
\t// parameters
\t//
\tparameter z_width = 16;
\tparameter d_width = z_width /2;
\t
\t//
\t// inputs & outputs
\t//
\tinput clk; // system clock
\tinput ena; // clock enable
\tinput [z_width -1:0] z; // divident
\tinput [d_width -1:0] d; // divisor
\toutput [d_width -1:0] q; // quotient
\toutput [d_width -1:0] s; // remainder
\toutput div0;
\toutput ovf;
\treg [d_width-1:0] q;
\treg [d_width-1:0] s;
\treg div0;
\treg ovf;
\t//\t
\t// functions
\t//
\tfunction [z_width:0] gen_s;
\t\tinput [z_width:0] si;
\t\tinput [z_width:0] di;
\tbegin
\t if(si[z_width])
\t gen_s = {si[z_width-1:0], 1\'b0} + di;
\t else
\t gen_s = {si[z_width-1:0], 1\'b0} - di;
\tend
\tendfunction
\tfunction [d_width-1:0] gen_q;
\t\tinput [d_width-1:0] qi;
\t\tinput [z_width:0] si;
\tbegin
\t gen_q = {qi[d_width-2:0], ~si[z_width]};
\tend
\tendfunction
\tfunction [d_width-1:0] assign_s;
\t\tinput [z_width:0] si;
\t\tinput [z_width:0] di;
\t\treg [z_width:0] tmp;
\tbegin
\t if(si[z_width])
\t tmp = si + di;
\t else
\t tmp = si;
\t assign_s = tmp[z_width-1:z_width-d_width];
\tend
\tendfunction
\t//
\t// variables
\t//
\treg [d_width-1:0] q_pipe [d_width-1:0];
\treg [z_width:0] s_pipe [d_width:0];
\treg [z_width:0] d_pipe [d_width:0];
\treg [d_width:0] div0_pipe, ovf_pipe;
\t//
\t// perform parameter checks
\t//
\t// synopsys translate_off
\tinitial
\tbegin
\t if(d_width !== z_width / 2)
\t $display("div.v parameter error (d_width != z_width/2).");
\tend
\t// synopsys translate_on
\tinteger n0, n1, n2, n3;
\t// generate divisor (d) pipe
\talways @(d)
\t d_pipe[0] <= {1\'b0, d, {(z_width-d_width){1\'b0}} };
\talways @(posedge clk)
\t if(ena)
\t for(n0=1; n0 <= d_width; n0=n0+1)
\t d_pipe[n0] <= d_pipe[n0-1];
\t// generate internal remainder pipe
\talways @(z)
\t s_pipe[0] <= z;
\talways @(posedge clk)
\t if(ena)
\t for(n1=1; n1 <= d_width; n1=n1+1)
\t s_pipe[n1] <= gen_s(s_pipe[n1-1], d_pipe[n1-1]);
\t// generate quotient pipe
\talways @(posedge clk)
\t q_pipe[0] <= 0;
\talways @(posedge clk)
\t if(ena)
\t for(n2=1; n2 < d_width; n2=n2+1)
\t q_pipe[n2] <= gen_q(q_pipe[n2-1], s_pipe[n2]);
\t// flags (divide_by_zero, overflow)
\talways @(z or d)
\tbegin
\t ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
\t div0_pipe[0] <= ~|d;
\tend
\talways @(posedge clk)
\t if(ena)
\t for(n3=1; n3 <= d_width; n3=n3+1)
\t begin
\t ovf_pipe[n3] <= ovf_pipe[n3-1];
\t div0_pipe[n3] <= div0_pipe[n3-1];
\t end
\t// assign outputs
\talways @(posedge clk)
\t if(ena)
\t ovf <= ovf_pipe[d_width];
\talways @(posedge clk)
\t if(ena)
\t div0 <= div0_pipe[d_width];
\talways @(posedge clk)
\t if(ena)
\t q <= gen_q(q_pipe[d_width-1], s_pipe[d_width]);
\talways @(posedge clk)
\t if(ena)
\t s <= assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_csrbrg();
reg sys_clk;
reg sys_rst;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [13:0] csr_a;
wire csr_we;
wire [31:0] csr_do;
reg [31:0] csr_di;
/* 100MHz system clock */
initial sys_clk = 1\'b0;
always #5 sys_clk = ~sys_clk;
csrbrg dut(
\t.sys_clk(sys_clk),
\t.sys_rst(sys_rst),
\t
\t.wb_adr_i(wb_adr_i),
\t.wb_dat_i(wb_dat_i),
\t.wb_dat_o(wb_dat_o),
\t.wb_cyc_i(wb_cyc_i),
\t.wb_stb_i(wb_stb_i),
\t.wb_we_i(wb_we_i),
\t.wb_ack_o(wb_ack_o),
\t
\t/* CSR bus master */
\t.csr_a(csr_a),
\t.csr_we(csr_we),
\t.csr_do(csr_do),
\t.csr_di(csr_di)
);
task waitclock;
begin
\t@(posedge sys_clk);
\t#1;
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
\twb_adr_i = address;
\twb_dat_i = data;
\twb_cyc_i = 1\'b1;
\twb_stb_i = 1\'b1;
\twb_we_i = 1\'b1;
\ti = 0;
\twhile(~wb_ack_o) begin
\t\ti = i+1;
\t\twaitclock;
\tend
\twaitclock;
\t$display("WB Write: %x=%x acked in %d clocks", address, data, i);
\twb_cyc_i = 1\'b0;
\twb_stb_i = 1\'b0;
\twb_we_i = 1\'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
\twb_adr_i = address;
\twb_cyc_i = 1\'b1;
\twb_stb_i = 1\'b1;
\twb_we_i = 1\'b0;
\ti = 0;
\twhile(~wb_ack_o) begin
\t\ti = i+1;
\t\twaitclock;
\tend
\t$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
\twaitclock;
\twb_cyc_i = 1\'b0;
\twb_stb_i = 1\'b0;
\twb_we_i = 1\'b0;
end
endtask
/* Simulate CSR slave */
reg [31:0] csr1;
reg [31:0] csr2;
wire csr_selected = (csr_a[13:10] == 4\'ha);
always @(posedge sys_clk) begin
\tif(csr_selected) begin
\t\tif(csr_we) begin
\t\t\t$display("Writing %x to CSR %x", csr_do, csr_a[0]);
\t\t\tcase(csr_a[0])
\t\t\t\t1\'b0: csr1 <= csr_do;
\t\t\t\t1\'b1: csr2 <= csr_do;
\t\t\tendcase
\t\tend
\t\tcase(csr_a[0])
\t\t\t1\'b0: csr_di <= csr1;
\t\t\t1\'b1: csr_di <= csr2;
\t\tendcase
\tend else
\t\t/* we must set data to 0 to be able to use a distributed OR topology
\t\t * in the slaves->master datapath.
\t\t */
\t\tcsr_di <= 32\'d0;
end
always begin
\t/* Reset / Initialize our logic */
\tsys_rst = 1\'b1;
\t
\twb_adr_i = 32\'d0;
\twb_dat_i = 32\'d0;
\twb_cyc_i = 1\'b0;
\twb_stb_i = 1\'b0;
\twb_we_i = 1\'b0;
\t
\twaitclock;
\t
\tsys_rst = 1\'b0;
\t
\twaitclock;
\t
\t/* Try some transfers */
\twbwrite(32\'h0000a000, 32\'hcafebabe);
\twbwrite(32\'h0000a004, 32\'habadface);
\twbread(32\'h0000a000);
\twbread(32\'h0000a004);
\t
\t$finish;
end
endmodule
|
/*
* 8254 timer simplified for Zet SoC
* Copyright (c) 2010 YS <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
/*
* This module uses:
* - Wishbone interface
* - Modes (binary) 2 and 3 only
* - Common clock for all 3 Timers (tclk_i)
* - Gate input for Timer2 only (gate2_i)
* Assumptions:
* 1. tclk_i is asynchronous simple wire (1.193182 MHz by default)
* 2. gate2_i is synchronous (comes from Wishbone controlled register)
* 3. Wishbone clock wb_clk_i is running always and it has much higher
* frequency than tclk_i
*/
`define WB_UNBUFFERED_8254
module timer
(
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input wb_adr_i,
input [1:0] wb_sel_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
input wb_stb_i,
input wb_cyc_i,
input wb_we_i,
output wb_ack_o,
output reg wb_tgc_o, // intr
// CLK
input tclk_i, // 1.193182 MHz = (14.31818/12) MHz
// SPEAKER
input gate2_i,
output out2_o
);
`ifdef WB_UNBUFFERED_8254
wire [15:0] data_ib;
wire wr_cyc1;
wire rd_cyc1;
wire [1:0] datasel;
`else
reg [15:0] data_ib;
reg wr_cyc1;
reg rd_cyc1, rd_cyc2;
reg [1:0] datasel;
`endif
wire intr, refresh;
reg intr1;
//reg [7:0] dat_o;
wire wrc, wrd0, wrd1, wrd2, rdd0, rdd1, rdd2;
wire [7:0] data0;
wire [7:0] data1;
wire [7:0] data2;
// Making 1 clock pulse on wb_tgc_o from intr
// unnecessary for real 8259A -> subj to remove later
always @(posedge wb_clk_i)
begin
intr1 <= wb_rst_i ? 1'b0 : intr;
wb_tgc_o <= wb_rst_i ? 1'b0 : (!intr1 & intr);
end
// 8-bit interface via wb_dat low byte (2-bit [2:1]??? wb_addr_i , no wb_sel_i)
/*
assign wb_ack_o = wb_stb_i & wb_cyc_i;
assign wrc = wb_ack_o & wb_we_i & (wb_adr_i == 2'b11);
assign wrd0 = wb_ack_o & wb_we_i & (wb_adr_i == 2'b00);
assign wrd1 = wb_ack_o & wb_we_i & (wb_adr_i == 2'b01);
assign wrd2 = wb_ack_o & wb_we_i & (wb_adr_i == 2'b10);
assign rdd0 = wb_ack_o & ~wb_we_i & (wb_adr_i == 2'b00);
assign rdd1 = wb_ack_o & ~wb_we_i & (wb_adr_i == 2'b01);
assign rdd2 = wb_ack_o & ~wb_we_i & (wb_adr_i == 2'b10);
always @(wb_adr_i or data0 or data1 or data2)
case (wb_adr_i)
2'b00: wb_dat_o = { 8'h0, data0 };
2'b01: wb_dat_o = { 8'h0, data1 };
2'b10: wb_dat_o = { 8'h0, data2 };
endcase
timer_counter cnt0(0, 6'h36, 16'hFFFF, wb_clk_i, wb_rst_i, wrc, wrd0, rdd0, wb_dat_i, data0, tclk_i, 1'b1, intr); // 16-bit 55 ms Mode 3
timer_counter cnt1(1, 6'h14, 16'h0012, wb_clk_i, wb_rst_i, wrc, wrd1, rdd1, wb_dat_i, data1, tclk_i, 1'b1, refresh); // 8-bit 15 us Mode 2
timer_counter cnt2(2, 6'h36, 16'h04A9, wb_clk_i, wb_rst_i, wrc, wrd2, rdd2, wb_dat_i, data2, tclk_i, gate2_i, out2_o); // 16-bit 1 ms Mode 3
*/
// 16-bit interface via wb_dat both bytes (1-bit wb_addr_i, 2-bit [1:0] wb_sel_i)
// assumes opposite wb_sel_i only: 2'b10 or 2'b01
reg [7:0] data_i;
reg [15:0] data_ob;
always @(datasel or data0 or data1 or data2)
case (datasel)
2'b00: data_ob = { 8'h0, data0 };
2'b01: data_ob = { data1, 8'h0 };
2'b10: data_ob = { 8'h0, data2 };
2'b11: data_ob = { 8'h0, 8'h0 }; // not checked yet!
endcase
always @(datasel or data_ib)
case (datasel)
2'b00: data_i = data_ib[7:0];
2'b01: data_i = data_ib[15:8];
2'b10: data_i = data_ib[7:0];
2'b11: data_i = data_ib[15:8];
endcase
assign wrc = wr_cyc1 & (datasel == 2'b11);
assign wrd0 = wr_cyc1 & (datasel == 2'b00);
assign wrd1 = wr_cyc1 & (datasel == 2'b01);
assign wrd2 = wr_cyc1 & (datasel == 2'b10);
assign rdd0 = rd_cyc1 & (datasel == 2'b00);
assign rdd1 = rd_cyc1 & (datasel == 2'b01);
assign rdd2 = rd_cyc1 & (datasel == 2'b10);
`ifdef WB_UNBUFFERED_8254
// 1 clock write, 1 clock read
assign wb_ack_o = wb_stb_i & wb_cyc_i;
assign wr_cyc1 = wb_ack_o & wb_we_i;
assign rd_cyc1 = wb_ack_o & ~wb_we_i;
assign datasel = {wb_adr_i,wb_sel_i[1]};
//assign wb_dat_o = data_ob;
always @(data_ob)
wb_dat_o = data_ob;
assign data_ib = wb_dat_i;
`else
// 2 clocks write, 3 clocks read
assign wb_ack_o = wr_cyc1 | rd_cyc2;
always @(posedge wb_clk_i)
begin
wr_cyc1 <= (wr_cyc1) ? 1'b0 : wb_stb_i & wb_cyc_i & wb_we_i; // single clock write pulse
rd_cyc1 <= (rd_cyc1 | rd_cyc2) ? 1'b0 : wb_stb_i & wb_cyc_i & ~wb_we_i; // single clock read pulse
rd_cyc2 <= rd_cyc1; // delayed single clock read pulse
datasel <= {wb_adr_i,wb_sel_i[1]};
wb_dat_o <= data_ob;
data_ib <= wb_dat_i;
end
`endif //def WB_UNBUFFERED_8254
// Module instantiations
timer_counter cnt0 (
.cntnum (2'd0),
.cw0 (6'h36), // 16-bit Mode 3
.cr0 (16'hFFFF), // 55 ms
.clkrw (wb_clk_i),
.rst (wb_rst_i),
.wrc (wrc),
.wrd (wrd0),
.rdd (rdd0),
.data_i (data_i),
.data_o (data0),
.clkt (tclk_i),
.gate (1'b1),
.out (intr)
);
timer_counter cnt1 (
.cntnum (2'd1),
.cw0 (6'h14), // 8-bit Mode 2
.cr0 (16'h0012), // 15 us
.clkrw (wb_clk_i),
.rst (wb_rst_i),
.wrc (wrc),
.wrd (wrd1),
.rdd (rdd1),
.data_i (data_i),
.data_o (data1),
.clkt (tclk_i),
.gate (1'b1),
.out (refresh)
);
timer_counter cnt2 (
.cntnum (2'd2),
.cw0 (6'h36), // 16-bit Mode 3
.cr0 (16'h04A9), // 1 ms
.clkrw (wb_clk_i),
.rst (wb_rst_i),
.wrc (wrc),
.wrd (wrd2),
.rdd (rdd2),
.data_i (data_i),
.data_o (data2),
.clkt (tclk_i),
.gate (gate2_i),
.out (out2_o)
);
endmodule
|
/*
* DAC register file for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_dac_regs (
input clk,
// VGA read interface
input [7:0] index,
output reg [3:0] red,
output reg [3:0] green,
output reg [3:0] blue,
// CPU interface
input write,
// CPU read interface
input [1:0] read_data_cycle,
input [7:0] read_data_register,
output reg [3:0] read_data,
// CPU write interface
input [1:0] write_data_cycle,
input [7:0] write_data_register,
input [3:0] write_data
);
// Registers, nets and parameters
reg [3:0] red_dac [0:255];
reg [3:0] green_dac [0:255];
reg [3:0] blue_dac [0:255];
// Behaviour
// VGA read interface
always @(posedge clk)
begin
red <= red_dac[index];
green <= green_dac[index];
blue <= blue_dac[index];
end
// CPU read interface
always @(posedge clk)
case (read_data_cycle)
2'b00: read_data <= red_dac[read_data_register];
2'b01: read_data <= green_dac[read_data_register];
2'b10: read_data <= blue_dac[read_data_register];
default: read_data <= 4'h0;
endcase
// CPU write interface
always @(posedge clk)
if (write)
case (write_data_cycle)
2'b00: red_dac[write_data_register] <= write_data;
2'b01: green_dac[write_data_register] <= write_data;
2'b10: blue_dac[write_data_register] <= write_data;
endcase
endmodule
|
/*
* Wishbone asynchronous bridge with slave register slice
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module wb_abrg_reg (
input sys_rst,
// Wishbone slave interface
input wbs_clk_i,
input [19:1] wbs_adr_i,
input [15:0] wbs_dat_i,
output [15:0] wbs_dat_o,
input [ 1:0] wbs_sel_i,
input wbs_tga_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
output wbs_ack_o,
// Wishbone master interface
input wbm_clk_i,
output reg [19:1] wbm_adr_o,
output reg [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output reg [ 1:0] wbm_sel_o,
output reg wbm_tga_o,
output wbm_stb_o,
output wbm_cyc_o,
output reg wbm_we_o,
input wbm_ack_i
);
// Registers and nets
wire wbs_stb;
wire init_tr;
reg wbm_stb;
reg [2:0] sync_stb;
reg [2:0] sync_ack;
reg ft_stb;
reg ft_ack;
reg stb_r;
reg ack_r;
reg [19:1] wbm_adr_o_r;
reg [15:0] wbm_dat_o_r;
reg [ 1:0] wbm_sel_o_r;
reg wbs_tga_i_r;
reg wbm_tga_o_r;
reg wbs_we_i_r;
reg wbm_we_o_r;
reg [15:0] wbs_dat_o_r;
reg [15:0] wbm_dat_i_r;
wire [19:1] wbs_adr_i_reg;
wire [15:0] wbs_dat_i_reg;
reg [15:0] wbs_dat_o_reg;
wire [ 1:0] wbs_sel_i_reg;
wire wbs_tga_i_reg;
wire wbs_stb_i_reg;
wire wbs_cyc_i_reg;
wire wbs_we_i_reg;
wire wbs_ack_o_reg;
// Instances
wb_regslice wb_slave_regslice (
.clk (wbs_clk_i),
.rst (sys_rst),
// Wishbone slave interface
.wbs_adr_i (wbs_adr_i),
.wbs_dat_i (wbs_dat_i),
.wbs_dat_o (wbs_dat_o),
.wbs_sel_i (wbs_sel_i),
.wbs_tga_i (wbs_tga_i),
.wbs_stb_i (wbs_stb_i),
.wbs_cyc_i (wbs_cyc_i),
.wbs_we_i (wbs_we_i),
.wbs_ack_o (wbs_ack_o),
// Wishbone master interface
.wbm_adr_o (wbs_adr_i_reg),
.wbm_dat_o (wbs_dat_i_reg),
.wbm_dat_i (wbs_dat_o_reg),
.wbm_sel_o (wbs_sel_i_reg),
.wbm_tga_o (wbs_tga_i_reg),
.wbm_stb_o (wbs_stb_i_reg),
.wbm_cyc_o (wbs_cyc_i_reg),
.wbm_we_o (wbs_we_i_reg),
.wbm_ack_i (wbs_ack_o_reg)
);
// Continous assignments
assign wbs_stb = wbs_stb_i_reg & wbs_cyc_i_reg;
// recreate the flag from the level change
assign wbs_ack_o_reg = (sync_ack[2] ^ sync_ack[1]);
assign wbm_stb_o = wbm_stb;
assign wbm_cyc_o = wbm_stb;
/*
* A new wishbone transaction is issued:
* . by changing stb from 0 to 1
* . by continue asserting stb after ack is received
*/
assign init_tr = ~stb_r & wbs_stb | ack_r & ~wbs_ack_o_reg & wbs_stb;
// Behaviour
// wbm_stb
always @(posedge wbm_clk_i)
wbm_stb <= sys_rst ? 1'b0
: (wbm_stb ? ~wbm_ack_i : sync_stb[2] ^ sync_stb[1]);
// old stb and ack state
always @(posedge wbs_clk_i) stb_r <= wbs_stb;
always @(posedge wbs_clk_i) ack_r <= wbs_ack_o_reg;
always @(posedge wbs_clk_i)
ft_stb <= sys_rst ? 1'b0 : (init_tr ? ~ft_stb : ft_stb);
// synchronize the last level change
always @(posedge wbm_clk_i)
sync_stb <= sys_rst ? 3'h0 : {sync_stb[1:0], ft_stb};
// this changes level when a flag is seen
always @(posedge wbm_clk_i)
ft_ack <= sys_rst ? 1'b0 : (wbm_ack_i ? ~ft_ack : ft_ack);
// which can then be synched to wbs_clk_i
always @(posedge wbs_clk_i)
sync_ack <= sys_rst ? 3'h0 : {sync_ack[1:0], ft_ack};
// rest of the wishbone signals
always @(posedge wbm_clk_i)
{wbm_adr_o, wbm_adr_o_r} <= {wbm_adr_o_r, wbs_adr_i_reg};
always @(posedge wbm_clk_i)
{wbm_dat_o, wbm_dat_o_r} <= {wbm_dat_o_r, wbs_dat_i_reg};
always @(posedge wbm_clk_i)
{wbm_sel_o, wbm_sel_o_r} <= {wbm_sel_o_r, wbs_sel_i_reg};
always @(posedge wbs_clk_i) wbs_we_i_r <= wbs_we_i_reg;
always @(posedge wbm_clk_i)
{wbm_we_o, wbm_we_o_r} <= {wbm_we_o_r, wbs_we_i_r};
always @(posedge wbs_clk_i) wbs_tga_i_r <= wbs_tga_i_reg;
always @(posedge wbm_clk_i)
{wbm_tga_o, wbm_tga_o_r} <= {wbm_tga_o_r, wbs_tga_i_r};
/*
* Register input coming from the slave as that can change
* after the ack is received
*/
always @(posedge wbm_clk_i)
wbm_dat_i_r <= wbm_ack_i ? wbm_dat_i : wbm_dat_i_r;
always @(posedge wbs_clk_i)
{wbs_dat_o_reg, wbs_dat_o_r} <= {wbs_dat_o_r, wbm_dat_i_r};
endmodule
|
/*\r
* Palette register file for VGA\r
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
module vga_palette_regs_fml (\r
input clk,\r
\r
// VGA read interface\r
input [3:0] attr,\r
output reg [7:0] index,\r
\r
// CPU interface\r
input [3:0] address,\r
input write,\r
output reg [7:0] read_data,\r
input [7:0] write_data\r
);\r
\r
// Registers\r
reg [7:0] palette [0:15];\r
\r
// Behaviour\r
// VGA read interface\r
always @(posedge clk) index <= palette[attr];\r
\r
// CPU read interface\r
always @(posedge clk) read_data <= palette[address];\r
\r
// CPU write interface\r
always @(posedge clk)\r
if (write) palette[address] <= write_data;\r
\r
endmodule\r
|
/*
* Wishbone Flash RAM core for Altera DE2 board (90ns registered)
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module flash8_r2 (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
input wb_we_i,
input wb_adr_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
// Pad signals
output reg [22:0] flash_addr_,
input [ 7:0] flash_data_,
output flash_we_n_,
output reg flash_oe_n_,
output reg flash_ce_n_,
output flash_rst_n_
);
// Registers and nets
wire op;
wire wr_command;
wire flash_addr0;
reg [21:0] address;
wire word;
wire op_word;
reg [ 3:0] st;
reg [ 7:0] lb;
// Combinatorial logic
assign op = wb_stb_i & wb_cyc_i;
assign word = wb_sel_i==2'b11;
assign op_word = op & word & !wb_we_i;
assign flash_rst_n_ = 1'b1;
assign flash_we_n_ = 1'b1;
assign flash_addr0 = (wb_sel_i==2'b10) | (word & |st[2:1]);
assign wr_command = op & wb_we_i; // Wishbone write access Signal
// Behaviour
// flash_addr_
always @(posedge wb_clk_i)
flash_addr_ <= { address, flash_addr0 };
// flash_oe_n_
always @(posedge wb_clk_i)
flash_oe_n_ <= !(op & !wb_we_i);
// flash_ce_n_
always @(posedge wb_clk_i)
flash_ce_n_ <= !(op & !wb_we_i);
// wb_dat_o
always @(posedge wb_clk_i)
wb_dat_o <= wb_rst_i ? 16'h0
: (st[2] ? (wb_sel_i[1] ? { flash_data_, lb }
: { 8'h0, flash_data_ })
: wb_dat_o);
// wb_ack_o
always @(posedge wb_clk_i)
wb_ack_o <= wb_rst_i ? 1'b0
: (wb_ack_o ? 1'b0 : (op & (wb_we_i ? 1'b1 : st[2])));
// st - state
always @(posedge wb_clk_i)
st <= wb_rst_i ? 4'h0
: (op & st==4'h0 ? (word ? 4'b0001 : 4'b0100)
: { st[2:0], 1'b0 });
// lb - low byte
always @(posedge wb_clk_i)
lb <= wb_rst_i ? 8'h0 : (op_word & st[1] ? flash_data_ : 8'h0);
// --------------------------------------------------------------------
// Register addresses and defaults
// --------------------------------------------------------------------
`define FLASH_ALO 1'h0 // Lower 16 bits of address lines
`define FLASH_AHI 1'h1 // Upper 6 bits of address lines
always @(posedge wb_clk_i) // Synchrounous
if(wb_rst_i)
address <= 22'h000000; // Interupt Enable default
else
if(wr_command) // If a write was requested
case(wb_adr_i) // Determine which register was writen to
`FLASH_ALO: address[15: 0] <= wb_dat_i;
`FLASH_AHI: address[21:16] <= wb_dat_i[5:0];
default: ; // Default
endcase // End of case
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_sdrio(
\tinput sys_clk,
\t
\tinput direction,
\tinput direction_r,
\tinput [ 1:0] mo,
\tinput [15:0] dout,
\toutput reg [15:0] di,
\t
\toutput [ 1:0] sdram_dqm,
\tinout [15:0] sdram_dq
);
wire [15:0] sdram_data_out;
assign sdram_dq = direction ? sdram_data_out : 16'hzzzz;
/*
* In this case, without DDR primitives and delays, this block
* is extremely simple
*/
assign sdram_dqm = mo;
assign sdram_data_out = dout;
// Behaviour
always @(posedge sys_clk) di <= sdram_dq;
endmodule
|
/*
* Memory arbitrer for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_mem_arbitrer (
input clk_i,
input rst_i,
// Wishbone slave 1
input [17:1] wb_adr_i,
input [ 1:0] wb_sel_i,
input wb_we_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_stb_i,
output wb_ack_o,
// CSR slave 1
input [17:1] csr_adr_i,
output [15:0] csr_dat_o,
input csr_stb_i,
// CSR master
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers
reg [1:0] wb_ack;
wire wb_ack_r;
wire wb_ack_w;
// Continous assignments
assign csrm_adr_o = csr_stb_i ? csr_adr_i : wb_adr_i;
assign csrm_sel_o = csr_stb_i ? 2'b11 : wb_sel_i;
assign csrm_we_o = wb_stb_i & !csr_stb_i & wb_we_i;
assign csrm_dat_o = wb_dat_i;
assign wb_dat_o = csrm_dat_i;
assign csr_dat_o = csrm_dat_i;
assign wb_ack_r = wb_ack[1];
assign wb_ack_w = wb_stb_i & !csr_stb_i;
assign wb_ack_o = wb_we_i ? wb_ack_w : wb_ack_r;
// Behaviour
always @(posedge clk_i)
wb_ack <= rst_i ? 2'b00
: { wb_ack[0], (wb_stb_i & !csr_stb_i & !(|wb_ack)) };
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// \t\t\taltpll
//
// Simulation Library Files(s):
// \t\t\taltera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation\'s design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
\tinclk0,
\tc0,
\tc1,
\tc4,
\tlocked);
\tinput\t inclk0;
\toutput\t c0;
\toutput\t c1;
\toutput\t c4;
\toutput\t locked;
\twire [4:0] sub_wire0;
\twire sub_wire2;
\twire [0:0] sub_wire7 = 1\'h0;
\twire [4:4] sub_wire4 = sub_wire0[4:4];
\twire [0:0] sub_wire3 = sub_wire0[0:0];
\twire [1:1] sub_wire1 = sub_wire0[1:1];
\twire c1 = sub_wire1;
\twire locked = sub_wire2;
\twire c0 = sub_wire3;
\twire c4 = sub_wire4;
\twire sub_wire5 = inclk0;
\twire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
\taltpll\taltpll_component (
\t\t\t\t.inclk (sub_wire6),
\t\t\t\t.clk (sub_wire0),
\t\t\t\t.locked (sub_wire2),
\t\t\t\t.activeclock (),
\t\t\t\t.areset (1\'b0),
\t\t\t\t.clkbad (),
\t\t\t\t.clkena ({6{1\'b1}}),
\t\t\t\t.clkloss (),
\t\t\t\t.clkswitch (1\'b0),
\t\t\t\t.configupdate (1\'b0),
\t\t\t\t.enable0 (),
\t\t\t\t.enable1 (),
\t\t\t\t.extclk (),
\t\t\t\t.extclkena ({4{1\'b1}}),
\t\t\t\t.fbin (1\'b1),
\t\t\t\t.fbmimicbidir (),
\t\t\t\t.fbout (),
\t\t\t\t.fref (),
\t\t\t\t.icdrclk (),
\t\t\t\t.pfdena (1\'b1),
\t\t\t\t.phasecounterselect ({4{1\'b1}}),
\t\t\t\t.phasedone (),
\t\t\t\t.phasestep (1\'b1),
\t\t\t\t.phaseupdown (1\'b1),
\t\t\t\t.pllena (1\'b1),
\t\t\t\t.scanaclr (1\'b0),
\t\t\t\t.scanclk (1\'b0),
\t\t\t\t.scanclkena (1\'b1),
\t\t\t\t.scandata (1\'b0),
\t\t\t\t.scandataout (),
\t\t\t\t.scandone (),
\t\t\t\t.scanread (1\'b0),
\t\t\t\t.scanwrite (1\'b0),
\t\t\t\t.sclkout0 (),
\t\t\t\t.sclkout1 (),
\t\t\t\t.vcooverrange (),
\t\t\t\t.vcounderrange ());
\tdefparam
\t\taltpll_component.bandwidth_type = "AUTO",
\t\taltpll_component.clk0_divide_by = 1,
\t\taltpll_component.clk0_duty_cycle = 50,
\t\taltpll_component.clk0_multiply_by = 2,
\t\taltpll_component.clk0_phase_shift = "0",
\t\taltpll_component.clk1_divide_by = 1,
\t\taltpll_component.clk1_duty_cycle = 50,
\t\taltpll_component.clk1_multiply_by = 2,
\t\taltpll_component.clk1_phase_shift = "-1750",
\t\taltpll_component.clk4_divide_by = 4,
\t\taltpll_component.clk4_duty_cycle = 50,
\t\taltpll_component.clk4_multiply_by = 1,
\t\taltpll_component.clk4_phase_shift = "0",
\t\taltpll_component.compensate_clock = "CLK0",
\t\taltpll_component.inclk0_input_frequency = 20000,
\t\taltpll_component.intended_device_family = "Cyclone IV E",
\t\taltpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
\t\taltpll_component.lpm_type = "altpll",
\t\taltpll_component.operation_mode = "NORMAL",
\t\taltpll_component.pll_type = "AUTO",
\t\taltpll_component.port_activeclock = "PORT_UNUSED",
\t\taltpll_component.port_areset = "PORT_UNUSED",
\t\taltpll_component.port_clkbad0 = "PORT_UNUSED",
\t\taltpll_component.port_clkbad1 = "PORT_UNUSED",
\t\taltpll_component.port_clkloss = "PORT_UNUSED",
\t\taltpll_component.port_clkswitch = "PORT_UNUSED",
\t\taltpll_component.port_configupdate = "PORT_UNUSED",
\t\taltpll_component.port_fbin = "PORT_UNUSED",
\t\taltpll_component.port_inclk0 = "PORT_USED",
\t\taltpll_component.port_inclk1 = "PORT_UNUSED",
\t\taltpll_component.port_locked = "PORT_USED",
\t\taltpll_component.port_pfdena = "PORT_UNUSED",
\t\taltpll_component.port_phasecounterselect = "PORT_UNUSED",
\t\taltpll_component.port_phasedone = "PORT_UNUSED",
\t\taltpll_component.port_phasestep = "PORT_UNUSED",
\t\taltpll_component.port_phaseupdown = "PORT_UNUSED",
\t\taltpll_component.port_pllena = "PORT_UNUSED",
\t\taltpll_component.port_scanaclr = "PORT_UNUSED",
\t\taltpll_component.port_scanclk = "PORT_UNUSED",
\t\taltpll_component.port_scanclkena = "PORT_UNUSED",
\t\taltpll_component.port_scandata = "PORT_UNUSED",
\t\taltpll_component.port_scandataout = "PORT_UNUSED",
\t\taltpll_component.port_scandone = "PORT_UNUSED",
\t\taltpll_component.port_scanread = "PORT_UNUSED",
\t\taltpll_component.port_scanwrite = "PORT_UNUSED",
\t\taltpll_component.port_clk0 = "PORT_USED",
\t\taltpll_component.port_clk1 = "PORT_USED",
\t\taltpll_component.port_clk2 = "PORT_UNUSED",
\t\taltpll_component.port_clk3 = "PORT_UNUSED",
\t\taltpll_component.port_clk4 = "PORT_USED",
\t\taltpll_component.port_clk5 = "PORT_UNUSED",
\t\taltpll_component.port_clkena0 = "PORT_UNUSED",
\t\taltpll_component.port_clkena1 = "PORT_UNUSED",
\t\taltpll_component.port_clkena2 = "PORT_UNUSED",
\t\taltpll_component.port_clkena3 = "PORT_UNUSED",
\t\taltpll_component.port_clkena4 = "PORT_UNUSED",
\t\taltpll_component.port_clkena5 = "PORT_UNUSED",
\t\taltpll_component.port_extclk0 = "PORT_UNUSED",
\t\taltpll_component.port_extclk1 = "PORT_UNUSED",
\t\taltpll_component.port_extclk2 = "PORT_UNUSED",
\t\taltpll_component.port_extclk3 = "PORT_UNUSED",
\t\taltpll_component.self_reset_on_loss_lock = "OFF",
\t\taltpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "12.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "12.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-63.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1750"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* Bitwise 8 and 16 bit shifter and rotator for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_shrot (
input [15:0] x,
input [ 7:0] y,
output [15:0] out,
input [ 2:0] func, // 0: rol, 1: ror, 2: rcl, 3: rcr,
// 4: shl/sal, 5: shr, 6: sar
input word_op,
input cfi,
input ofi,
output cfo,
output ofo
);
// Net declarations
wire [4:0] ror16;
wire [4:0] rol16;
wire [4:0] rcr16;
wire [4:0] rcl16;
wire [4:0] rot16;
wire [15:0] sal;
wire [15:0] sar;
wire [15:0] shr;
wire [15:0] sal16;
wire [15:0] sar16;
wire [15:0] shr16;
wire [7:0] sal8;
wire [7:0] sar8;
wire [7:0] shr8;
wire [3:0] ror8;
wire [3:0] rol8;
wire [3:0] rcr8;
wire [3:0] rcl8;
wire [3:0] rot8;
wire [ 7:0] outr8;
wire [15:0] outr16;
wire [15:0] rot;
wire cor8;
wire cor16;
wire unchanged;
wire ofo_sal;
wire ofo_sar;
wire ofo_shr;
wire cfo_sal;
wire cfo_sal8;
wire cfo_sal16;
wire cfo_sar;
wire cfo_sar8;
wire cfo_sar16;
wire cfo_shr;
wire cfo_shr8;
wire cfo_shr16;
wire ofor;
wire cfor;
// Module instantiation
zet_rxr8 rxr8 (
.x (x[7:0]),
.ci (cfi),
.y (rot8),
.e (func[1]),
.w (outr8),
.co (cor8)
);
zet_rxr16 rxr16 (
.x (x),
.ci (cfi),
.y (rot16),
.e (func[1]),
.w (outr16),
.co (cor16)
);
// Continous assignments
assign unchanged = word_op ? (y[4:0]==8'b0)
: (y[3:0]==4'b0);
// rotates
assign ror16 = { 1'b0, y[3:0] };
assign rol16 = { 1'b0, -y[3:0] };
assign ror8 = { 1'b0, y[2:0] };
assign rol8 = { 1'b0, -y[2:0] };
assign rcr16 = (y[4:0] <= 5'd16) ? y[4:0] : { 1'b0, y[3:0] - 4'b1 };
assign rcl16 = (y[4:0] <= 5'd17) ? 5'd17 - y[4:0] : 5'd2 - y[4:0];
assign rcr8 = y[3:0] <= 4'd8 ? y[3:0] : { 1'b0, y[2:0] - 3'b1 };
assign rcl8 = y[3:0] <= 4'd9 ? 4'd9 - y[3:0] : 4'd2 - y[3:0];
assign rot8 = func[1] ? (func[0] ? rcr8 : rcl8 )
: (func[0] ? ror8 : rol8 );
assign rot16 = func[1] ? (func[0] ? rcr16 : rcl16 )
: (func[0] ? ror16 : rol16 );
assign rot = word_op ? outr16 : { x[15:8], outr8 };
// shifts
assign { cfo_sal16, sal16 } = x << y;
assign { sar16, cfo_sar16 } = (y > 5'd16) ? 17'h1ffff
: (({x,1'b0} >> y) | (x[15] ? (17'h1ffff << (17 - y))
: 17'h0));
assign { shr16, cfo_shr16 } = ({x,1'b0} >> y);
assign { cfo_sal8, sal8 } = x[7:0] << y;
assign { sar8, cfo_sar8 } = (y > 5'd8) ? 9'h1ff
: (({x[7:0],1'b0} >> y) | (x[7] ? (9'h1ff << (9 - y))
: 9'h0));
assign { shr8, cfo_shr8 } = ({x[7:0],1'b0} >> y);
assign sal = word_op ? sal16 : { 8'd0, sal8 };
assign shr = word_op ? shr16 : { 8'd0, shr8 };
assign sar = word_op ? sar16 : { {8{sar8[7]}}, sar8 };
// overflows
assign ofor = func[0] ? // right
(word_op ? out[15]^out[14] : out[7]^out[6])
: // left
(word_op ? cfo^out[15] : cfo^out[7]);
assign ofo_sal = word_op ? (out[15] != cfo) : (out[7] != cfo);
assign ofo_sar = 1'b0;
assign ofo_shr = word_op ? x[15] : x[7];
assign ofo = unchanged ? ofi
: (func[2] ? (func[1] ? ofo_sar : (func[0] ? ofo_shr : ofo_sal))
: ofor);
// carries
assign cfor = func[1] ? (word_op ? cor16 : cor8)
: (func[0] ? (word_op ? out[15] : out[7])
: out[0]);
assign cfo_sal = word_op ? cfo_sal16 : cfo_sal8;
assign cfo_shr = word_op ? cfo_shr16 : cfo_shr8;
assign cfo_sar = word_op ? cfo_sar16 : cfo_sar8;
assign cfo = unchanged ? cfi
: (func[2] ? (func[1] ? cfo_sar
: (func[0] ? cfo_shr : cfo_sal))
: cfor);
// output
assign out = func[2] ? (func[1] ? sar : (func[0] ? shr : sal)) : rot;
endmodule
|
/*
* Text mode graphics for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
/*
* Pipeline description
* h_count[2:0]
* 000
* 001 col_addr, row_addr
* 010 ver_addr, hor_addr
* 011 csr_adr_o
* 100 csr_adr_i
* 101 sram_addr_
* 110 csr_dat_o
* 111 char_data_out, attr_data_out
* 000 vga_shift
* 001 vga_blue_o <= vga_shift[7]
*/
module vga_text_mode (
input clk,
input rst,
// CSR slave interface for reading
output reg [16:1] csr_adr_o,
input [15:0] csr_dat_i,
output csr_stb_o,
input [9:0] h_count,
input [9:0] v_count,
input horiz_sync_i,
input video_on_h_i,
output video_on_h_o,
// CRTC
input [5:0] cur_start,
input [5:0] cur_end,
input [4:0] vcursor,
input [6:0] hcursor,
output reg [3:0] attr,
output horiz_sync_o
);
// Registers and nets
reg [ 6:0] col_addr;
reg [ 4:0] row_addr;
reg [ 6:0] hor_addr;
reg [ 6:0] ver_addr;
wire [10:0] vga_addr;
wire [11:0] char_addr;
wire [ 7:0] char_data_out;
reg [ 7:0] attr_data_out;
reg [ 7:0] char_addr_in;
reg [7:0] pipe;
wire load_shift;
reg [9:0] video_on_h;
reg [9:0] horiz_sync;
wire fg_or_bg;
wire brown_bg;
wire brown_fg;
reg [ 7:0] vga_shift;
reg [ 3:0] fg_colour;
reg [ 2:0] bg_colour;
reg [22:0] blink_count;
// Cursor
reg cursor_on_v;
reg cursor_on_h;
reg cursor_on;
wire cursor_on1;
// Module instances
vga_char_rom char_rom (
.clk (clk),
.addr (char_addr),
.q (char_data_out)
);
// Continuous assignments
assign vga_addr = { 4'b0, hor_addr } + { ver_addr, 4'b0 };
assign char_addr = { char_addr_in, v_count[3:0] };
assign load_shift = pipe[7];
assign video_on_h_o = video_on_h[9];
assign horiz_sync_o = horiz_sync[9];
assign csr_stb_o = pipe[2];
assign fg_or_bg = vga_shift[7] ^ cursor_on;
assign cursor_on1 = cursor_on_h && cursor_on_v;
// Behaviour
// Address generation
always @(posedge clk)
if (rst)
begin
col_addr <= 7'h0;
row_addr <= 5'h0;
ver_addr <= 7'h0;
hor_addr <= 7'h0;
csr_adr_o <= 16'h0;
end
else
begin
// h_count[2:0] == 001
col_addr <= h_count[9:3];
row_addr <= v_count[8:4];
// h_count[2:0] == 010
ver_addr <= { 2'b00, row_addr } + { row_addr, 2'b00 };
// ver_addr = row_addr x 5
hor_addr <= col_addr;
// h_count[2:0] == 011
// vga_addr = row_addr * 80 + hor_addr
csr_adr_o <= { 5'h0, vga_addr };
end
// cursor
always @(posedge clk)
if (rst)
begin
cursor_on_v <= 1'b0;
cursor_on_h <= 1'b0;
end
else
begin
cursor_on_h <= (h_count[9:3] == hcursor[6:0]);
cursor_on_v <= (v_count[8:4] == vcursor[4:0])
&& ({2'b00, v_count[3:0]} >= cur_start)
&& ({2'b00, v_count[3:0]} <= cur_end);
end
// Pipeline count
always @(posedge clk)
pipe <= rst ? 8'b0 : { pipe[6:0], (h_count[2:0]==3'b0) };
// attr_data_out
always @(posedge clk) attr_data_out <= pipe[5] ? csr_dat_i[15:8]
: attr_data_out;
// char_addr_in
always @(posedge clk) char_addr_in <= pipe[5] ? csr_dat_i[7:0]
: char_addr_in;
// video_on_h
always @(posedge clk)
video_on_h <= rst ? 10'b0 : { video_on_h[8:0], video_on_h_i };
// horiz_sync
always @(posedge clk)
horiz_sync <= rst ? 10'b0 : { horiz_sync[8:0], horiz_sync_i };
// blink_count
always @(posedge clk)
blink_count <= rst ? 23'h0 : (blink_count + 23'h1);
// Video shift register
always @(posedge clk)
if (rst)
begin
fg_colour <= 4'b0;
bg_colour <= 3'b0;
vga_shift <= 8'h0;
end
else
if (load_shift)
begin
fg_colour <= attr_data_out[3:0];
bg_colour <= attr_data_out[6:4];
cursor_on <= (cursor_on1 | attr_data_out[7]) & blink_count[22];
vga_shift <= char_data_out;
end
else vga_shift <= { vga_shift[6:0], 1'b0 };
// pixel attribute
always @(posedge clk)
if (rst) attr <= 4'h0;
else attr <= fg_or_bg ? fg_colour : { 1'b0, bg_colour };
endmodule
|
/*
* Zet processor top level file
* Copyright (c) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
`include "defines.v"
module zet (
// Wishbone master interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
output [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o, // io/mem
output [ 1:0] wb_sel_o,
output wb_stb_o,
output wb_cyc_o,
input wb_ack_i,
input wb_tgc_i, // intr
output wb_tgc_o, // inta
input nmi,
output nmia,
output [19:0] pc // for debugging purposes
);
// Net declarations
wire [15:0] cpu_dat_o;
wire cpu_block;
wire [19:0] cpu_adr_o;
wire cpu_byte_o;
wire cpu_mem_op;
wire cpu_m_io;
wire [15:0] cpu_dat_i;
wire cpu_we_o;
wire [15:0] iid_dat_i;
// Module instantiations
zet_core core (
.clk (wb_clk_i),
.rst (wb_rst_i),
.intr (wb_tgc_i),
.inta (wb_tgc_o),
.nmi (nmi),
.nmia (nmia),
.cpu_adr_o (cpu_adr_o),
.iid_dat_i (iid_dat_i),
.cpu_dat_i (cpu_dat_i),
.cpu_dat_o (cpu_dat_o),
.cpu_byte_o (cpu_byte_o),
.cpu_block (cpu_block),
.cpu_mem_op (cpu_mem_op),
.cpu_m_io (cpu_m_io),
.cpu_we_o (cpu_we_o),
.pc (pc)
);
zet_wb_master wb_master (
.cpu_byte_o (cpu_byte_o),
.cpu_memop (cpu_mem_op),
.cpu_m_io (cpu_m_io),
.cpu_adr_o (cpu_adr_o),
.cpu_block (cpu_block),
.cpu_dat_i (cpu_dat_i),
.cpu_dat_o (cpu_dat_o),
.cpu_we_o (cpu_we_o),
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_adr_o (wb_adr_o),
.wb_we_o (wb_we_o),
.wb_tga_o (wb_tga_o),
.wb_sel_o (wb_sel_o),
.wb_stb_o (wb_stb_o),
.wb_cyc_o (wb_cyc_o),
.wb_ack_i (wb_ack_i)
);
// Assignments
assign iid_dat_i = (wb_tgc_o | nmia) ? wb_dat_i : cpu_dat_i;
endmodule
|
/*
* Zet processor core
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_core (
input clk,
input rst,
// interrupts
input intr,
output inta,
input nmi,
output nmia,
// interface to wishbone
output [19:0] cpu_adr_o,
input [15:0] iid_dat_i,
input [15:0] cpu_dat_i,
output [15:0] cpu_dat_o,
output cpu_byte_o,
input cpu_block,
output cpu_mem_op,
output cpu_m_io,
output cpu_we_o,
output [19:0] pc // for debugging purposes
);
// Net declarations
wire [`IR_SIZE-1:0] ir;
wire [15:0] off;
wire [15:0] imm;
wire wr_ip0;
wire [15:0] cs;
wire [15:0] ip;
wire of;
wire zf;
wire ifl;
wire iflm;
wire tfl;
wire tflm;
wire iflss;
wire wr_ss;
wire cx_zero;
wire div_exc;
wire [19:0] addr_exec;
wire byte_fetch;
wire byte_exec;
// wire decode - microcode
wire [`MICRO_ADDR_WIDTH-1:0] seq_addr;
wire [3:0] src;
wire [3:0] dst;
wire [3:0] base;
wire [3:0] index;
wire [1:0] seg;
wire end_seq;
wire [2:0] fdec;
wire div;
// wires fetch - decode
wire [7:0] opcode;
wire [7:0] modrm;
wire rep;
wire exec_st;
wire ld_base;
wire [2:0] sop_l;
wire need_modrm;
wire need_off;
wire need_imm;
wire off_size;
wire imm_size;
wire ext_int;
// wires fetch - microcode
wire [15:0] off_l;
wire [15:0] imm_l;
wire [15:0] imm_d;
wire [`IR_SIZE-1:0] rom_ir;
wire [5:0] ftype;
// wires fetch - exec
wire [15:0] imm_f;
// wires and regs for hlt
wire block_or_hlt;
wire hlt_op;
wire hlt_in;
wire hlt_out;
reg hlt_op_old;
reg hlt;
// regs for nmi
reg nmir;
reg nmi_old;
reg nmia_old;
// Module instantiations
zet_fetch fetch (
.clk (clk),
.rst (rst),
// to decode
.opcode (opcode),
.modrm (modrm),
.rep (rep),
.exec_st (exec_st),
.ld_base (ld_base),
.sop_l (sop_l),
// from decode
.need_modrm (need_modrm),
.need_off (need_off),
.need_imm (need_imm),
.off_size (off_size),
.imm_size (imm_size),
.ext_int (ext_int),
.end_seq (end_seq),
// to microcode
.off_l (off_l),
.imm_l (imm_l),
// from microcode
.ftype (ftype),
// to exec
.imm_f (imm_f),
.wr_ip0 (wr_ip0),
// from exec
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.iflm (iflm),
.tflm (tflm),
.iflss (iflss),
.cx_zero (cx_zero),
.div_exc (div_exc),
// to wb
.data (cpu_dat_i),
.pc (pc),
.bytefetch (byte_fetch),
.block (block_or_hlt),
.intr (intr),
.nmir (nmir)
);
zet_decode decode (
.clk (clk),
.rst (rst),
.opcode (opcode),
.modrm (modrm),
.rep (rep),
.block (block_or_hlt),
.exec_st (exec_st),
.div_exc (div_exc),
.ld_base (ld_base),
.div (div),
.tfl (tfl),
.tflm (tflm),
.need_modrm (need_modrm),
.need_off (need_off),
.need_imm (need_imm),
.off_size (off_size),
.imm_size (imm_size),
.sop_l (sop_l),
.intr (intr),
.ifl (ifl),
.iflm (iflm),
.inta (inta),
.ext_int (ext_int),
.nmir (nmir),
.nmia (nmia),
.wr_ss (wr_ss),
.iflss (iflss),
.seq_addr (seq_addr),
.src (src),
.dst (dst),
.base (base),
.index (index),
.seg (seg),
.f (fdec),
.end_seq (end_seq)
);
zet_micro_data micro_data (
// from decode
.n_micro (seq_addr),
.off_i (off_l),
.imm_i (imm_l),
.src (src),
.dst (dst),
.base (base),
.index (index),
.seg (seg),
.fdec (fdec),
.div (div),
.end_seq (end_seq),
// to exec
.ir (rom_ir),
.off_o (off),
.imm_o (imm_d)
);
zet_exec exec (
.clk (clk),
.rst (rst),
// from fetch
.ir (ir),
.off (off),
.imm (imm),
.wrip0 (wr_ip0),
// to fetch
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.ifl (ifl),
.tfl (tfl),
.cx_zero (cx_zero),
.div_exc (div_exc),
.wr_ss (wr_ss),
// from wb
.memout (iid_dat_i),
.wr_data (cpu_dat_o),
.addr (addr_exec),
.we (cpu_we_o),
.m_io (cpu_m_io),
.byteop (byte_exec),
.block (block_or_hlt)
);
// Assignments
assign cpu_adr_o = exec_st ? addr_exec : pc;
assign cpu_byte_o = exec_st ? byte_exec : byte_fetch;
assign cpu_mem_op = ir[`MEM_OP];
assign ir = exec_st ? rom_ir : `ADD_IP;
assign imm = exec_st ? imm_d : imm_f;
assign ftype = rom_ir[28:23];
assign hlt_op = ((opcode == `OP_HLT) && exec_st);
assign hlt_in = (hlt_op && !hlt_op_old && !hlt_out);
assign hlt_out = (intr & ifl) | nmir;
assign block_or_hlt = cpu_block | hlt | hlt_in;
// Behaviour
always @(posedge clk)
if (rst)
hlt_op_old <= 1\'b0;
else
if (hlt_op)
hlt_op_old <= 1\'b1;
else
hlt_op_old <= 1\'b0;
always @(posedge clk)
if (rst)
hlt <= 1\'b0;
else
if (hlt_in)
hlt <= 1\'b1;
else if (hlt_out)
hlt <= 1\'b0;
always @(posedge clk)
if (rst)
begin
nmir <= 1\'b0;
nmi_old <= 1\'b0;
nmia_old <= 1\'b0;
end
else
begin
nmi_old <= nmi;
nmia_old <= nmia;
if (nmi & ~nmi_old)
nmir <= 1\'b1;
else if (nmia_old)
nmir <= 1\'b0;
end
endmodule
|
/*
* GPIO module to deal with LEDs and switches
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module sw_leds (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input wb_adr_i,
output [15:0] wb_dat_o,
input [15:0] wb_dat_i,
input [ 1:0] wb_sel_i,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// GPIO inputs/outputs
output reg [13:0] leds_,
input [ 7:0] sw_,
input pb_,
input tick,
output reg nmi_pb
);
// Registers and nets
wire op;
reg tick_old;
reg tick1;
reg nmi_pb_pressed;
reg [2:0] nmi_cnt;
// Continuous assignments
assign op = wb_cyc_i & wb_stb_i;
assign wb_ack_o = op;
assign wb_dat_o = wb_adr_i ? { 2'b00, leds_ }
: { 8'h00, sw_ };
// Behaviour
always @(posedge wb_clk_i)
leds_ <= wb_rst_i ? 14'h0
: ((op & wb_we_i & wb_adr_i) ? wb_dat_i[13:0] : leds_);
always @(posedge wb_clk_i)
begin
tick_old <= tick;
tick1 <= tick & ~tick_old;
end
always @(posedge wb_clk_i)
nmi_pb_pressed <= !pb_;
always @(posedge wb_clk_i)
begin
if (wb_rst_i)
begin
nmi_pb <= 1'b0;
nmi_cnt <= 3'b111;
end
else
begin
if (nmi_cnt == 3'b111)
begin
if (nmi_pb_pressed != nmi_pb)
begin
nmi_pb <= nmi_pb_pressed;
nmi_cnt <= nmi_cnt + 3'b001; // nmi_cnt <= 3'b000;
end
end
else if (tick1)
nmi_cnt <= nmi_cnt + 3'b001;
end
end
endmodule
|
/*
* Internal RAM for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vdu_ram_2k_char (
input clk,
input rst,
input we,
input [10:0] addr,
output [ 7:0] rdata,
input [ 7:0] wdata
);
// Registers and nets
reg [ 7:0] mem[0:2047];
reg [10:0] addr_reg;
always @(posedge clk)
begin
if (we) mem[addr] <= wdata;
addr_reg <= addr;
end
// Combinatorial logic
assign rdata = mem[addr_reg];
initial $readmemh("buff_rom.dat", mem);
endmodule
|
/*
* RS-232 asynchronous TX module
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module serial_atx (
input clk,
input txd_start,
input baud1tick, // Desired baud rate
input [7:0] txd_data,
output reg txd, // Put together the start, data and stop bits
output txd_busy
);
// Transmitter state machine
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted
reg [3:0] state;
wire BaudTick = txd_busy ? baud1tick : 1'b0;
wire txd_ready;
reg [7:0] txd_dataReg;
// Continuous assignments
assign txd_ready = (state==0);
assign txd_busy = ~txd_ready;
always @(posedge clk) if(txd_ready & txd_start) txd_dataReg <= txd_data;
wire [7:0] txd_dataD = RegisterInputData ? txd_dataReg : txd_data;
always @(posedge clk)
case(state)
4'b0000: if(txd_start) state <= 4'b0001;
4'b0001: if(BaudTick) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
4'b0010: if(BaudTick) state <= 4'b0011; // stop1
4'b0011: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase
reg muxbit; // Output mux
always @( * )
case(state[2:0])
3'd0: muxbit <= txd_dataD[0];
3'd1: muxbit <= txd_dataD[1];
3'd2: muxbit <= txd_dataD[2];
3'd3: muxbit <= txd_dataD[3];
3'd4: muxbit <= txd_dataD[4];
3'd5: muxbit <= txd_dataD[5];
3'd6: muxbit <= txd_dataD[6];
3'd7: muxbit <= txd_dataD[7];
endcase
always @(posedge clk) txd <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
endmodule
|
/*
* Zet SoC top level file for Altera DE0 board
* Copyright (C) 2009, 2010 Zeus Gomez Marmolejo <[email protected]>
* Video SDRAM Additions by Charley Picker <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module kotku (
// Clock input
input clk_50_,
// General purpose IO
input [7:0] sw_,
input key_,
output [6:0] hex0_,
output [6:0] hex1_,
output [6:0] hex2_,
output [6:0] hex3_,
output [9:0] ledg_,
// flash signals
output [21:0] flash_addr_,
input [15:0] flash_data_,
output flash_oe_n_,
output flash_ce_n_,
// sdram signals
output [11:0] sdram_addr_,
inout [15:0] sdram_data_,
output [ 1:0] sdram_ba_,
output sdram_ras_n_,
output sdram_cas_n_,
output sdram_ce_,
output sdram_clk_,
output sdram_we_n_,
output sdram_cs_n_,
// VGA signals
output [ 3:0] tft_lcd_r_,
output [ 3:0] tft_lcd_g_,
output [ 3:0] tft_lcd_b_,
output tft_lcd_hsync_,
output tft_lcd_vsync_,
// UART signals
output uart_txd_,
// PS2 signals
input ps2_kclk_, // PS2 keyboard Clock
inout ps2_kdat_, // PS2 Keyboard Data
inout ps2_mclk_, // PS2 Mouse Clock
inout ps2_mdat_, // PS2 Mouse Data
// SD card signals
output sd_sclk_,
input sd_miso_,
output sd_mosi_,
output sd_ss_,
// To expansion header
output chassis_spk_,
output speaker_l_, // Speaker output, left channel
output speaker_r_ // Speaker output, right channel
);
// Registers and nets
wire clk;
wire rst_lck;
wire [15:0] dat_o;
wire [15:0] dat_i;
wire [19:1] adr;
wire we;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack;
wire lock;
// wires to BIOS ROM
wire [15:0] rom_dat_o;
wire [15:0] rom_dat_i;
wire rom_tga_i;
wire [19:1] rom_adr_i;
wire [ 1:0] rom_sel_i;
wire rom_we_i;
wire rom_cyc_i;
wire rom_stb_i;
wire rom_ack_o;
// Unused outputs
wire flash_we_n_;
wire flash_rst_n_;
wire [1:0] sdram_dqm_;
wire [7:0] leds_;
// Unused inputs
wire uart_rxd_;
// wires to flash controller
wire [15:0] fl_dat_o;
wire [15:0] fl_dat_i;
wire fl_tga_i;
wire [19:1] fl_adr_i;
wire [ 1:0] fl_sel_i;
wire fl_we_i;
wire fl_cyc_i;
wire fl_stb_i;
wire fl_ack_o;
// wires to vga controller
wire [15:0] vga_dat_o;
wire [15:0] vga_dat_i;
wire vga_tga_i;
wire [19:1] vga_adr_i;
wire [ 1:0] vga_sel_i;
wire vga_we_i;
wire vga_cyc_i;
wire vga_stb_i;
wire vga_ack_o;
// cross clock domain synchronized signals
wire [15:0] vga_dat_o_s;
wire [15:0] vga_dat_i_s;
wire vga_tga_i_s;
wire [19:1] vga_adr_i_s;
wire [ 1:0] vga_sel_i_s;
wire vga_we_i_s;
wire vga_cyc_i_s;
wire vga_stb_i_s;
wire vga_ack_o_s;
// wires to uart controller
wire [15:0] uart_dat_o;
wire [15:0] uart_dat_i;
wire uart_tga_i;
wire [19:1] uart_adr_i;
wire [ 1:0] uart_sel_i;
wire uart_we_i;
wire uart_cyc_i;
wire uart_stb_i;
wire uart_ack_o;
// wires for Sound module
wire [19:1] wb_sb_adr_i; // Sound Address
wire [15:0] wb_sb_dat_i; // Sound
wire [15:0] wb_sb_dat_o; // Sound
wire [ 1:0] wb_sb_sel_i; // Sound
wire wb_sb_cyc_i; // Sound
wire wb_sb_stb_i; // Sound
wire wb_sb_we_i; // Sound
wire wb_sb_ack_o; // Sound
wire wb_sb_tga_i; // Sound
// wires to keyboard controller
wire [15:0] keyb_dat_o;
wire [15:0] keyb_dat_i;
wire keyb_tga_i;
wire [19:1] keyb_adr_i;
wire [ 1:0] keyb_sel_i;
wire keyb_we_i;
wire keyb_cyc_i;
wire keyb_stb_i;
wire keyb_ack_o;
// wires to timer controller
wire [15:0] timer_dat_o;
wire [15:0] timer_dat_i;
wire timer_tga_i;
wire [19:1] timer_adr_i;
wire [ 1:0] timer_sel_i;
wire timer_we_i;
wire timer_cyc_i;
wire timer_stb_i;
wire timer_ack_o;
// wires to sd controller
wire [19:1] sd_adr_i;
wire [ 7:0] sd_dat_o;
wire [15:0] sd_dat_i;
wire sd_tga_i;
wire [ 1:0] sd_sel_i;
wire sd_we_i;
wire sd_cyc_i;
wire sd_stb_i;
wire sd_ack_o;
// wires to sd bridge
wire [19:1] sd_adr_i_s;
wire [15:0] sd_dat_o_s;
wire [15:0] sd_dat_i_s;
wire sd_tga_i_s;
wire [ 1:0] sd_sel_i_s;
wire sd_we_i_s;
wire sd_cyc_i_s;
wire sd_stb_i_s;
wire sd_ack_o_s;
// wires to gpio controller
wire [15:0] gpio_dat_o;
wire [15:0] gpio_dat_i;
wire gpio_tga_i;
wire [19:1] gpio_adr_i;
wire [ 1:0] gpio_sel_i;
wire gpio_we_i;
wire gpio_cyc_i;
wire gpio_stb_i;
wire gpio_ack_o;
// wires to SDRAM controller
wire [19:1] fmlbrg_adr_s;
wire [15:0] fmlbrg_dat_w_s;
wire [15:0] fmlbrg_dat_r_s;
wire [ 1:0] fmlbrg_sel_s;
wire fmlbrg_cyc_s;
wire fmlbrg_stb_s;
wire fmlbrg_tga_s;
wire fmlbrg_we_s;
wire fmlbrg_ack_s;
wire [19:1] fmlbrg_adr;
wire [15:0] fmlbrg_dat_w;
wire [15:0] fmlbrg_dat_r;
wire [ 1:0] fmlbrg_sel;
wire fmlbrg_cyc;
wire fmlbrg_stb;
wire fmlbrg_tga;
wire fmlbrg_we;
wire fmlbrg_ack;
wire [19:1] csrbrg_adr_s;
wire [15:0] csrbrg_dat_w_s;
wire [15:0] csrbrg_dat_r_s;
wire [ 1:0] csrbrg_sel_s;
wire csrbrg_cyc_s;
wire csrbrg_stb_s;
wire csrbrg_tga_s;
wire csrbrg_we_s;
wire csrbrg_ack_s;
wire [19:1] csrbrg_adr;
wire [15:0] csrbrg_dat_w;
wire [15:0] csrbrg_dat_r;
wire [ 1:0] csrbrg_sel;
wire csrbrg_tga;
wire csrbrg_cyc;
wire csrbrg_stb;
wire csrbrg_we;
wire csrbrg_ack;
wire [ 2:0] csr_a;
wire csr_we;
wire [15:0] csr_dw;
wire [15:0] csr_dr_hpdmc;
// wires to hpdmc slave interface
wire [22:0] fml_adr;
wire fml_stb;
wire fml_we;
wire fml_ack;
wire [ 1:0] fml_sel;
wire [15:0] fml_di;
wire [15:0] fml_do;
// wires to fml bridge master interface
wire [19:0] fml_fmlbrg_adr;
wire fml_fmlbrg_stb;
wire fml_fmlbrg_we;
wire fml_fmlbrg_ack;
wire [ 1:0] fml_fmlbrg_sel;
wire [15:0] fml_fmlbrg_di;
wire [15:0] fml_fmlbrg_do;
// wires to VGA CPU FML master interface
wire [19:0] vga_cpu_fml_adr; // 1MB Memory Address range
wire vga_cpu_fml_stb;
wire vga_cpu_fml_we;
wire vga_cpu_fml_ack;
wire [1:0] vga_cpu_fml_sel;
wire [15:0] vga_cpu_fml_do;
wire [15:0] vga_cpu_fml_di;
// wires to VGA LCD FML master interface
wire [19:0] vga_lcd_fml_adr; // 1MB Memory Address range
wire vga_lcd_fml_stb;
wire vga_lcd_fml_we;
wire vga_lcd_fml_ack;
wire [1:0] vga_lcd_fml_sel;
wire [15:0] vga_lcd_fml_do;
wire [15:0] vga_lcd_fml_di;
// wires to default stb/ack
wire def_cyc_i;
wire def_stb_i;
wire [15:0] sw_dat_o;
wire sdram_clk;
wire vga_clk;
wire [ 7:0] intv;
wire [ 2:0] iid;
wire intr;
wire inta;
wire nmi_pb;
wire nmi;
wire nmia;
wire [19:0] pc;
reg [16:0] rst_debounce;
wire timer_clk;
wire timer2_o;
// Audio only signals
wire [ 7:0] aud_dat_o;
wire aud_cyc_i;
wire aud_ack_o;
wire aud_sel_cond;
// Keyboard-audio shared signals
wire [ 7:0] kaud_dat_o;
wire kaud_cyc_i;
wire kaud_ack_o;
`ifndef SIMULATION
/*
* Debounce it (counter holds reset for 10.49ms),
* and generate power-on reset.
*/
initial rst_debounce <= 17'h1FFFF;
reg rst;
initial rst <= 1'b1;
always @(posedge clk) begin
if(~rst_lck) /* reset is active low */
rst_debounce <= 17'h1FFFF;
else if(rst_debounce != 17'd0)
rst_debounce <= rst_debounce - 17'd1;
rst <= rst_debounce != 17'd0;
end
`else
wire rst;
assign rst = !rst_lck;
`endif
// Module instantiations
pll pll (
.inclk0 (clk_50_),
.c0 (sdram_clk), // 100 Mhz
.c1 (), // 25 Mhz
.c2 (clk), // 12.5 Mhz
.locked (lock)
);
clk_gen #(
.res (21),
.phase (21'd100091)
) timerclk (
.clk_i (vga_clk), // 25 MHz
.rst_i (rst),
.clk_o (timer_clk) // 1.193178 MHz (required 1.193182 MHz)
);
bootrom bootrom (
.clk (clk), // Wishbone slave interface
.rst (rst),
.wb_dat_i (rom_dat_i),
.wb_dat_o (rom_dat_o),
.wb_adr_i (rom_adr_i),
.wb_we_i (rom_we_i ),
.wb_tga_i (rom_tga_i),
.wb_stb_i (rom_stb_i),
.wb_cyc_i (rom_cyc_i),
.wb_sel_i (rom_sel_i),
.wb_ack_o (rom_ack_o)
);
flash16 flash16 (
// Wishbone slave interface
.wb_clk_i (clk), // Main Clock
.wb_rst_i (rst), // Reset Line
.wb_adr_i (fl_adr_i[1]), // Address lines
.wb_sel_i (fl_sel_i), // Select lines
.wb_dat_i (fl_dat_i), // Command to send
.wb_dat_o (fl_dat_o), // Received data
.wb_cyc_i (fl_cyc_i), // Cycle
.wb_stb_i (fl_stb_i), // Strobe
.wb_we_i (fl_we_i), // Write enable
.wb_ack_o (fl_ack_o), // Normal bus termination
// Pad signals
.flash_addr_ (flash_addr_),
.flash_data_ (flash_data_),
.flash_we_n_ (flash_we_n_),
.flash_oe_n_ (flash_oe_n_),
.flash_ce_n_ (flash_ce_n_),
.flash_rst_n_ (flash_rst_n_)
);
wb_abrgr wb_fmlbrg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (fmlbrg_adr_s),
.wbs_dat_i (fmlbrg_dat_w_s),
.wbs_dat_o (fmlbrg_dat_r_s),
.wbs_sel_i (fmlbrg_sel_s),
.wbs_tga_i (fmlbrg_tga_s),
.wbs_stb_i (fmlbrg_stb_s),
.wbs_cyc_i (fmlbrg_cyc_s),
.wbs_we_i (fmlbrg_we_s),
.wbs_ack_o (fmlbrg_ack_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (fmlbrg_adr),
.wbm_dat_o (fmlbrg_dat_w),
.wbm_dat_i (fmlbrg_dat_r),
.wbm_sel_o (fmlbrg_sel),
.wbm_tga_o (fmlbrg_tga),
.wbm_stb_o (fmlbrg_stb),
.wbm_cyc_o (fmlbrg_cyc),
.wbm_we_o (fmlbrg_we),
.wbm_ack_i (fmlbrg_ack)
);
fmlbrg #(
.fml_depth (20), // 8086 can only address 1 MB
.cache_depth (10) // 1 Kbyte cache
) fmlbrg (
.sys_clk (sdram_clk),
.sys_rst (rst),
\t
\t // Wishbone slave interface
.wb_adr_i (fmlbrg_adr),
\t .wb_cti_i(3'b0),
.wb_dat_i (fmlbrg_dat_w),
.wb_dat_o (fmlbrg_dat_r),
.wb_sel_i (fmlbrg_sel),
.wb_cyc_i (fmlbrg_cyc),
.wb_stb_i (fmlbrg_stb),
.wb_tga_i (fmlbrg_tga),
.wb_we_i (fmlbrg_we),
.wb_ack_o (fmlbrg_ack),
// FML master 1 interface
.fml_adr (fml_fmlbrg_adr),
.fml_stb (fml_fmlbrg_stb),
.fml_we (fml_fmlbrg_we),
.fml_ack (fml_fmlbrg_ack),
.fml_sel (fml_fmlbrg_sel),
.fml_do (fml_fmlbrg_do),
.fml_di (fml_fmlbrg_di),
\t
\t // Direct Cache Bus
\t .dcb_stb(1'b0),
\t .dcb_adr(20'b0),
\t .dcb_dat(),
\t .dcb_hit()
\t
);
wb_abrgr wb_csrbrg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (csrbrg_adr_s),
.wbs_dat_i (csrbrg_dat_w_s),
.wbs_dat_o (csrbrg_dat_r_s),
.wbs_sel_i (csrbrg_sel_s),
.wbs_tga_i (csrbrg_tga_s),
.wbs_stb_i (csrbrg_stb_s),
.wbs_cyc_i (csrbrg_cyc_s),
.wbs_we_i (csrbrg_we_s),
.wbs_ack_o (csrbrg_ack_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (csrbrg_adr),
.wbm_dat_o (csrbrg_dat_w),
.wbm_dat_i (csrbrg_dat_r),
.wbm_sel_o (csrbrg_sel),
.wbm_tga_o (csrbrg_tga),
.wbm_stb_o (csrbrg_stb),
.wbm_cyc_o (csrbrg_cyc),
.wbm_we_o (csrbrg_we),
.wbm_ack_i (csrbrg_ack)
);
csrbrg csrbrg (
.sys_clk (sdram_clk),
.sys_rst (rst),
// Wishbone slave interface
.wb_adr_i (csrbrg_adr[3:1]),
.wb_dat_i (csrbrg_dat_w),
.wb_dat_o (csrbrg_dat_r),
.wb_cyc_i (csrbrg_cyc),
.wb_stb_i (csrbrg_stb),
.wb_we_i (csrbrg_we),
.wb_ack_o (csrbrg_ack),
// CSR master interface
.csr_a (csr_a),
.csr_we (csr_we),
.csr_do (csr_dw),
.csr_di (csr_dr_hpdmc)
);
fmlarb #(
.fml_depth (23)
) fmlarb (
.sys_clk (sdram_clk),
\t.sys_rst (rst),
\t
\t// Master 0 interface - VGA LCD FML (Reserved video memory port has highest priority)
\t.m0_adr ({3'b001, vga_lcd_fml_adr}), // 1 - 2 MB Addressable memory range
\t.m0_stb (vga_lcd_fml_stb),
\t.m0_we (vga_lcd_fml_we),
\t.m0_ack (vga_lcd_fml_ack),
\t.m0_sel (vga_lcd_fml_sel),
\t.m0_di (vga_lcd_fml_do),
\t.m0_do (vga_lcd_fml_di),
\t\t
\t// Master 1 interface - Wishbone FML bridge
\t.m1_adr ({3'b000, fml_fmlbrg_adr}), // 0 - 1 MB Addressable memory range
\t.m1_stb (fml_fmlbrg_stb),
\t.m1_we (fml_fmlbrg_we),
\t.m1_ack (fml_fmlbrg_ack),
\t.m1_sel (fml_fmlbrg_sel),
\t.m1_di (fml_fmlbrg_do),
\t.m1_do (fml_fmlbrg_di),
\t
\t// Master 2 interface - VGA CPU FML
\t.m2_adr ({3'b001, vga_cpu_fml_adr}), // 1 - 2 MB Addressable memory range
\t.m2_stb (vga_cpu_fml_stb),
\t.m2_we (vga_cpu_fml_we),
\t.m2_ack (vga_cpu_fml_ack),
\t.m2_sel (vga_cpu_fml_sel),
\t.m2_di (vga_cpu_fml_do),
\t.m2_do (vga_cpu_fml_di),
\t
\t// Master 3 interface - not connected
\t.m3_adr ({3'b010, 20'b0}), // 2 - 3 MB Addressable memory range
\t.m3_stb (1'b0),
\t.m3_we (1'b0),
\t.m3_ack (),
\t.m3_sel (2'b00),
\t.m3_di (16'h0000),
\t.m3_do (),
\t
\t// Master 4 interface - not connected
\t.m4_adr ({3'b011, 20'b0}), // 3 - 4 MB Addressable memory range
\t.m4_stb (1'b0),
\t.m4_we (1'b0),
\t.m4_ack (),
\t.m4_sel (2'b00),
\t.m4_di (16'h0000),
\t.m4_do (),
\t
\t// Master 5 interface - not connected
\t.m5_adr ({3'b100, 20'b0}), // 4 - 5 MB Addressable memory range
\t.m5_stb (1'b0),
\t.m5_we (1'b0),
\t.m5_ack (),
\t.m5_sel (2'b00),
\t.m5_di (16'h0000),
\t.m5_do (),
\t
\t// Arbitrer Slave interface - connected to hpdmc
\t.s_adr (fml_adr),
\t.s_stb (fml_stb),
\t.s_we (fml_we),
\t.s_ack (fml_ack),
\t.s_sel (fml_sel),
\t.s_di (fml_di),
\t.s_do (fml_do)
);
hpdmc #(
.csr_addr (1'b0),
.sdram_depth (23),
.sdram_columndepth (8)
) hpdmc (
.sys_clk (sdram_clk),
.sys_rst (rst),
// CSR slave interface
.csr_a (csr_a),
.csr_we (csr_we),
.csr_di (csr_dw),
.csr_do (csr_dr_hpdmc),
// FML slave interface
.fml_adr (fml_adr),
.fml_stb (fml_stb),
.fml_we (fml_we),
.fml_ack (fml_ack),
.fml_sel (fml_sel),
.fml_di (fml_do),
.fml_do (fml_di),
// SDRAM pad signals
.sdram_cke (sdram_ce_),
.sdram_cs_n (sdram_cs_n_),
.sdram_we_n (sdram_we_n_),
.sdram_cas_n (sdram_cas_n_),
.sdram_ras_n (sdram_ras_n_),
.sdram_dqm (sdram_dqm_),
.sdram_adr (sdram_addr_),
.sdram_ba (sdram_ba_),
.sdram_dq (sdram_data_)
);
wb_abrg vga_brg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (vga_adr_i_s),
.wbs_dat_i (vga_dat_i_s),
.wbs_dat_o (vga_dat_o_s),
.wbs_sel_i (vga_sel_i_s),
.wbs_tga_i (vga_tga_i_s),
.wbs_stb_i (vga_stb_i_s),
.wbs_cyc_i (vga_cyc_i_s),
.wbs_we_i (vga_we_i_s),
.wbs_ack_o (vga_ack_o_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (vga_adr_i),
.wbm_dat_o (vga_dat_i),
.wbm_dat_i (vga_dat_o),
.wbm_sel_o (vga_sel_i),
.wbm_tga_o (vga_tga_i),
.wbm_stb_o (vga_stb_i),
.wbm_cyc_o (vga_cyc_i),
.wbm_we_o (vga_we_i),
.wbm_ack_i (vga_ack_o)
);
vga_fml #(
.fml_depth (20) // 1MB Memory Address range
) vga (
.wb_rst_i (rst),
// Wishbone slave interface
.wb_clk_i (sdram_clk), // 100MHz VGA clock
.wb_dat_i (vga_dat_i),
.wb_dat_o (vga_dat_o),
.wb_adr_i (vga_adr_i[16:1]), // 128K
.wb_we_i (vga_we_i),
.wb_tga_i (vga_tga_i),
.wb_sel_i (vga_sel_i),
.wb_stb_i (vga_stb_i),
.wb_cyc_i (vga_cyc_i),
.wb_ack_o (vga_ack_o),
// VGA pad signals
.vga_red_o (tft_lcd_r_),
.vga_green_o (tft_lcd_g_),
.vga_blue_o (tft_lcd_b_),
.horiz_sync (tft_lcd_hsync_),
.vert_sync (tft_lcd_vsync_),
// VGA CPU FML master interface
.vga_cpu_fml_adr(vga_cpu_fml_adr),
.vga_cpu_fml_stb(vga_cpu_fml_stb),
.vga_cpu_fml_we(vga_cpu_fml_we),
.vga_cpu_fml_ack(vga_cpu_fml_ack),
.vga_cpu_fml_sel(vga_cpu_fml_sel),
.vga_cpu_fml_do(vga_cpu_fml_do),
.vga_cpu_fml_di(vga_cpu_fml_di),
// VGA LCD FML master interface
.vga_lcd_fml_adr(vga_lcd_fml_adr),
.vga_lcd_fml_stb(vga_lcd_fml_stb),
.vga_lcd_fml_we(vga_lcd_fml_we),
.vga_lcd_fml_ack(vga_lcd_fml_ack),
.vga_lcd_fml_sel(vga_lcd_fml_sel),
.vga_lcd_fml_do(vga_lcd_fml_do),
.vga_lcd_fml_di(vga_lcd_fml_di),
.vga_clk(vga_clk)
);
// RS232 COM1 Port
serial com1 (
.wb_clk_i (clk), // Main Clock
.wb_rst_i (rst), // Reset Line
.wb_adr_i (uart_adr_i[2:1]), // Address lines
.wb_sel_i (uart_sel_i), // Select lines
.wb_dat_i (uart_dat_i), // Command to send
.wb_dat_o (uart_dat_o),
.wb_we_i (uart_we_i), // Write enable
.wb_stb_i (uart_stb_i),
.wb_cyc_i (uart_cyc_i),
.wb_ack_o (uart_ack_o),
.wb_tgc_o (intv[4]), // Interrupt request
.rs232_tx (uart_txd_), // UART signals
.rs232_rx (uart_rxd_) // serial input/output
);
// Sound Module Instantiation
sound sound (
.wb_clk_i (clk), // Main Clock
.wb_rst_i (rst), // Reset Line
.wb_dat_i (wb_sb_dat_i), // Command to send
.wb_dat_o (wb_sb_dat_o), // Received data
.wb_cyc_i (wb_sb_cyc_i), // Cycle
.wb_stb_i (wb_sb_stb_i), // Strobe
.wb_adr_i (wb_sb_adr_i[3:1]), // Address lines
.wb_sel_i (wb_sb_sel_i), // Select lines
.wb_we_i (wb_sb_we_i), // Write enable
.wb_ack_o (wb_sb_ack_o), // Normal bus termination
.audio_l (speaker_l_), // Audio Output Left Channel
.audio_r (speaker_r_) // Audio Output Right Channel
);
ps2 ps2 (
.wb_clk_i (clk), // Main Clock
.wb_rst_i (rst), // Reset Line
.wb_adr_i (keyb_adr_i[2:1]), // Address lines
.wb_sel_i (keyb_sel_i), // Select lines
.wb_dat_i (keyb_dat_i), // Command to send to Ethernet
.wb_dat_o (keyb_dat_o),
.wb_we_i (keyb_we_i), // Write enable
.wb_stb_i (keyb_stb_i),
.wb_cyc_i (keyb_cyc_i),
.wb_ack_o (keyb_ack_o),
.wb_tgk_o (intv[1]), // Keyboard Interrupt request
.wb_tgm_o (intv[3]), // Mouse Interrupt request
.ps2_kbd_clk_ (ps2_kclk_),
.ps2_kbd_dat_ (ps2_kdat_),
.ps2_mse_clk_ (ps2_mclk_),
.ps2_mse_dat_ (ps2_mdat_)
);
speaker speaker (
.clk (clk),
.rst (rst),
.wb_dat_i (keyb_dat_i[15:8]),
.wb_dat_o (aud_dat_o),
.wb_we_i (keyb_we_i),
.wb_stb_i (keyb_stb_i),
.wb_cyc_i (aud_cyc_i),
.wb_ack_o (aud_ack_o),
.timer2 (timer2_o),
.speaker_ (chassis_spk_)
);
// Selection logic between keyboard and audio ports (port 65h: audio)
assign aud_sel_cond = keyb_adr_i[2:1]==2'b00 && keyb_sel_i[1];
assign aud_cyc_i = kaud_cyc_i && aud_sel_cond;
assign keyb_cyc_i = kaud_cyc_i && !aud_sel_cond;
assign kaud_ack_o = aud_cyc_i & aud_ack_o | keyb_cyc_i & keyb_ack_o;
assign kaud_dat_o = {8{aud_cyc_i}} & aud_dat_o
| {8{keyb_cyc_i}} & keyb_dat_o[15:8];
timer timer (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (timer_adr_i[1]),
.wb_sel_i (timer_sel_i),
.wb_dat_i (timer_dat_i),
.wb_dat_o (timer_dat_o),
.wb_stb_i (timer_stb_i),
.wb_cyc_i (timer_cyc_i),
.wb_we_i (timer_we_i),
.wb_ack_o (timer_ack_o),
.wb_tgc_o (intv[0]),
.tclk_i (timer_clk), // 1.193182 MHz = (14.31818/12) MHz
.gate2_i (aud_dat_o[0]),
.out2_o (timer2_o)
);
simple_pic pic0 (
.clk (clk),
.rst (rst),
.intv (intv),
.inta (inta),
.intr (intr),
.iid (iid)
);
wb_abrgr sd_brg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (sd_adr_i_s),
.wbs_dat_i (sd_dat_i_s),
.wbs_dat_o (sd_dat_o_s),
.wbs_sel_i (sd_sel_i_s),
.wbs_tga_i (sd_tga_i_s),
.wbs_stb_i (sd_stb_i_s),
.wbs_cyc_i (sd_cyc_i_s),
.wbs_we_i (sd_we_i_s),
.wbs_ack_o (sd_ack_o_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (sd_adr_i),
.wbm_dat_o (sd_dat_i),
.wbm_dat_i ({8'h0,sd_dat_o}),
.wbm_tga_o (sd_tga_i),
.wbm_sel_o (sd_sel_i),
.wbm_stb_o (sd_stb_i),
.wbm_cyc_o (sd_cyc_i),
.wbm_we_o (sd_we_i),
.wbm_ack_i (sd_ack_o)
);
sdspi sdspi (
// Serial pad signal
.sclk (sd_sclk_),
.miso (sd_miso_),
.mosi (sd_mosi_),
.ss (sd_ss_),
// Wishbone slave interface
.wb_clk_i (sdram_clk),
.wb_rst_i (rst),
.wb_dat_i (sd_dat_i[8:0]),
.wb_dat_o (sd_dat_o),
.wb_we_i (sd_we_i),
.wb_sel_i (sd_sel_i),
.wb_stb_i (sd_stb_i),
.wb_cyc_i (sd_cyc_i),
.wb_ack_o (sd_ack_o)
);
// Switches and leds
sw_leds sw_leds (
.wb_clk_i (clk),
.wb_rst_i (rst),
// Wishbone slave interface
.wb_adr_i (gpio_adr_i[1]),
.wb_dat_o (gpio_dat_o),
.wb_dat_i (gpio_dat_i),
.wb_sel_i (gpio_sel_i),
.wb_we_i (gpio_we_i),
.wb_stb_i (gpio_stb_i),
.wb_cyc_i (gpio_cyc_i),
.wb_ack_o (gpio_ack_o),
// GPIO inputs/outputs
.leds_ ({leds_,ledg_[9:4]}),
.sw_ (sw_),
.pb_ (key_),
.tick (intv[0]),
.nmi_pb (nmi_pb) // NMI from pushbutton
);
hex_display hex16 (
.num (pc[19:4]),
.en (1'b1),
.hex0 (hex0_),
.hex1 (hex1_),
.hex2 (hex2_),
.hex3 (hex3_)
);
zet zet (
.pc (pc),
// Wishbone master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.wb_tgc_i (intr),
.wb_tgc_o (inta),
.nmi (nmi),
.nmia (nmia)
);
wb_switch #(
.s0_addr_1 (20'b0_1111_1111_1111_0000_000), // bios boot mem 0xfff00 - 0xfffff
.s0_mask_1 (20'b1_1111_1111_1111_0000_000), // bios boot ROM Memory
.s1_addr_1 (20'b0_1010_0000_0000_0000_000), // mem 0xa0000 - 0xbffff
.s1_mask_1 (20'b1_1110_0000_0000_0000_000), // VGA
.s1_addr_2 (20'b1_0000_0000_0011_1100_000), // io 0x3c0 - 0x3df
.s1_mask_2 (20'b1_0000_1111_1111_1110_000), // VGA IO
.s2_addr_1 (20'b1_0000_0000_0011_1111_100), // io 0x3f8 - 0x3ff
.s2_mask_1 (20'b1_0000_1111_1111_1111_100), // RS232 IO
.s3_addr_1 (20'b1_0000_0000_0000_0110_000), // io 0x60, 0x64
.s3_mask_1 (20'b1_0000_1111_1111_1111_101), // Keyboard / Mouse IO
.s4_addr_1 (20'b1_0000_0000_0001_0000_000), // io 0x100 - 0x101
.s4_mask_1 (20'b1_0000_1111_1111_1111_111), // SD Card IO
.s5_addr_1 (20'b1_0000_1111_0001_0000_000), // io 0xf100 - 0xf103
.s5_mask_1 (20'b1_0000_1111_1111_1111_110), // GPIO
.s6_addr_1 (20'b1_0000_1111_0010_0000_000), // io 0xf200 - 0xf20f
.s6_mask_1 (20'b1_0000_1111_1111_1111_000), // CSR Bridge SDRAM Control
.s7_addr_1 (20'b1_0000_0000_0000_0100_000), // io 0x40 - 0x43
.s7_mask_1 (20'b1_0000_1111_1111_1111_110), // Timer control port
.s8_addr_1 (20'b1_0000_0000_0010_0011_100), // io 0x0238 - 0x023b
.s8_mask_1 (20'b1_0000_1111_1111_1111_110), // Flash IO port
.s9_addr_1 (20'b1_0000_0000_0010_0001_000), // io 0x0210 - 0x021F
.s9_mask_1 (20'b1_0000_1111_1111_1111_000), // Sound Blaster
.sA_addr_1 (20'b1_0000_1111_0011_0000_000), // io 0xf300 - 0xf3ff
.sA_mask_1 (20'b1_0000_1111_1111_0000_000), // SDRAM Control
.sA_addr_2 (20'b0_0000_0000_0000_0000_000), // mem 0x00000 - 0xfffff
.sA_mask_2 (20'b1_0000_0000_0000_0000_000) // Base RAM
) wbs (
// Master interface
.m_dat_i (dat_o),
.m_dat_o (sw_dat_o),
.m_adr_i ({tga,adr}),
.m_sel_i (sel),
.m_we_i (we),
.m_cyc_i (cyc),
.m_stb_i (stb),
.m_ack_o (ack),
// Slave 0 interface - bios rom
.s0_dat_i (rom_dat_o),
.s0_dat_o (rom_dat_i),
.s0_adr_o ({rom_tga_i,rom_adr_i}),
.s0_sel_o (rom_sel_i),
.s0_we_o (rom_we_i),
.s0_cyc_o (rom_cyc_i),
.s0_stb_o (rom_stb_i),
.s0_ack_i (rom_ack_o),
// Slave 1 interface - vga
.s1_dat_i (vga_dat_o_s),
.s1_dat_o (vga_dat_i_s),
.s1_adr_o ({vga_tga_i_s,vga_adr_i_s}),
.s1_sel_o (vga_sel_i_s),
.s1_we_o (vga_we_i_s),
.s1_cyc_o (vga_cyc_i_s),
.s1_stb_o (vga_stb_i_s),
.s1_ack_i (vga_ack_o_s),
// Slave 2 interface - uart
.s2_dat_i (uart_dat_o),
.s2_dat_o (uart_dat_i),
.s2_adr_o ({uart_tga_i,uart_adr_i}),
.s2_sel_o (uart_sel_i),
.s2_we_o (uart_we_i),
.s2_cyc_o (uart_cyc_i),
.s2_stb_o (uart_stb_i),
.s2_ack_i (uart_ack_o),
// Slave 3 interface - keyb
.s3_dat_i ({kaud_dat_o,keyb_dat_o[7:0]}),
.s3_dat_o (keyb_dat_i),
.s3_adr_o ({keyb_tga_i,keyb_adr_i}),
.s3_sel_o (keyb_sel_i),
.s3_we_o (keyb_we_i),
.s3_cyc_o (kaud_cyc_i),
.s3_stb_o (keyb_stb_i),
.s3_ack_i (kaud_ack_o),
// Slave 4 interface - sd
.s4_dat_i (sd_dat_o_s),
.s4_dat_o (sd_dat_i_s),
.s4_adr_o ({sd_tga_i_s,sd_adr_i_s}),
.s4_sel_o (sd_sel_i_s),
.s4_we_o (sd_we_i_s),
.s4_cyc_o (sd_cyc_i_s),
.s4_stb_o (sd_stb_i_s),
.s4_ack_i (sd_ack_o_s),
// Slave 5 interface - gpio
.s5_dat_i (gpio_dat_o),
.s5_dat_o (gpio_dat_i),
.s5_adr_o ({gpio_tga_i,gpio_adr_i}),
.s5_sel_o (gpio_sel_i),
.s5_we_o (gpio_we_i),
.s5_cyc_o (gpio_cyc_i),
.s5_stb_o (gpio_stb_i),
.s5_ack_i (gpio_ack_o),
// Slave 6 interface - csr bridge
.s6_dat_i (csrbrg_dat_r_s),
.s6_dat_o (csrbrg_dat_w_s),
.s6_adr_o ({csrbrg_tga_s,csrbrg_adr_s}),
.s6_sel_o (csrbrg_sel_s),
.s6_we_o (csrbrg_we_s),
.s6_cyc_o (csrbrg_cyc_s),
.s6_stb_o (csrbrg_stb_s),
.s6_ack_i (csrbrg_ack_s),
// Slave 7 interface - timer
.s7_dat_i (timer_dat_o),
.s7_dat_o (timer_dat_i),
.s7_adr_o ({timer_tga_i,timer_adr_i}),
.s7_sel_o (timer_sel_i),
.s7_we_o (timer_we_i),
.s7_cyc_o (timer_cyc_i),
.s7_stb_o (timer_stb_i),
.s7_ack_i (timer_ack_o),
// Slave 8 interface - flash
.s8_dat_i (fl_dat_o),
.s8_dat_o (fl_dat_i),
.s8_adr_o ({fl_tga_i,fl_adr_i}),
.s8_sel_o (fl_sel_i),
.s8_we_o (fl_we_i),
.s8_cyc_o (fl_cyc_i),
.s8_stb_o (fl_stb_i),
.s8_ack_i (fl_ack_o),
// Slave 9 interface - sb16
.s9_dat_i (wb_sb_dat_o),
.s9_dat_o (wb_sb_dat_i),
.s9_adr_o ({wb_sb_tga_i,wb_sb_adr_i}),
.s9_sel_o (wb_sb_sel_i),
.s9_we_o (wb_sb_we_i),
.s9_cyc_o (wb_sb_cyc_i),
.s9_stb_o (wb_sb_stb_i),
.s9_ack_i (wb_sb_ack_o),
// Slave A interface - sdram
.sA_dat_i (fmlbrg_dat_r_s),
.sA_dat_o (fmlbrg_dat_w_s),
.sA_adr_o ({fmlbrg_tga_s,fmlbrg_adr_s}),
.sA_sel_o (fmlbrg_sel_s),
.sA_we_o (fmlbrg_we_s),
.sA_cyc_o (fmlbrg_cyc_s),
.sA_stb_o (fmlbrg_stb_s),
.sA_ack_i (fmlbrg_ack_s),
// Slave B interface - default
.sB_dat_i (16'h0000),
.sB_dat_o (),
.sB_adr_o (),
.sB_sel_o (),
.sB_we_o (),
.sB_cyc_o (def_cyc_i),
.sB_stb_o (def_stb_i),
.sB_ack_i (def_cyc_i & def_stb_i)
);
// Continuous assignments
assign rst_lck = !sw_[0] & lock;
assign nmi = nmi_pb;
assign dat_i = nmia ? 16'h0002 :
(inta ? { 13'b0000_0000_0000_1, iid } :
sw_dat_o);
assign sdram_clk_ = sdram_clk;
assign ledg_[3:0] = pc[3:0];
endmodule
|
`timescale 10ns/100ps
module test_zet;
// Net declarations
wire [15:0] dat_o;
wire [15:0] mem_dat_i, io_dat_i, dat_i;
wire [19:1] adr;
wire we;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack, mem_ack, io_ack;
wire inta;
wire nmia;
wire [19:0] pc;
reg clk;
reg rst;
reg [15:0] io_reg;
reg intr;
// Module instantiations
memory mem0 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (mem_dat_i),
.wb_adr_i (adr),
.wb_we_i (we),
.wb_sel_i (sel),
.wb_stb_i (stb & !tga),
.wb_cyc_i (cyc & !tga),
.wb_ack_o (mem_ack)
);
zet zet (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.wb_tgc_i (1\'b0),
.wb_tgc_o (inta),
.nmi (1\'b0),
.nmia (nmia),
.pc (pc)
);
// Assignments
assign io_dat_i = (adr[15:1]==15\'h5b) ? { io_reg[7:0], 8\'h0 }
: ((adr[15:1]==15\'h5c) ? { 8\'h0, io_reg[15:8] } : 16\'h0);
assign dat_i = inta ? 16\'d3 : (tga ? io_dat_i : mem_dat_i);
assign ack = tga ? io_ack : mem_ack;
assign io_ack = stb;
// Behaviour
// IO Stub
always @(posedge clk)
if (adr[15:1]==15\'h5b && sel[1] && cyc && stb)
io_reg[7:0] <= dat_o[15:8];
else if (adr[15:1]==15\'h5c & sel[0] && cyc && stb)
io_reg[15:8] <= dat_o[7:0];
always #4 clk = ~clk; // 12.5 Mhz
initial
begin
intr <= 1\'b0;
clk <= 1\'b1;
rst <= 1\'b0;
#5 rst <= 1\'b1;
#5 rst <= 1\'b0;
#1000 intr <= 1\'b1;
//@(posedge inta)
@(posedge clk) intr <= 1\'b0;
end
initial
begin
$readmemh("data.rtlrom", mem0.ram, 19\'h78000);
$readmemb("../rtl/micro_rom.dat",
zet.core.micro_data.micro_rom.rom);
end
endmodule
|
`timescale 1ns/10ps
module memory (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o
);
// Registers and nets
reg [15:0] ram[0:2**19-1];
wire we;
wire [7:0] bhw, blw;
// Assignments
assign wb_dat_o = ram[wb_adr_i];
assign wb_ack_o = wb_stb_i;
assign we = wb_we_i & wb_stb_i & wb_cyc_i;
assign bhw = wb_sel_i[1] ? wb_dat_i[15:8]
: ram[wb_adr_i][15:8];
assign blw = wb_sel_i[0] ? wb_dat_i[7:0]
: ram[wb_adr_i][7:0];
// Behaviour
always @(posedge wb_clk_i)
if (we) ram[wb_adr_i] <= { bhw, blw };
endmodule
|
/*
* VGA CSR interface for SRAM
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module csr_sram (
input sys_clk,
// CSR slave interface
input [17:1] csr_adr_i,
input [ 1:0] csr_sel_i,
input csr_we_i,
input [15:0] csr_dat_i,
output reg [15:0] csr_dat_o,
// Pad signals
output [19:0] sram_addr_,
inout [15:0] sram_data_,
output reg sram_we_n_,
output reg sram_oe_n_,
output sram_ce_n_,
output reg [ 1:0] sram_bw_n_
);
// Registers and nets
reg [15:0] ww;
reg [16:0] sram_addr;
// Continuous assingments
assign sram_data_ = sram_we_n_ ? 16'hzzzz : ww;
assign sram_ce_n_ = 1'b0;
assign sram_addr_ = { 3'b0, sram_addr };
// Behaviour
// ww
always @(posedge sys_clk) ww <= csr_dat_i;
// sram_addr
always @(posedge sys_clk) sram_addr <= csr_adr_i;
// sram_we_n_
always @(posedge sys_clk) sram_we_n_ <= !csr_we_i;
// sram_bw_n_
always @(posedge sys_clk) sram_bw_n_ <= ~csr_sel_i;
// sram_oe_n_
always @(posedge sys_clk) sram_oe_n_ <= csr_we_i;
// csr_dat_o
always @(posedge sys_clk) csr_dat_o <= sram_data_;
endmodule
|
/*
* RS-232 asynchronous RX module
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module serial_arx (
input clk,
input rxd,
input baud8tick, // Desired baud rate
output reg [7:0] rxd_data,
output reg rxd_data_ready, // on clock pulse when rxd_data is valid
// We also detect if a gap occurs in the received stream of
// characters whuich can be useful if multiple characters are
// sent in burst so that multiple characters can be treated as a "packet"
output reg rxd_endofpacket, // one clock pulse, when no more data
// is received (rxd_idle is going high)
output rxd_idle // no data is being received
);
reg [1:0] rxd_sync_inv; // we invert rxd, so that the idle becomes "0", to prevent a phantom character to be received at startup
always @(posedge clk) if(baud8tick) rxd_sync_inv <= {rxd_sync_inv[0], ~rxd};
reg [1:0] rxd_cnt_inv;
reg rxd_bit_inv;
always @(posedge clk)
if(baud8tick) begin
if( rxd_sync_inv[1] && rxd_cnt_inv!=2\'b11) rxd_cnt_inv <= rxd_cnt_inv + 2\'h1;
else
if(~rxd_sync_inv[1] && rxd_cnt_inv!=2\'b00) rxd_cnt_inv <= rxd_cnt_inv - 2\'h1;
if(rxd_cnt_inv==2\'b00) rxd_bit_inv <= 1\'b0;
else
if(rxd_cnt_inv==2\'b11) rxd_bit_inv <= 1\'b1;
end
reg [3:0] state;
reg [3:0] bit_spacing;
// "next_bit" controls when the data sampling occurs depending on how noisy the rxd is, different
// values might work better with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4\'d10);
always @(posedge clk)
if(state==0)bit_spacing <= 4\'b0000;
else
if(baud8tick) bit_spacing <= {bit_spacing[2:0] + 4\'b0001} | {bit_spacing[3], 3\'b000};
always @(posedge clk)
if(baud8tick)
case(state)
4\'b0000: if(rxd_bit_inv)state <= 4\'b1000; // start bit found?
4\'b1000: if(next_bit) state <= 4\'b1001; // bit 0
4\'b1001: if(next_bit) state <= 4\'b1010; // bit 1
4\'b1010: if(next_bit) state <= 4\'b1011; // bit 2
4\'b1011: if(next_bit) state <= 4\'b1100; // bit 3
4\'b1100: if(next_bit) state <= 4\'b1101; // bit 4
4\'b1101: if(next_bit) state <= 4\'b1110; // bit 5
4\'b1110: if(next_bit) state <= 4\'b1111; // bit 6
4\'b1111: if(next_bit) state <= 4\'b0001; // bit 7
4\'b0001: if(next_bit) state <= 4\'b0000; // stop bit
default: state <= 4\'b0000;
endcase
always @(posedge clk)
if(baud8tick && next_bit && state[3]) rxd_data <= {~rxd_bit_inv, rxd_data[7:1]};
//reg rxd_data_error;
always @(posedge clk)
begin
rxd_data_ready <= (baud8tick && next_bit && state==4\'b0001 && ~rxd_bit_inv); // ready only if the stop bit is received
//rxd_data_error <= (baud8tick && next_bit && state==4\'b0001 && rxd_bit_inv); // error if the stop bit is not received
end
reg [4:0] gap_count;
always @(posedge clk) if (state!=0) gap_count<=5\'h00; else if(baud8tick & ~gap_count[4]) gap_count <= gap_count + 5\'h01;
assign rxd_idle = gap_count[4];
always @(posedge clk) rxd_endofpacket <= baud8tick & (gap_count==5\'h0F);
endmodule
|
/*
* Read memory interface for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_read_iface (
// Wishbone common signals
input wb_clk_i,
input wb_rst_i,
// Wishbone slave read interface
input [16:1] wbs_adr_i,
input [ 1:0] wbs_sel_i,
output [15:0] wbs_dat_o,
input wbs_stb_i,
output wbs_ack_o,
// Wishbone master read to SRAM
output [17:1] wbm_adr_o,
input [15:0] wbm_dat_i,
output reg wbm_stb_o,
input wbm_ack_i,
// VGA configuration registers
input memory_mapping1,
input read_mode,
input [1:0] read_map_select,
input [3:0] color_compare,
input [3:0] color_dont_care,
output [7:0] latch0,
output [7:0] latch1,
output [7:0] latch2,
output [7:0] latch3
);
// Registers and nets
reg [ 1:0] plane;
reg latch_sel;
reg [15:0] latch [0:3];
wire [15:1] offset;
wire [15:0] dat_o0, dat_o1;
wire [15:0] out_l0, out_l1, out_l2, out_l3;
wire cont;
// Continous assignments
assign latch0 = latch_sel ? latch[0][15:8] : latch[0][7:0];
assign latch1 = latch_sel ? latch[1][15:8] : latch[1][7:0];
assign latch2 = latch_sel ? latch[2][15:8] : latch[2][7:0];
assign latch3 = latch_sel ? latch[3][15:8] : latch[3][7:0];
assign wbm_adr_o = { offset, plane };
assign wbs_ack_o = (plane==2'b11 && wbm_ack_i);
assign offset = memory_mapping1 ? { 1'b0, wbs_adr_i[14:1] }
: wbs_adr_i[15:1];
assign wbs_dat_o = read_mode ? dat_o1 : dat_o0;
assign dat_o0 = (read_map_select==2'b11) ? wbm_dat_i
: latch[read_map_select];
assign dat_o1 = ~(out_l0 | out_l1 | out_l2 | out_l3);
assign out_l0 = (latch[0] ^ { 16{color_compare[0]} })
& { 16{color_dont_care[0]} };
assign out_l1 = (latch[1] ^ { 16{color_compare[1]} })
& { 16{color_dont_care[1]} };
assign out_l2 = (latch[2] ^ { 16{color_compare[2]} })
& { 16{color_dont_care[2]} };
assign out_l3 = (wbm_dat_i ^ { 16{color_compare[3]} })
& { 16{color_dont_care[3]} };
assign cont = wbm_ack_i && wbs_stb_i;
// Behaviour
// latch_sel
always @(posedge wb_clk_i)
latch_sel <= wb_rst_i ? 1'b0
: (wbs_stb_i ? wbs_sel_i[1] : latch_sel);
// wbm_stb_o
always @(posedge wb_clk_i)
wbm_stb_o <= wb_rst_i ? 1'b0 : (wbm_stb_o ? ~wbs_ack_o : wbs_stb_i);
// plane
always @(posedge wb_clk_i)
plane <= wb_rst_i ? 2'b00 : (cont ? (plane + 2'b01) : plane);
// Latch load
always @(posedge wb_clk_i)
if (wb_rst_i)
begin
latch[0] <= 8'h0;
latch[1] <= 8'h0;
latch[2] <= 8'h0;
latch[3] <= 8'h0;
end
else if (wbm_ack_i && wbm_stb_o) latch[plane] <= wbm_dat_i;
endmodule
|
/*\r
* DUT VGA Address Generation\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
//`timescale 1ns/10ps\r
`timescale 1ns/1ps\r
\r
module tb_vga_address;\r
\r
// Registers and nets\r
reg clk_50;\r
reg rst;\r
\r
reg enable_sequencer;\r
reg enable_crtc;\r
\r
// Sequencer input signals\r
\r
reg [9:0] h_count;\r
reg horiz_sync_i;\r
\r
reg [9:0] v_count;\r
reg vert_sync;\r
\r
reg video_on_h_i;\r
reg video_on_v;\r
\r
// CRTC configuration signals\r
\r
reg [5:0] cur_start;\r
reg [5:0] cur_end;\r
reg [4:0] vcursor;\r
reg [6:0] hcursor;\r
\r
reg [6:0] horiz_total;\r
reg [6:0] end_horiz;\r
reg [6:0] st_hor_retr;\r
reg [4:0] end_hor_retr;\r
reg [9:0] vert_total;\r
reg [9:0] end_vert;\r
reg [9:0] st_ver_retr;\r
reg [3:0] end_ver_retr;\r
\r
reg x_dotclockdiv2;\r
\r
// CSR slave interface for reading\r
wire [17:1] csr_adr_o;\r
reg [15:0] csr_dat_i;\r
reg csr_ack;\r
wire csr_stb_o;\r
\r
// FML slave interface for reading\r
wire [17:1] fml_adr_o;\r
reg [15:0] fml_dat_i;\r
wire fml_stb_o;\r
reg fml_ack;\r
wire fml_we = 1\'b0;\r
wire fml_dw = 16\'h1234;\r
\r
wire [3:0] attr_wm;\r
wire [3:0] attr_tm;\r
wire [3:0] fml_attr_tm;\r
wire [7:0] color;\r
\r
wire video_on_h_tm;\r
wire fml_video_on_h_tm;\r
wire video_on_h_wm;\r
wire video_on_h_gm;\r
\r
wire horiz_sync_tm;\r
wire fml_horiz_sync_tm;\r
wire horiz_sync_wm;\r
wire horiz_sync_gm;\r
\r
wire [16:1] csr_tm_adr_o;\r
wire csr_tm_stb_o;\r
wire [16:1] fml_csr_tm_adr_o;\r
wire fml_csr_tm_stb_o;\r
wire [17:1] csr_wm_adr_o;\r
wire csr_wm_stb_o;\r
wire [17:1] csr_gm_adr_o;\r
wire csr_gm_stb_o;\r
\r
wire [9:0] hor_disp_end;\r
wire [9:0] hor_scan_end;\r
wire [9:0] ver_disp_end;\r
wire [9:0] ver_sync_beg;\r
wire [3:0] ver_sync_end;\r
wire [9:0] ver_scan_end;\r
\r
/* Process FML requests */\r
reg [2:0] fml_wcount;\r
reg [2:0] fml_rcount;\r
reg [3:0] fml_pipe;\r
initial begin\r
\t fml_ack = 1\'b0;\r
\t fml_wcount = 0;\r
\t fml_rcount = 0;\r
end\r
\r
always @(posedge clk_50)\r
fml_pipe <= rst ? 4\'b0 : { fml_pipe[2:0], fml_csr_tm_stb_o };\r
\r
always @(posedge clk_50) begin\r
\t if(fml_pipe[1] & (fml_wcount == 0) & (fml_rcount == 0)) begin\r
\t\t fml_ack <= 1\'b1;\r
\t\t if(fml_we) begin\r
\t\t\t //$display("%t FML W addr %x data %x", $time, fml_csr_tm_adr_o, fml_dw);\r
\t\t\t fml_wcount <= 7;\r
\t\t end else begin\r
\t\t\t fml_dat_i = 16\'hbeef;\r
\t\t\t //$display("%t FML R addr %x data %x", $time, fml_csr_tm_adr_o, fml_dat_i);\r
\t\t\t fml_rcount <= 7;\r
\t\t end\r
\t end else\r
\t\t fml_ack <= 1\'b0;\r
\t if(fml_wcount != 0) begin\r
\t\t //#1 $display("%t FML W continuing %x / %d", $time, fml_dw, fml_wcount);\r
\t\t fml_wcount <= fml_wcount - 1;\r
\t end\r
\t if(fml_rcount != 0) begin\r
\t\t fml_dat_i = #1 {13\'h1eba, fml_rcount};\r
\t\t //$display("%t FML R continuing %x / %d", $time, fml_dat_i, fml_rcount);\r
\t\t fml_rcount <= fml_rcount - 1;\r
\t end\r
end\r
\r
/* Process CSR requests */\r
reg [15:0] csr_dat;\r
reg [2:0] csr_rcount;\r
reg [3:0] csr_pipe;\r
initial begin\r
\t csr_ack = 1\'b0;\t \r
\t csr_rcount = 0;\r
end\r
\r
always @(posedge clk_50)\r
csr_pipe <= rst ? 4\'b0 : { csr_pipe[2:0], csr_tm_stb_o };\r
\r
always @(posedge clk_50) begin\r
//if (csr_tm_stb_o)\r
//$display("%t CSR R addr %x", $time, csr_tm_adr_o);\r
if (csr_pipe[1] & (csr_rcount == 0))\r
begin\r
csr_ack <= 1\'b1;\r
\t\t csr_dat_i = 16\'hbeef;\r
\t\t\t //$display("%t CSR R data %x", $time, csr_dat_i);\r
\t\t\t csr_rcount <= 7;\r
\t\t end else\r
\t\t csr_ack <= 1\'b0;\t\t\r
\t if(csr_pipe[1] & (csr_rcount != 0)) begin\r
\t\t csr_dat_i = #1 {13\'h1eba, csr_rcount};\r
\t\t //$display("%t CSR R continuing %x / %d", $time, csr_dat_i, csr_rcount);\r
\t\t csr_rcount <= csr_rcount - 1;\r
\t end\t \r
end\r
\r
// Module instantiations\r
vga_text_mode text_mode (\r
.clk (clk_50),\r
.rst (rst),\r
\r
//.enable (enable_sequencer),\r
\r
// CSR slave interface for reading\r
.csr_adr_o (csr_tm_adr_o),\r
.csr_dat_i (csr_dat_i),\r
.csr_stb_o (csr_tm_stb_o),\r
\r
.h_count (h_count),\r
.v_count (v_count),\r
.horiz_sync_i (horiz_sync_i),\r
.video_on_h_i (video_on_h_i),\r
.video_on_h_o (video_on_h_tm),\r
\r
.cur_start (cur_start),\r
.cur_end (cur_end),\r
.vcursor (vcursor),\r
.hcursor (hcursor),\r
\r
.attr (attr_tm),\r
.horiz_sync_o (horiz_sync_tm)\r
);\r
\r
vga_text_mode_fml text_mode_fml (\r
.clk (clk_50),\r
.rst (rst),\r
\r
.enable (enable_sequencer),\r
\r
// CSR slave interface for reading\r
.fml_adr_o (fml_csr_tm_adr_o),\r
.fml_dat_i (fml_dat_i),\r
.fml_stb_o (fml_csr_tm_stb_o),\r
\r
.h_count (h_count),\r
.v_count (v_count),\r
.horiz_sync_i (horiz_sync_i),\r
.video_on_h_i (video_on_h_i),\r
.video_on_h_o (fml_video_on_h_tm),\r
\r
.cur_start (cur_start),\r
.cur_end (cur_end),\r
.vcursor (vcursor),\r
.hcursor (hcursor),\r
\r
.attr (fml_attr_tm),\r
.horiz_sync_o (fml_horiz_sync_tm)\r
);\r
\r
vga_planar planar (\r
.clk (clk_50),\r
.rst (rst),\r
\r
//.enable (enable_sequencer),\r
\r
// CSR slave interface for reading\r
.csr_adr_o (csr_wm_adr_o),\r
.csr_dat_i (csr_dat_i),\r
.csr_stb_o (csr_wm_stb_o),\r
\r
.attr_plane_enable (4\'hf),\r
.x_dotclockdiv2 (x_dotclockdiv2),\r
\r
.h_count (h_count),\r
.v_count (v_count),\r
.horiz_sync_i (horiz_sync_i),\r
.video_on_h_i (video_on_h_i),\r
.video_on_h_o (video_on_h_wm),\r
\r
.attr (attr_wm),\r
.horiz_sync_o (horiz_sync_wm)\r
);\r
\r
vga_linear linear (\r
.clk (clk_50),\r
.rst (rst),\r
\r
//.enable (enable_sequencer),\r
\r
// CSR slave interface for reading\r
.csr_adr_o (csr_gm_adr_o),\r
.csr_dat_i (csr_dat_i),\r
.csr_stb_o (csr_gm_stb_o),\r
\r
.h_count (h_count),\r
.v_count (v_count),\r
.horiz_sync_i (horiz_sync_i),\r
.video_on_h_i (video_on_h_i),\r
.video_on_h_o (video_on_h_gm),\r
\r
.color (color),\r
.horiz_sync_o (horiz_sync_gm)\r
);\r
\r
// Continuous assignments\r
// assign hor_scan_end = { horiz_total[6:2] + 1\'b1, horiz_total[1:0], 3\'h7 };\r
assign hor_scan_end = 10\'d799;\r
\r
// assign hor_disp_end = { end_horiz, 3\'h7 };\r
assign hor_disp_end = 10\'d639;\r
\r
// assign ver_scan_end = vert_total + 10\'d1;\r
assign ver_scan_end = 10\'d448;\r
\r
// assign ver_disp_end = end_vert + 10\'d1;\r
assign ver_disp_end = 10\'d400;\r
\r
assign ver_sync_beg = st_ver_retr;\r
\r
assign ver_sync_end = end_ver_retr + 4\'d1;\r
\r
// Behaviour\r
// Clock generation\r
//always #10 clk_50 <= !clk_50;\r
initial clk_50 = 1\'b0;\r
always #5 clk_50 = ~clk_50;\r
\r
task waitclock;\r
begin\r
\t@(posedge clk_50);\r
\t#1;\r
end\r
endtask\r
\r
task resetpixel;\r
begin\r
h_count = 10\'b0;\r
horiz_sync_i = 1\'b1;\r
v_count = 10\'b0;\r
vert_sync = 1\'b1;\r
video_on_h_i = 1\'b1;\r
video_on_v = 1\'b1;\r
$display("Pixel counter reset to zero");\r
end\r
endtask\r
\r
task nextpixel;\r
begin\r
if (enable_crtc)\r
begin\r
h_count <= (h_count==hor_scan_end) ? 10\'b0 : h_count + 10\'b1;\r
horiz_sync_i <= horiz_sync_i ? (h_count[9:3]!=st_hor_retr)\r
: (h_count[7:3]==end_hor_retr);\r
v_count <= (v_count==ver_scan_end && h_count==hor_scan_end) ? 10\'b0\r
: ((h_count==hor_scan_end) ? v_count + 10\'b1 : v_count);\r
vert_sync <= vert_sync ? (v_count!=ver_sync_beg)\r
: (v_count[3:0]==ver_sync_end);\r
\r
video_on_h_i <= (h_count==hor_scan_end) ? 1\'b1\r
: ((h_count==hor_disp_end) ? 1\'b0 : video_on_h_i);\r
video_on_v <= (v_count==10\'h0) ? 1\'b1\r
: ((v_count==ver_disp_end) ? 1\'b0 : video_on_v);\r
end\r
waitclock;\r
//$display("h_count = %d, v_count = %d", h_count, v_count);\r
end \r
endtask\r
\r
always begin\r
// Initialize to a known state\r
rst = 1\'b1; // reset is active \r
resetpixel; // Reset pixel counter\r
enable_crtc = 1\'b0; // Make sure the crtc is not active\r
enable_sequencer = 1\'b0; // Make sure sequencer is not active\r
\r
waitclock; \r
\r
rst = 1\'b0;\r
\r
enable_crtc = 1\'b1; // Enable crtc\r
enable_sequencer = 1\'b1; // Enable sequencer \r
\r
waitclock;\r
\r
// CRTC configuration signals\r
\r
cur_start = 5\'d0; // reg [5:0] cur_start,\r
cur_end = 5\'d0; // reg [5:0] cur_end,\r
vcursor = 4\'d0; // reg [4:0] vcursor,\r
hcursor = 6\'d0; // reg [6:0] hcursor,\r
\r
horiz_total = 7\'d639; // reg [6:0] horiz_total,\r
end_horiz = 7\'d750; // reg [6:0] end_horiz,\r
// st_hor_retr = 7\'d760; // reg [6:0] st_hor_retr,\r
st_hor_retr = 7\'d656; // reg [6:0] st_hor_retr,\r
// end_hor_retr = 5\'d10; // reg [4:0] end_hor_retr,\r
end_hor_retr = 5\'d752; // reg [4:0] end_hor_retr,\r
vert_total = 10\'d399; // reg [9:0] vert_total,\r
end_vert = 10\'d550; // reg [9:0] end_vert,\r
st_ver_retr = 10\'d560; // reg [9:0] st_ver_retr,\r
end_ver_retr = 4\'d10; // reg [3:0] end_ver_retr,\r
\r
x_dotclockdiv2 = 1\'b0; // reg x_dotclockdiv2\r
\r
//waitclock;\r
\r
// Total number of pixels to check\r
repeat (1000) begin\r
begin\r
if (attr_tm != fml_attr_tm) begin \r
$display("Attributes attr_tm = %x and fml_attr_tm = %x did not match at (h_count = %d and v_count = %d) at time index %t" , attr_tm, fml_attr_tm, h_count, v_count, $time); \r
end\r
if (csr_tm_adr_o != fml_csr_tm_adr_o) begin\r
$display("Address csr_tm_adr_o = %x and fml_csr_tm_adr_o = %x did not match at (h_count = %d and v_count = %d) at time index %t" , csr_tm_adr_o, fml_csr_tm_adr_o, h_count, v_count, $time); \r
end\r
if (video_on_h_tm != fml_video_on_h_tm) begin\r
$display("Video_on_h video_on_h_tm = %x and fml_video_on_h_tm = %x did not match at (h_count = %d and v_count = %d) at time index %t" , csr_tm_adr_o, fml_video_on_h_tm, h_count, v_count, $time);\r
end\r
if (horiz_sync_tm != fml_horiz_sync_tm) begin\r
$display("Horiz_sync horiz_sync_tm = %x and fml_horiz_sync_tm = %x did not match at (h_count = %d and v_count = %d) at time index %t" , horiz_sync_tm, fml_horiz_sync_tm, h_count, v_count, $time);\r
end\r
end\r
nextpixel;\r
end \r
\r
$stop;\r
\r
end \r
\r
endmodule
|
/*
* Microcode ROM for Zet
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
// altera message_off 10030
// get rid of the warning about
// not initializing the ROM
module zet_micro_rom (
input [`MICRO_ADDR_WIDTH-1:0] addr,
output [`MICRO_DATA_WIDTH-1:0] q
);
// Registers, nets and parameters
reg [`MICRO_DATA_WIDTH-1:0] rom[0:2**`MICRO_ADDR_WIDTH-1];
// Assignments
assign q = rom[addr];
// Behaviour
initial $readmemb("micro_rom.dat", rom);
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module seg_7 (
input [3:0] num,
input en,
output reg [6:0] seg
);
// Behaviour
always @(num or en)
if (!en) seg <= 7'h3f;
else
case (num)
4'h0: seg <= {1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
4'h1: seg <= {1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b1};
4'h2: seg <= {1'b0,1'b1,1'b0,1'b0,1'b1,1'b0,1'b0};
4'h3: seg <= {1'b0,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0};
4'h4: seg <= {1'b0,1'b0,1'b1,1'b1,1'b0,1'b0,1'b1};
4'h5: seg <= {1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,1'b0};
4'h6: seg <= {1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0};
4'h7: seg <= {1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0};
4'h8: seg <= {1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
4'h9: seg <= {1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0};
4'ha: seg <= {1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0};
4'hb: seg <= {1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1};
4'hc: seg <= {1'b0,1'b1,1'b0,1'b0,1'b1,1'b1,1'b1};
4'hd: seg <= {1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1};
4'he: seg <= {1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b0};
4'hf: seg <= {1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0};
endcase
endmodule
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "rom_def.v"
`define IR_SIZE 36
`define MEM_OP 31
`define ADD_IP `IR_SIZE\'bx__0__1__0__1__10_001_001__0__01__0__0_1111_xxxx_xxxx_1111_xx
`define OP_NOP 8\'h90
`define OP_HLT 8\'hF4
//`define DEBUG 1
//`define DEBUG_TRACE 1
|
/*
* Fetch FSM helper for next state
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_next_or_not (
input [1:0] prefix,
input [7:1] opcode,
input cx_zero,
input zf,
input ext_int,
output next_in_opco,
output next_in_exec
);
// Net declarations
wire exit_z, cmp_sca, exit_rep, valid_ops;
// Assignments
assign cmp_sca = opcode[2] & opcode[1];
assign exit_z = prefix[0] ? /* repz */ (cmp_sca ? ~zf : 1'b0 )
: /* repnz */ (cmp_sca ? zf : 1'b0 );
assign exit_rep = cx_zero | exit_z;
assign valid_ops = (opcode[7:1]==7'b1010_010 // movs
|| opcode[7:1]==7'b1010_011 // cmps
|| opcode[7:1]==7'b1010_101 // stos
|| opcode[7:1]==7'b1010_110 // lods
|| opcode[7:1]==7'b1010_111); // scas
assign next_in_exec = prefix[1] && valid_ops && !exit_rep && !ext_int;
assign next_in_opco = prefix[1] && valid_ops && cx_zero;
endmodule
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module zet_jmp_cond (
input [4:0] logic_flags,
input [3:0] cond,
input is_cx,
input [15:0] cx,
output reg jmp
);
// Net declarations
wire of, sf, zf, pf, cf;
wire cx_zero;
// Assignments
assign of = logic_flags[4];
assign sf = logic_flags[3];
assign zf = logic_flags[2];
assign pf = logic_flags[1];
assign cf = logic_flags[0];
assign cx_zero = ~(|cx);
// Behaviour
always @(cond or is_cx or cx_zero or zf or of or cf or sf or pf)
if (is_cx) case (cond)
4'b0000: jmp <= cx_zero; /* jcxz */
4'b0001: jmp <= ~cx_zero; /* loop */
4'b0010: jmp <= zf & ~cx_zero; /* loopz */
default: jmp <= ~zf & ~cx_zero; /* loopnz */
endcase
else case (cond)
4'b0000: jmp <= of;
4'b0001: jmp <= ~of;
4'b0010: jmp <= cf;
4'b0011: jmp <= ~cf;
4'b0100: jmp <= zf;
4'b0101: jmp <= ~zf;
4'b0110: jmp <= cf | zf;
4'b0111: jmp <= ~cf & ~zf;
4'b1000: jmp <= sf;
4'b1001: jmp <= ~sf;
4'b1010: jmp <= pf;
4'b1011: jmp <= ~pf;
4'b1100: jmp <= (sf ^ of);
4'b1101: jmp <= (sf ^~ of);
4'b1110: jmp <= zf | (sf ^ of);
4'b1111: jmp <= ~zf & (sf ^~ of);
endcase
endmodule
|
/*
* Wishbone Compatible PS2 core
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2 (
// Wishbone slave interface
input wb_clk_i, // Clock Input
input wb_rst_i, // Reset Input
input [15:0] wb_dat_i, // Command to send to mouse
output [15:0] wb_dat_o, // Received data
input wb_cyc_i, // Cycle
input wb_stb_i, // Strobe
input [ 2:1] wb_adr_i, // Wishbone address lines
input [ 1:0] wb_sel_i, // Wishbone Select lines
input wb_we_i, // Write enable
output wb_ack_o, // Normal bus termination
output wb_tgk_o, // Interrupt request
output wb_tgm_o, // Interrupt request
input ps2_kbd_clk_, // PS2 Keyboard Clock, Bidirectional
inout ps2_kbd_dat_, // PS2 Keyboard Data, Bidirectional
inout ps2_mse_clk_, // PS2 Mouse Clock, Bidirectional
inout ps2_mse_dat_ // PS2 Mouse Data, Bidirectional
);
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// This section is a simple WB interface
// --------------------------------------------------------------------
// --------------------------------------------------------------------
wire [7:0] dat_i;
wire [2:0] wb_ps2_addr;
wire wb_ack_i;
wire write_i;
wire read_i;
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// This section is a simple front end for the PS2 Mouse, it is NOT 100%
// 8042 compliant but is hopefully close enough to work for most apps.
// There are two variants in common use, the AT style and the PS2 style
// Interface, this is an implementation of the PS2 style which seems to be
// The most common. Reference: http://www.computer-engineering.org/ps2keyboard/
//
// |7|6|5|4|3|2|1|0| PS2 Status Register
// | | | | | | | `-- PS_IBF - Input Buffer Full-- 0: Empty, No unread input at port, 1: Data available for host to read
// | | | | | | `---- PS_OBF - Output Buffer Full-- 0: Output Buffer Empty, 1: data in buffer being processed
// | | | | | `------ PS_SYS - System flag-- POST read this to determine if power-on reset, 0: in reset, 1: BAT code received - System has already beed initialized
// | | | | `-------- PS_A2 - Address line A2-- Used internally by kbd controller, 0: A2 = 0 - Port 0x60 was last written to, 1: A2 = 1 - Port 0x64 was last written to
// | | | `---------- PS_INH - Inhibit flag-- Indicates if kbd communication is inhibited; 0: Keyboard Clock = 0 - Keyboard is inhibited , 1: Keyboard Clock = 1 - Keyboard is not inhibited
// | | `------------ PS_MOBF - Mouse Output Buffer Full; 0: Output buffer empty, 1: Output buffer full
// | `-------------- PS_TO - General Timout-- Indicates timeout during command write or response. (Same as TxTO + RxTO.)
// `---------------- RX_PERR - Parity Error-- Indicates communication error with keyboard (possibly noisy/loose connection)
//
// |7|6|5|4|3|2|1|0| PS2 Control Byte
// | | | | | | | `-- PS_INT - Input Buffer Full Interrupt-- When set, IRQ 1 is generated when data is available in the input buffer.
// | | | | | | `---- PS_INT2 - Mouse Input Buffer Full Interrupt - When set, IRQ 12 is generated when mouse data is available.
// | | | | | `------ PS_SYSF - System Flag-- Used to manually set/clear SYS flag in Status register.
// | | | | `-------- - No assignment
// | | | `---------- PS_EN - Disable keyboard-- Disables/enables keyboard interface
// | | `------------ PS_EN2 - Disable Mouse-- Disables/enables mouse interface
// | `-------------- PS_XLAT - Translate Scan Codes - Enables/disables translation to set 1 scan codes
// `---------------- - No assignment
//
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Status Register and Wires
// --------------------------------------------------------------------
wire PS_IBF;
wire PS_OBF;
wire PS_SYS;
wire PS_A2;
wire PS_INH;
wire PS_MOBF;
wire PS_TO;
wire RX_PERR;
wire [7:0] PS_STAT;
// --------------------------------------------------------------------
// Control Register and Wires
// --------------------------------------------------------------------
reg [7:0] PS_CNTL; // Control Register
wire PS_INT;
wire PS_INT2;
wire DAT_SEL;
wire DAT_wr;
wire DAT_rd;
wire CMD_SEL;
wire CMD_wr;
wire CMD_rdc;
wire CMD_wrc;
wire CMD_mwr;
wire CMD_tst;
wire CMD_mit;
wire [7:0] dat_o;
wire [7:0] d_dat_o;
wire [7:0] r_dat_o;
wire [7:0] t_dat_o;
wire [7:0] i_dat_o;
wire [7:0] p_dat_o;
wire [7:0] ps_tst_o;
wire [7:0] ps_mit_o;
wire cmd_msnd;
wire IBF;
reg cnt_r_flag; // Read Control lines flag
reg cnt_w_flag; // Write to Control lines flag
reg cmd_w_msnd; // Signal to send to mouse flag
reg cmd_r_test; // Signal to send test flag
reg cmd_r_mint; // Signal to send test flag
reg MSE_INT; // Mouse Receive interrupt signal
wire PS_READ;
wire [7:0] MSE_dat_o; // Receive Register
wire [7:0] MSE_dat_i;
wire MSE_RDY; // Signal data received
wire MSE_DONE; // Signal command finished sending
wire MSE_TOER; // Indicates a Transmit error occured
wire MSE_OVER; // Indicates buffer over run error
wire MSE_SEND;
wire KBD_INT;
wire [7:0] KBD_dat_o;
wire KBD_Txdone;
wire KBD_Rxdone;
// Unused output
wire released;
/*
* We comment this out as they are never read
*
wire PS_SYSF = PS_CNTL[2]; // 0: Power-on value - Tells POST to perform power-on tests/initialization. 1: BAT code received - Tells POST to perform "warm boot" tests/initiailization.
wire PS_EN = PS_CNTL[4]; // 0: Enable - Keyboard interface enabled. 1: Disable - All keyboard communication is disabled.
wire PS_EN2 = PS_CNTL[5]; // 0: Enable - Auxillary PS/2 device interface enabled 1: Disable - Auxillary PS/2 device interface disabled
wire PS_XLAT = PS_CNTL[6]; // 0: Translation disabled - Data appears at input buffer exactly as read from keyboard 1: Translation enabled - Scan codes translated to set 1 before put in input buffer
*/
`define default_cntl 8\'b0100_0111
// --------------------------------------------------------------------
// Behaviour for Command Register
// The PS2 has this funky command byte structure:
//
// - If you write 0x60 to 0x64 port and they next byte you write to port 0x60
// is stored as the command byte (nice and confusing).
//
// - If you write 0x20 to port 0x64, the next byte you read from port
// 0x60 is the command byte read back.
//
// - If you read from 0x64, you get the status
//
// - if you read 0x60, that is either mouse or keyboard data, depending
// on the last command sent
//
// - if you write data to 0x60, either mouse or keyboard data is transmitted
// to either the mouse or keyboard depending on the last command.
//
// Right now, we do not allow sending data to the keyboard, that maybe
// will change later on.
//
// --------------------------------------------------------------------
// Controller Commands:
// ,------------------------ - Currently Supported Command
// |
// 0x20 X Read control lines - Next byte read from 0x60 is control line info
// 0x60 X Write to control lines - Next byte writen to 0x60 is control line info
// 0x90-0x9F _ Write to output port - Writes command\'s lower nibble to lower nibble of output port
// 0xA1 _ Get version number - Returns firmware version number.
// 0xA4 _ Get password - Returns 0xFA if password exists; otherwise, 0xF1.
// 0xA5 _ Set password - Set the new password by sending a null-terminated string of scan codes as this command\'s parameter.
// 0xA6 _ Check password - Compares keyboard input with current password.
// 0xA7 _ Disable mouse interface - PS/2 mode only. Similar to "Disable keyboard interface" (0xAD) command.
// 0xA8 _ Enable mouse interface - PS/2 mode only. Similar to "Enable keyboard interface" (0xAE) command.
// 0xA9 X Mouse interface test - Returns 0x00 if okay, 0x01 if Clock line stuck low, 0x02 if clock line stuck high, 0x03 if data line stuck low, and 0x04 if data line stuck high.
// 0xAA X Controller self-test - Returns 0x55 if okay.
// 0xAB _ Keyboard interface test - Returns 0x00 if okay, 0x01 if Clock line stuck low, 0x02 if clock line stuck high, 0x03 if data line stuck low, and 0x04 if data line stuck high.
// 0xAD _ Disable keybrd interface- Sets bit 4 of command byte and disables all communication with keyboard.
// 0xAE _ Enable keybrd interface - Clears bit 4 of command byte and re-enables communication with keyboard.
// 0xAF _ Get version
// 0xC0 _ Read input port - Returns values on input port (see Input Port definition.)
// 0xC1 _ Copy input port LSn - PS/2 mode only. Copy input port\'s low nibble to Status register (see Input Port definition)
// 0xC2 _ Copy input port MSn - PS/2 mode only. Copy input port\'s high nibble to Status register (see Input Port definition.)
// 0xD0 _ Read output port - Returns values on output port (see Output Port definition.)
// 0xD1 _ Write output port - Write parameter to output port (see Output Port definition.)
// 0xD2 _ Write keyboard buffer - Parameter written to input buffer as if received from keyboard.
// 0xD3 _ Write mouse buffer - Parameter written to input buffer as if received from mouse.
// 0xD4 X Write mouse Device - Sends parameter to the auxillary PS/2 device.
// 0xE0 _ Read test port - Returns values on test port (see Test Port definition.)
// 0xF0-0xFF _ Pulse output port - Pulses command\'s lower nibble onto lower nibble of output port (see Output Port definition.)
// --------------------------------------------------------------------
`define PS2_CMD_A9 8\'hA9 // Mouse Interface test
`define PS2_CMD_AA 8\'hAA // Controller self test
`define PS2_CMD_D4 8\'hD4 // Write to mouse
`define PS2_CNT_RD 8\'h20 // Read command byte
`define PS2_CNT_WR 8\'h60 // Write control byte
`define PS2_DAT_REG 3\'b000 // 0x60 - RW Transmit / Receive register
`define PS2_CMD_REG 3\'b100 // 0x64 - RW - Status / command register
// --------------------------------------------------------------------
// Command Behavior
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Behavior of Control Register
// --------------------------------------------------------------------
always @(posedge wb_clk_i) begin // Synchrounous
if(wb_rst_i) begin
PS_CNTL <= `default_cntl; // Set initial default value
cnt_r_flag <= 1\'b0; // Reset the flag
cnt_w_flag <= 1\'b0; // Reset the flag
cmd_w_msnd <= 1\'b0; // Reset the flag
cmd_r_test <= 1\'b0; // Reset the flag
cmd_r_mint <= 1\'b0; // Reset the flag
end
else
if(CMD_rdc) begin
cnt_r_flag <= 1\'b1; // signal next read from 0x60 is control info
end
else
if(CMD_wrc) begin
cnt_w_flag <= 1\'b1; // signal next write to 0x60 is control info
cmd_w_msnd <= 1\'b0; // Reset the flag
end
else
if(CMD_mwr) begin
cmd_w_msnd <= 1\'b1; // signal next write to 0x60 is mouse info
end
else
if(CMD_tst) begin
cmd_r_test <= 1\'b1; // signal next read from 0x60 is test info
end
else
if(CMD_mit) begin
cmd_r_mint <= 1\'b1; // signal next read from 0x60 is test info
end
else
if(DAT_rd) begin
if(cnt_r_flag) cnt_r_flag <= 1\'b0; // Reset the flag
if(cmd_r_test) cmd_r_test <= 1\'b0; // Reset the flag
if(cmd_r_mint) cmd_r_mint <= 1\'b0; // Reset the flag
end
else
if(DAT_wr) begin
if(cnt_w_flag) begin
PS_CNTL <= dat_i; // User requested to write control info
cnt_w_flag <= 1\'b0; // Reset the flag
end
end
if(cmd_w_msnd && MSE_DONE) cmd_w_msnd <= 1\'b0; // Reset the flag
end // Synchrounous always
// --------------------------------------------------------------------
// Mouse Transceiver Section
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Mouse Receive Interrupt behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) MSE_INT <= 1\'b0; // Default value
else begin
if(MSE_RDY) MSE_INT <= 1\'b1; // Latch interrupt
if(PS_READ) MSE_INT <= 1\'b0; // Clear interrupt
end
end // Synchrounous always
// --------------------------------------------------------------------
// Instantiate the PS2 UART for MOUSE
// --------------------------------------------------------------------
ps2_mouse_nofifo mouse_nofifo (
.clk (wb_clk_i),
.reset (wb_rst_i),
.ps2_clk (ps2_mse_clk_),
.ps2_dat (ps2_mse_dat_),
.writedata (MSE_dat_i), // data to send
.write (MSE_SEND), // signal to send it
.command_was_sent (MSE_DONE), // Done sending
.readdata (MSE_dat_o), // data read
.irq (MSE_RDY), // signal data has arrived and is ready to be read
.inhibit (MSE_INT),
.error_sending_command (MSE_TOER), // Time out error
.buffer_overrun_error (MSE_OVER) // Buffer over run error
);
// --------------------------------------------------------------------
// Keyboard Receiver Section
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Instantiate the PS2 UART for KEYBOARD
// --------------------------------------------------------------------
ps2_keyb #(
.TIMER_60USEC_VALUE_PP (750),
.TIMER_60USEC_BITS_PP (10),
.TIMER_5USEC_VALUE_PP (60),
.TIMER_5USEC_BITS_PP (6)
) keyb (
.clk (wb_clk_i),
.reset (wb_rst_i),
.rx_shifting_done (KBD_Rxdone), // done receivign
.tx_shifting_done (KBD_Txdone), // done transmiting
.scancode (KBD_dat_o), // scancode
.rx_output_strobe (KBD_INT), // Signals a key presseed
.released (released),
.ps2_clk_ (ps2_kbd_clk_), // PS2 PAD signals
.ps2_data_ (ps2_kbd_dat_)
);
// Combinatorial logic
assign dat_i = wb_sel_i[0] ? wb_dat_i[7:0] : wb_dat_i[15:8]; // 8 to 16 bit WB
assign wb_dat_o = wb_sel_i[0] ? {8\'h00, dat_o} : {dat_o, 8\'h00}; // 8 to 16 bit WB
assign wb_ps2_addr = {wb_adr_i, wb_sel_i[1]}; // Compute Address
assign wb_ack_i = wb_stb_i & wb_cyc_i; // Immediate ack
assign wb_ack_o = wb_ack_i;
assign write_i = wb_ack_i & wb_we_i; // WISHBONE write access, Singal to send
assign read_i = wb_ack_i & ~wb_we_i; // WISHBONE write access, Singal to send
assign wb_tgm_o = MSE_INT & PS_INT2; // Mouse Receive interupts ocurred
assign wb_tgk_o = KBD_INT & PS_INT; // Keyboard Receive interupts ocurred
assign PS_IBF = IBF; // 0: Empty, No unread input at port, 1: Full, New input can be read from port 0x60
assign PS_OBF = KBD_Txdone; // 0: Ok to write to port 0x60 1: Full, Don\'t write to port 0x60
assign PS_SYS = 1\'b1; // 1: Always 1 cuz this is fpga so will always be initialized
assign PS_A2 = 1\'b0; // 0: A2 = 0 - Port 0x60 was last written to, 1: A2 = 1 - Port 0x64 was last written to
assign PS_INH = 1\'b1; // 0: Keyboard Clock = 0 - Keyboard is inhibited , 1: Keyboard Clock = 1 - Keyboard is not inhibited
assign PS_MOBF = MSE_DONE; // 0: Buffer empty - Okay to write to auxillary device\'s output buffer, 1: Output buffer full - Don\'t write to port auxillary device\'s output buffer
assign PS_TO = MSE_TOER; // 0: No Error - Keyboard received and responded to last command, 1: Timeout Error - See TxTO and RxTO for more information.
assign RX_PERR = MSE_OVER; // 0: No Error - Odd parity received and proper command response recieved, 1: Parity Error - Even parity received or 0xFE received as command response.
assign PS_STAT = {RX_PERR, PS_TO, PS_MOBF, PS_INH, PS_A2, PS_SYS, PS_OBF, PS_IBF}; // Status Register
assign PS_INT = PS_CNTL[0]; // 0: IBF Interrupt Disabled, 1: IBF Interrupt Enabled - Keyboard driver at software int 0x09 handles input.
assign PS_INT2 = PS_CNTL[1]; // 0: Auxillary IBF Interrupt Disabled, 1: Auxillary IBF Interrupt Enabled
assign DAT_SEL = (wb_ps2_addr == `PS2_DAT_REG);
assign DAT_wr = DAT_SEL && write_i;
assign DAT_rd = DAT_SEL && read_i;
assign CMD_SEL = (wb_ps2_addr == `PS2_CMD_REG);
assign CMD_wr = CMD_SEL && write_i;
assign CMD_rdc = CMD_wr && (dat_i == `PS2_CNT_RD); // Request to read control info
assign CMD_wrc = CMD_wr && (dat_i == `PS2_CNT_WR); // Request to write control info
assign CMD_mwr = CMD_wr && (dat_i == `PS2_CMD_D4); // Signal to transmit data to mouse
assign CMD_tst = CMD_wr && (dat_i == `PS2_CMD_AA); // User requested self test
assign CMD_mit = CMD_wr && (dat_i == `PS2_CMD_A9); // User mouse interface test
assign dat_o = d_dat_o; // Select register
assign d_dat_o = DAT_SEL ? r_dat_o : PS_STAT; // Select register
assign r_dat_o = cnt_r_flag ? PS_CNTL : t_dat_o; // return control or data
assign t_dat_o = cmd_r_test ? ps_tst_o : i_dat_o; // return control or data
assign i_dat_o = cmd_r_mint ? ps_mit_o : p_dat_o; // return control or data
assign p_dat_o = MSE_INT ? MSE_dat_o : KBD_dat_o; // defer to mouse
assign ps_tst_o = 8\'h55; // Controller self test
assign ps_mit_o = 8\'h00; // Controller self test
assign cmd_msnd = cmd_w_msnd && DAT_wr; // OK to write to mouse
assign IBF = MSE_INT || KBD_INT || cnt_r_flag || cmd_r_test || cmd_r_mint;
assign PS_READ = DAT_rd && !(cnt_r_flag || cmd_r_test || cmd_r_mint);
assign MSE_dat_i = dat_i; // Transmit register
assign MSE_SEND = cmd_msnd; // Signal to transmit data
endmodule
|
/*
* Single channel counter of 8254 timer simplified for Zet SoC
* Copyright (c) 2010 YS <[email protected]>
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
/*
* This module uses:
* - Modes (binary) 2 and 3 only
* Assumptions:
* 1. clkt is asynchronous simple wire (1.193182 MHz by default)
* 2. gate is synchronous (comes from Wishbone controlled register)
* 3. clkrw read/write clock (derived from Wishbone clock) is running
* always and it has much higher frequency than clkt
*/
module timer_counter(
input [1:0] cntnum, // Counter Number constant 0/1/2
input [5:0] cw0, // Initial Control Word constant
input [15:0] cr0, // Initial Constant Register constant
input clkrw, // Read/Write System Clock
input rst, // Reset
input wrc, // Write Command 1 clock pulse
input wrd, // Write Data 1 clock pulse
input rdd, // Read Data full cycle strobe
input [7:0] data_i, // Input Data
output reg [7:0] data_o, // Output Data
input clkt, // Timer Clock (asynchronous to clkrw)
input gate, // Timer Gate (synchronous to clkrw)
output out // Timer Out (synchronous to clkrw)
);
localparam
DATL = 2'd0,
DATH = 2'd1,
STAT = 2'd2;
reg [15:0] rCounter; // Timer Counter
reg [15:0] rConstant; // Constant Register
reg [5:0] rControl; // Control Word Register
reg [15:0] rLatchD; // Output Data Latch
reg [7:0] rLatchS; // Output State Latch
reg bOut;
reg bFn;
reg clcd, clcs; // Latch Data and Latch State command pulses
reg fWroteLow;
reg fWroteHigh;
reg fCount;
reg bCurrentClk;
reg bFilterClk1;
reg bFilterClk2;
reg fLatchData;
reg fLatchStat;
reg rdd1;
reg [1:0] outmux;
reg fToggleHigh;
wire fReadEnd;
wire [2:0] rbc_cnt_mask = data_i[3:1];
wire fMode3 = (rControl[2:1] == 2'b11);
wire fRWLow = rControl[4];
wire fRWHigh = rControl[5];
assign out = bOut;
// Write to Control Word Register
always @(posedge clkrw)
begin
if (rst)
begin
rControl <= cw0;
clcd <= 1'b0;
clcs <= 1'b0;
end
else
begin
if (wrc && data_i[7:6] == cntnum)
begin
if (data_i[5:4] == 2'b00)
clcd <= 1'b1; // CLC
else
rControl <= data_i[5:0]; // WRC
end
else if (wrc && data_i[7:6] == 2'b11 && rbc_cnt_mask[cntnum])
begin
clcd <= ~data_i[5]; // RBC
clcs <= ~data_i[4];
end
if (clcd)
clcd <= 1'b0; // 1 clock pulse clcd
if (clcs)
clcs <= 1'b0; // 1 clock pulse clcs
end
end
// Write to Constant Register
always @(posedge clkrw)
begin
if (rst)
begin
rConstant <= cr0;
fWroteLow <= 1'b0;
fWroteHigh <= 1'b0;
end
else
begin
if (fWroteHigh || wrc)
begin
fWroteLow <= 1'b0;
fWroteHigh <= 1'b0;
end
if (wrd) // need 1 clock pulse wrd!!!
begin
if (!fWroteLow)
begin
if (fRWLow)
rConstant[7:0] <= data_i[7:0];
fWroteLow <= 1'b1;
if (!fRWHigh)
begin
rConstant[15:8] <= 8'b00000000;
fWroteHigh <= 1'b1;
end
end
if (!fWroteHigh && (fWroteLow || !fRWLow))
begin
if (fRWHigh)
rConstant[15:8] <= data_i[7:0];
fWroteHigh <= 1'b1;
if (!fRWLow)
begin
rConstant[7:0] <= 8'b00000000;
fWroteLow <= 1'b1;
end
end
end // if (wrd)
end
end
// Synchronizing Count Clock with Wishbone Clock
always @(posedge clkrw)
begin
if (rst)
begin
fCount <= 1'b0;
bCurrentClk <= 1'b0;
bFilterClk1 <= 1'b0;
bFilterClk2 <= 1'b0;
end
else
begin
bFilterClk1 <= clkt;
bFilterClk2 <= bFilterClk1;
if ((bFilterClk1 == bFilterClk2) && (bCurrentClk != bFilterClk2))
begin
bCurrentClk <= bFilterClk2;
if (bCurrentClk == 1'b1) // falling edge of clkt
fCount <= 1'b1;
end
if (fCount)
fCount <= 1'b0; // 1 clock pulse fCount
end
end
// Timer Counter in mode 2 or mode 3
always @(posedge clkrw)
begin
if (rst)
begin
bOut <= 1'b1;
rCounter <= cr0 & ((cw0[2:1] == 2'b11) ? 16'hFFFE : 16'hFFFF); // (mode==3) ? :
bFn <= 1'b0;
end
else
begin
if (fWroteHigh)
begin
rCounter <= rConstant & ((fMode3) ? 16'hFFFE : 16'hFFFF);
bOut <= 1'b1;
end
else if (fCount && gate) // tclk_i && gate_i
begin
if ((fMode3) ? (bOut == 1'b0 && rCounter == 16'h0002) : (bOut == 1'b0))
begin
rCounter <= rConstant & ((fMode3) ? 16'hFFFE : 16'hFFFF);
bOut <= 1'b1;
end
else if (fMode3 && bOut == 1'b1 && rCounter == ((rConstant[0]) ? 16'h0000 : 16'h0002))
begin
rCounter <= rConstant & 16'hFFFE;
bOut <= 1'b0;
end
else if (!fMode3 && rCounter == 16'h0002)
bOut <= 1'b0;
else
rCounter <= rCounter - ((fMode3) ? 16'h0002 : 16'h0001);
end
end
end
// Output Latch Control
always @(posedge clkrw)
begin
if (rst)
begin
fLatchData <= 1'b0;
fLatchStat <= 1'b0;
rLatchD <= 16'b0;
rLatchS <= 8'b0;
end
else
begin
if (!fLatchData)
rLatchD <= rCounter;
if (!fLatchStat)
rLatchS <= {bOut, bFn, rControl};
if (clcd)
fLatchData <= 1'b1;
if (clcs)
fLatchStat <= 1'b1;
if (fReadEnd)
begin
if (fLatchStat)
fLatchStat <= 1'b0;
else if (fLatchData)
fLatchData <= 1'b0;
end
end
end
// Output Mux
always @(outmux or rLatchS or rLatchD)
begin
case (outmux)
STAT: data_o = rLatchS;
DATH: data_o = rLatchD[15:8];
DATL: data_o = rLatchD[7:0];
endcase
end
assign fReadEnd = !rdd && rdd1; // 1 clock pulse after read
// Read Data/State
always @(posedge clkrw)
begin
if (rst)
begin
rdd1 <= 1'b0;
outmux <= DATL;
fToggleHigh <= 1'b0;
end
else
begin
// Helper for fReadEnd
rdd1 <= rdd;
// Output Mux Control
if (fLatchStat)
outmux <= STAT;
else if ((fRWHigh && !fRWLow) || (fRWHigh && fToggleHigh))
outmux <= DATH;
else
outmux <= DATL;
if (wrc)
fToggleHigh <= 1'b0;
else if (fReadEnd && !fLatchStat)
fToggleHigh <= !fToggleHigh;
end
end
endmodule
|
/*
* Zet SoC top level file for Altera DE2-115 board
* Copyright (C) 2009, 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module kotku (
// Clock input
input clk_50_,
// General purpose IO
input [7:0] sw_,
input key_,
output [6:0] hex0_,
output [6:0] hex1_,
output [6:0] hex2_,
output [6:0] hex3_,
output [9:0] ledr_,
output [7:0] ledg_,
// flash signals
output [22:0] flash_addr_,
input [ 7:0] flash_data_,
output flash_oe_n_,
output flash_ce_n_,
// sdram signals
output [11:0] sdram_addr_,
inout [15:0] sdram_data_,
output [ 1:0] sdram_ba_,
output sdram_ras_n_,
output sdram_cas_n_,
output sdram_ce_,
output sdram_clk_,
output sdram_we_n_,
output sdram_cs_n_,
// VGA signals
output [ 3:0] tft_lcd_r_,
output [ 3:0] tft_lcd_g_,
output [ 3:0] tft_lcd_b_,
output tft_lcd_hsync_,
output tft_lcd_vsync_,
output tft_lcd_clk_,
// UART signals
output uart_txd_,
// PS2 signals
input ps2_kclk_, // PS2 keyboard Clock
inout ps2_kdat_, // PS2 Keyboard Data
inout ps2_mclk_, // PS2 Mouse Clock
inout ps2_mdat_, // PS2 Mouse Data
// SD card signals
output sd_sclk_,
input sd_miso_,
output sd_mosi_,
output sd_ss_,
// I2C for audio codec
inout i2c_sdat_,
output i2c_sclk_,
// Audio codec signals
input aud_daclrck_,
output aud_dacdat_,
input aud_bclk_,
output aud_xck_
);
// Registers and nets
wire clk;
wire rst_lck;
wire [15:0] dat_o;
wire [15:0] dat_i;
wire [19:1] adr;
wire we;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack;
wire lock;
// wires to BIOS ROM
wire [15:0] rom_dat_o;
wire [15:0] rom_dat_i;
wire rom_tga_i;
wire [19:1] rom_adr_i;
wire [ 1:0] rom_sel_i;
wire rom_we_i;
wire rom_cyc_i;
wire rom_stb_i;
wire rom_ack_o;
// wires to flash controller
wire [15:0] fl_dat_o;
wire [15:0] fl_dat_i;
wire fl_tga_i;
wire [19:1] fl_adr_i;
wire [ 1:0] fl_sel_i;
wire fl_we_i;
wire fl_cyc_i;
wire fl_stb_i;
wire fl_ack_o;
// Unused outputs
wire flash_we_n_;
wire flash_rst_n_;
wire [1:0] sdram_dqm_;
wire a12;
wire [2:0] s19_17;
// Unused inputs
wire uart_rxd_;
wire aud_adcdat_;
// wires to vga controller
wire [15:0] vga_dat_o;
wire [15:0] vga_dat_i;
wire vga_tga_i;
wire [19:1] vga_adr_i;
wire [ 1:0] vga_sel_i;
wire vga_we_i;
wire vga_cyc_i;
wire vga_stb_i;
wire vga_ack_o;
// cross clock domain synchronized signals
wire [15:0] vga_dat_o_s;
wire [15:0] vga_dat_i_s;
wire vga_tga_i_s;
wire [19:1] vga_adr_i_s;
wire [ 1:0] vga_sel_i_s;
wire vga_we_i_s;
wire vga_cyc_i_s;
wire vga_stb_i_s;
wire vga_ack_o_s;
// wires to uart controller
wire [15:0] uart_dat_o;
wire [15:0] uart_dat_i;
wire uart_tga_i;
wire [19:1] uart_adr_i;
wire [ 1:0] uart_sel_i;
wire uart_we_i;
wire uart_cyc_i;
wire uart_stb_i;
wire uart_ack_o;
// wires to keyboard controller
wire [15:0] keyb_dat_o;
wire [15:0] keyb_dat_i;
wire keyb_tga_i;
wire [19:1] keyb_adr_i;
wire [ 1:0] keyb_sel_i;
wire keyb_we_i;
wire keyb_cyc_i;
wire keyb_stb_i;
wire keyb_ack_o;
// wires to timer controller
wire [15:0] timer_dat_o;
wire [15:0] timer_dat_i;
wire timer_tga_i;
wire [19:1] timer_adr_i;
wire [ 1:0] timer_sel_i;
wire timer_we_i;
wire timer_cyc_i;
wire timer_stb_i;
wire timer_ack_o;
// wires to sd controller
wire [19:1] sd_adr_i;
wire [ 7:0] sd_dat_o;
wire [15:0] sd_dat_i;
wire sd_tga_i;
wire [ 1:0] sd_sel_i;
wire sd_we_i;
wire sd_cyc_i;
wire sd_stb_i;
wire sd_ack_o;
// wires to sd bridge
wire [19:1] sd_adr_i_s;
wire [15:0] sd_dat_o_s;
wire [15:0] sd_dat_i_s;
wire sd_tga_i_s;
wire [ 1:0] sd_sel_i_s;
wire sd_we_i_s;
wire sd_cyc_i_s;
wire sd_stb_i_s;
wire sd_ack_o_s;
// wires to gpio controller
wire [15:0] gpio_dat_o;
wire [15:0] gpio_dat_i;
wire gpio_tga_i;
wire [19:1] gpio_adr_i;
wire [ 1:0] gpio_sel_i;
wire gpio_we_i;
wire gpio_cyc_i;
wire gpio_stb_i;
wire gpio_ack_o;
// wires to SDRAM controller
wire [19:1] fmlbrg_adr_s;
wire [15:0] fmlbrg_dat_w_s;
wire [15:0] fmlbrg_dat_r_s;
wire [ 1:0] fmlbrg_sel_s;
wire fmlbrg_cyc_s;
wire fmlbrg_stb_s;
wire fmlbrg_tga_s;
wire fmlbrg_we_s;
wire fmlbrg_ack_s;
wire [19:1] fmlbrg_adr;
wire [15:0] fmlbrg_dat_w;
wire [15:0] fmlbrg_dat_r;
wire [ 1:0] fmlbrg_sel;
wire fmlbrg_cyc;
wire fmlbrg_stb;
wire fmlbrg_tga;
wire fmlbrg_we;
wire fmlbrg_ack;
wire [19:1] csrbrg_adr_s;
wire [15:0] csrbrg_dat_w_s;
wire [15:0] csrbrg_dat_r_s;
wire [ 1:0] csrbrg_sel_s;
wire csrbrg_cyc_s;
wire csrbrg_stb_s;
wire csrbrg_tga_s;
wire csrbrg_we_s;
wire csrbrg_ack_s;
wire [19:1] csrbrg_adr;
wire [15:0] csrbrg_dat_w;
wire [15:0] csrbrg_dat_r;
wire [ 1:0] csrbrg_sel;
wire csrbrg_tga;
wire csrbrg_cyc;
wire csrbrg_stb;
wire csrbrg_we;
wire csrbrg_ack;
wire sb_cyc_i;
wire sb_stb_i;
wire [ 2:0] csr_a;
wire csr_we;
wire [15:0] csr_dw;
wire [15:0] csr_dr_hpdmc;
// wires to hpdmc slave interface
wire [25:0] fml_adr;
wire fml_stb;
wire fml_we;
wire fml_ack;
wire [ 1:0] fml_sel;
wire [15:0] fml_di;
wire [15:0] fml_do;
// wires to fml bridge master interface
wire [19:0] fml_fmlbrg_adr;
wire fml_fmlbrg_stb;
wire fml_fmlbrg_we;
wire fml_fmlbrg_ack;
wire [ 1:0] fml_fmlbrg_sel;
wire [15:0] fml_fmlbrg_di;
wire [15:0] fml_fmlbrg_do;
// wires to VGA CPU FML master interface
wire [19:0] vga_cpu_fml_adr; // 1MB Memory Address range
wire vga_cpu_fml_stb;
wire vga_cpu_fml_we;
wire vga_cpu_fml_ack;
wire [1:0] vga_cpu_fml_sel;
wire [15:0] vga_cpu_fml_do;
wire [15:0] vga_cpu_fml_di;
// wires to VGA LCD FML master interface
wire [19:0] vga_lcd_fml_adr; // 1MB Memory Address range
wire vga_lcd_fml_stb;
wire vga_lcd_fml_we;
wire vga_lcd_fml_ack;
wire [1:0] vga_lcd_fml_sel;
wire [15:0] vga_lcd_fml_do;
wire [15:0] vga_lcd_fml_di;
// wires to default stb/ack
wire def_cyc_i;
wire def_stb_i;
wire [15:0] sw_dat_o;
wire sdram_clk;
wire vga_clk;
wire [ 7:0] intv;
wire [ 2:0] iid;
wire intr;
wire inta;
wire nmi_pb;
wire nmi;
wire nmia;
wire [19:0] pc;
reg [16:0] rst_debounce;
wire timer_clk;
wire timer2_o;
// Audio only signals
wire [ 7:0] aud_dat_o;
wire aud_cyc_i;
wire aud_ack_o;
wire aud_sel_cond;
// Keyboard-audio shared signals
wire [ 7:0] kaud_dat_o;
wire kaud_cyc_i;
wire kaud_ack_o;
`ifndef SIMULATION
/*
* Debounce it (counter holds reset for 10.49ms),
* and generate power-on reset.
*/
initial rst_debounce <= 17'h1FFFF;
reg rst;
initial rst <= 1'b1;
always @(posedge clk) begin
if(~rst_lck) /* reset is active low */
rst_debounce <= 17'h1FFFF;
else if(rst_debounce != 17'd0)
rst_debounce <= rst_debounce - 17'd1;
rst <= rst_debounce != 17'd0;
end
`else
wire rst;
assign rst = !rst_lck;
`endif
// Module instantiations
pll pll (
.inclk0 (clk_50_),
.c0 (sdram_clk), // 100 Mhz
.c1 (sdram_clk_), // to SDRAM chip
.c2 (), // 25 Mhz - vga_clk generated inside of vga
.c3 (), // 25 Mhz - tft_lcd_clk_ generated inside of vga
.c4 (clk), // 12.5 Mhz
.locked (lock)
);
clk_gen #(
.res (21),
.phase (21'd100091)
) timerclk (
.clk_i (vga_clk), // 25 MHz
.rst_i (rst),
.clk_o (timer_clk) // 1.193178 MHz (required 1.193182 MHz)
);
clk_gen #(
.res (18),
.phase (18'd29595)
) audioclk (
.clk_i (sdram_clk), // 100 MHz (use highest freq to minimize jitter)
.rst_i (rst),
.clk_o (aud_xck_) // 11.28960 MHz (required 11.28960 MHz)
);
bootrom bootrom (
.clk (clk), // Wishbone slave interface
.rst (rst),
.wb_dat_i (rom_dat_i),
.wb_dat_o (rom_dat_o),
.wb_adr_i (rom_adr_i),
.wb_we_i (rom_we_i ),
.wb_tga_i (rom_tga_i),
.wb_stb_i (rom_stb_i),
.wb_cyc_i (rom_cyc_i),
.wb_sel_i (rom_sel_i),
.wb_ack_o (rom_ack_o)
);
flash8_r2 flash8_r2 (
// Wishbone slave interface
.wb_clk_i (clk), // Main Clock
.wb_rst_i (rst), // Reset Line
.wb_adr_i (fl_adr_i[1]), // Address lines
.wb_sel_i (fl_sel_i), // Select lines
.wb_dat_i (fl_dat_i), // Command to send
.wb_dat_o (fl_dat_o), // Received data
.wb_cyc_i (fl_cyc_i), // Cycle
.wb_stb_i (fl_stb_i), // Strobe
.wb_we_i (fl_we_i), // Write enable
.wb_ack_o (fl_ack_o), // Normal bus termination
// Pad signals
.flash_addr_ (flash_addr_),
.flash_data_ (flash_data_),
.flash_we_n_ (flash_we_n_),
.flash_oe_n_ (flash_oe_n_),
.flash_ce_n_ (flash_ce_n_),
.flash_rst_n_ (flash_rst_n_)
);
wb_abrgr wb_fmlbrg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (fmlbrg_adr_s),
.wbs_dat_i (fmlbrg_dat_w_s),
.wbs_dat_o (fmlbrg_dat_r_s),
.wbs_sel_i (fmlbrg_sel_s),
.wbs_tga_i (fmlbrg_tga_s),
.wbs_stb_i (fmlbrg_stb_s),
.wbs_cyc_i (fmlbrg_cyc_s),
.wbs_we_i (fmlbrg_we_s),
.wbs_ack_o (fmlbrg_ack_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (fmlbrg_adr),
.wbm_dat_o (fmlbrg_dat_w),
.wbm_dat_i (fmlbrg_dat_r),
.wbm_sel_o (fmlbrg_sel),
.wbm_tga_o (fmlbrg_tga),
.wbm_stb_o (fmlbrg_stb),
.wbm_cyc_o (fmlbrg_cyc),
.wbm_we_o (fmlbrg_we),
.wbm_ack_i (fmlbrg_ack)
);
fmlbrg #(
.fml_depth (20), // 8086 can only address 1 MB
.cache_depth (10) // 1 Kbyte cache
) fmlbrg (
.sys_clk (sdram_clk),
.sys_rst (rst),
\t
\t // Wishbone slave interface
.wb_adr_i (fmlbrg_adr),
\t .wb_cti_i(3'b0),
.wb_dat_i (fmlbrg_dat_w),
.wb_dat_o (fmlbrg_dat_r),
.wb_sel_i (fmlbrg_sel),
.wb_cyc_i (fmlbrg_cyc),
.wb_stb_i (fmlbrg_stb),
.wb_tga_i (fmlbrg_tga),
.wb_we_i (fmlbrg_we),
.wb_ack_o (fmlbrg_ack),
// FML master 1 interface
.fml_adr (fml_fmlbrg_adr),
.fml_stb (fml_fmlbrg_stb),
.fml_we (fml_fmlbrg_we),
.fml_ack (fml_fmlbrg_ack),
.fml_sel (fml_fmlbrg_sel),
.fml_do (fml_fmlbrg_do),
.fml_di (fml_fmlbrg_di),
\t
\t // Direct Cache Bus
\t .dcb_stb(1'b0),
\t .dcb_adr(20'b0),
\t .dcb_dat(),
\t .dcb_hit()
\t
);
wb_abrgr wb_csrbrg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (csrbrg_adr_s),
.wbs_dat_i (csrbrg_dat_w_s),
.wbs_dat_o (csrbrg_dat_r_s),
.wbs_sel_i (csrbrg_sel_s),
.wbs_tga_i (csrbrg_tga_s),
.wbs_stb_i (csrbrg_stb_s),
.wbs_cyc_i (csrbrg_cyc_s),
.wbs_we_i (csrbrg_we_s),
.wbs_ack_o (csrbrg_ack_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (csrbrg_adr),
.wbm_dat_o (csrbrg_dat_w),
.wbm_dat_i (csrbrg_dat_r),
.wbm_sel_o (csrbrg_sel),
.wbm_tga_o (csrbrg_tga),
.wbm_stb_o (csrbrg_stb),
.wbm_cyc_o (csrbrg_cyc),
.wbm_we_o (csrbrg_we),
.wbm_ack_i (csrbrg_ack)
);
csrbrg csrbrg (
.sys_clk (sdram_clk),
.sys_rst (rst),
// Wishbone slave interface
.wb_adr_i (csrbrg_adr[3:1]),
.wb_dat_i (csrbrg_dat_w),
.wb_dat_o (csrbrg_dat_r),
.wb_cyc_i (csrbrg_cyc),
.wb_stb_i (csrbrg_stb),
.wb_we_i (csrbrg_we),
.wb_ack_o (csrbrg_ack),
// CSR master interface
.csr_a (csr_a),
.csr_we (csr_we),
.csr_do (csr_dw),
.csr_di (csr_dr_hpdmc)
);
fmlarb #(
.fml_depth (26)
) fmlarb (
.sys_clk (sdram_clk),
\t.sys_rst (rst),
\t
\t// Master 0 interface - VGA LCD FML (Reserved video memory port has highest priority)
\t.m0_adr ({6'b000_001, vga_lcd_fml_adr}), // 1 - 2 MB Addressable memory range
\t.m0_stb (vga_lcd_fml_stb),
\t.m0_we (vga_lcd_fml_we),
\t.m0_ack (vga_lcd_fml_ack),
\t.m0_sel (vga_lcd_fml_sel),
\t.m0_di (vga_lcd_fml_do),
\t.m0_do (vga_lcd_fml_di),
\t\t
\t// Master 1 interface - Wishbone FML bridge
\t.m1_adr ({6'b000_000, fml_fmlbrg_adr}), // 0 - 1 MB Addressable memory range
\t.m1_stb (fml_fmlbrg_stb),
\t.m1_we (fml_fmlbrg_we),
\t.m1_ack (fml_fmlbrg_ack),
\t.m1_sel (fml_fmlbrg_sel),
\t.m1_di (fml_fmlbrg_do),
\t.m1_do (fml_fmlbrg_di),
\t
\t// Master 2 interface - VGA CPU FML
\t.m2_adr ({6'b000_001, vga_cpu_fml_adr}), // 1 - 2 MB Addressable memory range
\t.m2_stb (vga_cpu_fml_stb),
\t.m2_we (vga_cpu_fml_we),
\t.m2_ack (vga_cpu_fml_ack),
\t.m2_sel (vga_cpu_fml_sel),
\t.m2_di (vga_cpu_fml_do),
\t.m2_do (vga_cpu_fml_di),
\t
\t// Master 3 interface - not connected
\t.m3_adr ({6'b000_010, 20'b0}), // 2 - 3 MB Addressable memory range
\t.m3_stb (1'b0),
\t.m3_we (1'b0),
\t.m3_ack (),
\t.m3_sel (2'b00),
\t.m3_di (16'h0000),
\t.m3_do (),
\t
\t// Master 4 interface - not connected
\t.m4_adr ({6'b000_011, 20'b0}), // 3 - 4 MB Addressable memory range
\t.m4_stb (1'b0),
\t.m4_we (1'b0),
\t.m4_ack (),
\t.m4_sel (2'b00),
\t.m4_di (16'h0000),
\t.m4_do (),
\t
\t// Master 5 interface - not connected
\t.m5_adr ({6'b000_100, 20'b0}), // 4 - 5 MB Addressable memory range
\t.m5_stb (1'b0),
\t.m5_we (1'b0),
\t.m5_ack (),
\t.m5_sel (2'b00),
\t.m5_di (16'h0000),
\t.m5_do (),
\t
\t// Arbitrer Slave interface - connected to hpdmc
\t.s_adr (fml_adr),
\t.s_stb (fml_stb),
\t.s_we (fml_we),
\t.s_ack (fml_ack),
\t.s_sel (fml_sel),
\t.s_di (fml_di),
\t.s_do (fml_do)
);
hpdmc #(
.csr_addr (1'b0),
.sdram_depth (26),
.sdram_columndepth (10)
) hpdmc (
.sys_clk (sdram_clk),
.sys_rst (rst),
// CSR slave interface
.csr_a (csr_a),
.csr_we (csr_we),
.csr_di (csr_dw),
.csr_do (csr_dr_hpdmc),
// FML slave interface
.fml_adr (fml_adr),
.fml_stb (fml_stb),
.fml_we (fml_we),
.fml_ack (fml_ack),
.fml_sel (fml_sel),
.fml_di (fml_do),
.fml_do (fml_di),
// SDRAM pad signals
.sdram_cke (sdram_ce_),
.sdram_cs_n (sdram_cs_n_),
.sdram_we_n (sdram_we_n_),
.sdram_cas_n (sdram_cas_n_),
.sdram_ras_n (sdram_ras_n_),
.sdram_dqm (sdram_dqm_),
.sdram_adr ({a12,sdram_addr_}),
.sdram_ba (sdram_ba_),
.sdram_dq (sdram_data_)
);
wb_abrg vga_brg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (vga_adr_i_s),
.wbs_dat_i (vga_dat_i_s),
.wbs_dat_o (vga_dat_o_s),
.wbs_sel_i (vga_sel_i_s),
.wbs_tga_i (vga_tga_i_s),
.wbs_stb_i (vga_stb_i_s),
.wbs_cyc_i (vga_cyc_i_s),
.wbs_we_i (vga_we_i_s),
.wbs_ack_o (vga_ack_o_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (vga_adr_i),
.wbm_dat_o (vga_dat_i),
.wbm_dat_i (vga_dat_o),
.wbm_sel_o (vga_sel_i),
.wbm_tga_o (vga_tga_i),
.wbm_stb_o (vga_stb_i),
.wbm_cyc_o (vga_cyc_i),
.wbm_we_o (vga_we_i),
.wbm_ack_i (vga_ack_o)
);
vga_fml #(
.fml_depth (20) // 1MB Memory Address range
) vga (
.wb_rst_i (rst),
// Wishbone slave interface
.wb_clk_i (sdram_clk), // 100MHz VGA clock
.wb_dat_i (vga_dat_i),
.wb_dat_o (vga_dat_o),
.wb_adr_i (vga_adr_i[16:1]), // 128K
.wb_we_i (vga_we_i),
.wb_tga_i (vga_tga_i),
.wb_sel_i (vga_sel_i),
.wb_stb_i (vga_stb_i),
.wb_cyc_i (vga_cyc_i),
.wb_ack_o (vga_ack_o),
// VGA pad signals
.vga_red_o (tft_lcd_r_),
.vga_green_o (tft_lcd_g_),
.vga_blue_o (tft_lcd_b_),
.horiz_sync (tft_lcd_hsync_),
.vert_sync (tft_lcd_vsync_),
// VGA CPU FML master interface
.vga_cpu_fml_adr(vga_cpu_fml_adr),
.vga_cpu_fml_stb(vga_cpu_fml_stb),
.vga_cpu_fml_we(vga_cpu_fml_we),
.vga_cpu_fml_ack(vga_cpu_fml_ack),
.vga_cpu_fml_sel(vga_cpu_fml_sel),
.vga_cpu_fml_do(vga_cpu_fml_do),
.vga_cpu_fml_di(vga_cpu_fml_di),
// VGA LCD FML master interface
.vga_lcd_fml_adr(vga_lcd_fml_adr),
.vga_lcd_fml_stb(vga_lcd_fml_stb),
.vga_lcd_fml_we(vga_lcd_fml_we),
.vga_lcd_fml_ack(vga_lcd_fml_ack),
.vga_lcd_fml_sel(vga_lcd_fml_sel),
.vga_lcd_fml_do(vga_lcd_fml_do),
.vga_lcd_fml_di(vga_lcd_fml_di),
.vga_clk(vga_clk)
);
// RS232 COM1 Port
serial com1 (
.wb_clk_i (clk), // Main Clock
.wb_rst_i (rst), // Reset Line
.wb_adr_i (uart_adr_i[2:1]), // Address lines
.wb_sel_i (uart_sel_i), // Select lines
.wb_dat_i (uart_dat_i), // Command to send
.wb_dat_o (uart_dat_o),
.wb_we_i (uart_we_i), // Write enable
.wb_stb_i (uart_stb_i),
.wb_cyc_i (uart_cyc_i),
.wb_ack_o (uart_ack_o),
.wb_tgc_o (intv[4]), // Interrupt request
.rs232_tx (uart_txd_), // UART signals
.rs232_rx (uart_rxd_) // serial input/output
);
ps2 ps2 (
.wb_clk_i (clk), // Main Clock
.wb_rst_i (rst), // Reset Line
.wb_adr_i (keyb_adr_i[2:1]), // Address lines
.wb_sel_i (keyb_sel_i), // Select lines
.wb_dat_i (keyb_dat_i), // Command to send to Ethernet
.wb_dat_o (keyb_dat_o),
.wb_we_i (keyb_we_i), // Write enable
.wb_stb_i (keyb_stb_i),
.wb_cyc_i (keyb_cyc_i),
.wb_ack_o (keyb_ack_o),
.wb_tgk_o (intv[1]), // Keyboard Interrupt request
.wb_tgm_o (intv[3]), // Mouse Interrupt request
.ps2_kbd_clk_ (ps2_kclk_),
.ps2_kbd_dat_ (ps2_kdat_),
.ps2_mse_clk_ (ps2_mclk_),
.ps2_mse_dat_ (ps2_mdat_)
);
`ifndef SIMULATION
/*
* Seems that we have a serious bug in Modelsim that prevents
* from simulating when this core is present
*/
speaker speaker (
.clk (clk),
.rst (rst),
.wb_dat_i (keyb_dat_i[15:8]),
.wb_dat_o (aud_dat_o),
.wb_we_i (keyb_we_i),
.wb_stb_i (keyb_stb_i),
.wb_cyc_i (aud_cyc_i),
.wb_ack_o (aud_ack_o),
.clk_100M (sdram_clk),
.clk_25M (vga_clk),
.timer2 (timer2_o),
.i2c_sclk_ (i2c_sclk_),
.i2c_sdat_ (i2c_sdat_),
.aud_adcdat_ (aud_adcdat_),
.aud_daclrck_ (aud_daclrck_),
.aud_dacdat_ (aud_dacdat_),
.aud_bclk_ (aud_bclk_)
);
`else
assign aud_dat_o = 16'h0;
assign aud_ack_o = keyb_stb_i & aud_cyc_i;
`endif
// Selection logic between keyboard and audio ports (port 65h: audio)
assign aud_sel_cond = keyb_adr_i[2:1]==2'b00 && keyb_sel_i[1];
assign aud_cyc_i = kaud_cyc_i && aud_sel_cond;
assign keyb_cyc_i = kaud_cyc_i && !aud_sel_cond;
assign kaud_ack_o = aud_cyc_i & aud_ack_o | keyb_cyc_i & keyb_ack_o;
assign kaud_dat_o = {8{aud_cyc_i}} & aud_dat_o
| {8{keyb_cyc_i}} & keyb_dat_o[15:8];
timer timer (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (timer_adr_i[1]),
.wb_sel_i (timer_sel_i),
.wb_dat_i (timer_dat_i),
.wb_dat_o (timer_dat_o),
.wb_stb_i (timer_stb_i),
.wb_cyc_i (timer_cyc_i),
.wb_we_i (timer_we_i),
.wb_ack_o (timer_ack_o),
.wb_tgc_o (intv[0]),
.tclk_i (timer_clk), // 1.193182 MHz = (14.31818/12) MHz
.gate2_i (aud_dat_o[0]),
.out2_o (timer2_o)
);
simple_pic pic0 (
.clk (clk),
.rst (rst),
.intv (intv),
.inta (inta),
.intr (intr),
.iid (iid)
);
wb_abrgr sd_brg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (sd_adr_i_s),
.wbs_dat_i (sd_dat_i_s),
.wbs_dat_o (sd_dat_o_s),
.wbs_sel_i (sd_sel_i_s),
.wbs_tga_i (sd_tga_i_s),
.wbs_stb_i (sd_stb_i_s),
.wbs_cyc_i (sd_cyc_i_s),
.wbs_we_i (sd_we_i_s),
.wbs_ack_o (sd_ack_o_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (sd_adr_i),
.wbm_dat_o (sd_dat_i),
.wbm_dat_i ({8'h0,sd_dat_o}),
.wbm_tga_o (sd_tga_i),
.wbm_sel_o (sd_sel_i),
.wbm_stb_o (sd_stb_i),
.wbm_cyc_o (sd_cyc_i),
.wbm_we_o (sd_we_i),
.wbm_ack_i (sd_ack_o)
);
sdspi sdspi (
// Serial pad signal
.sclk (sd_sclk_),
.miso (sd_miso_),
.mosi (sd_mosi_),
.ss (sd_ss_),
// Wishbone slave interface
.wb_clk_i (sdram_clk),
.wb_rst_i (rst),
.wb_dat_i (sd_dat_i[8:0]),
.wb_dat_o (sd_dat_o),
.wb_we_i (sd_we_i),
.wb_sel_i (sd_sel_i),
.wb_stb_i (sd_stb_i),
.wb_cyc_i (sd_cyc_i),
.wb_ack_o (sd_ack_o)
);
// Switches and leds
sw_leds sw_leds (
.wb_clk_i (clk),
.wb_rst_i (rst),
// Wishbone slave interface
.wb_adr_i (gpio_adr_i[1]),
.wb_dat_o (gpio_dat_o),
.wb_dat_i (gpio_dat_i),
.wb_sel_i (gpio_sel_i),
.wb_we_i (gpio_we_i),
.wb_stb_i (gpio_stb_i),
.wb_cyc_i (gpio_cyc_i),
.wb_ack_o (gpio_ack_o),
// GPIO inputs/outputs
.leds_ ({ledr_,ledg_[7:4]}),
.sw_ (sw_),
.pb_ (key_),
.tick (intv[0]),
.nmi_pb (nmi_pb) // NMI from pushbutton
);
hex_display hex16 (
.num (pc[19:4]),
.en (1'b1),
.hex0 (hex0_),
.hex1 (hex1_),
.hex2 (hex2_),
.hex3 (hex3_)
);
zet zet (
.pc (pc),
// Wishbone master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.wb_tgc_i (intr),
.wb_tgc_o (inta),
.nmi (nmi),
.nmia (nmia)
);
wb_switch #(
.s0_addr_1 (20'b0_1111_1111_1111_0000_000), // bios boot mem 0xfff00 - 0xfffff
.s0_mask_1 (20'b1_1111_1111_1111_0000_000), // bios boot ROM Memory
.s1_addr_1 (20'b0_1010_0000_0000_0000_000), // mem 0xa0000 - 0xbffff
.s1_mask_1 (20'b1_1110_0000_0000_0000_000), // VGA
.s1_addr_2 (20'b1_0000_0000_0011_1100_000), // io 0x3c0 - 0x3df
.s1_mask_2 (20'b1_0000_1111_1111_1110_000), // VGA IO
.s2_addr_1 (20'b1_0000_0000_0011_1111_100), // io 0x3f8 - 0x3ff
.s2_mask_1 (20'b1_0000_1111_1111_1111_100), // RS232 IO
.s3_addr_1 (20'b1_0000_0000_0000_0110_000), // io 0x60, 0x64
.s3_mask_1 (20'b1_0000_1111_1111_1111_101), // Keyboard / Mouse IO
.s4_addr_1 (20'b1_0000_0000_0001_0000_000), // io 0x100 - 0x101
.s4_mask_1 (20'b1_0000_1111_1111_1111_111), // SD Card IO
.s5_addr_1 (20'b1_0000_1111_0001_0000_000), // io 0xf100 - 0xf103
.s5_mask_1 (20'b1_0000_1111_1111_1111_110), // GPIO
.s6_addr_1 (20'b1_0000_1111_0010_0000_000), // io 0xf200 - 0xf20f
.s6_mask_1 (20'b1_0000_1111_1111_1111_000), // CSR Bridge SDRAM Control
.s7_addr_1 (20'b1_0000_0000_0000_0100_000), // io 0x40 - 0x43
.s7_mask_1 (20'b1_0000_1111_1111_1111_110), // Timer control port
.s8_addr_1 (20'b1_0000_0000_0010_0011_100), // io 0x0238 - 0x023b
.s8_mask_1 (20'b1_0000_1111_1111_1111_110), // Flash IO port
.s9_addr_1 (20'b1_0000_0000_0010_0001_000), // io 0x0210 - 0x021F
.s9_mask_1 (20'b1_0000_1111_1111_1111_000), // Sound Blaster
.sA_addr_1 (20'b1_0000_1111_0011_0000_000), // io 0xf300 - 0xf3ff
.sA_mask_1 (20'b1_0000_1111_1111_0000_000), // SDRAM Control
.sA_addr_2 (20'b0_0000_0000_0000_0000_000), // mem 0x00000 - 0xfffff
.sA_mask_2 (20'b1_0000_0000_0000_0000_000) // Base RAM
) wbs (
// Master interface
.m_dat_i (dat_o),
.m_dat_o (sw_dat_o),
.m_adr_i ({tga,adr}),
.m_sel_i (sel),
.m_we_i (we),
.m_cyc_i (cyc),
.m_stb_i (stb),
.m_ack_o (ack),
// Slave 0 interface - bios rom
.s0_dat_i (rom_dat_o),
.s0_dat_o (rom_dat_i),
.s0_adr_o ({rom_tga_i,rom_adr_i}),
.s0_sel_o (rom_sel_i),
.s0_we_o (rom_we_i),
.s0_cyc_o (rom_cyc_i),
.s0_stb_o (rom_stb_i),
.s0_ack_i (rom_ack_o),
// Slave 1 interface - vga
.s1_dat_i (vga_dat_o_s),
.s1_dat_o (vga_dat_i_s),
.s1_adr_o ({vga_tga_i_s,vga_adr_i_s}),
.s1_sel_o (vga_sel_i_s),
.s1_we_o (vga_we_i_s),
.s1_cyc_o (vga_cyc_i_s),
.s1_stb_o (vga_stb_i_s),
.s1_ack_i (vga_ack_o_s),
// Slave 2 interface - uart
.s2_dat_i (uart_dat_o),
.s2_dat_o (uart_dat_i),
.s2_adr_o ({uart_tga_i,uart_adr_i}),
.s2_sel_o (uart_sel_i),
.s2_we_o (uart_we_i),
.s2_cyc_o (uart_cyc_i),
.s2_stb_o (uart_stb_i),
.s2_ack_i (uart_ack_o),
// Slave 3 interface - keyb
.s3_dat_i ({kaud_dat_o,keyb_dat_o[7:0]}),
.s3_dat_o (keyb_dat_i),
.s3_adr_o ({keyb_tga_i,keyb_adr_i}),
.s3_sel_o (keyb_sel_i),
.s3_we_o (keyb_we_i),
.s3_cyc_o (kaud_cyc_i),
.s3_stb_o (keyb_stb_i),
.s3_ack_i (kaud_ack_o),
// Slave 4 interface - sd
.s4_dat_i (sd_dat_o_s),
.s4_dat_o (sd_dat_i_s),
.s4_adr_o ({sd_tga_i_s,sd_adr_i_s}),
.s4_sel_o (sd_sel_i_s),
.s4_we_o (sd_we_i_s),
.s4_cyc_o (sd_cyc_i_s),
.s4_stb_o (sd_stb_i_s),
.s4_ack_i (sd_ack_o_s),
// Slave 5 interface - gpio
.s5_dat_i (gpio_dat_o),
.s5_dat_o (gpio_dat_i),
.s5_adr_o ({gpio_tga_i,gpio_adr_i}),
.s5_sel_o (gpio_sel_i),
.s5_we_o (gpio_we_i),
.s5_cyc_o (gpio_cyc_i),
.s5_stb_o (gpio_stb_i),
.s5_ack_i (gpio_ack_o),
// Slave 6 interface - csr bridge
.s6_dat_i (csrbrg_dat_r_s),
.s6_dat_o (csrbrg_dat_w_s),
.s6_adr_o ({csrbrg_tga_s,csrbrg_adr_s}),
.s6_sel_o (csrbrg_sel_s),
.s6_we_o (csrbrg_we_s),
.s6_cyc_o (csrbrg_cyc_s),
.s6_stb_o (csrbrg_stb_s),
.s6_ack_i (csrbrg_ack_s),
// Slave 7 interface - timer
.s7_dat_i (timer_dat_o),
.s7_dat_o (timer_dat_i),
.s7_adr_o ({timer_tga_i,timer_adr_i}),
.s7_sel_o (timer_sel_i),
.s7_we_o (timer_we_i),
.s7_cyc_o (timer_cyc_i),
.s7_stb_o (timer_stb_i),
.s7_ack_i (timer_ack_o),
// Slave 8 interface - flash
.s8_dat_i (fl_dat_o),
.s8_dat_o (fl_dat_i),
.s8_adr_o ({fl_tga_i,fl_adr_i}),
.s8_sel_o (fl_sel_i),
.s8_we_o (fl_we_i),
.s8_cyc_o (fl_cyc_i),
.s8_stb_o (fl_stb_i),
.s8_ack_i (fl_ack_o),
// Slave 9 interface - not connected
.s9_dat_i (),
.s9_dat_o (),
.s9_adr_o (),
.s9_sel_o (),
.s9_we_o (),
.s9_cyc_o (sb_cyc_i),
.s9_stb_o (sb_stb_i),
.s9_ack_i (sb_cyc_i && sb_stb_i),
// Slave A interface - sdram
.sA_dat_i (fmlbrg_dat_r_s),
.sA_dat_o (fmlbrg_dat_w_s),
.sA_adr_o ({fmlbrg_tga_s,fmlbrg_adr_s}),
.sA_sel_o (fmlbrg_sel_s),
.sA_we_o (fmlbrg_we_s),
.sA_cyc_o (fmlbrg_cyc_s),
.sA_stb_o (fmlbrg_stb_s),
.sA_ack_i (fmlbrg_ack_s),
// Slave B interface - default
.sB_dat_i (16'h0000),
.sB_dat_o (),
.sB_adr_o (),
.sB_sel_o (),
.sB_we_o (),
.sB_cyc_o (def_cyc_i),
.sB_stb_o (def_stb_i),
.sB_ack_i (def_cyc_i & def_stb_i)
);
// Continuous assignments
assign rst_lck = !sw_[0] & lock;
assign nmi = nmi_pb;
assign dat_i = nmia ? 16'h0002 :
(inta ? { 13'b0000_0000_0000_1, iid } :
sw_dat_o);
// Required de2-115 adv7123 vga dac clock
assign tft_lcd_clk_ = vga_clk;
assign ledg_[3:0] = pc[3:0];
endmodule
|
/*
* Configuration interface for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
/*
* 3b4: 0000_0011_1011_0100 crtc_idx (not used in vdu.v)
* 3b5: 0000_0011_1011_0101 CRTC (not used in vdu.v)
* 3c0: 0000_0011_1100_0000 attribute_ctrl
* 3c4: 0000_0011_1100_0100 sequencer.index
* 3c5: 0000_0011_1100_0101 sequencer.seq
* 3c6: 0000_0011_1100_0110 pel.mask
* 3c7: 0000_0011_1100_0111 pel.dac_state
* 3c8: 0000_0011_1100_1000 pel.write_data_register
* 3c9: 0000_0011_1100_1001 pel.data
* 3ce: 0000_0011_1100_1110 graphics_ctrl.index
* 3cf: 0000_0011_1100_1111 graphics_ctrl.data
* 3d4: 0000_0011_1101_0100 crtc_idx
* 3d5: 0000_0011_1101_0101 CRTC
* 3da: 0000_0011_1101_1010 Input Status 1 (color emulation modes)
* 3db: 0000_0011_1101_1011 not used
*/
module vga_config_iface (
// Wishbone slave signals
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
input [ 4:1] wb_adr_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
output wb_ack_o,
// VGA configuration registers
// sequencer
output [3:0] map_mask, // 3c5 (3c4: 2)
output x_dotclockdiv2, // 3c5 (3c4: 1)
output chain_four, // 3c5 (3c4: 4)
// graphics_ctrl
output shift_reg1, // 3cf (3ce: 5)
output graphics_alpha, // 3cf (3ce: 6)
output memory_mapping1, // 3cf (3ce: 6)
output [1:0] write_mode, // 3cf (3ce: 5)
output [1:0] raster_op, // 3cf (3ce: 3)
output read_mode, // 3cf (3ce: 5)
output [7:0] bitmask, // 3cf (3ce: 8)
output [3:0] set_reset, // 3cf (3ce: 0)
output [3:0] enable_set_reset, // 3cf (3ce: 1)
output [1:0] read_map_select, // 3cf (3ce: 4)
output [3:0] color_compare, // 3cf (3ce: 2)
output [3:0] color_dont_care, // 3cf (3ce: 7)
// attribute_ctrl
output reg [3:0] pal_addr,
output pal_we,
input [7:0] pal_read,
output [7:0] pal_write,
// dac_regs
output dac_we,
output reg [1:0] dac_read_data_cycle,
output reg [7:0] dac_read_data_register,
input [3:0] dac_read_data,
output [1:0] dac_write_data_cycle, // word bypass
output [7:0] dac_write_data_register, // word bypass
output [3:0] dac_write_data,
// CRTC
output [ 5:0] cur_start,
output [ 5:0] cur_end,
output [15:0] start_addr,
output [ 4:0] vcursor,
output [ 6:0] hcursor,
output [ 6:0] horiz_total,
output [ 6:0] end_horiz,
output [ 6:0] st_hor_retr,
output [ 4:0] end_hor_retr,
output [ 9:0] vert_total,
output [ 9:0] end_vert,
output [ 9:0] st_ver_retr,
output [ 3:0] end_ver_retr,
input v_retrace,
input vh_retrace
);
// Registers and nets
reg [7:0] graphics_ctrl[0:8];
reg [3:0] graph_idx;
reg [7:0] CRTC[0:23];
reg [7:0] seq[0:4];
reg [4:0] crtc_idx;
reg [3:0] seq_idx;
reg flip_flop;
reg h_pal_addr;
reg ack_delay;
reg [1:0] dac_state;
reg [1:0] write_data_cycle;
reg [7:0] write_data_register;
integer i;
wire [3:0] graph_idx_wr;
wire [4:0] crtc_idx_wr;
wire [3:0] seq_idx_wr;
wire wr_graph;
wire wr_seq;
wire wr_crtc;
wire write;
wire read;
wire [7:0] start_hi;
wire [7:0] start_lo;
wire rst_flip_flop;
wire wr_attr;
wire rd_attr;
wire wr_pal_addr;
wire attr_ctrl_addr;
wire pel_adr_rd;
wire pel_adr_wr;
wire rd_dac;
wire dac_addr;
wire acc_dac;
wire wr_dac;
// Continuous assignments
assign wb_ack_o = (rd_attr | rd_dac) ? ack_delay : wb_stb_i;
assign seq_idx_wr = (wr_seq && wb_sel_i[0]) ? wb_dat_i[3:0] : seq_idx;
assign graph_idx_wr = (wr_graph && wb_sel_i[0]) ? wb_dat_i[3:0] : graph_idx;
assign crtc_idx_wr = (wr_crtc && wb_sel_i[0]) ? wb_dat_i[4:0] : crtc_idx;
assign map_mask = seq[2][3:0];
assign x_dotclockdiv2 = seq[1][3];
assign chain_four = seq[4][3];
assign shift_reg1 = graphics_ctrl[5][6];
assign graphics_alpha = graphics_ctrl[6][0];
assign memory_mapping1 = graphics_ctrl[6][3];
assign write_mode = graphics_ctrl[5][1:0];
assign raster_op = graphics_ctrl[3][4:3];
assign read_mode = graphics_ctrl[5][3];
assign bitmask = graphics_ctrl[8];
assign set_reset = graphics_ctrl[0][3:0];
assign enable_set_reset = graphics_ctrl[1][3:0];
assign read_map_select = graphics_ctrl[4][1:0];
assign color_compare = graphics_ctrl[2][3:0];
assign color_dont_care = graphics_ctrl[7][3:0];
assign cur_start = CRTC[10][5:0];
assign cur_end = CRTC[11][5:0];
assign start_hi = CRTC[12];
assign start_lo = CRTC[13];
assign vcursor = CRTC[14][4:0];
assign hcursor = CRTC[15][6:0];
assign horiz_total = CRTC[0][6:0];
assign end_horiz = CRTC[1][6:0];
assign st_hor_retr = CRTC[4][6:0];
assign end_hor_retr = CRTC[5][4:0];
assign vert_total = { CRTC[7][5], CRTC[7][0], CRTC[6] };
assign end_vert = { CRTC[7][6], CRTC[7][1], CRTC[18] };
assign st_ver_retr = { CRTC[7][7], CRTC[7][2], CRTC[16] };
assign end_ver_retr = CRTC[17][3:0];
assign write = wb_stb_i & wb_we_i;
assign read = wb_stb_i & !wb_we_i;
assign wr_seq = write & (wb_adr_i==4'h2);
assign wr_graph = write & (wb_adr_i==4'h7);
assign wr_crtc = write & (wb_adr_i==4'ha);
assign start_addr = { start_hi, start_lo };
assign attr_ctrl_addr = (wb_adr_i==4'h0);
assign dac_addr = (wb_adr_i==4'h4);
assign rst_flip_flop = read && (wb_adr_i==4'hd) && wb_sel_i[0];
assign wr_attr = write && attr_ctrl_addr && wb_sel_i[0];
assign rd_attr = read && attr_ctrl_addr && wb_sel_i[1];
assign wr_pal_addr = wr_attr && !flip_flop;
assign pel_adr_rd = write && (wb_adr_i==4'h3) && wb_sel_i[1];
assign pel_adr_wr = write && dac_addr && wb_sel_i[0];
assign pal_write = wb_dat_i[7:0];
assign pal_we = wr_attr && flip_flop && !h_pal_addr;
assign acc_dac = dac_addr && wb_sel_i[1];
assign rd_dac = (dac_state==2'b11) && read && acc_dac;
assign wr_dac = write && acc_dac;
assign dac_we = write && (wb_adr_i==4'h4) && wb_sel_i[1];
assign dac_write_data_cycle = wb_sel_i[0] ? 2'b00 : write_data_cycle;
assign dac_write_data = wb_dat_i[13:10];
assign dac_write_data_register = wb_sel_i[0] ? wb_dat_i[7:0]
: write_data_register;
// Behaviour
// write_data_register
always @(posedge wb_clk_i)
write_data_register <= wb_rst_i ? 8'h0
: (pel_adr_wr ? wb_dat_i[7:0]
: (wr_dac && (write_data_cycle==2'b10)) ?
(write_data_register + 8'h01) : write_data_register);
// write_data_cycle
always @(posedge wb_clk_i)
write_data_cycle <= (wb_rst_i | pel_adr_wr) ? 2'b00
: (wr_dac ? (write_data_cycle==2'b10 ? 2'b00
: write_data_cycle + 2'b01) : write_data_cycle);
// dac_read_data_register
always @(posedge wb_clk_i)
dac_read_data_register <= wb_rst_i ? 8'h00
: (pel_adr_rd ? wb_dat_i[15:8]
: (rd_dac && !wb_ack_o && (dac_read_data_cycle==2'b10)) ?
(dac_read_data_register + 8'h01) : dac_read_data_register);
// dac_read_data_cycle
always @(posedge wb_clk_i)
dac_read_data_cycle <= (wb_rst_i | pel_adr_rd) ? 2'b00
: (rd_dac && !wb_ack_o ? (dac_read_data_cycle==2'b10 ? 2'b00
: dac_read_data_cycle + 2'b01) : dac_read_data_cycle);
// dac_state
always @(posedge wb_clk_i)
dac_state <= wb_rst_i ? 2'b01
: (pel_adr_rd ? 2'b11 : (pel_adr_wr ? 2'b00 : dac_state));
// attribute_ctrl.flip_flop
always @(posedge wb_clk_i)
flip_flop <= (wb_rst_i | rst_flip_flop) ? 1'b0
: (wr_attr ? !flip_flop : flip_flop);
// pal_addr
always @(posedge wb_clk_i)
{ h_pal_addr, pal_addr } <= wb_rst_i ? 5'h0
: (wr_pal_addr ? wb_dat_i[4:0] : { h_pal_addr, pal_addr });
// seq_idx
always @(posedge wb_clk_i)
seq_idx <= wb_rst_i ? 4'h0 : seq_idx_wr;
// seq
always @(posedge wb_clk_i)
if (wr_seq & wb_sel_i[1])
seq[seq_idx_wr] <= wb_dat_i[15:8];
// graph_idx
always @(posedge wb_clk_i)
graph_idx <= wb_rst_i ? 4'h0 : graph_idx_wr;
// graphics_ctrl
always @(posedge wb_clk_i)
if (wr_graph & wb_sel_i[1])
graphics_ctrl[graph_idx_wr] <= wb_dat_i[15:8];
// crtc_idx
always @(posedge wb_clk_i)
crtc_idx <= wb_rst_i ? 5'h0 : crtc_idx_wr;
// CRTC
always @(posedge wb_clk_i)
if (wr_crtc & wb_sel_i[1])
CRTC[crtc_idx_wr] <= wb_dat_i[15:8];
// ack_delay
always @(posedge wb_clk_i)
ack_delay <= wb_rst_i ? 1'b0
: ack_delay ? 1'b0 : wb_stb_i;
// wb_dat_o
always @(*)
case (wb_adr_i)
4'h0: wb_dat_o = { pal_read, 3'b001, h_pal_addr, pal_addr };
4'h2: wb_dat_o = { seq[seq_idx], 4'h0, seq_idx };
4'h3: wb_dat_o = { 6'h0, dac_state, 8'hff };
4'h4: wb_dat_o = { 2'b00, dac_read_data, 2'b00, write_data_register };
4'h7: wb_dat_o = { graphics_ctrl[graph_idx], 4'h0, graph_idx };
4'ha: wb_dat_o = { CRTC[crtc_idx], 3'h0, crtc_idx };
4'hd: wb_dat_o = { 12'b0, v_retrace, 2'b0, vh_retrace };
default: wb_dat_o = 16'h0;
endcase
/*
initial
begin
for (i=0;i<=8 ;i=i+1) graphics_ctrl[i] = 8'h0;
for (i=0;i<=15;i=i+1) CRTC[i] = 8'h0;
end
*/
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module test_sdspi (
input clk_50_,
input sw0_,
output reg [7:0] ledg_,
// SD card signals
output sd_sclk_,
input sd_miso_,
output sd_mosi_,
output sd_ss_
);
// Registers and nets
wire clk;
wire sys_clk;
reg [1:0] clk_div;
wire lock;
wire rst;
reg [8:0] dat_i;
wire [7:0] dat_o;
reg we;
reg [1:0] sel;
reg stb;
wire ack;
reg [7:0] st;
reg [7:0] cnt;
// Module instantiations
pll pll (
.inclk0 (clk_50_),
.c2 (sys_clk),
.locked (lock)
);
sdspi sdspi (
// Serial pad signal
.sclk (sd_sclk_),
.miso (sd_miso_),
.mosi (sd_mosi_),
.ss (sd_ss_),
// Wishbone slave interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_we_i (we),
.wb_sel_i (sel),
.wb_stb_i (stb),
.wb_cyc_i (stb),
.wb_ack_o (ack)
);
// Continuous assignments
assign clk = clk_div[1];
assign rst = sw0_ | !lock;
// Behaviour
always @(posedge clk)
if (rst)
begin
dat_i <= 9'h0;
we <= 1'b0;
sel <= 2'b00;
stb <= 1'b0;
st <= 8'h0;
cnt <= 8'd90;
end
else
case (st)
8'h0:
begin
dat_i <= 9'hff;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h1;
end
8'h1:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= (cnt==8'd0) ? 8'h2 : 8'h1;
cnt <= cnt - 8'd1;
end
8'h2:
if (ack) begin
dat_i <= 9'h0ff;
we <= 1'b1;
sel <= 2'b11;
stb <= 1'b1;
st <= 8'h3;
end
8'h3:
if (ack) begin
dat_i <= 9'h40;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h4;
end
8'h4:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h5;
end
8'h5:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h6;
end
8'h6:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h7;
end
8'h7:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h8;
end
8'h8:
if (ack) begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h49;
end
8'h49:
if (ack) begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b0;
st <= 8'h50;
cnt <= 8'd4;
end
8'h50:
begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b0;
st <= (cnt==8'd0) ? 8'h9 : 8'h50;
cnt <= cnt - 8'd1;
end
8'h9:
begin
dat_i <= 9'hff;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h52;
end
8'h52:
if (ack) begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b0;
st <= 8'h53;
cnt <= 8'd7;
end
8'h53:
begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b0;
st <= (cnt==8'd0) ? 8'd10 : 8'h53;
cnt <= cnt - 8'd1;
end
8'd10:
begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd11;
end
8'd11:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd12;
end
8'd12:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd13;
end
8'd13:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd14;
end
8'd14:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd15;
end
endcase
/*
always #5 clk <= !clk;
initial
begin
clk <= 1'b0;
rst <= 1'b1;
miso <= 1'b1;
#100 rst <= 1'b0;
#935 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b1;
end
*/
// clk_div
always @(posedge sys_clk) clk_div <= clk_div + 2'd1;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring signed by unsigned divider ////
//// Uses the non-restoring unsigned by unsigned divider ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_su.v,v 1.2 2002/10/31 13:54:58 rherveille Exp $
//
// $Date: 2002/10/31 13:54:58 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: div_su.v,v $
// Revision 1.2 2002/10/31 13:54:58 rherveille
// Fixed a bug in the remainder output of div_su.v
//
// Revision 1.1.1.1 2002/10/29 20:29:09 rherveille
//
//
//
//synopsys translate_off
`timescale 1ns/10ps
//synopsys translate_on
module zet_div_su (clk, ena, z, d, q, s, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width-1:0] z; // divident
input [d_width-1:0] d; // divisor
output [d_width :0] q; // quotient
output [d_width :0] s; // remainder
output ovf;
reg [d_width:0] q, s;
reg ovf;
//
// variables
//
reg [z_width -1:0] iz;
reg [d_width -1:0] id;
reg [d_width +1:0] szpipe, sdpipe;
wire [d_width -1:0] iq, is;
wire idiv0, iovf;
//
// module body
//
// check d, take abs value
always @(posedge clk)
if (ena)
if (d[d_width-1])
id <= ~d +1'h1;
else
id <= d;
// check z, take abs value
always @(posedge clk)
if (ena)
if (z[z_width-1])
iz <= ~z +1'h1;
else
iz <= z;
// generate szpipe (z sign bit pipe)
integer n;
always @(posedge clk)
if(ena)
begin
szpipe[0] <= z[z_width-1];
for(n=1; n <= d_width+1; n=n+1)
szpipe[n] <= szpipe[n-1];
end
// generate sdpipe (d sign bit pipe)
integer m;
always @(posedge clk)
if(ena)
begin
sdpipe[0] <= d[d_width-1];
for(m=1; m <= d_width+1; m=m+1)
sdpipe[m] <= sdpipe[m-1];
end
// hookup non-restoring divider
zet_div_uu #(z_width, d_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(is),
.div0(idiv0),
.ovf(iovf)
);
// correct divider results if 'd' was negative
always @(posedge clk)
if(ena)
begin
q <= (szpipe[d_width+1]^sdpipe[d_width+1]) ?
((~iq) + 1'h1) : ({1'b0, iq});
s <= (szpipe[d_width+1]) ?
((~is) + 1'h1) : ({1'b0, is});
end
// delay flags same as results
always @(posedge clk)
if(ena)
begin
ovf <= iovf;
end
endmodule
|
/*
* Zet SoC top level file for Altera DE1 board
* Copyright (C) 2009, 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module kotku (
// Clock input
input clk_50_,
// General purpose IO
input [7:0] sw_,
input key_,
output [6:0] hex0_,
output [6:0] hex1_,
output [6:0] hex2_,
output [6:0] hex3_,
output [9:0] ledr_,
output [7:0] ledg_,
// flash signals
output [21:0] flash_addr_,
input [ 7:0] flash_data_,
output flash_oe_n_,
output flash_ce_n_,
// sdram signals
output [11:0] sdram_addr_,
inout [15:0] sdram_data_,
output [ 1:0] sdram_ba_,
output sdram_ras_n_,
output sdram_cas_n_,
output sdram_ce_,
output sdram_clk_,
output sdram_we_n_,
output sdram_cs_n_,
// VGA signals
output [ 3:0] tft_lcd_r_,
output [ 3:0] tft_lcd_g_,
output [ 3:0] tft_lcd_b_,
output tft_lcd_hsync_,
output tft_lcd_vsync_,
// UART signals
output uart_txd_,
// PS2 signals
input ps2_kclk_, // PS2 keyboard Clock
inout ps2_kdat_, // PS2 Keyboard Data
inout ps2_mclk_, // PS2 Mouse Clock
inout ps2_mdat_, // PS2 Mouse Data
// SD card signals
output sd_sclk_,
input sd_miso_,
output sd_mosi_,
output sd_ss_,
// I2C for audio codec
inout i2c_sdat_,
output i2c_sclk_,
// Audio codec signals
input aud_daclrck_,
output aud_dacdat_,
input aud_bclk_,
output aud_xck_
);
// Registers and nets
wire clk;
wire rst_lck;
wire [15:0] dat_o;
wire [15:0] dat_i;
wire [19:1] adr;
wire we;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack;
wire lock;
// wires to BIOS ROM
wire [15:0] rom_dat_o;
wire [15:0] rom_dat_i;
wire rom_tga_i;
wire [19:1] rom_adr_i;
wire [ 1:0] rom_sel_i;
wire rom_we_i;
wire rom_cyc_i;
wire rom_stb_i;
wire rom_ack_o;
// wires to flash controller
wire [15:0] fl_dat_o;
wire [15:0] fl_dat_i;
wire fl_tga_i;
wire [19:1] fl_adr_i;
wire [ 1:0] fl_sel_i;
wire fl_we_i;
wire fl_cyc_i;
wire fl_stb_i;
wire fl_ack_o;
// Unused outputs
wire flash_we_n_;
wire flash_rst_n_;
wire [1:0] sdram_dqm_;
wire [2:0] s19_17;
// Unused inputs
wire uart_rxd_;
wire aud_adcdat_;
// wires to vga controller
wire [15:0] vga_dat_o;
wire [15:0] vga_dat_i;
wire vga_tga_i;
wire [19:1] vga_adr_i;
wire [ 1:0] vga_sel_i;
wire vga_we_i;
wire vga_cyc_i;
wire vga_stb_i;
wire vga_ack_o;
// cross clock domain synchronized signals
wire [15:0] vga_dat_o_s;
wire [15:0] vga_dat_i_s;
wire vga_tga_i_s;
wire [19:1] vga_adr_i_s;
wire [ 1:0] vga_sel_i_s;
wire vga_we_i_s;
wire vga_cyc_i_s;
wire vga_stb_i_s;
wire vga_ack_o_s;
// wires to uart controller
wire [15:0] uart_dat_o;
wire [15:0] uart_dat_i;
wire uart_tga_i;
wire [19:1] uart_adr_i;
wire [ 1:0] uart_sel_i;
wire uart_we_i;
wire uart_cyc_i;
wire uart_stb_i;
wire uart_ack_o;
// wires to keyboard controller
wire [15:0] keyb_dat_o;
wire [15:0] keyb_dat_i;
wire keyb_tga_i;
wire [19:1] keyb_adr_i;
wire [ 1:0] keyb_sel_i;
wire keyb_we_i;
wire keyb_cyc_i;
wire keyb_stb_i;
wire keyb_ack_o;
// wires to timer controller
wire [15:0] timer_dat_o;
wire [15:0] timer_dat_i;
wire timer_tga_i;
wire [19:1] timer_adr_i;
wire [ 1:0] timer_sel_i;
wire timer_we_i;
wire timer_cyc_i;
wire timer_stb_i;
wire timer_ack_o;
// wires to sd controller
wire [19:1] sd_adr_i;
wire [ 7:0] sd_dat_o;
wire [15:0] sd_dat_i;
wire sd_tga_i;
wire [ 1:0] sd_sel_i;
wire sd_we_i;
wire sd_cyc_i;
wire sd_stb_i;
wire sd_ack_o;
// wires to sd bridge
wire [19:1] sd_adr_i_s;
wire [15:0] sd_dat_o_s;
wire [15:0] sd_dat_i_s;
wire sd_tga_i_s;
wire [ 1:0] sd_sel_i_s;
wire sd_we_i_s;
wire sd_cyc_i_s;
wire sd_stb_i_s;
wire sd_ack_o_s;
// wires to gpio controller
wire [15:0] gpio_dat_o;
wire [15:0] gpio_dat_i;
wire gpio_tga_i;
wire [19:1] gpio_adr_i;
wire [ 1:0] gpio_sel_i;
wire gpio_we_i;
wire gpio_cyc_i;
wire gpio_stb_i;
wire gpio_ack_o;
// wires to SDRAM controller
wire [19:1] fmlbrg_adr_s;
wire [15:0] fmlbrg_dat_w_s;
wire [15:0] fmlbrg_dat_r_s;
wire [ 1:0] fmlbrg_sel_s;
wire fmlbrg_cyc_s;
wire fmlbrg_stb_s;
wire fmlbrg_tga_s;
wire fmlbrg_we_s;
wire fmlbrg_ack_s;
wire [19:1] fmlbrg_adr;
wire [15:0] fmlbrg_dat_w;
wire [15:0] fmlbrg_dat_r;
wire [ 1:0] fmlbrg_sel;
wire fmlbrg_cyc;
wire fmlbrg_stb;
wire fmlbrg_tga;
wire fmlbrg_we;
wire fmlbrg_ack;
wire [19:1] csrbrg_adr_s;
wire [15:0] csrbrg_dat_w_s;
wire [15:0] csrbrg_dat_r_s;
wire [ 1:0] csrbrg_sel_s;
wire csrbrg_cyc_s;
wire csrbrg_stb_s;
wire csrbrg_tga_s;
wire csrbrg_we_s;
wire csrbrg_ack_s;
wire [19:1] csrbrg_adr;
wire [15:0] csrbrg_dat_w;
wire [15:0] csrbrg_dat_r;
wire [ 1:0] csrbrg_sel;
wire csrbrg_tga;
wire csrbrg_cyc;
wire csrbrg_stb;
wire csrbrg_we;
wire csrbrg_ack;
wire sb_cyc_i;
wire sb_stb_i;
wire [ 2:0] csr_a;
wire csr_we;
wire [15:0] csr_dw;
wire [15:0] csr_dr_hpdmc;
// wires to hpdmc slave interface
wire [22:0] fml_adr;
wire fml_stb;
wire fml_we;
wire fml_ack;
wire [ 1:0] fml_sel;
wire [15:0] fml_di;
wire [15:0] fml_do;
// wires to fml bridge master interface
wire [19:0] fml_fmlbrg_adr;
wire fml_fmlbrg_stb;
wire fml_fmlbrg_we;
wire fml_fmlbrg_ack;
wire [ 1:0] fml_fmlbrg_sel;
wire [15:0] fml_fmlbrg_di;
wire [15:0] fml_fmlbrg_do;
// wires to VGA CPU FML master interface
wire [19:0] vga_cpu_fml_adr; // 1MB Memory Address range
wire vga_cpu_fml_stb;
wire vga_cpu_fml_we;
wire vga_cpu_fml_ack;
wire [1:0] vga_cpu_fml_sel;
wire [15:0] vga_cpu_fml_do;
wire [15:0] vga_cpu_fml_di;
// wires to VGA LCD FML master interface
wire [19:0] vga_lcd_fml_adr; // 1MB Memory Address range
wire vga_lcd_fml_stb;
wire vga_lcd_fml_we;
wire vga_lcd_fml_ack;
wire [1:0] vga_lcd_fml_sel;
wire [15:0] vga_lcd_fml_do;
wire [15:0] vga_lcd_fml_di;
// wires to default stb/ack
wire def_cyc_i;
wire def_stb_i;
wire [15:0] sw_dat_o;
wire sdram_clk;
wire vga_clk;
wire [ 7:0] intv;
wire [ 2:0] iid;
wire intr;
wire inta;
wire nmi_pb;
wire nmi;
wire nmia;
wire [19:0] pc;
reg [16:0] rst_debounce;
wire timer_clk;
wire timer2_o;
// Audio only signals
wire [ 7:0] aud_dat_o;
wire aud_cyc_i;
wire aud_ack_o;
wire aud_sel_cond;
// Keyboard-audio shared signals
wire [ 7:0] kaud_dat_o;
wire kaud_cyc_i;
wire kaud_ack_o;
`ifndef SIMULATION
/*
* Debounce it (counter holds reset for 10.49ms),
* and generate power-on reset.
*/
initial rst_debounce <= 17'h1FFFF;
reg rst;
initial rst <= 1'b1;
always @(posedge clk) begin
if(~rst_lck) /* reset is active low */
rst_debounce <= 17'h1FFFF;
else if(rst_debounce != 17'd0)
rst_debounce <= rst_debounce - 17'd1;
rst <= rst_debounce != 17'd0;
end
`else
wire rst;
assign rst = !rst_lck;
`endif
// Module instantiations
pll pll (
.inclk0 (clk_50_),
.c0 (sdram_clk), // 100 Mhz
.c1 (), // 25 Mhz
.c2 (clk), // 12.5 Mhz
.locked (lock)
);
clk_gen #(
.res (21),
.phase (21'd100091)
) timerclk (
.clk_i (vga_clk), // 25 MHz
.rst_i (rst),
.clk_o (timer_clk) // 1.193178 MHz (required 1.193182 MHz)
);
clk_gen #(
.res (18),
.phase (18'd29595)
) audioclk (
.clk_i (sdram_clk), // 100 MHz (use highest freq to minimize jitter)
.rst_i (rst),
.clk_o (aud_xck_) // 11.28960 MHz (required 11.28960 MHz)
);
bootrom bootrom (
.clk (clk), // Wishbone slave interface
.rst (rst),
.wb_dat_i (rom_dat_i),
.wb_dat_o (rom_dat_o),
.wb_adr_i (rom_adr_i),
.wb_we_i (rom_we_i ),
.wb_tga_i (rom_tga_i),
.wb_stb_i (rom_stb_i),
.wb_cyc_i (rom_cyc_i),
.wb_sel_i (rom_sel_i),
.wb_ack_o (rom_ack_o)
);
flash8 flash8 (
// Wishbone slave interface
.wb_clk_i (clk), // Main Clock
.wb_rst_i (rst), // Reset Line
.wb_adr_i (fl_adr_i[1]), // Address lines
.wb_sel_i (fl_sel_i), // Select lines
.wb_dat_i (fl_dat_i), // Command to send
.wb_dat_o (fl_dat_o), // Received data
.wb_cyc_i (fl_cyc_i), // Cycle
.wb_stb_i (fl_stb_i), // Strobe
.wb_we_i (fl_we_i), // Write enable
.wb_ack_o (fl_ack_o), // Normal bus termination
// Pad signals
.flash_addr_ (flash_addr_),
.flash_data_ (flash_data_),
.flash_we_n_ (flash_we_n_),
.flash_oe_n_ (flash_oe_n_),
.flash_ce_n_ (flash_ce_n_),
.flash_rst_n_ (flash_rst_n_)
);
wb_abrgr wb_fmlbrg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (fmlbrg_adr_s),
.wbs_dat_i (fmlbrg_dat_w_s),
.wbs_dat_o (fmlbrg_dat_r_s),
.wbs_sel_i (fmlbrg_sel_s),
.wbs_tga_i (fmlbrg_tga_s),
.wbs_stb_i (fmlbrg_stb_s),
.wbs_cyc_i (fmlbrg_cyc_s),
.wbs_we_i (fmlbrg_we_s),
.wbs_ack_o (fmlbrg_ack_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (fmlbrg_adr),
.wbm_dat_o (fmlbrg_dat_w),
.wbm_dat_i (fmlbrg_dat_r),
.wbm_sel_o (fmlbrg_sel),
.wbm_tga_o (fmlbrg_tga),
.wbm_stb_o (fmlbrg_stb),
.wbm_cyc_o (fmlbrg_cyc),
.wbm_we_o (fmlbrg_we),
.wbm_ack_i (fmlbrg_ack)
);
fmlbrg #(
.fml_depth (20), // 8086 can only address 1 MB
.cache_depth (10) // 1 Kbyte cache
) fmlbrg (
.sys_clk (sdram_clk),
.sys_rst (rst),
// Wishbone slave interface
.wb_adr_i (fmlbrg_adr),
.wb_cti_i(3'b0),
.wb_dat_i (fmlbrg_dat_w),
.wb_dat_o (fmlbrg_dat_r),
.wb_sel_i (fmlbrg_sel),
.wb_cyc_i (fmlbrg_cyc),
.wb_stb_i (fmlbrg_stb),
.wb_tga_i (fmlbrg_tga),
.wb_we_i (fmlbrg_we),
.wb_ack_o (fmlbrg_ack),
// FML master 1 interface
.fml_adr (fml_fmlbrg_adr),
.fml_stb (fml_fmlbrg_stb),
.fml_we (fml_fmlbrg_we),
.fml_ack (fml_fmlbrg_ack),
.fml_sel (fml_fmlbrg_sel),
.fml_do (fml_fmlbrg_do),
.fml_di (fml_fmlbrg_di),
// Direct Cache Bus
.dcb_stb(1'b0),
.dcb_adr(20'b0),
.dcb_dat(),
.dcb_hit()
);
wb_abrgr wb_csrbrg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (csrbrg_adr_s),
.wbs_dat_i (csrbrg_dat_w_s),
.wbs_dat_o (csrbrg_dat_r_s),
.wbs_sel_i (csrbrg_sel_s),
.wbs_tga_i (csrbrg_tga_s),
.wbs_stb_i (csrbrg_stb_s),
.wbs_cyc_i (csrbrg_cyc_s),
.wbs_we_i (csrbrg_we_s),
.wbs_ack_o (csrbrg_ack_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (csrbrg_adr),
.wbm_dat_o (csrbrg_dat_w),
.wbm_dat_i (csrbrg_dat_r),
.wbm_sel_o (csrbrg_sel),
.wbm_tga_o (csrbrg_tga),
.wbm_stb_o (csrbrg_stb),
.wbm_cyc_o (csrbrg_cyc),
.wbm_we_o (csrbrg_we),
.wbm_ack_i (csrbrg_ack)
);
csrbrg csrbrg (
.sys_clk (sdram_clk),
.sys_rst (rst),
// Wishbone slave interface
.wb_adr_i (csrbrg_adr[3:1]),
.wb_dat_i (csrbrg_dat_w),
.wb_dat_o (csrbrg_dat_r),
.wb_cyc_i (csrbrg_cyc),
.wb_stb_i (csrbrg_stb),
.wb_we_i (csrbrg_we),
.wb_ack_o (csrbrg_ack),
// CSR master interface
.csr_a (csr_a),
.csr_we (csr_we),
.csr_do (csr_dw),
.csr_di (csr_dr_hpdmc)
);
fmlarb #(
.fml_depth (23)
) fmlarb (
.sys_clk (sdram_clk),
.sys_rst (rst),
// Master 0 interface - VGA LCD FML (Reserved video memory port has highest priority)
.m0_adr ({3'b001, vga_lcd_fml_adr}), // 1 - 2 MB Addressable memory range
.m0_stb (vga_lcd_fml_stb),
.m0_we (vga_lcd_fml_we),
.m0_ack (vga_lcd_fml_ack),
.m0_sel (vga_lcd_fml_sel),
.m0_di (vga_lcd_fml_do),
.m0_do (vga_lcd_fml_di),
// Master 1 interface - Wishbone FML bridge
.m1_adr ({3'b000, fml_fmlbrg_adr}), // 0 - 1 MB Addressable memory range
.m1_stb (fml_fmlbrg_stb),
.m1_we (fml_fmlbrg_we),
.m1_ack (fml_fmlbrg_ack),
.m1_sel (fml_fmlbrg_sel),
.m1_di (fml_fmlbrg_do),
.m1_do (fml_fmlbrg_di),
// Master 2 interface - VGA CPU FML
.m2_adr ({3'b001, vga_cpu_fml_adr}), // 1 - 2 MB Addressable memory range
.m2_stb (vga_cpu_fml_stb),
.m2_we (vga_cpu_fml_we),
.m2_ack (vga_cpu_fml_ack),
.m2_sel (vga_cpu_fml_sel),
.m2_di (vga_cpu_fml_do),
.m2_do (vga_cpu_fml_di),
// Master 3 interface - not connected
.m3_adr ({3'b010, 20'b0}), // 2 - 3 MB Addressable memory range
.m3_stb (1'b0),
.m3_we (1'b0),
.m3_ack (),
.m3_sel (2'b00),
.m3_di (16'h0000),
.m3_do (),
// Master 4 interface - not connected
.m4_adr ({3'b011, 20'b0}), // 3 - 4 MB Addressable memory range
.m4_stb (1'b0),
.m4_we (1'b0),
.m4_ack (),
.m4_sel (2'b00),
.m4_di (16'h0000),
.m4_do (),
// Master 5 interface - not connected
.m5_adr ({3'b100, 20'b0}), // 4 - 5 MB Addressable memory range
.m5_stb (1'b0),
.m5_we (1'b0),
.m5_ack (),
.m5_sel (2'b00),
.m5_di (16'h0000),
.m5_do (),
// Arbitrer Slave interface - connected to hpdmc
.s_adr (fml_adr),
.s_stb (fml_stb),
.s_we (fml_we),
.s_ack (fml_ack),
.s_sel (fml_sel),
.s_di (fml_di),
.s_do (fml_do)
);
hpdmc #(
.csr_addr (1'b0),
.sdram_depth (23),
.sdram_columndepth (8)
) hpdmc (
.sys_clk (sdram_clk),
.sys_rst (rst),
// CSR slave interface
.csr_a (csr_a),
.csr_we (csr_we),
.csr_di (csr_dw),
.csr_do (csr_dr_hpdmc),
// FML slave interface
.fml_adr (fml_adr),
.fml_stb (fml_stb),
.fml_we (fml_we),
.fml_ack (fml_ack),
.fml_sel (fml_sel),
.fml_di (fml_do),
.fml_do (fml_di),
// SDRAM pad signals
.sdram_cke (sdram_ce_),
.sdram_cs_n (sdram_cs_n_),
.sdram_we_n (sdram_we_n_),
.sdram_cas_n (sdram_cas_n_),
.sdram_ras_n (sdram_ras_n_),
.sdram_dqm (sdram_dqm_),
.sdram_adr (sdram_addr_),
.sdram_ba (sdram_ba_),
.sdram_dq (sdram_data_)
);
wb_abrgr vga_brg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (vga_adr_i_s),
.wbs_dat_i (vga_dat_i_s),
.wbs_dat_o (vga_dat_o_s),
.wbs_sel_i (vga_sel_i_s),
.wbs_tga_i (vga_tga_i_s),
.wbs_stb_i (vga_stb_i_s),
.wbs_cyc_i (vga_cyc_i_s),
.wbs_we_i (vga_we_i_s),
.wbs_ack_o (vga_ack_o_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (vga_adr_i),
.wbm_dat_o (vga_dat_i),
.wbm_dat_i (vga_dat_o),
.wbm_sel_o (vga_sel_i),
.wbm_tga_o (vga_tga_i),
.wbm_stb_o (vga_stb_i),
.wbm_cyc_o (vga_cyc_i),
.wbm_we_o (vga_we_i),
.wbm_ack_i (vga_ack_o)
);
vga_fml #(
.fml_depth (20) // 1MB Memory Address range
) vga (
.wb_rst_i (rst),
// Wishbone slave interface
.wb_clk_i (sdram_clk), // 100MHz VGA clock
.wb_dat_i (vga_dat_i),
.wb_dat_o (vga_dat_o),
.wb_adr_i (vga_adr_i[16:1]), // 128K
.wb_we_i (vga_we_i),
.wb_tga_i (vga_tga_i),
.wb_sel_i (vga_sel_i),
.wb_stb_i (vga_stb_i),
.wb_cyc_i (vga_cyc_i),
.wb_ack_o (vga_ack_o),
// VGA pad signals
.vga_red_o (tft_lcd_r_),
.vga_green_o (tft_lcd_g_),
.vga_blue_o (tft_lcd_b_),
.horiz_sync (tft_lcd_hsync_),
.vert_sync (tft_lcd_vsync_),
// VGA CPU FML master interface
.vga_cpu_fml_adr(vga_cpu_fml_adr),
.vga_cpu_fml_stb(vga_cpu_fml_stb),
.vga_cpu_fml_we(vga_cpu_fml_we),
.vga_cpu_fml_ack(vga_cpu_fml_ack),
.vga_cpu_fml_sel(vga_cpu_fml_sel),
.vga_cpu_fml_do(vga_cpu_fml_do),
.vga_cpu_fml_di(vga_cpu_fml_di),
// VGA LCD FML master interface
.vga_lcd_fml_adr(vga_lcd_fml_adr),
.vga_lcd_fml_stb(vga_lcd_fml_stb),
.vga_lcd_fml_we(vga_lcd_fml_we),
.vga_lcd_fml_ack(vga_lcd_fml_ack),
.vga_lcd_fml_sel(vga_lcd_fml_sel),
.vga_lcd_fml_do(vga_lcd_fml_do),
.vga_lcd_fml_di(vga_lcd_fml_di),
.vga_clk(vga_clk)
);
// RS232 COM1 Port
serial com1 (
.wb_clk_i (clk), // Main Clock
.wb_rst_i (rst), // Reset Line
.wb_adr_i (uart_adr_i[2:1]), // Address lines
.wb_sel_i (uart_sel_i), // Select lines
.wb_dat_i (uart_dat_i), // Command to send
.wb_dat_o (uart_dat_o),
.wb_we_i (uart_we_i), // Write enable
.wb_stb_i (uart_stb_i),
.wb_cyc_i (uart_cyc_i),
.wb_ack_o (uart_ack_o),
.wb_tgc_o (intv[4]), // Interrupt request
.rs232_tx (uart_txd_), // UART signals
.rs232_rx (uart_rxd_) // serial input/output
);
ps2 ps2 (
.wb_clk_i (clk), // Main Clock
.wb_rst_i (rst), // Reset Line
.wb_adr_i (keyb_adr_i[2:1]), // Address lines
.wb_sel_i (keyb_sel_i), // Select lines
.wb_dat_i (keyb_dat_i), // Command to send to Ethernet
.wb_dat_o (keyb_dat_o),
.wb_we_i (keyb_we_i), // Write enable
.wb_stb_i (keyb_stb_i),
.wb_cyc_i (keyb_cyc_i),
.wb_ack_o (keyb_ack_o),
.wb_tgk_o (intv[1]), // Keyboard Interrupt request
.wb_tgm_o (intv[3]), // Mouse Interrupt request
.ps2_kbd_clk_ (ps2_kclk_),
.ps2_kbd_dat_ (ps2_kdat_),
.ps2_mse_clk_ (ps2_mclk_),
.ps2_mse_dat_ (ps2_mdat_)
);
`ifndef SIMULATION
/*
* Seems that we have a serious bug in Modelsim that prevents
* from simulating when this core is present
*/
speaker speaker (
.clk (clk),
.rst (rst),
.wb_dat_i (keyb_dat_i[15:8]),
.wb_dat_o (aud_dat_o),
.wb_we_i (keyb_we_i),
.wb_stb_i (keyb_stb_i),
.wb_cyc_i (aud_cyc_i),
.wb_ack_o (aud_ack_o),
.clk_100M (sdram_clk),
.clk_25M (vga_clk),
.timer2 (timer2_o),
.i2c_sclk_ (i2c_sclk_),
.i2c_sdat_ (i2c_sdat_),
.aud_adcdat_ (aud_adcdat_),
.aud_daclrck_ (aud_daclrck_),
.aud_dacdat_ (aud_dacdat_),
.aud_bclk_ (aud_bclk_)
);
`else
assign aud_dat_o = 16'h0;
assign aud_ack_o = keyb_stb_i & aud_cyc_i;
`endif
// Selection logic between keyboard and audio ports (port 65h: audio)
assign aud_sel_cond = keyb_adr_i[2:1]==2'b00 && keyb_sel_i[1];
assign aud_cyc_i = kaud_cyc_i && aud_sel_cond;
assign keyb_cyc_i = kaud_cyc_i && !aud_sel_cond;
assign kaud_ack_o = aud_cyc_i & aud_ack_o | keyb_cyc_i & keyb_ack_o;
assign kaud_dat_o = {8{aud_cyc_i}} & aud_dat_o
| {8{keyb_cyc_i}} & keyb_dat_o[15:8];
timer timer (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (timer_adr_i[1]),
.wb_sel_i (timer_sel_i),
.wb_dat_i (timer_dat_i),
.wb_dat_o (timer_dat_o),
.wb_stb_i (timer_stb_i),
.wb_cyc_i (timer_cyc_i),
.wb_we_i (timer_we_i),
.wb_ack_o (timer_ack_o),
.wb_tgc_o (intv[0]),
.tclk_i (timer_clk), // 1.193182 MHz = (14.31818/12) MHz
.gate2_i (aud_dat_o[0]),
.out2_o (timer2_o)
);
simple_pic pic0 (
.clk (clk),
.rst (rst),
.intv (intv),
.inta (inta),
.intr (intr),
.iid (iid)
);
wb_abrgr sd_brg (
.sys_rst (rst),
// Wishbone slave interface
.wbs_clk_i (clk),
.wbs_adr_i (sd_adr_i_s),
.wbs_dat_i (sd_dat_i_s),
.wbs_dat_o (sd_dat_o_s),
.wbs_sel_i (sd_sel_i_s),
.wbs_tga_i (sd_tga_i_s),
.wbs_stb_i (sd_stb_i_s),
.wbs_cyc_i (sd_cyc_i_s),
.wbs_we_i (sd_we_i_s),
.wbs_ack_o (sd_ack_o_s),
// Wishbone master interface
.wbm_clk_i (sdram_clk),
.wbm_adr_o (sd_adr_i),
.wbm_dat_o (sd_dat_i),
.wbm_dat_i ({8'h0,sd_dat_o}),
.wbm_tga_o (sd_tga_i),
.wbm_sel_o (sd_sel_i),
.wbm_stb_o (sd_stb_i),
.wbm_cyc_o (sd_cyc_i),
.wbm_we_o (sd_we_i),
.wbm_ack_i (sd_ack_o)
);
sdspi sdspi (
// Serial pad signal
.sclk (sd_sclk_),
.miso (sd_miso_),
.mosi (sd_mosi_),
.ss (sd_ss_),
// Wishbone slave interface
.wb_clk_i (sdram_clk),
.wb_rst_i (rst),
.wb_dat_i (sd_dat_i[8:0]),
.wb_dat_o (sd_dat_o),
.wb_we_i (sd_we_i),
.wb_sel_i (sd_sel_i),
.wb_stb_i (sd_stb_i),
.wb_cyc_i (sd_cyc_i),
.wb_ack_o (sd_ack_o)
);
// Switches and leds
sw_leds sw_leds (
.wb_clk_i (clk),
.wb_rst_i (rst),
// Wishbone slave interface
.wb_adr_i (gpio_adr_i[1]),
.wb_dat_o (gpio_dat_o),
.wb_dat_i (gpio_dat_i),
.wb_sel_i (gpio_sel_i),
.wb_we_i (gpio_we_i),
.wb_stb_i (gpio_stb_i),
.wb_cyc_i (gpio_cyc_i),
.wb_ack_o (gpio_ack_o),
// GPIO inputs/outputs
.leds_ ({ledr_,ledg_[7:4]}),
.sw_ (sw_),
.pb_ (key_),
.tick (intv[0]),
.nmi_pb (nmi_pb) // NMI from pushbutton
);
hex_display hex16 (
.num (pc[19:4]),
.en (1'b1),
.hex0 (hex0_),
.hex1 (hex1_),
.hex2 (hex2_),
.hex3 (hex3_)
);
zet zet (
.pc (pc),
// Wishbone master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.wb_tgc_i (intr),
.wb_tgc_o (inta),
.nmi (nmi),
.nmia (nmia)
);
wb_switch #(
.s0_addr_1 (20'b0_1111_1111_1111_0000_000), // bios boot mem 0xfff00 - 0xfffff
.s0_mask_1 (20'b1_1111_1111_1111_0000_000), // bios boot ROM Memory
.s1_addr_1 (20'b0_1010_0000_0000_0000_000), // mem 0xa0000 - 0xbffff
.s1_mask_1 (20'b1_1110_0000_0000_0000_000), // VGA
.s1_addr_2 (20'b1_0000_0000_0011_1100_000), // io 0x3c0 - 0x3df
.s1_mask_2 (20'b1_0000_1111_1111_1110_000), // VGA IO
.s2_addr_1 (20'b1_0000_0000_0011_1111_100), // io 0x3f8 - 0x3ff
.s2_mask_1 (20'b1_0000_1111_1111_1111_100), // RS232 IO
.s3_addr_1 (20'b1_0000_0000_0000_0110_000), // io 0x60, 0x64
.s3_mask_1 (20'b1_0000_1111_1111_1111_101), // Keyboard / Mouse IO
.s4_addr_1 (20'b1_0000_0000_0001_0000_000), // io 0x100 - 0x101
.s4_mask_1 (20'b1_0000_1111_1111_1111_111), // SD Card IO
.s5_addr_1 (20'b1_0000_1111_0001_0000_000), // io 0xf100 - 0xf103
.s5_mask_1 (20'b1_0000_1111_1111_1111_110), // GPIO
.s6_addr_1 (20'b1_0000_1111_0010_0000_000), // io 0xf200 - 0xf20f
.s6_mask_1 (20'b1_0000_1111_1111_1111_000), // CSR Bridge SDRAM Control
.s7_addr_1 (20'b1_0000_0000_0000_0100_000), // io 0x40 - 0x43
.s7_mask_1 (20'b1_0000_1111_1111_1111_110), // Timer control port
.s8_addr_1 (20'b1_0000_0000_0010_0011_100), // io 0x0238 - 0x023b
.s8_mask_1 (20'b1_0000_1111_1111_1111_110), // Flash IO port
.s9_addr_1 (20'b1_0000_0000_0010_0001_000), // io 0x0210 - 0x021F
.s9_mask_1 (20'b1_0000_1111_1111_1111_000), // Sound Blaster
.sA_addr_1 (20'b1_0000_1111_0011_0000_000), // io 0xf300 - 0xf3ff
.sA_mask_1 (20'b1_0000_1111_1111_0000_000), // SDRAM Control
.sA_addr_2 (20'b0_0000_0000_0000_0000_000), // mem 0x00000 - 0xfffff
.sA_mask_2 (20'b1_0000_0000_0000_0000_000) // Base RAM
) wbs (
// Master interface
.m_dat_i (dat_o),
.m_dat_o (sw_dat_o),
.m_adr_i ({tga,adr}),
.m_sel_i (sel),
.m_we_i (we),
.m_cyc_i (cyc),
.m_stb_i (stb),
.m_ack_o (ack),
// Slave 0 interface - bios rom
.s0_dat_i (rom_dat_o),
.s0_dat_o (rom_dat_i),
.s0_adr_o ({rom_tga_i,rom_adr_i}),
.s0_sel_o (rom_sel_i),
.s0_we_o (rom_we_i),
.s0_cyc_o (rom_cyc_i),
.s0_stb_o (rom_stb_i),
.s0_ack_i (rom_ack_o),
// Slave 1 interface - vga
.s1_dat_i (vga_dat_o_s),
.s1_dat_o (vga_dat_i_s),
.s1_adr_o ({vga_tga_i_s,vga_adr_i_s}),
.s1_sel_o (vga_sel_i_s),
.s1_we_o (vga_we_i_s),
.s1_cyc_o (vga_cyc_i_s),
.s1_stb_o (vga_stb_i_s),
.s1_ack_i (vga_ack_o_s),
// Slave 2 interface - uart
.s2_dat_i (uart_dat_o),
.s2_dat_o (uart_dat_i),
.s2_adr_o ({uart_tga_i,uart_adr_i}),
.s2_sel_o (uart_sel_i),
.s2_we_o (uart_we_i),
.s2_cyc_o (uart_cyc_i),
.s2_stb_o (uart_stb_i),
.s2_ack_i (uart_ack_o),
// Slave 3 interface - keyb
.s3_dat_i ({kaud_dat_o,keyb_dat_o[7:0]}),
.s3_dat_o (keyb_dat_i),
.s3_adr_o ({keyb_tga_i,keyb_adr_i}),
.s3_sel_o (keyb_sel_i),
.s3_we_o (keyb_we_i),
.s3_cyc_o (kaud_cyc_i),
.s3_stb_o (keyb_stb_i),
.s3_ack_i (kaud_ack_o),
// Slave 4 interface - sd
.s4_dat_i (sd_dat_o_s),
.s4_dat_o (sd_dat_i_s),
.s4_adr_o ({sd_tga_i_s,sd_adr_i_s}),
.s4_sel_o (sd_sel_i_s),
.s4_we_o (sd_we_i_s),
.s4_cyc_o (sd_cyc_i_s),
.s4_stb_o (sd_stb_i_s),
.s4_ack_i (sd_ack_o_s),
// Slave 5 interface - gpio
.s5_dat_i (gpio_dat_o),
.s5_dat_o (gpio_dat_i),
.s5_adr_o ({gpio_tga_i,gpio_adr_i}),
.s5_sel_o (gpio_sel_i),
.s5_we_o (gpio_we_i),
.s5_cyc_o (gpio_cyc_i),
.s5_stb_o (gpio_stb_i),
.s5_ack_i (gpio_ack_o),
// Slave 6 interface - csr bridge
.s6_dat_i (csrbrg_dat_r_s),
.s6_dat_o (csrbrg_dat_w_s),
.s6_adr_o ({csrbrg_tga_s,csrbrg_adr_s}),
.s6_sel_o (csrbrg_sel_s),
.s6_we_o (csrbrg_we_s),
.s6_cyc_o (csrbrg_cyc_s),
.s6_stb_o (csrbrg_stb_s),
.s6_ack_i (csrbrg_ack_s),
// Slave 7 interface - timer
.s7_dat_i (timer_dat_o),
.s7_dat_o (timer_dat_i),
.s7_adr_o ({timer_tga_i,timer_adr_i}),
.s7_sel_o (timer_sel_i),
.s7_we_o (timer_we_i),
.s7_cyc_o (timer_cyc_i),
.s7_stb_o (timer_stb_i),
.s7_ack_i (timer_ack_o),
// Slave 8 interface - flash
.s8_dat_i (fl_dat_o),
.s8_dat_o (fl_dat_i),
.s8_adr_o ({fl_tga_i,fl_adr_i}),
.s8_sel_o (fl_sel_i),
.s8_we_o (fl_we_i),
.s8_cyc_o (fl_cyc_i),
.s8_stb_o (fl_stb_i),
.s8_ack_i (fl_ack_o),
// Slave 9 interface - not connected
.s9_dat_i (),
.s9_dat_o (),
.s9_adr_o (),
.s9_sel_o (),
.s9_we_o (),
.s9_cyc_o (sb_cyc_i),
.s9_stb_o (sb_stb_i),
.s9_ack_i (sb_cyc_i && sb_stb_i),
// Slave A interface - sdram
.sA_dat_i (fmlbrg_dat_r_s),
.sA_dat_o (fmlbrg_dat_w_s),
.sA_adr_o ({fmlbrg_tga_s,fmlbrg_adr_s}),
.sA_sel_o (fmlbrg_sel_s),
.sA_we_o (fmlbrg_we_s),
.sA_cyc_o (fmlbrg_cyc_s),
.sA_stb_o (fmlbrg_stb_s),
.sA_ack_i (fmlbrg_ack_s),
// Slave B interface - default
.sB_dat_i (16'h0000),
.sB_dat_o (),
.sB_adr_o (),
.sB_sel_o (),
.sB_we_o (),
.sB_cyc_o (def_cyc_i),
.sB_stb_o (def_stb_i),
.sB_ack_i (def_cyc_i & def_stb_i)
);
// Continuous assignments
assign rst_lck = !sw_[0] & lock;
assign nmi = nmi_pb;
assign dat_i = nmia ? 16'h0002 :
(inta ? { 13'b0000_0000_0000_1, iid } :
sw_dat_o);
assign sdram_clk_ = sdram_clk;
assign ledg_[3:0] = pc[3:0];
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* added stress test by Zeus Gomez Marmolejo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
//`define ENABLE_VCD
//`define TEST_SOMETRANSFERS
//`define TEST_RANDOMTRANSFERS
module tb_hpdmc;
/* 100MHz system clock */
reg clk;
initial clk = 1\'b0;
always #5 clk = ~clk;
wire sdram_cke;
wire sdram_cs_n;
wire sdram_we_n;
wire sdram_cas_n;
wire sdram_ras_n;
wire [1:0] sdram_dqm;
wire [11:0] sdram_adr;
wire [1:0] sdram_ba;
wire [15:0] sdram_dq;
// Module instances
mt48lc16m16a2 #(
.addr_bits (12),
.data_bits (16),
.col_bits (8),
//.mem_sizes (4194303)
.mem_sizes (256)
) m (
.Dq (sdram_dq),
.Addr (sdram_adr),
.Ba (sdram_ba),
.Clk (clk),
.Cke (sdram_cke),
.Cs_n (sdram_cs_n),
.Ras_n (sdram_ras_n),
.Cas_n (sdram_cas_n),
.We_n (sdram_we_n),
.Dqm (sdram_dqm)
);
reg rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
reg [22:0] fml_adr;
reg fml_stb;
reg fml_we;
wire fml_ack;
reg [1:0] fml_sel;
reg [15:0] fml_di;
wire [15:0] fml_do;
hpdmc dut(
\t.sys_clk(clk),
\t.sys_rst(rst),
\t.csr_a(csr_a),
\t.csr_we(csr_we),
\t.csr_di(csr_di),
\t.csr_do(csr_do),
\t
\t.fml_adr(fml_adr),
\t.fml_stb(fml_stb),
\t.fml_we(fml_we),
\t.fml_ack(fml_ack),
\t.fml_sel(fml_sel),
\t.fml_di(fml_di),
\t.fml_do(fml_do),
\t
\t.sdram_cke(sdram_cke),
\t.sdram_cs_n(sdram_cs_n),
\t.sdram_we_n(sdram_we_n),
\t.sdram_cas_n(sdram_cas_n),
\t.sdram_ras_n(sdram_ras_n),
\t.sdram_dqm(sdram_dqm),
\t.sdram_adr(sdram_adr),
\t.sdram_ba(sdram_ba),
\t.sdram_dq(sdram_dq)
);
task waitclock;
begin
\t@(posedge clk);
\t#1;
end
endtask
task waitnclock;
input [15:0] n;
integer i;
begin
\tfor(i=0;i<n;i=i+1)
\t\twaitclock;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
\tcsr_a = address[16:2];
\tcsr_di = data;
\tcsr_we = 1\'b1;
\twaitclock;
\t$display("Configuration Write: %x=%x", address, data);
\tcsr_we = 1\'b0;
end
endtask
task csrread;
input [31:0] address;
begin
\tcsr_a = address[16:2];
\twaitclock;
\t$display("Configuration Read : %x=%x", address, csr_do);
end
endtask
real reads;
real read_clocks;
task readburst;
input [31:0] address;
integer i;
begin
\t$display("READ [%x]", address);
\tfml_adr = address;
\tfml_stb = 1\'b1;
\tfml_we = 1\'b0;
\ti = 0;
\twhile(~fml_ack) begin
\t\ti = i+1;
\t\twaitclock;
\tend
\t$display("%t: Memory Read : %x=%x acked in %d clocks", $time, address, fml_do, i);
\tfml_stb = 1\'b0;
\treads = reads + 1;
\tread_clocks = read_clocks + i;
\tfor(i=0;i<3;i=i+1) begin
\t\twaitclock;
\t\t$display("%t: (R burst continuing) %x", $time, fml_do);
\tend
\t
\twaitclock;
end
endtask
real writes;
real write_clocks;
task writeburst;
input [31:0] address;
integer i;
begin
\t$display("WRITE [%x]", address);
\tfml_adr = address;
\tfml_stb = 1\'b1;
\tfml_we = 1\'b1;
\tfml_sel = 8\'hff;
\tfml_di = {$random, $random};
\ti = 0;
\twhile(~fml_ack) begin
\t\ti = i+1;
\t\twaitclock;
\tend
\t$display("%t: Memory Write : %x=%x acked in %d clocks", $time, address, fml_di, i);
\tfml_stb = 1\'b0;
\twrites = writes + 1;
\twrite_clocks = write_clocks + i;
\tfor(i=0;i<3;i=i+1) begin
\t\twaitclock;
\t\tfml_di = {$random, $random};
\t\t$display("%t: (W burst continuing) %x", $time, fml_di);
\tend
\twaitclock;
end
endtask
reg [5:0] i;
always
begin
i = 6\'d0;
while (1\'b1) begin
waitclock;
#1;
if (fml_ack) begin
i = i + 6\'d1;
fml_adr = {17\'h0, i};
end
end
end
always @(posedge clk)
fml_di <= $random;
task interleave;
input [31:0] iterations;
integer j;
begin
fml_stb = 1\'b1;
for(j = 0; j<iterations; j=j+1)
begin
$display ("iteration %d of %d", j, iterations);
// write
fml_we = 1\'b1;
waitclock;
while(~fml_ack) begin
waitclock;
end
// read
fml_we = 1\'b0;
waitclock;
while(~fml_ack) begin
waitclock;
end
// write
fml_we = 1\'b1;
waitclock;
while(~fml_ack) begin
waitclock;
end
// write
fml_we = 1\'b1;
waitclock;
while(~fml_ack) begin
waitclock;
end
// read
fml_we = 1\'b0;
waitclock;
while(~fml_ack) begin
waitclock;
end
// read
fml_we = 1\'b0;
waitclock;
while(~fml_ack) begin
waitclock;
end
end
fml_stb = 1\'b0;
waitclock;
end
endtask
integer n, addr;
always begin
`ifdef ENABLE_VCD
\t$dumpfile("hpdmc.vcd");
`endif
\t/* Reset / Initialize our logic */
\trst = 1\'b1;
\t
\tcsr_a = 14\'d0;
\tcsr_di = 32\'d0;
\tcsr_we = 1\'b0;
\t
\tfml_adr = 26\'d0;
\tfml_di = 64\'d0;
\tfml_sel = 8\'d0;
\tfml_stb = 1\'b0;
\tfml_we = 1\'b0;
\t
\twaitclock;
\t
\trst = 1\'b0;
\t
\twaitclock;
\t
\t/* SDRAM initialization sequence. */
\t/* The controller already comes up in Bypass mode with CKE disabled. */
\t
\t/* Wait 200us */
\t#200000;
\t
\t/* Bring CKE high */
\tcsrwrite(32\'h00, 32\'h07);
\t/* Precharge All:
\t * CS=1
\t * WE=1
\t * CAS=0
\t * RAS=1
\t * A=A10
\t * BA=Don\'t Care
\t */
\tcsrwrite(32\'h04, 32\'b00_0010000000000_1011);
\twaitnclock(2);
\t
\t/* Auto Refresh
\t * CS=1
\t * WE=0
\t * CAS=1
\t * RAS=1
\t * A=Don\'t Care
\t * BA=Don\'t Care
\t */
\tcsrwrite(32\'h04, 32\'b00_0000000000000_1101);
\twaitnclock(8);
\t
\t/* Auto Refresh */
\tcsrwrite(32\'h04, 32\'b00_0000000000000_1101);
\twaitnclock(8);
\t
\t/* Load Mode Register, DLL enabled */
\tcsrwrite(32\'h04, 32\'b00__000000_010_0_011__1111);
\twaitnclock(200);
\t
\t/* SDRAM initialization completed */
\t
`ifdef ENABLE_VCD
\t/* Now, we want to know what the controller will send to the SDRAM chips */
\t$dumpvars(0, dut);
`endif
\t
\t/* Bring up the controller ! */
\tcsrwrite(32\'h00, 32\'h04);
\twaitnclock(8);
`ifdef TEST_SOMETRANSFERS
\t/*
\t * Try some transfers.
\t */
\twriteburst(32\'h00);
\twriteburst(32\'h20);
\t//writeburst(32\'h40);
\t
\treadburst(32\'h00);
\treadburst(32\'h20);
\t/*readburst(32\'h40);
\twriteburst(32\'h40);
\treadburst(32\'h40);*/
`endif
fml_sel = 2\'b11;
interleave(5);
`ifdef TEST_RANDOMTRANSFERS
\twrites = 0;
\twrite_clocks = 0;
\treads = 0;
\tread_clocks = 0;
\tfor(n=0;n<500;n=n+1) begin
\t\taddr = $random;
\t\tif($random > 32\'h80000000) begin
\t\t\twriteburst(addr);
\t\t\t//writeburst(addr+32\'h20);
\t\t\t//writeburst(addr+32\'h40);
\t\tend else begin
\t\t\treadburst(addr);
\t\t\t//readburst(addr+32\'h20);
\t\t\t//readburst(addr+32\'h40);
\t\tend
\tend
\t
\t$display("");
\t$display("=======================================================");
\t$display(" Tested: %.0f reads, %.0f writes ", reads, writes);
\t$display("=======================================================");
\t$display(" Average read latency: %f cycles", read_clocks/reads);
\t$display(" Average write latency: %f cycles", write_clocks/writes);
\t$display("=======================================================");
\t$display(" Average read bandwidth: %f MBit/s @ 100MHz", (4/(4+read_clocks/reads))*64*100);
\t$display(" Average write bandwidth: %f MBit/s @ 100MHz", (4/(4+write_clocks/writes))*64*100);
\t$display("=======================================================");
`endif
//\t$finish;
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_mgmt #(
\tparameter sdram_depth = 26,
\tparameter sdram_columndepth = 9,
\tparameter sdram_addrdepth = sdram_depth-1-1-(sdram_columndepth+2)+1
) (
\tinput sys_clk,
\tinput sdram_rst,
\t
\tinput [2:0] tim_rp,
\tinput [2:0] tim_rcd,
\tinput [10:0] tim_refi,
\tinput [3:0] tim_rfc,
\t
\tinput stb,
\tinput we,
\tinput [sdram_depth-1-1:0] address, /* in 16-bit words */
\toutput reg ack,
\t
\toutput reg read,
\toutput reg write,
\toutput [3:0] concerned_bank,
\tinput read_safe,
\tinput write_safe,
\tinput [3:0] precharge_safe,
\t
\toutput sdram_cs_n,
\toutput sdram_we_n,
\toutput sdram_cas_n,
\toutput sdram_ras_n,
\toutput [sdram_addrdepth-1:0] sdram_adr,
\toutput [1:0] sdram_ba
);
/*
* Address Mapping :
* | ROW ADDRESS | BANK NUMBER | COL ADDRESS | for 16-bit words
* |depth-1 coldepth+2|coldepth+1 coldepth|coldepth-1 0|
* (depth for 16-bit words, which is sdram_depth-1)
*/
localparam rowdepth = sdram_depth-1-1-(sdram_columndepth+2)+1;
localparam sdram_addrdepth_o1024 = sdram_addrdepth-11;
wire [sdram_depth-1-1:0] address16 = address;
wire [sdram_columndepth-1:0] col_address = address16[sdram_columndepth-1:0];
wire [1:0] bank_address = address16[sdram_columndepth+1:sdram_columndepth];
wire [rowdepth-1:0] row_address = address16[sdram_depth-1-1:sdram_columndepth+2];
reg [3:0] bank_address_onehot;
always @(*) begin
\tcase(bank_address)
\t\t2\'b00: bank_address_onehot <= 4\'b0001;
\t\t2\'b01: bank_address_onehot <= 4\'b0010;
\t\t2\'b10: bank_address_onehot <= 4\'b0100;
\t\t2\'b11: bank_address_onehot <= 4\'b1000;
\tendcase
end
/* Track open rows */
reg [3:0] has_openrow;
reg [rowdepth-1:0] openrows[0:3];
reg [3:0] track_close;
reg [3:0] track_open;
always @(posedge sys_clk) begin
\tif(sdram_rst) begin
\t\thas_openrow <= 4\'h0;
\tend else begin
\t\thas_openrow <= (has_openrow | track_open) & ~track_close;
\t\t
\t\tif(track_open[0]) openrows[0] <= row_address;
\t\tif(track_open[1]) openrows[1] <= row_address;
\t\tif(track_open[2]) openrows[2] <= row_address;
\t\tif(track_open[3]) openrows[3] <= row_address;
\tend
end
/* Bank precharge safety */
assign concerned_bank = bank_address_onehot;
wire current_precharge_safe =
\t (precharge_safe[0] | ~bank_address_onehot[0])
\t&(precharge_safe[1] | ~bank_address_onehot[1])
\t&(precharge_safe[2] | ~bank_address_onehot[2])
\t&(precharge_safe[3] | ~bank_address_onehot[3]);
/* Check for page hits */
wire bank_open = has_openrow[bank_address];
wire page_hit = bank_open & (openrows[bank_address] == row_address);
/* Address drivers */
reg sdram_adr_loadrow;
reg sdram_adr_loadcol;
reg sdram_adr_loadA10;
assign sdram_adr =
\t ({sdram_addrdepth{sdram_adr_loadrow}}\t& row_address)
\t|({sdram_addrdepth{sdram_adr_loadcol}}\t& col_address)
\t|({sdram_addrdepth{sdram_adr_loadA10}}
& { {sdram_addrdepth_o1024{1\'b0}} , 11\'d1024});
assign sdram_ba = bank_address;
/* Command drivers */
reg sdram_cs;
reg sdram_we;
reg sdram_cas;
reg sdram_ras;
assign sdram_cs_n = ~sdram_cs;
assign sdram_we_n = ~sdram_we;
assign sdram_cas_n = ~sdram_cas;
assign sdram_ras_n = ~sdram_ras;
/* Timing counters */
/* The number of clocks we must wait following a PRECHARGE command (usually tRP). */
reg [2:0] precharge_counter;
reg reload_precharge_counter;
wire precharge_done = (precharge_counter == 3\'d0);
always @(posedge sys_clk) begin
\tif(reload_precharge_counter)
\t\tprecharge_counter <= tim_rp;
\telse if(~precharge_done)
\t\tprecharge_counter <= precharge_counter - 3\'d1;
end
/* The number of clocks we must wait following an ACTIVATE command (usually tRCD). */
reg [2:0] activate_counter;
reg reload_activate_counter;
wire activate_done = (activate_counter == 3\'d0);
always @(posedge sys_clk) begin
\tif(reload_activate_counter)
\t\tactivate_counter <= tim_rcd;
\telse if(~activate_done)
\t\tactivate_counter <= activate_counter - 3\'d1;
end
/* The number of clocks we have left before we must refresh one row in the SDRAM array (usually tREFI). */
reg [10:0] refresh_counter;
reg reload_refresh_counter;
wire must_refresh = refresh_counter == 11\'d0;
always @(posedge sys_clk) begin
\tif(sdram_rst)
\t\trefresh_counter <= 11\'d0;
\telse begin
\t\tif(reload_refresh_counter)
\t\t\trefresh_counter <= tim_refi;
\t\telse if(~must_refresh)
\t\t\trefresh_counter <= refresh_counter - 11\'d1;
\tend
end
/* The number of clocks we must wait following an AUTO REFRESH command (usually tRFC). */
reg [3:0] autorefresh_counter;
reg reload_autorefresh_counter;
wire autorefresh_done = (autorefresh_counter == 4\'d0);
always @(posedge sys_clk) begin
\tif(reload_autorefresh_counter)
\t\tautorefresh_counter <= tim_rfc;
\telse if(~autorefresh_done)
\t\tautorefresh_counter <= autorefresh_counter - 4\'d1;
end
/* FSM that pushes commands into the SDRAM */
reg [3:0] state;
reg [3:0] next_state;
localparam [3:0]
IDLE\t\t\t= 4\'d0,
ACTIVATE\t\t= 4\'d1,
READ\t\t\t= 4\'d2,
WRITE\t\t\t= 4\'d3,
PRECHARGEALL\t\t= 4\'d4,
AUTOREFRESH\t\t= 4\'d5,
AUTOREFRESH_WAIT\t= 4\'d6;
always @(posedge sys_clk) begin
\tif(sdram_rst)
\t\tstate <= IDLE;
\telse begin
\t\t//$display("state: %d -> %d", state, next_state);
\t\tstate <= next_state;
\tend
end
always @(*) begin
\tnext_state = state;
\t
\treload_precharge_counter = 1\'b0;
\treload_activate_counter = 1\'b0;
\treload_refresh_counter = 1\'b0;
\treload_autorefresh_counter = 1\'b0;
\t
\tsdram_cs = 1\'b0;
\tsdram_we = 1\'b0;
\tsdram_cas = 1\'b0;
\tsdram_ras = 1\'b0;
\t
\tsdram_adr_loadrow = 1\'b0;
\tsdram_adr_loadcol = 1\'b0;
\tsdram_adr_loadA10 = 1\'b0;
\t
\ttrack_close = 4\'b0000;
\ttrack_open = 4\'b0000;
\t
\tread = 1\'b0;
\twrite = 1\'b0;
\t
\tack = 1\'b0;
\t
\tcase(state)
\t\tIDLE: begin
\t\t\tif(must_refresh)
\t\t\t\tnext_state = PRECHARGEALL;
\t\t\telse begin
\t\t\t\tif(stb) begin
\t\t\t\t\tif(page_hit) begin
\t\t\t\t\t\tif(we) begin
\t\t\t\t\t\t\tif(write_safe) begin
\t\t\t\t\t\t\t\t/* Write */
\t\t\t\t\t\t\t\tsdram_cs = 1\'b1;
\t\t\t\t\t\t\t\tsdram_ras = 1\'b0;
\t\t\t\t\t\t\t\tsdram_cas = 1\'b1;
\t\t\t\t\t\t\t\tsdram_we = 1\'b1;
\t\t\t\t\t\t\t\tsdram_adr_loadcol = 1\'b1;
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\twrite = 1\'b1;
\t\t\t\t\t\t\t\tack = 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\tif(read_safe) begin
\t\t\t\t\t\t\t\t/* Read */
\t\t\t\t\t\t\t\tsdram_cs = 1\'b1;
\t\t\t\t\t\t\t\tsdram_ras = 1\'b0;
\t\t\t\t\t\t\t\tsdram_cas = 1\'b1;
\t\t\t\t\t\t\t\tsdram_we = 1\'b0;
\t\t\t\t\t\t\t\tsdram_adr_loadcol = 1\'b1;
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\tread = 1\'b1;
\t\t\t\t\t\t\t\tack = 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\tend else begin
\t\t\t\t\t\tif(bank_open) begin
\t\t\t\t\t\t\tif(current_precharge_safe) begin
\t\t\t\t\t\t\t\t/* Precharge Bank */
\t\t\t\t\t\t\t\tsdram_cs = 1\'b1;
\t\t\t\t\t\t\t\tsdram_ras = 1\'b1;
\t\t\t\t\t\t\t\tsdram_cas = 1\'b0;
\t\t\t\t\t\t\t\tsdram_we = 1\'b1;
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\ttrack_close = bank_address_onehot;
\t\t\t\t\t\t\t\treload_precharge_counter = 1\'b1;
\t\t\t\t\t\t\t\tnext_state = ACTIVATE;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend else begin
\t\t\t\t\t\t\t/* Activate */
\t\t\t\t\t\t\tsdram_cs = 1\'b1;
\t\t\t\t\t\t\tsdram_ras = 1\'b1;
\t\t\t\t\t\t\tsdram_cas = 1\'b0;
\t\t\t\t\t\t\tsdram_we = 1\'b0;
\t\t\t\t\t\t\tsdram_adr_loadrow = 1\'b1;
\t\t\t\t
\t\t\t\t\t\t\ttrack_open = bank_address_onehot;
\t\t\t\t\t\t\treload_activate_counter = 1\'b1;
\t\t\t\t\t\t\tif(we)
\t\t\t\t\t\t\t\tnext_state = WRITE;
\t\t\t\t\t\t\telse
\t\t\t\t\t\t\t\tnext_state = READ;
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\tend
\t\t\tend
\t\tend
\t\t
\t\tACTIVATE: begin
\t\t\tif(precharge_done) begin
\t\t\t\tsdram_cs = 1\'b1;
\t\t\t\tsdram_ras = 1\'b1;
\t\t\t\tsdram_cas = 1\'b0;
\t\t\t\tsdram_we = 1\'b0;
\t\t\t\tsdram_adr_loadrow = 1\'b1;
\t\t\t\t
\t\t\t\ttrack_open = bank_address_onehot;
\t\t\t\treload_activate_counter = 1\'b1;
\t\t\t\tif(we)
\t\t\t\t\tnext_state = WRITE;
\t\t\t\telse
\t\t\t\t\tnext_state = READ;
\t\t\tend
\t\tend
\t\tREAD: begin
\t\t\tif(activate_done) begin
\t\t\t\tif(read_safe) begin
\t\t\t\t\tsdram_cs = 1\'b1;
\t\t\t\t\tsdram_ras = 1\'b0;
\t\t\t\t\tsdram_cas = 1\'b1;
\t\t\t\t\tsdram_we = 1\'b0;
\t\t\t\t\tsdram_adr_loadcol = 1\'b1;
\t\t\t\t\t
\t\t\t\t\tread = 1\'b1;
\t\t\t\t\tack = 1\'b1;
\t\t\t\t\tnext_state = IDLE;
\t\t\t\tend
\t\t\tend
\t\tend
\t\tWRITE: begin
\t\t\tif(activate_done) begin
\t\t\t\tif(write_safe) begin
\t\t\t\t\tsdram_cs = 1\'b1;
\t\t\t\t\tsdram_ras = 1\'b0;
\t\t\t\t\tsdram_cas = 1\'b1;
\t\t\t\t\tsdram_we = 1\'b1;
\t\t\t\t\tsdram_adr_loadcol = 1\'b1;
\t\t\t\t\t
\t\t\t\t\twrite = 1\'b1;
\t\t\t\t\tack = 1\'b1;
\t\t\t\t\tnext_state = IDLE;
\t\t\t\tend
\t\t\tend
\t\tend
\t\t
\t\tPRECHARGEALL: begin
\t\t\tif(precharge_safe == 4\'b1111) begin
\t\t\t\tsdram_cs = 1\'b1;
\t\t\t\tsdram_ras = 1\'b1;
\t\t\t\tsdram_cas = 1\'b0;
\t\t\t\tsdram_we = 1\'b1;
\t\t\t\tsdram_adr_loadA10 = 1\'b1;
\t
\t\t\t\treload_precharge_counter = 1\'b1;
\t\t\t\t
\t\t\t\ttrack_close = 4\'b1111;
\t\t\t\t
\t\t\t\tnext_state = AUTOREFRESH;
\t\t\tend
\t\tend
\t\tAUTOREFRESH: begin
\t\t\tif(precharge_done) begin
\t\t\t\tsdram_cs = 1\'b1;
\t\t\t\tsdram_ras = 1\'b1;
\t\t\t\tsdram_cas = 1\'b1;
\t\t\t\tsdram_we = 1\'b0;
\t\t\t\treload_refresh_counter = 1\'b1;
\t\t\t\treload_autorefresh_counter = 1\'b1;
\t\t\t\tnext_state = AUTOREFRESH_WAIT;
\t\t\tend
\t\tend
\t\tAUTOREFRESH_WAIT: begin
\t\t\tif(autorefresh_done)
\t\t\t\tnext_state = IDLE;
\t\tend
\t\t
\tendcase
end
endmodule
|
/*\r
* CRTC controller for VGA\r
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>\r
*\r
* VGA FML support\r
* Copyright (C) 2013 Charley Picker <[email protected]>\r
*\r
* This file is part of the Zet processor. This processor is free\r
* hardware; you can redistribute it and/or modify it under the terms of\r
* the GNU General Public License as published by the Free Software\r
* Foundation; either version 3, or (at your option) any later version.\r
*\r
* Zet is distrubuted in the hope that it will be useful, but WITHOUT\r
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
* License for more details.\r
*\r
* You should have received a copy of the GNU General Public License\r
* along with Zet; see the file COPYING. If not, see\r
* <http://www.gnu.org/licenses/>.\r
*/\r
\r
module vga_crtc_fml (\r
input clk, // 100 Mhz clock\r
input rst,\r
\r
input enable_crtc,\r
\r
// CRTC configuration signals\r
\r
input [5:0] cur_start,\r
input [5:0] cur_end,\r
input [4:0] vcursor,\r
input [6:0] hcursor,\r
\r
input [6:0] horiz_total,\r
input [6:0] end_horiz,\r
input [6:0] st_hor_retr,\r
input [4:0] end_hor_retr,\r
input [9:0] vert_total,\r
input [9:0] end_vert,\r
input [9:0] st_ver_retr,\r
input [3:0] end_ver_retr,\r
\r
// CRTC output signals\r
\r
output reg [9:0] h_count, // Horizontal pipeline delay is 2 cycles\r
output reg horiz_sync_i,\r
\r
output reg [9:0] v_count, // 0 to VER_SCAN_END\r
output reg vert_sync,\r
\r
output reg video_on_h_i,\r
output reg video_on_v\r
\r
);\r
\r
// Registers and nets\r
wire [9:0] hor_disp_end;\r
wire [9:0] hor_scan_end;\r
wire [9:0] ver_disp_end;\r
wire [9:0] ver_sync_beg;\r
wire [3:0] ver_sync_end;\r
wire [9:0] ver_scan_end;\r
\r
// Continuous assignments\r
assign hor_scan_end = { horiz_total[6:2] + 1'b1, horiz_total[1:0], 3'h7 };\r
assign hor_disp_end = { end_horiz, 3'h7 };\r
assign ver_scan_end = vert_total + 10'd1;\r
assign ver_disp_end = end_vert + 10'd1;\r
assign ver_sync_beg = st_ver_retr;\r
assign ver_sync_end = end_ver_retr + 4'd1;\r
\r
// Sync generation & timing process\r
// Generate horizontal and vertical timing signals for video signal\r
always @(posedge clk)\r
if (rst)\r
begin\r
h_count <= 10'b0;\r
horiz_sync_i <= 1'b1;\r
v_count <= 10'b0;\r
vert_sync <= 1'b1;\r
video_on_h_i <= 1'b1;\r
video_on_v <= 1'b1;\r
end\r
else\r
if (enable_crtc)\r
begin\r
h_count <= (h_count==hor_scan_end) ? 10'b0 : h_count + 10'b1;\r
horiz_sync_i <= horiz_sync_i ? (h_count[9:3]!=st_hor_retr)\r
: (h_count[7:3]==end_hor_retr);\r
v_count <= (v_count==ver_scan_end && h_count==hor_scan_end) ? 10'b0\r
: ((h_count==hor_scan_end) ? v_count + 10'b1 : v_count);\r
vert_sync <= vert_sync ? (v_count!=ver_sync_beg)\r
: (v_count[3:0]==ver_sync_end);\r
\r
video_on_h_i <= (h_count==hor_scan_end) ? 1'b1\r
: ((h_count==hor_disp_end) ? 1'b0 : video_on_h_i);\r
video_on_v <= (v_count==10'h0) ? 1'b1\r
: ((v_count==ver_disp_end) ? 1'b0 : video_on_v);\r
end\r
\r
endmodule\r
|
/*
* Sound module
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// --------------------------------------------------------------------
// Description: Sound module. This is NOT a sound blaster emulator.
// This module produces simple sounds by implementing a simple interface,
// The user simply writes a byte of data to the left and/or right channels.
// Then poll the status register which will raise a flag when ready for the
// next byte of data. Alternatively, it can generate an interupt to request
// the next byte.
//
// Sound uses 16 I/O addresses 0x0nn0 to 0x0nnF, nn can be anything
//
// I/O Address Description
// ----------- ------------------
// 0x0210 Left Channel
// 0x0211 Right Channel
// 0x0212 High byte of timing increment
// 0x0213 Low byte of timing increment
// 0x0215 Control, 0x01 to enable interupt, 0x00 for polled mode
// 0x0217 Status, 0x80 when ready for next data, else 0x00
//
// --------------------------------------------------------------------
module sound (
input wb_clk_i,
input wb_rst_i,
input [ 2:0] wb_adr_i,
input [ 1:0] wb_sel_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output audio_l,
output audio_r
);
// --------------------------------------------------------------------
// Wishbone Handling
// --------------------------------------------------------------------
reg [7:0] sb_dat_o;
wire [3:0] sb_adr_i = {wb_adr_i, wb_sel_i[1]};
wire [7:0] sb_dat_i = wb_sel_i[0] ? wb_dat_i[7:0] : wb_dat_i[15:8]; // 16 to 8 bit
assign wb_dat_o = {sb_dat_o, sb_dat_o};
wire wb_ack_i = wb_stb_i & wb_cyc_i; // Immediate ack
wire wr_command = wb_ack_i & wb_we_i; // Wishbone write access, Singal to send
wire rd_command = wb_ack_i & ~wb_we_i; // Wishbone write access, Singal to send
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) wb_ack_o <= 1'b0;
else wb_ack_o <= wb_ack_i & ~wb_ack_o; // one clock delay on acknowledge output
end
// --------------------------------------------------------------------
// The following table lists the functions of the I/O ports:
// I/O Address Description Access
// ----------- -------------------
// Base + 0 Left channel data, write only
// Base + 1 Right channel data, write only
// Base + 2 High byte for timer, write only
// Base + 3 Low byte for timer, write only
// Base + 5 Control, write only
// Base + 7 Status, read only
// --------------------------------------------------------------------
`define REG_CHAN01 4'h0 // W - Channel 1
`define REG_CHAN02 4'h1 // W - Channel 1
`define REG_TIMERH 4'h2 // W - Timer increment high byte
`define REG_TIMERL 4'h3 // W - Timer increment low byte
`define REG_CONTRL 4'h5 // W - Control
`define REG_STATUS 4'h7 // R - Status
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// DefaultTime Constant
// --------------------------------------------------------------------
`define DSP_DEFAULT_RATE 16'd671 // Default sampling rate is 8Khz
// --------------------------------------------------------------------
// Sound Blaster Register behavior
// --------------------------------------------------------------------
reg start; // Start the timer
reg timeout; // Timer has timed out
reg [19:0] timer; // DAC output timer register
reg [15:0] time_inc; // DAC output time increment
wire [7:0] TMR_STATUS = {timeout, 7'h00};
always @(posedge wb_clk_i) begin // Synchrounous Logic
if(wb_rst_i) begin
sb_dat_o <= 8'h00; // Default value
end
else begin
if(rd_command) begin
case(sb_adr_i) // Determine which register was read
`REG_STATUS: sb_dat_o <= TMR_STATUS; // DSP Read status
`REG_TIMERH: sb_dat_o <= time_inc[15:8]; // Read back the timing register
`REG_TIMERL: sb_dat_o <= time_inc[ 7:0]; // Read back the timing register
default: sb_dat_o <= 8'h00; // Default
endcase // End of case
end
end // End of Reset if
end // End Synchrounous always
always @(posedge wb_clk_i) begin // Synchrounous Logic
if(wb_rst_i) begin
dsp_audio_l <= 8'h80; // default is equivalent to 1/2
dsp_audio_r <= 8'h80; // default is equivalent to 1/2
start <= 1'b0; // Timer not on
timeout <= 1'b0; // Not timed out
time_inc <= `DSP_DEFAULT_RATE; // Default value
end
else begin
if(wr_command) begin // If a write was requested
case(sb_adr_i) // Determine which register was writen to
`REG_CHAN01: begin
dsp_audio_l <= sb_dat_i; // Get the user data or data
start <= 1'b1;
timeout <= 1'b0;
end
`REG_CHAN02: begin
dsp_audio_r <= sb_dat_i; // Get the user data or data
start <= 1'b1;
timeout <= 1'b0;
end
`REG_TIMERH: time_inc[15:8] <= sb_dat_i; // Get the user data or data
`REG_TIMERL: time_inc[ 7:0] <= sb_dat_i; // Get the user data or data
default: ; // Default value
endcase // End of case
end // End of Write Command if
if(timed_out) begin
start <= 1'b0;
timeout <= 1'b1;
end
end // End of Reset if
end // End Synchrounous always
// --------------------------------------------------------------------
// Audio Timer interrupt Generation Section
// DAC Clock set to system clock which is 12,500,000Hz
// Interval = DAC_ClK / Incr = 12,500,000 / (1048576 / X ) = 8000Hz
// X = 1048576 / (12,500,000 / 8000) = 1048576 / 1562.5
// X = 671
// --------------------------------------------------------------------
wire timed_out = timer[19];
always @(posedge wb_clk_i) begin
if(wb_rst_i) begin
timer <= 20'd0;
end
else begin
if(start) timer <= timer + time_inc;
else timer <= 20'd0;
end
end
// --------------------------------------------------------------------
// PWM CLock Generation Section:
// We need to divide down the clock for PWM, dac_clk = 12.5Mhz
// then 12,500,000 / 512 = 24,414Hz which is a good sampling rate for audio
// 0 = 2
// 1 = 4
// 2 = 8 1,562,500Hz
// 3 = 16
// 4 = 32
// 5 = 64
// 6 = 128
// 7 = 256
// 8 = 512 24,414Hz
// --------------------------------------------------------------------
wire pwm_clk;
assign pwm_clk = wb_clk_i; // Because it's already at 12.5 Mhz
// --------------------------------------------------------------------
// Audio Generation Section
// --------------------------------------------------------------------
reg [7:0] dsp_audio_l;
reg [7:0] dsp_audio_r;
sound_dac8 left (pwm_clk, dsp_audio_l, audio_l); // 8 bit pwm DAC
sound_dac8 right(pwm_clk, dsp_audio_r, audio_r); // 8 bit pwm DAC
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module hex_display (
input [15:0] num,
input en,
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3
);
// Module instantiations
seg_7 hex_group0 (
.num (num[3:0]),
.en (en),
.seg (hex0)
);
seg_7 hex_group1 (
.num (num[7:4]),
.en (en),
.seg (hex1)
);
seg_7 hex_group2 (
.num (num[11:8]),
.en (en),
.seg (hex2)
);
seg_7 hex_group3 (
.num (num[15:12]),
.en (en),
.seg (hex3)
);
endmodule
|
/*
* Chain 4 memory interface for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_c4_iface (
// Wishbone common signals
input wb_clk_i,
input wb_rst_i,
// Wishbone slave interface
input [16:1] wbs_adr_i,
input [ 1:0] wbs_sel_i,
input wbs_we_i,
input [15:0] wbs_dat_i,
output [15:0] wbs_dat_o,
input wbs_stb_i,
output wbs_ack_o,
// Wishbone master to SRAM
output [17:1] wbm_adr_o,
output [ 1:0] wbm_sel_o,
output wbm_we_o,
output [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output reg wbm_stb_o,
input wbm_ack_i
);
// Registers and nets
reg plane_low;
reg [7:0] dat_low;
wire cont;
// Continuous assignments
assign wbs_ack_o = (plane_low & wbm_ack_i);
assign wbm_adr_o = { 1'b0, wbs_adr_i[15:2], wbs_adr_i[1], plane_low };
assign wbs_dat_o = { wbm_dat_i[7:0], dat_low };
assign wbm_sel_o = 2'b01;
assign wbm_dat_o = { 8'h0, plane_low ? wbs_dat_i[15:8] : wbs_dat_i[7:0] };
assign wbm_we_o = wbs_we_i & ((!plane_low & wbs_sel_i[0])
| (plane_low & wbs_sel_i[1]));
assign cont = wbm_ack_i && wbs_stb_i;
// Behaviour
// wbm_stb_o
always @(posedge wb_clk_i)
wbm_stb_o <= wb_rst_i ? 1'b0 : (wbm_stb_o ? ~wbs_ack_o : wbs_stb_i);
// plane_low
always @(posedge wb_clk_i)
plane_low <= wb_rst_i ? 1'b0 : (cont ? !plane_low : plane_low);
// dat_low
always @(posedge wb_clk_i)
dat_low <= wb_rst_i ? 8'h0
: ((wbm_ack_i && wbm_stb_o && !plane_low) ? wbm_dat_i[7:0] : dat_low);
endmodule
|
/*
* Integer conversion module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_conv (
input [15:0] x,
input [ 2:0] func,
output [31:0] out,
input [ 1:0] iflags, // afi, cfi
output [ 2:0] oflags // afo, ofo, cfo
);
// Net declarations
wire afi, cfi;
wire ofo, afo, cfo;
wire [15:0] aaa, aas;
wire [ 7:0] daa, tmpdaa, das, tmpdas;
wire [15:0] cbw, cwd;
wire acond, dcond;
wire tmpcf;
// Module instances
zet_mux8_16 mux8_16 (func, cbw, aaa, aas, 16'd0,
cwd, {x[15:8], daa}, {x[15:8], das}, 16'd0, out[15:0]);
// Assignments
assign aaa = (acond ? (x + 16'h0106) : x) & 16'hff0f;
assign aas = (acond ? (x - 16'h0106) : x) & 16'hff0f;
assign tmpdaa = acond ? (x[7:0] + 8'h06) : x[7:0];
assign daa = dcond ? (tmpdaa + 8'h60) : tmpdaa;
assign tmpdas = acond ? (x[7:0] - 8'h06) : x[7:0];
assign das = dcond ? (tmpdas - 8'h60) : tmpdas;
assign cbw = { { 8{x[ 7]}}, x[7:0] };
assign { out[31:16], cwd } = { {16{x[15]}}, x };
assign acond = ((x[7:0] & 8'h0f) > 8'h09) | afi;
assign dcond = (x[7:0] > 8'h99) | cfi;
assign afi = iflags[1];
assign cfi = iflags[0];
assign afo = acond;
assign ofo = 1'b0;
assign tmpcf = (x[7:0] < 8'h06) | cfi;
assign cfo = func[2] ? (dcond ? 1'b1 : (acond & tmpcf))
: acond;
assign oflags = { afo, ofo, cfo };
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module csrbrg(
\tinput sys_clk,
\tinput sys_rst,
\t
\t/* WB */
\tinput [3:1] wb_adr_i,
\tinput [15:0] wb_dat_i,
\toutput reg [15:0] wb_dat_o,
\tinput wb_cyc_i,
\tinput wb_stb_i,
\tinput wb_we_i,
\toutput reg wb_ack_o,
\t
\t/* CSR */
\toutput reg [2:0] csr_a,
\toutput reg csr_we,
\toutput reg [15:0] csr_do,
\tinput [15:0] csr_di
);
/* Datapath: WB <- CSR */
always @(posedge sys_clk) begin
\twb_dat_o <= csr_di;
end
/* Datapath: CSR -> WB */
reg next_csr_we;
always @(posedge sys_clk) begin
\tcsr_a <= wb_adr_i[3:1];
\tcsr_we <= next_csr_we;
\tcsr_do <= wb_dat_i;
end
/* Controller */
reg [1:0] state;
reg [1:0] next_state;
parameter IDLE\t\t= 2'd0;
parameter DELAYACK1\t= 2'd1;
parameter DELAYACK2\t= 2'd2;
parameter ACK\t\t= 2'd3;
always @(posedge sys_clk) begin
\tif(sys_rst)
\t\tstate <= IDLE;
\telse
\t\tstate <= next_state;
end
always @(*) begin
\tnext_state = state;
\t
\twb_ack_o = 1'b0;
\tnext_csr_we = 1'b0;
\t
\tcase(state)
\t\tIDLE: begin
\t\t\tif(wb_cyc_i & wb_stb_i) begin
\t\t\t\t/* We have a request for us */
\t\t\t\tnext_csr_we = wb_we_i;
\t\t\t\tif(wb_we_i)
\t\t\t\t\tnext_state = ACK;
\t\t\t\telse
\t\t\t\t\tnext_state = DELAYACK1;
\t\t\tend
\t\tend
\t\tDELAYACK1: next_state = DELAYACK2;
\t\tDELAYACK2: next_state = ACK;
\t\tACK: begin
\t\t\twb_ack_o = 1'b1;
\t\t\tnext_state = IDLE;
\t\tend
\tendcase
end
endmodule
|
/*
* Arithmetic Logic Unit for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module zet_alu (
input [31:0] x,
input [15:0] y,
output [31:0] out,
input [ 2:0] t,
input [ 2:0] func,
input [15:0] iflags,
output [ 8:0] oflags,
input word_op,
input [15:0] seg,
input [15:0] off,
input clk,
output div_exc
);
// Net declarations
wire [15:0] add, log, rot;
wire [15:0] arl;
wire [8:0] othflags;
wire [19:0] oth;
wire [31:0] cnv, mul;
wire af_add, af_cnv, af_arl;
wire cf_cnv, cf_add, cf_mul, cf_log, cf_arl, cf_rot;
wire of_cnv, of_add, of_mul, of_log, of_arl, of_rot;
wire ofi, sfi, zfi, afi, pfi, cfi;
wire ofo, sfo, zfo, afo, pfo, cfo;
wire flags_unchanged;
wire dexc;
// Module instances
zet_addsub addsub (x[15:0], y, add, func, word_op, cfi, cf_add, af_add, of_add);
zet_conv conv (
.x (x[15:0]),
.func (func),
.out (cnv),
.iflags ({afi, cfi}),
.oflags ({af_cnv, of_cnv, cf_cnv})
);
zet_muldiv muldiv (
.x (x),
.y (y),
.o (mul),
.f (func),
.word_op (word_op),
.cfo (cf_mul),
.ofo (of_mul),
.clk (clk),
.exc (dexc)
);
zet_bitlog bitlog (
.x (x[15:0]),
.o (log),
.cfo (cf_log),
.ofo (of_log)
);
zet_arlog arlog (
.x (x[15:0]),
.y (y),
.f (func),
.o (arl),
.word_op (word_op),
.cfi (cfi),
.cfo (cf_arl),
.afo (af_arl),
.ofo (of_arl)
);
zet_shrot shrot (
.x (x[15:0]),
.y (y[7:0]),
.out (rot),
.func (func),
.word_op (word_op),
.cfi (cfi),
.ofi (ofi),
.cfo (cf_rot),
.ofo (of_rot)
);
zet_othop othop (x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
zet_mux8_16 m0(t, {8'd0, y[7:0]}, add, cnv[15:0],
mul[15:0], log, arl, rot, oth[15:0], out[15:0]);
zet_mux8_16 m1(t, 16'd0, 16'd0, cnv[31:16], mul[31:16],
16'd0, 16'd0, 16'd0, {12'b0,oth[19:16]}, out[31:16]);
zet_mux8_1 a1(t, 1'b0, cf_add, cf_cnv, cf_mul, cf_log, cf_arl, cf_rot, 1'b0, cfo);
zet_mux8_1 a2(t, 1'b0, af_add, af_cnv, 1'b0, 1'b0, af_arl, afi, 1'b0, afo);
zet_mux8_1 a3(t, 1'b0, of_add, of_cnv, of_mul, of_log, of_arl, of_rot, 1'b0, ofo);
// Flags
assign pfo = flags_unchanged ? pfi : ^~ out[7:0];
assign zfo = flags_unchanged ? zfi
: ((word_op && (t!=3'd2)) ? ~|out[15:0] : ~|out[7:0]);
assign sfo = flags_unchanged ? sfi
: ((word_op && (t!=3'd2)) ? out[15] : out[7]);
assign oflags = (t == 3'd7) ? othflags
: { ofo, iflags[10:8], sfo, zfo, afo, pfo, cfo };
assign ofi = iflags[11];
assign sfi = iflags[7];
assign zfi = iflags[6];
assign afi = iflags[4];
assign pfi = iflags[2];
assign cfi = iflags[0];
assign flags_unchanged = (t == 3'd4
|| t == 3'd6 && (!func[2] || func[2]&&y[4:0]==5'h0));
assign div_exc = func[1] && (t==3'd3) && dexc;
endmodule
|
module wb_stream_writer_tb;
localparam FIFO_AW = 5;
localparam MAX_BURST_LEN = 32;
localparam WB_AW = 32;
localparam WB_DW = 32;
localparam WSB = WB_DW/8; //Word size in bytes
localparam MEM_SIZE = 128*WSB; //Memory size in bytes
localparam MAX_BUF_SIZE = 128; //Buffer size in bytes
localparam BURST_SIZE = 8;
//Configuration registers
localparam REG_CSR = 0*WSB;
localparam REG_START_ADDR = 1*WSB;
localparam REG_BUF_SIZE = 2*WSB;
localparam REG_BURST_SIZE = 3*WSB;
reg clk = 1\'b1;
reg rst = 1\'b1;
always#10 clk <= ~clk;
initial #100 rst <= 0;
vlog_tb_utils vlog_tb_utils0();
vlog_functions utils();
vlog_tap_generator #("wb_stream_writer_tb.tap", 1) tap();
//Wishbone memory interface
wire [WB_AW-1:0] wb_m2s_data_adr;
wire [WB_DW-1:0] wb_m2s_data_dat;
wire [WB_DW/8-1:0] wb_m2s_data_sel;
wire \t wb_m2s_data_we;
wire \t wb_m2s_data_cyc;
wire \t wb_m2s_data_stb;
wire [2:0] \t wb_m2s_data_cti;
wire [1:0] \t wb_m2s_data_bte;
wire [WB_DW-1:0] wb_s2m_data_dat;
wire \t wb_s2m_data_ack;
wire \t wb_s2m_data_err;
//Wishbone configuration interface
wire [WB_AW-1:0] wb_m2s_cfg_adr;
wire [WB_DW-1:0] wb_m2s_cfg_dat;
wire [WB_DW/8-1:0] wb_m2s_cfg_sel;
wire \t wb_m2s_cfg_we;
wire \t wb_m2s_cfg_cyc;
wire \t wb_m2s_cfg_stb;
wire [2:0] \t wb_m2s_cfg_cti;
wire [1:0] \t wb_m2s_cfg_bte;
wire [WB_DW-1:0] wb_s2m_cfg_dat;
wire \t wb_s2m_cfg_ack;
wire \t wb_s2m_cfg_err;
//Stream interface
wire [WB_DW-1:0] stream_data;
wire \t stream_valid;
wire \t stream_ready;
wire \t irq;
wb_stream_writer
#(.FIFO_AW (FIFO_AW),
.MAX_BURST_LEN (MAX_BURST_LEN))
dut
(.clk (clk),
.rst (rst),
//Stream data output
.wbm_adr_o (wb_m2s_data_adr),
.wbm_dat_o (wb_m2s_data_dat),
.wbm_sel_o (wb_m2s_data_sel),
.wbm_we_o (wb_m2s_data_we),
.wbm_cyc_o (wb_m2s_data_cyc),
.wbm_stb_o (wb_m2s_data_stb),
.wbm_cti_o (wb_m2s_data_cti),
.wbm_bte_o (wb_m2s_data_bte),
.wbm_dat_i (wb_s2m_data_dat),
.wbm_ack_i (wb_s2m_data_ack),
.wbm_err_i (wb_s2m_data_err),
//FIFO interface
.stream_m_data_o (stream_data),
.stream_m_valid_o (stream_valid),
.stream_m_ready_i (stream_ready),
.stream_m_irq_o (irq),
//Control Interface
.wbs_adr_i (wb_m2s_cfg_adr[4:0]),
.wbs_dat_i (wb_m2s_cfg_dat),
.wbs_sel_i (wb_m2s_cfg_sel),
.wbs_we_i (wb_m2s_cfg_we),
.wbs_cyc_i (wb_m2s_cfg_cyc),
.wbs_stb_i (wb_m2s_cfg_stb),
.wbs_cti_i (wb_m2s_cfg_cti),
.wbs_bte_i (wb_m2s_cfg_bte),
.wbs_dat_o (wb_s2m_cfg_dat),
.wbs_ack_o (wb_s2m_cfg_ack),
.wbs_err_o (wb_s2m_cfg_err));
stream_reader
#(.WIDTH (WB_DW),
.MAX_BLOCK_SIZE (MAX_BUF_SIZE/WSB))
stream_reader0
(.clk (clk),
.stream_s_data_i (stream_data),
.stream_s_valid_i (stream_valid),
.stream_s_ready_o (stream_ready));
wb_bfm_memory
#(.mem_size_bytes(MEM_SIZE),
.rd_min_delay (0),
.rd_max_delay (5))
wb_ram0
(//Wishbone Master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i\t(wb_m2s_data_adr),
.wb_dat_i\t(wb_m2s_data_dat),
.wb_sel_i\t(wb_m2s_data_sel),
.wb_we_i\t(wb_m2s_data_we),
.wb_cyc_i\t(wb_m2s_data_cyc),
.wb_stb_i\t(wb_m2s_data_stb),
.wb_cti_i\t(wb_m2s_data_cti),
.wb_bte_i\t(wb_m2s_data_bte),
.wb_dat_o\t(wb_s2m_data_dat),
.wb_ack_o\t(wb_s2m_data_ack),
.wb_err_o (wb_s2m_data_err),
.wb_rty_o ());
wb_bfm_master
#(.MAX_BURST_LEN (2))
wb_cfg
(.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_o (wb_m2s_cfg_adr),
.wb_dat_o (wb_m2s_cfg_dat),
.wb_sel_o (wb_m2s_cfg_sel),
.wb_we_o (wb_m2s_cfg_we),
.wb_cyc_o (wb_m2s_cfg_cyc),
.wb_stb_o (wb_m2s_cfg_stb),
.wb_cti_o (wb_m2s_cfg_cti),
.wb_bte_o (wb_m2s_cfg_bte),
.wb_dat_i (wb_s2m_cfg_dat),
.wb_ack_i (wb_s2m_cfg_ack),
.wb_err_i (wb_s2m_cfg_err),
.wb_rty_i (1\'b0));
integer \t transaction;
integer \t TRANSACTIONS;
reg \t\t VERBOSE = 0;
initial begin
if(!$value$plusargs("transactions=%d", TRANSACTIONS))
\tTRANSACTIONS = 1000;
if($test$plusargs("verbose"))
\tVERBOSE = 1;
@(negedge rst);
@(posedge clk);
//stream_reader0.rate = 0.08;
//fifo_reader0.timeout = 1000000;
//Initialize memory
init_mem();
@(posedge clk);
for(transaction=1;transaction<=TRANSACTIONS;transaction=transaction+1) begin
\t test_main();
\t utils.progress_bar("Completed transaction", transaction, TRANSACTIONS);
end
tap.ok("All done");
$finish;
end
task test_main;
reg [MAX_BUF_SIZE*WB_DW-1:0] received;
integer \t\t seed;
integer \t\t tmp;
integer \t\t start_addr;
integer \t\t buf_size;
integer \t\t burst_len;
begin
\t burst_len = $dist_uniform(seed, 2, MAX_BURST_LEN/WSB);
\t //FIXME: buf_size currently needs to be a multiple of burst_size
\t //buf_size = $dist_uniform(seed,1,MAX_BUF_SIZE/WSB)*WSB;
\t buf_size = burst_len*WSB*$dist_uniform(seed, 1, MAX_BUF_SIZE/(burst_len*WSB));
\t start_addr = $dist_uniform(seed,0,(MEM_SIZE-buf_size)/WSB)*WSB;
\t if(VERBOSE) $display("Setting start address to 0x%8x", start_addr);
\t if(VERBOSE) $display("Setting buffer size to %0d", buf_size);
\t if(VERBOSE) $display("Setting burst length to %0d", burst_len);
\t wb_write(REG_START_ADDR, start_addr);
\t wb_write(REG_BUF_SIZE , buf_size);
\t wb_write(REG_BURST_SIZE, burst_len);
\t @(posedge clk);
\t
\t fork
\t begin
\t //Enable stream writer
\t wb_write(REG_CSR, 1);
\t //Wait for interrupt
\t @(posedge irq);
\t //Clear interrupt
\t wb_write(REG_CSR, 2);
\t end
\t begin
\t //Start receive transactor
\t fifo_read(received, buf_size/WSB);
\t end
\t join
\t
\t verify(received, buf_size/WSB, start_addr);
end
endtask
task wb_write;
input [WB_AW-1:0] addr_i;
input [WB_DW-1:0] data_i;
reg \t\terr;
begin
\t wb_cfg.write(addr_i, data_i, 4\'hf, err);
\t if(err) begin
\t $display("Error writing to config interface address 0x%8x", addr_i);
$finish;
end
end
endtask
task fifo_read;
output [MAX_BUF_SIZE*8-1:0] data_o;
input integer \t\t\t length_i;
begin
\t stream_reader0.read_block(data_o, length_i);
end
endtask
task init_mem;
integer \t idx;
integer \t tmp;
integer \t seed;
begin
\t for(idx = 0; idx < MEM_SIZE/WSB ; idx = idx + 1) begin
\t tmp = $random(seed);
\t wb_ram0.mem[idx] = tmp[WB_DW-1:0];
\t if(VERBOSE) $display("Writing 0x%8x to address 0x%8x", tmp, idx*WSB);
\t end
end
endtask
task verify;
input [MAX_BUF_SIZE*8-1:0] received_i;
input integer \t\t samples_i;
input integer \t\t start_addr_i;
integer \t\t\t idx;
reg [WB_DW-1:0] \t\t expected;
reg [WB_DW-1:0] \t\t received;
reg \t\t\t err;
begin
\t err = 0;
\t for(idx=0 ; idx<samples_i ; idx=idx+1) begin
\t expected = wb_ram0.mem[start_addr_i/WSB+idx];
\t received = received_i[idx*WB_DW+:WB_DW];
\t
\t if(expected !==
\t received) begin
\t $display("Error at address 0x%8x. Expected 0x%8x, got 0x%8x", start_addr_i+idx*4, expected, received);
\t err = 1\'b1;
\t end //else $display("0x%8x : 0x%8x", start_addr_i+idx*WSB, received);
\t end
\t if(err)
\t $finish;
\t else
\t if (VERBOSE) $display("Successfully verified %0d words", idx);
end
endtask
endmodule
|
module wb_stream_writer_fifo
#(parameter DW = 0,
parameter AW = 0)
(input \t clk,
input \t rst,
output reg [AW:0] cnt,
input [DW-1:0] stream_s_data_i,
input \t stream_s_valid_i,
output \t stream_s_ready_o,
output [DW-1:0] stream_m_data_o,
output \t stream_m_valid_o,
input \t stream_m_ready_i);
wire \t fifo_rd_en;
wire [DW-1:0] fifo_dout;
wire \t fifo_empty;
wire \t full;
reg \t\t inc_cnt;
reg \t\t dec_cnt;
assign stream_s_ready_o = !full;
// orig_fifo is just a normal (non-FWFT) synchronous or asynchronous FIFO
fifo
#(.DEPTH_WIDTH (AW),
.DATA_WIDTH (DW))
fifo0
(
.clk (clk),
.rst (rst),
.rd_en_i (fifo_rd_en),
.rd_data_o (fifo_dout),
.empty_o (fifo_empty),
.wr_en_i (stream_s_valid_i & ~full),
.wr_data_i (stream_s_data_i),
.full_o (full));
stream_fifo_if
#(.DW (DW))
stream_if
(.clk (clk),
.rst (rst),
.fifo_data_i (fifo_dout),
.fifo_rd_en_o (fifo_rd_en),
.fifo_empty_i (fifo_empty),
.stream_m_data_o (stream_m_data_o),
.stream_m_valid_o (stream_m_valid_o),
.stream_m_ready_i (stream_m_ready_i));
always @(posedge clk) begin
inc_cnt = stream_s_valid_i & stream_s_ready_o;
dec_cnt = stream_m_valid_o & stream_m_ready_i;
if(inc_cnt & !dec_cnt)
\tcnt <= cnt + 1;
else if(dec_cnt & !inc_cnt)
\tcnt <= cnt - 1;
if (rst)
\tcnt <= 0;
end
endmodule
|
module wb_stream_reader
#(parameter WB_DW = 32,
parameter WB_AW = 32,
parameter FIFO_AW = 0,
parameter MAX_BURST_LEN = 2**FIFO_AW)
(input \t\t clk,
input rst,
//Wisbhone memory interface
output [WB_AW-1:0] wbm_adr_o,
output [WB_DW-1:0] wbm_dat_o,
output [WB_DW/8-1:0] wbm_sel_o,
output wbm_we_o ,
output wbm_cyc_o,
output wbm_stb_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input [WB_DW-1:0] wbm_dat_i,
input wbm_ack_i,
input wbm_err_i,
//Stream interface
input [WB_DW-1:0] stream_s_data_i,
input stream_s_valid_i,
output stream_s_ready_o,
output irq_o,
//Configuration interface
input [4:0] wbs_adr_i,
input [WB_DW-1:0] wbs_dat_i,
input [WB_DW/8-1:0] wbs_sel_i,
input wbs_we_i ,
input wbs_cyc_i,
input wbs_stb_i,
input [2:0] wbs_cti_i,
input [1:0] wbs_bte_i,
output [WB_DW-1:0] wbs_dat_o,
output wbs_ack_o,
output wbs_err_o);
//FIFO interface
wire [WB_DW-1:0] \t fifo_dout;
wire [FIFO_AW:0] \t fifo_cnt;
wire \t\t fifo_rd;
//Configuration parameters
wire \t\t enable;
wire [WB_DW-1:0] \t tx_cnt;
wire [WB_AW-1:0] \t start_adr;
wire [WB_AW-1:0] \t buf_size;
wire [WB_AW-1:0] \t burst_size;
wire \t\t busy;
wb_stream_reader_ctrl
#(.WB_AW (WB_AW),
.WB_DW (WB_DW),
.FIFO_AW (FIFO_AW),
.MAX_BURST_LEN (MAX_BURST_LEN))
ctrl
(.wb_clk_i (clk),
.wb_rst_i (rst),
//Stream data output
.wbm_adr_o (wbm_adr_o),
.wbm_dat_o (wbm_dat_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_cyc_o (wbm_cyc_o),
.wbm_stb_o (wbm_stb_o),
.wbm_cti_o (wbm_cti_o),
.wbm_bte_o (wbm_bte_o),
.wbm_dat_i (wbm_dat_i),
.wbm_ack_i (wbm_ack_i),
.wbm_err_i (wbm_err_i),
//FIFO interface
.fifo_d (fifo_dout),
.fifo_cnt (fifo_cnt),
.fifo_rd (fifo_rd),
//Configuration interface
.busy (busy),
.enable (enable),
.tx_cnt (tx_cnt),
.start_adr (start_adr),
.buf_size (buf_size),
.burst_size (burst_size));
wb_stream_reader_cfg
#(.WB_AW (WB_AW),
.WB_DW (WB_DW))
cfg
(.wb_clk_i (clk),
.wb_rst_i (rst),
//Wishbone IF
.wb_adr_i (wbs_adr_i),
.wb_dat_i (wbs_dat_i),
.wb_sel_i (wbs_sel_i),
.wb_we_i (wbs_we_i),
.wb_cyc_i (wbs_cyc_i),
.wb_stb_i (wbs_stb_i),
.wb_cti_i (wbs_cti_i),
.wb_bte_i (wbs_bte_i),
.wb_dat_o (wbs_dat_o),
.wb_ack_o (wbs_ack_o),
.wb_err_o (wbs_err_o),
//Application IF
.irq (irq_o),
.busy (busy),
.enable (enable),
.tx_cnt (tx_cnt),
.start_adr (start_adr),
.buf_size (buf_size),
.burst_size (burst_size));
wb_stream_writer_fifo
#(.DW (WB_DW),
.AW (FIFO_AW))
fifo
(.clk (clk),
.rst (rst),
.stream_s_data_i (stream_s_data_i),
.stream_s_valid_i (stream_s_valid_i),
.stream_s_ready_o (stream_s_ready_o),
.stream_m_data_o (fifo_dout),
.stream_m_valid_o (),
.stream_m_ready_i (fifo_rd),
.cnt (fifo_cnt));
endmodule
|
module wb_stream_writer
#(parameter WB_DW = 32,
parameter WB_AW = 32,
parameter FIFO_AW = 0,
parameter MAX_BURST_LEN = 2**FIFO_AW)
(input \t\t clk,
input rst,
//Wisbhone memory interface
output [WB_AW-1:0] wbm_adr_o,
output [WB_DW-1:0] wbm_dat_o,
output [WB_DW/8-1:0] wbm_sel_o,
output wbm_we_o ,
output wbm_cyc_o,
output wbm_stb_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input [WB_DW-1:0] wbm_dat_i,
input wbm_ack_i,
input wbm_err_i,
//Stream interface
output [WB_DW-1:0] stream_m_data_o,
output stream_m_valid_o,
input stream_m_ready_i,
output stream_m_irq_o,
//Configuration interface
input [4:0] wbs_adr_i,
input [WB_DW-1:0] wbs_dat_i,
input [WB_DW/8-1:0] wbs_sel_i,
input wbs_we_i ,
input wbs_cyc_i,
input wbs_stb_i,
input [2:0] wbs_cti_i,
input [1:0] wbs_bte_i,
output [WB_DW-1:0] wbs_dat_o,
output wbs_ack_o,
output wbs_err_o);
//FIFO interface
wire [WB_DW-1:0] \t fifo_din;
wire [FIFO_AW:0] \t fifo_cnt;
wire \t\t fifo_rd;
wire \t\t fifo_wr;
//Configuration parameters
wire \t\t enable;
wire [WB_DW-1:0] \t tx_cnt;
wire [WB_AW-1:0] \t start_adr;
wire [WB_AW-1:0] \t buf_size;
wire [WB_AW-1:0] \t burst_size;
wire \t\t busy;
wb_stream_writer_ctrl
#(.WB_AW (WB_AW),
.WB_DW (WB_DW),
.FIFO_AW (FIFO_AW),
.MAX_BURST_LEN (MAX_BURST_LEN))
ctrl
(.wb_clk_i (clk),
.wb_rst_i (rst),
//Stream data output
.wbm_adr_o (wbm_adr_o),
.wbm_dat_o (wbm_dat_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_cyc_o (wbm_cyc_o),
.wbm_stb_o (wbm_stb_o),
.wbm_cti_o (wbm_cti_o),
.wbm_bte_o (wbm_bte_o),
.wbm_dat_i (wbm_dat_i),
.wbm_ack_i (wbm_ack_i),
.wbm_err_i (wbm_err_i),
//FIFO interface
.fifo_d (fifo_din),
.fifo_wr (fifo_wr),
.fifo_cnt (fifo_cnt),
//Configuration interface
.busy (busy),
.enable (enable),
.tx_cnt (tx_cnt),
.start_adr (start_adr),
.buf_size (buf_size),
.burst_size (burst_size));
wb_stream_writer_cfg
#(.WB_AW (WB_AW),
.WB_DW (WB_DW))
cfg
(.wb_clk_i (clk),
.wb_rst_i (rst),
//Wishbone IF
.wb_adr_i (wbs_adr_i),
.wb_dat_i (wbs_dat_i),
.wb_sel_i (wbs_sel_i),
.wb_we_i (wbs_we_i),
.wb_cyc_i (wbs_cyc_i),
.wb_stb_i (wbs_stb_i),
.wb_cti_i (wbs_cti_i),
.wb_bte_i (wbs_bte_i),
.wb_dat_o (wbs_dat_o),
.wb_ack_o (wbs_ack_o),
.wb_err_o (wbs_err_o),
//Application IF
.irq (stream_m_irq_o),
.busy (busy),
.enable (enable),
.tx_cnt (tx_cnt),
.start_adr (start_adr),
.buf_size (buf_size),
.burst_size (burst_size));
wb_stream_writer_fifo
#(.DW (WB_DW),
.AW (FIFO_AW))
fifo0
(.clk (clk),
.rst (rst),
.stream_s_data_i (fifo_din),
.stream_s_valid_i (fifo_wr),
.stream_s_ready_o (),
.stream_m_data_o (stream_m_data_o),
.stream_m_valid_o (stream_m_valid_o),
.stream_m_ready_i (stream_m_ready_i),
.cnt (fifo_cnt));
endmodule
|
module wb_stream_reader_tb;
localparam FIFO_AW = 5;
localparam MAX_BURST_LEN = 32;
localparam WB_AW = 32;
localparam WB_DW = 32;
localparam WSB = WB_DW/8; //Word size in bytes
localparam MEM_SIZE = 128*WSB; //Memory size in bytes
localparam MAX_BUF_SIZE = 32*WSB; //Buffer size in bytes
localparam BURST_SIZE = 8;
//Configuration registers
localparam REG_CSR = 0*WSB;
localparam REG_START_ADDR = 1*WSB;
localparam REG_BUF_SIZE = 2*WSB;
localparam REG_BURST_SIZE = 3*WSB;
reg clk = 1\'b1;
reg rst = 1\'b1;
always#10 clk <= ~clk;
initial #100 rst <= 0;
vlog_tb_utils vlog_tb_utils0();
vlog_functions utils();
vlog_tap_generator #("wb_stream_reader_tb.tap", 1) tap();
//Wishbone memory interface
wire [WB_AW-1:0] wb_m2s_data_adr;
wire [WB_DW-1:0] wb_m2s_data_dat;
wire [WB_DW/8-1:0] wb_m2s_data_sel;
wire \t wb_m2s_data_we;
wire \t wb_m2s_data_cyc;
wire \t wb_m2s_data_stb;
wire [2:0] \t wb_m2s_data_cti;
wire [1:0] \t wb_m2s_data_bte;
wire [WB_DW-1:0] wb_s2m_data_dat;
wire \t wb_s2m_data_ack;
wire \t wb_s2m_data_err;
//Wishbone configuration interface
wire [WB_AW-1:0] wb_m2s_cfg_adr;
wire [WB_DW-1:0] wb_m2s_cfg_dat;
wire [WB_DW/8-1:0] wb_m2s_cfg_sel;
wire \t wb_m2s_cfg_we;
wire \t wb_m2s_cfg_cyc;
wire \t wb_m2s_cfg_stb;
wire [2:0] \t wb_m2s_cfg_cti;
wire [1:0] \t wb_m2s_cfg_bte;
wire [WB_DW-1:0] wb_s2m_cfg_dat;
wire \t wb_s2m_cfg_ack;
wire \t wb_s2m_cfg_err;
//Stream interface
wire [WB_DW-1:0] stream_data;
wire \t stream_valid;
wire \t stream_ready;
wire \t irq;
wb_stream_reader
#(.FIFO_AW (FIFO_AW),
.MAX_BURST_LEN (MAX_BURST_LEN))
dut
(.clk (clk),
.rst (rst),
//Stream data output
.wbm_adr_o (wb_m2s_data_adr),
.wbm_dat_o (wb_m2s_data_dat),
.wbm_sel_o (wb_m2s_data_sel),
.wbm_we_o (wb_m2s_data_we),
.wbm_cyc_o (wb_m2s_data_cyc),
.wbm_stb_o (wb_m2s_data_stb),
.wbm_cti_o (wb_m2s_data_cti),
.wbm_bte_o (wb_m2s_data_bte),
.wbm_dat_i (wb_s2m_data_dat),
.wbm_ack_i (wb_s2m_data_ack),
.wbm_err_i (wb_s2m_data_err),
//FIFO interface
.stream_s_data_i (stream_data),
.stream_s_valid_i (stream_valid),
.stream_s_ready_o (stream_ready),
.irq_o (irq),
//Control Interface
.wbs_adr_i (wb_m2s_cfg_adr[4:0]),
.wbs_dat_i (wb_m2s_cfg_dat),
.wbs_sel_i (wb_m2s_cfg_sel),
.wbs_we_i (wb_m2s_cfg_we),
.wbs_cyc_i (wb_m2s_cfg_cyc),
.wbs_stb_i (wb_m2s_cfg_stb),
.wbs_cti_i (wb_m2s_cfg_cti),
.wbs_bte_i (wb_m2s_cfg_bte),
.wbs_dat_o (wb_s2m_cfg_dat),
.wbs_ack_o (wb_s2m_cfg_ack),
.wbs_err_o (wb_s2m_cfg_err));
stream_writer
#(.WIDTH (WB_DW),
.MAX_BLOCK_SIZE (MAX_BUF_SIZE/WSB))
writer
(.clk (clk),
.stream_m_data_o (stream_data),
.stream_m_valid_o (stream_valid),
.stream_m_ready_i (stream_ready));
wb_bfm_memory
#(.mem_size_bytes(MEM_SIZE),
.rd_min_delay (0),
.rd_max_delay (5))
wb_ram0
(//Wishbone Master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i\t(wb_m2s_data_adr),
.wb_dat_i\t(wb_m2s_data_dat),
.wb_sel_i\t(wb_m2s_data_sel),
.wb_we_i\t(wb_m2s_data_we),
.wb_cyc_i\t(wb_m2s_data_cyc),
.wb_stb_i\t(wb_m2s_data_stb),
.wb_cti_i\t(wb_m2s_data_cti),
.wb_bte_i\t(wb_m2s_data_bte),
.wb_dat_o\t(wb_s2m_data_dat),
.wb_ack_o\t(wb_s2m_data_ack),
.wb_err_o (wb_s2m_data_err));
wb_bfm_master
#(.MAX_BURST_LEN (2))
wb_cfg
(.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_o (wb_m2s_cfg_adr),
.wb_dat_o (wb_m2s_cfg_dat),
.wb_sel_o (wb_m2s_cfg_sel),
.wb_we_o (wb_m2s_cfg_we),
.wb_cyc_o (wb_m2s_cfg_cyc),
.wb_stb_o (wb_m2s_cfg_stb),
.wb_cti_o (wb_m2s_cfg_cti),
.wb_bte_o (wb_m2s_cfg_bte),
.wb_dat_i (wb_s2m_cfg_dat),
.wb_ack_i (wb_s2m_cfg_ack),
.wb_err_i (wb_s2m_cfg_err),
.wb_rty_i (1\'b0));
integer \t transaction;
integer \t TRANSACTIONS;
reg \t\t VERBOSE = 0;
initial begin
if(!$value$plusargs("transactions=%d", TRANSACTIONS))
\tTRANSACTIONS = 1000;
if($test$plusargs("verbose"))
\tVERBOSE = 1;
@(negedge rst);
@(posedge clk);
//FIXME: Implement wb slave config IF
writer.rate = 0.1;
for(transaction=1;transaction<=TRANSACTIONS;transaction=transaction+1) begin
\t test_main();
\t utils.progress_bar("Completed transaction", transaction, TRANSACTIONS);
end
tap.ok("All done");
$finish;
end // initial begin
reg [WB_DW-1:0] stimuli [0:MAX_BUF_SIZE/WSB-1];
task test_main;
integer start_adr;
integer buf_size;
integer burst_len;
integer \t\t idx;
integer \t\t tmp;
integer \t\t seed;
reg [WB_DW*8*WSB-1:0] data_block;
begin
\t //FIXME: Burst length must be > 1
\t burst_len = $dist_uniform(seed, 2, MAX_BURST_LEN/WSB);
\t //FIXME: buf_size currently needs to be a multiple of burst_size
\t //buf_size = $dist_uniform(seed,1,MAX_BUF_SIZE/WSB)*WSB;
\t buf_size = burst_len*WSB*$dist_uniform(seed, 1, MAX_BUF_SIZE/(burst_len*WSB));
\t start_adr = $dist_uniform(seed,0,(MEM_SIZE-buf_size)/WSB)*WSB;
\t //Generate stimuli
\t for(idx=0 ; idx<buf_size/WSB ; idx=idx+1) begin
\t tmp = $random(seed);
\t stimuli[idx] = tmp[WB_DW-1:0];
\t end
\t cfg_write(REG_START_ADDR, start_adr); //Set start address
\t cfg_write(REG_BUF_SIZE , buf_size);//Set buffer size
\t cfg_write(REG_BURST_SIZE, burst_len);//Set burst length
\t cfg_write(REG_CSR, 1); //Start DMA
\t
\t //Start transmit and receive transactors
\t
\t fifo_write(buf_size/WSB);
\t @(posedge irq);
\t verify(start_adr, buf_size);
\t cfg_write(REG_CSR, 2); //Clear IRQ
end
endtask
task cfg_write;
input [WB_AW-1:0] addr_i;
input [WB_DW-1:0] data_i;
reg \t\terr;
begin
\t wb_cfg.write(addr_i, data_i, 4\'hf, err);
\t if(err) begin
\t $display("Error writing to config interface address 0x%8x", addr_i);
$finish;
end
end
endtask
task fifo_write;
input integer len;
integer idx;
begin
\t
\t for(idx=0;idx < len ; idx=idx+1) begin
\t writer.write_word(stimuli[idx]);
\t end
end
endtask
\t
task verify;
input integer start_adr;
input integer buf_size;
integer \t idx;
reg [WB_DW-1:0] expected;
reg [WB_DW-1:0] received;
reg \t err;
begin
\t for(idx = 0; idx < buf_size/WSB ; idx = idx + 1) begin
\t expected = stimuli[idx];
\t received = wb_ram0.mem[start_adr/WSB+idx];
\t
\t if(received !== expected) begin
\t $display("%m : Verify failed at address 0x%8x. Expected 0x%8x : Got 0x%8x",
\t\t start_adr+idx*WSB,
\t\t expected,
\t\t received);
$finish;
end
\t end
end
endtask
endmodule
|
`default_nettype none
module wb_reader
#(parameter WB_AW = 32,
parameter WB_DW = 32,
parameter MAX_BURST_LEN = 0)
(input wire wb_clk_i,
input wire wb_rst_i,
input wire [WB_AW-1:0] wb_adr_i,
input wire [WB_DW-1:0] wb_dat_i,
input wire [WB_DW/8-1:0] wb_sel_i,
input wire wb_we_i,
input wire [1:0] wb_bte_i,
input wire [2:0] wb_cti_i,
input wire wb_cyc_i,
input wire wb_stb_i,
output wire wb_ack_o,
output wire wb_err_o,
output wire [WB_DW-1:0] wb_dat_o);
wb_bfm_slave
#(.aw (WB_AW),
.dw (WB_DW))
bfm0
(.wb_clk (wb_clk_i),
.wb_rst (wb_rst_i),
.wb_adr_i (wb_adr_i),
.wb_dat_i (wb_dat_i),
.wb_sel_i (wb_sel_i),
.wb_we_i (wb_we_i),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_cti_i (wb_cti_i),
.wb_bte_i (wb_bte_i),
.wb_dat_o (wb_dat_o),
.wb_ack_o (wb_ack_o),
.wb_err_o (wb_err_o),
.wb_rty_o ());
task wb_read_burst;
output [MAX_BURST_LEN*WB_AW-1:0] addr_o;
output [MAX_BURST_LEN*WB_DW-1:0] data_o;
output integer \t length_o;
reg [WB_AW-1:0] \t addr;
reg [WB_DW-1:0] \t data;
integer \t\t idx;
begin
\t bfm0.init();
\t
\t addr = wb_adr_i;
\t
\t if(bfm0.op !== bfm0.WRITE)
\t $error("%m : Expected a wishbone write operation");
\t else if(bfm0.cycle_type !== bfm0.BURST_CYCLE)
\t $error("%m : Expected a burst cycle");
\t else begin
\t idx = 0;
\t while(bfm0.has_next) begin
\t //FIXME: Check mask
\t bfm0.write_ack(data);
\t //$display("%d : Got new data %x", idx, data);
\t data_o[idx*WB_DW+:WB_DW] = data;
\t addr_o[idx*WB_DW+:WB_AW] = addr;
\t idx = idx + 1;
\t addr = bfm0.next_addr(addr, bfm0.burst_type);
\t end
\t length_o = idx;
\t end // else: !if(bfm0.cycle_type !== BURST_CYCLE)
end
endtask
endmodule
|
//TODO: Allow burst size = 1
//TODO: Add timeout counter to clear out FIFO
module wb_stream_reader_ctrl
#(parameter WB_AW = 32,
parameter WB_DW = 32,
parameter FIFO_AW = 0,
parameter MAX_BURST_LEN = 0)
(//Stream data output
input \t\t wb_clk_i,
input \t\t wb_rst_i,
output [WB_AW-1:0] \t wbm_adr_o,
output [WB_DW-1:0] \t wbm_dat_o,
output [WB_DW/8-1:0] wbm_sel_o,
output \t\t wbm_we_o ,
output \t\t wbm_cyc_o,
output \t\t wbm_stb_o,
output reg [2:0] \t wbm_cti_o,
output [1:0] \t wbm_bte_o,
input [WB_DW-1:0] \t wbm_dat_i,
input \t\t wbm_ack_i,
input \t\t wbm_err_i,
//FIFO interface
input [WB_DW-1:0] \t fifo_d,
output \t\t fifo_rd,
input [FIFO_AW:0] \t fifo_cnt,
//Configuration interface
output reg \t\t busy,
input \t\t enable,
output reg [WB_DW-1:0] tx_cnt,
input [WB_AW-1:0] \t start_adr,
input [WB_AW-1:0] \t buf_size,
input [WB_AW-1:0] \t burst_size);
wire\t\t\t active;
wire \t\t timeout = 1'b0;
reg \t\t\t last_adr;
reg [$clog2(MAX_BURST_LEN-1):0] burst_cnt;
//FSM states
localparam S_IDLE = 0;
localparam S_ACTIVE = 1;
reg [1:0] \t\t\t state;
wire \t\t\t burst_end = (burst_cnt == burst_size-1);
wire fifo_ready = (fifo_cnt >= burst_size) & (fifo_cnt > 0);
always @(active or burst_end) begin
wbm_cti_o = !active ? 3'b000 :
\t\t burst_end ? 3'b111 :
\t\t 3'b010; //LINEAR_BURST;
end
assign active = (state == S_ACTIVE);
assign fifo_rd = wbm_ack_i;
assign wbm_sel_o = 4'hf;
assign wbm_we_o = active;
assign wbm_cyc_o = active;
assign wbm_stb_o = active;
assign wbm_bte_o = 2'b00;
assign wbm_dat_o = fifo_d;
assign wbm_adr_o = start_adr + tx_cnt*4;
always @(posedge wb_clk_i) begin
//Address generation
last_adr = (tx_cnt == buf_size[WB_AW-1:2]-1);
if (wbm_ack_i)
\t if (last_adr)
\t tx_cnt <= 0;
\t else
\t tx_cnt <= tx_cnt+1;
//Burst counter
if(!active)
\tburst_cnt <= 0;
else
\tif(wbm_ack_i)
\t burst_cnt <= burst_cnt + 1;
//FSM
case (state)
\tS_IDLE : begin
\t if (busy & fifo_ready)
\t state <= S_ACTIVE;
\t if (enable)
\t busy <= 1'b1;
\tend
\tS_ACTIVE : begin
\t if (burst_end & wbm_ack_i) begin
\t state <= S_IDLE;
\t if (last_adr)
\t\tbusy <= 1'b0;
\t end
\tend
\tdefault : begin
\t state <= S_IDLE;
\tend
endcase // case (state)
if(wb_rst_i) begin
\t state <= S_IDLE;
\t tx_cnt <= 0;
\t busy <= 1'b0;
end
end
endmodule
|
module wb_stream_reader_cfg
#(parameter WB_AW = 32,
parameter WB_DW = 32)
(
input wb_clk_i,
input wb_rst_i,
//Wishbone IF
input [4:0] wb_adr_i,
input [WB_DW-1:0] wb_dat_i,
input [WB_DW/8-1:0] wb_sel_i,
input wb_we_i ,
input wb_cyc_i,
input wb_stb_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output [WB_DW-1:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
//Application IF
output reg irq,
input busy,
output reg enable,
input [WB_DW-1:0] tx_cnt,
output reg [WB_AW-1:0] start_adr,
output reg [WB_AW-1:0] buf_size,
output reg [WB_AW-1:0] burst_size);
reg \t\t\t busy_r;
always @(posedge wb_clk_i)
if (wb_rst_i)
busy_r <= 0;
else
busy_r <= busy;
// Read
assign wb_dat_o = wb_adr_i[4:2] == 0 ? {{(WB_DW-2){1'b0}}, irq, busy} :
\t\t wb_adr_i[4:2] == 1 ? start_adr :
wb_adr_i[4:2] == 2 ? buf_size :
wb_adr_i[4:2] == 3 ? burst_size :
wb_adr_i[4:2] == 4 ? tx_cnt*4 :
0;
always @(posedge wb_clk_i) begin
// Ack generation
if (wb_ack_o)
\twb_ack_o <= 0;
else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
\twb_ack_o <= 1;
//Read/Write logic
enable <= 0;
if (wb_stb_i & wb_cyc_i & wb_we_i & wb_ack_o) begin
\t case (wb_adr_i[4:2])
\t 0 : begin
\t if (wb_dat_i[0]) enable <= 1;
\t if (wb_dat_i[1]) irq <= 0;
\t end
\t 1 : start_adr <= wb_dat_i;
\t 2 : buf_size <= wb_dat_i;
\t 3 : burst_size <= wb_dat_i;
\t default : ;
\t endcase
end
// irq logic, signal on falling edge of busy
if (!busy & busy_r)
\tirq <= 1;
if (wb_rst_i) begin
\t wb_ack_o <= 0;
\t enable <= 1'b0;
\t start_adr <= 0;
\t buf_size <= 0;
\t burst_size <= 0;
\t irq <= 0;
end
end
assign wb_err_o = 0;
endmodule
|
module wb_stream_writer_ctrl
#(parameter WB_AW = 32,
parameter WB_DW = 32,
parameter FIFO_AW = 0,
parameter MAX_BURST_LEN = 0)
(//Stream data output
input \t\t wb_clk_i,
input \t\t wb_rst_i,
output [WB_AW-1:0] \t wbm_adr_o,
output [WB_DW-1:0] \t wbm_dat_o,
output [WB_DW/8-1:0] wbm_sel_o,
output \t\t wbm_we_o ,
output \t\t wbm_cyc_o,
output \t\t wbm_stb_o,
output reg [2:0] \t wbm_cti_o,
output [1:0] \t wbm_bte_o,
input [WB_DW-1:0] \t wbm_dat_i,
input \t\t wbm_ack_i,
input \t\t wbm_err_i,
//FIFO interface
output [WB_DW-1:0] \t fifo_d,
output \t\t fifo_wr,
input [FIFO_AW:0] \t fifo_cnt,
//Configuration interface
output reg \t\t busy,
input \t\t enable,
output reg [WB_DW-1:0] tx_cnt,
input [WB_AW-1:0] \t start_adr,
input [WB_AW-1:0] \t buf_size,
input [WB_AW-1:0] \t burst_size);
wire\t\t\t active;
wire \t\t timeout = 1'b0;
reg \t\t\t last_adr;
reg [$clog2(MAX_BURST_LEN-1):0] burst_cnt;
//FSM states
localparam S_IDLE = 0;
localparam S_ACTIVE = 1;
reg [1:0] \t\t\t state;
wire \t\t\t burst_end = (burst_cnt == burst_size-1);
wire fifo_ready = (fifo_cnt+burst_size <= 2**FIFO_AW);
always @(active or burst_end) begin
wbm_cti_o = !active ? 3'b000 :
\t\t burst_end ? 3'b111 :
\t\t 3'b010; //LINEAR_BURST;
end
assign active = (state == S_ACTIVE);
assign fifo_d = wbm_dat_i;
assign fifo_wr = wbm_ack_i;
assign wbm_sel_o = 4'hf;
assign wbm_we_o = 1'b0;
assign wbm_cyc_o = active;
assign wbm_stb_o = active;
assign wbm_bte_o = 2'b00;
assign wbm_dat_o = {WB_DW{1'b0}};
assign wbm_adr_o = start_adr + tx_cnt*4;
always @(posedge wb_clk_i) begin
//Address generation
last_adr = (tx_cnt == buf_size[WB_AW-1:2]-1);
if (wbm_ack_i)
\t if (last_adr)
\t tx_cnt <= 0;
\t else
\t tx_cnt <= tx_cnt+1;
//Burst counter
if(!active)
\tburst_cnt <= 0;
else
\tif(wbm_ack_i)
\t burst_cnt <= burst_cnt + 1;
//FSM
case (state)
\tS_IDLE : begin
\t if (busy & fifo_ready)
\t state <= S_ACTIVE;
\t if (enable)
\t busy <= 1'b1;
\tend
\tS_ACTIVE : begin
\t if (burst_end & wbm_ack_i) begin
\t state <= S_IDLE;
\t if (last_adr)
\t\tbusy <= 1'b0;
\t end
\tend
\tdefault : begin
\t state <= S_IDLE;
\tend
endcase // case (state)
if(wb_rst_i) begin
\t state <= S_IDLE;
\t tx_cnt <= 0;
\t busy <= 1'b0;
end
end
endmodule
|
module wb_stream_writer_cfg
#(parameter WB_AW = 32,
parameter WB_DW = 32)
(
input wb_clk_i,
input wb_rst_i,
//Wishbone IF
input [4:0] wb_adr_i,
input [WB_DW-1:0] wb_dat_i,
input [WB_DW/8-1:0] wb_sel_i,
input wb_we_i ,
input wb_cyc_i,
input wb_stb_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output [WB_DW-1:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
//Application IF
output reg irq,
input busy,
output reg enable,
input [WB_DW-1:0] tx_cnt,
output reg [WB_AW-1:0] start_adr,
output reg [WB_AW-1:0] buf_size,
output reg [WB_AW-1:0] burst_size);
reg \t\t\t busy_r;
always @(posedge wb_clk_i)
if (wb_rst_i)
busy_r <= 0;
else
busy_r <= busy;
// Read
assign wb_dat_o = wb_adr_i[4:2] == 0 ? {{(WB_DW-2){1'b0}}, irq, busy} :
\t\t wb_adr_i[4:2] == 1 ? start_adr :
wb_adr_i[4:2] == 2 ? buf_size :
wb_adr_i[4:2] == 3 ? burst_size :
wb_adr_i[4:2] == 4 ? tx_cnt*4 :
0;
always @(posedge wb_clk_i) begin
// Ack generation
if (wb_ack_o)
\twb_ack_o <= 0;
else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
\twb_ack_o <= 1;
//Read/Write logic
enable <= 0;
if (wb_stb_i & wb_cyc_i & wb_we_i & wb_ack_o) begin
\t case (wb_adr_i[4:2])
\t 0 : begin
\t if (wb_dat_i[0]) enable <= 1;
\t if (wb_dat_i[1]) irq <= 0;
\t end
\t 1 : start_adr <= wb_dat_i;
\t 2 : buf_size <= wb_dat_i;
\t 3 : burst_size <= wb_dat_i;
\t default : ;
\t endcase
end
// irq logic, signal on falling edge of busy
if (!busy & busy_r)
\tirq <= 1;
if (wb_rst_i) begin
\t wb_ack_o <= 0;
\t enable <= 1'b0;
\t start_adr <= 0;
\t buf_size <= 0;
\t burst_size <= 0;
\t irq <= 0;
end
end
assign wb_err_o = 0;
endmodule
|
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode\r
// \r
// This file is part of PVS.\r
// \r
// PVS is free software: you can redistribute it and/or modify it under the\r
// terms of the GNU General Public License as published by the Free Software\r
// Foundation, either version 3 of the License, or (at your option) any later\r
// version.\r
// \r
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY\r
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR\r
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.\r
// \r
// You should have received a copy of the GNU General Public License along with\r
// PVS. If not, see <http://www.gnu.org/licenses/>.\r
\r
`timescale 1 ns / 1 ns\r
\r
// Widens the output signal using COUNT\r
\r
// inputs: \t\r
// CLK\r
//\tsignal_i - input signal\r
\r
// output:\t\r
//\tsignal_o - output signal\r
\r
// parameter: \r
// COUNT - counter val for width, default 15\r
\r
module output_pulse\r
(\r
clk,\r
\t\t\t signal_i,\r
\t\t\t signal_o\r
);\r
\t\t\t \r
//////////// INPUTS & OUTPUTS ////////////\t \r
input clk;\r
input signal_i;\r
output signal_o;\r
\t\t\t \r
//////////// PARAMETERS ////////////\r
parameter COUNT = 15; // with clk of 1.5kHz corresponds to 10ms width\r
\r
parameter s_idle = 1'b0;\r
parameter s_out = 1'b1;\r
\r
\r
//////////// SIGNALS & REGS ////////////\r
reg[15:0] cnt = 0;\r
reg state = 0;\r
\r
//////////// LOGIC ////////////\r
always @(posedge clk) begin\r
\t\tcase(state)\r
\t\t\ts_idle:\r
\t\t\tbegin\r
\t\t\t\tstate <= (signal_i) ? s_out : s_idle;\r
\t\t\t\tcnt <= 8'b0;\r
\t\t\tend\r
\t\t\ts_out:\r
\t\t\tbegin\r
\t\t\t\tstate <= (cnt >= COUNT) ? s_idle : s_out;\r
\t\t\t\tcnt <= cnt + 8'b1;\r
\t\t\tend\r
\t\tendcase\r
end\r
\r
//////////// OUTPUT ASSIGNS ////////////\r
assign signal_o = (state == s_out);\r
\r
endmodule\r
|
// from http://hdlsnippets.com/verilog_rising_edge_detect\r
module rising_edge_detect\r
(\r
input clk,\r
input signal,\r
output pulse\r
);\r
\r
reg signal_prev;\r
\r
always @(posedge clk) signal_prev <= signal;\r
\r
assign pulse = signal & ~signal_prev;\r
\r
endmodule
|
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode\r
// \r
// This file is part of PVS.\r
// \r
// PVS is free software: you can redistribute it and/or modify it under the\r
// terms of the GNU General Public License as published by the Free Software\r
// Foundation, either version 3 of the License, or (at your option) any later\r
// version.\r
// \r
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY\r
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR\r
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.\r
// \r
// You should have received a copy of the GNU General Public License along with\r
// PVS. If not, see <http://www.gnu.org/licenses/>.\r
\r
`timescale 1 ns / 1 ns\r
\r
// receives mode to switch via serial\r
// bit order:\r
// first 15-bits: SA_rest (little-endian)\r
// next 1-bit: pace_en\r
// next 14-bits: AV_forw (little-endian)\r
// next 1-bit: PACen\r
// next 1-bit: PVCen\r
// total: 32-bits, 4 byte transmission\r
\r
// DEFAULT CONFIGURATION\r
// SA_rest = 700\r
// pace_en = 1\r
// AV_forw = 200\r
// PACen = 0\r
// PVCen = 0\r
// KEEP IN MIND THE VHM DOES NOT REGISTER THESE INPUTS! (so this should!)\r
\r
module mode_setter\r
(\r
clk_fast,\r
\t\t\t clk_slow,\r
\t\t\t rx,\r
\t\t\t recv_pulse,\r
\t\t\t pace_en,\r
\t\t\t SA_rest,\r
\t\t\t AV_forw,\r
\t\t\t PACen,\r
\t\t\t PVCen,\r
);\r
\t\t\t \r
//////////// INPUTS & OUTPUTS ////////////\t \r
input clk_fast;\r
input clk_slow;\r
input rx;\r
output recv_pulse;\r
output pace_en;\r
output [15:0] SA_rest;\r
output [15:0] AV_forw;\r
output PACen;\r
output PVCen;\r
\t\t\t \r
//////////// PARAMETERS ////////////\r
parameter s_idle = 1'b0;\r
parameter s_out = 1'b1;\r
parameter CLOCK_RATIO = 16'd33334; // 50MHz / 1.5kHz\r
parameter NUM_BYTES = 4'd4; // two for SA_rest, two for AV_forw\r
\r
//////////// SIGNALS & REGS ////////////\r
wire [7:0] recv_data; // data from receiver\r
wire recv_data_ready; // data ready from receiver (1 clock pulse)\r
reg [7:0] recv_data_reg; // data latched from reg\r
\r
reg state; // state machine for determining if output is ready\r
reg recv_pulse_reg = 1'b0; // output ready pulse, used for reset by heart\r
reg [15:0] SA_rest_reg = 16'd900; // DEFAULT CASE\r
reg [15:0] SA_rest_temp_reg = 16'd900;\r
reg pace_en_reg = 1'b1;\t\t// DEFAULT CASE\r
reg pace_en_temp_reg = 1'b1;\r
reg [15:0] AV_forw_reg = 16'd50; // DEFAULT CASE\r
reg [15:0] AV_forw_temp_reg = 16'd50;\r
reg PACen_reg = 1'd0; // DEFAULT CASE\r
reg PACen_temp_reg = 1'd0;\r
reg PVCen_reg = 1'd0; // DEFAULT CASE\r
reg PVCen_temp_reg = 1'd0;\r
reg [15:0] cnt = 16'd0; // counter to keep signals stable\r
reg [3:0] byte_cnt = 4'd0; // cnt of bytes received so far\r
\r
//////////// LOGIC ////////////\r
async_receiver receiver \r
\t\t\t(\r
\t\t\t.clk(clk_fast), \r
\t\t\t.RxD(rx), \r
\t\t\t.RxD_data_ready(recv_data_ready), \r
\t\t\t.RxD_data(recv_data), \r
\t\t\t//.RxD_endofpacket, \r
\t\t\t//.RxD_idle\r
\t\t\t);\r
\t\r
always @(posedge clk_fast) begin\r
\t\tcase(state)\r
\t\t\ts_idle:\r
\t\t\tbegin\r
\t\t\t\tstate <= (byte_cnt >= NUM_BYTES) ? s_out : s_idle;\r
\t\t\t\t// recv_pulse, PACen, and PVCen should only be 1 cycle wide\r
\t\t\t\trecv_pulse_reg <= 1'b0;\r
\t\t\t\tPACen_reg <= 1'b0;\r
\t\t\t\tPVCen_reg <= 1'b0;\r
\t\t\t\t// = instead of <= on purpose from here\r
\t\t\t\trecv_data_reg = recv_data;\r
\t\t\t\tif (recv_data_ready && byte_cnt == 4'd0) begin\r
\t\t\t\t\tSA_rest_temp_reg[7:0] = recv_data_reg;\r
\t\t\t\tend\r
\t\t\t\telse if (recv_data_ready && byte_cnt == 4'd1) begin\r
\t\t\t\t\tSA_rest_temp_reg[14:8] = recv_data_reg[6:0];\r
\t\t\t\t\tSA_rest_temp_reg[15] = 1'b0;\r
\t\t\t\t\tpace_en_temp_reg = recv_data_reg[7];\r
\t\t\t\tend\r
\t\t\t\telse if (recv_data_ready && byte_cnt == 4'd2) begin\r
\t\t\t\t\tAV_forw_temp_reg[7:0] = recv_data_reg;\r
\t\t\t\tend\r
\t\t\t\telse if (recv_data_ready && byte_cnt == 4'd3) begin\r
\t\t\t\t\tAV_forw_temp_reg[15:8] = {2'b0,recv_data_reg[5:0]};\r
\t\t\t\t\tPACen_temp_reg = recv_data_reg[6];\r
\t\t\t\t\tPVCen_temp_reg = recv_data_reg[7];\r
\t\t\t\tend\r
\t\t\t\tcnt <= 16'd0;\r
\t\t\t\tif (recv_data_ready)\r
\t\t\t\t\tbyte_cnt <= byte_cnt + 4'd1;\r
\t\t\tend\r
\t\t\ts_out:\r
\t\t\tbegin\r
\t\t\t\tstate <= (cnt >= CLOCK_RATIO) ? s_idle : s_out;\r
\t\t\t\trecv_pulse_reg <= 1'b1;\r
\t\t\t\tSA_rest_reg <= SA_rest_temp_reg;\r
\t\t\t\tpace_en_reg <= pace_en_temp_reg;\r
\t\t\t\tAV_forw_reg <= AV_forw_temp_reg;\r
\t\t\t\tPACen_reg <= PACen_temp_reg;\r
\t\t\t\tPVCen_reg <= PVCen_temp_reg;\r
\t\t\t\tcnt <= cnt + 16'd1;\r
\t\t\t\tbyte_cnt <= 4'd0;\r
\t\t\tend\r
\t\tendcase\r
end\r
\t\t\t\r
\r
//////////// OUTPUT ASSIGNS ////////////\r
assign recv_pulse = recv_pulse_reg;\r
assign pace_en = pace_en_reg;\r
assign SA_rest = SA_rest_reg;\r
assign AV_forw = AV_forw_reg;\r
assign PACen = PACen_reg;\r
assign PVCen = PVCen_reg;\r
\r
endmodule\r
|
// RS-232 RX module\r
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006\r
\r
module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);\r
input clk, RxD;\r
output RxD_data_ready; // onc clock pulse when RxD_data is valid\r
output [7:0] RxD_data;\r
\r
parameter ClkFrequency = 50000000; // 50MHz\r
parameter Baud = 115200;\r
\r
// We also detect if a gap occurs in the received stream of characters\r
// That can be useful if multiple characters are sent in burst\r
// so that multiple characters can be treated as a "packet"\r
output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high)\r
output RxD_idle; // no data is being received\r
\r
// Baud generator (we use 8 times oversampling)\r
parameter Baud8 = Baud*8;\r
parameter Baud8GeneratorAccWidth = 16;\r
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);\r
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;\r
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;\r
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];\r
\r
////////////////////////////\r
reg [1:0] RxD_sync_inv;\r
always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};\r
// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup\r
\r
reg [1:0] RxD_cnt_inv;\r
reg RxD_bit_inv;\r
\r
always @(posedge clk)\r
if(Baud8Tick)\r
begin\r
\tif( RxD_sync_inv[1] && RxD_cnt_inv!=2\'b11) RxD_cnt_inv <= RxD_cnt_inv + 2\'h1;\r
\telse \r
\tif(~RxD_sync_inv[1] && RxD_cnt_inv!=2\'b00) RxD_cnt_inv <= RxD_cnt_inv - 2\'h1;\r
\r
\tif(RxD_cnt_inv==2\'b00) RxD_bit_inv <= 1\'b0;\r
\telse\r
\tif(RxD_cnt_inv==2\'b11) RxD_bit_inv <= 1\'b1;\r
end\r
\r
reg [3:0] state;\r
reg [3:0] bit_spacing;\r
\r
// "next_bit" controls when the data sampling occurs\r
// depending on how noisy the RxD is, different values might work better\r
// with a clean connection, values from 8 to 11 work\r
wire next_bit = (bit_spacing==4\'d10);\r
\r
always @(posedge clk)\r
if(state==0)\r
\tbit_spacing <= 4\'b0000;\r
else\r
if(Baud8Tick)\r
\tbit_spacing <= {bit_spacing[2:0] + 4\'b0001} | {bit_spacing[3], 3\'b000};\r
\r
always @(posedge clk)\r
if(Baud8Tick)\r
case(state)\r
\t4\'b0000: if(RxD_bit_inv) state <= 4\'b1000; // start bit found?\r
\t4\'b1000: if(next_bit) state <= 4\'b1001; // bit 0\r
\t4\'b1001: if(next_bit) state <= 4\'b1010; // bit 1\r
\t4\'b1010: if(next_bit) state <= 4\'b1011; // bit 2\r
\t4\'b1011: if(next_bit) state <= 4\'b1100; // bit 3\r
\t4\'b1100: if(next_bit) state <= 4\'b1101; // bit 4\r
\t4\'b1101: if(next_bit) state <= 4\'b1110; // bit 5\r
\t4\'b1110: if(next_bit) state <= 4\'b1111; // bit 6\r
\t4\'b1111: if(next_bit) state <= 4\'b0001; // bit 7\r
\t4\'b0001: if(next_bit) state <= 4\'b0000; // stop bit\r
\tdefault: state <= 4\'b0000;\r
endcase\r
\r
reg [7:0] RxD_data;\r
always @(posedge clk)\r
if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};\r
\r
reg RxD_data_ready, RxD_data_error;\r
always @(posedge clk)\r
begin\r
\tRxD_data_ready <= (Baud8Tick && next_bit && state==4\'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received\r
\tRxD_data_error <= (Baud8Tick && next_bit && state==4\'b0001 && RxD_bit_inv); // error if the stop bit is not received\r
end\r
\r
reg [4:0] gap_count;\r
always @(posedge clk) if (state!=0) gap_count<=5\'h00; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 5\'h01;\r
assign RxD_idle = gap_count[4];\r
reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==5\'h0F);\r
\r
endmodule
|
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode\r
// \r
// This file is part of PVS.\r
// \r
// PVS is free software: you can redistribute it and/or modify it under the\r
// terms of the GNU General Public License as published by the Free Software\r
// Foundation, either version 3 of the License, or (at your option) any later\r
// version.\r
// \r
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY\r
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR\r
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.\r
// \r
// You should have received a copy of the GNU General Public License along with\r
// PVS. If not, see <http://www.gnu.org/licenses/>.\r
\r
`timescale 1 ns / 1 ns\r
\r
// catches a pace and widens it using COUNT\r
\r
// inputs: \t\r
// clk_fast - rate to latch input signal\r
// clk_slow - rate to increment counter\r
//\tsignal_i - input signal\r
\r
// output:\t\r
//\tsignal_o - output signal\r
\r
// parameter: \r
// COUNT - counter val for width, default 15\r
\r
module pace_catcher\r
(\r
clk_fast,\r
\t\t\t clk_slow,\r
\t\t\t signal_i,\r
\t\t\t signal_o\r
);\r
\t\t\t \r
//////////// INPUTS & OUTPUTS ////////////\t \r
input clk_fast;\r
input clk_slow;\r
input signal_i;\r
output signal_o;\r
\t\t\t \r
//////////// PARAMETERS ////////////\r
parameter COUNT = 15; // with clk of 1.5kHz corresponds to 10ms width\r
\r
parameter s_idle = 0;\r
parameter s_out = 1;\r
\r
\r
//////////// SIGNALS & REGS ////////////\r
reg[15:0] cnt = 0;\r
reg state = 0;\r
\r
//////////// LOGIC ////////////\r
\r
// runs at fast clock to catch input signal\r
always @(posedge clk_fast) begin\r
\t\tcase(state)\r
\t\t\ts_idle:\r
\t\t\tbegin\r
\t\t\t\tstate <= (signal_i) ? s_out : s_idle;\r
\t\t\tend\r
\t\t\ts_out:\r
\t\t\tbegin\r
\t\t\t\tstate <= (cnt >= COUNT) ? s_idle : s_out;\r
\t\t\tend\r
\t\tendcase\r
end\r
\r
// runs at slow clock to increment slowly\r
always @(posedge clk_slow) begin\r
\t\tif (state == s_out) cnt <= cnt + 8'b1;\r
\t\telse if (state == s_idle) cnt <= 8'b0;\r
end\r
\r
//////////// OUTPUT ASSIGNS ////////////\r
assign signal_o = (state == s_out);\r
\r
endmodule\r
|
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode\r
// \r
// This file is part of PVS.\r
// \r
// PVS is free software: you can redistribute it and/or modify it under the\r
// terms of the GNU General Public License as published by the Free Software\r
// Foundation, either version 3 of the License, or (at your option) any later\r
// version.\r
// \r
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY\r
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR\r
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.\r
// \r
// You should have received a copy of the GNU General Public License along with\r
// PVS. If not, see <http://www.gnu.org/licenses/>.\r
\r
module TopLevel(\r
\r
\t//////////// CLOCK //////////\r
\tCLOCK_50,\r
\r
\t//////////// LED //////////\r
\tLED,\r
\r
\t//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////\r
\tPIN,\r
\tPIN_IN\r
);\r
\r
//=======================================================\r
// PARAMETER declarations\r
//=======================================================\r
\r
\r
//=======================================================\r
// PORT declarations\r
//=======================================================\r
\r
//////////// CLOCK //////////\r
input \t\t \t\tCLOCK_50;\r
\r
//////////// LED //////////\r
output\t\t [7:0]\t\tLED;\r
\r
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////\r
inout \t\t [33:0]\t\tPIN;\r
input \t\t [1:0]\t\tPIN_IN;\r
\r
//=======================================================\r
// REG/WIRE declarations\r
//=======================================================\r
wire CLOCK_1_5;\t// 1.5kHz clock (output of PLL0)\r
wire NA1out;\r
wire NA2out;\r
wire NA3out;\r
wire NA4out;\r
wire NA5out;\r
wire NA6out;\r
wire NA7out;\r
\r
wire NA1widened;\r
wire NA2widened;\r
wire NA3widened;\r
wire NA4widened;\r
wire NA5widened;\r
wire NA6widened;\r
wire NA7widened;\r
\r
wire pace_en;\r
wire apace_in;\r
wire vpace_in;\r
reg apace;\r
reg vpace;\r
wire apace_widened;\r
wire vpace_widened;\r
wire vhm_apace_input;\r
wire vhm_vpace_input;\r
reg apace_latch;\r
reg vpace_latch;\r
reg apace_latch_prev;\r
reg vpace_latch_prev;\r
\r
reg[31:0] counter = 32'd0;\r
reg tx_go;\r
reg tx_go_prev;\r
wire tx_go_shortened;\r
reg [7:0] header;\r
wire transmit_done;\r
wire tx;\r
\r
wire tachyLEDout;\r
wire bradyLEDout;\r
wire normalLEDout;\r
\r
wire rx;\r
wire recv_pulse;\r
wire [15:0] SA_rest;\r
wire [15:0] AV_forw;\r
wire PACen;\r
wire PVCen;\r
\r
//=======================================================\r
// Structural coding\r
//=======================================================\r
\r
// setup PLL for clock division\r
altpll0 pll0\r
\t(\r
\t.inclk0(CLOCK_50),\r
\t.c0(CLOCK_1_5)\r
\t);\r
\r
// setup VHM \r
case2mod_new heart\r
(\r
.clk(CLOCK_1_5),\r
\t\t\t .AP(vhm_apace_input),\r
\t\t .VP(vhm_vpace_input),\r
.SArest(SA_rest),\r
.AVforw(AV_forw), \r
.PAC_en(PACen),\r
.PVC_en(PVCen),\t\t\t \r
\t\t\t .clk_enable(1'b1),\r
.NA1Out(NA1out),\r
.NA2Out(NA2out),\r
.NA3Out(NA3out),\r
.NA4Out(NA4out),\r
.NA5Out(NA5out),\r
.NA6Out(NA6out),\r
.NA7Out(NA7out)\r
);\r
\t\t\r
\t\t \r
// widen NA1 pulse\t\r
output_pulse NA1_SA_pulse\r
(\r
.clk(CLOCK_1_5),\r
\t\t\t .signal_i(NA1out),\r
\t\t\t .signal_o(NA1widened),\r
);\r
\r
// widen NA2 pulse\t\r
output_pulse NA2_pulse\r
(\r
.clk(CLOCK_1_5),\r
\t\t\t .signal_i(NA2out),\r
\t\t\t .signal_o(NA2widened),\r
);\r
\t\t\t \r
// widen NA3 pulse\t\r
output_pulse NA3_pulse\r
(\r
.clk(CLOCK_1_5),\r
\t\t\t .signal_i(NA3out),\r
\t\t\t .signal_o(NA3widened),\r
);\r
\t\t\t \r
// widen NA4 pulse\t\r
output_pulse NA4_pulse\r
(\r
.clk(CLOCK_1_5),\r
\t\t\t .signal_i(NA4out),\r
\t\t\t .signal_o(NA4widened),\r
);\r
\t\t\t \r
// widen NA5 pulse\t\r
output_pulse NA5_pulse\r
(\r
.clk(CLOCK_1_5),\r
\t\t\t .signal_i(NA5out),\r
\t\t\t .signal_o(NA5widened),\r
);\r
\t\t\t \r
// widen NA6 pulse\t\r
output_pulse NA6_pulse\r
(\r
.clk(CLOCK_1_5),\r
\t\t\t .signal_i(NA6out),\r
\t\t\t .signal_o(NA6widened),\r
);\r
\t\t\t \r
// widen NA7 pulse\t\r
output_pulse NA7_pulse\r
(\r
.clk(CLOCK_1_5),\r
\t\t\t .signal_i(NA7out),\r
\t\t\t .signal_o(NA7widened),\r
);\r
\t\t\t \r
// counter increments every heart clk beat\r
always @(posedge CLOCK_1_5) begin\r
\tcounter <= counter + 32'd1;\r
end\r
\t\t\t \r
// set up clock serial transmitter for SA node & AP\r
// Note: NA1out and apace_widened are apparently\r
// exclusive, although this conclusion does not make sense.\r
// ANDing with tx_go_shortened makes sure the header is only\r
// available for 1 cycle\r
always @(posedge CLOCK_1_5) begin\r
\ttx_go <= (NA1out | NA3out | apace_latch | vpace_latch) && !tx_go_prev;\r
\theader <= (NA1out && !apace_latch) ? 8'd1 :\r
\t\t\t\t (!NA1out && apace_latch) ? 8'd2 :\r
\t\t\t\t (NA1out && apace_latch) ? 8'd3 :\r
\t\t\t\t (NA3out && !vpace_latch) ? 8'd4 :\r
\t\t\t\t (!NA3out && vpace_latch) ? 8'd5 :\r
\t\t\t\t (NA3out && vpace_latch) ? 8'd6 :\r
\t\t\t\t 8'd0;\r
\ttx_go_prev <= tx_go;\r
end\r
\r
// set up warning LED for brady/tachycardia\r
light_up warning_lighter\r
(\r
.clk(CLOCK_1_5),\r
\t\t\t .header(header),\r
\t\t\t .counter(counter),\r
\t\t\t .tachy_pin(tachyLEDout),\r
\t\t\t .brady_pin(bradyLEDout),\r
\t\t\t .normal_pin(normalLEDout)\r
);\t\t \r
\t\t\t \r
// shorten the go signal so it's 1 cycle in width\r
// this prevents simultaneous events of different\r
// widths from messing up serial\t\t\t\t\t \r
/*\r
rising_edge_detect go_shortener\r
\t\t\t\t(\r
\t\t\t\t .clk(CLOCK_1_5),\r
\t\t\t\t .signal(tx_go),\r
\t\t\t\t .pulse(tx_go_shortened)\r
\t\t\t\t);\r
*/\r
\t\t\t\t\t \r
clock_transmitter transmitter\r
(\r
.clk_fast(CLOCK_50),\r
\t\t\t .clk_slow(CLOCK_1_5),\r
\t\t\t .counter(counter),\r
\t\t\t .header(header),\r
.go(tx_go),//.go(tx_go_shortened),\r
\t\t\t .TxD(tx),\r
\t\t\t .done(transmit_done)\r
);\r
\t\r
// latch input pace pins with FF\r
always @(posedge CLOCK_50) begin\r
\tapace <= apace_in;\r
\tvpace <= vpace_in;\r
end\r
\r
// one cycle wide pace signals for serial\r
always @(posedge CLOCK_1_5) begin\r
\tapace_latch <= apace_widened && !apace_latch_prev && pace_en;\r
\tvpace_latch <= vpace_widened && !vpace_latch_prev && pace_en;\r
\tapace_latch_prev <= apace_latch;\r
\tvpace_latch_prev <= vpace_latch;\r
end\r
\r
// widen apace pulse\r
// the widen amount should be less than ERP\r
pace_catcher #(2) apace_widener\r
(\r
.clk_fast(CLOCK_50),\r
\t\t\t .clk_slow(CLOCK_1_5),\r
\t\t\t .signal_i(apace),\r
\t\t\t .signal_o(apace_widened),\r
);\r
\r
// widen vpace pulse\t\r
// the widen amount should be less than ERP \r
pace_catcher #(2) vpace_widener\r
(\r
.clk_fast(CLOCK_50),\r
\t\t\t .clk_slow(CLOCK_1_5),\r
\t\t\t .signal_i(vpace),\r
\t\t\t .signal_o(vpace_widened),\r
);\r
\t\t\r
// only give pace inputs if enabled\t\t\r
assign vhm_apace_input = apace_widened && pace_en;\r
assign vhm_vpace_input = vpace_widened && pace_en;\r
\t\t\t \r
mode_setter ms\r
(\r
.clk_fast(CLOCK_50),\r
\t\t\t .clk_slow(CLOCK_1_5),\r
\t\t\t .rx(rx),\r
\t\t\t .recv_pulse(recv_pulse),\r
\t\t\t .pace_en(pace_en),\r
\t\t\t .SA_rest(SA_rest),\r
\t\t\t .AV_forw(AV_forw),\r
\t\t\t .PACen(PACen),\r
\t\t\t .PVCen(PVCen)\r
);\r
\r
// assign LEDs\r
// LED[5..0]: NA6..1 widened\r
// LED[6]: toggles with serial reception\r
// LED[7]: toggles with serial transmission\r
reg LED7_toggle = 0; \r
always @(posedge CLOCK_50) begin\r
\tif (transmit_done) LED7_toggle <= LED7_toggle ^ 1;\r
end\r
assign LED[0] = apace_widened;\r
assign LED[1] = vpace_widened;\r
assign LED[2] = NA1widened;\r
assign LED[3] = NA2widened;\r
assign LED[4] = NA3widened;\r
assign LED[5] = NA7widened;\r
assign LED[6] = recv_pulse;\r
assign LED[7] = LED7_toggle;\r
\r
// assign pins\r
// PIN_IN[1..0]: vpace, apace\r
// PIN[0]: tx\r
// PIN[1]: rx\r
// PIN[10..4]: NA7..1 widened\r
assign apace_in = PIN_IN[0];\r
assign vpace_in = PIN_IN[1];\r
assign rx = PIN[0];\r
assign PIN[1] = tx;\r
assign PIN[4] = NA1widened;\r
assign PIN[5] = NA2widened; \r
assign PIN[6] = NA3widened;\r
assign PIN[7] = NA4widened; \r
assign PIN[8] = NA5widened;\r
assign PIN[9] = NA6widened; \t\r
assign PIN[10] = NA7widened;\r
\r
// warning indicators\r
assign PIN[16] = !normalLEDout; // active-low\r
assign PIN[18] = !bradyLEDout; // active-low\r
assign PIN[20] = !tachyLEDout; // active-low\r
\r
// debug signals\r
assign PIN[22] = tx_go;\r
assign PIN[24] = CLOCK_1_5;\r
assign PIN[26] = NA1out;\r
assign PIN[28] = apace_latch;\r
assign PIN[30] = NA3out;\r
assign PIN[32] = vpace_latch;\r
endmodule\r
|
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode\r
// \r
// This file is part of PVS.\r
// \r
// PVS is free software: you can redistribute it and/or modify it under the\r
// terms of the GNU General Public License as published by the Free Software\r
// Foundation, either version 3 of the License, or (at your option) any later\r
// version.\r
// \r
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY\r
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR\r
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.\r
// \r
// You should have received a copy of the GNU General Public License along with\r
// PVS. If not, see <http://www.gnu.org/licenses/>.\r
\r
`timescale 1 ns / 1 ns\r
\r
// Widens the output signal using COUNT\r
\r
// inputs: \t\r
// CLK\r
\r
\r
// output:\t\r
\r
// parameter: \r
// HIGH_PERIOD \r
\r
module led_flasher\r
(\r
clk,\r
\t\t\t LED_flash,\r
\t\t\t LED_out\r
);\r
\t\t\t \r
//////////// INPUTS & OUTPUTS ////////////\t \r
input clk;\r
input LED_flash;\r
output LED_out;\r
\t\t\t \r
//////////// PARAMETERS ////////////\r
parameter HIGH_PERIOD = 600; // with clk of 1.5kHz corresponds to 400ms width\r
parameter LOW_PERIOD = 600; // with clk of 1.5kHz corresponds to 400ms width\r
\r
parameter s_reset = 2'd0;\r
parameter s_off = 2'd1;\r
parameter s_on = 2'd2;\r
\r
\r
//////////// SIGNALS & REGS ////////////\r
reg[15:0] cnt = 0;\r
reg [1:0] state = 2'd0;\r
\r
//////////// LOGIC ////////////\r
always @(posedge clk) begin\r
\t\tcase(state)\r
\t\t\ts_reset:\r
\t\t\t\tbegin\r
\t\t\t\t\tcnt <= 16'd0;\r
\t\t\t\t\tstate <= (LED_flash) ? s_on : s_reset;\r
\t\t\t\tend\r
\t\t\t\r
\t\t\ts_off: \r
\t\t\t\tbegin\r
\t\t\t\t\tstate <= (cnt == LOW_PERIOD && LED_flash) ? s_on : \r
\t\t\t\t\t\t\t\t(!LED_flash) ? s_reset : \r
\t\t\t\t\t\t\t\ts_off;\r
\t\t\t\t\tcnt <= (cnt == LOW_PERIOD && LED_flash) ? 16'd0 : cnt + 16'd1;\r
\t\t\t\tend\r
\t\t\t\r
\t\t\ts_on: \r
\t\t\t\tbegin\r
\t\t\t\t\tstate <= (cnt == HIGH_PERIOD && LED_flash) ? s_off : \r
\t\t\t\t\t\t\t\t(!LED_flash) ? s_reset : \r
\t\t\t\t\t\t\t\ts_on;\r
\t\t\t\t\tcnt <= (cnt == HIGH_PERIOD && LED_flash) ? 16'd0 : cnt + 16'd1;\r
\t\t\t\tend\r
\t\tendcase\r
end\r
\r
//////////// OUTPUT ASSIGNS ////////////\r
assign LED_out = (state == s_on);\r
\r
endmodule\r
|
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode\r
// \r
// This file is part of PVS.\r
// \r
// PVS is free software: you can redistribute it and/or modify it under the\r
// terms of the GNU General Public License as published by the Free Software\r
// Foundation, either version 3 of the License, or (at your option) any later\r
// version.\r
// \r
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY\r
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR\r
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.\r
// \r
// You should have received a copy of the GNU General Public License along with\r
// PVS. If not, see <http://www.gnu.org/licenses/>.\r
\r
`timescale 1 ns / 1 ns\r
\r
// Transmits a 4-byte internal counter value using Serial I/O\r
\r
// inputs: \t\r
// clk_fast - 50MHz fast clock for serial I/O\r
//\tclk_slow - speed for counter to increment, and transmission interval\r
// counter - 4-byte counter to transmit\r
// header - 8-bit header byte for identification\r
// go - when to transmit (gets latched)\r
\r
// outputs:\t\r
//\tTxD - output serial transmission\r
// done - goes high when complete (width of clk_slow period)\r
\r
module clock_transmitter\r
(\r
clk_fast,\r
\t\t\t clk_slow,\r
\t\t\t counter,\r
\t\t\t header,\r
go,\r
\t\t\t TxD,\r
\t\t\t done\r
);\r
\t\t\t \r
input clk_fast;\r
input clk_slow;\r
input [31:0] counter;\r
input [7:0] header;\r
input go;\r
output TxD;\r
output done;\r
\r
parameter s_idle = 0;\r
parameter s_transmit_tx = 1;\r
parameter s_transmit_wait = 2;\r
parameter s_inc_byte = 3;\r
parameter s_finish = 4;\r
\r
reg[3:0] state = 4\'d0;\r
reg[7:0] data = 8\'d0;\r
reg[3:0] byte_count = 4\'d0;\r
\r
reg go_reg = 1\'b0;\r
reg go_reg_prev = 1\'b0;\r
reg [7:0] header_reg = 8\'d0;\r
reg [31:0] transmit_buf = 8\'d0;\r
wire tx_start_pulse;\r
reg tx_start = 1\'b0;\r
wire tx_busy;\r
wire tx_out;\r
\r
// need these "one pulses" to ensure\r
// transmitter is only started once during wait period\r
rising_edge_detect tx_detect\r
(\r
.clk(clk_fast),\r
.signal(tx_start),\r
.pulse(tx_start_pulse)\r
);\r
\r
// state machine:\r
// sits at idle until receives \'go\'\r
// starts transmitting, then waits for transmission to complete\r
// transmits next 8-bits\r
// continues until 32 bits transmitted\r
always @(posedge clk_slow) begin\r
\tcase(state)\r
\t\ts_idle:\r
\t\tbegin\r
\t\t\tgo_reg <= go & !go_reg_prev;\r
\t\t\t// hold onto header throughout transmission; reset in s_finish\r
\t\t\tif (header_reg == 8\'d0) header_reg <= header;\r
\t\t\tstate <= (go_reg) ? s_transmit_tx : s_idle;\r
\t\t\ttransmit_buf <= (go_reg) ? counter : 32\'d0;\r
\t\t\tbyte_count <= 4\'d0;\r
\t\t\tgo_reg_prev <= go_reg;\r
\t\tend\r
\t\t\t\r
\t\ts_transmit_tx: \r
\t\tbegin\r
\t\t\ttx_start <= (byte_count < 4\'d5); \r
\t\t\tdata <= (byte_count == 4\'d0) ? header_reg :\r
\t\t\t\t\t (byte_count == 4\'d1) ? transmit_buf[7:0] :\r
\t\t\t\t\t (byte_count == 4\'d2) ? transmit_buf[15:8] :\r
\t\t\t\t\t (byte_count == 4\'d3) ? transmit_buf[23:16] :\r
\t\t\t\t\t (byte_count == 4\'d4) ? transmit_buf[31:24] :\r
\t\t\t\t\t 8\'b0;\r
\t\t\tstate <= (byte_count < 4\'d5) ? s_transmit_wait : s_finish;\r
\t\tend\r
\t\t\r
\t\ts_transmit_wait: \r
\t\tbegin\r
\t\t\tstate <= (tx_busy) ? s_transmit_wait : s_inc_byte;\r
\t\t\ttx_start <= 0;\r
\t\tend\r
\t\t\t\t\t\r
\t\ts_inc_byte:\r
\t\tbegin\r
\t\t\tbyte_count <= byte_count + 4\'b1;\r
\t\t\tstate <= s_transmit_tx;\r
\t\tend\r
\t\t\r
\t\ts_finish:\r
\t\tbegin\r
\t\t\tstate <= s_idle;\r
\t\t\theader_reg <= 8\'b0;\r
\t\tend\r
\tendcase\r
end\r
\r
// declare transmitter\r
async_transmitter tx\r
\t(\r
\t.clk(clk_fast), \r
\t.TxD_start(tx_start_pulse), \r
\t.TxD_data(data), \r
\t.TxD(tx_out), \r
\t.TxD_busy(tx_busy)\r
\t);\r
\t\t\r
// assign outputs\r
assign done = (state == s_finish);\r
reg TxD;\r
always @(posedge clk_fast)\r
\t\tTxD <= (tx_busy) ? tx_out : 1\'b1;\r
\t\t\t \r
endmodule\r
|
// RS-232 TX module\r
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006\r
\r
//`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations)\r
\r
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);\r
input clk, TxD_start;\r
input [7:0] TxD_data;\r
output TxD, TxD_busy;\r
\r
parameter ClkFrequency = 50000000;\t// 50MHz\r
parameter Baud = 115200;\r
parameter RegisterInputData = 1;\t// in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted\r
\r
// Baud generator\r
parameter BaudGeneratorAccWidth = 16;\r
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;\r
`ifdef DEBUG\r
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h10000;\r
`else\r
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);\r
`endif\r
\r
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];\r
wire TxD_busy;\r
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;\r
\r
// Transmitter state machine\r
reg [3:0] state;\r
wire TxD_ready = (state==0);\r
assign TxD_busy = ~TxD_ready;\r
\r
reg [7:0] TxD_dataReg;\r
always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <= TxD_data;\r
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;\r
\r
always @(posedge clk)\r
case(state)\r
\t4'b0000: if(TxD_start) state <= 4'b0001;\r
\t4'b0001: if(BaudTick) state <= 4'b0100;\r
\t4'b0100: if(BaudTick) state <= 4'b1000; // start\r
\t4'b1000: if(BaudTick) state <= 4'b1001; // bit 0\r
\t4'b1001: if(BaudTick) state <= 4'b1010; // bit 1\r
\t4'b1010: if(BaudTick) state <= 4'b1011; // bit 2\r
\t4'b1011: if(BaudTick) state <= 4'b1100; // bit 3\r
\t4'b1100: if(BaudTick) state <= 4'b1101; // bit 4\r
\t4'b1101: if(BaudTick) state <= 4'b1110; // bit 5\r
\t4'b1110: if(BaudTick) state <= 4'b1111; // bit 6\r
\t4'b1111: if(BaudTick) state <= 4'b0010; // bit 7\r
\t4'b0010: if(BaudTick) state <= 4'b0000; // stop1\r
\t//4'b0011: if(BaudTick) state <= 4'b0000; // stop2\r
\tdefault: if(BaudTick) state <= 4'b0000;\r
endcase\r
\r
// Output mux\r
reg muxbit;\r
always @( * )\r
case(state[2:0])\r
\t3'd0: muxbit <= TxD_dataD[0];\r
\t3'd1: muxbit <= TxD_dataD[1];\r
\t3'd2: muxbit <= TxD_dataD[2];\r
\t3'd3: muxbit <= TxD_dataD[3];\r
\t3'd4: muxbit <= TxD_dataD[4];\r
\t3'd5: muxbit <= TxD_dataD[5];\r
\t3'd6: muxbit <= TxD_dataD[6];\r
\t3'd7: muxbit <= TxD_dataD[7];\r
endcase\r
\r
// Put together the start, data and stop bits\r
reg TxD;\r
always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free\r
\r
endmodule
|
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode\r
// \r
// This file is part of PVS.\r
// \r
// PVS is free software: you can redistribute it and/or modify it under the\r
// terms of the GNU General Public License as published by the Free Software\r
// Foundation, either version 3 of the License, or (at your option) any later\r
// version.\r
// \r
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY\r
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR\r
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.\r
// \r
// You should have received a copy of the GNU General Public License along with\r
// PVS. If not, see <http://www.gnu.org/licenses/>.\r
\r
`timescale 1 ns / 1 ns\r
\r
// Widens the output signal using COUNT\r
\r
// inputs: \t\r
// CLK\r
\r
\r
// output:\t\r
\r
// parameter: \r
// HIGH_PERIOD \r
\r
module light_up\r
(\r
clk,\r
\t\t\t header,\r
\t\t\t counter,\r
\t\t\t tachy_pin,\r
\t\t\t brady_pin,\r
\t\t\t normal_pin\r
);\r
\t\t\t \r
//////////// INPUTS & OUTPUTS ////////////\t \r
input clk;\r
input[7:0] header;\r
input[31:0] counter;\r
output tachy_pin;\r
output brady_pin;\r
output normal_pin;\r
\t\t\t \r
//////////// PARAMETERS ////////////\r
\r
parameter FAST_BEAT = 32'd750; // with clk of 1.5kHz corresponds to 120 beats per minute\r
parameter SLOW_BEAT = 32'd1800; // with clk of 1.5kHz corresponds to 50 beats per minute \r
parameter CORRECT_HEAD1 = 8'd4; // RV & !vp\r
parameter CORRECT_HEAD2 = 8'd6; // RV & vp\r
\r
//////////// SIGNALS & REGS ////////////\r
\r
reg brady_flash;\r
reg tachy_flash;\r
reg[31:0] counter_previous;\r
\r
wire[31:0] difference; \r
wire correct_header;\r
wire too_fast;\r
wire too_slow;\r
\r
//////////// LOGIC ////////////\r
assign correct_header = (header == CORRECT_HEAD1 || header == CORRECT_HEAD2);\r
assign difference = counter - counter_previous;\r
assign too_fast = difference <= FAST_BEAT;\r
assign too_slow = difference >= SLOW_BEAT;\r
\r
always @(posedge clk) begin\r
\tif (correct_header) begin\r
\t\ttachy_flash <= too_fast;\r
\t\tbrady_flash <= too_slow;\r
\t\tcounter_previous <= counter;\r
\tend\r
end\r
\r
led_flasher tachy_flasher\r
(\r
.clk(clk),\r
\t\t\t .LED_flash(tachy_flash),\r
\t\t\t .LED_out(tachy_pin)\r
);\r
\t\t\t \r
led_flasher brady_flasher\r
(\r
.clk(clk),\r
\t\t\t .LED_flash(brady_flash),\r
\t\t\t .LED_out(brady_pin)\r
);\r
\t\t\t \r
//////////// OUTPUT ASSIGNS ////////////\r
assign normal_pin = !tachy_flash && !brady_flash;\r
\r
endmodule\r
|
// megafunction wizard: %ALTPLL%\r
// GENERATION: STANDARD\r
// VERSION: WM1.0\r
// MODULE: altpll \r
\r
// ============================================================\r
// File Name: altpll0.v\r
// Megafunction Name(s):\r
// \t\t\taltpll\r
//\r
// Simulation Library Files(s):\r
// \t\t\taltera_mf\r
// ============================================================\r
// ************************************************************\r
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
//\r
// 11.1 Build 173 11/01/2011 SJ Web Edition\r
// ************************************************************\r
\r
\r
//Copyright (C) 1991-2011 Altera Corporation\r
//Your use of Altera Corporation\'s design tools, logic functions \r
//and other software and tools, and its AMPP partner logic \r
//functions, and any output files from any of the foregoing \r
//(including device programming or simulation files), and any \r
//associated documentation or information are expressly subject \r
//to the terms and conditions of the Altera Program License \r
//Subscription Agreement, Altera MegaCore Function License \r
//Agreement, or other applicable license agreement, including, \r
//without limitation, that your use is for the sole purpose of \r
//programming logic devices manufactured by Altera and sold by \r
//Altera or its authorized distributors. Please refer to the \r
//applicable agreement for further details.\r
\r
\r
// synopsys translate_off\r
`timescale 1 ps / 1 ps\r
// synopsys translate_on\r
module altpll0 (\r
\tinclk0,\r
\tc0);\r
\r
\tinput\t inclk0;\r
\toutput\t c0;\r
\r
\twire [4:0] sub_wire0;\r
\twire [0:0] sub_wire4 = 1\'h0;\r
\twire [0:0] sub_wire1 = sub_wire0[0:0];\r
\twire c0 = sub_wire1;\r
\twire sub_wire2 = inclk0;\r
\twire [1:0] sub_wire3 = {sub_wire4, sub_wire2};\r
\r
\taltpll\taltpll_component (\r
\t\t\t\t.inclk (sub_wire3),\r
\t\t\t\t.clk (sub_wire0),\r
\t\t\t\t.activeclock (),\r
\t\t\t\t.areset (1\'b0),\r
\t\t\t\t.clkbad (),\r
\t\t\t\t.clkena ({6{1\'b1}}),\r
\t\t\t\t.clkloss (),\r
\t\t\t\t.clkswitch (1\'b0),\r
\t\t\t\t.configupdate (1\'b0),\r
\t\t\t\t.enable0 (),\r
\t\t\t\t.enable1 (),\r
\t\t\t\t.extclk (),\r
\t\t\t\t.extclkena ({4{1\'b1}}),\r
\t\t\t\t.fbin (1\'b1),\r
\t\t\t\t.fbmimicbidir (),\r
\t\t\t\t.fbout (),\r
\t\t\t\t.fref (),\r
\t\t\t\t.icdrclk (),\r
\t\t\t\t.locked (),\r
\t\t\t\t.pfdena (1\'b1),\r
\t\t\t\t.phasecounterselect ({4{1\'b1}}),\r
\t\t\t\t.phasedone (),\r
\t\t\t\t.phasestep (1\'b1),\r
\t\t\t\t.phaseupdown (1\'b1),\r
\t\t\t\t.pllena (1\'b1),\r
\t\t\t\t.scanaclr (1\'b0),\r
\t\t\t\t.scanclk (1\'b0),\r
\t\t\t\t.scanclkena (1\'b1),\r
\t\t\t\t.scandata (1\'b0),\r
\t\t\t\t.scandataout (),\r
\t\t\t\t.scandone (),\r
\t\t\t\t.scanread (1\'b0),\r
\t\t\t\t.scanwrite (1\'b0),\r
\t\t\t\t.sclkout0 (),\r
\t\t\t\t.sclkout1 (),\r
\t\t\t\t.vcooverrange (),\r
\t\t\t\t.vcounderrange ());\r
\tdefparam\r
\t\taltpll_component.bandwidth_type = "AUTO",\r
\t\taltpll_component.clk0_divide_by = 100000,\r
\t\taltpll_component.clk0_duty_cycle = 50,\r
\t\taltpll_component.clk0_multiply_by = 3,\r
\t\taltpll_component.clk0_phase_shift = "0",\r
\t\taltpll_component.compensate_clock = "CLK0",\r
\t\taltpll_component.inclk0_input_frequency = 20000,\r
\t\taltpll_component.intended_device_family = "Cyclone IV E",\r
\t\taltpll_component.lpm_hint = "CBX_MODULE_PREFIX=altpll0",\r
\t\taltpll_component.lpm_type = "altpll",\r
\t\taltpll_component.operation_mode = "NORMAL",\r
\t\taltpll_component.pll_type = "AUTO",\r
\t\taltpll_component.port_activeclock = "PORT_UNUSED",\r
\t\taltpll_component.port_areset = "PORT_UNUSED",\r
\t\taltpll_component.port_clkbad0 = "PORT_UNUSED",\r
\t\taltpll_component.port_clkbad1 = "PORT_UNUSED",\r
\t\taltpll_component.port_clkloss = "PORT_UNUSED",\r
\t\taltpll_component.port_clkswitch = "PORT_UNUSED",\r
\t\taltpll_component.port_configupdate = "PORT_UNUSED",\r
\t\taltpll_component.port_fbin = "PORT_UNUSED",\r
\t\taltpll_component.port_inclk0 = "PORT_USED",\r
\t\taltpll_component.port_inclk1 = "PORT_UNUSED",\r
\t\taltpll_component.port_locked = "PORT_UNUSED",\r
\t\taltpll_component.port_pfdena = "PORT_UNUSED",\r
\t\taltpll_component.port_phasecounterselect = "PORT_UNUSED",\r
\t\taltpll_component.port_phasedone = "PORT_UNUSED",\r
\t\taltpll_component.port_phasestep = "PORT_UNUSED",\r
\t\taltpll_component.port_phaseupdown = "PORT_UNUSED",\r
\t\taltpll_component.port_pllena = "PORT_UNUSED",\r
\t\taltpll_component.port_scanaclr = "PORT_UNUSED",\r
\t\taltpll_component.port_scanclk = "PORT_UNUSED",\r
\t\taltpll_component.port_scanclkena = "PORT_UNUSED",\r
\t\taltpll_component.port_scandata = "PORT_UNUSED",\r
\t\taltpll_component.port_scandataout = "PORT_UNUSED",\r
\t\taltpll_component.port_scandone = "PORT_UNUSED",\r
\t\taltpll_component.port_scanread = "PORT_UNUSED",\r
\t\taltpll_component.port_scanwrite = "PORT_UNUSED",\r
\t\taltpll_component.port_clk0 = "PORT_USED",\r
\t\taltpll_component.port_clk1 = "PORT_UNUSED",\r
\t\taltpll_component.port_clk2 = "PORT_UNUSED",\r
\t\taltpll_component.port_clk3 = "PORT_UNUSED",\r
\t\taltpll_component.port_clk4 = "PORT_UNUSED",\r
\t\taltpll_component.port_clk5 = "PORT_UNUSED",\r
\t\taltpll_component.port_clkena0 = "PORT_UNUSED",\r
\t\taltpll_component.port_clkena1 = "PORT_UNUSED",\r
\t\taltpll_component.port_clkena2 = "PORT_UNUSED",\r
\t\taltpll_component.port_clkena3 = "PORT_UNUSED",\r
\t\taltpll_component.port_clkena4 = "PORT_UNUSED",\r
\t\taltpll_component.port_clkena5 = "PORT_UNUSED",\r
\t\taltpll_component.port_extclk0 = "PORT_UNUSED",\r
\t\taltpll_component.port_extclk1 = "PORT_UNUSED",\r
\t\taltpll_component.port_extclk2 = "PORT_UNUSED",\r
\t\taltpll_component.port_extclk3 = "PORT_UNUSED",\r
\t\taltpll_component.width_clock = 5;\r
\r
\r
endmodule\r
\r
// ============================================================\r
// CNX file retrieval info\r
// ============================================================\r
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"\r
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"\r
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"\r
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"\r
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"\r
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"\r
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"\r
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"\r
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"\r
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"\r
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"\r
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"\r
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"\r
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"\r
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"\r
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"\r
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"\r
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"\r
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.001500"\r
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"\r
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"\r
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"\r
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"\r
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"\r
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"\r
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"\r
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"\r
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"\r
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"\r
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"\r
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"\r
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"\r
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"\r
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"\r
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"\r
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"\r
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"\r
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"\r
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"\r
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"\r
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"\r
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"\r
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"\r
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.00150000"\r
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"\r
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"\r
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"\r
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"\r
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"\r
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"\r
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"\r
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"\r
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"\r
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"\r
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"\r
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"\r
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"\r
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"\r
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"\r
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"\r
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"\r
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"\r
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"\r
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"\r
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"\r
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"\r
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"\r
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"\r
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"\r
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"\r
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"\r
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"\r
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"\r
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"\r
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"\r
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"\r
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"\r
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"\r
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"\r
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"\r
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"\r
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "100000"\r
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"\r
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"\r
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"\r
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"\r
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"\r
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"\r
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"\r
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"\r
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"\r
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"\r
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"\r
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"\r
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"\r
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"\r
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"\r
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"\r
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\r
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\r
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\r
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.v TRUE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.v FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_bb.v FALSE\r
// Retrieval info: LIB_FILE: altera_mf\r
// Retrieval info: CBX_MODULE_PREFIX: ON\r
|
// Filename: channel_tb2.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Module connecting transmit to receive. This uses a clock of
// \t\t\t\tinsufficent period to ensure that the parity gen cant keep up.
`timescale 1ns/100ps
module channel_tb2();
\treg enable;\t\t\t\t// Enable for counter
\treg clear;\t\t\t\t// Clear for counter
\treg clk_en;\t\t\t\t// Clock enable
\twire clk;\t\t\t\t// Wire connecting clock to counter and both regs
\twire[9:0] data;\t\t\t// Bus connecting transmit and receive modules
\twire[8:0] data_out;\t\t// Data output of receive
\twire data_valid;\t\t// Output of comparator from receive module
\t// Transmit module containing counter and parity gen.
\ttransmit DUT1(enable, clear, clk, data);
\t// Receive module containing reg, parity gen, and comparator
\treceive DUT2(clk, data, data_out, data_valid);
\t// Clock feeding counter and both regs, period set to 10
\tclk #(17) DUT3(clk_en, clk);
\t// Using similar inputs as ctr_tb.v
\tinitial begin
\t\tenable = 0;
\t\tclear = 0;
\t\tclk_en = 1;
\t\t//#10 clear = 1;
\t\t//#40 clear = 0;
\t\t#50 enable = 1;
\t\t//#400 enable = 0;
\t\t//#100 enable = 1;
\t\t//#500 clear = 1;
\t\t//#60 clear = 0;
\tend
endmodule
|
// Filename: receive.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Module that receives a 10-bit bus which is fed into a register.
//\t\t\t\tThis data is also fed into a 9-bit parity generator. The ODD ouput
//\t\t\t\tis compared to the 10th data bit which is an even parity bit.
module receive(clk, data_in, data_out, data_valid);
\tinput clk;\t\t\t\t// Clock to be generated in test bench with clk module
\tinput[9:0] data_in;\t\t// Data coming from transmit, into reg and parity gen
\toutput[8:0] data_out;\t// 9-bit bus coming out of reg
\toutput data_valid;\t\t// Output of comparator
\twire[8:0] data_out;
\twire data_valid;
\twire odd_in;\t\t\t// Even parity bit going to comparator
\twire odd, even;\t\t\t// Outputs of parity generator
\t// 10-bit register
\t// Input from transmit module, output goes to output, parity gen, and comparator
\tregister_10bit U4(clk, data_in, {odd_in, data_out});
\t// 9-bit parity generator
\t// Input from data_out, output to comparator
\thc280 U5(data_out, even, odd);
\t// Parity bit comparator (XNOR gate). Since the hc280 outputs high on odd when
\t// there is an odd number of 1s in its input, this odd output is used as an even
\t// parity bit (odd number of 1s plus another 1 = even number of ones). So XNOR is
\t// used to check if there is either an odd number of ones and a high even parity
\t// bit or an even number of ones and a low even parity bit.
\txnor U6(data_valid, odd, odd_in);
endmodule
|
// Filename: hc280_tb.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Test bench for 9-bit odd/even parity generator/checker
`timescale 1ns/100ps
module hc280_tb();
\treg enable;\t\t\t\t\t\t//Enable for counter
\treg clr;\t\t\t\t\t\t//Clear signal for counter
\treg clk_en;\t\t\t\t\t\t//Enable for clock
\twire clk;\t\t\t\t\t\t//Output of clock
\twire[8:0] count;\t\t\t\t//Output of counter, goes to hc280 as input
\twire sigma_even, sigma_odd;\t\t//Output of hc280
\t// Parity generator/checker
\thc280 DUT1(count, sigma_even, sigma_odd);
\t// 9-bit counter feeding into parity bit generator
\tcounter_9bit DUT2(enable, clr, clk, count);
\t// Clock feeding into counter
\tclk DUT3(clk_en, clk);
\t// Using similar inputs as ctr_tb.v
\tinitial begin
\t\tenable = 0;
\t\tclr = 0;
\t\tclk_en = 1;
\t\t#10 clr = 1;
\t\t#40 clr = 0;
\t\t#50 enable = 1;
\t\t#400 enable = 0;
\t\t#100 enable = 1;
\t\t#500 clr = 1;
\t\t#60 clr = 0;
\tend
endmodule
|
// Filename: transmit.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Module containing a counter feeding into a 9-bit parity generator
//\t\t\t\tand 10-bit register. The even parity bit is also fed into the reg.
module transmit(enable, clear, clk, data_out);
\tinput enable;\t\t\t// Counter input which pauses counter
\tinput clear;\t\t\t// Counter input which resets count to zero
\tinput clk;\t\t\t\t// Clock to be generated in test bench with clk module
\toutput[9:0] data_out;\t// Output of register
\twire[9:0] data_out;
\twire[8:0] count;\t\t// Output of counter
\twire even, odd;\t\t\t// Output of parity generator
\t// 9-bit counter
\tcounter_9bit U1(enable, clear, clk, count);
\t// Parity generator that counts up number of 1s and if odd, is high on odd output.
\thc280 U2(count, even, odd);
\t// Since the hc280's odd output is used, this will be an even parity bit fed into
\t// the register along with the counter output.
\tregister_10bit U3(clk, {odd, count}, data_out);
endmodule
|
// Filename: hc280.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: 9-bit odd/even parity generator/checker
`timescale 1 ns/100 ps
module hc280(data_in, sigma_even, sigma_odd);
\tinput [8:0] data_in;
\toutput sigma_even, sigma_odd;
\treg sigma_even, sigma_odd;
\t// Typical propagation delays at 25C, 4.5V for 74HC280
\tspecify
\t\t(data_in *> sigma_even, sigma_odd) = (20,23);
\tendspecify
\t// On change of data_in, find parity bits
\talways @(data_in) begin
\t\tsigma_even = ~^data_in;
\t\tsigma_odd = ^data_in;
\tend
endmodule
|
// Filename: channel_tb1.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Module connecting transmit to receive. This uses a clock of
// \t\t\t\tsufficent period to ensure that the parity gen can keep up.
`timescale 1ns/100ps
module channel_tb1();
\treg enable;\t\t\t\t// Enable for counter
\treg clear;\t\t\t\t// Clear for counter
\treg clk_en;\t\t\t\t// Clock enable
\twire clk;\t\t\t\t// Wire connecting clock to counter and both regs
\twire[9:0] data;\t\t\t// Bus connecting transmit and receive modules
\twire[8:0] data_out;\t\t// Data output of receive
\twire data_valid;\t\t// Output of comparator from receive module
\t// Transmit module containing counter and parity gen.
\ttransmit DUT1(enable, clear, clk, data);
\t// Receive module containing reg, parity gen, and comparator
\treceive DUT2(clk, data, data_out, data_valid);
\t// Clock feeding counter and both regs, period set to 100
\tclk #(100) DUT3(clk_en, clk);
\t// Using similar inputs as ctr_tb.v
\tinitial begin
\t\tenable = 0;
\t\tclear = 0;
\t\tclk_en = 1;
\t\t#10 clear = 1;
\t\t#40 clear = 0;
\t\t#50 enable = 1;
\t\t#400 enable = 0;
\t\t#100 enable = 1;
\t\t#500 clear = 1;
\t\t#60 clear = 0;
\tend
endmodule
|
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