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// Filename: register_10bit.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: 10-bit bus interface register.
module register_10bit(clk, d_in, q_out);
\tinput clk;
\tinput [9:0] d_in;
\toutput[9:0] q_out;
\treg[9:0] q_out;
\t// Set input to output on rising edge clock
\talways @(posedge clk) begin
\t\tq_out = d_in;
\tend
endmodule
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////////////////////////////////////////////////////////////////////////////////////////////////////
// Filename: counter_9bit.v
// Author: T. Martin, Danny Dutton
// Date: 09/07/04
// Version: 4
// Description: This module is a behavioral description of a nine-bit counter with enable and
// asynchronous clear.
//
// \t\t This module has three inputs and one output:
//\t\t
// clk: (input) system clock
//\t\t clear:\t (input) active-high asynchronous clear
// enable: (input) count advances when asserted high
// cout:\t (output) 9-bit counter output
//
// This module has two parameters:
//
// CLRDEL: delay from clear asserted to output valid
// CLKDEL: delay from clk rising to output valid
//
// This module is not synthesizable. It is intended for modeling only and should not
// be used as a template for synthesizable modules.
//
// Modification History:
// Date By Version Change Description
// ========================================================
// 09/07/2004\tTLM 1 Original
// 08/24/2005\tPMA 2 Restructured for Fall 2005
// 10/03/2013\tTLM 3 Revised for DD 1, Fall 2013
//\t03/23/2015 \tDJD\t 4 \t\t Modified for 9-bit counter
`timescale 1 ns/100 ps
module counter_9bit (enable, clear, clk, cout);
\tparameter CLRDEL = 10;\t// delay from clear asserted to output valid
\tparameter CLKDEL = 15;\t// delay from clk rising to output valid
\tinput enable;\t\t// count advances when asserted high
\tinput clear;\t\t// asynchronous clear (active high)
\tinput clk;\t\t\t// system clock
\toutput [8:0] cout;\t// 9-bit counter output
\treg [8:0] cout;\t\t// cout is a reg
\t// Locally declared nets
\treg [8:0] count;\t// local count holder register
\tinitial count = 0;
\t// Build behavioral 4-bit up-counter with asynchronous clear
\talways @(posedge clk or clear) begin
\t\tif (clear == 1) begin
\t\t\tcount = 9'b0;
\t\t\tcout = #CLRDEL count;
\t\tend
\t\telse if (clk == 1) begin
\t\t\tif (enable == 1) begin
\t\t\t\tif (count == 9'd15) begin
\t\t\t\t\tcount = 0;
\t\t\t\tend
\t\t\t\telse begin
\t\t\t\t\tcount = count + 9'd1;
\t\t\t\tend
\t\t\tend\t
\t\t\tcout = #CLKDEL count;
\t\tend
\tend
endmodule
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// Filename: register_10bit_tb.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Test bench for 10-bit register
`timescale 1ns/100ps
module register_10bit_tb();
\treg clk_en;
\treg[9:0] data_in;
\twire[9:0] data_out;
\twire clk;
\tregister_10bit DUT1(clk, data_in, data_out);
\tclk DUT2(clk_en, clk);
\tinitial begin
\t\tclk_en = 1;
\t\tdata_in = 0;
\t\t#85 data_in = 10'd1;
\t\t#50 data_in = 10'd2;
\t\t#50 data_in = 10'd4;
\t\t#50 data_in = 10'd8;
\t\t#50 data_in = 10'd16;
\t\t#50 data_in = 10'd32;
\t\t#50 data_in = 10'd64;
\t\t#50 data_in = 10'd128;
\t\t#50 data_in = 10'd256;
\t\t#50 data_in = 10'd512;
\t\t#50 data_in = 10'd0;
\tend
endmodule
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`timescale 1ns / 1ps\r
\r
module Controlador_Menu_Editor(\r
\t\r
\tclk, \r
\treset,\r
\t\r
\tboton_arriba_in,\r
\tboton_abajo_in,\r
\tboton_izq_in,\r
\tboton_der_in,\r
\tboton_elige_in,\r
\t//boton_arriba, boton_abajo, boton_izq, boton_der, boton_elige,\r
\t\r
\ttext_red,\r
\ttext_green,\r
\ttext_blue,\r
\tchar_scale,\r
\tes_mayuscula,
\t
\ttext_red_temp,\r
\ttext_green_temp,\r
\ttext_blue_temp,\r
\tchar_scale_temp,\r
\tes_mayuscula_temp,\r
\t\r
\tnuevo,\r
\tguardar,\r
\tcerrar,\r
\t\r
\twhere_fila,\r
\twhere_columna\r
);\r
\t\r
\tinput clk, reset;\r
\tinput boton_arriba_in, boton_abajo_in, boton_izq_in, boton_der_in, boton_elige_in;\r
\r
\t\r
\twire boton_arriba, boton_abajo, boton_izq, boton_der, boton_elige;
\t\r
\t\r
\tNavegador_PushButtons nav_pb(\r
\t\t.clk_100Mhz (clk),\r
\t\t
\t\t.boton_arriba_in (boton_arriba_in),
\t\t.boton_abajo_in (boton_abajo_in),
\t\t.boton_izq_in (boton_izq_in),
\t\t.boton_der_in (boton_der_in),
\t\t.boton_elige_in (boton_elige_in),
\t\t
\t\t.boton_arriba_out (boton_arriba),
\t\t.boton_abajo_out (boton_abajo),
\t\t.boton_izq_out (boton_izq),
\t\t.boton_der_out (boton_der),
\t\t.boton_elige_out (boton_elige)\r
\t);\r
\t\r
\toutput reg [2:0] where_fila; \r
\toutput reg [2:0] where_columna;
\t\r
\toutput reg [9:0] char_scale;
\toutput wire [9:0] char_scale_temp;
\t
\toutput reg text_red, text_green, text_blue, es_mayuscula;
\toutput wire text_red_temp, text_green_temp, text_blue_temp, es_mayuscula_temp;
\t\r
\toutput reg nuevo, guardar, cerrar;
\t\t
\tassign text_red_temp = (where_fila == 5 && where_columna == 1)? 0 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 2)? 0 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 3)? 0 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 4)? 1 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 5)? 1 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 6)? 1 : 0;
\t\t\t\t\t\t\t\t
\tassign text_green_temp = (where_fila == 5 && where_columna == 1)? 0 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 2)? 1 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 3)? 1 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 4)? 0 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 5)? 0 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 6)? 1 : 0;
\t\t\t\t\t\t\t\t
\tassign text_blue_temp = (where_fila == 5 && where_columna == 1)? 1 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 2)? 0 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 3)? 1 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 4)? 0 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 5)? 1 :
\t\t\t\t\t\t\t\t (where_fila == 5 && where_columna == 6)? 0 : 1;
\t
\tassign es_mayuscula_temp = (where_fila == 4 && where_columna == 2)? 0 : 1;
\t
\tassign char_scale_temp = (where_fila == 6 && where_columna == 1)? 10'd1 :
\t\t\t\t\t\t\t\t\t (where_fila == 6 && where_columna == 2)? 10'd2 :
\t\t\t\t\t\t\t\t\t (where_fila == 6 && where_columna == 3)? 10'd3 :
\t\t\t\t\t\t\t\t\t 10'd2;\r
\r
\tinitial begin\r
\t\twhere_fila <= 1;\r
\t\twhere_columna <= 1;\r
\t\t\r
\t\tchar_scale <= 10'd2;\r
\t\ttext_red <= 1'b0;\r
\t\ttext_green <= 1'b0;\r
\t\ttext_blue <= 1'b1;\r
\t\tes_mayuscula <= 1'b1;\r
\t\tnuevo <= 1'b0;\r
\t\tguardar <= 1'b0;\r
\t\tcerrar <= 1'b0;\r
\tend\r
\t\r
\twire temp_clk;\r
\tassign temp_clk = (boton_abajo || boton_izq || boton_arriba || boton_der || boton_elige);\r
\t\r
\treg [2:0] estado, sigEstado;\r
\t\r
\tparameter inicio = 0;\r
\tparameter aumenta_fila = 1;\r
\tparameter disminuye_fila = 2;\r
\tparameter aumenta_columna = 3;\r
\tparameter disminuye_columna = 4;\r
\tparameter elige = 5;\r
\t\r
\talways @(posedge clk or posedge reset) begin\r
\t\tif (reset) \r
\t\t\testado <= inicio;\r
\t\telse\r
\t\t\testado <= sigEstado;\r
\tend\r
\t\r
\talways @(posedge temp_clk) begin\r
\t\tcase (estado)\r
\t\t\tinicio:\r
\t\t\t\tbegin\r
\t\t\t\tif (boton_arriba)\r
\t\t\t\t\tsigEstado = disminuye_columna;\r
\t\t\t\telse if (boton_abajo)\r
\t\t\t\t\tsigEstado = aumenta_columna;\r
\t\t\t\telse if (boton_izq)\r
\t\t\t\t\tsigEstado = disminuye_fila;\r
\t\t\t\telse if (boton_der)\r
\t\t\t\t\tsigEstado = aumenta_fila;\r
\t\t\t\telse if (boton_elige)\r
\t\t\t\t\tsigEstado = elige;\r
\t\t\t\telse \t\r
\t\t\t\t\tsigEstado = inicio;\r
\t\t\t\tend\r
\t\t\t\t\r
\t\t\taumenta_fila:\r
\t\t\t\tbegin
\t\t\t\t\tnuevo = 0;\r
\t\t\t\t\twhere_columna = 1;\r
\t\t\t\t\twhere_fila = (where_fila < 6)? where_fila + 1 : where_fila;\r
\t\t\t\t\tsigEstado = inicio;\r
\t\t\t\tend\r
\t\t\t\t\r
\t\t\tdisminuye_fila:\r
\t\t\t\tbegin\r
\t\t\t\t\twhere_columna = 1;\r
\t\t\t\t\twhere_fila = (where_fila > 1)? where_fila - 1 : where_fila;\r
\t\t\t\t\tsigEstado = inicio;\r
\t\t\t\tend\r
\t\t\t\t\r
\t\t\taumenta_columna:\r
\t\t\t\tbegin\r
\t\t\t\t\tcase (where_fila)\r
\t\t\t\t\t\t4:\r
\t\t\t\t\t\t\twhere_columna = (where_columna < 2)? where_columna + 1: where_columna;\r
\t\t\t\t\t\t5:\r
\t\t\t\t\t\t\twhere_columna = (where_columna < 6)? where_columna + 1: where_columna;\r
\t\t\t\t\t\t6:\r
\t\t\t\t\t\t\twhere_columna = (where_columna < 3)? where_columna + 1: where_columna;\r
\t\t\t\t\tendcase\r
\t\t\t\t\tsigEstado = inicio;\r
\t\t\t\tend\r
\t\t\t\t\r
\t\t\tdisminuye_columna:\r
\t\t\t\tbegin\r
\t\t\t\t\twhere_columna = (where_columna > 1)? where_columna - 1 : where_columna;\r
\t\t\t\t\tsigEstado = inicio;\r
\t\t\t\tend\r
\t\t\t\r
\t\t\telige:\r
\t\t\t\tbegin\r
\t\t\t\t\tcase (where_fila)\r
\t\t\t\t\t\t1:\r
\t\t\t\t\t\t\tnuevo = 1;\r
\t\t\t\t\t\t2:\r
\t\t\t\t\t\t\tguardar = 1;\r
\t\t\t\t\t\t3:\r
\t\t\t\t\t\t\tcerrar = 1;\r
\t\t\t\t\t\t4:\r
\t\t\t\t\t\t\tbegin\r
\t\t\t\t\t\t\tcase (where_columna)\r
\t\t\t\t\t\t\t\t1:\r
\t\t\t\t\t\t\t\t\tes_mayuscula = 1;\r
\t\t\t\t\t\t\t\t2:\r
\t\t\t\t\t\t\t\t\tes_mayuscula = 0;\r
\t\t\t\t\t\t\tendcase\r
\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t5:\r
\t\t\t\t\t\t\tbegin\r
\t\t\t\t\t\t\tcase (where_columna)\r
\t\t\t\t\t\t\t\t1: \r
\t\t\t\t\t\t\t\t\tbegin\r
\t\t\t\t\t\t\t\t\ttext_red = 0;\r
\t\t\t\t\t\t\t\t\ttext_green = 0;\r
\t\t\t\t\t\t\t\t\ttext_blue = 1;\r
\t\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t2:\r
\t\t\t\t\t\t\t\t\tbegin\r
\t\t\t\t\t\t\t\t\ttext_red = 0;\r
\t\t\t\t\t\t\t\t\ttext_green = 1;\r
\t\t\t\t\t\t\t\t\ttext_blue = 0;\r
\t\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t3:\r
\t\t\t\t\t\t\t\t\tbegin\r
\t\t\t\t\t\t\t\t\ttext_red = 0;\r
\t\t\t\t\t\t\t\t\ttext_green = 1;\r
\t\t\t\t\t\t\t\t\ttext_blue = 1;\r
\t\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t4:\r
\t\t\t\t\t\t\t\t\tbegin\r
\t\t\t\t\t\t\t\t\ttext_red = 1;\r
\t\t\t\t\t\t\t\t\ttext_green = 0;\r
\t\t\t\t\t\t\t\t\ttext_blue = 0;\r
\t\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t5:\r
\t\t\t\t\t\t\t\t\tbegin\r
\t\t\t\t\t\t\t\t\ttext_red = 1;\r
\t\t\t\t\t\t\t\t\ttext_green = 0;\r
\t\t\t\t\t\t\t\t\ttext_blue = 1;\r
\t\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t6:\r
\t\t\t\t\t\t\t\t\tbegin\r
\t\t\t\t\t\t\t\t\ttext_red = 1;\r
\t\t\t\t\t\t\t\t\ttext_green = 1;\r
\t\t\t\t\t\t\t\t\ttext_blue = 0;\r
\t\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\tendcase\r
\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t6:\r
\t\t\t\t\t\t\tbegin\r
\t\t\t\t\t\t\tcase (where_columna)\r
\t\t\t\t\t\t\t\t1:\r
\t\t\t\t\t\t\t\t\tchar_scale = 10'd1;\r
\t\t\t\t\t\t\t\t2:\r
\t\t\t\t\t\t\t\t\tchar_scale = 10'd2;\r
\t\t\t\t\t\t\t\t3: \r
\t\t\t\t\t\t\t\t\tchar_scale = 10'd3;\r
\t\t\t\t\t\t\tendcase\r
\t\t\t\t\t\t\tend\r
\t\t\t\t\tendcase\r
\t\t\t\t\tsigEstado = inicio;\r
\t\t\t\tend\r
\t\t\t\r
\t\t\tdefault: sigEstado = inicio;\r
\t\tendcase\r
\tend\r
\t\t\r
endmodule\r
|
// Listing 14.7
module textMenu_graph
(
input wire clk, reset,
input wire [2:0] item_selector,
input wire [9:0] pix_x, pix_y,
output wire graph_on,
output reg [2:0] graph_rgb
);
// costant and signal declaration
// x, y coordinates (0,0) to (639,479)
localparam MAX_X = 640;
localparam MAX_Y = 480;
\t//Top menu sections
\tlocalparam item1 = 4'd1;
\tlocalparam item2 = 4'd2;
\tlocalparam item3 = 4'd3;
\tlocalparam item4 = 4'd4;
\tlocalparam item5 = 4'd5;
\tlocalparam item6 = 4'd6;
\t
\t//Top menu vertical limits
\tlocalparam topMenu_y_limit_top = 0;
\tlocalparam topMenu_y_limit_bottom = 80;
\t
\t//Top menu horizontal limits
\tlocalparam topMenu_x_limit_left=0;
\tlocalparam topMenu_x_limit_right=640;
\t
\t//Top menu items sections horizontal each region
\tlocalparam topMenu_x_open_limit_left=10;
\tlocalparam topMenu_x_open_limit_right=topMenu_x_open_limit_left+60;
\tlocalparam topMenu_x_save_limit_left=topMenu_x_open_limit_right+10;
\tlocalparam topMenu_x_save_limit_right=topMenu_x_save_limit_left+60;
\tlocalparam topMenu_x_exit_limit_left=topMenu_x_save_limit_right+10;
\tlocalparam topMenu_x_exit_limit_right=topMenu_x_exit_limit_left+60;
\tlocalparam topMenu_x_center_width=topMenu_x_exit_limit_right+210;
\tlocalparam topMenu_x_caps_limit_left=topMenu_x_center_width+10;
\tlocalparam topMenu_x_caps_limit_right=topMenu_x_caps_limit_left+60;
\tlocalparam topMenu_x_color_limit_left=topMenu_x_caps_limit_right+10;
\tlocalparam topMenu_x_color_limit_right=topMenu_x_color_limit_left+60;
\tlocalparam topMenu_x_size_limit_left=topMenu_x_color_limit_right+10;
\tlocalparam topMenu_x_size_limit_right=topMenu_x_size_limit_left+60;
\t
\t//Top menu items vertical limits
\tlocalparam topMenu_y_item_top_limit=topMenu_y_limit_top+17;
\tlocalparam topMenu_y_item_bottom_limit=topMenu_y_item_top_limit+45;
\t
\twire menu_mostrar_separador;
\twire menu_mostrar;
\t
\tassign menu_mostrar_separador = (topMenu_x_limit_left<=pix_x) && (pix_x <= topMenu_x_limit_right) &&
\t\t\t\t\t\t\t (topMenu_y_limit_bottom-2<=pix_y) && (pix_y <= topMenu_y_limit_bottom);
\t\t\t\t\t\t\t\t
\t
\t\t\t\t\t\t
//\t\t\t\t\t\t
\treg[5:0] show_item_selector;
\treg [2:0] currentItem;
\t
\talways @ (*) begin
\t\t
\t\tcurrentItem= item_selector;
\t
\t\tcase(currentItem)
\t\t
\t\t\titem1: begin
\t\t\t\t\t\t\tshow_item_selector[0] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_open_limit_right-1<=pix_x) && (pix_x <= topMenu_x_open_limit_right));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titem2: begin
\t\t\t\t\t\t\tshow_item_selector[1] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_save_limit_right-1<=pix_x) && (pix_x <= topMenu_x_save_limit_right));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titem3: begin
\t\t\t\t\t\t\tshow_item_selector[2] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_exit_limit_right-1<=pix_x) && (pix_x <= topMenu_x_exit_limit_right));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titem4: begin
\t\t\t\t\t\t\tshow_item_selector[3] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_caps_limit_right-1<=pix_x) && (pix_x <= topMenu_x_caps_limit_right));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titem5: begin
\t\t\t\t\t\t\tshow_item_selector[4] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_color_limit_right-1<=pix_x) && (pix_x <= topMenu_x_color_limit_right));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titem6: begin
\t\t\t\t\t\t\tshow_item_selector[5] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_size_limit_right-1<=pix_x) && (pix_x <= topMenu_x_size_limit_right));
\t\t\t\t\t\t\tend
\t\t\tdefault: \tbegin
\t\t\t\t\t\t\tshow_item_selector= 3'b000;\t\t\t
\t\t\t\t\t\t\tend
\t\tendcase
\tend
//--------------------------------------------
// rgb multiplexing circuit
//--------------------------------------------
always @* begin
\t\t\tif (menu_mostrar_separador)
\t\t\t\tgraph_rgb = 3'b000;
\t\t\telse if (show_item_selector[0] || show_item_selector[1] || show_item_selector[2] ||
\t\t\t\t\t\tshow_item_selector[3] || show_item_selector[4] || show_item_selector[5])
\t\t\t\t\t\t\tgraph_rgb = 3'b100;
\tend
\t
\tassign graph_on=show_item_selector[0] || show_item_selector[1] || show_item_selector[2] ||
\t\t\t\t\t\tshow_item_selector[3] || show_item_selector[4] || show_item_selector[5] || menu_mostrar_separador;
\t\t
endmodule
|
`timescale 1ns / 1ps
module Navegador_PushButtons(
\tinput clk_100Mhz,\r
\t
\tinput boton_arriba_in,
\tinput boton_abajo_in,
\tinput boton_izq_in,
\tinput boton_der_in,
\tinput boton_elige_in,
\t
\toutput boton_arriba_out,
\toutput boton_abajo_out,
\toutput boton_izq_out,
\toutput boton_der_out,
\toutput boton_elige_out
);
\t
\tButton_Filter filt_boton_arriba (
\t\t.clk (clk_100Mhz),
\t\t.button_in (boton_arriba_in),
\t\t.hold(),
\t\t.filtered (boton_arriba_out)
\t);
\t
\tButton_Filter filt_boton_abajo (
\t\t.clk (clk_100Mhz),
\t\t.button_in (boton_abajo_in),
\t\t.hold(),
\t\t.filtered (boton_abajo_out)
\t);
\t
\tButton_Filter filt_boton_izq (
\t\t.clk (clk_100Mhz),
\t\t.button_in (boton_izq_in),
\t\t.hold(),
\t\t.filtered (boton_izq_out)
\t);
\t
\tButton_Filter filt_boton_der (
\t\t.clk (clk_100Mhz),
\t\t.button_in (boton_der_in),
\t\t.hold(),
\t\t.filtered (boton_der_out)
\t);
\t
\tButton_Filter filt_boton_elige (
\t\t.clk (clk_100Mhz),
\t\t.button_in (boton_elige_in),
\t\t.hold(),
\t\t.filtered (boton_elige_out)
\t);
endmodule
|
`timescale 1ns / 1ps
module Navegador_PushButtons(
\tinput clk_100Mhz,\r
\t
\tinput boton_arriba_in,
\tinput boton_abajo_in,
\tinput boton_izq_in,
\tinput boton_der_in,
\tinput boton_elige_in,
\t
\toutput boton_arriba_out,
\toutput boton_abajo_out,
\toutput boton_izq_out,
\toutput boton_der_out,
\toutput boton_elige_out
);
\t
\tButton_Filter filt_boton_arriba (
\t\t.clk (clk_100Mhz),
\t\t.button_in (boton_arriba_in),
\t\t.hold(),
\t\t.filtered (boton_arriba_out)
\t);
\t
\tButton_Filter filt_boton_abajo (
\t\t.clk (clk_100Mhz),
\t\t.button_in (boton_abajo_in),
\t\t.hold(),
\t\t.filtered (boton_abajo_out)
\t);
\t
\tButton_Filter filt_boton_izq (
\t\t.clk (clk_100Mhz),
\t\t.button_in (boton_izq_in),
\t\t.hold(),
\t\t.filtered (boton_izq_out)
\t);
\t
\tButton_Filter filt_boton_der (
\t\t.clk (clk_100Mhz),
\t\t.button_in (boton_der_in),
\t\t.hold(),
\t\t.filtered (boton_der_out)
\t);
\t
\tButton_Filter filt_boton_elige (
\t\t.clk (clk_100Mhz),
\t\t.button_in (boton_elige_in),
\t\t.hold(),
\t\t.filtered (boton_elige_out)
\t);
endmodule
|
`timescale 1ns / 1ps\r
\r
module Altera_UP_PS2_Command_Out (
\t// Inputs
\tclk,
\treset,
\tthe_command,
\tsend_command,
\tps2_clk_posedge,
\tps2_clk_negedge,
\t// Bidirectionals
\tPS2_CLK,
\tPS2_DAT,
\t// Outputs
\tcommand_was_sent,
\terror_communication_timed_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for initiating Host-to-Device communication
// when using a 50MHz system clock
parameter\tCLOCK_CYCLES_FOR_101US\t\t= 5050;
parameter\tNUMBER_OF_BITS_FOR_101US\t= 13;
parameter\tCOUNTER_INCREMENT_FOR_101US\t= 13'h0001;
//parameter\tCLOCK_CYCLES_FOR_101US\t\t= 50;
//parameter\tNUMBER_OF_BITS_FOR_101US\t= 6;
//parameter\tCOUNTER_INCREMENT_FOR_101US\t= 6'h01;
// Timing info for start of transmission error
// when using a 50MHz system clock
parameter\tCLOCK_CYCLES_FOR_15MS\t\t= 750000;
parameter\tNUMBER_OF_BITS_FOR_15MS\t\t= 20;
parameter\tCOUNTER_INCREMENT_FOR_15MS\t= 20'h00001;
// Timing info for sending data error
// when using a 50MHz system clock
parameter\tCLOCK_CYCLES_FOR_2MS\t\t= 100000;
parameter\tNUMBER_OF_BITS_FOR_2MS\t\t= 17;
parameter\tCOUNTER_INCREMENT_FOR_2MS\t= 17'h00001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input\t\t\t\tclk;
input\t\t\t\treset;
input\t\t[7:0]\tthe_command;
input\t\t\t\tsend_command;
input\t\t\t\tps2_clk_posedge;
input\t\t\t\tps2_clk_negedge;
// Bidirectionals
inout\t\t\t\tPS2_CLK;
inout\t\t\t \tPS2_DAT;
// Outputs
output\treg\t\t\tcommand_was_sent;
output\treg\t\t \terror_communication_timed_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter\tPS2_STATE_0_IDLE\t\t\t\t\t= 3'h0,
\t\t\tPS2_STATE_1_INITIATE_COMMUNICATION\t= 3'h1,
\t\t\tPS2_STATE_2_WAIT_FOR_CLOCK\t\t\t= 3'h2,
\t\t\tPS2_STATE_3_TRANSMIT_DATA\t\t\t= 3'h3,
\t\t\tPS2_STATE_4_TRANSMIT_STOP_BIT\t\t= 3'h4,
\t\t\tPS2_STATE_5_RECEIVE_ACK_BIT\t\t\t= 3'h5,
\t\t\tPS2_STATE_6_COMMAND_WAS_SENT\t\t= 3'h6,
\t\t\tPS2_STATE_7_TRANSMISSION_ERROR\t\t= 3'h7;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg\t\t\t[3:0]\tcur_bit;
reg\t\t\t[8:0]\tps2_command;
reg\t\t\t[NUMBER_OF_BITS_FOR_101US:1]\tcommand_initiate_counter;
reg\t\t\t[NUMBER_OF_BITS_FOR_15MS:1]\t\twaiting_counter;
reg\t\t\t[NUMBER_OF_BITS_FOR_2MS:1]\t\ttransfer_counter;
// State Machine Registers
reg\t\t\t[2:0]\tns_ps2_transmitter;
reg\t\t\t[2:0]\ts_ps2_transmitter;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\ts_ps2_transmitter <= PS2_STATE_0_IDLE;
\telse
\t\ts_ps2_transmitter <= ns_ps2_transmitter;
end
always @(*)
begin
\t// Defaults
\tns_ps2_transmitter = PS2_STATE_0_IDLE;
case (s_ps2_transmitter)
\tPS2_STATE_0_IDLE:
\t\tbegin
\t\t\tif (send_command == 1'b1)
\t\t\t\tns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_0_IDLE;
\t\tend
\tPS2_STATE_1_INITIATE_COMMUNICATION:
\t\tbegin
\t\t\tif (command_initiate_counter == CLOCK_CYCLES_FOR_101US)
\t\t\t\tns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
\t\tend
\tPS2_STATE_2_WAIT_FOR_CLOCK:
\t\tbegin
\t\t\tif (ps2_clk_negedge == 1'b1)
\t\t\t\tns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
\t\t\telse if (waiting_counter == CLOCK_CYCLES_FOR_15MS)
\t\t\t\tns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
\t\tend
\tPS2_STATE_3_TRANSMIT_DATA:
\t\tbegin
\t\t\tif ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1))
\t\t\t\tns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
\t\t\telse if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
\t\t\t\tns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
\t\tend
\tPS2_STATE_4_TRANSMIT_STOP_BIT:
\t\tbegin
\t\t\tif (ps2_clk_negedge == 1'b1)
\t\t\t\tns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
\t\t\telse if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
\t\t\t\tns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
\t\tend
\tPS2_STATE_5_RECEIVE_ACK_BIT:
\t\tbegin
\t\t\tif (ps2_clk_posedge == 1'b1)
\t\t\t\tns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
\t\t\telse if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
\t\t\t\tns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
\t\tend
\tPS2_STATE_6_COMMAND_WAS_SENT:
\t\tbegin
\t\t\tif (send_command == 1'b0)
\t\t\t\tns_ps2_transmitter = PS2_STATE_0_IDLE;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
\t\tend
\tPS2_STATE_7_TRANSMISSION_ERROR:
\t\tbegin
\t\t\tif (send_command == 1'b0)
\t\t\t\tns_ps2_transmitter = PS2_STATE_0_IDLE;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
\t\tend
\tdefault:
\t\tbegin
\t\t\tns_ps2_transmitter = PS2_STATE_0_IDLE;
\t\tend
\tendcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tps2_command <= 9'h000;
\telse if (s_ps2_transmitter == PS2_STATE_0_IDLE)
\t\tps2_command <= {(^the_command) ^ 1'b1, the_command};
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tcommand_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
\telse if ((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
\t\t\t(command_initiate_counter != CLOCK_CYCLES_FOR_101US))
\t\tcommand_initiate_counter <=
\t\t\tcommand_initiate_counter + COUNTER_INCREMENT_FOR_101US;
\telse if (s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION)
\t\tcommand_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\twaiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
\telse if ((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) &&
\t\t\t(waiting_counter != CLOCK_CYCLES_FOR_15MS))
\t\twaiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS;
\telse if (s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK)
\t\twaiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\ttransfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
\telse
\tbegin
\t\tif ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ||
\t\t\t(s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) ||
\t\t\t(s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT))
\t\tbegin
\t\t\tif (transfer_counter != CLOCK_CYCLES_FOR_2MS)
\t\t\t\ttransfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS;
\t\tend
\t\telse
\t\t\ttransfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
\tend
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tcur_bit <= 4'h0;
\telse if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) &&
\t\t\t(ps2_clk_negedge == 1'b1))
\t\tcur_bit <= cur_bit + 4'h1;
\telse if (s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA)
\t\tcur_bit <= 4'h0;
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tcommand_was_sent <= 1'b0;
\telse if (s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT)
\t\tcommand_was_sent <= 1'b1;
\telse if (send_command == 1'b0)
\t\t\tcommand_was_sent <= 1'b0;
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\terror_communication_timed_out <= 1'b0;
\telse if (s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR)
\t\terror_communication_timed_out <= 1'b1;
\telse if (send_command == 1'b0)
\t\terror_communication_timed_out <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign PS2_CLK\t=
\t(s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) ?
\t\t1'b0 :
\t\t1'bz;
assign PS2_DAT\t=
\t(s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] :
\t(s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 :
\t((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
\t\t(command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 :
\t\t\t1'bz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule\r
|
`timescale 1ns / 1ps\r
\r
module text_editor_top(
\t\tMemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS, \t
\t\tClkPort, \t\t\t\t\t\t\t\t\t
\t\tBtnC,\t\t\t\t\t\t\t\t\t\t\t\t\t\t
\t\tPS2KeyboardData,\t\t\t\t\t\t\t\t\t\t
\t\tPS2KeyboardClk,\t\t\t\t\t\t\t\t\t\t\t
\t\tvga_h_sync,\t\t\t\t\t\t\t\t\t\t\t\t
\t\tvga_v_sync,\t\t\t\t\t\t\t\t\t\t\t\t\t
\t\tvga_r,\t\t\t\t\t\t\t\t\t\t\t\t\t\t
\t\tvga_g,\t\t\t\t\t\t\t\t\t\t\t\t\t
\t\tvga_b,\t\t\t\t\t\t\t\t\t\t\t\t\t\t
\t\tboton_arriba_in,\r
\t\tboton_abajo_in,\r
\t\tboton_izq_in,\r
\t\tboton_der_in,\r
\t\tboton_elige_in,\r
\t\t\r
\t\twhere_fila,\r
\t\twhere_columna,
\t\tselector_menu\r
\t );
\t
\tinput boton_arriba_in,\r
\t\t\tboton_abajo_in,\r
\t\t\tboton_izq_in,\r
\t\t\tboton_der_in,\r
\t\t\tboton_elige_in;
\t\t\t
\tinput selector_menu;\r
\t\t\t\r
\twire boton_arriba,\r
\t\t\tboton_abajo,\r
\t\t\tboton_izq,\r
\t\t\tboton_der,\r
\t\t\tboton_elige;\r
\t\t\t
\t/************************************************************************
\t * INPUTS *
\t ************************************************************************/
\tinput\t\tClkPort;\t
\tinput\t\tBtnC;
\t
\t/************************************************************************
\t * BIDIRECTIONALS *
\t ************************************************************************/
\tinout\t\tPS2KeyboardData, PS2KeyboardClk;
\t
\t
\t/************************************************************************
\t * OUTPUTS *
\t ************************************************************************/
\toutput \tMemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS;\r
\t
\toutput \tvga_h_sync, vga_v_sync, vga_r, vga_g, vga_b;
\t
\t/************************************************************************
\t * LOCAL SIGNALS *
\t ************************************************************************/\t
\twire\t\t\tReset, ClkPort;
\twire\t\t\tboard_clk, sys_clk, PS2_clk, VGA_clk, cursor_clk;
\twire [1:0] \tssdscan_clk;
\treg [26:0]\tDIV_CLK;
\t
\treg [3:0]\tSSD;
\twire [3:0]\tSSD3, SSD2, SSD1, SSD0;
\treg [7:0] SSD_CATHODES;
\t
\twire [7:0]\tKeyData;
\twire\t\t\tKeyReleased;
\treg [7:0] CurrentKey;
\t
\treg [8:0]\tdocument_pointer;
\treg [8:0] write_location;
\treg\t\t\twrite_to_RAM;
\twire [7:0] RAM_data;
\twire [9:0] read_address;
\t
\treg vga_r, vga_g, vga_b;
\t
\t//assign { Ld7, Ld6, Ld5, Ld4, Ld3, Ld2, Ld1, Ld0\t} = document_pointer[7:0];
\t
\tassign Reset = BtnC;
\t
\t// Disable the three memories so that they do not interfere with the rest of the design.
\tassign {MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS} = 5\'b11111;
\t
\t
\t/************************************************************************
\t * CLOCK DIVISION *
\t ************************************************************************/
\tBUFGP BUFGP1 (board_clk, ClkPort); \t
\t// Our clock is too fast (100MHz) for SSD scanning
\t// create a series of slower "divided" clocks
\t// each successive bit is 1/2 frequency
\talways @(posedge board_clk, posedge Reset) begin\t\t\t\t\t\t\t
\t\tif (Reset)
\t\t\tDIV_CLK <= 0;
\t\telse
\t\t\tDIV_CLK <= DIV_CLK + 1\'b1;
\tend
\t
\tassign\tsys_clk = board_clk;\t\t// 100 MHz
\tassign\tPS2_clk = DIV_CLK[0];\t// 50 MHz
\tassign VGA_clk = DIV_CLK[1];\t// 25 MHz
\tassign cursor_clk = DIV_CLK[26];\t// .75 Hz
\t
\t
\t/************************************************************************
\t * VGA Control *
\t ************************************************************************/\t
\tparameter RAM_size = 10\'d512;\t\t\t\t// Size of the RAM
\tparameter write_area = RAM_size - 10\'d2;\t// Allowable write area in the RAM (last location used as a null location)
\tparameter char_dim = 10\'d16;\t\t\t\t\t// Dimension of a character (16x16 bits)
\tparameter char_scale_i = 10\'d2;\t\t\t\t\t// Initial character scale
\tparameter row_length_i = 10\'d18;\t\t\t\t\t// Initial length of a row (number of columns)
\tparameter col_length_i = 10\'d29;\t\t\t\t\t// Initial length of a column (number of rows)
\t
\twire text_red, text_green, text_blue;
\twire text_red_temp, text_green_temp, text_blue_temp;
\t
\twire [9:0] char_scale;
\twire [9:0] char_scale_temp;
\t
\twire es_mayuscula, nuevo, guardar, cerrar;
\twire es_mayuscula_temp;
\t\r
\toutput wire [2:0] where_fila;\r
\toutput wire [2:0]where_columna;
\t
\t//reg [9:0] char_scale;
\treg [9:0] row_length;
\treg [9:0] col_length;
\treg [9:0] scroll;
\t
\t//reg text_red;
\t//reg text_green;
\t//reg text_blue;
\twire [2:0] textMenu_rgb, text_rgb;
\t
\twire textMenu_graph_on, text_on;
\t
\twire inDisplayArea;
\twire [9:0] CounterX;
\twire [9:0] CounterY;
\t
\twire [9:0] CounterXDiv;
\twire [9:0] CounterYDiv;
\tassign CounterXDiv = CounterX / char_scale;
\tassign CounterYDiv = CounterY / char_scale;
\t
\twire shouldDraw;
\tassign shouldDraw = CounterXDiv < char_dim * row_length && CounterYDiv < char_dim * col_length;
\t
\twire [0:255] relativePixel;
\tassign relativePixel = CounterXDiv % char_dim + CounterYDiv % char_dim * char_dim;
\t
\twire drawCursor;
\tassign drawCursor = read_address == document_pointer && Cursor[relativePixel] && cursor_clk;
\t
\tassign read_address = (CounterXDiv / char_dim + CounterYDiv / char_dim * row_length + scroll * row_length) < RAM_size - 1\'b1 ?
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(CounterXDiv / char_dim + CounterYDiv / char_dim * row_length + scroll * row_length) :
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tRAM_size - 1\'b1;
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t
\t/************************************************************************
\t * VGA Control MENU *
\t ************************************************************************/
\thvsync_generator vgaSyncGen(
\t\t// Inputs
\t\t.clk(VGA_clk),
\t\t.reset(Reset),
\t\t
\t\t// Outputs
\t\t.vga_h_sync(vga_h_sync),
\t\t.vga_v_sync(vga_v_sync),
\t\t.inDisplayArea(inDisplayArea),
\t\t.CounterX(CounterX),
\t\t.CounterY(CounterY)
\t);
\t
\t//assign temp=1\'b1;
\t
\t // instantiate text module\r
text_screen_gen text_unit(
\t\t.clk(sys_clk),
\t\t.pixel_x(CounterX),
\t\t.pixel_y(CounterY),\r
.text_rgb(text_rgb),
\t\t.color_selector({text_blue_temp,text_green_temp,text_red_temp}),
\t\t.size_selector(char_scale_temp),
\t\t.caps_on(es_mayuscula_temp),
\t\t.text_on(text_on),
\t\t.window_selector(selector_menu)
\t);\r
// instantiate graph module\r
textMenu_graph graph_unit(
\t\t.clk(sys_clk),
\t\t.reset(Reset),
\t\t.item_selector(where_fila),\r
.pix_x(CounterX),
\t\t.pix_y(CounterY),\r
.graph_on(textMenu_graph_on),
\t\t.graph_rgb(textMenu_rgb),
\t\t.window_selector(selector_menu)
\t);
\t
\t
\talways @(posedge VGA_clk) begin
\t\tif(inDisplayArea) begin
\t\t\tif(text_on) begin
\t\t\t\tvga_r<=text_rgb[0];
\t\t\t\tvga_g<=text_rgb[1];
\t\t\t\tvga_b<=text_rgb[2];
\t\t\tend
\t\t\telse if (textMenu_graph_on) begin
\t\t\t\tvga_r<=textMenu_rgb[0];
\t\t\t\tvga_g<=textMenu_rgb[1];
\t\t\t\tvga_b<=textMenu_rgb[2];\t\t\t
\t\t\tend
\t\t\telse begin
\t\t\t\tvga_r <= Red;
\t\t\t\tvga_g <= Green;
\t\t\t\tvga_b <= Blue;
\t\t\tend
\t\tend
\t\telse begin
\t\t\tvga_r <= 1\'b0;
\t\t\tvga_g <= 1\'b0;
\t\t\tvga_b <= 1\'b0;
\t\tend
\tend
\t
\twire Red = !(shouldDraw && ((~drawCursor && text_red && toDraw[relativePixel]) || (drawCursor && !text_red) || (drawCursor && text_red && text_green && text_blue)));
\twire Blue = !(shouldDraw && ((~drawCursor && text_blue && toDraw[relativePixel]) || (drawCursor && !text_blue)));
\twire Green = !(shouldDraw && ((~drawCursor && text_green && toDraw[relativePixel]) || (drawCursor && !text_green)));
\t
\twire [0:255] toDraw;
\tassign toDraw = \tRAM_data == 8\'h70 ? Block :
\t\t\t\t\t\t\tRAM_data == 8\'h49 ? Period :
\t\t\t\t\t\t\tRAM_data == 8\'h41 ? Comma :
\t\t\t\t\t\t\tRAM_data == 8\'h52 ? Apost :
\t\t\t\t\t\t\t//mayusculas
\t\t\t\t\t\t\t(RAM_data == 8\'h1C && es_mayuscula)? A :
\t\t\t\t\t\t\t(RAM_data == 8\'h32 && es_mayuscula)? B :
\t\t\t\t\t\t\t(RAM_data == 8\'h21 && es_mayuscula)? C :
\t\t\t\t\t\t\t(RAM_data == 8\'h23 && es_mayuscula)? D :
\t\t\t\t\t\t\t(RAM_data == 8\'h24 && es_mayuscula)? E :
\t\t\t\t\t\t\t(RAM_data == 8\'h2B && es_mayuscula)? F :
\t\t\t\t\t\t\t(RAM_data == 8\'h34 && es_mayuscula)? G :
\t\t\t\t\t\t\t(RAM_data == 8\'h33 && es_mayuscula)? H :
\t\t\t\t\t\t\t(RAM_data == 8\'h43 && es_mayuscula)? I :
\t\t\t\t\t\t\t(RAM_data == 8\'h3B && es_mayuscula)? J :
\t\t\t\t\t\t\t(RAM_data == 8\'h42 && es_mayuscula)? K :
\t\t\t\t\t\t\t(RAM_data == 8\'h4B && es_mayuscula)? L :
\t\t\t\t\t\t\t(RAM_data == 8\'h3A && es_mayuscula)? M :
\t\t\t\t\t\t\t(RAM_data == 8\'h31 && es_mayuscula)? N :
\t\t\t\t\t\t\t(RAM_data == 8\'h44 && es_mayuscula)? O :
\t\t\t\t\t\t\t(RAM_data == 8\'h4D && es_mayuscula)? P :
\t\t\t\t\t\t\t(RAM_data == 8\'h15 && es_mayuscula)? Q :
\t\t\t\t\t\t\t(RAM_data == 8\'h2D && es_mayuscula)? R :
\t\t\t\t\t\t\t(RAM_data == 8\'h1B && es_mayuscula)? S :
\t\t\t\t\t\t\t(RAM_data == 8\'h2C && es_mayuscula)? T :
\t\t\t\t\t\t\t(RAM_data == 8\'h3C && es_mayuscula)? U :
\t\t\t\t\t\t\t(RAM_data == 8\'h2A && es_mayuscula)? V :
\t\t\t\t\t\t\t(RAM_data == 8\'h1D && es_mayuscula)? W :
\t\t\t\t\t\t\t(RAM_data == 8\'h22 && es_mayuscula)? X :
\t\t\t\t\t\t\t(RAM_data == 8\'h35 && es_mayuscula)? Y :
\t\t\t\t\t\t\t(RAM_data == 8\'h1A && es_mayuscula)? Z :
\t\t\t\t\t\t\t//minusculas
\t\t\t\t\t\t\t(RAM_data == 8\'h1C && !es_mayuscula)? a :
\t\t\t\t\t\t\t(RAM_data == 8\'h32 && !es_mayuscula)? b :
\t\t\t\t\t\t\t(RAM_data == 8\'h21 && !es_mayuscula)? c :
\t\t\t\t\t\t\t(RAM_data == 8\'h23 && !es_mayuscula)? d :
\t\t\t\t\t\t\t(RAM_data == 8\'h24 && !es_mayuscula)? e :
\t\t\t\t\t\t\t(RAM_data == 8\'h2B && !es_mayuscula)? f :
\t\t\t\t\t\t\t(RAM_data == 8\'h34 && !es_mayuscula)? g :
\t\t\t\t\t\t\t(RAM_data == 8\'h33 && !es_mayuscula)? h :
\t\t\t\t\t\t\t(RAM_data == 8\'h43 && !es_mayuscula)? i :
\t\t\t\t\t\t\t(RAM_data == 8\'h3B && !es_mayuscula)? j :
\t\t\t\t\t\t\t(RAM_data == 8\'h42 && !es_mayuscula)? k :
\t\t\t\t\t\t\t(RAM_data == 8\'h4B && !es_mayuscula)? l :
\t\t\t\t\t\t\t(RAM_data == 8\'h3A && !es_mayuscula)? m :
\t\t\t\t\t\t\t(RAM_data == 8\'h31 && !es_mayuscula)? n :
\t\t\t\t\t\t\t(RAM_data == 8\'h44 && !es_mayuscula)? o :
\t\t\t\t\t\t\t(RAM_data == 8\'h4D && !es_mayuscula)? p :
\t\t\t\t\t\t\t(RAM_data == 8\'h15 && !es_mayuscula)? q :
\t\t\t\t\t\t\t(RAM_data == 8\'h2D && !es_mayuscula)? r :
\t\t\t\t\t\t\t(RAM_data == 8\'h1B && !es_mayuscula)? s :
\t\t\t\t\t\t\t(RAM_data == 8\'h2C && !es_mayuscula)? t :
\t\t\t\t\t\t\t(RAM_data == 8\'h3C && !es_mayuscula)? u :
\t\t\t\t\t\t\t(RAM_data == 8\'h2A && !es_mayuscula)? v :
\t\t\t\t\t\t\t(RAM_data == 8\'h1D && !es_mayuscula)? w :
\t\t\t\t\t\t\t(RAM_data == 8\'h22 && !es_mayuscula)? x :
\t\t\t\t\t\t\t(RAM_data == 8\'h35 && !es_mayuscula)? y :
\t\t\t\t\t\t\t(RAM_data == 8\'h1A && !es_mayuscula)? z :
\t\t\t\t\t\t\t//numeros
\t\t\t\t\t\t\tRAM_data == 8\'h16 ? num1 :
\t\t\t\t\t\t\tRAM_data == 8\'h1E ? num2 :\r
\t\t\t\t\t\t\tRAM_data == 8\'h26 ? num3 :\r
\t\t\t\t\t\t\tRAM_data == 8\'h25 ? num4 :\r
\t\t\t\t\t\t\tRAM_data == 8\'h2E ? num5 :\r
\t\t\t\t\t\t\tRAM_data == 8\'h36 ? num6 :\r
\t\t\t\t\t\t\tRAM_data == 8\'h3D ? num7 :\r
\t\t\t\t\t\t\tRAM_data == 8\'h3E ? num8 :\r
\t\t\t\t\t\t\tRAM_data == 8\'h46 ? num9 :\r
\t\t\t\t\t\t\tRAM_data == 8\'h45 ? num0 :
\t\t\t\t\t\t\t256\'d0;
\t
\tparameter [0:255] Cursor = 256\'hC000C000C000C000C000C000C000C000C000C000C000C000C000C000C000C000;
\tparameter [0:255] Block = 256\'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
\tparameter [0:255] Period = 256\'h0000000000000000000000000000000000000000000000000000E000E000E000;
\tparameter [0:255] Comma = 256\'h000000000000000000000000000000000000000000000000000070007000E000;
\tparameter [0:255] Apost = 256\'h070007000E000000000000000000000000000000000000000000000000000000;
\tparameter [0:255] ExlPnt = 256\'hF000F000F000F000F000F000F000F000F000F000F00000000000F000F000F000;
\tparameter [0:255] A = 256\'h00001FE03870387070387038E01CE01CE01CFFFCFFFCE01CE01CE01CE01CE01C;
\tparameter [0:255] B = 256\'h0000FFC0FFF0F078F03CF03CF038FFE0FFE0F038F03CF03CF03CF07CFFF8FFE0;
\tparameter [0:255] C = 256\'h00001FF07FFCF81EF01EE000E000E000E000E000E000E000E01EF01E7FFC1FF0;
\tparameter [0:255] D = 256\'h0000FFE0FFF8F03CF01CF00EF00EF00EF00EF00EF00EF00EF01CF03CFFF8FFE0;
\tparameter [0:255] E = 256\'h0000FFFEFFFEE000E000E000E000FFFEFFFEE000E000E000E000E000FFFEFFFE;
\tparameter [0:255] F = 256\'h0000FFFEFFFEF000F000F000F000FFFEFFFEF000F000F000F000F000F000F000;
\tparameter [0:255] G = 256\'h00003FF07FF8F01EE00EC000C000C000C000C07EC07EC00EC00EF01E7FF83FF0;
\tparameter [0:255] H = 256\'h0000E00EE00EE00EE00EE00EE00EFFFEFFFEE00EE00EE00EE00EE00EE00EE00E;
\tparameter [0:255] I = 256\'h0000FFFCFFFC07800780078007800780078007800780078007800780FFFCFFFC;
\tparameter [0:255] J = 256\'h00003FFC3FFC001C001C001C001C001C001C001CE01CE01CE01CF03C7FF83FF0;
\tparameter [0:255] K = 256\'h0000E00EE00EE01CE038E070E0E0FFC0FFC0E0E0E070E038E01CE00EE00EE00E;
\tparameter [0:255] L = 256\'h0000E000E000E000E000E000E000E000E000E000E000E000E000E000FFFCFFFC;
\tparameter [0:255] M = 256\'h0000F87CFCFCFCFCECDCEFDCE79CE31CE01CE01CE01CE01CE01CE01CE01CE01C;
\tparameter [0:255] N = 256\'h0000F81CF81CEC1CEC1CE61CE61CE31CE31CE31CE19CE19CE0DCE0DCE07CE07C;
\tparameter [0:255] O = 256\'h00003FF07878E01CE01CE01CE01CE01CE01CE01CE01CE01CE01CF03C78783FF0;
\tparameter [0:255] P = 256\'h0000FFC0FFF8F07CF03CF03CF03CF07CFFF8FFC0F000F000F000F000F000F000;
\tparameter [0:255] Q = 256\'h00003FF07878E01CE01CE01CE01CE01CE01CE01CE01CE01CE01CF03C787C0FDE;
\tparameter [0:255] R = 256\'h0000FFF0FFFCF01EF01EF01EF01EFFF0FFC0F0F0F078F03CF03CF01EF01EF01E;
\tparameter [0:255] S = 256\'h00000FF03FFCE01EE00EE00EF0007FF01FFC001EE00EE00EF00E781E3FFC07F8;
\tparameter [0:255] T = 256\'h0000FFFEFFFE0380038003800380038003800380038003800380038003800380;
\tparameter [0:255] U = 256\'h0000E00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00E783C1FF0;
\tparameter [0:255] V = 256\'h0000E00EF01EF01E783C783C3C783C783C781EF01EF00FE00FE007C003800100;
\tparameter [0:255] W = 256\'h0000E01CE01CE01CE01CE01CE01CE01CE01CE31CE79CEFDCECDCFCFCFCFCF87C;
\tparameter [0:255] X = 256\'h0000F01EF01E78783CF03CF01FE00FC007800FC01FE03CF03CF07878F03CF03C;
\tparameter [0:255] Y = 256\'h0000E00EE00E701C781C3C780FE007C003800380038003800380038003800380;
\tparameter [0:255] Z = 256\'h0000FFFEFFFE001E003C007800F001E003C00F001E003C007800F000FFFEFFFE;
\t
\tparameter [0:255] num1 = 256\'h0000003C00FC01DC039C071C001C001C001C001C001C001C001C001C001C001C;\r
\tparameter [0:255] num2 = 256\'h00000FF01FF8381C001C001C001C0038007000E001C0038007001C003FFC3FFC;\r
\tparameter [0:255] num3 = 256\'h00003FFC3FFC000C00180060018003C000E0003000380038003800383FF03FC0;\r
\tparameter [0:255] num4 = 256\'h0000007C00DC019C031C061C0C1C181C301C3FFC001C001C001C001C001C001C;\r
\tparameter [0:255] num5 = 256\'h00003FFC3FFC3000300030003FC001E00070003000380038007000E03FC03F00;\r
\tparameter [0:255] num6 = 256\'h000000E003800E0018003800380038003FE03FF03C18381838181C181FF00FE0;\r
\tparameter [0:255] num7 = 256\'h00003FFC3FFC000C000C000C00180030006000C00180030006000C0018003000;\r
\tparameter [0:255] num8 = 256\'h00001FF83FFC381C381C381C3FFC3FFC381C381C381C381C381C381C3FFC1FF8;\r
\tparameter [0:255] num9 = 256\'h00001FFC3FFC381C300C300C381C1FFC0FFC000C000C000C000C000C007C007C;\r
\tparameter [0:255] num0 = 256\'h00001FF83FFC381C381C381C381C381C381C381C381C381C381C381C3FFC1FF8;
\t//minusculas
\tparameter [0:255] a = 256\'h00000000000000000000000007F007F80018000C03FC0FFC0C0C0C0C0FFC07FC;\r
\tparameter [0:255] b = 256\'h0000E000E000E000E000E000FFF8FFFCE01CE01CE01CE01CE01CE01CFFFCFFFC;\r
\tparameter [0:255] c = 256\'h000000000000000000001FF07FFCF81EF01EE000E000E000E01EF01E7FFC1FF0;\r
\tparameter [0:255] d = 256\'h0000000E000E000E000E000E000E1FFE7FFE781E700E700E701E383E1FFE0FCE;\r
\tparameter [0:255] e = 256\'h000000000000000000001FF03FF8701CE01CE01CFFFCFFFCE000E0007FFC3FFC;\r
\tparameter [0:255] f = 256\'h0000000000003FFE7FFE7000F000F000F000FFFEFFFEF000F000F000F000F000;\r
\tparameter [0:255] g = 256\'h00000000000007E00FF01818380C300C300C1C0C0FFC001C001C381C1FFC0FF8;\r
\tparameter [0:255] h = 256\'h0000E000E000E000E000E000E000FFFEFFFEE00EE00EE00EE00EE00EE00EE00E;\r
\tparameter [0:255] i = 256\'h0000000000000000078007800780000000000780078007800780078007800780;\r
\tparameter [0:255] j = 256\'h000000000000001C001C001C00000000001C001CE01CE01CE01CF03C7FF83FF0;\r
\tparameter [0:255] k = 256\'h0000000000000000E00EE00EE01CE038E070E0E0FFC0FFE0E070E070E070E070;\r
\tparameter [0:255] l = 256\'h0000038003800380038003800380038003800380038003800380038003800380;\r
\tparameter [0:255] m = 256\'h00000000000000000000000000000000FCFCFCDCEFDCE79CE31CE01CE01CE01C;\r
\tparameter [0:255] n = 256\'h00000000000000000000000000000000E7F8FFFCF01CE01CE01CE01CE01CE01C;\r
\tparameter [0:255] o = 256\'h00000000000000000000000000003FF07878E01CE01CE01CE01CF03C78783FF0;\r
\tparameter [0:255] p = 256\'h0000000000000000FFC0FFF8F07CF03CF03CF03CF07CFFF8FFC0F000F000F000;\r
\tparameter [0:255] q = 256\'h000000000000000003FF1FFF3E0F3C0F3C0F3C0F3E0F1FFF03FF000F000F000F;\r
\tparameter [0:255] r = 256\'h0000000000000000000000000000F3FCF7FCFE00FC00F800F000F000F000F000;\r
\tparameter [0:255] s = 256\'h0000000000000000000000000FF03FFCE01EF0007FF01FFC000E781E3FFC07F8;\r
\tparameter [0:255] t = 256\'h00000380038003800380FFFEFFFE038003800380038003800380038003800380;\r
\tparameter [0:255] u = 256\'h00000000000000000000000000000000E00EE00EE00EE00EE00EE00E783C1FF0;\r
\tparameter [0:255] v = 256\'h0000000000000000000000003C783C783C781EF01EF00FE00FE007C003800100;\r
\tparameter [0:255] w = 256\'h0000000000000000000000000000E01CE01CE31CE79CEFDCECDCFCFCFCFCF87C;\r
\tparameter [0:255] x = 256\'h00000000000000000000000000003CF03CF01FE00FC007800FC01FE03CF03CF0;\r
\tparameter [0:255] y = 256\'h000000000000000000000000E00F701E781C3C780FE007C007800F001E003C00;\r
\tparameter [0:255] z = 256\'h000000000000000000000000FFFEFFFE001E007801E007801E007800FFFEFFFE;
\t
\t/************************************************************************
\t * PS2 KEYBOARD *
\t ************************************************************************/\t
\ttext_editor_keyboard_controller KeyBoard(
\t\t// Inputs
\t\t.sys_Clk(sys_clk),
\t\t.PS2_Clk(PS2_clk),
\t\t.Reset(Reset),
\t
\t\t// Bidirectionals
\t\t.PS2KeyboardData(PS2KeyboardData),
\t\t.PS2KeyboardClk(PS2KeyboardClk),
\t
\t\t// Outputs
\t\t.KeyData(KeyData),
\t\t.KeyReleased(KeyReleased)
);
\t
\t
\t/************************************************************************
\t * TEXT RAM *
\t ************************************************************************/
\t text_editor_RAM RAM(
\t\t// Inputs
\t\t.clk(sys_clk),
\t\t.Reset(Reset),
\t\t.write(write_to_RAM),
\t\t.write_address(write_location),
\t\t.write_data(CurrentKey),
\t\t.read_address(read_address[8:0]),
\t
\t\t// Outputs
\t\t.read_data(RAM_data)
\t );\r
\t \r
\t /************************************************************************
\t * PUSHBUTTONS *
\t ************************************************************************/
\t \t \r
\t Controlador_Menu_Editor(\r
\t\t.clk (sys_clk), \r
\t\t.reset (Reset),\r
\t\t.boton_arriba_in(boton_arriba_in),\r
\t\t.boton_abajo_in(boton_abajo_in),\r
\t\t.boton_izq_in(boton_izq_in),\r
\t\t.boton_der_in(boton_der_in),\r
\t\t.boton_elige_in(boton_elige_in),
\t\t\r
\t\t.text_red(text_red),\r
\t\t.text_green(text_green),\r
\t\t.text_blue(text_blue),\r
\t\t.char_scale(char_scale),
\t\t.es_mayuscula(es_mayuscula),
\t\t
\t\t.text_red_temp(text_red_temp),\r
\t\t.text_green_temp(text_green_temp),\r
\t\t.text_blue_temp(text_blue_temp),\r
\t\t.char_scale_temp(char_scale_temp),
\t\t.es_mayuscula_temp(es_mayuscula_temp),\r
\t\t\r
\t\t.nuevo(nuevo),\r
\t\t.guardar(guardar),\r
\t\t.cerrar(cerrar),
\t\t\r
\t\t.where_fila(where_fila),\r
\t\t.where_columna(where_columna)\r
);
\t
\t
\t/************************************************************************
\t * STATE MACHINE *
\t ************************************************************************/\t
\treg [1:0] state;\t\t
\tlocalparam \t
\t\tINI = 2\'b00,
\t\tGETKEY = 2\'b01,
\t\tEDIT = 2\'b10,
\t\tWRITE = 2\'b11,
\t\tUNK = 2\'bXX;
\t
\talways @ (posedge sys_clk, posedge Reset) begin: STATE_MACHINE
\t\tif (Reset || !selector_menu || nuevo ) begin
\t\t\tCurrentKey <= 8\'hXX;
\t\t\tdocument_pointer <= 9\'bXXXXXXXXX;
\t\t\twrite_location <= 9\'bXXXXXXXXX;
\t\t\twrite_to_RAM <= 1\'bX;
\t\t\t//char_scale <= 10\'bXXXXXXXXXX;
\t\t\trow_length <= 10\'bXXXXXXXXXX;
\t\t\tcol_length <= 10\'bXXXXXXXXXX;
\t\t\tscroll <= 10\'bXXXXXXXXXX;
\t\t\t//text_red <= 1\'bX;
\t\t\t//text_green <= 1\'bX;
\t\t\t//text_blue <= 1\'bX;
\t\t\t
\t\t\tstate <= INI;
\t\tend else begin\t\t\t
\t\t\tcase (state)
\t\t\t\tINI: begin
\t\t\t\t\tstate <= GETKEY;
\t\t\t\t\t
\t\t\t\t\tCurrentKey <= 8\'h29; // SPACE
\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\tdocument_pointer <= 10\'d0;
\t\t\t\t\twrite_location <= 10\'d0;
\t\t\t\t\t//char_scale <= char_scale_i;
\t\t\t\t\trow_length <= row_length_i;
\t\t\t\t\tcol_length <= col_length_i;
\t\t\t\t\tscroll <= 10\'d0;
\t\t\t\t\t//text_red <= 1\'b0;
\t\t\t\t\t//text_green <= 1\'b1;
\t\t\t\t\t//text_blue <= 1\'b0;
\t\t\t\tend
\t\t\t\t
\t\t\t\tGETKEY: begin
\t\t\t\t\tif (KeyReleased) begin
\t\t\t\t\t\tstate <= EDIT;
\t\t\t\t\tend
\t\t\t\t\t
\t\t\t\t\tCurrentKey <= KeyData;
\t\t\t\t\t
\t\t\t\t\tcase(char_scale)
\t\t\t\t\t\t2\'d1: begin row_length <= 10\'d36; col_length <= 10\'d15; end
\t\t\t\t\t\t2\'d2: begin row_length <= 10\'d18; col_length <= 10\'d29; end
\t\t\t\t\t\t2\'d3: begin row_length <= 10\'d12; col_length <= 10\'d43; end
\t\t\t\t\t\tdefault: begin row_length <= 10\'d18; col_length <= 10\'d29; end
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t\t
\t\t\t\tEDIT: begin
\t\t\t\t\tstate <= WRITE;
\t\t\t\t\twrite_to_RAM <= 1\'b1;
\t\t\t\t\twrite_location <= document_pointer;
\t\t\t\t\t
\t\t\t\t\tcase (CurrentKey)
\t\t\t\t\t\t8\'h66: begin // BACKSPACE
\t\t\t\t\t\t\tif (document_pointer > 10\'d0) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer - 1\'b1;
\t\t\t\t\t\t\t\twrite_location <= document_pointer - 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t
\t\t\t\t\t\t\tCurrentKey <= 8\'h29; // SPACE
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h6B: begin // LEFT ARROW
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (document_pointer > 10\'d0) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer - 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h74: begin // RIGHT ARROW
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (document_pointer < write_area) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer + 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h75: begin // UP ARROW
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (document_pointer >= row_length) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer - row_length;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h72: begin // DOWN ARROW
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (document_pointer <= write_area - row_length) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer + row_length;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t//------------cambia tamanio de letra----------------------
\t\t\t\t\t\t/*
\t\t\t\t\t\t8\'h79: begin // + KEYPAD
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (char_scale < 10\'d3) begin
\t\t\t\t\t\t\t\tchar_scale <= char_scale + 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h7B: begin // - KEYPAD
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (char_scale > 10\'d1) begin
\t\t\t\t\t\t\t\tchar_scale <= char_scale - 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t*/
\t\t\t\t\t\t//--------------------------------------------------------
\t\t\t\t\t\t8\'h7D: begin // PG UP
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (scroll < col_length - 2\'d2) begin
\t\t\t\t\t\t\t\tscroll <= scroll + 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h7A: begin // PG DOWN
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (scroll > 10\'d0) begin
\t\t\t\t\t\t\t\tscroll <= scroll - 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t//------------------------cambia color de la letra------------------------------
\t\t\t\t\t\t/*
\t\t\t\t\t\t8\'h05: begin // F1 (Red color)
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\ttext_red <= ~text_red;
\t\t\t\t\t\t\tif (text_red && !text_blue) begin
\t\t\t\t\t\t\t\ttext_green <= 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h06: begin // F2 (Green color)
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\ttext_green <= ~text_green;
\t\t\t\t\t\t\tif (text_green && !text_blue && !text_red) begin
\t\t\t\t\t\t\t\ttext_green <= 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h04: begin // F3 (Blue color)
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\ttext_blue <= ~text_blue;
\t\t\t\t\t\t\tif (text_blue && !text_red) begin
\t\t\t\t\t\t\t\ttext_green <= 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t*/
\t\t\t\t\t\t//----------------------------------------------------------------------------
\t\t\t\t\t\t8\'h71: begin // DELETE KEY\t\t\t\t\t\t
\t\t\t\t\t\t\tCurrentKey <= 8\'h29; // SPACE
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\tdefault: begin
\t\t\t\t\t\t\tif (document_pointer < write_area) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer + 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t\t
\t\t\t\tWRITE: begin
\t\t\t\t\tstate <= GETKEY;
\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\tend
\t\t\t\t
\t\t\t\tdefault: begin
\t\t\t\t\tstate <= UNK;
\t\t\t\tend
\t\t\tendcase
\t\tend
\t
\tend\r
\t\r
\t\r
\t//-------------------------MENU EDITOR TEXTO---------------------------------------\r
\t\r
\t//---------------------------------------------------------------------------------
endmodule\r
|
`timescale 1ns / 1ps
module Button_Filter(
input clk, button_in,
\toutput hold, filtered
\t);
\t
\treg [24:0] holdtime_c;
\treg hold, filtered;
\t
\tinitial begin
\t\thold = 1'bx;
\t\tfiltered = 1'bx;
\tend
\t
\talways @(posedge clk) begin
\t\tif (button_in != hold) begin
\t\t\thold = button_in;
\t\t\tholdtime_c = 0;
\t\tend
\t\telse if (holdtime_c == 25'b1111111111111111111111111)
\t\t\tfiltered = hold;
\t\telse
\t\t\tholdtime_c = holdtime_c + 1;
\tend
\t
endmodule
|
`timescale 1ns / 1ps\r
\r
module text_editor_keyboard_controller(
input sys_Clk,
\t input PS2_Clk,
input Reset,
inout PS2KeyboardData,
inout PS2KeyboardClk,
output reg [7:0] KeyData,
output reg KeyReleased
);\t
\t
\t
\t/************************************************************************
\t * LOCAL SIGNALS *
\t ************************************************************************/
\treg [1:0] state;\t\t
\tlocalparam \t
\t\tI = 2'b00,
\t\tBAT = 2'b01,
\t\tDATA = 2'b10,
\t\tUNK = 2'bXX;
\t
\twire [7:0]\treceived_data;
\twire\t\t\treceived_data_en;
\treg [7:0] previous_word;
\t
\treg send_command;
\treg [7:0] the_command;
\twire command_sent;
\t
\t
\t/************************************************************************
\t * PS2 KEYBOARD *
\t ************************************************************************/\t
\tPS2_Controller PS2_Keyboard_Controller(
\t\t// Inputs
\t\t.CLOCK_50(PS2_Clk),
\t\t.reset(Reset),
\t\t.the_command(the_command),
\t\t.send_command(send_command),
\t\t// Bidirectionals
\t\t.PS2_CLK(PS2KeyboardClk),\t\t\t\t// PS2 Clock
\t\t.PS2_DAT(PS2KeyboardData),\t\t\t\t// PS2 Data
\t\t// Outputs
\t\t.command_was_sent(command_sent),
\t\t.error_communication_timed_out( ),
\t\t.received_data(received_data),
\t\t.received_data_en(received_data_en)\t// If 1 - new data has been received
\t);
\t
\t/************************************************************************
\t * STATE MACHINE *
\t ************************************************************************/\t
\talways @ (posedge sys_Clk, posedge Reset) begin: STATE_MACHINE
\t\tif(Reset) begin
\t\t\t\tstate <= I;
\t\t\t\tprevious_word <= 8'hXX;
\t\t\t\tsend_command <= 1'bX;
\t\t\t\tthe_command <= 8'hXX;
\t\t\t\tKeyData <= 8'hXX;
\t\tend else
\t\t\tcase(state)\t
\t\t\t\t\tI: begin
\t\t\t\t\t\tstate <= BAT;
\t\t\t\t\t\t
\t\t\t\t\t\tKeyData <= 8'h00;
\t\t\t\t\t\tprevious_word <= 8'h00;
\t\t\t\t\t\tKeyReleased <= 1'b0;
\t\t\t\t\t\tsend_command <= 1'b1;
\t\t\t\t\t\tthe_command <= 8'hFF;\t// RESET KEYBOARD
\t\t\t\t\tend
\t\t\t\t\t
\t\t\t\t\tBAT: begin
\t\t\t\t\t\tif (command_sent) begin
\t\t\t\t\t\t\tsend_command <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\t\tcase (received_data)
\t\t\t\t\t\t\t8'hAA: begin\t\t\t// SUCCESSFUL POST
\t\t\t\t\t\t\t\tstate <= DATA;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t
\t\t\t\t\t\t\t8'hFC: begin
\t\t\t\t\t\t\t\tsend_command <= 1'b1;\t// TRY TO POST AGAIN
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t
\t\t\t\t\t\t\tdefault: begin
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\tend
\t\t\t\t\t\tendcase
\t\t\t\t\tend
\t\t\t\t\t
\t\t\t\t\tDATA: begin
\t\t\t\t\t\tif (command_sent) begin
\t\t\t\t\t\t\tsend_command <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\tif (KeyReleased) begin
\t\t\t\t\t\t\tKeyReleased <= 1'b0;
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\tif (received_data_en) begin
\t\t\t\t\t\t\tprevious_word <= received_data;
\t\t\t\t\t\t\t
\t\t\t\t\t\t\tcase(received_data)
\t\t\t\t\t\t\t\t8'hF0: begin
\t\t\t\t\t\t\t\t\t// Key Released
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'hFA: begin
\t\t\t\t\t\t\t\t\t// Acknowledge
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'hAA: begin
\t\t\t\t\t\t\t\t\t// Self Test Passed
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'hEE: begin
\t\t\t\t\t\t\t\t\t// Echo Response
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'hFE: begin
\t\t\t\t\t\t\t\t\t// Resend Request
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'h00: begin
\t\t\t\t\t\t\t\t\t// Error
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'hFF: begin
\t\t\t\t\t\t\t\t\t// Error
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'h12: begin
\t\t\t\t\t\t\t\t\t// Shift
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'h59: begin
\t\t\t\t\t\t\t\t\t// Shift
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'h58: begin
\t\t\t\t\t\t\t\t\t// Caps
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'h0D: begin
\t\t\t\t\t\t\t\t\t// Tab
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'h14: begin
\t\t\t\t\t\t\t\t\t// Ctrl
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'h11: begin
\t\t\t\t\t\t\t\t\t// Alt
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'hE0: begin
\t\t\t\t\t\t\t\t\t// Extra
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\t8'h5A: begin
\t\t\t\t\t\t\t\t\t// Enter
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\t
\t\t\t\t\t\t\t\tdefault: begin
\t\t\t\t\t\t\t\t\tif (previous_word == 8'hF0) begin // IF PREV WORD WAS KEY RELEASED SCAN CODE
\t\t\t\t\t\t\t\t\t\tKeyData <= received_data;
\t\t\t\t\t\t\t\t\t\tKeyReleased <= 1'b1;
\t\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t\tend
\t\t\t\t\t\t\tendcase
\t\t\t\t\t\tend
\t\t\t\t\tend
\t\t\t\t\t
\t\t\t\t\tdefault:
\t\t\t\t\t\tstate <= UNK;
\t\t\tendcase
\tend
endmodule\r
\r
|
`timescale 1ns / 1ps\r
\r
\r
module Simulacion_Controlador_menu;\r
\r
\t// Inputs\r
\treg boton_arriba;\r
\treg boton_abajo;\r
\treg boton_izq;\r
\treg boton_der;\r
\treg boton_elige;\r
\r
\t// Outputs\r
\twire text_red;\r
\twire text_green;\r
\twire text_blue;\r
\twire char_scale;\r
\twire es_mayuscula;\r
\twire nuevo;\r
\twire guardar;\r
\twire cerrar;\r
\twire wf;\r
\twire wc;\r
\r
\t// Instantiate the Unit Under Test (UUT)\r
\tControlador_Menu_Editor uut (\r
\t\t.boton_arriba(boton_arriba), \r
\t\t.boton_abajo(boton_abajo), \r
\t\t.boton_izq(boton_izq), \r
\t\t.boton_der(boton_der), \r
\t\t.boton_elige(boton_elige), \r
\t\t.text_red(text_red), \r
\t\t.text_green(text_green), \r
\t\t.text_blue(text_blue), \r
\t\t.char_scale(char_scale), \r
\t\t.es_mayuscula(es_mayuscula), \r
\t\t.nuevo(nuevo), \r
\t\t.guardar(guardar), \r
\t\t.cerrar(cerrar),\r
\t\t.where_fila (wf),\r
\t\t.where_columna (wc)\r
\t);\r
\r
\tinitial begin\r
\t\t// Initialize Inputs\r
\t\tboton_arriba = 0;\r
\t\tboton_abajo = 0;\r
\t\tboton_izq = 0;\r
\t\tboton_der = 0;\r
\t\tboton_elige = 0;\r
\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 1;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 1;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 1;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 1;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\r
\tend\r
\r
endmodule\r
\r
|
`timescale 1ns / 1ps\r
\r
module hvsync_generator(
input wire clk,
input wire reset,
output reg vga_h_sync,
output reg vga_v_sync,
output reg [10:0] CounterX,
output reg [10:0] CounterY,
output reg inDisplayArea
);
parameter TotalHorizontalPixels = 11'd800;
parameter HorizontalSyncWidth = 11'd96;
parameter VerticalSyncWidth = 11'd2;
parameter TotalVerticalLines = 11'd525;
parameter HorizontalBackPorchTime = 11'd144 ;
parameter HorizontalFrontPorchTime = 11'd784 ;
parameter VerticalBackPorchTime = 11'd12 ;
parameter VerticalFrontPorchTime = 11'd492;
reg VerticalSyncEnable;
reg [10:0] HorizontalCounter;
reg [10:0] VerticalCounter;
//Counter for the horizontal sync signal
always @(posedge clk or posedge reset)
begin
\tif(reset == 1)
\t\tHorizontalCounter <= 0;
\telse
\t\tbegin
\t\t\tif(HorizontalCounter == TotalHorizontalPixels - 1)
\t\t\t\tbegin //the counter has hreached the end of a horizontal line
\t\t\t\t\tHorizontalCounter<=0;
\t\t\t\t\tVerticalSyncEnable <= 1;
\t\t\t\tend
\t\t\telse
\t\t\t\tbegin
\t\t\t\t\tHorizontalCounter<=HorizontalCounter+1;
\t\t\t\t\tVerticalSyncEnable <=0;
\t\t\t\tend
\t\tend
end
//Generate the vga_h_sync pulse
//Horizontal Sync is low when HorizontalCounter is 0-127
always @(*)
begin
\tif((HorizontalCounter<HorizontalSyncWidth))
\t\tvga_h_sync = 1;
\telse
\t\tvga_h_sync = 0;
end
//Counter for the vertical sync
always @(posedge clk or posedge reset)
begin
\tif(reset == 1)
\t\tVerticalCounter<=0;
\telse
\tbegin
\t\tif(VerticalSyncEnable == 1)
\t\t\tbegin
\t\t\t\tif(VerticalCounter==TotalVerticalLines-1)
\t\t\t\t\tVerticalCounter<=0;
\t\t\t\telse
\t\t\t\t\tVerticalCounter<=VerticalCounter+1;
\t\t\tend
\tend
end
//generate the vga_v_sync pulse
always @(*)
begin
\tif(VerticalCounter < VerticalSyncWidth)
\t\tvga_v_sync = 1;
\telse
\t\tvga_v_sync = 0;
end
always @(posedge clk)
begin
\tif((HorizontalCounter<HorizontalFrontPorchTime) && (HorizontalCounter>HorizontalBackPorchTime) && (VerticalCounter<VerticalFrontPorchTime) && (VerticalCounter>VerticalBackPorchTime))
\t\tbegin
\t\t\tinDisplayArea <= 1;
\t\t\tCounterX<= HorizontalCounter - HorizontalBackPorchTime;
\t\t\tCounterY<= VerticalCounter - VerticalBackPorchTime;
\t\tend
\telse
\t\tbegin
\t\t\tinDisplayArea <= 0;
\t\t\tCounterX<=0;
\t\t\tCounterY<=0;
\t\tend
end
endmodule
|
`timescale 1ns / 1ps\r
\r
module text_editor_RAM(
input\t\t\t\t\t\t\tclk,
\t input\t\t\t\t\t\t\tReset,
input\t\t\t\t\t\t\twrite,
\t input [ADDR_WIDTH-1:0] \twrite_address,
\t input [DATA_WIDTH-1:0] \twrite_data,
\t input [ADDR_WIDTH-1:0] \tread_address,
\t
\t output [DATA_WIDTH-1:0]\tread_data
);
\t
\t parameter DATA_WIDTH = 8;
\t parameter ADDR_WIDTH = 9;
\t parameter RAM_DEPTH = 1 << ADDR_WIDTH;
\t
\t reg [DATA_WIDTH-1:0] data [0:RAM_DEPTH-1]; // Array to store 512 8-bit words (characters)
\t
\t always @ (posedge clk, posedge Reset) begin: RAM_logic
\t\tif (Reset) begin: Reset
\t\t\tinteger i;
\t\t\tfor (i = 0; i < RAM_DEPTH; i = i + 1) begin
\t\t\t\tdata[i] <= 8\'h29; // a "Space"
\t\t\tend\t\t\t
\t\tend else if (write) begin
\t\t\tdata[write_address] <= write_data;
\t\tend
\t end
\t
\t assign read_data = data[read_address];
endmodule\r
|
`timescale 1ns / 1ps\r
\r
module text_editor_RAM(
input\t\t\t\t\t\t\tclk,
\t input\t\t\t\t\t\t\tReset,
input\t\t\t\t\t\t\twrite,
\t input [ADDR_WIDTH-1:0] \twrite_address,
\t input [DATA_WIDTH-1:0] \twrite_data,
\t input [ADDR_WIDTH-1:0] \tread_address,
\t
\t output [DATA_WIDTH-1:0]\tread_data
);
\t
\t parameter DATA_WIDTH = 8;
\t parameter ADDR_WIDTH = 9;
\t parameter RAM_DEPTH = 1 << ADDR_WIDTH;
\t
\t reg [DATA_WIDTH-1:0] data [0:RAM_DEPTH-1]; // Array to store 512 8-bit words (characters)
\t
\t always @ (posedge clk, posedge Reset) begin: RAM_logic
\t\tif (Reset) begin: Reset
\t\t\tinteger i;
\t\t\tfor (i = 0; i < RAM_DEPTH; i = i + 1) begin
\t\t\t\tdata[i] <= 8\'h29; // a "Space"
\t\t\tend\t\t\t
\t\tend else if (write) begin
\t\t\tdata[write_address] <= write_data;
\t\tend
\t end
\t
\t assign read_data = data[read_address];
endmodule\r
|
// Listing 14.7
module textMenu_graph
(
input wire clk, reset,
input wire [2:0] item_selector,
input wire [9:0] pix_x, pix_y,
\t input wire window_selector,
output wire graph_on,
output reg [2:0] graph_rgb
);
// costant and signal declaration
// x, y coordinates (0,0) to (639,479)
localparam MAX_X = 640;
localparam MAX_Y = 480;
\t//Top menu text window sections
\tlocalparam itemTextMenu1 = 4'd1;
\tlocalparam itemTextMenu2 = 4'd2;
\tlocalparam itemTextMenu3 = 4'd3;
\tlocalparam itemTextMenu4 = 4'd4;
\tlocalparam itemTextMenu5 = 4'd5;
\tlocalparam itemTextMenu6 = 4'd6;
\t
\t//Main menu dialog sections
\tlocalparam itemMainMenu1=1'b0;
\tlocalparam itemMainMenu2=1'b1;
\t
\t//Menu main window vertical limits
\tlocalparam topMenu_main_y_limit_top = 115;
\tlocalparam topMenu_main_y_limit_bottom = 288;
\t
\t//Top menu text window vertical limits
\tlocalparam topMenu_y_limit_top = 0;
\tlocalparam topMenu_y_limit_bottom = 80;
\t
\t//Top menu text window horizontal limits
\tlocalparam topMenu_x_limit_left=0;
\tlocalparam topMenu_x_limit_right=640;
\t
\t//Top menu main window horizontal limits
\tlocalparam topMenu_main_x_limit_left=186;
\tlocalparam topMenu_main_x_limit_right=416;
\t
\t//Top menu items sections horizontal each region
\tlocalparam topMenu_x_open_limit_left=10;
\tlocalparam topMenu_x_open_limit_right=topMenu_x_open_limit_left+60;
\tlocalparam topMenu_x_save_limit_left=topMenu_x_open_limit_right+10;
\tlocalparam topMenu_x_save_limit_right=topMenu_x_save_limit_left+60;
\tlocalparam topMenu_x_exit_limit_left=topMenu_x_save_limit_right+10;
\tlocalparam topMenu_x_exit_limit_right=topMenu_x_exit_limit_left+60;
\tlocalparam topMenu_x_center_width=topMenu_x_exit_limit_right+210;
\tlocalparam topMenu_x_caps_limit_left=topMenu_x_center_width+10;
\tlocalparam topMenu_x_caps_limit_right=topMenu_x_caps_limit_left+60;
\tlocalparam topMenu_x_color_limit_left=topMenu_x_caps_limit_right+10;
\tlocalparam topMenu_x_color_limit_right=topMenu_x_color_limit_left+60;
\tlocalparam topMenu_x_size_limit_left=topMenu_x_color_limit_right+10;
\tlocalparam topMenu_x_size_limit_right=topMenu_x_size_limit_left+60;
\t
\tlocalparam topMenu_main_y_item_top_limit= topMenu_main_y_limit_top+10; //////////
\tlocalparam topMenu_main_y_item_bottom_limit= topMenu_main_y_item_top_limit+45;
\tlocalparam topMenu_main_x_item_left_limit= topMenu_main_x_limit_left;
\tlocalparam topMenu_main_x_item_right_limit= topMenu_main_x_limit_left+60;
\t
\t
\t//Top menu items vertical limits
\tlocalparam topMenu_y_item_top_limit=topMenu_y_limit_top+17;
\tlocalparam topMenu_y_item_bottom_limit=topMenu_y_item_top_limit+45;
\t
\twire menu_mostrar_separador;
\twire menu_mostrar;
\t
\tassign menu_mostrar_separador = (topMenu_x_limit_left<=pix_x) && (pix_x <= topMenu_x_limit_right) &&
\t\t\t\t\t\t\t (topMenu_y_limit_bottom-2<=pix_y) && (pix_y <= topMenu_y_limit_bottom);
\tassign menu_mostrar=((topMenu_main_y_limit_top<=pix_y) && (pix_y <= topMenu_main_y_limit_top+1) &&
\t\t\t\t\t\t\t\t(topMenu_main_x_limit_left<=pix_x) && (pix_x <= topMenu_main_x_limit_right)) ||
\t\t\t\t\t\t\t\t((topMenu_main_y_limit_bottom-1<=pix_y) && (pix_y <= topMenu_main_y_limit_bottom) &&
\t\t\t\t\t\t\t\t(topMenu_main_x_limit_left<=pix_x) && (pix_x <= topMenu_main_x_limit_right)) ||
\t\t\t\t\t\t\t\t((topMenu_main_y_limit_top<=pix_y) && (pix_y <= topMenu_main_y_limit_bottom) &&
\t\t\t\t\t\t\t\t(topMenu_main_x_limit_left<=pix_x) && (pix_x <= topMenu_main_x_limit_left+1)) ||
\t\t\t\t\t\t\t\t((topMenu_main_y_limit_top<=pix_y) && (pix_y <= topMenu_main_y_limit_bottom) &&
\t\t\t\t\t\t\t\t(topMenu_main_x_limit_right-1<=pix_x) && (pix_x <= topMenu_main_x_limit_right));
\t
\treg[5:0] show_item_selector;
\treg [1:0] show_item_main_selector;
\t
\treg [2:0] currentItemTextMenu;
\treg currentItemMainMenu;
\t
always @ (*) begin
\t\t
\t\tcurrentItemTextMenu= item_selector;
\t
\t\tcase(currentItemTextMenu)
\t\t
\t\t\titemTextMenu1: begin
\t\t\t\t\t\t\tshow_item_selector[0] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_open_limit_right-1<=pix_x) && (pix_x <= topMenu_x_open_limit_right));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titemTextMenu2: begin
\t\t\t\t\t\t\tshow_item_selector[1] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_save_limit_right-1<=pix_x) && (pix_x <= topMenu_x_save_limit_right));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titemTextMenu3: begin
\t\t\t\t\t\t\tshow_item_selector[2] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_exit_limit_right-1<=pix_x) && (pix_x <= topMenu_x_exit_limit_right));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titemTextMenu4: begin
\t\t\t\t\t\t\tshow_item_selector[3] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_caps_limit_right-1<=pix_x) && (pix_x <= topMenu_x_caps_limit_right));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titemTextMenu5: begin
\t\t\t\t\t\t\tshow_item_selector[4] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_color_limit_right-1<=pix_x) && (pix_x <= topMenu_x_color_limit_right));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titemTextMenu6: begin
\t\t\t\t\t\t\tshow_item_selector[5] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_right)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_left+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_x_size_limit_right-1<=pix_x) && (pix_x <= topMenu_x_size_limit_right));
\t\t\t\t\t\t\tend
\t\t\tdefault: \tbegin
\t\t\t\t\t\t\tshow_item_selector= 3'b000;\t\t\t
\t\t\t\t\t\t\tend
\t\tendcase
\tend
\t
\t
\talways @ (*) begin
\t\t
\t\tcurrentItemMainMenu =item_selector[1:0];
\t
\t\tcase(currentItemMainMenu)
\t\t
\t\t\titemMainMenu1: begin
\t\t\t\t\t\t\tshow_item_main_selector[0] = ((topMenu_main_y_item_top_limit<=pix_y) && (pix_y <= topMenu_main_y_item_top_limit+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_main_y_item_top_limit-1<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_main_y_item_top_limit<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_left_limit+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_main_y_item_top_limit<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_main_x_item_right_limit-1<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit));
\t\t\t\t\t\t\tend
\t\t\t
\t\t\titemMainMenu2: begin
\t\t\t\t\t\t\tshow_item_main_selector[1] = ((topMenu_main_y_item_top_limit+50<=pix_y) && (pix_y <= topMenu_main_y_item_top_limit+50+1) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_main_y_item_top_limit+50-1<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit+50) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_main_y_item_top_limit+50<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit+50) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_main_x_item_left_limit<=pix_x) && (pix_x <= topMenu_main_x_item_left_limit+1)) ||
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((topMenu_main_y_item_top_limit+50<=pix_y) && (pix_y <= topMenu_main_y_item_bottom_limit+50) &&
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(topMenu_main_x_item_right_limit-1<=pix_x) && (pix_x <= topMenu_main_x_item_right_limit));
\t\t\t\t\t\t\tend
\t\t\tdefault: \tbegin
\t\t\t\t\t\t\tshow_item_main_selector= 2'b00;\t\t\t
\t\t\t\t\t\t\tend
\t\tendcase
\tend
//--------------------------------------------
// rgb multiplexing circuit
//--------------------------------------------
always @* begin
\tgraph_rgb = 3'b111;
\t\tif(window_selector) begin
\t\t\tif (menu_mostrar_separador)
\t\t\t\tgraph_rgb = 3'b000;
\t\t\telse if (show_item_selector[0] || show_item_selector[1] || show_item_selector[2] ||
\t\tshow_item_selector[3] || show_item_selector[4] || show_item_selector[5])
\t\t\t\t\tgraph_rgb = 3'b000;
\t\t\telse
\t\t\t\tgraph_rgb = 3'b111; // black background
\t\tend
\t\telse if (!window_selector) begin
\t\t\tif(menu_mostrar)
\t\t\t\tgraph_rgb=3'b000;
\t\t\telse if(show_item_main_selector[0] || show_item_main_selector[1])
\t\t\t\tgraph_rgb =3'b000;
\t\t\telse
\t\t\t\tgraph_rgb = 3'b111; // black background
\t\tend
\tend
\t
\tassign graph_on=((show_item_selector[0] || show_item_selector[1] || show_item_selector[2] ||
\t\t\t\t\t\t show_item_selector[3] || show_item_selector[4] || show_item_selector[5] || menu_mostrar_separador) && window_selector) ||
\t\t\t\t\t\t((/*show_item_main_selector[0]||show_item_main_selector[1]||*/ menu_mostrar) && !window_selector);
endmodule
|
`timescale 1ns / 1ps\r
\r
module text_editor_keyboard_controller(\r
input sys_Clk,\r
\t input PS2_Clk,\r
input Reset,\r
inout PS2KeyboardData,\r
inout PS2KeyboardClk,\r
output reg [7:0] KeyData,\r
output reg KeyReleased\r
);\t\r
\t \r
\t\r
\t/************************************************************************\r
\t * LOCAL SIGNALS *\r
\t ************************************************************************/\r
\treg [1:0] state;\t\t\r
\tlocalparam \t\r
\t\tI = 2'b00,\r
\t\tBAT = 2'b01,\r
\t\tDATA = 2'b10,\r
\t\tUNK = 2'bXX;\r
\t\r
\twire [7:0]\treceived_data;\r
\twire\t\t\treceived_data_en;\r
\treg [7:0] previous_word;\r
\t\r
\treg send_command;\r
\treg [7:0] the_command;\r
\twire command_sent;\r
\t\r
\t\r
\t/************************************************************************\r
\t * PS2 KEYBOARD *\r
\t ************************************************************************/\t\r
\tPS2_Controller PS2_Keyboard_Controller(\r
\t\t// Inputs\r
\t\t.CLOCK_50(PS2_Clk),\r
\t\t.reset(Reset),\r
\t\t.the_command(the_command),\r
\t\t.send_command(send_command),\r
\r
\t\t// Bidirectionals\r
\t\t.PS2_CLK(PS2KeyboardClk),\t\t\t\t// PS2 Clock\r
\t\t.PS2_DAT(PS2KeyboardData),\t\t\t\t// PS2 Data\r
\r
\t\t// Outputs\r
\t\t.command_was_sent(command_sent),\r
\t\t.error_communication_timed_out( ),\r
\t\t.received_data(received_data),\r
\t\t.received_data_en(received_data_en)\t// If 1 - new data has been received\r
\t);\r
\t\r
\t/************************************************************************\r
\t * STATE MACHINE *\r
\t ************************************************************************/\t\r
\talways @ (posedge sys_Clk, posedge Reset) begin: STATE_MACHINE\r
\t\tif(Reset) begin\r
\t\t\t\tstate <= I;\r
\t\t\t\tprevious_word <= 8'hXX;\r
\t\t\t\tsend_command <= 1'bX;\r
\t\t\t\tthe_command <= 8'hXX;\r
\t\t\t\tKeyData <= 8'hXX;\r
\t\tend else\r
\t\t\tcase(state)\t\r
\t\t\t\t\tI: begin\r
\t\t\t\t\t\tstate <= BAT;\r
\t\t\t\t\t\t\r
\t\t\t\t\t\tKeyData <= 8'h00;\r
\t\t\t\t\t\tprevious_word <= 8'h00;\r
\t\t\t\t\t\tKeyReleased <= 1'b0;\r
\t\t\t\t\t\tsend_command <= 1'b1;\r
\t\t\t\t\t\tthe_command <= 8'hFF;\t// RESET KEYBOARD\r
\t\t\t\t\tend\r
\t\t\t\t\t\r
\t\t\t\t\tBAT: begin\r
\t\t\t\t\t\tif (command_sent) begin\r
\t\t\t\t\t\t\tsend_command <= 1'b0;\r
\t\t\t\t\t\tend\r
\t\t\t\t\t\tcase (received_data)\r
\t\t\t\t\t\t\t8'hAA: begin\t\t\t// SUCCESSFUL POST\r
\t\t\t\t\t\t\t\tstate <= DATA;\r
\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t8'hFC: begin\r
\t\t\t\t\t\t\t\tsend_command <= 1'b1;\t// TRY TO POST AGAIN\r
\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\tdefault: begin\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\tend\r
\t\t\t\t\t\tendcase\r
\t\t\t\t\tend\r
\t\t\t\t\t\r
\t\t\t\t\tDATA: begin\r
\t\t\t\t\t\tif (command_sent) begin\r
\t\t\t\t\t\t\tsend_command <= 1'b0;\r
\t\t\t\t\t\tend\r
\t\t\t\t\t\t\r
\t\t\t\t\t\tif (KeyReleased) begin\r
\t\t\t\t\t\t\tKeyReleased <= 1'b0;\r
\t\t\t\t\t\tend\r
\t\t\t\t\t\t\r
\t\t\t\t\t\tif (received_data_en) begin\r
\t\t\t\t\t\t\tprevious_word <= received_data;\r
\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\tcase(received_data)\r
\t\t\t\t\t\t\t\t8'hF0: begin\r
\t\t\t\t\t\t\t\t\t// Key Released\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'hFA: begin\r
\t\t\t\t\t\t\t\t\t// Acknowledge\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'hAA: begin\r
\t\t\t\t\t\t\t\t\t// Self Test Passed\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'hEE: begin\r
\t\t\t\t\t\t\t\t\t// Echo Response\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'hFE: begin\r
\t\t\t\t\t\t\t\t\t// Resend Request\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'h00: begin\r
\t\t\t\t\t\t\t\t\t// Error\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'hFF: begin\r
\t\t\t\t\t\t\t\t\t// Error\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'h12: begin\r
\t\t\t\t\t\t\t\t\t// Shift\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'h59: begin\r
\t\t\t\t\t\t\t\t\t// Shift\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'h58: begin\r
\t\t\t\t\t\t\t\t\t// Caps\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'h0D: begin\r
\t\t\t\t\t\t\t\t\t// Tab\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'h14: begin\r
\t\t\t\t\t\t\t\t\t// Ctrl\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'h11: begin\r
\t\t\t\t\t\t\t\t\t// Alt\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'hE0: begin\r
\t\t\t\t\t\t\t\t\t// Extra\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\t8'h5A: begin\r
\t\t\t\t\t\t\t\t\t// Enter\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\t\r
\t\t\t\t\t\t\t\tdefault: begin\r
\t\t\t\t\t\t\t\t\tif (previous_word == 8'hF0) begin // IF PREV WORD WAS KEY RELEASED SCAN CODE\r
\t\t\t\t\t\t\t\t\t\tKeyData <= received_data;\r
\t\t\t\t\t\t\t\t\t\tKeyReleased <= 1'b1;\r
\t\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\t\tend\r
\t\t\t\t\t\t\tendcase\r
\t\t\t\t\t\tend\r
\t\t\t\t\tend\r
\t\t\t\t\t\r
\t\t\t\t\tdefault:\r
\t\t\t\t\t\tstate <= UNK;\r
\t\t\tendcase\r
\tend\r
endmodule\r
\r
|
`timescale 1ns / 1ps\r
\r
module Altera_UP_PS2_Data_In (
\t// Inputs
\tclk,
\treset,
\twait_for_incoming_data,
\tstart_receiving_data,
\tps2_clk_posedge,
\tps2_clk_negedge,
\tps2_data,
\t// Bidirectionals
\t// Outputs
\treceived_data,
\treceived_data_en\t\t\t// If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input\t\t\t\tclk;
input\t\t\t\treset;
input\t\t\t\twait_for_incoming_data;
input\t\t\t\tstart_receiving_data;
input\t\t\t\tps2_clk_posedge;
input\t\t\t\tps2_clk_negedge;
input\t\t\t \tps2_data;
// Bidirectionals
// Outputs
output reg\t[7:0]\treceived_data;
output reg\t\t \treceived_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam\tPS2_STATE_0_IDLE\t\t\t= 3'h0,
\t\t\tPS2_STATE_1_WAIT_FOR_DATA\t= 3'h1,
\t\t\tPS2_STATE_2_DATA_IN\t\t\t= 3'h2,
\t\t\tPS2_STATE_3_PARITY_IN\t\t= 3'h3,
\t\t\tPS2_STATE_4_STOP_IN\t\t\t= 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg\t\t\t[3:0]\tdata_count;
reg\t\t\t[7:0]\tdata_shift_reg;
// State Machine Registers
reg\t\t\t[2:0]\tns_ps2_receiver;
reg\t\t\t[2:0]\ts_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\ts_ps2_receiver <= PS2_STATE_0_IDLE;
\telse
\t\ts_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
\t// Defaults
\tns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
\tPS2_STATE_0_IDLE:
\t\tbegin
\t\t\tif ((wait_for_incoming_data == 1'b1) &&
\t\t\t\t\t(received_data_en == 1'b0))
\t\t\t\tns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
\t\t\telse if ((start_receiving_data == 1'b1) &&
\t\t\t\t\t(received_data_en == 1'b0))
\t\t\t\tns_ps2_receiver = PS2_STATE_2_DATA_IN;
\t\t\telse
\t\t\t\tns_ps2_receiver = PS2_STATE_0_IDLE;
\t\tend
\tPS2_STATE_1_WAIT_FOR_DATA:
\t\tbegin
\t\t\tif ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
\t\t\t\tns_ps2_receiver = PS2_STATE_2_DATA_IN;
\t\t\telse if (wait_for_incoming_data == 1'b0)
\t\t\t\tns_ps2_receiver = PS2_STATE_0_IDLE;
\t\t\telse
\t\t\t\tns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
\t\tend
\tPS2_STATE_2_DATA_IN:
\t\tbegin
\t\t\tif ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
\t\t\t\tns_ps2_receiver = PS2_STATE_3_PARITY_IN;
\t\t\telse
\t\t\t\tns_ps2_receiver = PS2_STATE_2_DATA_IN;
\t\tend
\tPS2_STATE_3_PARITY_IN:
\t\tbegin
\t\t\tif (ps2_clk_posedge == 1'b1)
\t\t\t\tns_ps2_receiver = PS2_STATE_4_STOP_IN;
\t\t\telse
\t\t\t\tns_ps2_receiver = PS2_STATE_3_PARITY_IN;
\t\tend
\tPS2_STATE_4_STOP_IN:
\t\tbegin
\t\t\tif (ps2_clk_posedge == 1'b1)
\t\t\t\tns_ps2_receiver = PS2_STATE_0_IDLE;
\t\t\telse
\t\t\t\tns_ps2_receiver = PS2_STATE_4_STOP_IN;
\t\tend
\tdefault:
\t\tbegin
\t\t\tns_ps2_receiver = PS2_STATE_0_IDLE;
\t\tend
\tendcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tdata_count\t<= 3'h0;
\telse if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
\t\t\t(ps2_clk_posedge == 1'b1))
\t\tdata_count\t<= data_count + 3'h1;
\telse if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
\t\tdata_count\t<= 3'h0;
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tdata_shift_reg\t\t\t<= 8'h00;
\telse if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
\t\t\t(ps2_clk_posedge == 1'b1))
\t\tdata_shift_reg\t<= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\treceived_data\t\t<= 8'h00;
\telse if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
\t\treceived_data\t<= data_shift_reg;
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\treceived_data_en\t\t<= 1'b0;
\telse if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
\t\t\t(ps2_clk_posedge == 1'b1))
\t\treceived_data_en\t<= 1'b1;
\telse
\t\treceived_data_en\t<= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
`timescale 1ns / 1ps
module Button_Filter(
input clk, button_in,
\toutput hold, filtered
\t);
\t
\treg [24:0] holdtime_c;
\treg hold, filtered;
\t
\tinitial begin
\t\thold = 1'bx;
\t\tfiltered = 1'bx;
\tend
\t
\talways @(posedge clk) begin
\t\tif (button_in != hold) begin
\t\t\thold = button_in;
\t\t\tholdtime_c = 0;
\t\tend
\t\telse if (holdtime_c == 25'b1111111111111111111111111)
\t\t\tfiltered = hold;
\t\telse
\t\t\tholdtime_c = holdtime_c + 1;
\tend
\t
endmodule
|
`timescale 1ns / 1ps
module text_editor_top(
\t\tMemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS, \t// Disable the three memory chips
\t\tClkPort, \t\t\t\t\t\t\t\t\t// the 100 MHz incoming clock signal
\t\tBtnC,\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t// the middle button used as Reset
\t\tLd7, Ld6, Ld5, Ld4, Ld3, Ld2, Ld1, Ld0,
\t\tAn3, An2, An1, An0,\t\t\t\t\t\t\t\t\t\t// 4 anodes
\t\tCa, Cb, Cc, Cd, Ce, Cf, Cg,\t\t\t\t\t\t\t// 7 cathodes
\t\tDp,\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t// Dot Point Cathode on SSDs
\t\tPS2KeyboardData,\t\t\t\t\t\t\t\t\t\t\t// PS2 Keyboard data bus
\t\tPS2KeyboardClk,\t\t\t\t\t\t\t\t\t\t\t// PS2 Keyboard data clock
\t\tvga_h_sync,\t\t\t\t\t\t\t\t\t\t\t\t\t// VGA Output Horizontal Sync signal
\t\tvga_v_sync,\t\t\t\t\t\t\t\t\t\t\t\t\t// VGA Output Vertical Sync signal
\t\tvga_r,\t\t\t\t\t\t\t\t\t\t\t\t\t\t// Red value for current scanning pixel
\t\tvga_g,\t\t\t\t\t\t\t\t\t\t\t\t\t\t// Green value for current scanning pixel
\t\tvga_b\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t// Blue value for current scanning pixel
\t );
\t
\t/************************************************************************
\t * INPUTS *
\t ************************************************************************/
\tinput\t\tClkPort;\t
\tinput\t\tBtnC;
\t
\t/************************************************************************
\t * BIDIRECTIONALS *
\t ************************************************************************/
\tinout\t\tPS2KeyboardData, PS2KeyboardClk;
\t
\t
\t/************************************************************************
\t * OUTPUTS *
\t ************************************************************************/
\toutput \tMemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS;
\t
\toutput\tLd7, Ld6, Ld5, Ld4, Ld3, Ld2, Ld1, Ld0;
\t
\toutput \tCg, Cf, Ce, Cd, Cc, Cb, Ca, Dp;
\toutput \tAn0, An1, An2, An3;
\t
\toutput \tvga_h_sync, vga_v_sync, vga_r, vga_g, vga_b;
\t
\t/************************************************************************
\t * LOCAL SIGNALS *
\t ************************************************************************/\t
\twire\t\t\tReset, ClkPort;
\twire\t\t\tboard_clk, sys_clk, PS2_clk, VGA_clk, cursor_clk;
\twire [1:0] \tssdscan_clk;
\treg [26:0]\tDIV_CLK;
\t
\treg [3:0]\tSSD;
\twire [3:0]\tSSD3, SSD2, SSD1, SSD0;
\treg [7:0] SSD_CATHODES;
\t
\twire [7:0]\tKeyData;
\twire\t\t\tKeyReleased;
\treg [7:0] CurrentKey;
\t
\treg [8:0]\tdocument_pointer;
\treg [8:0] write_location;
\treg\t\t\twrite_to_RAM;
\twire [7:0] RAM_data;
\twire [9:0] read_address;
\t
\treg vga_r, vga_g, vga_b;
\t
\tassign { Ld7, Ld6, Ld5, Ld4, Ld3, Ld2, Ld1, Ld0\t} = document_pointer[7:0];
\t
\tassign Reset = BtnC;
\t
\t// Disable the three memories so that they do not interfere with the rest of the design.
\tassign {MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS} = 5\'b11111;
\t
\t
\t/************************************************************************
\t * CLOCK DIVISION *
\t ************************************************************************/
\tBUFGP BUFGP1 (board_clk, ClkPort); \t
\t// Our clock is too fast (100MHz) for SSD scanning
\t// create a series of slower "divided" clocks
\t// each successive bit is 1/2 frequency
\talways @(posedge board_clk, posedge Reset) begin\t\t\t\t\t\t\t
\t\tif (Reset)
\t\t\tDIV_CLK <= 0;
\t\telse
\t\t\tDIV_CLK <= DIV_CLK + 1\'b1;
\tend
\t
\tassign\tsys_clk = board_clk;\t\t// 100 MHz
\tassign\tPS2_clk = DIV_CLK[0];\t// 50 MHz
\tassign VGA_clk = DIV_CLK[1];\t// 25 MHz
\tassign cursor_clk = DIV_CLK[26];\t// .75 Hz
\t
\t
\t/************************************************************************
\t * VGA Control *
\t ************************************************************************/\t
\tparameter RAM_size = 10\'d512;\t\t\t\t// Size of the RAM
\tparameter write_area = RAM_size - 10\'d2;\t// Allowable write area in the RAM (last location used as a null location)
\tparameter char_dim = 10\'d16;\t\t\t\t\t// Dimension of a character (16x16 bits)
\tparameter char_scale_i = 10\'d2;\t\t\t\t\t// Initial character scale
\tparameter row_length_i = 10\'d18;\t\t\t\t\t// Initial length of a row (number of columns)
\tparameter col_length_i = 10\'d29;\t\t\t\t\t// Initial length of a column (number of rows)
\t
\treg [9:0] char_scale;
\treg [9:0] row_length;
\treg [9:0] col_length;
\treg [9:0] scroll;
\t
\treg text_red;
\treg text_green;
\treg text_blue;
\t
\twire inDisplayArea;
\twire [9:0] CounterX;
\twire [9:0] CounterY;
\t
\twire [9:0] CounterXDiv;
\twire [9:0] CounterYDiv;
\tassign CounterXDiv = CounterX / char_scale;
\tassign CounterYDiv = CounterY / char_scale;
\t
\twire shouldDraw;
\tassign shouldDraw = CounterXDiv < char_dim * row_length && CounterYDiv < char_dim * col_length;
\t
\twire [0:255] relativePixel;
\tassign relativePixel = CounterXDiv % char_dim + CounterYDiv % char_dim * char_dim;
\t
\twire drawCursor;
\tassign drawCursor = read_address == document_pointer && Cursor[relativePixel] && cursor_clk;
\t
\tassign read_address = (CounterXDiv / char_dim + CounterYDiv / char_dim * row_length + scroll * row_length) < RAM_size - 1\'b1 ?
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t(CounterXDiv / char_dim + CounterYDiv / char_dim * row_length + scroll * row_length) :
\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tRAM_size - 1\'b1;
\t
\thvsync_generator vgaSyncGen(
\t\t// Inputs
\t\t.clk(VGA_clk),
\t\t.reset(Reset),
\t\t
\t\t// Outputs
\t\t.vga_h_sync(vga_h_sync),
\t\t.vga_v_sync(vga_v_sync),
\t\t.inDisplayArea(inDisplayArea),
\t\t.CounterX(CounterX),
\t\t.CounterY(CounterY)
\t);
\t
\talways @(posedge VGA_clk) begin
\t\tvga_r <= Red & inDisplayArea;
\t\tvga_g <= Green & inDisplayArea;
\t\tvga_b <= Blue & inDisplayArea;
\tend
\t
\twire Red = shouldDraw && ((~drawCursor && text_red && toDraw[relativePixel]) || (drawCursor && !text_red) || (drawCursor && text_red && text_green && text_blue));
\twire Blue = shouldDraw && ((~drawCursor && text_blue && toDraw[relativePixel]) || (drawCursor && !text_blue));
\twire Green = shouldDraw && ((~drawCursor && text_green && toDraw[relativePixel]) || (drawCursor && !text_green));
\t
\twire [0:255] toDraw;
\tassign toDraw = \tRAM_data == 8\'h70 ? Block :
\t\t\t\t\t\t\tRAM_data == 8\'h49 ? Period :
\t\t\t\t\t\t\tRAM_data == 8\'h41 ? Comma :
\t\t\t\t\t\t\tRAM_data == 8\'h52 ? Apost :
\t\t\t\t\t\t\tRAM_data == 8\'h1C ? A :
\t\t\t\t\t\t\tRAM_data == 8\'h32 ? B :
\t\t\t\t\t\t\tRAM_data == 8\'h21 ? C :
\t\t\t\t\t\t\tRAM_data == 8\'h23 ? D :
\t\t\t\t\t\t\tRAM_data == 8\'h24 ? E :
\t\t\t\t\t\t\tRAM_data == 8\'h2B ? F :
\t\t\t\t\t\t\tRAM_data == 8\'h34 ? G :
\t\t\t\t\t\t\tRAM_data == 8\'h33 ? H :
\t\t\t\t\t\t\tRAM_data == 8\'h43 ? I :
\t\t\t\t\t\t\tRAM_data == 8\'h3B ? J :
\t\t\t\t\t\t\tRAM_data == 8\'h42 ? K :
\t\t\t\t\t\t\tRAM_data == 8\'h4B ? L :
\t\t\t\t\t\t\tRAM_data == 8\'h3A ? M :
\t\t\t\t\t\t\tRAM_data == 8\'h31 ? N :
\t\t\t\t\t\t\tRAM_data == 8\'h44 ? O :
\t\t\t\t\t\t\tRAM_data == 8\'h4D ? P :
\t\t\t\t\t\t\tRAM_data == 8\'h15 ? Q :
\t\t\t\t\t\t\tRAM_data == 8\'h2D ? R :
\t\t\t\t\t\t\tRAM_data == 8\'h1B ? S :
\t\t\t\t\t\t\tRAM_data == 8\'h2C ? T :
\t\t\t\t\t\t\tRAM_data == 8\'h3C ? U :
\t\t\t\t\t\t\tRAM_data == 8\'h2A ? V :
\t\t\t\t\t\t\tRAM_data == 8\'h1D ? W :
\t\t\t\t\t\t\tRAM_data == 8\'h22 ? X :
\t\t\t\t\t\t\tRAM_data == 8\'h35 ? Y :
\t\t\t\t\t\t\tRAM_data == 8\'h1A ? Z :\r
\t\t\t\t\t\t\tRAM_data == 8\'h16 ? num1 :\r
\t\t\t\t\t\t\tRAM_data == 8\'h1E ? num2 :
\t\t\t\t\t\t\tRAM_data == 8\'h26 ? num3 :
\t\t\t\t\t\t\tRAM_data == 8\'h25 ? num4 :
\t\t\t\t\t\t\tRAM_data == 8\'h2E ? num5 :
\t\t\t\t\t\t\tRAM_data == 8\'h36 ? num6 :
\t\t\t\t\t\t\tRAM_data == 8\'h3D ? num7 :
\t\t\t\t\t\t\tRAM_data == 8\'h3E ? num8 :
\t\t\t\t\t\t\tRAM_data == 8\'h46 ? num9 :
\t\t\t\t\t\t\tRAM_data == 8\'h45 ? num0 :
\t\t\t\t\t\t\t256\'d0;
\t
\tparameter [0:255] Cursor = 256\'hC000C000C000C000C000C000C000C000C000C000C000C000C000C000C000C000;
\tparameter [0:255] Block = 256\'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
\tparameter [0:255] Period = 256\'h0000000000000000000000000000000000000000000000000000E000E000E000;
\tparameter [0:255] Comma = 256\'h000000000000000000000000000000000000000000000000000070007000E000;
\tparameter [0:255] Apost = 256\'h070007000E000000000000000000000000000000000000000000000000000000;
\tparameter [0:255] A = 256\'h00001FE03870387070387038E01CE01CE01CFFFCFFFCE01CE01CE01CE01CE01C;
\tparameter [0:255] B = 256\'h0000FFC0FFF0F078F03CF03CF038FFE0FFE0F038F03CF03CF03CF07CFFF8FFE0;
\tparameter [0:255] C = 256\'h00001FF07FFCF81EF01EE000E000E000E000E000E000E000E01EF01E7FFC1FF0;
\tparameter [0:255] D = 256\'h0000FFE0FFF8F03CF01CF00EF00EF00EF00EF00EF00EF00EF01CF03CFFF8FFE0;
\tparameter [0:255] E = 256\'h0000FFFEFFFEE000E000E000E000FFFEFFFEE000E000E000E000E000FFFEFFFE;
\tparameter [0:255] F = 256\'h0000FFFEFFFEF000F000F000F000FFFEFFFEF000F000F000F000F000F000F000;
\tparameter [0:255] G = 256\'h00003FF07FF8F01EE00EC000C000C000C000C07EC07EC00EC00EF01E7FF83FF0;
\tparameter [0:255] H = 256\'h0000E00EE00EE00EE00EE00EE00EFFFEFFFEE00EE00EE00EE00EE00EE00EE00E;
\tparameter [0:255] I = 256\'h0000FFFCFFFC07800780078007800780078007800780078007800780FFFCFFFC;
\tparameter [0:255] J = 256\'h00003FFC3FFC001C001C001C001C001C001C001CE01CE01CE01CF03C7FF83FF0;
\tparameter [0:255] K = 256\'h0000E00EE00EE01CE038E070E0E0FFC0FFC0E0E0E070E038E01CE00EE00EE00E;
\tparameter [0:255] L = 256\'h0000E000E000E000E000E000E000E000E000E000E000E000E000E000FFFCFFFC;
\tparameter [0:255] M = 256\'h0000F87CFCFCFCFCECDCEFDCE79CE31CE01CE01CE01CE01CE01CE01CE01CE01C;
\tparameter [0:255] N = 256\'h0000F81CF81CEC1CEC1CE61CE61CE31CE31CE31CE19CE19CE0DCE0DCE07CE07C;
\tparameter [0:255] O = 256\'h00003FF07878E01CE01CE01CE01CE01CE01CE01CE01CE01CE01CF03C78783FF0;
\tparameter [0:255] P = 256\'h0000FFC0FFF8F07CF03CF03CF03CF07CFFF8FFC0F000F000F000F000F000F000;
\tparameter [0:255] Q = 256\'h00003FF07878E01CE01CE01CE01CE01CE01CE01CE01CE01CE01CF03C787C0FDE;
\tparameter [0:255] R = 256\'h0000FFF0FFFCF01EF01EF01EF01EFFF0FFC0F0F0F078F03CF03CF01EF01EF01E;
\tparameter [0:255] S = 256\'h00000FF03FFCE01EE00EE00EF0007FF01FFC001EE00EE00EF00E781E3FFC07F8;
\tparameter [0:255] T = 256\'h0000FFFEFFFE0380038003800380038003800380038003800380038003800380;
\tparameter [0:255] U = 256\'h0000E00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00E783C1FF0;
\tparameter [0:255] V = 256\'h0000E00EF01EF01E783C783C3C783C783C781EF01EF00FE00FE007C003800100;
\tparameter [0:255] W = 256\'h0000E01CE01CE01CE01CE01CE01CE01CE01CE31CE79CEFDCECDCFCFCFCFCF87C;
\tparameter [0:255] X = 256\'h0000F01EF01E78783CF03CF01FE00FC007800FC01FE03CF03CF07878F03CF03C;
\tparameter [0:255] Y = 256\'h0000E00EE00E701C781C3C780FE007C003800380038003800380038003800380;
\tparameter [0:255] Z = 256\'h0000FFFEFFFE001E003C007800F001E003C00F001E003C007800F000FFFEFFFE;
\t\r
\tparameter [0:255] num1 = 256\'h0000003C00FC01DC039C071C001C001C001C001C001C001C001C001C001C001C;
\tparameter [0:255] num2 = 256\'h00000FF01FF8381C001C001C001C0038007000E001C0038007001C003FFC3FFC;
\tparameter [0:255] num3 = 256\'h00003FFC3FFC000C00180060018003C000E0003000380038003800383FF03FC0;
\tparameter [0:255] num4 = 256\'h0000007C00DC019C031C061C0C1C181C301C3FFC001C001C001C001C001C001C;
\tparameter [0:255] num5 = 256\'h00003FFC3FFC3000300030003FC001E00070003000380038007000E03FC03F00;
\tparameter [0:255] num6 = 256\'h000000E003800E0018003800380038003FE03FF03C18381838181C181FF00FE0;
\tparameter [0:255] num7 = 256\'h00003FFC3FFC001C001C001C3FFC3FFC001C001C001C001C001C001C001C001C;
\tparameter [0:255] num8 = 256\'h00001FF83FFC381C381C381C3FFC3FFC381C381C381C381C381C381C3FFC1FF8;
\tparameter [0:255] num9 = 256\'h00001FFC3FFC381C300C300C381C1FFC0FFC000C000C000C000C000C007C007C;
\tparameter [0:255] num0 = 256\'h00001FF83FFC381C381C381C381C381C381C381C381C381C381C381C3FFC1FF8;
\t
\t/************************************************************************
\t * PS2 KEYBOARD *
\t ************************************************************************/\t
\ttext_editor_keyboard_controller KeyBoard(
\t\t// Inputs
\t\t.sys_Clk(sys_clk),
\t\t.PS2_Clk(PS2_clk),
\t\t.Reset(Reset),
\t
\t\t// Bidirectionals
\t\t.PS2KeyboardData(PS2KeyboardData),
\t\t.PS2KeyboardClk(PS2KeyboardClk),
\t
\t\t// Outputs
\t\t.KeyData(KeyData),
\t\t.KeyReleased(KeyReleased)
);
\t
\t
\t/************************************************************************
\t * TEXT RAM *
\t ************************************************************************/
\t text_editor_RAM RAM(
\t\t// Inputs
\t\t.clk(sys_clk),
\t\t.Reset(Reset),
\t\t.write(write_to_RAM),
\t\t.write_address(write_location),
\t\t.write_data(CurrentKey),
\t\t.read_address(read_address[8:0]),
\t
\t\t// Outputs
\t\t.read_data(RAM_data)
\t );
\t
\t
\t/************************************************************************
\t * STATE MACHINE *
\t ************************************************************************/\t
\treg [1:0] state;\t\t
\tlocalparam \t
\t\tINI = 2\'b00,
\t\tGETKEY = 2\'b01,
\t\tEDIT = 2\'b10,
\t\tWRITE = 2\'b11,
\t\tUNK = 2\'bXX;
\t
\talways @ (posedge sys_clk, posedge Reset) begin: STATE_MACHINE
\t\tif (Reset) begin
\t\t\tCurrentKey <= 8\'hXX;
\t\t\tdocument_pointer <= 9\'bXXXXXXXXX;
\t\t\twrite_location <= 9\'bXXXXXXXXX;
\t\t\twrite_to_RAM <= 1\'bX;
\t\t\tchar_scale <= 10\'bXXXXXXXXXX;
\t\t\trow_length <= 10\'bXXXXXXXXXX;
\t\t\tcol_length <= 10\'bXXXXXXXXXX;
\t\t\tscroll <= 10\'bXXXXXXXXXX;
\t\t\ttext_red <= 1\'bX;
\t\t\ttext_green <= 1\'bX;
\t\t\ttext_blue <= 1\'bX;
\t\t\t
\t\t\tstate <= INI;
\t\tend else begin\t\t\t
\t\t\tcase (state)
\t\t\t\tINI: begin
\t\t\t\t\tstate <= GETKEY;
\t\t\t\t\t
\t\t\t\t\tCurrentKey <= 8\'h29; // SPACE
\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\tdocument_pointer <= 10\'d0;
\t\t\t\t\twrite_location <= 10\'d0;
\t\t\t\t\tchar_scale <= char_scale_i;
\t\t\t\t\trow_length <= row_length_i;
\t\t\t\t\tcol_length <= col_length_i;
\t\t\t\t\tscroll <= 10\'d0;
\t\t\t\t\ttext_red <= 1\'b0;
\t\t\t\t\ttext_green <= 1\'b1;
\t\t\t\t\ttext_blue <= 1\'b0;
\t\t\t\tend
\t\t\t\t
\t\t\t\tGETKEY: begin
\t\t\t\t\tif (KeyReleased) begin
\t\t\t\t\t\tstate <= EDIT;
\t\t\t\t\tend
\t\t\t\t\t
\t\t\t\t\tCurrentKey <= KeyData;
\t\t\t\t\t
\t\t\t\t\tcase(char_scale)
\t\t\t\t\t\t2\'d1: begin row_length <= 10\'d36; col_length <= 10\'d15; end
\t\t\t\t\t\t2\'d2: begin row_length <= 10\'d18; col_length <= 10\'d29; end
\t\t\t\t\t\t2\'d3: begin row_length <= 10\'d12; col_length <= 10\'d43; end
\t\t\t\t\t\tdefault: begin row_length <= 10\'d18; col_length <= 10\'d29; end
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t\t
\t\t\t\tEDIT: begin
\t\t\t\t\tstate <= WRITE;
\t\t\t\t\twrite_to_RAM <= 1\'b1;
\t\t\t\t\twrite_location <= document_pointer;
\t\t\t\t\t
\t\t\t\t\tcase (CurrentKey)
\t\t\t\t\t\t8\'h66: begin // BACKSPACE
\t\t\t\t\t\t\tif (document_pointer > 10\'d0) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer - 1\'b1;
\t\t\t\t\t\t\t\twrite_location <= document_pointer - 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\t\t
\t\t\t\t\t\t\tCurrentKey <= 8\'h29; // SPACE
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h6B: begin // LEFT ARROW
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (document_pointer > 10\'d0) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer - 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h74: begin // RIGHT ARROW
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (document_pointer < write_area) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer + 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h75: begin // UP ARROW
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (document_pointer >= row_length) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer - row_length;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h72: begin // DOWN ARROW
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (document_pointer <= write_area - row_length) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer + row_length;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h79: begin // + KEYPAD
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (char_scale < 10\'d3) begin
\t\t\t\t\t\t\t\tchar_scale <= char_scale + 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h7B: begin // - KEYPAD
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (char_scale > 10\'d1) begin
\t\t\t\t\t\t\t\tchar_scale <= char_scale - 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h7D: begin // PG UP
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (scroll < col_length - 2\'d2) begin
\t\t\t\t\t\t\t\tscroll <= scroll + 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h7A: begin // PG DOWN
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\tif (scroll > 10\'d0) begin
\t\t\t\t\t\t\t\tscroll <= scroll - 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h05: begin // F1 (Red color)
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\ttext_red <= ~text_red;
\t\t\t\t\t\t\tif (text_red && !text_blue) begin
\t\t\t\t\t\t\t\ttext_green <= 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h06: begin // F2 (Green color)
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\ttext_green <= ~text_green;
\t\t\t\t\t\t\tif (text_green && !text_blue && !text_red) begin
\t\t\t\t\t\t\t\ttext_green <= 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h04: begin // F3 (Blue color)
\t\t\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\t\t\t\ttext_blue <= ~text_blue;
\t\t\t\t\t\t\tif (text_blue && !text_red) begin
\t\t\t\t\t\t\t\ttext_green <= 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\t8\'h71: begin // DELETE KEY\t\t\t\t\t\t
\t\t\t\t\t\t\tCurrentKey <= 8\'h29; // SPACE
\t\t\t\t\t\tend
\t\t\t\t\t\t
\t\t\t\t\t\tdefault: begin
\t\t\t\t\t\t\tif (document_pointer < write_area) begin
\t\t\t\t\t\t\t\tdocument_pointer <= document_pointer + 1\'b1;
\t\t\t\t\t\t\tend
\t\t\t\t\t\tend
\t\t\t\t\tendcase
\t\t\t\tend
\t\t\t\t
\t\t\t\tWRITE: begin
\t\t\t\t\tstate <= GETKEY;
\t\t\t\t\twrite_to_RAM <= 1\'b0;
\t\t\t\tend
\t\t\t\t
\t\t\t\tdefault: begin
\t\t\t\t\tstate <= UNK;
\t\t\t\tend
\t\t\tendcase
\t\tend
\t
\tend
\t
\t
\t/************************************************************************
\t * SSD OUTPUT *
\t ************************************************************************/\t\t
\tassign SSD3 = 0;
\tassign SSD2 = 0;
\tassign SSD1 = KeyData[7:4];
\tassign SSD0 = KeyData[3:0];
\t
\tassign ssdscan_clk = DIV_CLK[19:18];
\t
\tassign An3\t= 1; //!(~(ssdscan_clk[1]) && ~(ssdscan_clk[0])); // when ssdscan_clk = 00 **Used for debugging, disabled in final project**
\tassign An2\t= 1; //!(~(ssdscan_clk[1]) && (ssdscan_clk[0])); // when ssdscan_clk = 01 **Used for debugging, disabled in final project**
\tassign An1\t= !((ssdscan_clk[1]) && ~(ssdscan_clk[0])); // when ssdscan_clk = 10
\tassign An0\t= !((ssdscan_clk[1]) && (ssdscan_clk[0])); // when ssdscan_clk = 11
\t
\t
\talways @ (ssdscan_clk, SSD0, SSD1, SSD2, SSD3) begin: SSD_SCAN_OUT
\t\tcase (ssdscan_clk)
\t\t\t\t 2\'b00: SSD = SSD3;
\t\t\t\t 2\'b01: SSD = SSD2;
\t\t\t\t 2\'b10: SSD = SSD1;
\t\t\t\t 2\'b11: SSD = SSD0;
\t\tendcase
\tend
\t
\t// and finally convert SSD_num to ssd
\t// We convert the output of our 4-bit 4x1 mux
\tassign {Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp} = {SSD_CATHODES};
\t// Following is Hex-to-SSD conversion
\talways @ (SSD)
\tbegin : HEX_TO_SSD
\t\tcase (SSD)
\t\t\t4\'b0000: SSD_CATHODES = 8\'b00000011; // 0
\t\t\t4\'b0001: SSD_CATHODES = 8\'b10011111; // 1
\t\t\t4\'b0010: SSD_CATHODES = 8\'b00100101; // 2
\t\t\t4\'b0011: SSD_CATHODES = 8\'b00001101; // 3
\t\t\t4\'b0100: SSD_CATHODES = 8\'b10011001; // 4
\t\t\t4\'b0101: SSD_CATHODES = 8\'b01001001; // 5
\t\t\t4\'b0110: SSD_CATHODES = 8\'b01000001; // 6
\t\t\t4\'b0111: SSD_CATHODES = 8\'b00011111; // 7
\t\t\t4\'b1000: SSD_CATHODES = 8\'b00000001; // 8
\t\t\t4\'b1001: SSD_CATHODES = 8\'b00001001; // 9
\t\t\t4\'b1010: SSD_CATHODES = 8\'b00010001; // A
\t\t\t4\'b1011: SSD_CATHODES = 8\'b11000001; // B
\t\t\t4\'b1100: SSD_CATHODES = 8\'b01100011; // C
\t\t\t4\'b1101: SSD_CATHODES = 8\'b10000101; // D
\t\t\t4\'b1110: SSD_CATHODES = 8\'b01100001; // E
\t\t\t4\'b1111: SSD_CATHODES = 8\'b01110001; // F
\t\t\tdefault: SSD_CATHODES = 8\'bXXXXXXXX; // default is not needed as we covered all cases
\t\tendcase
\tend\t
endmodule\r
|
`timescale 1ns / 1ps\r
\r
\r
module sim_menu;\r
\r
\t// Inputs\r
\treg clk;\r
\treg reset;\r
\treg boton_arriba;\r
\treg boton_abajo;\r
\treg boton_izq;\r
\treg boton_der;\r
\treg boton_elige;\r
\r
\t// Outputs\r
\twire text_red;\r
\twire text_green;\r
\twire text_blue;\r
\twire [9:0] char_scale;\r
\twire es_mayuscula;\r
\twire nuevo;\r
\twire guardar;\r
\twire cerrar;\r
\twire [2:0] where_fila;\r
\twire [2:0] where_columna;\r
\r
\t// Instantiate the Unit Under Test (UUT)\r
\tControlador_Menu_Editor uut (\r
\t\t.clk(clk), \r
\t\t.reset(reset), \r
\t\t.boton_arriba(boton_arriba), \r
\t\t.boton_abajo(boton_abajo), \r
\t\t.boton_izq(boton_izq), \r
\t\t.boton_der(boton_der), \r
\t\t.boton_elige(boton_elige), \r
\t\t.text_red(text_red), \r
\t\t.text_green(text_green), \r
\t\t.text_blue(text_blue), \r
\t\t.char_scale(char_scale), \r
\t\t.es_mayuscula(es_mayuscula), \r
\t\t.nuevo(nuevo), \r
\t\t.guardar(guardar), \r
\t\t.cerrar(cerrar), \r
\t\t.where_fila(where_fila), \r
\t\t.where_columna(where_columna)\r
\t);\r
\talways \r
\t\t#10 clk = ~clk;\r
\r
\tinitial begin\r
\t\t// Initialize Inputs\r
\t\tclk = 0;\r
\t\treset = 0;\r
\t\tboton_arriba = 0;\r
\t\tboton_abajo = 0;\r
\t\tboton_izq = 0;\r
\t\tboton_der = 0;\r
\t\tboton_elige = 0;\r
\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 1;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 1;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 1;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 1;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 1;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 1;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 1;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 1;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 1;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 1;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 1;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 1;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\t\t\r
\t\t#10;\r
\t\t\tboton_arriba = 0;\r
\t\t\tboton_abajo = 0;\r
\t\t\tboton_izq = 0;\r
\t\t\tboton_der = 0;\r
\t\t\tboton_elige = 0;\r
\r
\tend\r
\r
endmodule\r
\r
|
`timescale 1ns / 1ps\r
\r
module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
\t// Inputs
\tCLOCK_50,
\treset,
\tthe_command,
\tsend_command,
\t// Bidirectionals
\tPS2_CLK,\t\t\t\t\t// PS2 Clock
\tPS2_DAT,\t\t\t\t\t// PS2 Data
\t// Outputs
\tcommand_was_sent,
\terror_communication_timed_out,
\treceived_data,
\treceived_data_en\t\t\t// If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input\t\t\tCLOCK_50;
input\t\t\treset;
input\t[7:0]\tthe_command;
input\t\t\tsend_command;
// Bidirectionals
inout\t\t\tPS2_CLK;
inout\t\t \tPS2_DAT;
// Outputs
output\t\t\tcommand_was_sent;
output\t\t\terror_communication_timed_out;
output\t[7:0]\treceived_data;
output\t\t \treceived_data_en;
wire [7:0] the_command_w;
wire send_command_w, command_was_sent_w, error_communication_timed_out_w;
generate
\tif(INITIALIZE_MOUSE) begin
\t\tassign the_command_w = init_done ? the_command : 8'hf4;
\t\tassign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w);
\t\tassign command_was_sent = init_done ? command_was_sent_w : 0;
\t\tassign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1;
\t\t
\t\treg init_done;
\t\t
\t\talways @(posedge CLOCK_50)
\t\t\tif(reset) init_done <= 0;
\t\t\telse if(command_was_sent_w) init_done <= 1;
\t\t
\tend else begin
\t\tassign the_command_w = the_command;
\t\tassign send_command_w = send_command;
\t\tassign command_was_sent = command_was_sent_w;
\t\tassign error_communication_timed_out = error_communication_timed_out_w;
\tend
endgenerate
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam\tPS2_STATE_0_IDLE\t\t\t= 3'h0,
\t\t\tPS2_STATE_1_DATA_IN\t\t\t= 3'h1,
\t\t\tPS2_STATE_2_COMMAND_OUT\t\t= 3'h2,
\t\t\tPS2_STATE_3_END_TRANSFER\t= 3'h3,
\t\t\tPS2_STATE_4_END_DELAYED\t\t= 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire\t\t\tps2_clk_posedge;
wire\t\t\tps2_clk_negedge;
wire\t\t\tstart_receiving_data;
wire\t\t\twait_for_incoming_data;
// Internal Registers
reg\t\t[7:0]\tidle_counter;
reg\t\t\t\tps2_clk_reg;
reg\t\t\t\tps2_data_reg;
reg\t\t\t\tlast_ps2_clk;
// State Machine Registers
reg\t\t[2:0]\tns_ps2_transceiver;
reg\t\t[2:0]\ts_ps2_transceiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
\tif (reset == 1'b1)
\t\ts_ps2_transceiver <= PS2_STATE_0_IDLE;
\telse
\t\ts_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*)
begin
\t// Defaults
\tns_ps2_transceiver = PS2_STATE_0_IDLE;
case (s_ps2_transceiver)
\tPS2_STATE_0_IDLE:
\t\tbegin
\t\t\tif ((idle_counter == 8'hFF) &&
\t\t\t\t\t(send_command == 1'b1))
\t\t\t\tns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
\t\t\telse if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
\t\t\t\tns_ps2_transceiver = PS2_STATE_1_DATA_IN;
\t\t\telse
\t\t\t\tns_ps2_transceiver = PS2_STATE_0_IDLE;
\t\tend
\tPS2_STATE_1_DATA_IN:
\t\tbegin
\t\t\tif ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/)
\t\t\t\tns_ps2_transceiver = PS2_STATE_0_IDLE;
\t\t\telse
\t\t\t\tns_ps2_transceiver = PS2_STATE_1_DATA_IN;
\t\tend
\tPS2_STATE_2_COMMAND_OUT:
\t\tbegin
\t\t\tif ((command_was_sent == 1'b1) ||
\t\t\t\t(error_communication_timed_out == 1'b1))
\t\t\t\tns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
\t\t\telse
\t\t\t\tns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
\t\tend
\tPS2_STATE_3_END_TRANSFER:
\t\tbegin
\t\t\tif (send_command == 1'b0)
\t\t\t\tns_ps2_transceiver = PS2_STATE_0_IDLE;
\t\t\telse if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
\t\t\t\tns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
\t\t\telse
\t\t\t\tns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
\t\tend
\tPS2_STATE_4_END_DELAYED:\t
\t\tbegin
\t\t\tif (received_data_en == 1'b1)
\t\t\tbegin
\t\t\t\tif (send_command == 1'b0)
\t\t\t\t\tns_ps2_transceiver = PS2_STATE_0_IDLE;
\t\t\t\telse
\t\t\t\t\tns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
\t\t\tend
\t\t\telse
\t\t\t\tns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
\t\tend\t
\tdefault:
\t\t\tns_ps2_transceiver = PS2_STATE_0_IDLE;
\tendcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
\tif (reset == 1'b1)
\tbegin
\t\tlast_ps2_clk\t<= 1'b1;
\t\tps2_clk_reg\t\t<= 1'b1;
\t\tps2_data_reg\t<= 1'b1;
\tend
\telse
\tbegin
\t\tlast_ps2_clk\t<= ps2_clk_reg;
\t\tps2_clk_reg\t\t<= PS2_CLK;
\t\tps2_data_reg\t<= PS2_DAT;
\tend
end
always @(posedge CLOCK_50)
begin
\tif (reset == 1'b1)
\t\tidle_counter <= 6'h00;
\telse if ((s_ps2_transceiver == PS2_STATE_0_IDLE) &&
\t\t\t(idle_counter != 8'hFF))
\t\tidle_counter <= idle_counter + 6'h01;
\telse if (s_ps2_transceiver != PS2_STATE_0_IDLE)
\t\tidle_counter <= 6'h00;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign ps2_clk_posedge =
\t\t\t((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge =
\t\t\t((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data\t\t= (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data\t=
\t\t\t(s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_PS2_Data_In PS2_Data_In (
\t// Inputs
\t.clk\t\t\t\t\t\t\t(CLOCK_50),
\t.reset\t\t\t\t\t\t\t(reset),
\t.wait_for_incoming_data\t\t\t(wait_for_incoming_data),
\t.start_receiving_data\t\t\t(start_receiving_data),
\t.ps2_clk_posedge\t\t\t\t(ps2_clk_posedge),
\t.ps2_clk_negedge\t\t\t\t(ps2_clk_negedge),
\t.ps2_data\t\t\t\t\t\t(ps2_data_reg),
\t// Bidirectionals
\t// Outputs
\t.received_data\t\t\t\t\t(received_data),
\t.received_data_en\t\t\t\t(received_data_en)
);
Altera_UP_PS2_Command_Out PS2_Command_Out (
\t// Inputs
\t.clk\t\t\t\t\t\t\t(CLOCK_50),
\t.reset\t\t\t\t\t\t\t(reset),
\t.the_command\t\t\t\t\t(the_command_w),
\t.send_command\t\t\t\t\t(send_command_w),
\t.ps2_clk_posedge\t\t\t\t(ps2_clk_posedge),
\t.ps2_clk_negedge\t\t\t\t(ps2_clk_negedge),
\t// Bidirectionals
\t.PS2_CLK\t\t\t\t\t\t(PS2_CLK),
\t.PS2_DAT\t\t\t\t\t\t(PS2_DAT),
\t// Outputs
\t.command_was_sent\t\t\t\t(command_was_sent_w),
\t.error_communication_timed_out\t(error_communication_timed_out_w)
);
endmodule\r
|
`timescale 1ns / 1ps
module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
\t// Inputs
\tCLOCK_50,
\treset,
\tthe_command,
\tsend_command,
\t// Bidirectionals
\tPS2_CLK,\t\t\t\t\t// PS2 Clock
\tPS2_DAT,\t\t\t\t\t// PS2 Data
\t// Outputs
\tcommand_was_sent,
\terror_communication_timed_out,
\treceived_data,
\treceived_data_en\t\t\t// If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input\t\t\tCLOCK_50;
input\t\t\treset;
input\t[7:0]\tthe_command;
input\t\t\tsend_command;
// Bidirectionals
inout\t\t\tPS2_CLK;
inout\t\t \tPS2_DAT;
// Outputs
output\t\t\tcommand_was_sent;
output\t\t\terror_communication_timed_out;
output\t[7:0]\treceived_data;
output\t\t \treceived_data_en;
wire [7:0] the_command_w;
wire send_command_w, command_was_sent_w, error_communication_timed_out_w;
generate
\tif(INITIALIZE_MOUSE) begin
\t\tassign the_command_w = init_done ? the_command : 8'hf4;
\t\tassign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w);
\t\tassign command_was_sent = init_done ? command_was_sent_w : 0;
\t\tassign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1;
\t\t
\t\treg init_done;
\t\t
\t\talways @(posedge CLOCK_50)
\t\t\tif(reset) init_done <= 0;
\t\t\telse if(command_was_sent_w) init_done <= 1;
\t\t
\tend else begin
\t\tassign the_command_w = the_command;
\t\tassign send_command_w = send_command;
\t\tassign command_was_sent = command_was_sent_w;
\t\tassign error_communication_timed_out = error_communication_timed_out_w;
\tend
endgenerate
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam\tPS2_STATE_0_IDLE\t\t\t= 3'h0,
\t\t\tPS2_STATE_1_DATA_IN\t\t\t= 3'h1,
\t\t\tPS2_STATE_2_COMMAND_OUT\t\t= 3'h2,
\t\t\tPS2_STATE_3_END_TRANSFER\t= 3'h3,
\t\t\tPS2_STATE_4_END_DELAYED\t\t= 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire\t\t\tps2_clk_posedge;
wire\t\t\tps2_clk_negedge;
wire\t\t\tstart_receiving_data;
wire\t\t\twait_for_incoming_data;
// Internal Registers
reg\t\t[7:0]\tidle_counter;
reg\t\t\t\tps2_clk_reg;
reg\t\t\t\tps2_data_reg;
reg\t\t\t\tlast_ps2_clk;
// State Machine Registers
reg\t\t[2:0]\tns_ps2_transceiver;
reg\t\t[2:0]\ts_ps2_transceiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
\tif (reset == 1'b1)
\t\ts_ps2_transceiver <= PS2_STATE_0_IDLE;
\telse
\t\ts_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*)
begin
\t// Defaults
\tns_ps2_transceiver = PS2_STATE_0_IDLE;
case (s_ps2_transceiver)
\tPS2_STATE_0_IDLE:
\t\tbegin
\t\t\tif ((idle_counter == 8'hFF) &&
\t\t\t\t\t(send_command == 1'b1))
\t\t\t\tns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
\t\t\telse if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
\t\t\t\tns_ps2_transceiver = PS2_STATE_1_DATA_IN;
\t\t\telse
\t\t\t\tns_ps2_transceiver = PS2_STATE_0_IDLE;
\t\tend
\tPS2_STATE_1_DATA_IN:
\t\tbegin
\t\t\tif ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/)
\t\t\t\tns_ps2_transceiver = PS2_STATE_0_IDLE;
\t\t\telse
\t\t\t\tns_ps2_transceiver = PS2_STATE_1_DATA_IN;
\t\tend
\tPS2_STATE_2_COMMAND_OUT:
\t\tbegin
\t\t\tif ((command_was_sent == 1'b1) ||
\t\t\t\t(error_communication_timed_out == 1'b1))
\t\t\t\tns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
\t\t\telse
\t\t\t\tns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
\t\tend
\tPS2_STATE_3_END_TRANSFER:
\t\tbegin
\t\t\tif (send_command == 1'b0)
\t\t\t\tns_ps2_transceiver = PS2_STATE_0_IDLE;
\t\t\telse if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
\t\t\t\tns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
\t\t\telse
\t\t\t\tns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
\t\tend
\tPS2_STATE_4_END_DELAYED:\t
\t\tbegin
\t\t\tif (received_data_en == 1'b1)
\t\t\tbegin
\t\t\t\tif (send_command == 1'b0)
\t\t\t\t\tns_ps2_transceiver = PS2_STATE_0_IDLE;
\t\t\t\telse
\t\t\t\t\tns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
\t\t\tend
\t\t\telse
\t\t\t\tns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
\t\tend\t
\tdefault:
\t\t\tns_ps2_transceiver = PS2_STATE_0_IDLE;
\tendcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
\tif (reset == 1'b1)
\tbegin
\t\tlast_ps2_clk\t<= 1'b1;
\t\tps2_clk_reg\t\t<= 1'b1;
\t\tps2_data_reg\t<= 1'b1;
\tend
\telse
\tbegin
\t\tlast_ps2_clk\t<= ps2_clk_reg;
\t\tps2_clk_reg\t\t<= PS2_CLK;
\t\tps2_data_reg\t<= PS2_DAT;
\tend
end
always @(posedge CLOCK_50)
begin
\tif (reset == 1'b1)
\t\tidle_counter <= 6'h00;
\telse if ((s_ps2_transceiver == PS2_STATE_0_IDLE) &&
\t\t\t(idle_counter != 8'hFF))
\t\tidle_counter <= idle_counter + 6'h01;
\telse if (s_ps2_transceiver != PS2_STATE_0_IDLE)
\t\tidle_counter <= 6'h00;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign ps2_clk_posedge =
\t\t\t((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge =
\t\t\t((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data\t\t= (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data\t=
\t\t\t(s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_PS2_Data_In PS2_Data_In (
\t// Inputs
\t.clk\t\t\t\t\t\t\t(CLOCK_50),
\t.reset\t\t\t\t\t\t\t(reset),
\t.wait_for_incoming_data\t\t\t(wait_for_incoming_data),
\t.start_receiving_data\t\t\t(start_receiving_data),
\t.ps2_clk_posedge\t\t\t\t(ps2_clk_posedge),
\t.ps2_clk_negedge\t\t\t\t(ps2_clk_negedge),
\t.ps2_data\t\t\t\t\t\t(ps2_data_reg),
\t// Bidirectionals
\t// Outputs
\t.received_data\t\t\t\t\t(received_data),
\t.received_data_en\t\t\t\t(received_data_en)
);
Altera_UP_PS2_Command_Out PS2_Command_Out (
\t// Inputs
\t.clk\t\t\t\t\t\t\t(CLOCK_50),
\t.reset\t\t\t\t\t\t\t(reset),
\t.the_command\t\t\t\t\t(the_command_w),
\t.send_command\t\t\t\t\t(send_command_w),
\t.ps2_clk_posedge\t\t\t\t(ps2_clk_posedge),
\t.ps2_clk_negedge\t\t\t\t(ps2_clk_negedge),
\t// Bidirectionals
\t.PS2_CLK\t\t\t\t\t\t(PS2_CLK),
\t.PS2_DAT\t\t\t\t\t\t(PS2_DAT),
\t// Outputs
\t.command_was_sent\t\t\t\t(command_was_sent_w),
\t.error_communication_timed_out\t(error_communication_timed_out_w)
);
endmodule\r
|
`timescale 1ns / 1ps\r
\r
module Altera_UP_PS2_Data_In (
\t// Inputs
\tclk,
\treset,
\twait_for_incoming_data,
\tstart_receiving_data,
\tps2_clk_posedge,
\tps2_clk_negedge,
\tps2_data,
\t// Bidirectionals
\t// Outputs
\treceived_data,
\treceived_data_en\t\t\t// If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input\t\t\t\tclk;
input\t\t\t\treset;
input\t\t\t\twait_for_incoming_data;
input\t\t\t\tstart_receiving_data;
input\t\t\t\tps2_clk_posedge;
input\t\t\t\tps2_clk_negedge;
input\t\t\t \tps2_data;
// Bidirectionals
// Outputs
output reg\t[7:0]\treceived_data;
output reg\t\t \treceived_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam\tPS2_STATE_0_IDLE\t\t\t= 3'h0,
\t\t\tPS2_STATE_1_WAIT_FOR_DATA\t= 3'h1,
\t\t\tPS2_STATE_2_DATA_IN\t\t\t= 3'h2,
\t\t\tPS2_STATE_3_PARITY_IN\t\t= 3'h3,
\t\t\tPS2_STATE_4_STOP_IN\t\t\t= 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg\t\t\t[3:0]\tdata_count;
reg\t\t\t[7:0]\tdata_shift_reg;
// State Machine Registers
reg\t\t\t[2:0]\tns_ps2_receiver;
reg\t\t\t[2:0]\ts_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\ts_ps2_receiver <= PS2_STATE_0_IDLE;
\telse
\t\ts_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
\t// Defaults
\tns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
\tPS2_STATE_0_IDLE:
\t\tbegin
\t\t\tif ((wait_for_incoming_data == 1'b1) &&
\t\t\t\t\t(received_data_en == 1'b0))
\t\t\t\tns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
\t\t\telse if ((start_receiving_data == 1'b1) &&
\t\t\t\t\t(received_data_en == 1'b0))
\t\t\t\tns_ps2_receiver = PS2_STATE_2_DATA_IN;
\t\t\telse
\t\t\t\tns_ps2_receiver = PS2_STATE_0_IDLE;
\t\tend
\tPS2_STATE_1_WAIT_FOR_DATA:
\t\tbegin
\t\t\tif ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
\t\t\t\tns_ps2_receiver = PS2_STATE_2_DATA_IN;
\t\t\telse if (wait_for_incoming_data == 1'b0)
\t\t\t\tns_ps2_receiver = PS2_STATE_0_IDLE;
\t\t\telse
\t\t\t\tns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
\t\tend
\tPS2_STATE_2_DATA_IN:
\t\tbegin
\t\t\tif ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
\t\t\t\tns_ps2_receiver = PS2_STATE_3_PARITY_IN;
\t\t\telse
\t\t\t\tns_ps2_receiver = PS2_STATE_2_DATA_IN;
\t\tend
\tPS2_STATE_3_PARITY_IN:
\t\tbegin
\t\t\tif (ps2_clk_posedge == 1'b1)
\t\t\t\tns_ps2_receiver = PS2_STATE_4_STOP_IN;
\t\t\telse
\t\t\t\tns_ps2_receiver = PS2_STATE_3_PARITY_IN;
\t\tend
\tPS2_STATE_4_STOP_IN:
\t\tbegin
\t\t\tif (ps2_clk_posedge == 1'b1)
\t\t\t\tns_ps2_receiver = PS2_STATE_0_IDLE;
\t\t\telse
\t\t\t\tns_ps2_receiver = PS2_STATE_4_STOP_IN;
\t\tend
\tdefault:
\t\tbegin
\t\t\tns_ps2_receiver = PS2_STATE_0_IDLE;
\t\tend
\tendcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tdata_count\t<= 3'h0;
\telse if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
\t\t\t(ps2_clk_posedge == 1'b1))
\t\tdata_count\t<= data_count + 3'h1;
\telse if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
\t\tdata_count\t<= 3'h0;
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tdata_shift_reg\t\t\t<= 8'h00;
\telse if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
\t\t\t(ps2_clk_posedge == 1'b1))
\t\tdata_shift_reg\t<= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\treceived_data\t\t<= 8'h00;
\telse if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
\t\treceived_data\t<= data_shift_reg;
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\treceived_data_en\t\t<= 1'b0;
\telse if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
\t\t\t(ps2_clk_posedge == 1'b1))
\t\treceived_data_en\t<= 1'b1;
\telse
\t\treceived_data_en\t<= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule\r
|
`timescale 1ns / 1ps\r
\r
module Altera_UP_PS2_Command_Out (
\t// Inputs
\tclk,
\treset,
\tthe_command,
\tsend_command,
\tps2_clk_posedge,
\tps2_clk_negedge,
\t// Bidirectionals
\tPS2_CLK,
\tPS2_DAT,
\t// Outputs
\tcommand_was_sent,
\terror_communication_timed_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for initiating Host-to-Device communication
// when using a 50MHz system clock
parameter\tCLOCK_CYCLES_FOR_101US\t\t= 5050;
parameter\tNUMBER_OF_BITS_FOR_101US\t= 13;
parameter\tCOUNTER_INCREMENT_FOR_101US\t= 13'h0001;
//parameter\tCLOCK_CYCLES_FOR_101US\t\t= 50;
//parameter\tNUMBER_OF_BITS_FOR_101US\t= 6;
//parameter\tCOUNTER_INCREMENT_FOR_101US\t= 6'h01;
// Timing info for start of transmission error
// when using a 50MHz system clock
parameter\tCLOCK_CYCLES_FOR_15MS\t\t= 750000;
parameter\tNUMBER_OF_BITS_FOR_15MS\t\t= 20;
parameter\tCOUNTER_INCREMENT_FOR_15MS\t= 20'h00001;
// Timing info for sending data error
// when using a 50MHz system clock
parameter\tCLOCK_CYCLES_FOR_2MS\t\t= 100000;
parameter\tNUMBER_OF_BITS_FOR_2MS\t\t= 17;
parameter\tCOUNTER_INCREMENT_FOR_2MS\t= 17'h00001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input\t\t\t\tclk;
input\t\t\t\treset;
input\t\t[7:0]\tthe_command;
input\t\t\t\tsend_command;
input\t\t\t\tps2_clk_posedge;
input\t\t\t\tps2_clk_negedge;
// Bidirectionals
inout\t\t\t\tPS2_CLK;
inout\t\t\t \tPS2_DAT;
// Outputs
output\treg\t\t\tcommand_was_sent;
output\treg\t\t \terror_communication_timed_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter\tPS2_STATE_0_IDLE\t\t\t\t\t= 3'h0,
\t\t\tPS2_STATE_1_INITIATE_COMMUNICATION\t= 3'h1,
\t\t\tPS2_STATE_2_WAIT_FOR_CLOCK\t\t\t= 3'h2,
\t\t\tPS2_STATE_3_TRANSMIT_DATA\t\t\t= 3'h3,
\t\t\tPS2_STATE_4_TRANSMIT_STOP_BIT\t\t= 3'h4,
\t\t\tPS2_STATE_5_RECEIVE_ACK_BIT\t\t\t= 3'h5,
\t\t\tPS2_STATE_6_COMMAND_WAS_SENT\t\t= 3'h6,
\t\t\tPS2_STATE_7_TRANSMISSION_ERROR\t\t= 3'h7;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg\t\t\t[3:0]\tcur_bit;
reg\t\t\t[8:0]\tps2_command;
reg\t\t\t[NUMBER_OF_BITS_FOR_101US:1]\tcommand_initiate_counter;
reg\t\t\t[NUMBER_OF_BITS_FOR_15MS:1]\t\twaiting_counter;
reg\t\t\t[NUMBER_OF_BITS_FOR_2MS:1]\t\ttransfer_counter;
// State Machine Registers
reg\t\t\t[2:0]\tns_ps2_transmitter;
reg\t\t\t[2:0]\ts_ps2_transmitter;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\ts_ps2_transmitter <= PS2_STATE_0_IDLE;
\telse
\t\ts_ps2_transmitter <= ns_ps2_transmitter;
end
always @(*)
begin
\t// Defaults
\tns_ps2_transmitter = PS2_STATE_0_IDLE;
case (s_ps2_transmitter)
\tPS2_STATE_0_IDLE:
\t\tbegin
\t\t\tif (send_command == 1'b1)
\t\t\t\tns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_0_IDLE;
\t\tend
\tPS2_STATE_1_INITIATE_COMMUNICATION:
\t\tbegin
\t\t\tif (command_initiate_counter == CLOCK_CYCLES_FOR_101US)
\t\t\t\tns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
\t\tend
\tPS2_STATE_2_WAIT_FOR_CLOCK:
\t\tbegin
\t\t\tif (ps2_clk_negedge == 1'b1)
\t\t\t\tns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
\t\t\telse if (waiting_counter == CLOCK_CYCLES_FOR_15MS)
\t\t\t\tns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
\t\tend
\tPS2_STATE_3_TRANSMIT_DATA:
\t\tbegin
\t\t\tif ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1))
\t\t\t\tns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
\t\t\telse if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
\t\t\t\tns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
\t\tend
\tPS2_STATE_4_TRANSMIT_STOP_BIT:
\t\tbegin
\t\t\tif (ps2_clk_negedge == 1'b1)
\t\t\t\tns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
\t\t\telse if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
\t\t\t\tns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
\t\tend
\tPS2_STATE_5_RECEIVE_ACK_BIT:
\t\tbegin
\t\t\tif (ps2_clk_posedge == 1'b1)
\t\t\t\tns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
\t\t\telse if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
\t\t\t\tns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
\t\tend
\tPS2_STATE_6_COMMAND_WAS_SENT:
\t\tbegin
\t\t\tif (send_command == 1'b0)
\t\t\t\tns_ps2_transmitter = PS2_STATE_0_IDLE;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
\t\tend
\tPS2_STATE_7_TRANSMISSION_ERROR:
\t\tbegin
\t\t\tif (send_command == 1'b0)
\t\t\t\tns_ps2_transmitter = PS2_STATE_0_IDLE;
\t\t\telse
\t\t\t\tns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
\t\tend
\tdefault:
\t\tbegin
\t\t\tns_ps2_transmitter = PS2_STATE_0_IDLE;
\t\tend
\tendcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tps2_command <= 9'h000;
\telse if (s_ps2_transmitter == PS2_STATE_0_IDLE)
\t\tps2_command <= {(^the_command) ^ 1'b1, the_command};
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tcommand_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
\telse if ((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
\t\t\t(command_initiate_counter != CLOCK_CYCLES_FOR_101US))
\t\tcommand_initiate_counter <=
\t\t\tcommand_initiate_counter + COUNTER_INCREMENT_FOR_101US;
\telse if (s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION)
\t\tcommand_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\twaiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
\telse if ((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) &&
\t\t\t(waiting_counter != CLOCK_CYCLES_FOR_15MS))
\t\twaiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS;
\telse if (s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK)
\t\twaiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\ttransfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
\telse
\tbegin
\t\tif ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ||
\t\t\t(s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) ||
\t\t\t(s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT))
\t\tbegin
\t\t\tif (transfer_counter != CLOCK_CYCLES_FOR_2MS)
\t\t\t\ttransfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS;
\t\tend
\t\telse
\t\t\ttransfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
\tend
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tcur_bit <= 4'h0;
\telse if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) &&
\t\t\t(ps2_clk_negedge == 1'b1))
\t\tcur_bit <= cur_bit + 4'h1;
\telse if (s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA)
\t\tcur_bit <= 4'h0;
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tcommand_was_sent <= 1'b0;
\telse if (s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT)
\t\tcommand_was_sent <= 1'b1;
\telse if (send_command == 1'b0)
\t\t\tcommand_was_sent <= 1'b0;
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\terror_communication_timed_out <= 1'b0;
\telse if (s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR)
\t\terror_communication_timed_out <= 1'b1;
\telse if (send_command == 1'b0)
\t\terror_communication_timed_out <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign PS2_CLK\t=
\t(s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) ?
\t\t1'b0 :
\t\t1'bz;
assign PS2_DAT\t=
\t(s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] :
\t(s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 :
\t((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
\t\t(command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 :
\t\t\t1'bz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule\r
|
`timescale 1ns / 1ps\r
\r
module hvsync_generator(clk, reset,vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY);
input clk;
input reset;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output [9:0] CounterX;
output [9:0] CounterY;
//////////////////////////////////////////////////
reg [9:0] CounterX;
reg [9:0] CounterY;
reg vga_HS, vga_VS;
reg inDisplayArea;
//increment column counter
always @(posedge clk)
begin
if(reset)
CounterX <= 0;
else if(CounterX==10'h320)\t//800
\t CounterX <= 0;
else
\t CounterX <= CounterX + 1'b1;
end
//increment row counter
always @(posedge clk)
begin
if(reset)
CounterY<=0;
else if(CounterY==10'h209) //521
CounterY<=0;
else if(CounterX==10'h320) //800
CounterY <= CounterY + 1'b1;
end
//generate synchronization signal for both vertical and horizontal
always @(posedge clk)
begin
\tvga_HS <= (CounterX > 655 && CounterX < 752); \t\t// change these values to move the display horizontally
\tvga_VS <= (CounterY == 490 || CounterY == 491); \t// change these values to move the display vertically
end
always @(posedge clk)
if(reset)
inDisplayArea<=0;
else
\t inDisplayArea <= (CounterX<640) && (CounterY<480);
\t
assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;
endmodule\r
|
// ROM with synchonous read (inferring Block RAM)
// character ROM
// - 8-by-16 (8-by-2^4) font
// - 128 (2^7) characters
// - ROM size: 512-by-8 (2^11-by-8) bits
// 16K bits: 1 BRAM
module font_rom
(
input wire clk,
input wire [10:0] addr,
output reg [7:0] data
);
// signal declaration
reg [10:0] addr_reg;
// body
always @(posedge clk)
addr_reg <= addr;
always @*
case (addr_reg)
//code x00
11'h000: data = 8'b00000000; //
11'h001: data = 8'b00000000; //
11'h002: data = 8'b00000000; //
11'h003: data = 8'b00000000; //
11'h004: data = 8'b00000000; //
11'h005: data = 8'b00000000; //
11'h006: data = 8'b00000000; //
11'h007: data = 8'b00000000; //
11'h008: data = 8'b00000000; //
11'h009: data = 8'b00000000; //
11'h00a: data = 8'b00000000; //
11'h00b: data = 8'b00000000; //
11'h00c: data = 8'b00000000; //
11'h00d: data = 8'b00000000; //
11'h00e: data = 8'b00000000; //
11'h00f: data = 8'b00000000; //
//code x01
11'h010: data = 8'b00000000; //
11'h011: data = 8'b00000000; //
11'h012: data = 8'b01111110; // ******
11'h013: data = 8'b10000001; // * *
11'h014: data = 8'b10100101; // * * * *
11'h015: data = 8'b10000001; // * *
11'h016: data = 8'b10000001; // * *
11'h017: data = 8'b10111101; // * **** *
11'h018: data = 8'b10011001; // * ** *
11'h019: data = 8'b10000001; // * *
11'h01a: data = 8'b10000001; // * *
11'h01b: data = 8'b01111110; // ******
11'h01c: data = 8'b00000000; //
11'h01d: data = 8'b00000000; //
11'h01e: data = 8'b00000000; //
11'h01f: data = 8'b00000000; //
//code x02
11'h020: data = 8'b00000000; //
11'h021: data = 8'b00000000; //
11'h022: data = 8'b01111110; // ******
11'h023: data = 8'b11111111; // ********
11'h024: data = 8'b11011011; // ** ** **
11'h025: data = 8'b11111111; // ********
11'h026: data = 8'b11111111; // ********
11'h027: data = 8'b11000011; // ** **
11'h028: data = 8'b11100111; // *** ***
11'h029: data = 8'b11111111; // ********
11'h02a: data = 8'b11111111; // ********
11'h02b: data = 8'b01111110; // ******
11'h02c: data = 8'b00000000; //
11'h02d: data = 8'b00000000; //
11'h02e: data = 8'b00000000; //
11'h02f: data = 8'b00000000; //
//code x03
11'h030: data = 8'b00000000; //
11'h031: data = 8'b00000000; //
11'h032: data = 8'b00000000; //
11'h033: data = 8'b00000000; //
11'h034: data = 8'b01101100; // ** **
11'h035: data = 8'b11111110; // *******
11'h036: data = 8'b11111110; // *******
11'h037: data = 8'b11111110; // *******
11'h038: data = 8'b11111110; // *******
11'h039: data = 8'b01111100; // *****
11'h03a: data = 8'b00111000; // ***
11'h03b: data = 8'b00010000; // *
11'h03c: data = 8'b00000000; //
11'h03d: data = 8'b00000000; //
11'h03e: data = 8'b00000000; //
11'h03f: data = 8'b00000000; //
//code x04
11'h040: data = 8'b00000000; //
11'h041: data = 8'b00000000; //
11'h042: data = 8'b00000000; //
11'h043: data = 8'b00000000; //
11'h044: data = 8'b00010000; // *
11'h045: data = 8'b00111000; // ***
11'h046: data = 8'b01111100; // *****
11'h047: data = 8'b11111110; // *******
11'h048: data = 8'b01111100; // *****
11'h049: data = 8'b00111000; // ***
11'h04a: data = 8'b00010000; // *
11'h04b: data = 8'b00000000; //
11'h04c: data = 8'b00000000; //
11'h04d: data = 8'b00000000; //
11'h04e: data = 8'b00000000; //
11'h04f: data = 8'b00000000; //
//code x05
11'h050: data = 8'b00000000; //
11'h051: data = 8'b00000000; //
11'h052: data = 8'b00000000; //
11'h053: data = 8'b00011000; // **
11'h054: data = 8'b00111100; // ****
11'h055: data = 8'b00111100; // ****
11'h056: data = 8'b11100111; // *** ***
11'h057: data = 8'b11100111; // *** ***
11'h058: data = 8'b11100111; // *** ***
11'h059: data = 8'b00011000; // **
11'h05a: data = 8'b00011000; // **
11'h05b: data = 8'b00111100; // ****
11'h05c: data = 8'b00000000; //
11'h05d: data = 8'b00000000; //
11'h05e: data = 8'b00000000; //
11'h05f: data = 8'b00000000; //
//code x06
11'h060: data = 8'b00000000; //
11'h061: data = 8'b00000000; //
11'h062: data = 8'b00000000; //
11'h063: data = 8'b00011000; // **
11'h064: data = 8'b00111100; // ****
11'h065: data = 8'b01111110; // ******
11'h066: data = 8'b11111111; // ********
11'h067: data = 8'b11111111; // ********
11'h068: data = 8'b01111110; // ******
11'h069: data = 8'b00011000; // **
11'h06a: data = 8'b00011000; // **
11'h06b: data = 8'b00111100; // ****
11'h06c: data = 8'b00000000; //
11'h06d: data = 8'b00000000; //
11'h06e: data = 8'b00000000; //
11'h06f: data = 8'b00000000; //
//code x07
11'h070: data = 8'b00000000; //
11'h071: data = 8'b00000000; //
11'h072: data = 8'b00000000; //
11'h073: data = 8'b00000000; //
11'h074: data = 8'b00000000; //
11'h075: data = 8'b00000000; //
11'h076: data = 8'b00011000; // **
11'h077: data = 8'b00111100; // ****
11'h078: data = 8'b00111100; // ****
11'h079: data = 8'b00011000; // **
11'h07a: data = 8'b00000000; //
11'h07b: data = 8'b00000000; //
11'h07c: data = 8'b00000000; //
11'h07d: data = 8'b00000000; //
11'h07e: data = 8'b00000000; //
11'h07f: data = 8'b00000000; //
//code x08
11'h080: data = 8'b11111111; // ********
11'h081: data = 8'b11111111; // ********
11'h082: data = 8'b11111111; // ********
11'h083: data = 8'b11111111; // ********
11'h084: data = 8'b11111111; // ********
11'h085: data = 8'b11111111; // ********
11'h086: data = 8'b11100111; // *** ***
11'h087: data = 8'b11000011; // ** **
11'h088: data = 8'b11000011; // ** **
11'h089: data = 8'b11100111; // *** ***
11'h08a: data = 8'b11111111; // ********
11'h08b: data = 8'b11111111; // ********
11'h08c: data = 8'b11111111; // ********
11'h08d: data = 8'b11111111; // ********
11'h08e: data = 8'b11111111; // ********
11'h08f: data = 8'b11111111; // ********
//code x09
11'h090: data = 8'b00000000; //
11'h091: data = 8'b00000000; //
11'h092: data = 8'b00000000; //
11'h093: data = 8'b00000000; //
11'h094: data = 8'b00000000; //
11'h095: data = 8'b00111100; // ****
11'h096: data = 8'b01100110; // ** **
11'h097: data = 8'b01000010; // * *
11'h098: data = 8'b01000010; // * *
11'h099: data = 8'b01100110; // ** **
11'h09a: data = 8'b00111100; // ****
11'h09b: data = 8'b00000000; //
11'h09c: data = 8'b00000000; //
11'h09d: data = 8'b00000000; //
11'h09e: data = 8'b00000000; //
11'h09f: data = 8'b00000000; //
//code x0a
11'h0a0: data = 8'b11111111; // ********
11'h0a1: data = 8'b11111111; // ********
11'h0a2: data = 8'b11111111; // ********
11'h0a3: data = 8'b11111111; // ********
11'h0a4: data = 8'b11111111; // ********
11'h0a5: data = 8'b11000011; // ** **
11'h0a6: data = 8'b10011001; // * ** *
11'h0a7: data = 8'b10111101; // * **** *
11'h0a8: data = 8'b10111101; // * **** *
11'h0a9: data = 8'b10011001; // * ** *
11'h0aa: data = 8'b11000011; // ** **
11'h0ab: data = 8'b11111111; // ********
11'h0ac: data = 8'b11111111; // ********
11'h0ad: data = 8'b11111111; // ********
11'h0ae: data = 8'b11111111; // ********
11'h0af: data = 8'b11111111; // ********
//code x0b
11'h0b0: data = 8'b00000000; //
11'h0b1: data = 8'b00000000; //
11'h0b2: data = 8'b00011110; // ****
11'h0b3: data = 8'b00001110; // ***
11'h0b4: data = 8'b00011010; // ** *
11'h0b5: data = 8'b00110010; // ** *
11'h0b6: data = 8'b01111000; // ****
11'h0b7: data = 8'b11001100; // ** **
11'h0b8: data = 8'b11001100; // ** **
11'h0b9: data = 8'b11001100; // ** **
11'h0ba: data = 8'b11001100; // ** **
11'h0bb: data = 8'b01111000; // ****
11'h0bc: data = 8'b00000000; //
11'h0bd: data = 8'b00000000; //
11'h0be: data = 8'b00000000; //
11'h0bf: data = 8'b00000000; //
//code x0c
11'h0c0: data = 8'b00000000; //
11'h0c1: data = 8'b00000000; //
11'h0c2: data = 8'b00111100; // ****
11'h0c3: data = 8'b01100110; // ** **
11'h0c4: data = 8'b01100110; // ** **
11'h0c5: data = 8'b01100110; // ** **
11'h0c6: data = 8'b01100110; // ** **
11'h0c7: data = 8'b00111100; // ****
11'h0c8: data = 8'b00011000; // **
11'h0c9: data = 8'b01111110; // ******
11'h0ca: data = 8'b00011000; // **
11'h0cb: data = 8'b00011000; // **
11'h0cc: data = 8'b00000000; //
11'h0cd: data = 8'b00000000; //
11'h0ce: data = 8'b00000000; //
11'h0cf: data = 8'b00000000; //
//code x0d
11'h0d0: data = 8'b00000000; //
11'h0d1: data = 8'b00000000; //
11'h0d2: data = 8'b00111111; // ******
11'h0d3: data = 8'b00110011; // ** **
11'h0d4: data = 8'b00111111; // ******
11'h0d5: data = 8'b00110000; // **
11'h0d6: data = 8'b00110000; // **
11'h0d7: data = 8'b00110000; // **
11'h0d8: data = 8'b00110000; // **
11'h0d9: data = 8'b01110000; // ***
11'h0da: data = 8'b11110000; // ****
11'h0db: data = 8'b11100000; // ***
11'h0dc: data = 8'b00000000; //
11'h0dd: data = 8'b00000000; //
11'h0de: data = 8'b00000000; //
11'h0df: data = 8'b00000000; //
//code x0e
11'h0e0: data = 8'b00000000; //
11'h0e1: data = 8'b00000000; //
11'h0e2: data = 8'b01111111; // *******
11'h0e3: data = 8'b01100011; // ** **
11'h0e4: data = 8'b01111111; // *******
11'h0e5: data = 8'b01100011; // ** **
11'h0e6: data = 8'b01100011; // ** **
11'h0e7: data = 8'b01100011; // ** **
11'h0e8: data = 8'b01100011; // ** **
11'h0e9: data = 8'b01100111; // ** ***
11'h0ea: data = 8'b11100111; // *** ***
11'h0eb: data = 8'b11100110; // *** **
11'h0ec: data = 8'b11000000; // **
11'h0ed: data = 8'b00000000; //
11'h0ee: data = 8'b00000000; //
11'h0ef: data = 8'b00000000; //
//code x0f
11'h0f0: data = 8'b00000000; //
11'h0f1: data = 8'b00000000; //
11'h0f2: data = 8'b00000000; //
11'h0f3: data = 8'b00011000; // **
11'h0f4: data = 8'b00011000; // **
11'h0f5: data = 8'b11011011; // ** ** **
11'h0f6: data = 8'b00111100; // ****
11'h0f7: data = 8'b11100111; // *** ***
11'h0f8: data = 8'b00111100; // ****
11'h0f9: data = 8'b11011011; // ** ** **
11'h0fa: data = 8'b00011000; // **
11'h0fb: data = 8'b00011000; // **
11'h0fc: data = 8'b00000000; //
11'h0fd: data = 8'b00000000; //
11'h0fe: data = 8'b00000000; //
11'h0ff: data = 8'b00000000; //
//code x10
11'h100: data = 8'b00000000; //
11'h101: data = 8'b10000000; // *
11'h102: data = 8'b11000000; // **
11'h103: data = 8'b11100000; // ***
11'h104: data = 8'b11110000; // ****
11'h105: data = 8'b11111000; // *****
11'h106: data = 8'b11111110; // *******
11'h107: data = 8'b11111000; // *****
11'h108: data = 8'b11110000; // ****
11'h109: data = 8'b11100000; // ***
11'h10a: data = 8'b11000000; // **
11'h10b: data = 8'b10000000; // *
11'h10c: data = 8'b00000000; //
11'h10d: data = 8'b00000000; //
11'h10e: data = 8'b00000000; //
11'h10f: data = 8'b00000000; //
//code x11
11'h110: data = 8'b00000000; //
11'h111: data = 8'b00000010; // *
11'h112: data = 8'b00000110; // **
11'h113: data = 8'b00001110; // ***
11'h114: data = 8'b00011110; // ****
11'h115: data = 8'b00111110; // *****
11'h116: data = 8'b11111110; // *******
11'h117: data = 8'b00111110; // *****
11'h118: data = 8'b00011110; // ****
11'h119: data = 8'b00001110; // ***
11'h11a: data = 8'b00000110; // **
11'h11b: data = 8'b00000010; // *
11'h11c: data = 8'b00000000; //
11'h11d: data = 8'b00000000; //
11'h11e: data = 8'b00000000; //
11'h11f: data = 8'b00000000; //
//code x12
11'h120: data = 8'b00000000; //
11'h121: data = 8'b00000000; //
11'h122: data = 8'b00011000; // **
11'h123: data = 8'b00111100; // ****
11'h124: data = 8'b01111110; // ******
11'h125: data = 8'b00011000; // **
11'h126: data = 8'b00011000; // **
11'h127: data = 8'b00011000; // **
11'h128: data = 8'b01111110; // ******
11'h129: data = 8'b00111100; // ****
11'h12a: data = 8'b00011000; // **
11'h12b: data = 8'b00000000; //
11'h12c: data = 8'b00000000; //
11'h12d: data = 8'b00000000; //
11'h12e: data = 8'b00000000; //
11'h12f: data = 8'b00000000; //
//code x13
11'h130: data = 8'b00000000; //
11'h131: data = 8'b00000000; //
11'h132: data = 8'b01100110; // ** **
11'h133: data = 8'b01100110; // ** **
11'h134: data = 8'b01100110; // ** **
11'h135: data = 8'b01100110; // ** **
11'h136: data = 8'b01100110; // ** **
11'h137: data = 8'b01100110; // ** **
11'h138: data = 8'b01100110; // ** **
11'h139: data = 8'b00000000; //
11'h13a: data = 8'b01100110; // ** **
11'h13b: data = 8'b01100110; // ** **
11'h13c: data = 8'b00000000; //
11'h13d: data = 8'b00000000; //
11'h13e: data = 8'b00000000; //
11'h13f: data = 8'b00000000; //
//code x14
11'h140: data = 8'b00000000; //
11'h141: data = 8'b00000000; //
11'h142: data = 8'b01111111; // *******
11'h143: data = 8'b11011011; // ** ** **
11'h144: data = 8'b11011011; // ** ** **
11'h145: data = 8'b11011011; // ** ** **
11'h146: data = 8'b01111011; // **** **
11'h147: data = 8'b00011011; // ** **
11'h148: data = 8'b00011011; // ** **
11'h149: data = 8'b00011011; // ** **
11'h14a: data = 8'b00011011; // ** **
11'h14b: data = 8'b00011011; // ** **
11'h14c: data = 8'b00000000; //
11'h14d: data = 8'b00000000; //
11'h14e: data = 8'b00000000; //
11'h14f: data = 8'b00000000; //
//code x15
11'h150: data = 8'b00000000; //
11'h151: data = 8'b01111100; // *****
11'h152: data = 8'b11000110; // ** **
11'h153: data = 8'b01100000; // **
11'h154: data = 8'b00111000; // ***
11'h155: data = 8'b01101100; // ** **
11'h156: data = 8'b11000110; // ** **
11'h157: data = 8'b11000110; // ** **
11'h158: data = 8'b01101100; // ** **
11'h159: data = 8'b00111000; // ***
11'h15a: data = 8'b00001100; // **
11'h15b: data = 8'b11000110; // ** **
11'h15c: data = 8'b01111100; // *****
11'h15d: data = 8'b00000000; //
11'h15e: data = 8'b00000000; //
11'h15f: data = 8'b00000000; //
//code x16
11'h160: data = 8'b00000000; //
11'h161: data = 8'b00000000; //
11'h162: data = 8'b00000000; //
11'h163: data = 8'b00000000; //
11'h164: data = 8'b00000000; //
11'h165: data = 8'b00000000; //
11'h166: data = 8'b00000000; //
11'h167: data = 8'b00000000; //
11'h168: data = 8'b11111110; // *******
11'h169: data = 8'b11111110; // *******
11'h16a: data = 8'b11111110; // *******
11'h16b: data = 8'b11111110; // *******
11'h16c: data = 8'b00000000; //
11'h16d: data = 8'b00000000; //
11'h16e: data = 8'b00000000; //
11'h16f: data = 8'b00000000; //
//code x17
11'h170: data = 8'b00000000; //
11'h171: data = 8'b00000000; //
11'h172: data = 8'b00011000; // **
11'h173: data = 8'b00111100; // ****
11'h174: data = 8'b01111110; // ******
11'h175: data = 8'b00011000; // **
11'h176: data = 8'b00011000; // **
11'h177: data = 8'b00011000; // **
11'h178: data = 8'b01111110; // ******
11'h179: data = 8'b00111100; // ****
11'h17a: data = 8'b00011000; // **
11'h17b: data = 8'b01111110; // ******
11'h17c: data = 8'b00110000; //
11'h17d: data = 8'b00000000; //
11'h17e: data = 8'b00000000; //
11'h17f: data = 8'b00000000; //
//code x18
11'h180: data = 8'b00000000; //
11'h181: data = 8'b00000000; //
11'h182: data = 8'b00011000; // **
11'h183: data = 8'b00111100; // ****
11'h184: data = 8'b01111110; // ******
11'h185: data = 8'b00011000; // **
11'h186: data = 8'b00011000; // **
11'h187: data = 8'b00011000; // **
11'h188: data = 8'b00011000; // **
11'h189: data = 8'b00011000; // **
11'h18a: data = 8'b00011000; // **
11'h18b: data = 8'b00011000; // **
11'h18c: data = 8'b00000000; //
11'h18d: data = 8'b00000000; //
11'h18e: data = 8'b00000000; //
11'h18f: data = 8'b00000000; //
//code x19
11'h190: data = 8'b00000000; //
11'h191: data = 8'b00000000; //
11'h192: data = 8'b00011000; // **
11'h193: data = 8'b00011000; // **
11'h194: data = 8'b00011000; // **
11'h195: data = 8'b00011000; // **
11'h196: data = 8'b00011000; // **
11'h197: data = 8'b00011000; // **
11'h198: data = 8'b00011000; // **
11'h199: data = 8'b01111110; // ******
11'h19a: data = 8'b00111100; // ****
11'h19b: data = 8'b00011000; // **
11'h19c: data = 8'b00000000; //
11'h19d: data = 8'b00000000; //
11'h19e: data = 8'b00000000; //
11'h19f: data = 8'b00000000; //
//code x1a
11'h1a0: data = 8'b00000000; //
11'h1a1: data = 8'b00000000; //
11'h1a2: data = 8'b00000000; //
11'h1a3: data = 8'b00000000; //
11'h1a4: data = 8'b00000000; //
11'h1a5: data = 8'b00011000; // **
11'h1a6: data = 8'b00001100; // **
11'h1a7: data = 8'b11111110; // *******
11'h1a8: data = 8'b00001100; // **
11'h1a9: data = 8'b00011000; // **
11'h1aa: data = 8'b00000000; //
11'h1ab: data = 8'b00000000; //
11'h1ac: data = 8'b00000000; //
11'h1ad: data = 8'b00000000; //
11'h1ae: data = 8'b00000000; //
11'h1af: data = 8'b00000000; //
//code x1b
11'h1b0: data = 8'b00000000; //
11'h1b1: data = 8'b00000000; //
11'h1b2: data = 8'b00000000; //
11'h1b3: data = 8'b00000000; //
11'h1b4: data = 8'b00000000; //
11'h1b5: data = 8'b00110000; // **
11'h1b6: data = 8'b01100000; // **
11'h1b7: data = 8'b11111110; // *******
11'h1b8: data = 8'b01100000; // **
11'h1b9: data = 8'b00110000; // **
11'h1ba: data = 8'b00000000; //
11'h1bb: data = 8'b00000000; //
11'h1bc: data = 8'b00000000; //
11'h1bd: data = 8'b00000000; //
11'h1be: data = 8'b00000000; //
11'h1bf: data = 8'b00000000; //
//code x1c
11'h1c0: data = 8'b00000000; //
11'h1c1: data = 8'b00000000; //
11'h1c2: data = 8'b00000000; //
11'h1c3: data = 8'b00000000; //
11'h1c4: data = 8'b00000000; //
11'h1c5: data = 8'b00000000; //
11'h1c6: data = 8'b11000000; // **
11'h1c7: data = 8'b11000000; // **
11'h1c8: data = 8'b11000000; // **
11'h1c9: data = 8'b11111110; // *******
11'h1ca: data = 8'b00000000; //
11'h1cb: data = 8'b00000000; //
11'h1cc: data = 8'b00000000; //
11'h1cd: data = 8'b00000000; //
11'h1ce: data = 8'b00000000; //
11'h1cf: data = 8'b00000000; //
//code x1d
11'h1d0: data = 8'b00000000; //
11'h1d1: data = 8'b00000000; //
11'h1d2: data = 8'b00000000; //
11'h1d3: data = 8'b00000000; //
11'h1d4: data = 8'b00000000; //
11'h1d5: data = 8'b00100100; // * *
11'h1d6: data = 8'b01100110; // ** **
11'h1d7: data = 8'b11111111; // ********
11'h1d8: data = 8'b01100110; // ** **
11'h1d9: data = 8'b00100100; // * *
11'h1da: data = 8'b00000000; //
11'h1db: data = 8'b00000000; //
11'h1dc: data = 8'b00000000; //
11'h1dd: data = 8'b00000000; //
11'h1de: data = 8'b00000000; //
11'h1df: data = 8'b00000000; //
//code x1e
11'h1e0: data = 8'b00000000; //
11'h1e1: data = 8'b00000000; //
11'h1e2: data = 8'b00000000; //
11'h1e3: data = 8'b00000000; //
11'h1e4: data = 8'b00010000; // *
11'h1e5: data = 8'b00111000; // ***
11'h1e6: data = 8'b00111000; // ***
11'h1e7: data = 8'b01111100; // *****
11'h1e8: data = 8'b01111100; // *****
11'h1e9: data = 8'b11111110; // *******
11'h1ea: data = 8'b11111110; // *******
11'h1eb: data = 8'b00000000; //
11'h1ec: data = 8'b00000000; //
11'h1ed: data = 8'b00000000; //
11'h1ee: data = 8'b00000000; //
11'h1ef: data = 8'b00000000; //
//code x1f
11'h1f0: data = 8'b00000000; //
11'h1f1: data = 8'b00000000; //
11'h1f2: data = 8'b00000000; //
11'h1f3: data = 8'b00000000; //
11'h1f4: data = 8'b11111110; // *******
11'h1f5: data = 8'b11111110; // *******
11'h1f6: data = 8'b01111100; // *****
11'h1f7: data = 8'b01111100; // *****
11'h1f8: data = 8'b00111000; // ***
11'h1f9: data = 8'b00111000; // ***
11'h1fa: data = 8'b00010000; // *
11'h1fb: data = 8'b00000000; //
11'h1fc: data = 8'b00000000; //
11'h1fd: data = 8'b00000000; //
11'h1fe: data = 8'b00000000; //
11'h1ff: data = 8'b00000000; //
//code x20
11'h200: data = 8'b00000000; //
11'h201: data = 8'b00000000; //
11'h202: data = 8'b00000000; //
11'h203: data = 8'b00000000; //
11'h204: data = 8'b00000000; //
11'h205: data = 8'b00000000; //
11'h206: data = 8'b00000000; //
11'h207: data = 8'b00000000; //
11'h208: data = 8'b00000000; //
11'h209: data = 8'b00000000; //
11'h20a: data = 8'b00000000; //
11'h20b: data = 8'b00000000; //
11'h20c: data = 8'b00000000; //
11'h20d: data = 8'b00000000; //
11'h20e: data = 8'b00000000; //
11'h20f: data = 8'b00000000; //
//code x21
11'h210: data = 8'b00000000; //
11'h211: data = 8'b00000000; //
11'h212: data = 8'b00011000; // **
11'h213: data = 8'b00111100; // ****
11'h214: data = 8'b00111100; // ****
11'h215: data = 8'b00111100; // ****
11'h216: data = 8'b00011000; // **
11'h217: data = 8'b00011000; // **
11'h218: data = 8'b00011000; // **
11'h219: data = 8'b00000000; //
11'h21a: data = 8'b00011000; // **
11'h21b: data = 8'b00011000; // **
11'h21c: data = 8'b00000000; //
11'h21d: data = 8'b00000000; //
11'h21e: data = 8'b00000000; //
11'h21f: data = 8'b00000000; //
//code x22
11'h220: data = 8'b00000000; //
11'h221: data = 8'b01100110; // ** **
11'h222: data = 8'b01100110; // ** **
11'h223: data = 8'b01100110; // ** **
11'h224: data = 8'b00100100; // * *
11'h225: data = 8'b00000000; //
11'h226: data = 8'b00000000; //
11'h227: data = 8'b00000000; //
11'h228: data = 8'b00000000; //
11'h229: data = 8'b00000000; //
11'h22a: data = 8'b00000000; //
11'h22b: data = 8'b00000000; //
11'h22c: data = 8'b00000000; //
11'h22d: data = 8'b00000000; //
11'h22e: data = 8'b00000000; //
11'h22f: data = 8'b00000000; //
//code x23
11'h230: data = 8'b00000000; //
11'h231: data = 8'b00000000; //
11'h232: data = 8'b00000000; //
11'h233: data = 8'b01101100; // ** **
11'h234: data = 8'b01101100; // ** **
11'h235: data = 8'b11111110; // *******
11'h236: data = 8'b01101100; // ** **
11'h237: data = 8'b01101100; // ** **
11'h238: data = 8'b01101100; // ** **
11'h239: data = 8'b11111110; // *******
11'h23a: data = 8'b01101100; // ** **
11'h23b: data = 8'b01101100; // ** **
11'h23c: data = 8'b00000000; //
11'h23d: data = 8'b00000000; //
11'h23e: data = 8'b00000000; //
11'h23f: data = 8'b00000000; //
//code x24
11'h240: data = 8'b00011000; // **
11'h241: data = 8'b00011000; // **
11'h242: data = 8'b01111100; // *****
11'h243: data = 8'b11000110; // ** **
11'h244: data = 8'b11000010; // ** *
11'h245: data = 8'b11000000; // **
11'h246: data = 8'b01111100; // *****
11'h247: data = 8'b00000110; // **
11'h248: data = 8'b00000110; // **
11'h249: data = 8'b10000110; // * **
11'h24a: data = 8'b11000110; // ** **
11'h24b: data = 8'b01111100; // *****
11'h24c: data = 8'b00011000; // **
11'h24d: data = 8'b00011000; // **
11'h24e: data = 8'b00000000; //
11'h24f: data = 8'b00000000; //
//code x25
11'h250: data = 8'b00000000; //
11'h251: data = 8'b00000000; //
11'h252: data = 8'b00000000; //
11'h253: data = 8'b00000000; //
11'h254: data = 8'b11000010; // ** *
11'h255: data = 8'b11000110; // ** **
11'h256: data = 8'b00001100; // **
11'h257: data = 8'b00011000; // **
11'h258: data = 8'b00110000; // **
11'h259: data = 8'b01100000; // **
11'h25a: data = 8'b11000110; // ** **
11'h25b: data = 8'b10000110; // * **
11'h25c: data = 8'b00000000; //
11'h25d: data = 8'b00000000; //
11'h25e: data = 8'b00000000; //
11'h25f: data = 8'b00000000; //
//code x26
11'h260: data = 8'b00000000; //
11'h261: data = 8'b00000000; //
11'h262: data = 8'b00111000; // ***
11'h263: data = 8'b01101100; // ** **
11'h264: data = 8'b01101100; // ** **
11'h265: data = 8'b00111000; // ***
11'h266: data = 8'b01110110; // *** **
11'h267: data = 8'b11011100; // ** ***
11'h268: data = 8'b11001100; // ** **
11'h269: data = 8'b11001100; // ** **
11'h26a: data = 8'b11001100; // ** **
11'h26b: data = 8'b01110110; // *** **
11'h26c: data = 8'b00000000; //
11'h26d: data = 8'b00000000; //
11'h26e: data = 8'b00000000; //
11'h26f: data = 8'b00000000; //
//code x27
11'h270: data = 8'b00000000; //
11'h271: data = 8'b00110000; // **
11'h272: data = 8'b00110000; // **
11'h273: data = 8'b00110000; // **
11'h274: data = 8'b01100000; // **
11'h275: data = 8'b00000000; //
11'h276: data = 8'b00000000; //
11'h277: data = 8'b00000000; //
11'h278: data = 8'b00000000; //
11'h279: data = 8'b00000000; //
11'h27a: data = 8'b00000000; //
11'h27b: data = 8'b00000000; //
11'h27c: data = 8'b00000000; //
11'h27d: data = 8'b00000000; //
11'h27e: data = 8'b00000000; //
11'h27f: data = 8'b00000000; //
//code x28
11'h280: data = 8'b00000000; //
11'h281: data = 8'b00000000; //
11'h282: data = 8'b00001100; // **
11'h283: data = 8'b00011000; // **
11'h284: data = 8'b00110000; // **
11'h285: data = 8'b00110000; // **
11'h286: data = 8'b00110000; // **
11'h287: data = 8'b00110000; // **
11'h288: data = 8'b00110000; // **
11'h289: data = 8'b00110000; // **
11'h28a: data = 8'b00011000; // **
11'h28b: data = 8'b00001100; // **
11'h28c: data = 8'b00000000; //
11'h28d: data = 8'b00000000; //
11'h28e: data = 8'b00000000; //
11'h28f: data = 8'b00000000; //
//code x29
11'h290: data = 8'b00000000; //
11'h291: data = 8'b00000000; //
11'h292: data = 8'b00110000; // **
11'h293: data = 8'b00011000; // **
11'h294: data = 8'b00001100; // **
11'h295: data = 8'b00001100; // **
11'h296: data = 8'b00001100; // **
11'h297: data = 8'b00001100; // **
11'h298: data = 8'b00001100; // **
11'h299: data = 8'b00001100; // **
11'h29a: data = 8'b00011000; // **
11'h29b: data = 8'b00110000; // **
11'h29c: data = 8'b00000000; //
11'h29d: data = 8'b00000000; //
11'h29e: data = 8'b00000000; //
11'h29f: data = 8'b00000000; //
//code x2a
11'h2a0: data = 8'b00000000; //
11'h2a1: data = 8'b00000000; //
11'h2a2: data = 8'b00000000; //
11'h2a3: data = 8'b00000000; //
11'h2a4: data = 8'b00000000; //
11'h2a5: data = 8'b01100110; // ** **
11'h2a6: data = 8'b00111100; // ****
11'h2a7: data = 8'b11111111; // ********
11'h2a8: data = 8'b00111100; // ****
11'h2a9: data = 8'b01100110; // ** **
11'h2aa: data = 8'b00000000; //
11'h2ab: data = 8'b00000000; //
11'h2ac: data = 8'b00000000; //
11'h2ad: data = 8'b00000000; //
11'h2ae: data = 8'b00000000; //
11'h2af: data = 8'b00000000; //
//code x2b
11'h2b0: data = 8'b00000000; //
11'h2b1: data = 8'b00000000; //
11'h2b2: data = 8'b00000000; //
11'h2b3: data = 8'b00000000; //
11'h2b4: data = 8'b00000000; //
11'h2b5: data = 8'b00011000; // **
11'h2b6: data = 8'b00011000; // **
11'h2b7: data = 8'b01111110; // ******
11'h2b8: data = 8'b00011000; // **
11'h2b9: data = 8'b00011000; // **
11'h2ba: data = 8'b00000000; //
11'h2bb: data = 8'b00000000; //
11'h2bc: data = 8'b00000000; //
11'h2bd: data = 8'b00000000; //
11'h2be: data = 8'b00000000; //
11'h2bf: data = 8'b00000000; //
//code x2c
11'h2c0: data = 8'b00000000; //
11'h2c1: data = 8'b00000000; //
11'h2c2: data = 8'b00000000; //
11'h2c3: data = 8'b00000000; //
11'h2c4: data = 8'b00000000; //
11'h2c5: data = 8'b00000000; //
11'h2c6: data = 8'b00000000; //
11'h2c7: data = 8'b00000000; //
11'h2c8: data = 8'b00000000; //
11'h2c9: data = 8'b00011000; // **
11'h2ca: data = 8'b00011000; // **
11'h2cb: data = 8'b00011000; // **
11'h2cc: data = 8'b00110000; // **
11'h2cd: data = 8'b00000000; //
11'h2ce: data = 8'b00000000; //
11'h2cf: data = 8'b00000000; //
//code x2d
11'h2d0: data = 8'b00000000; //
11'h2d1: data = 8'b00000000; //
11'h2d2: data = 8'b00000000; //
11'h2d3: data = 8'b00000000; //
11'h2d4: data = 8'b00000000; //
11'h2d5: data = 8'b00000000; //
11'h2d6: data = 8'b00000000; //
11'h2d7: data = 8'b01111110; // ******
11'h2d8: data = 8'b00000000; //
11'h2d9: data = 8'b00000000; //
11'h2da: data = 8'b00000000; //
11'h2db: data = 8'b00000000; //
11'h2dc: data = 8'b00000000; //
11'h2dd: data = 8'b00000000; //
11'h2de: data = 8'b00000000; //
11'h2df: data = 8'b00000000; //
//code x2e
11'h2e0: data = 8'b00000000; //
11'h2e1: data = 8'b00000000; //
11'h2e2: data = 8'b00000000; //
11'h2e3: data = 8'b00000000; //
11'h2e4: data = 8'b00000000; //
11'h2e5: data = 8'b00000000; //
11'h2e6: data = 8'b00000000; //
11'h2e7: data = 8'b00000000; //
11'h2e8: data = 8'b00000000; //
11'h2e9: data = 8'b00000000; //
11'h2ea: data = 8'b00011000; // **
11'h2eb: data = 8'b00011000; // **
11'h2ec: data = 8'b00000000; //
11'h2ed: data = 8'b00000000; //
11'h2ee: data = 8'b00000000; //
11'h2ef: data = 8'b00000000; //
//code x2f
11'h2f0: data = 8'b00000000; //
11'h2f1: data = 8'b00000000; //
11'h2f2: data = 8'b00000000; //
11'h2f3: data = 8'b00000000; //
11'h2f4: data = 8'b00000010; // *
11'h2f5: data = 8'b00000110; // **
11'h2f6: data = 8'b00001100; // **
11'h2f7: data = 8'b00011000; // **
11'h2f8: data = 8'b00110000; // **
11'h2f9: data = 8'b01100000; // **
11'h2fa: data = 8'b11000000; // **
11'h2fb: data = 8'b10000000; // *
11'h2fc: data = 8'b00000000; //
11'h2fd: data = 8'b00000000; //
11'h2fe: data = 8'b00000000; //
11'h2ff: data = 8'b00000000; //
//code x30
11'h300: data = 8'b00000000; //
11'h301: data = 8'b00000000; //
11'h302: data = 8'b01111100; // *****
11'h303: data = 8'b11000110; // ** **
11'h304: data = 8'b11000110; // ** **
11'h305: data = 8'b11001110; // ** ***
11'h306: data = 8'b11011110; // ** ****
11'h307: data = 8'b11110110; // **** **
11'h308: data = 8'b11100110; // *** **
11'h309: data = 8'b11000110; // ** **
11'h30a: data = 8'b11000110; // ** **
11'h30b: data = 8'b01111100; // *****
11'h30c: data = 8'b00000000; //
11'h30d: data = 8'b00000000; //
11'h30e: data = 8'b00000000; //
11'h30f: data = 8'b00000000; //
//code x31
11'h310: data = 8'b00000000; //
11'h311: data = 8'b00000000; //
11'h312: data = 8'b00011000; //
11'h313: data = 8'b00111000; //
11'h314: data = 8'b01111000; // **
11'h315: data = 8'b00011000; // ***
11'h316: data = 8'b00011000; // ****
11'h317: data = 8'b00011000; // **
11'h318: data = 8'b00011000; // **
11'h319: data = 8'b00011000; // **
11'h31a: data = 8'b00011000; // **
11'h31b: data = 8'b01111110; // **
11'h31c: data = 8'b00000000; // **
11'h31d: data = 8'b00000000; // ******
11'h31e: data = 8'b00000000; //
11'h31f: data = 8'b00000000; //
//code x32
11'h320: data = 8'b00000000; //
11'h321: data = 8'b00000000; //
11'h322: data = 8'b01111100; // *****
11'h323: data = 8'b11000110; // ** **
11'h324: data = 8'b00000110; // **
11'h325: data = 8'b00001100; // **
11'h326: data = 8'b00011000; // **
11'h327: data = 8'b00110000; // **
11'h328: data = 8'b01100000; // **
11'h329: data = 8'b11000000; // **
11'h32a: data = 8'b11000110; // ** **
11'h32b: data = 8'b11111110; // *******
11'h32c: data = 8'b00000000; //
11'h32d: data = 8'b00000000; //
11'h32e: data = 8'b00000000; //
11'h32f: data = 8'b00000000; //
//code x33
11'h330: data = 8'b00000000; //
11'h331: data = 8'b00000000; //
11'h332: data = 8'b01111100; // *****
11'h333: data = 8'b11000110; // ** **
11'h334: data = 8'b00000110; // **
11'h335: data = 8'b00000110; // **
11'h336: data = 8'b00111100; // ****
11'h337: data = 8'b00000110; // **
11'h338: data = 8'b00000110; // **
11'h339: data = 8'b00000110; // **
11'h33a: data = 8'b11000110; // ** **
11'h33b: data = 8'b01111100; // *****
11'h33c: data = 8'b00000000; //
11'h33d: data = 8'b00000000; //
11'h33e: data = 8'b00000000; //
11'h33f: data = 8'b00000000; //
//code x34
11'h340: data = 8'b00000000; //
11'h341: data = 8'b00000000; //
11'h342: data = 8'b00001100; // **
11'h343: data = 8'b00011100; // ***
11'h344: data = 8'b00111100; // ****
11'h345: data = 8'b01101100; // ** **
11'h346: data = 8'b11001100; // ** **
11'h347: data = 8'b11111110; // *******
11'h348: data = 8'b00001100; // **
11'h349: data = 8'b00001100; // **
11'h34a: data = 8'b00001100; // **
11'h34b: data = 8'b00011110; // ****
11'h34c: data = 8'b00000000; //
11'h34d: data = 8'b00000000; //
11'h34e: data = 8'b00000000; //
11'h34f: data = 8'b00000000; //
//code x35
11'h350: data = 8'b00000000; //
11'h351: data = 8'b00000000; //
11'h352: data = 8'b11111110; // *******
11'h353: data = 8'b11000000; // **
11'h354: data = 8'b11000000; // **
11'h355: data = 8'b11000000; // **
11'h356: data = 8'b11111100; // ******
11'h357: data = 8'b00000110; // **
11'h358: data = 8'b00000110; // **
11'h359: data = 8'b00000110; // **
11'h35a: data = 8'b11000110; // ** **
11'h35b: data = 8'b01111100; // *****
11'h35c: data = 8'b00000000; //
11'h35d: data = 8'b00000000; //
11'h35e: data = 8'b00000000; //
11'h35f: data = 8'b00000000; //
//code x36
11'h360: data = 8'b00000000; //
11'h361: data = 8'b00000000; //
11'h362: data = 8'b00111000; // ***
11'h363: data = 8'b01100000; // **
11'h364: data = 8'b11000000; // **
11'h365: data = 8'b11000000; // **
11'h366: data = 8'b11111100; // ******
11'h367: data = 8'b11000110; // ** **
11'h368: data = 8'b11000110; // ** **
11'h369: data = 8'b11000110; // ** **
11'h36a: data = 8'b11000110; // ** **
11'h36b: data = 8'b01111100; // *****
11'h36c: data = 8'b00000000; //
11'h36d: data = 8'b00000000; //
11'h36e: data = 8'b00000000; //
11'h36f: data = 8'b00000000; //
//code x37
11'h370: data = 8'b00000000; //
11'h371: data = 8'b00000000; //
11'h372: data = 8'b11111110; // *******
11'h373: data = 8'b11000110; // ** **
11'h374: data = 8'b00000110; // **
11'h375: data = 8'b00000110; // **
11'h376: data = 8'b00001100; // **
11'h377: data = 8'b00011000; // **
11'h378: data = 8'b00110000; // **
11'h379: data = 8'b00110000; // **
11'h37a: data = 8'b00110000; // **
11'h37b: data = 8'b00110000; // **
11'h37c: data = 8'b00000000; //
11'h37d: data = 8'b00000000; //
11'h37e: data = 8'b00000000; //
11'h37f: data = 8'b00000000; //
//code x38
11'h380: data = 8'b00000000; //
11'h381: data = 8'b00000000; //
11'h382: data = 8'b01111100; // *****
11'h383: data = 8'b11000110; // ** **
11'h384: data = 8'b11000110; // ** **
11'h385: data = 8'b11000110; // ** **
11'h386: data = 8'b01111100; // *****
11'h387: data = 8'b11000110; // ** **
11'h388: data = 8'b11000110; // ** **
11'h389: data = 8'b11000110; // ** **
11'h38a: data = 8'b11000110; // ** **
11'h38b: data = 8'b01111100; // *****
11'h38c: data = 8'b00000000; //
11'h38d: data = 8'b00000000; //
11'h38e: data = 8'b00000000; //
11'h38f: data = 8'b00000000; //
//code x39
11'h390: data = 8'b00000000; //
11'h391: data = 8'b00000000; //
11'h392: data = 8'b01111100; // *****
11'h393: data = 8'b11000110; // ** **
11'h394: data = 8'b11000110; // ** **
11'h395: data = 8'b11000110; // ** **
11'h396: data = 8'b01111110; // ******
11'h397: data = 8'b00000110; // **
11'h398: data = 8'b00000110; // **
11'h399: data = 8'b00000110; // **
11'h39a: data = 8'b00001100; // **
11'h39b: data = 8'b01111000; // ****
11'h39c: data = 8'b00000000; //
11'h39d: data = 8'b00000000; //
11'h39e: data = 8'b00000000; //
11'h39f: data = 8'b00000000; //
//code x3a
11'h3a0: data = 8'b00000000; //
11'h3a1: data = 8'b00000000; //
11'h3a2: data = 8'b00000000; //
11'h3a3: data = 8'b00000000; //
11'h3a4: data = 8'b00011000; // **
11'h3a5: data = 8'b00011000; // **
11'h3a6: data = 8'b00000000; //
11'h3a7: data = 8'b00000000; //
11'h3a8: data = 8'b00000000; //
11'h3a9: data = 8'b00011000; // **
11'h3aa: data = 8'b00011000; // **
11'h3ab: data = 8'b00000000; //
11'h3ac: data = 8'b00000000; //
11'h3ad: data = 8'b00000000; //
11'h3ae: data = 8'b00000000; //
11'h3af: data = 8'b00000000; //
//code x3b
11'h3b0: data = 8'b00000000; //
11'h3b1: data = 8'b00000000; //
11'h3b2: data = 8'b00000000; //
11'h3b3: data = 8'b00000000; //
11'h3b4: data = 8'b00011000; // **
11'h3b5: data = 8'b00011000; // **
11'h3b6: data = 8'b00000000; //
11'h3b7: data = 8'b00000000; //
11'h3b8: data = 8'b00000000; //
11'h3b9: data = 8'b00011000; // **
11'h3ba: data = 8'b00011000; // **
11'h3bb: data = 8'b00110000; // **
11'h3bc: data = 8'b00000000; //
11'h3bd: data = 8'b00000000; //
11'h3be: data = 8'b00000000; //
11'h3bf: data = 8'b00000000; //
//code x3c
11'h3c0: data = 8'b00000000; //
11'h3c1: data = 8'b00000000; //
11'h3c2: data = 8'b00000000; //
11'h3c3: data = 8'b00000110; // **
11'h3c4: data = 8'b00001100; // **
11'h3c5: data = 8'b00011000; // **
11'h3c6: data = 8'b00110000; // **
11'h3c7: data = 8'b01100000; // **
11'h3c8: data = 8'b00110000; // **
11'h3c9: data = 8'b00011000; // **
11'h3ca: data = 8'b00001100; // **
11'h3cb: data = 8'b00000110; // **
11'h3cc: data = 8'b00000000; //
11'h3cd: data = 8'b00000000; //
11'h3ce: data = 8'b00000000; //
11'h3cf: data = 8'b00000000; //
//code x3d
11'h3d0: data = 8'b00000000; //
11'h3d1: data = 8'b00000000; //
11'h3d2: data = 8'b00000000; //
11'h3d3: data = 8'b00000000; //
11'h3d4: data = 8'b00000000; //
11'h3d5: data = 8'b01111110; // ******
11'h3d6: data = 8'b00000000; //
11'h3d7: data = 8'b00000000; //
11'h3d8: data = 8'b01111110; // ******
11'h3d9: data = 8'b00000000; //
11'h3da: data = 8'b00000000; //
11'h3db: data = 8'b00000000; //
11'h3dc: data = 8'b00000000; //
11'h3dd: data = 8'b00000000; //
11'h3de: data = 8'b00000000; //
11'h3df: data = 8'b00000000; //
//code x3e
11'h3e0: data = 8'b00000000; //
11'h3e1: data = 8'b00000000; //
11'h3e2: data = 8'b00000000; //
11'h3e3: data = 8'b01100000; // **
11'h3e4: data = 8'b00110000; // **
11'h3e5: data = 8'b00011000; // **
11'h3e6: data = 8'b00001100; // **
11'h3e7: data = 8'b00000110; // **
11'h3e8: data = 8'b00001100; // **
11'h3e9: data = 8'b00011000; // **
11'h3ea: data = 8'b00110000; // **
11'h3eb: data = 8'b01100000; // **
11'h3ec: data = 8'b00000000; //
11'h3ed: data = 8'b00000000; //
11'h3ee: data = 8'b00000000; //
11'h3ef: data = 8'b00000000; //
//code x3f
11'h3f0: data = 8'b00000000; //
11'h3f1: data = 8'b00000000; //
11'h3f2: data = 8'b01111100; // *****
11'h3f3: data = 8'b11000110; // ** **
11'h3f4: data = 8'b11000110; // ** **
11'h3f5: data = 8'b00001100; // **
11'h3f6: data = 8'b00011000; // **
11'h3f7: data = 8'b00011000; // **
11'h3f8: data = 8'b00011000; // **
11'h3f9: data = 8'b00000000; //
11'h3fa: data = 8'b00011000; // **
11'h3fb: data = 8'b00011000; // **
11'h3fc: data = 8'b00000000; //
11'h3fd: data = 8'b00000000; //
11'h3fe: data = 8'b00000000; //
11'h3ff: data = 8'b00000000; //
//code x40
11'h400: data = 8'b00000000; //
11'h401: data = 8'b00000000; //
11'h402: data = 8'b01111100; // *****
11'h403: data = 8'b11000110; // ** **
11'h404: data = 8'b11000110; // ** **
11'h405: data = 8'b11000110; // ** **
11'h406: data = 8'b11011110; // ** ****
11'h407: data = 8'b11011110; // ** ****
11'h408: data = 8'b11011110; // ** ****
11'h409: data = 8'b11011100; // ** ***
11'h40a: data = 8'b11000000; // **
11'h40b: data = 8'b01111100; // *****
11'h40c: data = 8'b00000000; //
11'h40d: data = 8'b00000000; //
11'h40e: data = 8'b00000000; //
11'h40f: data = 8'b00000000; //
//code x41
11'h410: data = 8'b00000000; //
11'h411: data = 8'b00000000; //
11'h412: data = 8'b00010000; // *
11'h413: data = 8'b00111000; // ***
11'h414: data = 8'b01101100; // ** **
11'h415: data = 8'b11000110; // ** **
11'h416: data = 8'b11000110; // ** **
11'h417: data = 8'b11111110; // *******
11'h418: data = 8'b11000110; // ** **
11'h419: data = 8'b11000110; // ** **
11'h41a: data = 8'b11000110; // ** **
11'h41b: data = 8'b11000110; // ** **
11'h41c: data = 8'b00000000; //
11'h41d: data = 8'b00000000; //
11'h41e: data = 8'b00000000; //
11'h41f: data = 8'b00000000; //
//code x42
11'h420: data = 8'b00000000; //
11'h421: data = 8'b00000000; //
11'h422: data = 8'b11111100; // ******
11'h423: data = 8'b01100110; // ** **
11'h424: data = 8'b01100110; // ** **
11'h425: data = 8'b01100110; // ** **
11'h426: data = 8'b01111100; // *****
11'h427: data = 8'b01100110; // ** **
11'h428: data = 8'b01100110; // ** **
11'h429: data = 8'b01100110; // ** **
11'h42a: data = 8'b01100110; // ** **
11'h42b: data = 8'b11111100; // ******
11'h42c: data = 8'b00000000; //
11'h42d: data = 8'b00000000; //
11'h42e: data = 8'b00000000; //
11'h42f: data = 8'b00000000; //
//code x43
11'h430: data = 8'b00000000; //
11'h431: data = 8'b00000000; //
11'h432: data = 8'b00111100; // ****
11'h433: data = 8'b01100110; // ** **
11'h434: data = 8'b11000010; // ** *
11'h435: data = 8'b11000000; // **
11'h436: data = 8'b11000000; // **
11'h437: data = 8'b11000000; // **
11'h438: data = 8'b11000000; // **
11'h439: data = 8'b11000010; // ** *
11'h43a: data = 8'b01100110; // ** **
11'h43b: data = 8'b00111100; // ****
11'h43c: data = 8'b00000000; //
11'h43d: data = 8'b00000000; //
11'h43e: data = 8'b00000000; //
11'h43f: data = 8'b00000000; //
//code x44
11'h440: data = 8'b00000000; //
11'h441: data = 8'b00000000; //
11'h442: data = 8'b11111000; // *****
11'h443: data = 8'b01101100; // ** **
11'h444: data = 8'b01100110; // ** **
11'h445: data = 8'b01100110; // ** **
11'h446: data = 8'b01100110; // ** **
11'h447: data = 8'b01100110; // ** **
11'h448: data = 8'b01100110; // ** **
11'h449: data = 8'b01100110; // ** **
11'h44a: data = 8'b01101100; // ** **
11'h44b: data = 8'b11111000; // *****
11'h44c: data = 8'b00000000; //
11'h44d: data = 8'b00000000; //
11'h44e: data = 8'b00000000; //
11'h44f: data = 8'b00000000; //
//code x45
11'h450: data = 8'b00000000; //
11'h451: data = 8'b00000000; //
11'h452: data = 8'b11111110; // *******
11'h453: data = 8'b01100110; // ** **
11'h454: data = 8'b01100010; // ** *
11'h455: data = 8'b01101000; // ** *
11'h456: data = 8'b01111000; // ****
11'h457: data = 8'b01101000; // ** *
11'h458: data = 8'b01100000; // **
11'h459: data = 8'b01100010; // ** *
11'h45a: data = 8'b01100110; // ** **
11'h45b: data = 8'b11111110; // *******
11'h45c: data = 8'b00000000; //
11'h45d: data = 8'b00000000; //
11'h45e: data = 8'b00000000; //
11'h45f: data = 8'b00000000; //
//code x46
11'h460: data = 8'b00000000; //
11'h461: data = 8'b00000000; //
11'h462: data = 8'b11111110; // *******
11'h463: data = 8'b01100110; // ** **
11'h464: data = 8'b01100010; // ** *
11'h465: data = 8'b01101000; // ** *
11'h466: data = 8'b01111000; // ****
11'h467: data = 8'b01101000; // ** *
11'h468: data = 8'b01100000; // **
11'h469: data = 8'b01100000; // **
11'h46a: data = 8'b01100000; // **
11'h46b: data = 8'b11110000; // ****
11'h46c: data = 8'b00000000; //
11'h46d: data = 8'b00000000; //
11'h46e: data = 8'b00000000; //
11'h46f: data = 8'b00000000; //
//code x47
11'h470: data = 8'b00000000; //
11'h471: data = 8'b00000000; //
11'h472: data = 8'b00111100; // ****
11'h473: data = 8'b01100110; // ** **
11'h474: data = 8'b11000010; // ** *
11'h475: data = 8'b11000000; // **
11'h476: data = 8'b11000000; // **
11'h477: data = 8'b11011110; // ** ****
11'h478: data = 8'b11000110; // ** **
11'h479: data = 8'b11000110; // ** **
11'h47a: data = 8'b01100110; // ** **
11'h47b: data = 8'b00111010; // *** *
11'h47c: data = 8'b00000000; //
11'h47d: data = 8'b00000000; //
11'h47e: data = 8'b00000000; //
11'h47f: data = 8'b00000000; //
//code x48
11'h480: data = 8'b00000000; //
11'h481: data = 8'b00000000; //
11'h482: data = 8'b11000110; // ** **
11'h483: data = 8'b11000110; // ** **
11'h484: data = 8'b11000110; // ** **
11'h485: data = 8'b11000110; // ** **
11'h486: data = 8'b11111110; // *******
11'h487: data = 8'b11000110; // ** **
11'h488: data = 8'b11000110; // ** **
11'h489: data = 8'b11000110; // ** **
11'h48a: data = 8'b11000110; // ** **
11'h48b: data = 8'b11000110; // ** **
11'h48c: data = 8'b00000000; //
11'h48d: data = 8'b00000000; //
11'h48e: data = 8'b00000000; //
11'h48f: data = 8'b00000000; //
//code x49
11'h490: data = 8'b00000000; //
11'h491: data = 8'b00000000; //
11'h492: data = 8'b00111100; // ****
11'h493: data = 8'b00011000; // **
11'h494: data = 8'b00011000; // **
11'h495: data = 8'b00011000; // **
11'h496: data = 8'b00011000; // **
11'h497: data = 8'b00011000; // **
11'h498: data = 8'b00011000; // **
11'h499: data = 8'b00011000; // **
11'h49a: data = 8'b00011000; // **
11'h49b: data = 8'b00111100; // ****
11'h49c: data = 8'b00000000; //
11'h49d: data = 8'b00000000; //
11'h49e: data = 8'b00000000; //
11'h49f: data = 8'b00000000; //
//code x4a
11'h4a0: data = 8'b00000000; //
11'h4a1: data = 8'b00000000; //
11'h4a2: data = 8'b00011110; // ****
11'h4a3: data = 8'b00001100; // **
11'h4a4: data = 8'b00001100; // **
11'h4a5: data = 8'b00001100; // **
11'h4a6: data = 8'b00001100; // **
11'h4a7: data = 8'b00001100; // **
11'h4a8: data = 8'b11001100; // ** **
11'h4a9: data = 8'b11001100; // ** **
11'h4aa: data = 8'b11001100; // ** **
11'h4ab: data = 8'b01111000; // ****
11'h4ac: data = 8'b00000000; //
11'h4ad: data = 8'b00000000; //
11'h4ae: data = 8'b00000000; //
11'h4af: data = 8'b00000000; //
//code x4b
11'h4b0: data = 8'b00000000; //
11'h4b1: data = 8'b00000000; //
11'h4b2: data = 8'b11100110; // *** **
11'h4b3: data = 8'b01100110; // ** **
11'h4b4: data = 8'b01100110; // ** **
11'h4b5: data = 8'b01101100; // ** **
11'h4b6: data = 8'b01111000; // ****
11'h4b7: data = 8'b01111000; // ****
11'h4b8: data = 8'b01101100; // ** **
11'h4b9: data = 8'b01100110; // ** **
11'h4ba: data = 8'b01100110; // ** **
11'h4bb: data = 8'b11100110; // *** **
11'h4bc: data = 8'b00000000; //
11'h4bd: data = 8'b00000000; //
11'h4be: data = 8'b00000000; //
11'h4bf: data = 8'b00000000; //
//code x4c
11'h4c0: data = 8'b00000000; //
11'h4c1: data = 8'b00000000; //
11'h4c2: data = 8'b11110000; // ****
11'h4c3: data = 8'b01100000; // **
11'h4c4: data = 8'b01100000; // **
11'h4c5: data = 8'b01100000; // **
11'h4c6: data = 8'b01100000; // **
11'h4c7: data = 8'b01100000; // **
11'h4c8: data = 8'b01100000; // **
11'h4c9: data = 8'b01100010; // ** *
11'h4ca: data = 8'b01100110; // ** **
11'h4cb: data = 8'b11111110; // *******
11'h4cc: data = 8'b00000000; //
11'h4cd: data = 8'b00000000; //
11'h4ce: data = 8'b00000000; //
11'h4cf: data = 8'b00000000; //
//code x4d
11'h4d0: data = 8'b00000000; //
11'h4d1: data = 8'b00000000; //
11'h4d2: data = 8'b11000011; // ** **
11'h4d3: data = 8'b11100111; // *** ***
11'h4d4: data = 8'b11111111; // ********
11'h4d5: data = 8'b11111111; // ********
11'h4d6: data = 8'b11011011; // ** ** **
11'h4d7: data = 8'b11000011; // ** **
11'h4d8: data = 8'b11000011; // ** **
11'h4d9: data = 8'b11000011; // ** **
11'h4da: data = 8'b11000011; // ** **
11'h4db: data = 8'b11000011; // ** **
11'h4dc: data = 8'b00000000; //
11'h4dd: data = 8'b00000000; //
11'h4de: data = 8'b00000000; //
11'h4df: data = 8'b00000000; //
//code x4e
11'h4e0: data = 8'b00000000; //
11'h4e1: data = 8'b00000000; //
11'h4e2: data = 8'b11000110; // ** **
11'h4e3: data = 8'b11100110; // *** **
11'h4e4: data = 8'b11110110; // **** **
11'h4e5: data = 8'b11111110; // *******
11'h4e6: data = 8'b11011110; // ** ****
11'h4e7: data = 8'b11001110; // ** ***
11'h4e8: data = 8'b11000110; // ** **
11'h4e9: data = 8'b11000110; // ** **
11'h4ea: data = 8'b11000110; // ** **
11'h4eb: data = 8'b11000110; // ** **
11'h4ec: data = 8'b00000000; //
11'h4ed: data = 8'b00000000; //
11'h4ee: data = 8'b00000000; //
11'h4ef: data = 8'b00000000; //
//code x4f
11'h4f0: data = 8'b00000000; //
11'h4f1: data = 8'b00000000; //
11'h4f2: data = 8'b01111100; // *****
11'h4f3: data = 8'b11000110; // ** **
11'h4f4: data = 8'b11000110; // ** **
11'h4f5: data = 8'b11000110; // ** **
11'h4f6: data = 8'b11000110; // ** **
11'h4f7: data = 8'b11000110; // ** **
11'h4f8: data = 8'b11000110; // ** **
11'h4f9: data = 8'b11000110; // ** **
11'h4fa: data = 8'b11000110; // ** **
11'h4fb: data = 8'b01111100; // *****
11'h4fc: data = 8'b00000000; //
11'h4fd: data = 8'b00000000; //
11'h4fe: data = 8'b00000000; //
11'h4ff: data = 8'b00000000; //
//code x50
11'h500: data = 8'b00000000; //
11'h501: data = 8'b00000000; //
11'h502: data = 8'b11111100; // ******
11'h503: data = 8'b01100110; // ** **
11'h504: data = 8'b01100110; // ** **
11'h505: data = 8'b01100110; // ** **
11'h506: data = 8'b01111100; // *****
11'h507: data = 8'b01100000; // **
11'h508: data = 8'b01100000; // **
11'h509: data = 8'b01100000; // **
11'h50a: data = 8'b01100000; // **
11'h50b: data = 8'b11110000; // ****
11'h50c: data = 8'b00000000; //
11'h50d: data = 8'b00000000; //
11'h50e: data = 8'b00000000; //
11'h50f: data = 8'b00000000; //
//code x510f
11'h510: data = 8'b00000000; //
11'h511: data = 8'b00000000; //
11'h512: data = 8'b01111100; // *****
11'h513: data = 8'b11000110; // ** **
11'h514: data = 8'b11000110; // ** **
11'h515: data = 8'b11000110; // ** **
11'h516: data = 8'b11000110; // ** **
11'h517: data = 8'b11000110; // ** **
11'h518: data = 8'b11000110; // ** **
11'h519: data = 8'b11010110; // ** * **
11'h51a: data = 8'b11011110; // ** ****
11'h51b: data = 8'b01111100; // *****
11'h51c: data = 8'b00001100; // **
11'h51d: data = 8'b00001110; // ***
11'h51e: data = 8'b00000000; //
11'h51f: data = 8'b00000000; //
//code x52
11'h520: data = 8'b00000000; //
11'h521: data = 8'b00000000; //
11'h522: data = 8'b11111100; // ******
11'h523: data = 8'b01100110; // ** **
11'h524: data = 8'b01100110; // ** **
11'h525: data = 8'b01100110; // ** **
11'h526: data = 8'b01111100; // *****
11'h527: data = 8'b01101100; // ** **
11'h528: data = 8'b01100110; // ** **
11'h529: data = 8'b01100110; // ** **
11'h52a: data = 8'b01100110; // ** **
11'h52b: data = 8'b11100110; // *** **
11'h52c: data = 8'b00000000; //
11'h52d: data = 8'b00000000; //
11'h52e: data = 8'b00000000; //
11'h52f: data = 8'b00000000; //
//code x53
11'h530: data = 8'b00000000; //
11'h531: data = 8'b00000000; //
11'h532: data = 8'b01111100; // *****
11'h533: data = 8'b11000110; // ** **
11'h534: data = 8'b11000110; // ** **
11'h535: data = 8'b01100000; // **
11'h536: data = 8'b00111000; // ***
11'h537: data = 8'b00001100; // **
11'h538: data = 8'b00000110; // **
11'h539: data = 8'b11000110; // ** **
11'h53a: data = 8'b11000110; // ** **
11'h53b: data = 8'b01111100; // *****
11'h53c: data = 8'b00000000; //
11'h53d: data = 8'b00000000; //
11'h53e: data = 8'b00000000; //
11'h53f: data = 8'b00000000; //
//code x54
11'h540: data = 8'b00000000; //
11'h541: data = 8'b00000000; //
11'h542: data = 8'b11111111; // ********
11'h543: data = 8'b11011011; // ** ** **
11'h544: data = 8'b10011001; // * ** *
11'h545: data = 8'b00011000; // **
11'h546: data = 8'b00011000; // **
11'h547: data = 8'b00011000; // **
11'h548: data = 8'b00011000; // **
11'h549: data = 8'b00011000; // **
11'h54a: data = 8'b00011000; // **
11'h54b: data = 8'b00111100; // ****
11'h54c: data = 8'b00000000; //
11'h54d: data = 8'b00000000; //
11'h54e: data = 8'b00000000; //
11'h54f: data = 8'b00000000; //
//code x55
11'h550: data = 8'b00000000; //
11'h551: data = 8'b00000000; //
11'h552: data = 8'b11000110; // ** **
11'h553: data = 8'b11000110; // ** **
11'h554: data = 8'b11000110; // ** **
11'h555: data = 8'b11000110; // ** **
11'h556: data = 8'b11000110; // ** **
11'h557: data = 8'b11000110; // ** **
11'h558: data = 8'b11000110; // ** **
11'h559: data = 8'b11000110; // ** **
11'h55a: data = 8'b11000110; // ** **
11'h55b: data = 8'b01111100; // *****
11'h55c: data = 8'b00000000; //
11'h55d: data = 8'b00000000; //
11'h55e: data = 8'b00000000; //
11'h55f: data = 8'b00000000; //
//code x56
11'h560: data = 8'b00000000; //
11'h561: data = 8'b00000000; //
11'h562: data = 8'b11000011; // ** **
11'h563: data = 8'b11000011; // ** **
11'h564: data = 8'b11000011; // ** **
11'h565: data = 8'b11000011; // ** **
11'h566: data = 8'b11000011; // ** **
11'h567: data = 8'b11000011; // ** **
11'h568: data = 8'b11000011; // ** **
11'h569: data = 8'b01100110; // ** **
11'h56a: data = 8'b00111100; // ****
11'h56b: data = 8'b00011000; // **
11'h56c: data = 8'b00000000; //
11'h56d: data = 8'b00000000; //
11'h56e: data = 8'b00000000; //
11'h56f: data = 8'b00000000; //
//code x57
11'h570: data = 8'b00000000; //
11'h571: data = 8'b00000000; //
11'h572: data = 8'b11000011; // ** **
11'h573: data = 8'b11000011; // ** **
11'h574: data = 8'b11000011; // ** **
11'h575: data = 8'b11000011; // ** **
11'h576: data = 8'b11000011; // ** **
11'h577: data = 8'b11011011; // ** ** **
11'h578: data = 8'b11011011; // ** ** **
11'h579: data = 8'b11111111; // ********
11'h57a: data = 8'b01100110; // ** **
11'h57b: data = 8'b01100110; // ** **
11'h57c: data = 8'b00000000; //
11'h57d: data = 8'b00000000; //
11'h57e: data = 8'b00000000; //
11'h57f: data = 8'b00000000; //
//code x58
11'h580: data = 8'b00000000; //
11'h581: data = 8'b00000000; //
11'h582: data = 8'b11000011; // ** **
11'h583: data = 8'b11000011; // ** **
11'h584: data = 8'b01100110; // ** **
11'h585: data = 8'b00111100; // ****
11'h586: data = 8'b00011000; // **
11'h587: data = 8'b00011000; // **
11'h588: data = 8'b00111100; // ****
11'h589: data = 8'b01100110; // ** **
11'h58a: data = 8'b11000011; // ** **
11'h58b: data = 8'b11000011; // ** **
11'h58c: data = 8'b00000000; //
11'h58d: data = 8'b00000000; //
11'h58e: data = 8'b00000000; //
11'h58f: data = 8'b00000000; //
//code x59
11'h590: data = 8'b00000000; //
11'h591: data = 8'b00000000; //
11'h592: data = 8'b11000011; // ** **
11'h593: data = 8'b11000011; // ** **
11'h594: data = 8'b11000011; // ** **
11'h595: data = 8'b01100110; // ** **
11'h596: data = 8'b00111100; // ****
11'h597: data = 8'b00011000; // **
11'h598: data = 8'b00011000; // **
11'h599: data = 8'b00011000; // **
11'h59a: data = 8'b00011000; // **
11'h59b: data = 8'b00111100; // ****
11'h59c: data = 8'b00000000; //
11'h59d: data = 8'b00000000; //
11'h59e: data = 8'b00000000; //
11'h59f: data = 8'b00000000; //
//code x5a
11'h5a0: data = 8'b00000000; //
11'h5a1: data = 8'b00000000; //
11'h5a2: data = 8'b11111111; // ********
11'h5a3: data = 8'b11000011; // ** **
11'h5a4: data = 8'b10000110; // * **
11'h5a5: data = 8'b00001100; // **
11'h5a6: data = 8'b00011000; // **
11'h5a7: data = 8'b00110000; // **
11'h5a8: data = 8'b01100000; // **
11'h5a9: data = 8'b11000001; // ** *
11'h5aa: data = 8'b11000011; // ** **
11'h5ab: data = 8'b11111111; // ********
11'h5ac: data = 8'b00000000; //
11'h5ad: data = 8'b00000000; //
11'h5ae: data = 8'b00000000; //
11'h5af: data = 8'b00000000; //
//code x5b
11'h5b0: data = 8'b00000000; //
11'h5b1: data = 8'b00000000; //
11'h5b2: data = 8'b00111100; // ****
11'h5b3: data = 8'b00110000; // **
11'h5b4: data = 8'b00110000; // **
11'h5b5: data = 8'b00110000; // **
11'h5b6: data = 8'b00110000; // **
11'h5b7: data = 8'b00110000; // **
11'h5b8: data = 8'b00110000; // **
11'h5b9: data = 8'b00110000; // **
11'h5ba: data = 8'b00110000; // **
11'h5bb: data = 8'b00111100; // ****
11'h5bc: data = 8'b00000000; //
11'h5bd: data = 8'b00000000; //
11'h5be: data = 8'b00000000; //
11'h5bf: data = 8'b00000000; //
//code x5c
11'h5c0: data = 8'b00000000; //
11'h5c1: data = 8'b00000000; //
11'h5c2: data = 8'b00000000; //
11'h5c3: data = 8'b10000000; // *
11'h5c4: data = 8'b11000000; // **
11'h5c5: data = 8'b11100000; // ***
11'h5c6: data = 8'b01110000; // ***
11'h5c7: data = 8'b00111000; // ***
11'h5c8: data = 8'b00011100; // ***
11'h5c9: data = 8'b00001110; // ***
11'h5ca: data = 8'b00000110; // **
11'h5cb: data = 8'b00000010; // *
11'h5cc: data = 8'b00000000; //
11'h5cd: data = 8'b00000000; //
11'h5ce: data = 8'b00000000; //
11'h5cf: data = 8'b00000000; //
//code x5d
11'h5d0: data = 8'b00000000; //
11'h5d1: data = 8'b00000000; //
11'h5d2: data = 8'b00111100; // ****
11'h5d3: data = 8'b00001100; // **
11'h5d4: data = 8'b00001100; // **
11'h5d5: data = 8'b00001100; // **
11'h5d6: data = 8'b00001100; // **
11'h5d7: data = 8'b00001100; // **
11'h5d8: data = 8'b00001100; // **
11'h5d9: data = 8'b00001100; // **
11'h5da: data = 8'b00001100; // **
11'h5db: data = 8'b00111100; // ****
11'h5dc: data = 8'b00000000; //
11'h5dd: data = 8'b00000000; //
11'h5de: data = 8'b00000000; //
11'h5df: data = 8'b00000000; //
//code x5e
11'h5e0: data = 8'b00010000; // *
11'h5e1: data = 8'b00111000; // ***
11'h5e2: data = 8'b01101100; // ** **
11'h5e3: data = 8'b11000110; // ** **
11'h5e4: data = 8'b00000000; //
11'h5e5: data = 8'b00000000; //
11'h5e6: data = 8'b00000000; //
11'h5e7: data = 8'b00000000; //
11'h5e8: data = 8'b00000000; //
11'h5e9: data = 8'b00000000; //
11'h5ea: data = 8'b00000000; //
11'h5eb: data = 8'b00000000; //
11'h5ec: data = 8'b00000000; //
11'h5ed: data = 8'b00000000; //
11'h5ee: data = 8'b00000000; //
11'h5ef: data = 8'b00000000; //
//code x5f
11'h5f0: data = 8'b00000000; //
11'h5f1: data = 8'b00000000; //
11'h5f2: data = 8'b00000000; //
11'h5f3: data = 8'b00000000; //
11'h5f4: data = 8'b00000000; //
11'h5f5: data = 8'b00000000; //
11'h5f6: data = 8'b00000000; //
11'h5f7: data = 8'b00000000; //
11'h5f8: data = 8'b00000000; //
11'h5f9: data = 8'b00000000; //
11'h5fa: data = 8'b00000000; //
11'h5fb: data = 8'b00000000; //
11'h5fc: data = 8'b00000000; //
11'h5fd: data = 8'b11111111; // ********
11'h5fe: data = 8'b00000000; //
11'h5ff: data = 8'b00000000; //
//code x60
11'h600: data = 8'b00110000; // **
11'h601: data = 8'b00110000; // **
11'h602: data = 8'b00011000; // **
11'h603: data = 8'b00000000; //
11'h604: data = 8'b00000000; //
11'h605: data = 8'b00000000; //
11'h606: data = 8'b00000000; //
11'h607: data = 8'b00000000; //
11'h608: data = 8'b00000000; //
11'h609: data = 8'b00000000; //
11'h60a: data = 8'b00000000; //
11'h60b: data = 8'b00000000; //
11'h60c: data = 8'b00000000; //
11'h60d: data = 8'b00000000; //
11'h60e: data = 8'b00000000; //
11'h60f: data = 8'b00000000; //
//code x61
11'h610: data = 8'b00000000; //
11'h611: data = 8'b00000000; //
11'h612: data = 8'b00000000; //
11'h613: data = 8'b00000000; //
11'h614: data = 8'b00000000; //
11'h615: data = 8'b01111000; // ****
11'h616: data = 8'b00001100; // **
11'h617: data = 8'b01111100; // *****
11'h618: data = 8'b11001100; // ** **
11'h619: data = 8'b11001100; // ** **
11'h61a: data = 8'b11001100; // ** **
11'h61b: data = 8'b01110110; // *** **
11'h61c: data = 8'b00000000; //
11'h61d: data = 8'b00000000; //
11'h61e: data = 8'b00000000; //
11'h61f: data = 8'b00000000; //
//code x62
11'h620: data = 8'b00000000; //
11'h621: data = 8'b00000000; //
11'h622: data = 8'b11100000; // ***
11'h623: data = 8'b01100000; // **
11'h624: data = 8'b01100000; // **
11'h625: data = 8'b01111000; // ****
11'h626: data = 8'b01101100; // ** **
11'h627: data = 8'b01100110; // ** **
11'h628: data = 8'b01100110; // ** **
11'h629: data = 8'b01100110; // ** **
11'h62a: data = 8'b01100110; // ** **
11'h62b: data = 8'b01111100; // *****
11'h62c: data = 8'b00000000; //
11'h62d: data = 8'b00000000; //
11'h62e: data = 8'b00000000; //
11'h62f: data = 8'b00000000; //
//code x63
11'h630: data = 8'b00000000; //
11'h631: data = 8'b00000000; //
11'h632: data = 8'b00000000; //
11'h633: data = 8'b00000000; //
11'h634: data = 8'b00000000; //
11'h635: data = 8'b01111100; // *****
11'h636: data = 8'b11000110; // ** **
11'h637: data = 8'b11000000; // **
11'h638: data = 8'b11000000; // **
11'h639: data = 8'b11000000; // **
11'h63a: data = 8'b11000110; // ** **
11'h63b: data = 8'b01111100; // *****
11'h63c: data = 8'b00000000; //
11'h63d: data = 8'b00000000; //
11'h63e: data = 8'b00000000; //
11'h63f: data = 8'b00000000; //
//code x64
11'h640: data = 8'b00000000; //
11'h641: data = 8'b00000000; //
11'h642: data = 8'b00011100; // ***
11'h643: data = 8'b00001100; // **
11'h644: data = 8'b00001100; // **
11'h645: data = 8'b00111100; // ****
11'h646: data = 8'b01101100; // ** **
11'h647: data = 8'b11001100; // ** **
11'h648: data = 8'b11001100; // ** **
11'h649: data = 8'b11001100; // ** **
11'h64a: data = 8'b11001100; // ** **
11'h64b: data = 8'b01110110; // *** **
11'h64c: data = 8'b00000000; //
11'h64d: data = 8'b00000000; //
11'h64e: data = 8'b00000000; //
11'h64f: data = 8'b00000000; //
//code x65
11'h650: data = 8'b00000000; //
11'h651: data = 8'b00000000; //
11'h652: data = 8'b00000000; //
11'h653: data = 8'b00000000; //
11'h654: data = 8'b00000000; //
11'h655: data = 8'b01111100; // *****
11'h656: data = 8'b11000110; // ** **
11'h657: data = 8'b11111110; // *******
11'h658: data = 8'b11000000; // **
11'h659: data = 8'b11000000; // **
11'h65a: data = 8'b11000110; // ** **
11'h65b: data = 8'b01111100; // *****
11'h65c: data = 8'b00000000; //
11'h65d: data = 8'b00000000; //
11'h65e: data = 8'b00000000; //
11'h65f: data = 8'b00000000; //
//code x66
11'h660: data = 8'b00000000; //
11'h661: data = 8'b00000000; //
11'h662: data = 8'b00111000; // ***
11'h663: data = 8'b01101100; // ** **
11'h664: data = 8'b01100100; // ** *
11'h665: data = 8'b01100000; // **
11'h666: data = 8'b11110000; // ****
11'h667: data = 8'b01100000; // **
11'h668: data = 8'b01100000; // **
11'h669: data = 8'b01100000; // **
11'h66a: data = 8'b01100000; // **
11'h66b: data = 8'b11110000; // ****
11'h66c: data = 8'b00000000; //
11'h66d: data = 8'b00000000; //
11'h66e: data = 8'b00000000; //
11'h66f: data = 8'b00000000; //
//code x67
11'h670: data = 8'b00000000; //
11'h671: data = 8'b00000000; //
11'h672: data = 8'b00000000; //
11'h673: data = 8'b00000000; //
11'h674: data = 8'b00000000; //
11'h675: data = 8'b01110110; // *** **
11'h676: data = 8'b11001100; // ** **
11'h677: data = 8'b11001100; // ** **
11'h678: data = 8'b11001100; // ** **
11'h679: data = 8'b11001100; // ** **
11'h67a: data = 8'b11001100; // ** **
11'h67b: data = 8'b01111100; // *****
11'h67c: data = 8'b00001100; // **
11'h67d: data = 8'b11001100; // ** **
11'h67e: data = 8'b01111000; // ****
11'h67f: data = 8'b00000000; //
//code x68
11'h680: data = 8'b00000000; //
11'h681: data = 8'b00000000; //
11'h682: data = 8'b11100000; // ***
11'h683: data = 8'b01100000; // **
11'h684: data = 8'b01100000; // **
11'h685: data = 8'b01101100; // ** **
11'h686: data = 8'b01110110; // *** **
11'h687: data = 8'b01100110; // ** **
11'h688: data = 8'b01100110; // ** **
11'h689: data = 8'b01100110; // ** **
11'h68a: data = 8'b01100110; // ** **
11'h68b: data = 8'b11100110; // *** **
11'h68c: data = 8'b00000000; //
11'h68d: data = 8'b00000000; //
11'h68e: data = 8'b00000000; //
11'h68f: data = 8'b00000000; //
//code x69
11'h690: data = 8'b00000000; //
11'h691: data = 8'b00000000; //
11'h692: data = 8'b00011000; // **
11'h693: data = 8'b00011000; // **
11'h694: data = 8'b00000000; //
11'h695: data = 8'b00111000; // ***
11'h696: data = 8'b00011000; // **
11'h697: data = 8'b00011000; // **
11'h698: data = 8'b00011000; // **
11'h699: data = 8'b00011000; // **
11'h69a: data = 8'b00011000; // **
11'h69b: data = 8'b00111100; // ****
11'h69c: data = 8'b00000000; //
11'h69d: data = 8'b00000000; //
11'h69e: data = 8'b00000000; //
11'h69f: data = 8'b00000000; //
//code x6a
11'h6a0: data = 8'b00000000; //
11'h6a1: data = 8'b00000000; //
11'h6a2: data = 8'b00000110; // **
11'h6a3: data = 8'b00000110; // **
11'h6a4: data = 8'b00000000; //
11'h6a5: data = 8'b00001110; // ***
11'h6a6: data = 8'b00000110; // **
11'h6a7: data = 8'b00000110; // **
11'h6a8: data = 8'b00000110; // **
11'h6a9: data = 8'b00000110; // **
11'h6aa: data = 8'b00000110; // **
11'h6ab: data = 8'b00000110; // **
11'h6ac: data = 8'b01100110; // ** **
11'h6ad: data = 8'b01100110; // ** **
11'h6ae: data = 8'b00111100; // ****
11'h6af: data = 8'b00000000; //
//code x6b
11'h6b0: data = 8'b00000000; //
11'h6b1: data = 8'b00000000; //
11'h6b2: data = 8'b11100000; // ***
11'h6b3: data = 8'b01100000; // **
11'h6b4: data = 8'b01100000; // **
11'h6b5: data = 8'b01100110; // ** **
11'h6b6: data = 8'b01101100; // ** **
11'h6b7: data = 8'b01111000; // ****
11'h6b8: data = 8'b01111000; // ****
11'h6b9: data = 8'b01101100; // ** **
11'h6ba: data = 8'b01100110; // ** **
11'h6bb: data = 8'b11100110; // *** **
11'h6bc: data = 8'b00000000; //
11'h6bd: data = 8'b00000000; //
11'h6be: data = 8'b00000000; //
11'h6bf: data = 8'b00000000; //
//code x6c
11'h6c0: data = 8'b00000000; //
11'h6c1: data = 8'b00000000; //
11'h6c2: data = 8'b00111000; // ***
11'h6c3: data = 8'b00011000; // **
11'h6c4: data = 8'b00011000; // **
11'h6c5: data = 8'b00011000; // **
11'h6c6: data = 8'b00011000; // **
11'h6c7: data = 8'b00011000; // **
11'h6c8: data = 8'b00011000; // **
11'h6c9: data = 8'b00011000; // **
11'h6ca: data = 8'b00011000; // **
11'h6cb: data = 8'b00111100; // ****
11'h6cc: data = 8'b00000000; //
11'h6cd: data = 8'b00000000; //
11'h6ce: data = 8'b00000000; //
11'h6cf: data = 8'b00000000; //
//code x6d
11'h6d0: data = 8'b00000000; //
11'h6d1: data = 8'b00000000; //
11'h6d2: data = 8'b00000000; //
11'h6d3: data = 8'b00000000; //
11'h6d4: data = 8'b00000000; //
11'h6d5: data = 8'b11100110; // *** **
11'h6d6: data = 8'b11111111; // ********
11'h6d7: data = 8'b11011011; // ** ** **
11'h6d8: data = 8'b11011011; // ** ** **
11'h6d9: data = 8'b11011011; // ** ** **
11'h6da: data = 8'b11011011; // ** ** **
11'h6db: data = 8'b11011011; // ** ** **
11'h6dc: data = 8'b00000000; //
11'h6dd: data = 8'b00000000; //
11'h6de: data = 8'b00000000; //
11'h6df: data = 8'b00000000; //
//code x6e
11'h6e0: data = 8'b00000000; //
11'h6e1: data = 8'b00000000; //
11'h6e2: data = 8'b00000000; //
11'h6e3: data = 8'b00000000; //
11'h6e4: data = 8'b00000000; //
11'h6e5: data = 8'b11011100; // ** ***
11'h6e6: data = 8'b01100110; // ** **
11'h6e7: data = 8'b01100110; // ** **
11'h6e8: data = 8'b01100110; // ** **
11'h6e9: data = 8'b01100110; // ** **
11'h6ea: data = 8'b01100110; // ** **
11'h6eb: data = 8'b01100110; // ** **
11'h6ec: data = 8'b00000000; //
11'h6ed: data = 8'b00000000; //
11'h6ee: data = 8'b00000000; //
11'h6ef: data = 8'b00000000; //
//code x6f
11'h6f0: data = 8'b00000000; //
11'h6f1: data = 8'b00000000; //
11'h6f2: data = 8'b00000000; //
11'h6f3: data = 8'b00000000; //
11'h6f4: data = 8'b00000000; //
11'h6f5: data = 8'b01111100; // *****
11'h6f6: data = 8'b11000110; // ** **
11'h6f7: data = 8'b11000110; // ** **
11'h6f8: data = 8'b11000110; // ** **
11'h6f9: data = 8'b11000110; // ** **
11'h6fa: data = 8'b11000110; // ** **
11'h6fb: data = 8'b01111100; // *****
11'h6fc: data = 8'b00000000; //
11'h6fd: data = 8'b00000000; //
11'h6fe: data = 8'b00000000; //
11'h6ff: data = 8'b00000000; //
//code x70
11'h700: data = 8'b00000000; //
11'h701: data = 8'b00000000; //
11'h702: data = 8'b00000000; //
11'h703: data = 8'b00000000; //
11'h704: data = 8'b00000000; //
11'h705: data = 8'b11011100; // ** ***
11'h706: data = 8'b01100110; // ** **
11'h707: data = 8'b01100110; // ** **
11'h708: data = 8'b01100110; // ** **
11'h709: data = 8'b01100110; // ** **
11'h70a: data = 8'b01100110; // ** **
11'h70b: data = 8'b01111100; // *****
11'h70c: data = 8'b01100000; // **
11'h70d: data = 8'b01100000; // **
11'h70e: data = 8'b11110000; // ****
11'h70f: data = 8'b00000000; //
//code x71
11'h710: data = 8'b00000000; //
11'h711: data = 8'b00000000; //
11'h712: data = 8'b00000000; //
11'h713: data = 8'b00000000; //
11'h714: data = 8'b00000000; //
11'h715: data = 8'b01110110; // *** **
11'h716: data = 8'b11001100; // ** **
11'h717: data = 8'b11001100; // ** **
11'h718: data = 8'b11001100; // ** **
11'h719: data = 8'b11001100; // ** **
11'h71a: data = 8'b11001100; // ** **
11'h71b: data = 8'b01111100; // *****
11'h71c: data = 8'b00001100; // **
11'h71d: data = 8'b00001100; // **
11'h71e: data = 8'b00011110; // ****
11'h71f: data = 8'b00000000; //
//code x72
11'h720: data = 8'b00000000; //
11'h721: data = 8'b00000000; //
11'h722: data = 8'b00000000; //
11'h723: data = 8'b00000000; //
11'h724: data = 8'b00000000; //
11'h725: data = 8'b11011100; // ** ***
11'h726: data = 8'b01110110; // *** **
11'h727: data = 8'b01100110; // ** **
11'h728: data = 8'b01100000; // **
11'h729: data = 8'b01100000; // **
11'h72a: data = 8'b01100000; // **
11'h72b: data = 8'b11110000; // ****
11'h72c: data = 8'b00000000; //
11'h72d: data = 8'b00000000; //
11'h72e: data = 8'b00000000; //
11'h72f: data = 8'b00000000; //
//code x73
11'h730: data = 8'b00000000; //
11'h731: data = 8'b00000000; //
11'h732: data = 8'b00000000; //
11'h733: data = 8'b00000000; //
11'h734: data = 8'b00000000; //
11'h735: data = 8'b01111100; // *****
11'h736: data = 8'b11000110; // ** **
11'h737: data = 8'b01100000; // **
11'h738: data = 8'b00111000; // ***
11'h739: data = 8'b00001100; // **
11'h73a: data = 8'b11000110; // ** **
11'h73b: data = 8'b01111100; // *****
11'h73c: data = 8'b00000000; //
11'h73d: data = 8'b00000000; //
11'h73e: data = 8'b00000000; //
11'h73f: data = 8'b00000000; //
//code x74
11'h740: data = 8'b00000000; //
11'h741: data = 8'b00000000; //
11'h742: data = 8'b00010000; // *
11'h743: data = 8'b00110000; // **
11'h744: data = 8'b00110000; // **
11'h745: data = 8'b11111100; // ******
11'h746: data = 8'b00110000; // **
11'h747: data = 8'b00110000; // **
11'h748: data = 8'b00110000; // **
11'h749: data = 8'b00110000; // **
11'h74a: data = 8'b00110110; // ** **
11'h74b: data = 8'b00011100; // ***
11'h74c: data = 8'b00000000; //
11'h74d: data = 8'b00000000; //
11'h74e: data = 8'b00000000; //
11'h74f: data = 8'b00000000; //
//code x75
11'h750: data = 8'b00000000; //
11'h751: data = 8'b00000000; //
11'h752: data = 8'b00000000; //
11'h753: data = 8'b00000000; //
11'h754: data = 8'b00000000; //
11'h755: data = 8'b11001100; // ** **
11'h756: data = 8'b11001100; // ** **
11'h757: data = 8'b11001100; // ** **
11'h758: data = 8'b11001100; // ** **
11'h759: data = 8'b11001100; // ** **
11'h75a: data = 8'b11001100; // ** **
11'h75b: data = 8'b01110110; // *** **
11'h75c: data = 8'b00000000; //
11'h75d: data = 8'b00000000; //
11'h75e: data = 8'b00000000; //
11'h75f: data = 8'b00000000; //
//code x76
11'h760: data = 8'b00000000; //
11'h761: data = 8'b00000000; //
11'h762: data = 8'b00000000; //
11'h763: data = 8'b00000000; //
11'h764: data = 8'b00000000; //
11'h765: data = 8'b11000011; // ** **
11'h766: data = 8'b11000011; // ** **
11'h767: data = 8'b11000011; // ** **
11'h768: data = 8'b11000011; // ** **
11'h769: data = 8'b01100110; // ** **
11'h76a: data = 8'b00111100; // ****
11'h7"b"6b: data = 8'b00011000; // **
11'h76c: data = 8'b00000000; //
11'h76d: data = 8'b00000000; //
11'h76e: data = 8'b00000000; //
11'h76f: data = 8'b00000000; //
//code x77
11'h770: data = 8'b00000000; //
11'h771: data = 8'b00000000; //
11'h772: data = 8'b00000000; //
11'h773: data = 8'b00000000; //
11'h774: data = 8'b00000000; //
11'h775: data = 8'b11000011; // ** **
11'h776: data = 8'b11000011; // ** **
11'h777: data = 8'b11000011; // ** **
11'h778: data = 8'b11011011; // ** ** **
11'h779: data = 8'b11011011; // ** ** **
11'h77a: data = 8'b11111111; // ********
11'h77b: data = 8'b01100110; // ** **
11'h77c: data = 8'b00000000; //
11'h77d: data = 8'b00000000; //
11'h77e: data = 8'b00000000; //
11'h77f: data = 8'b00000000; //
//code x78
11'h780: data = 8'b00000000; //
11'h781: data = 8'b00000000; //
11'h782: data = 8'b00000000; //
11'h783: data = 8'b00000000; //
11'h784: data = 8'b00000000; //
11'h785: data = 8'b11000011; // ** **
11'h786: data = 8'b01100110; // ** **
11'h787: data = 8'b00111100; // ****
11'h788: data = 8'b00011000; // **
11'h789: data = 8'b00111100; // ****
11'h78a: data = 8'b01100110; // ** **
11'h78b: data = 8'b11000011; // ** **
11'h78c: data = 8'b00000000; //
11'h78d: data = 8'b00000000; //
11'h78e: data = 8'b00000000; //
11'h78f: data = 8'b00000000; //
//code x79
11'h790: data = 8'b00000000; //
11'h791: data = 8'b00000000; //
11'h792: data = 8'b00000000; //
11'h793: data = 8'b00000000; //
11'h794: data = 8'b00000000; //
11'h795: data = 8'b11000110; // ** **
11'h796: data = 8'b11000110; // ** **
11'h797: data = 8'b11000110; // ** **
11'h798: data = 8'b11000110; // ** **
11'h799: data = 8'b11000110; // ** **
11'h79a: data = 8'b11000110; // ** **
11'h79b: data = 8'b01111110; // ******
11'h79c: data = 8'b00000110; // **
11'h79d: data = 8'b00001100; // **
11'h79e: data = 8'b11111000; // *****
11'h79f: data = 8'b00000000; //
//code x7a
11'h7a0: data = 8'b00000000; //
11'h7a1: data = 8'b00000000; //
11'h7a2: data = 8'b00000000; //
11'h7a3: data = 8'b00000000; //
11'h7a4: data = 8'b00000000; //
11'h7a5: data = 8'b11111110; // *******
11'h7a6: data = 8'b11001100; // ** **
11'h7a7: data = 8'b00011000; // **
11'h7a8: data = 8'b00110000; // **
11'h7a9: data = 8'b01100000; // **
11'h7aa: data = 8'b11000110; // ** **
11'h7ab: data = 8'b11111110; // *******
11'h7ac: data = 8'b00000000; //
11'h7ad: data = 8'b00000000; //
11'h7ae: data = 8'b00000000; //
11'h7af: data = 8'b00000000; //
//code x7b
11'h7b0: data = 8'b00000000; //
11'h7b1: data = 8'b00000000; //
11'h7b2: data = 8'b00001110; // ***
11'h7b3: data = 8'b00011000; // **
11'h7b4: data = 8'b00011000; // **
11'h7b5: data = 8'b00011000; // **
11'h7b6: data = 8'b01110000; // ***
11'h7b7: data = 8'b00011000; // **
11'h7b8: data = 8'b00011000; // **
11'h7b9: data = 8'b00011000; // **
11'h7ba: data = 8'b00011000; // **
11'h7bb: data = 8'b00001110; // ***
11'h7bc: data = 8'b00000000; //
11'h7bd: data = 8'b00000000; //
11'h7be: data = 8'b00000000; //
11'h7bf: data = 8'b00000000; //
//code x7c
11'h7c0: data = 8'b00000000; //
11'h7c1: data = 8'b00000000; //
11'h7c2: data = 8'b00011000; // **
11'h7c3: data = 8'b00011000; // **
11'h7c4: data = 8'b00011000; // **
11'h7c5: data = 8'b00011000; // **
11'h7c6: data = 8'b00000000; //
11'h7c7: data = 8'b00011000; // **
11'h7c8: data = 8'b00011000; // **
11'h7c9: data = 8'b00011000; // **
11'h7ca: data = 8'b00011000; // **
11'h7cb: data = 8'b00011000; // **
11'h7cc: data = 8'b00000000; //
11'h7cd: data = 8'b00000000; //
11'h7ce: data = 8'b00000000; //
11'h7cf: data = 8'b00000000; //
//code x7d
11'h7d0: data = 8'b00000000; //
11'h7d1: data = 8'b00000000; //
11'h7d2: data = 8'b01110000; // ***
11'h7d3: data = 8'b00011000; // **
11'h7d4: data = 8'b00011000; // **
11'h7d5: data = 8'b00011000; // **
11'h7d6: data = 8'b00001110; // ***
11'h7d7: data = 8'b00011000; // **
11'h7d8: data = 8'b00011000; // **
11'h7d9: data = 8'b00011000; // **
11'h7da: data = 8'b00011000; // **
11'h7db: data = 8'b01110000; // ***
11'h7dc: data = 8'b00000000; //
11'h7dd: data = 8'b00000000; //
11'h7de: data = 8'b00000000; //
11'h7df: data = 8'b00000000; //
//code x7e
11'h7e0: data = 8'b00000000; //
11'h7e1: data = 8'b00000000; //
11'h7e2: data = 8'b01110110; // *** **
11'h7e3: data = 8'b11011100; // ** ***
11'h7e4: data = 8'b00000000; //
11'h7e5: data = 8'b00000000; //
11'h7e6: data = 8'b00000000; //
11'h7e7: data = 8'b00000000; //
11'h7e8: data = 8'b00000000; //
11'h7e9: data = 8'b00000000; //
11'h7ea: data = 8'b00000000; //
11'h7eb: data = 8'b00000000; //
11'h7ec: data = 8'b00000000; //
11'h7ed: data = 8'b00000000; //
11'h7ee: data = 8'b00000000; //
11'h7ef: data = 8'b00000000; //
//code x7f
11'h7f0: data = 8'b00000000; //
11'h7f1: data = 8'b00000000; //
11'h7f2: data = 8'b00000000; //
11'h7f3: data = 8'b00000000; //
11'h7f4: data = 8'b00010000; // *
11'h7f5: data = 8'b00111000; // ***
11'h7f6: data = 8'b01101100; // ** **
11'h7f7: data = 8'b11000110; // ** **
11'h7f8: data = 8'b11000110; // ** **
11'h7f9: data = 8'b11000110; // ** **
11'h7fa: data = 8'b11111110; // *******
11'h7fb: data = 8'b00000000; //
11'h7fc: data = 8'b00000000; //
11'h7fd: data = 8'b00000000; //
11'h7fe: data = 8'b00000000; //
11'h7ff: data = 8'b00000000; // \t
endcase
\t
endmodule
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|
// Listing 14.4\r
module text_screen_gen\r
(\r
input wire clk, reset,
\t input wire caps_on,
\t input wire [2:0] color_selector,
\t input wire [1:0] size_selector,\r
input wire [9:0] pixel_x, pixel_y,
\t input wire window_selector,\r
output reg [2:0] text_rgb,
\t output wire text_on\r
);\r
\r
// signal declaration\r
// font ROM\r
wire [10:0] rom_addr;\r
reg [6:0] char_addr;\r
reg [3:0] row_addr;\r
reg [2:0] bit_addr;\r
wire [7:0] font_word;\r
wire font_bit;\r
\t//labels, text editor window
\twire open_label_on, save_label_on, exit_label_on, caps_label_on, color_label_on, size_label_on, center_label_on;
\twire [2:0] bit_addr_open_label, bit_addr_save_label,bit_addr_exit_label,bit_addr_center_label;
\twire [2:0] bit_addr_caps_label, bit_addr_color_label, bit_addr_size_label;
wire [3:0] row_addr_open_label, row_addr_save_label, row_addr_exit_label, row_addr_center_label;
wire [3:0] row_addr_caps_label, row_addr_color_label, row_addr_size_label;
\treg [6:0] char_addr_open_label, char_addr_save_label,char_addr_exit_label, char_addr_center_label;
\treg [6:0] char_addr_caps_label, char_addr_color_label, char_addr_size_label;
\t
\t//labels, init dialog
\t\r
\twire new_label_on, open_label_on_1, center_label_1_on;
\twire [2:0] bit_addr_open_1_label, bit_addr_new_label, bit_addr_center_1_label;
\twire [3:0] row_addr_open_1_label, row_addr_new_label, row_addr_center_1_label;
\treg [6:0] char_addr_open_1_label, char_addr_center_1_label, char_addr_new_label;
\t
\t
\t// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));\r
\r
\r
\tassign open_label_on = (pixel_y[9:4]==2) && (pixel_x[9:3]<=6 &&(pixel_x[9:3]>=4));
assign row_addr_open_label = pixel_y[4:0];
assign bit_addr_open_label = pixel_x[3:0];
always @*
case (pixel_x[6:3])
4'd4: char_addr_open_label = 7'h4e; // N
4'd5: char_addr_open_label = 7'h65; // e
4'd6: char_addr_open_label = 7'h77; // w
endcase
\t\t
\tassign save_label_on = (pixel_y[9:4]==2) && (pixel_x[9:3]<=15 &&(pixel_x[9:3]>=12));
assign row_addr_save_label = pixel_y[4:0];
assign bit_addr_save_label = pixel_x[3:0];
always @*
case (pixel_x[6:3])
4'd12: char_addr_save_label = 7'h53; // S
4'd13: char_addr_save_label = 7'h61; // a
4'd14: char_addr_save_label = 7'h76; // v
\t\t\t4'd15: char_addr_save_label = 7'h65;// e
\t\t\t
endcase
\t\t
\tassign exit_label_on = (pixel_y[9:4]==2) && (pixel_x[9:3]<=23 &&(pixel_x[9:3]>=20));
assign row_addr_exit_label = pixel_y[4:0];
assign bit_addr_exit_label = pixel_x[3:0];
always @*
case (pixel_x[6:3])
4'd20: char_addr_exit_label = 7'h45; // E
4'd21: char_addr_exit_label = 7'h78; // x
4'd22: char_addr_exit_label = 7'h69; // i
\t\t\t4'd23: char_addr_exit_label = 7'h74;// t
\t\t\t
endcase
\t
\tassign center_label_on = (pixel_y[9:5]==1) && (pixel_x[9:4]<=23 &&(pixel_x[9:4]>=15));
assign row_addr_center_label = pixel_y[4:1];
assign bit_addr_center_label = pixel_x[4:1];
always @*
case (pixel_x[7:4])
4'd15: char_addr_center_label = 7'h44; // D
4'd16: char_addr_center_label = 7'h45; // E
4'd17: char_addr_center_label = 7'h4d; // M
\t\t\t4'd18: char_addr_center_label = 7'h4f;// O
\t\t\t4'd19: char_addr_center_label = 7'h20; //
4'd20: char_addr_center_label = 7'h57; // W
4'd21: char_addr_center_label = 7'h4f; // O
\t\t\t4'd22: char_addr_center_label = 7'h52;// R
\t\t\t4'd23: char_addr_center_label = 7'h44;// D
\t\t\t
endcase
\t
\tassign caps_label_on = (pixel_y[9:4]==2) && (pixel_x[9:3]<=57 &&(pixel_x[9:3]>=56));
assign row_addr_caps_label = pixel_y[4:0];
assign bit_addr_caps_label = pixel_x[3:0];
always @*
case (pixel_x[6:3])
4'd56:
\t\t\t\tbegin
\t\t\t\tif (caps_on)
\t\t\t\t\tchar_addr_caps_label = 7'h41; // A
\t\t\t\telse if (!caps_on)
\t\t\t\t\tchar_addr_caps_label = 7'h61; // a
\t\t\t\tend
4'd57:
\t\t\t\tbegin
\t\t\t\tif (caps_on)
\t\t\t\t\tchar_addr_caps_label = 7'h61; // a
\t\t\t\telse if (!caps_on)
\t\t\t\t\tchar_addr_caps_label = 7'h41; // A
\t\t\t\tend
endcase
\t\t
\tassign color_label_on = (pixel_y[9:4]==2) && (pixel_x[9:3]<=68 &&(pixel_x[9:3]>=64));
assign row_addr_color_label = pixel_y[4:0];
assign bit_addr_color_label = pixel_x[3:0];
always @*
case (pixel_x[6:3])
4'd64: char_addr_color_label = 7'h43; // C
4'd65: char_addr_color_label = 7'h6f; // o
4'd66: char_addr_color_label = 7'h6c; // l
\t\t\t4'd67: char_addr_color_label = 7'h6f;// o
\t\t\t4'd68: char_addr_color_label = 7'h72;// r
\t\t\t
endcase
\t\t
\tassign size_label_on = (pixel_y[9:4]==2) && (pixel_x[9:3]<=78 &&(pixel_x[9:3]>=71));
assign row_addr_size_label = pixel_y[4:0];
assign bit_addr_size_label = pixel_x[3:0];
always @*
case (pixel_x[6:3])
4'd71: char_addr_size_label = 7'h53; // S
4'd72: char_addr_size_label = 7'h69; // i
4'd73: char_addr_size_label = 7'h7a; // z
\t\t\t4'd74: char_addr_size_label = 7'h65;// e
\t\t\t4'd75: char_addr_size_label = 7'h3a; // :
4'd76: char_addr_size_label = 7'h20; //
\t\t\t4'd77: char_addr_size_label = 7'h31; // 1
\t\t\t4'd78:
\t\t\t\tbegin
\t\t\t\t\tif(size_selector==10'd1)
\t\t\t\t\t\tchar_addr_size_label = 7'h30; // 0
\t\t\t\t\telse if (size_selector==10'd2)
\t\t\t\t\t\tchar_addr_size_label = 7'h32;// 2
\t\t\t\t\telse if(size_selector==10'd3)
\t\t\t\t\t\tchar_addr_size_label = 7'h34;// 4
\t\t\t\tend\t\t\t
endcase
\tassign center_1_label_on = (pixel_y[9:5]==4) && (pixel_x[9:4]<=23 &&(pixel_x[9:4]>=15));
assign row_addr_center_1_label = pixel_y[4:1];
assign bit_addr_center_1_label = pixel_x[4:1];
always @*
case (pixel_x[7:4])
4'd15: char_addr_center_1_label = 7'h44; // D
4'd16: char_addr_center_1_label = 7'h45; // E
4'd17: char_addr_center_1_label = 7'h4d; // M
\t\t\t4'd18: char_addr_center_1_label = 7'h4f;// O
\t\t\t4'd19: char_addr_center_1_label = 7'h20; //
4'd20: char_addr_center_1_label = 7'h57; // W
4'd21: char_addr_center_1_label = 7'h4f; // O
\t\t\t4'd22: char_addr_center_1_label = 7'h52;// R
\t\t\t4'd23: char_addr_center_1_label = 7'h44;// D
\t\t\t
endcase
\t\t
\t\t
\tassign new_label_on = (pixel_y[9:4]==15) && (pixel_x[9:3]<=26 &&(pixel_x[9:3]>=24));
assign row_addr_new_label = pixel_y[4:0];
assign bit_addr_new_label = pixel_x[3:0];
always @*
case (pixel_x[6:3])
4'd24: char_addr_new_label = 7'h4e; // N
4'd25: char_addr_new_label = 7'h65; // e
4'd26: char_addr_new_label = 7'h77; // w
endcase
\t\t
\tassign open_1_label_on = (pixel_y[9:4]==10) && (pixel_x[9:3]<=27 &&(pixel_x[9:3]>=24));
assign row_addr_open_1_label = pixel_y[4:0];
assign bit_addr_open_1_label = pixel_x[3:0];
always @*
case (pixel_x[6:3])
4'd24: char_addr_open_1_label = 7'h4f; // O
4'd25: char_addr_open_1_label = 7'h70; // p
4'd26: char_addr_open_1_label = 7'h65; // e
\t\t\t4'd27: char_addr_open_1_label = 7'h6e; // n
endcase
//-------------------------------------------
// mux for font ROM addresses and rgb
//-------------------------------------------
always @*
begin
text_rgb = 3'b111; // background, white
\t\tif(window_selector) begin
\t\t\tif (open_label_on)
\t\t\t\tbegin
\t\t\t\t\tchar_addr = char_addr_open_label;
\t\t\t\t\trow_addr = row_addr_open_label;
\t\t\t\t\tbit_addr = bit_addr_open_label;
\t\t\t\t\tif (font_bit)
\t\t\t\t\t\ttext_rgb = 3'b000;
\t\t\t\tend
\t\t\telse if (save_label_on)
\t\t\t\tbegin
\t\t\t\t\tchar_addr = char_addr_save_label;
\t\t\t\t\trow_addr = row_addr_save_label;
\t\t\t\t\tbit_addr = bit_addr_save_label;
\t\t\t\t\tif (font_bit)
\t\t\t\t\t\ttext_rgb = 3'b000;
\t\t\t\tend
\t\t\telse if (exit_label_on)
\t\t\t\tbegin
\t\t\t\t\tchar_addr = char_addr_exit_label;
\t\t\t\t\trow_addr = row_addr_exit_label;
\t\t\t\t\tbit_addr = bit_addr_exit_label;
\t\t\t\t\tif (font_bit)
\t\t\t\t\t\ttext_rgb = 3'b000;
\t\t\t\tend
\t\t\telse if (center_label_on)
\t\t\t\tbegin
\t\t\t\t\tchar_addr = char_addr_center_label;
\t\t\t\t\trow_addr = row_addr_center_label;
\t\t\t\t\tbit_addr = bit_addr_center_label;
\t\t\t\t\tif (font_bit)
\t\t\t\t\t\ttext_rgb = 3'b000;
\t\t\t\tend
\t\t\telse if (caps_label_on)
\t\t\t\tbegin
\t\t\t\t\tchar_addr = char_addr_caps_label;
\t\t\t\t\trow_addr = row_addr_caps_label;
\t\t\t\t\tbit_addr = bit_addr_caps_label;
\t\t\t\t\tif (font_bit)
\t\t\t\t\t\ttext_rgb = 3'b000;
\t\t\t\tend
\t\t\telse if (color_label_on)
\t\t\t\tbegin
\t\t\t\t\tchar_addr = char_addr_color_label;
\t\t\t\t\trow_addr = row_addr_color_label;
\t\t\t\t\tbit_addr = bit_addr_color_label;
\t\t\t\t\tif (font_bit)
\t\t\t\t\t\ttext_rgb = color_selector;
\t\t\t\tend
\t\t\telse if (size_label_on)
\t\t\t\tbegin
\t\t\t\t\tchar_addr = char_addr_size_label;
\t\t\t\t\trow_addr = row_addr_size_label;
\t\t\t\t\tbit_addr = bit_addr_size_label;
\t\t\t\t\tif (font_bit)
\t\t\t\t\t\ttext_rgb = 3'b000;
\t\t\t\tend
\t\tend
\t\telse if (!window_selector) begin
\t\t\tif (open_1_label_on)
\t\t\t\t\tbegin
\t\t\t\t\t\tchar_addr = char_addr_open_1_label;
\t\t\t\t\t\trow_addr = row_addr_open_1_label;
\t\t\t\t\t\tbit_addr = bit_addr_open_1_label;
\t\t\t\t\t\tif (font_bit)
\t\t\t\t\t\t\ttext_rgb = 3'b000;
\t\t\t\t\tend
\t\t\telse if (new_label_on)
\t\t\t\t\tbegin
\t\t\t\t\t\tchar_addr = char_addr_new_label;
\t\t\t\t\t\trow_addr = row_addr_new_label;
\t\t\t\t\t\tbit_addr = bit_addr_new_label;
\t\t\t\t\t\tif (font_bit)
\t\t\t\t\t\t\ttext_rgb = 3'b000;
\t\t\t\t\tend
\t\t\telse if (center_1_label_on)
\t\t\t\t\tbegin
\t\t\t\t\t\tchar_addr = char_addr_center_1_label;
\t\t\t\t\t\trow_addr = row_addr_center_1_label;
\t\t\t\t\t\tbit_addr = bit_addr_center_1_label;
\t\t\t\t\t\tif (font_bit)
\t\t\t\t\t\t\ttext_rgb = 3'b000;
\t\t\t\t\tend
\t\tend
\tend
\t
\t assign text_on = ((open_label_on||save_label_on||exit_label_on||center_label_on||caps_label_on||color_label_on||size_label_on) && window_selector) ||
\t ((open_1_label_on||new_label_on||center_1_label_on)&& !window_selector);
//-------------------------------------------
// font rom interface
//-------------------------------------------
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];\r
endmodule\r
\r
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
\tinput [31:0] x, y, z;
\toutput [31:0] o;
\tassign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
\tinput [31:0] x, y, z;
\toutput [31:0] o;
\tassign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y[31:29] = x[6:4] ^ x[17:15];
\tassign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y[31:22] = x[16:7] ^ x[18:9];
\tassign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
\tinput [31:0] x, y, z;
\toutput [31:0] o;
\tassign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
\tinput [31:0] x, y, z;
\toutput [31:0] o;
\tassign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y[31:29] = x[6:4] ^ x[17:15];
\tassign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
\tinput [31:0] x;
\toutput [31:0] y;
\tassign y[31:22] = x[16:7] ^ x[18:9];
\tassign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
LIBAVCODEC_$MAJOR {
global: av*;
audio_resample;
audio_resample_close;
#deprecated, remove after next bump
img_get_alpha_info;
dsputil_init;
ff_find_pix_fmt;
ff_framenum_to_drop_timecode;
ff_framenum_to_smtpe_timecode;
ff_raw_pix_fmt_tags;
ff_init_smtpe_timecode;
ff_fft*;
ff_mdct*;
ff_dct*;
ff_rdft*;
ff_prores_idct_put_10_sse2;
ff_simple_idct*;
ff_aanscales;
ff_faan*;
ff_mmx_idct;
ff_fdct*;
fdct_ifast;
j_rev_dct;
ff_mmxext_idct;
ff_idct_xvid*;
ff_jpeg_fdct*;
#XBMC's configure checks for ff_vdpau_vc1_decode_picture()
ff_vdpau_vc1_decode_picture;
local: *;
};
|
LIBPOSTPROC_$MAJOR {
global: postproc_*; pp_*;
local: *;
};
|
LIBAVFORMAT_$MAJOR {
global: av*;
#FIXME those are for ffserver
ff_inet_aton;
ff_socket_nonblock;
ffm_set_write_index;
ffm_read_write_index;
ffm_write_write_index;
ff_rtsp_parse_line;
ff_rtp_get_local_rtp_port;
ff_rtp_get_local_rtcp_port;
ffio_open_dyn_packet_buf;
ffio_set_buf_size;
ffurl_close;
ffurl_open;
ffurl_read_complete;
ffurl_seek;
ffurl_size;
ffurl_write;
url_open;
url_close;
url_write;
url_get_max_packet_size;
#those are deprecated, remove on next bump
find_info_tag;
parse_date;
dump_format;
url_*;
ff_timefilter_destroy;
ff_timefilter_new;
ff_timefilter_update;
ff_timefilter_reset;
get_*;
put_*;
udp_set_remote_url;
udp_get_local_port;
init_checksum;
init_put_byte;
local: *;
};
|
LIBAVRESAMPLE_$MAJOR {
global: av*;
local: *;
};
|
LIBAVDEVICE_$MAJOR {
global: avdevice_*;
local: *;
};
|
LIBAVFILTER_$MAJOR {
global: avfilter_*; av_*;
ff_default_query_formats;
local: *;
};
|
LIBSWRESAMPLE_$MAJOR {
global: swr_*; ff_*; swresample_*;
local: *;
};
|
LIBAVUTIL_$MAJOR {
global: av_*; ff_*; avutil_*;
local: *;
};
|
LIBSWSCALE_$MAJOR {
global: swscale_*; sws_*; ff_*;
local: *;
};
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* VC router
*
*/
\r
`include "types.v"\r
//`include "parameters.v"\r
\r
typedef flit_pri_t flit_priority_t;\r
module NW_vc_router (i_flit_in, i_flit_out,
\t\t i_cntrl_in, i_cntrl_out,
\t\t i_input_full_flag,
\t\t clk, rst_n);
`include "NW_functions.v"
//parameter type flit_priority_t = flit_pri_t;
parameter network_x = 4;
parameter network_y = 4;
parameter buf_len = 4;
parameter NP=5;
parameter NV=2;
// numbers of virtual-channels on entry/exit to network?
parameter router_num_vcs_on_entry = 1;
parameter router_num_vcs_on_exit = 2; //4
//
// Pipeline VC and switch allocation?
//
parameter uarch_pipeline=0;
// with or without an explicit pipelining register?
// can just read from head of FIFO twice
parameter uarch_explicit_pipeline_register=0;
//
// Check VC buffer is full (at dest.) before making a switch request?
//
parameter uarch_full_vc_check_before_switch_request=0;
//
// Switch Allocation
//
// perform VC and switch allocation in parallel
parameter swalloc_speculative=0;
//
// VC Allocation
//
parameter vcalloc_unrestricted=1;
//
// VC Selection
//
parameter vcselect_bydestinationnode = 0;
parameter vcselect_leastfullbuffer = 0;
parameter vcselect_arbstateupdate = 0;
parameter vcselect_usepacketmask = 0;
parameter vcselect_onlywhenempty = 0;
//
// Prioritised Communications
//
// prioritise switch allocation by position of flit in packet (head=0, tail=N)
parameter priority_switch_alloc_byflitid=0;
// prioritise switch allocation based on flit.control.flit_priority
parameter priority_flit_dynamic_switch_alloc=0;
// prioritise vc allocation based on flit.control.flit_priority
parameter priority_flit_dynamic_vc_alloc=0;
// size of flit.control.flit_priority field (in bits)
parameter priority_flit_bits=4;
//
// prioritise_network_traffic = 0 - no modifications to flit_priority are made by the router
// prioritise_network_traffic = 1 - router sets flit_priority to 1 on exit, traffic in network has
// priority over newly injected traffic
// prioritise_network_traffic = 2 - flit_priority is increased at each router as the flit exists
// flit_priority is determined by its current hop count
// (be careful to ensure enough priority bits are available)
// Upto a limit of \'priority_flit_limit\'
parameter priority_network_traffic=0;
parameter priority_flit_limit=4;
//==================================================================
// FIFO rec. data from tile/core is full?
output [router_num_vcs_on_entry-1:0] i_input_full_flag;
// link data and control
input flit_t i_flit_in [NP-1:0];
output flit_t i_flit_out [NP-1:0];
input chan_cntrl_t i_cntrl_in [NP-1:0];
output chan_cntrl_t i_cntrl_out [NP-1:0];
input clk, rst_n;
// Credit count for each VC at each output port
logic [NP-1:0][NV-1:0][clogb2(buf_len+1)-1:0] vc_credits;
flit_priority_t req_priority [NP-1:0][NV-1:0];
logic [NP-1:0] output_valid_flit_check;
logic [NP-1:0][NV-1:0] pop_vc_valid_check;
logic [NP-1:0] free_vc_blocked;
logic [NP-1:0] no_free_vc;
logic [NP-1:0][NV-1:0] switch_req, spec_switch_req;
// vc_t x_vc_status [NP-1:0];
logic [NP-1:0][NV-1:0] x_vc_status;
logic [NP-1:0] \t x_push;
logic [NP-1:0][NV-1:0] x_pop;
flit_t x_flit_xbarin[NP-1:0];
flit_t x_flit_xbarin_pipe[NP-1:0];
flit_t x_flit_xbarout[NP-1:0];
// logic [clogb2(NV)-1:0] x_vc_id [NP-1:0];
// logic [clogb2(NV)-1:0] x_select [NP-1:0];
vc_index_t x_vc_id [NP-1:0];
vc_index_t x_select [NP-1:0];
flit_t x_flit_bufout [NP-1:0];
flit_t x_data_in_reg [NP-1:0];
fifov_flags_t x_flags [NP-1:0][NV-1:0];
logic [NV-1:0] \t x_allocated_vc [NP-1:0][NV-1:0];
logic [NV-1:0] \t vc_for_blocked_check [NP-1:0][NV-1:0];
logic [NP-1:0][NV-1:0] x_allocated_vc_valid;
logic [NP-1:0][NV-1:0][NV-1:0] x_vc_new;
logic [NP-1:0][NV-1:0] \t x_vc_new_valid;
output_port_t x_output_port [NP-1:0][NV-1:0];
output_port_t x_output_port_for_vc [NP-1:0][NV-1:0];
output_port_t x_output_port_for_sw [NP-1:0][NV-1:0];
vc_t [NP-1:0] x_free_vc;
logic [NP-1:0][NP-1:0] xbar_select;
logic [NP-1:0][NV-1:0] vc_request; // VC request from each input VC
logic [NP-1:0] \t vc_allocated_at_output; // for each output port, has a VC been allocated?
logic [NP-1:0][NV-1:0] allocated_vc_blocked, check_full_vc;
logic [NP-1:0][NV-1:0] switch_grant;
// logic [`PV-1:0] \t input_vc_mux_sel;
logic [NP-1:0][NV-1:0] input_vc_mux_sel;
logic [NP-1:0] \t output_used; // output channel used on this cycle?
logic [NP-1:0] \t outgoing_blocked, output_requested;
// logic [`PV-1:0] \t blocked;
// logic [NP-1:0][NV-1:0] blocked;
\t
logic [NP-1:0][NV-1:0] pipereg_ready, pipereg_valid, pipereg_push, pipereg_pop;
flit_t pipereg_data_in [NP-1:0][NV-1:0];\r
flit_t pipereg_data_out [NP-1:0][NV-1:0];
flit_t routed_flit_buffer_out [NP-1:0][NV-1:0];\r
flit_t flit_buffer_out [NP-1:0][NV-1:0];
//
// unrestricted VC free pool/allocation
//
logic [NP-1:0][NV-1:0] vc_alloc_status; // which output VCs are free to be allocated
logic [NP-1:0][NV-1:0] vc_allocated; // indicates which VCs were allocated on this clock cycle
logic [NP-1:0][NV-1:0][NV-1:0] vc_requested; // which VCs were selected to be requested at each input VC?
//
logic [NP-1:0][NV-1:0] \t vc_empty; // is downstream FIFO associated with VC empty?
genvar \t\t i,j,k;
integer db_out_used, db_in_popped, p,v;
// quick parameter sanity check
// synopsys translate_off
always@(negedge rst_n) begin
if (swalloc_speculative) begin
\t assert (!uarch_pipeline) else begin
\t $error("*** Speculative switch allocation cannot be applied to pipelined designs ***");
\t $finish;
\t end
\t assert (!uarch_explicit_pipeline_register) else begin
\t $error("*** Speculative switch allocation cannot be applied to pipelined designs ***");
\t $finish;
\t end
end
if (uarch_explicit_pipeline_register) begin
\t assert (uarch_pipeline) else begin
\t $error("*** Pipelining registers can only be added if the \'(uarch_)pipeline\' parameter is set ***");
\t $finish;
\t end
end
end
// synopsys translate_on
// **************************************
// map new interface to old interface
// **************************************
generate
for (i=0; i<NP; i++) begin:map
//\t assign nearly_full_in [(i+1)*NV-1:i*NV] = i_cntrl_in[i].nearly_full;
`ifdef NEARLY_FULL_FLOW_CONTROL
\t for (j=0; j<NV; j++) begin:nv
\t assign i_cntrl_out[i].nearly_full[j] = x_flags[i][j].nearly_full;
\t end
`endif\t
end
endgenerate
// *******************************************************************************
// output ports
// *******************************************************************************
generate
for (i=0; i<NP; i++) begin:output_ports
//
// Free VC pools
//
if (i==`TILE) begin
\t //
\t // may have less than a full complement of VCs on exit from network
\t //
\t NW_vc_free_pool #(.num_vcs_local(router_num_vcs_on_exit),
\t\t\t .num_vcs_global(NV),
\t\t\t .fifo_free_pool(!vcalloc_unrestricted),
\t\t\t .only_allocate_vc_when_empty(vcselect_onlywhenempty)) vcfreepool
\t (.flit(x_flit_xbarout[i]),
\t .valid(output_used[i]),
\t // FIFO free pool
\t .oh_free_vc(x_free_vc[i]),
\t .no_free_vc(no_free_vc[i]),
\t .vc_consumed(vc_allocated_at_output[i]),
\t // Unrestricted free pool
\t .vc_alloc_status(vc_alloc_status[i]),
\t .vc_allocated(vc_allocated[i]),
\t .vc_empty(vc_empty[i]),
\t //
\t .clk, .rst_n);
end else begin
\t NW_vc_free_pool #(.num_vcs_local(NV),
\t\t\t .num_vcs_global(NV),
\t\t\t .fifo_free_pool(!vcalloc_unrestricted),
\t\t\t .only_allocate_vc_when_empty(vcselect_onlywhenempty)) vcfreepool
\t (.flit(x_flit_xbarout[i]),
\t .valid(output_used[i]),
\t // FIFO free pool
\t .oh_free_vc(x_free_vc[i]),
\t .no_free_vc(no_free_vc[i]),
\t .vc_consumed(vc_allocated_at_output[i]),
\t // Unrestricted free pool
\t .vc_alloc_status(vc_alloc_status[i]),
\t .vc_allocated(vc_allocated[i]),
\t .vc_empty(vc_empty[i]),
\t //
\t .clk, .rst_n);
end // else: !if(i==`TILE)
//
// Flow Control
//
NW_vc_fc_out #(.num_vcs(NV),
\t\t .init_credits(buf_len))
\tfcout (.flit(x_flit_xbarout[i]),
\t .flit_valid(output_used[i]),
\t .channel_cntrl_in(i_cntrl_in[i]),
\t .vc_status(x_vc_status[i]),
\t .vc_empty(vc_empty[i]),
\t .vc_credits(vc_credits[i]),
\t .clk, .rst_n);
// indicate to upstream router that new buffer is free when
// we remove flit from an input FIFO (credit-based flow-control)
`ifdef CREDIT_FLOW_CONTROL
always@(posedge clk) begin
\t if (!rst_n) begin
\t i_cntrl_out[i].credit_valid<=1\'b0;
\t end else begin
\t //
\t // ensure \'credit\' is registered before it is sent to the upstream router
\t //
\t if (uarch_explicit_pipeline_register) begin
\t //
\t // can only send one credit per cycle, so have to look at output of
\t // pipeline register and not FIFO->pipe-reg. transfers
\t //
\t i_cntrl_out[i].credit<=oh2bin(pipereg_pop[i]);
\t i_cntrl_out[i].credit_valid<=|pipereg_pop[i];
\t
\t end else begin
\t // send credit corresponding to flit sent from this input port
\t i_cntrl_out[i].credit<=x_select[i];
\t i_cntrl_out[i].credit_valid<=|x_pop[i];
\t end
\t end
end
`endif
// assign blocked[(i+1)*NV-1:i*NV]=x_vc_status[i];
// assign blocked[i]=x_vc_status[i];
if (!vcalloc_unrestricted) begin
\t assign free_vc_blocked[i]=|(x_vc_status[i] & x_free_vc[i]);
end
end
endgenerate
// *******************************************************************************
// input ports (vc buffers and VC registers)
// *******************************************************************************
generate
for (i=0; i<router_num_vcs_on_entry; i++) begin:vcsx
\t assign i_input_full_flag[i] = x_flags[`TILE][i].full; // TILE input FIFO[i] is full?
end
for (i=0; i<NP; i++) begin:input_ports
\t // should support .nv and .num_vcs (e.g. for tile input that may only
\t // support a single input VC)
\t
\t // input port \'i\'
\t NW_vc_input_port #(.num_vcs(NV),
\t\t\t .buffer_length(buf_len),
\t\t\t .pipelined_vc_switch_alloc(uarch_pipeline),
\t\t\t .explicit_pipe_registers(uarch_explicit_pipeline_register)) inport
\t (.push(x_push[i]),
\t .pop(x_pop[i]),
\t .data_in(i_flit_in[i]),
\t .vc_id(x_vc_id[i]),
\t .select(input_vc_mux_sel[i]), // use one-hot
//\t .select(x_select[i]),
\t .data_out(x_flit_xbarin[i]),
\t //\t .output_port(x_output_port[i]),
\t .data_in_reg(x_data_in_reg[i]),
\t .flags(x_flags[i]),
\t //\t .buf_finished_empty(x_buf_finished_empty[i]),
\t .allocated_vc(x_allocated_vc[i]),
\t .allocated_vc_valid(x_allocated_vc_valid[i]),
\t .vc_new(x_vc_new[i]),
\t .vc_new_valid(x_vc_new_valid[i]),
\t //\t .head_is_tail(head_is_tail[i]),
\t .flit_buffer_out(flit_buffer_out[i]),
\t .clk, .rst_n);
//
// output port fields and flit priorities
// flit priorities come from flit.control.flit_priority (if required)
//
for (j=0; j<NV; j++) begin:allvcs2
\t assign x_output_port_for_vc[i][j] = flit_buffer_out[i][j].control.output_port;
\t //
\t // Explicit Pipelining Register
\t //
\t if (uarch_explicit_pipeline_register) begin
\t assign x_output_port_for_sw[i][j] = pipereg_data_out[i][j].control.output_port;
\t end else begin
\t assign x_output_port_for_sw[i][j] = flit_buffer_out[i][j].control.output_port;
\t end
end
// *** DATA IN *** //
assign x_push[i]=i_flit_in[i].control.valid;
// cast result of oh2bin to type of x_vc_id[i]
assign x_vc_id[i]= vc_index_t\'(oh2bin(i_flit_in[i].control.vc_id));
// *** DATA OUT *** //
// was selected VC at input port \'i\' granted access to crossbar?
// If we have performed speculative switch allocation we need
// to check flit received VC before removing it from the input FIFO.
for (j=0; j<NV; j++) begin:allvcs3
\t if (swalloc_speculative) begin
\t assign pop_vc_valid_check[i][j] = (x_allocated_vc_valid[i][j] || x_vc_new_valid[i][j]);
\t end else begin
\t assign pop_vc_valid_check[i][j] = 1\'b1;
\t end
end
if (uarch_explicit_pipeline_register) begin
\t // remove from FIFO when copied to pipelining register
\t assign x_pop[i]= pipereg_push[i];
end else begin
\t if (uarch_full_vc_check_before_switch_request) begin
\t // VC blocked check already made before request
\t assign x_pop[i] = switch_grant[i] & pop_vc_valid_check[i];
\t end else begin
\t // need to check VC isn\'t blocked
\t assign x_pop[i]= switch_grant[i] & ~allocated_vc_blocked[i] & pop_vc_valid_check[i];
\t end
end
// convert one-hot select at input port \'i\' to binary for vc_input_port
// assign x_select[i]= vc_index_t\'(oh2bin(input_vc_mux_sel[(i+1)*NV-1:i*NV]));
assign \t x_select[i]= vc_index_t\'(oh2bin(input_vc_mux_sel[i]));
/**************************************************************************/
//
// add explicit pipelining register if requested.
//
// pipelining register after VC allocation stage. Switch requests
// are in this case received from this register.
//
if (uarch_explicit_pipeline_register) begin
\t
\t for (j=0; j<NV; j++) begin:allvcs
\t //
\t // push - * pipe register ready to receive
\t // * VC FIFO has a flit
\t // * flit has been allocated a VC (previously or on this cycle)
\t //
\t assign pipereg_push[i][j] = pipereg_ready[i][j] && !x_flags[i][j].empty &&
\t\t\t\t\t(x_allocated_vc_valid[i][j] || x_vc_new_valid[i][j]);
\t //
\t // pop
\t //
\t if (uarch_full_vc_check_before_switch_request)
\t\t assign pipereg_pop[i][j] = switch_grant[i][j];
\t else
\t\t assign pipereg_pop[i][j] = switch_grant[i][j] && ~allocated_vc_blocked[i][j];
\t //
\t // data_in
\t //
\t always_comb
\t begin
\t\t //
\t\t // flit that is stored in pipelining register always has a valid VC
\t\t //
\t\t pipereg_data_in[i][j] = flit_buffer_out[i][j];
\t\t pipereg_data_in[i][j].control.vc_id = x_allocated_vc[i][j];
\t end
\t
\t NW_pipereg pipe_reg1
\t (.push(pipereg_push[i][j]),
\t .pop(pipereg_pop[i][j]),
\t .data_in(pipereg_data_in[i][j]),
\t .data_out(pipereg_data_out[i][j]),
\t .ready(pipereg_ready[i][j]),
\t .valid(pipereg_valid[i][j]),
\t .clk, .rst_n);
\t end
\t
end
/**************************************************************************/
//
// Switch and Virtual-Channel allocation requests
//
for (j=0; j<NV; j++) begin:reqs
\t //
\t // VIRTUAL-CHANNEL ALLOCATION REQUESTS
\t //
\t assign vc_request[i][j]= (NW_route_valid_input_vc(i,j)) ?
\t\t\t\t !x_flags[i][j].empty & !x_allocated_vc_valid[i][j] : 1\'b0;
\t
\t //
\t // SWITCH ALLOCATION REQUESTS
\t //
\t // Full VC buffer check. Perform check prior to making a switch request or
\t // later at output port. Schedule-quality/clock-cycle trade-off
\t if (uarch_full_vc_check_before_switch_request) begin
\t assign check_full_vc[i][j]=!allocated_vc_blocked[i][j];
\t end else begin
\t assign check_full_vc[i][j]=1\'b1; // check at end of cycle.
\t end
\t // Pipelined VC / Switch Alloc.
\t if (uarch_pipeline==1) begin
\t
\t if (uarch_explicit_pipeline_register) begin
\t
\t //
\t // switch req come from pipeline registers
\t // (as does output port info.)
\t //
\t assign switch_req[i][j] = (NW_route_valid_input_vc(i,j)) ?
\t\t\t\t\t pipereg_valid[i][j] &&
\t\t\t\t\t check_full_vc[i][j] : 1\'b0;
\t
\t assign vc_for_blocked_check[i][j] = pipereg_data_out[i][j].control.vc_id;
\t
\t end else begin
\t assign switch_req[i][j] = (NW_route_valid_input_vc(i,j)) ?
\t\t\t\t\t !x_flags[i][j].empty &&
\t\t\t\t\t x_allocated_vc_valid[i][j] &&
\t\t\t\t\t check_full_vc[i][j] : 1\'b0;
\t
\t assign vc_for_blocked_check[i][j] = x_allocated_vc[i][j];
\t end
\t
\t // is current VC blocked?
\t // - VC allocation happened in previous clock cycle so don\'t have to
\t // worry about new VCs. Just look at status of allocated VC.
\t unary_select_pair #(i, NP, NV) blocked_mux
\t (x_output_port_for_sw[i][j],
\t //\t x_allocated_vc[i][j],
\t vc_for_blocked_check[i][j],
//\t blocked,
\t x_vc_status,
\t allocated_vc_blocked[i][j]);
\t
\t end else begin
\t //
\t // ** Single Cycle **
\t //
\t if (!swalloc_speculative) begin
\t //
\t // Without speculative switch alloc.
\t //
\t // VC allocation takes place first. Need to check outcome
\t // of this VC allocation before making request (x_vc_new_valid)
\t //
\t assign switch_req[i][j] = (NW_route_valid_input_vc(i,j)) ?
\t\t\t\t\t !x_flags[i][j].empty &&
\t\t\t\t\t (x_allocated_vc_valid[i][j] || x_vc_new_valid[i][j]) &&
\t\t\t\t\t check_full_vc[i][j] : 1\'b0;
\t end else begin // if (!swalloc_speculative)
\t //
\t // With speculative switch allocation
\t // Only make non-speculative requests when VC has been allocated
\t // in previous clock cycle.
\t //
\t assign switch_req[i][j] = (NW_route_valid_input_vc(i,j)) ?
\t\t\t\t\t !x_flags[i][j].empty &&
\t\t\t\t\t x_allocated_vc_valid[i][j] &&
\t\t\t\t\t check_full_vc[i][j] : 1\'b0;
\t // If we are performing speculative switch allocation
\t // need to make speculative switch requests.
\t // (requests from flits without allocated output VCs)
\t assign spec_switch_req[i][j] = (NW_route_valid_input_vc(i,j)) ?
!x_flags[i][j].empty &&
\t\t\t\t\t !x_allocated_vc_valid[i][j] &&
check_full_vc[i][j] : 1\'b0;
\t end
\t end
end // block: reqs
end // block: input_ports
if (uarch_pipeline==0) begin
//
// if single-cycle we need to consider newly allocated
// virtual-channels too when determining if VCs are blocked
//
NW_vc_status #(.np(NP), .nv(NV)) vstat
\t(.output_port(x_output_port_for_sw),
.free_vc_blocked(free_vc_blocked),
\t .vc_requested(vc_requested),
.allocated_vc(x_allocated_vc),
.allocated_vc_valid(x_allocated_vc_valid),
// .vc_status(blocked),
\t .vc_status(x_vc_status),
.vc_blocked(allocated_vc_blocked));
end
endgenerate
// ----------------------------------------------------------------------
// virtual-channel allocation logic
// ----------------------------------------------------------------------
NW_vc_allocator #(.buf_len(buf_len), .np(NP), .nv(NV), .xs(network_x), .ys(network_y),
\t\t .dynamic_priority_vc_alloc( priority_flit_dynamic_vc_alloc),
\t\t .vcalloc_unrestricted(vcalloc_unrestricted),
\t\t .vcselect_bydestinationnode(vcselect_bydestinationnode),
\t\t .vcselect_leastfullbuffer(vcselect_leastfullbuffer),
\t\t .vcselect_arbstateupdate(vcselect_arbstateupdate),
\t\t .vcselect_usepacketmask(vcselect_usepacketmask))
vcalloc
(.req(vc_request),
\t.req_priority(req_priority),
\t.output_port(x_output_port_for_vc),
\t.vc_new(x_vc_new),
\t.vc_new_valid(x_vc_new_valid),
\t.next_free_vc(x_free_vc),
\t.no_free_vc(no_free_vc),
\t.pop_free_vc(vc_allocated_at_output),
\t// unrestricted VC pool
\t.vc_allocated(vc_allocated),
\t.vc_requested(vc_requested),
\t.vc_alloc_status(vc_alloc_status),
\t.flit(flit_buffer_out),
\t.vc_credits(vc_credits),
\t.clk, .rst_n);
// ----------------------------------------------------------------------
// switch-allocation logic (or speculative switch allocation)
// ----------------------------------------------------------------------
generate
if (!swalloc_speculative) begin
\t //
\t // for pipelined VC/switch allocation or switch allocation following
\t // VC allocation in single-cycle.
\t //
\t NW_vc_switch_allocator
\t #(.np(NP), .nv(NV),
\t .dynamic_priority_switch_alloc(priority_flit_dynamic_switch_alloc || priority_switch_alloc_byflitid)\r
\t //,
//.flit_priority_t(flit_priority_t)\r
)
\t swalloc
\t (.req(switch_req),
\t .req_priority(req_priority),
\t .output_port(x_output_port_for_sw),
\t .grant(switch_grant),
\t .vc_mux_sel(input_vc_mux_sel),
\t .xbar_select(xbar_select),
\t .any_request_for_output(output_requested),
\t .clk, .rst_n);
\t
end else begin // if (!swalloc_speculative)
\t
\t/* NW_speculative_switch_allocator
\t #(.np(NP), .nv(NV),
\t .dynamic_priority_switch_alloc(priority_flit_dynamic_switch_alloc)\r
\t //,
\t //.flit_priority_t(flit_priority_t)\r
\t )
\t specswitch
\t (.nonspec_req(switch_req),
\t .spec_req(spec_switch_req),
\t .req_priority(req_priority),
\t .output_port(x_output_port_for_sw),
\t .grant(switch_grant),
\t .vc_mux_sel(input_vc_mux_sel),
\t .xbar_select(xbar_select),
\t .any_request_for_output(output_requested),
\t .clk, .rst_n);*/
end // else: !if(!swalloc_speculative)
endgenerate
// ----------------------------------------------------------------------
// crossbar
// ----------------------------------------------------------------------
generate
if (uarch_explicit_pipeline_register) begin
\t //
\t // crossbar inputs come from mux fed by pipelining registers
\t //
\t for (i=0; i<NP; i++) begin:allinps
\t NW_route rfn (.flit_in(pipereg_data_out[i][x_select[i]]),
\t\t\t .flit_out(x_flit_xbarin_pipe[i]), .clk, .rst_n);
\t
\t end
\t
\t NW_crossbar_oh_select #( .n(NP)) myxbar
\t (x_flit_xbarin_pipe, xbar_select, x_flit_xbarout);
\t
end else begin
\t //
\t // crossbar inputs from VC input ports
\t //
\t NW_crossbar_oh_select #( .n(NP)) myxbar
\t (x_flit_xbarin, xbar_select, x_flit_xbarout);
end
endgenerate
// ----------------------------------------------------------------------
// output port logic
// ----------------------------------------------------------------------
generate
for (i=0; i<NP; i++) begin:outports
if (swalloc_speculative) begin
\t // need to check flit at output has valid output VC
\t assign output_valid_flit_check[i] = |(x_flit_xbarout[i].control.vc_id);
end else begin
\t assign output_valid_flit_check[i] = 1\'b1;
end
if (uarch_full_vc_check_before_switch_request) begin
\t //
\t // output is valid if any request for this output was made
\t // (request can only be made if 1. VC is already allocated
\t // and 2. vc is not blocked (full).
\t //
\t // What about two requests at same input port (different VCs)
\t // to different output ports?
\t // - \'output_requested\' is request to second stage of arbiters
\t // in switch allocator so this is OK.
\t
\t assign output_used[i] = output_requested[i] && output_valid_flit_check[i];
\t
end else begin
\t //
\t // need to check VC id. of flit leaving on this port is
\t // not blocked.
\t //
\t assign outgoing_blocked[i] = |(x_flit_xbarout[i].control.vc_id & x_vc_status[i]) ;
\t assign output_used[i] = output_requested[i] && !outgoing_blocked[i] && output_valid_flit_check[i];
end
always_comb
begin
i_flit_out[i]=x_flit_xbarout[i];
i_flit_out[i].control.valid=output_used[i];
\t // injected flits from tile have the lowest priority, once in network priority is increased.
`ifdef FLIT_DYNAMIC_PRIORITY
\t if (priority_network_traffic==1) begin
\t i_flit_out[i].control.flit_priority=1; // 4
\t end else begin
\t // flit priority is determined by the number of hops the flit has taken
\t if (priority_network_traffic==2) begin
\t\t if (i_flit_out[i].control.flit_priority<priority_flit_limit) begin
\t\t i_flit_out[i].control.flit_priority=i_flit_out[i].control.flit_priority+1;
\t\t end
\t end
\t end
`endif
\tend
end // block: outports
endgenerate
// synopsys translate_off
/* -----------------------------------------------------------------------------------
* assert (only unallocated VCs are allocated to waiting packets)
* -----------------------------------------------------------------------------------
*/
always@(posedge clk) begin
if (!rst_n) begin
end else begin
\t for (p=0; p<NP; p++) begin
\t for (v=0; v<NV; v++) begin
\t if (x_vc_new_valid[p][v]) begin
\t\t // check x_vc_new is free to be allocated
\t\t if (vcalloc_unrestricted) begin
\t\t if (!vc_alloc_status[oh2bin(x_output_port_for_vc[p][v])][oh2bin(x_vc_new[p][v])]) begin
\t\t\t$display ("%m: Error: Newly allocated VC is already allocated to another packet");
$display ("Input port=%1d, VC=%1d", p,v);
\t\t\t$display ("Requesting Output Port %b (%1d)", x_output_port_for_vc[p][v],
\t\t\t\t oh2bin(x_output_port_for_vc[p][v]));
\t\t\t$display ("VC requested %b ", vc_requested[p][v]);
\t\t\t$display ("x_vc_new %b ", x_vc_new[p][v]);
\t\t\t$finish;
\t\t end
\t\t end
\t end
\t end
\t end
end
end
// synopsys translate_on
// synopsys translate_off
/* -----------------------------------------------------------------------------------
* assert (no. of flits leaving router == no. of flits dequeued from input FIFOs)
* -----------------------------------------------------------------------------------
*/
always@(posedge clk) begin
if (!rst_n) begin
end else begin
\t db_out_used = 0;
\t db_in_popped = 0;
\t // count number of outputs used.
\t for (p=0; p<NP; p++) begin
\t if (output_used[p]) db_out_used++;
\t end
\t // count number of flits removed from input fifos
\t for (p=0; p<NP; p++) begin
\t for (v=0; v<NV; v++) begin
\t if (x_pop[p][v]) db_in_popped++;
\t end
\t end
\t if (db_out_used!=db_in_popped) begin
\t $display ("%m: Error: more flits sent on output than dequeued from input FIFOs!");
\t for (p=0; p<NP; p++) begin
\t $display ("-------------------------------------------------");
\t $display ("Input Port=%1d", p);
\t $display ("-------------------------------------------------");
\t for (v=0; v<NV; v++) begin
\t\t $write ("VC=%1d: ", v);
\t\t if ((switch_req[p][v])||(spec_switch_req[p][v])||(switch_grant[p][v]))
\t\t $write ("[OUTP=%1d]", oh2bin(x_output_port_for_sw[p][v]));
\t\t if (switch_req[p][v]) $write ("(Switch_Req)");
\t\t if (spec_switch_req[p][v]) $write ("(Spec_Switch_Req)");
\t\t if (switch_grant[p][v]) $write ("(Switch_Grant)");
\t\t if (x_vc_new_valid[p][v]) $write ("(New VC Alloc\'d)");
\t\t
\t\t $display ("");
\t end
\t end // for (p=0; p<NP; p++)
\t $display ("-------------------------------------------------");
\t $display ("Output Used=%b", output_used);
\t $display ("-------------------------------------------------");
//\t $finish;
\t end // if (db_out_used!=db_in_popped)
end
end // always@ (posedge clk)
// synopsys translate_on
endmodule // simple_router
|
\r
/* -------------------------------------------------------------------------------\r
* (C)2007 Robert Mullins\r
* Computer Architecture Group, Computer Laboratory\r
* University of Cambridge, UK.\r
* -------------------------------------------------------------------------------\r
* \r
* Type definitions\r
* \r
* \'flit_t\' gets defined here\r
* \r
*/\r
\r
//\r
// `defines are read from defines.v (generated from configuration file)\r
//\r
\r
`ifndef __TYPES_V__\r
`define __TYPES_V__\r
\r
typedef enum integer { VC, LOCHSIDE, ISLAY } router_t;\r
\r
typedef bit unsigned [3:0] priority_type;\r
\r
//`define NEARLY_FULL_FLOW_CONTROL\r
`define CREDIT_FLOW_CONTROL\r
`include "defines.v"\r
\t \r
typedef logic [`VC_INDEX_BITS-1:0] vc_index_t;\r
\r
typedef logic [`ROUTER_RADIX-1:0] output_port_t;\r
typedef logic [`ROUTER_NUM_VCS-1:0] vc_t;\r
typedef logic [`CHANNEL_DATA_WIDTH-1:0] data_t;\r
\r
// could save one bit here\r
typedef logic signed [`X_ADDR_BITS:0] x_displ_t;\r
typedef logic signed [`Y_ADDR_BITS:0] y_displ_t;\r
\r
//`ifdef FLIT_DYNAMIC_PRIORITY\r
typedef logic unsigned [`FLIT_DYNAMIC_PRIORITY_BITS-1:0] flit_pri_t;\r
//`else\r
//typedef bit flit_pri_t;\r
//`endif\r
\r
typedef struct packed \r
\t{\r
//`ifdef NEARLY_FULL_FLOW_CONTROL\r
\t //vc_t nearly_full;\r
//`endif\r
//`ifdef CREDIT_FLOW_CONTROL\r
\t vc_index_t credit;\r
//`endif\r
\t logic credit_valid;\r
\t } chan_cntrl_t;\r
\r
typedef struct packed\r
\t{\r
\t logic measure; // 1 - include in statistics? (else 0 - warmup or drain phase)\r
\t integer flit_id; // sequential flit id.\r
\t integer packet_id; // sequential (for a particular source node) packet id.\r
\t integer inject_time; // time flit entered source FIFO\r
\t \r
\t integer hops; // no. of routers flit traverses on journey\r
\t \r
\t integer xdest, ydest; // final destination\r
\t integer xsrc, ysrc; // where was packet sent from\r
\t \r
\t } debug_flit_t;\r
\r
typedef struct packed\r
\t{\r
\t logic valid;\t \r
\t logic tail;\r
\t // output port required at next router\r
\t output_port_t output_port;\r
\t \r
\t // destination as displacement from source\r
\t x_displ_t x_disp;\r
\t y_displ_t y_disp;\r
\t \r
\t vc_t vc_id;\r
\t } control_flit_t;\r
\r
typedef struct packed\r
\t{\r
\t data_t data;\r
\t control_flit_t control;\r
\t } flit_t;\r
\r
\r
/*typedef struct packed\r
\t{\r
\t data_t data;\r
\t control_flit_t control;\r
`ifdef DEBUG\r
\t debug_flit_t debug;\r
`endif\r
\t } fifo_elements_t;*/\r
\t \t \r
// port ids for 5 port router (input or output)\r
`define port5id_north 5\'b00001\r
`define port5id_east 5\'b00010\r
`define port5id_south 5\'b00100\r
`define port5id_west 5\'b01000\r
`define port5id_tile 5\'b10000\r
\r
`define NORTH 0\r
`define EAST 1\r
`define SOUTH 2\r
`define WEST 3\r
`define TILE 4\r
\r
`define PV NP*NV\r
\r
// arrays of struct with real numbers are not supported by SystemVerilog?\r
\r
typedef struct \r
{\r
integer total_latency;\r
integer total_hops;\r
integer min_latency, max_latency;\r
integer min_hops, max_hops;\r
\r
// start and end of measurement period\r
integer measure_start, measure_end, flit_count; \r
\r
// record statistics for packets with common journey lengths (hop count)\r
integer total_lat_for_hop_count [(`NETWORK_X+`NETWORK_Y):0];\r
integer total_packets_with_hop_count [(`NETWORK_X+`NETWORK_Y):0];\r
\r
// record frequency of different packet latencies\r
integer lat_freq[100:0];\r
\r
} sim_stats_t;\r
\r
parameter MAXINT = 2^32-1;\r
\r
`endif
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Logic to determine if the virtual-channel held by a particular packet
* (buffered in an input VC FIFO) is blocked or ready?
*
* Looks at currently allocated VC or the next free VC that would be allocated
* at this port (as VC allocation may be taking place concurrently).
*
*/
module NW_vc_status (output_port,
\t\t free_vc_blocked,
\t\t vc_requested,
\t\t allocated_vc,
\t\t allocated_vc_valid,
\t\t vc_status,
\t\t vc_blocked);
parameter np=5;
parameter nv=4;
parameter unrestricted_vc_alloc = 0;
input output_port_t output_port [np-1:0][nv-1:0];
input [np-1:0] free_vc_blocked; // at each output port
input [nv-1:0] allocated_vc [np-1:0][nv-1:0]; // allocated VC ID
input [np-1:0][nv-1:0] allocated_vc_valid; // holding allocated VC?
input [np-1:0][nv-1:0] vc_status; // blocked/ready status for each output VC
output [np-1:0][nv-1:0] vc_blocked;
input [np-1:0][nv-1:0][nv-1:0] vc_requested;
logic [np-1:0][nv-1:0][np-1:0] next_blocked;
logic [np-1:0][nv-1:0] b, current_vc_blocked, new_vc_blocked;
logic [np-1:0][nv-1:0][nv-1:0] current_vc;
genvar ip,vc,op;
generate
for (ip=0; ip<np; ip++) begin:il
\t for (vc=0; vc<nv; vc++) begin:vl
\t if (unrestricted_vc_alloc) begin
\t assign current_vc[ip][vc] = (allocated_vc_valid[ip][vc]) ? allocated_vc[ip][vc] : vc_requested[ip][vc];
\t
\t end else begin
\t
for (op=0; op<np; op=op+1) begin:ol
\t\t
\t\t assign next_blocked[ip][vc][op] = (NW_route_valid_turn(ip, op)) ?
\t\t\t\t\t\t output_port[ip][vc][op] & free_vc_blocked[op] : 1'b0;
\t\t
\t end
\t assign new_vc_blocked[ip][vc]=|next_blocked[ip][vc];
\t assign current_vc[ip][vc] = allocated_vc[ip][vc];
\t end
\t
\t unary_select_pair #(ip, np, nv) blocked_mux
\t (output_port[ip][vc],
//\t allocated_vc[ip][vc],
\t current_vc[ip][vc],
\t vc_status,
\t current_vc_blocked[ip][vc]);
\t
\t /* (excludes impossible turn optimisations)
\t assign current_vc_blocked[ip][vc] =
vc_status[oh2bin(output_port[ip][vc])][oh2bin(allocated_vc[ip][vc])];
\t
\t */
\t if (unrestricted_vc_alloc) begin
\t assign b[ip][vc] = current_vc_blocked[ip][vc];
\t end else begin
\t assign b[ip][vc] = (allocated_vc_valid[ip][vc]) ? current_vc_blocked[ip][vc] : new_vc_blocked[ip][vc];
\t end
\t assign vc_blocked[ip][vc] = (NW_route_valid_input_vc (ip,vc)) ? b[ip][vc] : 1'b0;
\t end
end
endgenerate
endmodule // NW_vc_status
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Pipelining Register (Interlocked pipeline register or single-element FIFO)
*
*
* ----------------
* ----> push pop <-----
* <---- ready valid ----->
*
* ----> data_in data_out ----->
*
* ----> clk
* ----> rst_n
* ----------------
*
*
* if (ready) register can accept data on next clock edge
* i.e. (1) register is empty (!valid)
* or (2) register is (valid) and (pop) is asserted
*
* if (valid) register contents are valid
*/
`include "types.v" \r
typedef flit_t reg_t;\r
module NW_pipereg (push, pop, data_in, data_out, ready, valid, clk, rst_n);
//parameter type reg_t = flit_t;
input push, pop, clk, rst_n;
input reg_t data_in;
output reg_t data_out;
output valid, ready;
logic valid;
reg_t r;
always@(posedge clk) begin
if (!rst_n) begin
\t valid<=1\'b0;
end else begin
\t // attempt to push when register isn\'t ready
\t assert (!(push & !ready)) else $fatal;
\t if (pop) begin
//\t $display ("%d: %m: pop", $time);
\t end
\t
\t if (push) begin
\t r <= data_in;
\t valid<=1\'b1;
//\t $display ("%d: %m: push, new data=%1d, output_port=%b", $time, data_in.data, data_in.control.output_port);
\t
\t end else begin
\t if (pop) begin
\t valid<=1\'b0;
\t end
\t end
\t
end
end // always@ (posedge clk)
assign ready = !valid || pop ;
assign data_out = r;
endmodule // NW_pipereg
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Matrix Arbiter
*
* See Dally/Towles (p.359) for implementation details and full description
*
* Multistage Options
* ==================
*
* [multistage=0] Arbiter state is updated whenever a request is granted.
*
* [multistage=1] This arbiter is meant for situations where the initial
* request must progress through multiple stages of arbitration. An
* additional input to the arbiter (success) ensures that the state of
* the arbiter is only updated if the request is finally granted (at the
* last stage of arbitration).
*
* || This assumes \'success\' is produced before the end of the current clock
* || cycle.
*
* [multistage=2] Used in situations where multistage=1 would be, but when
* \'success\' is not available until the next clock cycle.
*
* Prioritised inputs
* ==================
*
* [priority_support = 0 | 1]
*
* Input requested are prioritized by associated \'req_priority\' input,
* may be anything from a single bit to N-bits wide.
*
* e.g. for 16 priority levels:
*
* parameter priority_support = 1;
* parameter type priority_type = bit unsigned [3:0];
*
* Note: The priority input is ignored if the associated request is
* not asserted.
*
*/
//#################################
// NOT IMPLEMENTED YET:
//
// - parameter GRANT_HOLD
// don\'t update matrix state until request
// assoc. with current grant is released
// - winning request will hold grant for as long as it is asserted
//
// - parameter PRIORITIZE first F inputs -
// inputs 0..F are priority inputs
// input 0 will be granted if requested
// input 1 will be granted (if input 0 is not asserted)
// ..etc to input F
//
// weighted arbiter,....
module comb_matrix_arb_next_state (state, grant, new_state);
parameter size=4;
input [size*size-1:0] state;
input [size-1:0] grant;
output [size*size-1:0] new_state;
genvar i,j;
generate
for (i=0; i<size; i=i+1) begin:ol2
for (j=0; j<size; j=j+1) begin:il2
assign new_state[j*size+i]= (state[j*size+i]&&!grant[j])||(grant[i]);
end
end
endgenerate
endmodule // comb_matrix_arb_next_state
module matrix_arb (request, req_priority, max_priority, grant, success, clk, rst_n);
parameter size= 4;
parameter multistage = 0;
parameter grant_hold = 0;
parameter priority_support = 0;
//parameter type priority_type = bit unsigned [3:0]; // e.g. 16-levels of priority
input [size-1:0] request;
input priority_type req_priority [size-1:0]; // optional
output priority_type max_priority;
output [size-1:0] grant;
input success;
input clk, rst_n;
genvar i,j;
logic [size-1:0] req;
logic [size-1:0] newgrant;
logic [size*size-1:0] next_state, current_state;
logic [size-1:0] pri [size-1:0];
logic [size*size-1:0] new_state;
logic [size*size-1:0] state;
logic update;
genvar r;
integer k;
priority_type highest_pri;
// #########################################
// Support for Prioritized Requests
// #########################################
assign max_priority = highest_pri;
// always@(posedge clk) begin
// $display ("%m: req=%b, grant=%b", req, grant);
// end
always_comb
begin
//\tif (priority_support && $bits(priority_type)>1) begin
\tif (priority_support) begin
\t highest_pri=\'0;
\t for (k=0; k<size; k++) begin
\t if (request[k] && (req_priority[k]>highest_pri)) highest_pri=req_priority[k];
\t end
\tend
end
generate
if (priority_support) begin
\t //
\t // determine what is highest priority request
\t // filter out any request with lower priority
\t //
\t for (r=0; r<size; r++) begin:ll
\t assign req[r]=request[r] && (req_priority[r]>=highest_pri);
\t end
end else begin // if (priority_support)
\t assign req=request;
end
endgenerate
// ##########################################
// Generate grants
// ##########################################
generate
for (i=0; i<size; i=i+1) begin:ol1
// generate grant i
for (j=0; j<size; j=j+1) begin:il1
if (j==i)
// request i wins if requesting and....
assign pri[i][j]=req[i];
else
// ....no other request with higher priority
if (j>i)
// j beats i
assign pri[i][j]=!(req[j]&&state[j*size+i]);
else
// !(i beats j)
assign pri[i][j]=!(req[j]&&!state[i*size+j]);
end
assign grant[i]=&pri[i];
end
endgenerate
generate
if (multistage==2) begin
assign state = success ? next_state : current_state;
end else begin
assign state = current_state;
end
endgenerate
//
// calculate next matrix state based on current requests and grants
//
comb_matrix_arb_next_state #(size) calc_next (.*);
always@(posedge clk) begin
if (!rst_n) begin
current_state<=\'1; //-1;
\tnext_state<=\'1; //-1;
end else begin
\t// **************************************************
\t// Multistage Arbiter with Late Success Notification (multistage==2)
\t// **************************************************
\tif (multistage==2) begin
\t update<=|req;
\t if (|req) begin
\t // This \'next_state\' will only be used on next clock cycle if
\t // \'success\' is asserted
\t next_state <= new_state;
\t end
\t if (update) begin
\t current_state <= state;
\t end
\tend else begin
\t // ************************************
\t // Multistage Arbiter (multistage==1)
\t // ************************************
\t // check request was ultimately successful before updating arbiter state
\t // we know about success before the next clock cycle.
\t if ((multistage==1)&!success) begin
\t // request was not ultimately successful, don\'t update priorities
\t end else begin
\t // **********************************
\t // Basic Arbiter (multistage==0)
\t // **********************************
\t // Update state whenever at least one request has been made
if (|req) begin
\t\t current_state<=new_state;
end
\t end
\tend
end
end
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Misc. functions package
*
* - clogb2(x) - ceiling(log2(x))
* - oh2bin(x) - one-hot to binary encoder
* - max (x,y) - returns larger of x and y
* - min (x,y) - returns smaller of x and y
* - abs (x) - absolute function
*/
function automatic integer abs (input integer x);
begin
if (x>=0) return (x); else return (-x);
end
endfunction
function automatic integer min (input integer x, input integer y);
begin
min = (x<y) ? x : y;
end
endfunction
function automatic integer max (input integer x, input integer y);
begin
max = (x>y) ? x : y;
end
endfunction
// A constant function to return ceil(logb2(x))
// Is this already present in the Systemverilog standard?
function automatic integer clogb2 (input integer depth);
integer i,x;
begin
x=1;
for (i = 0; 2**i < depth; i = i + 1)
\tx = i + 1;
clogb2=x;
end
endfunction
// one hot to binary encoder (careful not to produce priority encoder!)
function automatic integer oh2bin (input integer oh);
integer unsigned i,j;
begin
oh2bin='0;
for (i=0; i<5; i++) begin
\t for (j=0; j<32; j++) begin
\t if ((1'b1 << i)&j) begin
\t oh2bin[i] = oh2bin[i] | oh[j] ;
\t end
\t end
end
end
endfunction // oh2bin
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* vc_input_port
*
* - Buffers incoming flits and updates VC ID field with VC allocated for
* packet at current router.
*
* - Determine which port is needed at next router (route packet)
*
* pipelined_vc_switch_alloc = 0 | 1
* =================================
*
* Do we need to consider VCs allocated on this cycle when returning
* currently allocated VC id.?
* If VC/switch allocation is pipelined, current VC will always be
* read from the \'vc_reg\' register.
*
*/
module NW_vc_input_port(push, pop, data_in, vc_id, select, data_out, output_port, data_in_reg,
\t\t\tflags, buf_finished_empty,
\t\t\t// currently allocated VCs and valid bits
\t\t\tallocated_vc, allocated_vc_valid,
\t\t\t// incoming newly granted/allocated VCs and valid bits
\t\t\tvc_new, vc_new_valid,
\t\t\thead_is_tail,
\t\t\tflit_buffer_out,
\t\t\tclk, rst_n);
// number of virtual channels
parameter num_vcs = 4;
// length of each virtual channel buffer
parameter buffer_length = 8;
// Are VC and switch allocation pipelined?
parameter pipelined_vc_switch_alloc = 0;
// use of explicit pipelining registers?
parameter explicit_pipe_registers = 0;
input push, clk, rst_n;
input [num_vcs-1:0] pop;
input flit_t data_in;
output flit_t data_out;
output output_port_t output_port [num_vcs-1:0];
output flit_t data_in_reg;
output [num_vcs-1:0] head_is_tail;
output flit_t flit_buffer_out [num_vcs-1:0];
output [num_vcs-1:0] buf_finished_empty;
`include "NW_functions.v"
input [clogb2(num_vcs)-1:0] vc_id;
// input [clogb2(num_vcs)-1:0] select;
input [num_vcs-1:0] select;
output fifov_flags_t flags [num_vcs-1:0];
output [num_vcs-1:0] allocated_vc [num_vcs-1:0];
output [num_vcs-1:0] allocated_vc_valid;
\t
input [num_vcs-1:0][num_vcs-1:0] vc_new;
input [num_vcs-1:0] \tvc_new_valid;
logic [num_vcs-1:0] vc_reg [num_vcs-1:0];
logic [num_vcs-1:0] allocated_vc_valid;
flit_t buffer_data_out, routed;
logic [clogb2(num_vcs)-1:0] select_bin;
logic sel_allocated_vc_valid;
logic [num_vcs-1:0] sel_vc_reg, sel_vc_new;
integer i;
genvar vc;
assign select_bin = vc_index_t\'(oh2bin(select));
//
// virtual-channel buffers
//
/*
NW_behav_vc_buffers #(.size(buffer_length),
\t\t .n(num_vcs),
\t\t .fifo_elements_t(flit_t),
\t\t .output_all_head_flits(1)) vc_bufsi
(.push(push), .pop(pop), .data_in(data_in), .vc_id(vc_id), .select(select),
.data_out(buffer_data_out), .output_port(output_port), .data_in_reg(data_in_reg),
.flags(flags),
.head_is_tail(head_is_tail),
.flit_buffer_out(flit_buffer_out),
.clk, .rst_n);
*/
NW_vc_buffers #(.size(buffer_length),
\t\t .n(num_vcs),
\t\t //.fifo_elements_t(flit_t),
\t\t .output_all_head_flits(1)) vc_bufsi
(.push(push), .pop(pop), .data_in(data_in), .vc_id(vc_id), .select(select),
.data_out(buffer_data_out), .output_port(output_port), .data_in_reg(data_in_reg),
.flags(flags), .buf_finished_empty(buf_finished_empty),
.head_is_tail(head_is_tail),
.flit_buffer_out(flit_buffer_out),
.clk, .rst_n);
generate
for (vc=0; vc<num_vcs; vc++) begin:eachvc
if ((pipelined_vc_switch_alloc)&&(!explicit_pipe_registers)) begin
\t //
\t // if VC and switch allocation are pipelined,
\t // current VC is always read from register.
\t //
\t assign allocated_vc[vc] = vc_reg[vc];
\t
end else begin
\t
\t // is VC already held or will it be allocated on this cycle?
\t assign allocated_vc[vc] = vc_reg[vc]; //(allocated_vc_valid[vc]) ? vc_reg[vc] : vc_new[vc];
end
end
endgenerate
always@(posedge clk) begin
if (!rst_n) begin
\t for (i=0; i<num_vcs; i++) begin
\t // No allocated VCs on reset
\t allocated_vc_valid[i]<=1\'b0;
\t end
end else begin
\t //
\t // if we have sent the last flit (tail) we don\'t hold a VC anymore
\t //
\t
//\t if (data_out.control.tail && pop[select]) begin
//\t allocated_vc_valid[select]<=1\'b0;
//\t end
\t
\t for (i=0; i<num_vcs; i++) begin
\t if (flit_buffer_out[i].control.tail && pop[i]) begin
\t //
\t // tail has gone, no longer hold a valid VC
\t //
\t allocated_vc_valid[i]<=1\'b0;
\t vc_reg[i]<=\'0;
\t end else begin
\t // [may obtain, use and release VC in one cycle (single flit packets), if so
\t // allocated_vc_valid[] is never set
\t
\t if (vc_new_valid[i]) begin
\t\t //
\t\t // receive new VC
\t\t //
//\t\t $display ("%m: new VC (%b) written to reg. at input VC buffer %1d", vc_new[i], i);
\t\t allocated_vc_valid[i]<=1\'b1;
\t\t vc_reg[i]<=vc_new[i];
\t\t assert (vc_new[i]!=\'0) else begin
\t\t $display ("New VC id. is blank?"); $fatal;
\t\t end
\t end
\t end
\t end
end // else: !if(!rst_n)
end // always@ (posedge clk)
// allocated_vc_valid[select_bin], vc_reg[select_bin], vc_new[select_bin]
assign sel_allocated_vc_valid = |(allocated_vc_valid & select);
// NW_mux_oh_select #(.dtype_t(logic[num_vcs-1:0]), .n(num_vcs)) selvcr (vc_reg, select, sel_vc_reg);
// NW_mux_oh_select #(.dtype_t(logic[num_vcs-1:0]), .n(num_vcs)) selvcn (vc_new, select, sel_vc_new);
generate
if (!explicit_pipe_registers) begin
\t NW_route rfn (.flit_in(buffer_data_out), .flit_out(routed), .clk, .rst_n);
\t
\t always_comb
\t begin
\t data_out = routed;
\t data_out.control.vc_id = (sel_allocated_vc_valid) ? vc_reg[select_bin] : vc_new[select_bin];
\t
//\t data_out.control.vc_id = (sel_allocated_vc_valid) ? sel_vc_reg : sel_vc_new;
\t //data_out.control.vc_id = (allocated_vc_valid[select_bin]) ? vc_reg[select_bin] : vc_new[select_bin];
\t //allocated_vc[select]; rdm34
\t end
end
endgenerate
endmodule // vc_input_port
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Tree Matrix Arbiter
*
* - 'multistage' parameter - see description in matrix_arbiter.v
*
* The tree arbiter splits the request vector into groups, performing arbitration
* simultaneously within groups and between groups. Note this has implications
* for fairness.
*
* Only builds one level of a tree
*
*/
module NW_tree_arbiter (request, req_priority, grant, success, clk, rst_n);
parameter multistage=0;
parameter size=20;
parameter groupsize=4;
parameter numgroups=size/groupsize;
parameter priority_support = 0;
//parameter type priority_type = bit unsigned [3:0]; // e.g. 16-levels of priority
input [size-1:0] request;
input priority_type req_priority [numgroups-1:0][groupsize-1:0]; // optional
output [size-1:0] grant;
input \t success;
input \t clk, rst_n;
logic [size-1:0] intra_group_grant;
logic [numgroups-1:0] group_grant, any_group_request;
logic [numgroups-1:0] current_group_success, last_group_success;
logic [numgroups-1:0] group_success;
priority_type max_priority [numgroups-1:0];
genvar i;
generate
for (i=0; i<numgroups; i=i+1) begin:arbiters
if (multistage==0) begin
\t //
\t // group_arbs need to be multistage=1, as group may not get granted
\t //
\t matrix_arb #(.size(groupsize),
\t\t .multistage(1),
\t\t //.priority_type(priority_type),
\t\t .priority_support(priority_support)) arb
\t (.request(request[(i+1)*groupsize-1:i*groupsize]),
\t .req_priority(req_priority[i]),
\t .max_priority(max_priority[i]),
\t .grant(intra_group_grant[(i+1)*groupsize-1:i*groupsize]),
\t .success(group_success[i]),
\t .clk, .rst_n);
\t
end else begin
\t matrix_arb #(.size(groupsize),
\t\t .multistage(multistage),
\t\t // .priority_type(priority_type),
\t\t .priority_support(priority_support)) arb
\t (.request(request[(i+1)*groupsize-1:i*groupsize]),
\t .req_priority(req_priority[i]),
\t .max_priority(max_priority[i]),
\t .grant(intra_group_grant[(i+1)*groupsize-1:i*groupsize]),
\t .success(group_success[i] & success),
//\t .success('1),
\t .clk, .rst_n);
end
\t\t\t
assign any_group_request[i] = |request[(i+1)*groupsize-1:i*groupsize];
assign grant[(i+1)*groupsize-1:i*groupsize]=
\t intra_group_grant[(i+1)*groupsize-1:i*groupsize] & {groupsize{group_grant[i]}};
//.success(any_group_request[i] & group_grant[i] & success),
//assign current_group_success[i]=|grant[(i+1)*groupsize-1:i*groupsize];
assign current_group_success[i]= group_grant[i];
end
if (multistage==2) begin
always@(posedge clk) begin
\t if (!rst_n) begin
\t last_group_success<='0;
\t end else begin
\t last_group_success<=current_group_success;
\t end
end
assign group_success=last_group_success;
end else begin
assign group_success=current_group_success;
end
endgenerate
matrix_arb #(.size(numgroups),
\t\t.multistage(multistage),
\t\t//.priority_type(priority_type),
\t\t.priority_support(priority_support)) group_arb
(.request(any_group_request),
.req_priority(max_priority),
.grant(group_grant),
.success(success),
.clk, .rst_n);
endmodule // tree_arbiter
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Virtual-Channel (Channel-level) Flow-Control
* ============================================
*
* Supports
* - credit flow-control
* - stop/go style flow-control
*
* Credit Counter Optimization (for credit-based flow-control)
* ===========================
*
* optimized_credit_counter = 0 | 1
*
* Set to \'1\' to move credit counter logic to start of next clock cycle.
* Remove add/sub from critical path.
*
* To move add/sub logic we buffer the last credit rec. and the any
* flit sent on the output.
*
*/
module NW_vc_fc_out (flit, flit_valid,
\t\t channel_cntrl_in,
\t\t vc_status, // vc_status[vc]=1 if blocked (fifo is full)
\t\t // only when using credit-based flow control
\t\t vc_empty, // vc_empty[vc]=1 if VC fifo is empty (credits=init_credits)
\t\t vc_credits,
\t\t clk, rst_n);
`include "NW_functions.v"
parameter num_vcs = 4;
parameter init_credits = 4;
parameter optimized_credit_counter = 1;
// +1 as has to hold \'init_credits\' value
parameter counter_bits = clogb2(init_credits+1);
input flit_t flit;
input flit_valid;
input chan_cntrl_t channel_cntrl_in;
output vc_t vc_status;
output [num_vcs-1:0] vc_empty;
output [num_vcs-1:0][counter_bits-1:0] vc_credits;
input clk, rst_n;
logic [num_vcs-1:0][counter_bits-1:0] counter;
logic [num_vcs-1:0] inc, dec;
// buffer credit and flit vc id.\'s so we can move counter in credit counter optimization
logic last_credit_valid, last_flit_valid;
logic [num_vcs-1:0] last_flit_vc_id;
// logic [counter_bits-1:0] last_credit;
vc_index_t last_credit;
logic [num_vcs-1:0][counter_bits-1:0] counter_current;
logic [num_vcs-1:0] \t vc_empty;
genvar i;
// fsm states
parameter stop=1\'b0, go=1\'b1;
logic [num_vcs-1:0] current_state, next_state;
// *************************************
// Stop/Go Flow Control
// *************************************
`ifdef NEARLY_FULL_FLOW_CONTROL
generate
for (i=0; i<num_vcs; i++) begin:pervc
\t always@(posedge clk) begin
\t if (!rst_n)
\t current_state[i]<=go;
\t else
\t current_state[i]<=next_state[i];
\t end
\t
\t always_comb begin
\t case (current_state[i])
\t stop:
\t\tif (channel_cntrl_in.nearly_full[i])
\t\t begin
\t\t next_state[i]<=go;
\t\t end
\t\telse
\t\t begin
\t\t next_state[i]<=stop;
\t\t end
\t go:
\t\t// nearly full and flit sent
\t\tif (channel_cntrl_in.nearly_full[i] && flit_valid && (oh2bin(flit.control.vc_id)==i))
\t\t begin
\t\t next_state[i]<=stop;
\t\t end
\t\telse
\t\t begin
\t\t next_state[i]<=go;
\t\t end
\t endcase
\t end // always_comb begin
\t assign vc_status[i]=(current_state[i]==stop);
end // block: pervc
endgenerate
`endif
// *************************************
// Credit-based Flow Control
// *************************************
`ifdef CREDIT_FLOW_CONTROL
generate
if (optimized_credit_counter) begin
\t // ***********************************
\t // optimized credit-counter (moves counter logic off critical path)
\t // ***********************************
\t always@(posedge clk) begin
\t last_credit_valid <= channel_cntrl_in.credit_valid;
\t last_credit <= channel_cntrl_in.credit;
\t last_flit_valid <= flit_valid;
\t last_flit_vc_id <= flit.control.vc_id;
//\t $display ("empty=%b", vc_empty);
\t end
\t assign vc_credits = counter_current;
\t
\t for (i=0; i<num_vcs; i++) begin:pervc1
\t always_comb begin:addsub
\t if (inc[i] && !dec[i])
\t\t counter_current[i]=counter[i]+1;
\t else if (dec[i] && !inc[i])
\t\t counter_current[i]=counter[i]-1;
\t else
\t\t counter_current[i]=counter[i];
\t end
\t
\t always@(posedge clk) begin
\t if (!rst_n) begin
\t\t counter[i]<=init_credits;
\t\t vc_empty[i]<=\'1;
\t end else begin
\t\t counter[i]<=counter_current[i];
\t\t
\t\t if ((counter_current[i]==0) ||
\t\t ((counter_current[i]==1) && flit_valid && (oh2bin(flit.control.vc_id)==i)) &&
\t\t !(channel_cntrl_in.credit_valid && (channel_cntrl_in.credit==i))) begin
\t\t vc_status[i] <= 1\'b1;
\t\t vc_empty[i] <= 1\'b0;
\t\t end else begin
\t\t vc_status[i] <= 1\'b0;
\t\t vc_empty[i] <= (counter_current[i]==init_credits);
\t\t end
\t end // else: !if(!rst_n)
\t end // always@ (posedge clk)
\t assign inc[i]=(last_credit_valid) && (last_credit==i);
assign dec[i]=(last_flit_valid) && (oh2bin(last_flit_vc_id)==i);
\t end
\t
end else begin
\t assign vc_credits = counter;
\t
\t // ***********************************
\t // unoptimized credit-counter
\t // ***********************************
\t for (i=0; i<num_vcs; i++) begin:pervc
\t always@(posedge clk) begin
\t if (!rst_n) begin
\t\t counter[i]<=init_credits;
\t end else begin
\t\t
\t\t if (inc[i] && !dec[i]) begin
\t\t assert (counter[i]!=init_credits) else $fatal;
\t\t counter[i]<=counter[i]+1;
\t\t end
\t\t
\t\t if (dec[i] && !inc[i]) begin
\t\t assert (counter[i]!=0) else $fatal;
\t\t counter[i]<=counter[i]-1;
\t\t end
\t\t
\t\t
\t end // else: !if(!rst_n)
\t end
\t
\t // received credit for VC i?
\t assign inc[i]=(channel_cntrl_in.credit_valid) && (channel_cntrl_in.credit==i);
\t // flit sent, one less credit
\t assign dec[i]=(flit_valid) && (oh2bin(flit.control.vc_id)==i);
\t
\t // if counter==0, VC is blocked
\t assign vc_status[i]=(counter[i]==0);
\t // if counter==init_credits, VC buffer is empty
\t assign vc_empty[i]=(counter[i]==init_credits);
\t
\t end // block: pervc
end
endgenerate
`endif
endmodule
|
// USED ONLY TO SELECT VC BLOCKED STATUS
// OPTIMISE FOR XY ROUTING
/* autovdoc@
*
* component@ unary_select_pair
* what@ A sort of mux!
* authors@ Robert Mullins
* date@ 5.3.04
* revised@ 5.3.04
* description@
*
* Takes two unary (one-hot) encoded select signals and selects one bit of the input.
*
* Implements the following:
*
* {\\tt selectedbit=datain[binary(sela)*WB+binary(selb)]}
*
* pin@ sel_a, WA, in, select signal A (unary encoded)
* pin@ sel_b, WB, in, select signal B (unary encoded)
* pin@ data_in, WA*WB, in, input data
* pin@ selected_bit, 1, out, selected data bit (see above)
*
* param@ WA, >1, width of select signal A
* param@ WB, >1, width of select signal B
*
* autovdoc@
*/
module unary_select_pair (sel_a, sel_b, data_in, selected_bit);
parameter input_port = 0; // from 'input_port' to 'sel_a' output port
parameter WA = 4;
parameter WB = 4;
input [WA-1:0] sel_a;
input [WB-1:0] sel_b;
input [WA*WB-1:0] data_in;
output selected_bit;
genvar i,j;
wire [WA*WB-1:0] selected;
generate
for (i=0; i<WA; i=i+1) begin:ol
for (j=0; j<WB; j=j+1) begin:il
\t assign selected[i*WB+j] = (NW_route_valid_turn(input_port, i)) ?
\t\t\t\t data_in[i*WB+j] & sel_a[i] & sel_b[j] : 1'b0;
\t
\t /*
\t // i = output_port
\t // assume XY routing and that data never leaves on port it entered
\t if ((input_port==i) || (((input_port==`NORTH)||(input_port==`SOUTH)) &&
\t ((i==`EAST)||(i==`WEST)))) begin
\t assign selected[i*WB+j]=1'b0;
\t end else begin
\t assign selected[i*WB+j]=data_in[i*WB+j] & sel_a[i] & sel_b[j];
\t end
\t */
end
end
endgenerate
assign selected_bit=|selected;
endmodule // unary_select_pair
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* VC Switch Allocator
* ===================
*
* Technically this is an input first seperable allocator (see Dally/Towles p.367)
*
* Arbitration Stage 1:
* * Arbitrate between requests from VCs at each input port (np x nv:1 arbiters)
* * Select the output port request of the winning flit
*
* Arbitration Stage 2:
* * Arbitrate between requests for each output port (np x np:1 arbiters)
* * Determine which input port requests were successful.
*
*
* ----> req --> grant
* ----> required_output_port
* . .
* . [STAGE 1] [STAGE 2] .
* . Arbitrate between Arbitrate between .
* ----> req requests from same winners of stage 1 --> grant
* ----> required_output_port input port that require the
* same output port
*
* Parameters
* ==========
*
* # np - number of ports (assumes no. input = no. output)
* # nv - number of virtual-channels
*
* (NOT SUPPORTED IN CONFIGURATION FILE)
* Lonely Outputs Optimization [experimentation only, very poor synthesis results]
* ===========================
*
* ** Ignores flit priority if present **
*
* # priority_lonely_outputs = 0 | 1
*
* Prioritises a request if it represents the only request for a
* particular output. See Dally/Towles p.373 for rationale. Note
* this scheme doesn't perform a full count of requests for each
* output. It simply looks for cases where an output is requested
* by a single input.
*
*/
module NW_vc_switch_allocator (req,
\t\t\t req_priority, // for flit prioritisation support
\t\t\t output_port,
\t\t\t grant,
\t\t\t vc_mux_sel, // not used by Lochside
\t\t\t xbar_select, // not used by Lochside
\t\t\t any_request_for_output, // not used by Lochside
\t\t\t taken_by_nonspec, // not used by Lochside
\t\t\t clk, rst_n);
parameter np=5;
parameter nv=4;
parameter priority_lonely_outputs = 0;
parameter speculative_alloc = 0;
parameter dynamic_priority_switch_alloc = 0;
//parameter type flit_priority_t = logic unsigned [3:0];
parameter turn_opt = 1 ; // 0 useful when testing, default 1
input [np-1:0][nv-1:0] req;
input flit_priority_t req_priority [np-1:0][nv-1:0];
input output_port_t output_port [np-1:0][nv-1:0];
output [np-1:0][nv-1:0] grant;
output [np-1:0][nv-1:0] vc_mux_sel;
output [np-1:0][np-1:0] xbar_select;
output [np-1:0] any_request_for_output;
input [np-1:0] taken_by_nonspec; // has a non-spec request been granted at this input port?
input clk, rst_n;
logic [np-1:0] input_port_success;
logic [np-1:0][nv-1:0] stage1_grant;
output_port_t winning_port_req [np-1:0];
logic [np-1:0][np-1:0] output_port_req, all_grants_for_input, output_port_grant,
\t\t permitted_output_port_req, permitted_output_port_grant;
logic [np-1:0] uncontested, contested;
logic priority_bit [np-1:0][nv-1:0];
flit_priority_t max_priority[np-1:0];
flit_priority_t req_priority_stage2 [np-1:0][np-1:0];
genvar i,j;
// buffers at each input port arbitrate for access to single port on crossbar
// (winners of stage1 go on to arbitrate for access to actually output port)
assign vc_mux_sel = stage1_grant;
function logic [np-1:0] find_uncontested(input [np-1:0][nv-1:0] req,
input output_port_t output_port [np-1:0][nv-1:0]);
logic [np-1:0] contested, uncontested;
integer o,p,v;
begin
\t for (o=0; o<np; o++) begin
\t
\t uncontested[o]=1'b0;
\t contested[o]=1'b0;
\t
\t for (p=0; p<np; p++) begin
\t for (v=0; v<nv; v++) begin
\t\t if ((req[p][v])&&(output_port[p][v][o])) begin
\t\t // request at input port 'p' at VC 'v' is requesting port 'o'
\t\t if (!uncontested[o]&&!contested[o]) begin
\t\t\tuncontested[o]=1'b1;
\t\t end else begin
\t\t\tif (uncontested[o]&&!contested[o]) begin
\t\t\t contested[o]=1'b1;
\t\t\t uncontested[o]=1'b0;
\t\t\tend
\t\t end
\t\t end
\t end
\t end
\t end // for (o=0; o<np; o++)
\t find_uncontested=uncontested;
end
endfunction
// arbitrate between virtual-channels at each input port\t
generate
// ************************************************
// look for uncontested requests for an output port
// ************************************************
if (priority_lonely_outputs) begin
\t assign uncontested=find_uncontested(req, output_port);
\t
\t // foreach output port
\t for (i=0; i<np; i++) begin:ips
\t // set priority bit if request needs uncontested port
\t for (j=0;j<nv;j++) begin:vcs
\t assign priority_bit[i][j]=|(output_port[i][j] & uncontested);
\t end
\t end
end // if (priority_lonely_outputs)
for (i=0; i<np; i++) begin:inport
\t // **********************************
\t // nv:1 arbiter at each input port
\t // **********************************
\t if (priority_lonely_outputs) begin
\t matrix_arb #(.size(nv),
\t\t\t .multistage(1),
\t\t\t //.priority_type(bit),
\t\t\t .priority_support(1)) vc_arb
\t (.request(req[i]),
\t .req_priority(priority_bit[i]),
\t .grant(stage1_grant[i]),
\t .success(input_port_success[i]),
\t .clk, .rst_n);\t
\t end else begin
\t matrix_arb #(.size(nv),
\t\t\t .multistage(1),
\t\t\t //.priority_type(flit_priority_t),
\t\t\t .priority_support(dynamic_priority_switch_alloc)) vc_arb
\t (.request(req[i]),
\t .req_priority(req_priority[i]),
\t .max_priority(max_priority[i]),
\t .grant(stage1_grant[i]),
\t .success(input_port_success[i]),
\t .clk, .rst_n);
\t end
\t // select output port request of (first-stage) winner
\t NW_mux_oh_select #( .n(nv)) reqmux
(output_port[i], stage1_grant[i], winning_port_req[i]);
\t // setup requests for output ports
\t for (j=0; j<np; j++) begin:outport
\t //
\t // request priorities for second stage of arbitration
\t // - requests from input i will have priority 'max_priority[i]'
\t //
\t assign req_priority_stage2[j][i] = max_priority[i];
\t
\t // if turn is invalid output port request will never be made
\t if (turn_opt) begin
\t assign output_port_req[j][i]=(NW_route_valid_turn(i,j)) ? winning_port_req[i][j] : 1'b0;
\t end else begin
\t assign output_port_req[j][i] = winning_port_req[i][j];
\t end
\t // for cases when both speculative and non-speculative versions of a switch
\t // allocator are employed together.
\t if (speculative_alloc) begin
\t assign permitted_output_port_req[j][i] = output_port_req[j][i] & !taken_by_nonspec[i];
\t end else begin
\t assign permitted_output_port_req[j][i] = output_port_req[j][i];
\t end
\t end
\t
\t for (j=0; j<nv; j++) begin:suc
\t // was request successful at both input and output arbitration?
\t assign grant[i][j]=stage1_grant[i][j] && input_port_success[i];
\t end
end // block: inport
for (i=0; i<np; i++) begin:outport
\t // **********************************
\t // np:1 arbiter at each output port
\t // **********************************
\t if (priority_lonely_outputs) begin
\t matrix_arb #(.size(np),
\t\t\t .multistage(0)) outport_arb
\t (.request(output_port_req[i]),
\t .grant(output_port_grant[i]),
\t .clk, .rst_n);
\t end else begin
\t matrix_arb #(.size(np),
\t\t\t .multistage(0),
\t\t\t //.priority_type(flit_priority_t),
\t\t\t .priority_support(dynamic_priority_switch_alloc)) outport_arb
\t (.request(output_port_req[i]),
\t .req_priority(req_priority_stage2[i]),
\t .grant(output_port_grant[i]),
\t .clk, .rst_n);
\t end
\t for (j=0; j<np; j++) begin:g
\t // was input port successful?
\t assign all_grants_for_input[j][i]=output_port_grant[i][j];
\t if (speculative_alloc) begin
\t assign permitted_output_port_grant[j][i] = output_port_grant[j][i] && !taken_by_nonspec[i];
\t end else begin
\t assign permitted_output_port_grant[j][i] = output_port_grant[j][i];
\t end
\t\t\t\t\t\t
\t end
\t assign input_port_success[i]=|all_grants_for_input[i];
\t assign any_request_for_output[i]=|permitted_output_port_req[i];
end
endgenerate
assign xbar_select = permitted_output_port_grant;
endmodule // NW_vc_switch_allocator
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* XY routing
*
* Routing Function
* ================
*
* Simple XY routing
* - Function updates flit with the output port required at next router
* and modifies displacement fields as head flit gets closer to
* destination.
*
* More complex routing algorithms may be implemented by making edits here
* and to the flit\'s control field defn.
*
* Valid Turn?
* ===========
*
* NW_route_valid_turn(from, to)
*
* This function is associated with the routing algorithm and is used to
* optimize the synthesis of the implementation by indicating impossible
* turns - hence superfluous logic.
*
* Valid Input VC
* ==============
*
* Does a particular input VC exist. e.g. Tile input port may only contain
* one VC buffer.
*
*/
function automatic bit NW_route_valid_input_vc;
\r
input integer port;\r
input integer vc;\r
`include "parameters.v"
bit valid;
begin
valid=1\'b1;
// if ((port==`TILE)&&(vc!=0)) valid=1\'b0;
if (port==`TILE) begin
\t if (vc>=router_num_vcs_on_entry) valid=1\'b0;
end
NW_route_valid_input_vc=valid;
end
endfunction // automatic
function automatic bit NW_route_valid_turn;
\r
input output_port_t from;\r
input output_port_t to;\r
\r
bit valid;
begin
valid=1\'b1;
// flits don\'t leave on the same port as they entered
if (from==to) valid=1\'b0;
`ifdef OPT_MESHXYTURNS
// Optimise turns for XY routing in a mesh
if (((from==`NORTH)||(from==`SOUTH))&&((to==`EAST)||(to==`WEST))) valid=1\'b0;
`endif
NW_route_valid_turn=valid;
end
endfunction // bit
module NW_route (flit_in, flit_out, clk, rst_n);
input flit_t flit_in;
output flit_t flit_out;
input clk, rst_n;
function flit_t next_route;
\r
\t input flit_t flit_in;\r
\t
logic [4:0] route;
flit_t new_flit;
begin
\t new_flit=flit_in;
\t // Simple XY Routing
\t if (flit_in.control.x_disp!=0) begin
\t if (flit_in.control.x_disp>0) begin
\t route = `port5id_east;
\t new_flit.control.x_disp--;
\t end else begin
\t route = `port5id_west;
\t new_flit.control.x_disp++;
\t end
\t end else begin
\t if (flit_in.control.y_disp==0) begin
\t route=`port5id_tile;
\t end else if (flit_in.control.y_disp>0) begin
\t route=`port5id_south;
\t new_flit.control.y_disp--;
\t end else begin
\t route=`port5id_north;
\t new_flit.control.y_disp++;
\t end
\t end
\t new_flit.control.output_port = route;
\t
\t next_route = new_flit;
end
endfunction // flit_t
assign flit_out=next_route(flit_in);
endmodule // route
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* VC allocator
* Allocates new virtual-channels for newly arrived packets.
*
* "unrestricted" VC allocation (Peh/Dally style)
*
* Takes place in two stages:
*
* stage 1. ** VC Selection **
* Each waiting packet determines which VC it will request.
* (v:1 arbitration). Can support VC alloc. mask here (from
* packet header or static or dynamic..)
*
*
* stage 2. ** VC Allocation **
* Access to each output VC is arbitrated (PV x PV:1 arbiters)
*
*/
//
// ** THIS IS NOT USED ** only for hacking at present.... (*:
//
`include "types.v"
function automatic logic[15:0] NW_vc_sel_mask (input flit_t f);
begin
case (f.control.output_port)
\t`port5id_tile:
\t begin
\t NW_vc_sel_mask=\'1;
\t end
\t`port5id_north:
\t begin
\t // north next too
\t if (f.control.y_disp+1<0) begin
\t\tNW_vc_sel_mask=4\'b0011;
\t end else begin
\t\tNW_vc_sel_mask=4\'b1100;
\t end
\t end
\t`port5id_east:
\t begin
\t // east next too
\t if (f.control.x_disp-1>0) begin
\t\tNW_vc_sel_mask=4\'b0011;
\t end else begin
\t\tNW_vc_sel_mask=4\'b1100;
\t end
\t end
\t`port5id_south:
\t begin
\t // south next too
\t if (f.control.y_disp-1>0) begin
\t\tNW_vc_sel_mask=4\'b0011;
\t end else begin
\t\tNW_vc_sel_mask=4\'b1100;
\t end
\t end
\t`port5id_west:
\t begin
\t // west next too
\t if (f.control.x_disp+1<0) begin
\t\tNW_vc_sel_mask=4\'b0011;
\t end else begin
\t\tNW_vc_sel_mask=4\'b1100;
\t end
\t end
endcase
end
endfunction // NW_vc_sel_mask
module NW_vc_unrestricted_allocator (req, // VC request
\t\t\t\t output_port, // for which port?
\t\t\t\t //vc_mask, // which VC\'s are we permitted to request
\t\t\t\t req_priority, // prioritized requests? (between VC requests)
\t\t\t\t vc_status, // which VCs are free
\t\t\t\t vc_new, // newly allocated VC id.
\t\t\t\t vc_new_valid, // has new VC been allocated?
\t\t\t\t vc_allocated, // change VC status from free to allocated?
\t\t\t\t vc_requested, // which VCs were requested at each input VC?
\t\t\t\t flit, // head of each input VC buffer
\t\t\t\t vc_credits, // credits for each VC at each output port
\t\t\t\t clk, rst_n);
// `include "NW_functions.v";
//parameter type flit_priority_t = flit_pri_t;
parameter buf_len = 4;
\t\t
parameter xs=4;
parameter ys=4;
\t
parameter np=5;
parameter nv=4;
// some packets can make higher priority requests for VCs
// ** NOT YET IMPLEMENTED **
parameter dynamic_priority_vc_alloc = 0;
//
// selection policies
//
parameter vcselect_bydestinationnode = 0;
parameter vcselect_leastfullbuffer = 0;
parameter vcselect_arbstateupdate = 0; // always/never update state of VC select matrix arbiter
parameter vcselect_usepacketmask = 0; // packet determines which VCs may be requested (not with bydestinationnode!)
typedef logic unsigned [clogb2(buf_len+1)-1:0] pri_t;
//-----
input [np-1:0][nv-1:0] req;
input output_port_t output_port [np-1:0][nv-1:0];
//input [np-1:0][nv-1:0][nv-1:0] vc_mask;
input flit_priority_t req_priority [np-1:0][nv-1:0];
input [np-1:0][nv-1:0] vc_status;
output [np-1:0][nv-1:0][nv-1:0] vc_new;
output [np-1:0][nv-1:0] vc_new_valid;
output [np-1:0][nv-1:0] vc_allocated;
output [np-1:0][nv-1:0][nv-1:0] vc_requested;
input flit_t flit [np-1:0][nv-1:0];
input [np-1:0][nv-1:0][clogb2(buf_len+1)-1:0] vc_credits;
input clk, rst_n;
genvar i,j,k,l;
logic [np-1:0][nv-1:0][nv-1:0] stage1_request, stage1_grant;
logic [np-1:0][nv-1:0][nv-1:0] selected_status;
logic [np-1:0][nv-1:0][np-1:0][nv-1:0] stage2_requests, stage2_grants;
logic [np-1:0][nv-1:0][nv-1:0][np-1:0] vc_new_;\r
\r
logic [np-1:0][nv-1:0][nv-1:0] vc_mask;\r
pri_t pri [np-1:0][nv-1:0][nv-1:0];
assign vc_requested=stage1_grant;
generate
for (i=0; i<np; i++) begin:foriports
\t for (j=0; j<nv; j++) begin:forvcs
\t //
\t // Determine value of \'vc_mask\'
\t //
\t // What VCs may be requested?
\t //
\t // (a) all
\t // (b) use mask set in packet\'s control field
\t // (c) or select VC solely by destination node
\t //
\t if (vcselect_bydestinationnode || vcselect_usepacketmask) begin
\t if (vcselect_bydestinationnode) begin
\t\t //
\t\t // unless exiting network! - should be set as vcalloc_mask at source!!!!! TO-DO
\t\t // OR just set second stage request directly?
\t\t /*assign vc_mask[i][j] = (output_port[i][j]==`port5id_tile) ? \'1 :
\t\t\t\t\t 1\'b1<<(flit[i][j].debug.xdest+xs*flit[i][j].debug.ydest);
//\t\t\t\t\t 1\'b1<<(flit[i][j].debug.xsrc+xs*flit[i][j].debug.ysrc);
*/
\t end else begin
\t\t
\t end
\t end else begin
\t // packet may request any free VC
\t assign vc_mask[i][j] = \'1;
\t end
\t
\t //\t
\t // Select VC status bits at output port of interest (determine which VCs are free to be allocated)
\t //
\t assign selected_status[i][j] = vc_status[oh2bin(output_port[i][j])];
\t //
\t // Requests for VC selection arbiter
\t //
\t // Narrows requests from all possible VCs that could be requested to 1
\t //
\t for (k=0; k<nv; k++) begin:forvcs2
\t // Request is made if
\t // (1) Packet requires VC
\t // (2) VC Mask bit is set
\t // (3) VC is currently free, so it can be allocated
\t //
\t assign stage1_request[i][j][k] = req[i][j] && vc_mask[i][j][k] && selected_status[i][j][k];
\t // VC selection priority = number of credits
\t if (vcselect_leastfullbuffer) begin
\t\t assign pri[i][j][k] = vc_credits[oh2bin(output_port[i][j])][k];
\t end
\t end
\t //
\t // first-stage of arbitration
\t //
\t // Arbiter state doesn\'t mean much here as requests on different clock cycles may be associated
\t // with different output ports. vcselect_arbstateupdate determines if state is always or never
\t // updated.
\t //
\t matrix_arb #(.size(nv), .multistage(1),
\t\t\t .priority_support(vcselect_leastfullbuffer)\r
\t\t\t //,
\t\t\t //.priority_type(pri_t)\r
\t\t\t )
\t\t\t stage1arb
\t\t\t (.request(stage1_request[i][j]),
\t\t\t .req_priority(pri[i][j]),
\t\t\t .grant(stage1_grant[i][j]),
//\t\t\t .success(vc_new_valid[i][j]),
\t\t\t .success((vcselect_arbstateupdate==1)),
\t\t\t .clk, .rst_n);
\t //
\t // second-stage of arbitration, determines who gets VC
\t //
\t for (k=0; k<np; k++) begin:fo
\t for (l=0; l<nv; l++) begin:fv
\t\t assign stage2_requests[k][l][i][j] = stage1_grant[i][j][l] && output_port[i][j][k];
\t end
\t end
\t //
\t // np*nv np*nv:1 tree arbiters
\t //
\t NW_tree_arbiter #(.multistage(0),
.size(np*nv),
.groupsize(nv),
.priority_support(dynamic_priority_vc_alloc)\r
//,
//.priority_type(flit_priority_t)\r
) vcarb
(.request(stage2_requests[i][j]),
.req_priority(req_priority),
.grant(stage2_grants[i][j]),
.clk, .rst_n);
\t assign vc_allocated[i][j]=|(stage2_requests[i][j]);
\t //
\t // new VC IDs
\t //
\t for (k=0; k<np; k++) begin:fo2
\t for (l=0; l<nv; l++) begin:fv2
\t\t // could get vc x from any one of the output ports
\t\t assign vc_new_[i][j][l][k]=stage2_grants[k][l][i][j];
\t end
\t end
\t for (l=0; l<nv; l++) begin:fv3
\t assign vc_new[i][j][l]=|vc_new_[i][j][l];
\t end
\t assign vc_new_valid[i][j]=|vc_new[i][j];
\t end
end
endgenerate
endmodule // NW_vc_unrestricted_allocator
|
/********** defines.v **********/
// `defines are only used to create type definitions (and in some local optimisations)
// module parameters should always be used locally in
// modules
\r
`ifndef DEFINES_V\r
`define DEFINES_V\r
`define OPT_MESHXYTURNS
`define CHANNEL_DATA_WIDTH 32
`define FLIT_DYNAMIC_PRIORITY_BITS 4
`define X_ADDR_BITS 2
`define Y_ADDR_BITS 2
`define ROUTER_NUM_VCS 2
`define VC_INDEX_BITS 2
`define ROUTER_RADIX 5
`define NETWORK_X 4
`define NETWORK_Y 4
\r
`endif
|
`ifndef PARAMETERS_V\r
`define PARAMETERS_V\r
\r
`include "types.v"\r
\r
/******* parameters.v **********/\r
parameter verbose=0;\r
parameter priority_switch_alloc_byflitid=0;\r
parameter router_num_vcs=2;\r
parameter sim_injection_rate=0.3;\r
parameter vcselect_usepacketmask=0;\r
parameter router_num_vcs_on_exit=2;\r
parameter router_num_vcs_on_entry=1;\r
parameter network_y=4;\r
parameter debug=0;\r
parameter priority_flit_bits=4;\r
parameter opt_specoutputportreq=0;\r
parameter vcselect_onlywhenempty=0;\r
parameter priority_flit_limit=4;\r
parameter uarch_explicit_pipeline_register=1;\r
parameter opt_meshxyturns=1;\r
parameter priority_singleflitpacketboost=0;\r
//parameter router_arch=VC;\r
parameter priority_flit_dynamic_switch_alloc=0;\r
parameter uarch_pipeline=1;\r
parameter network_x=4;\r
parameter priority_network_traffic=0;\r
parameter sim_packet_fixed_length=1;\r
parameter vcselect_leastfullbuffer=0;\r
parameter opt_noswitchreqifwasblocked=0;\r
parameter sim_packetb_length=5;\r
parameter vcselect_arbstateupdate=0;\r
parameter sim_packetab=0;\r
parameter vcselect_bydestinationnode=0;\r
parameter channel_latency=0;\r
parameter swalloc_speculative=0;\r
parameter sim_packet_length=4;\r
parameter priority_switch_alloc_byjourneylength=0;\r
parameter priority_flit_dynamic_vc_alloc=0;\r
parameter router_buf_len=4;\r
parameter sim_packeta_length=1;\r
parameter sim_measurement_packets=10;\r
parameter uarch_full_vc_check_before_switch_request=1;\r
parameter sim_packeta_prob=0.67;\r
parameter sim_warmup_packets=10;\r
parameter channel_data_width=16;\r
parameter router_radix=5;\r
parameter vcalloc_unrestricted=1;\r
\r
`endif
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* FIFO-based VC Free Pool
* ============-==========
*
* Serves next free VC id. Tail flits sent on output link replenish free VC pool
*
* One free VC pool per output port
*
*/
module NW_vc_free_pool (flit, valid,
\t\t\t// FIFO free pool
\t\t\toh_free_vc, no_free_vc, // head of free VC FIFO, free VC FIFO empty?
\t\t\tvc_consumed, // VC allocated at this output
\t\t\t// Unrestricted free pool
\t\t\tvc_alloc_status, // VC allocation status
\t\t\tvc_allocated, // which VCs were allocated on this cycle?
\t\t\tvc_empty, // is downstream FIFO associated with VC empty?
\t\t\tclk, rst_n);
parameter num_vcs_global = 4; // in router
parameter num_vcs_local = 4; // at this output port
parameter fifo_free_pool = 0; // organise free pool as FIFO (offer at most one VC per output port per cycle)
// only applicable if fifo_free_pool = 0
parameter only_allocate_vc_when_empty = 0; // only allow a VC to be allocated when it is empty
//-------
input flit_t flit;
input valid;
output vc_t oh_free_vc;
output no_free_vc;
input vc_consumed;
input [num_vcs_global-1:0] vc_allocated;
output [num_vcs_global-1:0] vc_alloc_status;
input [num_vcs_global-1:0] vc_empty;
input clk, rst_n;
logic [num_vcs_global-1:0] vc_alloc_status_reg;
vc_t fifo_out;
fifov_flags_t fifo_flags;
logic push;
integer i;
generate
// =============================================================
// Organise Free VC pool as FIFO
// permits at most one VC to be allocated per output per cycle.
// =============================================================
if (fifo_free_pool) begin
\t
\t // avoid adding output reg output port serving tile without VCs
\t // (could avoid instantiating a FIFO at all in that case)
\t NW_fifo_v #(.init_fifo_contents(1),
\t\t //.fifo_elements_t(vc_t),
\t\t .size(num_vcs_local+1),
\t\t .input_reg(0),
\t\t .output_reg(num_vcs_local>2))
//\t \t .output_reg(0))
\t free_vc_fifo (.push(push),
\t\t\t .pop(vc_consumed),
\t\t\t .data_in(flit.control.vc_id),
\t\t\t .data_out(fifo_out),
\t\t\t .flags(fifo_flags),
\t\t\t .clk, .rst_n);
\t
\t if (num_vcs_local>2) begin
\t assign oh_free_vc = fifo_out;// & {(num_vcs_local){!fifo_flags.empty}}; //- assumes output reg is used
\t end else begin
\t assign oh_free_vc = fifo_out & {(num_vcs_local){!fifo_flags.empty}};
\t end
\t
\t assign push = valid && flit.control.tail;
\t
\t assign no_free_vc = fifo_flags.fast_empty; // or |oh_free_vc
\t
\t always@(posedge clk) begin
\t /*
\t if (vc_consumed) begin
\t $display ("%d: %m: pop free VC FIFO (vc=%b)", $time, fifo_out);
end
\t if (push) begin
\t $display ("%d: %m: push free VC on FIFO (flit.vc_id=%b, flit.tail=%b)",
\t\t $time, flit.control.vc_id, flit.control.tail);
end
\t */
\t
\t // synopsys translate_off
\t if (push && fifo_flags.full && !vc_consumed) begin
\t $display ("%d: %m: Error free VC fifo full, push and !pop ....", $time);
\t $display ("flit.vc_id = %b", flit.control.vc_id);
\t $display ("flit.tail = %b", flit.control.tail);
\t $display ("vc_consumed = %b", vc_consumed);
\t $finish;
\t end
\t // synopsys translate_on
\t end // always@ (posedge clk)
end else begin // if (fifo_free_pool)
\t // =============================================================
\t // Unrestricted VC allocation
\t // =============================================================
\t always@(posedge clk) begin
\t if (!rst_n) begin
\t for (i=0; i<num_vcs_global; i++) begin:forvcs2
\t\t vc_alloc_status_reg[i] <= (i<num_vcs_local);
\t end
\t end else begin
\t for (i=0; i<num_vcs_global; i++) begin:forvcs
\t\t //
\t\t // VC consumed, mark VC as allocated
\t\t //
\t\t if (vc_allocated[i]) vc_alloc_status_reg[i]<=1\'b0;
\t end
\t if (valid && flit.control.tail) begin
\t\t //
\t\t // Tail flit departs, packets VC is ready to be used again
\t\t //
\t\t // what about single flit packets - test
\t\t assert (!vc_alloc_status_reg[oh2bin(flit.control.vc_id)]);
\t\t
\t\t vc_alloc_status_reg[oh2bin(flit.control.vc_id)]<=1\'b1;
\t end
\t end
\t end // always@ (posedge clk)
\t if (only_allocate_vc_when_empty) begin
\t assign vc_alloc_status = vc_alloc_status_reg & vc_empty;
\t end else begin
\t assign vc_alloc_status = vc_alloc_status_reg;
\t end
end
endgenerate
endmodule // NW_vc_free_pool
|
\r
/* -------------------------------------------------------------------------------\r
* (C)2007 Robert Mullins\r
* Computer Architecture Group, Computer Laboratory\r
* University of Cambridge, UK.\r
* -------------------------------------------------------------------------------\r
*\r
* FIFO\r
* ====\r
*\r
* Implementation notes:\r
* \r
* - Read and write pointers are simple ring counters\r
* \r
* - Number of items held in FIFO is recorded in shift register\r
* (Full/empty flags are most and least-significant bits of register)\r
* \r
* - Supports input and/or output registers on FIFO\r
* \r
* Examples:\r
* \r
* fifo_v #(.fifo_elements_t(int), .size(8)) myfifo (.*);\r
* \r
* Instantiates a FIFO that can hold up to 8 integers.\r
* \r
* fifo_v #(.fifo_elements_t(int), .size(8), .output_reg(1)) myfifo (.*);\r
* \r
* Instantiates a FIFO that can hold up to 8 integers with output register\r
* \r
* Output Register\r
* ===============\r
* \r
* Instantiate a FIFO of length (size-1) + an output register and bypass logic\r
* \r
* output_reg = 0 (default) - no output register\r
* output_reg = 1 - instantiate a single output register\r
* \r
* _\r
* ______ |\\ | |\r
* _|-[_FIFO_]-->| |__| |__ Out\r
* |----------->| | |_|\r
* bypass |/ Reg.\r
*\r
* \r
* Input Register\r
* ==============\r
* \r
* input_reg = 0 (default) - no input register, FIFO receives data directly\r
* input_reg = 1 - assume **external** input register and bypass logic \r
* input_reg = 2 - instantiate input register and bypass logic \r
* \r
* In case 1. the FIFO is still of length \'size\' as it is assumed the external\r
* input register is always enabled (used when building VC buffers).\r
* \r
* _ ______ |\\\r
* | | |-[_FIFO_]-->| |___ Out\r
* | |__|___________>| |\r
* |_| |/\r
* Reg.\r
* \r
* Input and Output Registers\r
* ==========================\r
* \r
* Can set input_reg=2, output_reg=1 to create FIFO with both input and output\r
* registers. FIFO behaviour remains identical at the cycle-level with the \r
* addition of input/output registers.\r
* \r
* InReg OutReg\r
* _ ______ _ \r
* | |---[_FIFO_]---| |\r
* | | |____________| |___|\\\r
* |_| | |_| | |__ Out\r
* |__________________| |\r
* |/\r
* FIFO Initialisation\r
* ===================\r
* \r
* init_fifo_contents = 0 - FIFO is empty on reset\r
* init_fifo_contents = 1 - FIFO is nearly_full on reset (mem[i]=1\'b1<<i, mem[size]=0)\r
* init_fifo_contents = 2 - FIFO is nearly empty on reset (mem[0]=1)\r
* \r
* \r
* =============================================================================== \r
*/ \r
\r
// other FIFO types: double buffered, two slower FIFOs + output register\r
// FIFOs with second entry outputs (as required by router)\r
// pending write input register\r
//\r
// - second output with output registers [two output registers?]\r
//\r
\r
//`ifdef VCS\r
//import fifo_package::*;\r
//`endif\r
\r
/************************************************************************************\r
*\r
* FIFO \r
*\r
************************************************************************************/\r
\r
typedef struct packed\r
{\r
logic full, empty, nearly_full, nearly_empty;\r
logic fast_empty;\r
} fifov_flags_t;\r
\r
\r
typedef flit_t fifo_elements_t;\r
\r
\r
module NW_fifo_v (push, pop, data_in, data_out, second_data_out, flags, clk, rst_n);\r
\r
// initialise FIFO contents? (usually no initialisation, set to 0)\r
parameter init_fifo_contents = 0;\r
// Type of FIFO elements\r
//parameter type fifo_elements_t = integer ;\r
\r
//parameter fifo_elements_t = integer ;\r
// max no. of entries\r
parameter size = 8;\r
// opt. delay between clk+ and data becoming valid on output of FIFO?\r
parameter output_reg = 1;\r
// external input register and bypass logic? or (2) internal input register\r
parameter input_reg = 0;\r
// trade performance for power savings? (may degrade performance in some cases!) - rename late_pop?\r
parameter low_power = 0;\r
// need second data out?\r
parameter generate_second_data_out = 1;\r
\r
input push, pop;\r
output fifov_flags_t flags;\r
input fifo_elements_t data_in;\r
output fifo_elements_t data_out, second_data_out;\r
input clk, rst_n;\r
\r
fifo_elements_t second;\r
\r
logic is_push, select_bypass, fifo_push, fifo_pop;\r
fifo_elements_t in_reg, fifo_data_out;\r
\r
generate\r
if (input_reg==0) begin\r
\r
fifo_r #(.init_fifo_contents(init_fifo_contents),\r
\t //.fifo_elements_t(fifo_elements_t),\r
\t .size(size),\r
\t .output_reg(output_reg),\r
\t .low_power(low_power)) fifo_r\r
\t(push, pop, data_in, data_out, second, clk, rst_n);\r
\r
end else if (input_reg==1) begin\r
\r
//\r
// instantiate FIFO which can be used with *external* input register and bypass\r
//\t\t\t\r
fifo_r #(.init_fifo_contents(init_fifo_contents),\r
\t //.fifo_elements_t(fifo_elements_t),\r
\t .size(size),\r
\t .output_reg(output_reg),\r
\t .low_power(low_power)) fifo_r\r
\t(fifo_push, fifo_pop, data_in, data_out, second, clk, rst_n);\r
\r
end else if (input_reg==2) begin \r
\r
//\r
// instantiate FIFO and input register and bypass\r
//\t\t\t\r
fifo_r #(.init_fifo_contents(init_fifo_contents),\r
\t // .fifo_elements_t(fifo_elements_t),\r
\t .size(size),\r
\t .output_reg(output_reg),\r
\t .low_power(low_power)) fifo_r\r
\t(fifo_push, fifo_pop, in_reg, fifo_data_out, second, clk, rst_n);\r
\r
//\r
// instantiate input register and bypass (input_reg==2)\r
//\r
always@(posedge clk) \r
\tbegin\r
if (!rst_n) begin\r
in_reg<=\'0;\r
end else begin\r
\t if (push) begin\r
\t\tin_reg<=data_in;\r
\t end else\r
\t\tin_reg<=\'0; // rdm34\r
\t end\r
\tend\r
\r
assign data_out = (select_bypass) ? in_reg : fifo_data_out;\r
end \r
\r
endgenerate\r
\r
generate\r
//\r
// if input_reg==0, push and pop are used directly\r
//\r
if (!low_power && !(output_reg && input_reg!=0)) begin\r
/* Always write even if data bypassed FIFO altogether. May reduce router\r
\t cycle time in cases where \'fifo_push\' is generated late in the clock\r
\t cycle. Downside - this wastes energy */\r
\t assign fifo_push = is_push;\r
\t assign fifo_pop = pop;\r
end else begin\r
\t // only copy input register contents to FIFO if there was a push operation\r
\t // and contents didn\'t bypass FIFO altogether\r
\t assign fifo_push = is_push && !(select_bypass && pop);\r
\t // similarly for pop, only pop if we aren\'t bypasses the FIFO\r
\t assign fifo_pop = pop && !select_bypass;\r
end\r
endgenerate\r
\r
always@(posedge clk) begin\r
\r
if (!rst_n) begin\r
\t is_push <= 1\'b0;\r
\t select_bypass <= 1\'b1;\r
end else begin\r
\t is_push <= push;\r
\r
\t select_bypass <= flags.empty || (flags.nearly_empty && pop);\r
end\r
end\r
\r
/************************************************************************************\r
* Generate Flags for FIFO (flags are always generated for a FIFO of length \'size\')\r
************************************************************************************/\r
fifo_flags #(.size(size), \r
\t\t.init_fifo_contents(init_fifo_contents)) genflags \r
(push, pop, flags, clk, rst_n);\r
\r
/************************************************************************************\r
* Need second data out?\r
************************************************************************************/\r
generate\r
if (generate_second_data_out) begin\r
\t assign second_data_out = second;\r
end else begin\r
\t assign second_data_out = \'x;\r
end\r
endgenerate\r
endmodule // fifo_v\r
\r
\r
/************************************************************************************\r
*\r
* FIFO + Output Register (if requested)\r
* \r
************************************************************************************/\r
\r
module fifo_r (push, pop, data_in, data_out, second_data_out, clk, rst_n);\r
\r
// initialise FIFO\r
parameter init_fifo_contents = 0;\r
// what does FIFO hold?\r
//parameter type fifo_elements_t = int ;\r
// max no. of entries\r
parameter size = 8;\r
// opt. delay between clk+ and data becoming valid on output of FIFO?\r
parameter output_reg = 1;\r
// trade power for performance\r
parameter low_power = 0;\r
\r
// \'always_write\'\r
// regardless of \'push\' always write input data to FIFO slot pointed to by write\r
// pointer (one extra entry is added to FIFO to ensure FIFO data is not overwritten).\r
parameter always_write = 1\'b0; //!low_power;\r
\r
//==========\r
\r
input push, pop;\r
input fifo_elements_t data_in;\r
output fifo_elements_t data_out, second_data_out;\r
input clk, rst_n;\r
\r
fifov_flags_t local_flags;\r
\r
fifo_elements_t fifo_data_out, second_data;\r
fifo_elements_t fifo_out_reg;\r
\r
fifo_elements_t to_reg;\r
\r
logic bypass, fifo_push, fifo_pop;\r
\r
generate\r
if (!output_reg) begin\r
\r
fifo_buffer #(.init_fifo_contents(init_fifo_contents), \r
\t\t //.fifo_elements_t(fifo_elements_t), \r
\t\t .size(always_write+size), .output_reg(0), \r
\t\t .low_power(low_power), .always_write(always_write))\r
fifo_buf (push, pop, data_in, data_out, second_data, clk, rst_n);\r
\r
assign second_data_out = second_data;\r
\r
end else begin\r
//\r
// FIFO + output register \r
//\r
fifo_buffer #(.init_fifo_contents(init_fifo_contents),\r
\t\t //.fifo_elements_t(fifo_elements_t), \r
\t\t .size(always_write+size), .output_reg(0), .low_power(low_power),\r
\t\t .always_write(always_write))\r
fifo_buf (push, pop, data_in, fifo_data_out, second_data, clk, rst_n);\r
\r
//\r
// local flags to determine when to bypass, read and write FIFO\r
//\r
// *rdm34, better if we could use global flags, are these flags ever on critical path?\r
//\r
fifo_flags #(.size(always_write+size), \r
\t\t .init_fifo_contents(init_fifo_contents)) gen_localflags\r
\t(push, pop, local_flags, clk, rst_n); \r
\r
always@(posedge clk) begin\r
\t if (!rst_n) begin\r
// initialise FIFO contents?\r
if (init_fifo_contents!=0) begin\r
fifo_out_reg<=1;\r
end\r
\t end else begin\r
\t fifo_out_reg<=to_reg;\r
\r
\t /*\r
if (local_flags.empty || (local_flags.nearly_empty && pop)) begin\r
if (push) begin\r
\t\t fifo_out_reg<=data_in;\r
end else begin\r
\t\t // fifo_out_reg<=\'0; // FIFO is empty\r
end\r
end else if (pop) begin\r
fifo_out_reg<=second_data;\r
end else begin\r
fifo_out_reg<=fifo_data_out;\r
end\r
\t */\r
\t \r
\t end // else: !if(!rst_n)\r
end // always@ (posedge clk)\r
\r
// select data to write to fifo_out_reg\r
always_comb\r
\tbegin\r
if (local_flags.empty || (local_flags.nearly_empty && pop)) begin\r
if (push) begin\r
\t\t to_reg = data_in;\r
end else begin\r
\t\t // FIFO is empty\r
\t\t //if (init_fifo_contents!=0) to_reg=\'0; else to_reg=\'x;\r
\t\t to_reg = \'0;\r
end\r
end else if (pop) begin\r
\t to_reg = second_data;\r
end else begin\r
to_reg = fifo_data_out;\r
end\r
\tend\r
\r
assign data_out = fifo_out_reg;\r
assign second_data_out = second_data;\r
\r
end\r
endgenerate\r
\r
endmodule // fifo_r\r
\r
/************************************************************************************\r
*\r
* Maintain FIFO flags (full, nearly_full, nearly_empty and empty)\r
* \r
* This design uses a shift register to ensure flags are available quickly.\r
* \r
************************************************************************************/\r
\r
module fifo_flags (push, pop, flags, clk, rst_n);\r
input push, pop;\r
output fifov_flags_t flags;\r
input clk, rst_n;\r
\r
parameter size = 8;\r
parameter init_fifo_contents = 0;\r
\r
reg [size:0] counter; // counter must hold 1..size + empty state\r
\r
logic \t was_push, was_pop;\r
\r
fifov_flags_t flags_reg;\r
logic \t add, sub, same;\r
\r
logic \t fast_empty;\r
\r
/*\r
* maintain flags\r
*\r
*\r
* maintain shift register as counter to determine if FIFO is full or empty\r
* full=counter[size-1], empty=counter[0], etc..\r
* init: counter=1\'b1;\r
* (push & !pop): shift left\r
* (pop & !push): shift right\r
*/\r
\r
always@(posedge clk) begin\r
if (!rst_n) begin\r
\t \r
\t //\r
\t // initialise flags counter on reset\r
\t //\r
\t if (init_fifo_contents==2) begin\r
\t // nearly_empty\r
\t counter<={{(size-1){1\'b0}},2\'b10};\r
\t end else if (init_fifo_contents==1) begin\r
\t // nearly_full\r
\t counter<={2\'b01,{(size-1){1\'b0}}}; \r
\t end else begin\r
\t // empty\r
\t counter<={{size{1\'b0}},1\'b1};\r
\t end\r
\r
\t was_push<=1\'b0;\r
\t was_pop<=1\'b0;\r
\r
\t fast_empty <=1\'b1;\r
\t \r
end else begin\r
\t if (add) begin\r
\t assert (counter!={1\'b1,{size{1\'b0}}}) else $fatal;\r
\t counter <= {counter[size-1:0], 1\'b0};\r
\t end else if (sub) begin\r
\t assert (counter!={{size{1\'b0}},1\'b1}) else $fatal;\r
\t counter <= {1\'b0, counter[size:1]};\r
\t end\r
\t \r
\t assert (counter!=0) else $fatal;\r
\r
\t was_push<=push;\r
\t was_pop<=pop;\r
\r
\t assert (push!==1\'bx) else $fatal;\r
\t assert (pop!==1\'bx) else $fatal;\r
\r
\t fast_empty <= (flags.empty && !push && !pop) || (flags.nearly_empty && pop && !push);\r
\t \r
end // else: !if(!rst_n)\r
\r
end\r
\r
assign add = was_push && !was_pop;\r
assign sub = was_pop && !was_push;\r
assign same = !(add || sub);\r
\r
assign flags.full = (counter[size] && !sub) || (counter[size-1] && add);\r
assign flags.empty = (counter[0] && !add) || (counter[1] && sub);\r
\r
assign flags.nearly_full = (counter[size-1:0] && same) || (counter[size] && sub) || (counter[size-2] && add);\r
assign flags.nearly_empty = (counter[1] && same) || (counter[0] && add) || (counter[2] && sub);\r
\r
assign flags.fast_empty = fast_empty;\r
\r
/*\r
always@(posedge clk) begin\r
if (size>3) begin\r
\t if (rst_n) begin\r
\r
\t if ((flags.full && flags.empty)||\r
\t\t(flags.full && flags.nearly_empty)||\r
\t\t(flags.full && flags.nearly_full)||\r
\t\t(flags.nearly_full && flags.nearly_empty) ||\r
\t\t(flags.nearly_full && flags.empty) ||\r
\t\t(flags.nearly_empty && flags.empty)) begin\r
\r
\t $display ("%d: %m", $time);\r
\t \r
\t $display ("flags.full =%b", flags.full);\r
\t $display ("flags.nfull=%b (counter[size, -1, -2]=%b, %b, %b)", \r
\t\t\t flags.nearly_full, counter[size], counter[size-1], counter[size-2]);\r
\t $display ("flags.nempt=%b", flags.nearly_empty);\r
\t $display ("flags.empt =%b", flags.empty);\r
\t $display ("Counter=%b", counter);\r
\t end\r
\t end\r
end\r
end\r
*/\r
\r
endmodule // fifo_flags\r
\r
/************************************************************************************\r
*\r
* Simple core FIFO module\r
* \r
************************************************************************************/\r
\r
module fifo_buffer (push, pop, data_in, data_out, second_data_out, clk, rst_n);\r
\r
// initialise FIFO\r
parameter init_fifo_contents = 0;\r
// what does FIFO hold?\r
//parameter type fifo_elements_t = logic ;\r
// max no. of entries\r
parameter int unsigned size = 4;\r
// part of fast read FIFO?\r
parameter output_reg = 0;\r
// trade power for performance\r
parameter low_power = 0;\r
// write input data to FIFO[wt_ptr] every clock cycle regardless of \'push\'\r
parameter always_write = 0;\r
\r
input push, pop;\r
input fifo_elements_t data_in;\r
output fifo_elements_t data_out;\r
output fifo_elements_t second_data_out;\r
input clk, rst_n;\r
\r
// reg [size-1:0] rd_ptr, wt_ptr;\r
logic unsigned [size-1:0] rd_ptr, wt_ptr;\r
\r
fifo_elements_t fifo_mem[0:size-1];\r
\r
logic select_bypass;\r
\r
integer i,j;\r
\r
always@(posedge clk) begin\r
\r
assert (size>=2) else $fatal();\r
\r
if (!rst_n) begin\r
\t //\r
\t // reset read and write pointers\r
\t //\r
\t if ((init_fifo_contents==2)&&(output_reg==0)) begin\r
\t // initialise with single entry set to 1\r
\t fifo_mem[0]<=1;\r
\t rd_ptr<={{size-1{1\'b0}},1\'b1};\r
wt_ptr <= {{size-2{1\'b0}},2\'b10};\r
\t end else if (init_fifo_contents==1) begin\r
\t // initialise FIFO full (contents 1\'b1<<(i+output_reg))\r
\t for (i=0; i<size-1; i=i+1) begin\r
\t fifo_mem[i]<=1\'b1<<(i+output_reg);\r
\t end\r
\t rd_ptr<={{size-1{1\'b0}},1\'b1};\r
wt_ptr<={1\'b1,{size-1{1\'b0}}}; \r
\t end else begin\r
\t //\r
\t // initialise empty FIFO\r
\t //\r
\t rd_ptr<={{size-1{1\'b0}},1\'b1};\r
wt_ptr<={{size-1{1\'b0}},1\'b1};\r
\t end\r
\t \r
end else begin\r
\r
\t if (push || always_write) begin\r
\t // enqueue new data\r
\t for (i=0; i<size; i++) begin\r
\t if (wt_ptr[i]==1\'b1) begin\r
\t\t fifo_mem[i] <= data_in;\r
\t end\r
\t end\r
\t end\r
\r
\t if (push) begin\r
\t // rotate write pointer\r
\t wt_ptr <= {wt_ptr[size-2:0], wt_ptr[size-1]};\r
\t end\r
\t \r
\t if (pop) begin\r
\t // rotate read pointer\r
rd_ptr <= {rd_ptr[size-2:0], rd_ptr[size-1]};\t \r
\t end\r
\t \r
end // else: !if(!rst_n)\r
end // always@ (posedge clk)\r
\r
/*\r
*\r
* FIFO output is item pointed to by read pointer \r
* \r
*/\r
always_comb begin\r
//\r
// one bit of read pointer is always set, ensure synthesis tool \r
// doesn\'t add logic to force a default\r
//\r
data_out = \'x; \r
second_data_out =\'x;\r
\r
for (j=0; j<size; j++) begin\r
\t if (rd_ptr[j]==1\'b1) begin\r
\r
\t // output entry pointed to by read pointer\r
\t data_out = fifo_mem[j];\r
\t \r
\t // output next entry after head\r
\t if ((j+1)==size) begin\r
\t second_data_out = fifo_mem[0];\r
\t end else begin\r
\t second_data_out = fifo_mem[j+1];\r
\t end\r
\r
\t end\r
end \r
\r
end\r
\r
endmodule // fifo_buffer\r
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Simple/useful components
*
*/
//
// Register
//
/*module NW_reg (data_in, data_out, clk, rst_n);
parameter type reg_t = byte;
input reg_t data_in;
output reg_t data_out;
input clk, rst_n;
always@(posedge clk) begin
if (!rst_n) begin
\t data_out<='0;
end else begin
\t data_out<=data_in;
end
end
endmodule */ // NW_reg
//
// Multiplexer with one-hot encoded select input
//
// - output is '0 if no select input is asserted
//
\r
module NW_mux_oh_select (data_in, select, data_out);
//parameter type dtype_t = byte;
parameter n = 4;
input fifo_elements_t data_in [n-1:0];
input [n-1:0] select;
output fifo_elements_t data_out;
int i;
always_comb
begin
\tdata_out='0;
\tfor (i=0; i<n; i++) begin
\t if (select[i]) data_out = data_in[i];
\tend
end
endmodule // NW_mux_oh_select
//
// Crossbar built from multiplexers, one-hot encoded select input
//\r
module NW_crossbar_oh_select (data_in, select, data_out);
//parameter type dtype_t = byte;
parameter n = 4;
input flit_t data_in [n-1:0];
// select[output][select-input];
input [n-1:0][n-1:0] select; // n one-hot encoded select signals per output
output flit_t data_out [n-1:0];
genvar i;
generate
for (i=0; i<n; i++) begin:outmuxes
\t NW_mux_oh_select #( .n(n)) xbarmux (data_in, select[i], data_out[i]);
end
endgenerate
endmodule // NW_crossbar_oh_select
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Virtual-channel allocation arbiter
*
* This VC arbiter simply consists of one arbiter per output-port.
* Each arbiter has np*nv inputs.
*
*/
module NW_vc_arbiter (request,
\t\t req_priority,
\t\t grant,
\t\t vc_allocated,
//\t\t vcreq_foroutput,
\t\t clk, rst_n);
parameter np=5;
parameter nv=4;
parameter multistage=2;
parameter dynamic_priority_vc_alloc=0;
//parameter type flit_priority_t = flit_pri_t;
input [np-1:0][nv-1:0][np-1:0] request;
input flit_priority_t req_priority [np-1:0][nv-1:0];
output [np-1:0][nv-1:0][np-1:0] grant;
// was VC allocated? previous grant was successful! use new arb. state (make sure things are fair)
input [np-1:0] \t vc_allocated;
input clk, rst_n;
// inputs and outputs to matrix arbiters
wire [np*nv-1:0] output_req [np-1:0];
wire [np*nv-1:0] output_grant [np-1:0];
genvar ip, vc, op;
generate
for (ip=0; ip<np; ip=ip+1) begin:i
for (vc=0; vc<nv; vc=vc+1) begin:v
\t for (op=0; op<np; op=op+1) begin:o
\t // generate inputs to arbiters
\t assign output_req[op][ip*nv+vc] = (NW_route_valid_turn(ip, op)) ? request[ip][vc][op] : 1'b0;
\t // put output signals in correct order
\t assign grant[ip][vc][op]=output_grant[op][ip*nv+vc];
\t end
end
end
//
// np x np*nv-input matrix arbiters
//
for (op=0; op<np; op=op+1) begin:o2
NW_tree_arbiter #(.multistage(multistage),
\t\t\t.size(np*nv),
\t\t\t.groupsize(nv),
\t\t\t.priority_support(dynamic_priority_vc_alloc)\r
\t\t\t//,
\t\t\t//.priority_type(flit_priority_t)\r
\t\t\t) vcarb
\t(.request(output_req[op]),
\t .req_priority(req_priority),
\t .grant(output_grant[op]),
\t .success(vc_allocated[op]),// be careful
\t .clk, .rst_n);
// assign vcreq_foroutput[op]=|output_req[op];
end
endgenerate
endmodule // precomp_vc_alloc
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* VC allocator
*
* Allocates new virtual-channels for newly arrived packets.
*
* Supported VC allocation architectures:
*
* (A) "fifo_free_pool" - Free VC pool is organised as a FIFO, at most one VC
* may be allocated per output port per clock cycle
*
* In this case we just need P x PV:1 arbiters
*
* (B) "unrestricted" - Peh/Dally style VC allocation.
* Takes place in two stages:
*
* stage 1. Each waiting packet determines which VC it will request.
* (v:1 arbitration). Can support VC alloc. mask here (from
* packet header or static or dynamic..)
*
*
* stage 2. Access to each output VC is arbitrated (PV x PV:1 arbiters)
*
*/
module NW_vc_allocator (req, output_port, // VC request, for which port?
\t\t\treq_priority, // prioritized requests?
\t\t\tvc_new, vc_new_valid, // newly allocated VC ids
\t\t\t// ** restricted FIFO case **
\t\t\tnext_free_vc, // next free VC at each output port
\t\t\tno_free_vc, // free VC fifo empty?
\t\t\tpop_free_vc, // VC consumed at output port
\t\t\t// ** unrestricted case **
\t\t\tvc_mask, // which VCs is input VC permitted to request
//\t\t\tvc_sel_priority, // Priorities for VC selection stage
\t\t\tvc_allocated, // which VCs were allocated on this cycle?
\t\t\tvc_requested, // which VCs were requested by each input VC?
\t\t\tvc_alloc_status, // which VCs are free?
\t\t\tflit, // head of each VC buffer
\t\t\tvc_credits, // Credits available at each VC at each output port
\t\t\tclk, rst_n);
`include "NW_functions.v"
//parameter type flit_priority_t = flit_pri_t;
parameter buf_len=4;
parameter xs=4;
parameter ys=4;
\t\t
parameter np=5;
parameter nv=4;
parameter dynamic_priority_vc_alloc = 0;
parameter vcalloc_unrestricted = 0;
// specifically for unrestricted VC pool case
// parameter type vc_priority_t = bit unsigned [2:0];
// parameter prioritize_vc_selection = 0;
// parameter use_vc_allocation_mask = 1;
parameter vcselect_bydestinationnode = 0;
parameter vcselect_leastfullbuffer = 0;
parameter vcselect_arbstateupdate = 0;
parameter vcselect_usepacketmask = 0;
//-----
input [np-1:0][nv-1:0] req;
input flit_priority_t req_priority [np-1:0][nv-1:0];
input output_port_t output_port [np-1:0][nv-1:0];
input [np-1:0][nv-1:0] next_free_vc;
input [np-1:0] no_free_vc; // free VC fifo empty?
output [np-1:0][nv-1:0][nv-1:0] vc_new;
output [np-1:0][nv-1:0] vc_new_valid;
output [np-1:0] pop_free_vc;
input [np-1:0][nv-1:0][nv-1:0] vc_mask;
// input vc_priority_t vc_sel_priority [np-1:0][nv-1:0][nv-1:0];
output [np-1:0][nv-1:0] vc_allocated;
output [np-1:0][nv-1:0][nv-1:0] vc_requested;
input [np-1:0][nv-1:0] vc_alloc_status;
input flit_t flit [np-1:0][nv-1:0];
input [np-1:0][nv-1:0][clogb2(buf_len+1)-1:0] vc_credits;
input clk, rst_n;
generate
if (!vcalloc_unrestricted) begin
\t /*NW_vc_restricted_allocator
\t #(.np(np), .nv(nv),
\t .dynamic_priority_vc_alloc(dynamic_priority_vc_alloc))
\t restricted
\t (
\t\t.req,
\t\t.output_port,
\t\t.req_priority,
\t\t.vc_new,
\t\t.vc_new_valid,
\t\t.next_free_vc,
\t\t.no_free_vc,
\t\t.pop_free_vc,
\t\t.clk, .rst_n
\t\t);*/
end else begin // if (!vcalloc_unrestricted)
\t
\t NW_vc_unrestricted_allocator
\t #(.np(np), .nv(nv), .xs(xs), .ys(ys), .buf_len(buf_len),
\t .dynamic_priority_vc_alloc(dynamic_priority_vc_alloc),
\t .vcselect_bydestinationnode(vcselect_bydestinationnode),
\t .vcselect_leastfullbuffer(vcselect_leastfullbuffer),
\t .vcselect_arbstateupdate(vcselect_arbstateupdate),
\t .vcselect_usepacketmask(vcselect_usepacketmask))
\t unrestricted
\t (
\t\t.req,
\t\t.output_port,
\t\t//.vc_mask,
\t\t.req_priority,
//\t\t.vc_sel_priority,
\t\t.vc_status(vc_alloc_status),
\t\t.vc_new,
\t\t.vc_new_valid,
\t\t.vc_allocated,
\t\t.vc_requested,
\t\t.flit, .vc_credits,
\t\t.clk, .rst_n
\t\t);
end
endgenerate
endmodule // NW_vc_allocator
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Virtual-Channel Buffers
* =======================
*
* Instantiates \'N\' FIFOs in parallel, if \'push\' is asserted
* data_in is sent to FIFO[vc_id].
*
* The output is determined by an external \'select\' input.
*
* if \'pop\' is asserted by the end of the clock cycle, the
* FIFO that was read (indicated by \'select\') recieves a
* pop command.
*
* - flags[] provides access to all FIFO status flags.
* - output_port[] provides access to \'output_port\' field of flits at head of FIFOs
*
* Assumptions:
* - \'vc_id\' is binary encoded (select is one-hot) //and \'select\' are binary encoded.
*
*/
module NW_vc_buffers (push, pop, data_in, vc_id, select,
\t\t data_out, output_port, data_in_reg,
\t\t flags, buf_finished_empty,
\t\t head_is_tail, flit_buffer_out,
\t\t clk, rst_n);
`include "NW_functions.v"
// length of VC FIFOs
parameter size = 3;
// number of virtual channels
parameter n = 4;
// what does each FIFO hold?
//parameter type fifo_elements_t = flit_t;
// optimize FIFO parameters for different fields of flit
parameter optimize_fifo_fields = 0;
// export output of each VC buffer
parameter output_all_head_flits = 0;
input push;
input [n-1:0] pop;
input fifo_elements_t data_in;
input [clogb2(n)-1:0] vc_id;
// input [clogb2(n)-1:0] select;
input [n-1:0] \t select;
output fifo_elements_t data_out;
output fifov_flags_t flags [n-1:0];
output output_port_t output_port [n-1:0];
output flit_t data_in_reg;
output fifo_elements_t flit_buffer_out [n-1:0];
output [n-1:0] head_is_tail;
// at the end of the last clock cycle was vc_buffer[i] empty?
// - i.e. is the next flit entering an empty FIFO
// used for various things, e.g. abort detection
output [n-1:0] buf_finished_empty;
input clk, rst_n;
// logic [clogb2(n)-1:0] select_bin;
fifo_elements_t sel_fifo_out;
// single input register
fifo_elements_t in_reg;
// fifo outputs
fifo_elements_t fifo_out [n-1:0];
// fifo push/pop control
logic [n-1:0] push_fifo, pop_fifo;
// need to bypass FIFO and output contents of input register?
logic [n-1:0] fifo_bypass;
logic [n-1:0] fifo_bypass2;
output_port_t op_fifo_out [n-1:0];
control_flit_t control_fifo_out [n-1:0];
genvar i;
integer j;
assign data_in_reg = in_reg;
assign buf_finished_empty = fifo_bypass;
// assign select_bin = vc_index_t\'(oh2bin(select));
generate
for (i=0; i<n; i++) begin:vcbufs
if (optimize_fifo_fields) begin
\t //
\t // use multiple FIFOs for different fields of flit so there
\t // parameters can be optimized individually. Allows us to
\t // move logic from start to end of clock cycle and vice-versa -
\t // depending on what is on critical path.
\t //
\t //
\t // break down into control and data fields
\t //
\t // *** CONTROL FIFO ***
\t NW_fifo_v #(.init_fifo_contents(0),
\t\t //.fifo_elements_t(control_flit_t),
\t\t .size(size),
\t\t .output_reg(0),
\t\t .input_reg(1) // must be 1 - assume external input reg.
\t\t ) vc_fifo_c
\t (.push(push_fifo[i]),
\t .pop(pop_fifo[i]),
\t .data_in(in_reg.control),
\t .data_out(control_fifo_out[i]),
\t .flags(flags[i]),
\t .clk, .rst_n);
\t // *** OUTPUT PORT REQUEST ONLY ***
\t NW_fifo_v #(.init_fifo_contents(0),
\t\t //.fifo_elements_t(output_port_t),
\t\t .size(size),
\t\t .output_reg(1),
\t\t .input_reg(1) // must be 1 - assume external input reg.
\t\t ) vc_fifo_op
\t (.push(push_fifo[i]),
\t .pop(pop_fifo[i]),
\t .data_in(in_reg.control.output_port),
\t .data_out(op_fifo_out[i]),
//\t .flags(flags[i]),
\t .clk, .rst_n);
\t always_comb
\t begin
\t fifo_out[i].control = control_fifo_out[i];
\t fifo_out[i].control.output_port = op_fifo_out[i];
\t end
\t
\t // *** DATA FIFO ***
\t NW_fifo_v #(.init_fifo_contents(0),
\t\t //.fifo_elements_t(data_t),
\t\t .size(size),
\t\t .output_reg(0), // remove FIFO output register ****
\t\t .input_reg(1) // must be 1 - assume external input reg.
\t\t ) vc_fifo_d
\t (.push(push_fifo[i]),
\t .pop(pop_fifo[i]),
\t .data_in(in_reg.data),
\t .data_out(fifo_out[i].data),
//\t .flags(flags[i]), only need one set of flags (obviously identical to control FIFO\'s)
\t .clk, .rst_n);
`ifdef DEBUG
\t // need FIFO for debug too
\t NW_fifo_v #(.init_fifo_contents(0),
\t\t //.fifo_elements_t(debug_flit_t),
\t\t .size(size),
\t\t .output_reg(1),
\t\t .input_reg(1)
\t\t ) vc_fifo
\t (.push(push_fifo[i]),
\t .pop(pop_fifo[i]),
\t //.data_in(in_reg.debug),
\t //.data_out(fifo_out[i].debug),
//\t .flags(flags[i]),
\t .clk, .rst_n);
`endif
\t
end else begin
\t // **********************************
\t // SINGLE FIFO holds complete flit
\t // **********************************
\t NW_fifo_v #(.init_fifo_contents(0),
\t\t //.fifo_elements_t(fifo_elements_t),
\t\t .size(size),
\t\t .output_reg(0),
\t\t .input_reg(1)
\t\t ) vc_fifo
\t (.push(push_fifo[i]),
\t .pop(pop_fifo[i]),
\t .data_in(in_reg),
\t .data_out(fifo_out[i]),
\t .flags(flags[i]),
\t .clk, .rst_n);
end
\t
always@(posedge clk) begin
\t if (!rst_n) begin
\t fifo_bypass[i] <= 1\'b1;
\t
\t fifo_bypass2[i] <= 1\'b1; // duplicate
\t end else begin
\t fifo_bypass[i] <= flags[i].empty || (flags[i].nearly_empty && pop_fifo[i]);
\t fifo_bypass2[i] <= flags[i].empty || (flags[i].nearly_empty && pop_fifo[i]); // duplicate
\t end
end
assign push_fifo[i] = push & (vc_id==i);
assign pop_fifo[i] = pop[i]; //pop & (select==i);
assign head_is_tail[i] = fifo_out[i].control.tail; // && !flags[i].empty;
// we need to know which output port is required by all packets, in order to make
// virtual-channel and switch allocation requests.
assign output_port[i] =
\t fifo_bypass2[i] ? in_reg.control.output_port : fifo_out[i].control.output_port;
end
endgenerate
//
// assign data_out = (fifo_bypass[select]) ? in_reg : fifo_out[select];
//
NW_mux_oh_select #( .n(n))
fifosel (.data_in(fifo_out), .select(select), .data_out(sel_fifo_out));
assign sel_fifo_bypass = |(fifo_bypass & select);
assign data_out = sel_fifo_bypass ? in_reg : sel_fifo_out; //fifo_out[select_bin];
//
// some architectures require access to head of all VC buffers
//
generate
if (output_all_head_flits) begin
\t for (i=0; i<n; i++) begin:allvcs
\t assign flit_buffer_out[i] = (fifo_bypass[i]) ? in_reg : fifo_out[i];
\t end
end
endgenerate
//
// in_reg
//
always@(posedge clk) begin
if (!rst_n) begin
\t in_reg.control.valid <= 1\'b0;
\t in_reg.control.tail <= 1\'b1;
\t in_reg.control.output_port <=\'0;
end else begin
\t if (push) begin
\t in_reg <= data_in;
\t end else begin
\t in_reg.control.valid<=1\'b0;
\t in_reg.control.output_port<=\'0;
\t end
end
end
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module hex_display (
input [15:0] num,
input en,
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3
);
// Module instantiations
seg_7 hex_group0 (
.num (num[3:0]),
.en (en),
.seg (hex0)
);
seg_7 hex_group1 (
.num (num[7:4]),
.en (en),
.seg (hex1)
);
seg_7 hex_group2 (
.num (num[11:8]),
.en (en),
.seg (hex2)
);
seg_7 hex_group3 (
.num (num[15:12]),
.en (en),
.seg (hex3)
);
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// div_pipelined.v\r
// Created: 4.3.2012\r
// Modified: 4.5.2012\r
//\r
// Testbench for div_pipelined.v\r
//\r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module t_div_pipelined();\r
\r
reg clk, start, reset_n;\r
reg [7:0] dividend, divisor;\r
wire data_valid, div_by_zero;\r
wire [7:0] quotient, quotient_correct;\r
\r
parameter\r
BITS = 8;\r
\r
div_pipelined\r
#(\r
.BITS(BITS)\r
)\r
div_pipelined\r
(\r
.clk(clk),\r
.reset_n(reset_n),\r
.dividend(dividend),\r
.divisor(divisor),\r
.quotient(quotient),\r
.div_by_zero(div_by_zero),\r
// .quotient_correct(quotient_correct),\r
.start(start),\r
.data_valid(data_valid)\r
);\r
\r
initial begin\r
#10 reset_n = 0;\r
#50 reset_n = 1;\r
#1\r
clk = 0;\r
dividend = -1;\r
divisor = 127;\r
#1000 $finish;\r
end\r
\r
// always\r
// #20 dividend = dividend + 1;\r
\r
always begin\r
#10 divisor = divisor - 1; start = 1;\r
#10 start = 0;\r
end\r
\r
always\r
#5 clk = ~clk;\r
\r
\r
endmodule\r
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// button_debounce.v\r
// Created: 10/10/2009\r
// Modified: 3/20/2012\r
//\r
// Counter based debounce circuit originally written for EC551 (back\r
// in the day) and then modified (i.e. chagned entirely) into 3 always\r
// block format. This debouncer generates a signal that goes high for\r
// 1 clock cycle after the clock sees an asserted value on the button\r
// line. This action is then disabled until the counter hits a\r
// specified count value that is determined by the clock frequency and\r
// desired debounce frequency. An alternative implementation would not\r
// use a counter, but would use the shift register approach, looking\r
// for repeated matches (say 5) on the button line.\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module button_debounce\r
(\r
input clk, // clock\r
input reset_n, // asynchronous reset \r
input button, // bouncy button\r
output reg debounce // debounced 1-cycle signal\r
);\r
\r
parameter\r
CLK_FREQUENCY = 66000000,\r
DEBOUNCE_HZ = 2;\r
// These parameters are specified such that you can choose any power\r
// of 2 frequency for a debouncer between 1 Hz and\r
// CLK_FREQUENCY. Note, that this will throw errors if you choose a\r
// non power of 2 frequency (i.e. count_value evaluates to some\r
// number / 3 which isn't interpreted as a logical right shift). I'm\r
// assuming this will not work for DEBOUNCE_HZ values less than 1,\r
// however, I'm uncertain of the value of a debouncer for fractional\r
// hertz button presses.\r
localparam\r
COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,\r
WAIT = 0,\r
FIRE = 1,\r
COUNT = 2;\r
\r
reg [1:0] state, next_state;\r
reg [25:0] count;\r
\r
always @ (posedge clk or negedge reset_n)\r
state <= (!reset_n) ? WAIT : next_state;\r
\r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
debounce <= 0;\r
count <= 0;\r
end\r
else begin\r
debounce <= 0;\r
count <= 0;\r
case (state)\r
WAIT: begin\r
end\r
FIRE: begin\r
debounce <= 1;\r
end\r
COUNT: begin\r
count <= count + 1;\r
end\r
endcase \r
end\r
end\r
\r
always @ * begin\r
case (state)\r
WAIT: next_state = (button) ? FIRE : state;\r
FIRE: next_state = COUNT;\r
COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;\r
default: next_state = WAIT;\r
endcase\r
end\r
\r
endmodule\r
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// sign_extender.v\r
// Created: 5.16.2012\r
// Modified: 5.16.2012\r
//\r
// Generic sign extension module\r
//\r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns/1ps\r
module sign_extender\r
#(\r
parameter\r
INPUT_WIDTH = 8,\r
OUTPUT_WIDTH = 16\r
)\r
(\r
input [INPUT_WIDTH-1:0] original,\r
output reg [OUTPUT_WIDTH-1:0] sign_extended_original\r
);\r
\r
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;\r
\r
generate\r
genvar i;\r
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend\r
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;\r
end\r
endgenerate\r
\r
always @ * begin\r
sign_extended_original = {sign_extend,original};\r
end\r
\r
endmodule\r
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
assign dsp_sel[0] = i;
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF3(
.Q(a), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(d), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF2(
.Q(b), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(a), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF1(
.Q(c), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(b), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF0(
.Q(d), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(c), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF7(
.Q(e), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(h), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF6(
.Q(f), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(e), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF5(
.Q(g), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(f), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF4(
.Q(h), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(g), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF11(
.Q(i), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(l), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF10(
.Q(j), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(i), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF9(
.Q(k), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(j), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF8(
.Q(l), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(k), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// pipeline_registers.v\r
// Created: 4.4.2012\r
// Modified: 4.4.2012\r
//\r
// Implements a series of pipeline registers specified by the input\r
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the\r
// size of the signal passed through each of the pipeline\r
// registers. NUMBER_OF_STAGES is the number of pipeline registers\r
// generated. This accepts values of 0 (yes, it just passes data from\r
// input to output...) up to however many stages specified.\r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module pipeline_registers\r
(\r
input clk,\r
input reset_n,\r
input [BIT_WIDTH-1:0] pipe_in,\r
output reg [BIT_WIDTH-1:0] pipe_out\r
);\r
\r
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP\r
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE\r
// OVERWRITTEN!\r
parameter \r
BIT_WIDTH = 10,\r
NUMBER_OF_STAGES = 5;\r
\r
// Main generate function for conditional hardware instantiation\r
generate\r
genvar i;\r
// Pass-through case for the odd event that no pipeline stages are\r
// specified.\r
if (NUMBER_OF_STAGES == 0) begin\r
always @ *\r
pipe_out = pipe_in;\r
end\r
// Single flop case for a single stage pipeline\r
else if (NUMBER_OF_STAGES == 1) begin\r
always @ (posedge clk or negedge reset_n)\r
pipe_out <= (!reset_n) ? 0 : pipe_in;\r
end\r
// Case for 2 or more pipeline stages\r
else begin\r
// Create the necessary regs\r
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;\r
// Create logic for the initial and final pipeline registers\r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
pipe_gen[BIT_WIDTH-1:0] <= 0;\r
pipe_out <= 0;\r
end\r
else begin\r
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;\r
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];\r
end\r
end\r
// Create the intermediate pipeline registers if there are 3 or\r
// more pipeline stages\r
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline\r
always @ (posedge clk or negedge reset_n)\r
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];\r
end\r
end\r
endgenerate\r
\r
endmodule\r
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// t_sqrt_pipelined.v\r
// Created: 4.2.2012\r
// Modified: 4.5.2012\r
//\r
// Testbench for generic sqrt operation\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module t_sqrt_pipelined();\r
\r
parameter \r
INPUT_BITS = 4;\r
localparam\r
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;\r
\r
reg [INPUT_BITS-1:0] radicand;\r
reg clk, start, reset_n;\r
\r
wire [OUTPUT_BITS-1:0] root;\r
wire data_valid;\r
// wire [7:0] root_good;\r
\r
sqrt_pipelined \r
#(\r
.INPUT_BITS(INPUT_BITS)\r
)\r
sqrt_pipelined \r
(\r
.clk(clk),\r
.reset_n(reset_n),\r
.start(start),\r
.radicand(radicand), \r
.data_valid(data_valid),\r
.root(root)\r
);\r
\r
initial begin\r
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;\r
#10 reset_n = 0; clk = 0;\r
#50 reset_n = 1; radicand = 0;\r
// #40 radicand = 81; start = 1;\r
// #10 radicand = 16'bx; start = 0;\r
#10000 $finish;\r
end\r
\r
always\r
#5 clk = ~clk;\r
\r
always begin\r
#10 radicand = radicand + 1; start = 1;\r
#10 start = 0;\r
end\r
\r
\r
// always begin\r
// #80 start = 1;\r
// #10 start = 0;\r
// end\r
\r
endmodule\r
\r
|
Require Export Sorted.
Require Export Mergesort.
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// sqrt_pipelined.v\r
// Created: 4.2.2012\r
// Modified: 4.5.2012\r
//\r
// Implements a fixed-point parameterized pipelined square root\r
// operation on an unsigned input of any bit length. The number of\r
// stages in the pipeline is equal to the number of output bits in the\r
// computation. This pipelien sustains a throughput of one computation\r
// per clock cycle.\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module sqrt_pipelined\r
(\r
input clk, // clock\r
input reset_n, // asynchronous reset\r
input start, // optional start signal\r
input [INPUT_BITS-1:0] radicand, // unsigned radicand\r
output reg data_valid, // optional data valid signal\r
output reg [OUTPUT_BITS-1:0] root // unsigned root \r
);\r
\r
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP\r
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE\r
// OVERWRITTEN!\r
parameter\r
INPUT_BITS = 16; // number of input bits (any integer)\r
localparam\r
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits\r
\r
reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation\r
reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values\r
reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values\r
wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values\r
\r
// This is the first stage of the pipeline.\r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
start_gen[0] <= 0;\r
radicand_gen[INPUT_BITS-1:0] <= 0;\r
root_gen[INPUT_BITS-1:0] <= 0;\r
end\r
else begin\r
start_gen[0] <= start;\r
if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin\r
radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];\r
root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];\r
end\r
else begin\r
radicand_gen[INPUT_BITS-1:0] <= radicand;\r
root_gen[INPUT_BITS-1:0] <= 0;\r
end\r
end\r
end\r
\r
// Main generate loop to create the masks and pipeline stages.\r
generate\r
genvar i;\r
// Generate all the mask values. These are built up in the\r
// following fashion:\r
// LAST MASK: 0x00...001 \r
// 0x00...004 Increasing # OUTPUT_BITS\r
// 0x00...010 |\r
// 0x00...040 v\r
// ...\r
// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS\r
// \r
// Note that the first mask used can either be of the 0x1... or\r
// 0x4... variety. This is purely determined by the number of\r
// computation stages. However, the last mask used will always be\r
// 0x1 and the second to last mask used will always be 0x4.\r
for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4\r
if (i % 2) // i is odd, this is a 4 mask\r
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);\r
else // i is even, this is a 1 mask\r
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);\r
end\r
// Generate all the pipeline stages to compute the square root of\r
// the input radicand stream. The general approach is to compare\r
// the current values of the root plus the mask to the\r
// radicand. If root/mask sum is greater than the radicand,\r
// subtract the mask and the root from the radicand and store the\r
// radicand for the next stage. Additionally, the root is\r
// increased by the value of the mask and stored for the next\r
// stage. If this test fails, then the radicand and the root\r
// retain their value through to the next stage. The one weird\r
// thing is that the mask indices appear to be incremented by one\r
// additional position. This is not the case, however, because the\r
// first mask is used in the first stage (always block after the\r
// generate statement).\r
for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline\r
always @ (posedge clk or negedge reset_n) begin : pipeline_stage\r
if (!reset_n) begin\r
start_gen[i+1] <= 0;\r
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;\r
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;\r
end\r
else begin\r
start_gen[i+1] <= start_gen[i];\r
if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] + \r
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin\r
\t radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] - \r
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] - \r
root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];\r
\t root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) + \r
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];\r
end\r
else begin\r
\t radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];\r
\t root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;\r
end\r
end\r
end\r
end\r
endgenerate\r
\r
// This is the final stage which just implements a rounding\r
// operation. This stage could be tacked on as a combinational logic\r
// stage, but who cares about latency, anyway? This is NOT a true\r
// rounding stage. In order to add convergent rounding, you need to\r
// increase the input bit width by 2 (increase the number of\r
// pipeline stages by 1) and implement rounding in the module that\r
// instantiates this one. \r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
data_valid <= 0;\r
root <= 0;\r
end\r
else begin\r
data_valid <= start_gen[OUTPUT_BITS-1];\r
if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])\r
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;\r
else\r
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];\r
end\r
end\r
\r
endmodule\r
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
\tinput [3:0] opA,opB;
\tinput [4:0] sum;
\tinput [1:0] dsp_sel;
\toutput [3:0] out;
\t
\treg cout;
\t
\talways @ (sum)
\t\tbegin
\t\t\tif (sum[4] == 1)
\t\t\t\tcout <= 4'b0001;
\t\t\telse
\t\t\t\tcout <= 4'b0000;
\t\tend
\t
\treg out;
\t
\talways @(dsp_sel,sum,cout,opB,opA)
\t\tbegin
\t\t\tif (dsp_sel == 2'b00)
\t\t\t\tout <= sum[3:0];
\t\t\telse if (dsp_sel == 2'b01)
\t\t\t\tout <= cout;
\t\t\telse if (dsp_sel == 2'b10)
\t\t\t\tout <= opB;
\t\t\telse if (dsp_sel == 2'b11)
\t\t\t\tout <= opA;
\t\tend
endmodule
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// button_debounce.v\r
// Created: 4.5.2012\r
// Modified: 4.5.2012\r
//\r
// Testbench for button_debounce.v.\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module t_button_debounce();\r
\r
parameter\r
CLK_FREQUENCY = 66000000,\r
DEBOUNCE_HZ = 2;\r
\r
reg clk, reset_n, button;\r
wire debounce;\r
\r
button_debounce\r
#(\r
.CLK_FREQUENCY(CLK_FREQUENCY),\r
.DEBOUNCE_HZ(DEBOUNCE_HZ)\r
)\r
button_debounce\r
(\r
.clk(clk),\r
.reset_n(reset_n),\r
.button(button),\r
.debounce(debounce)\r
);\r
\r
initial begin\r
clk = 1'bx; reset_n = 1'bx; button = 1'bx;\r
#10 reset_n = 1;\r
#10 reset_n = 0; clk = 0;\r
#10 reset_n = 1;\r
#10 button = 0;\r
end\r
\r
always\r
#5 clk = ~clk;\r
\r
always begin\r
#100 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
end\r
\r
endmodule\r
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// div_pipelined.v\r
// Created: 4.3.2012\r
// Modified: 4.5.2012\r
//\r
// Testbench for div_pipelined.v\r
//\r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module t_div_pipelined();\r
\r
reg clk, start, reset_n;\r
reg [7:0] dividend, divisor;\r
wire data_valid, div_by_zero;\r
wire [7:0] quotient, quotient_correct;\r
\r
parameter\r
BITS = 8;\r
\r
div_pipelined\r
#(\r
.BITS(BITS)\r
)\r
div_pipelined\r
(\r
.clk(clk),\r
.reset_n(reset_n),\r
.dividend(dividend),\r
.divisor(divisor),\r
.quotient(quotient),\r
.div_by_zero(div_by_zero),\r
// .quotient_correct(quotient_correct),\r
.start(start),\r
.data_valid(data_valid)\r
);\r
\r
initial begin\r
#10 reset_n = 0;\r
#50 reset_n = 1;\r
#1\r
clk = 0;\r
dividend = -1;\r
divisor = 127;\r
#1000 $finish;\r
end\r
\r
// always\r
// #20 dividend = dividend + 1;\r
\r
always begin\r
#10 divisor = divisor - 1; start = 1;\r
#10 start = 0;\r
end\r
\r
always\r
#5 clk = ~clk;\r
\r
\r
endmodule\r
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
assign dsp_sel[0] = i;
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF3(
.Q(a), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(d), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF2(
.Q(b), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(a), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF1(
.Q(c), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(b), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF0(
.Q(d), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(c), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF7(
.Q(e), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(h), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF6(
.Q(f), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(e), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF5(
.Q(g), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(f), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF4(
.Q(h), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(g), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF11(
.Q(i), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(l), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF10(
.Q(j), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(i), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF9(
.Q(k), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(j), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF8(
.Q(l), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(k), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// button_debounce.v\r
// Created: 10/10/2009\r
// Modified: 3/20/2012\r
//\r
// Counter based debounce circuit originally written for EC551 (back\r
// in the day) and then modified (i.e. chagned entirely) into 3 always\r
// block format. This debouncer generates a signal that goes high for\r
// 1 clock cycle after the clock sees an asserted value on the button\r
// line. This action is then disabled until the counter hits a\r
// specified count value that is determined by the clock frequency and\r
// desired debounce frequency. An alternative implementation would not\r
// use a counter, but would use the shift register approach, looking\r
// for repeated matches (say 5) on the button line.\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module button_debounce\r
(\r
input clk, // clock\r
input reset_n, // asynchronous reset \r
input button, // bouncy button\r
output reg debounce // debounced 1-cycle signal\r
);\r
\r
parameter\r
CLK_FREQUENCY = 66000000,\r
DEBOUNCE_HZ = 2;\r
// These parameters are specified such that you can choose any power\r
// of 2 frequency for a debouncer between 1 Hz and\r
// CLK_FREQUENCY. Note, that this will throw errors if you choose a\r
// non power of 2 frequency (i.e. count_value evaluates to some\r
// number / 3 which isn't interpreted as a logical right shift). I'm\r
// assuming this will not work for DEBOUNCE_HZ values less than 1,\r
// however, I'm uncertain of the value of a debouncer for fractional\r
// hertz button presses.\r
localparam\r
COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,\r
WAIT = 0,\r
FIRE = 1,\r
COUNT = 2;\r
\r
reg [1:0] state, next_state;\r
reg [25:0] count;\r
\r
always @ (posedge clk or negedge reset_n)\r
state <= (!reset_n) ? WAIT : next_state;\r
\r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
debounce <= 0;\r
count <= 0;\r
end\r
else begin\r
debounce <= 0;\r
count <= 0;\r
case (state)\r
WAIT: begin\r
end\r
FIRE: begin\r
debounce <= 1;\r
end\r
COUNT: begin\r
count <= count + 1;\r
end\r
endcase \r
end\r
end\r
\r
always @ * begin\r
case (state)\r
WAIT: next_state = (button) ? FIRE : state;\r
FIRE: next_state = COUNT;\r
COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;\r
default: next_state = WAIT;\r
endcase\r
end\r
\r
endmodule\r
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module hex_display (
input [15:0] num,
input en,
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3
);
// Module instantiations
seg_7 hex_group0 (
.num (num[3:0]),
.en (en),
.seg (hex0)
);
seg_7 hex_group1 (
.num (num[7:4]),
.en (en),
.seg (hex1)
);
seg_7 hex_group2 (
.num (num[11:8]),
.en (en),
.seg (hex2)
);
seg_7 hex_group3 (
.num (num[15:12]),
.en (en),
.seg (hex3)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// pipeline_registers.v\r
// Created: 4.4.2012\r
// Modified: 4.4.2012\r
//\r
// Implements a series of pipeline registers specified by the input\r
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the\r
// size of the signal passed through each of the pipeline\r
// registers. NUMBER_OF_STAGES is the number of pipeline registers\r
// generated. This accepts values of 0 (yes, it just passes data from\r
// input to output...) up to however many stages specified.\r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module pipeline_registers\r
(\r
input clk,\r
input reset_n,\r
input [BIT_WIDTH-1:0] pipe_in,\r
output reg [BIT_WIDTH-1:0] pipe_out\r
);\r
\r
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP\r
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE\r
// OVERWRITTEN!\r
parameter \r
BIT_WIDTH = 10,\r
NUMBER_OF_STAGES = 5;\r
\r
// Main generate function for conditional hardware instantiation\r
generate\r
genvar i;\r
// Pass-through case for the odd event that no pipeline stages are\r
// specified.\r
if (NUMBER_OF_STAGES == 0) begin\r
always @ *\r
pipe_out = pipe_in;\r
end\r
// Single flop case for a single stage pipeline\r
else if (NUMBER_OF_STAGES == 1) begin\r
always @ (posedge clk or negedge reset_n)\r
pipe_out <= (!reset_n) ? 0 : pipe_in;\r
end\r
// Case for 2 or more pipeline stages\r
else begin\r
// Create the necessary regs\r
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;\r
// Create logic for the initial and final pipeline registers\r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
pipe_gen[BIT_WIDTH-1:0] <= 0;\r
pipe_out <= 0;\r
end\r
else begin\r
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;\r
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];\r
end\r
end\r
// Create the intermediate pipeline registers if there are 3 or\r
// more pipeline stages\r
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline\r
always @ (posedge clk or negedge reset_n)\r
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];\r
end\r
end\r
endgenerate\r
\r
endmodule\r
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// button_debounce.v\r
// Created: 4.5.2012\r
// Modified: 4.5.2012\r
//\r
// Testbench for button_debounce.v.\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module t_button_debounce();\r
\r
parameter\r
CLK_FREQUENCY = 66000000,\r
DEBOUNCE_HZ = 2;\r
\r
reg clk, reset_n, button;\r
wire debounce;\r
\r
button_debounce\r
#(\r
.CLK_FREQUENCY(CLK_FREQUENCY),\r
.DEBOUNCE_HZ(DEBOUNCE_HZ)\r
)\r
button_debounce\r
(\r
.clk(clk),\r
.reset_n(reset_n),\r
.button(button),\r
.debounce(debounce)\r
);\r
\r
initial begin\r
clk = 1'bx; reset_n = 1'bx; button = 1'bx;\r
#10 reset_n = 1;\r
#10 reset_n = 0; clk = 0;\r
#10 reset_n = 1;\r
#10 button = 0;\r
end\r
\r
always\r
#5 clk = ~clk;\r
\r
always begin\r
#100 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
#0.1 button = ~button;\r
end\r
\r
endmodule\r
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
\tinput [3:0] opA,opB;
\tinput [4:0] sum;
\tinput [1:0] dsp_sel;
\toutput [3:0] out;
\t
\treg cout;
\t
\talways @ (sum)
\t\tbegin
\t\t\tif (sum[4] == 1)
\t\t\t\tcout <= 4'b0001;
\t\t\telse
\t\t\t\tcout <= 4'b0000;
\t\tend
\t
\treg out;
\t
\talways @(dsp_sel,sum,cout,opB,opA)
\t\tbegin
\t\t\tif (dsp_sel == 2'b00)
\t\t\t\tout <= sum[3:0];
\t\t\telse if (dsp_sel == 2'b01)
\t\t\t\tout <= cout;
\t\t\telse if (dsp_sel == 2'b10)
\t\t\t\tout <= opB;
\t\t\telse if (dsp_sel == 2'b11)
\t\t\t\tout <= opA;
\t\tend
endmodule
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// sqrt_pipelined.v\r
// Created: 4.2.2012\r
// Modified: 4.5.2012\r
//\r
// Implements a fixed-point parameterized pipelined square root\r
// operation on an unsigned input of any bit length. The number of\r
// stages in the pipeline is equal to the number of output bits in the\r
// computation. This pipelien sustains a throughput of one computation\r
// per clock cycle.\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module sqrt_pipelined\r
(\r
input clk, // clock\r
input reset_n, // asynchronous reset\r
input start, // optional start signal\r
input [INPUT_BITS-1:0] radicand, // unsigned radicand\r
output reg data_valid, // optional data valid signal\r
output reg [OUTPUT_BITS-1:0] root // unsigned root \r
);\r
\r
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP\r
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE\r
// OVERWRITTEN!\r
parameter\r
INPUT_BITS = 16; // number of input bits (any integer)\r
localparam\r
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits\r
\r
reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation\r
reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values\r
reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values\r
wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values\r
\r
// This is the first stage of the pipeline.\r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
start_gen[0] <= 0;\r
radicand_gen[INPUT_BITS-1:0] <= 0;\r
root_gen[INPUT_BITS-1:0] <= 0;\r
end\r
else begin\r
start_gen[0] <= start;\r
if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin\r
radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];\r
root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];\r
end\r
else begin\r
radicand_gen[INPUT_BITS-1:0] <= radicand;\r
root_gen[INPUT_BITS-1:0] <= 0;\r
end\r
end\r
end\r
\r
// Main generate loop to create the masks and pipeline stages.\r
generate\r
genvar i;\r
// Generate all the mask values. These are built up in the\r
// following fashion:\r
// LAST MASK: 0x00...001 \r
// 0x00...004 Increasing # OUTPUT_BITS\r
// 0x00...010 |\r
// 0x00...040 v\r
// ...\r
// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS\r
// \r
// Note that the first mask used can either be of the 0x1... or\r
// 0x4... variety. This is purely determined by the number of\r
// computation stages. However, the last mask used will always be\r
// 0x1 and the second to last mask used will always be 0x4.\r
for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4\r
if (i % 2) // i is odd, this is a 4 mask\r
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);\r
else // i is even, this is a 1 mask\r
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);\r
end\r
// Generate all the pipeline stages to compute the square root of\r
// the input radicand stream. The general approach is to compare\r
// the current values of the root plus the mask to the\r
// radicand. If root/mask sum is greater than the radicand,\r
// subtract the mask and the root from the radicand and store the\r
// radicand for the next stage. Additionally, the root is\r
// increased by the value of the mask and stored for the next\r
// stage. If this test fails, then the radicand and the root\r
// retain their value through to the next stage. The one weird\r
// thing is that the mask indices appear to be incremented by one\r
// additional position. This is not the case, however, because the\r
// first mask is used in the first stage (always block after the\r
// generate statement).\r
for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline\r
always @ (posedge clk or negedge reset_n) begin : pipeline_stage\r
if (!reset_n) begin\r
start_gen[i+1] <= 0;\r
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;\r
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;\r
end\r
else begin\r
start_gen[i+1] <= start_gen[i];\r
if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] + \r
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin\r
\t radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] - \r
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] - \r
root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];\r
\t root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) + \r
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];\r
end\r
else begin\r
\t radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];\r
\t root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;\r
end\r
end\r
end\r
end\r
endgenerate\r
\r
// This is the final stage which just implements a rounding\r
// operation. This stage could be tacked on as a combinational logic\r
// stage, but who cares about latency, anyway? This is NOT a true\r
// rounding stage. In order to add convergent rounding, you need to\r
// increase the input bit width by 2 (increase the number of\r
// pipeline stages by 1) and implement rounding in the module that\r
// instantiates this one. \r
always @ (posedge clk or negedge reset_n) begin\r
if (!reset_n) begin\r
data_valid <= 0;\r
root <= 0;\r
end\r
else begin\r
data_valid <= start_gen[OUTPUT_BITS-1];\r
if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])\r
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;\r
else\r
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];\r
end\r
end\r
\r
endmodule\r
|
Require Export Sorted.
Require Export Mergesort.
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// sign_extender.v\r
// Created: 5.16.2012\r
// Modified: 5.16.2012\r
//\r
// Generic sign extension module\r
//\r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns/1ps\r
module sign_extender\r
#(\r
parameter\r
INPUT_WIDTH = 8,\r
OUTPUT_WIDTH = 16\r
)\r
(\r
input [INPUT_WIDTH-1:0] original,\r
output reg [OUTPUT_WIDTH-1:0] sign_extended_original\r
);\r
\r
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;\r
\r
generate\r
genvar i;\r
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend\r
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;\r
end\r
endgenerate\r
\r
always @ * begin\r
sign_extended_original = {sign_extend,original};\r
end\r
\r
endmodule\r
|
////////////////////////////////////////////////////////////////////////////////\r
// Original Author: Schuyler Eldridge\r
// Contact Point: Schuyler Eldridge ([email protected])\r
// t_sqrt_pipelined.v\r
// Created: 4.2.2012\r
// Modified: 4.5.2012\r
//\r
// Testbench for generic sqrt operation\r
// \r
// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
//\r
// This program is free software: you can redistribute it and/or modify\r
// it under the terms of the GNU General Public License as published by\r
// the Free Software Foundation, either version 3 of the License.\r
//\r
// This program is distributed in the hope that it will be useful,\r
// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
// GNU General Public License for more details.\r
//\r
// You should have received a copy of the GNU General Public License\r
// along with this program. If not, see <http://www.gnu.org/licenses/>.\r
////////////////////////////////////////////////////////////////////////////////\r
`timescale 1ns / 1ps\r
module t_sqrt_pipelined();\r
\r
parameter \r
INPUT_BITS = 4;\r
localparam\r
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;\r
\r
reg [INPUT_BITS-1:0] radicand;\r
reg clk, start, reset_n;\r
\r
wire [OUTPUT_BITS-1:0] root;\r
wire data_valid;\r
// wire [7:0] root_good;\r
\r
sqrt_pipelined \r
#(\r
.INPUT_BITS(INPUT_BITS)\r
)\r
sqrt_pipelined \r
(\r
.clk(clk),\r
.reset_n(reset_n),\r
.start(start),\r
.radicand(radicand), \r
.data_valid(data_valid),\r
.root(root)\r
);\r
\r
initial begin\r
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;\r
#10 reset_n = 0; clk = 0;\r
#50 reset_n = 1; radicand = 0;\r
// #40 radicand = 81; start = 1;\r
// #10 radicand = 16'bx; start = 0;\r
#10000 $finish;\r
end\r
\r
always\r
#5 clk = ~clk;\r
\r
always begin\r
#10 radicand = radicand + 1; start = 1;\r
#10 start = 0;\r
end\r
\r
\r
// always begin\r
// #80 start = 1;\r
// #10 start = 0;\r
// end\r
\r
endmodule\r
\r
|
Module SyntaxError.
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
S O => false
| S (S n') => evenb n'
end.
End SyntaxError.
|
Module Error.
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => 1
end.
End Error.
|
module verilator_warning;
reg val;
endmodule
|
module verilog_verilator_error;
initial begin
forever begin
i = $fopen("test.log");
end
end
endmodule
|
(** This module offers an abstract domain of polyhedra on integers. *)
Require PedraQ.
Require DomainFunctors.
Require Import ASCond.
Require Import ZNoneItv.
Module FullDom <: FullItvAbstractDomain ZNum ZCond ZNItv
:= DomainFunctors.MakeZ PedraQ.BasicD PedraQ.CstrD PedraQ.AffItvD PedraQ.Rename PedraQ.BasicD.
|
Require DemoPLTests.
Require Import DemoExtract.
Extraction Library DemoPLTests.
|
//
// Wishbone wrapper for seven-segment LED display controller
//
// Copyright (C) 2015 Andrzej <[email protected]>
//
// Redistribution and use in source and non-source forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in non-source form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// Register map (assuming 32b access):
// 00 [1] - IRQ mask. 1 - IRQ enabled.
// [0] - Enable display controller
// 04 [15:0] - Clock divider for multiplexing.
// To obtain a scanning rate further divide by 256 (for PWM) and by n_digits.
// 08 [7:0] - Brightness control. 0 - minimum brightness (non-zero), 255 - maximum.
// Logarithmic progression (percepted).
// 0c [0] - (Write) Write \'1\' to clear IRQ flag.
// 0c [0] - (Read) IRQ Flag.
// 20 [n_segs-1:0] - First digit (or column)
// 24 [n_segs-1:0] - Second digit (or column)
// ...
//
// Example of instantiation:
// // open-drain output with logic inversion
// wire [7:0] sseg_disp_seg_oe;
// generate
// for (i = 0; i < 8; i = i+1) begin: sseg_disp_seg_tris
// assign sseg_disp_seg_o [i] = sseg_disp_seg_oe[i] ? 1\'b0 : 1\'bz;
// end
// endgenerate
//
// wire [7:0] sseg_disp_seg_sel;
// assign sseg_disp_an_o = ~sseg_disp_seg_sel;
//
// wb_sseg_ctrl
// #(
// .n_digits (8),
//`ifdef SIM
// .def_clk_div(4) // speed up simulation time
//`else
// .def_clk_div(128)
//`endif
// )
// sseg_ctrl
// (
// .wb_clk_i (wb_clk),
// .wb_rst_i (wb_rst),
// .async_rst_i (async_rst),
// // Wishbone slave interface
// .wb_adr_i (wb_m2s_sseg_ctrl_adr[5:2]),
// .wb_dat_i (wb_m2s_sseg_ctrl_dat),
// .wb_sel_i (wb_m2s_sseg_ctrl_sel),
// .wb_we_i (wb_m2s_sseg_ctrl_we),
// .wb_cyc_i (wb_m2s_sseg_ctrl_cyc),
// .wb_stb_i (wb_m2s_sseg_ctrl_stb),
// .wb_cti_i (wb_m2s_sseg_ctrl_cti),
// .wb_bte_i (wb_m2s_sseg_ctrl_bte),
// .wb_dat_o (wb_s2m_sseg_ctrl_dat),
// .wb_ack_o (wb_s2m_sseg_ctrl_ack),
// .wb_err_o (wb_s2m_sseg_ctrl_err),
// .wb_rty_o (wb_s2m_sseg_ctrl_rty),
// // display i/f
// .seg_o (sseg_disp_seg_oe),
// .seg_sel_o (sseg_disp_seg_sel),
// // frame sync irq
// .irq_o (sseg_didp_irq)
// );
module wb_sseg_ctrl
#(
parameter n_digits = 8,
parameter n_segs = 8,
parameter def_clk_div = 128,
//parameter def_clk_div = 4,
parameter dw = 16,
parameter aw = 4
)
(
input wb_clk_i,
input wb_rst_i,
input async_rst_i,
// Wishbone Interface
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [dw-1:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
output wb_rty_o,
// display i/f
output [n_segs-1:0] seg_o,
output [n_digits-1:0] seg_sel_o,
// frame sync irq (end of the sweep)
output irq_o
);
wire sync;
// address decoder
reg [2**aw-1:0] sel;
integer i;
always @(*)
begin
sel = {2**aw{1\'b0}};
for (i = 0; i < 2**aw; i = i + 1)
if (wb_adr_i == i)
sel[i] = 1\'b1;
end
// enable register
reg enable_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
enable_reg <= 1\'b0;
else if (wb_rst_i)
enable_reg <= 1\'b0;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[0])
enable_reg <= wb_dat_i[0];
// mask IRQ register
reg IRQ_mask_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
IRQ_mask_reg <= 1\'b0;
else if (wb_rst_i)
IRQ_mask_reg <= 1\'b0;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[0])
IRQ_mask_reg <= wb_dat_i[1];
// clock divider register
reg [15:0] clk_div_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
clk_div_reg <= def_clk_div;
else if (wb_rst_i)
clk_div_reg <= def_clk_div;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[1])
clk_div_reg <= wb_dat_i[15:0];
// brightness register
reg [7:0] brightness_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
brightness_reg <= 8\'hff;
else if (wb_rst_i)
brightness_reg <= 8\'hff;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[2])
brightness_reg <= wb_dat_i[7:0];
// data to display
reg [n_digits*n_segs-1:0] segments_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
segments_reg <= 0;
else if (wb_rst_i)
segments_reg <= 0;
else if (wb_cyc_i & wb_stb_i & wb_we_i)
for (i = 0; i < n_digits; i = i + 1)
if (sel[i+8])
segments_reg[n_segs*(i+1)-1 -: n_segs] <= wb_dat_i[n_segs-1:0];
// IRQ flag
// write \'1\' to clear it
reg IRQ_flag_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
IRQ_flag_reg <= 1\'b0;
else if (wb_rst_i)
IRQ_flag_reg <= 1\'b0;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[3] & wb_dat_i[0])
IRQ_flag_reg <= 1\'b0;
else if (sync)
IRQ_flag_reg <= 1\'b1;
assign irq_o = IRQ_flag_reg & IRQ_mask_reg;
// read back register values
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_dat_o <= 32\'b0;
else if (wb_cyc_i)
begin
wb_dat_o <= 0;
if (sel[0]) wb_dat_o[1:0] <= {IRQ_mask_reg, enable_reg};
if (sel[1]) wb_dat_o[15:0] <= clk_div_reg;
if (sel[2]) wb_dat_o[7:0] <= brightness_reg;
if (sel[3]) wb_dat_o[0] <= IRQ_flag_reg;
for (i = 0; i < n_digits; i = i + 1)
if (sel[i+8])
wb_dat_o[n_segs-1:0] <= segments_reg[n_segs*(i+1)-1 -: n_segs];
end
// Ack generation
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o <= 0;
else if (wb_ack_o)
wb_ack_o <= 0;
else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
wb_ack_o <= 1;
assign wb_err_o = 0;
assign wb_rty_o = 0;
// instantiate the controller
sseg_ctrl #(.n_digits(n_digits)) ctrl
(
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.async_rst_i (async_rst_i),
// config registers
.enable_i (enable_reg),
.clk_div_i (clk_div_reg),
.brightness_i (brightness_reg),
.segments_i (segments_reg),
// display i/f
.seg_o (seg_o),
.seg_sel_o (seg_sel_o),
// sync irq
.sync_o (sync)
);
endmodule
|
//
// Seven-segment LED display controller
//
// Copyright (C) 2015 Andrzej <[email protected]>
//
// Redistribution and use in source and non-source forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in non-source form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
module sseg_ctrl
#(
parameter n_digits = 8,
parameter n_segs = 8
)
(
input clk_i,
input rst_i,
input async_rst_i,
// config registers
input enable_i,
input [15:0] clk_div_i,
input [7:0] brightness_i,
input [n_digits*n_segs-1:0] segments_i,
// display i/f
output [n_segs-1:0] seg_o,
output [n_digits-1:0] seg_sel_o,
// sync irq (end of the sweep)
output sync_o
);
// time-base strobe generator
reg [15:0] cnt_strobe_reg;
wire strobe = (enable_i & cnt_strobe_reg == 16\'b0);
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
cnt_strobe_reg <= 16\'b0;
else if (rst_i | ~enable_i)
cnt_strobe_reg <= 16\'b0;
else if (strobe)
cnt_strobe_reg <= clk_div_i;
else
cnt_strobe_reg <= cnt_strobe_reg - 16\'d1;
// digit strobe generator
reg [7:0] cnt_strobe_dig_reg;
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
cnt_strobe_dig_reg <= 8\'b0;
else if (rst_i | ~enable_i)
cnt_strobe_dig_reg <= 8\'b0;
else if (strobe)
cnt_strobe_dig_reg <= cnt_strobe_dig_reg - 8\'d1;
wire strobe_dig = (strobe & cnt_strobe_dig_reg == 8\'hff);
// pwm reg
reg pwm_reg;
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
pwm_reg <= 1\'b0;
else if (rst_i | ~enable_i)
pwm_reg <= 1\'b0;
else if (strobe)
pwm_reg <= (cnt_strobe_dig_reg <= brightness_i);
// frame strobe generator
reg [4:0] cnt_strobe_frame_reg;
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
cnt_strobe_frame_reg <= 5\'b0;
else if (rst_i | ~enable_i)
cnt_strobe_frame_reg <= 5\'b0;
else if (strobe_dig &cnt_strobe_frame_reg == 5\'b0)
cnt_strobe_frame_reg <= n_digits - 1;
else if (strobe_dig)
cnt_strobe_frame_reg <= cnt_strobe_frame_reg - 5\'d1;
wire strobe_frame = (strobe_dig & cnt_strobe_frame_reg == 5\'b0);
// multiplex digits
wire [n_digits-1:0] seg_sel_reg_new;
assign seg_sel_reg_new = {strobe_frame, seg_sel_reg[n_digits-1:1]};
reg [n_digits-1:0] seg_sel_reg;
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
seg_sel_reg <= 0;
else if (rst_i | ~enable_i)
seg_sel_reg <= 0;
else if (strobe_dig)
seg_sel_reg <= seg_sel_reg_new;
// output seg_sel
assign seg_sel_o = seg_sel_reg; // & {n_digits{pwm_reg}};
// segment value
integer i;
reg [n_segs-1:0] seg_reg;
always @(posedge clk_i or posedge async_rst_i)
if (async_rst_i)
seg_reg <= 0;
else if (rst_i | ~enable_i)
seg_reg <= 0;
else if (strobe_dig)
for (i = 0; i < n_digits; i = i + 1)
if (seg_sel_reg_new[i])
seg_reg <= segments_i[n_segs*(n_digits-i)-1 -: n_segs];
//seg_o <= segments_i[n_segs*(i+1)-1 -: n_segs];
// output seg
assign seg_o = seg_reg & {n_segs{pwm_reg}};
assign sync_o = strobe_frame;
endmodule
|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
|
#!/bin/bash
if [ -z "$1" ] ; then
echo "\xe4\xbd\xbf\xe7\x94\xa8\xe6\x96\xb9\xe6\xb3\x95\xef\xbc\x9a$0 \xe6\x96\xb0\xe7\x89\x88\xe6\x9c\xac\xe5\x8f\xb7"
exit 1
fi
pushd $(dirname $0)
sed -i "s/Version:.*/Version:\\t$1/g" gammu.spec
popd
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_clock_mux.v
//
// *Module Description:
// Standard clock mux for the openMSP430
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_clock_mux (
// OUTPUTs
clk_out, // Clock output
// INPUTs
clk_in0, // Clock input 0
clk_in1, // Clock input 1
reset, // Reset
scan_mode, // Scan mode (clk_in0 is selected in scan mode)
select_in // Clock selection
);
// OUTPUTs
//=========
output clk_out; // Clock output
// INPUTs
//=========
input clk_in0; // Clock input 0
input clk_in1; // Clock input 1
input reset; // Reset
input scan_mode; // Scan mode (clk_in0 is selected in scan mode)
input select_in; // Clock selection
//===========================================================================================================================//
// 1) CLOCK MUX //
//===========================================================================================================================//
// //
// The following (glitch free) clock mux is implemented as following: //
// //
// //
// //
// //
// +-----. +--------+ +--------+ //
// select_in >>----+-------------O| \\ | | | | +-----. //
// | | |---| D Q |---| D Q |--+-------| \\ //
// | +-------O| / | | | | | | |O-+ //
// | | +-----\' | | | | | +--O| / | //
// | | | /\\ | | /\\ | | | +-----\' | //
// | | +--+--+--+ +--+--+--+ | | | //
// | | O | | | | //
// | | | | | | | +-----. //
// clk_in0 >>----------------------------------+------------+-----------+ +--| \\ //
// | | | | |----<< clk_out //
// | | +---------------------------------------+ +--| / //
// | | | | +-----\' //
// | +---------------------------------------------+ | //
// | | | | //
// | | +-----. +--------+ +--------+ | | //
// | +-O| \\ | | | | | +-----. | //
// | | |---| D Q |---| D Q |--+-------| \\ | //
// +--------------| / | | | | | |O-+ //
// +-----\' | | | | +--O| / //
// | /\\ | | /\\ | | +-----\' //
// +--+--+--+ +--+--+--+ | //
// O | | //
// | | | //
// clk_in1 >>----------------------------------+------------+-----------+ //
// //
// //
//===========================================================================================================================//
//-----------------------------------------------------------------------------
// Wire declarations
//-----------------------------------------------------------------------------
wire in0_select;
reg in0_select_s;
reg in0_select_ss;
wire in0_enable;
wire in1_select;
reg in1_select_s;
reg in1_select_ss;
wire in1_enable;
wire clk_in0_inv;
wire clk_in1_inv;
wire clk_in0_scan_fix_inv;
wire clk_in1_scan_fix_inv;
wire gated_clk_in0;
wire gated_clk_in1;
//-----------------------------------------------------------------------------
// Optional scan repair for neg-edge clocked FF
//-----------------------------------------------------------------------------
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_clk_in0_inv (.scan_mode(scan_mode), .data_in_scan(clk_in0), .data_in_func(~clk_in0), .data_out(clk_in0_scan_fix_inv));
omsp_scan_mux scan_mux_repair_clk_in1_inv (.scan_mode(scan_mode), .data_in_scan(clk_in1), .data_in_func(~clk_in1), .data_out(clk_in1_scan_fix_inv));
`else
assign clk_in0_scan_fix_inv = ~clk_in0;
assign clk_in1_scan_fix_inv = ~clk_in1;
`endif
//-----------------------------------------------------------------------------
// CLK_IN0 Selection
//-----------------------------------------------------------------------------
assign in0_select = ~select_in & ~in1_select_ss;
always @ (posedge clk_in0_scan_fix_inv or posedge reset)
if (reset) in0_select_s <= 1\'b1;
else in0_select_s <= in0_select;
always @ (posedge clk_in0 or posedge reset)
if (reset) in0_select_ss <= 1\'b1;
else in0_select_ss <= in0_select_s;
assign in0_enable = in0_select_ss | scan_mode;
//-----------------------------------------------------------------------------
// CLK_IN1 Selection
//-----------------------------------------------------------------------------
assign in1_select = select_in & ~in0_select_ss;
always @ (posedge clk_in1_scan_fix_inv or posedge reset)
if (reset) in1_select_s <= 1\'b0;
else in1_select_s <= in1_select;
always @ (posedge clk_in1 or posedge reset)
if (reset) in1_select_ss <= 1\'b0;
else in1_select_ss <= in1_select_s;
assign in1_enable = in1_select_ss & ~scan_mode;
//-----------------------------------------------------------------------------
// Clock MUX
//-----------------------------------------------------------------------------
//
// IMPORTANT NOTE:
// Because the clock network is a critical part of the design,
// the following combinatorial logic should be replaced with
// direct instanciation of standard cells from target library.
// Don\'t forget the "dont_touch" attribute to make sure
// synthesis won\'t mess it up.
//
// Replace with standard cell INVERTER
assign clk_in0_inv = ~clk_in0;
assign clk_in1_inv = ~clk_in1;
// Replace with standard cell NAND2
assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
// Replace with standard cell AND2
assign clk_out = (gated_clk_in0 & gated_clk_in1);
endmodule // omsp_clock_gate
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_undefines.v
//
// *Module Description:
// openMSP430 Verilog `undef file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// BASIC SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
// Program Memory sizes
`ifdef PMEM_SIZE_CUSTOM
`undef PMEM_SIZE_CUSTOM
`endif
`ifdef PMEM_SIZE_59_KB
`undef PMEM_SIZE_59_KB
`endif
`ifdef PMEM_SIZE_55_KB
`undef PMEM_SIZE_55_KB
`endif
`ifdef PMEM_SIZE_54_KB
`undef PMEM_SIZE_54_KB
`endif
`ifdef PMEM_SIZE_51_KB
`undef PMEM_SIZE_51_KB
`endif
`ifdef PMEM_SIZE_48_KB
`undef PMEM_SIZE_48_KB
`endif
`ifdef PMEM_SIZE_41_KB
`undef PMEM_SIZE_41_KB
`endif
`ifdef PMEM_SIZE_32_KB
`undef PMEM_SIZE_32_KB
`endif
`ifdef PMEM_SIZE_24_KB
`undef PMEM_SIZE_24_KB
`endif
`ifdef PMEM_SIZE_16_KB
`undef PMEM_SIZE_16_KB
`endif
`ifdef PMEM_SIZE_12_KB
`undef PMEM_SIZE_12_KB
`endif
`ifdef PMEM_SIZE_8_KB
`undef PMEM_SIZE_8_KB
`endif
`ifdef PMEM_SIZE_4_KB
`undef PMEM_SIZE_4_KB
`endif
`ifdef PMEM_SIZE_2_KB
`undef PMEM_SIZE_2_KB
`endif
`ifdef PMEM_SIZE_1_KB
`undef PMEM_SIZE_1_KB
`endif
// Data Memory sizes
`ifdef DMEM_SIZE_CUSTOM
`undef DMEM_SIZE_CUSTOM
`endif
`ifdef DMEM_SIZE_32_KB
`undef DMEM_SIZE_32_KB
`endif
`ifdef DMEM_SIZE_24_KB
`undef DMEM_SIZE_24_KB
`endif
`ifdef DMEM_SIZE_16_KB
`undef DMEM_SIZE_16_KB
`endif
`ifdef DMEM_SIZE_10_KB
`undef DMEM_SIZE_10_KB
`endif
`ifdef DMEM_SIZE_8_KB
`undef DMEM_SIZE_8_KB
`endif
`ifdef DMEM_SIZE_5_KB
`undef DMEM_SIZE_5_KB
`endif
`ifdef DMEM_SIZE_4_KB
`undef DMEM_SIZE_4_KB
`endif
`ifdef DMEM_SIZE_2p5_KB
`undef DMEM_SIZE_2p5_KB
`endif
`ifdef DMEM_SIZE_2_KB
`undef DMEM_SIZE_2_KB
`endif
`ifdef DMEM_SIZE_1_KB
`undef DMEM_SIZE_1_KB
`endif
`ifdef DMEM_SIZE_512_B
`undef DMEM_SIZE_512_B
`endif
`ifdef DMEM_SIZE_256_B
`undef DMEM_SIZE_256_B
`endif
`ifdef DMEM_SIZE_128_B
`undef DMEM_SIZE_128_B
`endif
// Include/Exclude Hardware Multiplier
`ifdef MULTIPLIER
`undef MULTIPLIER
`endif
// Include Debug interface
`ifdef DBG_EN
`undef DBG_EN
`endif
//----------------------------------------------------------------------------
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
//----------------------------------------------------------------------------
// Custom user version number
`ifdef USER_VERSION
`undef USER_VERSION
`endif
// Include/Exclude Watchdog timer
`ifdef WATCHDOG
`undef WATCHDOG
`endif
// Include/Exclude DMA interface support
`ifdef DMA_IF_EN
`undef DMA_IF_EN
`endif
// Include/Exclude Non-Maskable-Interrupt support
`ifdef NMI
`undef NMI
`endif
// Number of available IRQs
`ifdef IRQ_16
`undef IRQ_16
`endif
`ifdef IRQ_32
`undef IRQ_32
`endif
`ifdef IRQ_64
`undef IRQ_64
`endif
// Input synchronizers
`ifdef SYNC_NMI
`undef SYNC_NMI
`endif
`ifdef SYNC_CPU_EN
`undef SYNC_CPU_EN
`endif
`ifdef SYNC_DBG_EN
`undef SYNC_DBG_EN
`endif
// Peripheral Memory Space:
`ifdef PER_SIZE_CUSTOM
`undef PER_SIZE_CUSTOM
`endif
`ifdef PER_SIZE_32_KB
`undef PER_SIZE_32_KB
`endif
`ifdef PER_SIZE_16_KB
`undef PER_SIZE_16_KB
`endif
`ifdef PER_SIZE_8_KB
`undef PER_SIZE_8_KB
`endif
`ifdef PER_SIZE_4_KB
`undef PER_SIZE_4_KB
`endif
`ifdef PER_SIZE_2_KB
`undef PER_SIZE_2_KB
`endif
`ifdef PER_SIZE_1_KB
`undef PER_SIZE_1_KB
`endif
`ifdef PER_SIZE_512_B
`undef PER_SIZE_512_B
`endif
// Let the CPU break after a PUC occurrence by default
`ifdef DBG_RST_BRK_EN
`undef DBG_RST_BRK_EN
`endif
//----------------------------------------------------------------------------
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//----------------------------------------------------------------------------
// Serial Debug interface protocol
`ifdef DBG_UART
`undef DBG_UART
`endif
`ifdef DBG_I2C
`undef DBG_I2C
`endif
// Enable the I2C broadcast address
`ifdef DBG_I2C_BROADCAST
`undef DBG_I2C_BROADCAST
`endif
// Number of hardware breakpoint units
`ifdef DBG_HWBRK_0
`undef DBG_HWBRK_0
`endif
`ifdef DBG_HWBRK_1
`undef DBG_HWBRK_1
`endif
`ifdef DBG_HWBRK_2
`undef DBG_HWBRK_2
`endif
`ifdef DBG_HWBRK_3
`undef DBG_HWBRK_3
`endif
// Enable/Disable the hardware breakpoint RANGE mode
`ifdef DBG_HWBRK_RANGE
`undef DBG_HWBRK_RANGE
`endif
// Custom Program/Data and Peripheral Memory Spaces
`undef PMEM_CUSTOM_AWIDTH
`undef PMEM_CUSTOM_SIZE
`undef DMEM_CUSTOM_AWIDTH
`undef DMEM_CUSTOM_SIZE
`undef PER_CUSTOM_AWIDTH
`undef PER_CUSTOM_SIZE
// ASIC version
`ifdef ASIC
`undef ASIC
`endif
//----------------------------------------------------------------------------
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//----------------------------------------------------------------------------
// ASIC/FPGA-like clocking
`ifdef ASIC_CLOCKING
`undef ASIC_CLOCKING
`endif
// Fine grained clock gating
`ifdef CLOCK_GATING
`undef CLOCK_GATING
`endif
// LFXT clock domain
`ifdef LFXT_DOMAIN
`undef LFXT_DOMAIN
`endif
// MCLK: Clock Mux
`ifdef MCLK_MUX
`undef MCLK_MUX
`endif
// SMCLK: Clock Mux
`ifdef SMCLK_MUX
`undef SMCLK_MUX
`endif
// WATCHDOG: Clock Mux
`ifdef WATCHDOG_MUX
`undef WATCHDOG_MUX
`endif
`ifdef WATCHDOG_NOMUX_ACLK
`undef WATCHDOG_NOMUX_ACLK
`endif
// MCLK: Clock divider
`ifdef MCLK_DIVIDER
`undef MCLK_DIVIDER
`endif
// SMCLK: Clock divider (/1/2/4/8)
`ifdef SMCLK_DIVIDER
`undef SMCLK_DIVIDER
`endif
// ACLK: Clock divider (/1/2/4/8)
`ifdef ACLK_DIVIDER
`undef ACLK_DIVIDER
`endif
// LOW POWER MODE: CPUOFF
`ifdef CPUOFF_EN
`undef CPUOFF_EN
`endif
// LOW POWER MODE: SCG0
`ifdef SCG0_EN
`undef SCG0_EN
`endif
// LOW POWER MODE: SCG1
`ifdef SCG1_EN
`undef SCG1_EN
`endif
// LOW POWER MODE: OSCOFF
`ifdef OSCOFF_EN
`undef OSCOFF_EN
`endif
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
// Program Memory Size
`ifdef PMEM_AWIDTH
`undef PMEM_AWIDTH
`endif
`ifdef PMEM_SIZE
`undef PMEM_SIZE
`endif
// Data Memory Size
`ifdef DMEM_AWIDTH
`undef DMEM_AWIDTH
`endif
`ifdef DMEM_SIZE
`undef DMEM_SIZE
`endif
// Peripheral Memory Size
`ifdef PER_AWIDTH
`undef PER_AWIDTH
`endif
`ifdef PER_SIZE
`undef PER_SIZE
`endif
// Data Memory Base Adresses
`ifdef DMEM_BASE
`undef DMEM_BASE
`endif
// Program & Data Memory most significant address bit (for 16 bit words)
`ifdef PMEM_MSB
`undef PMEM_MSB
`endif
`ifdef DMEM_MSB
`undef DMEM_MSB
`endif
`ifdef PER_MSB
`undef PER_MSB
`endif
// Number of available IRQs
`ifdef IRQ_NR
`undef IRQ_NR
`endif
`ifdef IRQ_NR_GE_32
`undef IRQ_NR_GE_32
`endif
// Instructions type
`ifdef INST_SO
`undef INST_SO
`endif
`ifdef INST_JMP
`undef INST_JMP
`endif
`ifdef INST_TO
`undef INST_TO
`endif
// Single-operand arithmetic
`ifdef RRC
`undef RRC
`endif
`ifdef SWPB
`undef SWPB
`endif
`ifdef RRA
`undef RRA
`endif
`ifdef SXT
`undef SXT
`endif
`ifdef PUSH
`undef PUSH
`endif
`ifdef CALL
`undef CALL
`endif
`ifdef RETI
`undef RETI
`endif
`ifdef IRQ
`undef IRQ
`endif
// Conditional jump
`ifdef JNE
`undef JNE
`endif
`ifdef JEQ
`undef JEQ
`endif
`ifdef JNC
`undef JNC
`endif
`ifdef JC
`undef JC
`endif
`ifdef JN
`undef JN
`endif
`ifdef JGE
`undef JGE
`endif
`ifdef JL
`undef JL
`endif
`ifdef JMP
`undef JMP
`endif
// Two-operand arithmetic
`ifdef MOV
`undef MOV
`endif
`ifdef ADD
`undef ADD
`endif
`ifdef ADDC
`undef ADDC
`endif
`ifdef SUBC
`undef SUBC
`endif
`ifdef SUB
`undef SUB
`endif
`ifdef CMP
`undef CMP
`endif
`ifdef DADD
`undef DADD
`endif
`ifdef BIT
`undef BIT
`endif
`ifdef BIC
`undef BIC
`endif
`ifdef BIS
`undef BIS
`endif
`ifdef XOR
`undef XOR
`endif
`ifdef AND
`undef AND
`endif
// Addressing modes
`ifdef DIR
`undef DIR
`endif
`ifdef IDX
`undef IDX
`endif
`ifdef INDIR
`undef INDIR
`endif
`ifdef INDIR_I
`undef INDIR_I
`endif
`ifdef SYMB
`undef SYMB
`endif
`ifdef IMM
`undef IMM
`endif
`ifdef ABS
`undef ABS
`endif
`ifdef CONST
`undef CONST
`endif
// Instruction state machine
`ifdef I_IRQ_FETCH
`undef I_IRQ_FETCH
`endif
`ifdef I_IRQ_DONE
`undef I_IRQ_DONE
`endif
`ifdef I_DEC
`undef I_DEC
`endif
`ifdef I_EXT1
`undef I_EXT1
`endif
`ifdef I_EXT2
`undef I_EXT2
`endif
`ifdef I_IDLE
`undef I_IDLE
`endif
// Execution state machine
`ifdef E_IRQ_0
`undef E_IRQ_0
`endif
`ifdef E_IRQ_1
`undef E_IRQ_1
`endif
`ifdef E_IRQ_2
`undef E_IRQ_2
`endif
`ifdef E_IRQ_3
`undef E_IRQ_3
`endif
`ifdef E_IRQ_4
`undef E_IRQ_4
`endif
`ifdef E_SRC_AD
`undef E_SRC_AD
`endif
`ifdef E_SRC_RD
`undef E_SRC_RD
`endif
`ifdef E_SRC_WR
`undef E_SRC_WR
`endif
`ifdef E_DST_AD
`undef E_DST_AD
`endif
`ifdef E_DST_RD
`undef E_DST_RD
`endif
`ifdef E_DST_WR
`undef E_DST_WR
`endif
`ifdef E_EXEC
`undef E_EXEC
`endif
`ifdef E_JUMP
`undef E_JUMP
`endif
`ifdef E_IDLE
`undef E_IDLE
`endif
// ALU control signals
`ifdef ALU_SRC_INV
`undef ALU_SRC_INV
`endif
`ifdef ALU_INC
`undef ALU_INC
`endif
`ifdef ALU_INC_C
`undef ALU_INC_C
`endif
`ifdef ALU_ADD
`undef ALU_ADD
`endif
`ifdef ALU_AND
`undef ALU_AND
`endif
`ifdef ALU_OR
`undef ALU_OR
`endif
`ifdef ALU_XOR
`undef ALU_XOR
`endif
`ifdef ALU_DADD
`undef ALU_DADD
`endif
`ifdef ALU_STAT_7
`undef ALU_STAT_7
`endif
`ifdef ALU_STAT_F
`undef ALU_STAT_F
`endif
`ifdef ALU_SHIFT
`undef ALU_SHIFT
`endif
`ifdef EXEC_NO_WR
`undef EXEC_NO_WR
`endif
// Debug interface
`ifdef DBG_UART_WR
`undef DBG_UART_WR
`endif
`ifdef DBG_UART_BW
`undef DBG_UART_BW
`endif
`ifdef DBG_UART_ADDR
`undef DBG_UART_ADDR
`endif
// Debug interface CPU_CTL register
`ifdef HALT
`undef HALT
`endif
`ifdef RUN
`undef RUN
`endif
`ifdef ISTEP
`undef ISTEP
`endif
`ifdef SW_BRK_EN
`undef SW_BRK_EN
`endif
`ifdef FRZ_BRK_EN
`undef FRZ_BRK_EN
`endif
`ifdef RST_BRK_EN
`undef RST_BRK_EN
`endif
`ifdef CPU_RST
`undef CPU_RST
`endif
// Debug interface CPU_STAT register
`ifdef HALT_RUN
`undef HALT_RUN
`endif
`ifdef PUC_PND
`undef PUC_PND
`endif
`ifdef SWBRK_PND
`undef SWBRK_PND
`endif
`ifdef HWBRK0_PND
`undef HWBRK0_PND
`endif
`ifdef HWBRK1_PND
`undef HWBRK1_PND
`endif
// Debug interface BRKx_CTL register
`ifdef BRK_MODE_RD
`undef BRK_MODE_RD
`endif
`ifdef BRK_MODE_WR
`undef BRK_MODE_WR
`endif
`ifdef BRK_MODE
`undef BRK_MODE
`endif
`ifdef BRK_EN
`undef BRK_EN
`endif
`ifdef BRK_I_EN
`undef BRK_I_EN
`endif
`ifdef BRK_RANGE
`undef BRK_RANGE
`endif
// Basic clock module: BCSCTL1 Control Register
`ifdef DIVAx
`undef DIVAx
`endif
`ifdef DMA_CPUOFF
`undef DMA_CPUOFF
`endif
`ifdef DMA_SCG0
`undef DMA_SCG0
`endif
`ifdef DMA_SCG1
`undef DMA_SCG1
`endif
`ifdef DMA_OSCOFF
`undef DMA_OSCOFF
`endif
// Basic clock module: BCSCTL2 Control Register
`ifdef SELMx
`undef SELMx
`endif
`ifdef DIVMx
`undef DIVMx
`endif
`ifdef SELS
`undef SELS
`endif
`ifdef DIVSx
`undef DIVSx
`endif
// MCLK Clock gate
`ifdef MCLK_CGATE
`undef MCLK_CGATE
`endif
// SMCLK Clock gate
`ifdef SMCLK_CGATE
`undef SMCLK_CGATE
`endif
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
// Debug interface: CPU version
`ifdef CPU_VERSION
`undef CPU_VERSION
`endif
// Debug interface: Software breakpoint opcode
`ifdef DBG_SWBRK_OP
`undef DBG_SWBRK_OP
`endif
// Debug UART interface auto data synchronization
`ifdef DBG_UART_AUTO_SYNC
`undef DBG_UART_AUTO_SYNC
`endif
// Debug UART interface data rate
`ifdef DBG_UART_BAUD
`undef DBG_UART_BAUD
`endif
`ifdef DBG_DCO_FREQ
`undef DBG_DCO_FREQ
`endif
`ifdef DBG_UART_CNT
`undef DBG_UART_CNT
`endif
// Debug interface input synchronizer
`ifdef SYNC_DBG_UART_RXD
`undef SYNC_DBG_UART_RXD
`endif
// Enable/Disable the hardware breakpoint RANGE mode
`ifdef HWBRK_RANGE
`undef HWBRK_RANGE
`endif
// Counter width for the debug interface UART
`ifdef DBG_UART_XFER_CNT_W
`undef DBG_UART_XFER_CNT_W
`endif
//
// MULTIPLIER CONFIGURATION
//======================================
`ifdef MPY_16x16
`undef MPY_16x16
`endif
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_and_gate.v
//
// *Module Description:
// Generic AND gate cell for the openMSP430
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_and_gate (
// OUTPUTs
y, // AND gate output
// INPUTs
a, // AND gate input A
b // AND gate input B
);
// OUTPUTs
//=========
output y; // AND gate output
// INPUTs
//=========
input a; // AND gate input A
input b; // AND gate input B
//=============================================================================
// 1) SOME COMMENTS ON THIS MODULE
//=============================================================================
//
// In its ASIC version, some combinatorial pathes of the openMSP430 are
// sensitive to glitches, in particular the ones generating the wakeup
// signals.
// To prevent synthesis from optmizing combinatorial clouds into glitchy
// logic, this AND gate module has been instanciated in the critical places.
//
// Make sure that synthesis doesn\'t ungroup this module. As an alternative,
// a standard cell from the library could also be directly instanciated here
// (don\'t forget the "dont_touch" attribute)
//
//
//=============================================================================
// 2) AND GATE
//=============================================================================
assign y = a & b;
endmodule // omsp_and_gate
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: io_cell.v
//
// *Module Description:
// I/O cell model
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module io_cell (
// INOUTs
pad, // I/O Pad
\t\t
// OUTPUTs
data_in, // Input value
// INPUTs
data_out_en, // Output enable
data_out // Output value
);
// INOUTs
//=========
inout pad; // I/O Pad
// OUTPUTs
//=========
output data_in; // Input value
// INPUTs
//=========
input data_out_en; // Output enable
input data_out; // Output value
//=============================================================================
// 1) I/O CELL
//=============================================================================
assign data_in = pad;
assign pad = data_out_en ? data_out : 1\'bz;
endmodule // io_cell
|
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